DevVGA-SVGA.cpp@ 82199

Last change on this file since 82199 was 82199, checked in by vboxsync, 5 years ago
DevVGA: The FIFO shouldn't be prefetchable. Workarounds for old saved state with non-prefetchable VRAM (VMSVGA). bugref:9218
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1	/* $Id: DevVGA-SVGA.cpp 82199 2019-11-25 20:54:14Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	*/
13
14	/*
15	* Copyright (C) 2013-2019 Oracle Corporation
16	*
17	* This file is part of VirtualBox Open Source Edition (OSE), as
18	* available from http://www.virtualbox.org. This file is free software;
19	* you can redistribute it and/or modify it under the terms of the GNU
20	* General Public License (GPL) as published by the Free Software
21	* Foundation, in version 2 as it comes in the "COPYING" file of the
22	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
23	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
24	*/
25
26
27	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
28	*
29	* This device emulation was contributed by trivirt AG. It offers an
30	* alternative to our Bochs based VGA graphics and 3d emulations. This is
31	* valuable for Xorg based guests, as there is driver support shipping with Xorg
32	* since it forked from XFree86.
33	*
34	*
35	* @section sec_dev_vmsvga_sdk The VMware SDK
36	*
37	* This is officially deprecated now, however it's still quite useful,
38	* especially for getting the old features working:
39	* http://vmware-svga.sourceforge.net/
40	*
41	* They currently point developers at the following resources.
42	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
43	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
44	* - http://cgit.freedesktop.org/mesa/vmwgfx/
45	*
46	* @subsection subsec_dev_vmsvga_sdk_results Test results
47	*
48	* Test results:
49	* - 2dmark.img:
50	* + todo
51	* - backdoor-tclo.img:
52	* + todo
53	* - blit-cube.img:
54	* + todo
55	* - bunnies.img:
56	* + todo
57	* - cube.img:
58	* + todo
59	* - cubemark.img:
60	* + todo
61	* - dynamic-vertex-stress.img:
62	* + todo
63	* - dynamic-vertex.img:
64	* + todo
65	* - fence-stress.img:
66	* + todo
67	* - gmr-test.img:
68	* + todo
69	* - half-float-test.img:
70	* + todo
71	* - noscreen-cursor.img:
72	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
73	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
74	* visible though.)
75	* - Cursor animation via the palette doesn't work.
76	* - During debugging, it turns out that the framebuffer content seems to
77	* be halfways ignore or something (memset(fb, 0xcc, lots)).
78	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
79	* grow it 0x10 fold (128KB -> 2MB like in WS10).
80	* - null.img:
81	* + todo
82	* - pong.img:
83	* + todo
84	* - presentReadback.img:
85	* + todo
86	* - resolution-set.img:
87	* + todo
88	* - rt-gamma-test.img:
89	* + todo
90	* - screen-annotation.img:
91	* + todo
92	* - screen-cursor.img:
93	* + todo
94	* - screen-dma-coalesce.img:
95	* + todo
96	* - screen-gmr-discontig.img:
97	* + todo
98	* - screen-gmr-remap.img:
99	* + todo
100	* - screen-multimon.img:
101	* + todo
102	* - screen-present-clip.img:
103	* + todo
104	* - screen-render-test.img:
105	* + todo
106	* - screen-simple.img:
107	* + todo
108	* - screen-text.img:
109	* + todo
110	* - simple-shaders.img:
111	* + todo
112	* - simple_blit.img:
113	* + todo
114	* - tiny-2d-updates.img:
115	* + todo
116	* - video-formats.img:
117	* + todo
118	* - video-sync.img:
119	* + todo
120	*
121	*/
122
123
124	/*********************************************************************************************************************************
125	* Header Files *
126	*********************************************************************************************************************************/
127	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
128	#define VMSVGA_USE_EMT_HALT_CODE
129	#include <VBox/vmm/pdmdev.h>
130	#include <VBox/version.h>
131	#include <VBox/err.h>
132	#include <VBox/log.h>
133	#include <VBox/vmm/pgm.h>
134	#ifdef VMSVGA_USE_EMT_HALT_CODE
135	# include <VBox/vmm/vmapi.h>
136	# include <VBox/vmm/vmcpuset.h>
137	#endif
138	#include <VBox/sup.h>
139
140	#include <iprt/assert.h>
141	#include <iprt/semaphore.h>
142	#include <iprt/uuid.h>
143	#ifdef IN_RING3
144	# include <iprt/ctype.h>
145	# include <iprt/mem.h>
146	# ifdef VBOX_STRICT
147	# include <iprt/time.h>
148	# endif
149	#endif
150
151	#include <VBox/AssertGuest.h>
152	#include <VBox/VMMDev.h>
153	#include <VBoxVideo.h>
154	#include <VBox/bioslogo.h>
155
156	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
157	#include "DevVGA.h"
158
159	#include "DevVGA-SVGA.h"
160	#include "vmsvga/svga_escape.h"
161	#include "vmsvga/svga_overlay.h"
162	#include "vmsvga/svga3d_caps.h"
163	#ifdef VBOX_WITH_VMSVGA3D
164	# include "DevVGA-SVGA3d.h"
165	# ifdef RT_OS_DARWIN
166	# include "DevVGA-SVGA3d-cocoa.h"
167	# endif
168	#endif
169
170
171	/*********************************************************************************************************************************
172	* Defined Constants And Macros *
173	*********************************************************************************************************************************/
174	/**
175	* Macro for checking if a fixed FIFO register is valid according to the
176	* current FIFO configuration.
177	*
178	* @returns true / false.
179	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
180	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
181	*/
182	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
183
184
185	/*********************************************************************************************************************************
186	* Structures and Typedefs *
187	*********************************************************************************************************************************/
188	/**
189	* 64-bit GMR descriptor.
190	*/
191	typedef struct
192	{
193	RTGCPHYS GCPhys;
194	uint64_t numPages;
195	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
196
197	/**
198	* GMR slot
199	*/
200	typedef struct
201	{
202	uint32_t cMaxPages;
203	uint32_t cbTotal;
204	uint32_t numDescriptors;
205	PVMSVGAGMRDESCRIPTOR paDesc;
206	} GMR, *PGMR;
207
208	#ifdef IN_RING3
209	/**
210	* Internal SVGA ring-3 only state.
211	*/
212	typedef struct VMSVGAR3STATE
213	{
214	GMR *paGMR; // [VMSVGAState::cGMR]
215	struct
216	{
217	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
218	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
219	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
220	} GMRFB;
221	struct
222	{
223	bool fActive;
224	uint32_t xHotspot;
225	uint32_t yHotspot;
226	uint32_t width;
227	uint32_t height;
228	uint32_t cbData;
229	void *pData;
230	} Cursor;
231	SVGAColorBGRX colorAnnotation;
232
233	# ifdef VMSVGA_USE_EMT_HALT_CODE
234	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
235	uint32_t volatile cBusyDelayedEmts;
236	/** Set of EMTs that are */
237	VMCPUSET BusyDelayedEmts;
238	# else
239	/** Number of EMTs waiting on hBusyDelayedEmts. */
240	uint32_t volatile cBusyDelayedEmts;
241	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
242	* busy (ugly). */
243	RTSEMEVENTMULTI hBusyDelayedEmts;
244	# endif
245
246	/** Information obout screens. */
247	VMSVGASCREENOBJECT aScreens[64];
248
249	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
250	STAMPROFILE StatBusyDelayEmts;
251
252	STAMPROFILE StatR3Cmd3dPresentProf;
253	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
254	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
255	STAMCOUNTER StatR3CmdDefineGmr2;
256	STAMCOUNTER StatR3CmdDefineGmr2Free;
257	STAMCOUNTER StatR3CmdDefineGmr2Modify;
258	STAMCOUNTER StatR3CmdRemapGmr2;
259	STAMCOUNTER StatR3CmdRemapGmr2Modify;
260	STAMCOUNTER StatR3CmdInvalidCmd;
261	STAMCOUNTER StatR3CmdFence;
262	STAMCOUNTER StatR3CmdUpdate;
263	STAMCOUNTER StatR3CmdUpdateVerbose;
264	STAMCOUNTER StatR3CmdDefineCursor;
265	STAMCOUNTER StatR3CmdDefineAlphaCursor;
266	STAMCOUNTER StatR3CmdEscape;
267	STAMCOUNTER StatR3CmdDefineScreen;
268	STAMCOUNTER StatR3CmdDestroyScreen;
269	STAMCOUNTER StatR3CmdDefineGmrFb;
270	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
271	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
272	STAMCOUNTER StatR3CmdAnnotationFill;
273	STAMCOUNTER StatR3CmdAnnotationCopy;
274	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
275	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
276	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
277	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
279	STAMCOUNTER StatR3Cmd3dSurfaceDma;
280	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
281	STAMCOUNTER StatR3Cmd3dContextDefine;
282	STAMCOUNTER StatR3Cmd3dContextDestroy;
283	STAMCOUNTER StatR3Cmd3dSetTransform;
284	STAMCOUNTER StatR3Cmd3dSetZRange;
285	STAMCOUNTER StatR3Cmd3dSetRenderState;
286	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
287	STAMCOUNTER StatR3Cmd3dSetTextureState;
288	STAMCOUNTER StatR3Cmd3dSetMaterial;
289	STAMCOUNTER StatR3Cmd3dSetLightData;
290	STAMCOUNTER StatR3Cmd3dSetLightEnable;
291	STAMCOUNTER StatR3Cmd3dSetViewPort;
292	STAMCOUNTER StatR3Cmd3dSetClipPlane;
293	STAMCOUNTER StatR3Cmd3dClear;
294	STAMCOUNTER StatR3Cmd3dPresent;
295	STAMCOUNTER StatR3Cmd3dPresentReadBack;
296	STAMCOUNTER StatR3Cmd3dShaderDefine;
297	STAMCOUNTER StatR3Cmd3dShaderDestroy;
298	STAMCOUNTER StatR3Cmd3dSetShader;
299	STAMCOUNTER StatR3Cmd3dSetShaderConst;
300	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
301	STAMCOUNTER StatR3Cmd3dSetScissorRect;
302	STAMCOUNTER StatR3Cmd3dBeginQuery;
303	STAMCOUNTER StatR3Cmd3dEndQuery;
304	STAMCOUNTER StatR3Cmd3dWaitForQuery;
305	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
306	STAMCOUNTER StatR3Cmd3dActivateSurface;
307	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
308
309	STAMCOUNTER StatR3RegConfigDoneWr;
310	STAMCOUNTER StatR3RegGmrDescriptorWr;
311	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
312	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
313
314	STAMCOUNTER StatFifoCommands;
315	STAMCOUNTER StatFifoErrors;
316	STAMCOUNTER StatFifoUnkCmds;
317	STAMCOUNTER StatFifoTodoTimeout;
318	STAMCOUNTER StatFifoTodoWoken;
319	STAMPROFILE StatFifoStalls;
320	STAMPROFILE StatFifoExtendedSleep;
321	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
322	STAMCOUNTER StatFifoAccessHandler;
323	# endif
324	STAMCOUNTER StatFifoCursorFetchAgain;
325	STAMCOUNTER StatFifoCursorNoChange;
326	STAMCOUNTER StatFifoCursorPosition;
327	STAMCOUNTER StatFifoCursorVisiblity;
328	STAMCOUNTER StatFifoWatchdogWakeUps;
329	} VMSVGAR3STATE, *PVMSVGAR3STATE;
330	#endif /* IN_RING3 */
331
332
333	/*********************************************************************************************************************************
334	* Internal Functions *
335	*********************************************************************************************************************************/
336	#ifdef IN_RING3
337	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
338	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
339	# endif
340	# ifdef DEBUG_GMR_ACCESS
341	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
342	# endif
343	#endif
344
345
346	/*********************************************************************************************************************************
347	* Global Variables *
348	*********************************************************************************************************************************/
349	#ifdef IN_RING3
350
351	/**
352	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
353	*/
354	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
355	{
356	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
357	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
358	SSMFIELD_ENTRY_TERM()
359	};
360
361	/**
362	* SSM descriptor table for the GMR structure.
363	*/
364	static SSMFIELD const g_aGMRFields[] =
365	{
366	SSMFIELD_ENTRY( GMR, cMaxPages),
367	SSMFIELD_ENTRY( GMR, cbTotal),
368	SSMFIELD_ENTRY( GMR, numDescriptors),
369	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
375	*/
376	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
377	{
378	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
379	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
380	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
381	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
389	SSMFIELD_ENTRY_TERM()
390	};
391
392	/**
393	* SSM descriptor table for the VMSVGAR3STATE structure.
394	*/
395	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
396	{
397	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
398	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
399	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
400	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
401	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
405	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
407	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
408	#ifdef VMSVGA_USE_EMT_HALT_CODE
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
410	#else
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
412	#endif
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
414	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
470
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
483	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
485	# endif
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
490
491	SSMFIELD_ENTRY_TERM()
492	};
493
494	/**
495	* SSM descriptor table for the VGAState.svga structure.
496	*/
497	static SSMFIELD const g_aVGAStateSVGAFields[] =
498	{
499	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
501	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
502	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
503	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
504	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
505	SSMFIELD_ENTRY( VMSVGAState, fBusy),
506	SSMFIELD_ENTRY( VMSVGAState, fTraces),
507	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
508	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
509	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
510	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
511	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
512	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
513	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
514	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
515	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
516	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
517	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
519	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
520	SSMFIELD_ENTRY( VMSVGAState, uWidth),
521	SSMFIELD_ENTRY( VMSVGAState, uHeight),
522	SSMFIELD_ENTRY( VMSVGAState, uBpp),
523	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
524	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
525	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
526	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
527	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
528	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
529	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
530	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
531	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
532	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
533	SSMFIELD_ENTRY_TERM()
534	};
535	#endif /* IN_RING3 */
536
537
538	/*********************************************************************************************************************************
539	* Internal Functions *
540	*********************************************************************************************************************************/
541	#ifdef IN_RING3
542	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
543	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
544	uint32_t uVersion, uint32_t uPass);
545	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
546	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
547	#endif /* IN_RING3 */
548
549
550
551	#ifdef IN_RING3
552	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
553	{
554	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
555	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
556	&& pSVGAState
557	&& pSVGAState->aScreens[idScreen].fDefined)
558	{
559	return &pSVGAState->aScreens[idScreen];
560	}
561	return NULL;
562	}
563	#endif /* IN_RING3 */
564
565	#ifdef LOG_ENABLED
566
567	/**
568	* Index register string name lookup
569	*
570	* @returns Index register string or "UNKNOWN"
571	* @param pThis The shared VGA/VMSVGA state.
572	* @param idxReg The index register.
573	*/
574	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
575	{
576	switch (idxReg)
577	{
578	case SVGA_REG_ID: return "SVGA_REG_ID";
579	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
580	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
581	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
582	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
583	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
584	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
585	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
586	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
587	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
588	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
589	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
590	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
591	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
592	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
593	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
594	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
595	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
596	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
597	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
598	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
599	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
600	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
601	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
602	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
603	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
604	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
605	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
606	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
607	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
608	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
609	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
610	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
611	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
612	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
613	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
614	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
615	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
616	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
617	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
618	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
619	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
620	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
621	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
622	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
623	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
624	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
625	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
626	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
627	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
628
629	default:
630	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
631	return "SVGA_SCRATCH_BASE reg";
632	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
633	return "SVGA_PALETTE_BASE reg";
634	return "UNKNOWN";
635	}
636	}
637
638	#ifdef IN_RING3
639	/**
640	* FIFO command name lookup
641	*
642	* @returns FIFO command string or "UNKNOWN"
643	* @param u32Cmd FIFO command
644	*/
645	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
646	{
647	switch (u32Cmd)
648	{
649	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
650	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
651	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
652	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
653	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
654	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
655	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
656	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
657	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
658	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
659	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
660	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
661	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
662	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
663	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
664	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
665	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
666	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
667	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
668	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
669	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
670	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
671	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
672	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
673	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
674	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
675	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
676	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
677	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
678	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
679	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
680	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
681	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
682	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
683	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
684	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
685	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
686	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
687	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
688	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
689	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
690	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
691	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
692	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
693	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
694	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
695	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
696	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
697	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
698	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
699	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
700	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
701	default: return "UNKNOWN";
702	}
703	}
704	# endif /* IN_RING3 */
705
706	#endif /* LOG_ENABLED */
707
708	#ifdef IN_RING3
709	/**
710	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
711	*/
712	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
713	{
714	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
715	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
716
717	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
718	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
719
720	/** @todo Test how it interacts with multiple screen objects. */
721	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
722	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
723	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
724
725	if (x < uWidth)
726	{
727	pThis->svga.viewport.x = x;
728	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
729	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
730	}
731	else
732	{
733	pThis->svga.viewport.x = uWidth;
734	pThis->svga.viewport.cx = 0;
735	pThis->svga.viewport.xRight = uWidth;
736	}
737	if (y < uHeight)
738	{
739	pThis->svga.viewport.y = y;
740	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
741	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
742	pThis->svga.viewport.yHighWC = uHeight - y;
743	}
744	else
745	{
746	pThis->svga.viewport.y = uHeight;
747	pThis->svga.viewport.cy = 0;
748	pThis->svga.viewport.yLowWC = 0;
749	pThis->svga.viewport.yHighWC = 0;
750	}
751
752	# ifdef VBOX_WITH_VMSVGA3D
753	/*
754	* Now inform the 3D backend.
755	*/
756	if (pThis->svga.f3DEnabled)
757	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
758	# else
759	RT_NOREF(OldViewport);
760	# endif
761	}
762	#endif /* IN_RING3 */
763
764	/**
765	* Read port register
766	*
767	* @returns VBox status code.
768	* @param pDevIns The device instance.
769	* @param pThis The shared VGA/VMSVGA state.
770	* @param pu32 Where to store the read value
771	*/
772	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
773	{
774	#ifdef IN_RING3
775	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
776	#endif
777	int rc = VINF_SUCCESS;
778	*pu32 = 0;
779
780	/* Rough index register validation. */
781	uint32_t idxReg = pThis->svga.u32IndexReg;
782	#if !defined(IN_RING3) && defined(VBOX_STRICT)
783	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
784	VINF_IOM_R3_IOPORT_READ);
785	#else
786	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
787	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
788	VINF_SUCCESS);
789	#endif
790	RT_UNTRUSTED_VALIDATED_FENCE();
791
792	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
793	if ( idxReg >= SVGA_REG_CAPABILITIES
794	&& pThis->svga.u32SVGAId == SVGA_ID_0)
795	{
796	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
797	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
798	}
799
800	switch (idxReg)
801	{
802	case SVGA_REG_ID:
803	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
804	*pu32 = pThis->svga.u32SVGAId;
805	break;
806
807	case SVGA_REG_ENABLE:
808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
809	*pu32 = pThis->svga.fEnabled;
810	break;
811
812	case SVGA_REG_WIDTH:
813	{
814	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
815	if ( pThis->svga.fEnabled
816	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
817	*pu32 = pThis->svga.uWidth;
818	else
819	{
820	#ifndef IN_RING3
821	rc = VINF_IOM_R3_IOPORT_READ;
822	#else
823	*pu32 = pThisCC->pDrv->cx;
824	#endif
825	}
826	break;
827	}
828
829	case SVGA_REG_HEIGHT:
830	{
831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
832	if ( pThis->svga.fEnabled
833	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
834	*pu32 = pThis->svga.uHeight;
835	else
836	{
837	#ifndef IN_RING3
838	rc = VINF_IOM_R3_IOPORT_READ;
839	#else
840	*pu32 = pThisCC->pDrv->cy;
841	#endif
842	}
843	break;
844	}
845
846	case SVGA_REG_MAX_WIDTH:
847	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
848	*pu32 = pThis->svga.u32MaxWidth;
849	break;
850
851	case SVGA_REG_MAX_HEIGHT:
852	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
853	*pu32 = pThis->svga.u32MaxHeight;
854	break;
855
856	case SVGA_REG_DEPTH:
857	/* This returns the color depth of the current mode. */
858	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
859	switch (pThis->svga.uBpp)
860	{
861	case 15:
862	case 16:
863	case 24:
864	*pu32 = pThis->svga.uBpp;
865	break;
866
867	default:
868	case 32:
869	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
870	break;
871	}
872	break;
873
874	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
875	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
876	if ( pThis->svga.fEnabled
877	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
878	*pu32 = pThis->svga.uBpp;
879	else
880	{
881	#ifndef IN_RING3
882	rc = VINF_IOM_R3_IOPORT_READ;
883	#else
884	*pu32 = pThisCC->pDrv->cBits;
885	#endif
886	}
887	break;
888
889	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
891	if ( pThis->svga.fEnabled
892	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
893	*pu32 = (pThis->svga.uBpp + 7) & ~7;
894	else
895	{
896	#ifndef IN_RING3
897	rc = VINF_IOM_R3_IOPORT_READ;
898	#else
899	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
900	#endif
901	}
902	break;
903
904	case SVGA_REG_PSEUDOCOLOR:
905	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
906	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
907	break;
908
909	case SVGA_REG_RED_MASK:
910	case SVGA_REG_GREEN_MASK:
911	case SVGA_REG_BLUE_MASK:
912	{
913	uint32_t uBpp;
914
915	if ( pThis->svga.fEnabled
916	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
917	{
918	uBpp = pThis->svga.uBpp;
919	}
920	else
921	{
922	#ifndef IN_RING3
923	rc = VINF_IOM_R3_IOPORT_READ;
924	break;
925	#else
926	uBpp = pThisCC->pDrv->cBits;
927	#endif
928	}
929	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
930	switch (uBpp)
931	{
932	case 8:
933	u32RedMask = 0x07;
934	u32GreenMask = 0x38;
935	u32BlueMask = 0xc0;
936	break;
937
938	case 15:
939	u32RedMask = 0x0000001f;
940	u32GreenMask = 0x000003e0;
941	u32BlueMask = 0x00007c00;
942	break;
943
944	case 16:
945	u32RedMask = 0x0000001f;
946	u32GreenMask = 0x000007e0;
947	u32BlueMask = 0x0000f800;
948	break;
949
950	case 24:
951	case 32:
952	default:
953	u32RedMask = 0x00ff0000;
954	u32GreenMask = 0x0000ff00;
955	u32BlueMask = 0x000000ff;
956	break;
957	}
958	switch (idxReg)
959	{
960	case SVGA_REG_RED_MASK:
961	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
962	*pu32 = u32RedMask;
963	break;
964
965	case SVGA_REG_GREEN_MASK:
966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
967	*pu32 = u32GreenMask;
968	break;
969
970	case SVGA_REG_BLUE_MASK:
971	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
972	*pu32 = u32BlueMask;
973	break;
974	}
975	break;
976	}
977
978	case SVGA_REG_BYTES_PER_LINE:
979	{
980	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
981	if ( pThis->svga.fEnabled
982	&& pThis->svga.cbScanline)
983	*pu32 = pThis->svga.cbScanline;
984	else
985	{
986	#ifndef IN_RING3
987	rc = VINF_IOM_R3_IOPORT_READ;
988	#else
989	*pu32 = pThisCC->pDrv->cbScanline;
990	#endif
991	}
992	break;
993	}
994
995	case SVGA_REG_VRAM_SIZE: /* VRAM size */
996	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
997	*pu32 = pThis->vram_size;
998	break;
999
1000	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1002	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1003	*pu32 = pThis->GCPhysVRAM;
1004	break;
1005
1006	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1008	/* Always zero in our case. */
1009	*pu32 = 0;
1010	break;
1011
1012	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1013	{
1014	#ifndef IN_RING3
1015	rc = VINF_IOM_R3_IOPORT_READ;
1016	#else
1017	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1018
1019	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1020	if ( pThis->svga.fEnabled
1021	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1022	{
1023	/* Hardware enabled; return real framebuffer size .*/
1024	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1025	}
1026	else
1027	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1028
1029	pu32 = RT_MIN(pThis->vram_size, pu32);
1030	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1031	#endif
1032	break;
1033	}
1034
1035	case SVGA_REG_CAPABILITIES:
1036	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1037	*pu32 = pThis->svga.u32RegCaps;
1038	break;
1039
1040	case SVGA_REG_MEM_START: /* FIFO start */
1041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1042	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1043	*pu32 = pThis->svga.GCPhysFIFO;
1044	break;
1045
1046	case SVGA_REG_MEM_SIZE: /* FIFO size */
1047	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1048	*pu32 = pThis->svga.cbFIFO;
1049	break;
1050
1051	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1052	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1053	*pu32 = pThis->svga.fConfigured;
1054	break;
1055
1056	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1057	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1058	*pu32 = 0;
1059	break;
1060
1061	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1062	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1063	if (pThis->svga.fBusy)
1064	{
1065	#ifndef IN_RING3
1066	/* Go to ring-3 and halt the CPU. */
1067	rc = VINF_IOM_R3_IOPORT_READ;
1068	RT_NOREF(pDevIns);
1069	break;
1070	#else
1071	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1072	/* The guest is basically doing a HLT via the device here, but with
1073	a special wake up condition on FIFO completion. */
1074	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1075	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1076	PVM pVM = PDMDevHlpGetVM(pDevIns);
1077	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1078	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1079	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1080	if (pThis->svga.fBusy)
1081	{
1082	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1083	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1084	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1085	}
1086	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1087	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1088	# else
1089
1090	/* Delay the EMT a bit so the FIFO and others can get some work done.
1091	This used to be a crude 50 ms sleep. The current code tries to be
1092	more efficient, but the consept is still very crude. */
1093	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1094	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1095	RTThreadYield();
1096	if (pThis->svga.fBusy)
1097	{
1098	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1099
1100	if (pThis->svga.fBusy && cRefs == 1)
1101	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1102	if (pThis->svga.fBusy)
1103	{
1104	/** @todo If this code is going to stay, we need to call into the halt/wait
1105	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1106	* suffer when the guest is polling on a busy FIFO. */
1107	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1108	if (cNsMaxWait >= RT_NS_100US)
1109	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1110	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1111	RT_MIN(cNsMaxWait, RT_NS_10MS));
1112	}
1113
1114	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1115	}
1116	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1117	# endif
1118	*pu32 = pThis->svga.fBusy != 0;
1119	#endif
1120	}
1121	else
1122	*pu32 = false;
1123	break;
1124
1125	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1126	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1127	*pu32 = pThis->svga.u32GuestId;
1128	break;
1129
1130	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1131	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1132	*pu32 = pThis->svga.cScratchRegion;
1133	break;
1134
1135	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1137	*pu32 = SVGA_FIFO_NUM_REGS;
1138	break;
1139
1140	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1142	*pu32 = pThis->svga.u32PitchLock;
1143	break;
1144
1145	case SVGA_REG_IRQMASK: /* Interrupt mask */
1146	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1147	*pu32 = pThis->svga.u32IrqMask;
1148	break;
1149
1150	/* See "Guest memory regions" below. */
1151	case SVGA_REG_GMR_ID:
1152	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1153	*pu32 = pThis->svga.u32CurrentGMRId;
1154	break;
1155
1156	case SVGA_REG_GMR_DESCRIPTOR:
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1158	/* Write only */
1159	*pu32 = 0;
1160	break;
1161
1162	case SVGA_REG_GMR_MAX_IDS:
1163	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1164	*pu32 = pThis->svga.cGMR;
1165	break;
1166
1167	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1168	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1169	*pu32 = VMSVGA_MAX_GMR_PAGES;
1170	break;
1171
1172	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1174	*pu32 = pThis->svga.fTraces;
1175	break;
1176
1177	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1179	*pu32 = VMSVGA_MAX_GMR_PAGES;
1180	break;
1181
1182	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1183	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1184	*pu32 = VMSVGA_SURFACE_SIZE;
1185	break;
1186
1187	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1188	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1189	break;
1190
1191	/* Mouse cursor support. */
1192	case SVGA_REG_CURSOR_ID:
1193	case SVGA_REG_CURSOR_X:
1194	case SVGA_REG_CURSOR_Y:
1195	case SVGA_REG_CURSOR_ON:
1196	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1197	break;
1198
1199	/* Legacy multi-monitor support */
1200	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1201	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1202	*pu32 = 1;
1203	break;
1204
1205	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1206	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1207	*pu32 = 0;
1208	break;
1209
1210	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1211	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1212	*pu32 = 0;
1213	break;
1214
1215	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1216	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1217	*pu32 = 0;
1218	break;
1219
1220	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1221	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1222	*pu32 = 0;
1223	break;
1224
1225	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1226	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1227	*pu32 = pThis->svga.uWidth;
1228	break;
1229
1230	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1231	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1232	*pu32 = pThis->svga.uHeight;
1233	break;
1234
1235	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1236	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1237	/* We must return something sensible here otherwise the Linux driver
1238	will take a legacy code path without 3d support. This number also
1239	limits how many screens Linux guests will allow. */
1240	*pu32 = pThis->cMonitors;
1241	break;
1242
1243	default:
1244	{
1245	uint32_t offReg;
1246	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1247	{
1248	RT_UNTRUSTED_VALIDATED_FENCE();
1249	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1250	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1251	}
1252	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1253	{
1254	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1255	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1256	RT_UNTRUSTED_VALIDATED_FENCE();
1257	uint32_t u32 = pThis->last_palette[offReg / 3];
1258	switch (offReg % 3)
1259	{
1260	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1261	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1262	case 2: pu32 = u32 & 0xff; break; / blue */
1263	}
1264	}
1265	else
1266	{
1267	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1268	rc = VINF_IOM_R3_IOPORT_READ;
1269	#else
1270	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1271
1272	/* Do not assert. The guest might be reading all registers. */
1273	LogFunc(("Unknown reg=%#x\n", idxReg));
1274	#endif
1275	}
1276	break;
1277	}
1278	}
1279	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1280	return rc;
1281	}
1282
1283	#ifdef IN_RING3
1284	/**
1285	* Apply the current resolution settings to change the video mode.
1286	*
1287	* @returns VBox status code.
1288	* @param pThis The shared VGA state.
1289	* @param pThisCC The ring-3 VGA state.
1290	*/
1291	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1292	{
1293	int rc;
1294
1295	/* Always do changemode on FIFO thread. */
1296	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1297
1298	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1299
1300	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1301
1302	if (pThis->svga.fGFBRegisters)
1303	{
1304	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1305	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1306	* deletes all screens other than screen #0, and redefines screen
1307	* #0 according to the specified mode. Drivers that use
1308	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1309	*/
1310
1311	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1312	pScreen->fDefined = true;
1313	pScreen->fModified = true;
1314	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1315	pScreen->idScreen = 0;
1316	pScreen->xOrigin = 0;
1317	pScreen->yOrigin = 0;
1318	pScreen->offVRAM = 0;
1319	pScreen->cbPitch = pThis->svga.cbScanline;
1320	pScreen->cWidth = pThis->svga.uWidth;
1321	pScreen->cHeight = pThis->svga.uHeight;
1322	pScreen->cBpp = pThis->svga.uBpp;
1323
1324	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1325	{
1326	/* Delete screen. */
1327	pScreen = &pSVGAState->aScreens[iScreen];
1328	if (pScreen->fDefined)
1329	{
1330	pScreen->fModified = true;
1331	pScreen->fDefined = false;
1332	}
1333	}
1334	}
1335	else
1336	{
1337	/* "If Screen Objects are supported, they can be used to fully
1338	* replace the functionality provided by the framebuffer registers
1339	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1340	*/
1341	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1342	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1343	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1344	}
1345
1346	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1347	{
1348	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
1349	if (!pScreen->fModified)
1350	continue;
1351
1352	pScreen->fModified = false;
1353
1354	VBVAINFOVIEW view;
1355	RT_ZERO(view);
1356	view.u32ViewIndex = pScreen->idScreen;
1357	// view.u32ViewOffset = 0;
1358	view.u32ViewSize = pThis->vram_size;
1359	view.u32MaxScreenSize = pThis->vram_size;
1360
1361	VBVAINFOSCREEN screen;
1362	RT_ZERO(screen);
1363	screen.u32ViewIndex = pScreen->idScreen;
1364
1365	if (pScreen->fDefined)
1366	{
1367	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
1368	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
1369	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
1370	{
1371	Assert(pThis->svga.fGFBRegisters);
1372	continue;
1373	}
1374
1375	screen.i32OriginX = pScreen->xOrigin;
1376	screen.i32OriginY = pScreen->yOrigin;
1377	screen.u32StartOffset = pScreen->offVRAM;
1378	screen.u32LineSize = pScreen->cbPitch;
1379	screen.u32Width = pScreen->cWidth;
1380	screen.u32Height = pScreen->cHeight;
1381	screen.u16BitsPerPixel = pScreen->cBpp;
1382	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
1383	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
1384	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
1385	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
1386	}
1387	else
1388	{
1389	/* Screen is destroyed. */
1390	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
1391	}
1392
1393	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
1394	AssertRC(rc);
1395	}
1396
1397	/* Last stuff. For the VGA device screenshot. */
1398	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1399	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1400	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1401	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1402	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1403
1404	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1405	if ( pThis->svga.viewport.cx == 0
1406	&& pThis->svga.viewport.cy == 0)
1407	{
1408	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1409	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1410	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1411	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1412	pThis->svga.viewport.yLowWC = 0;
1413	}
1414
1415	return VINF_SUCCESS;
1416	}
1417
1418	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1419	{
1420	VBVACMDHDR cmd;
1421	cmd.x = (int16_t)(pScreen->xOrigin + x);
1422	cmd.y = (int16_t)(pScreen->yOrigin + y);
1423	cmd.w = (uint16_t)w;
1424	cmd.h = (uint16_t)h;
1425
1426	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1427	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1428	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1429	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1430
1431	return VINF_SUCCESS;
1432	}
1433
1434	#endif /* IN_RING3 */
1435	#if defined(IN_RING0) \|\| defined(IN_RING3)
1436
1437	/**
1438	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1439	*
1440	* @param pThis The shared VGA/VMSVGA instance data.
1441	* @param pThisCC The VGA/VMSVGA state for the current context.
1442	* @param fState The busy state.
1443	*/
1444	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1445	{
1446	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1447
1448	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1449	{
1450	/* Race / unfortunately scheduling. Highly unlikly. */
1451	uint32_t cLoops = 64;
1452	do
1453	{
1454	ASMNopPause();
1455	fState = (pThis->svga.fBusy != 0);
1456	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1457	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1458	}
1459	}
1460
1461
1462	/**
1463	* Update the scanline pitch in response to the guest changing mode
1464	* width/bpp.
1465	*
1466	* @param pThis The shared VGA/VMSVGA state.
1467	* @param pThisCC The VGA/VMSVGA state for the current context.
1468	*/
1469	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1470	{
1471	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1472	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1473	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1474	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1475
1476	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1477	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1478	* location but it has a different meaning.
1479	*/
1480	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1481	uFifoPitchLock = 0;
1482
1483	/* Sanitize values. */
1484	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1485	uFifoPitchLock = 0;
1486	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1487	uRegPitchLock = 0;
1488
1489	/* Prefer the register value to the FIFO value.*/
1490	if (uRegPitchLock)
1491	pThis->svga.cbScanline = uRegPitchLock;
1492	else if (uFifoPitchLock)
1493	pThis->svga.cbScanline = uFifoPitchLock;
1494	else
1495	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1496
1497	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1498	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1499	}
1500
1501	#endif /* IN_RING0 \|\| IN_RING3 */
1502
1503
1504	/**
1505	* Write port register
1506	*
1507	* @returns Strict VBox status code.
1508	* @param pDevIns The device instance.
1509	* @param pThis The shared VGA/VMSVGA state.
1510	* @param pThisCC The VGA/VMSVGA state for the current context.
1511	* @param u32 Value to write
1512	*/
1513	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1514	{
1515	#ifdef IN_RING3
1516	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1517	#endif
1518	VBOXSTRICTRC rc = VINF_SUCCESS;
1519	RT_NOREF(pThisCC);
1520
1521	/* Rough index register validation. */
1522	uint32_t idxReg = pThis->svga.u32IndexReg;
1523	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1524	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1525	VINF_IOM_R3_IOPORT_WRITE);
1526	#else
1527	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1528	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1529	VINF_SUCCESS);
1530	#endif
1531	RT_UNTRUSTED_VALIDATED_FENCE();
1532
1533	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1534	if ( idxReg >= SVGA_REG_CAPABILITIES
1535	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1536	{
1537	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1538	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1539	}
1540	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1541	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1542	switch (idxReg)
1543	{
1544	case SVGA_REG_WIDTH:
1545	case SVGA_REG_HEIGHT:
1546	case SVGA_REG_PITCHLOCK:
1547	case SVGA_REG_BITS_PER_PIXEL:
1548	pThis->svga.fGFBRegisters = true;
1549	break;
1550	default:
1551	break;
1552	}
1553
1554	switch (idxReg)
1555	{
1556	case SVGA_REG_ID:
1557	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1558	if ( u32 == SVGA_ID_0
1559	\|\| u32 == SVGA_ID_1
1560	\|\| u32 == SVGA_ID_2)
1561	pThis->svga.u32SVGAId = u32;
1562	else
1563	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1564	break;
1565
1566	case SVGA_REG_ENABLE:
1567	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1568	#ifdef IN_RING3
1569	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1570	&& pThis->svga.fEnabled == false)
1571	{
1572	/* Make a backup copy of the first 512kb in order to save font data etc. */
1573	/** @todo should probably swap here, rather than copy + zero */
1574	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1575	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1576	}
1577
1578	pThis->svga.fEnabled = u32;
1579	if (pThis->svga.fEnabled)
1580	{
1581	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1582	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1583	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1584	{
1585	/* Keep the current mode. */
1586	pThis->svga.uWidth = pThisCC->pDrv->cx;
1587	pThis->svga.uHeight = pThisCC->pDrv->cy;
1588	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1589	}
1590
1591	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1592	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1593	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1594	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1595	# ifdef LOG_ENABLED
1596	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1597	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1598	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1599	# endif
1600
1601	/* Disable or enable dirty page tracking according to the current fTraces value. */
1602	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1603
1604	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1605	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1606	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1607	}
1608	else
1609	{
1610	/* Restore the text mode backup. */
1611	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1612
1613	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1614
1615	/* Enable dirty page tracking again when going into legacy mode. */
1616	vmsvgaR3SetTraces(pDevIns, pThis, true);
1617
1618	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1619	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1620	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1621
1622	/* Clear the pitch lock. */
1623	pThis->svga.u32PitchLock = 0;
1624	}
1625	#else /* !IN_RING3 */
1626	rc = VINF_IOM_R3_IOPORT_WRITE;
1627	#endif /* !IN_RING3 */
1628	break;
1629
1630	case SVGA_REG_WIDTH:
1631	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1632	if (pThis->svga.uWidth != u32)
1633	{
1634	#if defined(IN_RING3) \|\| defined(IN_RING0)
1635	pThis->svga.uWidth = u32;
1636	vmsvgaHCUpdatePitch(pThis, pThisCC);
1637	if (pThis->svga.fEnabled)
1638	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1639	#else
1640	rc = VINF_IOM_R3_IOPORT_WRITE;
1641	#endif
1642	}
1643	/* else: nop */
1644	break;
1645
1646	case SVGA_REG_HEIGHT:
1647	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1648	if (pThis->svga.uHeight != u32)
1649	{
1650	pThis->svga.uHeight = u32;
1651	if (pThis->svga.fEnabled)
1652	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1653	}
1654	/* else: nop */
1655	break;
1656
1657	case SVGA_REG_DEPTH:
1658	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1659	/** @todo read-only?? */
1660	break;
1661
1662	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1663	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1664	if (pThis->svga.uBpp != u32)
1665	{
1666	#if defined(IN_RING3) \|\| defined(IN_RING0)
1667	pThis->svga.uBpp = u32;
1668	vmsvgaHCUpdatePitch(pThis, pThisCC);
1669	if (pThis->svga.fEnabled)
1670	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1671	#else
1672	rc = VINF_IOM_R3_IOPORT_WRITE;
1673	#endif
1674	}
1675	/* else: nop */
1676	break;
1677
1678	case SVGA_REG_PSEUDOCOLOR:
1679	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1680	break;
1681
1682	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1683	#ifdef IN_RING3
1684	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1685	pThis->svga.fConfigured = u32;
1686	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1687	if (!pThis->svga.fConfigured)
1688	pThis->svga.fTraces = true;
1689	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1690	#else
1691	rc = VINF_IOM_R3_IOPORT_WRITE;
1692	#endif
1693	break;
1694
1695	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1696	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1697	if ( pThis->svga.fEnabled
1698	&& pThis->svga.fConfigured)
1699	{
1700	#if defined(IN_RING3) \|\| defined(IN_RING0)
1701	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1702	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1703	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1704	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1705
1706	/* Kick the FIFO thread to start processing commands again. */
1707	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1708	#else
1709	rc = VINF_IOM_R3_IOPORT_WRITE;
1710	#endif
1711	}
1712	/* else nothing to do. */
1713	else
1714	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1715
1716	break;
1717
1718	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1719	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1720	break;
1721
1722	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1724	pThis->svga.u32GuestId = u32;
1725	break;
1726
1727	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1728	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1729	pThis->svga.u32PitchLock = u32;
1730	/* Should this also update the FIFO pitch lock? Unclear. */
1731	break;
1732
1733	case SVGA_REG_IRQMASK: /* Interrupt mask */
1734	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1735	pThis->svga.u32IrqMask = u32;
1736
1737	/* Irq pending after the above change? */
1738	if (pThis->svga.u32IrqStatus & u32)
1739	{
1740	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1741	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1742	}
1743	else
1744	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1745	break;
1746
1747	/* Mouse cursor support */
1748	case SVGA_REG_CURSOR_ID:
1749	case SVGA_REG_CURSOR_X:
1750	case SVGA_REG_CURSOR_Y:
1751	case SVGA_REG_CURSOR_ON:
1752	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1753	break;
1754
1755	/* Legacy multi-monitor support */
1756	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1757	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1758	break;
1759	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1760	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1761	break;
1762	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1763	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1764	break;
1765	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1766	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1767	break;
1768	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1769	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1770	break;
1771	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1772	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1773	break;
1774	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1776	break;
1777	#ifdef VBOX_WITH_VMSVGA3D
1778	/* See "Guest memory regions" below. */
1779	case SVGA_REG_GMR_ID:
1780	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1781	pThis->svga.u32CurrentGMRId = u32;
1782	break;
1783
1784	case SVGA_REG_GMR_DESCRIPTOR:
1785	# ifndef IN_RING3
1786	rc = VINF_IOM_R3_IOPORT_WRITE;
1787	break;
1788	# else /* IN_RING3 */
1789	{
1790	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1791
1792	/* Validate current GMR id. */
1793	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1794	AssertBreak(idGMR < pThis->svga.cGMR);
1795	RT_UNTRUSTED_VALIDATED_FENCE();
1796
1797	/* Free the old GMR if present. */
1798	vmsvgaR3GmrFree(pThisCC, idGMR);
1799
1800	/* Just undefine the GMR? */
1801	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1802	if (GCPhys == 0)
1803	{
1804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1805	break;
1806	}
1807
1808
1809	/* Never cross a page boundary automatically. */
1810	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1811	uint32_t cPagesTotal = 0;
1812	uint32_t iDesc = 0;
1813	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1814	uint32_t cLoops = 0;
1815	RTGCPHYS GCPhysBase = GCPhys;
1816	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1817	{
1818	/* Read descriptor. */
1819	SVGAGuestMemDescriptor desc;
1820	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1821	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1822
1823	if (desc.numPages != 0)
1824	{
1825	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1826	cPagesTotal += desc.numPages;
1827	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1828
1829	if ((iDesc & 15) == 0)
1830	{
1831	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1832	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1833	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1834	}
1835
1836	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1837	paDescs[iDesc++].numPages = desc.numPages;
1838
1839	/* Continue with the next descriptor. */
1840	GCPhys += sizeof(desc);
1841	}
1842	else if (desc.ppn == 0)
1843	break; /* terminator */
1844	else /* Pointer to the next physical page of descriptors. */
1845	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1846
1847	cLoops++;
1848	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1849	}
1850
1851	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1852	if (RT_SUCCESS(rc))
1853	{
1854	/* Commit the GMR. */
1855	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1856	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1857	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1858	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1859	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1860	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1861	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1862	}
1863	else
1864	{
1865	RTMemFree(paDescs);
1866	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1867	}
1868	break;
1869	}
1870	# endif /* IN_RING3 */
1871	#endif // VBOX_WITH_VMSVGA3D
1872
1873	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1874	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1875	if (pThis->svga.fTraces == u32)
1876	break; /* nothing to do */
1877
1878	#ifdef IN_RING3
1879	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1880	#else
1881	rc = VINF_IOM_R3_IOPORT_WRITE;
1882	#endif
1883	break;
1884
1885	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1886	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1887	break;
1888
1889	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1891	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1892	break;
1893
1894	case SVGA_REG_FB_START:
1895	case SVGA_REG_MEM_START:
1896	case SVGA_REG_HOST_BITS_PER_PIXEL:
1897	case SVGA_REG_MAX_WIDTH:
1898	case SVGA_REG_MAX_HEIGHT:
1899	case SVGA_REG_VRAM_SIZE:
1900	case SVGA_REG_FB_SIZE:
1901	case SVGA_REG_CAPABILITIES:
1902	case SVGA_REG_MEM_SIZE:
1903	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1904	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1905	case SVGA_REG_BYTES_PER_LINE:
1906	case SVGA_REG_FB_OFFSET:
1907	case SVGA_REG_RED_MASK:
1908	case SVGA_REG_GREEN_MASK:
1909	case SVGA_REG_BLUE_MASK:
1910	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1911	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1912	case SVGA_REG_GMR_MAX_IDS:
1913	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1914	/* Read only - ignore. */
1915	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1916	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1917	break;
1918
1919	default:
1920	{
1921	uint32_t offReg;
1922	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1923	{
1924	RT_UNTRUSTED_VALIDATED_FENCE();
1925	pThis->svga.au32ScratchRegion[offReg] = u32;
1926	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1927	}
1928	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1929	{
1930	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1931	Btw, see rgb_to_pixel32. */
1932	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1933	u32 &= 0xff;
1934	RT_UNTRUSTED_VALIDATED_FENCE();
1935	uint32_t uRgb = pThis->last_palette[offReg / 3];
1936	switch (offReg % 3)
1937	{
1938	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1939	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1940	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1941	}
1942	pThis->last_palette[offReg / 3] = uRgb;
1943	}
1944	else
1945	{
1946	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1947	rc = VINF_IOM_R3_IOPORT_WRITE;
1948	#else
1949	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
1950	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
1951	#endif
1952	}
1953	break;
1954	}
1955	}
1956	return rc;
1957	}
1958
1959	/**
1960	* @callback_method_impl{FNIOMIOPORTNEWIN}
1961	*/
1962	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
1963	{
1964	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
1965	RT_NOREF_PV(pvUser);
1966
1967	/* Only dword accesses. */
1968	if (cb == 4)
1969	{
1970	switch (offPort)
1971	{
1972	case SVGA_INDEX_PORT:
1973	*pu32 = pThis->svga.u32IndexReg;
1974	break;
1975
1976	case SVGA_VALUE_PORT:
1977	return vmsvgaReadPort(pDevIns, pThis, pu32);
1978
1979	case SVGA_BIOS_PORT:
1980	Log(("Ignoring BIOS port read\n"));
1981	*pu32 = 0;
1982	break;
1983
1984	case SVGA_IRQSTATUS_PORT:
1985	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
1986	*pu32 = pThis->svga.u32IrqStatus;
1987	break;
1988
1989	default:
1990	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
1991	*pu32 = UINT32_MAX;
1992	break;
1993	}
1994	}
1995	else
1996	{
1997	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
1998	*pu32 = UINT32_MAX;
1999	}
2000	return VINF_SUCCESS;
2001	}
2002
2003	/**
2004	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2005	*/
2006	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2007	{
2008	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2009	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2010	RT_NOREF_PV(pvUser);
2011
2012	/* Only dword accesses. */
2013	if (cb == 4)
2014	switch (offPort)
2015	{
2016	case SVGA_INDEX_PORT:
2017	pThis->svga.u32IndexReg = u32;
2018	break;
2019
2020	case SVGA_VALUE_PORT:
2021	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2022
2023	case SVGA_BIOS_PORT:
2024	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2025	break;
2026
2027	case SVGA_IRQSTATUS_PORT:
2028	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2029	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2030	/* Clear the irq in case all events have been cleared. */
2031	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2032	{
2033	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2034	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2035	}
2036	break;
2037
2038	default:
2039	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2040	break;
2041	}
2042	else
2043	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2044
2045	return VINF_SUCCESS;
2046	}
2047
2048	#ifdef IN_RING3
2049
2050	# ifdef DEBUG_FIFO_ACCESS
2051	/**
2052	* Handle FIFO memory access.
2053	* @returns VBox status code.
2054	* @param pVM VM handle.
2055	* @param pThis The shared VGA/VMSVGA instance data.
2056	* @param GCPhys The access physical address.
2057	* @param fWriteAccess Read or write access
2058	*/
2059	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2060	{
2061	RT_NOREF(pVM);
2062	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2063	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2064
2065	switch (GCPhysOffset >> 2)
2066	{
2067	case SVGA_FIFO_MIN:
2068	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2069	break;
2070	case SVGA_FIFO_MAX:
2071	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2072	break;
2073	case SVGA_FIFO_NEXT_CMD:
2074	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2075	break;
2076	case SVGA_FIFO_STOP:
2077	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2078	break;
2079	case SVGA_FIFO_CAPABILITIES:
2080	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2081	break;
2082	case SVGA_FIFO_FLAGS:
2083	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2084	break;
2085	case SVGA_FIFO_FENCE:
2086	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2087	break;
2088	case SVGA_FIFO_3D_HWVERSION:
2089	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2090	break;
2091	case SVGA_FIFO_PITCHLOCK:
2092	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2093	break;
2094	case SVGA_FIFO_CURSOR_ON:
2095	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2096	break;
2097	case SVGA_FIFO_CURSOR_X:
2098	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2099	break;
2100	case SVGA_FIFO_CURSOR_Y:
2101	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2102	break;
2103	case SVGA_FIFO_CURSOR_COUNT:
2104	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2105	break;
2106	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2107	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2108	break;
2109	case SVGA_FIFO_RESERVED:
2110	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2111	break;
2112	case SVGA_FIFO_CURSOR_SCREEN_ID:
2113	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2114	break;
2115	case SVGA_FIFO_DEAD:
2116	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2117	break;
2118	case SVGA_FIFO_3D_HWVERSION_REVISED:
2119	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2120	break;
2121	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2122	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2123	break;
2124	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2125	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2126	break;
2127	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2128	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2129	break;
2130	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2131	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2132	break;
2133	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2134	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2135	break;
2136	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2137	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2138	break;
2139	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2140	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2141	break;
2142	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2143	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2144	break;
2145	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2146	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2147	break;
2148	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2149	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2150	break;
2151	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2152	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2153	break;
2154	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2155	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2156	break;
2157	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2158	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2159	break;
2160	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2161	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2162	break;
2163	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2164	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2165	break;
2166	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2167	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2168	break;
2169	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2170	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2171	break;
2172	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2173	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2174	break;
2175	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2176	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2177	break;
2178	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2179	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2180	break;
2181	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2182	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2183	break;
2184	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2185	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2186	break;
2187	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2188	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2189	break;
2190	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2191	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2192	break;
2193	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2194	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2195	break;
2196	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2197	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2198	break;
2199	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2200	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2201	break;
2202	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2203	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2204	break;
2205	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2206	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2207	break;
2208	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2209	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2210	break;
2211	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2212	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2213	break;
2214	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2215	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2216	break;
2217	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2218	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2219	break;
2220	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2221	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2222	break;
2223	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2224	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2225	break;
2226	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2227	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2228	break;
2229	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2230	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2231	break;
2232	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2233	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2234	break;
2235	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2236	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2237	break;
2238	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2239	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2240	break;
2241	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2242	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2243	break;
2244	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2245	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2246	break;
2247	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2248	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2249	break;
2250	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2251	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2252	break;
2253	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2254	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2255	break;
2256	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2257	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2258	break;
2259	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2260	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2261	break;
2262	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2263	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2264	break;
2265	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2266	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2267	break;
2268	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2269	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2270	break;
2271	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2272	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2273	break;
2274	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2275	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2276	break;
2277	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2278	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2279	break;
2280	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2281	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2282	break;
2283	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2284	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2285	break;
2286	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2287	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2288	break;
2289	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2290	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2291	break;
2292	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2293	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2294	break;
2295	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2296	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2297	break;
2298	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2299	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2300	break;
2301	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2302	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2303	break;
2304	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2305	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2306	break;
2307	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2308	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2309	break;
2310	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2311	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2312	break;
2313	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2314	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2315	break;
2316	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2317	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2318	break;
2319	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2320	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2321	break;
2322	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2323	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2324	break;
2325	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2326	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2327	break;
2328	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2329	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2330	break;
2331	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2332	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2333	break;
2334	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2335	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2336	break;
2337	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2338	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2339	break;
2340	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2341	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2342	break;
2343	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2344	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2345	break;
2346	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2347	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2348	break;
2349	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2350	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2351	break;
2352	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2353	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2354	break;
2355	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2356	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2357	break;
2358	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2359	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2360	break;
2361	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2362	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2363	break;
2364	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2365	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2366	break;
2367	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2368	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2369	break;
2370	case SVGA_FIFO_3D_CAPS_LAST:
2371	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2372	break;
2373	case SVGA_FIFO_GUEST_3D_HWVERSION:
2374	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2375	break;
2376	case SVGA_FIFO_FENCE_GOAL:
2377	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2378	break;
2379	case SVGA_FIFO_BUSY:
2380	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2381	break;
2382	default:
2383	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2384	break;
2385	}
2386
2387	return VINF_EM_RAW_EMULATE_INSTR;
2388	}
2389	# endif /* DEBUG_FIFO_ACCESS */
2390
2391	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2392	/**
2393	* HC access handler for the FIFO.
2394	*
2395	* @returns VINF_SUCCESS if the handler have carried out the operation.
2396	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2397	* @param pVM VM Handle.
2398	* @param pVCpu The cross context CPU structure for the calling EMT.
2399	* @param GCPhys The physical address the guest is writing to.
2400	* @param pvPhys The HC mapping of that address.
2401	* @param pvBuf What the guest is reading/writing.
2402	* @param cbBuf How much it's reading/writing.
2403	* @param enmAccessType The access type.
2404	* @param enmOrigin Who is making the access.
2405	* @param pvUser User argument.
2406	*/
2407	static DECLCALLBACK(VBOXSTRICTRC)
2408	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2409	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2410	{
2411	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2412	PVGASTATE pThis = (PVGASTATE)pvUser;
2413	AssertPtr(pThis);
2414
2415	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2416	/*
2417	* Wake up the FIFO thread as it might have work to do now.
2418	*/
2419	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2420	AssertLogRelRC(rc);
2421	# endif
2422
2423	# ifdef DEBUG_FIFO_ACCESS
2424	/*
2425	* When in debug-fifo-access mode, we do not disable the access handler,
2426	* but leave it on as we wish to catch all access.
2427	*/
2428	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2429	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2430	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2431	/*
2432	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2433	*/
2434	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2435	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2436	# endif
2437	if (RT_SUCCESS(rc))
2438	return VINF_PGM_HANDLER_DO_DEFAULT;
2439	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2440	return rc;
2441	}
2442	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2443
2444	#endif /* IN_RING3 */
2445
2446	#ifdef DEBUG_GMR_ACCESS
2447	# ifdef IN_RING3
2448
2449	/**
2450	* HC access handler for the FIFO.
2451	*
2452	* @returns VINF_SUCCESS if the handler have carried out the operation.
2453	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2454	* @param pVM VM Handle.
2455	* @param pVCpu The cross context CPU structure for the calling EMT.
2456	* @param GCPhys The physical address the guest is writing to.
2457	* @param pvPhys The HC mapping of that address.
2458	* @param pvBuf What the guest is reading/writing.
2459	* @param cbBuf How much it's reading/writing.
2460	* @param enmAccessType The access type.
2461	* @param enmOrigin Who is making the access.
2462	* @param pvUser User argument.
2463	*/
2464	static DECLCALLBACK(VBOXSTRICTRC)
2465	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2466	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2467	{
2468	PVGASTATE pThis = (PVGASTATE)pvUser;
2469	Assert(pThis);
2470	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2471	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2472
2473	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2474
2475	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2476	{
2477	PGMR pGMR = &pSVGAState->paGMR[i];
2478
2479	if (pGMR->numDescriptors)
2480	{
2481	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2482	{
2483	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2484	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2485	{
2486	/*
2487	* Turn off the write handler for this particular page and make it R/W.
2488	* Then return telling the caller to restart the guest instruction.
2489	*/
2490	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2491	AssertRC(rc);
2492	return VINF_PGM_HANDLER_DO_DEFAULT;
2493	}
2494	}
2495	}
2496	}
2497
2498	return VINF_PGM_HANDLER_DO_DEFAULT;
2499	}
2500
2501	/** Callback handler for VMR3ReqCallWaitU */
2502	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2503	{
2504	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2505	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2506	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2507	int rc;
2508
2509	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2510	{
2511	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2512	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2513	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2514	AssertRC(rc);
2515	}
2516	return VINF_SUCCESS;
2517	}
2518
2519	/** Callback handler for VMR3ReqCallWaitU */
2520	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2521	{
2522	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2523	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2524	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2525
2526	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2527	{
2528	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2529	AssertRC(rc);
2530	}
2531	return VINF_SUCCESS;
2532	}
2533
2534	/** Callback handler for VMR3ReqCallWaitU */
2535	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2536	{
2537	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2538
2539	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2540	{
2541	PGMR pGMR = &pSVGAState->paGMR[i];
2542
2543	if (pGMR->numDescriptors)
2544	{
2545	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2546	{
2547	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2548	AssertRC(rc);
2549	}
2550	}
2551	}
2552	return VINF_SUCCESS;
2553	}
2554
2555	# endif /* IN_RING3 */
2556	#endif /* DEBUG_GMR_ACCESS */
2557
2558	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2559
2560	#ifdef IN_RING3
2561
2562
2563	/**
2564	* Common worker for changing the pointer shape.
2565	*
2566	* @param pThisCC The VGA/VMSVGA state for ring-3.
2567	* @param pSVGAState The VMSVGA ring-3 instance data.
2568	* @param fAlpha Whether there is alpha or not.
2569	* @param xHot Hotspot x coordinate.
2570	* @param yHot Hotspot y coordinate.
2571	* @param cx Width.
2572	* @param cy Height.
2573	* @param pbData Heap copy of the cursor data. Consumed.
2574	* @param cbData The size of the data.
2575	*/
2576	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2577	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2578	{
2579	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2580	# ifdef LOG_ENABLED
2581	if (LogIs2Enabled())
2582	{
2583	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2584	if (!fAlpha)
2585	{
2586	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2587	for (uint32_t y = 0; y < cy; y++)
2588	{
2589	Log2(("%3u:", y));
2590	uint8_t const pbLine = &pbData[y cbAndLine];
2591	for (uint32_t x = 0; x < cx; x += 8)
2592	{
2593	uint8_t b = pbLine[x / 8];
2594	char szByte[12];
2595	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2596	szByte[1] = b & 0x40 ? '*' : ' ';
2597	szByte[2] = b & 0x20 ? '*' : ' ';
2598	szByte[3] = b & 0x10 ? '*' : ' ';
2599	szByte[4] = b & 0x08 ? '*' : ' ';
2600	szByte[5] = b & 0x04 ? '*' : ' ';
2601	szByte[6] = b & 0x02 ? '*' : ' ';
2602	szByte[7] = b & 0x01 ? '*' : ' ';
2603	szByte[8] = '\0';
2604	Log2(("%s", szByte));
2605	}
2606	Log2(("\n"));
2607	}
2608	}
2609
2610	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2611	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2612	for (uint32_t y = 0; y < cy; y++)
2613	{
2614	Log2(("%3u:", y));
2615	uint32_t const pu32Line = &pu32Xor[y cx];
2616	for (uint32_t x = 0; x < cx; x++)
2617	Log2((" %08x", pu32Line[x]));
2618	Log2(("\n"));
2619	}
2620	}
2621	# endif
2622
2623	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2624	AssertRC(rc);
2625
2626	if (pSVGAState->Cursor.fActive)
2627	RTMemFree(pSVGAState->Cursor.pData);
2628
2629	pSVGAState->Cursor.fActive = true;
2630	pSVGAState->Cursor.xHotspot = xHot;
2631	pSVGAState->Cursor.yHotspot = yHot;
2632	pSVGAState->Cursor.width = cx;
2633	pSVGAState->Cursor.height = cy;
2634	pSVGAState->Cursor.cbData = cbData;
2635	pSVGAState->Cursor.pData = pbData;
2636	}
2637
2638
2639	/**
2640	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2641	*
2642	* @param pThis The shared VGA/VMSVGA state.
2643	* @param pThisCC The VGA/VMSVGA state for ring-3.
2644	* @param pSVGAState The VMSVGA ring-3 instance data.
2645	* @param pCursor The cursor.
2646	* @param pbSrcAndMask The AND mask.
2647	* @param cbSrcAndLine The scanline length of the AND mask.
2648	* @param pbSrcXorMask The XOR mask.
2649	* @param cbSrcXorLine The scanline length of the XOR mask.
2650	*/
2651	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2652	SVGAFifoCmdDefineCursor const *pCursor,
2653	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2654	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2655	{
2656	uint32_t const cx = pCursor->width;
2657	uint32_t const cy = pCursor->height;
2658
2659	/*
2660	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2661	* The AND data uses 8-bit aligned scanlines.
2662	* The XOR data must be starting on a 32-bit boundrary.
2663	*/
2664	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2665	uint32_t cbDstAndMask = cbDstAndLine * cy;
2666	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2667	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2668
2669	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2670	AssertReturnVoid(pbCopy);
2671
2672	/* Convert the AND mask. */
2673	uint8_t *pbDst = pbCopy;
2674	uint8_t const *pbSrc = pbSrcAndMask;
2675	switch (pCursor->andMaskDepth)
2676	{
2677	case 1:
2678	if (cbSrcAndLine == cbDstAndLine)
2679	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2680	else
2681	{
2682	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2683	for (uint32_t y = 0; y < cy; y++)
2684	{
2685	memcpy(pbDst, pbSrc, cbDstAndLine);
2686	pbDst += cbDstAndLine;
2687	pbSrc += cbSrcAndLine;
2688	}
2689	}
2690	break;
2691	/* Should take the XOR mask into account for the multi-bit AND mask. */
2692	case 8:
2693	for (uint32_t y = 0; y < cy; y++)
2694	{
2695	for (uint32_t x = 0; x < cx; )
2696	{
2697	uint8_t bDst = 0;
2698	uint8_t fBit = 1;
2699	do
2700	{
2701	uintptr_t const idxPal = pbSrc[x] * 3;
2702	if ((( pThis->last_palette[idxPal]
2703	\| (pThis->last_palette[idxPal] >> 8)
2704	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2705	bDst \|= fBit;
2706	fBit <<= 1;
2707	x++;
2708	} while (x < cx && (x & 7));
2709	pbDst[(x - 1) / 8] = bDst;
2710	}
2711	pbDst += cbDstAndLine;
2712	pbSrc += cbSrcAndLine;
2713	}
2714	break;
2715	case 15:
2716	for (uint32_t y = 0; y < cy; y++)
2717	{
2718	for (uint32_t x = 0; x < cx; )
2719	{
2720	uint8_t bDst = 0;
2721	uint8_t fBit = 1;
2722	do
2723	{
2724	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2725	bDst \|= fBit;
2726	fBit <<= 1;
2727	x++;
2728	} while (x < cx && (x & 7));
2729	pbDst[(x - 1) / 8] = bDst;
2730	}
2731	pbDst += cbDstAndLine;
2732	pbSrc += cbSrcAndLine;
2733	}
2734	break;
2735	case 16:
2736	for (uint32_t y = 0; y < cy; y++)
2737	{
2738	for (uint32_t x = 0; x < cx; )
2739	{
2740	uint8_t bDst = 0;
2741	uint8_t fBit = 1;
2742	do
2743	{
2744	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2745	bDst \|= fBit;
2746	fBit <<= 1;
2747	x++;
2748	} while (x < cx && (x & 7));
2749	pbDst[(x - 1) / 8] = bDst;
2750	}
2751	pbDst += cbDstAndLine;
2752	pbSrc += cbSrcAndLine;
2753	}
2754	break;
2755	case 24:
2756	for (uint32_t y = 0; y < cy; y++)
2757	{
2758	for (uint32_t x = 0; x < cx; )
2759	{
2760	uint8_t bDst = 0;
2761	uint8_t fBit = 1;
2762	do
2763	{
2764	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2765	bDst \|= fBit;
2766	fBit <<= 1;
2767	x++;
2768	} while (x < cx && (x & 7));
2769	pbDst[(x - 1) / 8] = bDst;
2770	}
2771	pbDst += cbDstAndLine;
2772	pbSrc += cbSrcAndLine;
2773	}
2774	break;
2775	case 32:
2776	for (uint32_t y = 0; y < cy; y++)
2777	{
2778	for (uint32_t x = 0; x < cx; )
2779	{
2780	uint8_t bDst = 0;
2781	uint8_t fBit = 1;
2782	do
2783	{
2784	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2785	bDst \|= fBit;
2786	fBit <<= 1;
2787	x++;
2788	} while (x < cx && (x & 7));
2789	pbDst[(x - 1) / 8] = bDst;
2790	}
2791	pbDst += cbDstAndLine;
2792	pbSrc += cbSrcAndLine;
2793	}
2794	break;
2795	default:
2796	RTMemFree(pbCopy);
2797	AssertFailedReturnVoid();
2798	}
2799
2800	/* Convert the XOR mask. */
2801	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2802	pbSrc = pbSrcXorMask;
2803	switch (pCursor->xorMaskDepth)
2804	{
2805	case 1:
2806	for (uint32_t y = 0; y < cy; y++)
2807	{
2808	for (uint32_t x = 0; x < cx; )
2809	{
2810	/* most significant bit is the left most one. */
2811	uint8_t bSrc = pbSrc[x / 8];
2812	do
2813	{
2814	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2815	bSrc <<= 1;
2816	x++;
2817	} while ((x & 7) && x < cx);
2818	}
2819	pbSrc += cbSrcXorLine;
2820	}
2821	break;
2822	case 8:
2823	for (uint32_t y = 0; y < cy; y++)
2824	{
2825	for (uint32_t x = 0; x < cx; x++)
2826	{
2827	uint32_t u = pThis->last_palette[pbSrc[x]];
2828	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2829	}
2830	pbSrc += cbSrcXorLine;
2831	}
2832	break;
2833	case 15: /* Src: RGB-5-5-5 */
2834	for (uint32_t y = 0; y < cy; y++)
2835	{
2836	for (uint32_t x = 0; x < cx; x++)
2837	{
2838	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2839	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2840	((uValue >> 5) & 0x1f) << 3,
2841	((uValue >> 10) & 0x1f) << 3, 0);
2842	}
2843	pbSrc += cbSrcXorLine;
2844	}
2845	break;
2846	case 16: /* Src: RGB-5-6-5 */
2847	for (uint32_t y = 0; y < cy; y++)
2848	{
2849	for (uint32_t x = 0; x < cx; x++)
2850	{
2851	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2852	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2853	((uValue >> 5) & 0x3f) << 2,
2854	((uValue >> 11) & 0x1f) << 3, 0);
2855	}
2856	pbSrc += cbSrcXorLine;
2857	}
2858	break;
2859	case 24:
2860	for (uint32_t y = 0; y < cy; y++)
2861	{
2862	for (uint32_t x = 0; x < cx; x++)
2863	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2864	pbSrc += cbSrcXorLine;
2865	}
2866	break;
2867	case 32:
2868	for (uint32_t y = 0; y < cy; y++)
2869	{
2870	for (uint32_t x = 0; x < cx; x++)
2871	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2872	pbSrc += cbSrcXorLine;
2873	}
2874	break;
2875	default:
2876	RTMemFree(pbCopy);
2877	AssertFailedReturnVoid();
2878	}
2879
2880	/*
2881	* Pass it to the frontend/whatever.
2882	*/
2883	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2884	}
2885
2886
2887	/**
2888	* Worker for vmsvgaR3FifoThread that handles an external command.
2889	*
2890	* @param pDevIns The device instance.
2891	* @param pThis The shared VGA/VMSVGA instance data.
2892	* @param pThisCC The VGA/VMSVGA state for ring-3.
2893	*/
2894	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2895	{
2896	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2897	switch (pThis->svga.u8FIFOExtCommand)
2898	{
2899	case VMSVGA_FIFO_EXTCMD_RESET:
2900	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2901	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2902	# ifdef VBOX_WITH_VMSVGA3D
2903	if (pThis->svga.f3DEnabled)
2904	{
2905	/* The 3d subsystem must be reset from the fifo thread. */
2906	vmsvga3dReset(pThisCC);
2907	}
2908	# endif
2909	break;
2910
2911	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2912	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2913	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2914	# ifdef VBOX_WITH_VMSVGA3D
2915	if (pThis->svga.f3DEnabled)
2916	{
2917	/* The 3d subsystem must be shut down from the fifo thread. */
2918	vmsvga3dTerminate(pThisCC);
2919	}
2920	# endif
2921	break;
2922
2923	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2924	{
2925	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2926	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2927	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2928	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2929	# ifdef VBOX_WITH_VMSVGA3D
2930	if (pThis->svga.f3DEnabled)
2931	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2932	# endif
2933	break;
2934	}
2935
2936	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2937	{
2938	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2939	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2940	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2941	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2942	# ifdef VBOX_WITH_VMSVGA3D
2943	if (pThis->svga.f3DEnabled)
2944	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2945	# endif
2946	break;
2947	}
2948
2949	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
2950	{
2951	# ifdef VBOX_WITH_VMSVGA3D
2952	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
2953	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
2954	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
2955	# endif
2956	break;
2957	}
2958
2959
2960	default:
2961	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
2962	break;
2963	}
2964
2965	/*
2966	* Signal the end of the external command.
2967	*/
2968	pThisCC->svga.pvFIFOExtCmdParam = NULL;
2969	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
2970	ASMMemoryFence(); /* paranoia^2 */
2971	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
2972	AssertLogRelRC(rc);
2973	}
2974
2975	/**
2976	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
2977	* doing a job on the FIFO thread (even when it's officially suspended).
2978	*
2979	* @returns VBox status code (fully asserted).
2980	* @param pDevIns The device instance.
2981	* @param pThis The shared VGA/VMSVGA instance data.
2982	* @param pThisCC The VGA/VMSVGA state for ring-3.
2983	* @param uExtCmd The command to execute on the FIFO thread.
2984	* @param pvParam Pointer to command parameters.
2985	* @param cMsWait The time to wait for the command, given in
2986	* milliseconds.
2987	*/
2988	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
2989	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
2990	{
2991	Assert(cMsWait >= RT_MS_1SEC * 5);
2992	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
2993	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
2994
2995	int rc;
2996	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
2997	PDMTHREADSTATE enmState = pThread->enmState;
2998	if (enmState == PDMTHREADSTATE_SUSPENDED)
2999	{
3000	/*
3001	* The thread is suspended, we have to temporarily wake it up so it can
3002	* perform the task.
3003	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3004	*/
3005	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3006	/* Post the request. */
3007	pThis->svga.fFifoExtCommandWakeup = true;
3008	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3009	pThis->svga.u8FIFOExtCommand = uExtCmd;
3010	ASMMemoryFence(); /* paranoia^3 */
3011
3012	/* Resume the thread. */
3013	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3014	AssertLogRelRC(rc);
3015	if (RT_SUCCESS(rc))
3016	{
3017	/* Wait. Take care in case the semaphore was already posted (same as below). */
3018	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3019	if ( rc == VINF_SUCCESS
3020	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3021	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3022	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3023	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3024
3025	/* suspend the thread */
3026	pThis->svga.fFifoExtCommandWakeup = false;
3027	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3028	AssertLogRelRC(rc2);
3029	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3030	rc = rc2;
3031	}
3032	pThis->svga.fFifoExtCommandWakeup = false;
3033	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3034	}
3035	else if (enmState == PDMTHREADSTATE_RUNNING)
3036	{
3037	/*
3038	* The thread is running, should only happen during reset and vmsvga3dsfc.
3039	* We ASSUME not racing code here, both wrt thread state and ext commands.
3040	*/
3041	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3042	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3043
3044	/* Post the request. */
3045	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3046	pThis->svga.u8FIFOExtCommand = uExtCmd;
3047	ASMMemoryFence(); /* paranoia^2 */
3048	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3049	AssertLogRelRC(rc);
3050
3051	/* Wait. Take care in case the semaphore was already posted (same as above). */
3052	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3053	if ( rc == VINF_SUCCESS
3054	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3055	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3056	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3057	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3058
3059	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3060	}
3061	else
3062	{
3063	/*
3064	* Something is wrong with the thread!
3065	*/
3066	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3067	rc = VERR_INVALID_STATE;
3068	}
3069	return rc;
3070	}
3071
3072
3073	/**
3074	* Marks the FIFO non-busy, notifying any waiting EMTs.
3075	*
3076	* @param pDevIns The device instance.
3077	* @param pThis The shared VGA/VMSVGA instance data.
3078	* @param pThisCC The VGA/VMSVGA state for ring-3.
3079	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3080	* @param offFifoMin The start byte offset of the command FIFO.
3081	*/
3082	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3083	{
3084	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3085	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3086	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3087
3088	/* Wake up any waiting EMTs. */
3089	if (pSVGAState->cBusyDelayedEmts > 0)
3090	{
3091	# ifdef VMSVGA_USE_EMT_HALT_CODE
3092	PVM pVM = PDMDevHlpGetVM(pDevIns);
3093	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3094	if (idCpu != NIL_VMCPUID)
3095	{
3096	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3097	while (idCpu-- > 0)
3098	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3099	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3100	}
3101	# else
3102	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3103	AssertRC(rc2);
3104	# endif
3105	}
3106	}
3107
3108	/**
3109	* Reads (more) payload into the command buffer.
3110	*
3111	* @returns pbBounceBuf on success
3112	* @retval (void *)1 if the thread was requested to stop.
3113	* @retval NULL on FIFO error.
3114	*
3115	* @param cbPayloadReq The number of bytes of payload requested.
3116	* @param pFIFO The FIFO.
3117	* @param offCurrentCmd The FIFO byte offset of the current command.
3118	* @param offFifoMin The start byte offset of the command FIFO.
3119	* @param offFifoMax The end byte offset of the command FIFO.
3120	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3121	* always sufficient size.
3122	* @param pcbAlreadyRead How much payload we've already read into the bounce
3123	* buffer. (We will NEVER re-read anything.)
3124	* @param pThread The calling PDM thread handle.
3125	* @param pThis The shared VGA/VMSVGA instance data.
3126	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3127	* statistics collection.
3128	* @param pDevIns The device instance.
3129	*/
3130	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3131	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3132	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3133	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3134	{
3135	Assert(pbBounceBuf);
3136	Assert(pcbAlreadyRead);
3137	Assert(offFifoMin < offFifoMax);
3138	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3139	Assert(offFifoMax <= pThis->svga.cbFIFO);
3140
3141	/*
3142	* Check if the requested payload size has already been satisfied .
3143	* .
3144	* When called to read more, the caller is responsible for making sure the .
3145	* new command size (cbRequsted) never is smaller than what has already .
3146	* been read.
3147	*/
3148	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3149	if (cbPayloadReq <= cbAlreadyRead)
3150	{
3151	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3152	return pbBounceBuf;
3153	}
3154
3155	/*
3156	* Commands bigger than the fifo buffer are invalid.
3157	*/
3158	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3159	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3160	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3161	NULL);
3162
3163	/*
3164	* Move offCurrentCmd past the command dword.
3165	*/
3166	offCurrentCmd += sizeof(uint32_t);
3167	if (offCurrentCmd >= offFifoMax)
3168	offCurrentCmd = offFifoMin;
3169
3170	/*
3171	* Do we have sufficient payload data available already?
3172	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3173	*/
3174	uint32_t cbAfter, cbBefore;
3175	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3176	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3177	if (offNextCmd >= offCurrentCmd)
3178	{
3179	if (RT_LIKELY(offNextCmd < offFifoMax))
3180	cbAfter = offNextCmd - offCurrentCmd;
3181	else
3182	{
3183	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3184	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3185	offNextCmd, offFifoMin, offFifoMax));
3186	cbAfter = offFifoMax - offCurrentCmd;
3187	}
3188	cbBefore = 0;
3189	}
3190	else
3191	{
3192	cbAfter = offFifoMax - offCurrentCmd;
3193	if (offNextCmd >= offFifoMin)
3194	cbBefore = offNextCmd - offFifoMin;
3195	else
3196	{
3197	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3198	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3199	offNextCmd, offFifoMin, offFifoMax));
3200	cbBefore = 0;
3201	}
3202	}
3203	if (cbAfter + cbBefore < cbPayloadReq)
3204	{
3205	/*
3206	* Insufficient, must wait for it to arrive.
3207	*/
3208	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3209	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3210	for (uint32_t i = 0;; i++)
3211	{
3212	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3213	{
3214	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3215	return (void *)(uintptr_t)1;
3216	}
3217	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3218	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3219
3220	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3221
3222	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3223	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3224	if (offNextCmd >= offCurrentCmd)
3225	{
3226	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3227	cbBefore = 0;
3228	}
3229	else
3230	{
3231	cbAfter = offFifoMax - offCurrentCmd;
3232	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3233	}
3234
3235	if (cbAfter + cbBefore >= cbPayloadReq)
3236	break;
3237	}
3238	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3239	}
3240
3241	/*
3242	* Copy out the memory and update what pcbAlreadyRead points to.
3243	*/
3244	if (cbAfter >= cbPayloadReq)
3245	memcpy(pbBounceBuf + cbAlreadyRead,
3246	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3247	cbPayloadReq - cbAlreadyRead);
3248	else
3249	{
3250	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3251	if (cbAlreadyRead < cbAfter)
3252	{
3253	memcpy(pbBounceBuf + cbAlreadyRead,
3254	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3255	cbAfter - cbAlreadyRead);
3256	cbAlreadyRead = cbAfter;
3257	}
3258	memcpy(pbBounceBuf + cbAlreadyRead,
3259	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3260	cbPayloadReq - cbAlreadyRead);
3261	}
3262	*pcbAlreadyRead = cbPayloadReq;
3263	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3264	return pbBounceBuf;
3265	}
3266
3267
3268	/**
3269	* Sends cursor position and visibility information from the FIFO to the front-end.
3270	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3271	*/
3272	static uint32_t
3273	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3274	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3275	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3276	{
3277	/*
3278	* Check if the cursor update counter has changed and try get a stable
3279	* set of values if it has. This is race-prone, especially consindering
3280	* the screen ID, but little we can do about that.
3281	*/
3282	uint32_t x, y, fVisible, idScreen;
3283	for (uint32_t i = 0; ; i++)
3284	{
3285	x = pFIFO[SVGA_FIFO_CURSOR_X];
3286	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3287	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3288	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3289	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3290	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3291	\|\| i > 3)
3292	break;
3293	if (i == 0)
3294	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3295	ASMNopPause();
3296	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3297	}
3298
3299	/*
3300	* Check if anything has changed, as calling into pDrv is not light-weight.
3301	*/
3302	if ( *pxLast == x
3303	&& *pyLast == y
3304	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3305	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3306	else
3307	{
3308	/*
3309	* Detected changes.
3310	*
3311	* We handle global, not per-screen visibility information by sending
3312	* pfnVBVAMousePointerShape without shape data.
3313	*/
3314	*pxLast = x;
3315	*pyLast = y;
3316	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3317	if (idScreen != SVGA_ID_INVALID)
3318	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3319	else if (*pfLastVisible != fVisible)
3320	{
3321	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3322	*pfLastVisible = fVisible;
3323	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3324	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3325	}
3326	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3327	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3328	}
3329
3330	/*
3331	* Update done. Signal this to the guest.
3332	*/
3333	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3334
3335	return uCursorUpdateCount;
3336	}
3337
3338
3339	/**
3340	* Checks if there is work to be done, either cursor updating or FIFO commands.
3341	*
3342	* @returns true if pending work, false if not.
3343	* @param pFIFO The FIFO to examine.
3344	* @param uLastCursorCount The last cursor update counter value.
3345	*/
3346	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3347	{
3348	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3349	return true;
3350
3351	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3352	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3353	return true;
3354
3355	return false;
3356	}
3357
3358
3359	/**
3360	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3361	*
3362	* @param pDevIns The device instance.
3363	* @param pThis The shared VGA/VMSVGA instance data.
3364	* @param pThisCC The VGA/VMSVGA state for ring-3.
3365	*/
3366	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3367	{
3368	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3369	to recheck it before doing the signalling. */
3370	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3371	AssertReturnVoid(pFIFO);
3372	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3373	&& pThis->svga.fFIFOThreadSleeping)
3374	{
3375	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3376	AssertRC(rc);
3377	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3378	}
3379	}
3380
3381
3382	/*
3383	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3384	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3385	*/
3386	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3387	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3388	*
3389	* Will break out of the switch on failure.
3390	* Will restart and quit the loop if the thread was requested to stop.
3391	*
3392	* @param a_PtrVar Request variable pointer.
3393	* @param a_Type Request typedef (not pointer) for casting.
3394	* @param a_cbPayloadReq How much payload to fetch.
3395	* @remarks Accesses a bunch of variables in the current scope!
3396	*/
3397	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3398	if (1) { \
3399	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3400	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3401	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3402	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3403	} else do {} while (0)
3404	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3405	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3406	* buffer after figuring out the actual command size.
3407	*
3408	* Will break out of the switch on failure.
3409	*
3410	* @param a_PtrVar Request variable pointer.
3411	* @param a_Type Request typedef (not pointer) for casting.
3412	* @param a_cbPayloadReq How much payload to fetch.
3413	* @remarks Accesses a bunch of variables in the current scope!
3414	*/
3415	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3416	if (1) { \
3417	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3418	} else do {} while (0)
3419
3420	/**
3421	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3422	*/
3423	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3424	{
3425	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3426	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3427	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3428	int rc;
3429
3430	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3431	return VINF_SUCCESS;
3432
3433	/*
3434	* Special mode where we only execute an external command and the go back
3435	* to being suspended. Currently, all ext cmds ends up here, with the reset
3436	* one also being eligble for runtime execution further down as well.
3437	*/
3438	if (pThis->svga.fFifoExtCommandWakeup)
3439	{
3440	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3441	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3442	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3443	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3444	else
3445	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3446	return VINF_SUCCESS;
3447	}
3448
3449
3450	/*
3451	* Signal the semaphore to make sure we don't wait for 250ms after a
3452	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3453	*/
3454	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3455
3456	/*
3457	* Allocate a bounce buffer for command we get from the FIFO.
3458	* (All code must return via the end of the function to free this buffer.)
3459	*/
3460	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3461	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3462
3463	/*
3464	* Polling/sleep interval config.
3465	*
3466	* We wait for an a short interval if the guest has recently given us work
3467	* to do, but the interval increases the longer we're kept idle. Once we've
3468	* reached the refresh timer interval, we'll switch to extended waits,
3469	* depending on it or the guest to kick us into action when needed.
3470	*
3471	* Should the refresh time go fishing, we'll just continue increasing the
3472	* sleep length till we reaches the 250 ms max after about 16 seconds.
3473	*/
3474	RTMSINTERVAL const cMsMinSleep = 16;
3475	RTMSINTERVAL const cMsIncSleep = 2;
3476	RTMSINTERVAL const cMsMaxSleep = 250;
3477	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3478	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3479
3480	/*
3481	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3482	*
3483	* Initialize with values that will detect an update from the guest.
3484	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3485	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3486	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3487	*/
3488	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3489	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3490	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3491	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3492	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3493
3494	/*
3495	* The FIFO loop.
3496	*/
3497	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3498	bool fBadOrDisabledFifo = false;
3499	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3500	{
3501	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3502	/*
3503	* Should service the run loop every so often.
3504	*/
3505	if (pThis->svga.f3DEnabled)
3506	vmsvga3dCocoaServiceRunLoop();
3507	# endif
3508
3509	/*
3510	* Unless there's already work pending, go to sleep for a short while.
3511	* (See polling/sleep interval config above.)
3512	*/
3513	if ( fBadOrDisabledFifo
3514	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3515	{
3516	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3517	Assert(pThis->cMilliesRefreshInterval > 0);
3518	if (cMsSleep < pThis->cMilliesRefreshInterval)
3519	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3520	else
3521	{
3522	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3523	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3524	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3525	# endif
3526	if ( !fBadOrDisabledFifo
3527	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3528	rc = VINF_SUCCESS;
3529	else
3530	{
3531	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3532	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3533	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3534	}
3535	}
3536	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3537	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3538	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3539	{
3540	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3541	break;
3542	}
3543	}
3544	else
3545	rc = VINF_SUCCESS;
3546	fBadOrDisabledFifo = false;
3547	if (rc == VERR_TIMEOUT)
3548	{
3549	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3550	{
3551	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3552	continue;
3553	}
3554	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3555
3556	Log(("vmsvgaR3FifoLoop: timeout\n"));
3557	}
3558	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3559	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3560	cMsSleep = cMsMinSleep;
3561
3562	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3563	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3564	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3565
3566	/*
3567	* Handle external commands (currently only reset).
3568	*/
3569	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3570	{
3571	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3572	continue;
3573	}
3574
3575	/*
3576	* The device must be enabled and configured.
3577	*/
3578	if ( !pThis->svga.fEnabled
3579	\|\| !pThis->svga.fConfigured)
3580	{
3581	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3582	fBadOrDisabledFifo = true;
3583	cMsSleep = cMsMaxSleep; /* cheat */
3584	continue;
3585	}
3586
3587	/*
3588	* Get and check the min/max values. We ASSUME that they will remain
3589	* unchanged while we process requests. A further ASSUMPTION is that
3590	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3591	* we don't read it back while in the loop.
3592	*/
3593	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3594	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3595	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3596	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3597	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3598	\|\| offFifoMax <= offFifoMin
3599	\|\| offFifoMax > pThis->svga.cbFIFO
3600	\|\| (offFifoMax & 3) != 0
3601	\|\| (offFifoMin & 3) != 0
3602	\|\| offCurrentCmd < offFifoMin
3603	\|\| offCurrentCmd > offFifoMax))
3604	{
3605	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3606	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3607	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3608	fBadOrDisabledFifo = true;
3609	continue;
3610	}
3611	RT_UNTRUSTED_VALIDATED_FENCE();
3612	if (RT_UNLIKELY(offCurrentCmd & 3))
3613	{
3614	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3615	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3616	offCurrentCmd &= ~UINT32_C(3);
3617	}
3618
3619	/*
3620	* Update the cursor position before we start on the FIFO commands.
3621	*/
3622	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3623	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3624	{
3625	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3626	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3627	{ /* halfways likely */ }
3628	else
3629	{
3630	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3631	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3632	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3633	}
3634	}
3635
3636	/*
3637	* Mark the FIFO as busy.
3638	*/
3639	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3640	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3641	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3642
3643	/*
3644	* Execute all queued FIFO commands.
3645	* Quit if pending external command or changes in the thread state.
3646	*/
3647	bool fDone = false;
3648	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3649	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3650	{
3651	uint32_t cbPayload = 0;
3652	uint32_t u32IrqStatus = 0;
3653
3654	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3655
3656	/* First check any pending actions. */
3657	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3658	{
3659	vmsvgaR3ChangeMode(pThis, pThisCC);
3660	# ifdef VBOX_WITH_VMSVGA3D
3661	if (pThisCC->svga.p3dState != NULL)
3662	vmsvga3dChangeMode(pThisCC);
3663	# endif
3664	}
3665
3666	/* Check for pending external commands (reset). */
3667	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3668	break;
3669
3670	/*
3671	* Process the command.
3672	*/
3673	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3674	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3675	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3676	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3677	switch (enmCmdId)
3678	{
3679	case SVGA_CMD_INVALID_CMD:
3680	/* Nothing to do. */
3681	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3682	break;
3683
3684	case SVGA_CMD_FENCE:
3685	{
3686	SVGAFifoCmdFence *pCmdFence;
3687	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3689	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3690	{
3691	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3692	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3693
3694	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3695	{
3696	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3697	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3698	}
3699	else
3700	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3701	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3702	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3703	{
3704	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3705	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3706	}
3707	}
3708	else
3709	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3710	break;
3711	}
3712	case SVGA_CMD_UPDATE:
3713	case SVGA_CMD_UPDATE_VERBOSE:
3714	{
3715	SVGAFifoCmdUpdate *pUpdate;
3716	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3717	if (enmCmdId == SVGA_CMD_UPDATE)
3718	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3719	else
3720	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3721	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3722	/** @todo Multiple screens? */
3723	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3724	AssertBreak(pScreen);
3725	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3726	break;
3727	}
3728
3729	case SVGA_CMD_DEFINE_CURSOR:
3730	{
3731	/* Followed by bitmap data. */
3732	SVGAFifoCmdDefineCursor *pCursor;
3733	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3734	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3735
3736	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3737	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3738	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3739	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3740	AssertBreak(pCursor->andMaskDepth <= 32);
3741	AssertBreak(pCursor->xorMaskDepth <= 32);
3742	RT_UNTRUSTED_VALIDATED_FENCE();
3743
3744	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3745	uint32_t cbAndMask = cbAndLine * pCursor->height;
3746	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3747	uint32_t cbXorMask = cbXorLine * pCursor->height;
3748	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3749
3750	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3751	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3752	break;
3753	}
3754
3755	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3756	{
3757	/* Followed by bitmap data. */
3758	uint32_t cbCursorShape, cbAndMask;
3759	uint8_t *pCursorCopy;
3760	uint32_t cbCmd;
3761
3762	SVGAFifoCmdDefineAlphaCursor *pCursor;
3763	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3764	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3765
3766	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3767
3768	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3769	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3770	RT_UNTRUSTED_VALIDATED_FENCE();
3771
3772	/* Refetch the bitmap data as well. */
3773	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3774	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3775	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3776
3777	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3778	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3779	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3780	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3781
3782	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3783	AssertBreak(pCursorCopy);
3784
3785	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3786	memset(pCursorCopy, 0xff, cbAndMask);
3787	/* Colour data */
3788	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3789
3790	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3791	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3792	break;
3793	}
3794
3795	case SVGA_CMD_ESCAPE:
3796	{
3797	/* Followed by nsize bytes of data. */
3798	SVGAFifoCmdEscape *pEscape;
3799	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3800	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3801
3802	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3803	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3804	RT_UNTRUSTED_VALIDATED_FENCE();
3805	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3806	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3807
3808	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3809	{
3810	AssertBreak(pEscape->size >= sizeof(uint32_t));
3811	RT_UNTRUSTED_VALIDATED_FENCE();
3812	uint32_t cmd = (uint32_t )(pEscape + 1);
3813	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3814
3815	switch (cmd)
3816	{
3817	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3818	{
3819	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3820	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3821	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3822
3823	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3824	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3825	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3826
3827	RT_NOREF_PV(pVideoCmd);
3828	break;
3829
3830	}
3831
3832	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3833	{
3834	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3835	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3836	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3837	RT_NOREF_PV(pVideoCmd);
3838	break;
3839	}
3840
3841	default:
3842	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3843	break;
3844	}
3845	}
3846	else
3847	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3848
3849	break;
3850	}
3851	# ifdef VBOX_WITH_VMSVGA3D
3852	case SVGA_CMD_DEFINE_GMR2:
3853	{
3854	SVGAFifoCmdDefineGMR2 *pCmd;
3855	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3856	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3857	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3858
3859	/* Validate current GMR id. */
3860	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3861	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3862	RT_UNTRUSTED_VALIDATED_FENCE();
3863
3864	if (!pCmd->numPages)
3865	{
3866	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3867	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3868	}
3869	else
3870	{
3871	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3872	if (pGMR->cMaxPages)
3873	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3874
3875	/* Not sure if we should always free the descriptor, but for simplicity
3876	we do so if the new size is smaller than the current. */
3877	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3878	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3879	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3880
3881	pGMR->cMaxPages = pCmd->numPages;
3882	/* The rest is done by the REMAP_GMR2 command. */
3883	}
3884	break;
3885	}
3886
3887	case SVGA_CMD_REMAP_GMR2:
3888	{
3889	/* Followed by page descriptors or guest ptr. */
3890	SVGAFifoCmdRemapGMR2 *pCmd;
3891	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3892	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3893
3894	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3895	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3896	RT_UNTRUSTED_VALIDATED_FENCE();
3897
3898	/* Calculate the size of what comes after next and fetch it. */
3899	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3900	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3901	cbCmd += sizeof(SVGAGuestPtr);
3902	else
3903	{
3904	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3905	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3906	{
3907	cbCmd += cbPageDesc;
3908	pCmd->numPages = 1;
3909	}
3910	else
3911	{
3912	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3913	cbCmd += cbPageDesc * pCmd->numPages;
3914	}
3915	}
3916	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3917
3918	/* Validate current GMR id and size. */
3919	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3920	RT_UNTRUSTED_VALIDATED_FENCE();
3921	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3922	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3923	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3924	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3925
3926	if (pCmd->numPages == 0)
3927	break;
3928
3929	/** @todo Move to a separate function vmsvgaGMRRemap() */
3930
3931	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3932	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3933
3934	/*
3935	* We flatten the existing descriptors into a page array, overwrite the
3936	* pages specified in this command and then recompress the descriptor.
3937	*/
3938	/** @todo Optimize the GMR remap algorithm! */
3939
3940	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3941	uint64_t *paNewPage64 = NULL;
3942	if (pGMR->paDesc)
3943	{
3944	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
3945
3946	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
3947	AssertBreak(paNewPage64);
3948
3949	uint32_t idxPage = 0;
3950	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3951	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3952	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
3953	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
3954	RT_UNTRUSTED_VALIDATED_FENCE();
3955	}
3956
3957	/* Free the old GMR if present. */
3958	if (pGMR->paDesc)
3959	RTMemFree(pGMR->paDesc);
3960
3961	/* Allocate the maximum amount possible (everything non-continuous) */
3962	PVMSVGAGMRDESCRIPTOR paDescs;
3963	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
3964	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
3965
3966	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3967	{
3968	/** @todo */
3969	AssertFailed();
3970	pGMR->numDescriptors = 0;
3971	}
3972	else
3973	{
3974	uint32_t paPages32 = (uint32_t )(pCmd + 1);
3975	uint64_t paPages64 = (uint64_t )(pCmd + 1);
3976	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3977
3978	if (paNewPage64)
3979	{
3980	/* Overwrite the old page array with the new page values. */
3981	if (fGCPhys64)
3982	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3983	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
3984	else
3985	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3986	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
3987
3988	/* Use the updated page array instead of the command data. */
3989	fGCPhys64 = true;
3990	paPages64 = paNewPage64;
3991	pCmd->numPages = cNewTotalPages;
3992	}
3993
3994	/* The first page. */
3995	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
3996	* applied to paNewPage64. */
3997	RTGCPHYS GCPhys;
3998	if (fGCPhys64)
3999	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4000	else
4001	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4002	paDescs[0].GCPhys = GCPhys;
4003	paDescs[0].numPages = 1;
4004
4005	/* Subsequent pages. */
4006	uint32_t iDescriptor = 0;
4007	for (uint32_t i = 1; i < pCmd->numPages; i++)
4008	{
4009	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4010	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4011	else
4012	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4013
4014	/* Continuous physical memory? */
4015	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4016	{
4017	Assert(paDescs[iDescriptor].numPages);
4018	paDescs[iDescriptor].numPages++;
4019	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4020	}
4021	else
4022	{
4023	iDescriptor++;
4024	paDescs[iDescriptor].GCPhys = GCPhys;
4025	paDescs[iDescriptor].numPages = 1;
4026	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4027	}
4028	}
4029
4030	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4031	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4032	pGMR->numDescriptors = iDescriptor + 1;
4033	}
4034
4035	if (paNewPage64)
4036	RTMemFree(paNewPage64);
4037
4038	# ifdef DEBUG_GMR_ACCESS
4039	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4040	# endif
4041	break;
4042	}
4043	# endif // VBOX_WITH_VMSVGA3D
4044	case SVGA_CMD_DEFINE_SCREEN:
4045	{
4046	/* The size of this command is specified by the guest and depends on capabilities. */
4047	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4048
4049	SVGAFifoCmdDefineScreen *pCmd;
4050	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4051	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4052	RT_UNTRUSTED_VALIDATED_FENCE();
4053
4054	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4055	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4056	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4057
4058	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4059	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4060	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4061
4062	uint32_t const idScreen = pCmd->screen.id;
4063	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4064
4065	uint32_t const uWidth = pCmd->screen.size.width;
4066	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4067
4068	uint32_t const uHeight = pCmd->screen.size.height;
4069	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4070
4071	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4072	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4073	AssertBreak(cbWidth <= cbPitch);
4074
4075	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4076	AssertBreak(uScreenOffset < pThis->vram_size);
4077
4078	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4079	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4080	AssertBreak( (uHeight == 0 && cbPitch == 0)
4081	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4082	RT_UNTRUSTED_VALIDATED_FENCE();
4083
4084	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4085
4086	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4087
4088	pScreen->fDefined = true;
4089	pScreen->fModified = true;
4090	pScreen->fuScreen = pCmd->screen.flags;
4091	pScreen->idScreen = idScreen;
4092	if (!fBlank)
4093	{
4094	AssertBreak(uWidth > 0 && uHeight > 0);
4095
4096	pScreen->xOrigin = pCmd->screen.root.x;
4097	pScreen->yOrigin = pCmd->screen.root.y;
4098	pScreen->cWidth = uWidth;
4099	pScreen->cHeight = uHeight;
4100	pScreen->offVRAM = uScreenOffset;
4101	pScreen->cbPitch = cbPitch;
4102	pScreen->cBpp = 32;
4103	}
4104	else
4105	{
4106	/* Keep old values. */
4107	}
4108
4109	pThis->svga.fGFBRegisters = false;
4110	vmsvgaR3ChangeMode(pThis, pThisCC);
4111	break;
4112	}
4113
4114	case SVGA_CMD_DESTROY_SCREEN:
4115	{
4116	SVGAFifoCmdDestroyScreen *pCmd;
4117	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4118	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4119
4120	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4121
4122	uint32_t const idScreen = pCmd->screenId;
4123	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4124	RT_UNTRUSTED_VALIDATED_FENCE();
4125
4126	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4127	pScreen->fModified = true;
4128	pScreen->fDefined = false;
4129	pScreen->idScreen = idScreen;
4130
4131	vmsvgaR3ChangeMode(pThis, pThisCC);
4132	break;
4133	}
4134
4135	case SVGA_CMD_DEFINE_GMRFB:
4136	{
4137	SVGAFifoCmdDefineGMRFB *pCmd;
4138	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4139	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4140
4141	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4142	pSVGAState->GMRFB.ptr = pCmd->ptr;
4143	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4144	pSVGAState->GMRFB.format = pCmd->format;
4145	break;
4146	}
4147
4148	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4149	{
4150	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4151	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4152	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4153
4154	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4155	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4156
4157	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4158	RT_UNTRUSTED_VALIDATED_FENCE();
4159
4160	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4161	AssertBreak(pScreen);
4162
4163	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4164	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4165
4166	/* Clip destRect to the screen dimensions. */
4167	SVGASignedRect screenRect;
4168	screenRect.left = 0;
4169	screenRect.top = 0;
4170	screenRect.right = pScreen->cWidth;
4171	screenRect.bottom = pScreen->cHeight;
4172	SVGASignedRect clipRect = pCmd->destRect;
4173	vmsvgaR3ClipRect(&screenRect, &clipRect);
4174	RT_UNTRUSTED_VALIDATED_FENCE();
4175
4176	uint32_t const width = clipRect.right - clipRect.left;
4177	uint32_t const height = clipRect.bottom - clipRect.top;
4178
4179	if ( width == 0
4180	\|\| height == 0)
4181	break; /* Nothing to do. */
4182
4183	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4184	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4185
4186	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4187	* Prepare parameters for vmsvgaR3GmrTransfer.
4188	*/
4189	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4190
4191	/* Destination: host buffer which describes the screen 0 VRAM.
4192	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4193	*/
4194	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4195	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4196	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4197	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4198	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4199	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4200	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4201	+ cbScanline * clipRect.top;
4202	int32_t const cbHstPitch = cbScanline;
4203
4204	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4205	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4206	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4207	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4208	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4209
4210	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4211	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4212	gstPtr, offGst, cbGstPitch,
4213	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4214	AssertRC(rc);
4215	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4216	break;
4217	}
4218
4219	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4220	{
4221	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4222	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4223	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4224
4225	/* Note! This can fetch 3d render results as well!! */
4226	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4227	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4228
4229	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4230	RT_UNTRUSTED_VALIDATED_FENCE();
4231
4232	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4233	AssertBreak(pScreen);
4234
4235	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4236	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4237
4238	/* Clip destRect to the screen dimensions. */
4239	SVGASignedRect screenRect;
4240	screenRect.left = 0;
4241	screenRect.top = 0;
4242	screenRect.right = pScreen->cWidth;
4243	screenRect.bottom = pScreen->cHeight;
4244	SVGASignedRect clipRect = pCmd->srcRect;
4245	vmsvgaR3ClipRect(&screenRect, &clipRect);
4246	RT_UNTRUSTED_VALIDATED_FENCE();
4247
4248	uint32_t const width = clipRect.right - clipRect.left;
4249	uint32_t const height = clipRect.bottom - clipRect.top;
4250
4251	if ( width == 0
4252	\|\| height == 0)
4253	break; /* Nothing to do. */
4254
4255	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4256	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4257
4258	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4259	* Prepare parameters for vmsvgaR3GmrTransfer.
4260	*/
4261	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4262
4263	/* Source: host buffer which describes the screen 0 VRAM.
4264	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4265	*/
4266	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4267	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4268	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4269	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4270	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4271	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4272	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4273	+ cbScanline * clipRect.top;
4274	int32_t const cbHstPitch = cbScanline;
4275
4276	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4277	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4278	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4279	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4280	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4281
4282	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4283	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4284	gstPtr, offGst, cbGstPitch,
4285	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4286	AssertRC(rc);
4287	break;
4288	}
4289
4290	case SVGA_CMD_ANNOTATION_FILL:
4291	{
4292	SVGAFifoCmdAnnotationFill *pCmd;
4293	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4295
4296	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4297	pSVGAState->colorAnnotation = pCmd->color;
4298	break;
4299	}
4300
4301	case SVGA_CMD_ANNOTATION_COPY:
4302	{
4303	SVGAFifoCmdAnnotationCopy *pCmd;
4304	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4305	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4306
4307	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4308	AssertFailed();
4309	break;
4310	}
4311
4312	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4313
4314	default:
4315	# ifdef VBOX_WITH_VMSVGA3D
4316	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4317	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4318	{
4319	RT_UNTRUSTED_VALIDATED_FENCE();
4320
4321	/* All 3d commands start with a common header, which defines the size of the command. */
4322	SVGA3dCmdHeader *pHdr;
4323	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4324	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4325	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4326	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4327
4328	if (RT_LIKELY(pThis->svga.f3DEnabled))
4329	{ /* likely */ }
4330	else
4331	{
4332	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4333	break;
4334	}
4335
4336	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4337	* Check that the 3D command has at least a_cbMin of payload bytes after the
4338	* header. Will break out of the switch if it doesn't.
4339	*/
4340	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4341	if (1) { \
4342	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4343	RT_UNTRUSTED_VALIDATED_FENCE(); \
4344	} else do {} while (0)
4345	switch ((int)enmCmdId)
4346	{
4347	case SVGA_3D_CMD_SURFACE_DEFINE:
4348	{
4349	uint32_t cMipLevels;
4350	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4351	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4352	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4353
4354	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4355	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4356	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4357	# ifdef DEBUG_GMR_ACCESS
4358	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4359	# endif
4360	break;
4361	}
4362
4363	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4364	{
4365	uint32_t cMipLevels;
4366	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4367	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4368	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4369
4370	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4371	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4372	pCmd->multisampleCount, pCmd->autogenFilter,
4373	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4374	break;
4375	}
4376
4377	case SVGA_3D_CMD_SURFACE_DESTROY:
4378	{
4379	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4380	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4381	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4382	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4383	break;
4384	}
4385
4386	case SVGA_3D_CMD_SURFACE_COPY:
4387	{
4388	uint32_t cCopyBoxes;
4389	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4390	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4391	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4392
4393	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4394	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4395	break;
4396	}
4397
4398	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4399	{
4400	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4401	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4402	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4403
4404	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4405	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4406	break;
4407	}
4408
4409	case SVGA_3D_CMD_SURFACE_DMA:
4410	{
4411	uint32_t cCopyBoxes;
4412	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4413	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4414	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4415
4416	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4417	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4418	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4419	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4420	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4421	break;
4422	}
4423
4424	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4425	{
4426	uint32_t cRects;
4427	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4428	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4429	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4430
4431	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4432	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4433	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4434	break;
4435	}
4436
4437	case SVGA_3D_CMD_CONTEXT_DEFINE:
4438	{
4439	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4440	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4441	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4442
4443	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4444	break;
4445	}
4446
4447	case SVGA_3D_CMD_CONTEXT_DESTROY:
4448	{
4449	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4450	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4451	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4452
4453	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4454	break;
4455	}
4456
4457	case SVGA_3D_CMD_SETTRANSFORM:
4458	{
4459	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4460	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4461	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4462
4463	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4464	break;
4465	}
4466
4467	case SVGA_3D_CMD_SETZRANGE:
4468	{
4469	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4470	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4471	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4472
4473	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4474	break;
4475	}
4476
4477	case SVGA_3D_CMD_SETRENDERSTATE:
4478	{
4479	uint32_t cRenderStates;
4480	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4481	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4482	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4483
4484	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4485	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4486	break;
4487	}
4488
4489	case SVGA_3D_CMD_SETRENDERTARGET:
4490	{
4491	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4492	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4493	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4494
4495	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4496	break;
4497	}
4498
4499	case SVGA_3D_CMD_SETTEXTURESTATE:
4500	{
4501	uint32_t cTextureStates;
4502	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4503	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4504	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4505
4506	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4507	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4508	break;
4509	}
4510
4511	case SVGA_3D_CMD_SETMATERIAL:
4512	{
4513	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4514	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4515	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4516
4517	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4518	break;
4519	}
4520
4521	case SVGA_3D_CMD_SETLIGHTDATA:
4522	{
4523	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4524	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4525	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4526
4527	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4528	break;
4529	}
4530
4531	case SVGA_3D_CMD_SETLIGHTENABLED:
4532	{
4533	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4534	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4535	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4536
4537	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4538	break;
4539	}
4540
4541	case SVGA_3D_CMD_SETVIEWPORT:
4542	{
4543	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4544	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4545	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4546
4547	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4548	break;
4549	}
4550
4551	case SVGA_3D_CMD_SETCLIPPLANE:
4552	{
4553	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4554	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4555	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4556
4557	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4558	break;
4559	}
4560
4561	case SVGA_3D_CMD_CLEAR:
4562	{
4563	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4564	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4565	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4566
4567	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4568	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4569	break;
4570	}
4571
4572	case SVGA_3D_CMD_PRESENT:
4573	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4574	{
4575	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4576	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4577	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4578	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4579	else
4580	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4581
4582	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4583
4584	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4585	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4586	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4587	break;
4588	}
4589
4590	case SVGA_3D_CMD_SHADER_DEFINE:
4591	{
4592	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4593	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4594	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4595
4596	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4597	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4598	break;
4599	}
4600
4601	case SVGA_3D_CMD_SHADER_DESTROY:
4602	{
4603	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4604	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4605	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4606
4607	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4608	break;
4609	}
4610
4611	case SVGA_3D_CMD_SET_SHADER:
4612	{
4613	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4614	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4615	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4616
4617	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4618	break;
4619	}
4620
4621	case SVGA_3D_CMD_SET_SHADER_CONST:
4622	{
4623	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4624	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4625	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4626
4627	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4628	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4629	break;
4630	}
4631
4632	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4633	{
4634	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4635	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4636	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4637
4638	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4639	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4640	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4641	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4642	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4643
4644	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4645	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4646
4647	RT_UNTRUSTED_VALIDATED_FENCE();
4648
4649	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4650	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4651	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4652
4653	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4654	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4655	pNumRange, cVertexDivisor, pVertexDivisor);
4656	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4657	break;
4658	}
4659
4660	case SVGA_3D_CMD_SETSCISSORRECT:
4661	{
4662	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4663	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4664	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4665
4666	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4667	break;
4668	}
4669
4670	case SVGA_3D_CMD_BEGIN_QUERY:
4671	{
4672	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4673	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4674	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4675
4676	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4677	break;
4678	}
4679
4680	case SVGA_3D_CMD_END_QUERY:
4681	{
4682	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4683	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4684	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4685
4686	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4687	break;
4688	}
4689
4690	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4691	{
4692	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4693	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4694	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4695
4696	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4697	break;
4698	}
4699
4700	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4701	{
4702	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4703	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4704	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4705
4706	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4707	break;
4708	}
4709
4710	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4711	/* context id + surface id? */
4712	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4713	break;
4714	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4715	/* context id + surface id? */
4716	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4717	break;
4718
4719	default:
4720	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4721	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4722	break;
4723	}
4724	}
4725	else
4726	# endif // VBOX_WITH_VMSVGA3D
4727	{
4728	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4729	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4730	}
4731	}
4732
4733	/* Go to the next slot */
4734	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4735	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4736	if (offCurrentCmd >= offFifoMax)
4737	{
4738	offCurrentCmd -= offFifoMax - offFifoMin;
4739	Assert(offCurrentCmd >= offFifoMin);
4740	Assert(offCurrentCmd < offFifoMax);
4741	}
4742	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4743	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4744
4745	/*
4746	* Raise IRQ if required. Must enter the critical section here
4747	* before making final decisions here, otherwise cubebench and
4748	* others may end up waiting forever.
4749	*/
4750	if ( u32IrqStatus
4751	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4752	{
4753	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4754	AssertRC(rc2);
4755
4756	/* FIFO progress might trigger an interrupt. */
4757	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4758	{
4759	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4760	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4761	}
4762
4763	/* Unmasked IRQ pending? */
4764	if (pThis->svga.u32IrqMask & u32IrqStatus)
4765	{
4766	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4767	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4768	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4769	}
4770
4771	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4772	}
4773	}
4774
4775	/* If really done, clear the busy flag. */
4776	if (fDone)
4777	{
4778	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4779	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4780	}
4781	}
4782
4783	/*
4784	* Free the bounce buffer. (There are no returns above!)
4785	*/
4786	RTMemFree(pbBounceBuf);
4787
4788	return VINF_SUCCESS;
4789	}
4790
4791	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4792	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4793	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4794
4795	/**
4796	* Free the specified GMR
4797	*
4798	* @param pThisCC The VGA/VMSVGA state for ring-3.
4799	* @param idGMR GMR id
4800	*/
4801	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4802	{
4803	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4804
4805	/* Free the old descriptor if present. */
4806	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4807	if ( pGMR->numDescriptors
4808	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4809	{
4810	# ifdef DEBUG_GMR_ACCESS
4811	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4812	# endif
4813
4814	Assert(pGMR->paDesc);
4815	RTMemFree(pGMR->paDesc);
4816	pGMR->paDesc = NULL;
4817	pGMR->numDescriptors = 0;
4818	pGMR->cbTotal = 0;
4819	pGMR->cMaxPages = 0;
4820	}
4821	Assert(!pGMR->cMaxPages);
4822	Assert(!pGMR->cbTotal);
4823	}
4824
4825	/**
4826	* Copy between a GMR and a host memory buffer.
4827	*
4828	* @returns VBox status code.
4829	* @param pThis The shared VGA/VMSVGA instance data.
4830	* @param pThisCC The VGA/VMSVGA state for ring-3.
4831	* @param enmTransferType Transfer type (read/write)
4832	* @param pbHstBuf Host buffer pointer (valid)
4833	* @param cbHstBuf Size of host buffer (valid)
4834	* @param offHst Host buffer offset of the first scanline
4835	* @param cbHstPitch Destination buffer pitch
4836	* @param gstPtr GMR description
4837	* @param offGst Guest buffer offset of the first scanline
4838	* @param cbGstPitch Guest buffer pitch
4839	* @param cbWidth Width in bytes to copy
4840	* @param cHeight Number of scanllines to copy
4841	*/
4842	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4843	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4844	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4845	uint32_t cbWidth, uint32_t cHeight)
4846	{
4847	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4848	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4849	int rc;
4850
4851	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4852	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4853	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4854	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4855	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4856
4857	PGMR pGMR;
4858	uint32_t cbGmr; /* The GMR size in bytes. */
4859	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4860	{
4861	pGMR = NULL;
4862	cbGmr = pThis->vram_size;
4863	}
4864	else
4865	{
4866	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4867	RT_UNTRUSTED_VALIDATED_FENCE();
4868	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4869	cbGmr = pGMR->cbTotal;
4870	}
4871
4872	/*
4873	* GMR
4874	*/
4875	/* Calculate GMR offset of the data to be copied. */
4876	AssertMsgReturn(gstPtr.offset < cbGmr,
4877	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4878	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4879	VERR_INVALID_PARAMETER);
4880	RT_UNTRUSTED_VALIDATED_FENCE();
4881	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4882	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4883	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4884	VERR_INVALID_PARAMETER);
4885	RT_UNTRUSTED_VALIDATED_FENCE();
4886	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4887
4888	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4889	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4890	AssertMsgReturn(cbGmrScanline != 0,
4891	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4892	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4893	VERR_INVALID_PARAMETER);
4894	RT_UNTRUSTED_VALIDATED_FENCE();
4895	AssertMsgReturn(cbWidth <= cbGmrScanline,
4896	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4897	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4898	VERR_INVALID_PARAMETER);
4899	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4900	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4901	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4902	VERR_INVALID_PARAMETER);
4903	RT_UNTRUSTED_VALIDATED_FENCE();
4904
4905	/* How many bytes are available for the data in the GMR. */
4906	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4907
4908	/* How many scanlines would fit into the available data. */
4909	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4910	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4911	if (cbWidth <= cbGmrLastScanline)
4912	++cGmrScanlines;
4913
4914	if (cHeight > cGmrScanlines)
4915	cHeight = cGmrScanlines;
4916
4917	AssertMsgReturn(cHeight > 0,
4918	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4919	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4920	VERR_INVALID_PARAMETER);
4921	RT_UNTRUSTED_VALIDATED_FENCE();
4922
4923	/*
4924	* Host buffer.
4925	*/
4926	AssertMsgReturn(offHst < cbHstBuf,
4927	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4928	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4929	VERR_INVALID_PARAMETER);
4930
4931	/* Verify that cbWidth is less than scanline and fits into the buffer. */
4932	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
4933	AssertMsgReturn(cbHstScanline != 0,
4934	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4935	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4936	VERR_INVALID_PARAMETER);
4937	AssertMsgReturn(cbWidth <= cbHstScanline,
4938	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4939	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4940	VERR_INVALID_PARAMETER);
4941	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
4942	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4943	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4944	VERR_INVALID_PARAMETER);
4945
4946	/* How many bytes are available for the data in the buffer. */
4947	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
4948
4949	/* How many scanlines would fit into the available data. */
4950	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
4951	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
4952	if (cbWidth <= cbHstLastScanline)
4953	++cHstScanlines;
4954
4955	if (cHeight > cHstScanlines)
4956	cHeight = cHstScanlines;
4957
4958	AssertMsgReturn(cHeight > 0,
4959	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
4960	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
4961	VERR_INVALID_PARAMETER);
4962
4963	uint8_t *pbHst = pbHstBuf + offHst;
4964
4965	/* Shortcut for the framebuffer. */
4966	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4967	{
4968	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
4969
4970	uint8_t const *pbSrc;
4971	int32_t cbSrcPitch;
4972	uint8_t *pbDst;
4973	int32_t cbDstPitch;
4974
4975	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
4976	{
4977	pbSrc = pbHst;
4978	cbSrcPitch = cbHstPitch;
4979	pbDst = pbGst;
4980	cbDstPitch = cbGstPitch;
4981	}
4982	else
4983	{
4984	pbSrc = pbGst;
4985	cbSrcPitch = cbGstPitch;
4986	pbDst = pbHst;
4987	cbDstPitch = cbHstPitch;
4988	}
4989
4990	if ( cbWidth == (uint32_t)cbGstPitch
4991	&& cbGstPitch == cbHstPitch)
4992	{
4993	/* Entire scanlines, positive pitch. */
4994	memcpy(pbDst, pbSrc, cbWidth * cHeight);
4995	}
4996	else
4997	{
4998	for (uint32_t i = 0; i < cHeight; ++i)
4999	{
5000	memcpy(pbDst, pbSrc, cbWidth);
5001
5002	pbDst += cbDstPitch;
5003	pbSrc += cbSrcPitch;
5004	}
5005	}
5006	return VINF_SUCCESS;
5007	}
5008
5009	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5010	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5011
5012	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5013	uint32_t iDesc = 0; /* Index in the descriptor array. */
5014	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5015	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5016	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5017	for (uint32_t i = 0; i < cHeight; ++i)
5018	{
5019	uint32_t cbCurrentWidth = cbWidth;
5020	uint32_t offGmrCurrent = offGmrScanline;
5021	uint8_t *pbCurrentHost = pbHstScanline;
5022
5023	/* Find the right descriptor */
5024	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5025	{
5026	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5027	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5028	++iDesc;
5029	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5030	}
5031
5032	while (cbCurrentWidth)
5033	{
5034	uint32_t cbToCopy;
5035
5036	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5037	{
5038	cbToCopy = cbCurrentWidth;
5039	}
5040	else
5041	{
5042	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5043	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5044	}
5045
5046	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5047
5048	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5049
5050	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5051	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5052	else
5053	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5054	AssertRCBreak(rc);
5055
5056	cbCurrentWidth -= cbToCopy;
5057	offGmrCurrent += cbToCopy;
5058	pbCurrentHost += cbToCopy;
5059
5060	/* Go to the next descriptor if there's anything left. */
5061	if (cbCurrentWidth)
5062	{
5063	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5064	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5065	++iDesc;
5066	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5067	}
5068	}
5069
5070	offGmrScanline += cbGstPitch;
5071	pbHstScanline += cbHstPitch;
5072	}
5073
5074	return VINF_SUCCESS;
5075	}
5076
5077
5078	/**
5079	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5080	*
5081	* @param pSizeSrc Source surface dimensions.
5082	* @param pSizeDest Destination surface dimensions.
5083	* @param pBox Coordinates to be clipped.
5084	*/
5085	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5086	{
5087	/* Src x, w */
5088	if (pBox->srcx > pSizeSrc->width)
5089	pBox->srcx = pSizeSrc->width;
5090	if (pBox->w > pSizeSrc->width - pBox->srcx)
5091	pBox->w = pSizeSrc->width - pBox->srcx;
5092
5093	/* Src y, h */
5094	if (pBox->srcy > pSizeSrc->height)
5095	pBox->srcy = pSizeSrc->height;
5096	if (pBox->h > pSizeSrc->height - pBox->srcy)
5097	pBox->h = pSizeSrc->height - pBox->srcy;
5098
5099	/* Src z, d */
5100	if (pBox->srcz > pSizeSrc->depth)
5101	pBox->srcz = pSizeSrc->depth;
5102	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5103	pBox->d = pSizeSrc->depth - pBox->srcz;
5104
5105	/* Dest x, w */
5106	if (pBox->x > pSizeDest->width)
5107	pBox->x = pSizeDest->width;
5108	if (pBox->w > pSizeDest->width - pBox->x)
5109	pBox->w = pSizeDest->width - pBox->x;
5110
5111	/* Dest y, h */
5112	if (pBox->y > pSizeDest->height)
5113	pBox->y = pSizeDest->height;
5114	if (pBox->h > pSizeDest->height - pBox->y)
5115	pBox->h = pSizeDest->height - pBox->y;
5116
5117	/* Dest z, d */
5118	if (pBox->z > pSizeDest->depth)
5119	pBox->z = pSizeDest->depth;
5120	if (pBox->d > pSizeDest->depth - pBox->z)
5121	pBox->d = pSizeDest->depth - pBox->z;
5122	}
5123
5124	/**
5125	* Unsigned coordinates in pBox. Clip to [0; pSize).
5126	*
5127	* @param pSize Source surface dimensions.
5128	* @param pBox Coordinates to be clipped.
5129	*/
5130	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5131	{
5132	/* x, w */
5133	if (pBox->x > pSize->width)
5134	pBox->x = pSize->width;
5135	if (pBox->w > pSize->width - pBox->x)
5136	pBox->w = pSize->width - pBox->x;
5137
5138	/* y, h */
5139	if (pBox->y > pSize->height)
5140	pBox->y = pSize->height;
5141	if (pBox->h > pSize->height - pBox->y)
5142	pBox->h = pSize->height - pBox->y;
5143
5144	/* z, d */
5145	if (pBox->z > pSize->depth)
5146	pBox->z = pSize->depth;
5147	if (pBox->d > pSize->depth - pBox->z)
5148	pBox->d = pSize->depth - pBox->z;
5149	}
5150
5151	/**
5152	* Clip.
5153	*
5154	* @param pBound Bounding rectangle.
5155	* @param pRect Rectangle to be clipped.
5156	*/
5157	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5158	{
5159	int32_t left;
5160	int32_t top;
5161	int32_t right;
5162	int32_t bottom;
5163
5164	/* Right order. */
5165	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5166	if (pRect->left < pRect->right)
5167	{
5168	left = pRect->left;
5169	right = pRect->right;
5170	}
5171	else
5172	{
5173	left = pRect->right;
5174	right = pRect->left;
5175	}
5176	if (pRect->top < pRect->bottom)
5177	{
5178	top = pRect->top;
5179	bottom = pRect->bottom;
5180	}
5181	else
5182	{
5183	top = pRect->bottom;
5184	bottom = pRect->top;
5185	}
5186
5187	if (left < pBound->left)
5188	left = pBound->left;
5189	if (right < pBound->left)
5190	right = pBound->left;
5191
5192	if (left > pBound->right)
5193	left = pBound->right;
5194	if (right > pBound->right)
5195	right = pBound->right;
5196
5197	if (top < pBound->top)
5198	top = pBound->top;
5199	if (bottom < pBound->top)
5200	bottom = pBound->top;
5201
5202	if (top > pBound->bottom)
5203	top = pBound->bottom;
5204	if (bottom > pBound->bottom)
5205	bottom = pBound->bottom;
5206
5207	pRect->left = left;
5208	pRect->right = right;
5209	pRect->top = top;
5210	pRect->bottom = bottom;
5211	}
5212
5213	/**
5214	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5215	* Unblock the FIFO I/O thread so it can respond to a state change.}
5216	*/
5217	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5218	{
5219	RT_NOREF(pDevIns);
5220	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5221	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5222	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5223	}
5224
5225	/**
5226	* Enables or disables dirty page tracking for the framebuffer
5227	*
5228	* @param pDevIns The device instance.
5229	* @param pThis The shared VGA/VMSVGA instance data.
5230	* @param fTraces Enable/disable traces
5231	*/
5232	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5233	{
5234	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5235	&& !fTraces)
5236	{
5237	//Assert(pThis->svga.fTraces);
5238	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5239	return;
5240	}
5241
5242	pThis->svga.fTraces = fTraces;
5243	if (pThis->svga.fTraces)
5244	{
5245	unsigned cbFrameBuffer = pThis->vram_size;
5246
5247	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5248	/** @todo How does this work with screens? */
5249	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5250	{
5251	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5252	Assert(pThis->svga.cbScanline);
5253	# endif
5254	/* Hardware enabled; return real framebuffer size .*/
5255	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5256	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5257	}
5258
5259	if (!pThis->svga.fVRAMTracking)
5260	{
5261	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5262	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5263	pThis->svga.fVRAMTracking = true;
5264	}
5265	}
5266	else
5267	{
5268	if (pThis->svga.fVRAMTracking)
5269	{
5270	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5271	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5272	pThis->svga.fVRAMTracking = false;
5273	}
5274	}
5275	}
5276
5277	/**
5278	* @callback_method_impl{FNPCIIOREGIONMAP}
5279	*/
5280	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5281	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5282	{
5283	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5284	int rc;
5285	RT_NOREF(pPciDev);
5286	Assert(pPciDev == pDevIns->apPciDevs[0]);
5287
5288	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5289	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5290	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5291	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5292	, VERR_INTERNAL_ERROR);
5293	if (GCPhysAddress != NIL_RTGCPHYS)
5294	{
5295	/*
5296	* Mapping the FIFO RAM.
5297	*/
5298	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5299	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5300	AssertRC(rc);
5301
5302	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5303	if (RT_SUCCESS(rc))
5304	{
5305	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5306	# ifdef DEBUG_FIFO_ACCESS
5307	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5308	# else
5309	GCPhysAddress + PAGE_SIZE - 1,
5310	# endif
5311	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5312	"VMSVGA FIFO");
5313	AssertRC(rc);
5314	}
5315	# endif
5316	if (RT_SUCCESS(rc))
5317	{
5318	pThis->svga.GCPhysFIFO = GCPhysAddress;
5319	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5320	}
5321	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5322	}
5323	else
5324	{
5325	Assert(pThis->svga.GCPhysFIFO);
5326	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5327	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5328	AssertRC(rc);
5329	# else
5330	rc = VINF_SUCCESS;
5331	# endif
5332	pThis->svga.GCPhysFIFO = 0;
5333	}
5334	return rc;
5335	}
5336
5337	# ifdef VBOX_WITH_VMSVGA3D
5338
5339	/**
5340	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5341	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5342	*
5343	* @param pDevIns The device instance.
5344	* @param pThis The The shared VGA/VMSVGA instance data.
5345	* @param pThisCC The VGA/VMSVGA state for ring-3.
5346	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5347	* UINT32_MAX is used, all surfaces are processed.
5348	*/
5349	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5350	{
5351	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5352	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5353	}
5354
5355
5356	/**
5357	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5358	*/
5359	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5360	{
5361	/* There might be a specific surface ID at the start of the
5362	arguments, if not show all surfaces. */
5363	uint32_t sid = UINT32_MAX;
5364	if (pszArgs)
5365	pszArgs = RTStrStripL(pszArgs);
5366	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5367	sid = RTStrToUInt32(pszArgs);
5368
5369	/* Verbose or terse display, we default to verbose. */
5370	bool fVerbose = true;
5371	if (RTStrIStr(pszArgs, "terse"))
5372	fVerbose = false;
5373
5374	/* The size of the ascii art (x direction, y is 3/4 of x). */
5375	uint32_t cxAscii = 80;
5376	if (RTStrIStr(pszArgs, "gigantic"))
5377	cxAscii = 300;
5378	else if (RTStrIStr(pszArgs, "huge"))
5379	cxAscii = 180;
5380	else if (RTStrIStr(pszArgs, "big"))
5381	cxAscii = 132;
5382	else if (RTStrIStr(pszArgs, "normal"))
5383	cxAscii = 80;
5384	else if (RTStrIStr(pszArgs, "medium"))
5385	cxAscii = 64;
5386	else if (RTStrIStr(pszArgs, "small"))
5387	cxAscii = 48;
5388	else if (RTStrIStr(pszArgs, "tiny"))
5389	cxAscii = 24;
5390
5391	/* Y invert the image when producing the ASCII art. */
5392	bool fInvY = false;
5393	if (RTStrIStr(pszArgs, "invy"))
5394	fInvY = true;
5395
5396	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5397	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5398	}
5399
5400
5401	/**
5402	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5403	*/
5404	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5405	{
5406	/* pszArg = "sid[>dir]"
5407	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5408	*/
5409	char *pszBitmapPath = NULL;
5410	uint32_t sid = UINT32_MAX;
5411	if (pszArgs)
5412	pszArgs = RTStrStripL(pszArgs);
5413	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5414	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5415	if ( pszBitmapPath
5416	&& *pszBitmapPath == '>')
5417	++pszBitmapPath;
5418
5419	const bool fVerbose = true;
5420	const uint32_t cxAscii = 0; /* No ASCII */
5421	const bool fInvY = false; /* Do not invert. */
5422	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5423	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5424	}
5425
5426
5427	/**
5428	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5429	*/
5430	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5431	{
5432	/* There might be a specific surface ID at the start of the
5433	arguments, if not show all contexts. */
5434	uint32_t sid = UINT32_MAX;
5435	if (pszArgs)
5436	pszArgs = RTStrStripL(pszArgs);
5437	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5438	sid = RTStrToUInt32(pszArgs);
5439
5440	/* Verbose or terse display, we default to verbose. */
5441	bool fVerbose = true;
5442	if (RTStrIStr(pszArgs, "terse"))
5443	fVerbose = false;
5444
5445	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5446	}
5447
5448	# endif /* VBOX_WITH_VMSVGA3D */
5449
5450	/**
5451	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5452	*/
5453	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5454	{
5455	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5456	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5457	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5458	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5459	RT_NOREF(pszArgs);
5460
5461	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5462	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5463	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5464	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5465	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5466	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5467	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5468	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5469	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5470	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5471	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5472	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5473	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5474	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5475	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5476	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5477	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5478	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5479	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5480	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5481	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5482	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5483	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5484	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5485	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5486
5487	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5488	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5489	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5490	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5491
5492	# ifdef VBOX_WITH_VMSVGA3D
5493	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5494	# endif
5495	if (pThisCC->pDrv)
5496	{
5497	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5498	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5499	}
5500	}
5501
5502	/**
5503	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5504	*/
5505	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5506	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5507	{
5508	RT_NOREF(uPass);
5509
5510	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5511	int rc;
5512
5513	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5514	{
5515	uint32_t cScreens = 0;
5516	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5517	AssertRCReturn(rc, rc);
5518	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5519	("cScreens=%#x\n", cScreens),
5520	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5521
5522	for (uint32_t i = 0; i < cScreens; ++i)
5523	{
5524	VMSVGASCREENOBJECT screen;
5525	RT_ZERO(screen);
5526
5527	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5528	AssertLogRelRCReturn(rc, rc);
5529
5530	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5531	{
5532	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5533	*pScreen = screen;
5534	pScreen->fModified = true;
5535	}
5536	else
5537	{
5538	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5539	}
5540	}
5541	}
5542	else
5543	{
5544	/* Try to setup at least the first screen. */
5545	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5546	pScreen->fDefined = true;
5547	pScreen->fModified = true;
5548	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5549	pScreen->idScreen = 0;
5550	pScreen->xOrigin = 0;
5551	pScreen->yOrigin = 0;
5552	pScreen->offVRAM = pThis->svga.uScreenOffset;
5553	pScreen->cbPitch = pThis->svga.cbScanline;
5554	pScreen->cWidth = pThis->svga.uWidth;
5555	pScreen->cHeight = pThis->svga.uHeight;
5556	pScreen->cBpp = pThis->svga.uBpp;
5557	}
5558
5559	return VINF_SUCCESS;
5560	}
5561
5562	/**
5563	* @copydoc FNSSMDEVLOADEXEC
5564	*/
5565	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5566	{
5567	RT_NOREF(uPass);
5568	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5569	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5570	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5571	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5572	int rc;
5573
5574	/* Load our part of the VGAState */
5575	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5576	AssertRCReturn(rc, rc);
5577
5578	/* Load the VGA framebuffer. */
5579	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5580	uint32_t cbVgaFramebuffer = _32K;
5581	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5582	{
5583	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5584	AssertRCReturn(rc, rc);
5585	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5586	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5587	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5588	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5589	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5590	}
5591	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5592	AssertRCReturn(rc, rc);
5593	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5594	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5595	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5596	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5597
5598	/* Load the VMSVGA state. */
5599	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5600	AssertRCReturn(rc, rc);
5601
5602	/* Load the active cursor bitmaps. */
5603	if (pSVGAState->Cursor.fActive)
5604	{
5605	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5606	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5607
5608	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5609	AssertRCReturn(rc, rc);
5610	}
5611
5612	/* Load the GMR state. */
5613	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5614	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5615	{
5616	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5617	AssertRCReturn(rc, rc);
5618	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5619	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5620	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5621	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5622	}
5623
5624	if (pThis->svga.cGMR != cGMR)
5625	{
5626	/* Reallocate GMR array. */
5627	Assert(pSVGAState->paGMR != NULL);
5628	RTMemFree(pSVGAState->paGMR);
5629	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5630	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5631	pThis->svga.cGMR = cGMR;
5632	}
5633
5634	for (uint32_t i = 0; i < cGMR; ++i)
5635	{
5636	PGMR pGMR = &pSVGAState->paGMR[i];
5637
5638	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5639	AssertRCReturn(rc, rc);
5640
5641	if (pGMR->numDescriptors)
5642	{
5643	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5644	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5645	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5646
5647	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5648	{
5649	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5650	AssertRCReturn(rc, rc);
5651	}
5652	}
5653	}
5654
5655	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5656	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5657	# endif
5658
5659	VMSVGA_STATE_LOAD LoadState;
5660	LoadState.pSSM = pSSM;
5661	LoadState.uVersion = uVersion;
5662	LoadState.uPass = uPass;
5663	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5664	AssertLogRelRCReturn(rc, rc);
5665
5666	return VINF_SUCCESS;
5667	}
5668
5669	/**
5670	* Reinit the video mode after the state has been loaded.
5671	*/
5672	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5673	{
5674	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5675	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5676	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5677
5678	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5679
5680	/* Set the active cursor. */
5681	if (pSVGAState->Cursor.fActive)
5682	{
5683	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5684	true /fVisible/,
5685	true /fAlpha/,
5686	pSVGAState->Cursor.xHotspot,
5687	pSVGAState->Cursor.yHotspot,
5688	pSVGAState->Cursor.width,
5689	pSVGAState->Cursor.height,
5690	pSVGAState->Cursor.pData);
5691	AssertRC(rc);
5692	}
5693	return VINF_SUCCESS;
5694	}
5695
5696	/**
5697	* Portion of SVGA state which must be saved in the FIFO thread.
5698	*/
5699	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5700	{
5701	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5702	int rc;
5703
5704	/* Save the screen objects. */
5705	/* Count defined screen object. */
5706	uint32_t cScreens = 0;
5707	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5708	{
5709	if (pSVGAState->aScreens[i].fDefined)
5710	++cScreens;
5711	}
5712
5713	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5714	AssertLogRelRCReturn(rc, rc);
5715
5716	for (uint32_t i = 0; i < cScreens; ++i)
5717	{
5718	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5719
5720	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5721	AssertLogRelRCReturn(rc, rc);
5722	}
5723	return VINF_SUCCESS;
5724	}
5725
5726	/**
5727	* @copydoc FNSSMDEVSAVEEXEC
5728	*/
5729	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5730	{
5731	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5732	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5733	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5734	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5735	int rc;
5736
5737	/* Save our part of the VGAState */
5738	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5739	AssertLogRelRCReturn(rc, rc);
5740
5741	/* Save the framebuffer backup. */
5742	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5743	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5744	AssertLogRelRCReturn(rc, rc);
5745
5746	/* Save the VMSVGA state. */
5747	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5748	AssertLogRelRCReturn(rc, rc);
5749
5750	/* Save the active cursor bitmaps. */
5751	if (pSVGAState->Cursor.fActive)
5752	{
5753	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5754	AssertLogRelRCReturn(rc, rc);
5755	}
5756
5757	/* Save the GMR state */
5758	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5759	AssertLogRelRCReturn(rc, rc);
5760	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5761	{
5762	PGMR pGMR = &pSVGAState->paGMR[i];
5763
5764	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5765	AssertLogRelRCReturn(rc, rc);
5766
5767	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5768	{
5769	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5770	AssertLogRelRCReturn(rc, rc);
5771	}
5772	}
5773
5774	/*
5775	* Must save some state (3D in particular) in the FIFO thread.
5776	*/
5777	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5778	AssertLogRelRCReturn(rc, rc);
5779
5780	return VINF_SUCCESS;
5781	}
5782
5783	/**
5784	* Destructor for PVMSVGAR3STATE structure.
5785	*
5786	* @param pThis The shared VGA/VMSVGA instance data.
5787	* @param pSVGAState Pointer to the structure. It is not deallocated.
5788	*/
5789	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5790	{
5791	# ifndef VMSVGA_USE_EMT_HALT_CODE
5792	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5793	{
5794	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5795	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5796	}
5797	# endif
5798
5799	if (pSVGAState->Cursor.fActive)
5800	{
5801	RTMemFree(pSVGAState->Cursor.pData);
5802	pSVGAState->Cursor.pData = NULL;
5803	pSVGAState->Cursor.fActive = false;
5804	}
5805
5806	if (pSVGAState->paGMR)
5807	{
5808	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5809	if (pSVGAState->paGMR[i].paDesc)
5810	RTMemFree(pSVGAState->paGMR[i].paDesc);
5811
5812	RTMemFree(pSVGAState->paGMR);
5813	pSVGAState->paGMR = NULL;
5814	}
5815	}
5816
5817	/**
5818	* Constructor for PVMSVGAR3STATE structure.
5819	*
5820	* @returns VBox status code.
5821	* @param pThis The shared VGA/VMSVGA instance data.
5822	* @param pSVGAState Pointer to the structure. It is already allocated.
5823	*/
5824	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5825	{
5826	int rc = VINF_SUCCESS;
5827	RT_ZERO(*pSVGAState);
5828
5829	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5830	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5831
5832	# ifndef VMSVGA_USE_EMT_HALT_CODE
5833	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5834	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5835	AssertRCReturn(rc, rc);
5836	# endif
5837
5838	return rc;
5839	}
5840
5841	/**
5842	* Initializes the host capabilities: registers and FIFO.
5843	*
5844	* @returns VBox status code.
5845	* @param pThis The shared VGA/VMSVGA instance data.
5846	* @param pThisCC The VGA/VMSVGA state for ring-3.
5847	*/
5848	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5849	{
5850	/* Register caps. */
5851	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5852	\| SVGA_CAP_GMR2
5853	\| SVGA_CAP_CURSOR
5854	\| SVGA_CAP_CURSOR_BYPASS_2
5855	\| SVGA_CAP_EXTENDED_FIFO
5856	\| SVGA_CAP_IRQMASK
5857	\| SVGA_CAP_PITCHLOCK
5858	\| SVGA_CAP_TRACES
5859	\| SVGA_CAP_SCREEN_OBJECT_2
5860	\| SVGA_CAP_ALPHA_CURSOR;
5861	# ifdef VBOX_WITH_VMSVGA3D
5862	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5863	# endif
5864
5865	/* Clear the FIFO. */
5866	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5867
5868	/* Setup FIFO capabilities. */
5869	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5870	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5871	\| SVGA_FIFO_CAP_GMR2
5872	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5873	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5874	\| SVGA_FIFO_CAP_RESERVE
5875	\| SVGA_FIFO_CAP_PITCHLOCK;
5876
5877	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5878	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5879	}
5880
5881	# ifdef VBOX_WITH_VMSVGA3D
5882	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5883	static const char * const g_apszVmSvgaDevCapNames[] =
5884	{
5885	"x3D", /* = 0 */
5886	"xMAX_LIGHTS",
5887	"xMAX_TEXTURES",
5888	"xMAX_CLIP_PLANES",
5889	"xVERTEX_SHADER_VERSION",
5890	"xVERTEX_SHADER",
5891	"xFRAGMENT_SHADER_VERSION",
5892	"xFRAGMENT_SHADER",
5893	"xMAX_RENDER_TARGETS",
5894	"xS23E8_TEXTURES",
5895	"xS10E5_TEXTURES",
5896	"xMAX_FIXED_VERTEXBLEND",
5897	"xD16_BUFFER_FORMAT",
5898	"xD24S8_BUFFER_FORMAT",
5899	"xD24X8_BUFFER_FORMAT",
5900	"xQUERY_TYPES",
5901	"xTEXTURE_GRADIENT_SAMPLING",
5902	"rMAX_POINT_SIZE",
5903	"xMAX_SHADER_TEXTURES",
5904	"xMAX_TEXTURE_WIDTH",
5905	"xMAX_TEXTURE_HEIGHT",
5906	"xMAX_VOLUME_EXTENT",
5907	"xMAX_TEXTURE_REPEAT",
5908	"xMAX_TEXTURE_ASPECT_RATIO",
5909	"xMAX_TEXTURE_ANISOTROPY",
5910	"xMAX_PRIMITIVE_COUNT",
5911	"xMAX_VERTEX_INDEX",
5912	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
5913	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
5914	"xMAX_VERTEX_SHADER_TEMPS",
5915	"xMAX_FRAGMENT_SHADER_TEMPS",
5916	"xTEXTURE_OPS",
5917	"xSURFACEFMT_X8R8G8B8",
5918	"xSURFACEFMT_A8R8G8B8",
5919	"xSURFACEFMT_A2R10G10B10",
5920	"xSURFACEFMT_X1R5G5B5",
5921	"xSURFACEFMT_A1R5G5B5",
5922	"xSURFACEFMT_A4R4G4B4",
5923	"xSURFACEFMT_R5G6B5",
5924	"xSURFACEFMT_LUMINANCE16",
5925	"xSURFACEFMT_LUMINANCE8_ALPHA8",
5926	"xSURFACEFMT_ALPHA8",
5927	"xSURFACEFMT_LUMINANCE8",
5928	"xSURFACEFMT_Z_D16",
5929	"xSURFACEFMT_Z_D24S8",
5930	"xSURFACEFMT_Z_D24X8",
5931	"xSURFACEFMT_DXT1",
5932	"xSURFACEFMT_DXT2",
5933	"xSURFACEFMT_DXT3",
5934	"xSURFACEFMT_DXT4",
5935	"xSURFACEFMT_DXT5",
5936	"xSURFACEFMT_BUMPX8L8V8U8",
5937	"xSURFACEFMT_A2W10V10U10",
5938	"xSURFACEFMT_BUMPU8V8",
5939	"xSURFACEFMT_Q8W8V8U8",
5940	"xSURFACEFMT_CxV8U8",
5941	"xSURFACEFMT_R_S10E5",
5942	"xSURFACEFMT_R_S23E8",
5943	"xSURFACEFMT_RG_S10E5",
5944	"xSURFACEFMT_RG_S23E8",
5945	"xSURFACEFMT_ARGB_S10E5",
5946	"xSURFACEFMT_ARGB_S23E8",
5947	"xMISSING62",
5948	"xMAX_VERTEX_SHADER_TEXTURES",
5949	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
5950	"xSURFACEFMT_V16U16",
5951	"xSURFACEFMT_G16R16",
5952	"xSURFACEFMT_A16B16G16R16",
5953	"xSURFACEFMT_UYVY",
5954	"xSURFACEFMT_YUY2",
5955	"xMULTISAMPLE_NONMASKABLESAMPLES",
5956	"xMULTISAMPLE_MASKABLESAMPLES",
5957	"xALPHATOCOVERAGE",
5958	"xSUPERSAMPLE",
5959	"xAUTOGENMIPMAPS",
5960	"xSURFACEFMT_NV12",
5961	"xSURFACEFMT_AYUV",
5962	"xMAX_CONTEXT_IDS",
5963	"xMAX_SURFACE_IDS",
5964	"xSURFACEFMT_Z_DF16",
5965	"xSURFACEFMT_Z_DF24",
5966	"xSURFACEFMT_Z_D24S8_INT",
5967	"xSURFACEFMT_BC4_UNORM",
5968	"xSURFACEFMT_BC5_UNORM", /* 83 */
5969	};
5970
5971	/**
5972	* Initializes the host 3D capabilities in FIFO.
5973	*
5974	* @returns VBox status code.
5975	* @param pThis The shared VGA/VMSVGA instance data.
5976	* @param pThisCC The VGA/VMSVGA state for ring-3.
5977	*/
5978	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
5979	{
5980	/** @todo Probably query the capabilities once and cache in a memory buffer. */
5981	bool fSavedBuffering = RTLogRelSetBuffering(true);
5982	SVGA3dCapsRecord *pCaps;
5983	SVGA3dCapPair *pData;
5984	uint32_t idxCap = 0;
5985
5986	/* 3d hardware version; latest and greatest */
5987	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5988	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5989
5990	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5991	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5992	pData = (SVGA3dCapPair *)&pCaps->data;
5993
5994	/* Fill out all 3d capabilities. */
5995	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
5996	{
5997	uint32_t val = 0;
5998
5999	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6000	if (RT_SUCCESS(rc))
6001	{
6002	pData[idxCap][0] = i;
6003	pData[idxCap][1] = val;
6004	idxCap++;
6005	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6006	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6007	else
6008	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6009	&g_apszVmSvgaDevCapNames[i][1]));
6010	}
6011	else
6012	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6013	}
6014	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6015	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6016
6017	/* Mark end of record array. */
6018	pCaps->header.length = 0;
6019
6020	RTLogRelSetBuffering(fSavedBuffering);
6021	}
6022
6023	# endif
6024
6025	/**
6026	* Resets the SVGA hardware state
6027	*
6028	* @returns VBox status code.
6029	* @param pDevIns The device instance.
6030	*/
6031	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6032	{
6033	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6034	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6035	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6036
6037	/* Reset before init? */
6038	if (!pSVGAState)
6039	return VINF_SUCCESS;
6040
6041	Log(("vmsvgaR3Reset\n"));
6042
6043	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6044	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6045	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6046
6047	/* Reset other stuff. */
6048	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6049	RT_ZERO(pThis->svga.au32ScratchRegion);
6050
6051	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6052	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6053
6054	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6055
6056	/* Initialize FIFO and register capabilities. */
6057	vmsvgaR3InitCaps(pThis, pThisCC);
6058
6059	# ifdef VBOX_WITH_VMSVGA3D
6060	if (pThis->svga.f3DEnabled)
6061	vmsvgaR3InitFifo3DCaps(pThisCC);
6062	# endif
6063
6064	/* VRAM tracking is enabled by default during bootup. */
6065	pThis->svga.fVRAMTracking = true;
6066	pThis->svga.fEnabled = false;
6067
6068	/* Invalidate current settings. */
6069	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6070	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6071	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6072	pThis->svga.cbScanline = 0;
6073	pThis->svga.u32PitchLock = 0;
6074
6075	return rc;
6076	}
6077
6078	/**
6079	* Cleans up the SVGA hardware state
6080	*
6081	* @returns VBox status code.
6082	* @param pDevIns The device instance.
6083	*/
6084	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6085	{
6086	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6087	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6088
6089	/*
6090	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6091	*/
6092	if (pThisCC->svga.pFIFOIOThread)
6093	{
6094	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6095	NULL /pvParam/, 30000 /ms/);
6096	AssertLogRelRC(rc);
6097
6098	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6099	AssertLogRelRC(rc);
6100	pThisCC->svga.pFIFOIOThread = NULL;
6101	}
6102
6103	/*
6104	* Destroy the special SVGA state.
6105	*/
6106	if (pThisCC->svga.pSvgaR3State)
6107	{
6108	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6109
6110	RTMemFree(pThisCC->svga.pSvgaR3State);
6111	pThisCC->svga.pSvgaR3State = NULL;
6112	}
6113
6114	/*
6115	* Free our resources residing in the VGA state.
6116	*/
6117	if (pThisCC->svga.pbVgaFrameBufferR3)
6118	{
6119	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6120	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6121	}
6122	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6123	{
6124	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6125	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6126	}
6127	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6128	{
6129	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6130	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6131	}
6132
6133	return VINF_SUCCESS;
6134	}
6135
6136	/**
6137	* Initialize the SVGA hardware state
6138	*
6139	* @returns VBox status code.
6140	* @param pDevIns The device instance.
6141	*/
6142	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6143	{
6144	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6145	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6146	PVMSVGAR3STATE pSVGAState;
6147	int rc;
6148
6149	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6150	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6151
6152	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6153
6154	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6155	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6156	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6157
6158	/* Create event semaphore. */
6159	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6160	AssertRCReturn(rc, rc);
6161
6162	/* Create event semaphore. */
6163	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6164	AssertRCReturn(rc, rc);
6165
6166	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6167	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6168
6169	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6170	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6171
6172	pSVGAState = pThisCC->svga.pSvgaR3State;
6173
6174	/* Initialize FIFO and register capabilities. */
6175	vmsvgaR3InitCaps(pThis, pThisCC);
6176
6177	# ifdef VBOX_WITH_VMSVGA3D
6178	if (pThis->svga.f3DEnabled)
6179	{
6180	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6181	if (RT_FAILURE(rc))
6182	{
6183	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6184	pThis->svga.f3DEnabled = false;
6185	}
6186	}
6187	# endif
6188	/* VRAM tracking is enabled by default during bootup. */
6189	pThis->svga.fVRAMTracking = true;
6190
6191	/* Invalidate current settings. */
6192	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6193	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6194	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6195	pThis->svga.cbScanline = 0;
6196
6197	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6198	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6199	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6200	{
6201	pThis->svga.u32MaxWidth -= 256;
6202	pThis->svga.u32MaxHeight -= 256;
6203	}
6204	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6205
6206	# ifdef DEBUG_GMR_ACCESS
6207	/* Register the GMR access handler type. */
6208	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6209	vmsvgaR3GmrAccessHandler,
6210	NULL, NULL, NULL,
6211	NULL, NULL, NULL,
6212	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6213	AssertRCReturn(rc, rc);
6214	# endif
6215
6216	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6217	/* Register the FIFO access handler type. In addition to
6218	debugging FIFO access, this is also used to facilitate
6219	extended fifo thread sleeps. */
6220	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6221	# ifdef DEBUG_FIFO_ACCESS
6222	PGMPHYSHANDLERKIND_ALL,
6223	# else
6224	PGMPHYSHANDLERKIND_WRITE,
6225	# endif
6226	vmsvgaR3FifoAccessHandler,
6227	NULL, NULL, NULL,
6228	NULL, NULL, NULL,
6229	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6230	AssertRCReturn(rc, rc);
6231	# endif
6232
6233	/* Create the async IO thread. */
6234	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6235	RTTHREADTYPE_IO, "VMSVGA FIFO");
6236	if (RT_FAILURE(rc))
6237	{
6238	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6239	return rc;
6240	}
6241
6242	/*
6243	* Statistics.
6244	*/
6245	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6246	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6247	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6248	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6249	# ifdef VBOX_WITH_STATISTICS
6250	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6251	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6252	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6253	# endif
6254	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6255	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6256	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6257	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6258	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6259	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6260	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6261	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6262	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6263	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6264	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6265	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6266	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6267	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6268	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6269	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6270	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6271	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6272	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6273	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6274	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6275	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6276	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6277	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6278	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6279	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6280	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6281	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6282	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6283	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6284	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6285	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6286	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6287	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6288	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6289	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6290	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6291	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6292	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6293	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6294	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6295	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6296	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6297	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6298	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6299	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6300	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6301	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6302	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6303	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6304	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6305	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6306	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6307
6308	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6309	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6310	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6311	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6312	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6313	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6314	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6315	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6316	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6317	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6318	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6319	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6320	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6321	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6322	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6323	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6324	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6325	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6326	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6327	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6328	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6329	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6330	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6331	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6332	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6333	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6334	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6335	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6336	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6337	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6338	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6339	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6340
6341	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6342	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6343	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6344	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6345	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6346	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6347	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6348	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6349	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6350	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6351	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6352	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6353	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6354	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6355	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6356	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6357	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6358	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6359	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6360	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6361	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6362	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6363	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6364	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6365	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6366	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6367	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6368	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6369	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6370	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6371	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6372	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6373	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6374	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6375	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6376	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6377	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6378	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6379	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6380	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6381	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6382	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6383	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6384	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6385	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6386	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6387	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6388	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6389	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6390
6391	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6392	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6393	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6394	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6395	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6396	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6397	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6398	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6399	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6400	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6401	# endif
6402	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6403	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6404	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6405	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6406	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6407
6408	# undef REG_CNT
6409	# undef REG_PRF
6410
6411	/*
6412	* Info handlers.
6413	*/
6414	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6415	# ifdef VBOX_WITH_VMSVGA3D
6416	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6417	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6418	"VMSVGA 3d surface details. "
6419	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6420	vmsvgaR3Info3dSurface);
6421	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6422	"VMSVGA 3d surface details and bitmap: "
6423	"sid[>dir]",
6424	vmsvgaR3Info3dSurfaceBmp);
6425	# endif
6426
6427	return VINF_SUCCESS;
6428	}
6429
6430	/**
6431	* Power On notification.
6432	*
6433	* @returns VBox status code.
6434	* @param pDevIns The device instance data.
6435	*
6436	* @remarks Caller enters the device critical section.
6437	*/
6438	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6439	{
6440	# ifdef VBOX_WITH_VMSVGA3D
6441	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6442	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6443	if (pThis->svga.f3DEnabled)
6444	{
6445	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6446
6447	if (RT_SUCCESS(rc))
6448	{
6449	/* Initialize FIFO 3D capabilities. */
6450	vmsvgaR3InitFifo3DCaps(pThisCC);
6451	}
6452	}
6453	# else /* !VBOX_WITH_VMSVGA3D */
6454	RT_NOREF(pDevIns);
6455	# endif /* !VBOX_WITH_VMSVGA3D */
6456	}
6457
6458	#endif /* IN_RING3 */
6459

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 82199

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