DevVGA-SVGA.cpp@ 83193

Last change on this file since 83193 was 83156, checked in by vboxsync, 5 years ago
bugref:9637 Some PDMIDISPLAYPORT::pfnReportMonitorPositions nits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 296.8 KB

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1	/* $Id: DevVGA-SVGA.cpp 83156 2020-02-25 18:19:56Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdEscape;
271	STAMCOUNTER StatR3CmdDefineScreen;
272	STAMCOUNTER StatR3CmdDestroyScreen;
273	STAMCOUNTER StatR3CmdDefineGmrFb;
274	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
275	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
276	STAMCOUNTER StatR3CmdAnnotationFill;
277	STAMCOUNTER StatR3CmdAnnotationCopy;
278	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
279	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
280	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
281	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
282	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
283	STAMCOUNTER StatR3Cmd3dSurfaceDma;
284	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
285	STAMCOUNTER StatR3Cmd3dContextDefine;
286	STAMCOUNTER StatR3Cmd3dContextDestroy;
287	STAMCOUNTER StatR3Cmd3dSetTransform;
288	STAMCOUNTER StatR3Cmd3dSetZRange;
289	STAMCOUNTER StatR3Cmd3dSetRenderState;
290	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
291	STAMCOUNTER StatR3Cmd3dSetTextureState;
292	STAMCOUNTER StatR3Cmd3dSetMaterial;
293	STAMCOUNTER StatR3Cmd3dSetLightData;
294	STAMCOUNTER StatR3Cmd3dSetLightEnable;
295	STAMCOUNTER StatR3Cmd3dSetViewPort;
296	STAMCOUNTER StatR3Cmd3dSetClipPlane;
297	STAMCOUNTER StatR3Cmd3dClear;
298	STAMCOUNTER StatR3Cmd3dPresent;
299	STAMCOUNTER StatR3Cmd3dPresentReadBack;
300	STAMCOUNTER StatR3Cmd3dShaderDefine;
301	STAMCOUNTER StatR3Cmd3dShaderDestroy;
302	STAMCOUNTER StatR3Cmd3dSetShader;
303	STAMCOUNTER StatR3Cmd3dSetShaderConst;
304	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
305	STAMCOUNTER StatR3Cmd3dSetScissorRect;
306	STAMCOUNTER StatR3Cmd3dBeginQuery;
307	STAMCOUNTER StatR3Cmd3dEndQuery;
308	STAMCOUNTER StatR3Cmd3dWaitForQuery;
309	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
310	STAMCOUNTER StatR3Cmd3dActivateSurface;
311	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
312
313	STAMCOUNTER StatR3RegConfigDoneWr;
314	STAMCOUNTER StatR3RegGmrDescriptorWr;
315	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
316	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
317
318	STAMCOUNTER StatFifoCommands;
319	STAMCOUNTER StatFifoErrors;
320	STAMCOUNTER StatFifoUnkCmds;
321	STAMCOUNTER StatFifoTodoTimeout;
322	STAMCOUNTER StatFifoTodoWoken;
323	STAMPROFILE StatFifoStalls;
324	STAMPROFILE StatFifoExtendedSleep;
325	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
326	STAMCOUNTER StatFifoAccessHandler;
327	# endif
328	STAMCOUNTER StatFifoCursorFetchAgain;
329	STAMCOUNTER StatFifoCursorNoChange;
330	STAMCOUNTER StatFifoCursorPosition;
331	STAMCOUNTER StatFifoCursorVisiblity;
332	STAMCOUNTER StatFifoWatchdogWakeUps;
333	} VMSVGAR3STATE, *PVMSVGAR3STATE;
334	#endif /* IN_RING3 */
335
336
337	/*********************************************************************************************************************************
338	* Internal Functions *
339	*********************************************************************************************************************************/
340	#ifdef IN_RING3
341	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
342	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
343	# endif
344	# ifdef DEBUG_GMR_ACCESS
345	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
346	# endif
347	#endif
348
349
350	/*********************************************************************************************************************************
351	* Global Variables *
352	*********************************************************************************************************************************/
353	#ifdef IN_RING3
354
355	/**
356	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
357	*/
358	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
359	{
360	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
361	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
362	SSMFIELD_ENTRY_TERM()
363	};
364
365	/**
366	* SSM descriptor table for the GMR structure.
367	*/
368	static SSMFIELD const g_aGMRFields[] =
369	{
370	SSMFIELD_ENTRY( GMR, cMaxPages),
371	SSMFIELD_ENTRY( GMR, cbTotal),
372	SSMFIELD_ENTRY( GMR, numDescriptors),
373	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
374	SSMFIELD_ENTRY_TERM()
375	};
376
377	/**
378	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
379	*/
380	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
381	{
382	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
383	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
384	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
385	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
386	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
393	SSMFIELD_ENTRY_TERM()
394	};
395
396	/**
397	* SSM descriptor table for the VMSVGAR3STATE structure.
398	*/
399	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
400	{
401	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
402	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
403	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
404	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
405	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
406	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
409	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
411	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
412	#ifdef VMSVGA_USE_EMT_HALT_CODE
413	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
414	#else
415	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
416	#endif
417	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
475
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
480
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
488	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
490	# endif
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
495
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	/**
500	* SSM descriptor table for the VGAState.svga structure.
501	*/
502	static SSMFIELD const g_aVGAStateSVGAFields[] =
503	{
504	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
507	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
508	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
509	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
510	SSMFIELD_ENTRY( VMSVGAState, fBusy),
511	SSMFIELD_ENTRY( VMSVGAState, fTraces),
512	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
513	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
514	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
515	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
516	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
517	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
518	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
519	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
520	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
523	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
524	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
525	SSMFIELD_ENTRY( VMSVGAState, uWidth),
526	SSMFIELD_ENTRY( VMSVGAState, uHeight),
527	SSMFIELD_ENTRY( VMSVGAState, uBpp),
528	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
529	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
530	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
531	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
532	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
533	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
534	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
536	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
538	SSMFIELD_ENTRY_TERM()
539	};
540	#endif /* IN_RING3 */
541
542
543	/*********************************************************************************************************************************
544	* Internal Functions *
545	*********************************************************************************************************************************/
546	#ifdef IN_RING3
547	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
548	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
549	uint32_t uVersion, uint32_t uPass);
550	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
551	# ifdef VBOX_WITH_VMSVGA3D
552	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
553	# endif /* VBOX_WITH_VMSVGA3D */
554	#endif /* IN_RING3 */
555
556
557
558	#ifdef IN_RING3
559	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
560	{
561	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
562	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
563	&& pSVGAState
564	&& pSVGAState->aScreens[idScreen].fDefined)
565	{
566	return &pSVGAState->aScreens[idScreen];
567	}
568	return NULL;
569	}
570	#endif /* IN_RING3 */
571
572	#ifdef LOG_ENABLED
573
574	/**
575	* Index register string name lookup
576	*
577	* @returns Index register string or "UNKNOWN"
578	* @param pThis The shared VGA/VMSVGA state.
579	* @param idxReg The index register.
580	*/
581	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
582	{
583	switch (idxReg)
584	{
585	case SVGA_REG_ID: return "SVGA_REG_ID";
586	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
587	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
588	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
589	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
590	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
591	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
592	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
593	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
594	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
595	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
596	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
597	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
598	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
599	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
600	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
601	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
602	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
603	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
604	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
605	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
606	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
607	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
608	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
609	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
610	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
611	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
612	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
613	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
614	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
615	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
616	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
617	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
618	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
619	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
620	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
621	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
622	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
623	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
624	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
625	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
626	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
627	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
628	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
629	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
630	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
631	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
632	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
633	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
634	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
635
636	default:
637	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
638	return "SVGA_SCRATCH_BASE reg";
639	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
640	return "SVGA_PALETTE_BASE reg";
641	return "UNKNOWN";
642	}
643	}
644
645	#ifdef IN_RING3
646	/**
647	* FIFO command name lookup
648	*
649	* @returns FIFO command string or "UNKNOWN"
650	* @param u32Cmd FIFO command
651	*/
652	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
653	{
654	switch (u32Cmd)
655	{
656	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
657	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
658	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
659	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
660	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
661	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
662	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
663	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
664	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
665	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
666	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
667	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
668	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
669	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
670	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
671	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
672	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
673	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
674	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
675	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
676	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
677	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
678	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
679	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
680	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
681	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
682	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
683	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
684	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
685	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
686	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
687	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
688	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
689	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
690	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
691	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
692	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
693	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
694	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
695	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
696	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
697	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
698	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
699	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
700	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
701	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
702	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
703	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
704	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
705	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
706	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
707	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
708	default: return "UNKNOWN";
709	}
710	}
711	# endif /* IN_RING3 */
712
713	#endif /* LOG_ENABLED */
714	#ifdef IN_RING3
715
716	/**
717	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
718	*/
719	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
720	{
721	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
722	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
723
724	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
725	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
726
727	/** @todo Test how it interacts with multiple screen objects. */
728	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
729	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
730	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
731
732	if (x < uWidth)
733	{
734	pThis->svga.viewport.x = x;
735	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
736	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
737	}
738	else
739	{
740	pThis->svga.viewport.x = uWidth;
741	pThis->svga.viewport.cx = 0;
742	pThis->svga.viewport.xRight = uWidth;
743	}
744	if (y < uHeight)
745	{
746	pThis->svga.viewport.y = y;
747	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
748	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
749	pThis->svga.viewport.yHighWC = uHeight - y;
750	}
751	else
752	{
753	pThis->svga.viewport.y = uHeight;
754	pThis->svga.viewport.cy = 0;
755	pThis->svga.viewport.yLowWC = 0;
756	pThis->svga.viewport.yHighWC = 0;
757	}
758
759	# ifdef VBOX_WITH_VMSVGA3D
760	/*
761	* Now inform the 3D backend.
762	*/
763	if (pThis->svga.f3DEnabled)
764	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
765	# else
766	RT_NOREF(OldViewport);
767	# endif
768	}
769
770
771	/**
772	* Updating screen information in API
773	*
774	* @param pThis The The shared VGA/VMSVGA instance data.
775	* @param pThisCC The VGA/VMSVGA state for ring-3.
776	*/
777	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
778	{
779	int rc;
780
781	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
782
783	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
784	{
785	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
786	if (!pScreen->fModified)
787	continue;
788
789	pScreen->fModified = false;
790
791	VBVAINFOVIEW view;
792	RT_ZERO(view);
793	view.u32ViewIndex = pScreen->idScreen;
794	// view.u32ViewOffset = 0;
795	view.u32ViewSize = pThis->vram_size;
796	view.u32MaxScreenSize = pThis->vram_size;
797
798	VBVAINFOSCREEN screen;
799	RT_ZERO(screen);
800	screen.u32ViewIndex = pScreen->idScreen;
801
802	if (pScreen->fDefined)
803	{
804	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
805	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
806	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
807	{
808	Assert(pThis->svga.fGFBRegisters);
809	continue;
810	}
811
812	screen.i32OriginX = pScreen->xOrigin;
813	screen.i32OriginY = pScreen->yOrigin;
814	screen.u32StartOffset = pScreen->offVRAM;
815	screen.u32LineSize = pScreen->cbPitch;
816	screen.u32Width = pScreen->cWidth;
817	screen.u32Height = pScreen->cHeight;
818	screen.u16BitsPerPixel = pScreen->cBpp;
819	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
820	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
821	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
822	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
823	}
824	else
825	{
826	/* Screen is destroyed. */
827	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
828	}
829
830	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
831	AssertRC(rc);
832	}
833	}
834
835
836	/**
837	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
838	*
839	* Used to update screen offsets (positions) since appearently vmwgfx fails to
840	* pass correct offsets thru FIFO.
841	*/
842	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
843	{
844	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
845	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
846	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
847
848	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
849	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
850	for (uint32_t i = 0; i < cPositions; ++i)
851	{
852	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
853	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
854	continue;
855
856	if (pSVGAState->aScreens[i].xOrigin == -1)
857	continue;
858	if (pSVGAState->aScreens[i].yOrigin == -1)
859	continue;
860
861	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
862	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
863	pSVGAState->aScreens[i].fModified = true;
864	}
865
866	vmsvgaR3VBVAResize(pThis, pThisCC);
867	}
868
869	#endif /* IN_RING3 */
870
871	/**
872	* Read port register
873	*
874	* @returns VBox status code.
875	* @param pDevIns The device instance.
876	* @param pThis The shared VGA/VMSVGA state.
877	* @param pu32 Where to store the read value
878	*/
879	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
880	{
881	#ifdef IN_RING3
882	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
883	#endif
884	int rc = VINF_SUCCESS;
885	*pu32 = 0;
886
887	/* Rough index register validation. */
888	uint32_t idxReg = pThis->svga.u32IndexReg;
889	#if !defined(IN_RING3) && defined(VBOX_STRICT)
890	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
891	VINF_IOM_R3_IOPORT_READ);
892	#else
893	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
895	VINF_SUCCESS);
896	#endif
897	RT_UNTRUSTED_VALIDATED_FENCE();
898
899	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
900	if ( idxReg >= SVGA_REG_CAPABILITIES
901	&& pThis->svga.u32SVGAId == SVGA_ID_0)
902	{
903	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
904	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
905	}
906
907	switch (idxReg)
908	{
909	case SVGA_REG_ID:
910	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
911	*pu32 = pThis->svga.u32SVGAId;
912	break;
913
914	case SVGA_REG_ENABLE:
915	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
916	*pu32 = pThis->svga.fEnabled;
917	break;
918
919	case SVGA_REG_WIDTH:
920	{
921	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
922	if ( pThis->svga.fEnabled
923	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
924	*pu32 = pThis->svga.uWidth;
925	else
926	{
927	#ifndef IN_RING3
928	rc = VINF_IOM_R3_IOPORT_READ;
929	#else
930	*pu32 = pThisCC->pDrv->cx;
931	#endif
932	}
933	break;
934	}
935
936	case SVGA_REG_HEIGHT:
937	{
938	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
939	if ( pThis->svga.fEnabled
940	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
941	*pu32 = pThis->svga.uHeight;
942	else
943	{
944	#ifndef IN_RING3
945	rc = VINF_IOM_R3_IOPORT_READ;
946	#else
947	*pu32 = pThisCC->pDrv->cy;
948	#endif
949	}
950	break;
951	}
952
953	case SVGA_REG_MAX_WIDTH:
954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
955	*pu32 = pThis->svga.u32MaxWidth;
956	break;
957
958	case SVGA_REG_MAX_HEIGHT:
959	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
960	*pu32 = pThis->svga.u32MaxHeight;
961	break;
962
963	case SVGA_REG_DEPTH:
964	/* This returns the color depth of the current mode. */
965	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
966	switch (pThis->svga.uBpp)
967	{
968	case 15:
969	case 16:
970	case 24:
971	*pu32 = pThis->svga.uBpp;
972	break;
973
974	default:
975	case 32:
976	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
977	break;
978	}
979	break;
980
981	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
983	if ( pThis->svga.fEnabled
984	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
985	*pu32 = pThis->svga.uBpp;
986	else
987	{
988	#ifndef IN_RING3
989	rc = VINF_IOM_R3_IOPORT_READ;
990	#else
991	*pu32 = pThisCC->pDrv->cBits;
992	#endif
993	}
994	break;
995
996	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
997	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
998	if ( pThis->svga.fEnabled
999	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1000	*pu32 = (pThis->svga.uBpp + 7) & ~7;
1001	else
1002	{
1003	#ifndef IN_RING3
1004	rc = VINF_IOM_R3_IOPORT_READ;
1005	#else
1006	*pu32 = (pThisCC->pDrv->cBits + 7) & ~7;
1007	#endif
1008	}
1009	break;
1010
1011	case SVGA_REG_PSEUDOCOLOR:
1012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1013	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1014	break;
1015
1016	case SVGA_REG_RED_MASK:
1017	case SVGA_REG_GREEN_MASK:
1018	case SVGA_REG_BLUE_MASK:
1019	{
1020	uint32_t uBpp;
1021
1022	if ( pThis->svga.fEnabled
1023	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1024	{
1025	uBpp = pThis->svga.uBpp;
1026	}
1027	else
1028	{
1029	#ifndef IN_RING3
1030	rc = VINF_IOM_R3_IOPORT_READ;
1031	break;
1032	#else
1033	uBpp = pThisCC->pDrv->cBits;
1034	#endif
1035	}
1036	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1037	switch (uBpp)
1038	{
1039	case 8:
1040	u32RedMask = 0x07;
1041	u32GreenMask = 0x38;
1042	u32BlueMask = 0xc0;
1043	break;
1044
1045	case 15:
1046	u32RedMask = 0x0000001f;
1047	u32GreenMask = 0x000003e0;
1048	u32BlueMask = 0x00007c00;
1049	break;
1050
1051	case 16:
1052	u32RedMask = 0x0000001f;
1053	u32GreenMask = 0x000007e0;
1054	u32BlueMask = 0x0000f800;
1055	break;
1056
1057	case 24:
1058	case 32:
1059	default:
1060	u32RedMask = 0x00ff0000;
1061	u32GreenMask = 0x0000ff00;
1062	u32BlueMask = 0x000000ff;
1063	break;
1064	}
1065	switch (idxReg)
1066	{
1067	case SVGA_REG_RED_MASK:
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1069	*pu32 = u32RedMask;
1070	break;
1071
1072	case SVGA_REG_GREEN_MASK:
1073	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1074	*pu32 = u32GreenMask;
1075	break;
1076
1077	case SVGA_REG_BLUE_MASK:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1079	*pu32 = u32BlueMask;
1080	break;
1081	}
1082	break;
1083	}
1084
1085	case SVGA_REG_BYTES_PER_LINE:
1086	{
1087	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1088	if ( pThis->svga.fEnabled
1089	&& pThis->svga.cbScanline)
1090	*pu32 = pThis->svga.cbScanline;
1091	else
1092	{
1093	#ifndef IN_RING3
1094	rc = VINF_IOM_R3_IOPORT_READ;
1095	#else
1096	*pu32 = pThisCC->pDrv->cbScanline;
1097	#endif
1098	}
1099	break;
1100	}
1101
1102	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1103	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1104	*pu32 = pThis->vram_size;
1105	break;
1106
1107	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1108	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1109	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1110	*pu32 = pThis->GCPhysVRAM;
1111	break;
1112
1113	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1114	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1115	/* Always zero in our case. */
1116	*pu32 = 0;
1117	break;
1118
1119	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1120	{
1121	#ifndef IN_RING3
1122	rc = VINF_IOM_R3_IOPORT_READ;
1123	#else
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1125
1126	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1127	if ( pThis->svga.fEnabled
1128	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1129	{
1130	/* Hardware enabled; return real framebuffer size .*/
1131	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1132	}
1133	else
1134	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1135
1136	pu32 = RT_MIN(pThis->vram_size, pu32);
1137	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1138	#endif
1139	break;
1140	}
1141
1142	case SVGA_REG_CAPABILITIES:
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1144	*pu32 = pThis->svga.u32RegCaps;
1145	break;
1146
1147	case SVGA_REG_MEM_START: /* FIFO start */
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1149	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1150	*pu32 = pThis->svga.GCPhysFIFO;
1151	break;
1152
1153	case SVGA_REG_MEM_SIZE: /* FIFO size */
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1155	*pu32 = pThis->svga.cbFIFO;
1156	break;
1157
1158	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1160	*pu32 = pThis->svga.fConfigured;
1161	break;
1162
1163	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1165	*pu32 = 0;
1166	break;
1167
1168	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1170	if (pThis->svga.fBusy)
1171	{
1172	#ifndef IN_RING3
1173	/* Go to ring-3 and halt the CPU. */
1174	rc = VINF_IOM_R3_IOPORT_READ;
1175	RT_NOREF(pDevIns);
1176	break;
1177	#else
1178	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1179	/* The guest is basically doing a HLT via the device here, but with
1180	a special wake up condition on FIFO completion. */
1181	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1182	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1183	PVM pVM = PDMDevHlpGetVM(pDevIns);
1184	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1185	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1186	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1187	if (pThis->svga.fBusy)
1188	{
1189	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1190	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1191	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1192	}
1193	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1194	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1195	# else
1196
1197	/* Delay the EMT a bit so the FIFO and others can get some work done.
1198	This used to be a crude 50 ms sleep. The current code tries to be
1199	more efficient, but the consept is still very crude. */
1200	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1201	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1202	RTThreadYield();
1203	if (pThis->svga.fBusy)
1204	{
1205	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1206
1207	if (pThis->svga.fBusy && cRefs == 1)
1208	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1209	if (pThis->svga.fBusy)
1210	{
1211	/** @todo If this code is going to stay, we need to call into the halt/wait
1212	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1213	* suffer when the guest is polling on a busy FIFO. */
1214	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1215	if (cNsMaxWait >= RT_NS_100US)
1216	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1217	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1218	RT_MIN(cNsMaxWait, RT_NS_10MS));
1219	}
1220
1221	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1222	}
1223	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1224	# endif
1225	*pu32 = pThis->svga.fBusy != 0;
1226	#endif
1227	}
1228	else
1229	*pu32 = false;
1230	break;
1231
1232	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1234	*pu32 = pThis->svga.u32GuestId;
1235	break;
1236
1237	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1239	*pu32 = pThis->svga.cScratchRegion;
1240	break;
1241
1242	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1244	*pu32 = SVGA_FIFO_NUM_REGS;
1245	break;
1246
1247	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1249	*pu32 = pThis->svga.u32PitchLock;
1250	break;
1251
1252	case SVGA_REG_IRQMASK: /* Interrupt mask */
1253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1254	*pu32 = pThis->svga.u32IrqMask;
1255	break;
1256
1257	/* See "Guest memory regions" below. */
1258	case SVGA_REG_GMR_ID:
1259	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1260	*pu32 = pThis->svga.u32CurrentGMRId;
1261	break;
1262
1263	case SVGA_REG_GMR_DESCRIPTOR:
1264	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1265	/* Write only */
1266	*pu32 = 0;
1267	break;
1268
1269	case SVGA_REG_GMR_MAX_IDS:
1270	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1271	*pu32 = pThis->svga.cGMR;
1272	break;
1273
1274	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1275	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1276	*pu32 = VMSVGA_MAX_GMR_PAGES;
1277	break;
1278
1279	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1281	*pu32 = pThis->svga.fTraces;
1282	break;
1283
1284	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1286	*pu32 = VMSVGA_MAX_GMR_PAGES;
1287	break;
1288
1289	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1290	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1291	*pu32 = VMSVGA_SURFACE_SIZE;
1292	break;
1293
1294	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1295	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1296	break;
1297
1298	/* Mouse cursor support. */
1299	case SVGA_REG_CURSOR_ID:
1300	case SVGA_REG_CURSOR_X:
1301	case SVGA_REG_CURSOR_Y:
1302	case SVGA_REG_CURSOR_ON:
1303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxRd);
1304	break;
1305
1306	/* Legacy multi-monitor support */
1307	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1308	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1309	*pu32 = 1;
1310	break;
1311
1312	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1313	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1314	*pu32 = 0;
1315	break;
1316
1317	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1318	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1319	*pu32 = 0;
1320	break;
1321
1322	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1324	*pu32 = 0;
1325	break;
1326
1327	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1328	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1329	*pu32 = 0;
1330	break;
1331
1332	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1333	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1334	*pu32 = pThis->svga.uWidth;
1335	break;
1336
1337	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1338	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1339	*pu32 = pThis->svga.uHeight;
1340	break;
1341
1342	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1343	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1344	/* We must return something sensible here otherwise the Linux driver
1345	will take a legacy code path without 3d support. This number also
1346	limits how many screens Linux guests will allow. */
1347	*pu32 = pThis->cMonitors;
1348	break;
1349
1350	default:
1351	{
1352	uint32_t offReg;
1353	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1354	{
1355	RT_UNTRUSTED_VALIDATED_FENCE();
1356	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1357	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1358	}
1359	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1360	{
1361	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1362	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1363	RT_UNTRUSTED_VALIDATED_FENCE();
1364	uint32_t u32 = pThis->last_palette[offReg / 3];
1365	switch (offReg % 3)
1366	{
1367	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1368	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1369	case 2: pu32 = u32 & 0xff; break; / blue */
1370	}
1371	}
1372	else
1373	{
1374	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1375	rc = VINF_IOM_R3_IOPORT_READ;
1376	#else
1377	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1378
1379	/* Do not assert. The guest might be reading all registers. */
1380	LogFunc(("Unknown reg=%#x\n", idxReg));
1381	#endif
1382	}
1383	break;
1384	}
1385	}
1386	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1387	return rc;
1388	}
1389
1390	#ifdef IN_RING3
1391	/**
1392	* Apply the current resolution settings to change the video mode.
1393	*
1394	* @returns VBox status code.
1395	* @param pThis The shared VGA state.
1396	* @param pThisCC The ring-3 VGA state.
1397	*/
1398	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1399	{
1400	/* Always do changemode on FIFO thread. */
1401	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1402
1403	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1404
1405	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1406
1407	if (pThis->svga.fGFBRegisters)
1408	{
1409	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1410	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1411	* deletes all screens other than screen #0, and redefines screen
1412	* #0 according to the specified mode. Drivers that use
1413	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1414	*/
1415
1416	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1417	pScreen->fDefined = true;
1418	pScreen->fModified = true;
1419	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1420	pScreen->idScreen = 0;
1421	pScreen->xOrigin = 0;
1422	pScreen->yOrigin = 0;
1423	pScreen->offVRAM = 0;
1424	pScreen->cbPitch = pThis->svga.cbScanline;
1425	pScreen->cWidth = pThis->svga.uWidth;
1426	pScreen->cHeight = pThis->svga.uHeight;
1427	pScreen->cBpp = pThis->svga.uBpp;
1428
1429	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1430	{
1431	/* Delete screen. */
1432	pScreen = &pSVGAState->aScreens[iScreen];
1433	if (pScreen->fDefined)
1434	{
1435	pScreen->fModified = true;
1436	pScreen->fDefined = false;
1437	}
1438	}
1439	}
1440	else
1441	{
1442	/* "If Screen Objects are supported, they can be used to fully
1443	* replace the functionality provided by the framebuffer registers
1444	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1445	*/
1446	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1447	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1448	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
1449	}
1450
1451	vmsvgaR3VBVAResize(pThis, pThisCC);
1452
1453	/* Last stuff. For the VGA device screenshot. */
1454	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1455	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1456	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1457	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1458	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1459
1460	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1461	if ( pThis->svga.viewport.cx == 0
1462	&& pThis->svga.viewport.cy == 0)
1463	{
1464	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1465	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1466	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1467	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1468	pThis->svga.viewport.yLowWC = 0;
1469	}
1470
1471	return VINF_SUCCESS;
1472	}
1473
1474	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1475	{
1476	VBVACMDHDR cmd;
1477	cmd.x = (int16_t)(pScreen->xOrigin + x);
1478	cmd.y = (int16_t)(pScreen->yOrigin + y);
1479	cmd.w = (uint16_t)w;
1480	cmd.h = (uint16_t)h;
1481
1482	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1483	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1484	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1485	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1486
1487	return VINF_SUCCESS;
1488	}
1489
1490	#endif /* IN_RING3 */
1491	#if defined(IN_RING0) \|\| defined(IN_RING3)
1492
1493	/**
1494	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1495	*
1496	* @param pThis The shared VGA/VMSVGA instance data.
1497	* @param pThisCC The VGA/VMSVGA state for the current context.
1498	* @param fState The busy state.
1499	*/
1500	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1501	{
1502	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1503
1504	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1505	{
1506	/* Race / unfortunately scheduling. Highly unlikly. */
1507	uint32_t cLoops = 64;
1508	do
1509	{
1510	ASMNopPause();
1511	fState = (pThis->svga.fBusy != 0);
1512	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1513	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1514	}
1515	}
1516
1517
1518	/**
1519	* Update the scanline pitch in response to the guest changing mode
1520	* width/bpp.
1521	*
1522	* @param pThis The shared VGA/VMSVGA state.
1523	* @param pThisCC The VGA/VMSVGA state for the current context.
1524	*/
1525	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1526	{
1527	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1528	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1529	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1530	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1531
1532	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1533	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1534	* location but it has a different meaning.
1535	*/
1536	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1537	uFifoPitchLock = 0;
1538
1539	/* Sanitize values. */
1540	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1541	uFifoPitchLock = 0;
1542	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1543	uRegPitchLock = 0;
1544
1545	/* Prefer the register value to the FIFO value.*/
1546	if (uRegPitchLock)
1547	pThis->svga.cbScanline = uRegPitchLock;
1548	else if (uFifoPitchLock)
1549	pThis->svga.cbScanline = uFifoPitchLock;
1550	else
1551	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1552
1553	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1554	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1555	}
1556
1557	#endif /* IN_RING0 \|\| IN_RING3 */
1558
1559
1560	/**
1561	* Write port register
1562	*
1563	* @returns Strict VBox status code.
1564	* @param pDevIns The device instance.
1565	* @param pThis The shared VGA/VMSVGA state.
1566	* @param pThisCC The VGA/VMSVGA state for the current context.
1567	* @param u32 Value to write
1568	*/
1569	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1570	{
1571	#ifdef IN_RING3
1572	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1573	#endif
1574	VBOXSTRICTRC rc = VINF_SUCCESS;
1575	RT_NOREF(pThisCC);
1576
1577	/* Rough index register validation. */
1578	uint32_t idxReg = pThis->svga.u32IndexReg;
1579	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1580	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1581	VINF_IOM_R3_IOPORT_WRITE);
1582	#else
1583	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1584	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1585	VINF_SUCCESS);
1586	#endif
1587	RT_UNTRUSTED_VALIDATED_FENCE();
1588
1589	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1590	if ( idxReg >= SVGA_REG_CAPABILITIES
1591	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1592	{
1593	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1594	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1595	}
1596	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1597	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1598	switch (idxReg)
1599	{
1600	case SVGA_REG_WIDTH:
1601	case SVGA_REG_HEIGHT:
1602	case SVGA_REG_PITCHLOCK:
1603	case SVGA_REG_BITS_PER_PIXEL:
1604	pThis->svga.fGFBRegisters = true;
1605	break;
1606	default:
1607	break;
1608	}
1609
1610	switch (idxReg)
1611	{
1612	case SVGA_REG_ID:
1613	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1614	if ( u32 == SVGA_ID_0
1615	\|\| u32 == SVGA_ID_1
1616	\|\| u32 == SVGA_ID_2)
1617	pThis->svga.u32SVGAId = u32;
1618	else
1619	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1620	break;
1621
1622	case SVGA_REG_ENABLE:
1623	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1624	#ifdef IN_RING3
1625	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1626	&& pThis->svga.fEnabled == false)
1627	{
1628	/* Make a backup copy of the first 512kb in order to save font data etc. */
1629	/** @todo should probably swap here, rather than copy + zero */
1630	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1631	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1632	}
1633
1634	pThis->svga.fEnabled = u32;
1635	if (pThis->svga.fEnabled)
1636	{
1637	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1638	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
1639	&& pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
1640	{
1641	/* Keep the current mode. */
1642	pThis->svga.uWidth = pThisCC->pDrv->cx;
1643	pThis->svga.uHeight = pThisCC->pDrv->cy;
1644	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1645	}
1646
1647	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1648	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED
1649	&& pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)
1650	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1651	# ifdef LOG_ENABLED
1652	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1653	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1654	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1655	# endif
1656
1657	/* Disable or enable dirty page tracking according to the current fTraces value. */
1658	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1659
1660	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1661	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1662	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1663	}
1664	else
1665	{
1666	/* Restore the text mode backup. */
1667	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1668
1669	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1670
1671	/* Enable dirty page tracking again when going into legacy mode. */
1672	vmsvgaR3SetTraces(pDevIns, pThis, true);
1673
1674	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1675	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1676	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1677
1678	/* Clear the pitch lock. */
1679	pThis->svga.u32PitchLock = 0;
1680	}
1681	#else /* !IN_RING3 */
1682	rc = VINF_IOM_R3_IOPORT_WRITE;
1683	#endif /* !IN_RING3 */
1684	break;
1685
1686	case SVGA_REG_WIDTH:
1687	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1688	if (pThis->svga.uWidth != u32)
1689	{
1690	#if defined(IN_RING3) \|\| defined(IN_RING0)
1691	pThis->svga.uWidth = u32;
1692	vmsvgaHCUpdatePitch(pThis, pThisCC);
1693	if (pThis->svga.fEnabled)
1694	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1695	#else
1696	rc = VINF_IOM_R3_IOPORT_WRITE;
1697	#endif
1698	}
1699	/* else: nop */
1700	break;
1701
1702	case SVGA_REG_HEIGHT:
1703	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1704	if (pThis->svga.uHeight != u32)
1705	{
1706	pThis->svga.uHeight = u32;
1707	if (pThis->svga.fEnabled)
1708	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1709	}
1710	/* else: nop */
1711	break;
1712
1713	case SVGA_REG_DEPTH:
1714	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1715	/** @todo read-only?? */
1716	break;
1717
1718	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1719	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1720	if (pThis->svga.uBpp != u32)
1721	{
1722	#if defined(IN_RING3) \|\| defined(IN_RING0)
1723	pThis->svga.uBpp = u32;
1724	vmsvgaHCUpdatePitch(pThis, pThisCC);
1725	if (pThis->svga.fEnabled)
1726	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1727	#else
1728	rc = VINF_IOM_R3_IOPORT_WRITE;
1729	#endif
1730	}
1731	/* else: nop */
1732	break;
1733
1734	case SVGA_REG_PSEUDOCOLOR:
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1736	break;
1737
1738	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1739	#ifdef IN_RING3
1740	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1741	pThis->svga.fConfigured = u32;
1742	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1743	if (!pThis->svga.fConfigured)
1744	pThis->svga.fTraces = true;
1745	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1746	#else
1747	rc = VINF_IOM_R3_IOPORT_WRITE;
1748	#endif
1749	break;
1750
1751	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1752	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1753	if ( pThis->svga.fEnabled
1754	&& pThis->svga.fConfigured)
1755	{
1756	#if defined(IN_RING3) \|\| defined(IN_RING0)
1757	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1758	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1759	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1760	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1761
1762	/* Kick the FIFO thread to start processing commands again. */
1763	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1764	#else
1765	rc = VINF_IOM_R3_IOPORT_WRITE;
1766	#endif
1767	}
1768	/* else nothing to do. */
1769	else
1770	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1771
1772	break;
1773
1774	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1775	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1776	break;
1777
1778	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1779	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1780	pThis->svga.u32GuestId = u32;
1781	break;
1782
1783	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1784	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1785	pThis->svga.u32PitchLock = u32;
1786	/* Should this also update the FIFO pitch lock? Unclear. */
1787	break;
1788
1789	case SVGA_REG_IRQMASK: /* Interrupt mask */
1790	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1791	pThis->svga.u32IrqMask = u32;
1792
1793	/* Irq pending after the above change? */
1794	if (pThis->svga.u32IrqStatus & u32)
1795	{
1796	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1797	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1798	}
1799	else
1800	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1801	break;
1802
1803	/* Mouse cursor support */
1804	case SVGA_REG_CURSOR_ID:
1805	case SVGA_REG_CURSOR_X:
1806	case SVGA_REG_CURSOR_Y:
1807	case SVGA_REG_CURSOR_ON:
1808	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXxxxWr);
1809	break;
1810
1811	/* Legacy multi-monitor support */
1812	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1813	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1814	break;
1815	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1816	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1817	break;
1818	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1819	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1820	break;
1821	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1822	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1823	break;
1824	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1825	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1826	break;
1827	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1828	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1829	break;
1830	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1832	break;
1833	#ifdef VBOX_WITH_VMSVGA3D
1834	/* See "Guest memory regions" below. */
1835	case SVGA_REG_GMR_ID:
1836	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1837	pThis->svga.u32CurrentGMRId = u32;
1838	break;
1839
1840	case SVGA_REG_GMR_DESCRIPTOR:
1841	# ifndef IN_RING3
1842	rc = VINF_IOM_R3_IOPORT_WRITE;
1843	break;
1844	# else /* IN_RING3 */
1845	{
1846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1847
1848	/* Validate current GMR id. */
1849	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1850	AssertBreak(idGMR < pThis->svga.cGMR);
1851	RT_UNTRUSTED_VALIDATED_FENCE();
1852
1853	/* Free the old GMR if present. */
1854	vmsvgaR3GmrFree(pThisCC, idGMR);
1855
1856	/* Just undefine the GMR? */
1857	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1858	if (GCPhys == 0)
1859	{
1860	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1861	break;
1862	}
1863
1864
1865	/* Never cross a page boundary automatically. */
1866	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1867	uint32_t cPagesTotal = 0;
1868	uint32_t iDesc = 0;
1869	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1870	uint32_t cLoops = 0;
1871	RTGCPHYS GCPhysBase = GCPhys;
1872	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
1873	{
1874	/* Read descriptor. */
1875	SVGAGuestMemDescriptor desc;
1876	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
1877	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
1878
1879	if (desc.numPages != 0)
1880	{
1881	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1882	cPagesTotal += desc.numPages;
1883	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
1884
1885	if ((iDesc & 15) == 0)
1886	{
1887	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
1888	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
1889	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
1890	}
1891
1892	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1893	paDescs[iDesc++].numPages = desc.numPages;
1894
1895	/* Continue with the next descriptor. */
1896	GCPhys += sizeof(desc);
1897	}
1898	else if (desc.ppn == 0)
1899	break; /* terminator */
1900	else /* Pointer to the next physical page of descriptors. */
1901	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
1902
1903	cLoops++;
1904	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
1905	}
1906
1907	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
1908	if (RT_SUCCESS(rc))
1909	{
1910	/* Commit the GMR. */
1911	pSVGAState->paGMR[idGMR].paDesc = paDescs;
1912	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
1913	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
1914	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
1915	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
1916	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
1917	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
1918	}
1919	else
1920	{
1921	RTMemFree(paDescs);
1922	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
1923	}
1924	break;
1925	}
1926	# endif /* IN_RING3 */
1927	#endif // VBOX_WITH_VMSVGA3D
1928
1929	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1930	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
1931	if (pThis->svga.fTraces == u32)
1932	break; /* nothing to do */
1933
1934	#ifdef IN_RING3
1935	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
1936	#else
1937	rc = VINF_IOM_R3_IOPORT_WRITE;
1938	#endif
1939	break;
1940
1941	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1942	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
1943	break;
1944
1945	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1946	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
1947	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
1948	break;
1949
1950	case SVGA_REG_FB_START:
1951	case SVGA_REG_MEM_START:
1952	case SVGA_REG_HOST_BITS_PER_PIXEL:
1953	case SVGA_REG_MAX_WIDTH:
1954	case SVGA_REG_MAX_HEIGHT:
1955	case SVGA_REG_VRAM_SIZE:
1956	case SVGA_REG_FB_SIZE:
1957	case SVGA_REG_CAPABILITIES:
1958	case SVGA_REG_MEM_SIZE:
1959	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1960	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1961	case SVGA_REG_BYTES_PER_LINE:
1962	case SVGA_REG_FB_OFFSET:
1963	case SVGA_REG_RED_MASK:
1964	case SVGA_REG_GREEN_MASK:
1965	case SVGA_REG_BLUE_MASK:
1966	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1967	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1968	case SVGA_REG_GMR_MAX_IDS:
1969	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1970	/* Read only - ignore. */
1971	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
1972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
1973	break;
1974
1975	default:
1976	{
1977	uint32_t offReg;
1978	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1979	{
1980	RT_UNTRUSTED_VALIDATED_FENCE();
1981	pThis->svga.au32ScratchRegion[offReg] = u32;
1982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
1983	}
1984	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1985	{
1986	/* Note! Using last_palette rather than palette here to preserve the VGA one.
1987	Btw, see rgb_to_pixel32. */
1988	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
1989	u32 &= 0xff;
1990	RT_UNTRUSTED_VALIDATED_FENCE();
1991	uint32_t uRgb = pThis->last_palette[offReg / 3];
1992	switch (offReg % 3)
1993	{
1994	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
1995	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
1996	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
1997	}
1998	pThis->last_palette[offReg / 3] = uRgb;
1999	}
2000	else
2001	{
2002	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2003	rc = VINF_IOM_R3_IOPORT_WRITE;
2004	#else
2005	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2006	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2007	#endif
2008	}
2009	break;
2010	}
2011	}
2012	return rc;
2013	}
2014
2015	/**
2016	* @callback_method_impl{FNIOMIOPORTNEWIN}
2017	*/
2018	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2019	{
2020	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2021	RT_NOREF_PV(pvUser);
2022
2023	/* Only dword accesses. */
2024	if (cb == 4)
2025	{
2026	switch (offPort)
2027	{
2028	case SVGA_INDEX_PORT:
2029	*pu32 = pThis->svga.u32IndexReg;
2030	break;
2031
2032	case SVGA_VALUE_PORT:
2033	return vmsvgaReadPort(pDevIns, pThis, pu32);
2034
2035	case SVGA_BIOS_PORT:
2036	Log(("Ignoring BIOS port read\n"));
2037	*pu32 = 0;
2038	break;
2039
2040	case SVGA_IRQSTATUS_PORT:
2041	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2042	*pu32 = pThis->svga.u32IrqStatus;
2043	break;
2044
2045	default:
2046	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2047	*pu32 = UINT32_MAX;
2048	break;
2049	}
2050	}
2051	else
2052	{
2053	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2054	*pu32 = UINT32_MAX;
2055	}
2056	return VINF_SUCCESS;
2057	}
2058
2059	/**
2060	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2061	*/
2062	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2063	{
2064	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2065	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2066	RT_NOREF_PV(pvUser);
2067
2068	/* Only dword accesses. */
2069	if (cb == 4)
2070	switch (offPort)
2071	{
2072	case SVGA_INDEX_PORT:
2073	pThis->svga.u32IndexReg = u32;
2074	break;
2075
2076	case SVGA_VALUE_PORT:
2077	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2078
2079	case SVGA_BIOS_PORT:
2080	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2081	break;
2082
2083	case SVGA_IRQSTATUS_PORT:
2084	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2085	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2086	/* Clear the irq in case all events have been cleared. */
2087	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2088	{
2089	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2090	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2091	}
2092	break;
2093
2094	default:
2095	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2096	break;
2097	}
2098	else
2099	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2100
2101	return VINF_SUCCESS;
2102	}
2103
2104	#ifdef IN_RING3
2105
2106	# ifdef DEBUG_FIFO_ACCESS
2107	/**
2108	* Handle FIFO memory access.
2109	* @returns VBox status code.
2110	* @param pVM VM handle.
2111	* @param pThis The shared VGA/VMSVGA instance data.
2112	* @param GCPhys The access physical address.
2113	* @param fWriteAccess Read or write access
2114	*/
2115	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2116	{
2117	RT_NOREF(pVM);
2118	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2119	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2120
2121	switch (GCPhysOffset >> 2)
2122	{
2123	case SVGA_FIFO_MIN:
2124	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2125	break;
2126	case SVGA_FIFO_MAX:
2127	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2128	break;
2129	case SVGA_FIFO_NEXT_CMD:
2130	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2131	break;
2132	case SVGA_FIFO_STOP:
2133	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2134	break;
2135	case SVGA_FIFO_CAPABILITIES:
2136	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2137	break;
2138	case SVGA_FIFO_FLAGS:
2139	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2140	break;
2141	case SVGA_FIFO_FENCE:
2142	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2143	break;
2144	case SVGA_FIFO_3D_HWVERSION:
2145	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2146	break;
2147	case SVGA_FIFO_PITCHLOCK:
2148	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2149	break;
2150	case SVGA_FIFO_CURSOR_ON:
2151	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2152	break;
2153	case SVGA_FIFO_CURSOR_X:
2154	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2155	break;
2156	case SVGA_FIFO_CURSOR_Y:
2157	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2158	break;
2159	case SVGA_FIFO_CURSOR_COUNT:
2160	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2161	break;
2162	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2163	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2164	break;
2165	case SVGA_FIFO_RESERVED:
2166	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2167	break;
2168	case SVGA_FIFO_CURSOR_SCREEN_ID:
2169	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2170	break;
2171	case SVGA_FIFO_DEAD:
2172	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2173	break;
2174	case SVGA_FIFO_3D_HWVERSION_REVISED:
2175	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2176	break;
2177	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2178	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2179	break;
2180	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2181	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2182	break;
2183	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2184	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2185	break;
2186	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2187	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2188	break;
2189	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2190	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2191	break;
2192	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2193	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2194	break;
2195	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2196	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2197	break;
2198	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2199	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2200	break;
2201	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2202	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2203	break;
2204	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2205	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2206	break;
2207	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2208	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2209	break;
2210	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2211	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2212	break;
2213	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2214	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2215	break;
2216	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2217	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2218	break;
2219	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2220	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2221	break;
2222	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2223	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2224	break;
2225	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2226	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2227	break;
2228	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2229	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2230	break;
2231	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2232	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2233	break;
2234	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2235	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2236	break;
2237	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2238	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2239	break;
2240	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2241	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2242	break;
2243	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2244	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2245	break;
2246	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2247	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2248	break;
2249	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2250	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2251	break;
2252	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2253	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2254	break;
2255	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2256	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2257	break;
2258	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2259	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2260	break;
2261	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2262	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2263	break;
2264	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2265	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2266	break;
2267	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2268	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2269	break;
2270	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2271	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2272	break;
2273	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_3D_CAPS_LAST:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_GUEST_3D_HWVERSION:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_FENCE_GOAL:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_BUSY:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	default:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	}
2442
2443	return VINF_EM_RAW_EMULATE_INSTR;
2444	}
2445	# endif /* DEBUG_FIFO_ACCESS */
2446
2447	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2448	/**
2449	* HC access handler for the FIFO.
2450	*
2451	* @returns VINF_SUCCESS if the handler have carried out the operation.
2452	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2453	* @param pVM VM Handle.
2454	* @param pVCpu The cross context CPU structure for the calling EMT.
2455	* @param GCPhys The physical address the guest is writing to.
2456	* @param pvPhys The HC mapping of that address.
2457	* @param pvBuf What the guest is reading/writing.
2458	* @param cbBuf How much it's reading/writing.
2459	* @param enmAccessType The access type.
2460	* @param enmOrigin Who is making the access.
2461	* @param pvUser User argument.
2462	*/
2463	static DECLCALLBACK(VBOXSTRICTRC)
2464	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2465	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2466	{
2467	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2468	PVGASTATE pThis = (PVGASTATE)pvUser;
2469	AssertPtr(pThis);
2470
2471	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2472	/*
2473	* Wake up the FIFO thread as it might have work to do now.
2474	*/
2475	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2476	AssertLogRelRC(rc);
2477	# endif
2478
2479	# ifdef DEBUG_FIFO_ACCESS
2480	/*
2481	* When in debug-fifo-access mode, we do not disable the access handler,
2482	* but leave it on as we wish to catch all access.
2483	*/
2484	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2485	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2486	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2487	/*
2488	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2489	*/
2490	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2491	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2492	# endif
2493	if (RT_SUCCESS(rc))
2494	return VINF_PGM_HANDLER_DO_DEFAULT;
2495	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2496	return rc;
2497	}
2498	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2499
2500	#endif /* IN_RING3 */
2501
2502	#ifdef DEBUG_GMR_ACCESS
2503	# ifdef IN_RING3
2504
2505	/**
2506	* HC access handler for the FIFO.
2507	*
2508	* @returns VINF_SUCCESS if the handler have carried out the operation.
2509	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2510	* @param pVM VM Handle.
2511	* @param pVCpu The cross context CPU structure for the calling EMT.
2512	* @param GCPhys The physical address the guest is writing to.
2513	* @param pvPhys The HC mapping of that address.
2514	* @param pvBuf What the guest is reading/writing.
2515	* @param cbBuf How much it's reading/writing.
2516	* @param enmAccessType The access type.
2517	* @param enmOrigin Who is making the access.
2518	* @param pvUser User argument.
2519	*/
2520	static DECLCALLBACK(VBOXSTRICTRC)
2521	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2522	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2523	{
2524	PVGASTATE pThis = (PVGASTATE)pvUser;
2525	Assert(pThis);
2526	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2527	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2528
2529	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2530
2531	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2532	{
2533	PGMR pGMR = &pSVGAState->paGMR[i];
2534
2535	if (pGMR->numDescriptors)
2536	{
2537	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2538	{
2539	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2540	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2541	{
2542	/*
2543	* Turn off the write handler for this particular page and make it R/W.
2544	* Then return telling the caller to restart the guest instruction.
2545	*/
2546	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2547	AssertRC(rc);
2548	return VINF_PGM_HANDLER_DO_DEFAULT;
2549	}
2550	}
2551	}
2552	}
2553
2554	return VINF_PGM_HANDLER_DO_DEFAULT;
2555	}
2556
2557	/** Callback handler for VMR3ReqCallWaitU */
2558	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2559	{
2560	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2561	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2562	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2563	int rc;
2564
2565	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2566	{
2567	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2568	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2569	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2570	AssertRC(rc);
2571	}
2572	return VINF_SUCCESS;
2573	}
2574
2575	/** Callback handler for VMR3ReqCallWaitU */
2576	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2577	{
2578	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2579	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2580	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2581
2582	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2583	{
2584	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2585	AssertRC(rc);
2586	}
2587	return VINF_SUCCESS;
2588	}
2589
2590	/** Callback handler for VMR3ReqCallWaitU */
2591	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2592	{
2593	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2594
2595	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2596	{
2597	PGMR pGMR = &pSVGAState->paGMR[i];
2598
2599	if (pGMR->numDescriptors)
2600	{
2601	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2602	{
2603	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2604	AssertRC(rc);
2605	}
2606	}
2607	}
2608	return VINF_SUCCESS;
2609	}
2610
2611	# endif /* IN_RING3 */
2612	#endif /* DEBUG_GMR_ACCESS */
2613
2614	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2615
2616	#ifdef IN_RING3
2617
2618
2619	/**
2620	* Common worker for changing the pointer shape.
2621	*
2622	* @param pThisCC The VGA/VMSVGA state for ring-3.
2623	* @param pSVGAState The VMSVGA ring-3 instance data.
2624	* @param fAlpha Whether there is alpha or not.
2625	* @param xHot Hotspot x coordinate.
2626	* @param yHot Hotspot y coordinate.
2627	* @param cx Width.
2628	* @param cy Height.
2629	* @param pbData Heap copy of the cursor data. Consumed.
2630	* @param cbData The size of the data.
2631	*/
2632	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2633	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2634	{
2635	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2636	# ifdef LOG_ENABLED
2637	if (LogIs2Enabled())
2638	{
2639	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2640	if (!fAlpha)
2641	{
2642	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2643	for (uint32_t y = 0; y < cy; y++)
2644	{
2645	Log2(("%3u:", y));
2646	uint8_t const pbLine = &pbData[y cbAndLine];
2647	for (uint32_t x = 0; x < cx; x += 8)
2648	{
2649	uint8_t b = pbLine[x / 8];
2650	char szByte[12];
2651	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2652	szByte[1] = b & 0x40 ? '*' : ' ';
2653	szByte[2] = b & 0x20 ? '*' : ' ';
2654	szByte[3] = b & 0x10 ? '*' : ' ';
2655	szByte[4] = b & 0x08 ? '*' : ' ';
2656	szByte[5] = b & 0x04 ? '*' : ' ';
2657	szByte[6] = b & 0x02 ? '*' : ' ';
2658	szByte[7] = b & 0x01 ? '*' : ' ';
2659	szByte[8] = '\0';
2660	Log2(("%s", szByte));
2661	}
2662	Log2(("\n"));
2663	}
2664	}
2665
2666	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2667	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2668	for (uint32_t y = 0; y < cy; y++)
2669	{
2670	Log2(("%3u:", y));
2671	uint32_t const pu32Line = &pu32Xor[y cx];
2672	for (uint32_t x = 0; x < cx; x++)
2673	Log2((" %08x", pu32Line[x]));
2674	Log2(("\n"));
2675	}
2676	}
2677	# endif
2678
2679	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2680	AssertRC(rc);
2681
2682	if (pSVGAState->Cursor.fActive)
2683	RTMemFree(pSVGAState->Cursor.pData);
2684
2685	pSVGAState->Cursor.fActive = true;
2686	pSVGAState->Cursor.xHotspot = xHot;
2687	pSVGAState->Cursor.yHotspot = yHot;
2688	pSVGAState->Cursor.width = cx;
2689	pSVGAState->Cursor.height = cy;
2690	pSVGAState->Cursor.cbData = cbData;
2691	pSVGAState->Cursor.pData = pbData;
2692	}
2693
2694
2695	/**
2696	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2697	*
2698	* @param pThis The shared VGA/VMSVGA state.
2699	* @param pThisCC The VGA/VMSVGA state for ring-3.
2700	* @param pSVGAState The VMSVGA ring-3 instance data.
2701	* @param pCursor The cursor.
2702	* @param pbSrcAndMask The AND mask.
2703	* @param cbSrcAndLine The scanline length of the AND mask.
2704	* @param pbSrcXorMask The XOR mask.
2705	* @param cbSrcXorLine The scanline length of the XOR mask.
2706	*/
2707	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2708	SVGAFifoCmdDefineCursor const *pCursor,
2709	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2710	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2711	{
2712	uint32_t const cx = pCursor->width;
2713	uint32_t const cy = pCursor->height;
2714
2715	/*
2716	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2717	* The AND data uses 8-bit aligned scanlines.
2718	* The XOR data must be starting on a 32-bit boundrary.
2719	*/
2720	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2721	uint32_t cbDstAndMask = cbDstAndLine * cy;
2722	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2723	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2724
2725	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2726	AssertReturnVoid(pbCopy);
2727
2728	/* Convert the AND mask. */
2729	uint8_t *pbDst = pbCopy;
2730	uint8_t const *pbSrc = pbSrcAndMask;
2731	switch (pCursor->andMaskDepth)
2732	{
2733	case 1:
2734	if (cbSrcAndLine == cbDstAndLine)
2735	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2736	else
2737	{
2738	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2739	for (uint32_t y = 0; y < cy; y++)
2740	{
2741	memcpy(pbDst, pbSrc, cbDstAndLine);
2742	pbDst += cbDstAndLine;
2743	pbSrc += cbSrcAndLine;
2744	}
2745	}
2746	break;
2747	/* Should take the XOR mask into account for the multi-bit AND mask. */
2748	case 8:
2749	for (uint32_t y = 0; y < cy; y++)
2750	{
2751	for (uint32_t x = 0; x < cx; )
2752	{
2753	uint8_t bDst = 0;
2754	uint8_t fBit = 1;
2755	do
2756	{
2757	uintptr_t const idxPal = pbSrc[x] * 3;
2758	if ((( pThis->last_palette[idxPal]
2759	\| (pThis->last_palette[idxPal] >> 8)
2760	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2761	bDst \|= fBit;
2762	fBit <<= 1;
2763	x++;
2764	} while (x < cx && (x & 7));
2765	pbDst[(x - 1) / 8] = bDst;
2766	}
2767	pbDst += cbDstAndLine;
2768	pbSrc += cbSrcAndLine;
2769	}
2770	break;
2771	case 15:
2772	for (uint32_t y = 0; y < cy; y++)
2773	{
2774	for (uint32_t x = 0; x < cx; )
2775	{
2776	uint8_t bDst = 0;
2777	uint8_t fBit = 1;
2778	do
2779	{
2780	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2781	bDst \|= fBit;
2782	fBit <<= 1;
2783	x++;
2784	} while (x < cx && (x & 7));
2785	pbDst[(x - 1) / 8] = bDst;
2786	}
2787	pbDst += cbDstAndLine;
2788	pbSrc += cbSrcAndLine;
2789	}
2790	break;
2791	case 16:
2792	for (uint32_t y = 0; y < cy; y++)
2793	{
2794	for (uint32_t x = 0; x < cx; )
2795	{
2796	uint8_t bDst = 0;
2797	uint8_t fBit = 1;
2798	do
2799	{
2800	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2801	bDst \|= fBit;
2802	fBit <<= 1;
2803	x++;
2804	} while (x < cx && (x & 7));
2805	pbDst[(x - 1) / 8] = bDst;
2806	}
2807	pbDst += cbDstAndLine;
2808	pbSrc += cbSrcAndLine;
2809	}
2810	break;
2811	case 24:
2812	for (uint32_t y = 0; y < cy; y++)
2813	{
2814	for (uint32_t x = 0; x < cx; )
2815	{
2816	uint8_t bDst = 0;
2817	uint8_t fBit = 1;
2818	do
2819	{
2820	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2821	bDst \|= fBit;
2822	fBit <<= 1;
2823	x++;
2824	} while (x < cx && (x & 7));
2825	pbDst[(x - 1) / 8] = bDst;
2826	}
2827	pbDst += cbDstAndLine;
2828	pbSrc += cbSrcAndLine;
2829	}
2830	break;
2831	case 32:
2832	for (uint32_t y = 0; y < cy; y++)
2833	{
2834	for (uint32_t x = 0; x < cx; )
2835	{
2836	uint8_t bDst = 0;
2837	uint8_t fBit = 1;
2838	do
2839	{
2840	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2841	bDst \|= fBit;
2842	fBit <<= 1;
2843	x++;
2844	} while (x < cx && (x & 7));
2845	pbDst[(x - 1) / 8] = bDst;
2846	}
2847	pbDst += cbDstAndLine;
2848	pbSrc += cbSrcAndLine;
2849	}
2850	break;
2851	default:
2852	RTMemFree(pbCopy);
2853	AssertFailedReturnVoid();
2854	}
2855
2856	/* Convert the XOR mask. */
2857	uint32_t pu32Dst = (uint32_t )(pbCopy + cbDstAndMask);
2858	pbSrc = pbSrcXorMask;
2859	switch (pCursor->xorMaskDepth)
2860	{
2861	case 1:
2862	for (uint32_t y = 0; y < cy; y++)
2863	{
2864	for (uint32_t x = 0; x < cx; )
2865	{
2866	/* most significant bit is the left most one. */
2867	uint8_t bSrc = pbSrc[x / 8];
2868	do
2869	{
2870	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2871	bSrc <<= 1;
2872	x++;
2873	} while ((x & 7) && x < cx);
2874	}
2875	pbSrc += cbSrcXorLine;
2876	}
2877	break;
2878	case 8:
2879	for (uint32_t y = 0; y < cy; y++)
2880	{
2881	for (uint32_t x = 0; x < cx; x++)
2882	{
2883	uint32_t u = pThis->last_palette[pbSrc[x]];
2884	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
2885	}
2886	pbSrc += cbSrcXorLine;
2887	}
2888	break;
2889	case 15: /* Src: RGB-5-5-5 */
2890	for (uint32_t y = 0; y < cy; y++)
2891	{
2892	for (uint32_t x = 0; x < cx; x++)
2893	{
2894	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2895	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2896	((uValue >> 5) & 0x1f) << 3,
2897	((uValue >> 10) & 0x1f) << 3, 0);
2898	}
2899	pbSrc += cbSrcXorLine;
2900	}
2901	break;
2902	case 16: /* Src: RGB-5-6-5 */
2903	for (uint32_t y = 0; y < cy; y++)
2904	{
2905	for (uint32_t x = 0; x < cx; x++)
2906	{
2907	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
2908	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
2909	((uValue >> 5) & 0x3f) << 2,
2910	((uValue >> 11) & 0x1f) << 3, 0);
2911	}
2912	pbSrc += cbSrcXorLine;
2913	}
2914	break;
2915	case 24:
2916	for (uint32_t y = 0; y < cy; y++)
2917	{
2918	for (uint32_t x = 0; x < cx; x++)
2919	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
2920	pbSrc += cbSrcXorLine;
2921	}
2922	break;
2923	case 32:
2924	for (uint32_t y = 0; y < cy; y++)
2925	{
2926	for (uint32_t x = 0; x < cx; x++)
2927	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
2928	pbSrc += cbSrcXorLine;
2929	}
2930	break;
2931	default:
2932	RTMemFree(pbCopy);
2933	AssertFailedReturnVoid();
2934	}
2935
2936	/*
2937	* Pass it to the frontend/whatever.
2938	*/
2939	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
2940	}
2941
2942
2943	/**
2944	* Worker for vmsvgaR3FifoThread that handles an external command.
2945	*
2946	* @param pDevIns The device instance.
2947	* @param pThis The shared VGA/VMSVGA instance data.
2948	* @param pThisCC The VGA/VMSVGA state for ring-3.
2949	*/
2950	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
2951	{
2952	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
2953	switch (pThis->svga.u8FIFOExtCommand)
2954	{
2955	case VMSVGA_FIFO_EXTCMD_RESET:
2956	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
2957	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2958	# ifdef VBOX_WITH_VMSVGA3D
2959	if (pThis->svga.f3DEnabled)
2960	{
2961	/* The 3d subsystem must be reset from the fifo thread. */
2962	vmsvga3dReset(pThisCC);
2963	}
2964	# endif
2965	break;
2966
2967	case VMSVGA_FIFO_EXTCMD_TERMINATE:
2968	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
2969	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
2970	# ifdef VBOX_WITH_VMSVGA3D
2971	if (pThis->svga.f3DEnabled)
2972	{
2973	/* The 3d subsystem must be shut down from the fifo thread. */
2974	vmsvga3dTerminate(pThisCC);
2975	}
2976	# endif
2977	break;
2978
2979	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
2980	{
2981	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
2982	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
2983	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
2984	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
2985	# ifdef VBOX_WITH_VMSVGA3D
2986	if (pThis->svga.f3DEnabled)
2987	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
2988	# endif
2989	break;
2990	}
2991
2992	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
2993	{
2994	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
2995	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
2996	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
2997	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
2998	# ifdef VBOX_WITH_VMSVGA3D
2999	if (pThis->svga.f3DEnabled)
3000	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3001	# endif
3002	break;
3003	}
3004
3005	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3006	{
3007	# ifdef VBOX_WITH_VMSVGA3D
3008	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3009	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3010	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3011	# endif
3012	break;
3013	}
3014
3015
3016	default:
3017	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3018	break;
3019	}
3020
3021	/*
3022	* Signal the end of the external command.
3023	*/
3024	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3025	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3026	ASMMemoryFence(); /* paranoia^2 */
3027	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3028	AssertLogRelRC(rc);
3029	}
3030
3031	/**
3032	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3033	* doing a job on the FIFO thread (even when it's officially suspended).
3034	*
3035	* @returns VBox status code (fully asserted).
3036	* @param pDevIns The device instance.
3037	* @param pThis The shared VGA/VMSVGA instance data.
3038	* @param pThisCC The VGA/VMSVGA state for ring-3.
3039	* @param uExtCmd The command to execute on the FIFO thread.
3040	* @param pvParam Pointer to command parameters.
3041	* @param cMsWait The time to wait for the command, given in
3042	* milliseconds.
3043	*/
3044	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3045	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3046	{
3047	Assert(cMsWait >= RT_MS_1SEC * 5);
3048	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3049	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3050
3051	int rc;
3052	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3053	PDMTHREADSTATE enmState = pThread->enmState;
3054	if (enmState == PDMTHREADSTATE_SUSPENDED)
3055	{
3056	/*
3057	* The thread is suspended, we have to temporarily wake it up so it can
3058	* perform the task.
3059	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3060	*/
3061	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3062	/* Post the request. */
3063	pThis->svga.fFifoExtCommandWakeup = true;
3064	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3065	pThis->svga.u8FIFOExtCommand = uExtCmd;
3066	ASMMemoryFence(); /* paranoia^3 */
3067
3068	/* Resume the thread. */
3069	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3070	AssertLogRelRC(rc);
3071	if (RT_SUCCESS(rc))
3072	{
3073	/* Wait. Take care in case the semaphore was already posted (same as below). */
3074	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3075	if ( rc == VINF_SUCCESS
3076	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3077	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3078	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3079	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3080
3081	/* suspend the thread */
3082	pThis->svga.fFifoExtCommandWakeup = false;
3083	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3084	AssertLogRelRC(rc2);
3085	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3086	rc = rc2;
3087	}
3088	pThis->svga.fFifoExtCommandWakeup = false;
3089	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3090	}
3091	else if (enmState == PDMTHREADSTATE_RUNNING)
3092	{
3093	/*
3094	* The thread is running, should only happen during reset and vmsvga3dsfc.
3095	* We ASSUME not racing code here, both wrt thread state and ext commands.
3096	*/
3097	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3098	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3099
3100	/* Post the request. */
3101	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3102	pThis->svga.u8FIFOExtCommand = uExtCmd;
3103	ASMMemoryFence(); /* paranoia^2 */
3104	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3105	AssertLogRelRC(rc);
3106
3107	/* Wait. Take care in case the semaphore was already posted (same as above). */
3108	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3109	if ( rc == VINF_SUCCESS
3110	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3111	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3112	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3113	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3114
3115	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3116	}
3117	else
3118	{
3119	/*
3120	* Something is wrong with the thread!
3121	*/
3122	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3123	rc = VERR_INVALID_STATE;
3124	}
3125	return rc;
3126	}
3127
3128
3129	/**
3130	* Marks the FIFO non-busy, notifying any waiting EMTs.
3131	*
3132	* @param pDevIns The device instance.
3133	* @param pThis The shared VGA/VMSVGA instance data.
3134	* @param pThisCC The VGA/VMSVGA state for ring-3.
3135	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3136	* @param offFifoMin The start byte offset of the command FIFO.
3137	*/
3138	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3139	{
3140	ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
3141	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3142	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3143
3144	/* Wake up any waiting EMTs. */
3145	if (pSVGAState->cBusyDelayedEmts > 0)
3146	{
3147	# ifdef VMSVGA_USE_EMT_HALT_CODE
3148	PVM pVM = PDMDevHlpGetVM(pDevIns);
3149	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3150	if (idCpu != NIL_VMCPUID)
3151	{
3152	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3153	while (idCpu-- > 0)
3154	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3155	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3156	}
3157	# else
3158	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3159	AssertRC(rc2);
3160	# endif
3161	}
3162	}
3163
3164	/**
3165	* Reads (more) payload into the command buffer.
3166	*
3167	* @returns pbBounceBuf on success
3168	* @retval (void *)1 if the thread was requested to stop.
3169	* @retval NULL on FIFO error.
3170	*
3171	* @param cbPayloadReq The number of bytes of payload requested.
3172	* @param pFIFO The FIFO.
3173	* @param offCurrentCmd The FIFO byte offset of the current command.
3174	* @param offFifoMin The start byte offset of the command FIFO.
3175	* @param offFifoMax The end byte offset of the command FIFO.
3176	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3177	* always sufficient size.
3178	* @param pcbAlreadyRead How much payload we've already read into the bounce
3179	* buffer. (We will NEVER re-read anything.)
3180	* @param pThread The calling PDM thread handle.
3181	* @param pThis The shared VGA/VMSVGA instance data.
3182	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3183	* statistics collection.
3184	* @param pDevIns The device instance.
3185	*/
3186	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3187	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3188	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3189	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3190	{
3191	Assert(pbBounceBuf);
3192	Assert(pcbAlreadyRead);
3193	Assert(offFifoMin < offFifoMax);
3194	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3195	Assert(offFifoMax <= pThis->svga.cbFIFO);
3196
3197	/*
3198	* Check if the requested payload size has already been satisfied .
3199	* .
3200	* When called to read more, the caller is responsible for making sure the .
3201	* new command size (cbRequsted) never is smaller than what has already .
3202	* been read.
3203	*/
3204	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3205	if (cbPayloadReq <= cbAlreadyRead)
3206	{
3207	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3208	return pbBounceBuf;
3209	}
3210
3211	/*
3212	* Commands bigger than the fifo buffer are invalid.
3213	*/
3214	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3215	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3216	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3217	NULL);
3218
3219	/*
3220	* Move offCurrentCmd past the command dword.
3221	*/
3222	offCurrentCmd += sizeof(uint32_t);
3223	if (offCurrentCmd >= offFifoMax)
3224	offCurrentCmd = offFifoMin;
3225
3226	/*
3227	* Do we have sufficient payload data available already?
3228	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3229	*/
3230	uint32_t cbAfter, cbBefore;
3231	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3232	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3233	if (offNextCmd >= offCurrentCmd)
3234	{
3235	if (RT_LIKELY(offNextCmd < offFifoMax))
3236	cbAfter = offNextCmd - offCurrentCmd;
3237	else
3238	{
3239	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3240	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3241	offNextCmd, offFifoMin, offFifoMax));
3242	cbAfter = offFifoMax - offCurrentCmd;
3243	}
3244	cbBefore = 0;
3245	}
3246	else
3247	{
3248	cbAfter = offFifoMax - offCurrentCmd;
3249	if (offNextCmd >= offFifoMin)
3250	cbBefore = offNextCmd - offFifoMin;
3251	else
3252	{
3253	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3254	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3255	offNextCmd, offFifoMin, offFifoMax));
3256	cbBefore = 0;
3257	}
3258	}
3259	if (cbAfter + cbBefore < cbPayloadReq)
3260	{
3261	/*
3262	* Insufficient, must wait for it to arrive.
3263	*/
3264	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3265	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3266	for (uint32_t i = 0;; i++)
3267	{
3268	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3269	{
3270	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3271	return (void *)(uintptr_t)1;
3272	}
3273	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3274	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3275
3276	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3277
3278	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3279	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3280	if (offNextCmd >= offCurrentCmd)
3281	{
3282	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3283	cbBefore = 0;
3284	}
3285	else
3286	{
3287	cbAfter = offFifoMax - offCurrentCmd;
3288	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3289	}
3290
3291	if (cbAfter + cbBefore >= cbPayloadReq)
3292	break;
3293	}
3294	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3295	}
3296
3297	/*
3298	* Copy out the memory and update what pcbAlreadyRead points to.
3299	*/
3300	if (cbAfter >= cbPayloadReq)
3301	memcpy(pbBounceBuf + cbAlreadyRead,
3302	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3303	cbPayloadReq - cbAlreadyRead);
3304	else
3305	{
3306	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3307	if (cbAlreadyRead < cbAfter)
3308	{
3309	memcpy(pbBounceBuf + cbAlreadyRead,
3310	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3311	cbAfter - cbAlreadyRead);
3312	cbAlreadyRead = cbAfter;
3313	}
3314	memcpy(pbBounceBuf + cbAlreadyRead,
3315	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3316	cbPayloadReq - cbAlreadyRead);
3317	}
3318	*pcbAlreadyRead = cbPayloadReq;
3319	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3320	return pbBounceBuf;
3321	}
3322
3323
3324	/**
3325	* Sends cursor position and visibility information from the FIFO to the front-end.
3326	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3327	*/
3328	static uint32_t
3329	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3330	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3331	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3332	{
3333	/*
3334	* Check if the cursor update counter has changed and try get a stable
3335	* set of values if it has. This is race-prone, especially consindering
3336	* the screen ID, but little we can do about that.
3337	*/
3338	uint32_t x, y, fVisible, idScreen;
3339	for (uint32_t i = 0; ; i++)
3340	{
3341	x = pFIFO[SVGA_FIFO_CURSOR_X];
3342	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3343	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3344	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3345	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3346	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3347	\|\| i > 3)
3348	break;
3349	if (i == 0)
3350	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3351	ASMNopPause();
3352	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3353	}
3354
3355	/*
3356	* Check if anything has changed, as calling into pDrv is not light-weight.
3357	*/
3358	if ( *pxLast == x
3359	&& *pyLast == y
3360	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3361	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3362	else
3363	{
3364	/*
3365	* Detected changes.
3366	*
3367	* We handle global, not per-screen visibility information by sending
3368	* pfnVBVAMousePointerShape without shape data.
3369	*/
3370	*pxLast = x;
3371	*pyLast = y;
3372	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3373	if (idScreen != SVGA_ID_INVALID)
3374	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3375	else if (*pfLastVisible != fVisible)
3376	{
3377	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3378	*pfLastVisible = fVisible;
3379	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3380	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3381	}
3382	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3383	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3384	}
3385
3386	/*
3387	* Update done. Signal this to the guest.
3388	*/
3389	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3390
3391	return uCursorUpdateCount;
3392	}
3393
3394
3395	/**
3396	* Checks if there is work to be done, either cursor updating or FIFO commands.
3397	*
3398	* @returns true if pending work, false if not.
3399	* @param pFIFO The FIFO to examine.
3400	* @param uLastCursorCount The last cursor update counter value.
3401	*/
3402	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3403	{
3404	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3405	return true;
3406
3407	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3408	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3409	return true;
3410
3411	return false;
3412	}
3413
3414
3415	/**
3416	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3417	*
3418	* @param pDevIns The device instance.
3419	* @param pThis The shared VGA/VMSVGA instance data.
3420	* @param pThisCC The VGA/VMSVGA state for ring-3.
3421	*/
3422	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3423	{
3424	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3425	to recheck it before doing the signalling. */
3426	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3427	AssertReturnVoid(pFIFO);
3428	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3429	&& pThis->svga.fFIFOThreadSleeping)
3430	{
3431	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3432	AssertRC(rc);
3433	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3434	}
3435	}
3436
3437
3438	/*
3439	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3440	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3441	*/
3442	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3443	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3444	*
3445	* Will break out of the switch on failure.
3446	* Will restart and quit the loop if the thread was requested to stop.
3447	*
3448	* @param a_PtrVar Request variable pointer.
3449	* @param a_Type Request typedef (not pointer) for casting.
3450	* @param a_cbPayloadReq How much payload to fetch.
3451	* @remarks Accesses a bunch of variables in the current scope!
3452	*/
3453	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3454	if (1) { \
3455	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3456	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3457	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3458	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3459	} else do {} while (0)
3460	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3461	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3462	* buffer after figuring out the actual command size.
3463	*
3464	* Will break out of the switch on failure.
3465	*
3466	* @param a_PtrVar Request variable pointer.
3467	* @param a_Type Request typedef (not pointer) for casting.
3468	* @param a_cbPayloadReq How much payload to fetch.
3469	* @remarks Accesses a bunch of variables in the current scope!
3470	*/
3471	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3472	if (1) { \
3473	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3474	} else do {} while (0)
3475
3476	/**
3477	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3478	*/
3479	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3480	{
3481	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3482	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3483	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3484	int rc;
3485
3486	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3487	return VINF_SUCCESS;
3488
3489	/*
3490	* Special mode where we only execute an external command and the go back
3491	* to being suspended. Currently, all ext cmds ends up here, with the reset
3492	* one also being eligble for runtime execution further down as well.
3493	*/
3494	if (pThis->svga.fFifoExtCommandWakeup)
3495	{
3496	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3497	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3498	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3499	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3500	else
3501	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3502	return VINF_SUCCESS;
3503	}
3504
3505
3506	/*
3507	* Signal the semaphore to make sure we don't wait for 250ms after a
3508	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3509	*/
3510	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3511
3512	/*
3513	* Allocate a bounce buffer for command we get from the FIFO.
3514	* (All code must return via the end of the function to free this buffer.)
3515	*/
3516	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3517	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3518
3519	/*
3520	* Polling/sleep interval config.
3521	*
3522	* We wait for an a short interval if the guest has recently given us work
3523	* to do, but the interval increases the longer we're kept idle. Once we've
3524	* reached the refresh timer interval, we'll switch to extended waits,
3525	* depending on it or the guest to kick us into action when needed.
3526	*
3527	* Should the refresh time go fishing, we'll just continue increasing the
3528	* sleep length till we reaches the 250 ms max after about 16 seconds.
3529	*/
3530	RTMSINTERVAL const cMsMinSleep = 16;
3531	RTMSINTERVAL const cMsIncSleep = 2;
3532	RTMSINTERVAL const cMsMaxSleep = 250;
3533	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3534	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3535
3536	/*
3537	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3538	*
3539	* Initialize with values that will detect an update from the guest.
3540	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3541	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3542	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3543	*/
3544	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3545	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3546	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3547	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3548	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3549
3550	/*
3551	* The FIFO loop.
3552	*/
3553	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3554	bool fBadOrDisabledFifo = false;
3555	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3556	{
3557	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3558	/*
3559	* Should service the run loop every so often.
3560	*/
3561	if (pThis->svga.f3DEnabled)
3562	vmsvga3dCocoaServiceRunLoop();
3563	# endif
3564
3565	/*
3566	* Unless there's already work pending, go to sleep for a short while.
3567	* (See polling/sleep interval config above.)
3568	*/
3569	if ( fBadOrDisabledFifo
3570	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3571	{
3572	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3573	Assert(pThis->cMilliesRefreshInterval > 0);
3574	if (cMsSleep < pThis->cMilliesRefreshInterval)
3575	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3576	else
3577	{
3578	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3579	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3580	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3581	# endif
3582	if ( !fBadOrDisabledFifo
3583	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3584	rc = VINF_SUCCESS;
3585	else
3586	{
3587	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3588	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3589	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3590	}
3591	}
3592	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3593	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3594	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3595	{
3596	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3597	break;
3598	}
3599	}
3600	else
3601	rc = VINF_SUCCESS;
3602	fBadOrDisabledFifo = false;
3603	if (rc == VERR_TIMEOUT)
3604	{
3605	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3606	{
3607	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3608	continue;
3609	}
3610	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3611
3612	Log(("vmsvgaR3FifoLoop: timeout\n"));
3613	}
3614	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3615	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3616	cMsSleep = cMsMinSleep;
3617
3618	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3619	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3620	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3621
3622	/*
3623	* Handle external commands (currently only reset).
3624	*/
3625	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3626	{
3627	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3628	continue;
3629	}
3630
3631	/*
3632	* The device must be enabled and configured.
3633	*/
3634	if ( !pThis->svga.fEnabled
3635	\|\| !pThis->svga.fConfigured)
3636	{
3637	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3638	fBadOrDisabledFifo = true;
3639	cMsSleep = cMsMaxSleep; /* cheat */
3640	continue;
3641	}
3642
3643	/*
3644	* Get and check the min/max values. We ASSUME that they will remain
3645	* unchanged while we process requests. A further ASSUMPTION is that
3646	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3647	* we don't read it back while in the loop.
3648	*/
3649	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3650	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3651	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3652	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3653	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3654	\|\| offFifoMax <= offFifoMin
3655	\|\| offFifoMax > pThis->svga.cbFIFO
3656	\|\| (offFifoMax & 3) != 0
3657	\|\| (offFifoMin & 3) != 0
3658	\|\| offCurrentCmd < offFifoMin
3659	\|\| offCurrentCmd > offFifoMax))
3660	{
3661	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3662	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3663	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3664	fBadOrDisabledFifo = true;
3665	continue;
3666	}
3667	RT_UNTRUSTED_VALIDATED_FENCE();
3668	if (RT_UNLIKELY(offCurrentCmd & 3))
3669	{
3670	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3671	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3672	offCurrentCmd &= ~UINT32_C(3);
3673	}
3674
3675	/*
3676	* Update the cursor position before we start on the FIFO commands.
3677	*/
3678	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3679	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3680	{
3681	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3682	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3683	{ /* halfways likely */ }
3684	else
3685	{
3686	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3687	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3688	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3689	}
3690	}
3691
3692	/*
3693	* Mark the FIFO as busy.
3694	*/
3695	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
3696	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3697	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3698
3699	/*
3700	* Execute all queued FIFO commands.
3701	* Quit if pending external command or changes in the thread state.
3702	*/
3703	bool fDone = false;
3704	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3705	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3706	{
3707	uint32_t cbPayload = 0;
3708	uint32_t u32IrqStatus = 0;
3709
3710	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3711
3712	/* First check any pending actions. */
3713	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3714	{
3715	vmsvgaR3ChangeMode(pThis, pThisCC);
3716	# ifdef VBOX_WITH_VMSVGA3D
3717	if (pThisCC->svga.p3dState != NULL)
3718	vmsvga3dChangeMode(pThisCC);
3719	# endif
3720	}
3721
3722	/* Check for pending external commands (reset). */
3723	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3724	break;
3725
3726	/*
3727	* Process the command.
3728	*/
3729	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3730	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3731	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3732	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3733	switch (enmCmdId)
3734	{
3735	case SVGA_CMD_INVALID_CMD:
3736	/* Nothing to do. */
3737	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3738	break;
3739
3740	case SVGA_CMD_FENCE:
3741	{
3742	SVGAFifoCmdFence *pCmdFence;
3743	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3744	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3745	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3746	{
3747	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3748	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3749
3750	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3751	{
3752	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3753	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3754	}
3755	else
3756	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3757	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3758	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3759	{
3760	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3761	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3762	}
3763	}
3764	else
3765	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3766	break;
3767	}
3768	case SVGA_CMD_UPDATE:
3769	case SVGA_CMD_UPDATE_VERBOSE:
3770	{
3771	SVGAFifoCmdUpdate *pUpdate;
3772	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3773	if (enmCmdId == SVGA_CMD_UPDATE)
3774	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3775	else
3776	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3777	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3778	/** @todo Multiple screens? */
3779	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3780	AssertBreak(pScreen);
3781	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3782	break;
3783	}
3784
3785	case SVGA_CMD_DEFINE_CURSOR:
3786	{
3787	/* Followed by bitmap data. */
3788	SVGAFifoCmdDefineCursor *pCursor;
3789	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3790	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3791
3792	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3793	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3794	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3795	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3796	AssertBreak(pCursor->andMaskDepth <= 32);
3797	AssertBreak(pCursor->xorMaskDepth <= 32);
3798	RT_UNTRUSTED_VALIDATED_FENCE();
3799
3800	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3801	uint32_t cbAndMask = cbAndLine * pCursor->height;
3802	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3803	uint32_t cbXorMask = cbXorLine * pCursor->height;
3804	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3805
3806	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3807	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3808	break;
3809	}
3810
3811	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3812	{
3813	/* Followed by bitmap data. */
3814	uint32_t cbCursorShape, cbAndMask;
3815	uint8_t *pCursorCopy;
3816	uint32_t cbCmd;
3817
3818	SVGAFifoCmdDefineAlphaCursor *pCursor;
3819	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3820	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3821
3822	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3823
3824	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3825	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3826	RT_UNTRUSTED_VALIDATED_FENCE();
3827
3828	/* Refetch the bitmap data as well. */
3829	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3830	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3831	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3832
3833	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3834	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3835	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3836	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3837
3838	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3839	AssertBreak(pCursorCopy);
3840
3841	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3842	memset(pCursorCopy, 0xff, cbAndMask);
3843	/* Colour data */
3844	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3845
3846	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3847	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3848	break;
3849	}
3850
3851	case SVGA_CMD_ESCAPE:
3852	{
3853	/* Followed by nsize bytes of data. */
3854	SVGAFifoCmdEscape *pEscape;
3855	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
3856	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
3857
3858	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
3859	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
3860	RT_UNTRUSTED_VALIDATED_FENCE();
3861	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
3862	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
3863
3864	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
3865	{
3866	AssertBreak(pEscape->size >= sizeof(uint32_t));
3867	RT_UNTRUSTED_VALIDATED_FENCE();
3868	uint32_t cmd = (uint32_t )(pEscape + 1);
3869	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
3870
3871	switch (cmd)
3872	{
3873	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
3874	{
3875	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
3876	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
3877	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
3878
3879	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
3880	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
3881	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
3882
3883	RT_NOREF_PV(pVideoCmd);
3884	break;
3885
3886	}
3887
3888	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
3889	{
3890	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
3891	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
3892	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
3893	RT_NOREF_PV(pVideoCmd);
3894	break;
3895	}
3896
3897	default:
3898	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
3899	break;
3900	}
3901	}
3902	else
3903	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
3904
3905	break;
3906	}
3907	# ifdef VBOX_WITH_VMSVGA3D
3908	case SVGA_CMD_DEFINE_GMR2:
3909	{
3910	SVGAFifoCmdDefineGMR2 *pCmd;
3911	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
3912	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
3913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
3914
3915	/* Validate current GMR id. */
3916	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3917	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3918	RT_UNTRUSTED_VALIDATED_FENCE();
3919
3920	if (!pCmd->numPages)
3921	{
3922	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
3923	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3924	}
3925	else
3926	{
3927	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3928	if (pGMR->cMaxPages)
3929	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
3930
3931	/* Not sure if we should always free the descriptor, but for simplicity
3932	we do so if the new size is smaller than the current. */
3933	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
3934	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
3935	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
3936
3937	pGMR->cMaxPages = pCmd->numPages;
3938	/* The rest is done by the REMAP_GMR2 command. */
3939	}
3940	break;
3941	}
3942
3943	case SVGA_CMD_REMAP_GMR2:
3944	{
3945	/* Followed by page descriptors or guest ptr. */
3946	SVGAFifoCmdRemapGMR2 *pCmd;
3947	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
3948	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
3949
3950	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
3951	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3952	RT_UNTRUSTED_VALIDATED_FENCE();
3953
3954	/* Calculate the size of what comes after next and fetch it. */
3955	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
3956	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3957	cbCmd += sizeof(SVGAGuestPtr);
3958	else
3959	{
3960	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3961	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3962	{
3963	cbCmd += cbPageDesc;
3964	pCmd->numPages = 1;
3965	}
3966	else
3967	{
3968	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
3969	cbCmd += cbPageDesc * pCmd->numPages;
3970	}
3971	}
3972	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
3973
3974	/* Validate current GMR id and size. */
3975	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
3976	RT_UNTRUSTED_VALIDATED_FENCE();
3977	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
3978	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
3979	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
3980	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
3981
3982	if (pCmd->numPages == 0)
3983	break;
3984
3985	/** @todo Move to a separate function vmsvgaGMRRemap() */
3986
3987	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
3988	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
3989
3990	/*
3991	* We flatten the existing descriptors into a page array, overwrite the
3992	* pages specified in this command and then recompress the descriptor.
3993	*/
3994	/** @todo Optimize the GMR remap algorithm! */
3995
3996	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
3997	uint64_t *paNewPage64 = NULL;
3998	if (pGMR->paDesc)
3999	{
4000	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4001
4002	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4003	AssertBreak(paNewPage64);
4004
4005	uint32_t idxPage = 0;
4006	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4007	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4008	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4009	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4010	RT_UNTRUSTED_VALIDATED_FENCE();
4011	}
4012
4013	/* Free the old GMR if present. */
4014	if (pGMR->paDesc)
4015	RTMemFree(pGMR->paDesc);
4016
4017	/* Allocate the maximum amount possible (everything non-continuous) */
4018	PVMSVGAGMRDESCRIPTOR paDescs;
4019	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4020	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4021
4022	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4023	{
4024	/** @todo */
4025	AssertFailed();
4026	pGMR->numDescriptors = 0;
4027	}
4028	else
4029	{
4030	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4031	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4032	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4033
4034	if (paNewPage64)
4035	{
4036	/* Overwrite the old page array with the new page values. */
4037	if (fGCPhys64)
4038	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4039	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4040	else
4041	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4042	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4043
4044	/* Use the updated page array instead of the command data. */
4045	fGCPhys64 = true;
4046	paPages64 = paNewPage64;
4047	pCmd->numPages = cNewTotalPages;
4048	}
4049
4050	/* The first page. */
4051	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4052	* applied to paNewPage64. */
4053	RTGCPHYS GCPhys;
4054	if (fGCPhys64)
4055	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4056	else
4057	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4058	paDescs[0].GCPhys = GCPhys;
4059	paDescs[0].numPages = 1;
4060
4061	/* Subsequent pages. */
4062	uint32_t iDescriptor = 0;
4063	for (uint32_t i = 1; i < pCmd->numPages; i++)
4064	{
4065	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4066	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4067	else
4068	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4069
4070	/* Continuous physical memory? */
4071	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4072	{
4073	Assert(paDescs[iDescriptor].numPages);
4074	paDescs[iDescriptor].numPages++;
4075	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4076	}
4077	else
4078	{
4079	iDescriptor++;
4080	paDescs[iDescriptor].GCPhys = GCPhys;
4081	paDescs[iDescriptor].numPages = 1;
4082	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4083	}
4084	}
4085
4086	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4087	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4088	pGMR->numDescriptors = iDescriptor + 1;
4089	}
4090
4091	if (paNewPage64)
4092	RTMemFree(paNewPage64);
4093
4094	# ifdef DEBUG_GMR_ACCESS
4095	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4096	# endif
4097	break;
4098	}
4099	# endif // VBOX_WITH_VMSVGA3D
4100	case SVGA_CMD_DEFINE_SCREEN:
4101	{
4102	/* The size of this command is specified by the guest and depends on capabilities. */
4103	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4104
4105	SVGAFifoCmdDefineScreen *pCmd;
4106	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4107	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4108	RT_UNTRUSTED_VALIDATED_FENCE();
4109
4110	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4111	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4112	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4113
4114	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4115	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4116	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4117
4118	uint32_t const idScreen = pCmd->screen.id;
4119	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4120
4121	uint32_t const uWidth = pCmd->screen.size.width;
4122	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4123
4124	uint32_t const uHeight = pCmd->screen.size.height;
4125	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4126
4127	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4128	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4129	AssertBreak(cbWidth <= cbPitch);
4130
4131	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4132	AssertBreak(uScreenOffset < pThis->vram_size);
4133
4134	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4135	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4136	AssertBreak( (uHeight == 0 && cbPitch == 0)
4137	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4138	RT_UNTRUSTED_VALIDATED_FENCE();
4139
4140	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4141
4142	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4143
4144	pScreen->fDefined = true;
4145	pScreen->fModified = true;
4146	pScreen->fuScreen = pCmd->screen.flags;
4147	pScreen->idScreen = idScreen;
4148	if (!fBlank)
4149	{
4150	AssertBreak(uWidth > 0 && uHeight > 0);
4151
4152	pScreen->xOrigin = pCmd->screen.root.x;
4153	pScreen->yOrigin = pCmd->screen.root.y;
4154	pScreen->cWidth = uWidth;
4155	pScreen->cHeight = uHeight;
4156	pScreen->offVRAM = uScreenOffset;
4157	pScreen->cbPitch = cbPitch;
4158	pScreen->cBpp = 32;
4159	}
4160	else
4161	{
4162	/* Keep old values. */
4163	}
4164
4165	pThis->svga.fGFBRegisters = false;
4166	vmsvgaR3ChangeMode(pThis, pThisCC);
4167	break;
4168	}
4169
4170	case SVGA_CMD_DESTROY_SCREEN:
4171	{
4172	SVGAFifoCmdDestroyScreen *pCmd;
4173	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4174	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4175
4176	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4177
4178	uint32_t const idScreen = pCmd->screenId;
4179	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4180	RT_UNTRUSTED_VALIDATED_FENCE();
4181
4182	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4183	pScreen->fModified = true;
4184	pScreen->fDefined = false;
4185	pScreen->idScreen = idScreen;
4186
4187	vmsvgaR3ChangeMode(pThis, pThisCC);
4188	break;
4189	}
4190
4191	case SVGA_CMD_DEFINE_GMRFB:
4192	{
4193	SVGAFifoCmdDefineGMRFB *pCmd;
4194	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4195	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4196
4197	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4198	pSVGAState->GMRFB.ptr = pCmd->ptr;
4199	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4200	pSVGAState->GMRFB.format = pCmd->format;
4201	break;
4202	}
4203
4204	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4205	{
4206	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4207	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4208	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4209
4210	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4211	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4212
4213	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4214	RT_UNTRUSTED_VALIDATED_FENCE();
4215
4216	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4217	AssertBreak(pScreen);
4218
4219	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4220	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4221
4222	/* Clip destRect to the screen dimensions. */
4223	SVGASignedRect screenRect;
4224	screenRect.left = 0;
4225	screenRect.top = 0;
4226	screenRect.right = pScreen->cWidth;
4227	screenRect.bottom = pScreen->cHeight;
4228	SVGASignedRect clipRect = pCmd->destRect;
4229	vmsvgaR3ClipRect(&screenRect, &clipRect);
4230	RT_UNTRUSTED_VALIDATED_FENCE();
4231
4232	uint32_t const width = clipRect.right - clipRect.left;
4233	uint32_t const height = clipRect.bottom - clipRect.top;
4234
4235	if ( width == 0
4236	\|\| height == 0)
4237	break; /* Nothing to do. */
4238
4239	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4240	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4241
4242	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4243	* Prepare parameters for vmsvgaR3GmrTransfer.
4244	*/
4245	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4246
4247	/* Destination: host buffer which describes the screen 0 VRAM.
4248	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4249	*/
4250	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4251	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4252	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4253	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4254	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4255	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4256	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4257	+ cbScanline * clipRect.top;
4258	int32_t const cbHstPitch = cbScanline;
4259
4260	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4261	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4262	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4263	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4264	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4265
4266	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4267	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4268	gstPtr, offGst, cbGstPitch,
4269	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4270	AssertRC(rc);
4271	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4272	break;
4273	}
4274
4275	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4276	{
4277	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4278	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4279	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4280
4281	/* Note! This can fetch 3d render results as well!! */
4282	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4283	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4284
4285	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4286	RT_UNTRUSTED_VALIDATED_FENCE();
4287
4288	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4289	AssertBreak(pScreen);
4290
4291	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4292	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4293
4294	/* Clip destRect to the screen dimensions. */
4295	SVGASignedRect screenRect;
4296	screenRect.left = 0;
4297	screenRect.top = 0;
4298	screenRect.right = pScreen->cWidth;
4299	screenRect.bottom = pScreen->cHeight;
4300	SVGASignedRect clipRect = pCmd->srcRect;
4301	vmsvgaR3ClipRect(&screenRect, &clipRect);
4302	RT_UNTRUSTED_VALIDATED_FENCE();
4303
4304	uint32_t const width = clipRect.right - clipRect.left;
4305	uint32_t const height = clipRect.bottom - clipRect.top;
4306
4307	if ( width == 0
4308	\|\| height == 0)
4309	break; /* Nothing to do. */
4310
4311	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4312	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4313
4314	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4315	* Prepare parameters for vmsvgaR3GmrTransfer.
4316	*/
4317	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4318
4319	/* Source: host buffer which describes the screen 0 VRAM.
4320	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4321	*/
4322	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4323	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4324	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4325	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4326	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4327	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4328	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4329	+ cbScanline * clipRect.top;
4330	int32_t const cbHstPitch = cbScanline;
4331
4332	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4333	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4334	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4335	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4336	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4337
4338	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4339	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4340	gstPtr, offGst, cbGstPitch,
4341	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4342	AssertRC(rc);
4343	break;
4344	}
4345
4346	case SVGA_CMD_ANNOTATION_FILL:
4347	{
4348	SVGAFifoCmdAnnotationFill *pCmd;
4349	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4350	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4351
4352	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4353	pSVGAState->colorAnnotation = pCmd->color;
4354	break;
4355	}
4356
4357	case SVGA_CMD_ANNOTATION_COPY:
4358	{
4359	SVGAFifoCmdAnnotationCopy *pCmd;
4360	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4361	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4362
4363	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4364	AssertFailed();
4365	break;
4366	}
4367
4368	/** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
4369
4370	default:
4371	# ifdef VBOX_WITH_VMSVGA3D
4372	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4373	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4374	{
4375	RT_UNTRUSTED_VALIDATED_FENCE();
4376
4377	/* All 3d commands start with a common header, which defines the size of the command. */
4378	SVGA3dCmdHeader *pHdr;
4379	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4380	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4381	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4382	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4383
4384	if (RT_LIKELY(pThis->svga.f3DEnabled))
4385	{ /* likely */ }
4386	else
4387	{
4388	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4389	break;
4390	}
4391
4392	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4393	* Check that the 3D command has at least a_cbMin of payload bytes after the
4394	* header. Will break out of the switch if it doesn't.
4395	*/
4396	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4397	if (1) { \
4398	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4399	RT_UNTRUSTED_VALIDATED_FENCE(); \
4400	} else do {} while (0)
4401	switch ((int)enmCmdId)
4402	{
4403	case SVGA_3D_CMD_SURFACE_DEFINE:
4404	{
4405	uint32_t cMipLevels;
4406	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4407	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4408	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4409
4410	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4411	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4412	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4413	# ifdef DEBUG_GMR_ACCESS
4414	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4415	# endif
4416	break;
4417	}
4418
4419	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4420	{
4421	uint32_t cMipLevels;
4422	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4423	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4424	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4425
4426	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4427	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4428	pCmd->multisampleCount, pCmd->autogenFilter,
4429	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4430	break;
4431	}
4432
4433	case SVGA_3D_CMD_SURFACE_DESTROY:
4434	{
4435	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4436	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4437	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4438	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4439	break;
4440	}
4441
4442	case SVGA_3D_CMD_SURFACE_COPY:
4443	{
4444	uint32_t cCopyBoxes;
4445	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4446	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4448
4449	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4450	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4451	break;
4452	}
4453
4454	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4455	{
4456	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4457	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4459
4460	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4461	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4462	break;
4463	}
4464
4465	case SVGA_3D_CMD_SURFACE_DMA:
4466	{
4467	uint32_t cCopyBoxes;
4468	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4469	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4470	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4471
4472	uint64_t u64NanoTS = 0;
4473	if (LogRelIs3Enabled())
4474	u64NanoTS = RTTimeNanoTS();
4475	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4476	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4477	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4478	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4479	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4480	if (LogRelIs3Enabled())
4481	{
4482	if (cCopyBoxes)
4483	{
4484	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4485	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4486	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4487	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4488	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4489	}
4490	}
4491	break;
4492	}
4493
4494	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4495	{
4496	uint32_t cRects;
4497	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4498	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4499	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4500
4501	uint64_t u64NanoTS = 0;
4502	if (LogRelIs3Enabled())
4503	u64NanoTS = RTTimeNanoTS();
4504	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4505	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4506	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4507	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4508	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4509	if (LogRelIs3Enabled())
4510	{
4511	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4512	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4513	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4514	pFirstRect->left, pFirstRect->top,
4515	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4516	}
4517	break;
4518	}
4519
4520	case SVGA_3D_CMD_CONTEXT_DEFINE:
4521	{
4522	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4523	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4524	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4525
4526	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4527	break;
4528	}
4529
4530	case SVGA_3D_CMD_CONTEXT_DESTROY:
4531	{
4532	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4533	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4534	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4535
4536	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4537	break;
4538	}
4539
4540	case SVGA_3D_CMD_SETTRANSFORM:
4541	{
4542	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4543	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4544	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4545
4546	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4547	break;
4548	}
4549
4550	case SVGA_3D_CMD_SETZRANGE:
4551	{
4552	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4553	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4554	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4555
4556	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4557	break;
4558	}
4559
4560	case SVGA_3D_CMD_SETRENDERSTATE:
4561	{
4562	uint32_t cRenderStates;
4563	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4564	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4565	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4566
4567	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4568	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4569	break;
4570	}
4571
4572	case SVGA_3D_CMD_SETRENDERTARGET:
4573	{
4574	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4575	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4576	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4577
4578	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4579	break;
4580	}
4581
4582	case SVGA_3D_CMD_SETTEXTURESTATE:
4583	{
4584	uint32_t cTextureStates;
4585	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4586	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4587	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4588
4589	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4590	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4591	break;
4592	}
4593
4594	case SVGA_3D_CMD_SETMATERIAL:
4595	{
4596	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4597	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4598	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4599
4600	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4601	break;
4602	}
4603
4604	case SVGA_3D_CMD_SETLIGHTDATA:
4605	{
4606	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4607	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4608	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4609
4610	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4611	break;
4612	}
4613
4614	case SVGA_3D_CMD_SETLIGHTENABLED:
4615	{
4616	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4617	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4618	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4619
4620	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4621	break;
4622	}
4623
4624	case SVGA_3D_CMD_SETVIEWPORT:
4625	{
4626	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4627	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4628	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4629
4630	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4631	break;
4632	}
4633
4634	case SVGA_3D_CMD_SETCLIPPLANE:
4635	{
4636	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4637	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4638	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4639
4640	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4641	break;
4642	}
4643
4644	case SVGA_3D_CMD_CLEAR:
4645	{
4646	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4647	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4648	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4649
4650	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4651	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4652	break;
4653	}
4654
4655	case SVGA_3D_CMD_PRESENT:
4656	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4657	{
4658	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4659	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4660	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4661	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4662	else
4663	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4664
4665	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4666
4667	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4668	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4669	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4670	break;
4671	}
4672
4673	case SVGA_3D_CMD_SHADER_DEFINE:
4674	{
4675	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4676	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4677	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4678
4679	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4680	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4681	break;
4682	}
4683
4684	case SVGA_3D_CMD_SHADER_DESTROY:
4685	{
4686	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4687	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4688	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4689
4690	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4691	break;
4692	}
4693
4694	case SVGA_3D_CMD_SET_SHADER:
4695	{
4696	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4697	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4698	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4699
4700	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_SET_SHADER_CONST:
4705	{
4706	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4709
4710	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4711	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4712	break;
4713	}
4714
4715	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4716	{
4717	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4718	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4719	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4720
4721	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4722	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4723	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4724	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4725	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4726
4727	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4728	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4729
4730	RT_UNTRUSTED_VALIDATED_FENCE();
4731
4732	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4733	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4734	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4735
4736	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4737	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4738	pNumRange, cVertexDivisor, pVertexDivisor);
4739	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4740	break;
4741	}
4742
4743	case SVGA_3D_CMD_SETSCISSORRECT:
4744	{
4745	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4746	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4748
4749	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4750	break;
4751	}
4752
4753	case SVGA_3D_CMD_BEGIN_QUERY:
4754	{
4755	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
4756	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4757	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
4758
4759	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
4760	break;
4761	}
4762
4763	case SVGA_3D_CMD_END_QUERY:
4764	{
4765	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
4766	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4767	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
4768
4769	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4770	break;
4771	}
4772
4773	case SVGA_3D_CMD_WAIT_FOR_QUERY:
4774	{
4775	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
4776	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4777	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
4778
4779	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
4780	break;
4781	}
4782
4783	case SVGA_3D_CMD_GENERATE_MIPMAPS:
4784	{
4785	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
4786	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4787	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
4788
4789	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
4790	break;
4791	}
4792
4793	case SVGA_3D_CMD_ACTIVATE_SURFACE:
4794	/* context id + surface id? */
4795	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
4796	break;
4797	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
4798	/* context id + surface id? */
4799	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
4800	break;
4801
4802	default:
4803	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4804	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4805	break;
4806	}
4807	}
4808	else
4809	# endif // VBOX_WITH_VMSVGA3D
4810	{
4811	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4812	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4813	}
4814	}
4815
4816	/* Go to the next slot */
4817	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4818	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4819	if (offCurrentCmd >= offFifoMax)
4820	{
4821	offCurrentCmd -= offFifoMax - offFifoMin;
4822	Assert(offCurrentCmd >= offFifoMin);
4823	Assert(offCurrentCmd < offFifoMax);
4824	}
4825	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4826	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4827
4828	/*
4829	* Raise IRQ if required. Must enter the critical section here
4830	* before making final decisions here, otherwise cubebench and
4831	* others may end up waiting forever.
4832	*/
4833	if ( u32IrqStatus
4834	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4835	{
4836	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4837	AssertRC(rc2);
4838
4839	/* FIFO progress might trigger an interrupt. */
4840	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
4841	{
4842	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
4843	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
4844	}
4845
4846	/* Unmasked IRQ pending? */
4847	if (pThis->svga.u32IrqMask & u32IrqStatus)
4848	{
4849	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
4850	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
4851	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
4852	}
4853
4854	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4855	}
4856	}
4857
4858	/* If really done, clear the busy flag. */
4859	if (fDone)
4860	{
4861	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
4862	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4863	}
4864	}
4865
4866	/*
4867	* Free the bounce buffer. (There are no returns above!)
4868	*/
4869	RTMemFree(pbBounceBuf);
4870
4871	return VINF_SUCCESS;
4872	}
4873
4874	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4875	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4876	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4877
4878	#ifdef VBOX_WITH_VMSVGA3D
4879	/**
4880	* Free the specified GMR
4881	*
4882	* @param pThisCC The VGA/VMSVGA state for ring-3.
4883	* @param idGMR GMR id
4884	*/
4885	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
4886	{
4887	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4888
4889	/* Free the old descriptor if present. */
4890	PGMR pGMR = &pSVGAState->paGMR[idGMR];
4891	if ( pGMR->numDescriptors
4892	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
4893	{
4894	# ifdef DEBUG_GMR_ACCESS
4895	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
4896	# endif
4897
4898	Assert(pGMR->paDesc);
4899	RTMemFree(pGMR->paDesc);
4900	pGMR->paDesc = NULL;
4901	pGMR->numDescriptors = 0;
4902	pGMR->cbTotal = 0;
4903	pGMR->cMaxPages = 0;
4904	}
4905	Assert(!pGMR->cMaxPages);
4906	Assert(!pGMR->cbTotal);
4907	}
4908	#endif /* VBOX_WITH_VMSVGA3D */
4909
4910	/**
4911	* Copy between a GMR and a host memory buffer.
4912	*
4913	* @returns VBox status code.
4914	* @param pThis The shared VGA/VMSVGA instance data.
4915	* @param pThisCC The VGA/VMSVGA state for ring-3.
4916	* @param enmTransferType Transfer type (read/write)
4917	* @param pbHstBuf Host buffer pointer (valid)
4918	* @param cbHstBuf Size of host buffer (valid)
4919	* @param offHst Host buffer offset of the first scanline
4920	* @param cbHstPitch Destination buffer pitch
4921	* @param gstPtr GMR description
4922	* @param offGst Guest buffer offset of the first scanline
4923	* @param cbGstPitch Guest buffer pitch
4924	* @param cbWidth Width in bytes to copy
4925	* @param cHeight Number of scanllines to copy
4926	*/
4927	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
4928	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
4929	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
4930	uint32_t cbWidth, uint32_t cHeight)
4931	{
4932	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4933	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
4934	int rc;
4935
4936	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
4937	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
4938	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4939	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
4940	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
4941
4942	PGMR pGMR;
4943	uint32_t cbGmr; /* The GMR size in bytes. */
4944	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
4945	{
4946	pGMR = NULL;
4947	cbGmr = pThis->vram_size;
4948	}
4949	else
4950	{
4951	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
4952	RT_UNTRUSTED_VALIDATED_FENCE();
4953	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
4954	cbGmr = pGMR->cbTotal;
4955	}
4956
4957	/*
4958	* GMR
4959	*/
4960	/* Calculate GMR offset of the data to be copied. */
4961	AssertMsgReturn(gstPtr.offset < cbGmr,
4962	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4963	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4964	VERR_INVALID_PARAMETER);
4965	RT_UNTRUSTED_VALIDATED_FENCE();
4966	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
4967	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4968	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4969	VERR_INVALID_PARAMETER);
4970	RT_UNTRUSTED_VALIDATED_FENCE();
4971	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
4972
4973	/* Verify that cbWidth is less than scanline and fits into the GMR. */
4974	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
4975	AssertMsgReturn(cbGmrScanline != 0,
4976	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4977	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4978	VERR_INVALID_PARAMETER);
4979	RT_UNTRUSTED_VALIDATED_FENCE();
4980	AssertMsgReturn(cbWidth <= cbGmrScanline,
4981	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4982	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4983	VERR_INVALID_PARAMETER);
4984	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
4985	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
4986	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
4987	VERR_INVALID_PARAMETER);
4988	RT_UNTRUSTED_VALIDATED_FENCE();
4989
4990	/* How many bytes are available for the data in the GMR. */
4991	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
4992
4993	/* How many scanlines would fit into the available data. */
4994	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
4995	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
4996	if (cbWidth <= cbGmrLastScanline)
4997	++cGmrScanlines;
4998
4999	if (cHeight > cGmrScanlines)
5000	cHeight = cGmrScanlines;
5001
5002	AssertMsgReturn(cHeight > 0,
5003	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5004	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5005	VERR_INVALID_PARAMETER);
5006	RT_UNTRUSTED_VALIDATED_FENCE();
5007
5008	/*
5009	* Host buffer.
5010	*/
5011	AssertMsgReturn(offHst < cbHstBuf,
5012	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5013	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5014	VERR_INVALID_PARAMETER);
5015
5016	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5017	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5018	AssertMsgReturn(cbHstScanline != 0,
5019	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5020	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5021	VERR_INVALID_PARAMETER);
5022	AssertMsgReturn(cbWidth <= cbHstScanline,
5023	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5024	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5025	VERR_INVALID_PARAMETER);
5026	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5027	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5028	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5029	VERR_INVALID_PARAMETER);
5030
5031	/* How many bytes are available for the data in the buffer. */
5032	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5033
5034	/* How many scanlines would fit into the available data. */
5035	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5036	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5037	if (cbWidth <= cbHstLastScanline)
5038	++cHstScanlines;
5039
5040	if (cHeight > cHstScanlines)
5041	cHeight = cHstScanlines;
5042
5043	AssertMsgReturn(cHeight > 0,
5044	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5045	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5046	VERR_INVALID_PARAMETER);
5047
5048	uint8_t *pbHst = pbHstBuf + offHst;
5049
5050	/* Shortcut for the framebuffer. */
5051	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5052	{
5053	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5054
5055	uint8_t const *pbSrc;
5056	int32_t cbSrcPitch;
5057	uint8_t *pbDst;
5058	int32_t cbDstPitch;
5059
5060	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5061	{
5062	pbSrc = pbHst;
5063	cbSrcPitch = cbHstPitch;
5064	pbDst = pbGst;
5065	cbDstPitch = cbGstPitch;
5066	}
5067	else
5068	{
5069	pbSrc = pbGst;
5070	cbSrcPitch = cbGstPitch;
5071	pbDst = pbHst;
5072	cbDstPitch = cbHstPitch;
5073	}
5074
5075	if ( cbWidth == (uint32_t)cbGstPitch
5076	&& cbGstPitch == cbHstPitch)
5077	{
5078	/* Entire scanlines, positive pitch. */
5079	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5080	}
5081	else
5082	{
5083	for (uint32_t i = 0; i < cHeight; ++i)
5084	{
5085	memcpy(pbDst, pbSrc, cbWidth);
5086
5087	pbDst += cbDstPitch;
5088	pbSrc += cbSrcPitch;
5089	}
5090	}
5091	return VINF_SUCCESS;
5092	}
5093
5094	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5095	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5096
5097	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5098	uint32_t iDesc = 0; /* Index in the descriptor array. */
5099	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5100	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5101	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5102	for (uint32_t i = 0; i < cHeight; ++i)
5103	{
5104	uint32_t cbCurrentWidth = cbWidth;
5105	uint32_t offGmrCurrent = offGmrScanline;
5106	uint8_t *pbCurrentHost = pbHstScanline;
5107
5108	/* Find the right descriptor */
5109	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5110	{
5111	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5112	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5113	++iDesc;
5114	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5115	}
5116
5117	while (cbCurrentWidth)
5118	{
5119	uint32_t cbToCopy;
5120
5121	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5122	{
5123	cbToCopy = cbCurrentWidth;
5124	}
5125	else
5126	{
5127	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5128	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5129	}
5130
5131	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5132
5133	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5134
5135	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5136	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5137	else
5138	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5139	AssertRCBreak(rc);
5140
5141	cbCurrentWidth -= cbToCopy;
5142	offGmrCurrent += cbToCopy;
5143	pbCurrentHost += cbToCopy;
5144
5145	/* Go to the next descriptor if there's anything left. */
5146	if (cbCurrentWidth)
5147	{
5148	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5149	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5150	++iDesc;
5151	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5152	}
5153	}
5154
5155	offGmrScanline += cbGstPitch;
5156	pbHstScanline += cbHstPitch;
5157	}
5158
5159	return VINF_SUCCESS;
5160	}
5161
5162
5163	/**
5164	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5165	*
5166	* @param pSizeSrc Source surface dimensions.
5167	* @param pSizeDest Destination surface dimensions.
5168	* @param pBox Coordinates to be clipped.
5169	*/
5170	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5171	{
5172	/* Src x, w */
5173	if (pBox->srcx > pSizeSrc->width)
5174	pBox->srcx = pSizeSrc->width;
5175	if (pBox->w > pSizeSrc->width - pBox->srcx)
5176	pBox->w = pSizeSrc->width - pBox->srcx;
5177
5178	/* Src y, h */
5179	if (pBox->srcy > pSizeSrc->height)
5180	pBox->srcy = pSizeSrc->height;
5181	if (pBox->h > pSizeSrc->height - pBox->srcy)
5182	pBox->h = pSizeSrc->height - pBox->srcy;
5183
5184	/* Src z, d */
5185	if (pBox->srcz > pSizeSrc->depth)
5186	pBox->srcz = pSizeSrc->depth;
5187	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5188	pBox->d = pSizeSrc->depth - pBox->srcz;
5189
5190	/* Dest x, w */
5191	if (pBox->x > pSizeDest->width)
5192	pBox->x = pSizeDest->width;
5193	if (pBox->w > pSizeDest->width - pBox->x)
5194	pBox->w = pSizeDest->width - pBox->x;
5195
5196	/* Dest y, h */
5197	if (pBox->y > pSizeDest->height)
5198	pBox->y = pSizeDest->height;
5199	if (pBox->h > pSizeDest->height - pBox->y)
5200	pBox->h = pSizeDest->height - pBox->y;
5201
5202	/* Dest z, d */
5203	if (pBox->z > pSizeDest->depth)
5204	pBox->z = pSizeDest->depth;
5205	if (pBox->d > pSizeDest->depth - pBox->z)
5206	pBox->d = pSizeDest->depth - pBox->z;
5207	}
5208
5209	/**
5210	* Unsigned coordinates in pBox. Clip to [0; pSize).
5211	*
5212	* @param pSize Source surface dimensions.
5213	* @param pBox Coordinates to be clipped.
5214	*/
5215	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5216	{
5217	/* x, w */
5218	if (pBox->x > pSize->width)
5219	pBox->x = pSize->width;
5220	if (pBox->w > pSize->width - pBox->x)
5221	pBox->w = pSize->width - pBox->x;
5222
5223	/* y, h */
5224	if (pBox->y > pSize->height)
5225	pBox->y = pSize->height;
5226	if (pBox->h > pSize->height - pBox->y)
5227	pBox->h = pSize->height - pBox->y;
5228
5229	/* z, d */
5230	if (pBox->z > pSize->depth)
5231	pBox->z = pSize->depth;
5232	if (pBox->d > pSize->depth - pBox->z)
5233	pBox->d = pSize->depth - pBox->z;
5234	}
5235
5236	/**
5237	* Clip.
5238	*
5239	* @param pBound Bounding rectangle.
5240	* @param pRect Rectangle to be clipped.
5241	*/
5242	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5243	{
5244	int32_t left;
5245	int32_t top;
5246	int32_t right;
5247	int32_t bottom;
5248
5249	/* Right order. */
5250	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5251	if (pRect->left < pRect->right)
5252	{
5253	left = pRect->left;
5254	right = pRect->right;
5255	}
5256	else
5257	{
5258	left = pRect->right;
5259	right = pRect->left;
5260	}
5261	if (pRect->top < pRect->bottom)
5262	{
5263	top = pRect->top;
5264	bottom = pRect->bottom;
5265	}
5266	else
5267	{
5268	top = pRect->bottom;
5269	bottom = pRect->top;
5270	}
5271
5272	if (left < pBound->left)
5273	left = pBound->left;
5274	if (right < pBound->left)
5275	right = pBound->left;
5276
5277	if (left > pBound->right)
5278	left = pBound->right;
5279	if (right > pBound->right)
5280	right = pBound->right;
5281
5282	if (top < pBound->top)
5283	top = pBound->top;
5284	if (bottom < pBound->top)
5285	bottom = pBound->top;
5286
5287	if (top > pBound->bottom)
5288	top = pBound->bottom;
5289	if (bottom > pBound->bottom)
5290	bottom = pBound->bottom;
5291
5292	pRect->left = left;
5293	pRect->right = right;
5294	pRect->top = top;
5295	pRect->bottom = bottom;
5296	}
5297
5298	/**
5299	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5300	* Unblock the FIFO I/O thread so it can respond to a state change.}
5301	*/
5302	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5303	{
5304	RT_NOREF(pDevIns);
5305	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5306	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5307	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5308	}
5309
5310	/**
5311	* Enables or disables dirty page tracking for the framebuffer
5312	*
5313	* @param pDevIns The device instance.
5314	* @param pThis The shared VGA/VMSVGA instance data.
5315	* @param fTraces Enable/disable traces
5316	*/
5317	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5318	{
5319	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5320	&& !fTraces)
5321	{
5322	//Assert(pThis->svga.fTraces);
5323	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5324	return;
5325	}
5326
5327	pThis->svga.fTraces = fTraces;
5328	if (pThis->svga.fTraces)
5329	{
5330	unsigned cbFrameBuffer = pThis->vram_size;
5331
5332	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5333	/** @todo How does this work with screens? */
5334	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5335	{
5336	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5337	Assert(pThis->svga.cbScanline);
5338	# endif
5339	/* Hardware enabled; return real framebuffer size .*/
5340	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5341	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5342	}
5343
5344	if (!pThis->svga.fVRAMTracking)
5345	{
5346	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5347	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5348	pThis->svga.fVRAMTracking = true;
5349	}
5350	}
5351	else
5352	{
5353	if (pThis->svga.fVRAMTracking)
5354	{
5355	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5356	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5357	pThis->svga.fVRAMTracking = false;
5358	}
5359	}
5360	}
5361
5362	/**
5363	* @callback_method_impl{FNPCIIOREGIONMAP}
5364	*/
5365	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5366	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5367	{
5368	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5369	int rc;
5370	RT_NOREF(pPciDev);
5371	Assert(pPciDev == pDevIns->apPciDevs[0]);
5372
5373	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5374	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5375	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5376	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5377	, VERR_INTERNAL_ERROR);
5378	if (GCPhysAddress != NIL_RTGCPHYS)
5379	{
5380	/*
5381	* Mapping the FIFO RAM.
5382	*/
5383	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5384	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5385	AssertRC(rc);
5386
5387	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5388	if (RT_SUCCESS(rc))
5389	{
5390	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5391	# ifdef DEBUG_FIFO_ACCESS
5392	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5393	# else
5394	GCPhysAddress + PAGE_SIZE - 1,
5395	# endif
5396	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5397	"VMSVGA FIFO");
5398	AssertRC(rc);
5399	}
5400	# endif
5401	if (RT_SUCCESS(rc))
5402	{
5403	pThis->svga.GCPhysFIFO = GCPhysAddress;
5404	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5405	}
5406	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5407	}
5408	else
5409	{
5410	Assert(pThis->svga.GCPhysFIFO);
5411	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5412	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5413	AssertRC(rc);
5414	# else
5415	rc = VINF_SUCCESS;
5416	# endif
5417	pThis->svga.GCPhysFIFO = 0;
5418	}
5419	return rc;
5420	}
5421
5422	# ifdef VBOX_WITH_VMSVGA3D
5423
5424	/**
5425	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5426	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5427	*
5428	* @param pDevIns The device instance.
5429	* @param pThis The The shared VGA/VMSVGA instance data.
5430	* @param pThisCC The VGA/VMSVGA state for ring-3.
5431	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5432	* UINT32_MAX is used, all surfaces are processed.
5433	*/
5434	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5435	{
5436	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5437	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5438	}
5439
5440
5441	/**
5442	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5443	*/
5444	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5445	{
5446	/* There might be a specific surface ID at the start of the
5447	arguments, if not show all surfaces. */
5448	uint32_t sid = UINT32_MAX;
5449	if (pszArgs)
5450	pszArgs = RTStrStripL(pszArgs);
5451	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5452	sid = RTStrToUInt32(pszArgs);
5453
5454	/* Verbose or terse display, we default to verbose. */
5455	bool fVerbose = true;
5456	if (RTStrIStr(pszArgs, "terse"))
5457	fVerbose = false;
5458
5459	/* The size of the ascii art (x direction, y is 3/4 of x). */
5460	uint32_t cxAscii = 80;
5461	if (RTStrIStr(pszArgs, "gigantic"))
5462	cxAscii = 300;
5463	else if (RTStrIStr(pszArgs, "huge"))
5464	cxAscii = 180;
5465	else if (RTStrIStr(pszArgs, "big"))
5466	cxAscii = 132;
5467	else if (RTStrIStr(pszArgs, "normal"))
5468	cxAscii = 80;
5469	else if (RTStrIStr(pszArgs, "medium"))
5470	cxAscii = 64;
5471	else if (RTStrIStr(pszArgs, "small"))
5472	cxAscii = 48;
5473	else if (RTStrIStr(pszArgs, "tiny"))
5474	cxAscii = 24;
5475
5476	/* Y invert the image when producing the ASCII art. */
5477	bool fInvY = false;
5478	if (RTStrIStr(pszArgs, "invy"))
5479	fInvY = true;
5480
5481	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5482	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5483	}
5484
5485
5486	/**
5487	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5488	*/
5489	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5490	{
5491	/* pszArg = "sid[>dir]"
5492	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5493	*/
5494	char *pszBitmapPath = NULL;
5495	uint32_t sid = UINT32_MAX;
5496	if (pszArgs)
5497	pszArgs = RTStrStripL(pszArgs);
5498	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5499	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5500	if ( pszBitmapPath
5501	&& *pszBitmapPath == '>')
5502	++pszBitmapPath;
5503
5504	const bool fVerbose = true;
5505	const uint32_t cxAscii = 0; /* No ASCII */
5506	const bool fInvY = false; /* Do not invert. */
5507	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5508	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5509	}
5510
5511	/**
5512	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5513	*/
5514	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5515	{
5516	/* There might be a specific surface ID at the start of the
5517	arguments, if not show all contexts. */
5518	uint32_t sid = UINT32_MAX;
5519	if (pszArgs)
5520	pszArgs = RTStrStripL(pszArgs);
5521	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5522	sid = RTStrToUInt32(pszArgs);
5523
5524	/* Verbose or terse display, we default to verbose. */
5525	bool fVerbose = true;
5526	if (RTStrIStr(pszArgs, "terse"))
5527	fVerbose = false;
5528
5529	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5530	}
5531	# endif /* VBOX_WITH_VMSVGA3D */
5532
5533	/**
5534	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5535	*/
5536	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5537	{
5538	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5539	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5540	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5541	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5542	RT_NOREF(pszArgs);
5543
5544	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5545	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5546	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5547	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5548	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5549	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5550	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5551	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5552	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5553	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5554	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5555	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5556	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5557	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5558	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5559	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5560	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5561	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5562	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5563	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5564	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5565	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5566	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5567	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5568	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5569
5570	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5571	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5572	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5573	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5574
5575	# ifdef VBOX_WITH_VMSVGA3D
5576	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5577	# endif
5578	if (pThisCC->pDrv)
5579	{
5580	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5581	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5582	}
5583
5584	/* Dump screen information. */
5585	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5586	{
5587	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5588	if (pScreen)
5589	{
5590	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5591	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5592	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5593	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5594	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5595	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5596	{
5597	pHlp->pfnPrintf(pHlp, " (");
5598	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5599	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5600	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5601	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5602	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5603	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5604	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5605	pHlp->pfnPrintf(pHlp, " BLANKING");
5606	pHlp->pfnPrintf(pHlp, " )");
5607	}
5608	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5609	}
5610	}
5611
5612	}
5613
5614	/**
5615	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5616	*/
5617	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5618	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5619	{
5620	RT_NOREF(uPass);
5621
5622	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5623	int rc;
5624
5625	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5626	{
5627	uint32_t cScreens = 0;
5628	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5629	AssertRCReturn(rc, rc);
5630	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5631	("cScreens=%#x\n", cScreens),
5632	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5633
5634	for (uint32_t i = 0; i < cScreens; ++i)
5635	{
5636	VMSVGASCREENOBJECT screen;
5637	RT_ZERO(screen);
5638
5639	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5640	AssertLogRelRCReturn(rc, rc);
5641
5642	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5643	{
5644	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5645	*pScreen = screen;
5646	pScreen->fModified = true;
5647	}
5648	else
5649	{
5650	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5651	}
5652	}
5653	}
5654	else
5655	{
5656	/* Try to setup at least the first screen. */
5657	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5658	pScreen->fDefined = true;
5659	pScreen->fModified = true;
5660	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5661	pScreen->idScreen = 0;
5662	pScreen->xOrigin = 0;
5663	pScreen->yOrigin = 0;
5664	pScreen->offVRAM = pThis->svga.uScreenOffset;
5665	pScreen->cbPitch = pThis->svga.cbScanline;
5666	pScreen->cWidth = pThis->svga.uWidth;
5667	pScreen->cHeight = pThis->svga.uHeight;
5668	pScreen->cBpp = pThis->svga.uBpp;
5669	}
5670
5671	return VINF_SUCCESS;
5672	}
5673
5674	/**
5675	* @copydoc FNSSMDEVLOADEXEC
5676	*/
5677	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5678	{
5679	RT_NOREF(uPass);
5680	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5681	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5682	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5683	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5684	int rc;
5685
5686	/* Load our part of the VGAState */
5687	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5688	AssertRCReturn(rc, rc);
5689
5690	/* Load the VGA framebuffer. */
5691	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5692	uint32_t cbVgaFramebuffer = _32K;
5693	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5694	{
5695	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5696	AssertRCReturn(rc, rc);
5697	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5698	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5699	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5700	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5701	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5702	}
5703	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5704	AssertRCReturn(rc, rc);
5705	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5706	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5707	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5708	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5709
5710	/* Load the VMSVGA state. */
5711	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5712	AssertRCReturn(rc, rc);
5713
5714	/* Load the active cursor bitmaps. */
5715	if (pSVGAState->Cursor.fActive)
5716	{
5717	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5718	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5719
5720	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5721	AssertRCReturn(rc, rc);
5722	}
5723
5724	/* Load the GMR state. */
5725	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5726	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5727	{
5728	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5729	AssertRCReturn(rc, rc);
5730	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5731	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5732	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5733	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5734	}
5735
5736	if (pThis->svga.cGMR != cGMR)
5737	{
5738	/* Reallocate GMR array. */
5739	Assert(pSVGAState->paGMR != NULL);
5740	RTMemFree(pSVGAState->paGMR);
5741	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5742	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5743	pThis->svga.cGMR = cGMR;
5744	}
5745
5746	for (uint32_t i = 0; i < cGMR; ++i)
5747	{
5748	PGMR pGMR = &pSVGAState->paGMR[i];
5749
5750	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5751	AssertRCReturn(rc, rc);
5752
5753	if (pGMR->numDescriptors)
5754	{
5755	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5756	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5757	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5758
5759	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5760	{
5761	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5762	AssertRCReturn(rc, rc);
5763	}
5764	}
5765	}
5766
5767	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5768	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5769	# endif
5770
5771	VMSVGA_STATE_LOAD LoadState;
5772	LoadState.pSSM = pSSM;
5773	LoadState.uVersion = uVersion;
5774	LoadState.uPass = uPass;
5775	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5776	AssertLogRelRCReturn(rc, rc);
5777
5778	return VINF_SUCCESS;
5779	}
5780
5781	/**
5782	* Reinit the video mode after the state has been loaded.
5783	*/
5784	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5785	{
5786	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5787	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5788	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5789
5790	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5791
5792	/* Set the active cursor. */
5793	if (pSVGAState->Cursor.fActive)
5794	{
5795	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5796	true /fVisible/,
5797	true /fAlpha/,
5798	pSVGAState->Cursor.xHotspot,
5799	pSVGAState->Cursor.yHotspot,
5800	pSVGAState->Cursor.width,
5801	pSVGAState->Cursor.height,
5802	pSVGAState->Cursor.pData);
5803	AssertRC(rc);
5804	}
5805	return VINF_SUCCESS;
5806	}
5807
5808	/**
5809	* Portion of SVGA state which must be saved in the FIFO thread.
5810	*/
5811	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5812	{
5813	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5814	int rc;
5815
5816	/* Save the screen objects. */
5817	/* Count defined screen object. */
5818	uint32_t cScreens = 0;
5819	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5820	{
5821	if (pSVGAState->aScreens[i].fDefined)
5822	++cScreens;
5823	}
5824
5825	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5826	AssertLogRelRCReturn(rc, rc);
5827
5828	for (uint32_t i = 0; i < cScreens; ++i)
5829	{
5830	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5831
5832	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5833	AssertLogRelRCReturn(rc, rc);
5834	}
5835	return VINF_SUCCESS;
5836	}
5837
5838	/**
5839	* @copydoc FNSSMDEVSAVEEXEC
5840	*/
5841	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5842	{
5843	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5844	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5845	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5846	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5847	int rc;
5848
5849	/* Save our part of the VGAState */
5850	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5851	AssertLogRelRCReturn(rc, rc);
5852
5853	/* Save the framebuffer backup. */
5854	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5855	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5856	AssertLogRelRCReturn(rc, rc);
5857
5858	/* Save the VMSVGA state. */
5859	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5860	AssertLogRelRCReturn(rc, rc);
5861
5862	/* Save the active cursor bitmaps. */
5863	if (pSVGAState->Cursor.fActive)
5864	{
5865	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5866	AssertLogRelRCReturn(rc, rc);
5867	}
5868
5869	/* Save the GMR state */
5870	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5871	AssertLogRelRCReturn(rc, rc);
5872	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5873	{
5874	PGMR pGMR = &pSVGAState->paGMR[i];
5875
5876	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5877	AssertLogRelRCReturn(rc, rc);
5878
5879	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5880	{
5881	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5882	AssertLogRelRCReturn(rc, rc);
5883	}
5884	}
5885
5886	/*
5887	* Must save some state (3D in particular) in the FIFO thread.
5888	*/
5889	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5890	AssertLogRelRCReturn(rc, rc);
5891
5892	return VINF_SUCCESS;
5893	}
5894
5895	/**
5896	* Destructor for PVMSVGAR3STATE structure.
5897	*
5898	* @param pThis The shared VGA/VMSVGA instance data.
5899	* @param pSVGAState Pointer to the structure. It is not deallocated.
5900	*/
5901	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5902	{
5903	# ifndef VMSVGA_USE_EMT_HALT_CODE
5904	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5905	{
5906	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5907	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5908	}
5909	# endif
5910
5911	if (pSVGAState->Cursor.fActive)
5912	{
5913	RTMemFree(pSVGAState->Cursor.pData);
5914	pSVGAState->Cursor.pData = NULL;
5915	pSVGAState->Cursor.fActive = false;
5916	}
5917
5918	if (pSVGAState->paGMR)
5919	{
5920	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5921	if (pSVGAState->paGMR[i].paDesc)
5922	RTMemFree(pSVGAState->paGMR[i].paDesc);
5923
5924	RTMemFree(pSVGAState->paGMR);
5925	pSVGAState->paGMR = NULL;
5926	}
5927	}
5928
5929	/**
5930	* Constructor for PVMSVGAR3STATE structure.
5931	*
5932	* @returns VBox status code.
5933	* @param pThis The shared VGA/VMSVGA instance data.
5934	* @param pSVGAState Pointer to the structure. It is already allocated.
5935	*/
5936	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5937	{
5938	int rc = VINF_SUCCESS;
5939	RT_ZERO(*pSVGAState);
5940
5941	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5942	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5943
5944	# ifndef VMSVGA_USE_EMT_HALT_CODE
5945	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5946	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5947	AssertRCReturn(rc, rc);
5948	# endif
5949
5950	return rc;
5951	}
5952
5953	/**
5954	* Initializes the host capabilities: registers and FIFO.
5955	*
5956	* @returns VBox status code.
5957	* @param pThis The shared VGA/VMSVGA instance data.
5958	* @param pThisCC The VGA/VMSVGA state for ring-3.
5959	*/
5960	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5961	{
5962	/* Register caps. */
5963	pThis->svga.u32RegCaps = SVGA_CAP_GMR
5964	\| SVGA_CAP_GMR2
5965	\| SVGA_CAP_CURSOR
5966	\| SVGA_CAP_CURSOR_BYPASS_2
5967	\| SVGA_CAP_EXTENDED_FIFO
5968	\| SVGA_CAP_IRQMASK
5969	\| SVGA_CAP_PITCHLOCK
5970	\| SVGA_CAP_TRACES
5971	\| SVGA_CAP_SCREEN_OBJECT_2
5972	\| SVGA_CAP_ALPHA_CURSOR;
5973	# ifdef VBOX_WITH_VMSVGA3D
5974	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
5975	# endif
5976
5977	/* Clear the FIFO. */
5978	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5979
5980	/* Setup FIFO capabilities. */
5981	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5982	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5983	\| SVGA_FIFO_CAP_GMR2
5984	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5985	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
5986	\| SVGA_FIFO_CAP_RESERVE
5987	\| SVGA_FIFO_CAP_PITCHLOCK;
5988
5989	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5990	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5991	}
5992
5993	# ifdef VBOX_WITH_VMSVGA3D
5994	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
5995	static const char * const g_apszVmSvgaDevCapNames[] =
5996	{
5997	"x3D", /* = 0 */
5998	"xMAX_LIGHTS",
5999	"xMAX_TEXTURES",
6000	"xMAX_CLIP_PLANES",
6001	"xVERTEX_SHADER_VERSION",
6002	"xVERTEX_SHADER",
6003	"xFRAGMENT_SHADER_VERSION",
6004	"xFRAGMENT_SHADER",
6005	"xMAX_RENDER_TARGETS",
6006	"xS23E8_TEXTURES",
6007	"xS10E5_TEXTURES",
6008	"xMAX_FIXED_VERTEXBLEND",
6009	"xD16_BUFFER_FORMAT",
6010	"xD24S8_BUFFER_FORMAT",
6011	"xD24X8_BUFFER_FORMAT",
6012	"xQUERY_TYPES",
6013	"xTEXTURE_GRADIENT_SAMPLING",
6014	"rMAX_POINT_SIZE",
6015	"xMAX_SHADER_TEXTURES",
6016	"xMAX_TEXTURE_WIDTH",
6017	"xMAX_TEXTURE_HEIGHT",
6018	"xMAX_VOLUME_EXTENT",
6019	"xMAX_TEXTURE_REPEAT",
6020	"xMAX_TEXTURE_ASPECT_RATIO",
6021	"xMAX_TEXTURE_ANISOTROPY",
6022	"xMAX_PRIMITIVE_COUNT",
6023	"xMAX_VERTEX_INDEX",
6024	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6025	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6026	"xMAX_VERTEX_SHADER_TEMPS",
6027	"xMAX_FRAGMENT_SHADER_TEMPS",
6028	"xTEXTURE_OPS",
6029	"xSURFACEFMT_X8R8G8B8",
6030	"xSURFACEFMT_A8R8G8B8",
6031	"xSURFACEFMT_A2R10G10B10",
6032	"xSURFACEFMT_X1R5G5B5",
6033	"xSURFACEFMT_A1R5G5B5",
6034	"xSURFACEFMT_A4R4G4B4",
6035	"xSURFACEFMT_R5G6B5",
6036	"xSURFACEFMT_LUMINANCE16",
6037	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6038	"xSURFACEFMT_ALPHA8",
6039	"xSURFACEFMT_LUMINANCE8",
6040	"xSURFACEFMT_Z_D16",
6041	"xSURFACEFMT_Z_D24S8",
6042	"xSURFACEFMT_Z_D24X8",
6043	"xSURFACEFMT_DXT1",
6044	"xSURFACEFMT_DXT2",
6045	"xSURFACEFMT_DXT3",
6046	"xSURFACEFMT_DXT4",
6047	"xSURFACEFMT_DXT5",
6048	"xSURFACEFMT_BUMPX8L8V8U8",
6049	"xSURFACEFMT_A2W10V10U10",
6050	"xSURFACEFMT_BUMPU8V8",
6051	"xSURFACEFMT_Q8W8V8U8",
6052	"xSURFACEFMT_CxV8U8",
6053	"xSURFACEFMT_R_S10E5",
6054	"xSURFACEFMT_R_S23E8",
6055	"xSURFACEFMT_RG_S10E5",
6056	"xSURFACEFMT_RG_S23E8",
6057	"xSURFACEFMT_ARGB_S10E5",
6058	"xSURFACEFMT_ARGB_S23E8",
6059	"xMISSING62",
6060	"xMAX_VERTEX_SHADER_TEXTURES",
6061	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6062	"xSURFACEFMT_V16U16",
6063	"xSURFACEFMT_G16R16",
6064	"xSURFACEFMT_A16B16G16R16",
6065	"xSURFACEFMT_UYVY",
6066	"xSURFACEFMT_YUY2",
6067	"xMULTISAMPLE_NONMASKABLESAMPLES",
6068	"xMULTISAMPLE_MASKABLESAMPLES",
6069	"xALPHATOCOVERAGE",
6070	"xSUPERSAMPLE",
6071	"xAUTOGENMIPMAPS",
6072	"xSURFACEFMT_NV12",
6073	"xSURFACEFMT_AYUV",
6074	"xMAX_CONTEXT_IDS",
6075	"xMAX_SURFACE_IDS",
6076	"xSURFACEFMT_Z_DF16",
6077	"xSURFACEFMT_Z_DF24",
6078	"xSURFACEFMT_Z_D24S8_INT",
6079	"xSURFACEFMT_BC4_UNORM",
6080	"xSURFACEFMT_BC5_UNORM", /* 83 */
6081	};
6082
6083	/**
6084	* Initializes the host 3D capabilities in FIFO.
6085	*
6086	* @returns VBox status code.
6087	* @param pThis The shared VGA/VMSVGA instance data.
6088	* @param pThisCC The VGA/VMSVGA state for ring-3.
6089	*/
6090	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6091	{
6092	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6093	bool fSavedBuffering = RTLogRelSetBuffering(true);
6094	SVGA3dCapsRecord *pCaps;
6095	SVGA3dCapPair *pData;
6096	uint32_t idxCap = 0;
6097
6098	/* 3d hardware version; latest and greatest */
6099	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6100	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6101
6102	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6103	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6104	pData = (SVGA3dCapPair *)&pCaps->data;
6105
6106	/* Fill out all 3d capabilities. */
6107	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6108	{
6109	uint32_t val = 0;
6110
6111	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6112	if (RT_SUCCESS(rc))
6113	{
6114	pData[idxCap][0] = i;
6115	pData[idxCap][1] = val;
6116	idxCap++;
6117	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6118	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6119	else
6120	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6121	&g_apszVmSvgaDevCapNames[i][1]));
6122	}
6123	else
6124	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6125	}
6126	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6127	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6128
6129	/* Mark end of record array. */
6130	pCaps->header.length = 0;
6131
6132	RTLogRelSetBuffering(fSavedBuffering);
6133	}
6134
6135	# endif
6136
6137	/**
6138	* Resets the SVGA hardware state
6139	*
6140	* @returns VBox status code.
6141	* @param pDevIns The device instance.
6142	*/
6143	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6144	{
6145	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6146	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6147	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6148
6149	/* Reset before init? */
6150	if (!pSVGAState)
6151	return VINF_SUCCESS;
6152
6153	Log(("vmsvgaR3Reset\n"));
6154
6155	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6156	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6157	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6158
6159	/* Reset other stuff. */
6160	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6161	RT_ZERO(pThis->svga.au32ScratchRegion);
6162
6163	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6164	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6165
6166	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6167
6168	/* Initialize FIFO and register capabilities. */
6169	vmsvgaR3InitCaps(pThis, pThisCC);
6170
6171	# ifdef VBOX_WITH_VMSVGA3D
6172	if (pThis->svga.f3DEnabled)
6173	vmsvgaR3InitFifo3DCaps(pThisCC);
6174	# endif
6175
6176	/* VRAM tracking is enabled by default during bootup. */
6177	pThis->svga.fVRAMTracking = true;
6178	pThis->svga.fEnabled = false;
6179
6180	/* Invalidate current settings. */
6181	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6182	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6183	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6184	pThis->svga.cbScanline = 0;
6185	pThis->svga.u32PitchLock = 0;
6186
6187	return rc;
6188	}
6189
6190	/**
6191	* Cleans up the SVGA hardware state
6192	*
6193	* @returns VBox status code.
6194	* @param pDevIns The device instance.
6195	*/
6196	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6197	{
6198	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6199	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6200
6201	/*
6202	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6203	*/
6204	if (pThisCC->svga.pFIFOIOThread)
6205	{
6206	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6207	NULL /pvParam/, 30000 /ms/);
6208	AssertLogRelRC(rc);
6209
6210	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6211	AssertLogRelRC(rc);
6212	pThisCC->svga.pFIFOIOThread = NULL;
6213	}
6214
6215	/*
6216	* Destroy the special SVGA state.
6217	*/
6218	if (pThisCC->svga.pSvgaR3State)
6219	{
6220	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6221
6222	RTMemFree(pThisCC->svga.pSvgaR3State);
6223	pThisCC->svga.pSvgaR3State = NULL;
6224	}
6225
6226	/*
6227	* Free our resources residing in the VGA state.
6228	*/
6229	if (pThisCC->svga.pbVgaFrameBufferR3)
6230	{
6231	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6232	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6233	}
6234	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6235	{
6236	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6237	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6238	}
6239	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6240	{
6241	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6242	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6243	}
6244
6245	return VINF_SUCCESS;
6246	}
6247
6248	/**
6249	* Initialize the SVGA hardware state
6250	*
6251	* @returns VBox status code.
6252	* @param pDevIns The device instance.
6253	*/
6254	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6255	{
6256	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6257	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6258	PVMSVGAR3STATE pSVGAState;
6259	int rc;
6260
6261	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6262	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6263
6264	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6265
6266	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6267	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6268	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6269
6270	/* Create event semaphore. */
6271	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6272	AssertRCReturn(rc, rc);
6273
6274	/* Create event semaphore. */
6275	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6276	AssertRCReturn(rc, rc);
6277
6278	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6279	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6280
6281	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6282	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6283
6284	pSVGAState = pThisCC->svga.pSvgaR3State;
6285
6286	/* Initialize FIFO and register capabilities. */
6287	vmsvgaR3InitCaps(pThis, pThisCC);
6288
6289	# ifdef VBOX_WITH_VMSVGA3D
6290	if (pThis->svga.f3DEnabled)
6291	{
6292	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6293	if (RT_FAILURE(rc))
6294	{
6295	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6296	pThis->svga.f3DEnabled = false;
6297	}
6298	}
6299	# endif
6300	/* VRAM tracking is enabled by default during bootup. */
6301	pThis->svga.fVRAMTracking = true;
6302
6303	/* Invalidate current settings. */
6304	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6305	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6306	pThis->svga.uBpp = VMSVGA_VAL_UNINITIALIZED;
6307	pThis->svga.cbScanline = 0;
6308
6309	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6310	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6311	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6312	{
6313	pThis->svga.u32MaxWidth -= 256;
6314	pThis->svga.u32MaxHeight -= 256;
6315	}
6316	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6317
6318	# ifdef DEBUG_GMR_ACCESS
6319	/* Register the GMR access handler type. */
6320	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6321	vmsvgaR3GmrAccessHandler,
6322	NULL, NULL, NULL,
6323	NULL, NULL, NULL,
6324	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6325	AssertRCReturn(rc, rc);
6326	# endif
6327
6328	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6329	/* Register the FIFO access handler type. In addition to
6330	debugging FIFO access, this is also used to facilitate
6331	extended fifo thread sleeps. */
6332	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6333	# ifdef DEBUG_FIFO_ACCESS
6334	PGMPHYSHANDLERKIND_ALL,
6335	# else
6336	PGMPHYSHANDLERKIND_WRITE,
6337	# endif
6338	vmsvgaR3FifoAccessHandler,
6339	NULL, NULL, NULL,
6340	NULL, NULL, NULL,
6341	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6342	AssertRCReturn(rc, rc);
6343	# endif
6344
6345	/* Create the async IO thread. */
6346	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6347	RTTHREADTYPE_IO, "VMSVGA FIFO");
6348	if (RT_FAILURE(rc))
6349	{
6350	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6351	return rc;
6352	}
6353
6354	/*
6355	* Statistics.
6356	*/
6357	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6358	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6359	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6360	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6361	# ifdef VBOX_WITH_STATISTICS
6362	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6363	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6364	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6365	# endif
6366	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6367	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6368	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6369	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6370	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6371	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6372	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6373	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6374	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6375	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6376	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6377	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6378	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6379	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6380	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6381	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6382	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6383	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6384	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6385	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6386	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6387	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6388	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6389	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6390	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6391	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6392	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6393	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6394	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6395	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6396	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6397	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6398	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6399	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6400	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6401	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6402	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6403	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6404	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6405	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6406	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6407	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6408	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6409	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6410	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6411	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6412	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6413	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6414	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6415	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6416	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6417	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6418	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6419	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6420
6421	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6422	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6423	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6424	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6425	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6426	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6427	REG_CNT(&pThis->svga.StatRegCursorXxxxWr, "VMSVGA/Reg/CursorXxxxWrite", "SVGA_REG_CURSOR_XXXX writes.");
6428	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6429	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6430	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6431	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6432	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6433	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6434	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6435	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6436	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6437	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6438	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6439	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6440	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6441	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6442	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6443	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6444	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6445	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6446	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6447	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6448	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6449	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6450	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6451	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6452	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6453
6454	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6455	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6456	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6457	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6458	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6459	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6460	REG_CNT(&pThis->svga.StatRegCursorXxxxRd, "VMSVGA/Reg/CursorXxxxRead", "SVGA_REG_CURSOR_XXXX reads.");
6461	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6462	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6463	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6464	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6465	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6466	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6467	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6468	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6469	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6470	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6471	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6472	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6473	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6474	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6475	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6476	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6477	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6478	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6479	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6480	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6481	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6482	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6483	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6484	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6485	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6486	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6487	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6488	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6489	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6490	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6491	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6492	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6493	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6494	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6495	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6496	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6497	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6498	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6499	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6500	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6501	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6502	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6503
6504	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6505	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6506	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6507	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6508	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6509	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6510	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6511	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6512	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6513	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6514	# endif
6515	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6516	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6517	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6518	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6519	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6520
6521	# undef REG_CNT
6522	# undef REG_PRF
6523
6524	/*
6525	* Info handlers.
6526	*/
6527	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6528	# ifdef VBOX_WITH_VMSVGA3D
6529	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6530	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6531	"VMSVGA 3d surface details. "
6532	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6533	vmsvgaR3Info3dSurface);
6534	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6535	"VMSVGA 3d surface details and bitmap: "
6536	"sid[>dir]",
6537	vmsvgaR3Info3dSurfaceBmp);
6538	# endif
6539
6540	return VINF_SUCCESS;
6541	}
6542
6543	/**
6544	* Power On notification.
6545	*
6546	* @returns VBox status code.
6547	* @param pDevIns The device instance data.
6548	*
6549	* @remarks Caller enters the device critical section.
6550	*/
6551	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6552	{
6553	# ifdef VBOX_WITH_VMSVGA3D
6554	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6555	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6556	if (pThis->svga.f3DEnabled)
6557	{
6558	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6559
6560	if (RT_SUCCESS(rc))
6561	{
6562	/* Initialize FIFO 3D capabilities. */
6563	vmsvgaR3InitFifo3DCaps(pThisCC);
6564	}
6565	}
6566	# else /* !VBOX_WITH_VMSVGA3D */
6567	RT_NOREF(pDevIns);
6568	# endif /* !VBOX_WITH_VMSVGA3D */
6569	}
6570
6571	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 83193

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