DevVGA-SVGA.cpp@ 84677

Last change on this file since 84677 was 84013, checked in by vboxsync, 5 years ago
Devices/DevVGA-SVGA: Check if screen is not defined (aScreens[idScreen].fDefined == false) yet instead of (debug) asserting.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 311.9 KB

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1	/* $Id: DevVGA-SVGA.cpp 84013 2020-04-27 14:56:13Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdMoveCursor;
271	STAMCOUNTER StatR3CmdDisplayCursor;
272	STAMCOUNTER StatR3CmdRectFill;
273	STAMCOUNTER StatR3CmdRectCopy;
274	STAMCOUNTER StatR3CmdRectRopCopy;
275	STAMCOUNTER StatR3CmdEscape;
276	STAMCOUNTER StatR3CmdDefineScreen;
277	STAMCOUNTER StatR3CmdDestroyScreen;
278	STAMCOUNTER StatR3CmdDefineGmrFb;
279	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
280	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
281	STAMCOUNTER StatR3CmdAnnotationFill;
282	STAMCOUNTER StatR3CmdAnnotationCopy;
283	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
284	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
285	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
286	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
287	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
288	STAMCOUNTER StatR3Cmd3dSurfaceDma;
289	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
290	STAMCOUNTER StatR3Cmd3dContextDefine;
291	STAMCOUNTER StatR3Cmd3dContextDestroy;
292	STAMCOUNTER StatR3Cmd3dSetTransform;
293	STAMCOUNTER StatR3Cmd3dSetZRange;
294	STAMCOUNTER StatR3Cmd3dSetRenderState;
295	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
296	STAMCOUNTER StatR3Cmd3dSetTextureState;
297	STAMCOUNTER StatR3Cmd3dSetMaterial;
298	STAMCOUNTER StatR3Cmd3dSetLightData;
299	STAMCOUNTER StatR3Cmd3dSetLightEnable;
300	STAMCOUNTER StatR3Cmd3dSetViewPort;
301	STAMCOUNTER StatR3Cmd3dSetClipPlane;
302	STAMCOUNTER StatR3Cmd3dClear;
303	STAMCOUNTER StatR3Cmd3dPresent;
304	STAMCOUNTER StatR3Cmd3dPresentReadBack;
305	STAMCOUNTER StatR3Cmd3dShaderDefine;
306	STAMCOUNTER StatR3Cmd3dShaderDestroy;
307	STAMCOUNTER StatR3Cmd3dSetShader;
308	STAMCOUNTER StatR3Cmd3dSetShaderConst;
309	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
310	STAMCOUNTER StatR3Cmd3dSetScissorRect;
311	STAMCOUNTER StatR3Cmd3dBeginQuery;
312	STAMCOUNTER StatR3Cmd3dEndQuery;
313	STAMCOUNTER StatR3Cmd3dWaitForQuery;
314	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
315	STAMCOUNTER StatR3Cmd3dActivateSurface;
316	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
317
318	STAMCOUNTER StatR3RegConfigDoneWr;
319	STAMCOUNTER StatR3RegGmrDescriptorWr;
320	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
321	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
322
323	STAMCOUNTER StatFifoCommands;
324	STAMCOUNTER StatFifoErrors;
325	STAMCOUNTER StatFifoUnkCmds;
326	STAMCOUNTER StatFifoTodoTimeout;
327	STAMCOUNTER StatFifoTodoWoken;
328	STAMPROFILE StatFifoStalls;
329	STAMPROFILE StatFifoExtendedSleep;
330	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
331	STAMCOUNTER StatFifoAccessHandler;
332	# endif
333	STAMCOUNTER StatFifoCursorFetchAgain;
334	STAMCOUNTER StatFifoCursorNoChange;
335	STAMCOUNTER StatFifoCursorPosition;
336	STAMCOUNTER StatFifoCursorVisiblity;
337	STAMCOUNTER StatFifoWatchdogWakeUps;
338	} VMSVGAR3STATE, *PVMSVGAR3STATE;
339	#endif /* IN_RING3 */
340
341
342	/*********************************************************************************************************************************
343	* Internal Functions *
344	*********************************************************************************************************************************/
345	#ifdef IN_RING3
346	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
347	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
348	# endif
349	# ifdef DEBUG_GMR_ACCESS
350	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
351	# endif
352	#endif
353
354
355	/*********************************************************************************************************************************
356	* Global Variables *
357	*********************************************************************************************************************************/
358	#ifdef IN_RING3
359
360	/**
361	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
362	*/
363	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
364	{
365	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
366	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
367	SSMFIELD_ENTRY_TERM()
368	};
369
370	/**
371	* SSM descriptor table for the GMR structure.
372	*/
373	static SSMFIELD const g_aGMRFields[] =
374	{
375	SSMFIELD_ENTRY( GMR, cMaxPages),
376	SSMFIELD_ENTRY( GMR, cbTotal),
377	SSMFIELD_ENTRY( GMR, numDescriptors),
378	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
379	SSMFIELD_ENTRY_TERM()
380	};
381
382	/**
383	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
384	*/
385	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
386	{
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
395	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
396	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
397	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
398	SSMFIELD_ENTRY_TERM()
399	};
400
401	/**
402	* SSM descriptor table for the VMSVGAR3STATE structure.
403	*/
404	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
405	{
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
409	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
411	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
412	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
413	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
414	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
415	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
417	#ifdef VMSVGA_USE_EMT_HALT_CODE
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
419	#else
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
421	#endif
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
485
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
490
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
498	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
500	# endif
501	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
504	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
505
506	SSMFIELD_ENTRY_TERM()
507	};
508
509	/**
510	* SSM descriptor table for the VGAState.svga structure.
511	*/
512	static SSMFIELD const g_aVGAStateSVGAFields[] =
513	{
514	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
515	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
516	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
517	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
518	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
519	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
520	SSMFIELD_ENTRY( VMSVGAState, fBusy),
521	SSMFIELD_ENTRY( VMSVGAState, fTraces),
522	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
523	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
524	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
525	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
526	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
527	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
528	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
529	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
530	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
531	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
532	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
533	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
534	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
535	SSMFIELD_ENTRY( VMSVGAState, uWidth),
536	SSMFIELD_ENTRY( VMSVGAState, uHeight),
537	SSMFIELD_ENTRY( VMSVGAState, uBpp),
538	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
539	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
540	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
541	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
542	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
543	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
544	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
545	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
546	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
547	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
548	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
549	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
550	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
551	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
552	SSMFIELD_ENTRY_TERM()
553	};
554	#endif /* IN_RING3 */
555
556
557	/*********************************************************************************************************************************
558	* Internal Functions *
559	*********************************************************************************************************************************/
560	#ifdef IN_RING3
561	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
562	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
563	uint32_t uVersion, uint32_t uPass);
564	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
565	# ifdef VBOX_WITH_VMSVGA3D
566	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
567	# endif /* VBOX_WITH_VMSVGA3D */
568	#endif /* IN_RING3 */
569
570
571
572	#ifdef IN_RING3
573	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
574	{
575	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
576	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
577	&& pSVGAState
578	&& pSVGAState->aScreens[idScreen].fDefined)
579	{
580	return &pSVGAState->aScreens[idScreen];
581	}
582	return NULL;
583	}
584	#endif /* IN_RING3 */
585
586	#ifdef LOG_ENABLED
587
588	/**
589	* Index register string name lookup
590	*
591	* @returns Index register string or "UNKNOWN"
592	* @param pThis The shared VGA/VMSVGA state.
593	* @param idxReg The index register.
594	*/
595	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
596	{
597	switch (idxReg)
598	{
599	case SVGA_REG_ID: return "SVGA_REG_ID";
600	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
601	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
602	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
603	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
604	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
605	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
606	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
607	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
608	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
609	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
610	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
611	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
612	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
613	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
614	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
615	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
616	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
617	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
618	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
619	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
620	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
621	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
622	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
623	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
624	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
625	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
626	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
627	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
628	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
629	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
630	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
631	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
632	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
633	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
634	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
635	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
636	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
637	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
638	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
639	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
640	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
641	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
642	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
643	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
644	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
645	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
646	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
647	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
648	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
649
650	default:
651	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
652	return "SVGA_SCRATCH_BASE reg";
653	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
654	return "SVGA_PALETTE_BASE reg";
655	return "UNKNOWN";
656	}
657	}
658
659	#ifdef IN_RING3
660	/**
661	* FIFO command name lookup
662	*
663	* @returns FIFO command string or "UNKNOWN"
664	* @param u32Cmd FIFO command
665	*/
666	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
667	{
668	switch (u32Cmd)
669	{
670	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
671	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
672	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
673	case SVGA_CMD_RECT_ROP_COPY: return "SVGA_CMD_RECT_ROP_COPY";
674	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
675	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
676	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
677	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
678	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
679	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
680	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
681	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
682	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
683	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
684	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
685	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
686	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
687	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
688	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
689	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
690	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
691	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
692	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
693	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
694	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
695	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
696	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
697	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
698	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
699	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
700	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
701	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
702	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
703	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
704	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
705	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
706	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
707	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
708	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
709	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
710	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
711	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
712	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
713	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
714	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
715	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
716	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
717	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
718	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
719	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
720	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
721	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
722	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
723	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
724	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
725	default: return "UNKNOWN";
726	}
727	}
728	# endif /* IN_RING3 */
729
730	#endif /* LOG_ENABLED */
731	#ifdef IN_RING3
732
733	/**
734	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
735	*/
736	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
737	{
738	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
739	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
740
741	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
742	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
743
744	/** @todo Test how it interacts with multiple screen objects. */
745	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
746	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
747	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
748
749	if (x < uWidth)
750	{
751	pThis->svga.viewport.x = x;
752	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
753	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
754	}
755	else
756	{
757	pThis->svga.viewport.x = uWidth;
758	pThis->svga.viewport.cx = 0;
759	pThis->svga.viewport.xRight = uWidth;
760	}
761	if (y < uHeight)
762	{
763	pThis->svga.viewport.y = y;
764	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
765	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
766	pThis->svga.viewport.yHighWC = uHeight - y;
767	}
768	else
769	{
770	pThis->svga.viewport.y = uHeight;
771	pThis->svga.viewport.cy = 0;
772	pThis->svga.viewport.yLowWC = 0;
773	pThis->svga.viewport.yHighWC = 0;
774	}
775
776	# ifdef VBOX_WITH_VMSVGA3D
777	/*
778	* Now inform the 3D backend.
779	*/
780	if (pThis->svga.f3DEnabled)
781	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
782	# else
783	RT_NOREF(OldViewport);
784	# endif
785	}
786
787
788	/**
789	* Updating screen information in API
790	*
791	* @param pThis The The shared VGA/VMSVGA instance data.
792	* @param pThisCC The VGA/VMSVGA state for ring-3.
793	*/
794	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
795	{
796	int rc;
797
798	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
799
800	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
801	{
802	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
803	if (!pScreen->fModified)
804	continue;
805
806	pScreen->fModified = false;
807
808	VBVAINFOVIEW view;
809	RT_ZERO(view);
810	view.u32ViewIndex = pScreen->idScreen;
811	// view.u32ViewOffset = 0;
812	view.u32ViewSize = pThis->vram_size;
813	view.u32MaxScreenSize = pThis->vram_size;
814
815	VBVAINFOSCREEN screen;
816	RT_ZERO(screen);
817	screen.u32ViewIndex = pScreen->idScreen;
818
819	if (pScreen->fDefined)
820	{
821	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
822	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
823	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
824	{
825	Assert(pThis->svga.fGFBRegisters);
826	continue;
827	}
828
829	screen.i32OriginX = pScreen->xOrigin;
830	screen.i32OriginY = pScreen->yOrigin;
831	screen.u32StartOffset = pScreen->offVRAM;
832	screen.u32LineSize = pScreen->cbPitch;
833	screen.u32Width = pScreen->cWidth;
834	screen.u32Height = pScreen->cHeight;
835	screen.u16BitsPerPixel = pScreen->cBpp;
836	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
837	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
838	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
839	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
840	}
841	else
842	{
843	/* Screen is destroyed. */
844	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
845	}
846
847	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
848	AssertRC(rc);
849	}
850	}
851
852
853	/**
854	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
855	*
856	* Used to update screen offsets (positions) since appearently vmwgfx fails to
857	* pass correct offsets thru FIFO.
858	*/
859	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
860	{
861	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
862	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
863	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
864
865	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
866	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
867	for (uint32_t i = 0; i < cPositions; ++i)
868	{
869	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
870	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
871	continue;
872
873	if (pSVGAState->aScreens[i].xOrigin == -1)
874	continue;
875	if (pSVGAState->aScreens[i].yOrigin == -1)
876	continue;
877
878	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
879	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
880	pSVGAState->aScreens[i].fModified = true;
881	}
882
883	vmsvgaR3VBVAResize(pThis, pThisCC);
884	}
885
886	#endif /* IN_RING3 */
887
888	/**
889	* Read port register
890	*
891	* @returns VBox status code.
892	* @param pDevIns The device instance.
893	* @param pThis The shared VGA/VMSVGA state.
894	* @param pu32 Where to store the read value
895	*/
896	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
897	{
898	#ifdef IN_RING3
899	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
900	#endif
901	int rc = VINF_SUCCESS;
902	*pu32 = 0;
903
904	/* Rough index register validation. */
905	uint32_t idxReg = pThis->svga.u32IndexReg;
906	#if !defined(IN_RING3) && defined(VBOX_STRICT)
907	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
908	VINF_IOM_R3_IOPORT_READ);
909	#else
910	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
911	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
912	VINF_SUCCESS);
913	#endif
914	RT_UNTRUSTED_VALIDATED_FENCE();
915
916	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
917	if ( idxReg >= SVGA_REG_CAPABILITIES
918	&& pThis->svga.u32SVGAId == SVGA_ID_0)
919	{
920	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
921	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
922	}
923
924	switch (idxReg)
925	{
926	case SVGA_REG_ID:
927	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
928	*pu32 = pThis->svga.u32SVGAId;
929	break;
930
931	case SVGA_REG_ENABLE:
932	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
933	*pu32 = pThis->svga.fEnabled;
934	break;
935
936	case SVGA_REG_WIDTH:
937	{
938	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
939	if ( pThis->svga.fEnabled
940	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
941	*pu32 = pThis->svga.uWidth;
942	else
943	{
944	#ifndef IN_RING3
945	rc = VINF_IOM_R3_IOPORT_READ;
946	#else
947	*pu32 = pThisCC->pDrv->cx;
948	#endif
949	}
950	break;
951	}
952
953	case SVGA_REG_HEIGHT:
954	{
955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
956	if ( pThis->svga.fEnabled
957	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
958	*pu32 = pThis->svga.uHeight;
959	else
960	{
961	#ifndef IN_RING3
962	rc = VINF_IOM_R3_IOPORT_READ;
963	#else
964	*pu32 = pThisCC->pDrv->cy;
965	#endif
966	}
967	break;
968	}
969
970	case SVGA_REG_MAX_WIDTH:
971	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
972	*pu32 = pThis->svga.u32MaxWidth;
973	break;
974
975	case SVGA_REG_MAX_HEIGHT:
976	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
977	*pu32 = pThis->svga.u32MaxHeight;
978	break;
979
980	case SVGA_REG_DEPTH:
981	/* This returns the color depth of the current mode. */
982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
983	switch (pThis->svga.uBpp)
984	{
985	case 15:
986	case 16:
987	case 24:
988	*pu32 = pThis->svga.uBpp;
989	break;
990
991	default:
992	case 32:
993	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
994	break;
995	}
996	break;
997
998	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
999	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1000	*pu32 = pThis->svga.uHostBpp;
1001	break;
1002
1003	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1005	*pu32 = pThis->svga.uBpp;
1006	break;
1007
1008	case SVGA_REG_PSEUDOCOLOR:
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1010	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1011	break;
1012
1013	case SVGA_REG_RED_MASK:
1014	case SVGA_REG_GREEN_MASK:
1015	case SVGA_REG_BLUE_MASK:
1016	{
1017	uint32_t uBpp;
1018
1019	if (pThis->svga.fEnabled)
1020	uBpp = pThis->svga.uBpp;
1021	else
1022	uBpp = pThis->svga.uHostBpp;
1023
1024	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1025	switch (uBpp)
1026	{
1027	case 8:
1028	u32RedMask = 0x07;
1029	u32GreenMask = 0x38;
1030	u32BlueMask = 0xc0;
1031	break;
1032
1033	case 15:
1034	u32RedMask = 0x0000001f;
1035	u32GreenMask = 0x000003e0;
1036	u32BlueMask = 0x00007c00;
1037	break;
1038
1039	case 16:
1040	u32RedMask = 0x0000001f;
1041	u32GreenMask = 0x000007e0;
1042	u32BlueMask = 0x0000f800;
1043	break;
1044
1045	case 24:
1046	case 32:
1047	default:
1048	u32RedMask = 0x00ff0000;
1049	u32GreenMask = 0x0000ff00;
1050	u32BlueMask = 0x000000ff;
1051	break;
1052	}
1053	switch (idxReg)
1054	{
1055	case SVGA_REG_RED_MASK:
1056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1057	*pu32 = u32RedMask;
1058	break;
1059
1060	case SVGA_REG_GREEN_MASK:
1061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1062	*pu32 = u32GreenMask;
1063	break;
1064
1065	case SVGA_REG_BLUE_MASK:
1066	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1067	*pu32 = u32BlueMask;
1068	break;
1069	}
1070	break;
1071	}
1072
1073	case SVGA_REG_BYTES_PER_LINE:
1074	{
1075	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1076	if ( pThis->svga.fEnabled
1077	&& pThis->svga.cbScanline)
1078	*pu32 = pThis->svga.cbScanline;
1079	else
1080	{
1081	#ifndef IN_RING3
1082	rc = VINF_IOM_R3_IOPORT_READ;
1083	#else
1084	*pu32 = pThisCC->pDrv->cbScanline;
1085	#endif
1086	}
1087	break;
1088	}
1089
1090	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1092	*pu32 = pThis->vram_size;
1093	break;
1094
1095	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1096	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1097	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1098	*pu32 = pThis->GCPhysVRAM;
1099	break;
1100
1101	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1102	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1103	/* Always zero in our case. */
1104	*pu32 = 0;
1105	break;
1106
1107	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1108	{
1109	#ifndef IN_RING3
1110	rc = VINF_IOM_R3_IOPORT_READ;
1111	#else
1112	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1113
1114	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1115	if ( pThis->svga.fEnabled
1116	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1117	{
1118	/* Hardware enabled; return real framebuffer size .*/
1119	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1120	}
1121	else
1122	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1123
1124	pu32 = RT_MIN(pThis->vram_size, pu32);
1125	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1126	#endif
1127	break;
1128	}
1129
1130	case SVGA_REG_CAPABILITIES:
1131	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1132	*pu32 = pThis->svga.u32RegCaps;
1133	break;
1134
1135	case SVGA_REG_MEM_START: /* FIFO start */
1136	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1137	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1138	*pu32 = pThis->svga.GCPhysFIFO;
1139	break;
1140
1141	case SVGA_REG_MEM_SIZE: /* FIFO size */
1142	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1143	*pu32 = pThis->svga.cbFIFO;
1144	break;
1145
1146	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1147	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1148	*pu32 = pThis->svga.fConfigured;
1149	break;
1150
1151	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1152	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1153	*pu32 = 0;
1154	break;
1155
1156	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1158	if (pThis->svga.fBusy)
1159	{
1160	#ifndef IN_RING3
1161	/* Go to ring-3 and halt the CPU. */
1162	rc = VINF_IOM_R3_IOPORT_READ;
1163	RT_NOREF(pDevIns);
1164	break;
1165	#else
1166	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1167	/* The guest is basically doing a HLT via the device here, but with
1168	a special wake up condition on FIFO completion. */
1169	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1170	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1171	PVM pVM = PDMDevHlpGetVM(pDevIns);
1172	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1173	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1174	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1175	if (pThis->svga.fBusy)
1176	{
1177	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1178	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1179	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1180	}
1181	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1182	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1183	# else
1184
1185	/* Delay the EMT a bit so the FIFO and others can get some work done.
1186	This used to be a crude 50 ms sleep. The current code tries to be
1187	more efficient, but the consept is still very crude. */
1188	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1189	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1190	RTThreadYield();
1191	if (pThis->svga.fBusy)
1192	{
1193	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1194
1195	if (pThis->svga.fBusy && cRefs == 1)
1196	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1197	if (pThis->svga.fBusy)
1198	{
1199	/** @todo If this code is going to stay, we need to call into the halt/wait
1200	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1201	* suffer when the guest is polling on a busy FIFO. */
1202	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1203	if (cNsMaxWait >= RT_NS_100US)
1204	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1205	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1206	RT_MIN(cNsMaxWait, RT_NS_10MS));
1207	}
1208
1209	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1210	}
1211	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1212	# endif
1213	*pu32 = pThis->svga.fBusy != 0;
1214	#endif
1215	}
1216	else
1217	*pu32 = false;
1218	break;
1219
1220	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1221	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1222	*pu32 = pThis->svga.u32GuestId;
1223	break;
1224
1225	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1226	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1227	*pu32 = pThis->svga.cScratchRegion;
1228	break;
1229
1230	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1231	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1232	*pu32 = SVGA_FIFO_NUM_REGS;
1233	break;
1234
1235	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1236	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1237	*pu32 = pThis->svga.u32PitchLock;
1238	break;
1239
1240	case SVGA_REG_IRQMASK: /* Interrupt mask */
1241	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1242	*pu32 = pThis->svga.u32IrqMask;
1243	break;
1244
1245	/* See "Guest memory regions" below. */
1246	case SVGA_REG_GMR_ID:
1247	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1248	*pu32 = pThis->svga.u32CurrentGMRId;
1249	break;
1250
1251	case SVGA_REG_GMR_DESCRIPTOR:
1252	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1253	/* Write only */
1254	*pu32 = 0;
1255	break;
1256
1257	case SVGA_REG_GMR_MAX_IDS:
1258	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1259	*pu32 = pThis->svga.cGMR;
1260	break;
1261
1262	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1263	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1264	*pu32 = VMSVGA_MAX_GMR_PAGES;
1265	break;
1266
1267	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1268	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1269	*pu32 = pThis->svga.fTraces;
1270	break;
1271
1272	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1273	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1274	*pu32 = VMSVGA_MAX_GMR_PAGES;
1275	break;
1276
1277	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1278	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1279	*pu32 = VMSVGA_SURFACE_SIZE;
1280	break;
1281
1282	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1283	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1284	break;
1285
1286	/* Mouse cursor support. */
1287	case SVGA_REG_CURSOR_ID:
1288	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1289	*pu32 = pThis->svga.uCursorID;
1290	break;
1291
1292	case SVGA_REG_CURSOR_X:
1293	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1294	*pu32 = pThis->svga.uCursorX;
1295	break;
1296
1297	case SVGA_REG_CURSOR_Y:
1298	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1299	*pu32 = pThis->svga.uCursorY;
1300	break;
1301
1302	case SVGA_REG_CURSOR_ON:
1303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1304	*pu32 = pThis->svga.uCursorOn;
1305	break;
1306
1307	/* Legacy multi-monitor support */
1308	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1309	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1310	*pu32 = 1;
1311	break;
1312
1313	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1314	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1315	*pu32 = 0;
1316	break;
1317
1318	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1319	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1320	*pu32 = 0;
1321	break;
1322
1323	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1324	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1325	*pu32 = 0;
1326	break;
1327
1328	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1329	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1330	*pu32 = 0;
1331	break;
1332
1333	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1335	*pu32 = pThis->svga.uWidth;
1336	break;
1337
1338	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1340	*pu32 = pThis->svga.uHeight;
1341	break;
1342
1343	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1345	/* We must return something sensible here otherwise the Linux driver
1346	will take a legacy code path without 3d support. This number also
1347	limits how many screens Linux guests will allow. */
1348	*pu32 = pThis->cMonitors;
1349	break;
1350
1351	default:
1352	{
1353	uint32_t offReg;
1354	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1355	{
1356	RT_UNTRUSTED_VALIDATED_FENCE();
1357	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1358	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1359	}
1360	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1361	{
1362	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1363	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1364	RT_UNTRUSTED_VALIDATED_FENCE();
1365	uint32_t u32 = pThis->last_palette[offReg / 3];
1366	switch (offReg % 3)
1367	{
1368	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1369	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1370	case 2: pu32 = u32 & 0xff; break; / blue */
1371	}
1372	}
1373	else
1374	{
1375	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1376	rc = VINF_IOM_R3_IOPORT_READ;
1377	#else
1378	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1379
1380	/* Do not assert. The guest might be reading all registers. */
1381	LogFunc(("Unknown reg=%#x\n", idxReg));
1382	#endif
1383	}
1384	break;
1385	}
1386	}
1387	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1388	return rc;
1389	}
1390
1391	#ifdef IN_RING3
1392	/**
1393	* Apply the current resolution settings to change the video mode.
1394	*
1395	* @returns VBox status code.
1396	* @param pThis The shared VGA state.
1397	* @param pThisCC The ring-3 VGA state.
1398	*/
1399	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1400	{
1401	/* Always do changemode on FIFO thread. */
1402	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1403
1404	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1405
1406	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1407
1408	if (pThis->svga.fGFBRegisters)
1409	{
1410	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1411	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1412	* deletes all screens other than screen #0, and redefines screen
1413	* #0 according to the specified mode. Drivers that use
1414	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1415	*/
1416
1417	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1418	pScreen->fDefined = true;
1419	pScreen->fModified = true;
1420	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1421	pScreen->idScreen = 0;
1422	pScreen->xOrigin = 0;
1423	pScreen->yOrigin = 0;
1424	pScreen->offVRAM = 0;
1425	pScreen->cbPitch = pThis->svga.cbScanline;
1426	pScreen->cWidth = pThis->svga.uWidth;
1427	pScreen->cHeight = pThis->svga.uHeight;
1428	pScreen->cBpp = pThis->svga.uBpp;
1429
1430	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1431	{
1432	/* Delete screen. */
1433	pScreen = &pSVGAState->aScreens[iScreen];
1434	if (pScreen->fDefined)
1435	{
1436	pScreen->fModified = true;
1437	pScreen->fDefined = false;
1438	}
1439	}
1440	}
1441	else
1442	{
1443	/* "If Screen Objects are supported, they can be used to fully
1444	* replace the functionality provided by the framebuffer registers
1445	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1446	*/
1447	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1448	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1449	pThis->svga.uBpp = pThis->svga.uHostBpp;
1450	}
1451
1452	vmsvgaR3VBVAResize(pThis, pThisCC);
1453
1454	/* Last stuff. For the VGA device screenshot. */
1455	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1456	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1457	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1458	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1459	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1460
1461	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1462	if ( pThis->svga.viewport.cx == 0
1463	&& pThis->svga.viewport.cy == 0)
1464	{
1465	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1466	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1467	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1468	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1469	pThis->svga.viewport.yLowWC = 0;
1470	}
1471
1472	return VINF_SUCCESS;
1473	}
1474
1475	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1476	{
1477	VBVACMDHDR cmd;
1478	cmd.x = (int16_t)(pScreen->xOrigin + x);
1479	cmd.y = (int16_t)(pScreen->yOrigin + y);
1480	cmd.w = (uint16_t)w;
1481	cmd.h = (uint16_t)h;
1482
1483	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1484	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1485	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1486	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1487
1488	return VINF_SUCCESS;
1489	}
1490
1491	#endif /* IN_RING3 */
1492	#if defined(IN_RING0) \|\| defined(IN_RING3)
1493
1494	/**
1495	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1496	*
1497	* @param pThis The shared VGA/VMSVGA instance data.
1498	* @param pThisCC The VGA/VMSVGA state for the current context.
1499	* @param fState The busy state.
1500	*/
1501	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1502	{
1503	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1504
1505	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1506	{
1507	/* Race / unfortunately scheduling. Highly unlikly. */
1508	uint32_t cLoops = 64;
1509	do
1510	{
1511	ASMNopPause();
1512	fState = (pThis->svga.fBusy != 0);
1513	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1514	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1515	}
1516	}
1517
1518
1519	/**
1520	* Update the scanline pitch in response to the guest changing mode
1521	* width/bpp.
1522	*
1523	* @param pThis The shared VGA/VMSVGA state.
1524	* @param pThisCC The VGA/VMSVGA state for the current context.
1525	*/
1526	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1527	{
1528	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1529	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1530	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1531	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1532
1533	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1534	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1535	* location but it has a different meaning.
1536	*/
1537	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1538	uFifoPitchLock = 0;
1539
1540	/* Sanitize values. */
1541	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1542	uFifoPitchLock = 0;
1543	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1544	uRegPitchLock = 0;
1545
1546	/* Prefer the register value to the FIFO value.*/
1547	if (uRegPitchLock)
1548	pThis->svga.cbScanline = uRegPitchLock;
1549	else if (uFifoPitchLock)
1550	pThis->svga.cbScanline = uFifoPitchLock;
1551	else
1552	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1553
1554	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1555	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1556	}
1557
1558	#endif /* IN_RING0 \|\| IN_RING3 */
1559
1560	#ifdef IN_RING3
1561
1562	/**
1563	* Sends cursor position and visibility information from legacy
1564	* SVGA registers to the front-end.
1565	*/
1566	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1567	{
1568	/*
1569	* Writing the X/Y/ID registers does not trigger changes; only writing the
1570	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1571	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1572	* register if they don't have to.
1573	*/
1574	uint32_t x, y, idScreen;
1575	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1576
1577	x = pThis->svga.uCursorX;
1578	y = pThis->svga.uCursorY;
1579	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1580
1581	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1582	* were extended as follows:
1583	*
1584	* SVGA_CURSOR_ON_HIDE 0
1585	* SVGA_CURSOR_ON_SHOW 1
1586	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1587	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1588	*
1589	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1590	* distinguish between the non-zero values but still remember them.
1591	*/
1592	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1593	{
1594	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1595	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1596	}
1597	pThis->svga.uCursorOn = uCursorOn;
1598	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1599	}
1600
1601
1602	/**
1603	* Copy a rectangle of pixels within guest VRAM.
1604	*/
1605	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1606	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1607	{
1608	if (!width \|\| !height)
1609	return; /* Nothing to do, don't even bother. */
1610
1611	/*
1612	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1613	* corresponding to the current display mode.
1614	*/
1615	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1616	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1617	uint8_t const *pSrc;
1618	uint8_t *pDst;
1619	unsigned const cbRectWidth = width * cbPixel;
1620	unsigned uMaxOffset;
1621
1622	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1623	if (uMaxOffset >= cbFrameBuffer)
1624	{
1625	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1626	return; /* Just don't listen to a bad guest. */
1627	}
1628
1629	pSrc = pDst = pThisCC->pbVRam;
1630	pSrc += srcY * cbScanline + srcX * cbPixel;
1631	pDst += dstY * cbScanline + dstX * cbPixel;
1632
1633	if (srcY >= dstY)
1634	{
1635	/* Source below destination, copy top to bottom. */
1636	for (; height > 0; height--)
1637	{
1638	memmove(pDst, pSrc, cbRectWidth);
1639	pSrc += cbScanline;
1640	pDst += cbScanline;
1641	}
1642	}
1643	else
1644	{
1645	/* Source above destination, copy bottom to top. */
1646	pSrc += cbScanline * (height - 1);
1647	pDst += cbScanline * (height - 1);
1648	for (; height > 0; height--)
1649	{
1650	memmove(pDst, pSrc, cbRectWidth);
1651	pSrc -= cbScanline;
1652	pDst -= cbScanline;
1653	}
1654	}
1655	}
1656
1657	#endif /* IN_RING3 */
1658
1659
1660	/**
1661	* Write port register
1662	*
1663	* @returns Strict VBox status code.
1664	* @param pDevIns The device instance.
1665	* @param pThis The shared VGA/VMSVGA state.
1666	* @param pThisCC The VGA/VMSVGA state for the current context.
1667	* @param u32 Value to write
1668	*/
1669	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1670	{
1671	#ifdef IN_RING3
1672	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1673	#endif
1674	VBOXSTRICTRC rc = VINF_SUCCESS;
1675	RT_NOREF(pThisCC);
1676
1677	/* Rough index register validation. */
1678	uint32_t idxReg = pThis->svga.u32IndexReg;
1679	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1680	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1681	VINF_IOM_R3_IOPORT_WRITE);
1682	#else
1683	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1684	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1685	VINF_SUCCESS);
1686	#endif
1687	RT_UNTRUSTED_VALIDATED_FENCE();
1688
1689	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1690	if ( idxReg >= SVGA_REG_CAPABILITIES
1691	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1692	{
1693	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1694	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1695	}
1696	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1697	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1698	switch (idxReg)
1699	{
1700	case SVGA_REG_WIDTH:
1701	case SVGA_REG_HEIGHT:
1702	case SVGA_REG_PITCHLOCK:
1703	case SVGA_REG_BITS_PER_PIXEL:
1704	pThis->svga.fGFBRegisters = true;
1705	break;
1706	default:
1707	break;
1708	}
1709
1710	switch (idxReg)
1711	{
1712	case SVGA_REG_ID:
1713	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1714	if ( u32 == SVGA_ID_0
1715	\|\| u32 == SVGA_ID_1
1716	\|\| u32 == SVGA_ID_2)
1717	pThis->svga.u32SVGAId = u32;
1718	else
1719	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1720	break;
1721
1722	case SVGA_REG_ENABLE:
1723	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1724	#ifdef IN_RING3
1725	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1726	&& pThis->svga.fEnabled == false)
1727	{
1728	/* Make a backup copy of the first 512kb in order to save font data etc. */
1729	/** @todo should probably swap here, rather than copy + zero */
1730	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1731	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1732	}
1733
1734	pThis->svga.fEnabled = u32;
1735	if (pThis->svga.fEnabled)
1736	{
1737	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1738	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1739	{
1740	/* Keep the current mode. */
1741	pThis->svga.uWidth = pThisCC->pDrv->cx;
1742	pThis->svga.uHeight = pThisCC->pDrv->cy;
1743	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1744	}
1745
1746	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1747	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1748	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1749	# ifdef LOG_ENABLED
1750	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1751	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1752	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1753	# endif
1754
1755	/* Disable or enable dirty page tracking according to the current fTraces value. */
1756	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1757
1758	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1759	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1760	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1761
1762	/* Make the cursor visible again as needed. */
1763	if (pSVGAState->Cursor.fActive)
1764	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1765	}
1766	else
1767	{
1768	/* Make sure the cursor is off. */
1769	if (pSVGAState->Cursor.fActive)
1770	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1771
1772	/* Restore the text mode backup. */
1773	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1774
1775	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1776
1777	/* Enable dirty page tracking again when going into legacy mode. */
1778	vmsvgaR3SetTraces(pDevIns, pThis, true);
1779
1780	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1781	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1782	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1783
1784	/* Clear the pitch lock. */
1785	pThis->svga.u32PitchLock = 0;
1786	}
1787	#else /* !IN_RING3 */
1788	rc = VINF_IOM_R3_IOPORT_WRITE;
1789	#endif /* !IN_RING3 */
1790	break;
1791
1792	case SVGA_REG_WIDTH:
1793	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1794	if (pThis->svga.uWidth != u32)
1795	{
1796	#if defined(IN_RING3) \|\| defined(IN_RING0)
1797	pThis->svga.uWidth = u32;
1798	vmsvgaHCUpdatePitch(pThis, pThisCC);
1799	if (pThis->svga.fEnabled)
1800	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1801	#else
1802	rc = VINF_IOM_R3_IOPORT_WRITE;
1803	#endif
1804	}
1805	/* else: nop */
1806	break;
1807
1808	case SVGA_REG_HEIGHT:
1809	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1810	if (pThis->svga.uHeight != u32)
1811	{
1812	pThis->svga.uHeight = u32;
1813	if (pThis->svga.fEnabled)
1814	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1815	}
1816	/* else: nop */
1817	break;
1818
1819	case SVGA_REG_DEPTH:
1820	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1821	/** @todo read-only?? */
1822	break;
1823
1824	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1825	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1826	if (pThis->svga.uBpp != u32)
1827	{
1828	#if defined(IN_RING3) \|\| defined(IN_RING0)
1829	pThis->svga.uBpp = u32;
1830	vmsvgaHCUpdatePitch(pThis, pThisCC);
1831	if (pThis->svga.fEnabled)
1832	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1833	#else
1834	rc = VINF_IOM_R3_IOPORT_WRITE;
1835	#endif
1836	}
1837	/* else: nop */
1838	break;
1839
1840	case SVGA_REG_PSEUDOCOLOR:
1841	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1842	break;
1843
1844	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1845	#ifdef IN_RING3
1846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1847	pThis->svga.fConfigured = u32;
1848	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1849	if (!pThis->svga.fConfigured)
1850	pThis->svga.fTraces = true;
1851	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1852	#else
1853	rc = VINF_IOM_R3_IOPORT_WRITE;
1854	#endif
1855	break;
1856
1857	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1858	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1859	if ( pThis->svga.fEnabled
1860	&& pThis->svga.fConfigured)
1861	{
1862	#if defined(IN_RING3) \|\| defined(IN_RING0)
1863	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1864	/*
1865	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1866	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1867	*/
1868	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1869	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1870	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1871
1872	/* Kick the FIFO thread to start processing commands again. */
1873	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1874	#else
1875	rc = VINF_IOM_R3_IOPORT_WRITE;
1876	#endif
1877	}
1878	/* else nothing to do. */
1879	else
1880	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1881
1882	break;
1883
1884	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1885	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1886	break;
1887
1888	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1889	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1890	pThis->svga.u32GuestId = u32;
1891	break;
1892
1893	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1894	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1895	pThis->svga.u32PitchLock = u32;
1896	/* Should this also update the FIFO pitch lock? Unclear. */
1897	break;
1898
1899	case SVGA_REG_IRQMASK: /* Interrupt mask */
1900	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1901	pThis->svga.u32IrqMask = u32;
1902
1903	/* Irq pending after the above change? */
1904	if (pThis->svga.u32IrqStatus & u32)
1905	{
1906	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1907	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1908	}
1909	else
1910	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1911	break;
1912
1913	/* Mouse cursor support */
1914	case SVGA_REG_CURSOR_ID:
1915	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1916	pThis->svga.uCursorID = u32;
1917	break;
1918
1919	case SVGA_REG_CURSOR_X:
1920	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1921	pThis->svga.uCursorX = u32;
1922	break;
1923
1924	case SVGA_REG_CURSOR_Y:
1925	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1926	pThis->svga.uCursorY = u32;
1927	break;
1928
1929	case SVGA_REG_CURSOR_ON:
1930	#ifdef IN_RING3
1931	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1932	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1933	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1934	#else
1935	rc = VINF_IOM_R3_IOPORT_WRITE;
1936	#endif
1937	break;
1938
1939	/* Legacy multi-monitor support */
1940	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1941	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1942	break;
1943	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1944	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1945	break;
1946	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1948	break;
1949	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1950	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1951	break;
1952	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1953	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1954	break;
1955	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1956	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1957	break;
1958	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1959	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1960	break;
1961	#ifdef VBOX_WITH_VMSVGA3D
1962	/* See "Guest memory regions" below. */
1963	case SVGA_REG_GMR_ID:
1964	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1965	pThis->svga.u32CurrentGMRId = u32;
1966	break;
1967
1968	case SVGA_REG_GMR_DESCRIPTOR:
1969	# ifndef IN_RING3
1970	rc = VINF_IOM_R3_IOPORT_WRITE;
1971	break;
1972	# else /* IN_RING3 */
1973	{
1974	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1975
1976	/* Validate current GMR id. */
1977	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1978	AssertBreak(idGMR < pThis->svga.cGMR);
1979	RT_UNTRUSTED_VALIDATED_FENCE();
1980
1981	/* Free the old GMR if present. */
1982	vmsvgaR3GmrFree(pThisCC, idGMR);
1983
1984	/* Just undefine the GMR? */
1985	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1986	if (GCPhys == 0)
1987	{
1988	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1989	break;
1990	}
1991
1992
1993	/* Never cross a page boundary automatically. */
1994	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1995	uint32_t cPagesTotal = 0;
1996	uint32_t iDesc = 0;
1997	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
1998	uint32_t cLoops = 0;
1999	RTGCPHYS GCPhysBase = GCPhys;
2000	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2001	{
2002	/* Read descriptor. */
2003	SVGAGuestMemDescriptor desc;
2004	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2005	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2006
2007	if (desc.numPages != 0)
2008	{
2009	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2010	cPagesTotal += desc.numPages;
2011	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2012
2013	if ((iDesc & 15) == 0)
2014	{
2015	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2016	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2017	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2018	}
2019
2020	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2021	paDescs[iDesc++].numPages = desc.numPages;
2022
2023	/* Continue with the next descriptor. */
2024	GCPhys += sizeof(desc);
2025	}
2026	else if (desc.ppn == 0)
2027	break; /* terminator */
2028	else /* Pointer to the next physical page of descriptors. */
2029	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2030
2031	cLoops++;
2032	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2033	}
2034
2035	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2036	if (RT_SUCCESS(rc))
2037	{
2038	/* Commit the GMR. */
2039	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2040	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2041	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2042	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2043	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2044	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2045	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2046	}
2047	else
2048	{
2049	RTMemFree(paDescs);
2050	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2051	}
2052	break;
2053	}
2054	# endif /* IN_RING3 */
2055	#endif // VBOX_WITH_VMSVGA3D
2056
2057	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2059	if (pThis->svga.fTraces == u32)
2060	break; /* nothing to do */
2061
2062	#ifdef IN_RING3
2063	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2064	#else
2065	rc = VINF_IOM_R3_IOPORT_WRITE;
2066	#endif
2067	break;
2068
2069	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2070	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2071	break;
2072
2073	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2074	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2075	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2076	break;
2077
2078	case SVGA_REG_FB_START:
2079	case SVGA_REG_MEM_START:
2080	case SVGA_REG_HOST_BITS_PER_PIXEL:
2081	case SVGA_REG_MAX_WIDTH:
2082	case SVGA_REG_MAX_HEIGHT:
2083	case SVGA_REG_VRAM_SIZE:
2084	case SVGA_REG_FB_SIZE:
2085	case SVGA_REG_CAPABILITIES:
2086	case SVGA_REG_MEM_SIZE:
2087	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2088	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2089	case SVGA_REG_BYTES_PER_LINE:
2090	case SVGA_REG_FB_OFFSET:
2091	case SVGA_REG_RED_MASK:
2092	case SVGA_REG_GREEN_MASK:
2093	case SVGA_REG_BLUE_MASK:
2094	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2095	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2096	case SVGA_REG_GMR_MAX_IDS:
2097	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2098	/* Read only - ignore. */
2099	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2100	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2101	break;
2102
2103	default:
2104	{
2105	uint32_t offReg;
2106	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2107	{
2108	RT_UNTRUSTED_VALIDATED_FENCE();
2109	pThis->svga.au32ScratchRegion[offReg] = u32;
2110	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2111	}
2112	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2113	{
2114	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2115	Btw, see rgb_to_pixel32. */
2116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2117	u32 &= 0xff;
2118	RT_UNTRUSTED_VALIDATED_FENCE();
2119	uint32_t uRgb = pThis->last_palette[offReg / 3];
2120	switch (offReg % 3)
2121	{
2122	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2123	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2124	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2125	}
2126	pThis->last_palette[offReg / 3] = uRgb;
2127	}
2128	else
2129	{
2130	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2131	rc = VINF_IOM_R3_IOPORT_WRITE;
2132	#else
2133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2134	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2135	#endif
2136	}
2137	break;
2138	}
2139	}
2140	return rc;
2141	}
2142
2143	/**
2144	* @callback_method_impl{FNIOMIOPORTNEWIN}
2145	*/
2146	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2147	{
2148	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2149	RT_NOREF_PV(pvUser);
2150
2151	/* Only dword accesses. */
2152	if (cb == 4)
2153	{
2154	switch (offPort)
2155	{
2156	case SVGA_INDEX_PORT:
2157	*pu32 = pThis->svga.u32IndexReg;
2158	break;
2159
2160	case SVGA_VALUE_PORT:
2161	return vmsvgaReadPort(pDevIns, pThis, pu32);
2162
2163	case SVGA_BIOS_PORT:
2164	Log(("Ignoring BIOS port read\n"));
2165	*pu32 = 0;
2166	break;
2167
2168	case SVGA_IRQSTATUS_PORT:
2169	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2170	*pu32 = pThis->svga.u32IrqStatus;
2171	break;
2172
2173	default:
2174	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2175	*pu32 = UINT32_MAX;
2176	break;
2177	}
2178	}
2179	else
2180	{
2181	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2182	*pu32 = UINT32_MAX;
2183	}
2184	return VINF_SUCCESS;
2185	}
2186
2187	/**
2188	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2189	*/
2190	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2191	{
2192	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2193	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2194	RT_NOREF_PV(pvUser);
2195
2196	/* Only dword accesses. */
2197	if (cb == 4)
2198	switch (offPort)
2199	{
2200	case SVGA_INDEX_PORT:
2201	pThis->svga.u32IndexReg = u32;
2202	break;
2203
2204	case SVGA_VALUE_PORT:
2205	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2206
2207	case SVGA_BIOS_PORT:
2208	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2209	break;
2210
2211	case SVGA_IRQSTATUS_PORT:
2212	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2213	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2214	/* Clear the irq in case all events have been cleared. */
2215	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2216	{
2217	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2218	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2219	}
2220	break;
2221
2222	default:
2223	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2224	break;
2225	}
2226	else
2227	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2228
2229	return VINF_SUCCESS;
2230	}
2231
2232	#ifdef IN_RING3
2233
2234	# ifdef DEBUG_FIFO_ACCESS
2235	/**
2236	* Handle FIFO memory access.
2237	* @returns VBox status code.
2238	* @param pVM VM handle.
2239	* @param pThis The shared VGA/VMSVGA instance data.
2240	* @param GCPhys The access physical address.
2241	* @param fWriteAccess Read or write access
2242	*/
2243	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2244	{
2245	RT_NOREF(pVM);
2246	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2247	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2248
2249	switch (GCPhysOffset >> 2)
2250	{
2251	case SVGA_FIFO_MIN:
2252	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2253	break;
2254	case SVGA_FIFO_MAX:
2255	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2256	break;
2257	case SVGA_FIFO_NEXT_CMD:
2258	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2259	break;
2260	case SVGA_FIFO_STOP:
2261	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2262	break;
2263	case SVGA_FIFO_CAPABILITIES:
2264	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2265	break;
2266	case SVGA_FIFO_FLAGS:
2267	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2268	break;
2269	case SVGA_FIFO_FENCE:
2270	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2271	break;
2272	case SVGA_FIFO_3D_HWVERSION:
2273	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2274	break;
2275	case SVGA_FIFO_PITCHLOCK:
2276	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2277	break;
2278	case SVGA_FIFO_CURSOR_ON:
2279	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2280	break;
2281	case SVGA_FIFO_CURSOR_X:
2282	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2283	break;
2284	case SVGA_FIFO_CURSOR_Y:
2285	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2286	break;
2287	case SVGA_FIFO_CURSOR_COUNT:
2288	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2289	break;
2290	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2291	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2292	break;
2293	case SVGA_FIFO_RESERVED:
2294	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2295	break;
2296	case SVGA_FIFO_CURSOR_SCREEN_ID:
2297	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2298	break;
2299	case SVGA_FIFO_DEAD:
2300	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2301	break;
2302	case SVGA_FIFO_3D_HWVERSION_REVISED:
2303	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2304	break;
2305	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2306	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2307	break;
2308	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2309	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2310	break;
2311	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2312	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2313	break;
2314	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2315	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2316	break;
2317	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2318	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2319	break;
2320	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2321	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2322	break;
2323	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2324	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2325	break;
2326	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2327	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2328	break;
2329	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2330	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2331	break;
2332	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2333	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2334	break;
2335	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2336	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2337	break;
2338	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2339	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2340	break;
2341	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2342	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2343	break;
2344	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2345	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2346	break;
2347	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2348	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2349	break;
2350	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2351	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2352	break;
2353	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2354	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2355	break;
2356	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2357	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2358	break;
2359	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2360	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2361	break;
2362	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2363	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2364	break;
2365	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2366	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2367	break;
2368	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2369	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2370	break;
2371	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2372	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2373	break;
2374	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2375	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2376	break;
2377	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2378	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2379	break;
2380	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2381	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2382	break;
2383	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2384	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2385	break;
2386	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2387	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2388	break;
2389	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2390	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2391	break;
2392	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2393	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2394	break;
2395	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2396	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2397	break;
2398	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2399	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2400	break;
2401	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2402	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2403	break;
2404	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2405	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2406	break;
2407	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2408	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2409	break;
2410	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2411	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2412	break;
2413	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2414	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2415	break;
2416	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2417	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2418	break;
2419	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2420	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2421	break;
2422	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2423	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2424	break;
2425	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2426	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2427	break;
2428	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2429	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2430	break;
2431	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2432	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2433	break;
2434	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2435	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2436	break;
2437	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2438	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2439	break;
2440	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2441	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2442	break;
2443	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2444	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2445	break;
2446	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2447	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2448	break;
2449	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2450	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2451	break;
2452	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2453	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2454	break;
2455	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2456	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2457	break;
2458	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2459	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2460	break;
2461	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2462	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2463	break;
2464	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2465	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2466	break;
2467	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2468	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2469	break;
2470	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2471	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2472	break;
2473	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2474	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2475	break;
2476	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2477	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2478	break;
2479	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2480	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2481	break;
2482	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2483	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2484	break;
2485	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2486	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2487	break;
2488	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2489	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2490	break;
2491	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2492	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2493	break;
2494	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2495	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2496	break;
2497	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2498	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2499	break;
2500	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2501	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2502	break;
2503	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2504	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2505	break;
2506	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2507	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2508	break;
2509	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2510	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2511	break;
2512	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2513	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2514	break;
2515	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2516	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2517	break;
2518	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2519	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2520	break;
2521	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2522	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2523	break;
2524	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2525	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2526	break;
2527	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2528	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2529	break;
2530	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2531	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2532	break;
2533	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2534	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2535	break;
2536	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2537	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2538	break;
2539	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2540	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2541	break;
2542	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2543	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2544	break;
2545	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2546	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2547	break;
2548	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2549	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2550	break;
2551	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2552	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2553	break;
2554	case SVGA_FIFO_3D_CAPS_LAST:
2555	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2556	break;
2557	case SVGA_FIFO_GUEST_3D_HWVERSION:
2558	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2559	break;
2560	case SVGA_FIFO_FENCE_GOAL:
2561	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2562	break;
2563	case SVGA_FIFO_BUSY:
2564	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2565	break;
2566	default:
2567	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2568	break;
2569	}
2570
2571	return VINF_EM_RAW_EMULATE_INSTR;
2572	}
2573	# endif /* DEBUG_FIFO_ACCESS */
2574
2575	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2576	/**
2577	* HC access handler for the FIFO.
2578	*
2579	* @returns VINF_SUCCESS if the handler have carried out the operation.
2580	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2581	* @param pVM VM Handle.
2582	* @param pVCpu The cross context CPU structure for the calling EMT.
2583	* @param GCPhys The physical address the guest is writing to.
2584	* @param pvPhys The HC mapping of that address.
2585	* @param pvBuf What the guest is reading/writing.
2586	* @param cbBuf How much it's reading/writing.
2587	* @param enmAccessType The access type.
2588	* @param enmOrigin Who is making the access.
2589	* @param pvUser User argument.
2590	*/
2591	static DECLCALLBACK(VBOXSTRICTRC)
2592	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2593	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2594	{
2595	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2596	PVGASTATE pThis = (PVGASTATE)pvUser;
2597	AssertPtr(pThis);
2598
2599	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2600	/*
2601	* Wake up the FIFO thread as it might have work to do now.
2602	*/
2603	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2604	AssertLogRelRC(rc);
2605	# endif
2606
2607	# ifdef DEBUG_FIFO_ACCESS
2608	/*
2609	* When in debug-fifo-access mode, we do not disable the access handler,
2610	* but leave it on as we wish to catch all access.
2611	*/
2612	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2613	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2614	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2615	/*
2616	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2617	*/
2618	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2619	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2620	# endif
2621	if (RT_SUCCESS(rc))
2622	return VINF_PGM_HANDLER_DO_DEFAULT;
2623	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2624	return rc;
2625	}
2626	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2627
2628	#endif /* IN_RING3 */
2629
2630	#ifdef DEBUG_GMR_ACCESS
2631	# ifdef IN_RING3
2632
2633	/**
2634	* HC access handler for the FIFO.
2635	*
2636	* @returns VINF_SUCCESS if the handler have carried out the operation.
2637	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2638	* @param pVM VM Handle.
2639	* @param pVCpu The cross context CPU structure for the calling EMT.
2640	* @param GCPhys The physical address the guest is writing to.
2641	* @param pvPhys The HC mapping of that address.
2642	* @param pvBuf What the guest is reading/writing.
2643	* @param cbBuf How much it's reading/writing.
2644	* @param enmAccessType The access type.
2645	* @param enmOrigin Who is making the access.
2646	* @param pvUser User argument.
2647	*/
2648	static DECLCALLBACK(VBOXSTRICTRC)
2649	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2650	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2651	{
2652	PVGASTATE pThis = (PVGASTATE)pvUser;
2653	Assert(pThis);
2654	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2655	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2656
2657	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2658
2659	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2660	{
2661	PGMR pGMR = &pSVGAState->paGMR[i];
2662
2663	if (pGMR->numDescriptors)
2664	{
2665	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2666	{
2667	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2668	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2669	{
2670	/*
2671	* Turn off the write handler for this particular page and make it R/W.
2672	* Then return telling the caller to restart the guest instruction.
2673	*/
2674	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2675	AssertRC(rc);
2676	return VINF_PGM_HANDLER_DO_DEFAULT;
2677	}
2678	}
2679	}
2680	}
2681
2682	return VINF_PGM_HANDLER_DO_DEFAULT;
2683	}
2684
2685	/** Callback handler for VMR3ReqCallWaitU */
2686	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2687	{
2688	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2689	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2690	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2691	int rc;
2692
2693	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2694	{
2695	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2696	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2697	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2698	AssertRC(rc);
2699	}
2700	return VINF_SUCCESS;
2701	}
2702
2703	/** Callback handler for VMR3ReqCallWaitU */
2704	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2705	{
2706	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2707	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2708	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2709
2710	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2711	{
2712	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2713	AssertRC(rc);
2714	}
2715	return VINF_SUCCESS;
2716	}
2717
2718	/** Callback handler for VMR3ReqCallWaitU */
2719	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2720	{
2721	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2722
2723	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2724	{
2725	PGMR pGMR = &pSVGAState->paGMR[i];
2726
2727	if (pGMR->numDescriptors)
2728	{
2729	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2730	{
2731	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2732	AssertRC(rc);
2733	}
2734	}
2735	}
2736	return VINF_SUCCESS;
2737	}
2738
2739	# endif /* IN_RING3 */
2740	#endif /* DEBUG_GMR_ACCESS */
2741
2742	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2743
2744	#ifdef IN_RING3
2745
2746
2747	/**
2748	* Common worker for changing the pointer shape.
2749	*
2750	* @param pThisCC The VGA/VMSVGA state for ring-3.
2751	* @param pSVGAState The VMSVGA ring-3 instance data.
2752	* @param fAlpha Whether there is alpha or not.
2753	* @param xHot Hotspot x coordinate.
2754	* @param yHot Hotspot y coordinate.
2755	* @param cx Width.
2756	* @param cy Height.
2757	* @param pbData Heap copy of the cursor data. Consumed.
2758	* @param cbData The size of the data.
2759	*/
2760	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2761	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2762	{
2763	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2764	# ifdef LOG_ENABLED
2765	if (LogIs2Enabled())
2766	{
2767	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2768	if (!fAlpha)
2769	{
2770	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2771	for (uint32_t y = 0; y < cy; y++)
2772	{
2773	Log2(("%3u:", y));
2774	uint8_t const pbLine = &pbData[y cbAndLine];
2775	for (uint32_t x = 0; x < cx; x += 8)
2776	{
2777	uint8_t b = pbLine[x / 8];
2778	char szByte[12];
2779	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2780	szByte[1] = b & 0x40 ? '*' : ' ';
2781	szByte[2] = b & 0x20 ? '*' : ' ';
2782	szByte[3] = b & 0x10 ? '*' : ' ';
2783	szByte[4] = b & 0x08 ? '*' : ' ';
2784	szByte[5] = b & 0x04 ? '*' : ' ';
2785	szByte[6] = b & 0x02 ? '*' : ' ';
2786	szByte[7] = b & 0x01 ? '*' : ' ';
2787	szByte[8] = '\0';
2788	Log2(("%s", szByte));
2789	}
2790	Log2(("\n"));
2791	}
2792	}
2793
2794	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2795	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2796	for (uint32_t y = 0; y < cy; y++)
2797	{
2798	Log2(("%3u:", y));
2799	uint32_t const pu32Line = &pu32Xor[y cx];
2800	for (uint32_t x = 0; x < cx; x++)
2801	Log2((" %08x", pu32Line[x]));
2802	Log2(("\n"));
2803	}
2804	}
2805	# endif
2806
2807	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2808	AssertRC(rc);
2809
2810	if (pSVGAState->Cursor.fActive)
2811	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
2812
2813	pSVGAState->Cursor.fActive = true;
2814	pSVGAState->Cursor.xHotspot = xHot;
2815	pSVGAState->Cursor.yHotspot = yHot;
2816	pSVGAState->Cursor.width = cx;
2817	pSVGAState->Cursor.height = cy;
2818	pSVGAState->Cursor.cbData = cbData;
2819	pSVGAState->Cursor.pData = pbData;
2820	}
2821
2822
2823	/**
2824	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2825	*
2826	* @param pThis The shared VGA/VMSVGA state.
2827	* @param pThisCC The VGA/VMSVGA state for ring-3.
2828	* @param pSVGAState The VMSVGA ring-3 instance data.
2829	* @param pCursor The cursor.
2830	* @param pbSrcAndMask The AND mask.
2831	* @param cbSrcAndLine The scanline length of the AND mask.
2832	* @param pbSrcXorMask The XOR mask.
2833	* @param cbSrcXorLine The scanline length of the XOR mask.
2834	*/
2835	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2836	SVGAFifoCmdDefineCursor const *pCursor,
2837	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2838	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2839	{
2840	uint32_t const cx = pCursor->width;
2841	uint32_t const cy = pCursor->height;
2842
2843	/*
2844	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2845	* The AND data uses 8-bit aligned scanlines.
2846	* The XOR data must be starting on a 32-bit boundrary.
2847	*/
2848	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2849	uint32_t cbDstAndMask = cbDstAndLine * cy;
2850	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2851	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2852
2853	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2854	AssertReturnVoid(pbCopy);
2855
2856	/* Convert the AND mask. */
2857	uint8_t *pbDst = pbCopy;
2858	uint8_t const *pbSrc = pbSrcAndMask;
2859	switch (pCursor->andMaskDepth)
2860	{
2861	case 1:
2862	if (cbSrcAndLine == cbDstAndLine)
2863	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2864	else
2865	{
2866	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2867	for (uint32_t y = 0; y < cy; y++)
2868	{
2869	memcpy(pbDst, pbSrc, cbDstAndLine);
2870	pbDst += cbDstAndLine;
2871	pbSrc += cbSrcAndLine;
2872	}
2873	}
2874	break;
2875	/* Should take the XOR mask into account for the multi-bit AND mask. */
2876	case 8:
2877	for (uint32_t y = 0; y < cy; y++)
2878	{
2879	for (uint32_t x = 0; x < cx; )
2880	{
2881	uint8_t bDst = 0;
2882	uint8_t fBit = 0x80;
2883	do
2884	{
2885	uintptr_t const idxPal = pbSrc[x] * 3;
2886	if ((( pThis->last_palette[idxPal]
2887	\| (pThis->last_palette[idxPal] >> 8)
2888	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2889	bDst \|= fBit;
2890	fBit >>= 1;
2891	x++;
2892	} while (x < cx && (x & 7));
2893	pbDst[(x - 1) / 8] = bDst;
2894	}
2895	pbDst += cbDstAndLine;
2896	pbSrc += cbSrcAndLine;
2897	}
2898	break;
2899	case 15:
2900	for (uint32_t y = 0; y < cy; y++)
2901	{
2902	for (uint32_t x = 0; x < cx; )
2903	{
2904	uint8_t bDst = 0;
2905	uint8_t fBit = 0x80;
2906	do
2907	{
2908	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2909	bDst \|= fBit;
2910	fBit >>= 1;
2911	x++;
2912	} while (x < cx && (x & 7));
2913	pbDst[(x - 1) / 8] = bDst;
2914	}
2915	pbDst += cbDstAndLine;
2916	pbSrc += cbSrcAndLine;
2917	}
2918	break;
2919	case 16:
2920	for (uint32_t y = 0; y < cy; y++)
2921	{
2922	for (uint32_t x = 0; x < cx; )
2923	{
2924	uint8_t bDst = 0;
2925	uint8_t fBit = 0x80;
2926	do
2927	{
2928	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2929	bDst \|= fBit;
2930	fBit >>= 1;
2931	x++;
2932	} while (x < cx && (x & 7));
2933	pbDst[(x - 1) / 8] = bDst;
2934	}
2935	pbDst += cbDstAndLine;
2936	pbSrc += cbSrcAndLine;
2937	}
2938	break;
2939	case 24:
2940	for (uint32_t y = 0; y < cy; y++)
2941	{
2942	for (uint32_t x = 0; x < cx; )
2943	{
2944	uint8_t bDst = 0;
2945	uint8_t fBit = 0x80;
2946	do
2947	{
2948	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2949	bDst \|= fBit;
2950	fBit >>= 1;
2951	x++;
2952	} while (x < cx && (x & 7));
2953	pbDst[(x - 1) / 8] = bDst;
2954	}
2955	pbDst += cbDstAndLine;
2956	pbSrc += cbSrcAndLine;
2957	}
2958	break;
2959	case 32:
2960	for (uint32_t y = 0; y < cy; y++)
2961	{
2962	for (uint32_t x = 0; x < cx; )
2963	{
2964	uint8_t bDst = 0;
2965	uint8_t fBit = 0x80;
2966	do
2967	{
2968	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2969	bDst \|= fBit;
2970	fBit >>= 1;
2971	x++;
2972	} while (x < cx && (x & 7));
2973	pbDst[(x - 1) / 8] = bDst;
2974	}
2975	pbDst += cbDstAndLine;
2976	pbSrc += cbSrcAndLine;
2977	}
2978	break;
2979	default:
2980	RTMemFreeZ(pbCopy, cbCopy);
2981	AssertFailedReturnVoid();
2982	}
2983
2984	/* Convert the XOR mask. */
2985	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
2986	pbSrc = pbSrcXorMask;
2987	switch (pCursor->xorMaskDepth)
2988	{
2989	case 1:
2990	for (uint32_t y = 0; y < cy; y++)
2991	{
2992	for (uint32_t x = 0; x < cx; )
2993	{
2994	/* most significant bit is the left most one. */
2995	uint8_t bSrc = pbSrc[x / 8];
2996	do
2997	{
2998	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
2999	bSrc <<= 1;
3000	x++;
3001	} while ((x & 7) && x < cx);
3002	}
3003	pbSrc += cbSrcXorLine;
3004	}
3005	break;
3006	case 8:
3007	for (uint32_t y = 0; y < cy; y++)
3008	{
3009	for (uint32_t x = 0; x < cx; x++)
3010	{
3011	uint32_t u = pThis->last_palette[pbSrc[x]];
3012	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3013	}
3014	pbSrc += cbSrcXorLine;
3015	}
3016	break;
3017	case 15: /* Src: RGB-5-5-5 */
3018	for (uint32_t y = 0; y < cy; y++)
3019	{
3020	for (uint32_t x = 0; x < cx; x++)
3021	{
3022	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3023	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3024	((uValue >> 5) & 0x1f) << 3,
3025	((uValue >> 10) & 0x1f) << 3, 0);
3026	}
3027	pbSrc += cbSrcXorLine;
3028	}
3029	break;
3030	case 16: /* Src: RGB-5-6-5 */
3031	for (uint32_t y = 0; y < cy; y++)
3032	{
3033	for (uint32_t x = 0; x < cx; x++)
3034	{
3035	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3036	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3037	((uValue >> 5) & 0x3f) << 2,
3038	((uValue >> 11) & 0x1f) << 3, 0);
3039	}
3040	pbSrc += cbSrcXorLine;
3041	}
3042	break;
3043	case 24:
3044	for (uint32_t y = 0; y < cy; y++)
3045	{
3046	for (uint32_t x = 0; x < cx; x++)
3047	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3048	pbSrc += cbSrcXorLine;
3049	}
3050	break;
3051	case 32:
3052	for (uint32_t y = 0; y < cy; y++)
3053	{
3054	for (uint32_t x = 0; x < cx; x++)
3055	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3056	pbSrc += cbSrcXorLine;
3057	}
3058	break;
3059	default:
3060	RTMemFreeZ(pbCopy, cbCopy);
3061	AssertFailedReturnVoid();
3062	}
3063
3064	/*
3065	* Pass it to the frontend/whatever.
3066	*/
3067	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3068	}
3069
3070
3071	/**
3072	* Worker for vmsvgaR3FifoThread that handles an external command.
3073	*
3074	* @param pDevIns The device instance.
3075	* @param pThis The shared VGA/VMSVGA instance data.
3076	* @param pThisCC The VGA/VMSVGA state for ring-3.
3077	*/
3078	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3079	{
3080	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3081	switch (pThis->svga.u8FIFOExtCommand)
3082	{
3083	case VMSVGA_FIFO_EXTCMD_RESET:
3084	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3085	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3086	# ifdef VBOX_WITH_VMSVGA3D
3087	if (pThis->svga.f3DEnabled)
3088	{
3089	/* The 3d subsystem must be reset from the fifo thread. */
3090	vmsvga3dReset(pThisCC);
3091	}
3092	# endif
3093	break;
3094
3095	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3096	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3097	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3098	# ifdef VBOX_WITH_VMSVGA3D
3099	if (pThis->svga.f3DEnabled)
3100	{
3101	/* The 3d subsystem must be shut down from the fifo thread. */
3102	vmsvga3dTerminate(pThisCC);
3103	}
3104	# endif
3105	break;
3106
3107	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3108	{
3109	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3110	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3111	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3112	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3113	# ifdef VBOX_WITH_VMSVGA3D
3114	if (pThis->svga.f3DEnabled)
3115	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3116	# endif
3117	break;
3118	}
3119
3120	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3121	{
3122	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3123	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3124	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3125	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3126	# ifdef VBOX_WITH_VMSVGA3D
3127	if (pThis->svga.f3DEnabled)
3128	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3129	# endif
3130	break;
3131	}
3132
3133	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3134	{
3135	# ifdef VBOX_WITH_VMSVGA3D
3136	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3137	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3138	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3139	# endif
3140	break;
3141	}
3142
3143
3144	default:
3145	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3146	break;
3147	}
3148
3149	/*
3150	* Signal the end of the external command.
3151	*/
3152	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3153	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3154	ASMMemoryFence(); /* paranoia^2 */
3155	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3156	AssertLogRelRC(rc);
3157	}
3158
3159	/**
3160	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3161	* doing a job on the FIFO thread (even when it's officially suspended).
3162	*
3163	* @returns VBox status code (fully asserted).
3164	* @param pDevIns The device instance.
3165	* @param pThis The shared VGA/VMSVGA instance data.
3166	* @param pThisCC The VGA/VMSVGA state for ring-3.
3167	* @param uExtCmd The command to execute on the FIFO thread.
3168	* @param pvParam Pointer to command parameters.
3169	* @param cMsWait The time to wait for the command, given in
3170	* milliseconds.
3171	*/
3172	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3173	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3174	{
3175	Assert(cMsWait >= RT_MS_1SEC * 5);
3176	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3177	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3178
3179	int rc;
3180	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3181	PDMTHREADSTATE enmState = pThread->enmState;
3182	if (enmState == PDMTHREADSTATE_SUSPENDED)
3183	{
3184	/*
3185	* The thread is suspended, we have to temporarily wake it up so it can
3186	* perform the task.
3187	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3188	*/
3189	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3190	/* Post the request. */
3191	pThis->svga.fFifoExtCommandWakeup = true;
3192	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3193	pThis->svga.u8FIFOExtCommand = uExtCmd;
3194	ASMMemoryFence(); /* paranoia^3 */
3195
3196	/* Resume the thread. */
3197	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3198	AssertLogRelRC(rc);
3199	if (RT_SUCCESS(rc))
3200	{
3201	/* Wait. Take care in case the semaphore was already posted (same as below). */
3202	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3203	if ( rc == VINF_SUCCESS
3204	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3205	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3206	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3207	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3208
3209	/* suspend the thread */
3210	pThis->svga.fFifoExtCommandWakeup = false;
3211	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3212	AssertLogRelRC(rc2);
3213	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3214	rc = rc2;
3215	}
3216	pThis->svga.fFifoExtCommandWakeup = false;
3217	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3218	}
3219	else if (enmState == PDMTHREADSTATE_RUNNING)
3220	{
3221	/*
3222	* The thread is running, should only happen during reset and vmsvga3dsfc.
3223	* We ASSUME not racing code here, both wrt thread state and ext commands.
3224	*/
3225	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3226	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3227
3228	/* Post the request. */
3229	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3230	pThis->svga.u8FIFOExtCommand = uExtCmd;
3231	ASMMemoryFence(); /* paranoia^2 */
3232	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3233	AssertLogRelRC(rc);
3234
3235	/* Wait. Take care in case the semaphore was already posted (same as above). */
3236	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3237	if ( rc == VINF_SUCCESS
3238	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3239	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3240	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3241	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3242
3243	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3244	}
3245	else
3246	{
3247	/*
3248	* Something is wrong with the thread!
3249	*/
3250	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3251	rc = VERR_INVALID_STATE;
3252	}
3253	return rc;
3254	}
3255
3256
3257	/**
3258	* Marks the FIFO non-busy, notifying any waiting EMTs.
3259	*
3260	* @param pDevIns The device instance.
3261	* @param pThis The shared VGA/VMSVGA instance data.
3262	* @param pThisCC The VGA/VMSVGA state for ring-3.
3263	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3264	* @param offFifoMin The start byte offset of the command FIFO.
3265	*/
3266	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3267	{
3268	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3269	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3270	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3271
3272	/* Wake up any waiting EMTs. */
3273	if (pSVGAState->cBusyDelayedEmts > 0)
3274	{
3275	# ifdef VMSVGA_USE_EMT_HALT_CODE
3276	PVM pVM = PDMDevHlpGetVM(pDevIns);
3277	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3278	if (idCpu != NIL_VMCPUID)
3279	{
3280	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3281	while (idCpu-- > 0)
3282	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3283	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3284	}
3285	# else
3286	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3287	AssertRC(rc2);
3288	# endif
3289	}
3290	}
3291
3292	/**
3293	* Reads (more) payload into the command buffer.
3294	*
3295	* @returns pbBounceBuf on success
3296	* @retval (void *)1 if the thread was requested to stop.
3297	* @retval NULL on FIFO error.
3298	*
3299	* @param cbPayloadReq The number of bytes of payload requested.
3300	* @param pFIFO The FIFO.
3301	* @param offCurrentCmd The FIFO byte offset of the current command.
3302	* @param offFifoMin The start byte offset of the command FIFO.
3303	* @param offFifoMax The end byte offset of the command FIFO.
3304	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3305	* always sufficient size.
3306	* @param pcbAlreadyRead How much payload we've already read into the bounce
3307	* buffer. (We will NEVER re-read anything.)
3308	* @param pThread The calling PDM thread handle.
3309	* @param pThis The shared VGA/VMSVGA instance data.
3310	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3311	* statistics collection.
3312	* @param pDevIns The device instance.
3313	*/
3314	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3315	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3316	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3317	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3318	{
3319	Assert(pbBounceBuf);
3320	Assert(pcbAlreadyRead);
3321	Assert(offFifoMin < offFifoMax);
3322	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3323	Assert(offFifoMax <= pThis->svga.cbFIFO);
3324
3325	/*
3326	* Check if the requested payload size has already been satisfied .
3327	* .
3328	* When called to read more, the caller is responsible for making sure the .
3329	* new command size (cbRequsted) never is smaller than what has already .
3330	* been read.
3331	*/
3332	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3333	if (cbPayloadReq <= cbAlreadyRead)
3334	{
3335	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3336	return pbBounceBuf;
3337	}
3338
3339	/*
3340	* Commands bigger than the fifo buffer are invalid.
3341	*/
3342	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3343	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3344	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3345	NULL);
3346
3347	/*
3348	* Move offCurrentCmd past the command dword.
3349	*/
3350	offCurrentCmd += sizeof(uint32_t);
3351	if (offCurrentCmd >= offFifoMax)
3352	offCurrentCmd = offFifoMin;
3353
3354	/*
3355	* Do we have sufficient payload data available already?
3356	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3357	*/
3358	uint32_t cbAfter, cbBefore;
3359	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3360	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3361	if (offNextCmd >= offCurrentCmd)
3362	{
3363	if (RT_LIKELY(offNextCmd < offFifoMax))
3364	cbAfter = offNextCmd - offCurrentCmd;
3365	else
3366	{
3367	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3368	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3369	offNextCmd, offFifoMin, offFifoMax));
3370	cbAfter = offFifoMax - offCurrentCmd;
3371	}
3372	cbBefore = 0;
3373	}
3374	else
3375	{
3376	cbAfter = offFifoMax - offCurrentCmd;
3377	if (offNextCmd >= offFifoMin)
3378	cbBefore = offNextCmd - offFifoMin;
3379	else
3380	{
3381	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3382	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3383	offNextCmd, offFifoMin, offFifoMax));
3384	cbBefore = 0;
3385	}
3386	}
3387	if (cbAfter + cbBefore < cbPayloadReq)
3388	{
3389	/*
3390	* Insufficient, must wait for it to arrive.
3391	*/
3392	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3393	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3394	for (uint32_t i = 0;; i++)
3395	{
3396	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3397	{
3398	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3399	return (void *)(uintptr_t)1;
3400	}
3401	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3402	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3403
3404	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3405
3406	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3407	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3408	if (offNextCmd >= offCurrentCmd)
3409	{
3410	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3411	cbBefore = 0;
3412	}
3413	else
3414	{
3415	cbAfter = offFifoMax - offCurrentCmd;
3416	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3417	}
3418
3419	if (cbAfter + cbBefore >= cbPayloadReq)
3420	break;
3421	}
3422	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3423	}
3424
3425	/*
3426	* Copy out the memory and update what pcbAlreadyRead points to.
3427	*/
3428	if (cbAfter >= cbPayloadReq)
3429	memcpy(pbBounceBuf + cbAlreadyRead,
3430	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3431	cbPayloadReq - cbAlreadyRead);
3432	else
3433	{
3434	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3435	if (cbAlreadyRead < cbAfter)
3436	{
3437	memcpy(pbBounceBuf + cbAlreadyRead,
3438	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3439	cbAfter - cbAlreadyRead);
3440	cbAlreadyRead = cbAfter;
3441	}
3442	memcpy(pbBounceBuf + cbAlreadyRead,
3443	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3444	cbPayloadReq - cbAlreadyRead);
3445	}
3446	*pcbAlreadyRead = cbPayloadReq;
3447	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3448	return pbBounceBuf;
3449	}
3450
3451
3452	/**
3453	* Sends cursor position and visibility information from the FIFO to the front-end.
3454	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3455	*/
3456	static uint32_t
3457	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3458	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3459	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3460	{
3461	/*
3462	* Check if the cursor update counter has changed and try get a stable
3463	* set of values if it has. This is race-prone, especially consindering
3464	* the screen ID, but little we can do about that.
3465	*/
3466	uint32_t x, y, fVisible, idScreen;
3467	for (uint32_t i = 0; ; i++)
3468	{
3469	x = pFIFO[SVGA_FIFO_CURSOR_X];
3470	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3471	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3472	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3473	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3474	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3475	\|\| i > 3)
3476	break;
3477	if (i == 0)
3478	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3479	ASMNopPause();
3480	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3481	}
3482
3483	/*
3484	* Check if anything has changed, as calling into pDrv is not light-weight.
3485	*/
3486	if ( *pxLast == x
3487	&& *pyLast == y
3488	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3489	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3490	else
3491	{
3492	/*
3493	* Detected changes.
3494	*
3495	* We handle global, not per-screen visibility information by sending
3496	* pfnVBVAMousePointerShape without shape data.
3497	*/
3498	*pxLast = x;
3499	*pyLast = y;
3500	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3501	if (idScreen != SVGA_ID_INVALID)
3502	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3503	else if (*pfLastVisible != fVisible)
3504	{
3505	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3506	*pfLastVisible = fVisible;
3507	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3508	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3509	}
3510	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3511	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3512	}
3513
3514	/*
3515	* Update done. Signal this to the guest.
3516	*/
3517	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3518
3519	return uCursorUpdateCount;
3520	}
3521
3522
3523	/**
3524	* Checks if there is work to be done, either cursor updating or FIFO commands.
3525	*
3526	* @returns true if pending work, false if not.
3527	* @param pFIFO The FIFO to examine.
3528	* @param uLastCursorCount The last cursor update counter value.
3529	*/
3530	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3531	{
3532	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3533	return true;
3534
3535	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3536	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3537	return true;
3538
3539	return false;
3540	}
3541
3542
3543	/**
3544	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3545	*
3546	* @param pDevIns The device instance.
3547	* @param pThis The shared VGA/VMSVGA instance data.
3548	* @param pThisCC The VGA/VMSVGA state for ring-3.
3549	*/
3550	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3551	{
3552	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3553	to recheck it before doing the signalling. */
3554	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3555	AssertReturnVoid(pFIFO);
3556	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3557	&& pThis->svga.fFIFOThreadSleeping)
3558	{
3559	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3560	AssertRC(rc);
3561	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3562	}
3563	}
3564
3565
3566	/**
3567	* Called by the FIFO thread to process pending actions.
3568	*
3569	* @param pDevIns The device instance.
3570	* @param pThis The shared VGA/VMSVGA instance data.
3571	* @param pThisCC The VGA/VMSVGA state for ring-3.
3572	*/
3573	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3574	{
3575	RT_NOREF(pDevIns);
3576
3577	/* Currently just mode changes. */
3578	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3579	{
3580	vmsvgaR3ChangeMode(pThis, pThisCC);
3581	# ifdef VBOX_WITH_VMSVGA3D
3582	if (pThisCC->svga.p3dState != NULL)
3583	vmsvga3dChangeMode(pThisCC);
3584	# endif
3585	}
3586	}
3587
3588
3589	/*
3590	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3591	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3592	*/
3593	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3594	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3595	*
3596	* Will break out of the switch on failure.
3597	* Will restart and quit the loop if the thread was requested to stop.
3598	*
3599	* @param a_PtrVar Request variable pointer.
3600	* @param a_Type Request typedef (not pointer) for casting.
3601	* @param a_cbPayloadReq How much payload to fetch.
3602	* @remarks Accesses a bunch of variables in the current scope!
3603	*/
3604	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3605	if (1) { \
3606	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3607	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3608	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3609	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3610	} else do {} while (0)
3611	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3612	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3613	* buffer after figuring out the actual command size.
3614	*
3615	* Will break out of the switch on failure.
3616	*
3617	* @param a_PtrVar Request variable pointer.
3618	* @param a_Type Request typedef (not pointer) for casting.
3619	* @param a_cbPayloadReq How much payload to fetch.
3620	* @remarks Accesses a bunch of variables in the current scope!
3621	*/
3622	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3623	if (1) { \
3624	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3625	} else do {} while (0)
3626
3627	/**
3628	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3629	*/
3630	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3631	{
3632	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3633	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3634	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3635	int rc;
3636
3637	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3638	return VINF_SUCCESS;
3639
3640	/*
3641	* Special mode where we only execute an external command and the go back
3642	* to being suspended. Currently, all ext cmds ends up here, with the reset
3643	* one also being eligble for runtime execution further down as well.
3644	*/
3645	if (pThis->svga.fFifoExtCommandWakeup)
3646	{
3647	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3648	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3649	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3650	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3651	else
3652	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3653	return VINF_SUCCESS;
3654	}
3655
3656
3657	/*
3658	* Signal the semaphore to make sure we don't wait for 250ms after a
3659	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3660	*/
3661	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3662
3663	/*
3664	* Allocate a bounce buffer for command we get from the FIFO.
3665	* (All code must return via the end of the function to free this buffer.)
3666	*/
3667	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3668	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3669
3670	/*
3671	* Polling/sleep interval config.
3672	*
3673	* We wait for an a short interval if the guest has recently given us work
3674	* to do, but the interval increases the longer we're kept idle. Once we've
3675	* reached the refresh timer interval, we'll switch to extended waits,
3676	* depending on it or the guest to kick us into action when needed.
3677	*
3678	* Should the refresh time go fishing, we'll just continue increasing the
3679	* sleep length till we reaches the 250 ms max after about 16 seconds.
3680	*/
3681	RTMSINTERVAL const cMsMinSleep = 16;
3682	RTMSINTERVAL const cMsIncSleep = 2;
3683	RTMSINTERVAL const cMsMaxSleep = 250;
3684	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3685	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3686
3687	/*
3688	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3689	*
3690	* Initialize with values that will detect an update from the guest.
3691	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3692	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3693	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3694	*/
3695	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3696	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3697	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3698	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3699	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3700
3701	/*
3702	* The FIFO loop.
3703	*/
3704	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3705	bool fBadOrDisabledFifo = false;
3706	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3707	{
3708	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3709	/*
3710	* Should service the run loop every so often.
3711	*/
3712	if (pThis->svga.f3DEnabled)
3713	vmsvga3dCocoaServiceRunLoop();
3714	# endif
3715
3716	/* First check any pending actions. */
3717	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3718
3719	/*
3720	* Unless there's already work pending, go to sleep for a short while.
3721	* (See polling/sleep interval config above.)
3722	*/
3723	if ( fBadOrDisabledFifo
3724	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3725	{
3726	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3727	Assert(pThis->cMilliesRefreshInterval > 0);
3728	if (cMsSleep < pThis->cMilliesRefreshInterval)
3729	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3730	else
3731	{
3732	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3733	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3734	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3735	# endif
3736	if ( !fBadOrDisabledFifo
3737	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3738	rc = VINF_SUCCESS;
3739	else
3740	{
3741	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3742	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3743	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3744	}
3745	}
3746	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3747	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3748	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3749	{
3750	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3751	break;
3752	}
3753	}
3754	else
3755	rc = VINF_SUCCESS;
3756	fBadOrDisabledFifo = false;
3757	if (rc == VERR_TIMEOUT)
3758	{
3759	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3760	{
3761	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3762	continue;
3763	}
3764	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3765
3766	Log(("vmsvgaR3FifoLoop: timeout\n"));
3767	}
3768	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3769	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3770	cMsSleep = cMsMinSleep;
3771
3772	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3773	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3774	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3775
3776	/*
3777	* Handle external commands (currently only reset).
3778	*/
3779	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3780	{
3781	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3782	continue;
3783	}
3784
3785	/*
3786	* The device must be enabled and configured.
3787	*/
3788	if ( !pThis->svga.fEnabled
3789	\|\| !pThis->svga.fConfigured)
3790	{
3791	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3792	fBadOrDisabledFifo = true;
3793	cMsSleep = cMsMaxSleep; /* cheat */
3794	continue;
3795	}
3796
3797	/*
3798	* Get and check the min/max values. We ASSUME that they will remain
3799	* unchanged while we process requests. A further ASSUMPTION is that
3800	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3801	* we don't read it back while in the loop.
3802	*/
3803	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3804	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3805	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3806	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3807	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3808	\|\| offFifoMax <= offFifoMin
3809	\|\| offFifoMax > pThis->svga.cbFIFO
3810	\|\| (offFifoMax & 3) != 0
3811	\|\| (offFifoMin & 3) != 0
3812	\|\| offCurrentCmd < offFifoMin
3813	\|\| offCurrentCmd > offFifoMax))
3814	{
3815	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3816	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3817	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3818	fBadOrDisabledFifo = true;
3819	continue;
3820	}
3821	RT_UNTRUSTED_VALIDATED_FENCE();
3822	if (RT_UNLIKELY(offCurrentCmd & 3))
3823	{
3824	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3825	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3826	offCurrentCmd &= ~UINT32_C(3);
3827	}
3828
3829	/*
3830	* Update the cursor position before we start on the FIFO commands.
3831	*/
3832	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3833	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3834	{
3835	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3836	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3837	{ /* halfways likely */ }
3838	else
3839	{
3840	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3841	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3842	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3843	}
3844	}
3845
3846	/*
3847	* Mark the FIFO as busy.
3848	*/
3849	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
3850	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3851	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3852
3853	/*
3854	* Execute all queued FIFO commands.
3855	* Quit if pending external command or changes in the thread state.
3856	*/
3857	bool fDone = false;
3858	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3859	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3860	{
3861	uint32_t cbPayload = 0;
3862	uint32_t u32IrqStatus = 0;
3863
3864	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3865
3866	/* First check any pending actions. */
3867	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3868
3869	/* Check for pending external commands (reset). */
3870	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3871	break;
3872
3873	/*
3874	* Process the command.
3875	*/
3876	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3877	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3878	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3879	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3880	switch (enmCmdId)
3881	{
3882	case SVGA_CMD_INVALID_CMD:
3883	/* Nothing to do. */
3884	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3885	break;
3886
3887	case SVGA_CMD_FENCE:
3888	{
3889	SVGAFifoCmdFence *pCmdFence;
3890	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3891	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3892	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3893	{
3894	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3895	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3896
3897	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3898	{
3899	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3900	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3901	}
3902	else
3903	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3904	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3905	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3906	{
3907	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3908	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3909	}
3910	}
3911	else
3912	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3913	break;
3914	}
3915	case SVGA_CMD_UPDATE:
3916	case SVGA_CMD_UPDATE_VERBOSE:
3917	{
3918	SVGAFifoCmdUpdate *pUpdate;
3919	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3920	if (enmCmdId == SVGA_CMD_UPDATE)
3921	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3922	else
3923	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3924	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3925	/** @todo Multiple screens? */
3926	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3927	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3928	break;
3929	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3930	break;
3931	}
3932
3933	case SVGA_CMD_DEFINE_CURSOR:
3934	{
3935	/* Followed by bitmap data. */
3936	SVGAFifoCmdDefineCursor *pCursor;
3937	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3938	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3939
3940	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3941	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3942	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3943	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3944	AssertBreak(pCursor->andMaskDepth <= 32);
3945	AssertBreak(pCursor->xorMaskDepth <= 32);
3946	RT_UNTRUSTED_VALIDATED_FENCE();
3947
3948	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3949	uint32_t cbAndMask = cbAndLine * pCursor->height;
3950	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3951	uint32_t cbXorMask = cbXorLine * pCursor->height;
3952	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3953
3954	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3955	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3956	break;
3957	}
3958
3959	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3960	{
3961	/* Followed by bitmap data. */
3962	uint32_t cbCursorShape, cbAndMask;
3963	uint8_t *pCursorCopy;
3964	uint32_t cbCmd;
3965
3966	SVGAFifoCmdDefineAlphaCursor *pCursor;
3967	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3968	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3969
3970	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3971
3972	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3973	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3974	RT_UNTRUSTED_VALIDATED_FENCE();
3975
3976	/* Refetch the bitmap data as well. */
3977	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3978	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3979	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3980
3981	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3982	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3983	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3984	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3985
3986	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3987	AssertPtrBreak(pCursorCopy);
3988
3989	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3990	memset(pCursorCopy, 0xff, cbAndMask);
3991	/* Colour data */
3992	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3993
3994	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3995	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3996	break;
3997	}
3998
3999	case SVGA_CMD_MOVE_CURSOR:
4000	{
4001	/* Deprecated; there should be no driver which requires this command. However, if
4002	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4003	* alignment.
4004	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4005	*/
4006	SVGAFifoCmdMoveCursor *pMoveCursor;
4007	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
4008	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
4009
4010	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
4011	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4012	break;
4013	}
4014
4015	case SVGA_CMD_DISPLAY_CURSOR:
4016	{
4017	/* Deprecated; there should be no driver which requires this command. However, if
4018	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4019	* alignment.
4020	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4021	*/
4022	SVGAFifoCmdDisplayCursor *pDisplayCursor;
4023	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
4024	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
4025
4026	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
4027	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4028	break;
4029	}
4030
4031	case SVGA_CMD_RECT_FILL:
4032	{
4033	SVGAFifoCmdRectFill *pRectFill;
4034	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectFill, SVGAFifoCmdRectFill, sizeof(*pRectFill));
4035	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectFill);
4036
4037	Log(("vmsvgaR3FifoLoop: RECT FILL %08X @ %d,%d (%dx%d)\n", pRectFill->pixel, pRectFill->destX, pRectFill->destY, pRectFill->width, pRectFill->height));
4038	LogRelMax(4, ("Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4039	break;
4040	}
4041
4042	case SVGA_CMD_RECT_COPY:
4043	{
4044	SVGAFifoCmdRectCopy *pRectCopy;
4045	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectCopy, SVGAFifoCmdRectCopy, sizeof(*pRectCopy));
4046	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectCopy);
4047
4048	Log(("vmsvgaR3FifoLoop: RECT COPY %d,%d -> %d,%d (%dx%d)\n", pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height));
4049	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4050	AssertPtrBreak(pScreen);
4051
4052	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4053	AssertBreak(pRectCopy->srcX < pThis->svga.u32MaxWidth);
4054	AssertBreak(pRectCopy->destX < pThis->svga.u32MaxWidth);
4055	AssertBreak(pRectCopy->width < pThis->svga.u32MaxWidth);
4056	AssertBreak(pRectCopy->srcY < pThis->svga.u32MaxHeight);
4057	AssertBreak(pRectCopy->destY < pThis->svga.u32MaxHeight);
4058	AssertBreak(pRectCopy->height < pThis->svga.u32MaxHeight);
4059
4060	vmsvgaR3RectCopy(pThisCC, pScreen, pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY,
4061	pRectCopy->width, pRectCopy->height, pThis->vram_size);
4062	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height);
4063	break;
4064	}
4065
4066	case SVGA_CMD_RECT_ROP_COPY:
4067	{
4068	SVGAFifoCmdRectRopCopy *pRRCopy;
4069	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRRCopy, SVGAFifoCmdRectRopCopy, sizeof(*pRRCopy));
4070	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectRopCopy);
4071
4072	Log(("vmsvgaR3FifoLoop: RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4073	if (pRRCopy->rop != SVGA_ROP_COPY)
4074	{
4075	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4076	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4077	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4078	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4079	*/
4080	LogRelMax(4, ("RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4081	break;
4082	}
4083
4084	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4085	AssertPtrBreak(pScreen);
4086
4087	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4088	AssertBreak(pRRCopy->srcX < pThis->svga.u32MaxWidth);
4089	AssertBreak(pRRCopy->destX < pThis->svga.u32MaxWidth);
4090	AssertBreak(pRRCopy->width < pThis->svga.u32MaxWidth);
4091	AssertBreak(pRRCopy->srcY < pThis->svga.u32MaxHeight);
4092	AssertBreak(pRRCopy->destY < pThis->svga.u32MaxHeight);
4093	AssertBreak(pRRCopy->height < pThis->svga.u32MaxHeight);
4094
4095	vmsvgaR3RectCopy(pThisCC, pScreen, pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY,
4096	pRRCopy->width, pRRCopy->height, pThis->vram_size);
4097	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height);
4098	break;
4099	}
4100
4101	case SVGA_CMD_ESCAPE:
4102	{
4103	/* Followed by nsize bytes of data. */
4104	SVGAFifoCmdEscape *pEscape;
4105	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
4106	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
4107
4108	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
4109	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
4110	RT_UNTRUSTED_VALIDATED_FENCE();
4111	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
4112	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
4113
4114	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
4115	{
4116	AssertBreak(pEscape->size >= sizeof(uint32_t));
4117	RT_UNTRUSTED_VALIDATED_FENCE();
4118	uint32_t cmd = (uint32_t )(pEscape + 1);
4119	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
4120
4121	switch (cmd)
4122	{
4123	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4124	{
4125	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
4126	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
4127	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4128
4129	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
4130	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4131	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4132
4133	RT_NOREF_PV(pVideoCmd);
4134	break;
4135
4136	}
4137
4138	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4139	{
4140	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4141	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4142	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4143	RT_NOREF_PV(pVideoCmd);
4144	break;
4145	}
4146
4147	default:
4148	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4149	break;
4150	}
4151	}
4152	else
4153	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4154
4155	break;
4156	}
4157	# ifdef VBOX_WITH_VMSVGA3D
4158	case SVGA_CMD_DEFINE_GMR2:
4159	{
4160	SVGAFifoCmdDefineGMR2 *pCmd;
4161	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4162	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4163	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4164
4165	/* Validate current GMR id. */
4166	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4167	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4168	RT_UNTRUSTED_VALIDATED_FENCE();
4169
4170	if (!pCmd->numPages)
4171	{
4172	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4173	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4174	}
4175	else
4176	{
4177	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4178	if (pGMR->cMaxPages)
4179	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4180
4181	/* Not sure if we should always free the descriptor, but for simplicity
4182	we do so if the new size is smaller than the current. */
4183	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4184	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4185	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4186
4187	pGMR->cMaxPages = pCmd->numPages;
4188	/* The rest is done by the REMAP_GMR2 command. */
4189	}
4190	break;
4191	}
4192
4193	case SVGA_CMD_REMAP_GMR2:
4194	{
4195	/* Followed by page descriptors or guest ptr. */
4196	SVGAFifoCmdRemapGMR2 *pCmd;
4197	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4198	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4199
4200	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4201	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4202	RT_UNTRUSTED_VALIDATED_FENCE();
4203
4204	/* Calculate the size of what comes after next and fetch it. */
4205	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4206	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4207	cbCmd += sizeof(SVGAGuestPtr);
4208	else
4209	{
4210	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4211	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4212	{
4213	cbCmd += cbPageDesc;
4214	pCmd->numPages = 1;
4215	}
4216	else
4217	{
4218	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4219	cbCmd += cbPageDesc * pCmd->numPages;
4220	}
4221	}
4222	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4223
4224	/* Validate current GMR id and size. */
4225	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4226	RT_UNTRUSTED_VALIDATED_FENCE();
4227	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4228	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4229	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4230	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4231
4232	if (pCmd->numPages == 0)
4233	break;
4234
4235	/** @todo Move to a separate function vmsvgaGMRRemap() */
4236
4237	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4238	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4239
4240	/*
4241	* We flatten the existing descriptors into a page array, overwrite the
4242	* pages specified in this command and then recompress the descriptor.
4243	*/
4244	/** @todo Optimize the GMR remap algorithm! */
4245
4246	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4247	uint64_t *paNewPage64 = NULL;
4248	if (pGMR->paDesc)
4249	{
4250	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4251
4252	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4253	AssertPtrBreak(paNewPage64);
4254
4255	uint32_t idxPage = 0;
4256	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4257	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4258	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4259	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4260	RT_UNTRUSTED_VALIDATED_FENCE();
4261	}
4262
4263	/* Free the old GMR if present. */
4264	if (pGMR->paDesc)
4265	RTMemFree(pGMR->paDesc);
4266
4267	/* Allocate the maximum amount possible (everything non-continuous) */
4268	PVMSVGAGMRDESCRIPTOR paDescs;
4269	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4270	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4271
4272	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4273	{
4274	/** @todo */
4275	AssertFailed();
4276	pGMR->numDescriptors = 0;
4277	}
4278	else
4279	{
4280	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4281	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4282	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4283
4284	if (paNewPage64)
4285	{
4286	/* Overwrite the old page array with the new page values. */
4287	if (fGCPhys64)
4288	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4289	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4290	else
4291	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4292	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4293
4294	/* Use the updated page array instead of the command data. */
4295	fGCPhys64 = true;
4296	paPages64 = paNewPage64;
4297	pCmd->numPages = cNewTotalPages;
4298	}
4299
4300	/* The first page. */
4301	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4302	* applied to paNewPage64. */
4303	RTGCPHYS GCPhys;
4304	if (fGCPhys64)
4305	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4306	else
4307	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4308	paDescs[0].GCPhys = GCPhys;
4309	paDescs[0].numPages = 1;
4310
4311	/* Subsequent pages. */
4312	uint32_t iDescriptor = 0;
4313	for (uint32_t i = 1; i < pCmd->numPages; i++)
4314	{
4315	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4316	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4317	else
4318	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4319
4320	/* Continuous physical memory? */
4321	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4322	{
4323	Assert(paDescs[iDescriptor].numPages);
4324	paDescs[iDescriptor].numPages++;
4325	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4326	}
4327	else
4328	{
4329	iDescriptor++;
4330	paDescs[iDescriptor].GCPhys = GCPhys;
4331	paDescs[iDescriptor].numPages = 1;
4332	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4333	}
4334	}
4335
4336	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4337	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4338	pGMR->numDescriptors = iDescriptor + 1;
4339	}
4340
4341	if (paNewPage64)
4342	RTMemFree(paNewPage64);
4343
4344	# ifdef DEBUG_GMR_ACCESS
4345	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4346	# endif
4347	break;
4348	}
4349	# endif // VBOX_WITH_VMSVGA3D
4350	case SVGA_CMD_DEFINE_SCREEN:
4351	{
4352	/* The size of this command is specified by the guest and depends on capabilities. */
4353	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4354
4355	SVGAFifoCmdDefineScreen *pCmd;
4356	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4357	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4358	RT_UNTRUSTED_VALIDATED_FENCE();
4359
4360	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4361	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4362	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4363
4364	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4365	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4366	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4367
4368	uint32_t const idScreen = pCmd->screen.id;
4369	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4370
4371	uint32_t const uWidth = pCmd->screen.size.width;
4372	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4373
4374	uint32_t const uHeight = pCmd->screen.size.height;
4375	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4376
4377	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4378	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4379	AssertBreak(cbWidth <= cbPitch);
4380
4381	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4382	AssertBreak(uScreenOffset < pThis->vram_size);
4383
4384	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4385	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4386	AssertBreak( (uHeight == 0 && cbPitch == 0)
4387	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4388	RT_UNTRUSTED_VALIDATED_FENCE();
4389
4390	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4391
4392	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4393
4394	pScreen->fDefined = true;
4395	pScreen->fModified = true;
4396	pScreen->fuScreen = pCmd->screen.flags;
4397	pScreen->idScreen = idScreen;
4398	if (!fBlank)
4399	{
4400	AssertBreak(uWidth > 0 && uHeight > 0);
4401
4402	pScreen->xOrigin = pCmd->screen.root.x;
4403	pScreen->yOrigin = pCmd->screen.root.y;
4404	pScreen->cWidth = uWidth;
4405	pScreen->cHeight = uHeight;
4406	pScreen->offVRAM = uScreenOffset;
4407	pScreen->cbPitch = cbPitch;
4408	pScreen->cBpp = 32;
4409	}
4410	else
4411	{
4412	/* Keep old values. */
4413	}
4414
4415	pThis->svga.fGFBRegisters = false;
4416	vmsvgaR3ChangeMode(pThis, pThisCC);
4417	break;
4418	}
4419
4420	case SVGA_CMD_DESTROY_SCREEN:
4421	{
4422	SVGAFifoCmdDestroyScreen *pCmd;
4423	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4424	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4425
4426	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4427
4428	uint32_t const idScreen = pCmd->screenId;
4429	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4430	RT_UNTRUSTED_VALIDATED_FENCE();
4431
4432	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4433	pScreen->fModified = true;
4434	pScreen->fDefined = false;
4435	pScreen->idScreen = idScreen;
4436
4437	vmsvgaR3ChangeMode(pThis, pThisCC);
4438	break;
4439	}
4440
4441	case SVGA_CMD_DEFINE_GMRFB:
4442	{
4443	SVGAFifoCmdDefineGMRFB *pCmd;
4444	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4445	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4446
4447	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4448	pSVGAState->GMRFB.ptr = pCmd->ptr;
4449	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4450	pSVGAState->GMRFB.format = pCmd->format;
4451	break;
4452	}
4453
4454	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4455	{
4456	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4457	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4458	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4459
4460	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4461	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4462
4463	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4464	RT_UNTRUSTED_VALIDATED_FENCE();
4465
4466	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4467	AssertPtrBreak(pScreen);
4468
4469	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4470	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4471
4472	/* Clip destRect to the screen dimensions. */
4473	SVGASignedRect screenRect;
4474	screenRect.left = 0;
4475	screenRect.top = 0;
4476	screenRect.right = pScreen->cWidth;
4477	screenRect.bottom = pScreen->cHeight;
4478	SVGASignedRect clipRect = pCmd->destRect;
4479	vmsvgaR3ClipRect(&screenRect, &clipRect);
4480	RT_UNTRUSTED_VALIDATED_FENCE();
4481
4482	uint32_t const width = clipRect.right - clipRect.left;
4483	uint32_t const height = clipRect.bottom - clipRect.top;
4484
4485	if ( width == 0
4486	\|\| height == 0)
4487	break; /* Nothing to do. */
4488
4489	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4490	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4491
4492	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4493	* Prepare parameters for vmsvgaR3GmrTransfer.
4494	*/
4495	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4496
4497	/* Destination: host buffer which describes the screen 0 VRAM.
4498	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4499	*/
4500	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4501	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4502	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4503	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4504	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4505	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4506	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4507	+ cbScanline * clipRect.top;
4508	int32_t const cbHstPitch = cbScanline;
4509
4510	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4511	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4512	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4513	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4514	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4515
4516	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4517	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4518	gstPtr, offGst, cbGstPitch,
4519	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4520	AssertRC(rc);
4521	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4522	break;
4523	}
4524
4525	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4526	{
4527	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4528	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4529	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4530
4531	/* Note! This can fetch 3d render results as well!! */
4532	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4533	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4534
4535	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4536	RT_UNTRUSTED_VALIDATED_FENCE();
4537
4538	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4539	AssertPtrBreak(pScreen);
4540
4541	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4542	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4543
4544	/* Clip destRect to the screen dimensions. */
4545	SVGASignedRect screenRect;
4546	screenRect.left = 0;
4547	screenRect.top = 0;
4548	screenRect.right = pScreen->cWidth;
4549	screenRect.bottom = pScreen->cHeight;
4550	SVGASignedRect clipRect = pCmd->srcRect;
4551	vmsvgaR3ClipRect(&screenRect, &clipRect);
4552	RT_UNTRUSTED_VALIDATED_FENCE();
4553
4554	uint32_t const width = clipRect.right - clipRect.left;
4555	uint32_t const height = clipRect.bottom - clipRect.top;
4556
4557	if ( width == 0
4558	\|\| height == 0)
4559	break; /* Nothing to do. */
4560
4561	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4562	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4563
4564	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4565	* Prepare parameters for vmsvgaR3GmrTransfer.
4566	*/
4567	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4568
4569	/* Source: host buffer which describes the screen 0 VRAM.
4570	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4571	*/
4572	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4573	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4574	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4575	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4576	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4577	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4578	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4579	+ cbScanline * clipRect.top;
4580	int32_t const cbHstPitch = cbScanline;
4581
4582	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4583	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4584	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4585	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4586	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4587
4588	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4589	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4590	gstPtr, offGst, cbGstPitch,
4591	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4592	AssertRC(rc);
4593	break;
4594	}
4595
4596	case SVGA_CMD_ANNOTATION_FILL:
4597	{
4598	SVGAFifoCmdAnnotationFill *pCmd;
4599	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4600	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4601
4602	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4603	pSVGAState->colorAnnotation = pCmd->color;
4604	break;
4605	}
4606
4607	case SVGA_CMD_ANNOTATION_COPY:
4608	{
4609	SVGAFifoCmdAnnotationCopy *pCmd;
4610	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4611	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4612
4613	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4614	AssertFailed();
4615	break;
4616	}
4617
4618	default:
4619	# ifdef VBOX_WITH_VMSVGA3D
4620	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4621	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4622	{
4623	RT_UNTRUSTED_VALIDATED_FENCE();
4624
4625	/* All 3d commands start with a common header, which defines the size of the command. */
4626	SVGA3dCmdHeader *pHdr;
4627	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4628	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4629	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4630	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4631
4632	if (RT_LIKELY(pThis->svga.f3DEnabled))
4633	{ /* likely */ }
4634	else
4635	{
4636	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4637	break;
4638	}
4639
4640	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4641	* Check that the 3D command has at least a_cbMin of payload bytes after the
4642	* header. Will break out of the switch if it doesn't.
4643	*/
4644	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4645	if (1) { \
4646	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4647	RT_UNTRUSTED_VALIDATED_FENCE(); \
4648	} else do {} while (0)
4649	switch ((int)enmCmdId)
4650	{
4651	case SVGA_3D_CMD_SURFACE_DEFINE:
4652	{
4653	uint32_t cMipLevels;
4654	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4655	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4656	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4657
4658	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4659	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4660	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4661	# ifdef DEBUG_GMR_ACCESS
4662	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4663	# endif
4664	break;
4665	}
4666
4667	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4668	{
4669	uint32_t cMipLevels;
4670	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4671	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4672	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4673
4674	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4675	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4676	pCmd->multisampleCount, pCmd->autogenFilter,
4677	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4678	break;
4679	}
4680
4681	case SVGA_3D_CMD_SURFACE_DESTROY:
4682	{
4683	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4684	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4685	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4686	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4687	break;
4688	}
4689
4690	case SVGA_3D_CMD_SURFACE_COPY:
4691	{
4692	uint32_t cCopyBoxes;
4693	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4694	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4695	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4696
4697	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4698	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4699	break;
4700	}
4701
4702	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4703	{
4704	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4705	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4706	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4707
4708	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4709	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4710	break;
4711	}
4712
4713	case SVGA_3D_CMD_SURFACE_DMA:
4714	{
4715	uint32_t cCopyBoxes;
4716	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4717	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4718	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4719
4720	uint64_t u64NanoTS = 0;
4721	if (LogRelIs3Enabled())
4722	u64NanoTS = RTTimeNanoTS();
4723	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4724	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4725	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4726	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4727	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4728	if (LogRelIs3Enabled())
4729	{
4730	if (cCopyBoxes)
4731	{
4732	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4733	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4734	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4735	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4736	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4737	}
4738	}
4739	break;
4740	}
4741
4742	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4743	{
4744	uint32_t cRects;
4745	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4746	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4748
4749	uint64_t u64NanoTS = 0;
4750	if (LogRelIs3Enabled())
4751	u64NanoTS = RTTimeNanoTS();
4752	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4753	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4754	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4755	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4756	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4757	if (LogRelIs3Enabled())
4758	{
4759	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4760	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4761	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4762	pFirstRect->left, pFirstRect->top,
4763	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4764	}
4765	break;
4766	}
4767
4768	case SVGA_3D_CMD_CONTEXT_DEFINE:
4769	{
4770	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4771	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4772	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4773
4774	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4775	break;
4776	}
4777
4778	case SVGA_3D_CMD_CONTEXT_DESTROY:
4779	{
4780	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4781	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4782	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4783
4784	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4785	break;
4786	}
4787
4788	case SVGA_3D_CMD_SETTRANSFORM:
4789	{
4790	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4791	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4792	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4793
4794	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4795	break;
4796	}
4797
4798	case SVGA_3D_CMD_SETZRANGE:
4799	{
4800	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4801	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4802	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4803
4804	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4805	break;
4806	}
4807
4808	case SVGA_3D_CMD_SETRENDERSTATE:
4809	{
4810	uint32_t cRenderStates;
4811	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4812	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4813	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4814
4815	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4816	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4817	break;
4818	}
4819
4820	case SVGA_3D_CMD_SETRENDERTARGET:
4821	{
4822	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4823	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4824	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4825
4826	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4827	break;
4828	}
4829
4830	case SVGA_3D_CMD_SETTEXTURESTATE:
4831	{
4832	uint32_t cTextureStates;
4833	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4834	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4835	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4836
4837	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4838	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4839	break;
4840	}
4841
4842	case SVGA_3D_CMD_SETMATERIAL:
4843	{
4844	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4845	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4847
4848	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4849	break;
4850	}
4851
4852	case SVGA_3D_CMD_SETLIGHTDATA:
4853	{
4854	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4855	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4856	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4857
4858	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4859	break;
4860	}
4861
4862	case SVGA_3D_CMD_SETLIGHTENABLED:
4863	{
4864	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4865	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4866	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4867
4868	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4869	break;
4870	}
4871
4872	case SVGA_3D_CMD_SETVIEWPORT:
4873	{
4874	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4875	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4876	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4877
4878	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4879	break;
4880	}
4881
4882	case SVGA_3D_CMD_SETCLIPPLANE:
4883	{
4884	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4885	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4887
4888	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4889	break;
4890	}
4891
4892	case SVGA_3D_CMD_CLEAR:
4893	{
4894	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4895	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4896	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4897
4898	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4899	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4900	break;
4901	}
4902
4903	case SVGA_3D_CMD_PRESENT:
4904	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4905	{
4906	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4907	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4908	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4909	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4910	else
4911	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4912
4913	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4914
4915	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4916	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4917	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4918	break;
4919	}
4920
4921	case SVGA_3D_CMD_SHADER_DEFINE:
4922	{
4923	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4924	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4925	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4926
4927	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4928	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4929	break;
4930	}
4931
4932	case SVGA_3D_CMD_SHADER_DESTROY:
4933	{
4934	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4935	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4936	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4937
4938	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4939	break;
4940	}
4941
4942	case SVGA_3D_CMD_SET_SHADER:
4943	{
4944	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4945	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4946	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4947
4948	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4949	break;
4950	}
4951
4952	case SVGA_3D_CMD_SET_SHADER_CONST:
4953	{
4954	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4955	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4956	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4957
4958	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4959	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4960	break;
4961	}
4962
4963	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4964	{
4965	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4966	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4967	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4968
4969	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4970	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4971	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4972	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4973	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4974
4975	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4976	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4977
4978	RT_UNTRUSTED_VALIDATED_FENCE();
4979
4980	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4981	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4982	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4983
4984	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4985	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4986	pNumRange, cVertexDivisor, pVertexDivisor);
4987	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4988	break;
4989	}
4990
4991	case SVGA_3D_CMD_SETSCISSORRECT:
4992	{
4993	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4994	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4995	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4996
4997	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
4998	break;
4999	}
5000
5001	case SVGA_3D_CMD_BEGIN_QUERY:
5002	{
5003	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
5004	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5005	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
5006
5007	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5008	break;
5009	}
5010
5011	case SVGA_3D_CMD_END_QUERY:
5012	{
5013	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
5014	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5015	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
5016
5017	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5018	break;
5019	}
5020
5021	case SVGA_3D_CMD_WAIT_FOR_QUERY:
5022	{
5023	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
5024	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5025	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
5026
5027	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5028	break;
5029	}
5030
5031	case SVGA_3D_CMD_GENERATE_MIPMAPS:
5032	{
5033	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
5034	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5035	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
5036
5037	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5038	break;
5039	}
5040
5041	case SVGA_3D_CMD_ACTIVATE_SURFACE:
5042	/* context id + surface id? */
5043	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
5044	break;
5045	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5046	/* context id + surface id? */
5047	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
5048	break;
5049
5050	default:
5051	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5052	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5053	break;
5054	}
5055	}
5056	else
5057	# endif // VBOX_WITH_VMSVGA3D
5058	{
5059	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5060	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5061	}
5062	}
5063
5064	/* Go to the next slot */
5065	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5066	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5067	if (offCurrentCmd >= offFifoMax)
5068	{
5069	offCurrentCmd -= offFifoMax - offFifoMin;
5070	Assert(offCurrentCmd >= offFifoMin);
5071	Assert(offCurrentCmd < offFifoMax);
5072	}
5073	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5074	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5075
5076	/*
5077	* Raise IRQ if required. Must enter the critical section here
5078	* before making final decisions here, otherwise cubebench and
5079	* others may end up waiting forever.
5080	*/
5081	if ( u32IrqStatus
5082	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5083	{
5084	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5085	AssertRC(rc2);
5086
5087	/* FIFO progress might trigger an interrupt. */
5088	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5089	{
5090	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5091	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5092	}
5093
5094	/* Unmasked IRQ pending? */
5095	if (pThis->svga.u32IrqMask & u32IrqStatus)
5096	{
5097	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5098	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5099	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5100	}
5101
5102	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5103	}
5104	}
5105
5106	/* If really done, clear the busy flag. */
5107	if (fDone)
5108	{
5109	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5110	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5111	}
5112	}
5113
5114	/*
5115	* Free the bounce buffer. (There are no returns above!)
5116	*/
5117	RTMemFree(pbBounceBuf);
5118
5119	return VINF_SUCCESS;
5120	}
5121
5122	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5123	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5124	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5125
5126	#ifdef VBOX_WITH_VMSVGA3D
5127	/**
5128	* Free the specified GMR
5129	*
5130	* @param pThisCC The VGA/VMSVGA state for ring-3.
5131	* @param idGMR GMR id
5132	*/
5133	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5134	{
5135	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5136
5137	/* Free the old descriptor if present. */
5138	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5139	if ( pGMR->numDescriptors
5140	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5141	{
5142	# ifdef DEBUG_GMR_ACCESS
5143	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5144	# endif
5145
5146	Assert(pGMR->paDesc);
5147	RTMemFree(pGMR->paDesc);
5148	pGMR->paDesc = NULL;
5149	pGMR->numDescriptors = 0;
5150	pGMR->cbTotal = 0;
5151	pGMR->cMaxPages = 0;
5152	}
5153	Assert(!pGMR->cMaxPages);
5154	Assert(!pGMR->cbTotal);
5155	}
5156	#endif /* VBOX_WITH_VMSVGA3D */
5157
5158	/**
5159	* Copy between a GMR and a host memory buffer.
5160	*
5161	* @returns VBox status code.
5162	* @param pThis The shared VGA/VMSVGA instance data.
5163	* @param pThisCC The VGA/VMSVGA state for ring-3.
5164	* @param enmTransferType Transfer type (read/write)
5165	* @param pbHstBuf Host buffer pointer (valid)
5166	* @param cbHstBuf Size of host buffer (valid)
5167	* @param offHst Host buffer offset of the first scanline
5168	* @param cbHstPitch Destination buffer pitch
5169	* @param gstPtr GMR description
5170	* @param offGst Guest buffer offset of the first scanline
5171	* @param cbGstPitch Guest buffer pitch
5172	* @param cbWidth Width in bytes to copy
5173	* @param cHeight Number of scanllines to copy
5174	*/
5175	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5176	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5177	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5178	uint32_t cbWidth, uint32_t cHeight)
5179	{
5180	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5181	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5182	int rc;
5183
5184	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5185	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5186	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5187	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5188	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5189
5190	PGMR pGMR;
5191	uint32_t cbGmr; /* The GMR size in bytes. */
5192	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5193	{
5194	pGMR = NULL;
5195	cbGmr = pThis->vram_size;
5196	}
5197	else
5198	{
5199	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5200	RT_UNTRUSTED_VALIDATED_FENCE();
5201	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5202	cbGmr = pGMR->cbTotal;
5203	}
5204
5205	/*
5206	* GMR
5207	*/
5208	/* Calculate GMR offset of the data to be copied. */
5209	AssertMsgReturn(gstPtr.offset < cbGmr,
5210	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5211	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5212	VERR_INVALID_PARAMETER);
5213	RT_UNTRUSTED_VALIDATED_FENCE();
5214	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5215	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5216	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5217	VERR_INVALID_PARAMETER);
5218	RT_UNTRUSTED_VALIDATED_FENCE();
5219	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5220
5221	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5222	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5223	AssertMsgReturn(cbGmrScanline != 0,
5224	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5225	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5226	VERR_INVALID_PARAMETER);
5227	RT_UNTRUSTED_VALIDATED_FENCE();
5228	AssertMsgReturn(cbWidth <= cbGmrScanline,
5229	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5230	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5231	VERR_INVALID_PARAMETER);
5232	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5233	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5234	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5235	VERR_INVALID_PARAMETER);
5236	RT_UNTRUSTED_VALIDATED_FENCE();
5237
5238	/* How many bytes are available for the data in the GMR. */
5239	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5240
5241	/* How many scanlines would fit into the available data. */
5242	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5243	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5244	if (cbWidth <= cbGmrLastScanline)
5245	++cGmrScanlines;
5246
5247	if (cHeight > cGmrScanlines)
5248	cHeight = cGmrScanlines;
5249
5250	AssertMsgReturn(cHeight > 0,
5251	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5252	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5253	VERR_INVALID_PARAMETER);
5254	RT_UNTRUSTED_VALIDATED_FENCE();
5255
5256	/*
5257	* Host buffer.
5258	*/
5259	AssertMsgReturn(offHst < cbHstBuf,
5260	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5261	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5262	VERR_INVALID_PARAMETER);
5263
5264	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5265	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5266	AssertMsgReturn(cbHstScanline != 0,
5267	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5268	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5269	VERR_INVALID_PARAMETER);
5270	AssertMsgReturn(cbWidth <= cbHstScanline,
5271	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5272	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5273	VERR_INVALID_PARAMETER);
5274	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5275	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5276	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5277	VERR_INVALID_PARAMETER);
5278
5279	/* How many bytes are available for the data in the buffer. */
5280	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5281
5282	/* How many scanlines would fit into the available data. */
5283	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5284	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5285	if (cbWidth <= cbHstLastScanline)
5286	++cHstScanlines;
5287
5288	if (cHeight > cHstScanlines)
5289	cHeight = cHstScanlines;
5290
5291	AssertMsgReturn(cHeight > 0,
5292	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5293	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5294	VERR_INVALID_PARAMETER);
5295
5296	uint8_t *pbHst = pbHstBuf + offHst;
5297
5298	/* Shortcut for the framebuffer. */
5299	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5300	{
5301	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5302
5303	uint8_t const *pbSrc;
5304	int32_t cbSrcPitch;
5305	uint8_t *pbDst;
5306	int32_t cbDstPitch;
5307
5308	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5309	{
5310	pbSrc = pbHst;
5311	cbSrcPitch = cbHstPitch;
5312	pbDst = pbGst;
5313	cbDstPitch = cbGstPitch;
5314	}
5315	else
5316	{
5317	pbSrc = pbGst;
5318	cbSrcPitch = cbGstPitch;
5319	pbDst = pbHst;
5320	cbDstPitch = cbHstPitch;
5321	}
5322
5323	if ( cbWidth == (uint32_t)cbGstPitch
5324	&& cbGstPitch == cbHstPitch)
5325	{
5326	/* Entire scanlines, positive pitch. */
5327	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5328	}
5329	else
5330	{
5331	for (uint32_t i = 0; i < cHeight; ++i)
5332	{
5333	memcpy(pbDst, pbSrc, cbWidth);
5334
5335	pbDst += cbDstPitch;
5336	pbSrc += cbSrcPitch;
5337	}
5338	}
5339	return VINF_SUCCESS;
5340	}
5341
5342	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5343	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5344
5345	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5346	uint32_t iDesc = 0; /* Index in the descriptor array. */
5347	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5348	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5349	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5350	for (uint32_t i = 0; i < cHeight; ++i)
5351	{
5352	uint32_t cbCurrentWidth = cbWidth;
5353	uint32_t offGmrCurrent = offGmrScanline;
5354	uint8_t *pbCurrentHost = pbHstScanline;
5355
5356	/* Find the right descriptor */
5357	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5358	{
5359	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5360	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5361	++iDesc;
5362	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5363	}
5364
5365	while (cbCurrentWidth)
5366	{
5367	uint32_t cbToCopy;
5368
5369	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5370	{
5371	cbToCopy = cbCurrentWidth;
5372	}
5373	else
5374	{
5375	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5376	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5377	}
5378
5379	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5380
5381	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5382
5383	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5384	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5385	else
5386	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5387	AssertRCBreak(rc);
5388
5389	cbCurrentWidth -= cbToCopy;
5390	offGmrCurrent += cbToCopy;
5391	pbCurrentHost += cbToCopy;
5392
5393	/* Go to the next descriptor if there's anything left. */
5394	if (cbCurrentWidth)
5395	{
5396	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5397	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5398	++iDesc;
5399	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5400	}
5401	}
5402
5403	offGmrScanline += cbGstPitch;
5404	pbHstScanline += cbHstPitch;
5405	}
5406
5407	return VINF_SUCCESS;
5408	}
5409
5410
5411	/**
5412	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5413	*
5414	* @param pSizeSrc Source surface dimensions.
5415	* @param pSizeDest Destination surface dimensions.
5416	* @param pBox Coordinates to be clipped.
5417	*/
5418	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5419	{
5420	/* Src x, w */
5421	if (pBox->srcx > pSizeSrc->width)
5422	pBox->srcx = pSizeSrc->width;
5423	if (pBox->w > pSizeSrc->width - pBox->srcx)
5424	pBox->w = pSizeSrc->width - pBox->srcx;
5425
5426	/* Src y, h */
5427	if (pBox->srcy > pSizeSrc->height)
5428	pBox->srcy = pSizeSrc->height;
5429	if (pBox->h > pSizeSrc->height - pBox->srcy)
5430	pBox->h = pSizeSrc->height - pBox->srcy;
5431
5432	/* Src z, d */
5433	if (pBox->srcz > pSizeSrc->depth)
5434	pBox->srcz = pSizeSrc->depth;
5435	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5436	pBox->d = pSizeSrc->depth - pBox->srcz;
5437
5438	/* Dest x, w */
5439	if (pBox->x > pSizeDest->width)
5440	pBox->x = pSizeDest->width;
5441	if (pBox->w > pSizeDest->width - pBox->x)
5442	pBox->w = pSizeDest->width - pBox->x;
5443
5444	/* Dest y, h */
5445	if (pBox->y > pSizeDest->height)
5446	pBox->y = pSizeDest->height;
5447	if (pBox->h > pSizeDest->height - pBox->y)
5448	pBox->h = pSizeDest->height - pBox->y;
5449
5450	/* Dest z, d */
5451	if (pBox->z > pSizeDest->depth)
5452	pBox->z = pSizeDest->depth;
5453	if (pBox->d > pSizeDest->depth - pBox->z)
5454	pBox->d = pSizeDest->depth - pBox->z;
5455	}
5456
5457	/**
5458	* Unsigned coordinates in pBox. Clip to [0; pSize).
5459	*
5460	* @param pSize Source surface dimensions.
5461	* @param pBox Coordinates to be clipped.
5462	*/
5463	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5464	{
5465	/* x, w */
5466	if (pBox->x > pSize->width)
5467	pBox->x = pSize->width;
5468	if (pBox->w > pSize->width - pBox->x)
5469	pBox->w = pSize->width - pBox->x;
5470
5471	/* y, h */
5472	if (pBox->y > pSize->height)
5473	pBox->y = pSize->height;
5474	if (pBox->h > pSize->height - pBox->y)
5475	pBox->h = pSize->height - pBox->y;
5476
5477	/* z, d */
5478	if (pBox->z > pSize->depth)
5479	pBox->z = pSize->depth;
5480	if (pBox->d > pSize->depth - pBox->z)
5481	pBox->d = pSize->depth - pBox->z;
5482	}
5483
5484	/**
5485	* Clip.
5486	*
5487	* @param pBound Bounding rectangle.
5488	* @param pRect Rectangle to be clipped.
5489	*/
5490	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5491	{
5492	int32_t left;
5493	int32_t top;
5494	int32_t right;
5495	int32_t bottom;
5496
5497	/* Right order. */
5498	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5499	if (pRect->left < pRect->right)
5500	{
5501	left = pRect->left;
5502	right = pRect->right;
5503	}
5504	else
5505	{
5506	left = pRect->right;
5507	right = pRect->left;
5508	}
5509	if (pRect->top < pRect->bottom)
5510	{
5511	top = pRect->top;
5512	bottom = pRect->bottom;
5513	}
5514	else
5515	{
5516	top = pRect->bottom;
5517	bottom = pRect->top;
5518	}
5519
5520	if (left < pBound->left)
5521	left = pBound->left;
5522	if (right < pBound->left)
5523	right = pBound->left;
5524
5525	if (left > pBound->right)
5526	left = pBound->right;
5527	if (right > pBound->right)
5528	right = pBound->right;
5529
5530	if (top < pBound->top)
5531	top = pBound->top;
5532	if (bottom < pBound->top)
5533	bottom = pBound->top;
5534
5535	if (top > pBound->bottom)
5536	top = pBound->bottom;
5537	if (bottom > pBound->bottom)
5538	bottom = pBound->bottom;
5539
5540	pRect->left = left;
5541	pRect->right = right;
5542	pRect->top = top;
5543	pRect->bottom = bottom;
5544	}
5545
5546	/**
5547	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5548	* Unblock the FIFO I/O thread so it can respond to a state change.}
5549	*/
5550	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5551	{
5552	RT_NOREF(pDevIns);
5553	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5554	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5555	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5556	}
5557
5558	/**
5559	* Enables or disables dirty page tracking for the framebuffer
5560	*
5561	* @param pDevIns The device instance.
5562	* @param pThis The shared VGA/VMSVGA instance data.
5563	* @param fTraces Enable/disable traces
5564	*/
5565	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5566	{
5567	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5568	&& !fTraces)
5569	{
5570	//Assert(pThis->svga.fTraces);
5571	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5572	return;
5573	}
5574
5575	pThis->svga.fTraces = fTraces;
5576	if (pThis->svga.fTraces)
5577	{
5578	unsigned cbFrameBuffer = pThis->vram_size;
5579
5580	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5581	/** @todo How does this work with screens? */
5582	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5583	{
5584	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5585	Assert(pThis->svga.cbScanline);
5586	# endif
5587	/* Hardware enabled; return real framebuffer size .*/
5588	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5589	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5590	}
5591
5592	if (!pThis->svga.fVRAMTracking)
5593	{
5594	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5595	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5596	pThis->svga.fVRAMTracking = true;
5597	}
5598	}
5599	else
5600	{
5601	if (pThis->svga.fVRAMTracking)
5602	{
5603	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5604	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5605	pThis->svga.fVRAMTracking = false;
5606	}
5607	}
5608	}
5609
5610	/**
5611	* @callback_method_impl{FNPCIIOREGIONMAP}
5612	*/
5613	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5614	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5615	{
5616	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5617	int rc;
5618	RT_NOREF(pPciDev);
5619	Assert(pPciDev == pDevIns->apPciDevs[0]);
5620
5621	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5622	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5623	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5624	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5625	, VERR_INTERNAL_ERROR);
5626	if (GCPhysAddress != NIL_RTGCPHYS)
5627	{
5628	/*
5629	* Mapping the FIFO RAM.
5630	*/
5631	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5632	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5633	AssertRC(rc);
5634
5635	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5636	if (RT_SUCCESS(rc))
5637	{
5638	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5639	# ifdef DEBUG_FIFO_ACCESS
5640	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5641	# else
5642	GCPhysAddress + PAGE_SIZE - 1,
5643	# endif
5644	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5645	"VMSVGA FIFO");
5646	AssertRC(rc);
5647	}
5648	# endif
5649	if (RT_SUCCESS(rc))
5650	{
5651	pThis->svga.GCPhysFIFO = GCPhysAddress;
5652	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5653	}
5654	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5655	}
5656	else
5657	{
5658	Assert(pThis->svga.GCPhysFIFO);
5659	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5660	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5661	AssertRC(rc);
5662	# else
5663	rc = VINF_SUCCESS;
5664	# endif
5665	pThis->svga.GCPhysFIFO = 0;
5666	}
5667	return rc;
5668	}
5669
5670	# ifdef VBOX_WITH_VMSVGA3D
5671
5672	/**
5673	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5674	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5675	*
5676	* @param pDevIns The device instance.
5677	* @param pThis The The shared VGA/VMSVGA instance data.
5678	* @param pThisCC The VGA/VMSVGA state for ring-3.
5679	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5680	* UINT32_MAX is used, all surfaces are processed.
5681	*/
5682	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5683	{
5684	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5685	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5686	}
5687
5688
5689	/**
5690	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5691	*/
5692	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5693	{
5694	/* There might be a specific surface ID at the start of the
5695	arguments, if not show all surfaces. */
5696	uint32_t sid = UINT32_MAX;
5697	if (pszArgs)
5698	pszArgs = RTStrStripL(pszArgs);
5699	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5700	sid = RTStrToUInt32(pszArgs);
5701
5702	/* Verbose or terse display, we default to verbose. */
5703	bool fVerbose = true;
5704	if (RTStrIStr(pszArgs, "terse"))
5705	fVerbose = false;
5706
5707	/* The size of the ascii art (x direction, y is 3/4 of x). */
5708	uint32_t cxAscii = 80;
5709	if (RTStrIStr(pszArgs, "gigantic"))
5710	cxAscii = 300;
5711	else if (RTStrIStr(pszArgs, "huge"))
5712	cxAscii = 180;
5713	else if (RTStrIStr(pszArgs, "big"))
5714	cxAscii = 132;
5715	else if (RTStrIStr(pszArgs, "normal"))
5716	cxAscii = 80;
5717	else if (RTStrIStr(pszArgs, "medium"))
5718	cxAscii = 64;
5719	else if (RTStrIStr(pszArgs, "small"))
5720	cxAscii = 48;
5721	else if (RTStrIStr(pszArgs, "tiny"))
5722	cxAscii = 24;
5723
5724	/* Y invert the image when producing the ASCII art. */
5725	bool fInvY = false;
5726	if (RTStrIStr(pszArgs, "invy"))
5727	fInvY = true;
5728
5729	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5730	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5731	}
5732
5733
5734	/**
5735	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5736	*/
5737	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5738	{
5739	/* pszArg = "sid[>dir]"
5740	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5741	*/
5742	char *pszBitmapPath = NULL;
5743	uint32_t sid = UINT32_MAX;
5744	if (pszArgs)
5745	pszArgs = RTStrStripL(pszArgs);
5746	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5747	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5748	if ( pszBitmapPath
5749	&& *pszBitmapPath == '>')
5750	++pszBitmapPath;
5751
5752	const bool fVerbose = true;
5753	const uint32_t cxAscii = 0; /* No ASCII */
5754	const bool fInvY = false; /* Do not invert. */
5755	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5756	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5757	}
5758
5759	/**
5760	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5761	*/
5762	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5763	{
5764	/* There might be a specific surface ID at the start of the
5765	arguments, if not show all contexts. */
5766	uint32_t sid = UINT32_MAX;
5767	if (pszArgs)
5768	pszArgs = RTStrStripL(pszArgs);
5769	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5770	sid = RTStrToUInt32(pszArgs);
5771
5772	/* Verbose or terse display, we default to verbose. */
5773	bool fVerbose = true;
5774	if (RTStrIStr(pszArgs, "terse"))
5775	fVerbose = false;
5776
5777	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5778	}
5779	# endif /* VBOX_WITH_VMSVGA3D */
5780
5781	/**
5782	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5783	*/
5784	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5785	{
5786	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5787	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5788	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5789	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5790	RT_NOREF(pszArgs);
5791
5792	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5793	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5794	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5795	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5796	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5797	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5798	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5799	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5800	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5801	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5802	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5803	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5804	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5805	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5806	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5807	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5808	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5809	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5810	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5811	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5812	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5813	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5814	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5815	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5816	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5817
5818	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5819	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5820	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5821	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5822
5823	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5824	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5825
5826	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5827	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5828
5829	# ifdef VBOX_WITH_VMSVGA3D
5830	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5831	# endif
5832	if (pThisCC->pDrv)
5833	{
5834	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5835	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5836	}
5837
5838	/* Dump screen information. */
5839	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5840	{
5841	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5842	if (pScreen)
5843	{
5844	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5845	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5846	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5847	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5848	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5849	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5850	{
5851	pHlp->pfnPrintf(pHlp, " (");
5852	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5853	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5854	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5855	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5856	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5857	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5858	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5859	pHlp->pfnPrintf(pHlp, " BLANKING");
5860	pHlp->pfnPrintf(pHlp, " )");
5861	}
5862	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5863	}
5864	}
5865
5866	}
5867
5868	/**
5869	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5870	*/
5871	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5872	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5873	{
5874	RT_NOREF(uPass);
5875
5876	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5877	int rc;
5878
5879	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5880	{
5881	uint32_t cScreens = 0;
5882	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5883	AssertRCReturn(rc, rc);
5884	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5885	("cScreens=%#x\n", cScreens),
5886	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5887
5888	for (uint32_t i = 0; i < cScreens; ++i)
5889	{
5890	VMSVGASCREENOBJECT screen;
5891	RT_ZERO(screen);
5892
5893	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5894	AssertLogRelRCReturn(rc, rc);
5895
5896	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5897	{
5898	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5899	*pScreen = screen;
5900	pScreen->fModified = true;
5901	}
5902	else
5903	{
5904	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5905	}
5906	}
5907	}
5908	else
5909	{
5910	/* Try to setup at least the first screen. */
5911	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5912	pScreen->fDefined = true;
5913	pScreen->fModified = true;
5914	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5915	pScreen->idScreen = 0;
5916	pScreen->xOrigin = 0;
5917	pScreen->yOrigin = 0;
5918	pScreen->offVRAM = pThis->svga.uScreenOffset;
5919	pScreen->cbPitch = pThis->svga.cbScanline;
5920	pScreen->cWidth = pThis->svga.uWidth;
5921	pScreen->cHeight = pThis->svga.uHeight;
5922	pScreen->cBpp = pThis->svga.uBpp;
5923	}
5924
5925	return VINF_SUCCESS;
5926	}
5927
5928	/**
5929	* @copydoc FNSSMDEVLOADEXEC
5930	*/
5931	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5932	{
5933	RT_NOREF(uPass);
5934	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5935	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5936	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5937	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5938	int rc;
5939
5940	/* Load our part of the VGAState */
5941	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5942	AssertRCReturn(rc, rc);
5943
5944	/* Load the VGA framebuffer. */
5945	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5946	uint32_t cbVgaFramebuffer = _32K;
5947	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5948	{
5949	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5950	AssertRCReturn(rc, rc);
5951	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5952	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5953	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5954	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5955	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5956	}
5957	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5958	AssertRCReturn(rc, rc);
5959	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5960	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5961	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5962	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5963
5964	/* Load the VMSVGA state. */
5965	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5966	AssertRCReturn(rc, rc);
5967
5968	/* Load the active cursor bitmaps. */
5969	if (pSVGAState->Cursor.fActive)
5970	{
5971	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5972	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5973
5974	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5975	AssertRCReturn(rc, rc);
5976	}
5977
5978	/* Load the GMR state. */
5979	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5980	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5981	{
5982	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5983	AssertRCReturn(rc, rc);
5984	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5985	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5986	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5987	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5988	}
5989
5990	if (pThis->svga.cGMR != cGMR)
5991	{
5992	/* Reallocate GMR array. */
5993	Assert(pSVGAState->paGMR != NULL);
5994	RTMemFree(pSVGAState->paGMR);
5995	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5996	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5997	pThis->svga.cGMR = cGMR;
5998	}
5999
6000	for (uint32_t i = 0; i < cGMR; ++i)
6001	{
6002	PGMR pGMR = &pSVGAState->paGMR[i];
6003
6004	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6005	AssertRCReturn(rc, rc);
6006
6007	if (pGMR->numDescriptors)
6008	{
6009	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6010	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6011	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6012
6013	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6014	{
6015	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6016	AssertRCReturn(rc, rc);
6017	}
6018	}
6019	}
6020
6021	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6022	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
6023	# endif
6024
6025	VMSVGA_STATE_LOAD LoadState;
6026	LoadState.pSSM = pSSM;
6027	LoadState.uVersion = uVersion;
6028	LoadState.uPass = uPass;
6029	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6030	AssertLogRelRCReturn(rc, rc);
6031
6032	return VINF_SUCCESS;
6033	}
6034
6035	/**
6036	* Reinit the video mode after the state has been loaded.
6037	*/
6038	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6039	{
6040	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6041	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6042	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6043
6044	/* Set the active cursor. */
6045	if (pSVGAState->Cursor.fActive)
6046	{
6047	/* We don't store the alpha flag, but we can take a guess that if
6048	* the old register interface was used, the cursor was B&W.
6049	*/
6050	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6051
6052	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6053	true /fVisible/,
6054	fAlpha,
6055	pSVGAState->Cursor.xHotspot,
6056	pSVGAState->Cursor.yHotspot,
6057	pSVGAState->Cursor.width,
6058	pSVGAState->Cursor.height,
6059	pSVGAState->Cursor.pData);
6060	AssertRC(rc);
6061
6062	if (pThis->svga.uCursorOn)
6063	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6064	}
6065
6066	/* If the VRAM handler should not be registered, we have to explicitly
6067	* unregister it here!
6068	*/
6069	if (!pThis->svga.fVRAMTracking)
6070	{
6071	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6072	}
6073
6074	/* Let the FIFO thread deal with changing the mode. */
6075	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6076
6077	return VINF_SUCCESS;
6078	}
6079
6080	/**
6081	* Portion of SVGA state which must be saved in the FIFO thread.
6082	*/
6083	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6084	{
6085	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6086	int rc;
6087
6088	/* Save the screen objects. */
6089	/* Count defined screen object. */
6090	uint32_t cScreens = 0;
6091	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6092	{
6093	if (pSVGAState->aScreens[i].fDefined)
6094	++cScreens;
6095	}
6096
6097	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6098	AssertLogRelRCReturn(rc, rc);
6099
6100	for (uint32_t i = 0; i < cScreens; ++i)
6101	{
6102	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6103
6104	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6105	AssertLogRelRCReturn(rc, rc);
6106	}
6107	return VINF_SUCCESS;
6108	}
6109
6110	/**
6111	* @copydoc FNSSMDEVSAVEEXEC
6112	*/
6113	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6114	{
6115	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6116	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6117	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6118	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6119	int rc;
6120
6121	/* Save our part of the VGAState */
6122	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6123	AssertLogRelRCReturn(rc, rc);
6124
6125	/* Save the framebuffer backup. */
6126	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6127	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6128	AssertLogRelRCReturn(rc, rc);
6129
6130	/* Save the VMSVGA state. */
6131	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6132	AssertLogRelRCReturn(rc, rc);
6133
6134	/* Save the active cursor bitmaps. */
6135	if (pSVGAState->Cursor.fActive)
6136	{
6137	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6138	AssertLogRelRCReturn(rc, rc);
6139	}
6140
6141	/* Save the GMR state */
6142	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6143	AssertLogRelRCReturn(rc, rc);
6144	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6145	{
6146	PGMR pGMR = &pSVGAState->paGMR[i];
6147
6148	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6149	AssertLogRelRCReturn(rc, rc);
6150
6151	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6152	{
6153	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6154	AssertLogRelRCReturn(rc, rc);
6155	}
6156	}
6157
6158	/*
6159	* Must save some state (3D in particular) in the FIFO thread.
6160	*/
6161	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6162	AssertLogRelRCReturn(rc, rc);
6163
6164	return VINF_SUCCESS;
6165	}
6166
6167	/**
6168	* Destructor for PVMSVGAR3STATE structure.
6169	*
6170	* @param pThis The shared VGA/VMSVGA instance data.
6171	* @param pSVGAState Pointer to the structure. It is not deallocated.
6172	*/
6173	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6174	{
6175	# ifndef VMSVGA_USE_EMT_HALT_CODE
6176	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6177	{
6178	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6179	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6180	}
6181	# endif
6182
6183	if (pSVGAState->Cursor.fActive)
6184	{
6185	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6186	pSVGAState->Cursor.pData = NULL;
6187	pSVGAState->Cursor.fActive = false;
6188	}
6189
6190	if (pSVGAState->paGMR)
6191	{
6192	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6193	if (pSVGAState->paGMR[i].paDesc)
6194	RTMemFree(pSVGAState->paGMR[i].paDesc);
6195
6196	RTMemFree(pSVGAState->paGMR);
6197	pSVGAState->paGMR = NULL;
6198	}
6199	}
6200
6201	/**
6202	* Constructor for PVMSVGAR3STATE structure.
6203	*
6204	* @returns VBox status code.
6205	* @param pThis The shared VGA/VMSVGA instance data.
6206	* @param pSVGAState Pointer to the structure. It is already allocated.
6207	*/
6208	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6209	{
6210	int rc = VINF_SUCCESS;
6211	RT_ZERO(*pSVGAState);
6212
6213	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6214	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6215
6216	# ifndef VMSVGA_USE_EMT_HALT_CODE
6217	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6218	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6219	AssertRCReturn(rc, rc);
6220	# endif
6221
6222	return rc;
6223	}
6224
6225	/**
6226	* Initializes the host capabilities: registers and FIFO.
6227	*
6228	* @returns VBox status code.
6229	* @param pThis The shared VGA/VMSVGA instance data.
6230	* @param pThisCC The VGA/VMSVGA state for ring-3.
6231	*/
6232	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6233	{
6234	/* Register caps. */
6235	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6236	\| SVGA_CAP_GMR2
6237	\| SVGA_CAP_CURSOR
6238	\| SVGA_CAP_CURSOR_BYPASS
6239	\| SVGA_CAP_CURSOR_BYPASS_2
6240	\| SVGA_CAP_EXTENDED_FIFO
6241	\| SVGA_CAP_IRQMASK
6242	\| SVGA_CAP_PITCHLOCK
6243	\| SVGA_CAP_RECT_COPY
6244	\| SVGA_CAP_TRACES
6245	\| SVGA_CAP_SCREEN_OBJECT_2
6246	\| SVGA_CAP_ALPHA_CURSOR;
6247	# ifdef VBOX_WITH_VMSVGA3D
6248	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6249	# endif
6250
6251	/* Clear the FIFO. */
6252	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6253
6254	/* Setup FIFO capabilities. */
6255	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6256	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6257	\| SVGA_FIFO_CAP_GMR2
6258	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6259	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6260	\| SVGA_FIFO_CAP_RESERVE
6261	\| SVGA_FIFO_CAP_PITCHLOCK;
6262
6263	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6264	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6265	}
6266
6267	# ifdef VBOX_WITH_VMSVGA3D
6268	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6269	static const char * const g_apszVmSvgaDevCapNames[] =
6270	{
6271	"x3D", /* = 0 */
6272	"xMAX_LIGHTS",
6273	"xMAX_TEXTURES",
6274	"xMAX_CLIP_PLANES",
6275	"xVERTEX_SHADER_VERSION",
6276	"xVERTEX_SHADER",
6277	"xFRAGMENT_SHADER_VERSION",
6278	"xFRAGMENT_SHADER",
6279	"xMAX_RENDER_TARGETS",
6280	"xS23E8_TEXTURES",
6281	"xS10E5_TEXTURES",
6282	"xMAX_FIXED_VERTEXBLEND",
6283	"xD16_BUFFER_FORMAT",
6284	"xD24S8_BUFFER_FORMAT",
6285	"xD24X8_BUFFER_FORMAT",
6286	"xQUERY_TYPES",
6287	"xTEXTURE_GRADIENT_SAMPLING",
6288	"rMAX_POINT_SIZE",
6289	"xMAX_SHADER_TEXTURES",
6290	"xMAX_TEXTURE_WIDTH",
6291	"xMAX_TEXTURE_HEIGHT",
6292	"xMAX_VOLUME_EXTENT",
6293	"xMAX_TEXTURE_REPEAT",
6294	"xMAX_TEXTURE_ASPECT_RATIO",
6295	"xMAX_TEXTURE_ANISOTROPY",
6296	"xMAX_PRIMITIVE_COUNT",
6297	"xMAX_VERTEX_INDEX",
6298	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6299	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6300	"xMAX_VERTEX_SHADER_TEMPS",
6301	"xMAX_FRAGMENT_SHADER_TEMPS",
6302	"xTEXTURE_OPS",
6303	"xSURFACEFMT_X8R8G8B8",
6304	"xSURFACEFMT_A8R8G8B8",
6305	"xSURFACEFMT_A2R10G10B10",
6306	"xSURFACEFMT_X1R5G5B5",
6307	"xSURFACEFMT_A1R5G5B5",
6308	"xSURFACEFMT_A4R4G4B4",
6309	"xSURFACEFMT_R5G6B5",
6310	"xSURFACEFMT_LUMINANCE16",
6311	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6312	"xSURFACEFMT_ALPHA8",
6313	"xSURFACEFMT_LUMINANCE8",
6314	"xSURFACEFMT_Z_D16",
6315	"xSURFACEFMT_Z_D24S8",
6316	"xSURFACEFMT_Z_D24X8",
6317	"xSURFACEFMT_DXT1",
6318	"xSURFACEFMT_DXT2",
6319	"xSURFACEFMT_DXT3",
6320	"xSURFACEFMT_DXT4",
6321	"xSURFACEFMT_DXT5",
6322	"xSURFACEFMT_BUMPX8L8V8U8",
6323	"xSURFACEFMT_A2W10V10U10",
6324	"xSURFACEFMT_BUMPU8V8",
6325	"xSURFACEFMT_Q8W8V8U8",
6326	"xSURFACEFMT_CxV8U8",
6327	"xSURFACEFMT_R_S10E5",
6328	"xSURFACEFMT_R_S23E8",
6329	"xSURFACEFMT_RG_S10E5",
6330	"xSURFACEFMT_RG_S23E8",
6331	"xSURFACEFMT_ARGB_S10E5",
6332	"xSURFACEFMT_ARGB_S23E8",
6333	"xMISSING62",
6334	"xMAX_VERTEX_SHADER_TEXTURES",
6335	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6336	"xSURFACEFMT_V16U16",
6337	"xSURFACEFMT_G16R16",
6338	"xSURFACEFMT_A16B16G16R16",
6339	"xSURFACEFMT_UYVY",
6340	"xSURFACEFMT_YUY2",
6341	"xMULTISAMPLE_NONMASKABLESAMPLES",
6342	"xMULTISAMPLE_MASKABLESAMPLES",
6343	"xALPHATOCOVERAGE",
6344	"xSUPERSAMPLE",
6345	"xAUTOGENMIPMAPS",
6346	"xSURFACEFMT_NV12",
6347	"xSURFACEFMT_AYUV",
6348	"xMAX_CONTEXT_IDS",
6349	"xMAX_SURFACE_IDS",
6350	"xSURFACEFMT_Z_DF16",
6351	"xSURFACEFMT_Z_DF24",
6352	"xSURFACEFMT_Z_D24S8_INT",
6353	"xSURFACEFMT_BC4_UNORM",
6354	"xSURFACEFMT_BC5_UNORM", /* 83 */
6355	};
6356
6357	/**
6358	* Initializes the host 3D capabilities in FIFO.
6359	*
6360	* @returns VBox status code.
6361	* @param pThis The shared VGA/VMSVGA instance data.
6362	* @param pThisCC The VGA/VMSVGA state for ring-3.
6363	*/
6364	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6365	{
6366	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6367	bool fSavedBuffering = RTLogRelSetBuffering(true);
6368	SVGA3dCapsRecord *pCaps;
6369	SVGA3dCapPair *pData;
6370	uint32_t idxCap = 0;
6371
6372	/* 3d hardware version; latest and greatest */
6373	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6374	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6375
6376	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6377	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6378	pData = (SVGA3dCapPair *)&pCaps->data;
6379
6380	/* Fill out all 3d capabilities. */
6381	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6382	{
6383	uint32_t val = 0;
6384
6385	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6386	if (RT_SUCCESS(rc))
6387	{
6388	pData[idxCap][0] = i;
6389	pData[idxCap][1] = val;
6390	idxCap++;
6391	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6392	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6393	else
6394	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6395	&g_apszVmSvgaDevCapNames[i][1]));
6396	}
6397	else
6398	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6399	}
6400	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6401	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6402
6403	/* Mark end of record array. */
6404	pCaps->header.length = 0;
6405
6406	RTLogRelSetBuffering(fSavedBuffering);
6407	}
6408
6409	# endif
6410
6411	/**
6412	* Resets the SVGA hardware state
6413	*
6414	* @returns VBox status code.
6415	* @param pDevIns The device instance.
6416	*/
6417	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6418	{
6419	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6420	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6421	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6422
6423	/* Reset before init? */
6424	if (!pSVGAState)
6425	return VINF_SUCCESS;
6426
6427	Log(("vmsvgaR3Reset\n"));
6428
6429	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6430	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6431	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6432
6433	/* Reset other stuff. */
6434	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6435	RT_ZERO(pThis->svga.au32ScratchRegion);
6436
6437	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6438	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6439
6440	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6441
6442	/* Initialize FIFO and register capabilities. */
6443	vmsvgaR3InitCaps(pThis, pThisCC);
6444
6445	# ifdef VBOX_WITH_VMSVGA3D
6446	if (pThis->svga.f3DEnabled)
6447	vmsvgaR3InitFifo3DCaps(pThisCC);
6448	# endif
6449
6450	/* VRAM tracking is enabled by default during bootup. */
6451	pThis->svga.fVRAMTracking = true;
6452	pThis->svga.fEnabled = false;
6453
6454	/* Invalidate current settings. */
6455	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6456	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6457	pThis->svga.uBpp = pThis->svga.uHostBpp;
6458	pThis->svga.cbScanline = 0;
6459	pThis->svga.u32PitchLock = 0;
6460
6461	return rc;
6462	}
6463
6464	/**
6465	* Cleans up the SVGA hardware state
6466	*
6467	* @returns VBox status code.
6468	* @param pDevIns The device instance.
6469	*/
6470	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6471	{
6472	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6473	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6474
6475	/*
6476	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6477	*/
6478	if (pThisCC->svga.pFIFOIOThread)
6479	{
6480	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6481	NULL /pvParam/, 30000 /ms/);
6482	AssertLogRelRC(rc);
6483
6484	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6485	AssertLogRelRC(rc);
6486	pThisCC->svga.pFIFOIOThread = NULL;
6487	}
6488
6489	/*
6490	* Destroy the special SVGA state.
6491	*/
6492	if (pThisCC->svga.pSvgaR3State)
6493	{
6494	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6495
6496	RTMemFree(pThisCC->svga.pSvgaR3State);
6497	pThisCC->svga.pSvgaR3State = NULL;
6498	}
6499
6500	/*
6501	* Free our resources residing in the VGA state.
6502	*/
6503	if (pThisCC->svga.pbVgaFrameBufferR3)
6504	{
6505	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6506	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6507	}
6508	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6509	{
6510	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6511	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6512	}
6513	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6514	{
6515	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6516	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6517	}
6518
6519	return VINF_SUCCESS;
6520	}
6521
6522	/**
6523	* Initialize the SVGA hardware state
6524	*
6525	* @returns VBox status code.
6526	* @param pDevIns The device instance.
6527	*/
6528	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6529	{
6530	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6531	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6532	PVMSVGAR3STATE pSVGAState;
6533	int rc;
6534
6535	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6536	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6537
6538	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6539
6540	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6541	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6542	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6543
6544	/* Create event semaphore. */
6545	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6546	AssertRCReturn(rc, rc);
6547
6548	/* Create event semaphore. */
6549	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6550	AssertRCReturn(rc, rc);
6551
6552	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6553	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6554
6555	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6556	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6557
6558	pSVGAState = pThisCC->svga.pSvgaR3State;
6559
6560	/* Initialize FIFO and register capabilities. */
6561	vmsvgaR3InitCaps(pThis, pThisCC);
6562
6563	# ifdef VBOX_WITH_VMSVGA3D
6564	if (pThis->svga.f3DEnabled)
6565	{
6566	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6567	if (RT_FAILURE(rc))
6568	{
6569	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6570	pThis->svga.f3DEnabled = false;
6571	}
6572	}
6573	# endif
6574	/* VRAM tracking is enabled by default during bootup. */
6575	pThis->svga.fVRAMTracking = true;
6576
6577	/* Set up the host bpp. This value is as a default for the programmable
6578	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6579	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6580	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6581	*
6582	* NB: The driver cBits value is currently constant for the lifetime of the
6583	* VM. If that changes, the host bpp logic might need revisiting.
6584	*/
6585	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6586
6587	/* Invalidate current settings. */
6588	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6589	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6590	pThis->svga.uBpp = pThis->svga.uHostBpp;
6591	pThis->svga.cbScanline = 0;
6592
6593	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6594	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6595	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6596	{
6597	pThis->svga.u32MaxWidth -= 256;
6598	pThis->svga.u32MaxHeight -= 256;
6599	}
6600	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6601
6602	# ifdef DEBUG_GMR_ACCESS
6603	/* Register the GMR access handler type. */
6604	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6605	vmsvgaR3GmrAccessHandler,
6606	NULL, NULL, NULL,
6607	NULL, NULL, NULL,
6608	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6609	AssertRCReturn(rc, rc);
6610	# endif
6611
6612	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6613	/* Register the FIFO access handler type. In addition to
6614	debugging FIFO access, this is also used to facilitate
6615	extended fifo thread sleeps. */
6616	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6617	# ifdef DEBUG_FIFO_ACCESS
6618	PGMPHYSHANDLERKIND_ALL,
6619	# else
6620	PGMPHYSHANDLERKIND_WRITE,
6621	# endif
6622	vmsvgaR3FifoAccessHandler,
6623	NULL, NULL, NULL,
6624	NULL, NULL, NULL,
6625	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6626	AssertRCReturn(rc, rc);
6627	# endif
6628
6629	/* Create the async IO thread. */
6630	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6631	RTTHREADTYPE_IO, "VMSVGA FIFO");
6632	if (RT_FAILURE(rc))
6633	{
6634	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6635	return rc;
6636	}
6637
6638	/*
6639	* Statistics.
6640	*/
6641	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6642	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6643	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6644	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6645	# ifdef VBOX_WITH_STATISTICS
6646	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6647	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6648	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6649	# endif
6650	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6651	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6652	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6653	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6654	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6655	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6656	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6657	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6658	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6659	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6660	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6661	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6662	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6663	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6664	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6665	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6666	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6667	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6668	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6669	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6670	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6671	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6672	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6673	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6674	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6675	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6676	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6677	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6678	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6679	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6680	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6681	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6682	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6683	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6684	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6685	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6686	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6687	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6688	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6689	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6690	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6691	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6692	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6693	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6694	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6695	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6696	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6697	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6698	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6699	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6700	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6701	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6702	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6703	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6704	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6705	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6706	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6707	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6708	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6709
6710	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6711	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6712	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6713	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6714	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6715	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6716	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6717	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6718	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6719	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6720	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6721	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6722	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6723	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6724	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6725	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6726	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6727	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6728	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6729	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6730	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6731	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6732	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6733	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6734	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6735	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6736	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6737	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6738	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6739	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6740	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6741	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6742	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6743	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6744	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6745
6746	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6747	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6748	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6749	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6750	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6751	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6752	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6753	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6754	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6755	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6756	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6757	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6758	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6759	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6760	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6761	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6762	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6763	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6764	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6765	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6766	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6767	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6768	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6769	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6770	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6771	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6772	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6773	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6774	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6775	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6776	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6777	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6778	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6779	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6780	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6781	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6782	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6783	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6784	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6785	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6786	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6787	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6788	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6789	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6790	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6791	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6792	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6793	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6794	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6795	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6796	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6797	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6798
6799	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6800	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6801	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6802	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6803	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6804	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6805	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6806	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6807	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6808	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6809	# endif
6810	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6811	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6812	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6813	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6814	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6815
6816	# undef REG_CNT
6817	# undef REG_PRF
6818
6819	/*
6820	* Info handlers.
6821	*/
6822	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6823	# ifdef VBOX_WITH_VMSVGA3D
6824	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6825	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6826	"VMSVGA 3d surface details. "
6827	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6828	vmsvgaR3Info3dSurface);
6829	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6830	"VMSVGA 3d surface details and bitmap: "
6831	"sid[>dir]",
6832	vmsvgaR3Info3dSurfaceBmp);
6833	# endif
6834
6835	return VINF_SUCCESS;
6836	}
6837
6838	/**
6839	* Power On notification.
6840	*
6841	* @returns VBox status code.
6842	* @param pDevIns The device instance data.
6843	*
6844	* @remarks Caller enters the device critical section.
6845	*/
6846	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6847	{
6848	# ifdef VBOX_WITH_VMSVGA3D
6849	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6850	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6851	if (pThis->svga.f3DEnabled)
6852	{
6853	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6854
6855	if (RT_SUCCESS(rc))
6856	{
6857	/* Initialize FIFO 3D capabilities. */
6858	vmsvgaR3InitFifo3DCaps(pThisCC);
6859	}
6860	}
6861	# else /* !VBOX_WITH_VMSVGA3D */
6862	RT_NOREF(pDevIns);
6863	# endif /* !VBOX_WITH_VMSVGA3D */
6864	}
6865
6866	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 84677

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