DevVGA-SVGA.cpp@ 84722

Last change on this file since 84722 was 84722, checked in by vboxsync, 5 years ago
bugref:9637. setting vmsvga relevant functions in DevVGA only when vmsvga is used.
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1	/* $Id: DevVGA-SVGA.cpp 84722 2020-06-08 10:57:01Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	*/
16
17	/*
18	* Copyright (C) 2013-2020 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
31	*
32	* This device emulation was contributed by trivirt AG. It offers an
33	* alternative to our Bochs based VGA graphics and 3d emulations. This is
34	* valuable for Xorg based guests, as there is driver support shipping with Xorg
35	* since it forked from XFree86.
36	*
37	*
38	* @section sec_dev_vmsvga_sdk The VMware SDK
39	*
40	* This is officially deprecated now, however it's still quite useful,
41	* especially for getting the old features working:
42	* http://vmware-svga.sourceforge.net/
43	*
44	* They currently point developers at the following resources.
45	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
46	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
47	* - http://cgit.freedesktop.org/mesa/vmwgfx/
48	*
49	* @subsection subsec_dev_vmsvga_sdk_results Test results
50	*
51	* Test results:
52	* - 2dmark.img:
53	* + todo
54	* - backdoor-tclo.img:
55	* + todo
56	* - blit-cube.img:
57	* + todo
58	* - bunnies.img:
59	* + todo
60	* - cube.img:
61	* + todo
62	* - cubemark.img:
63	* + todo
64	* - dynamic-vertex-stress.img:
65	* + todo
66	* - dynamic-vertex.img:
67	* + todo
68	* - fence-stress.img:
69	* + todo
70	* - gmr-test.img:
71	* + todo
72	* - half-float-test.img:
73	* + todo
74	* - noscreen-cursor.img:
75	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
76	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
77	* visible though.)
78	* - Cursor animation via the palette doesn't work.
79	* - During debugging, it turns out that the framebuffer content seems to
80	* be halfways ignore or something (memset(fb, 0xcc, lots)).
81	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
82	* grow it 0x10 fold (128KB -> 2MB like in WS10).
83	* - null.img:
84	* + todo
85	* - pong.img:
86	* + todo
87	* - presentReadback.img:
88	* + todo
89	* - resolution-set.img:
90	* + todo
91	* - rt-gamma-test.img:
92	* + todo
93	* - screen-annotation.img:
94	* + todo
95	* - screen-cursor.img:
96	* + todo
97	* - screen-dma-coalesce.img:
98	* + todo
99	* - screen-gmr-discontig.img:
100	* + todo
101	* - screen-gmr-remap.img:
102	* + todo
103	* - screen-multimon.img:
104	* + todo
105	* - screen-present-clip.img:
106	* + todo
107	* - screen-render-test.img:
108	* + todo
109	* - screen-simple.img:
110	* + todo
111	* - screen-text.img:
112	* + todo
113	* - simple-shaders.img:
114	* + todo
115	* - simple_blit.img:
116	* + todo
117	* - tiny-2d-updates.img:
118	* + todo
119	* - video-formats.img:
120	* + todo
121	* - video-sync.img:
122	* + todo
123	*
124	*/
125
126
127	/*********************************************************************************************************************************
128	* Header Files *
129	*********************************************************************************************************************************/
130	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
131	#define VMSVGA_USE_EMT_HALT_CODE
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#ifdef VMSVGA_USE_EMT_HALT_CODE
138	# include <VBox/vmm/vmapi.h>
139	# include <VBox/vmm/vmcpuset.h>
140	#endif
141	#include <VBox/sup.h>
142
143	#include <iprt/assert.h>
144	#include <iprt/semaphore.h>
145	#include <iprt/uuid.h>
146	#ifdef IN_RING3
147	# include <iprt/ctype.h>
148	# include <iprt/mem.h>
149	# ifdef VBOX_STRICT
150	# include <iprt/time.h>
151	# endif
152	#endif
153
154	#include <VBox/AssertGuest.h>
155	#include <VBox/VMMDev.h>
156	#include <VBoxVideo.h>
157	#include <VBox/bioslogo.h>
158
159	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
160	#include "DevVGA.h"
161
162	#include "DevVGA-SVGA.h"
163	#include "vmsvga/svga_escape.h"
164	#include "vmsvga/svga_overlay.h"
165	#include "vmsvga/svga3d_caps.h"
166	#ifdef VBOX_WITH_VMSVGA3D
167	# include "DevVGA-SVGA3d.h"
168	# ifdef RT_OS_DARWIN
169	# include "DevVGA-SVGA3d-cocoa.h"
170	# endif
171	#endif
172
173
174	/*********************************************************************************************************************************
175	* Defined Constants And Macros *
176	*********************************************************************************************************************************/
177	/**
178	* Macro for checking if a fixed FIFO register is valid according to the
179	* current FIFO configuration.
180	*
181	* @returns true / false.
182	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
183	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
184	*/
185	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
186
187
188	/*********************************************************************************************************************************
189	* Structures and Typedefs *
190	*********************************************************************************************************************************/
191	/**
192	* 64-bit GMR descriptor.
193	*/
194	typedef struct
195	{
196	RTGCPHYS GCPhys;
197	uint64_t numPages;
198	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
199
200	/**
201	* GMR slot
202	*/
203	typedef struct
204	{
205	uint32_t cMaxPages;
206	uint32_t cbTotal;
207	uint32_t numDescriptors;
208	PVMSVGAGMRDESCRIPTOR paDesc;
209	} GMR, *PGMR;
210
211	#ifdef IN_RING3
212	/**
213	* Internal SVGA ring-3 only state.
214	*/
215	typedef struct VMSVGAR3STATE
216	{
217	GMR *paGMR; // [VMSVGAState::cGMR]
218	struct
219	{
220	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
221	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
222	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
223	} GMRFB;
224	struct
225	{
226	bool fActive;
227	uint32_t xHotspot;
228	uint32_t yHotspot;
229	uint32_t width;
230	uint32_t height;
231	uint32_t cbData;
232	void *pData;
233	} Cursor;
234	SVGAColorBGRX colorAnnotation;
235
236	# ifdef VMSVGA_USE_EMT_HALT_CODE
237	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
238	uint32_t volatile cBusyDelayedEmts;
239	/** Set of EMTs that are */
240	VMCPUSET BusyDelayedEmts;
241	# else
242	/** Number of EMTs waiting on hBusyDelayedEmts. */
243	uint32_t volatile cBusyDelayedEmts;
244	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
245	* busy (ugly). */
246	RTSEMEVENTMULTI hBusyDelayedEmts;
247	# endif
248
249	/** Information obout screens. */
250	VMSVGASCREENOBJECT aScreens[64];
251
252	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
253	STAMPROFILE StatBusyDelayEmts;
254
255	STAMPROFILE StatR3Cmd3dPresentProf;
256	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
257	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
258	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
259	STAMCOUNTER StatR3CmdDefineGmr2;
260	STAMCOUNTER StatR3CmdDefineGmr2Free;
261	STAMCOUNTER StatR3CmdDefineGmr2Modify;
262	STAMCOUNTER StatR3CmdRemapGmr2;
263	STAMCOUNTER StatR3CmdRemapGmr2Modify;
264	STAMCOUNTER StatR3CmdInvalidCmd;
265	STAMCOUNTER StatR3CmdFence;
266	STAMCOUNTER StatR3CmdUpdate;
267	STAMCOUNTER StatR3CmdUpdateVerbose;
268	STAMCOUNTER StatR3CmdDefineCursor;
269	STAMCOUNTER StatR3CmdDefineAlphaCursor;
270	STAMCOUNTER StatR3CmdMoveCursor;
271	STAMCOUNTER StatR3CmdDisplayCursor;
272	STAMCOUNTER StatR3CmdRectFill;
273	STAMCOUNTER StatR3CmdRectCopy;
274	STAMCOUNTER StatR3CmdRectRopCopy;
275	STAMCOUNTER StatR3CmdEscape;
276	STAMCOUNTER StatR3CmdDefineScreen;
277	STAMCOUNTER StatR3CmdDestroyScreen;
278	STAMCOUNTER StatR3CmdDefineGmrFb;
279	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
280	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
281	STAMCOUNTER StatR3CmdAnnotationFill;
282	STAMCOUNTER StatR3CmdAnnotationCopy;
283	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
284	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
285	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
286	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
287	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
288	STAMCOUNTER StatR3Cmd3dSurfaceDma;
289	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
290	STAMCOUNTER StatR3Cmd3dContextDefine;
291	STAMCOUNTER StatR3Cmd3dContextDestroy;
292	STAMCOUNTER StatR3Cmd3dSetTransform;
293	STAMCOUNTER StatR3Cmd3dSetZRange;
294	STAMCOUNTER StatR3Cmd3dSetRenderState;
295	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
296	STAMCOUNTER StatR3Cmd3dSetTextureState;
297	STAMCOUNTER StatR3Cmd3dSetMaterial;
298	STAMCOUNTER StatR3Cmd3dSetLightData;
299	STAMCOUNTER StatR3Cmd3dSetLightEnable;
300	STAMCOUNTER StatR3Cmd3dSetViewPort;
301	STAMCOUNTER StatR3Cmd3dSetClipPlane;
302	STAMCOUNTER StatR3Cmd3dClear;
303	STAMCOUNTER StatR3Cmd3dPresent;
304	STAMCOUNTER StatR3Cmd3dPresentReadBack;
305	STAMCOUNTER StatR3Cmd3dShaderDefine;
306	STAMCOUNTER StatR3Cmd3dShaderDestroy;
307	STAMCOUNTER StatR3Cmd3dSetShader;
308	STAMCOUNTER StatR3Cmd3dSetShaderConst;
309	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
310	STAMCOUNTER StatR3Cmd3dSetScissorRect;
311	STAMCOUNTER StatR3Cmd3dBeginQuery;
312	STAMCOUNTER StatR3Cmd3dEndQuery;
313	STAMCOUNTER StatR3Cmd3dWaitForQuery;
314	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
315	STAMCOUNTER StatR3Cmd3dActivateSurface;
316	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
317
318	STAMCOUNTER StatR3RegConfigDoneWr;
319	STAMCOUNTER StatR3RegGmrDescriptorWr;
320	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
321	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
322
323	STAMCOUNTER StatFifoCommands;
324	STAMCOUNTER StatFifoErrors;
325	STAMCOUNTER StatFifoUnkCmds;
326	STAMCOUNTER StatFifoTodoTimeout;
327	STAMCOUNTER StatFifoTodoWoken;
328	STAMPROFILE StatFifoStalls;
329	STAMPROFILE StatFifoExtendedSleep;
330	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
331	STAMCOUNTER StatFifoAccessHandler;
332	# endif
333	STAMCOUNTER StatFifoCursorFetchAgain;
334	STAMCOUNTER StatFifoCursorNoChange;
335	STAMCOUNTER StatFifoCursorPosition;
336	STAMCOUNTER StatFifoCursorVisiblity;
337	STAMCOUNTER StatFifoWatchdogWakeUps;
338	} VMSVGAR3STATE, *PVMSVGAR3STATE;
339	#endif /* IN_RING3 */
340
341
342	/*********************************************************************************************************************************
343	* Internal Functions *
344	*********************************************************************************************************************************/
345	#ifdef IN_RING3
346	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
347	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
348	# endif
349	# ifdef DEBUG_GMR_ACCESS
350	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
351	# endif
352	#endif
353
354
355	/*********************************************************************************************************************************
356	* Global Variables *
357	*********************************************************************************************************************************/
358	#ifdef IN_RING3
359
360	/**
361	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
362	*/
363	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
364	{
365	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
366	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
367	SSMFIELD_ENTRY_TERM()
368	};
369
370	/**
371	* SSM descriptor table for the GMR structure.
372	*/
373	static SSMFIELD const g_aGMRFields[] =
374	{
375	SSMFIELD_ENTRY( GMR, cMaxPages),
376	SSMFIELD_ENTRY( GMR, cbTotal),
377	SSMFIELD_ENTRY( GMR, numDescriptors),
378	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
379	SSMFIELD_ENTRY_TERM()
380	};
381
382	/**
383	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
384	*/
385	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
386	{
387	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
388	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
389	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
395	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
396	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
397	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
398	SSMFIELD_ENTRY_TERM()
399	};
400
401	/**
402	* SSM descriptor table for the VMSVGAR3STATE structure.
403	*/
404	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
405	{
406	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
407	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
408	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
409	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
411	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
412	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
413	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
414	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
415	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
416	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
417	#ifdef VMSVGA_USE_EMT_HALT_CODE
418	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
419	#else
420	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
421	#endif
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
485
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
490
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
498	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
500	# endif
501	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
504	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
505
506	SSMFIELD_ENTRY_TERM()
507	};
508
509	/**
510	* SSM descriptor table for the VGAState.svga structure.
511	*/
512	static SSMFIELD const g_aVGAStateSVGAFields[] =
513	{
514	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
515	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
516	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
517	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
518	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
519	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
520	SSMFIELD_ENTRY( VMSVGAState, fBusy),
521	SSMFIELD_ENTRY( VMSVGAState, fTraces),
522	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
523	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
524	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
525	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
526	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
527	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
528	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
529	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
530	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
531	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
532	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
533	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
534	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
535	SSMFIELD_ENTRY( VMSVGAState, uWidth),
536	SSMFIELD_ENTRY( VMSVGAState, uHeight),
537	SSMFIELD_ENTRY( VMSVGAState, uBpp),
538	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
539	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
540	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
541	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
542	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
543	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
544	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
545	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
546	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
547	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
548	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
549	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
550	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
551	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
552	SSMFIELD_ENTRY_TERM()
553	};
554	#endif /* IN_RING3 */
555
556
557	/*********************************************************************************************************************************
558	* Internal Functions *
559	*********************************************************************************************************************************/
560	#ifdef IN_RING3
561	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
562	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
563	uint32_t uVersion, uint32_t uPass);
564	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
565	# ifdef VBOX_WITH_VMSVGA3D
566	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
567	# endif /* VBOX_WITH_VMSVGA3D */
568	#endif /* IN_RING3 */
569
570
571
572	#ifdef IN_RING3
573	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
574	{
575	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
576	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
577	&& pSVGAState
578	&& pSVGAState->aScreens[idScreen].fDefined)
579	{
580	return &pSVGAState->aScreens[idScreen];
581	}
582	return NULL;
583	}
584	#endif /* IN_RING3 */
585
586	#ifdef LOG_ENABLED
587
588	/**
589	* Index register string name lookup
590	*
591	* @returns Index register string or "UNKNOWN"
592	* @param pThis The shared VGA/VMSVGA state.
593	* @param idxReg The index register.
594	*/
595	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
596	{
597	switch (idxReg)
598	{
599	case SVGA_REG_ID: return "SVGA_REG_ID";
600	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
601	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
602	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
603	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
604	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
605	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
606	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
607	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
608	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
609	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
610	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
611	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
612	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
613	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
614	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
615	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
616	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
617	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
618	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
619	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
620	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
621	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
622	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
623	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
624	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
625	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
626	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
627	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
628	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
629	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
630	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
631	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
632	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
633	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
634	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
635	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
636	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
637	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
638	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
639	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
640	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
641	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
642	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
643	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
644	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
645	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
646	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
647	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
648	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
649
650	default:
651	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
652	return "SVGA_SCRATCH_BASE reg";
653	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
654	return "SVGA_PALETTE_BASE reg";
655	return "UNKNOWN";
656	}
657	}
658
659	#ifdef IN_RING3
660	/**
661	* FIFO command name lookup
662	*
663	* @returns FIFO command string or "UNKNOWN"
664	* @param u32Cmd FIFO command
665	*/
666	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
667	{
668	switch (u32Cmd)
669	{
670	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
671	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
672	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
673	case SVGA_CMD_RECT_ROP_COPY: return "SVGA_CMD_RECT_ROP_COPY";
674	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
675	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
676	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
677	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
678	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
679	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
680	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
681	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
682	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
683	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
684	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
685	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
686	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
687	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
688	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
689	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
690	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
691	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
692	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
693	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
694	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
695	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
696	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
697	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
698	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
699	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
700	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
701	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
702	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
703	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
704	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
705	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
706	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
707	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
708	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
709	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
710	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
711	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
712	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
713	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
714	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
715	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
716	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
717	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
718	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
719	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
720	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
721	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
722	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
723	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
724	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
725	default: return "UNKNOWN";
726	}
727	}
728	# endif /* IN_RING3 */
729
730	#endif /* LOG_ENABLED */
731	#ifdef IN_RING3
732
733	/**
734	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
735	*/
736	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
737	{
738	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
739	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
740
741	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
742	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
743
744	/** @todo Test how it interacts with multiple screen objects. */
745	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
746	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
747	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
748
749	if (x < uWidth)
750	{
751	pThis->svga.viewport.x = x;
752	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
753	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
754	}
755	else
756	{
757	pThis->svga.viewport.x = uWidth;
758	pThis->svga.viewport.cx = 0;
759	pThis->svga.viewport.xRight = uWidth;
760	}
761	if (y < uHeight)
762	{
763	pThis->svga.viewport.y = y;
764	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
765	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
766	pThis->svga.viewport.yHighWC = uHeight - y;
767	}
768	else
769	{
770	pThis->svga.viewport.y = uHeight;
771	pThis->svga.viewport.cy = 0;
772	pThis->svga.viewport.yLowWC = 0;
773	pThis->svga.viewport.yHighWC = 0;
774	}
775
776	# ifdef VBOX_WITH_VMSVGA3D
777	/*
778	* Now inform the 3D backend.
779	*/
780	if (pThis->svga.f3DEnabled)
781	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
782	# else
783	RT_NOREF(OldViewport);
784	# endif
785	}
786
787
788	/**
789	* Updating screen information in API
790	*
791	* @param pThis The The shared VGA/VMSVGA instance data.
792	* @param pThisCC The VGA/VMSVGA state for ring-3.
793	*/
794	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
795	{
796	int rc;
797
798	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
799
800	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
801	{
802	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
803	if (!pScreen->fModified)
804	continue;
805
806	pScreen->fModified = false;
807
808	VBVAINFOVIEW view;
809	RT_ZERO(view);
810	view.u32ViewIndex = pScreen->idScreen;
811	// view.u32ViewOffset = 0;
812	view.u32ViewSize = pThis->vram_size;
813	view.u32MaxScreenSize = pThis->vram_size;
814
815	VBVAINFOSCREEN screen;
816	RT_ZERO(screen);
817	screen.u32ViewIndex = pScreen->idScreen;
818
819	if (pScreen->fDefined)
820	{
821	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
822	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
823	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
824	{
825	Assert(pThis->svga.fGFBRegisters);
826	continue;
827	}
828
829	screen.i32OriginX = pScreen->xOrigin;
830	screen.i32OriginY = pScreen->yOrigin;
831	screen.u32StartOffset = pScreen->offVRAM;
832	screen.u32LineSize = pScreen->cbPitch;
833	screen.u32Width = pScreen->cWidth;
834	screen.u32Height = pScreen->cHeight;
835	screen.u16BitsPerPixel = pScreen->cBpp;
836	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
837	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
838	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
839	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
840	}
841	else
842	{
843	/* Screen is destroyed. */
844	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
845	}
846
847	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
848	AssertRC(rc);
849	}
850	}
851
852
853	/**
854	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
855	*
856	* Used to update screen offsets (positions) since appearently vmwgfx fails to
857	* pass correct offsets thru FIFO.
858	*/
859	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
860	{
861	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
862	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
863	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
864
865	AssertReturnVoid(pSVGAState);
866
867	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
868	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
869	for (uint32_t i = 0; i < cPositions; ++i)
870	{
871	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
872	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
873	continue;
874
875	if (pSVGAState->aScreens[i].xOrigin == -1)
876	continue;
877	if (pSVGAState->aScreens[i].yOrigin == -1)
878	continue;
879
880	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
881	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
882	pSVGAState->aScreens[i].fModified = true;
883	}
884
885	vmsvgaR3VBVAResize(pThis, pThisCC);
886	}
887
888	#endif /* IN_RING3 */
889
890	/**
891	* Read port register
892	*
893	* @returns VBox status code.
894	* @param pDevIns The device instance.
895	* @param pThis The shared VGA/VMSVGA state.
896	* @param pu32 Where to store the read value
897	*/
898	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
899	{
900	#ifdef IN_RING3
901	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
902	#endif
903	int rc = VINF_SUCCESS;
904	*pu32 = 0;
905
906	/* Rough index register validation. */
907	uint32_t idxReg = pThis->svga.u32IndexReg;
908	#if !defined(IN_RING3) && defined(VBOX_STRICT)
909	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
910	VINF_IOM_R3_IOPORT_READ);
911	#else
912	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
913	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
914	VINF_SUCCESS);
915	#endif
916	RT_UNTRUSTED_VALIDATED_FENCE();
917
918	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
919	if ( idxReg >= SVGA_REG_CAPABILITIES
920	&& pThis->svga.u32SVGAId == SVGA_ID_0)
921	{
922	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
923	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
924	}
925
926	switch (idxReg)
927	{
928	case SVGA_REG_ID:
929	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
930	*pu32 = pThis->svga.u32SVGAId;
931	break;
932
933	case SVGA_REG_ENABLE:
934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
935	*pu32 = pThis->svga.fEnabled;
936	break;
937
938	case SVGA_REG_WIDTH:
939	{
940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
941	if ( pThis->svga.fEnabled
942	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
943	*pu32 = pThis->svga.uWidth;
944	else
945	{
946	#ifndef IN_RING3
947	rc = VINF_IOM_R3_IOPORT_READ;
948	#else
949	*pu32 = pThisCC->pDrv->cx;
950	#endif
951	}
952	break;
953	}
954
955	case SVGA_REG_HEIGHT:
956	{
957	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
958	if ( pThis->svga.fEnabled
959	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
960	*pu32 = pThis->svga.uHeight;
961	else
962	{
963	#ifndef IN_RING3
964	rc = VINF_IOM_R3_IOPORT_READ;
965	#else
966	*pu32 = pThisCC->pDrv->cy;
967	#endif
968	}
969	break;
970	}
971
972	case SVGA_REG_MAX_WIDTH:
973	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
974	*pu32 = pThis->svga.u32MaxWidth;
975	break;
976
977	case SVGA_REG_MAX_HEIGHT:
978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
979	*pu32 = pThis->svga.u32MaxHeight;
980	break;
981
982	case SVGA_REG_DEPTH:
983	/* This returns the color depth of the current mode. */
984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
985	switch (pThis->svga.uBpp)
986	{
987	case 15:
988	case 16:
989	case 24:
990	*pu32 = pThis->svga.uBpp;
991	break;
992
993	default:
994	case 32:
995	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
996	break;
997	}
998	break;
999
1000	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1002	*pu32 = pThis->svga.uHostBpp;
1003	break;
1004
1005	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1006	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1007	*pu32 = pThis->svga.uBpp;
1008	break;
1009
1010	case SVGA_REG_PSEUDOCOLOR:
1011	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1012	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1013	break;
1014
1015	case SVGA_REG_RED_MASK:
1016	case SVGA_REG_GREEN_MASK:
1017	case SVGA_REG_BLUE_MASK:
1018	{
1019	uint32_t uBpp;
1020
1021	if (pThis->svga.fEnabled)
1022	uBpp = pThis->svga.uBpp;
1023	else
1024	uBpp = pThis->svga.uHostBpp;
1025
1026	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1027	switch (uBpp)
1028	{
1029	case 8:
1030	u32RedMask = 0x07;
1031	u32GreenMask = 0x38;
1032	u32BlueMask = 0xc0;
1033	break;
1034
1035	case 15:
1036	u32RedMask = 0x0000001f;
1037	u32GreenMask = 0x000003e0;
1038	u32BlueMask = 0x00007c00;
1039	break;
1040
1041	case 16:
1042	u32RedMask = 0x0000001f;
1043	u32GreenMask = 0x000007e0;
1044	u32BlueMask = 0x0000f800;
1045	break;
1046
1047	case 24:
1048	case 32:
1049	default:
1050	u32RedMask = 0x00ff0000;
1051	u32GreenMask = 0x0000ff00;
1052	u32BlueMask = 0x000000ff;
1053	break;
1054	}
1055	switch (idxReg)
1056	{
1057	case SVGA_REG_RED_MASK:
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1059	*pu32 = u32RedMask;
1060	break;
1061
1062	case SVGA_REG_GREEN_MASK:
1063	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1064	*pu32 = u32GreenMask;
1065	break;
1066
1067	case SVGA_REG_BLUE_MASK:
1068	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1069	*pu32 = u32BlueMask;
1070	break;
1071	}
1072	break;
1073	}
1074
1075	case SVGA_REG_BYTES_PER_LINE:
1076	{
1077	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1078	if ( pThis->svga.fEnabled
1079	&& pThis->svga.cbScanline)
1080	*pu32 = pThis->svga.cbScanline;
1081	else
1082	{
1083	#ifndef IN_RING3
1084	rc = VINF_IOM_R3_IOPORT_READ;
1085	#else
1086	*pu32 = pThisCC->pDrv->cbScanline;
1087	#endif
1088	}
1089	break;
1090	}
1091
1092	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1093	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1094	*pu32 = pThis->vram_size;
1095	break;
1096
1097	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1098	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1099	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1100	*pu32 = pThis->GCPhysVRAM;
1101	break;
1102
1103	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1104	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1105	/* Always zero in our case. */
1106	*pu32 = 0;
1107	break;
1108
1109	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1110	{
1111	#ifndef IN_RING3
1112	rc = VINF_IOM_R3_IOPORT_READ;
1113	#else
1114	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1115
1116	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1117	if ( pThis->svga.fEnabled
1118	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1119	{
1120	/* Hardware enabled; return real framebuffer size .*/
1121	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1122	}
1123	else
1124	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1125
1126	pu32 = RT_MIN(pThis->vram_size, pu32);
1127	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1128	#endif
1129	break;
1130	}
1131
1132	case SVGA_REG_CAPABILITIES:
1133	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1134	*pu32 = pThis->svga.u32RegCaps;
1135	break;
1136
1137	case SVGA_REG_MEM_START: /* FIFO start */
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1139	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1140	*pu32 = pThis->svga.GCPhysFIFO;
1141	break;
1142
1143	case SVGA_REG_MEM_SIZE: /* FIFO size */
1144	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1145	*pu32 = pThis->svga.cbFIFO;
1146	break;
1147
1148	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1149	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1150	*pu32 = pThis->svga.fConfigured;
1151	break;
1152
1153	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1154	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1155	*pu32 = 0;
1156	break;
1157
1158	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1159	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1160	if (pThis->svga.fBusy)
1161	{
1162	#ifndef IN_RING3
1163	/* Go to ring-3 and halt the CPU. */
1164	rc = VINF_IOM_R3_IOPORT_READ;
1165	RT_NOREF(pDevIns);
1166	break;
1167	#else
1168	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1169	/* The guest is basically doing a HLT via the device here, but with
1170	a special wake up condition on FIFO completion. */
1171	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1172	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1173	PVM pVM = PDMDevHlpGetVM(pDevIns);
1174	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1175	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1176	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1177	if (pThis->svga.fBusy)
1178	{
1179	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1180	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1181	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1182	}
1183	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1184	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1185	# else
1186
1187	/* Delay the EMT a bit so the FIFO and others can get some work done.
1188	This used to be a crude 50 ms sleep. The current code tries to be
1189	more efficient, but the consept is still very crude. */
1190	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1191	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1192	RTThreadYield();
1193	if (pThis->svga.fBusy)
1194	{
1195	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1196
1197	if (pThis->svga.fBusy && cRefs == 1)
1198	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1199	if (pThis->svga.fBusy)
1200	{
1201	/** @todo If this code is going to stay, we need to call into the halt/wait
1202	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1203	* suffer when the guest is polling on a busy FIFO. */
1204	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1205	if (cNsMaxWait >= RT_NS_100US)
1206	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1207	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1208	RT_MIN(cNsMaxWait, RT_NS_10MS));
1209	}
1210
1211	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1212	}
1213	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1214	# endif
1215	*pu32 = pThis->svga.fBusy != 0;
1216	#endif
1217	}
1218	else
1219	*pu32 = false;
1220	break;
1221
1222	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1223	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1224	*pu32 = pThis->svga.u32GuestId;
1225	break;
1226
1227	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1228	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1229	*pu32 = pThis->svga.cScratchRegion;
1230	break;
1231
1232	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1233	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1234	*pu32 = SVGA_FIFO_NUM_REGS;
1235	break;
1236
1237	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1238	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1239	*pu32 = pThis->svga.u32PitchLock;
1240	break;
1241
1242	case SVGA_REG_IRQMASK: /* Interrupt mask */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1244	*pu32 = pThis->svga.u32IrqMask;
1245	break;
1246
1247	/* See "Guest memory regions" below. */
1248	case SVGA_REG_GMR_ID:
1249	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1250	*pu32 = pThis->svga.u32CurrentGMRId;
1251	break;
1252
1253	case SVGA_REG_GMR_DESCRIPTOR:
1254	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1255	/* Write only */
1256	*pu32 = 0;
1257	break;
1258
1259	case SVGA_REG_GMR_MAX_IDS:
1260	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1261	*pu32 = pThis->svga.cGMR;
1262	break;
1263
1264	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1265	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1266	*pu32 = VMSVGA_MAX_GMR_PAGES;
1267	break;
1268
1269	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1270	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1271	*pu32 = pThis->svga.fTraces;
1272	break;
1273
1274	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1275	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1276	*pu32 = VMSVGA_MAX_GMR_PAGES;
1277	break;
1278
1279	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1281	*pu32 = VMSVGA_SURFACE_SIZE;
1282	break;
1283
1284	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1286	break;
1287
1288	/* Mouse cursor support. */
1289	case SVGA_REG_CURSOR_ID:
1290	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1291	*pu32 = pThis->svga.uCursorID;
1292	break;
1293
1294	case SVGA_REG_CURSOR_X:
1295	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1296	*pu32 = pThis->svga.uCursorX;
1297	break;
1298
1299	case SVGA_REG_CURSOR_Y:
1300	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1301	*pu32 = pThis->svga.uCursorY;
1302	break;
1303
1304	case SVGA_REG_CURSOR_ON:
1305	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1306	*pu32 = pThis->svga.uCursorOn;
1307	break;
1308
1309	/* Legacy multi-monitor support */
1310	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1311	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1312	*pu32 = 1;
1313	break;
1314
1315	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1316	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1317	*pu32 = 0;
1318	break;
1319
1320	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1321	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1322	*pu32 = 0;
1323	break;
1324
1325	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1326	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1327	*pu32 = 0;
1328	break;
1329
1330	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1332	*pu32 = 0;
1333	break;
1334
1335	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1337	*pu32 = pThis->svga.uWidth;
1338	break;
1339
1340	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1342	*pu32 = pThis->svga.uHeight;
1343	break;
1344
1345	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1347	/* We must return something sensible here otherwise the Linux driver
1348	will take a legacy code path without 3d support. This number also
1349	limits how many screens Linux guests will allow. */
1350	*pu32 = pThis->cMonitors;
1351	break;
1352
1353	default:
1354	{
1355	uint32_t offReg;
1356	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1357	{
1358	RT_UNTRUSTED_VALIDATED_FENCE();
1359	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1360	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1361	}
1362	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1363	{
1364	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1365	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1366	RT_UNTRUSTED_VALIDATED_FENCE();
1367	uint32_t u32 = pThis->last_palette[offReg / 3];
1368	switch (offReg % 3)
1369	{
1370	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1371	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1372	case 2: pu32 = u32 & 0xff; break; / blue */
1373	}
1374	}
1375	else
1376	{
1377	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1378	rc = VINF_IOM_R3_IOPORT_READ;
1379	#else
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1381
1382	/* Do not assert. The guest might be reading all registers. */
1383	LogFunc(("Unknown reg=%#x\n", idxReg));
1384	#endif
1385	}
1386	break;
1387	}
1388	}
1389	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1390	return rc;
1391	}
1392
1393	#ifdef IN_RING3
1394	/**
1395	* Apply the current resolution settings to change the video mode.
1396	*
1397	* @returns VBox status code.
1398	* @param pThis The shared VGA state.
1399	* @param pThisCC The ring-3 VGA state.
1400	*/
1401	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1402	{
1403	/* Always do changemode on FIFO thread. */
1404	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1405
1406	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1407
1408	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1409
1410	if (pThis->svga.fGFBRegisters)
1411	{
1412	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1413	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1414	* deletes all screens other than screen #0, and redefines screen
1415	* #0 according to the specified mode. Drivers that use
1416	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1417	*/
1418
1419	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1420	pScreen->fDefined = true;
1421	pScreen->fModified = true;
1422	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1423	pScreen->idScreen = 0;
1424	pScreen->xOrigin = 0;
1425	pScreen->yOrigin = 0;
1426	pScreen->offVRAM = 0;
1427	pScreen->cbPitch = pThis->svga.cbScanline;
1428	pScreen->cWidth = pThis->svga.uWidth;
1429	pScreen->cHeight = pThis->svga.uHeight;
1430	pScreen->cBpp = pThis->svga.uBpp;
1431
1432	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1433	{
1434	/* Delete screen. */
1435	pScreen = &pSVGAState->aScreens[iScreen];
1436	if (pScreen->fDefined)
1437	{
1438	pScreen->fModified = true;
1439	pScreen->fDefined = false;
1440	}
1441	}
1442	}
1443	else
1444	{
1445	/* "If Screen Objects are supported, they can be used to fully
1446	* replace the functionality provided by the framebuffer registers
1447	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1448	*/
1449	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1450	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1451	pThis->svga.uBpp = pThis->svga.uHostBpp;
1452	}
1453
1454	vmsvgaR3VBVAResize(pThis, pThisCC);
1455
1456	/* Last stuff. For the VGA device screenshot. */
1457	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1458	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1459	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1460	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1461	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1462
1463	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1464	if ( pThis->svga.viewport.cx == 0
1465	&& pThis->svga.viewport.cy == 0)
1466	{
1467	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1468	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1469	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1470	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1471	pThis->svga.viewport.yLowWC = 0;
1472	}
1473
1474	return VINF_SUCCESS;
1475	}
1476
1477	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1478	{
1479	VBVACMDHDR cmd;
1480	cmd.x = (int16_t)(pScreen->xOrigin + x);
1481	cmd.y = (int16_t)(pScreen->yOrigin + y);
1482	cmd.w = (uint16_t)w;
1483	cmd.h = (uint16_t)h;
1484
1485	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1486	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1487	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1488	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1489
1490	return VINF_SUCCESS;
1491	}
1492
1493	#endif /* IN_RING3 */
1494	#if defined(IN_RING0) \|\| defined(IN_RING3)
1495
1496	/**
1497	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1498	*
1499	* @param pThis The shared VGA/VMSVGA instance data.
1500	* @param pThisCC The VGA/VMSVGA state for the current context.
1501	* @param fState The busy state.
1502	*/
1503	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1504	{
1505	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1506
1507	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1508	{
1509	/* Race / unfortunately scheduling. Highly unlikly. */
1510	uint32_t cLoops = 64;
1511	do
1512	{
1513	ASMNopPause();
1514	fState = (pThis->svga.fBusy != 0);
1515	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1516	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1517	}
1518	}
1519
1520
1521	/**
1522	* Update the scanline pitch in response to the guest changing mode
1523	* width/bpp.
1524	*
1525	* @param pThis The shared VGA/VMSVGA state.
1526	* @param pThisCC The VGA/VMSVGA state for the current context.
1527	*/
1528	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1529	{
1530	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1531	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1532	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1533	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1534
1535	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1536	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1537	* location but it has a different meaning.
1538	*/
1539	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1540	uFifoPitchLock = 0;
1541
1542	/* Sanitize values. */
1543	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1544	uFifoPitchLock = 0;
1545	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1546	uRegPitchLock = 0;
1547
1548	/* Prefer the register value to the FIFO value.*/
1549	if (uRegPitchLock)
1550	pThis->svga.cbScanline = uRegPitchLock;
1551	else if (uFifoPitchLock)
1552	pThis->svga.cbScanline = uFifoPitchLock;
1553	else
1554	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1555
1556	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1557	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1558	}
1559
1560	#endif /* IN_RING0 \|\| IN_RING3 */
1561
1562	#ifdef IN_RING3
1563
1564	/**
1565	* Sends cursor position and visibility information from legacy
1566	* SVGA registers to the front-end.
1567	*/
1568	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1569	{
1570	/*
1571	* Writing the X/Y/ID registers does not trigger changes; only writing the
1572	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1573	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1574	* register if they don't have to.
1575	*/
1576	uint32_t x, y, idScreen;
1577	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1578
1579	x = pThis->svga.uCursorX;
1580	y = pThis->svga.uCursorY;
1581	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1582
1583	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1584	* were extended as follows:
1585	*
1586	* SVGA_CURSOR_ON_HIDE 0
1587	* SVGA_CURSOR_ON_SHOW 1
1588	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1589	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1590	*
1591	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1592	* distinguish between the non-zero values but still remember them.
1593	*/
1594	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1595	{
1596	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1597	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1598	}
1599	pThis->svga.uCursorOn = uCursorOn;
1600	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1601	}
1602
1603
1604	/**
1605	* Copy a rectangle of pixels within guest VRAM.
1606	*/
1607	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1608	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1609	{
1610	if (!width \|\| !height)
1611	return; /* Nothing to do, don't even bother. */
1612
1613	/*
1614	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1615	* corresponding to the current display mode.
1616	*/
1617	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1618	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1619	uint8_t const *pSrc;
1620	uint8_t *pDst;
1621	unsigned const cbRectWidth = width * cbPixel;
1622	unsigned uMaxOffset;
1623
1624	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1625	if (uMaxOffset >= cbFrameBuffer)
1626	{
1627	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1628	return; /* Just don't listen to a bad guest. */
1629	}
1630
1631	pSrc = pDst = pThisCC->pbVRam;
1632	pSrc += srcY * cbScanline + srcX * cbPixel;
1633	pDst += dstY * cbScanline + dstX * cbPixel;
1634
1635	if (srcY >= dstY)
1636	{
1637	/* Source below destination, copy top to bottom. */
1638	for (; height > 0; height--)
1639	{
1640	memmove(pDst, pSrc, cbRectWidth);
1641	pSrc += cbScanline;
1642	pDst += cbScanline;
1643	}
1644	}
1645	else
1646	{
1647	/* Source above destination, copy bottom to top. */
1648	pSrc += cbScanline * (height - 1);
1649	pDst += cbScanline * (height - 1);
1650	for (; height > 0; height--)
1651	{
1652	memmove(pDst, pSrc, cbRectWidth);
1653	pSrc -= cbScanline;
1654	pDst -= cbScanline;
1655	}
1656	}
1657	}
1658
1659	#endif /* IN_RING3 */
1660
1661
1662	/**
1663	* Write port register
1664	*
1665	* @returns Strict VBox status code.
1666	* @param pDevIns The device instance.
1667	* @param pThis The shared VGA/VMSVGA state.
1668	* @param pThisCC The VGA/VMSVGA state for the current context.
1669	* @param u32 Value to write
1670	*/
1671	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1672	{
1673	#ifdef IN_RING3
1674	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1675	#endif
1676	VBOXSTRICTRC rc = VINF_SUCCESS;
1677	RT_NOREF(pThisCC);
1678
1679	/* Rough index register validation. */
1680	uint32_t idxReg = pThis->svga.u32IndexReg;
1681	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1682	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1683	VINF_IOM_R3_IOPORT_WRITE);
1684	#else
1685	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1686	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1687	VINF_SUCCESS);
1688	#endif
1689	RT_UNTRUSTED_VALIDATED_FENCE();
1690
1691	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1692	if ( idxReg >= SVGA_REG_CAPABILITIES
1693	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1694	{
1695	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1696	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1697	}
1698	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1699	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1700	switch (idxReg)
1701	{
1702	case SVGA_REG_WIDTH:
1703	case SVGA_REG_HEIGHT:
1704	case SVGA_REG_PITCHLOCK:
1705	case SVGA_REG_BITS_PER_PIXEL:
1706	pThis->svga.fGFBRegisters = true;
1707	break;
1708	default:
1709	break;
1710	}
1711
1712	switch (idxReg)
1713	{
1714	case SVGA_REG_ID:
1715	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1716	if ( u32 == SVGA_ID_0
1717	\|\| u32 == SVGA_ID_1
1718	\|\| u32 == SVGA_ID_2)
1719	pThis->svga.u32SVGAId = u32;
1720	else
1721	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1722	break;
1723
1724	case SVGA_REG_ENABLE:
1725	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1726	#ifdef IN_RING3
1727	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1728	&& pThis->svga.fEnabled == false)
1729	{
1730	/* Make a backup copy of the first 512kb in order to save font data etc. */
1731	/** @todo should probably swap here, rather than copy + zero */
1732	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1733	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1734	}
1735
1736	pThis->svga.fEnabled = u32;
1737	if (pThis->svga.fEnabled)
1738	{
1739	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1740	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1741	{
1742	/* Keep the current mode. */
1743	pThis->svga.uWidth = pThisCC->pDrv->cx;
1744	pThis->svga.uHeight = pThisCC->pDrv->cy;
1745	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1746	}
1747
1748	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1749	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1750	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1751	# ifdef LOG_ENABLED
1752	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1753	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1754	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1755	# endif
1756
1757	/* Disable or enable dirty page tracking according to the current fTraces value. */
1758	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1759
1760	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1761	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1762	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1763
1764	/* Make the cursor visible again as needed. */
1765	if (pSVGAState->Cursor.fActive)
1766	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1767	}
1768	else
1769	{
1770	/* Make sure the cursor is off. */
1771	if (pSVGAState->Cursor.fActive)
1772	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1773
1774	/* Restore the text mode backup. */
1775	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1776
1777	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1778
1779	/* Enable dirty page tracking again when going into legacy mode. */
1780	vmsvgaR3SetTraces(pDevIns, pThis, true);
1781
1782	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1783	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1784	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1785
1786	/* Clear the pitch lock. */
1787	pThis->svga.u32PitchLock = 0;
1788	}
1789	#else /* !IN_RING3 */
1790	rc = VINF_IOM_R3_IOPORT_WRITE;
1791	#endif /* !IN_RING3 */
1792	break;
1793
1794	case SVGA_REG_WIDTH:
1795	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1796	if (pThis->svga.uWidth != u32)
1797	{
1798	#if defined(IN_RING3) \|\| defined(IN_RING0)
1799	pThis->svga.uWidth = u32;
1800	vmsvgaHCUpdatePitch(pThis, pThisCC);
1801	if (pThis->svga.fEnabled)
1802	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1803	#else
1804	rc = VINF_IOM_R3_IOPORT_WRITE;
1805	#endif
1806	}
1807	/* else: nop */
1808	break;
1809
1810	case SVGA_REG_HEIGHT:
1811	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1812	if (pThis->svga.uHeight != u32)
1813	{
1814	pThis->svga.uHeight = u32;
1815	if (pThis->svga.fEnabled)
1816	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1817	}
1818	/* else: nop */
1819	break;
1820
1821	case SVGA_REG_DEPTH:
1822	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1823	/** @todo read-only?? */
1824	break;
1825
1826	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1827	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1828	if (pThis->svga.uBpp != u32)
1829	{
1830	#if defined(IN_RING3) \|\| defined(IN_RING0)
1831	pThis->svga.uBpp = u32;
1832	vmsvgaHCUpdatePitch(pThis, pThisCC);
1833	if (pThis->svga.fEnabled)
1834	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1835	#else
1836	rc = VINF_IOM_R3_IOPORT_WRITE;
1837	#endif
1838	}
1839	/* else: nop */
1840	break;
1841
1842	case SVGA_REG_PSEUDOCOLOR:
1843	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1844	break;
1845
1846	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1847	#ifdef IN_RING3
1848	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1849	pThis->svga.fConfigured = u32;
1850	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1851	if (!pThis->svga.fConfigured)
1852	pThis->svga.fTraces = true;
1853	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1854	#else
1855	rc = VINF_IOM_R3_IOPORT_WRITE;
1856	#endif
1857	break;
1858
1859	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1860	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1861	if ( pThis->svga.fEnabled
1862	&& pThis->svga.fConfigured)
1863	{
1864	#if defined(IN_RING3) \|\| defined(IN_RING0)
1865	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1866	/*
1867	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1868	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1869	*/
1870	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1871	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1872	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1873
1874	/* Kick the FIFO thread to start processing commands again. */
1875	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1876	#else
1877	rc = VINF_IOM_R3_IOPORT_WRITE;
1878	#endif
1879	}
1880	/* else nothing to do. */
1881	else
1882	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1883
1884	break;
1885
1886	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1887	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1888	break;
1889
1890	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1891	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1892	pThis->svga.u32GuestId = u32;
1893	break;
1894
1895	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1896	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1897	pThis->svga.u32PitchLock = u32;
1898	/* Should this also update the FIFO pitch lock? Unclear. */
1899	break;
1900
1901	case SVGA_REG_IRQMASK: /* Interrupt mask */
1902	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1903	pThis->svga.u32IrqMask = u32;
1904
1905	/* Irq pending after the above change? */
1906	if (pThis->svga.u32IrqStatus & u32)
1907	{
1908	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1909	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1910	}
1911	else
1912	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1913	break;
1914
1915	/* Mouse cursor support */
1916	case SVGA_REG_CURSOR_ID:
1917	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1918	pThis->svga.uCursorID = u32;
1919	break;
1920
1921	case SVGA_REG_CURSOR_X:
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1923	pThis->svga.uCursorX = u32;
1924	break;
1925
1926	case SVGA_REG_CURSOR_Y:
1927	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1928	pThis->svga.uCursorY = u32;
1929	break;
1930
1931	case SVGA_REG_CURSOR_ON:
1932	#ifdef IN_RING3
1933	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1934	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1935	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1936	#else
1937	rc = VINF_IOM_R3_IOPORT_WRITE;
1938	#endif
1939	break;
1940
1941	/* Legacy multi-monitor support */
1942	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1943	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1944	break;
1945	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1946	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1947	break;
1948	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1949	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1950	break;
1951	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1952	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1953	break;
1954	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1956	break;
1957	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1958	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1959	break;
1960	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1961	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1962	break;
1963	#ifdef VBOX_WITH_VMSVGA3D
1964	/* See "Guest memory regions" below. */
1965	case SVGA_REG_GMR_ID:
1966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1967	pThis->svga.u32CurrentGMRId = u32;
1968	break;
1969
1970	case SVGA_REG_GMR_DESCRIPTOR:
1971	# ifndef IN_RING3
1972	rc = VINF_IOM_R3_IOPORT_WRITE;
1973	break;
1974	# else /* IN_RING3 */
1975	{
1976	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1977
1978	/* Validate current GMR id. */
1979	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
1980	AssertBreak(idGMR < pThis->svga.cGMR);
1981	RT_UNTRUSTED_VALIDATED_FENCE();
1982
1983	/* Free the old GMR if present. */
1984	vmsvgaR3GmrFree(pThisCC, idGMR);
1985
1986	/* Just undefine the GMR? */
1987	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
1988	if (GCPhys == 0)
1989	{
1990	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
1991	break;
1992	}
1993
1994
1995	/* Never cross a page boundary automatically. */
1996	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
1997	uint32_t cPagesTotal = 0;
1998	uint32_t iDesc = 0;
1999	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2000	uint32_t cLoops = 0;
2001	RTGCPHYS GCPhysBase = GCPhys;
2002	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2003	{
2004	/* Read descriptor. */
2005	SVGAGuestMemDescriptor desc;
2006	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2007	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2008
2009	if (desc.numPages != 0)
2010	{
2011	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2012	cPagesTotal += desc.numPages;
2013	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2014
2015	if ((iDesc & 15) == 0)
2016	{
2017	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2018	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2019	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2020	}
2021
2022	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2023	paDescs[iDesc++].numPages = desc.numPages;
2024
2025	/* Continue with the next descriptor. */
2026	GCPhys += sizeof(desc);
2027	}
2028	else if (desc.ppn == 0)
2029	break; /* terminator */
2030	else /* Pointer to the next physical page of descriptors. */
2031	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2032
2033	cLoops++;
2034	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2035	}
2036
2037	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2038	if (RT_SUCCESS(rc))
2039	{
2040	/* Commit the GMR. */
2041	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2042	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2043	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2044	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2045	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2046	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2047	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2048	}
2049	else
2050	{
2051	RTMemFree(paDescs);
2052	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2053	}
2054	break;
2055	}
2056	# endif /* IN_RING3 */
2057	#endif // VBOX_WITH_VMSVGA3D
2058
2059	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2060	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2061	if (pThis->svga.fTraces == u32)
2062	break; /* nothing to do */
2063
2064	#ifdef IN_RING3
2065	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2066	#else
2067	rc = VINF_IOM_R3_IOPORT_WRITE;
2068	#endif
2069	break;
2070
2071	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2072	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2073	break;
2074
2075	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2076	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2077	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2078	break;
2079
2080	case SVGA_REG_FB_START:
2081	case SVGA_REG_MEM_START:
2082	case SVGA_REG_HOST_BITS_PER_PIXEL:
2083	case SVGA_REG_MAX_WIDTH:
2084	case SVGA_REG_MAX_HEIGHT:
2085	case SVGA_REG_VRAM_SIZE:
2086	case SVGA_REG_FB_SIZE:
2087	case SVGA_REG_CAPABILITIES:
2088	case SVGA_REG_MEM_SIZE:
2089	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2090	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2091	case SVGA_REG_BYTES_PER_LINE:
2092	case SVGA_REG_FB_OFFSET:
2093	case SVGA_REG_RED_MASK:
2094	case SVGA_REG_GREEN_MASK:
2095	case SVGA_REG_BLUE_MASK:
2096	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2097	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2098	case SVGA_REG_GMR_MAX_IDS:
2099	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2100	/* Read only - ignore. */
2101	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2102	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2103	break;
2104
2105	default:
2106	{
2107	uint32_t offReg;
2108	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2109	{
2110	RT_UNTRUSTED_VALIDATED_FENCE();
2111	pThis->svga.au32ScratchRegion[offReg] = u32;
2112	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2113	}
2114	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2115	{
2116	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2117	Btw, see rgb_to_pixel32. */
2118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2119	u32 &= 0xff;
2120	RT_UNTRUSTED_VALIDATED_FENCE();
2121	uint32_t uRgb = pThis->last_palette[offReg / 3];
2122	switch (offReg % 3)
2123	{
2124	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2125	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2126	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2127	}
2128	pThis->last_palette[offReg / 3] = uRgb;
2129	}
2130	else
2131	{
2132	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2133	rc = VINF_IOM_R3_IOPORT_WRITE;
2134	#else
2135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2136	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2137	#endif
2138	}
2139	break;
2140	}
2141	}
2142	return rc;
2143	}
2144
2145	/**
2146	* @callback_method_impl{FNIOMIOPORTNEWIN}
2147	*/
2148	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2149	{
2150	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2151	RT_NOREF_PV(pvUser);
2152
2153	/* Only dword accesses. */
2154	if (cb == 4)
2155	{
2156	switch (offPort)
2157	{
2158	case SVGA_INDEX_PORT:
2159	*pu32 = pThis->svga.u32IndexReg;
2160	break;
2161
2162	case SVGA_VALUE_PORT:
2163	return vmsvgaReadPort(pDevIns, pThis, pu32);
2164
2165	case SVGA_BIOS_PORT:
2166	Log(("Ignoring BIOS port read\n"));
2167	*pu32 = 0;
2168	break;
2169
2170	case SVGA_IRQSTATUS_PORT:
2171	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2172	*pu32 = pThis->svga.u32IrqStatus;
2173	break;
2174
2175	default:
2176	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2177	*pu32 = UINT32_MAX;
2178	break;
2179	}
2180	}
2181	else
2182	{
2183	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2184	*pu32 = UINT32_MAX;
2185	}
2186	return VINF_SUCCESS;
2187	}
2188
2189	/**
2190	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2191	*/
2192	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2193	{
2194	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2195	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2196	RT_NOREF_PV(pvUser);
2197
2198	/* Only dword accesses. */
2199	if (cb == 4)
2200	switch (offPort)
2201	{
2202	case SVGA_INDEX_PORT:
2203	pThis->svga.u32IndexReg = u32;
2204	break;
2205
2206	case SVGA_VALUE_PORT:
2207	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2208
2209	case SVGA_BIOS_PORT:
2210	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2211	break;
2212
2213	case SVGA_IRQSTATUS_PORT:
2214	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2215	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2216	/* Clear the irq in case all events have been cleared. */
2217	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2218	{
2219	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2220	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2221	}
2222	break;
2223
2224	default:
2225	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2226	break;
2227	}
2228	else
2229	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2230
2231	return VINF_SUCCESS;
2232	}
2233
2234	#ifdef IN_RING3
2235
2236	# ifdef DEBUG_FIFO_ACCESS
2237	/**
2238	* Handle FIFO memory access.
2239	* @returns VBox status code.
2240	* @param pVM VM handle.
2241	* @param pThis The shared VGA/VMSVGA instance data.
2242	* @param GCPhys The access physical address.
2243	* @param fWriteAccess Read or write access
2244	*/
2245	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2246	{
2247	RT_NOREF(pVM);
2248	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2249	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2250
2251	switch (GCPhysOffset >> 2)
2252	{
2253	case SVGA_FIFO_MIN:
2254	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2255	break;
2256	case SVGA_FIFO_MAX:
2257	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2258	break;
2259	case SVGA_FIFO_NEXT_CMD:
2260	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2261	break;
2262	case SVGA_FIFO_STOP:
2263	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2264	break;
2265	case SVGA_FIFO_CAPABILITIES:
2266	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2267	break;
2268	case SVGA_FIFO_FLAGS:
2269	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2270	break;
2271	case SVGA_FIFO_FENCE:
2272	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2273	break;
2274	case SVGA_FIFO_3D_HWVERSION:
2275	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2276	break;
2277	case SVGA_FIFO_PITCHLOCK:
2278	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2279	break;
2280	case SVGA_FIFO_CURSOR_ON:
2281	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2282	break;
2283	case SVGA_FIFO_CURSOR_X:
2284	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2285	break;
2286	case SVGA_FIFO_CURSOR_Y:
2287	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2288	break;
2289	case SVGA_FIFO_CURSOR_COUNT:
2290	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2291	break;
2292	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2293	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2294	break;
2295	case SVGA_FIFO_RESERVED:
2296	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2297	break;
2298	case SVGA_FIFO_CURSOR_SCREEN_ID:
2299	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2300	break;
2301	case SVGA_FIFO_DEAD:
2302	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2303	break;
2304	case SVGA_FIFO_3D_HWVERSION_REVISED:
2305	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2306	break;
2307	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2308	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2309	break;
2310	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2311	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2312	break;
2313	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2314	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2315	break;
2316	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2317	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2318	break;
2319	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2320	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2321	break;
2322	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2323	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2324	break;
2325	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2326	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2327	break;
2328	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2329	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2330	break;
2331	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2332	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2333	break;
2334	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2335	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2336	break;
2337	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2338	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2339	break;
2340	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2341	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2342	break;
2343	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2344	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2345	break;
2346	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2347	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2348	break;
2349	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2350	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2351	break;
2352	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2353	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2354	break;
2355	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2356	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2357	break;
2358	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2359	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2360	break;
2361	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2362	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2363	break;
2364	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2365	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2366	break;
2367	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2368	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2369	break;
2370	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2371	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2372	break;
2373	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2374	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2375	break;
2376	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2377	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2378	break;
2379	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2380	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2381	break;
2382	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2383	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2384	break;
2385	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2386	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2387	break;
2388	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2389	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2390	break;
2391	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2392	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2393	break;
2394	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2395	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2396	break;
2397	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2398	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2399	break;
2400	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2401	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2402	break;
2403	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2404	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2405	break;
2406	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2407	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2408	break;
2409	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2410	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2411	break;
2412	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2413	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2414	break;
2415	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2416	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2417	break;
2418	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2419	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2420	break;
2421	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2422	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2423	break;
2424	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2425	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2426	break;
2427	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2428	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2429	break;
2430	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2431	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2432	break;
2433	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2434	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2435	break;
2436	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2437	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2438	break;
2439	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2440	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2441	break;
2442	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2443	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2444	break;
2445	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2446	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2447	break;
2448	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2449	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2450	break;
2451	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2452	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2453	break;
2454	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2455	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2456	break;
2457	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2458	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2459	break;
2460	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2461	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2462	break;
2463	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2464	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2465	break;
2466	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2467	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2468	break;
2469	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2470	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2471	break;
2472	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2473	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2474	break;
2475	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2476	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2477	break;
2478	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2479	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2480	break;
2481	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2482	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2483	break;
2484	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2485	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2486	break;
2487	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2488	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2489	break;
2490	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2491	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2492	break;
2493	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2494	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2495	break;
2496	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2497	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2498	break;
2499	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2500	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2501	break;
2502	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2503	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2504	break;
2505	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2506	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2507	break;
2508	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2509	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2510	break;
2511	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2512	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2513	break;
2514	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2515	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2516	break;
2517	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2518	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2519	break;
2520	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2521	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2522	break;
2523	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2524	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2525	break;
2526	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2527	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2528	break;
2529	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2530	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2531	break;
2532	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2533	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2534	break;
2535	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2536	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2537	break;
2538	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2539	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2540	break;
2541	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2542	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2543	break;
2544	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2545	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546	break;
2547	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2548	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549	break;
2550	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2551	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552	break;
2553	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2554	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555	break;
2556	case SVGA_FIFO_3D_CAPS_LAST:
2557	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558	break;
2559	case SVGA_FIFO_GUEST_3D_HWVERSION:
2560	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561	break;
2562	case SVGA_FIFO_FENCE_GOAL:
2563	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564	break;
2565	case SVGA_FIFO_BUSY:
2566	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567	break;
2568	default:
2569	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2570	break;
2571	}
2572
2573	return VINF_EM_RAW_EMULATE_INSTR;
2574	}
2575	# endif /* DEBUG_FIFO_ACCESS */
2576
2577	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2578	/**
2579	* HC access handler for the FIFO.
2580	*
2581	* @returns VINF_SUCCESS if the handler have carried out the operation.
2582	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2583	* @param pVM VM Handle.
2584	* @param pVCpu The cross context CPU structure for the calling EMT.
2585	* @param GCPhys The physical address the guest is writing to.
2586	* @param pvPhys The HC mapping of that address.
2587	* @param pvBuf What the guest is reading/writing.
2588	* @param cbBuf How much it's reading/writing.
2589	* @param enmAccessType The access type.
2590	* @param enmOrigin Who is making the access.
2591	* @param pvUser User argument.
2592	*/
2593	static DECLCALLBACK(VBOXSTRICTRC)
2594	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2595	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2596	{
2597	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2598	PVGASTATE pThis = (PVGASTATE)pvUser;
2599	AssertPtr(pThis);
2600
2601	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2602	/*
2603	* Wake up the FIFO thread as it might have work to do now.
2604	*/
2605	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2606	AssertLogRelRC(rc);
2607	# endif
2608
2609	# ifdef DEBUG_FIFO_ACCESS
2610	/*
2611	* When in debug-fifo-access mode, we do not disable the access handler,
2612	* but leave it on as we wish to catch all access.
2613	*/
2614	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2615	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2616	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2617	/*
2618	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2619	*/
2620	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2621	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2622	# endif
2623	if (RT_SUCCESS(rc))
2624	return VINF_PGM_HANDLER_DO_DEFAULT;
2625	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2626	return rc;
2627	}
2628	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2629
2630	#endif /* IN_RING3 */
2631
2632	#ifdef DEBUG_GMR_ACCESS
2633	# ifdef IN_RING3
2634
2635	/**
2636	* HC access handler for the FIFO.
2637	*
2638	* @returns VINF_SUCCESS if the handler have carried out the operation.
2639	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2640	* @param pVM VM Handle.
2641	* @param pVCpu The cross context CPU structure for the calling EMT.
2642	* @param GCPhys The physical address the guest is writing to.
2643	* @param pvPhys The HC mapping of that address.
2644	* @param pvBuf What the guest is reading/writing.
2645	* @param cbBuf How much it's reading/writing.
2646	* @param enmAccessType The access type.
2647	* @param enmOrigin Who is making the access.
2648	* @param pvUser User argument.
2649	*/
2650	static DECLCALLBACK(VBOXSTRICTRC)
2651	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2652	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2653	{
2654	PVGASTATE pThis = (PVGASTATE)pvUser;
2655	Assert(pThis);
2656	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2657	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2658
2659	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2660
2661	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2662	{
2663	PGMR pGMR = &pSVGAState->paGMR[i];
2664
2665	if (pGMR->numDescriptors)
2666	{
2667	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2668	{
2669	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2670	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2671	{
2672	/*
2673	* Turn off the write handler for this particular page and make it R/W.
2674	* Then return telling the caller to restart the guest instruction.
2675	*/
2676	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2677	AssertRC(rc);
2678	return VINF_PGM_HANDLER_DO_DEFAULT;
2679	}
2680	}
2681	}
2682	}
2683
2684	return VINF_PGM_HANDLER_DO_DEFAULT;
2685	}
2686
2687	/** Callback handler for VMR3ReqCallWaitU */
2688	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2689	{
2690	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2691	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2692	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2693	int rc;
2694
2695	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2696	{
2697	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2698	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2699	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2700	AssertRC(rc);
2701	}
2702	return VINF_SUCCESS;
2703	}
2704
2705	/** Callback handler for VMR3ReqCallWaitU */
2706	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2707	{
2708	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2709	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2710	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2711
2712	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2713	{
2714	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2715	AssertRC(rc);
2716	}
2717	return VINF_SUCCESS;
2718	}
2719
2720	/** Callback handler for VMR3ReqCallWaitU */
2721	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2722	{
2723	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2724
2725	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2726	{
2727	PGMR pGMR = &pSVGAState->paGMR[i];
2728
2729	if (pGMR->numDescriptors)
2730	{
2731	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2732	{
2733	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2734	AssertRC(rc);
2735	}
2736	}
2737	}
2738	return VINF_SUCCESS;
2739	}
2740
2741	# endif /* IN_RING3 */
2742	#endif /* DEBUG_GMR_ACCESS */
2743
2744	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2745
2746	#ifdef IN_RING3
2747
2748
2749	/**
2750	* Common worker for changing the pointer shape.
2751	*
2752	* @param pThisCC The VGA/VMSVGA state for ring-3.
2753	* @param pSVGAState The VMSVGA ring-3 instance data.
2754	* @param fAlpha Whether there is alpha or not.
2755	* @param xHot Hotspot x coordinate.
2756	* @param yHot Hotspot y coordinate.
2757	* @param cx Width.
2758	* @param cy Height.
2759	* @param pbData Heap copy of the cursor data. Consumed.
2760	* @param cbData The size of the data.
2761	*/
2762	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2763	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2764	{
2765	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2766	# ifdef LOG_ENABLED
2767	if (LogIs2Enabled())
2768	{
2769	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2770	if (!fAlpha)
2771	{
2772	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2773	for (uint32_t y = 0; y < cy; y++)
2774	{
2775	Log2(("%3u:", y));
2776	uint8_t const pbLine = &pbData[y cbAndLine];
2777	for (uint32_t x = 0; x < cx; x += 8)
2778	{
2779	uint8_t b = pbLine[x / 8];
2780	char szByte[12];
2781	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2782	szByte[1] = b & 0x40 ? '*' : ' ';
2783	szByte[2] = b & 0x20 ? '*' : ' ';
2784	szByte[3] = b & 0x10 ? '*' : ' ';
2785	szByte[4] = b & 0x08 ? '*' : ' ';
2786	szByte[5] = b & 0x04 ? '*' : ' ';
2787	szByte[6] = b & 0x02 ? '*' : ' ';
2788	szByte[7] = b & 0x01 ? '*' : ' ';
2789	szByte[8] = '\0';
2790	Log2(("%s", szByte));
2791	}
2792	Log2(("\n"));
2793	}
2794	}
2795
2796	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2797	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2798	for (uint32_t y = 0; y < cy; y++)
2799	{
2800	Log2(("%3u:", y));
2801	uint32_t const pu32Line = &pu32Xor[y cx];
2802	for (uint32_t x = 0; x < cx; x++)
2803	Log2((" %08x", pu32Line[x]));
2804	Log2(("\n"));
2805	}
2806	}
2807	# endif
2808
2809	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2810	AssertRC(rc);
2811
2812	if (pSVGAState->Cursor.fActive)
2813	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
2814
2815	pSVGAState->Cursor.fActive = true;
2816	pSVGAState->Cursor.xHotspot = xHot;
2817	pSVGAState->Cursor.yHotspot = yHot;
2818	pSVGAState->Cursor.width = cx;
2819	pSVGAState->Cursor.height = cy;
2820	pSVGAState->Cursor.cbData = cbData;
2821	pSVGAState->Cursor.pData = pbData;
2822	}
2823
2824
2825	/**
2826	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2827	*
2828	* @param pThis The shared VGA/VMSVGA state.
2829	* @param pThisCC The VGA/VMSVGA state for ring-3.
2830	* @param pSVGAState The VMSVGA ring-3 instance data.
2831	* @param pCursor The cursor.
2832	* @param pbSrcAndMask The AND mask.
2833	* @param cbSrcAndLine The scanline length of the AND mask.
2834	* @param pbSrcXorMask The XOR mask.
2835	* @param cbSrcXorLine The scanline length of the XOR mask.
2836	*/
2837	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2838	SVGAFifoCmdDefineCursor const *pCursor,
2839	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2840	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2841	{
2842	uint32_t const cx = pCursor->width;
2843	uint32_t const cy = pCursor->height;
2844
2845	/*
2846	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2847	* The AND data uses 8-bit aligned scanlines.
2848	* The XOR data must be starting on a 32-bit boundrary.
2849	*/
2850	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2851	uint32_t cbDstAndMask = cbDstAndLine * cy;
2852	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2853	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2854
2855	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2856	AssertReturnVoid(pbCopy);
2857
2858	/* Convert the AND mask. */
2859	uint8_t *pbDst = pbCopy;
2860	uint8_t const *pbSrc = pbSrcAndMask;
2861	switch (pCursor->andMaskDepth)
2862	{
2863	case 1:
2864	if (cbSrcAndLine == cbDstAndLine)
2865	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2866	else
2867	{
2868	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2869	for (uint32_t y = 0; y < cy; y++)
2870	{
2871	memcpy(pbDst, pbSrc, cbDstAndLine);
2872	pbDst += cbDstAndLine;
2873	pbSrc += cbSrcAndLine;
2874	}
2875	}
2876	break;
2877	/* Should take the XOR mask into account for the multi-bit AND mask. */
2878	case 8:
2879	for (uint32_t y = 0; y < cy; y++)
2880	{
2881	for (uint32_t x = 0; x < cx; )
2882	{
2883	uint8_t bDst = 0;
2884	uint8_t fBit = 0x80;
2885	do
2886	{
2887	uintptr_t const idxPal = pbSrc[x] * 3;
2888	if ((( pThis->last_palette[idxPal]
2889	\| (pThis->last_palette[idxPal] >> 8)
2890	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2891	bDst \|= fBit;
2892	fBit >>= 1;
2893	x++;
2894	} while (x < cx && (x & 7));
2895	pbDst[(x - 1) / 8] = bDst;
2896	}
2897	pbDst += cbDstAndLine;
2898	pbSrc += cbSrcAndLine;
2899	}
2900	break;
2901	case 15:
2902	for (uint32_t y = 0; y < cy; y++)
2903	{
2904	for (uint32_t x = 0; x < cx; )
2905	{
2906	uint8_t bDst = 0;
2907	uint8_t fBit = 0x80;
2908	do
2909	{
2910	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2911	bDst \|= fBit;
2912	fBit >>= 1;
2913	x++;
2914	} while (x < cx && (x & 7));
2915	pbDst[(x - 1) / 8] = bDst;
2916	}
2917	pbDst += cbDstAndLine;
2918	pbSrc += cbSrcAndLine;
2919	}
2920	break;
2921	case 16:
2922	for (uint32_t y = 0; y < cy; y++)
2923	{
2924	for (uint32_t x = 0; x < cx; )
2925	{
2926	uint8_t bDst = 0;
2927	uint8_t fBit = 0x80;
2928	do
2929	{
2930	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2931	bDst \|= fBit;
2932	fBit >>= 1;
2933	x++;
2934	} while (x < cx && (x & 7));
2935	pbDst[(x - 1) / 8] = bDst;
2936	}
2937	pbDst += cbDstAndLine;
2938	pbSrc += cbSrcAndLine;
2939	}
2940	break;
2941	case 24:
2942	for (uint32_t y = 0; y < cy; y++)
2943	{
2944	for (uint32_t x = 0; x < cx; )
2945	{
2946	uint8_t bDst = 0;
2947	uint8_t fBit = 0x80;
2948	do
2949	{
2950	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2951	bDst \|= fBit;
2952	fBit >>= 1;
2953	x++;
2954	} while (x < cx && (x & 7));
2955	pbDst[(x - 1) / 8] = bDst;
2956	}
2957	pbDst += cbDstAndLine;
2958	pbSrc += cbSrcAndLine;
2959	}
2960	break;
2961	case 32:
2962	for (uint32_t y = 0; y < cy; y++)
2963	{
2964	for (uint32_t x = 0; x < cx; )
2965	{
2966	uint8_t bDst = 0;
2967	uint8_t fBit = 0x80;
2968	do
2969	{
2970	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2971	bDst \|= fBit;
2972	fBit >>= 1;
2973	x++;
2974	} while (x < cx && (x & 7));
2975	pbDst[(x - 1) / 8] = bDst;
2976	}
2977	pbDst += cbDstAndLine;
2978	pbSrc += cbSrcAndLine;
2979	}
2980	break;
2981	default:
2982	RTMemFreeZ(pbCopy, cbCopy);
2983	AssertFailedReturnVoid();
2984	}
2985
2986	/* Convert the XOR mask. */
2987	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
2988	pbSrc = pbSrcXorMask;
2989	switch (pCursor->xorMaskDepth)
2990	{
2991	case 1:
2992	for (uint32_t y = 0; y < cy; y++)
2993	{
2994	for (uint32_t x = 0; x < cx; )
2995	{
2996	/* most significant bit is the left most one. */
2997	uint8_t bSrc = pbSrc[x / 8];
2998	do
2999	{
3000	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
3001	bSrc <<= 1;
3002	x++;
3003	} while ((x & 7) && x < cx);
3004	}
3005	pbSrc += cbSrcXorLine;
3006	}
3007	break;
3008	case 8:
3009	for (uint32_t y = 0; y < cy; y++)
3010	{
3011	for (uint32_t x = 0; x < cx; x++)
3012	{
3013	uint32_t u = pThis->last_palette[pbSrc[x]];
3014	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3015	}
3016	pbSrc += cbSrcXorLine;
3017	}
3018	break;
3019	case 15: /* Src: RGB-5-5-5 */
3020	for (uint32_t y = 0; y < cy; y++)
3021	{
3022	for (uint32_t x = 0; x < cx; x++)
3023	{
3024	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3025	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3026	((uValue >> 5) & 0x1f) << 3,
3027	((uValue >> 10) & 0x1f) << 3, 0);
3028	}
3029	pbSrc += cbSrcXorLine;
3030	}
3031	break;
3032	case 16: /* Src: RGB-5-6-5 */
3033	for (uint32_t y = 0; y < cy; y++)
3034	{
3035	for (uint32_t x = 0; x < cx; x++)
3036	{
3037	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3038	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3039	((uValue >> 5) & 0x3f) << 2,
3040	((uValue >> 11) & 0x1f) << 3, 0);
3041	}
3042	pbSrc += cbSrcXorLine;
3043	}
3044	break;
3045	case 24:
3046	for (uint32_t y = 0; y < cy; y++)
3047	{
3048	for (uint32_t x = 0; x < cx; x++)
3049	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3050	pbSrc += cbSrcXorLine;
3051	}
3052	break;
3053	case 32:
3054	for (uint32_t y = 0; y < cy; y++)
3055	{
3056	for (uint32_t x = 0; x < cx; x++)
3057	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3058	pbSrc += cbSrcXorLine;
3059	}
3060	break;
3061	default:
3062	RTMemFreeZ(pbCopy, cbCopy);
3063	AssertFailedReturnVoid();
3064	}
3065
3066	/*
3067	* Pass it to the frontend/whatever.
3068	*/
3069	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3070	}
3071
3072
3073	/**
3074	* Worker for vmsvgaR3FifoThread that handles an external command.
3075	*
3076	* @param pDevIns The device instance.
3077	* @param pThis The shared VGA/VMSVGA instance data.
3078	* @param pThisCC The VGA/VMSVGA state for ring-3.
3079	*/
3080	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3081	{
3082	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3083	switch (pThis->svga.u8FIFOExtCommand)
3084	{
3085	case VMSVGA_FIFO_EXTCMD_RESET:
3086	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3087	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3088	# ifdef VBOX_WITH_VMSVGA3D
3089	if (pThis->svga.f3DEnabled)
3090	{
3091	/* The 3d subsystem must be reset from the fifo thread. */
3092	vmsvga3dReset(pThisCC);
3093	}
3094	# endif
3095	break;
3096
3097	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3098	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3099	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3100	# ifdef VBOX_WITH_VMSVGA3D
3101	if (pThis->svga.f3DEnabled)
3102	{
3103	/* The 3d subsystem must be shut down from the fifo thread. */
3104	vmsvga3dTerminate(pThisCC);
3105	}
3106	# endif
3107	break;
3108
3109	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3110	{
3111	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3112	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3113	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3114	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3115	# ifdef VBOX_WITH_VMSVGA3D
3116	if (pThis->svga.f3DEnabled)
3117	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3118	# endif
3119	break;
3120	}
3121
3122	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3123	{
3124	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3125	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3126	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3127	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3128	# ifdef VBOX_WITH_VMSVGA3D
3129	if (pThis->svga.f3DEnabled)
3130	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3131	# endif
3132	break;
3133	}
3134
3135	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3136	{
3137	# ifdef VBOX_WITH_VMSVGA3D
3138	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3139	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3140	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3141	# endif
3142	break;
3143	}
3144
3145
3146	default:
3147	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3148	break;
3149	}
3150
3151	/*
3152	* Signal the end of the external command.
3153	*/
3154	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3155	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3156	ASMMemoryFence(); /* paranoia^2 */
3157	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3158	AssertLogRelRC(rc);
3159	}
3160
3161	/**
3162	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3163	* doing a job on the FIFO thread (even when it's officially suspended).
3164	*
3165	* @returns VBox status code (fully asserted).
3166	* @param pDevIns The device instance.
3167	* @param pThis The shared VGA/VMSVGA instance data.
3168	* @param pThisCC The VGA/VMSVGA state for ring-3.
3169	* @param uExtCmd The command to execute on the FIFO thread.
3170	* @param pvParam Pointer to command parameters.
3171	* @param cMsWait The time to wait for the command, given in
3172	* milliseconds.
3173	*/
3174	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3175	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3176	{
3177	Assert(cMsWait >= RT_MS_1SEC * 5);
3178	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3179	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3180
3181	int rc;
3182	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3183	PDMTHREADSTATE enmState = pThread->enmState;
3184	if (enmState == PDMTHREADSTATE_SUSPENDED)
3185	{
3186	/*
3187	* The thread is suspended, we have to temporarily wake it up so it can
3188	* perform the task.
3189	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3190	*/
3191	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3192	/* Post the request. */
3193	pThis->svga.fFifoExtCommandWakeup = true;
3194	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3195	pThis->svga.u8FIFOExtCommand = uExtCmd;
3196	ASMMemoryFence(); /* paranoia^3 */
3197
3198	/* Resume the thread. */
3199	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3200	AssertLogRelRC(rc);
3201	if (RT_SUCCESS(rc))
3202	{
3203	/* Wait. Take care in case the semaphore was already posted (same as below). */
3204	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3205	if ( rc == VINF_SUCCESS
3206	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3207	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3208	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3209	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3210
3211	/* suspend the thread */
3212	pThis->svga.fFifoExtCommandWakeup = false;
3213	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3214	AssertLogRelRC(rc2);
3215	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3216	rc = rc2;
3217	}
3218	pThis->svga.fFifoExtCommandWakeup = false;
3219	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3220	}
3221	else if (enmState == PDMTHREADSTATE_RUNNING)
3222	{
3223	/*
3224	* The thread is running, should only happen during reset and vmsvga3dsfc.
3225	* We ASSUME not racing code here, both wrt thread state and ext commands.
3226	*/
3227	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3228	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3229
3230	/* Post the request. */
3231	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3232	pThis->svga.u8FIFOExtCommand = uExtCmd;
3233	ASMMemoryFence(); /* paranoia^2 */
3234	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3235	AssertLogRelRC(rc);
3236
3237	/* Wait. Take care in case the semaphore was already posted (same as above). */
3238	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3239	if ( rc == VINF_SUCCESS
3240	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3241	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3242	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3243	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3244
3245	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3246	}
3247	else
3248	{
3249	/*
3250	* Something is wrong with the thread!
3251	*/
3252	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3253	rc = VERR_INVALID_STATE;
3254	}
3255	return rc;
3256	}
3257
3258
3259	/**
3260	* Marks the FIFO non-busy, notifying any waiting EMTs.
3261	*
3262	* @param pDevIns The device instance.
3263	* @param pThis The shared VGA/VMSVGA instance data.
3264	* @param pThisCC The VGA/VMSVGA state for ring-3.
3265	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3266	* @param offFifoMin The start byte offset of the command FIFO.
3267	*/
3268	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3269	{
3270	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3271	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3272	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3273
3274	/* Wake up any waiting EMTs. */
3275	if (pSVGAState->cBusyDelayedEmts > 0)
3276	{
3277	# ifdef VMSVGA_USE_EMT_HALT_CODE
3278	PVM pVM = PDMDevHlpGetVM(pDevIns);
3279	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3280	if (idCpu != NIL_VMCPUID)
3281	{
3282	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3283	while (idCpu-- > 0)
3284	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3285	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3286	}
3287	# else
3288	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3289	AssertRC(rc2);
3290	# endif
3291	}
3292	}
3293
3294	/**
3295	* Reads (more) payload into the command buffer.
3296	*
3297	* @returns pbBounceBuf on success
3298	* @retval (void *)1 if the thread was requested to stop.
3299	* @retval NULL on FIFO error.
3300	*
3301	* @param cbPayloadReq The number of bytes of payload requested.
3302	* @param pFIFO The FIFO.
3303	* @param offCurrentCmd The FIFO byte offset of the current command.
3304	* @param offFifoMin The start byte offset of the command FIFO.
3305	* @param offFifoMax The end byte offset of the command FIFO.
3306	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3307	* always sufficient size.
3308	* @param pcbAlreadyRead How much payload we've already read into the bounce
3309	* buffer. (We will NEVER re-read anything.)
3310	* @param pThread The calling PDM thread handle.
3311	* @param pThis The shared VGA/VMSVGA instance data.
3312	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3313	* statistics collection.
3314	* @param pDevIns The device instance.
3315	*/
3316	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3317	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3318	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3319	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3320	{
3321	Assert(pbBounceBuf);
3322	Assert(pcbAlreadyRead);
3323	Assert(offFifoMin < offFifoMax);
3324	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3325	Assert(offFifoMax <= pThis->svga.cbFIFO);
3326
3327	/*
3328	* Check if the requested payload size has already been satisfied .
3329	* .
3330	* When called to read more, the caller is responsible for making sure the .
3331	* new command size (cbRequsted) never is smaller than what has already .
3332	* been read.
3333	*/
3334	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3335	if (cbPayloadReq <= cbAlreadyRead)
3336	{
3337	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3338	return pbBounceBuf;
3339	}
3340
3341	/*
3342	* Commands bigger than the fifo buffer are invalid.
3343	*/
3344	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3345	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3346	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3347	NULL);
3348
3349	/*
3350	* Move offCurrentCmd past the command dword.
3351	*/
3352	offCurrentCmd += sizeof(uint32_t);
3353	if (offCurrentCmd >= offFifoMax)
3354	offCurrentCmd = offFifoMin;
3355
3356	/*
3357	* Do we have sufficient payload data available already?
3358	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3359	*/
3360	uint32_t cbAfter, cbBefore;
3361	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3362	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3363	if (offNextCmd >= offCurrentCmd)
3364	{
3365	if (RT_LIKELY(offNextCmd < offFifoMax))
3366	cbAfter = offNextCmd - offCurrentCmd;
3367	else
3368	{
3369	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3370	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3371	offNextCmd, offFifoMin, offFifoMax));
3372	cbAfter = offFifoMax - offCurrentCmd;
3373	}
3374	cbBefore = 0;
3375	}
3376	else
3377	{
3378	cbAfter = offFifoMax - offCurrentCmd;
3379	if (offNextCmd >= offFifoMin)
3380	cbBefore = offNextCmd - offFifoMin;
3381	else
3382	{
3383	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3384	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3385	offNextCmd, offFifoMin, offFifoMax));
3386	cbBefore = 0;
3387	}
3388	}
3389	if (cbAfter + cbBefore < cbPayloadReq)
3390	{
3391	/*
3392	* Insufficient, must wait for it to arrive.
3393	*/
3394	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3395	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3396	for (uint32_t i = 0;; i++)
3397	{
3398	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3399	{
3400	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3401	return (void *)(uintptr_t)1;
3402	}
3403	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3404	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3405
3406	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3407
3408	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3409	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3410	if (offNextCmd >= offCurrentCmd)
3411	{
3412	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3413	cbBefore = 0;
3414	}
3415	else
3416	{
3417	cbAfter = offFifoMax - offCurrentCmd;
3418	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3419	}
3420
3421	if (cbAfter + cbBefore >= cbPayloadReq)
3422	break;
3423	}
3424	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3425	}
3426
3427	/*
3428	* Copy out the memory and update what pcbAlreadyRead points to.
3429	*/
3430	if (cbAfter >= cbPayloadReq)
3431	memcpy(pbBounceBuf + cbAlreadyRead,
3432	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3433	cbPayloadReq - cbAlreadyRead);
3434	else
3435	{
3436	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3437	if (cbAlreadyRead < cbAfter)
3438	{
3439	memcpy(pbBounceBuf + cbAlreadyRead,
3440	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3441	cbAfter - cbAlreadyRead);
3442	cbAlreadyRead = cbAfter;
3443	}
3444	memcpy(pbBounceBuf + cbAlreadyRead,
3445	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3446	cbPayloadReq - cbAlreadyRead);
3447	}
3448	*pcbAlreadyRead = cbPayloadReq;
3449	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3450	return pbBounceBuf;
3451	}
3452
3453
3454	/**
3455	* Sends cursor position and visibility information from the FIFO to the front-end.
3456	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3457	*/
3458	static uint32_t
3459	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3460	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3461	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3462	{
3463	/*
3464	* Check if the cursor update counter has changed and try get a stable
3465	* set of values if it has. This is race-prone, especially consindering
3466	* the screen ID, but little we can do about that.
3467	*/
3468	uint32_t x, y, fVisible, idScreen;
3469	for (uint32_t i = 0; ; i++)
3470	{
3471	x = pFIFO[SVGA_FIFO_CURSOR_X];
3472	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3473	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3474	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3475	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3476	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3477	\|\| i > 3)
3478	break;
3479	if (i == 0)
3480	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3481	ASMNopPause();
3482	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3483	}
3484
3485	/*
3486	* Check if anything has changed, as calling into pDrv is not light-weight.
3487	*/
3488	if ( *pxLast == x
3489	&& *pyLast == y
3490	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3491	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3492	else
3493	{
3494	/*
3495	* Detected changes.
3496	*
3497	* We handle global, not per-screen visibility information by sending
3498	* pfnVBVAMousePointerShape without shape data.
3499	*/
3500	*pxLast = x;
3501	*pyLast = y;
3502	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3503	if (idScreen != SVGA_ID_INVALID)
3504	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3505	else if (*pfLastVisible != fVisible)
3506	{
3507	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3508	*pfLastVisible = fVisible;
3509	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3510	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3511	}
3512	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3513	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3514	}
3515
3516	/*
3517	* Update done. Signal this to the guest.
3518	*/
3519	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3520
3521	return uCursorUpdateCount;
3522	}
3523
3524
3525	/**
3526	* Checks if there is work to be done, either cursor updating or FIFO commands.
3527	*
3528	* @returns true if pending work, false if not.
3529	* @param pFIFO The FIFO to examine.
3530	* @param uLastCursorCount The last cursor update counter value.
3531	*/
3532	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3533	{
3534	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3535	return true;
3536
3537	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3538	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3539	return true;
3540
3541	return false;
3542	}
3543
3544
3545	/**
3546	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3547	*
3548	* @param pDevIns The device instance.
3549	* @param pThis The shared VGA/VMSVGA instance data.
3550	* @param pThisCC The VGA/VMSVGA state for ring-3.
3551	*/
3552	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3553	{
3554	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3555	to recheck it before doing the signalling. */
3556	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3557	AssertReturnVoid(pFIFO);
3558	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3559	&& pThis->svga.fFIFOThreadSleeping)
3560	{
3561	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3562	AssertRC(rc);
3563	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3564	}
3565	}
3566
3567
3568	/**
3569	* Called by the FIFO thread to process pending actions.
3570	*
3571	* @param pDevIns The device instance.
3572	* @param pThis The shared VGA/VMSVGA instance data.
3573	* @param pThisCC The VGA/VMSVGA state for ring-3.
3574	*/
3575	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3576	{
3577	RT_NOREF(pDevIns);
3578
3579	/* Currently just mode changes. */
3580	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3581	{
3582	vmsvgaR3ChangeMode(pThis, pThisCC);
3583	# ifdef VBOX_WITH_VMSVGA3D
3584	if (pThisCC->svga.p3dState != NULL)
3585	vmsvga3dChangeMode(pThisCC);
3586	# endif
3587	}
3588	}
3589
3590
3591	/*
3592	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3593	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3594	*/
3595	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3596	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3597	*
3598	* Will break out of the switch on failure.
3599	* Will restart and quit the loop if the thread was requested to stop.
3600	*
3601	* @param a_PtrVar Request variable pointer.
3602	* @param a_Type Request typedef (not pointer) for casting.
3603	* @param a_cbPayloadReq How much payload to fetch.
3604	* @remarks Accesses a bunch of variables in the current scope!
3605	*/
3606	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3607	if (1) { \
3608	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3609	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3610	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3611	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3612	} else do {} while (0)
3613	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3614	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3615	* buffer after figuring out the actual command size.
3616	*
3617	* Will break out of the switch on failure.
3618	*
3619	* @param a_PtrVar Request variable pointer.
3620	* @param a_Type Request typedef (not pointer) for casting.
3621	* @param a_cbPayloadReq How much payload to fetch.
3622	* @remarks Accesses a bunch of variables in the current scope!
3623	*/
3624	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3625	if (1) { \
3626	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3627	} else do {} while (0)
3628
3629	/**
3630	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3631	*/
3632	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3633	{
3634	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3635	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3636	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3637	int rc;
3638
3639	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3640	return VINF_SUCCESS;
3641
3642	/*
3643	* Special mode where we only execute an external command and the go back
3644	* to being suspended. Currently, all ext cmds ends up here, with the reset
3645	* one also being eligble for runtime execution further down as well.
3646	*/
3647	if (pThis->svga.fFifoExtCommandWakeup)
3648	{
3649	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3650	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3651	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3652	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3653	else
3654	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3655	return VINF_SUCCESS;
3656	}
3657
3658
3659	/*
3660	* Signal the semaphore to make sure we don't wait for 250ms after a
3661	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3662	*/
3663	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3664
3665	/*
3666	* Allocate a bounce buffer for command we get from the FIFO.
3667	* (All code must return via the end of the function to free this buffer.)
3668	*/
3669	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3670	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3671
3672	/*
3673	* Polling/sleep interval config.
3674	*
3675	* We wait for an a short interval if the guest has recently given us work
3676	* to do, but the interval increases the longer we're kept idle. Once we've
3677	* reached the refresh timer interval, we'll switch to extended waits,
3678	* depending on it or the guest to kick us into action when needed.
3679	*
3680	* Should the refresh time go fishing, we'll just continue increasing the
3681	* sleep length till we reaches the 250 ms max after about 16 seconds.
3682	*/
3683	RTMSINTERVAL const cMsMinSleep = 16;
3684	RTMSINTERVAL const cMsIncSleep = 2;
3685	RTMSINTERVAL const cMsMaxSleep = 250;
3686	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3687	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3688
3689	/*
3690	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3691	*
3692	* Initialize with values that will detect an update from the guest.
3693	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3694	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3695	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3696	*/
3697	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3698	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3699	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3700	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3701	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3702
3703	/*
3704	* The FIFO loop.
3705	*/
3706	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3707	bool fBadOrDisabledFifo = false;
3708	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3709	{
3710	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3711	/*
3712	* Should service the run loop every so often.
3713	*/
3714	if (pThis->svga.f3DEnabled)
3715	vmsvga3dCocoaServiceRunLoop();
3716	# endif
3717
3718	/* First check any pending actions. */
3719	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3720
3721	/*
3722	* Unless there's already work pending, go to sleep for a short while.
3723	* (See polling/sleep interval config above.)
3724	*/
3725	if ( fBadOrDisabledFifo
3726	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3727	{
3728	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3729	Assert(pThis->cMilliesRefreshInterval > 0);
3730	if (cMsSleep < pThis->cMilliesRefreshInterval)
3731	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3732	else
3733	{
3734	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3735	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3736	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3737	# endif
3738	if ( !fBadOrDisabledFifo
3739	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3740	rc = VINF_SUCCESS;
3741	else
3742	{
3743	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3744	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3745	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3746	}
3747	}
3748	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3749	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3750	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3751	{
3752	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3753	break;
3754	}
3755	}
3756	else
3757	rc = VINF_SUCCESS;
3758	fBadOrDisabledFifo = false;
3759	if (rc == VERR_TIMEOUT)
3760	{
3761	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3762	{
3763	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3764	continue;
3765	}
3766	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3767
3768	Log(("vmsvgaR3FifoLoop: timeout\n"));
3769	}
3770	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3771	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3772	cMsSleep = cMsMinSleep;
3773
3774	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3775	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3776	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3777
3778	/*
3779	* Handle external commands (currently only reset).
3780	*/
3781	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3782	{
3783	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3784	continue;
3785	}
3786
3787	/*
3788	* The device must be enabled and configured.
3789	*/
3790	if ( !pThis->svga.fEnabled
3791	\|\| !pThis->svga.fConfigured)
3792	{
3793	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3794	fBadOrDisabledFifo = true;
3795	cMsSleep = cMsMaxSleep; /* cheat */
3796	continue;
3797	}
3798
3799	/*
3800	* Get and check the min/max values. We ASSUME that they will remain
3801	* unchanged while we process requests. A further ASSUMPTION is that
3802	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3803	* we don't read it back while in the loop.
3804	*/
3805	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3806	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3807	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3808	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3809	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3810	\|\| offFifoMax <= offFifoMin
3811	\|\| offFifoMax > pThis->svga.cbFIFO
3812	\|\| (offFifoMax & 3) != 0
3813	\|\| (offFifoMin & 3) != 0
3814	\|\| offCurrentCmd < offFifoMin
3815	\|\| offCurrentCmd > offFifoMax))
3816	{
3817	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3818	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3819	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3820	fBadOrDisabledFifo = true;
3821	continue;
3822	}
3823	RT_UNTRUSTED_VALIDATED_FENCE();
3824	if (RT_UNLIKELY(offCurrentCmd & 3))
3825	{
3826	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3827	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3828	offCurrentCmd &= ~UINT32_C(3);
3829	}
3830
3831	/*
3832	* Update the cursor position before we start on the FIFO commands.
3833	*/
3834	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3835	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3836	{
3837	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3838	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3839	{ /* halfways likely */ }
3840	else
3841	{
3842	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3843	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3844	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3845	}
3846	}
3847
3848	/*
3849	* Mark the FIFO as busy.
3850	*/
3851	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
3852	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3853	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3854
3855	/*
3856	* Execute all queued FIFO commands.
3857	* Quit if pending external command or changes in the thread state.
3858	*/
3859	bool fDone = false;
3860	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3861	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3862	{
3863	uint32_t cbPayload = 0;
3864	uint32_t u32IrqStatus = 0;
3865
3866	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3867
3868	/* First check any pending actions. */
3869	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3870
3871	/* Check for pending external commands (reset). */
3872	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3873	break;
3874
3875	/*
3876	* Process the command.
3877	*/
3878	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3879	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3880	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3881	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3882	switch (enmCmdId)
3883	{
3884	case SVGA_CMD_INVALID_CMD:
3885	/* Nothing to do. */
3886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3887	break;
3888
3889	case SVGA_CMD_FENCE:
3890	{
3891	SVGAFifoCmdFence *pCmdFence;
3892	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3893	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3894	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3895	{
3896	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3897	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3898
3899	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3900	{
3901	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3902	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3903	}
3904	else
3905	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3906	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3907	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3908	{
3909	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3910	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3911	}
3912	}
3913	else
3914	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3915	break;
3916	}
3917	case SVGA_CMD_UPDATE:
3918	case SVGA_CMD_UPDATE_VERBOSE:
3919	{
3920	SVGAFifoCmdUpdate *pUpdate;
3921	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3922	if (enmCmdId == SVGA_CMD_UPDATE)
3923	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3924	else
3925	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3926	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3927	/** @todo Multiple screens? */
3928	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3929	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3930	break;
3931	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3932	break;
3933	}
3934
3935	case SVGA_CMD_DEFINE_CURSOR:
3936	{
3937	/* Followed by bitmap data. */
3938	SVGAFifoCmdDefineCursor *pCursor;
3939	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3940	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3941
3942	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3943	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3944	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3945	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3946	AssertBreak(pCursor->andMaskDepth <= 32);
3947	AssertBreak(pCursor->xorMaskDepth <= 32);
3948	RT_UNTRUSTED_VALIDATED_FENCE();
3949
3950	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3951	uint32_t cbAndMask = cbAndLine * pCursor->height;
3952	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3953	uint32_t cbXorMask = cbXorLine * pCursor->height;
3954	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3955
3956	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3957	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3958	break;
3959	}
3960
3961	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3962	{
3963	/* Followed by bitmap data. */
3964	uint32_t cbCursorShape, cbAndMask;
3965	uint8_t *pCursorCopy;
3966	uint32_t cbCmd;
3967
3968	SVGAFifoCmdDefineAlphaCursor *pCursor;
3969	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3970	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
3971
3972	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3973
3974	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
3975	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3976	RT_UNTRUSTED_VALIDATED_FENCE();
3977
3978	/* Refetch the bitmap data as well. */
3979	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
3980	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
3981	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
3982
3983	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
3984	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
3985	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
3986	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
3987
3988	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
3989	AssertPtrBreak(pCursorCopy);
3990
3991	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
3992	memset(pCursorCopy, 0xff, cbAndMask);
3993	/* Colour data */
3994	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
3995
3996	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
3997	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
3998	break;
3999	}
4000
4001	case SVGA_CMD_MOVE_CURSOR:
4002	{
4003	/* Deprecated; there should be no driver which requires this command. However, if
4004	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4005	* alignment.
4006	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4007	*/
4008	SVGAFifoCmdMoveCursor *pMoveCursor;
4009	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
4010	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
4011
4012	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
4013	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4014	break;
4015	}
4016
4017	case SVGA_CMD_DISPLAY_CURSOR:
4018	{
4019	/* Deprecated; there should be no driver which requires this command. However, if
4020	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4021	* alignment.
4022	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4023	*/
4024	SVGAFifoCmdDisplayCursor *pDisplayCursor;
4025	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
4026	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
4027
4028	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
4029	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4030	break;
4031	}
4032
4033	case SVGA_CMD_RECT_FILL:
4034	{
4035	SVGAFifoCmdRectFill *pRectFill;
4036	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectFill, SVGAFifoCmdRectFill, sizeof(*pRectFill));
4037	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectFill);
4038
4039	Log(("vmsvgaR3FifoLoop: RECT FILL %08X @ %d,%d (%dx%d)\n", pRectFill->pixel, pRectFill->destX, pRectFill->destY, pRectFill->width, pRectFill->height));
4040	LogRelMax(4, ("Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4041	break;
4042	}
4043
4044	case SVGA_CMD_RECT_COPY:
4045	{
4046	SVGAFifoCmdRectCopy *pRectCopy;
4047	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectCopy, SVGAFifoCmdRectCopy, sizeof(*pRectCopy));
4048	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectCopy);
4049
4050	Log(("vmsvgaR3FifoLoop: RECT COPY %d,%d -> %d,%d (%dx%d)\n", pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height));
4051	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4052	AssertPtrBreak(pScreen);
4053
4054	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4055	AssertBreak(pRectCopy->srcX < pThis->svga.u32MaxWidth);
4056	AssertBreak(pRectCopy->destX < pThis->svga.u32MaxWidth);
4057	AssertBreak(pRectCopy->width < pThis->svga.u32MaxWidth);
4058	AssertBreak(pRectCopy->srcY < pThis->svga.u32MaxHeight);
4059	AssertBreak(pRectCopy->destY < pThis->svga.u32MaxHeight);
4060	AssertBreak(pRectCopy->height < pThis->svga.u32MaxHeight);
4061
4062	vmsvgaR3RectCopy(pThisCC, pScreen, pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY,
4063	pRectCopy->width, pRectCopy->height, pThis->vram_size);
4064	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height);
4065	break;
4066	}
4067
4068	case SVGA_CMD_RECT_ROP_COPY:
4069	{
4070	SVGAFifoCmdRectRopCopy *pRRCopy;
4071	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRRCopy, SVGAFifoCmdRectRopCopy, sizeof(*pRRCopy));
4072	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectRopCopy);
4073
4074	Log(("vmsvgaR3FifoLoop: RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4075	if (pRRCopy->rop != SVGA_ROP_COPY)
4076	{
4077	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4078	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4079	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4080	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4081	*/
4082	LogRelMax(4, ("RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4083	break;
4084	}
4085
4086	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4087	AssertPtrBreak(pScreen);
4088
4089	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4090	AssertBreak(pRRCopy->srcX < pThis->svga.u32MaxWidth);
4091	AssertBreak(pRRCopy->destX < pThis->svga.u32MaxWidth);
4092	AssertBreak(pRRCopy->width < pThis->svga.u32MaxWidth);
4093	AssertBreak(pRRCopy->srcY < pThis->svga.u32MaxHeight);
4094	AssertBreak(pRRCopy->destY < pThis->svga.u32MaxHeight);
4095	AssertBreak(pRRCopy->height < pThis->svga.u32MaxHeight);
4096
4097	vmsvgaR3RectCopy(pThisCC, pScreen, pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY,
4098	pRRCopy->width, pRRCopy->height, pThis->vram_size);
4099	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height);
4100	break;
4101	}
4102
4103	case SVGA_CMD_ESCAPE:
4104	{
4105	/* Followed by nsize bytes of data. */
4106	SVGAFifoCmdEscape *pEscape;
4107	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
4108	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
4109
4110	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
4111	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
4112	RT_UNTRUSTED_VALIDATED_FENCE();
4113	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
4114	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
4115
4116	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
4117	{
4118	AssertBreak(pEscape->size >= sizeof(uint32_t));
4119	RT_UNTRUSTED_VALIDATED_FENCE();
4120	uint32_t cmd = (uint32_t )(pEscape + 1);
4121	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
4122
4123	switch (cmd)
4124	{
4125	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4126	{
4127	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
4128	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
4129	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4130
4131	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
4132	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4133	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4134
4135	RT_NOREF_PV(pVideoCmd);
4136	break;
4137
4138	}
4139
4140	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4141	{
4142	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4143	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4144	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4145	RT_NOREF_PV(pVideoCmd);
4146	break;
4147	}
4148
4149	default:
4150	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4151	break;
4152	}
4153	}
4154	else
4155	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4156
4157	break;
4158	}
4159	# ifdef VBOX_WITH_VMSVGA3D
4160	case SVGA_CMD_DEFINE_GMR2:
4161	{
4162	SVGAFifoCmdDefineGMR2 *pCmd;
4163	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4164	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4165	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4166
4167	/* Validate current GMR id. */
4168	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4169	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4170	RT_UNTRUSTED_VALIDATED_FENCE();
4171
4172	if (!pCmd->numPages)
4173	{
4174	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4175	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4176	}
4177	else
4178	{
4179	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4180	if (pGMR->cMaxPages)
4181	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4182
4183	/* Not sure if we should always free the descriptor, but for simplicity
4184	we do so if the new size is smaller than the current. */
4185	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4186	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4187	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4188
4189	pGMR->cMaxPages = pCmd->numPages;
4190	/* The rest is done by the REMAP_GMR2 command. */
4191	}
4192	break;
4193	}
4194
4195	case SVGA_CMD_REMAP_GMR2:
4196	{
4197	/* Followed by page descriptors or guest ptr. */
4198	SVGAFifoCmdRemapGMR2 *pCmd;
4199	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4200	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4201
4202	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4203	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4204	RT_UNTRUSTED_VALIDATED_FENCE();
4205
4206	/* Calculate the size of what comes after next and fetch it. */
4207	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4208	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4209	cbCmd += sizeof(SVGAGuestPtr);
4210	else
4211	{
4212	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4213	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4214	{
4215	cbCmd += cbPageDesc;
4216	pCmd->numPages = 1;
4217	}
4218	else
4219	{
4220	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4221	cbCmd += cbPageDesc * pCmd->numPages;
4222	}
4223	}
4224	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4225
4226	/* Validate current GMR id and size. */
4227	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4228	RT_UNTRUSTED_VALIDATED_FENCE();
4229	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4230	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4231	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4232	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4233
4234	if (pCmd->numPages == 0)
4235	break;
4236
4237	/** @todo Move to a separate function vmsvgaGMRRemap() */
4238
4239	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4240	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4241
4242	/*
4243	* We flatten the existing descriptors into a page array, overwrite the
4244	* pages specified in this command and then recompress the descriptor.
4245	*/
4246	/** @todo Optimize the GMR remap algorithm! */
4247
4248	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4249	uint64_t *paNewPage64 = NULL;
4250	if (pGMR->paDesc)
4251	{
4252	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4253
4254	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4255	AssertPtrBreak(paNewPage64);
4256
4257	uint32_t idxPage = 0;
4258	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4259	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4260	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4261	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4262	RT_UNTRUSTED_VALIDATED_FENCE();
4263	}
4264
4265	/* Free the old GMR if present. */
4266	if (pGMR->paDesc)
4267	RTMemFree(pGMR->paDesc);
4268
4269	/* Allocate the maximum amount possible (everything non-continuous) */
4270	PVMSVGAGMRDESCRIPTOR paDescs;
4271	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4272	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4273
4274	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4275	{
4276	/** @todo */
4277	AssertFailed();
4278	pGMR->numDescriptors = 0;
4279	}
4280	else
4281	{
4282	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4283	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4284	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4285
4286	if (paNewPage64)
4287	{
4288	/* Overwrite the old page array with the new page values. */
4289	if (fGCPhys64)
4290	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4291	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4292	else
4293	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4294	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4295
4296	/* Use the updated page array instead of the command data. */
4297	fGCPhys64 = true;
4298	paPages64 = paNewPage64;
4299	pCmd->numPages = cNewTotalPages;
4300	}
4301
4302	/* The first page. */
4303	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4304	* applied to paNewPage64. */
4305	RTGCPHYS GCPhys;
4306	if (fGCPhys64)
4307	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4308	else
4309	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4310	paDescs[0].GCPhys = GCPhys;
4311	paDescs[0].numPages = 1;
4312
4313	/* Subsequent pages. */
4314	uint32_t iDescriptor = 0;
4315	for (uint32_t i = 1; i < pCmd->numPages; i++)
4316	{
4317	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4318	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4319	else
4320	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4321
4322	/* Continuous physical memory? */
4323	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4324	{
4325	Assert(paDescs[iDescriptor].numPages);
4326	paDescs[iDescriptor].numPages++;
4327	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4328	}
4329	else
4330	{
4331	iDescriptor++;
4332	paDescs[iDescriptor].GCPhys = GCPhys;
4333	paDescs[iDescriptor].numPages = 1;
4334	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4335	}
4336	}
4337
4338	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4339	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4340	pGMR->numDescriptors = iDescriptor + 1;
4341	}
4342
4343	if (paNewPage64)
4344	RTMemFree(paNewPage64);
4345
4346	# ifdef DEBUG_GMR_ACCESS
4347	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4348	# endif
4349	break;
4350	}
4351	# endif // VBOX_WITH_VMSVGA3D
4352	case SVGA_CMD_DEFINE_SCREEN:
4353	{
4354	/* The size of this command is specified by the guest and depends on capabilities. */
4355	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4356
4357	SVGAFifoCmdDefineScreen *pCmd;
4358	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4359	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4360	RT_UNTRUSTED_VALIDATED_FENCE();
4361
4362	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4363	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4364	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4365
4366	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4367	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4368	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4369
4370	uint32_t const idScreen = pCmd->screen.id;
4371	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4372
4373	uint32_t const uWidth = pCmd->screen.size.width;
4374	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4375
4376	uint32_t const uHeight = pCmd->screen.size.height;
4377	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4378
4379	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4380	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4381	AssertBreak(cbWidth <= cbPitch);
4382
4383	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4384	AssertBreak(uScreenOffset < pThis->vram_size);
4385
4386	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4387	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4388	AssertBreak( (uHeight == 0 && cbPitch == 0)
4389	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4390	RT_UNTRUSTED_VALIDATED_FENCE();
4391
4392	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4393
4394	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4395
4396	pScreen->fDefined = true;
4397	pScreen->fModified = true;
4398	pScreen->fuScreen = pCmd->screen.flags;
4399	pScreen->idScreen = idScreen;
4400	if (!fBlank)
4401	{
4402	AssertBreak(uWidth > 0 && uHeight > 0);
4403
4404	pScreen->xOrigin = pCmd->screen.root.x;
4405	pScreen->yOrigin = pCmd->screen.root.y;
4406	pScreen->cWidth = uWidth;
4407	pScreen->cHeight = uHeight;
4408	pScreen->offVRAM = uScreenOffset;
4409	pScreen->cbPitch = cbPitch;
4410	pScreen->cBpp = 32;
4411	}
4412	else
4413	{
4414	/* Keep old values. */
4415	}
4416
4417	pThis->svga.fGFBRegisters = false;
4418	vmsvgaR3ChangeMode(pThis, pThisCC);
4419	break;
4420	}
4421
4422	case SVGA_CMD_DESTROY_SCREEN:
4423	{
4424	SVGAFifoCmdDestroyScreen *pCmd;
4425	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4426	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4427
4428	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4429
4430	uint32_t const idScreen = pCmd->screenId;
4431	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4432	RT_UNTRUSTED_VALIDATED_FENCE();
4433
4434	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4435	pScreen->fModified = true;
4436	pScreen->fDefined = false;
4437	pScreen->idScreen = idScreen;
4438
4439	vmsvgaR3ChangeMode(pThis, pThisCC);
4440	break;
4441	}
4442
4443	case SVGA_CMD_DEFINE_GMRFB:
4444	{
4445	SVGAFifoCmdDefineGMRFB *pCmd;
4446	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4447	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4448
4449	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4450	pSVGAState->GMRFB.ptr = pCmd->ptr;
4451	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4452	pSVGAState->GMRFB.format = pCmd->format;
4453	break;
4454	}
4455
4456	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4457	{
4458	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4459	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4460	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4461
4462	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4463	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4464
4465	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4466	RT_UNTRUSTED_VALIDATED_FENCE();
4467
4468	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4469	AssertPtrBreak(pScreen);
4470
4471	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4472	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4473
4474	/* Clip destRect to the screen dimensions. */
4475	SVGASignedRect screenRect;
4476	screenRect.left = 0;
4477	screenRect.top = 0;
4478	screenRect.right = pScreen->cWidth;
4479	screenRect.bottom = pScreen->cHeight;
4480	SVGASignedRect clipRect = pCmd->destRect;
4481	vmsvgaR3ClipRect(&screenRect, &clipRect);
4482	RT_UNTRUSTED_VALIDATED_FENCE();
4483
4484	uint32_t const width = clipRect.right - clipRect.left;
4485	uint32_t const height = clipRect.bottom - clipRect.top;
4486
4487	if ( width == 0
4488	\|\| height == 0)
4489	break; /* Nothing to do. */
4490
4491	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4492	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4493
4494	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4495	* Prepare parameters for vmsvgaR3GmrTransfer.
4496	*/
4497	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4498
4499	/* Destination: host buffer which describes the screen 0 VRAM.
4500	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4501	*/
4502	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4503	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4504	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4505	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4506	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4507	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4508	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4509	+ cbScanline * clipRect.top;
4510	int32_t const cbHstPitch = cbScanline;
4511
4512	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4513	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4514	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4515	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4516	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4517
4518	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4519	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4520	gstPtr, offGst, cbGstPitch,
4521	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4522	AssertRC(rc);
4523	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4524	break;
4525	}
4526
4527	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4528	{
4529	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4530	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4531	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4532
4533	/* Note! This can fetch 3d render results as well!! */
4534	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4535	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4536
4537	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4538	RT_UNTRUSTED_VALIDATED_FENCE();
4539
4540	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4541	AssertPtrBreak(pScreen);
4542
4543	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4544	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4545
4546	/* Clip destRect to the screen dimensions. */
4547	SVGASignedRect screenRect;
4548	screenRect.left = 0;
4549	screenRect.top = 0;
4550	screenRect.right = pScreen->cWidth;
4551	screenRect.bottom = pScreen->cHeight;
4552	SVGASignedRect clipRect = pCmd->srcRect;
4553	vmsvgaR3ClipRect(&screenRect, &clipRect);
4554	RT_UNTRUSTED_VALIDATED_FENCE();
4555
4556	uint32_t const width = clipRect.right - clipRect.left;
4557	uint32_t const height = clipRect.bottom - clipRect.top;
4558
4559	if ( width == 0
4560	\|\| height == 0)
4561	break; /* Nothing to do. */
4562
4563	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4564	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4565
4566	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4567	* Prepare parameters for vmsvgaR3GmrTransfer.
4568	*/
4569	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4570
4571	/* Source: host buffer which describes the screen 0 VRAM.
4572	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4573	*/
4574	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4575	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4576	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4577	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4578	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4579	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4580	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4581	+ cbScanline * clipRect.top;
4582	int32_t const cbHstPitch = cbScanline;
4583
4584	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4585	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4586	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4587	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4588	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4589
4590	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4591	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4592	gstPtr, offGst, cbGstPitch,
4593	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4594	AssertRC(rc);
4595	break;
4596	}
4597
4598	case SVGA_CMD_ANNOTATION_FILL:
4599	{
4600	SVGAFifoCmdAnnotationFill *pCmd;
4601	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4602	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4603
4604	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4605	pSVGAState->colorAnnotation = pCmd->color;
4606	break;
4607	}
4608
4609	case SVGA_CMD_ANNOTATION_COPY:
4610	{
4611	SVGAFifoCmdAnnotationCopy *pCmd;
4612	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4613	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4614
4615	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4616	AssertFailed();
4617	break;
4618	}
4619
4620	default:
4621	# ifdef VBOX_WITH_VMSVGA3D
4622	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4623	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4624	{
4625	RT_UNTRUSTED_VALIDATED_FENCE();
4626
4627	/* All 3d commands start with a common header, which defines the size of the command. */
4628	SVGA3dCmdHeader *pHdr;
4629	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4630	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4631	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4632	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4633
4634	if (RT_LIKELY(pThis->svga.f3DEnabled))
4635	{ /* likely */ }
4636	else
4637	{
4638	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4639	break;
4640	}
4641
4642	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4643	* Check that the 3D command has at least a_cbMin of payload bytes after the
4644	* header. Will break out of the switch if it doesn't.
4645	*/
4646	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4647	if (1) { \
4648	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4649	RT_UNTRUSTED_VALIDATED_FENCE(); \
4650	} else do {} while (0)
4651	switch ((int)enmCmdId)
4652	{
4653	case SVGA_3D_CMD_SURFACE_DEFINE:
4654	{
4655	uint32_t cMipLevels;
4656	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4657	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4658	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4659
4660	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4661	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4662	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4663	# ifdef DEBUG_GMR_ACCESS
4664	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4665	# endif
4666	break;
4667	}
4668
4669	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4670	{
4671	uint32_t cMipLevels;
4672	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4673	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4674	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4675
4676	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4677	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4678	pCmd->multisampleCount, pCmd->autogenFilter,
4679	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4680	break;
4681	}
4682
4683	case SVGA_3D_CMD_SURFACE_DESTROY:
4684	{
4685	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4686	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4687	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4688	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4689	break;
4690	}
4691
4692	case SVGA_3D_CMD_SURFACE_COPY:
4693	{
4694	uint32_t cCopyBoxes;
4695	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4696	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4697	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4698
4699	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4700	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4701	break;
4702	}
4703
4704	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4705	{
4706	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4709
4710	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4711	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4712	break;
4713	}
4714
4715	case SVGA_3D_CMD_SURFACE_DMA:
4716	{
4717	uint32_t cCopyBoxes;
4718	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4719	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4720	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4721
4722	uint64_t u64NanoTS = 0;
4723	if (LogRelIs3Enabled())
4724	u64NanoTS = RTTimeNanoTS();
4725	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4726	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4727	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4728	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4729	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4730	if (LogRelIs3Enabled())
4731	{
4732	if (cCopyBoxes)
4733	{
4734	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4735	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4736	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4737	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4738	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4739	}
4740	}
4741	break;
4742	}
4743
4744	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4745	{
4746	uint32_t cRects;
4747	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4748	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4749	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4750
4751	uint64_t u64NanoTS = 0;
4752	if (LogRelIs3Enabled())
4753	u64NanoTS = RTTimeNanoTS();
4754	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4755	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4756	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4757	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4758	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4759	if (LogRelIs3Enabled())
4760	{
4761	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4762	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4763	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cRects,
4764	pFirstRect->left, pFirstRect->top,
4765	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4766	}
4767	break;
4768	}
4769
4770	case SVGA_3D_CMD_CONTEXT_DEFINE:
4771	{
4772	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4773	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4774	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4775
4776	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4777	break;
4778	}
4779
4780	case SVGA_3D_CMD_CONTEXT_DESTROY:
4781	{
4782	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4783	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4784	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4785
4786	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4787	break;
4788	}
4789
4790	case SVGA_3D_CMD_SETTRANSFORM:
4791	{
4792	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4793	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4794	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4795
4796	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4797	break;
4798	}
4799
4800	case SVGA_3D_CMD_SETZRANGE:
4801	{
4802	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4803	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4805
4806	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4807	break;
4808	}
4809
4810	case SVGA_3D_CMD_SETRENDERSTATE:
4811	{
4812	uint32_t cRenderStates;
4813	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4814	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4815	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4816
4817	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4818	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4819	break;
4820	}
4821
4822	case SVGA_3D_CMD_SETRENDERTARGET:
4823	{
4824	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4825	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4826	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4827
4828	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4829	break;
4830	}
4831
4832	case SVGA_3D_CMD_SETTEXTURESTATE:
4833	{
4834	uint32_t cTextureStates;
4835	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4836	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4837	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4838
4839	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4840	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4841	break;
4842	}
4843
4844	case SVGA_3D_CMD_SETMATERIAL:
4845	{
4846	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4847	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4848	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4849
4850	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4851	break;
4852	}
4853
4854	case SVGA_3D_CMD_SETLIGHTDATA:
4855	{
4856	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4857	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4858	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4859
4860	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4861	break;
4862	}
4863
4864	case SVGA_3D_CMD_SETLIGHTENABLED:
4865	{
4866	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4867	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4869
4870	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4871	break;
4872	}
4873
4874	case SVGA_3D_CMD_SETVIEWPORT:
4875	{
4876	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4877	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4879
4880	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4881	break;
4882	}
4883
4884	case SVGA_3D_CMD_SETCLIPPLANE:
4885	{
4886	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4887	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4888	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4889
4890	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4891	break;
4892	}
4893
4894	case SVGA_3D_CMD_CLEAR:
4895	{
4896	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4897	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4898	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4899
4900	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4901	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4902	break;
4903	}
4904
4905	case SVGA_3D_CMD_PRESENT:
4906	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4907	{
4908	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4909	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4910	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4911	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4912	else
4913	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4914
4915	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4916
4917	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4918	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4919	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4920	break;
4921	}
4922
4923	case SVGA_3D_CMD_SHADER_DEFINE:
4924	{
4925	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4926	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4927	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4928
4929	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4930	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4931	break;
4932	}
4933
4934	case SVGA_3D_CMD_SHADER_DESTROY:
4935	{
4936	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4937	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4938	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4939
4940	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4941	break;
4942	}
4943
4944	case SVGA_3D_CMD_SET_SHADER:
4945	{
4946	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4947	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4948	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
4949
4950	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
4951	break;
4952	}
4953
4954	case SVGA_3D_CMD_SET_SHADER_CONST:
4955	{
4956	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
4957	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4958	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
4959
4960	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
4961	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
4962	break;
4963	}
4964
4965	case SVGA_3D_CMD_DRAW_PRIMITIVES:
4966	{
4967	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
4968	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4969	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
4970
4971	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
4972	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
4973	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
4974	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
4975	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
4976
4977	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
4978	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
4979
4980	RT_UNTRUSTED_VALIDATED_FENCE();
4981
4982	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
4983	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
4984	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
4985
4986	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4987	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
4988	pNumRange, cVertexDivisor, pVertexDivisor);
4989	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
4990	break;
4991	}
4992
4993	case SVGA_3D_CMD_SETSCISSORRECT:
4994	{
4995	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
4996	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4997	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
4998
4999	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
5000	break;
5001	}
5002
5003	case SVGA_3D_CMD_BEGIN_QUERY:
5004	{
5005	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
5006	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5007	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
5008
5009	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5010	break;
5011	}
5012
5013	case SVGA_3D_CMD_END_QUERY:
5014	{
5015	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
5016	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5017	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
5018
5019	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5020	break;
5021	}
5022
5023	case SVGA_3D_CMD_WAIT_FOR_QUERY:
5024	{
5025	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
5026	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5027	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
5028
5029	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5030	break;
5031	}
5032
5033	case SVGA_3D_CMD_GENERATE_MIPMAPS:
5034	{
5035	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
5036	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5037	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
5038
5039	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5040	break;
5041	}
5042
5043	case SVGA_3D_CMD_ACTIVATE_SURFACE:
5044	/* context id + surface id? */
5045	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
5046	break;
5047	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5048	/* context id + surface id? */
5049	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
5050	break;
5051
5052	default:
5053	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5054	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5055	break;
5056	}
5057	}
5058	else
5059	# endif // VBOX_WITH_VMSVGA3D
5060	{
5061	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5062	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5063	}
5064	}
5065
5066	/* Go to the next slot */
5067	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5068	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5069	if (offCurrentCmd >= offFifoMax)
5070	{
5071	offCurrentCmd -= offFifoMax - offFifoMin;
5072	Assert(offCurrentCmd >= offFifoMin);
5073	Assert(offCurrentCmd < offFifoMax);
5074	}
5075	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5076	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5077
5078	/*
5079	* Raise IRQ if required. Must enter the critical section here
5080	* before making final decisions here, otherwise cubebench and
5081	* others may end up waiting forever.
5082	*/
5083	if ( u32IrqStatus
5084	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5085	{
5086	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5087	AssertRC(rc2);
5088
5089	/* FIFO progress might trigger an interrupt. */
5090	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5091	{
5092	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5093	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5094	}
5095
5096	/* Unmasked IRQ pending? */
5097	if (pThis->svga.u32IrqMask & u32IrqStatus)
5098	{
5099	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5100	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5101	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5102	}
5103
5104	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5105	}
5106	}
5107
5108	/* If really done, clear the busy flag. */
5109	if (fDone)
5110	{
5111	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5112	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5113	}
5114	}
5115
5116	/*
5117	* Free the bounce buffer. (There are no returns above!)
5118	*/
5119	RTMemFree(pbBounceBuf);
5120
5121	return VINF_SUCCESS;
5122	}
5123
5124	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5125	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5126	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5127
5128	#ifdef VBOX_WITH_VMSVGA3D
5129	/**
5130	* Free the specified GMR
5131	*
5132	* @param pThisCC The VGA/VMSVGA state for ring-3.
5133	* @param idGMR GMR id
5134	*/
5135	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5136	{
5137	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5138
5139	/* Free the old descriptor if present. */
5140	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5141	if ( pGMR->numDescriptors
5142	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5143	{
5144	# ifdef DEBUG_GMR_ACCESS
5145	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5146	# endif
5147
5148	Assert(pGMR->paDesc);
5149	RTMemFree(pGMR->paDesc);
5150	pGMR->paDesc = NULL;
5151	pGMR->numDescriptors = 0;
5152	pGMR->cbTotal = 0;
5153	pGMR->cMaxPages = 0;
5154	}
5155	Assert(!pGMR->cMaxPages);
5156	Assert(!pGMR->cbTotal);
5157	}
5158	#endif /* VBOX_WITH_VMSVGA3D */
5159
5160	/**
5161	* Copy between a GMR and a host memory buffer.
5162	*
5163	* @returns VBox status code.
5164	* @param pThis The shared VGA/VMSVGA instance data.
5165	* @param pThisCC The VGA/VMSVGA state for ring-3.
5166	* @param enmTransferType Transfer type (read/write)
5167	* @param pbHstBuf Host buffer pointer (valid)
5168	* @param cbHstBuf Size of host buffer (valid)
5169	* @param offHst Host buffer offset of the first scanline
5170	* @param cbHstPitch Destination buffer pitch
5171	* @param gstPtr GMR description
5172	* @param offGst Guest buffer offset of the first scanline
5173	* @param cbGstPitch Guest buffer pitch
5174	* @param cbWidth Width in bytes to copy
5175	* @param cHeight Number of scanllines to copy
5176	*/
5177	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5178	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5179	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5180	uint32_t cbWidth, uint32_t cHeight)
5181	{
5182	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5183	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5184	int rc;
5185
5186	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5187	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5188	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5189	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5190	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5191
5192	PGMR pGMR;
5193	uint32_t cbGmr; /* The GMR size in bytes. */
5194	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5195	{
5196	pGMR = NULL;
5197	cbGmr = pThis->vram_size;
5198	}
5199	else
5200	{
5201	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5202	RT_UNTRUSTED_VALIDATED_FENCE();
5203	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5204	cbGmr = pGMR->cbTotal;
5205	}
5206
5207	/*
5208	* GMR
5209	*/
5210	/* Calculate GMR offset of the data to be copied. */
5211	AssertMsgReturn(gstPtr.offset < cbGmr,
5212	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5213	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5214	VERR_INVALID_PARAMETER);
5215	RT_UNTRUSTED_VALIDATED_FENCE();
5216	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5217	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5218	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5219	VERR_INVALID_PARAMETER);
5220	RT_UNTRUSTED_VALIDATED_FENCE();
5221	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5222
5223	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5224	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5225	AssertMsgReturn(cbGmrScanline != 0,
5226	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5227	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5228	VERR_INVALID_PARAMETER);
5229	RT_UNTRUSTED_VALIDATED_FENCE();
5230	AssertMsgReturn(cbWidth <= cbGmrScanline,
5231	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5232	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5233	VERR_INVALID_PARAMETER);
5234	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5235	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5236	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5237	VERR_INVALID_PARAMETER);
5238	RT_UNTRUSTED_VALIDATED_FENCE();
5239
5240	/* How many bytes are available for the data in the GMR. */
5241	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5242
5243	/* How many scanlines would fit into the available data. */
5244	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5245	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5246	if (cbWidth <= cbGmrLastScanline)
5247	++cGmrScanlines;
5248
5249	if (cHeight > cGmrScanlines)
5250	cHeight = cGmrScanlines;
5251
5252	AssertMsgReturn(cHeight > 0,
5253	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5254	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5255	VERR_INVALID_PARAMETER);
5256	RT_UNTRUSTED_VALIDATED_FENCE();
5257
5258	/*
5259	* Host buffer.
5260	*/
5261	AssertMsgReturn(offHst < cbHstBuf,
5262	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5263	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5264	VERR_INVALID_PARAMETER);
5265
5266	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5267	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5268	AssertMsgReturn(cbHstScanline != 0,
5269	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5270	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5271	VERR_INVALID_PARAMETER);
5272	AssertMsgReturn(cbWidth <= cbHstScanline,
5273	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5274	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5275	VERR_INVALID_PARAMETER);
5276	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5277	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5278	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5279	VERR_INVALID_PARAMETER);
5280
5281	/* How many bytes are available for the data in the buffer. */
5282	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5283
5284	/* How many scanlines would fit into the available data. */
5285	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5286	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5287	if (cbWidth <= cbHstLastScanline)
5288	++cHstScanlines;
5289
5290	if (cHeight > cHstScanlines)
5291	cHeight = cHstScanlines;
5292
5293	AssertMsgReturn(cHeight > 0,
5294	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5295	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5296	VERR_INVALID_PARAMETER);
5297
5298	uint8_t *pbHst = pbHstBuf + offHst;
5299
5300	/* Shortcut for the framebuffer. */
5301	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5302	{
5303	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5304
5305	uint8_t const *pbSrc;
5306	int32_t cbSrcPitch;
5307	uint8_t *pbDst;
5308	int32_t cbDstPitch;
5309
5310	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5311	{
5312	pbSrc = pbHst;
5313	cbSrcPitch = cbHstPitch;
5314	pbDst = pbGst;
5315	cbDstPitch = cbGstPitch;
5316	}
5317	else
5318	{
5319	pbSrc = pbGst;
5320	cbSrcPitch = cbGstPitch;
5321	pbDst = pbHst;
5322	cbDstPitch = cbHstPitch;
5323	}
5324
5325	if ( cbWidth == (uint32_t)cbGstPitch
5326	&& cbGstPitch == cbHstPitch)
5327	{
5328	/* Entire scanlines, positive pitch. */
5329	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5330	}
5331	else
5332	{
5333	for (uint32_t i = 0; i < cHeight; ++i)
5334	{
5335	memcpy(pbDst, pbSrc, cbWidth);
5336
5337	pbDst += cbDstPitch;
5338	pbSrc += cbSrcPitch;
5339	}
5340	}
5341	return VINF_SUCCESS;
5342	}
5343
5344	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5345	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5346
5347	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5348	uint32_t iDesc = 0; /* Index in the descriptor array. */
5349	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5350	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5351	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5352	for (uint32_t i = 0; i < cHeight; ++i)
5353	{
5354	uint32_t cbCurrentWidth = cbWidth;
5355	uint32_t offGmrCurrent = offGmrScanline;
5356	uint8_t *pbCurrentHost = pbHstScanline;
5357
5358	/* Find the right descriptor */
5359	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5360	{
5361	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5362	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5363	++iDesc;
5364	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5365	}
5366
5367	while (cbCurrentWidth)
5368	{
5369	uint32_t cbToCopy;
5370
5371	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5372	{
5373	cbToCopy = cbCurrentWidth;
5374	}
5375	else
5376	{
5377	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5378	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5379	}
5380
5381	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5382
5383	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5384
5385	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5386	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5387	else
5388	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5389	AssertRCBreak(rc);
5390
5391	cbCurrentWidth -= cbToCopy;
5392	offGmrCurrent += cbToCopy;
5393	pbCurrentHost += cbToCopy;
5394
5395	/* Go to the next descriptor if there's anything left. */
5396	if (cbCurrentWidth)
5397	{
5398	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5399	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5400	++iDesc;
5401	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5402	}
5403	}
5404
5405	offGmrScanline += cbGstPitch;
5406	pbHstScanline += cbHstPitch;
5407	}
5408
5409	return VINF_SUCCESS;
5410	}
5411
5412
5413	/**
5414	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5415	*
5416	* @param pSizeSrc Source surface dimensions.
5417	* @param pSizeDest Destination surface dimensions.
5418	* @param pBox Coordinates to be clipped.
5419	*/
5420	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5421	{
5422	/* Src x, w */
5423	if (pBox->srcx > pSizeSrc->width)
5424	pBox->srcx = pSizeSrc->width;
5425	if (pBox->w > pSizeSrc->width - pBox->srcx)
5426	pBox->w = pSizeSrc->width - pBox->srcx;
5427
5428	/* Src y, h */
5429	if (pBox->srcy > pSizeSrc->height)
5430	pBox->srcy = pSizeSrc->height;
5431	if (pBox->h > pSizeSrc->height - pBox->srcy)
5432	pBox->h = pSizeSrc->height - pBox->srcy;
5433
5434	/* Src z, d */
5435	if (pBox->srcz > pSizeSrc->depth)
5436	pBox->srcz = pSizeSrc->depth;
5437	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5438	pBox->d = pSizeSrc->depth - pBox->srcz;
5439
5440	/* Dest x, w */
5441	if (pBox->x > pSizeDest->width)
5442	pBox->x = pSizeDest->width;
5443	if (pBox->w > pSizeDest->width - pBox->x)
5444	pBox->w = pSizeDest->width - pBox->x;
5445
5446	/* Dest y, h */
5447	if (pBox->y > pSizeDest->height)
5448	pBox->y = pSizeDest->height;
5449	if (pBox->h > pSizeDest->height - pBox->y)
5450	pBox->h = pSizeDest->height - pBox->y;
5451
5452	/* Dest z, d */
5453	if (pBox->z > pSizeDest->depth)
5454	pBox->z = pSizeDest->depth;
5455	if (pBox->d > pSizeDest->depth - pBox->z)
5456	pBox->d = pSizeDest->depth - pBox->z;
5457	}
5458
5459	/**
5460	* Unsigned coordinates in pBox. Clip to [0; pSize).
5461	*
5462	* @param pSize Source surface dimensions.
5463	* @param pBox Coordinates to be clipped.
5464	*/
5465	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5466	{
5467	/* x, w */
5468	if (pBox->x > pSize->width)
5469	pBox->x = pSize->width;
5470	if (pBox->w > pSize->width - pBox->x)
5471	pBox->w = pSize->width - pBox->x;
5472
5473	/* y, h */
5474	if (pBox->y > pSize->height)
5475	pBox->y = pSize->height;
5476	if (pBox->h > pSize->height - pBox->y)
5477	pBox->h = pSize->height - pBox->y;
5478
5479	/* z, d */
5480	if (pBox->z > pSize->depth)
5481	pBox->z = pSize->depth;
5482	if (pBox->d > pSize->depth - pBox->z)
5483	pBox->d = pSize->depth - pBox->z;
5484	}
5485
5486	/**
5487	* Clip.
5488	*
5489	* @param pBound Bounding rectangle.
5490	* @param pRect Rectangle to be clipped.
5491	*/
5492	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5493	{
5494	int32_t left;
5495	int32_t top;
5496	int32_t right;
5497	int32_t bottom;
5498
5499	/* Right order. */
5500	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5501	if (pRect->left < pRect->right)
5502	{
5503	left = pRect->left;
5504	right = pRect->right;
5505	}
5506	else
5507	{
5508	left = pRect->right;
5509	right = pRect->left;
5510	}
5511	if (pRect->top < pRect->bottom)
5512	{
5513	top = pRect->top;
5514	bottom = pRect->bottom;
5515	}
5516	else
5517	{
5518	top = pRect->bottom;
5519	bottom = pRect->top;
5520	}
5521
5522	if (left < pBound->left)
5523	left = pBound->left;
5524	if (right < pBound->left)
5525	right = pBound->left;
5526
5527	if (left > pBound->right)
5528	left = pBound->right;
5529	if (right > pBound->right)
5530	right = pBound->right;
5531
5532	if (top < pBound->top)
5533	top = pBound->top;
5534	if (bottom < pBound->top)
5535	bottom = pBound->top;
5536
5537	if (top > pBound->bottom)
5538	top = pBound->bottom;
5539	if (bottom > pBound->bottom)
5540	bottom = pBound->bottom;
5541
5542	pRect->left = left;
5543	pRect->right = right;
5544	pRect->top = top;
5545	pRect->bottom = bottom;
5546	}
5547
5548	/**
5549	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5550	* Unblock the FIFO I/O thread so it can respond to a state change.}
5551	*/
5552	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5553	{
5554	RT_NOREF(pDevIns);
5555	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5556	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5557	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5558	}
5559
5560	/**
5561	* Enables or disables dirty page tracking for the framebuffer
5562	*
5563	* @param pDevIns The device instance.
5564	* @param pThis The shared VGA/VMSVGA instance data.
5565	* @param fTraces Enable/disable traces
5566	*/
5567	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5568	{
5569	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5570	&& !fTraces)
5571	{
5572	//Assert(pThis->svga.fTraces);
5573	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5574	return;
5575	}
5576
5577	pThis->svga.fTraces = fTraces;
5578	if (pThis->svga.fTraces)
5579	{
5580	unsigned cbFrameBuffer = pThis->vram_size;
5581
5582	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5583	/** @todo How does this work with screens? */
5584	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5585	{
5586	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5587	Assert(pThis->svga.cbScanline);
5588	# endif
5589	/* Hardware enabled; return real framebuffer size .*/
5590	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5591	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5592	}
5593
5594	if (!pThis->svga.fVRAMTracking)
5595	{
5596	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5597	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5598	pThis->svga.fVRAMTracking = true;
5599	}
5600	}
5601	else
5602	{
5603	if (pThis->svga.fVRAMTracking)
5604	{
5605	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5606	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5607	pThis->svga.fVRAMTracking = false;
5608	}
5609	}
5610	}
5611
5612	/**
5613	* @callback_method_impl{FNPCIIOREGIONMAP}
5614	*/
5615	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5616	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5617	{
5618	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5619	int rc;
5620	RT_NOREF(pPciDev);
5621	Assert(pPciDev == pDevIns->apPciDevs[0]);
5622
5623	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5624	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5625	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5626	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5627	, VERR_INTERNAL_ERROR);
5628	if (GCPhysAddress != NIL_RTGCPHYS)
5629	{
5630	/*
5631	* Mapping the FIFO RAM.
5632	*/
5633	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5634	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5635	AssertRC(rc);
5636
5637	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5638	if (RT_SUCCESS(rc))
5639	{
5640	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5641	# ifdef DEBUG_FIFO_ACCESS
5642	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5643	# else
5644	GCPhysAddress + PAGE_SIZE - 1,
5645	# endif
5646	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5647	"VMSVGA FIFO");
5648	AssertRC(rc);
5649	}
5650	# endif
5651	if (RT_SUCCESS(rc))
5652	{
5653	pThis->svga.GCPhysFIFO = GCPhysAddress;
5654	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5655	}
5656	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5657	}
5658	else
5659	{
5660	Assert(pThis->svga.GCPhysFIFO);
5661	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5662	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5663	AssertRC(rc);
5664	# else
5665	rc = VINF_SUCCESS;
5666	# endif
5667	pThis->svga.GCPhysFIFO = 0;
5668	}
5669	return rc;
5670	}
5671
5672	# ifdef VBOX_WITH_VMSVGA3D
5673
5674	/**
5675	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5676	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5677	*
5678	* @param pDevIns The device instance.
5679	* @param pThis The The shared VGA/VMSVGA instance data.
5680	* @param pThisCC The VGA/VMSVGA state for ring-3.
5681	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5682	* UINT32_MAX is used, all surfaces are processed.
5683	*/
5684	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5685	{
5686	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5687	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5688	}
5689
5690
5691	/**
5692	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5693	*/
5694	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5695	{
5696	/* There might be a specific surface ID at the start of the
5697	arguments, if not show all surfaces. */
5698	uint32_t sid = UINT32_MAX;
5699	if (pszArgs)
5700	pszArgs = RTStrStripL(pszArgs);
5701	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5702	sid = RTStrToUInt32(pszArgs);
5703
5704	/* Verbose or terse display, we default to verbose. */
5705	bool fVerbose = true;
5706	if (RTStrIStr(pszArgs, "terse"))
5707	fVerbose = false;
5708
5709	/* The size of the ascii art (x direction, y is 3/4 of x). */
5710	uint32_t cxAscii = 80;
5711	if (RTStrIStr(pszArgs, "gigantic"))
5712	cxAscii = 300;
5713	else if (RTStrIStr(pszArgs, "huge"))
5714	cxAscii = 180;
5715	else if (RTStrIStr(pszArgs, "big"))
5716	cxAscii = 132;
5717	else if (RTStrIStr(pszArgs, "normal"))
5718	cxAscii = 80;
5719	else if (RTStrIStr(pszArgs, "medium"))
5720	cxAscii = 64;
5721	else if (RTStrIStr(pszArgs, "small"))
5722	cxAscii = 48;
5723	else if (RTStrIStr(pszArgs, "tiny"))
5724	cxAscii = 24;
5725
5726	/* Y invert the image when producing the ASCII art. */
5727	bool fInvY = false;
5728	if (RTStrIStr(pszArgs, "invy"))
5729	fInvY = true;
5730
5731	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5732	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5733	}
5734
5735
5736	/**
5737	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5738	*/
5739	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5740	{
5741	/* pszArg = "sid[>dir]"
5742	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5743	*/
5744	char *pszBitmapPath = NULL;
5745	uint32_t sid = UINT32_MAX;
5746	if (pszArgs)
5747	pszArgs = RTStrStripL(pszArgs);
5748	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5749	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5750	if ( pszBitmapPath
5751	&& *pszBitmapPath == '>')
5752	++pszBitmapPath;
5753
5754	const bool fVerbose = true;
5755	const uint32_t cxAscii = 0; /* No ASCII */
5756	const bool fInvY = false; /* Do not invert. */
5757	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5758	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5759	}
5760
5761	/**
5762	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5763	*/
5764	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5765	{
5766	/* There might be a specific surface ID at the start of the
5767	arguments, if not show all contexts. */
5768	uint32_t sid = UINT32_MAX;
5769	if (pszArgs)
5770	pszArgs = RTStrStripL(pszArgs);
5771	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5772	sid = RTStrToUInt32(pszArgs);
5773
5774	/* Verbose or terse display, we default to verbose. */
5775	bool fVerbose = true;
5776	if (RTStrIStr(pszArgs, "terse"))
5777	fVerbose = false;
5778
5779	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5780	}
5781	# endif /* VBOX_WITH_VMSVGA3D */
5782
5783	/**
5784	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5785	*/
5786	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5787	{
5788	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5789	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5790	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5791	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5792	RT_NOREF(pszArgs);
5793
5794	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5795	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5796	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5797	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5798	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5799	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5800	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5801	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5802	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5803	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5804	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5805	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5806	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5807	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5808	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5809	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5810	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5811	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5812	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5813	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5814	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5815	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5816	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5817	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5818	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5819
5820	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5821	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5822	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5823	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5824
5825	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5826	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5827
5828	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5829	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5830
5831	# ifdef VBOX_WITH_VMSVGA3D
5832	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5833	# endif
5834	if (pThisCC->pDrv)
5835	{
5836	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5837	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5838	}
5839
5840	/* Dump screen information. */
5841	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5842	{
5843	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5844	if (pScreen)
5845	{
5846	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5847	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5848	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5849	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5850	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5851	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5852	{
5853	pHlp->pfnPrintf(pHlp, " (");
5854	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5855	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5856	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5857	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5858	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5859	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5860	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5861	pHlp->pfnPrintf(pHlp, " BLANKING");
5862	pHlp->pfnPrintf(pHlp, " )");
5863	}
5864	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5865	}
5866	}
5867
5868	}
5869
5870	/**
5871	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5872	*/
5873	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5874	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5875	{
5876	RT_NOREF(uPass);
5877
5878	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5879	int rc;
5880
5881	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5882	{
5883	uint32_t cScreens = 0;
5884	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5885	AssertRCReturn(rc, rc);
5886	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5887	("cScreens=%#x\n", cScreens),
5888	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5889
5890	for (uint32_t i = 0; i < cScreens; ++i)
5891	{
5892	VMSVGASCREENOBJECT screen;
5893	RT_ZERO(screen);
5894
5895	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5896	AssertLogRelRCReturn(rc, rc);
5897
5898	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5899	{
5900	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5901	*pScreen = screen;
5902	pScreen->fModified = true;
5903	}
5904	else
5905	{
5906	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5907	}
5908	}
5909	}
5910	else
5911	{
5912	/* Try to setup at least the first screen. */
5913	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5914	pScreen->fDefined = true;
5915	pScreen->fModified = true;
5916	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5917	pScreen->idScreen = 0;
5918	pScreen->xOrigin = 0;
5919	pScreen->yOrigin = 0;
5920	pScreen->offVRAM = pThis->svga.uScreenOffset;
5921	pScreen->cbPitch = pThis->svga.cbScanline;
5922	pScreen->cWidth = pThis->svga.uWidth;
5923	pScreen->cHeight = pThis->svga.uHeight;
5924	pScreen->cBpp = pThis->svga.uBpp;
5925	}
5926
5927	return VINF_SUCCESS;
5928	}
5929
5930	/**
5931	* @copydoc FNSSMDEVLOADEXEC
5932	*/
5933	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5934	{
5935	RT_NOREF(uPass);
5936	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5937	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5938	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5939	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5940	int rc;
5941
5942	/* Load our part of the VGAState */
5943	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5944	AssertRCReturn(rc, rc);
5945
5946	/* Load the VGA framebuffer. */
5947	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5948	uint32_t cbVgaFramebuffer = _32K;
5949	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5950	{
5951	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5952	AssertRCReturn(rc, rc);
5953	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5954	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5955	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5956	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5957	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5958	}
5959	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5960	AssertRCReturn(rc, rc);
5961	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5962	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5963	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5964	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5965
5966	/* Load the VMSVGA state. */
5967	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5968	AssertRCReturn(rc, rc);
5969
5970	/* Load the active cursor bitmaps. */
5971	if (pSVGAState->Cursor.fActive)
5972	{
5973	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5974	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5975
5976	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5977	AssertRCReturn(rc, rc);
5978	}
5979
5980	/* Load the GMR state. */
5981	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5982	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5983	{
5984	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5985	AssertRCReturn(rc, rc);
5986	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5987	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5988	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5989	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5990	}
5991
5992	if (pThis->svga.cGMR != cGMR)
5993	{
5994	/* Reallocate GMR array. */
5995	Assert(pSVGAState->paGMR != NULL);
5996	RTMemFree(pSVGAState->paGMR);
5997	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5998	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5999	pThis->svga.cGMR = cGMR;
6000	}
6001
6002	for (uint32_t i = 0; i < cGMR; ++i)
6003	{
6004	PGMR pGMR = &pSVGAState->paGMR[i];
6005
6006	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6007	AssertRCReturn(rc, rc);
6008
6009	if (pGMR->numDescriptors)
6010	{
6011	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6012	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6013	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6014
6015	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6016	{
6017	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6018	AssertRCReturn(rc, rc);
6019	}
6020	}
6021	}
6022
6023	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6024	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
6025	# endif
6026
6027	VMSVGA_STATE_LOAD LoadState;
6028	LoadState.pSSM = pSSM;
6029	LoadState.uVersion = uVersion;
6030	LoadState.uPass = uPass;
6031	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6032	AssertLogRelRCReturn(rc, rc);
6033
6034	return VINF_SUCCESS;
6035	}
6036
6037	/**
6038	* Reinit the video mode after the state has been loaded.
6039	*/
6040	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6041	{
6042	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6043	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6044	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6045
6046	/* Set the active cursor. */
6047	if (pSVGAState->Cursor.fActive)
6048	{
6049	/* We don't store the alpha flag, but we can take a guess that if
6050	* the old register interface was used, the cursor was B&W.
6051	*/
6052	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6053
6054	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6055	true /fVisible/,
6056	fAlpha,
6057	pSVGAState->Cursor.xHotspot,
6058	pSVGAState->Cursor.yHotspot,
6059	pSVGAState->Cursor.width,
6060	pSVGAState->Cursor.height,
6061	pSVGAState->Cursor.pData);
6062	AssertRC(rc);
6063
6064	if (pThis->svga.uCursorOn)
6065	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6066	}
6067
6068	/* If the VRAM handler should not be registered, we have to explicitly
6069	* unregister it here!
6070	*/
6071	if (!pThis->svga.fVRAMTracking)
6072	{
6073	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6074	}
6075
6076	/* Let the FIFO thread deal with changing the mode. */
6077	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6078
6079	return VINF_SUCCESS;
6080	}
6081
6082	/**
6083	* Portion of SVGA state which must be saved in the FIFO thread.
6084	*/
6085	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6086	{
6087	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6088	int rc;
6089
6090	/* Save the screen objects. */
6091	/* Count defined screen object. */
6092	uint32_t cScreens = 0;
6093	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6094	{
6095	if (pSVGAState->aScreens[i].fDefined)
6096	++cScreens;
6097	}
6098
6099	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6100	AssertLogRelRCReturn(rc, rc);
6101
6102	for (uint32_t i = 0; i < cScreens; ++i)
6103	{
6104	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6105
6106	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6107	AssertLogRelRCReturn(rc, rc);
6108	}
6109	return VINF_SUCCESS;
6110	}
6111
6112	/**
6113	* @copydoc FNSSMDEVSAVEEXEC
6114	*/
6115	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6116	{
6117	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6118	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6119	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6120	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6121	int rc;
6122
6123	/* Save our part of the VGAState */
6124	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6125	AssertLogRelRCReturn(rc, rc);
6126
6127	/* Save the framebuffer backup. */
6128	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6129	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6130	AssertLogRelRCReturn(rc, rc);
6131
6132	/* Save the VMSVGA state. */
6133	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6134	AssertLogRelRCReturn(rc, rc);
6135
6136	/* Save the active cursor bitmaps. */
6137	if (pSVGAState->Cursor.fActive)
6138	{
6139	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6140	AssertLogRelRCReturn(rc, rc);
6141	}
6142
6143	/* Save the GMR state */
6144	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6145	AssertLogRelRCReturn(rc, rc);
6146	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6147	{
6148	PGMR pGMR = &pSVGAState->paGMR[i];
6149
6150	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6151	AssertLogRelRCReturn(rc, rc);
6152
6153	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6154	{
6155	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6156	AssertLogRelRCReturn(rc, rc);
6157	}
6158	}
6159
6160	/*
6161	* Must save some state (3D in particular) in the FIFO thread.
6162	*/
6163	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6164	AssertLogRelRCReturn(rc, rc);
6165
6166	return VINF_SUCCESS;
6167	}
6168
6169	/**
6170	* Destructor for PVMSVGAR3STATE structure.
6171	*
6172	* @param pThis The shared VGA/VMSVGA instance data.
6173	* @param pSVGAState Pointer to the structure. It is not deallocated.
6174	*/
6175	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6176	{
6177	# ifndef VMSVGA_USE_EMT_HALT_CODE
6178	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6179	{
6180	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6181	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6182	}
6183	# endif
6184
6185	if (pSVGAState->Cursor.fActive)
6186	{
6187	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6188	pSVGAState->Cursor.pData = NULL;
6189	pSVGAState->Cursor.fActive = false;
6190	}
6191
6192	if (pSVGAState->paGMR)
6193	{
6194	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6195	if (pSVGAState->paGMR[i].paDesc)
6196	RTMemFree(pSVGAState->paGMR[i].paDesc);
6197
6198	RTMemFree(pSVGAState->paGMR);
6199	pSVGAState->paGMR = NULL;
6200	}
6201	}
6202
6203	/**
6204	* Constructor for PVMSVGAR3STATE structure.
6205	*
6206	* @returns VBox status code.
6207	* @param pThis The shared VGA/VMSVGA instance data.
6208	* @param pSVGAState Pointer to the structure. It is already allocated.
6209	*/
6210	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6211	{
6212	int rc = VINF_SUCCESS;
6213	RT_ZERO(*pSVGAState);
6214
6215	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6216	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6217
6218	# ifndef VMSVGA_USE_EMT_HALT_CODE
6219	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6220	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6221	AssertRCReturn(rc, rc);
6222	# endif
6223
6224	return rc;
6225	}
6226
6227	/**
6228	* Initializes the host capabilities: registers and FIFO.
6229	*
6230	* @returns VBox status code.
6231	* @param pThis The shared VGA/VMSVGA instance data.
6232	* @param pThisCC The VGA/VMSVGA state for ring-3.
6233	*/
6234	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6235	{
6236	/* Register caps. */
6237	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6238	\| SVGA_CAP_GMR2
6239	\| SVGA_CAP_CURSOR
6240	\| SVGA_CAP_CURSOR_BYPASS
6241	\| SVGA_CAP_CURSOR_BYPASS_2
6242	\| SVGA_CAP_EXTENDED_FIFO
6243	\| SVGA_CAP_IRQMASK
6244	\| SVGA_CAP_PITCHLOCK
6245	\| SVGA_CAP_RECT_COPY
6246	\| SVGA_CAP_TRACES
6247	\| SVGA_CAP_SCREEN_OBJECT_2
6248	\| SVGA_CAP_ALPHA_CURSOR;
6249	# ifdef VBOX_WITH_VMSVGA3D
6250	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6251	# endif
6252
6253	/* Clear the FIFO. */
6254	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6255
6256	/* Setup FIFO capabilities. */
6257	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6258	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6259	\| SVGA_FIFO_CAP_GMR2
6260	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6261	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6262	\| SVGA_FIFO_CAP_RESERVE
6263	\| SVGA_FIFO_CAP_PITCHLOCK;
6264
6265	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6266	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6267	}
6268
6269	# ifdef VBOX_WITH_VMSVGA3D
6270	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6271	static const char * const g_apszVmSvgaDevCapNames[] =
6272	{
6273	"x3D", /* = 0 */
6274	"xMAX_LIGHTS",
6275	"xMAX_TEXTURES",
6276	"xMAX_CLIP_PLANES",
6277	"xVERTEX_SHADER_VERSION",
6278	"xVERTEX_SHADER",
6279	"xFRAGMENT_SHADER_VERSION",
6280	"xFRAGMENT_SHADER",
6281	"xMAX_RENDER_TARGETS",
6282	"xS23E8_TEXTURES",
6283	"xS10E5_TEXTURES",
6284	"xMAX_FIXED_VERTEXBLEND",
6285	"xD16_BUFFER_FORMAT",
6286	"xD24S8_BUFFER_FORMAT",
6287	"xD24X8_BUFFER_FORMAT",
6288	"xQUERY_TYPES",
6289	"xTEXTURE_GRADIENT_SAMPLING",
6290	"rMAX_POINT_SIZE",
6291	"xMAX_SHADER_TEXTURES",
6292	"xMAX_TEXTURE_WIDTH",
6293	"xMAX_TEXTURE_HEIGHT",
6294	"xMAX_VOLUME_EXTENT",
6295	"xMAX_TEXTURE_REPEAT",
6296	"xMAX_TEXTURE_ASPECT_RATIO",
6297	"xMAX_TEXTURE_ANISOTROPY",
6298	"xMAX_PRIMITIVE_COUNT",
6299	"xMAX_VERTEX_INDEX",
6300	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6301	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6302	"xMAX_VERTEX_SHADER_TEMPS",
6303	"xMAX_FRAGMENT_SHADER_TEMPS",
6304	"xTEXTURE_OPS",
6305	"xSURFACEFMT_X8R8G8B8",
6306	"xSURFACEFMT_A8R8G8B8",
6307	"xSURFACEFMT_A2R10G10B10",
6308	"xSURFACEFMT_X1R5G5B5",
6309	"xSURFACEFMT_A1R5G5B5",
6310	"xSURFACEFMT_A4R4G4B4",
6311	"xSURFACEFMT_R5G6B5",
6312	"xSURFACEFMT_LUMINANCE16",
6313	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6314	"xSURFACEFMT_ALPHA8",
6315	"xSURFACEFMT_LUMINANCE8",
6316	"xSURFACEFMT_Z_D16",
6317	"xSURFACEFMT_Z_D24S8",
6318	"xSURFACEFMT_Z_D24X8",
6319	"xSURFACEFMT_DXT1",
6320	"xSURFACEFMT_DXT2",
6321	"xSURFACEFMT_DXT3",
6322	"xSURFACEFMT_DXT4",
6323	"xSURFACEFMT_DXT5",
6324	"xSURFACEFMT_BUMPX8L8V8U8",
6325	"xSURFACEFMT_A2W10V10U10",
6326	"xSURFACEFMT_BUMPU8V8",
6327	"xSURFACEFMT_Q8W8V8U8",
6328	"xSURFACEFMT_CxV8U8",
6329	"xSURFACEFMT_R_S10E5",
6330	"xSURFACEFMT_R_S23E8",
6331	"xSURFACEFMT_RG_S10E5",
6332	"xSURFACEFMT_RG_S23E8",
6333	"xSURFACEFMT_ARGB_S10E5",
6334	"xSURFACEFMT_ARGB_S23E8",
6335	"xMISSING62",
6336	"xMAX_VERTEX_SHADER_TEXTURES",
6337	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6338	"xSURFACEFMT_V16U16",
6339	"xSURFACEFMT_G16R16",
6340	"xSURFACEFMT_A16B16G16R16",
6341	"xSURFACEFMT_UYVY",
6342	"xSURFACEFMT_YUY2",
6343	"xMULTISAMPLE_NONMASKABLESAMPLES",
6344	"xMULTISAMPLE_MASKABLESAMPLES",
6345	"xALPHATOCOVERAGE",
6346	"xSUPERSAMPLE",
6347	"xAUTOGENMIPMAPS",
6348	"xSURFACEFMT_NV12",
6349	"xSURFACEFMT_AYUV",
6350	"xMAX_CONTEXT_IDS",
6351	"xMAX_SURFACE_IDS",
6352	"xSURFACEFMT_Z_DF16",
6353	"xSURFACEFMT_Z_DF24",
6354	"xSURFACEFMT_Z_D24S8_INT",
6355	"xSURFACEFMT_BC4_UNORM",
6356	"xSURFACEFMT_BC5_UNORM", /* 83 */
6357	};
6358
6359	/**
6360	* Initializes the host 3D capabilities in FIFO.
6361	*
6362	* @returns VBox status code.
6363	* @param pThis The shared VGA/VMSVGA instance data.
6364	* @param pThisCC The VGA/VMSVGA state for ring-3.
6365	*/
6366	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6367	{
6368	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6369	bool fSavedBuffering = RTLogRelSetBuffering(true);
6370	SVGA3dCapsRecord *pCaps;
6371	SVGA3dCapPair *pData;
6372	uint32_t idxCap = 0;
6373
6374	/* 3d hardware version; latest and greatest */
6375	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6376	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6377
6378	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6379	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6380	pData = (SVGA3dCapPair *)&pCaps->data;
6381
6382	/* Fill out all 3d capabilities. */
6383	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6384	{
6385	uint32_t val = 0;
6386
6387	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6388	if (RT_SUCCESS(rc))
6389	{
6390	pData[idxCap][0] = i;
6391	pData[idxCap][1] = val;
6392	idxCap++;
6393	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6394	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6395	else
6396	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6397	&g_apszVmSvgaDevCapNames[i][1]));
6398	}
6399	else
6400	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6401	}
6402	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6403	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6404
6405	/* Mark end of record array. */
6406	pCaps->header.length = 0;
6407
6408	RTLogRelSetBuffering(fSavedBuffering);
6409	}
6410
6411	# endif
6412
6413	/**
6414	* Resets the SVGA hardware state
6415	*
6416	* @returns VBox status code.
6417	* @param pDevIns The device instance.
6418	*/
6419	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6420	{
6421	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6422	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6423	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6424
6425	/* Reset before init? */
6426	if (!pSVGAState)
6427	return VINF_SUCCESS;
6428
6429	Log(("vmsvgaR3Reset\n"));
6430
6431	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6432	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6433	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6434
6435	/* Reset other stuff. */
6436	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6437	RT_ZERO(pThis->svga.au32ScratchRegion);
6438
6439	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6440	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6441
6442	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6443
6444	/* Initialize FIFO and register capabilities. */
6445	vmsvgaR3InitCaps(pThis, pThisCC);
6446
6447	# ifdef VBOX_WITH_VMSVGA3D
6448	if (pThis->svga.f3DEnabled)
6449	vmsvgaR3InitFifo3DCaps(pThisCC);
6450	# endif
6451
6452	/* VRAM tracking is enabled by default during bootup. */
6453	pThis->svga.fVRAMTracking = true;
6454	pThis->svga.fEnabled = false;
6455
6456	/* Invalidate current settings. */
6457	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6458	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6459	pThis->svga.uBpp = pThis->svga.uHostBpp;
6460	pThis->svga.cbScanline = 0;
6461	pThis->svga.u32PitchLock = 0;
6462
6463	return rc;
6464	}
6465
6466	/**
6467	* Cleans up the SVGA hardware state
6468	*
6469	* @returns VBox status code.
6470	* @param pDevIns The device instance.
6471	*/
6472	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6473	{
6474	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6475	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6476
6477	/*
6478	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6479	*/
6480	if (pThisCC->svga.pFIFOIOThread)
6481	{
6482	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6483	NULL /pvParam/, 30000 /ms/);
6484	AssertLogRelRC(rc);
6485
6486	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6487	AssertLogRelRC(rc);
6488	pThisCC->svga.pFIFOIOThread = NULL;
6489	}
6490
6491	/*
6492	* Destroy the special SVGA state.
6493	*/
6494	if (pThisCC->svga.pSvgaR3State)
6495	{
6496	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6497
6498	RTMemFree(pThisCC->svga.pSvgaR3State);
6499	pThisCC->svga.pSvgaR3State = NULL;
6500	}
6501
6502	/*
6503	* Free our resources residing in the VGA state.
6504	*/
6505	if (pThisCC->svga.pbVgaFrameBufferR3)
6506	{
6507	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6508	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6509	}
6510	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6511	{
6512	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6513	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6514	}
6515	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6516	{
6517	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6518	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6519	}
6520
6521	return VINF_SUCCESS;
6522	}
6523
6524	/**
6525	* Initialize the SVGA hardware state
6526	*
6527	* @returns VBox status code.
6528	* @param pDevIns The device instance.
6529	*/
6530	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6531	{
6532	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6533	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6534	PVMSVGAR3STATE pSVGAState;
6535	int rc;
6536
6537	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6538	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6539
6540	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6541
6542	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6543	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6544	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6545
6546	/* Create event semaphore. */
6547	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6548	AssertRCReturn(rc, rc);
6549
6550	/* Create event semaphore. */
6551	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6552	AssertRCReturn(rc, rc);
6553
6554	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6555	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6556
6557	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6558	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6559
6560	pSVGAState = pThisCC->svga.pSvgaR3State;
6561
6562	/* Initialize FIFO and register capabilities. */
6563	vmsvgaR3InitCaps(pThis, pThisCC);
6564
6565	# ifdef VBOX_WITH_VMSVGA3D
6566	if (pThis->svga.f3DEnabled)
6567	{
6568	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6569	if (RT_FAILURE(rc))
6570	{
6571	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6572	pThis->svga.f3DEnabled = false;
6573	}
6574	}
6575	# endif
6576	/* VRAM tracking is enabled by default during bootup. */
6577	pThis->svga.fVRAMTracking = true;
6578
6579	/* Set up the host bpp. This value is as a default for the programmable
6580	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6581	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6582	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6583	*
6584	* NB: The driver cBits value is currently constant for the lifetime of the
6585	* VM. If that changes, the host bpp logic might need revisiting.
6586	*/
6587	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6588
6589	/* Invalidate current settings. */
6590	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6591	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6592	pThis->svga.uBpp = pThis->svga.uHostBpp;
6593	pThis->svga.cbScanline = 0;
6594
6595	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6596	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6597	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6598	{
6599	pThis->svga.u32MaxWidth -= 256;
6600	pThis->svga.u32MaxHeight -= 256;
6601	}
6602	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6603
6604	# ifdef DEBUG_GMR_ACCESS
6605	/* Register the GMR access handler type. */
6606	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6607	vmsvgaR3GmrAccessHandler,
6608	NULL, NULL, NULL,
6609	NULL, NULL, NULL,
6610	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6611	AssertRCReturn(rc, rc);
6612	# endif
6613
6614	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6615	/* Register the FIFO access handler type. In addition to
6616	debugging FIFO access, this is also used to facilitate
6617	extended fifo thread sleeps. */
6618	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6619	# ifdef DEBUG_FIFO_ACCESS
6620	PGMPHYSHANDLERKIND_ALL,
6621	# else
6622	PGMPHYSHANDLERKIND_WRITE,
6623	# endif
6624	vmsvgaR3FifoAccessHandler,
6625	NULL, NULL, NULL,
6626	NULL, NULL, NULL,
6627	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6628	AssertRCReturn(rc, rc);
6629	# endif
6630
6631	/* Create the async IO thread. */
6632	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6633	RTTHREADTYPE_IO, "VMSVGA FIFO");
6634	if (RT_FAILURE(rc))
6635	{
6636	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6637	return rc;
6638	}
6639
6640	/*
6641	* Statistics.
6642	*/
6643	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6644	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6645	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6646	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6647	# ifdef VBOX_WITH_STATISTICS
6648	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6649	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6650	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6651	# endif
6652	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6653	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6654	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6655	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6656	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6657	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6658	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6659	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6660	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6661	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6662	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6663	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6664	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6665	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6666	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6667	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6668	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6669	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6670	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6671	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6672	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6673	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6674	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6675	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6676	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6677	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6678	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6679	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6680	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6681	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6682	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6683	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6684	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6685	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6686	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6687	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6688	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6689	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6690	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6691	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6692	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6693	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6694	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6695	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6696	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6697	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6698	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6699	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6700	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6701	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6702	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6703	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6704	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6705	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6706	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6707	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6708	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6709	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6710	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6711
6712	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6713	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6714	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6715	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6716	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6717	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6718	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6719	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6720	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6721	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6722	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6723	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6724	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6725	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6726	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6727	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6728	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6729	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6730	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6731	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6732	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6733	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6734	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6735	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6736	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6737	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6738	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6739	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6740	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6741	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6742	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6743	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6744	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6745	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6746	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6747
6748	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6749	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6750	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6751	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6752	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6753	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6754	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6755	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6756	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6757	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6758	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6759	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6760	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6761	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6762	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6763	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6764	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6765	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6766	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6767	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6768	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6769	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6770	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6771	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6772	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6773	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6774	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6775	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6776	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6777	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6778	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6779	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6780	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6781	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6782	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6783	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6784	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6785	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6786	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6787	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6788	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6789	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6790	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6791	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6792	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6793	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6794	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6795	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6796	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6797	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6798	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6799	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6800
6801	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6802	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6803	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6804	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6805	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6806	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6807	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6808	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6809	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6810	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6811	# endif
6812	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6813	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6814	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6815	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6816	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6817
6818	# undef REG_CNT
6819	# undef REG_PRF
6820
6821	/*
6822	* Info handlers.
6823	*/
6824	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6825	# ifdef VBOX_WITH_VMSVGA3D
6826	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6827	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6828	"VMSVGA 3d surface details. "
6829	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6830	vmsvgaR3Info3dSurface);
6831	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6832	"VMSVGA 3d surface details and bitmap: "
6833	"sid[>dir]",
6834	vmsvgaR3Info3dSurfaceBmp);
6835	# endif
6836
6837	return VINF_SUCCESS;
6838	}
6839
6840	/**
6841	* Power On notification.
6842	*
6843	* @returns VBox status code.
6844	* @param pDevIns The device instance data.
6845	*
6846	* @remarks Caller enters the device critical section.
6847	*/
6848	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6849	{
6850	# ifdef VBOX_WITH_VMSVGA3D
6851	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6852	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6853	if (pThis->svga.f3DEnabled)
6854	{
6855	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6856
6857	if (RT_SUCCESS(rc))
6858	{
6859	/* Initialize FIFO 3D capabilities. */
6860	vmsvgaR3InitFifo3DCaps(pThisCC);
6861	}
6862	}
6863	# else /* !VBOX_WITH_VMSVGA3D */
6864	RT_NOREF(pDevIns);
6865	# endif /* !VBOX_WITH_VMSVGA3D */
6866	}
6867
6868	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 84722

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