DevVGA-SVGA.cpp@ 84754

Last change on this file since 84754 was 84754, checked in by vboxsync, 5 years ago
Devices/Graphics: fixed regression after r138536 (crash on startup with 3D disabled)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
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1	/* $Id: DevVGA-SVGA.cpp 84754 2020-06-10 12:09:27Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.virtualbox.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#define VMSVGA_USE_EMT_HALT_CODE
133	#include <VBox/vmm/pdmdev.h>
134	#include <VBox/version.h>
135	#include <VBox/err.h>
136	#include <VBox/log.h>
137	#include <VBox/vmm/pgm.h>
138	#ifdef VMSVGA_USE_EMT_HALT_CODE
139	# include <VBox/vmm/vmapi.h>
140	# include <VBox/vmm/vmcpuset.h>
141	#endif
142	#include <VBox/sup.h>
143
144	#include <iprt/assert.h>
145	#include <iprt/semaphore.h>
146	#include <iprt/uuid.h>
147	#ifdef IN_RING3
148	# include <iprt/ctype.h>
149	# include <iprt/mem.h>
150	# ifdef VBOX_STRICT
151	# include <iprt/time.h>
152	# endif
153	#endif
154
155	#include <VBox/AssertGuest.h>
156	#include <VBox/VMMDev.h>
157	#include <VBoxVideo.h>
158	#include <VBox/bioslogo.h>
159
160	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
161	#include "DevVGA.h"
162
163	#include "DevVGA-SVGA.h"
164	#include "vmsvga/svga_escape.h"
165	#include "vmsvga/svga_overlay.h"
166	#include "vmsvga/svga3d_caps.h"
167	#ifdef VBOX_WITH_VMSVGA3D
168	# include "DevVGA-SVGA3d.h"
169	# ifdef RT_OS_DARWIN
170	# include "DevVGA-SVGA3d-cocoa.h"
171	# endif
172	# ifdef RT_OS_LINUX
173	# ifdef IN_RING3
174	#include "DevVGA-SVGA3d-glLdr.h"
175	# endif
176	# endif
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Defined Constants And Macros *
182	*********************************************************************************************************************************/
183	/**
184	* Macro for checking if a fixed FIFO register is valid according to the
185	* current FIFO configuration.
186	*
187	* @returns true / false.
188	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
189	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
190	*/
191	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
192
193
194	/*********************************************************************************************************************************
195	* Structures and Typedefs *
196	*********************************************************************************************************************************/
197	/**
198	* 64-bit GMR descriptor.
199	*/
200	typedef struct
201	{
202	RTGCPHYS GCPhys;
203	uint64_t numPages;
204	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
205
206	/**
207	* GMR slot
208	*/
209	typedef struct
210	{
211	uint32_t cMaxPages;
212	uint32_t cbTotal;
213	uint32_t numDescriptors;
214	PVMSVGAGMRDESCRIPTOR paDesc;
215	} GMR, *PGMR;
216
217	#ifdef IN_RING3
218	/**
219	* Internal SVGA ring-3 only state.
220	*/
221	typedef struct VMSVGAR3STATE
222	{
223	GMR *paGMR; // [VMSVGAState::cGMR]
224	struct
225	{
226	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
227	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
228	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
229	} GMRFB;
230	struct
231	{
232	bool fActive;
233	uint32_t xHotspot;
234	uint32_t yHotspot;
235	uint32_t width;
236	uint32_t height;
237	uint32_t cbData;
238	void *pData;
239	} Cursor;
240	SVGAColorBGRX colorAnnotation;
241
242	# ifdef VMSVGA_USE_EMT_HALT_CODE
243	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
244	uint32_t volatile cBusyDelayedEmts;
245	/** Set of EMTs that are */
246	VMCPUSET BusyDelayedEmts;
247	# else
248	/** Number of EMTs waiting on hBusyDelayedEmts. */
249	uint32_t volatile cBusyDelayedEmts;
250	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
251	* busy (ugly). */
252	RTSEMEVENTMULTI hBusyDelayedEmts;
253	# endif
254
255	/** Information obout screens. */
256	VMSVGASCREENOBJECT aScreens[64];
257
258	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
259	STAMPROFILE StatBusyDelayEmts;
260
261	STAMPROFILE StatR3Cmd3dPresentProf;
262	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
263	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
264	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
265	STAMCOUNTER StatR3CmdDefineGmr2;
266	STAMCOUNTER StatR3CmdDefineGmr2Free;
267	STAMCOUNTER StatR3CmdDefineGmr2Modify;
268	STAMCOUNTER StatR3CmdRemapGmr2;
269	STAMCOUNTER StatR3CmdRemapGmr2Modify;
270	STAMCOUNTER StatR3CmdInvalidCmd;
271	STAMCOUNTER StatR3CmdFence;
272	STAMCOUNTER StatR3CmdUpdate;
273	STAMCOUNTER StatR3CmdUpdateVerbose;
274	STAMCOUNTER StatR3CmdDefineCursor;
275	STAMCOUNTER StatR3CmdDefineAlphaCursor;
276	STAMCOUNTER StatR3CmdMoveCursor;
277	STAMCOUNTER StatR3CmdDisplayCursor;
278	STAMCOUNTER StatR3CmdRectFill;
279	STAMCOUNTER StatR3CmdRectCopy;
280	STAMCOUNTER StatR3CmdRectRopCopy;
281	STAMCOUNTER StatR3CmdEscape;
282	STAMCOUNTER StatR3CmdDefineScreen;
283	STAMCOUNTER StatR3CmdDestroyScreen;
284	STAMCOUNTER StatR3CmdDefineGmrFb;
285	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
286	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
287	STAMCOUNTER StatR3CmdAnnotationFill;
288	STAMCOUNTER StatR3CmdAnnotationCopy;
289	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
290	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
291	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
292	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
293	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
294	STAMCOUNTER StatR3Cmd3dSurfaceDma;
295	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
296	STAMCOUNTER StatR3Cmd3dContextDefine;
297	STAMCOUNTER StatR3Cmd3dContextDestroy;
298	STAMCOUNTER StatR3Cmd3dSetTransform;
299	STAMCOUNTER StatR3Cmd3dSetZRange;
300	STAMCOUNTER StatR3Cmd3dSetRenderState;
301	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
302	STAMCOUNTER StatR3Cmd3dSetTextureState;
303	STAMCOUNTER StatR3Cmd3dSetMaterial;
304	STAMCOUNTER StatR3Cmd3dSetLightData;
305	STAMCOUNTER StatR3Cmd3dSetLightEnable;
306	STAMCOUNTER StatR3Cmd3dSetViewPort;
307	STAMCOUNTER StatR3Cmd3dSetClipPlane;
308	STAMCOUNTER StatR3Cmd3dClear;
309	STAMCOUNTER StatR3Cmd3dPresent;
310	STAMCOUNTER StatR3Cmd3dPresentReadBack;
311	STAMCOUNTER StatR3Cmd3dShaderDefine;
312	STAMCOUNTER StatR3Cmd3dShaderDestroy;
313	STAMCOUNTER StatR3Cmd3dSetShader;
314	STAMCOUNTER StatR3Cmd3dSetShaderConst;
315	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
316	STAMCOUNTER StatR3Cmd3dSetScissorRect;
317	STAMCOUNTER StatR3Cmd3dBeginQuery;
318	STAMCOUNTER StatR3Cmd3dEndQuery;
319	STAMCOUNTER StatR3Cmd3dWaitForQuery;
320	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
321	STAMCOUNTER StatR3Cmd3dActivateSurface;
322	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
323
324	STAMCOUNTER StatR3RegConfigDoneWr;
325	STAMCOUNTER StatR3RegGmrDescriptorWr;
326	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
327	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
328
329	STAMCOUNTER StatFifoCommands;
330	STAMCOUNTER StatFifoErrors;
331	STAMCOUNTER StatFifoUnkCmds;
332	STAMCOUNTER StatFifoTodoTimeout;
333	STAMCOUNTER StatFifoTodoWoken;
334	STAMPROFILE StatFifoStalls;
335	STAMPROFILE StatFifoExtendedSleep;
336	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
337	STAMCOUNTER StatFifoAccessHandler;
338	# endif
339	STAMCOUNTER StatFifoCursorFetchAgain;
340	STAMCOUNTER StatFifoCursorNoChange;
341	STAMCOUNTER StatFifoCursorPosition;
342	STAMCOUNTER StatFifoCursorVisiblity;
343	STAMCOUNTER StatFifoWatchdogWakeUps;
344	} VMSVGAR3STATE, *PVMSVGAR3STATE;
345	#endif /* IN_RING3 */
346
347
348	/*********************************************************************************************************************************
349	* Internal Functions *
350	*********************************************************************************************************************************/
351	#ifdef IN_RING3
352	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
353	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
354	# endif
355	# ifdef DEBUG_GMR_ACCESS
356	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
357	# endif
358	#endif
359
360
361	/*********************************************************************************************************************************
362	* Global Variables *
363	*********************************************************************************************************************************/
364	#ifdef IN_RING3
365
366	/**
367	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
368	*/
369	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
370	{
371	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
372	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
373	SSMFIELD_ENTRY_TERM()
374	};
375
376	/**
377	* SSM descriptor table for the GMR structure.
378	*/
379	static SSMFIELD const g_aGMRFields[] =
380	{
381	SSMFIELD_ENTRY( GMR, cMaxPages),
382	SSMFIELD_ENTRY( GMR, cbTotal),
383	SSMFIELD_ENTRY( GMR, numDescriptors),
384	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
385	SSMFIELD_ENTRY_TERM()
386	};
387
388	/**
389	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
390	*/
391	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
392	{
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
395	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
396	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
397	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
398	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
399	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
400	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
401	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
402	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
403	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
404	SSMFIELD_ENTRY_TERM()
405	};
406
407	/**
408	* SSM descriptor table for the VMSVGAR3STATE structure.
409	*/
410	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
411	{
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
413	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
414	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
415	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
416	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
417	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
418	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
419	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
420	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
421	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
423	#ifdef VMSVGA_USE_EMT_HALT_CODE
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
425	#else
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
427	#endif
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
491
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
496
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
501	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
504	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
505	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
506	# endif
507	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
508	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
511
512	SSMFIELD_ENTRY_TERM()
513	};
514
515	/**
516	* SSM descriptor table for the VGAState.svga structure.
517	*/
518	static SSMFIELD const g_aVGAStateSVGAFields[] =
519	{
520	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
523	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
524	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
525	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
526	SSMFIELD_ENTRY( VMSVGAState, fBusy),
527	SSMFIELD_ENTRY( VMSVGAState, fTraces),
528	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
529	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
530	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
531	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
532	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
533	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
534	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
535	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
536	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
538	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
540	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
541	SSMFIELD_ENTRY( VMSVGAState, uWidth),
542	SSMFIELD_ENTRY( VMSVGAState, uHeight),
543	SSMFIELD_ENTRY( VMSVGAState, uBpp),
544	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
545	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
546	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
547	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
548	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
549	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
550	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
551	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
552	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
553	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
554	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
555	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
556	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
557	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
558	SSMFIELD_ENTRY_TERM()
559	};
560	#endif /* IN_RING3 */
561
562
563	/*********************************************************************************************************************************
564	* Internal Functions *
565	*********************************************************************************************************************************/
566	#ifdef IN_RING3
567	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
568	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
569	uint32_t uVersion, uint32_t uPass);
570	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
571	# ifdef VBOX_WITH_VMSVGA3D
572	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
573	# endif /* VBOX_WITH_VMSVGA3D */
574	#endif /* IN_RING3 */
575
576
577
578	#ifdef IN_RING3
579	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
580	{
581	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
582	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
583	&& pSVGAState
584	&& pSVGAState->aScreens[idScreen].fDefined)
585	{
586	return &pSVGAState->aScreens[idScreen];
587	}
588	return NULL;
589	}
590
591	void vmsvgaR3ResetScreens(PVGASTATECC pThisCC)
592	{
593	# ifdef VBOX_WITH_VMSVGA3D
594	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
595	{
596	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
597	if (pScreen)
598	vmsvga3dDestroyScreen(pThisCC, pScreen);
599	}
600	# else
601	RT_NOREF(pThisCC);
602	# endif
603	}
604	#endif /* IN_RING3 */
605
606	#ifdef LOG_ENABLED
607
608	/**
609	* Index register string name lookup
610	*
611	* @returns Index register string or "UNKNOWN"
612	* @param pThis The shared VGA/VMSVGA state.
613	* @param idxReg The index register.
614	*/
615	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
616	{
617	switch (idxReg)
618	{
619	case SVGA_REG_ID: return "SVGA_REG_ID";
620	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
621	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
622	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
623	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
624	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
625	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
626	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
627	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
628	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
629	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
630	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
631	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
632	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
633	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
634	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
635	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
636	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
637	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
638	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
639	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
640	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
641	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
642	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
643	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
644	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
645	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
646	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
647	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
648	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
649	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
650	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
651	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
652	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
653	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
654	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
655	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
656	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
657	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
658	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
659	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
660	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
661	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
662	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
663	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
664	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
665	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
666	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
667	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
668	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
669
670	default:
671	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
672	return "SVGA_SCRATCH_BASE reg";
673	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
674	return "SVGA_PALETTE_BASE reg";
675	return "UNKNOWN";
676	}
677	}
678
679	#ifdef IN_RING3
680	/**
681	* FIFO command name lookup
682	*
683	* @returns FIFO command string or "UNKNOWN"
684	* @param u32Cmd FIFO command
685	*/
686	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
687	{
688	switch (u32Cmd)
689	{
690	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
691	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
692	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
693	case SVGA_CMD_RECT_ROP_COPY: return "SVGA_CMD_RECT_ROP_COPY";
694	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
695	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
696	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
697	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
698	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
699	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
700	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
701	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
702	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
703	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
704	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
705	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
706	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
707	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
708	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
709	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
710	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
711	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
712	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
713	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
714	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
715	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
716	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
717	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
718	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
719	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
720	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
721	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
722	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
723	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
724	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
725	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
726	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
727	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
728	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
729	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
730	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
731	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
732	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
733	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
734	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
735	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
736	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
737	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
738	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
739	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
740	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
741	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
742	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
743	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
744	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
745	default: return "UNKNOWN";
746	}
747	}
748	# endif /* IN_RING3 */
749
750	#endif /* LOG_ENABLED */
751	#ifdef IN_RING3
752
753	/**
754	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
755	*/
756	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
757	{
758	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
759	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
760
761	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
762	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
763
764	/** @todo Test how it interacts with multiple screen objects. */
765	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
766	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
767	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
768
769	if (x < uWidth)
770	{
771	pThis->svga.viewport.x = x;
772	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
773	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
774	}
775	else
776	{
777	pThis->svga.viewport.x = uWidth;
778	pThis->svga.viewport.cx = 0;
779	pThis->svga.viewport.xRight = uWidth;
780	}
781	if (y < uHeight)
782	{
783	pThis->svga.viewport.y = y;
784	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
785	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
786	pThis->svga.viewport.yHighWC = uHeight - y;
787	}
788	else
789	{
790	pThis->svga.viewport.y = uHeight;
791	pThis->svga.viewport.cy = 0;
792	pThis->svga.viewport.yLowWC = 0;
793	pThis->svga.viewport.yHighWC = 0;
794	}
795
796	# ifdef VBOX_WITH_VMSVGA3D
797	/*
798	* Now inform the 3D backend.
799	*/
800	if (pThis->svga.f3DEnabled)
801	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
802	# else
803	RT_NOREF(OldViewport);
804	# endif
805	}
806
807
808	/**
809	* Updating screen information in API
810	*
811	* @param pThis The The shared VGA/VMSVGA instance data.
812	* @param pThisCC The VGA/VMSVGA state for ring-3.
813	*/
814	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
815	{
816	int rc;
817
818	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
819
820	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
821	{
822	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
823	if (!pScreen->fModified)
824	continue;
825
826	pScreen->fModified = false;
827
828	VBVAINFOVIEW view;
829	RT_ZERO(view);
830	view.u32ViewIndex = pScreen->idScreen;
831	// view.u32ViewOffset = 0;
832	view.u32ViewSize = pThis->vram_size;
833	view.u32MaxScreenSize = pThis->vram_size;
834
835	VBVAINFOSCREEN screen;
836	RT_ZERO(screen);
837	screen.u32ViewIndex = pScreen->idScreen;
838
839	if (pScreen->fDefined)
840	{
841	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
842	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
843	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
844	{
845	Assert(pThis->svga.fGFBRegisters);
846	continue;
847	}
848
849	screen.i32OriginX = pScreen->xOrigin;
850	screen.i32OriginY = pScreen->yOrigin;
851	screen.u32StartOffset = pScreen->offVRAM;
852	screen.u32LineSize = pScreen->cbPitch;
853	screen.u32Width = pScreen->cWidth;
854	screen.u32Height = pScreen->cHeight;
855	screen.u16BitsPerPixel = pScreen->cBpp;
856	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
857	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
858	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
859	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
860	}
861	else
862	{
863	/* Screen is destroyed. */
864	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
865	}
866
867	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
868	AssertRC(rc);
869	}
870	}
871
872
873	/**
874	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
875	*
876	* Used to update screen offsets (positions) since appearently vmwgfx fails to
877	* pass correct offsets thru FIFO.
878	*/
879	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
880	{
881	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
882	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
883	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
884
885	AssertReturnVoid(pSVGAState);
886
887	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
888	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
889	for (uint32_t i = 0; i < cPositions; ++i)
890	{
891	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
892	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
893	continue;
894
895	if (pSVGAState->aScreens[i].xOrigin == -1)
896	continue;
897	if (pSVGAState->aScreens[i].yOrigin == -1)
898	continue;
899
900	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
901	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
902	pSVGAState->aScreens[i].fModified = true;
903	}
904
905	vmsvgaR3VBVAResize(pThis, pThisCC);
906	}
907
908	#endif /* IN_RING3 */
909
910	/**
911	* Read port register
912	*
913	* @returns VBox status code.
914	* @param pDevIns The device instance.
915	* @param pThis The shared VGA/VMSVGA state.
916	* @param pu32 Where to store the read value
917	*/
918	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
919	{
920	#ifdef IN_RING3
921	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
922	#endif
923	int rc = VINF_SUCCESS;
924	*pu32 = 0;
925
926	/* Rough index register validation. */
927	uint32_t idxReg = pThis->svga.u32IndexReg;
928	#if !defined(IN_RING3) && defined(VBOX_STRICT)
929	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
930	VINF_IOM_R3_IOPORT_READ);
931	#else
932	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
933	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
934	VINF_SUCCESS);
935	#endif
936	RT_UNTRUSTED_VALIDATED_FENCE();
937
938	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
939	if ( idxReg >= SVGA_REG_CAPABILITIES
940	&& pThis->svga.u32SVGAId == SVGA_ID_0)
941	{
942	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
943	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
944	}
945
946	switch (idxReg)
947	{
948	case SVGA_REG_ID:
949	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
950	*pu32 = pThis->svga.u32SVGAId;
951	break;
952
953	case SVGA_REG_ENABLE:
954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
955	*pu32 = pThis->svga.fEnabled;
956	break;
957
958	case SVGA_REG_WIDTH:
959	{
960	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
961	if ( pThis->svga.fEnabled
962	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
963	*pu32 = pThis->svga.uWidth;
964	else
965	{
966	#ifndef IN_RING3
967	rc = VINF_IOM_R3_IOPORT_READ;
968	#else
969	*pu32 = pThisCC->pDrv->cx;
970	#endif
971	}
972	break;
973	}
974
975	case SVGA_REG_HEIGHT:
976	{
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
978	if ( pThis->svga.fEnabled
979	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
980	*pu32 = pThis->svga.uHeight;
981	else
982	{
983	#ifndef IN_RING3
984	rc = VINF_IOM_R3_IOPORT_READ;
985	#else
986	*pu32 = pThisCC->pDrv->cy;
987	#endif
988	}
989	break;
990	}
991
992	case SVGA_REG_MAX_WIDTH:
993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
994	*pu32 = pThis->svga.u32MaxWidth;
995	break;
996
997	case SVGA_REG_MAX_HEIGHT:
998	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
999	*pu32 = pThis->svga.u32MaxHeight;
1000	break;
1001
1002	case SVGA_REG_DEPTH:
1003	/* This returns the color depth of the current mode. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1005	switch (pThis->svga.uBpp)
1006	{
1007	case 15:
1008	case 16:
1009	case 24:
1010	*pu32 = pThis->svga.uBpp;
1011	break;
1012
1013	default:
1014	case 32:
1015	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1016	break;
1017	}
1018	break;
1019
1020	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1022	*pu32 = pThis->svga.uHostBpp;
1023	break;
1024
1025	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1026	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1027	*pu32 = pThis->svga.uBpp;
1028	break;
1029
1030	case SVGA_REG_PSEUDOCOLOR:
1031	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1032	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1033	break;
1034
1035	case SVGA_REG_RED_MASK:
1036	case SVGA_REG_GREEN_MASK:
1037	case SVGA_REG_BLUE_MASK:
1038	{
1039	uint32_t uBpp;
1040
1041	if (pThis->svga.fEnabled)
1042	uBpp = pThis->svga.uBpp;
1043	else
1044	uBpp = pThis->svga.uHostBpp;
1045
1046	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1047	switch (uBpp)
1048	{
1049	case 8:
1050	u32RedMask = 0x07;
1051	u32GreenMask = 0x38;
1052	u32BlueMask = 0xc0;
1053	break;
1054
1055	case 15:
1056	u32RedMask = 0x0000001f;
1057	u32GreenMask = 0x000003e0;
1058	u32BlueMask = 0x00007c00;
1059	break;
1060
1061	case 16:
1062	u32RedMask = 0x0000001f;
1063	u32GreenMask = 0x000007e0;
1064	u32BlueMask = 0x0000f800;
1065	break;
1066
1067	case 24:
1068	case 32:
1069	default:
1070	u32RedMask = 0x00ff0000;
1071	u32GreenMask = 0x0000ff00;
1072	u32BlueMask = 0x000000ff;
1073	break;
1074	}
1075	switch (idxReg)
1076	{
1077	case SVGA_REG_RED_MASK:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1079	*pu32 = u32RedMask;
1080	break;
1081
1082	case SVGA_REG_GREEN_MASK:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1084	*pu32 = u32GreenMask;
1085	break;
1086
1087	case SVGA_REG_BLUE_MASK:
1088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1089	*pu32 = u32BlueMask;
1090	break;
1091	}
1092	break;
1093	}
1094
1095	case SVGA_REG_BYTES_PER_LINE:
1096	{
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1098	if ( pThis->svga.fEnabled
1099	&& pThis->svga.cbScanline)
1100	*pu32 = pThis->svga.cbScanline;
1101	else
1102	{
1103	#ifndef IN_RING3
1104	rc = VINF_IOM_R3_IOPORT_READ;
1105	#else
1106	*pu32 = pThisCC->pDrv->cbScanline;
1107	#endif
1108	}
1109	break;
1110	}
1111
1112	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1114	*pu32 = pThis->vram_size;
1115	break;
1116
1117	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1119	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1120	*pu32 = pThis->GCPhysVRAM;
1121	break;
1122
1123	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1125	/* Always zero in our case. */
1126	*pu32 = 0;
1127	break;
1128
1129	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1130	{
1131	#ifndef IN_RING3
1132	rc = VINF_IOM_R3_IOPORT_READ;
1133	#else
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1135
1136	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1137	if ( pThis->svga.fEnabled
1138	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1139	{
1140	/* Hardware enabled; return real framebuffer size .*/
1141	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1142	}
1143	else
1144	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1145
1146	pu32 = RT_MIN(pThis->vram_size, pu32);
1147	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1148	#endif
1149	break;
1150	}
1151
1152	case SVGA_REG_CAPABILITIES:
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1154	*pu32 = pThis->svga.u32RegCaps;
1155	break;
1156
1157	case SVGA_REG_MEM_START: /* FIFO start */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1159	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1160	*pu32 = pThis->svga.GCPhysFIFO;
1161	break;
1162
1163	case SVGA_REG_MEM_SIZE: /* FIFO size */
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1165	*pu32 = pThis->svga.cbFIFO;
1166	break;
1167
1168	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1170	*pu32 = pThis->svga.fConfigured;
1171	break;
1172
1173	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1174	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1175	*pu32 = 0;
1176	break;
1177
1178	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1180	if (pThis->svga.fBusy)
1181	{
1182	#ifndef IN_RING3
1183	/* Go to ring-3 and halt the CPU. */
1184	rc = VINF_IOM_R3_IOPORT_READ;
1185	RT_NOREF(pDevIns);
1186	break;
1187	#else
1188	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1189	/* The guest is basically doing a HLT via the device here, but with
1190	a special wake up condition on FIFO completion. */
1191	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1192	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1193	PVM pVM = PDMDevHlpGetVM(pDevIns);
1194	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1195	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1196	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1197	if (pThis->svga.fBusy)
1198	{
1199	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1200	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1201	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1202	}
1203	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1204	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1205	# else
1206
1207	/* Delay the EMT a bit so the FIFO and others can get some work done.
1208	This used to be a crude 50 ms sleep. The current code tries to be
1209	more efficient, but the consept is still very crude. */
1210	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1211	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1212	RTThreadYield();
1213	if (pThis->svga.fBusy)
1214	{
1215	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1216
1217	if (pThis->svga.fBusy && cRefs == 1)
1218	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1219	if (pThis->svga.fBusy)
1220	{
1221	/** @todo If this code is going to stay, we need to call into the halt/wait
1222	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1223	* suffer when the guest is polling on a busy FIFO. */
1224	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1225	if (cNsMaxWait >= RT_NS_100US)
1226	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1227	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1228	RT_MIN(cNsMaxWait, RT_NS_10MS));
1229	}
1230
1231	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1232	}
1233	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1234	# endif
1235	*pu32 = pThis->svga.fBusy != 0;
1236	#endif
1237	}
1238	else
1239	*pu32 = false;
1240	break;
1241
1242	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1244	*pu32 = pThis->svga.u32GuestId;
1245	break;
1246
1247	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1249	*pu32 = pThis->svga.cScratchRegion;
1250	break;
1251
1252	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1254	*pu32 = SVGA_FIFO_NUM_REGS;
1255	break;
1256
1257	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1258	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1259	*pu32 = pThis->svga.u32PitchLock;
1260	break;
1261
1262	case SVGA_REG_IRQMASK: /* Interrupt mask */
1263	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1264	*pu32 = pThis->svga.u32IrqMask;
1265	break;
1266
1267	/* See "Guest memory regions" below. */
1268	case SVGA_REG_GMR_ID:
1269	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1270	*pu32 = pThis->svga.u32CurrentGMRId;
1271	break;
1272
1273	case SVGA_REG_GMR_DESCRIPTOR:
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1275	/* Write only */
1276	*pu32 = 0;
1277	break;
1278
1279	case SVGA_REG_GMR_MAX_IDS:
1280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1281	*pu32 = pThis->svga.cGMR;
1282	break;
1283
1284	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1286	*pu32 = VMSVGA_MAX_GMR_PAGES;
1287	break;
1288
1289	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1290	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1291	*pu32 = pThis->svga.fTraces;
1292	break;
1293
1294	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1295	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1296	*pu32 = VMSVGA_MAX_GMR_PAGES;
1297	break;
1298
1299	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1300	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1301	*pu32 = VMSVGA_SURFACE_SIZE;
1302	break;
1303
1304	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1305	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1306	break;
1307
1308	/* Mouse cursor support. */
1309	case SVGA_REG_CURSOR_ID:
1310	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1311	*pu32 = pThis->svga.uCursorID;
1312	break;
1313
1314	case SVGA_REG_CURSOR_X:
1315	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1316	*pu32 = pThis->svga.uCursorX;
1317	break;
1318
1319	case SVGA_REG_CURSOR_Y:
1320	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1321	*pu32 = pThis->svga.uCursorY;
1322	break;
1323
1324	case SVGA_REG_CURSOR_ON:
1325	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1326	*pu32 = pThis->svga.uCursorOn;
1327	break;
1328
1329	/* Legacy multi-monitor support */
1330	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1332	*pu32 = 1;
1333	break;
1334
1335	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1337	*pu32 = 0;
1338	break;
1339
1340	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1342	*pu32 = 0;
1343	break;
1344
1345	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1347	*pu32 = 0;
1348	break;
1349
1350	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1352	*pu32 = 0;
1353	break;
1354
1355	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1357	*pu32 = pThis->svga.uWidth;
1358	break;
1359
1360	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1361	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1362	*pu32 = pThis->svga.uHeight;
1363	break;
1364
1365	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1367	/* We must return something sensible here otherwise the Linux driver
1368	will take a legacy code path without 3d support. This number also
1369	limits how many screens Linux guests will allow. */
1370	*pu32 = pThis->cMonitors;
1371	break;
1372
1373	default:
1374	{
1375	uint32_t offReg;
1376	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1377	{
1378	RT_UNTRUSTED_VALIDATED_FENCE();
1379	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1381	}
1382	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1383	{
1384	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1386	RT_UNTRUSTED_VALIDATED_FENCE();
1387	uint32_t u32 = pThis->last_palette[offReg / 3];
1388	switch (offReg % 3)
1389	{
1390	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1391	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1392	case 2: pu32 = u32 & 0xff; break; / blue */
1393	}
1394	}
1395	else
1396	{
1397	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1398	rc = VINF_IOM_R3_IOPORT_READ;
1399	#else
1400	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1401
1402	/* Do not assert. The guest might be reading all registers. */
1403	LogFunc(("Unknown reg=%#x\n", idxReg));
1404	#endif
1405	}
1406	break;
1407	}
1408	}
1409	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1410	return rc;
1411	}
1412
1413	#ifdef IN_RING3
1414	/**
1415	* Apply the current resolution settings to change the video mode.
1416	*
1417	* @returns VBox status code.
1418	* @param pThis The shared VGA state.
1419	* @param pThisCC The ring-3 VGA state.
1420	*/
1421	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1422	{
1423	/* Always do changemode on FIFO thread. */
1424	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1425
1426	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1427
1428	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1429
1430	if (pThis->svga.fGFBRegisters)
1431	{
1432	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1433	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1434	* deletes all screens other than screen #0, and redefines screen
1435	* #0 according to the specified mode. Drivers that use
1436	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1437	*/
1438
1439	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1440	pScreen->fDefined = true;
1441	pScreen->fModified = true;
1442	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1443	pScreen->idScreen = 0;
1444	pScreen->xOrigin = 0;
1445	pScreen->yOrigin = 0;
1446	pScreen->offVRAM = 0;
1447	pScreen->cbPitch = pThis->svga.cbScanline;
1448	pScreen->cWidth = pThis->svga.uWidth;
1449	pScreen->cHeight = pThis->svga.uHeight;
1450	pScreen->cBpp = pThis->svga.uBpp;
1451
1452	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1453	{
1454	/* Delete screen. */
1455	pScreen = &pSVGAState->aScreens[iScreen];
1456	if (pScreen->fDefined)
1457	{
1458	pScreen->fModified = true;
1459	pScreen->fDefined = false;
1460	}
1461	}
1462	}
1463	else
1464	{
1465	/* "If Screen Objects are supported, they can be used to fully
1466	* replace the functionality provided by the framebuffer registers
1467	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1468	*/
1469	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1470	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1471	pThis->svga.uBpp = pThis->svga.uHostBpp;
1472	}
1473
1474	vmsvgaR3VBVAResize(pThis, pThisCC);
1475
1476	/* Last stuff. For the VGA device screenshot. */
1477	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1478	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1479	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1480	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1481	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1482
1483	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1484	if ( pThis->svga.viewport.cx == 0
1485	&& pThis->svga.viewport.cy == 0)
1486	{
1487	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1488	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1489	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1490	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1491	pThis->svga.viewport.yLowWC = 0;
1492	}
1493
1494	return VINF_SUCCESS;
1495	}
1496
1497	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1498	{
1499	VBVACMDHDR cmd;
1500	cmd.x = (int16_t)(pScreen->xOrigin + x);
1501	cmd.y = (int16_t)(pScreen->yOrigin + y);
1502	cmd.w = (uint16_t)w;
1503	cmd.h = (uint16_t)h;
1504
1505	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1506	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1507	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1508	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1509
1510	return VINF_SUCCESS;
1511	}
1512
1513	#endif /* IN_RING3 */
1514	#if defined(IN_RING0) \|\| defined(IN_RING3)
1515
1516	/**
1517	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1518	*
1519	* @param pThis The shared VGA/VMSVGA instance data.
1520	* @param pThisCC The VGA/VMSVGA state for the current context.
1521	* @param fState The busy state.
1522	*/
1523	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1524	{
1525	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1526
1527	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1528	{
1529	/* Race / unfortunately scheduling. Highly unlikly. */
1530	uint32_t cLoops = 64;
1531	do
1532	{
1533	ASMNopPause();
1534	fState = (pThis->svga.fBusy != 0);
1535	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1536	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1537	}
1538	}
1539
1540
1541	/**
1542	* Update the scanline pitch in response to the guest changing mode
1543	* width/bpp.
1544	*
1545	* @param pThis The shared VGA/VMSVGA state.
1546	* @param pThisCC The VGA/VMSVGA state for the current context.
1547	*/
1548	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1549	{
1550	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1551	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1552	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1553	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1554
1555	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1556	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1557	* location but it has a different meaning.
1558	*/
1559	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1560	uFifoPitchLock = 0;
1561
1562	/* Sanitize values. */
1563	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1564	uFifoPitchLock = 0;
1565	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1566	uRegPitchLock = 0;
1567
1568	/* Prefer the register value to the FIFO value.*/
1569	if (uRegPitchLock)
1570	pThis->svga.cbScanline = uRegPitchLock;
1571	else if (uFifoPitchLock)
1572	pThis->svga.cbScanline = uFifoPitchLock;
1573	else
1574	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1575
1576	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1577	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1578	}
1579
1580	#endif /* IN_RING0 \|\| IN_RING3 */
1581
1582	#ifdef IN_RING3
1583
1584	/**
1585	* Sends cursor position and visibility information from legacy
1586	* SVGA registers to the front-end.
1587	*/
1588	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1589	{
1590	/*
1591	* Writing the X/Y/ID registers does not trigger changes; only writing the
1592	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1593	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1594	* register if they don't have to.
1595	*/
1596	uint32_t x, y, idScreen;
1597	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1598
1599	x = pThis->svga.uCursorX;
1600	y = pThis->svga.uCursorY;
1601	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1602
1603	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1604	* were extended as follows:
1605	*
1606	* SVGA_CURSOR_ON_HIDE 0
1607	* SVGA_CURSOR_ON_SHOW 1
1608	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1609	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1610	*
1611	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1612	* distinguish between the non-zero values but still remember them.
1613	*/
1614	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1615	{
1616	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1617	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1618	}
1619	pThis->svga.uCursorOn = uCursorOn;
1620	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1621	}
1622
1623
1624	/**
1625	* Copy a rectangle of pixels within guest VRAM.
1626	*/
1627	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1628	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1629	{
1630	if (!width \|\| !height)
1631	return; /* Nothing to do, don't even bother. */
1632
1633	/*
1634	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1635	* corresponding to the current display mode.
1636	*/
1637	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1638	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1639	uint8_t const *pSrc;
1640	uint8_t *pDst;
1641	unsigned const cbRectWidth = width * cbPixel;
1642	unsigned uMaxOffset;
1643
1644	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1645	if (uMaxOffset >= cbFrameBuffer)
1646	{
1647	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1648	return; /* Just don't listen to a bad guest. */
1649	}
1650
1651	pSrc = pDst = pThisCC->pbVRam;
1652	pSrc += srcY * cbScanline + srcX * cbPixel;
1653	pDst += dstY * cbScanline + dstX * cbPixel;
1654
1655	if (srcY >= dstY)
1656	{
1657	/* Source below destination, copy top to bottom. */
1658	for (; height > 0; height--)
1659	{
1660	memmove(pDst, pSrc, cbRectWidth);
1661	pSrc += cbScanline;
1662	pDst += cbScanline;
1663	}
1664	}
1665	else
1666	{
1667	/* Source above destination, copy bottom to top. */
1668	pSrc += cbScanline * (height - 1);
1669	pDst += cbScanline * (height - 1);
1670	for (; height > 0; height--)
1671	{
1672	memmove(pDst, pSrc, cbRectWidth);
1673	pSrc -= cbScanline;
1674	pDst -= cbScanline;
1675	}
1676	}
1677	}
1678
1679	#endif /* IN_RING3 */
1680
1681
1682	/**
1683	* Write port register
1684	*
1685	* @returns Strict VBox status code.
1686	* @param pDevIns The device instance.
1687	* @param pThis The shared VGA/VMSVGA state.
1688	* @param pThisCC The VGA/VMSVGA state for the current context.
1689	* @param u32 Value to write
1690	*/
1691	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1692	{
1693	#ifdef IN_RING3
1694	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1695	#endif
1696	VBOXSTRICTRC rc = VINF_SUCCESS;
1697	RT_NOREF(pThisCC);
1698
1699	/* Rough index register validation. */
1700	uint32_t idxReg = pThis->svga.u32IndexReg;
1701	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1702	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1703	VINF_IOM_R3_IOPORT_WRITE);
1704	#else
1705	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1706	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1707	VINF_SUCCESS);
1708	#endif
1709	RT_UNTRUSTED_VALIDATED_FENCE();
1710
1711	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1712	if ( idxReg >= SVGA_REG_CAPABILITIES
1713	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1714	{
1715	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1716	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1717	}
1718	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1719	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1720	switch (idxReg)
1721	{
1722	case SVGA_REG_WIDTH:
1723	case SVGA_REG_HEIGHT:
1724	case SVGA_REG_PITCHLOCK:
1725	case SVGA_REG_BITS_PER_PIXEL:
1726	pThis->svga.fGFBRegisters = true;
1727	break;
1728	default:
1729	break;
1730	}
1731
1732	switch (idxReg)
1733	{
1734	case SVGA_REG_ID:
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1736	if ( u32 == SVGA_ID_0
1737	\|\| u32 == SVGA_ID_1
1738	\|\| u32 == SVGA_ID_2)
1739	pThis->svga.u32SVGAId = u32;
1740	else
1741	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1742	break;
1743
1744	case SVGA_REG_ENABLE:
1745	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1746	#ifdef IN_RING3
1747	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1748	&& pThis->svga.fEnabled == false)
1749	{
1750	/* Make a backup copy of the first 512kb in order to save font data etc. */
1751	/** @todo should probably swap here, rather than copy + zero */
1752	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1753	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1754	}
1755
1756	pThis->svga.fEnabled = u32;
1757	if (pThis->svga.fEnabled)
1758	{
1759	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1760	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1761	{
1762	/* Keep the current mode. */
1763	pThis->svga.uWidth = pThisCC->pDrv->cx;
1764	pThis->svga.uHeight = pThisCC->pDrv->cy;
1765	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1766	}
1767
1768	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1769	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1770	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1771	# ifdef LOG_ENABLED
1772	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1773	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1774	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1775	# endif
1776
1777	/* Disable or enable dirty page tracking according to the current fTraces value. */
1778	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1779
1780	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1781	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1782	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1783
1784	/* Make the cursor visible again as needed. */
1785	if (pSVGAState->Cursor.fActive)
1786	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1787	}
1788	else
1789	{
1790	/* Make sure the cursor is off. */
1791	if (pSVGAState->Cursor.fActive)
1792	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1793
1794	/* Restore the text mode backup. */
1795	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1796
1797	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1798
1799	/* Enable dirty page tracking again when going into legacy mode. */
1800	vmsvgaR3SetTraces(pDevIns, pThis, true);
1801
1802	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1803	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1804	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1805
1806	/* Clear the pitch lock. */
1807	pThis->svga.u32PitchLock = 0;
1808	}
1809	#else /* !IN_RING3 */
1810	rc = VINF_IOM_R3_IOPORT_WRITE;
1811	#endif /* !IN_RING3 */
1812	break;
1813
1814	case SVGA_REG_WIDTH:
1815	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1816	if (pThis->svga.uWidth != u32)
1817	{
1818	#if defined(IN_RING3) \|\| defined(IN_RING0)
1819	pThis->svga.uWidth = u32;
1820	vmsvgaHCUpdatePitch(pThis, pThisCC);
1821	if (pThis->svga.fEnabled)
1822	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1823	#else
1824	rc = VINF_IOM_R3_IOPORT_WRITE;
1825	#endif
1826	}
1827	/* else: nop */
1828	break;
1829
1830	case SVGA_REG_HEIGHT:
1831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1832	if (pThis->svga.uHeight != u32)
1833	{
1834	pThis->svga.uHeight = u32;
1835	if (pThis->svga.fEnabled)
1836	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1837	}
1838	/* else: nop */
1839	break;
1840
1841	case SVGA_REG_DEPTH:
1842	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1843	/** @todo read-only?? */
1844	break;
1845
1846	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1847	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1848	if (pThis->svga.uBpp != u32)
1849	{
1850	#if defined(IN_RING3) \|\| defined(IN_RING0)
1851	pThis->svga.uBpp = u32;
1852	vmsvgaHCUpdatePitch(pThis, pThisCC);
1853	if (pThis->svga.fEnabled)
1854	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1855	#else
1856	rc = VINF_IOM_R3_IOPORT_WRITE;
1857	#endif
1858	}
1859	/* else: nop */
1860	break;
1861
1862	case SVGA_REG_PSEUDOCOLOR:
1863	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1864	break;
1865
1866	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1867	#ifdef IN_RING3
1868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1869	pThis->svga.fConfigured = u32;
1870	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1871	if (!pThis->svga.fConfigured)
1872	pThis->svga.fTraces = true;
1873	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1874	#else
1875	rc = VINF_IOM_R3_IOPORT_WRITE;
1876	#endif
1877	break;
1878
1879	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1880	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1881	if ( pThis->svga.fEnabled
1882	&& pThis->svga.fConfigured)
1883	{
1884	#if defined(IN_RING3) \|\| defined(IN_RING0)
1885	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1886	/*
1887	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1888	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1889	*/
1890	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1891	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1892	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1893
1894	/* Kick the FIFO thread to start processing commands again. */
1895	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1896	#else
1897	rc = VINF_IOM_R3_IOPORT_WRITE;
1898	#endif
1899	}
1900	/* else nothing to do. */
1901	else
1902	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1903
1904	break;
1905
1906	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1908	break;
1909
1910	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1911	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1912	pThis->svga.u32GuestId = u32;
1913	break;
1914
1915	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1916	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1917	pThis->svga.u32PitchLock = u32;
1918	/* Should this also update the FIFO pitch lock? Unclear. */
1919	break;
1920
1921	case SVGA_REG_IRQMASK: /* Interrupt mask */
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1923	pThis->svga.u32IrqMask = u32;
1924
1925	/* Irq pending after the above change? */
1926	if (pThis->svga.u32IrqStatus & u32)
1927	{
1928	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1929	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1930	}
1931	else
1932	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1933	break;
1934
1935	/* Mouse cursor support */
1936	case SVGA_REG_CURSOR_ID:
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1938	pThis->svga.uCursorID = u32;
1939	break;
1940
1941	case SVGA_REG_CURSOR_X:
1942	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1943	pThis->svga.uCursorX = u32;
1944	break;
1945
1946	case SVGA_REG_CURSOR_Y:
1947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1948	pThis->svga.uCursorY = u32;
1949	break;
1950
1951	case SVGA_REG_CURSOR_ON:
1952	#ifdef IN_RING3
1953	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1955	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1956	#else
1957	rc = VINF_IOM_R3_IOPORT_WRITE;
1958	#endif
1959	break;
1960
1961	/* Legacy multi-monitor support */
1962	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1964	break;
1965	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1967	break;
1968	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1970	break;
1971	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1973	break;
1974	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1976	break;
1977	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1979	break;
1980	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1982	break;
1983	#ifdef VBOX_WITH_VMSVGA3D
1984	/* See "Guest memory regions" below. */
1985	case SVGA_REG_GMR_ID:
1986	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1987	pThis->svga.u32CurrentGMRId = u32;
1988	break;
1989
1990	case SVGA_REG_GMR_DESCRIPTOR:
1991	# ifndef IN_RING3
1992	rc = VINF_IOM_R3_IOPORT_WRITE;
1993	break;
1994	# else /* IN_RING3 */
1995	{
1996	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1997
1998	/* Validate current GMR id. */
1999	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2000	AssertBreak(idGMR < pThis->svga.cGMR);
2001	RT_UNTRUSTED_VALIDATED_FENCE();
2002
2003	/* Free the old GMR if present. */
2004	vmsvgaR3GmrFree(pThisCC, idGMR);
2005
2006	/* Just undefine the GMR? */
2007	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2008	if (GCPhys == 0)
2009	{
2010	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2011	break;
2012	}
2013
2014
2015	/* Never cross a page boundary automatically. */
2016	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2017	uint32_t cPagesTotal = 0;
2018	uint32_t iDesc = 0;
2019	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2020	uint32_t cLoops = 0;
2021	RTGCPHYS GCPhysBase = GCPhys;
2022	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2023	{
2024	/* Read descriptor. */
2025	SVGAGuestMemDescriptor desc;
2026	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2027	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2028
2029	if (desc.numPages != 0)
2030	{
2031	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2032	cPagesTotal += desc.numPages;
2033	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2034
2035	if ((iDesc & 15) == 0)
2036	{
2037	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2038	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2039	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2040	}
2041
2042	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2043	paDescs[iDesc++].numPages = desc.numPages;
2044
2045	/* Continue with the next descriptor. */
2046	GCPhys += sizeof(desc);
2047	}
2048	else if (desc.ppn == 0)
2049	break; /* terminator */
2050	else /* Pointer to the next physical page of descriptors. */
2051	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2052
2053	cLoops++;
2054	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2055	}
2056
2057	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2058	if (RT_SUCCESS(rc))
2059	{
2060	/* Commit the GMR. */
2061	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2062	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2063	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2064	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2065	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2066	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2067	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2068	}
2069	else
2070	{
2071	RTMemFree(paDescs);
2072	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2073	}
2074	break;
2075	}
2076	# endif /* IN_RING3 */
2077	#endif // VBOX_WITH_VMSVGA3D
2078
2079	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2081	if (pThis->svga.fTraces == u32)
2082	break; /* nothing to do */
2083
2084	#ifdef IN_RING3
2085	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2086	#else
2087	rc = VINF_IOM_R3_IOPORT_WRITE;
2088	#endif
2089	break;
2090
2091	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2092	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2093	break;
2094
2095	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2096	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2097	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2098	break;
2099
2100	case SVGA_REG_FB_START:
2101	case SVGA_REG_MEM_START:
2102	case SVGA_REG_HOST_BITS_PER_PIXEL:
2103	case SVGA_REG_MAX_WIDTH:
2104	case SVGA_REG_MAX_HEIGHT:
2105	case SVGA_REG_VRAM_SIZE:
2106	case SVGA_REG_FB_SIZE:
2107	case SVGA_REG_CAPABILITIES:
2108	case SVGA_REG_MEM_SIZE:
2109	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2110	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2111	case SVGA_REG_BYTES_PER_LINE:
2112	case SVGA_REG_FB_OFFSET:
2113	case SVGA_REG_RED_MASK:
2114	case SVGA_REG_GREEN_MASK:
2115	case SVGA_REG_BLUE_MASK:
2116	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2117	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2118	case SVGA_REG_GMR_MAX_IDS:
2119	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2120	/* Read only - ignore. */
2121	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2122	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2123	break;
2124
2125	default:
2126	{
2127	uint32_t offReg;
2128	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2129	{
2130	RT_UNTRUSTED_VALIDATED_FENCE();
2131	pThis->svga.au32ScratchRegion[offReg] = u32;
2132	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2133	}
2134	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2135	{
2136	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2137	Btw, see rgb_to_pixel32. */
2138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2139	u32 &= 0xff;
2140	RT_UNTRUSTED_VALIDATED_FENCE();
2141	uint32_t uRgb = pThis->last_palette[offReg / 3];
2142	switch (offReg % 3)
2143	{
2144	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2145	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2146	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2147	}
2148	pThis->last_palette[offReg / 3] = uRgb;
2149	}
2150	else
2151	{
2152	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2153	rc = VINF_IOM_R3_IOPORT_WRITE;
2154	#else
2155	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2156	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2157	#endif
2158	}
2159	break;
2160	}
2161	}
2162	return rc;
2163	}
2164
2165	/**
2166	* @callback_method_impl{FNIOMIOPORTNEWIN}
2167	*/
2168	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2169	{
2170	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2171	RT_NOREF_PV(pvUser);
2172
2173	/* Only dword accesses. */
2174	if (cb == 4)
2175	{
2176	switch (offPort)
2177	{
2178	case SVGA_INDEX_PORT:
2179	*pu32 = pThis->svga.u32IndexReg;
2180	break;
2181
2182	case SVGA_VALUE_PORT:
2183	return vmsvgaReadPort(pDevIns, pThis, pu32);
2184
2185	case SVGA_BIOS_PORT:
2186	Log(("Ignoring BIOS port read\n"));
2187	*pu32 = 0;
2188	break;
2189
2190	case SVGA_IRQSTATUS_PORT:
2191	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2192	*pu32 = pThis->svga.u32IrqStatus;
2193	break;
2194
2195	default:
2196	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2197	*pu32 = UINT32_MAX;
2198	break;
2199	}
2200	}
2201	else
2202	{
2203	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2204	*pu32 = UINT32_MAX;
2205	}
2206	return VINF_SUCCESS;
2207	}
2208
2209	/**
2210	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2211	*/
2212	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2213	{
2214	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2215	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2216	RT_NOREF_PV(pvUser);
2217
2218	/* Only dword accesses. */
2219	if (cb == 4)
2220	switch (offPort)
2221	{
2222	case SVGA_INDEX_PORT:
2223	pThis->svga.u32IndexReg = u32;
2224	break;
2225
2226	case SVGA_VALUE_PORT:
2227	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2228
2229	case SVGA_BIOS_PORT:
2230	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2231	break;
2232
2233	case SVGA_IRQSTATUS_PORT:
2234	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2235	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2236	/* Clear the irq in case all events have been cleared. */
2237	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2238	{
2239	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2240	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2241	}
2242	break;
2243
2244	default:
2245	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2246	break;
2247	}
2248	else
2249	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2250
2251	return VINF_SUCCESS;
2252	}
2253
2254	#ifdef IN_RING3
2255
2256	# ifdef DEBUG_FIFO_ACCESS
2257	/**
2258	* Handle FIFO memory access.
2259	* @returns VBox status code.
2260	* @param pVM VM handle.
2261	* @param pThis The shared VGA/VMSVGA instance data.
2262	* @param GCPhys The access physical address.
2263	* @param fWriteAccess Read or write access
2264	*/
2265	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2266	{
2267	RT_NOREF(pVM);
2268	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2269	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2270
2271	switch (GCPhysOffset >> 2)
2272	{
2273	case SVGA_FIFO_MIN:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_MAX:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_NEXT_CMD:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_STOP:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_CAPABILITIES:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_FLAGS:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_FENCE:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_HWVERSION:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_PITCHLOCK:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_CURSOR_ON:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_CURSOR_X:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_CURSOR_Y:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_CURSOR_COUNT:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_RESERVED:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_CURSOR_SCREEN_ID:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_DEAD:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_HWVERSION_REVISED:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS_LAST:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_GUEST_3D_HWVERSION:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_FENCE_GOAL:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_BUSY:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	default:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	}
2592
2593	return VINF_EM_RAW_EMULATE_INSTR;
2594	}
2595	# endif /* DEBUG_FIFO_ACCESS */
2596
2597	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2598	/**
2599	* HC access handler for the FIFO.
2600	*
2601	* @returns VINF_SUCCESS if the handler have carried out the operation.
2602	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2603	* @param pVM VM Handle.
2604	* @param pVCpu The cross context CPU structure for the calling EMT.
2605	* @param GCPhys The physical address the guest is writing to.
2606	* @param pvPhys The HC mapping of that address.
2607	* @param pvBuf What the guest is reading/writing.
2608	* @param cbBuf How much it's reading/writing.
2609	* @param enmAccessType The access type.
2610	* @param enmOrigin Who is making the access.
2611	* @param pvUser User argument.
2612	*/
2613	static DECLCALLBACK(VBOXSTRICTRC)
2614	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2615	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2616	{
2617	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2618	PVGASTATE pThis = (PVGASTATE)pvUser;
2619	AssertPtr(pThis);
2620
2621	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2622	/*
2623	* Wake up the FIFO thread as it might have work to do now.
2624	*/
2625	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2626	AssertLogRelRC(rc);
2627	# endif
2628
2629	# ifdef DEBUG_FIFO_ACCESS
2630	/*
2631	* When in debug-fifo-access mode, we do not disable the access handler,
2632	* but leave it on as we wish to catch all access.
2633	*/
2634	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2635	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2636	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2637	/*
2638	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2639	*/
2640	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2641	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2642	# endif
2643	if (RT_SUCCESS(rc))
2644	return VINF_PGM_HANDLER_DO_DEFAULT;
2645	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2646	return rc;
2647	}
2648	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2649
2650	#endif /* IN_RING3 */
2651
2652	#ifdef DEBUG_GMR_ACCESS
2653	# ifdef IN_RING3
2654
2655	/**
2656	* HC access handler for the FIFO.
2657	*
2658	* @returns VINF_SUCCESS if the handler have carried out the operation.
2659	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2660	* @param pVM VM Handle.
2661	* @param pVCpu The cross context CPU structure for the calling EMT.
2662	* @param GCPhys The physical address the guest is writing to.
2663	* @param pvPhys The HC mapping of that address.
2664	* @param pvBuf What the guest is reading/writing.
2665	* @param cbBuf How much it's reading/writing.
2666	* @param enmAccessType The access type.
2667	* @param enmOrigin Who is making the access.
2668	* @param pvUser User argument.
2669	*/
2670	static DECLCALLBACK(VBOXSTRICTRC)
2671	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2672	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2673	{
2674	PVGASTATE pThis = (PVGASTATE)pvUser;
2675	Assert(pThis);
2676	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2677	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2678
2679	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2680
2681	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2682	{
2683	PGMR pGMR = &pSVGAState->paGMR[i];
2684
2685	if (pGMR->numDescriptors)
2686	{
2687	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2688	{
2689	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2690	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2691	{
2692	/*
2693	* Turn off the write handler for this particular page and make it R/W.
2694	* Then return telling the caller to restart the guest instruction.
2695	*/
2696	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2697	AssertRC(rc);
2698	return VINF_PGM_HANDLER_DO_DEFAULT;
2699	}
2700	}
2701	}
2702	}
2703
2704	return VINF_PGM_HANDLER_DO_DEFAULT;
2705	}
2706
2707	/** Callback handler for VMR3ReqCallWaitU */
2708	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2709	{
2710	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2711	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2712	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2713	int rc;
2714
2715	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2716	{
2717	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2718	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2719	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2720	AssertRC(rc);
2721	}
2722	return VINF_SUCCESS;
2723	}
2724
2725	/** Callback handler for VMR3ReqCallWaitU */
2726	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2727	{
2728	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2729	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2730	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2731
2732	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2733	{
2734	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2735	AssertRC(rc);
2736	}
2737	return VINF_SUCCESS;
2738	}
2739
2740	/** Callback handler for VMR3ReqCallWaitU */
2741	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2742	{
2743	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2744
2745	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2746	{
2747	PGMR pGMR = &pSVGAState->paGMR[i];
2748
2749	if (pGMR->numDescriptors)
2750	{
2751	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2752	{
2753	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2754	AssertRC(rc);
2755	}
2756	}
2757	}
2758	return VINF_SUCCESS;
2759	}
2760
2761	# endif /* IN_RING3 */
2762	#endif /* DEBUG_GMR_ACCESS */
2763
2764	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2765
2766	#ifdef IN_RING3
2767
2768
2769	/**
2770	* Common worker for changing the pointer shape.
2771	*
2772	* @param pThisCC The VGA/VMSVGA state for ring-3.
2773	* @param pSVGAState The VMSVGA ring-3 instance data.
2774	* @param fAlpha Whether there is alpha or not.
2775	* @param xHot Hotspot x coordinate.
2776	* @param yHot Hotspot y coordinate.
2777	* @param cx Width.
2778	* @param cy Height.
2779	* @param pbData Heap copy of the cursor data. Consumed.
2780	* @param cbData The size of the data.
2781	*/
2782	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2783	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2784	{
2785	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2786	# ifdef LOG_ENABLED
2787	if (LogIs2Enabled())
2788	{
2789	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2790	if (!fAlpha)
2791	{
2792	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2793	for (uint32_t y = 0; y < cy; y++)
2794	{
2795	Log2(("%3u:", y));
2796	uint8_t const pbLine = &pbData[y cbAndLine];
2797	for (uint32_t x = 0; x < cx; x += 8)
2798	{
2799	uint8_t b = pbLine[x / 8];
2800	char szByte[12];
2801	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2802	szByte[1] = b & 0x40 ? '*' : ' ';
2803	szByte[2] = b & 0x20 ? '*' : ' ';
2804	szByte[3] = b & 0x10 ? '*' : ' ';
2805	szByte[4] = b & 0x08 ? '*' : ' ';
2806	szByte[5] = b & 0x04 ? '*' : ' ';
2807	szByte[6] = b & 0x02 ? '*' : ' ';
2808	szByte[7] = b & 0x01 ? '*' : ' ';
2809	szByte[8] = '\0';
2810	Log2(("%s", szByte));
2811	}
2812	Log2(("\n"));
2813	}
2814	}
2815
2816	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2817	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2818	for (uint32_t y = 0; y < cy; y++)
2819	{
2820	Log2(("%3u:", y));
2821	uint32_t const pu32Line = &pu32Xor[y cx];
2822	for (uint32_t x = 0; x < cx; x++)
2823	Log2((" %08x", pu32Line[x]));
2824	Log2(("\n"));
2825	}
2826	}
2827	# endif
2828
2829	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2830	AssertRC(rc);
2831
2832	if (pSVGAState->Cursor.fActive)
2833	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
2834
2835	pSVGAState->Cursor.fActive = true;
2836	pSVGAState->Cursor.xHotspot = xHot;
2837	pSVGAState->Cursor.yHotspot = yHot;
2838	pSVGAState->Cursor.width = cx;
2839	pSVGAState->Cursor.height = cy;
2840	pSVGAState->Cursor.cbData = cbData;
2841	pSVGAState->Cursor.pData = pbData;
2842	}
2843
2844
2845	/**
2846	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2847	*
2848	* @param pThis The shared VGA/VMSVGA state.
2849	* @param pThisCC The VGA/VMSVGA state for ring-3.
2850	* @param pSVGAState The VMSVGA ring-3 instance data.
2851	* @param pCursor The cursor.
2852	* @param pbSrcAndMask The AND mask.
2853	* @param cbSrcAndLine The scanline length of the AND mask.
2854	* @param pbSrcXorMask The XOR mask.
2855	* @param cbSrcXorLine The scanline length of the XOR mask.
2856	*/
2857	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2858	SVGAFifoCmdDefineCursor const *pCursor,
2859	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2860	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2861	{
2862	uint32_t const cx = pCursor->width;
2863	uint32_t const cy = pCursor->height;
2864
2865	/*
2866	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2867	* The AND data uses 8-bit aligned scanlines.
2868	* The XOR data must be starting on a 32-bit boundrary.
2869	*/
2870	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2871	uint32_t cbDstAndMask = cbDstAndLine * cy;
2872	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2873	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2874
2875	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2876	AssertReturnVoid(pbCopy);
2877
2878	/* Convert the AND mask. */
2879	uint8_t *pbDst = pbCopy;
2880	uint8_t const *pbSrc = pbSrcAndMask;
2881	switch (pCursor->andMaskDepth)
2882	{
2883	case 1:
2884	if (cbSrcAndLine == cbDstAndLine)
2885	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2886	else
2887	{
2888	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2889	for (uint32_t y = 0; y < cy; y++)
2890	{
2891	memcpy(pbDst, pbSrc, cbDstAndLine);
2892	pbDst += cbDstAndLine;
2893	pbSrc += cbSrcAndLine;
2894	}
2895	}
2896	break;
2897	/* Should take the XOR mask into account for the multi-bit AND mask. */
2898	case 8:
2899	for (uint32_t y = 0; y < cy; y++)
2900	{
2901	for (uint32_t x = 0; x < cx; )
2902	{
2903	uint8_t bDst = 0;
2904	uint8_t fBit = 0x80;
2905	do
2906	{
2907	uintptr_t const idxPal = pbSrc[x] * 3;
2908	if ((( pThis->last_palette[idxPal]
2909	\| (pThis->last_palette[idxPal] >> 8)
2910	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2911	bDst \|= fBit;
2912	fBit >>= 1;
2913	x++;
2914	} while (x < cx && (x & 7));
2915	pbDst[(x - 1) / 8] = bDst;
2916	}
2917	pbDst += cbDstAndLine;
2918	pbSrc += cbSrcAndLine;
2919	}
2920	break;
2921	case 15:
2922	for (uint32_t y = 0; y < cy; y++)
2923	{
2924	for (uint32_t x = 0; x < cx; )
2925	{
2926	uint8_t bDst = 0;
2927	uint8_t fBit = 0x80;
2928	do
2929	{
2930	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2931	bDst \|= fBit;
2932	fBit >>= 1;
2933	x++;
2934	} while (x < cx && (x & 7));
2935	pbDst[(x - 1) / 8] = bDst;
2936	}
2937	pbDst += cbDstAndLine;
2938	pbSrc += cbSrcAndLine;
2939	}
2940	break;
2941	case 16:
2942	for (uint32_t y = 0; y < cy; y++)
2943	{
2944	for (uint32_t x = 0; x < cx; )
2945	{
2946	uint8_t bDst = 0;
2947	uint8_t fBit = 0x80;
2948	do
2949	{
2950	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2951	bDst \|= fBit;
2952	fBit >>= 1;
2953	x++;
2954	} while (x < cx && (x & 7));
2955	pbDst[(x - 1) / 8] = bDst;
2956	}
2957	pbDst += cbDstAndLine;
2958	pbSrc += cbSrcAndLine;
2959	}
2960	break;
2961	case 24:
2962	for (uint32_t y = 0; y < cy; y++)
2963	{
2964	for (uint32_t x = 0; x < cx; )
2965	{
2966	uint8_t bDst = 0;
2967	uint8_t fBit = 0x80;
2968	do
2969	{
2970	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2971	bDst \|= fBit;
2972	fBit >>= 1;
2973	x++;
2974	} while (x < cx && (x & 7));
2975	pbDst[(x - 1) / 8] = bDst;
2976	}
2977	pbDst += cbDstAndLine;
2978	pbSrc += cbSrcAndLine;
2979	}
2980	break;
2981	case 32:
2982	for (uint32_t y = 0; y < cy; y++)
2983	{
2984	for (uint32_t x = 0; x < cx; )
2985	{
2986	uint8_t bDst = 0;
2987	uint8_t fBit = 0x80;
2988	do
2989	{
2990	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2991	bDst \|= fBit;
2992	fBit >>= 1;
2993	x++;
2994	} while (x < cx && (x & 7));
2995	pbDst[(x - 1) / 8] = bDst;
2996	}
2997	pbDst += cbDstAndLine;
2998	pbSrc += cbSrcAndLine;
2999	}
3000	break;
3001	default:
3002	RTMemFreeZ(pbCopy, cbCopy);
3003	AssertFailedReturnVoid();
3004	}
3005
3006	/* Convert the XOR mask. */
3007	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
3008	pbSrc = pbSrcXorMask;
3009	switch (pCursor->xorMaskDepth)
3010	{
3011	case 1:
3012	for (uint32_t y = 0; y < cy; y++)
3013	{
3014	for (uint32_t x = 0; x < cx; )
3015	{
3016	/* most significant bit is the left most one. */
3017	uint8_t bSrc = pbSrc[x / 8];
3018	do
3019	{
3020	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
3021	bSrc <<= 1;
3022	x++;
3023	} while ((x & 7) && x < cx);
3024	}
3025	pbSrc += cbSrcXorLine;
3026	}
3027	break;
3028	case 8:
3029	for (uint32_t y = 0; y < cy; y++)
3030	{
3031	for (uint32_t x = 0; x < cx; x++)
3032	{
3033	uint32_t u = pThis->last_palette[pbSrc[x]];
3034	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3035	}
3036	pbSrc += cbSrcXorLine;
3037	}
3038	break;
3039	case 15: /* Src: RGB-5-5-5 */
3040	for (uint32_t y = 0; y < cy; y++)
3041	{
3042	for (uint32_t x = 0; x < cx; x++)
3043	{
3044	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3045	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3046	((uValue >> 5) & 0x1f) << 3,
3047	((uValue >> 10) & 0x1f) << 3, 0);
3048	}
3049	pbSrc += cbSrcXorLine;
3050	}
3051	break;
3052	case 16: /* Src: RGB-5-6-5 */
3053	for (uint32_t y = 0; y < cy; y++)
3054	{
3055	for (uint32_t x = 0; x < cx; x++)
3056	{
3057	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3058	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3059	((uValue >> 5) & 0x3f) << 2,
3060	((uValue >> 11) & 0x1f) << 3, 0);
3061	}
3062	pbSrc += cbSrcXorLine;
3063	}
3064	break;
3065	case 24:
3066	for (uint32_t y = 0; y < cy; y++)
3067	{
3068	for (uint32_t x = 0; x < cx; x++)
3069	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3070	pbSrc += cbSrcXorLine;
3071	}
3072	break;
3073	case 32:
3074	for (uint32_t y = 0; y < cy; y++)
3075	{
3076	for (uint32_t x = 0; x < cx; x++)
3077	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3078	pbSrc += cbSrcXorLine;
3079	}
3080	break;
3081	default:
3082	RTMemFreeZ(pbCopy, cbCopy);
3083	AssertFailedReturnVoid();
3084	}
3085
3086	/*
3087	* Pass it to the frontend/whatever.
3088	*/
3089	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3090	}
3091
3092
3093	/**
3094	* Worker for vmsvgaR3FifoThread that handles an external command.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param pThis The shared VGA/VMSVGA instance data.
3098	* @param pThisCC The VGA/VMSVGA state for ring-3.
3099	*/
3100	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3101	{
3102	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3103	switch (pThis->svga.u8FIFOExtCommand)
3104	{
3105	case VMSVGA_FIFO_EXTCMD_RESET:
3106	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3107	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3108	# ifdef VBOX_WITH_VMSVGA3D
3109	if (pThis->svga.f3DEnabled)
3110	{
3111	/* The 3d subsystem must be reset from the fifo thread. */
3112	vmsvgaR3ResetScreens(pThisCC); /** @todo Also destroy screens on PowerOff. */
3113	vmsvga3dReset(pThisCC);
3114	}
3115	# endif
3116	break;
3117
3118	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3119	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3120	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3121	# ifdef VBOX_WITH_VMSVGA3D
3122	if (pThis->svga.f3DEnabled)
3123	{
3124	/* The 3d subsystem must be shut down from the fifo thread. */
3125	vmsvga3dTerminate(pThisCC);
3126	}
3127	# endif
3128	break;
3129
3130	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3131	{
3132	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3133	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3134	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3135	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3136	# ifdef VBOX_WITH_VMSVGA3D
3137	if (pThis->svga.f3DEnabled)
3138	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3139	# endif
3140	break;
3141	}
3142
3143	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3144	{
3145	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3146	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3147	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3148	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3149	# ifdef VBOX_WITH_VMSVGA3D
3150	if (pThis->svga.f3DEnabled)
3151	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3152	# endif
3153	break;
3154	}
3155
3156	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3157	{
3158	# ifdef VBOX_WITH_VMSVGA3D
3159	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3160	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3161	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3162	# endif
3163	break;
3164	}
3165
3166
3167	default:
3168	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3169	break;
3170	}
3171
3172	/*
3173	* Signal the end of the external command.
3174	*/
3175	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3176	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3177	ASMMemoryFence(); /* paranoia^2 */
3178	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3179	AssertLogRelRC(rc);
3180	}
3181
3182	/**
3183	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3184	* doing a job on the FIFO thread (even when it's officially suspended).
3185	*
3186	* @returns VBox status code (fully asserted).
3187	* @param pDevIns The device instance.
3188	* @param pThis The shared VGA/VMSVGA instance data.
3189	* @param pThisCC The VGA/VMSVGA state for ring-3.
3190	* @param uExtCmd The command to execute on the FIFO thread.
3191	* @param pvParam Pointer to command parameters.
3192	* @param cMsWait The time to wait for the command, given in
3193	* milliseconds.
3194	*/
3195	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3196	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3197	{
3198	Assert(cMsWait >= RT_MS_1SEC * 5);
3199	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3200	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3201
3202	int rc;
3203	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3204	PDMTHREADSTATE enmState = pThread->enmState;
3205	if (enmState == PDMTHREADSTATE_SUSPENDED)
3206	{
3207	/*
3208	* The thread is suspended, we have to temporarily wake it up so it can
3209	* perform the task.
3210	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3211	*/
3212	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3213	/* Post the request. */
3214	pThis->svga.fFifoExtCommandWakeup = true;
3215	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3216	pThis->svga.u8FIFOExtCommand = uExtCmd;
3217	ASMMemoryFence(); /* paranoia^3 */
3218
3219	/* Resume the thread. */
3220	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3221	AssertLogRelRC(rc);
3222	if (RT_SUCCESS(rc))
3223	{
3224	/* Wait. Take care in case the semaphore was already posted (same as below). */
3225	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3226	if ( rc == VINF_SUCCESS
3227	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3228	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3229	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3230	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3231
3232	/* suspend the thread */
3233	pThis->svga.fFifoExtCommandWakeup = false;
3234	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3235	AssertLogRelRC(rc2);
3236	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3237	rc = rc2;
3238	}
3239	pThis->svga.fFifoExtCommandWakeup = false;
3240	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3241	}
3242	else if (enmState == PDMTHREADSTATE_RUNNING)
3243	{
3244	/*
3245	* The thread is running, should only happen during reset and vmsvga3dsfc.
3246	* We ASSUME not racing code here, both wrt thread state and ext commands.
3247	*/
3248	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3249	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS);
3250
3251	/* Post the request. */
3252	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3253	pThis->svga.u8FIFOExtCommand = uExtCmd;
3254	ASMMemoryFence(); /* paranoia^2 */
3255	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3256	AssertLogRelRC(rc);
3257
3258	/* Wait. Take care in case the semaphore was already posted (same as above). */
3259	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3260	if ( rc == VINF_SUCCESS
3261	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3262	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3263	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3264	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3265
3266	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3267	}
3268	else
3269	{
3270	/*
3271	* Something is wrong with the thread!
3272	*/
3273	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3274	rc = VERR_INVALID_STATE;
3275	}
3276	return rc;
3277	}
3278
3279
3280	/**
3281	* Marks the FIFO non-busy, notifying any waiting EMTs.
3282	*
3283	* @param pDevIns The device instance.
3284	* @param pThis The shared VGA/VMSVGA instance data.
3285	* @param pThisCC The VGA/VMSVGA state for ring-3.
3286	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3287	* @param offFifoMin The start byte offset of the command FIFO.
3288	*/
3289	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3290	{
3291	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3292	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3293	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3294
3295	/* Wake up any waiting EMTs. */
3296	if (pSVGAState->cBusyDelayedEmts > 0)
3297	{
3298	# ifdef VMSVGA_USE_EMT_HALT_CODE
3299	PVM pVM = PDMDevHlpGetVM(pDevIns);
3300	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3301	if (idCpu != NIL_VMCPUID)
3302	{
3303	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3304	while (idCpu-- > 0)
3305	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3306	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3307	}
3308	# else
3309	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3310	AssertRC(rc2);
3311	# endif
3312	}
3313	}
3314
3315	/**
3316	* Reads (more) payload into the command buffer.
3317	*
3318	* @returns pbBounceBuf on success
3319	* @retval (void *)1 if the thread was requested to stop.
3320	* @retval NULL on FIFO error.
3321	*
3322	* @param cbPayloadReq The number of bytes of payload requested.
3323	* @param pFIFO The FIFO.
3324	* @param offCurrentCmd The FIFO byte offset of the current command.
3325	* @param offFifoMin The start byte offset of the command FIFO.
3326	* @param offFifoMax The end byte offset of the command FIFO.
3327	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3328	* always sufficient size.
3329	* @param pcbAlreadyRead How much payload we've already read into the bounce
3330	* buffer. (We will NEVER re-read anything.)
3331	* @param pThread The calling PDM thread handle.
3332	* @param pThis The shared VGA/VMSVGA instance data.
3333	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3334	* statistics collection.
3335	* @param pDevIns The device instance.
3336	*/
3337	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3338	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3339	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3340	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3341	{
3342	Assert(pbBounceBuf);
3343	Assert(pcbAlreadyRead);
3344	Assert(offFifoMin < offFifoMax);
3345	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3346	Assert(offFifoMax <= pThis->svga.cbFIFO);
3347
3348	/*
3349	* Check if the requested payload size has already been satisfied .
3350	* .
3351	* When called to read more, the caller is responsible for making sure the .
3352	* new command size (cbRequsted) never is smaller than what has already .
3353	* been read.
3354	*/
3355	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3356	if (cbPayloadReq <= cbAlreadyRead)
3357	{
3358	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3359	return pbBounceBuf;
3360	}
3361
3362	/*
3363	* Commands bigger than the fifo buffer are invalid.
3364	*/
3365	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3366	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3367	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3368	NULL);
3369
3370	/*
3371	* Move offCurrentCmd past the command dword.
3372	*/
3373	offCurrentCmd += sizeof(uint32_t);
3374	if (offCurrentCmd >= offFifoMax)
3375	offCurrentCmd = offFifoMin;
3376
3377	/*
3378	* Do we have sufficient payload data available already?
3379	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3380	*/
3381	uint32_t cbAfter, cbBefore;
3382	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3383	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3384	if (offNextCmd >= offCurrentCmd)
3385	{
3386	if (RT_LIKELY(offNextCmd < offFifoMax))
3387	cbAfter = offNextCmd - offCurrentCmd;
3388	else
3389	{
3390	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3391	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3392	offNextCmd, offFifoMin, offFifoMax));
3393	cbAfter = offFifoMax - offCurrentCmd;
3394	}
3395	cbBefore = 0;
3396	}
3397	else
3398	{
3399	cbAfter = offFifoMax - offCurrentCmd;
3400	if (offNextCmd >= offFifoMin)
3401	cbBefore = offNextCmd - offFifoMin;
3402	else
3403	{
3404	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3405	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3406	offNextCmd, offFifoMin, offFifoMax));
3407	cbBefore = 0;
3408	}
3409	}
3410	if (cbAfter + cbBefore < cbPayloadReq)
3411	{
3412	/*
3413	* Insufficient, must wait for it to arrive.
3414	*/
3415	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3416	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3417	for (uint32_t i = 0;; i++)
3418	{
3419	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3420	{
3421	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3422	return (void *)(uintptr_t)1;
3423	}
3424	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3425	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3426
3427	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3428
3429	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3430	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3431	if (offNextCmd >= offCurrentCmd)
3432	{
3433	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3434	cbBefore = 0;
3435	}
3436	else
3437	{
3438	cbAfter = offFifoMax - offCurrentCmd;
3439	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3440	}
3441
3442	if (cbAfter + cbBefore >= cbPayloadReq)
3443	break;
3444	}
3445	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3446	}
3447
3448	/*
3449	* Copy out the memory and update what pcbAlreadyRead points to.
3450	*/
3451	if (cbAfter >= cbPayloadReq)
3452	memcpy(pbBounceBuf + cbAlreadyRead,
3453	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3454	cbPayloadReq - cbAlreadyRead);
3455	else
3456	{
3457	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3458	if (cbAlreadyRead < cbAfter)
3459	{
3460	memcpy(pbBounceBuf + cbAlreadyRead,
3461	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3462	cbAfter - cbAlreadyRead);
3463	cbAlreadyRead = cbAfter;
3464	}
3465	memcpy(pbBounceBuf + cbAlreadyRead,
3466	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3467	cbPayloadReq - cbAlreadyRead);
3468	}
3469	*pcbAlreadyRead = cbPayloadReq;
3470	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3471	return pbBounceBuf;
3472	}
3473
3474
3475	/**
3476	* Sends cursor position and visibility information from the FIFO to the front-end.
3477	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3478	*/
3479	static uint32_t
3480	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3481	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3482	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3483	{
3484	/*
3485	* Check if the cursor update counter has changed and try get a stable
3486	* set of values if it has. This is race-prone, especially consindering
3487	* the screen ID, but little we can do about that.
3488	*/
3489	uint32_t x, y, fVisible, idScreen;
3490	for (uint32_t i = 0; ; i++)
3491	{
3492	x = pFIFO[SVGA_FIFO_CURSOR_X];
3493	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3494	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3495	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3496	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3497	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3498	\|\| i > 3)
3499	break;
3500	if (i == 0)
3501	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3502	ASMNopPause();
3503	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3504	}
3505
3506	/*
3507	* Check if anything has changed, as calling into pDrv is not light-weight.
3508	*/
3509	if ( *pxLast == x
3510	&& *pyLast == y
3511	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3512	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3513	else
3514	{
3515	/*
3516	* Detected changes.
3517	*
3518	* We handle global, not per-screen visibility information by sending
3519	* pfnVBVAMousePointerShape without shape data.
3520	*/
3521	*pxLast = x;
3522	*pyLast = y;
3523	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3524	if (idScreen != SVGA_ID_INVALID)
3525	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3526	else if (*pfLastVisible != fVisible)
3527	{
3528	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3529	*pfLastVisible = fVisible;
3530	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3531	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3532	}
3533	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3534	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3535	}
3536
3537	/*
3538	* Update done. Signal this to the guest.
3539	*/
3540	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3541
3542	return uCursorUpdateCount;
3543	}
3544
3545
3546	/**
3547	* Checks if there is work to be done, either cursor updating or FIFO commands.
3548	*
3549	* @returns true if pending work, false if not.
3550	* @param pFIFO The FIFO to examine.
3551	* @param uLastCursorCount The last cursor update counter value.
3552	*/
3553	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3554	{
3555	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3556	return true;
3557
3558	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3559	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3560	return true;
3561
3562	return false;
3563	}
3564
3565
3566	/**
3567	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3568	*
3569	* @param pDevIns The device instance.
3570	* @param pThis The shared VGA/VMSVGA instance data.
3571	* @param pThisCC The VGA/VMSVGA state for ring-3.
3572	*/
3573	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3574	{
3575	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3576	to recheck it before doing the signalling. */
3577	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3578	AssertReturnVoid(pFIFO);
3579	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3580	&& pThis->svga.fFIFOThreadSleeping)
3581	{
3582	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3583	AssertRC(rc);
3584	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3585	}
3586	}
3587
3588
3589	/**
3590	* Called by the FIFO thread to process pending actions.
3591	*
3592	* @param pDevIns The device instance.
3593	* @param pThis The shared VGA/VMSVGA instance data.
3594	* @param pThisCC The VGA/VMSVGA state for ring-3.
3595	*/
3596	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3597	{
3598	RT_NOREF(pDevIns);
3599
3600	/* Currently just mode changes. */
3601	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3602	{
3603	vmsvgaR3ChangeMode(pThis, pThisCC);
3604	# ifdef VBOX_WITH_VMSVGA3D
3605	if (pThisCC->svga.p3dState != NULL)
3606	vmsvga3dChangeMode(pThisCC);
3607	# endif
3608	}
3609	}
3610
3611
3612	/*
3613	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3614	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3615	*/
3616	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3617	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3618	*
3619	* Will break out of the switch on failure.
3620	* Will restart and quit the loop if the thread was requested to stop.
3621	*
3622	* @param a_PtrVar Request variable pointer.
3623	* @param a_Type Request typedef (not pointer) for casting.
3624	* @param a_cbPayloadReq How much payload to fetch.
3625	* @remarks Accesses a bunch of variables in the current scope!
3626	*/
3627	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3628	if (1) { \
3629	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3630	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3631	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3632	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3633	} else do {} while (0)
3634	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3635	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3636	* buffer after figuring out the actual command size.
3637	*
3638	* Will break out of the switch on failure.
3639	*
3640	* @param a_PtrVar Request variable pointer.
3641	* @param a_Type Request typedef (not pointer) for casting.
3642	* @param a_cbPayloadReq How much payload to fetch.
3643	* @remarks Accesses a bunch of variables in the current scope!
3644	*/
3645	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3646	if (1) { \
3647	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3648	} else do {} while (0)
3649
3650	/**
3651	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3652	*/
3653	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3654	{
3655	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3656	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3657	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3658	int rc;
3659
3660	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
3661	if (pThis->svga.f3DEnabled)
3662	{
3663	/* The FIFO thread may use X API for accelerated screen output. */
3664	XInitThreads();
3665	}
3666	# endif
3667
3668	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3669	return VINF_SUCCESS;
3670
3671	/*
3672	* Special mode where we only execute an external command and the go back
3673	* to being suspended. Currently, all ext cmds ends up here, with the reset
3674	* one also being eligble for runtime execution further down as well.
3675	*/
3676	if (pThis->svga.fFifoExtCommandWakeup)
3677	{
3678	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3679	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3680	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3681	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3682	else
3683	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3684	return VINF_SUCCESS;
3685	}
3686
3687
3688	/*
3689	* Signal the semaphore to make sure we don't wait for 250ms after a
3690	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3691	*/
3692	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3693
3694	/*
3695	* Allocate a bounce buffer for command we get from the FIFO.
3696	* (All code must return via the end of the function to free this buffer.)
3697	*/
3698	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3699	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3700
3701	/*
3702	* Polling/sleep interval config.
3703	*
3704	* We wait for an a short interval if the guest has recently given us work
3705	* to do, but the interval increases the longer we're kept idle. Once we've
3706	* reached the refresh timer interval, we'll switch to extended waits,
3707	* depending on it or the guest to kick us into action when needed.
3708	*
3709	* Should the refresh time go fishing, we'll just continue increasing the
3710	* sleep length till we reaches the 250 ms max after about 16 seconds.
3711	*/
3712	RTMSINTERVAL const cMsMinSleep = 16;
3713	RTMSINTERVAL const cMsIncSleep = 2;
3714	RTMSINTERVAL const cMsMaxSleep = 250;
3715	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3716	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3717
3718	/*
3719	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3720	*
3721	* Initialize with values that will detect an update from the guest.
3722	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3723	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3724	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3725	*/
3726	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3727	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3728	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3729	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3730	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3731
3732	/*
3733	* The FIFO loop.
3734	*/
3735	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3736	bool fBadOrDisabledFifo = false;
3737	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3738	{
3739	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3740	/*
3741	* Should service the run loop every so often.
3742	*/
3743	if (pThis->svga.f3DEnabled)
3744	vmsvga3dCocoaServiceRunLoop();
3745	# endif
3746
3747	/* First check any pending actions. */
3748	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3749
3750	/*
3751	* Unless there's already work pending, go to sleep for a short while.
3752	* (See polling/sleep interval config above.)
3753	*/
3754	if ( fBadOrDisabledFifo
3755	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3756	{
3757	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3758	Assert(pThis->cMilliesRefreshInterval > 0);
3759	if (cMsSleep < pThis->cMilliesRefreshInterval)
3760	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3761	else
3762	{
3763	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3764	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3765	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3766	# endif
3767	if ( !fBadOrDisabledFifo
3768	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3769	rc = VINF_SUCCESS;
3770	else
3771	{
3772	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3773	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3774	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3775	}
3776	}
3777	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3778	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3779	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3780	{
3781	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3782	break;
3783	}
3784	}
3785	else
3786	rc = VINF_SUCCESS;
3787	fBadOrDisabledFifo = false;
3788	if (rc == VERR_TIMEOUT)
3789	{
3790	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3791	{
3792	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3793	continue;
3794	}
3795	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3796
3797	Log(("vmsvgaR3FifoLoop: timeout\n"));
3798	}
3799	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3800	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3801	cMsSleep = cMsMinSleep;
3802
3803	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3804	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3805	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3806
3807	/*
3808	* Handle external commands (currently only reset).
3809	*/
3810	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3811	{
3812	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3813	continue;
3814	}
3815
3816	/*
3817	* The device must be enabled and configured.
3818	*/
3819	if ( !pThis->svga.fEnabled
3820	\|\| !pThis->svga.fConfigured)
3821	{
3822	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3823	fBadOrDisabledFifo = true;
3824	cMsSleep = cMsMaxSleep; /* cheat */
3825	continue;
3826	}
3827
3828	/*
3829	* Get and check the min/max values. We ASSUME that they will remain
3830	* unchanged while we process requests. A further ASSUMPTION is that
3831	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3832	* we don't read it back while in the loop.
3833	*/
3834	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3835	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3836	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3837	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3838	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3839	\|\| offFifoMax <= offFifoMin
3840	\|\| offFifoMax > pThis->svga.cbFIFO
3841	\|\| (offFifoMax & 3) != 0
3842	\|\| (offFifoMin & 3) != 0
3843	\|\| offCurrentCmd < offFifoMin
3844	\|\| offCurrentCmd > offFifoMax))
3845	{
3846	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3847	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3848	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3849	fBadOrDisabledFifo = true;
3850	continue;
3851	}
3852	RT_UNTRUSTED_VALIDATED_FENCE();
3853	if (RT_UNLIKELY(offCurrentCmd & 3))
3854	{
3855	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3856	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3857	offCurrentCmd &= ~UINT32_C(3);
3858	}
3859
3860	/*
3861	* Update the cursor position before we start on the FIFO commands.
3862	*/
3863	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3864	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3865	{
3866	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3867	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3868	{ /* halfways likely */ }
3869	else
3870	{
3871	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3872	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3873	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3874	}
3875	}
3876
3877	/*
3878	* Mark the FIFO as busy.
3879	*/
3880	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
3881	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3882	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3883
3884	/*
3885	* Execute all queued FIFO commands.
3886	* Quit if pending external command or changes in the thread state.
3887	*/
3888	bool fDone = false;
3889	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3890	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3891	{
3892	uint32_t cbPayload = 0;
3893	uint32_t u32IrqStatus = 0;
3894
3895	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3896
3897	/* First check any pending actions. */
3898	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3899
3900	/* Check for pending external commands (reset). */
3901	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3902	break;
3903
3904	/*
3905	* Process the command.
3906	*/
3907	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3908	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3909	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3910	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3911	switch (enmCmdId)
3912	{
3913	case SVGA_CMD_INVALID_CMD:
3914	/* Nothing to do. */
3915	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3916	break;
3917
3918	case SVGA_CMD_FENCE:
3919	{
3920	SVGAFifoCmdFence *pCmdFence;
3921	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3922	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3923	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3924	{
3925	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3926	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3927
3928	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3929	{
3930	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3931	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3932	}
3933	else
3934	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3935	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3936	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3937	{
3938	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3939	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3940	}
3941	}
3942	else
3943	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3944	break;
3945	}
3946	case SVGA_CMD_UPDATE:
3947	case SVGA_CMD_UPDATE_VERBOSE:
3948	{
3949	SVGAFifoCmdUpdate *pUpdate;
3950	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3951	if (enmCmdId == SVGA_CMD_UPDATE)
3952	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3953	else
3954	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3955	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3956	/** @todo Multiple screens? */
3957	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3958	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3959	break;
3960	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3961	break;
3962	}
3963
3964	case SVGA_CMD_DEFINE_CURSOR:
3965	{
3966	/* Followed by bitmap data. */
3967	SVGAFifoCmdDefineCursor *pCursor;
3968	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3969	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3970
3971	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3972	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3973	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3974	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3975	AssertBreak(pCursor->andMaskDepth <= 32);
3976	AssertBreak(pCursor->xorMaskDepth <= 32);
3977	RT_UNTRUSTED_VALIDATED_FENCE();
3978
3979	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3980	uint32_t cbAndMask = cbAndLine * pCursor->height;
3981	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3982	uint32_t cbXorMask = cbXorLine * pCursor->height;
3983	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3984
3985	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3986	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3987	break;
3988	}
3989
3990	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3991	{
3992	/* Followed by bitmap data. */
3993	uint32_t cbCursorShape, cbAndMask;
3994	uint8_t *pCursorCopy;
3995	uint32_t cbCmd;
3996
3997	SVGAFifoCmdDefineAlphaCursor *pCursor;
3998	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
3999	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
4000
4001	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
4002
4003	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
4004	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
4005	RT_UNTRUSTED_VALIDATED_FENCE();
4006
4007	/* Refetch the bitmap data as well. */
4008	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4009	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4010	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
4011
4012	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
4013	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
4014	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
4015	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
4016
4017	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
4018	AssertPtrBreak(pCursorCopy);
4019
4020	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
4021	memset(pCursorCopy, 0xff, cbAndMask);
4022	/* Colour data */
4023	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
4024
4025	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
4026	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
4027	break;
4028	}
4029
4030	case SVGA_CMD_MOVE_CURSOR:
4031	{
4032	/* Deprecated; there should be no driver which requires this command. However, if
4033	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4034	* alignment.
4035	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4036	*/
4037	SVGAFifoCmdMoveCursor *pMoveCursor;
4038	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
4039	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
4040
4041	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
4042	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4043	break;
4044	}
4045
4046	case SVGA_CMD_DISPLAY_CURSOR:
4047	{
4048	/* Deprecated; there should be no driver which requires this command. However, if
4049	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4050	* alignment.
4051	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4052	*/
4053	SVGAFifoCmdDisplayCursor *pDisplayCursor;
4054	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
4055	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
4056
4057	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
4058	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4059	break;
4060	}
4061
4062	case SVGA_CMD_RECT_FILL:
4063	{
4064	SVGAFifoCmdRectFill *pRectFill;
4065	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectFill, SVGAFifoCmdRectFill, sizeof(*pRectFill));
4066	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectFill);
4067
4068	Log(("vmsvgaR3FifoLoop: RECT FILL %08X @ %d,%d (%dx%d)\n", pRectFill->pixel, pRectFill->destX, pRectFill->destY, pRectFill->width, pRectFill->height));
4069	LogRelMax(4, ("Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4070	break;
4071	}
4072
4073	case SVGA_CMD_RECT_COPY:
4074	{
4075	SVGAFifoCmdRectCopy *pRectCopy;
4076	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectCopy, SVGAFifoCmdRectCopy, sizeof(*pRectCopy));
4077	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectCopy);
4078
4079	Log(("vmsvgaR3FifoLoop: RECT COPY %d,%d -> %d,%d (%dx%d)\n", pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height));
4080	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4081	AssertPtrBreak(pScreen);
4082
4083	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4084	AssertBreak(pRectCopy->srcX < pThis->svga.u32MaxWidth);
4085	AssertBreak(pRectCopy->destX < pThis->svga.u32MaxWidth);
4086	AssertBreak(pRectCopy->width < pThis->svga.u32MaxWidth);
4087	AssertBreak(pRectCopy->srcY < pThis->svga.u32MaxHeight);
4088	AssertBreak(pRectCopy->destY < pThis->svga.u32MaxHeight);
4089	AssertBreak(pRectCopy->height < pThis->svga.u32MaxHeight);
4090
4091	vmsvgaR3RectCopy(pThisCC, pScreen, pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY,
4092	pRectCopy->width, pRectCopy->height, pThis->vram_size);
4093	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height);
4094	break;
4095	}
4096
4097	case SVGA_CMD_RECT_ROP_COPY:
4098	{
4099	SVGAFifoCmdRectRopCopy *pRRCopy;
4100	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRRCopy, SVGAFifoCmdRectRopCopy, sizeof(*pRRCopy));
4101	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectRopCopy);
4102
4103	Log(("vmsvgaR3FifoLoop: RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4104	if (pRRCopy->rop != SVGA_ROP_COPY)
4105	{
4106	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4107	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4108	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4109	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4110	*/
4111	LogRelMax(4, ("RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4112	break;
4113	}
4114
4115	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4116	AssertPtrBreak(pScreen);
4117
4118	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4119	AssertBreak(pRRCopy->srcX < pThis->svga.u32MaxWidth);
4120	AssertBreak(pRRCopy->destX < pThis->svga.u32MaxWidth);
4121	AssertBreak(pRRCopy->width < pThis->svga.u32MaxWidth);
4122	AssertBreak(pRRCopy->srcY < pThis->svga.u32MaxHeight);
4123	AssertBreak(pRRCopy->destY < pThis->svga.u32MaxHeight);
4124	AssertBreak(pRRCopy->height < pThis->svga.u32MaxHeight);
4125
4126	vmsvgaR3RectCopy(pThisCC, pScreen, pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY,
4127	pRRCopy->width, pRRCopy->height, pThis->vram_size);
4128	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height);
4129	break;
4130	}
4131
4132	case SVGA_CMD_ESCAPE:
4133	{
4134	/* Followed by nsize bytes of data. */
4135	SVGAFifoCmdEscape *pEscape;
4136	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
4137	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
4138
4139	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
4140	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
4141	RT_UNTRUSTED_VALIDATED_FENCE();
4142	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
4143	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
4144
4145	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
4146	{
4147	AssertBreak(pEscape->size >= sizeof(uint32_t));
4148	RT_UNTRUSTED_VALIDATED_FENCE();
4149	uint32_t cmd = (uint32_t )(pEscape + 1);
4150	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
4151
4152	switch (cmd)
4153	{
4154	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4155	{
4156	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
4157	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
4158	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4159
4160	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
4161	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4162	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4163
4164	RT_NOREF_PV(pVideoCmd);
4165	break;
4166
4167	}
4168
4169	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4170	{
4171	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4172	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4173	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4174	RT_NOREF_PV(pVideoCmd);
4175	break;
4176	}
4177
4178	default:
4179	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4180	break;
4181	}
4182	}
4183	else
4184	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4185
4186	break;
4187	}
4188	# ifdef VBOX_WITH_VMSVGA3D
4189	case SVGA_CMD_DEFINE_GMR2:
4190	{
4191	SVGAFifoCmdDefineGMR2 *pCmd;
4192	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4193	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4194	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4195
4196	/* Validate current GMR id. */
4197	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4198	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4199	RT_UNTRUSTED_VALIDATED_FENCE();
4200
4201	if (!pCmd->numPages)
4202	{
4203	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4204	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4205	}
4206	else
4207	{
4208	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4209	if (pGMR->cMaxPages)
4210	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4211
4212	/* Not sure if we should always free the descriptor, but for simplicity
4213	we do so if the new size is smaller than the current. */
4214	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4215	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4216	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4217
4218	pGMR->cMaxPages = pCmd->numPages;
4219	/* The rest is done by the REMAP_GMR2 command. */
4220	}
4221	break;
4222	}
4223
4224	case SVGA_CMD_REMAP_GMR2:
4225	{
4226	/* Followed by page descriptors or guest ptr. */
4227	SVGAFifoCmdRemapGMR2 *pCmd;
4228	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4229	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4230
4231	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4232	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4233	RT_UNTRUSTED_VALIDATED_FENCE();
4234
4235	/* Calculate the size of what comes after next and fetch it. */
4236	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4237	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4238	cbCmd += sizeof(SVGAGuestPtr);
4239	else
4240	{
4241	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4242	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4243	{
4244	cbCmd += cbPageDesc;
4245	pCmd->numPages = 1;
4246	}
4247	else
4248	{
4249	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4250	cbCmd += cbPageDesc * pCmd->numPages;
4251	}
4252	}
4253	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4254
4255	/* Validate current GMR id and size. */
4256	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4257	RT_UNTRUSTED_VALIDATED_FENCE();
4258	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4259	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4260	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4261	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4262
4263	if (pCmd->numPages == 0)
4264	break;
4265
4266	/** @todo Move to a separate function vmsvgaGMRRemap() */
4267
4268	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4269	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4270
4271	/*
4272	* We flatten the existing descriptors into a page array, overwrite the
4273	* pages specified in this command and then recompress the descriptor.
4274	*/
4275	/** @todo Optimize the GMR remap algorithm! */
4276
4277	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4278	uint64_t *paNewPage64 = NULL;
4279	if (pGMR->paDesc)
4280	{
4281	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4282
4283	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4284	AssertPtrBreak(paNewPage64);
4285
4286	uint32_t idxPage = 0;
4287	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4288	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4289	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4290	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4291	RT_UNTRUSTED_VALIDATED_FENCE();
4292	}
4293
4294	/* Free the old GMR if present. */
4295	if (pGMR->paDesc)
4296	RTMemFree(pGMR->paDesc);
4297
4298	/* Allocate the maximum amount possible (everything non-continuous) */
4299	PVMSVGAGMRDESCRIPTOR paDescs;
4300	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4301	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4302
4303	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4304	{
4305	/** @todo */
4306	AssertFailed();
4307	pGMR->numDescriptors = 0;
4308	}
4309	else
4310	{
4311	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4312	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4313	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4314
4315	if (paNewPage64)
4316	{
4317	/* Overwrite the old page array with the new page values. */
4318	if (fGCPhys64)
4319	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4320	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4321	else
4322	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4323	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4324
4325	/* Use the updated page array instead of the command data. */
4326	fGCPhys64 = true;
4327	paPages64 = paNewPage64;
4328	pCmd->numPages = cNewTotalPages;
4329	}
4330
4331	/* The first page. */
4332	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4333	* applied to paNewPage64. */
4334	RTGCPHYS GCPhys;
4335	if (fGCPhys64)
4336	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4337	else
4338	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4339	paDescs[0].GCPhys = GCPhys;
4340	paDescs[0].numPages = 1;
4341
4342	/* Subsequent pages. */
4343	uint32_t iDescriptor = 0;
4344	for (uint32_t i = 1; i < pCmd->numPages; i++)
4345	{
4346	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4347	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4348	else
4349	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4350
4351	/* Continuous physical memory? */
4352	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4353	{
4354	Assert(paDescs[iDescriptor].numPages);
4355	paDescs[iDescriptor].numPages++;
4356	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4357	}
4358	else
4359	{
4360	iDescriptor++;
4361	paDescs[iDescriptor].GCPhys = GCPhys;
4362	paDescs[iDescriptor].numPages = 1;
4363	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4364	}
4365	}
4366
4367	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4368	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4369	pGMR->numDescriptors = iDescriptor + 1;
4370	}
4371
4372	if (paNewPage64)
4373	RTMemFree(paNewPage64);
4374
4375	# ifdef DEBUG_GMR_ACCESS
4376	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4377	# endif
4378	break;
4379	}
4380	# endif // VBOX_WITH_VMSVGA3D
4381	case SVGA_CMD_DEFINE_SCREEN:
4382	{
4383	/* The size of this command is specified by the guest and depends on capabilities. */
4384	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4385
4386	SVGAFifoCmdDefineScreen *pCmd;
4387	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4388	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4389	RT_UNTRUSTED_VALIDATED_FENCE();
4390
4391	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4392	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4393	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4394
4395	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4396	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4397	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4398
4399	uint32_t const idScreen = pCmd->screen.id;
4400	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4401
4402	uint32_t const uWidth = pCmd->screen.size.width;
4403	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4404
4405	uint32_t const uHeight = pCmd->screen.size.height;
4406	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4407
4408	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4409	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4410	AssertBreak(cbWidth <= cbPitch);
4411
4412	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4413	AssertBreak(uScreenOffset < pThis->vram_size);
4414
4415	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4416	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4417	AssertBreak( (uHeight == 0 && cbPitch == 0)
4418	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4419	RT_UNTRUSTED_VALIDATED_FENCE();
4420
4421	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4422
4423	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4424
4425	pScreen->fDefined = true;
4426	pScreen->fModified = true;
4427	pScreen->fuScreen = pCmd->screen.flags;
4428	pScreen->idScreen = idScreen;
4429	if (!fBlank)
4430	{
4431	AssertBreak(uWidth > 0 && uHeight > 0);
4432
4433	pScreen->xOrigin = pCmd->screen.root.x;
4434	pScreen->yOrigin = pCmd->screen.root.y;
4435	pScreen->cWidth = uWidth;
4436	pScreen->cHeight = uHeight;
4437	pScreen->offVRAM = uScreenOffset;
4438	pScreen->cbPitch = cbPitch;
4439	pScreen->cBpp = 32;
4440	}
4441	else
4442	{
4443	/* Keep old values. */
4444	}
4445
4446	pThis->svga.fGFBRegisters = false;
4447	vmsvgaR3ChangeMode(pThis, pThisCC);
4448
4449	# ifdef VBOX_WITH_VMSVGA3D
4450	vmsvga3dDefineScreen(pThisCC, pScreen);
4451	# endif
4452	break;
4453	}
4454
4455	case SVGA_CMD_DESTROY_SCREEN:
4456	{
4457	SVGAFifoCmdDestroyScreen *pCmd;
4458	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4459	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4460
4461	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4462
4463	uint32_t const idScreen = pCmd->screenId;
4464	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4465	RT_UNTRUSTED_VALIDATED_FENCE();
4466
4467	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4468	pScreen->fModified = true;
4469	pScreen->fDefined = false;
4470	pScreen->idScreen = idScreen;
4471
4472	# ifdef VBOX_WITH_VMSVGA3D
4473	vmsvga3dDestroyScreen(pThisCC, pScreen);
4474	# endif
4475	vmsvgaR3ChangeMode(pThis, pThisCC);
4476	break;
4477	}
4478
4479	case SVGA_CMD_DEFINE_GMRFB:
4480	{
4481	SVGAFifoCmdDefineGMRFB *pCmd;
4482	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4483	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4484
4485	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4486	pSVGAState->GMRFB.ptr = pCmd->ptr;
4487	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4488	pSVGAState->GMRFB.format = pCmd->format;
4489	break;
4490	}
4491
4492	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4493	{
4494	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4495	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4496	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4497
4498	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4499	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4500
4501	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4502	RT_UNTRUSTED_VALIDATED_FENCE();
4503
4504	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4505	AssertPtrBreak(pScreen);
4506
4507	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4508	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4509
4510	/* Clip destRect to the screen dimensions. */
4511	SVGASignedRect screenRect;
4512	screenRect.left = 0;
4513	screenRect.top = 0;
4514	screenRect.right = pScreen->cWidth;
4515	screenRect.bottom = pScreen->cHeight;
4516	SVGASignedRect clipRect = pCmd->destRect;
4517	vmsvgaR3ClipRect(&screenRect, &clipRect);
4518	RT_UNTRUSTED_VALIDATED_FENCE();
4519
4520	uint32_t const width = clipRect.right - clipRect.left;
4521	uint32_t const height = clipRect.bottom - clipRect.top;
4522
4523	if ( width == 0
4524	\|\| height == 0)
4525	break; /* Nothing to do. */
4526
4527	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4528	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4529
4530	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4531	* Prepare parameters for vmsvgaR3GmrTransfer.
4532	*/
4533	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4534
4535	/* Destination: host buffer which describes the screen 0 VRAM.
4536	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4537	*/
4538	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4539	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4540	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4541	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4542	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4543	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4544	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4545	+ cbScanline * clipRect.top;
4546	int32_t const cbHstPitch = cbScanline;
4547
4548	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4549	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4550	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4551	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4552	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4553
4554	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4555	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4556	gstPtr, offGst, cbGstPitch,
4557	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4558	AssertRC(rc);
4559	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4560	break;
4561	}
4562
4563	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4564	{
4565	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4566	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4567	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4568
4569	/* Note! This can fetch 3d render results as well!! */
4570	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4571	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4572
4573	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4574	RT_UNTRUSTED_VALIDATED_FENCE();
4575
4576	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4577	AssertPtrBreak(pScreen);
4578
4579	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4580	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4581
4582	/* Clip destRect to the screen dimensions. */
4583	SVGASignedRect screenRect;
4584	screenRect.left = 0;
4585	screenRect.top = 0;
4586	screenRect.right = pScreen->cWidth;
4587	screenRect.bottom = pScreen->cHeight;
4588	SVGASignedRect clipRect = pCmd->srcRect;
4589	vmsvgaR3ClipRect(&screenRect, &clipRect);
4590	RT_UNTRUSTED_VALIDATED_FENCE();
4591
4592	uint32_t const width = clipRect.right - clipRect.left;
4593	uint32_t const height = clipRect.bottom - clipRect.top;
4594
4595	if ( width == 0
4596	\|\| height == 0)
4597	break; /* Nothing to do. */
4598
4599	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4600	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4601
4602	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4603	* Prepare parameters for vmsvgaR3GmrTransfer.
4604	*/
4605	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4606
4607	/* Source: host buffer which describes the screen 0 VRAM.
4608	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4609	*/
4610	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4611	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4612	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4613	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4614	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4615	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4616	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4617	+ cbScanline * clipRect.top;
4618	int32_t const cbHstPitch = cbScanline;
4619
4620	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4621	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4622	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4623	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4624	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4625
4626	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4627	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4628	gstPtr, offGst, cbGstPitch,
4629	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4630	AssertRC(rc);
4631	break;
4632	}
4633
4634	case SVGA_CMD_ANNOTATION_FILL:
4635	{
4636	SVGAFifoCmdAnnotationFill *pCmd;
4637	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4638	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4639
4640	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4641	pSVGAState->colorAnnotation = pCmd->color;
4642	break;
4643	}
4644
4645	case SVGA_CMD_ANNOTATION_COPY:
4646	{
4647	SVGAFifoCmdAnnotationCopy *pCmd;
4648	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4649	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4650
4651	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4652	AssertFailed();
4653	break;
4654	}
4655
4656	default:
4657	# ifdef VBOX_WITH_VMSVGA3D
4658	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4659	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4660	{
4661	RT_UNTRUSTED_VALIDATED_FENCE();
4662
4663	/* All 3d commands start with a common header, which defines the size of the command. */
4664	SVGA3dCmdHeader *pHdr;
4665	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4666	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4667	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4668	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4669
4670	if (RT_LIKELY(pThis->svga.f3DEnabled))
4671	{ /* likely */ }
4672	else
4673	{
4674	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4675	break;
4676	}
4677
4678	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4679	* Check that the 3D command has at least a_cbMin of payload bytes after the
4680	* header. Will break out of the switch if it doesn't.
4681	*/
4682	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4683	if (1) { \
4684	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4685	RT_UNTRUSTED_VALIDATED_FENCE(); \
4686	} else do {} while (0)
4687	switch ((int)enmCmdId)
4688	{
4689	case SVGA_3D_CMD_SURFACE_DEFINE:
4690	{
4691	uint32_t cMipLevels;
4692	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4693	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4694	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4695
4696	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4697	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4698	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4699	# ifdef DEBUG_GMR_ACCESS
4700	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4701	# endif
4702	break;
4703	}
4704
4705	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4706	{
4707	uint32_t cMipLevels;
4708	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4709	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4710	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4711
4712	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4713	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4714	pCmd->multisampleCount, pCmd->autogenFilter,
4715	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4716	break;
4717	}
4718
4719	case SVGA_3D_CMD_SURFACE_DESTROY:
4720	{
4721	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4722	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4723	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4724	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4725	break;
4726	}
4727
4728	case SVGA_3D_CMD_SURFACE_COPY:
4729	{
4730	uint32_t cCopyBoxes;
4731	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4732	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4733	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4734
4735	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4736	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4737	break;
4738	}
4739
4740	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4741	{
4742	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4743	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4744	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4745
4746	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4747	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4748	break;
4749	}
4750
4751	case SVGA_3D_CMD_SURFACE_DMA:
4752	{
4753	uint32_t cCopyBoxes;
4754	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4755	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4756	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4757
4758	uint64_t u64NanoTS = 0;
4759	if (LogRelIs3Enabled())
4760	u64NanoTS = RTTimeNanoTS();
4761	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4762	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4763	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4764	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4765	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4766	if (LogRelIs3Enabled())
4767	{
4768	if (cCopyBoxes)
4769	{
4770	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4771	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4772	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4773	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4774	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4775	}
4776	}
4777	break;
4778	}
4779
4780	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4781	{
4782	uint32_t cRects;
4783	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4784	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4785	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4786
4787	static uint64_t u64FrameStartNanoTS = 0;
4788	static uint64_t u64ElapsedPerSecNano = 0;
4789	static int cFrames = 0;
4790	uint64_t u64NanoTS = 0;
4791	if (LogRelIs3Enabled())
4792	u64NanoTS = RTTimeNanoTS();
4793	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4794	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4795	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4796	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4797	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4798	if (LogRelIs3Enabled())
4799	{
4800	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4801	u64ElapsedPerSecNano += u64ElapsedNano;
4802
4803	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4804	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4805	(u64ElapsedNano) / 1000ULL, cRects,
4806	pFirstRect->left, pFirstRect->top,
4807	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4808
4809	++cFrames;
4810	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4811	{
4812	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4813	cFrames, u64ElapsedPerSecNano / 1000ULL));
4814	u64FrameStartNanoTS = u64NanoTS;
4815	cFrames = 0;
4816	u64ElapsedPerSecNano = 0;
4817	}
4818	}
4819	break;
4820	}
4821
4822	case SVGA_3D_CMD_CONTEXT_DEFINE:
4823	{
4824	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4825	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4826	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4827
4828	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4829	break;
4830	}
4831
4832	case SVGA_3D_CMD_CONTEXT_DESTROY:
4833	{
4834	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4835	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4836	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4837
4838	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4839	break;
4840	}
4841
4842	case SVGA_3D_CMD_SETTRANSFORM:
4843	{
4844	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4845	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4846	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4847
4848	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4849	break;
4850	}
4851
4852	case SVGA_3D_CMD_SETZRANGE:
4853	{
4854	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4855	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4856	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4857
4858	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4859	break;
4860	}
4861
4862	case SVGA_3D_CMD_SETRENDERSTATE:
4863	{
4864	uint32_t cRenderStates;
4865	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4866	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4867	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4868
4869	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4870	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4871	break;
4872	}
4873
4874	case SVGA_3D_CMD_SETRENDERTARGET:
4875	{
4876	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4877	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4878	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4879
4880	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4881	break;
4882	}
4883
4884	case SVGA_3D_CMD_SETTEXTURESTATE:
4885	{
4886	uint32_t cTextureStates;
4887	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4888	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4889	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4890
4891	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4892	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4893	break;
4894	}
4895
4896	case SVGA_3D_CMD_SETMATERIAL:
4897	{
4898	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4899	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4900	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4901
4902	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4903	break;
4904	}
4905
4906	case SVGA_3D_CMD_SETLIGHTDATA:
4907	{
4908	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4909	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4910	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4911
4912	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4913	break;
4914	}
4915
4916	case SVGA_3D_CMD_SETLIGHTENABLED:
4917	{
4918	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4919	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4920	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4921
4922	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4923	break;
4924	}
4925
4926	case SVGA_3D_CMD_SETVIEWPORT:
4927	{
4928	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4929	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4930	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4931
4932	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4933	break;
4934	}
4935
4936	case SVGA_3D_CMD_SETCLIPPLANE:
4937	{
4938	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4939	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4940	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4941
4942	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4943	break;
4944	}
4945
4946	case SVGA_3D_CMD_CLEAR:
4947	{
4948	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4949	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4950	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4951
4952	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4953	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4954	break;
4955	}
4956
4957	case SVGA_3D_CMD_PRESENT:
4958	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4959	{
4960	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4961	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4962	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4963	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4964	else
4965	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4966
4967	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4968
4969	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4970	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4971	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4972	break;
4973	}
4974
4975	case SVGA_3D_CMD_SHADER_DEFINE:
4976	{
4977	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4978	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4979	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4980
4981	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4982	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4983	break;
4984	}
4985
4986	case SVGA_3D_CMD_SHADER_DESTROY:
4987	{
4988	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
4989	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4990	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
4991
4992	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
4993	break;
4994	}
4995
4996	case SVGA_3D_CMD_SET_SHADER:
4997	{
4998	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
4999	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5000	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
5001
5002	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
5003	break;
5004	}
5005
5006	case SVGA_3D_CMD_SET_SHADER_CONST:
5007	{
5008	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
5009	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5010	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
5011
5012	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
5013	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
5014	break;
5015	}
5016
5017	case SVGA_3D_CMD_DRAW_PRIMITIVES:
5018	{
5019	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
5020	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5021	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
5022
5023	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
5024	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
5025	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
5026	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
5027	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
5028
5029	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
5030	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
5031
5032	RT_UNTRUSTED_VALIDATED_FENCE();
5033
5034	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
5035	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
5036	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
5037
5038	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5039	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
5040	pNumRange, cVertexDivisor, pVertexDivisor);
5041	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5042	break;
5043	}
5044
5045	case SVGA_3D_CMD_SETSCISSORRECT:
5046	{
5047	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
5048	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5049	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
5050
5051	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
5052	break;
5053	}
5054
5055	case SVGA_3D_CMD_BEGIN_QUERY:
5056	{
5057	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
5058	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5059	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
5060
5061	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5062	break;
5063	}
5064
5065	case SVGA_3D_CMD_END_QUERY:
5066	{
5067	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
5068	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5069	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
5070
5071	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5072	break;
5073	}
5074
5075	case SVGA_3D_CMD_WAIT_FOR_QUERY:
5076	{
5077	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
5078	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5079	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
5080
5081	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5082	break;
5083	}
5084
5085	case SVGA_3D_CMD_GENERATE_MIPMAPS:
5086	{
5087	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
5088	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5089	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
5090
5091	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5092	break;
5093	}
5094
5095	case SVGA_3D_CMD_ACTIVATE_SURFACE:
5096	/* context id + surface id? */
5097	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
5098	break;
5099	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5100	/* context id + surface id? */
5101	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
5102	break;
5103
5104	default:
5105	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5106	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5107	break;
5108	}
5109	}
5110	else
5111	# endif // VBOX_WITH_VMSVGA3D
5112	{
5113	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5114	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5115	}
5116	}
5117
5118	/* Go to the next slot */
5119	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5120	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5121	if (offCurrentCmd >= offFifoMax)
5122	{
5123	offCurrentCmd -= offFifoMax - offFifoMin;
5124	Assert(offCurrentCmd >= offFifoMin);
5125	Assert(offCurrentCmd < offFifoMax);
5126	}
5127	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5128	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5129
5130	/*
5131	* Raise IRQ if required. Must enter the critical section here
5132	* before making final decisions here, otherwise cubebench and
5133	* others may end up waiting forever.
5134	*/
5135	if ( u32IrqStatus
5136	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5137	{
5138	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5139	AssertRC(rc2);
5140
5141	/* FIFO progress might trigger an interrupt. */
5142	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5143	{
5144	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5145	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5146	}
5147
5148	/* Unmasked IRQ pending? */
5149	if (pThis->svga.u32IrqMask & u32IrqStatus)
5150	{
5151	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5152	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5153	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5154	}
5155
5156	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5157	}
5158	}
5159
5160	/* If really done, clear the busy flag. */
5161	if (fDone)
5162	{
5163	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5164	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5165	}
5166	}
5167
5168	/*
5169	* Free the bounce buffer. (There are no returns above!)
5170	*/
5171	RTMemFree(pbBounceBuf);
5172
5173	return VINF_SUCCESS;
5174	}
5175
5176	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5177	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5178	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5179
5180	#ifdef VBOX_WITH_VMSVGA3D
5181	/**
5182	* Free the specified GMR
5183	*
5184	* @param pThisCC The VGA/VMSVGA state for ring-3.
5185	* @param idGMR GMR id
5186	*/
5187	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5188	{
5189	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5190
5191	/* Free the old descriptor if present. */
5192	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5193	if ( pGMR->numDescriptors
5194	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5195	{
5196	# ifdef DEBUG_GMR_ACCESS
5197	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5198	# endif
5199
5200	Assert(pGMR->paDesc);
5201	RTMemFree(pGMR->paDesc);
5202	pGMR->paDesc = NULL;
5203	pGMR->numDescriptors = 0;
5204	pGMR->cbTotal = 0;
5205	pGMR->cMaxPages = 0;
5206	}
5207	Assert(!pGMR->cMaxPages);
5208	Assert(!pGMR->cbTotal);
5209	}
5210	#endif /* VBOX_WITH_VMSVGA3D */
5211
5212	/**
5213	* Copy between a GMR and a host memory buffer.
5214	*
5215	* @returns VBox status code.
5216	* @param pThis The shared VGA/VMSVGA instance data.
5217	* @param pThisCC The VGA/VMSVGA state for ring-3.
5218	* @param enmTransferType Transfer type (read/write)
5219	* @param pbHstBuf Host buffer pointer (valid)
5220	* @param cbHstBuf Size of host buffer (valid)
5221	* @param offHst Host buffer offset of the first scanline
5222	* @param cbHstPitch Destination buffer pitch
5223	* @param gstPtr GMR description
5224	* @param offGst Guest buffer offset of the first scanline
5225	* @param cbGstPitch Guest buffer pitch
5226	* @param cbWidth Width in bytes to copy
5227	* @param cHeight Number of scanllines to copy
5228	*/
5229	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5230	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5231	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5232	uint32_t cbWidth, uint32_t cHeight)
5233	{
5234	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5235	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5236	int rc;
5237
5238	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5239	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5240	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5241	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5242	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5243
5244	PGMR pGMR;
5245	uint32_t cbGmr; /* The GMR size in bytes. */
5246	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5247	{
5248	pGMR = NULL;
5249	cbGmr = pThis->vram_size;
5250	}
5251	else
5252	{
5253	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5254	RT_UNTRUSTED_VALIDATED_FENCE();
5255	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5256	cbGmr = pGMR->cbTotal;
5257	}
5258
5259	/*
5260	* GMR
5261	*/
5262	/* Calculate GMR offset of the data to be copied. */
5263	AssertMsgReturn(gstPtr.offset < cbGmr,
5264	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5265	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5266	VERR_INVALID_PARAMETER);
5267	RT_UNTRUSTED_VALIDATED_FENCE();
5268	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5269	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5270	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5271	VERR_INVALID_PARAMETER);
5272	RT_UNTRUSTED_VALIDATED_FENCE();
5273	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5274
5275	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5276	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5277	AssertMsgReturn(cbGmrScanline != 0,
5278	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5279	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5280	VERR_INVALID_PARAMETER);
5281	RT_UNTRUSTED_VALIDATED_FENCE();
5282	AssertMsgReturn(cbWidth <= cbGmrScanline,
5283	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5284	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5285	VERR_INVALID_PARAMETER);
5286	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5287	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5288	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5289	VERR_INVALID_PARAMETER);
5290	RT_UNTRUSTED_VALIDATED_FENCE();
5291
5292	/* How many bytes are available for the data in the GMR. */
5293	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5294
5295	/* How many scanlines would fit into the available data. */
5296	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5297	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5298	if (cbWidth <= cbGmrLastScanline)
5299	++cGmrScanlines;
5300
5301	if (cHeight > cGmrScanlines)
5302	cHeight = cGmrScanlines;
5303
5304	AssertMsgReturn(cHeight > 0,
5305	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5306	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5307	VERR_INVALID_PARAMETER);
5308	RT_UNTRUSTED_VALIDATED_FENCE();
5309
5310	/*
5311	* Host buffer.
5312	*/
5313	AssertMsgReturn(offHst < cbHstBuf,
5314	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5315	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5316	VERR_INVALID_PARAMETER);
5317
5318	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5319	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5320	AssertMsgReturn(cbHstScanline != 0,
5321	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5322	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5323	VERR_INVALID_PARAMETER);
5324	AssertMsgReturn(cbWidth <= cbHstScanline,
5325	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5326	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5327	VERR_INVALID_PARAMETER);
5328	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5329	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5330	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5331	VERR_INVALID_PARAMETER);
5332
5333	/* How many bytes are available for the data in the buffer. */
5334	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5335
5336	/* How many scanlines would fit into the available data. */
5337	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5338	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5339	if (cbWidth <= cbHstLastScanline)
5340	++cHstScanlines;
5341
5342	if (cHeight > cHstScanlines)
5343	cHeight = cHstScanlines;
5344
5345	AssertMsgReturn(cHeight > 0,
5346	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5347	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5348	VERR_INVALID_PARAMETER);
5349
5350	uint8_t *pbHst = pbHstBuf + offHst;
5351
5352	/* Shortcut for the framebuffer. */
5353	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5354	{
5355	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5356
5357	uint8_t const *pbSrc;
5358	int32_t cbSrcPitch;
5359	uint8_t *pbDst;
5360	int32_t cbDstPitch;
5361
5362	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5363	{
5364	pbSrc = pbHst;
5365	cbSrcPitch = cbHstPitch;
5366	pbDst = pbGst;
5367	cbDstPitch = cbGstPitch;
5368	}
5369	else
5370	{
5371	pbSrc = pbGst;
5372	cbSrcPitch = cbGstPitch;
5373	pbDst = pbHst;
5374	cbDstPitch = cbHstPitch;
5375	}
5376
5377	if ( cbWidth == (uint32_t)cbGstPitch
5378	&& cbGstPitch == cbHstPitch)
5379	{
5380	/* Entire scanlines, positive pitch. */
5381	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5382	}
5383	else
5384	{
5385	for (uint32_t i = 0; i < cHeight; ++i)
5386	{
5387	memcpy(pbDst, pbSrc, cbWidth);
5388
5389	pbDst += cbDstPitch;
5390	pbSrc += cbSrcPitch;
5391	}
5392	}
5393	return VINF_SUCCESS;
5394	}
5395
5396	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5397	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5398
5399	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5400	uint32_t iDesc = 0; /* Index in the descriptor array. */
5401	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5402	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5403	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5404	for (uint32_t i = 0; i < cHeight; ++i)
5405	{
5406	uint32_t cbCurrentWidth = cbWidth;
5407	uint32_t offGmrCurrent = offGmrScanline;
5408	uint8_t *pbCurrentHost = pbHstScanline;
5409
5410	/* Find the right descriptor */
5411	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5412	{
5413	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5414	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5415	++iDesc;
5416	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5417	}
5418
5419	while (cbCurrentWidth)
5420	{
5421	uint32_t cbToCopy;
5422
5423	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5424	{
5425	cbToCopy = cbCurrentWidth;
5426	}
5427	else
5428	{
5429	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5430	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5431	}
5432
5433	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5434
5435	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5436
5437	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5438	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5439	else
5440	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5441	AssertRCBreak(rc);
5442
5443	cbCurrentWidth -= cbToCopy;
5444	offGmrCurrent += cbToCopy;
5445	pbCurrentHost += cbToCopy;
5446
5447	/* Go to the next descriptor if there's anything left. */
5448	if (cbCurrentWidth)
5449	{
5450	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5451	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5452	++iDesc;
5453	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5454	}
5455	}
5456
5457	offGmrScanline += cbGstPitch;
5458	pbHstScanline += cbHstPitch;
5459	}
5460
5461	return VINF_SUCCESS;
5462	}
5463
5464
5465	/**
5466	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5467	*
5468	* @param pSizeSrc Source surface dimensions.
5469	* @param pSizeDest Destination surface dimensions.
5470	* @param pBox Coordinates to be clipped.
5471	*/
5472	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5473	{
5474	/* Src x, w */
5475	if (pBox->srcx > pSizeSrc->width)
5476	pBox->srcx = pSizeSrc->width;
5477	if (pBox->w > pSizeSrc->width - pBox->srcx)
5478	pBox->w = pSizeSrc->width - pBox->srcx;
5479
5480	/* Src y, h */
5481	if (pBox->srcy > pSizeSrc->height)
5482	pBox->srcy = pSizeSrc->height;
5483	if (pBox->h > pSizeSrc->height - pBox->srcy)
5484	pBox->h = pSizeSrc->height - pBox->srcy;
5485
5486	/* Src z, d */
5487	if (pBox->srcz > pSizeSrc->depth)
5488	pBox->srcz = pSizeSrc->depth;
5489	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5490	pBox->d = pSizeSrc->depth - pBox->srcz;
5491
5492	/* Dest x, w */
5493	if (pBox->x > pSizeDest->width)
5494	pBox->x = pSizeDest->width;
5495	if (pBox->w > pSizeDest->width - pBox->x)
5496	pBox->w = pSizeDest->width - pBox->x;
5497
5498	/* Dest y, h */
5499	if (pBox->y > pSizeDest->height)
5500	pBox->y = pSizeDest->height;
5501	if (pBox->h > pSizeDest->height - pBox->y)
5502	pBox->h = pSizeDest->height - pBox->y;
5503
5504	/* Dest z, d */
5505	if (pBox->z > pSizeDest->depth)
5506	pBox->z = pSizeDest->depth;
5507	if (pBox->d > pSizeDest->depth - pBox->z)
5508	pBox->d = pSizeDest->depth - pBox->z;
5509	}
5510
5511	/**
5512	* Unsigned coordinates in pBox. Clip to [0; pSize).
5513	*
5514	* @param pSize Source surface dimensions.
5515	* @param pBox Coordinates to be clipped.
5516	*/
5517	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5518	{
5519	/* x, w */
5520	if (pBox->x > pSize->width)
5521	pBox->x = pSize->width;
5522	if (pBox->w > pSize->width - pBox->x)
5523	pBox->w = pSize->width - pBox->x;
5524
5525	/* y, h */
5526	if (pBox->y > pSize->height)
5527	pBox->y = pSize->height;
5528	if (pBox->h > pSize->height - pBox->y)
5529	pBox->h = pSize->height - pBox->y;
5530
5531	/* z, d */
5532	if (pBox->z > pSize->depth)
5533	pBox->z = pSize->depth;
5534	if (pBox->d > pSize->depth - pBox->z)
5535	pBox->d = pSize->depth - pBox->z;
5536	}
5537
5538	/**
5539	* Clip.
5540	*
5541	* @param pBound Bounding rectangle.
5542	* @param pRect Rectangle to be clipped.
5543	*/
5544	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5545	{
5546	int32_t left;
5547	int32_t top;
5548	int32_t right;
5549	int32_t bottom;
5550
5551	/* Right order. */
5552	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5553	if (pRect->left < pRect->right)
5554	{
5555	left = pRect->left;
5556	right = pRect->right;
5557	}
5558	else
5559	{
5560	left = pRect->right;
5561	right = pRect->left;
5562	}
5563	if (pRect->top < pRect->bottom)
5564	{
5565	top = pRect->top;
5566	bottom = pRect->bottom;
5567	}
5568	else
5569	{
5570	top = pRect->bottom;
5571	bottom = pRect->top;
5572	}
5573
5574	if (left < pBound->left)
5575	left = pBound->left;
5576	if (right < pBound->left)
5577	right = pBound->left;
5578
5579	if (left > pBound->right)
5580	left = pBound->right;
5581	if (right > pBound->right)
5582	right = pBound->right;
5583
5584	if (top < pBound->top)
5585	top = pBound->top;
5586	if (bottom < pBound->top)
5587	bottom = pBound->top;
5588
5589	if (top > pBound->bottom)
5590	top = pBound->bottom;
5591	if (bottom > pBound->bottom)
5592	bottom = pBound->bottom;
5593
5594	pRect->left = left;
5595	pRect->right = right;
5596	pRect->top = top;
5597	pRect->bottom = bottom;
5598	}
5599
5600	/**
5601	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5602	* Unblock the FIFO I/O thread so it can respond to a state change.}
5603	*/
5604	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5605	{
5606	RT_NOREF(pDevIns);
5607	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5608	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5609	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5610	}
5611
5612	/**
5613	* Enables or disables dirty page tracking for the framebuffer
5614	*
5615	* @param pDevIns The device instance.
5616	* @param pThis The shared VGA/VMSVGA instance data.
5617	* @param fTraces Enable/disable traces
5618	*/
5619	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5620	{
5621	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5622	&& !fTraces)
5623	{
5624	//Assert(pThis->svga.fTraces);
5625	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5626	return;
5627	}
5628
5629	pThis->svga.fTraces = fTraces;
5630	if (pThis->svga.fTraces)
5631	{
5632	unsigned cbFrameBuffer = pThis->vram_size;
5633
5634	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5635	/** @todo How does this work with screens? */
5636	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5637	{
5638	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5639	Assert(pThis->svga.cbScanline);
5640	# endif
5641	/* Hardware enabled; return real framebuffer size .*/
5642	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5643	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5644	}
5645
5646	if (!pThis->svga.fVRAMTracking)
5647	{
5648	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5649	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5650	pThis->svga.fVRAMTracking = true;
5651	}
5652	}
5653	else
5654	{
5655	if (pThis->svga.fVRAMTracking)
5656	{
5657	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5658	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5659	pThis->svga.fVRAMTracking = false;
5660	}
5661	}
5662	}
5663
5664	/**
5665	* @callback_method_impl{FNPCIIOREGIONMAP}
5666	*/
5667	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5668	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5669	{
5670	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5671	int rc;
5672	RT_NOREF(pPciDev);
5673	Assert(pPciDev == pDevIns->apPciDevs[0]);
5674
5675	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5676	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5677	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5678	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5679	, VERR_INTERNAL_ERROR);
5680	if (GCPhysAddress != NIL_RTGCPHYS)
5681	{
5682	/*
5683	* Mapping the FIFO RAM.
5684	*/
5685	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5686	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5687	AssertRC(rc);
5688
5689	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5690	if (RT_SUCCESS(rc))
5691	{
5692	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5693	# ifdef DEBUG_FIFO_ACCESS
5694	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5695	# else
5696	GCPhysAddress + PAGE_SIZE - 1,
5697	# endif
5698	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5699	"VMSVGA FIFO");
5700	AssertRC(rc);
5701	}
5702	# endif
5703	if (RT_SUCCESS(rc))
5704	{
5705	pThis->svga.GCPhysFIFO = GCPhysAddress;
5706	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5707	}
5708	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite erros here. */
5709	}
5710	else
5711	{
5712	Assert(pThis->svga.GCPhysFIFO);
5713	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5714	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5715	AssertRC(rc);
5716	# else
5717	rc = VINF_SUCCESS;
5718	# endif
5719	pThis->svga.GCPhysFIFO = 0;
5720	}
5721	return rc;
5722	}
5723
5724	# ifdef VBOX_WITH_VMSVGA3D
5725
5726	/**
5727	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5728	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5729	*
5730	* @param pDevIns The device instance.
5731	* @param pThis The The shared VGA/VMSVGA instance data.
5732	* @param pThisCC The VGA/VMSVGA state for ring-3.
5733	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5734	* UINT32_MAX is used, all surfaces are processed.
5735	*/
5736	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5737	{
5738	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5739	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5740	}
5741
5742
5743	/**
5744	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5745	*/
5746	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5747	{
5748	/* There might be a specific surface ID at the start of the
5749	arguments, if not show all surfaces. */
5750	uint32_t sid = UINT32_MAX;
5751	if (pszArgs)
5752	pszArgs = RTStrStripL(pszArgs);
5753	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5754	sid = RTStrToUInt32(pszArgs);
5755
5756	/* Verbose or terse display, we default to verbose. */
5757	bool fVerbose = true;
5758	if (RTStrIStr(pszArgs, "terse"))
5759	fVerbose = false;
5760
5761	/* The size of the ascii art (x direction, y is 3/4 of x). */
5762	uint32_t cxAscii = 80;
5763	if (RTStrIStr(pszArgs, "gigantic"))
5764	cxAscii = 300;
5765	else if (RTStrIStr(pszArgs, "huge"))
5766	cxAscii = 180;
5767	else if (RTStrIStr(pszArgs, "big"))
5768	cxAscii = 132;
5769	else if (RTStrIStr(pszArgs, "normal"))
5770	cxAscii = 80;
5771	else if (RTStrIStr(pszArgs, "medium"))
5772	cxAscii = 64;
5773	else if (RTStrIStr(pszArgs, "small"))
5774	cxAscii = 48;
5775	else if (RTStrIStr(pszArgs, "tiny"))
5776	cxAscii = 24;
5777
5778	/* Y invert the image when producing the ASCII art. */
5779	bool fInvY = false;
5780	if (RTStrIStr(pszArgs, "invy"))
5781	fInvY = true;
5782
5783	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5784	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5785	}
5786
5787
5788	/**
5789	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5790	*/
5791	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5792	{
5793	/* pszArg = "sid[>dir]"
5794	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5795	*/
5796	char *pszBitmapPath = NULL;
5797	uint32_t sid = UINT32_MAX;
5798	if (pszArgs)
5799	pszArgs = RTStrStripL(pszArgs);
5800	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5801	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5802	if ( pszBitmapPath
5803	&& *pszBitmapPath == '>')
5804	++pszBitmapPath;
5805
5806	const bool fVerbose = true;
5807	const uint32_t cxAscii = 0; /* No ASCII */
5808	const bool fInvY = false; /* Do not invert. */
5809	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5810	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5811	}
5812
5813	/**
5814	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5815	*/
5816	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5817	{
5818	/* There might be a specific surface ID at the start of the
5819	arguments, if not show all contexts. */
5820	uint32_t sid = UINT32_MAX;
5821	if (pszArgs)
5822	pszArgs = RTStrStripL(pszArgs);
5823	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5824	sid = RTStrToUInt32(pszArgs);
5825
5826	/* Verbose or terse display, we default to verbose. */
5827	bool fVerbose = true;
5828	if (RTStrIStr(pszArgs, "terse"))
5829	fVerbose = false;
5830
5831	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5832	}
5833	# endif /* VBOX_WITH_VMSVGA3D */
5834
5835	/**
5836	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5837	*/
5838	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5839	{
5840	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5841	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5842	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5843	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5844	RT_NOREF(pszArgs);
5845
5846	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5847	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5848	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5849	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5850	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5851	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5852	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5853	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5854	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5855	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5856	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5857	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5858	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5859	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5860	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5861	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5862	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5863	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5864	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5865	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5866	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5867	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5868	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5869	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5870	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5871
5872	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5873	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5874	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5875	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5876
5877	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5878	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5879
5880	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5881	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5882
5883	# ifdef VBOX_WITH_VMSVGA3D
5884	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5885	# endif
5886	if (pThisCC->pDrv)
5887	{
5888	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5889	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5890	}
5891
5892	/* Dump screen information. */
5893	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5894	{
5895	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5896	if (pScreen)
5897	{
5898	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5899	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5900	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5901	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5902	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5903	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5904	{
5905	pHlp->pfnPrintf(pHlp, " (");
5906	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5907	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5908	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5909	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5910	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5911	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5912	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5913	pHlp->pfnPrintf(pHlp, " BLANKING");
5914	pHlp->pfnPrintf(pHlp, " )");
5915	}
5916	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5917	}
5918	}
5919
5920	}
5921
5922	/**
5923	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5924	*/
5925	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5926	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5927	{
5928	RT_NOREF(uPass);
5929
5930	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5931	int rc;
5932
5933	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5934	{
5935	uint32_t cScreens = 0;
5936	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5937	AssertRCReturn(rc, rc);
5938	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5939	("cScreens=%#x\n", cScreens),
5940	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5941
5942	for (uint32_t i = 0; i < cScreens; ++i)
5943	{
5944	VMSVGASCREENOBJECT screen;
5945	RT_ZERO(screen);
5946
5947	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5948	AssertLogRelRCReturn(rc, rc);
5949
5950	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5951	{
5952	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5953	*pScreen = screen;
5954	pScreen->fModified = true;
5955	}
5956	else
5957	{
5958	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5959	}
5960	}
5961	}
5962	else
5963	{
5964	/* Try to setup at least the first screen. */
5965	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5966	pScreen->fDefined = true;
5967	pScreen->fModified = true;
5968	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5969	pScreen->idScreen = 0;
5970	pScreen->xOrigin = 0;
5971	pScreen->yOrigin = 0;
5972	pScreen->offVRAM = pThis->svga.uScreenOffset;
5973	pScreen->cbPitch = pThis->svga.cbScanline;
5974	pScreen->cWidth = pThis->svga.uWidth;
5975	pScreen->cHeight = pThis->svga.uHeight;
5976	pScreen->cBpp = pThis->svga.uBpp;
5977	}
5978
5979	return VINF_SUCCESS;
5980	}
5981
5982	/**
5983	* @copydoc FNSSMDEVLOADEXEC
5984	*/
5985	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5986	{
5987	RT_NOREF(uPass);
5988	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5989	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5990	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5991	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5992	int rc;
5993
5994	/* Load our part of the VGAState */
5995	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5996	AssertRCReturn(rc, rc);
5997
5998	/* Load the VGA framebuffer. */
5999	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
6000	uint32_t cbVgaFramebuffer = _32K;
6001	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
6002	{
6003	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
6004	AssertRCReturn(rc, rc);
6005	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
6006	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
6007	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6008	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
6009	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
6010	}
6011	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
6012	AssertRCReturn(rc, rc);
6013	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
6014	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
6015	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
6016	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
6017
6018	/* Load the VMSVGA state. */
6019	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6020	AssertRCReturn(rc, rc);
6021
6022	/* Load the active cursor bitmaps. */
6023	if (pSVGAState->Cursor.fActive)
6024	{
6025	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
6026	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
6027
6028	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6029	AssertRCReturn(rc, rc);
6030	}
6031
6032	/* Load the GMR state. */
6033	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
6034	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
6035	{
6036	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
6037	AssertRCReturn(rc, rc);
6038	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
6039	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
6040	("cGMR=%#x - expected 256B..1MB\n", cGMR),
6041	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6042	}
6043
6044	if (pThis->svga.cGMR != cGMR)
6045	{
6046	/* Reallocate GMR array. */
6047	Assert(pSVGAState->paGMR != NULL);
6048	RTMemFree(pSVGAState->paGMR);
6049	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
6050	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6051	pThis->svga.cGMR = cGMR;
6052	}
6053
6054	for (uint32_t i = 0; i < cGMR; ++i)
6055	{
6056	PGMR pGMR = &pSVGAState->paGMR[i];
6057
6058	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6059	AssertRCReturn(rc, rc);
6060
6061	if (pGMR->numDescriptors)
6062	{
6063	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6064	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6065	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6066
6067	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6068	{
6069	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6070	AssertRCReturn(rc, rc);
6071	}
6072	}
6073	}
6074
6075	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6076	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
6077	# endif
6078
6079	VMSVGA_STATE_LOAD LoadState;
6080	LoadState.pSSM = pSSM;
6081	LoadState.uVersion = uVersion;
6082	LoadState.uPass = uPass;
6083	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6084	AssertLogRelRCReturn(rc, rc);
6085
6086	return VINF_SUCCESS;
6087	}
6088
6089	/**
6090	* Reinit the video mode after the state has been loaded.
6091	*/
6092	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6093	{
6094	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6095	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6096	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6097
6098	/* Set the active cursor. */
6099	if (pSVGAState->Cursor.fActive)
6100	{
6101	/* We don't store the alpha flag, but we can take a guess that if
6102	* the old register interface was used, the cursor was B&W.
6103	*/
6104	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6105
6106	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6107	true /fVisible/,
6108	fAlpha,
6109	pSVGAState->Cursor.xHotspot,
6110	pSVGAState->Cursor.yHotspot,
6111	pSVGAState->Cursor.width,
6112	pSVGAState->Cursor.height,
6113	pSVGAState->Cursor.pData);
6114	AssertRC(rc);
6115
6116	if (pThis->svga.uCursorOn)
6117	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6118	}
6119
6120	/* If the VRAM handler should not be registered, we have to explicitly
6121	* unregister it here!
6122	*/
6123	if (!pThis->svga.fVRAMTracking)
6124	{
6125	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6126	}
6127
6128	/* Let the FIFO thread deal with changing the mode. */
6129	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6130
6131	return VINF_SUCCESS;
6132	}
6133
6134	/**
6135	* Portion of SVGA state which must be saved in the FIFO thread.
6136	*/
6137	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6138	{
6139	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6140	int rc;
6141
6142	/* Save the screen objects. */
6143	/* Count defined screen object. */
6144	uint32_t cScreens = 0;
6145	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6146	{
6147	if (pSVGAState->aScreens[i].fDefined)
6148	++cScreens;
6149	}
6150
6151	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6152	AssertLogRelRCReturn(rc, rc);
6153
6154	for (uint32_t i = 0; i < cScreens; ++i)
6155	{
6156	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6157
6158	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6159	AssertLogRelRCReturn(rc, rc);
6160	}
6161	return VINF_SUCCESS;
6162	}
6163
6164	/**
6165	* @copydoc FNSSMDEVSAVEEXEC
6166	*/
6167	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6168	{
6169	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6170	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6171	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6172	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6173	int rc;
6174
6175	/* Save our part of the VGAState */
6176	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6177	AssertLogRelRCReturn(rc, rc);
6178
6179	/* Save the framebuffer backup. */
6180	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6181	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6182	AssertLogRelRCReturn(rc, rc);
6183
6184	/* Save the VMSVGA state. */
6185	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6186	AssertLogRelRCReturn(rc, rc);
6187
6188	/* Save the active cursor bitmaps. */
6189	if (pSVGAState->Cursor.fActive)
6190	{
6191	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6192	AssertLogRelRCReturn(rc, rc);
6193	}
6194
6195	/* Save the GMR state */
6196	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6197	AssertLogRelRCReturn(rc, rc);
6198	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6199	{
6200	PGMR pGMR = &pSVGAState->paGMR[i];
6201
6202	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6203	AssertLogRelRCReturn(rc, rc);
6204
6205	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6206	{
6207	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6208	AssertLogRelRCReturn(rc, rc);
6209	}
6210	}
6211
6212	/*
6213	* Must save some state (3D in particular) in the FIFO thread.
6214	*/
6215	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6216	AssertLogRelRCReturn(rc, rc);
6217
6218	return VINF_SUCCESS;
6219	}
6220
6221	/**
6222	* Destructor for PVMSVGAR3STATE structure.
6223	*
6224	* @param pThis The shared VGA/VMSVGA instance data.
6225	* @param pSVGAState Pointer to the structure. It is not deallocated.
6226	*/
6227	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6228	{
6229	# ifndef VMSVGA_USE_EMT_HALT_CODE
6230	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6231	{
6232	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6233	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6234	}
6235	# endif
6236
6237	if (pSVGAState->Cursor.fActive)
6238	{
6239	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6240	pSVGAState->Cursor.pData = NULL;
6241	pSVGAState->Cursor.fActive = false;
6242	}
6243
6244	if (pSVGAState->paGMR)
6245	{
6246	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6247	if (pSVGAState->paGMR[i].paDesc)
6248	RTMemFree(pSVGAState->paGMR[i].paDesc);
6249
6250	RTMemFree(pSVGAState->paGMR);
6251	pSVGAState->paGMR = NULL;
6252	}
6253	}
6254
6255	/**
6256	* Constructor for PVMSVGAR3STATE structure.
6257	*
6258	* @returns VBox status code.
6259	* @param pThis The shared VGA/VMSVGA instance data.
6260	* @param pSVGAState Pointer to the structure. It is already allocated.
6261	*/
6262	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6263	{
6264	int rc = VINF_SUCCESS;
6265	RT_ZERO(*pSVGAState);
6266
6267	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6268	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6269
6270	# ifndef VMSVGA_USE_EMT_HALT_CODE
6271	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6272	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6273	AssertRCReturn(rc, rc);
6274	# endif
6275
6276	return rc;
6277	}
6278
6279	/**
6280	* Initializes the host capabilities: registers and FIFO.
6281	*
6282	* @returns VBox status code.
6283	* @param pThis The shared VGA/VMSVGA instance data.
6284	* @param pThisCC The VGA/VMSVGA state for ring-3.
6285	*/
6286	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6287	{
6288	/* Register caps. */
6289	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6290	\| SVGA_CAP_GMR2
6291	\| SVGA_CAP_CURSOR
6292	\| SVGA_CAP_CURSOR_BYPASS
6293	\| SVGA_CAP_CURSOR_BYPASS_2
6294	\| SVGA_CAP_EXTENDED_FIFO
6295	\| SVGA_CAP_IRQMASK
6296	\| SVGA_CAP_PITCHLOCK
6297	\| SVGA_CAP_RECT_COPY
6298	\| SVGA_CAP_TRACES
6299	\| SVGA_CAP_SCREEN_OBJECT_2
6300	\| SVGA_CAP_ALPHA_CURSOR;
6301	# ifdef VBOX_WITH_VMSVGA3D
6302	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6303	# endif
6304
6305	/* Clear the FIFO. */
6306	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6307
6308	/* Setup FIFO capabilities. */
6309	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6310	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6311	\| SVGA_FIFO_CAP_GMR2
6312	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6313	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6314	\| SVGA_FIFO_CAP_RESERVE
6315	\| SVGA_FIFO_CAP_PITCHLOCK;
6316
6317	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6318	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6319	}
6320
6321	# ifdef VBOX_WITH_VMSVGA3D
6322	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6323	static const char * const g_apszVmSvgaDevCapNames[] =
6324	{
6325	"x3D", /* = 0 */
6326	"xMAX_LIGHTS",
6327	"xMAX_TEXTURES",
6328	"xMAX_CLIP_PLANES",
6329	"xVERTEX_SHADER_VERSION",
6330	"xVERTEX_SHADER",
6331	"xFRAGMENT_SHADER_VERSION",
6332	"xFRAGMENT_SHADER",
6333	"xMAX_RENDER_TARGETS",
6334	"xS23E8_TEXTURES",
6335	"xS10E5_TEXTURES",
6336	"xMAX_FIXED_VERTEXBLEND",
6337	"xD16_BUFFER_FORMAT",
6338	"xD24S8_BUFFER_FORMAT",
6339	"xD24X8_BUFFER_FORMAT",
6340	"xQUERY_TYPES",
6341	"xTEXTURE_GRADIENT_SAMPLING",
6342	"rMAX_POINT_SIZE",
6343	"xMAX_SHADER_TEXTURES",
6344	"xMAX_TEXTURE_WIDTH",
6345	"xMAX_TEXTURE_HEIGHT",
6346	"xMAX_VOLUME_EXTENT",
6347	"xMAX_TEXTURE_REPEAT",
6348	"xMAX_TEXTURE_ASPECT_RATIO",
6349	"xMAX_TEXTURE_ANISOTROPY",
6350	"xMAX_PRIMITIVE_COUNT",
6351	"xMAX_VERTEX_INDEX",
6352	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6353	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6354	"xMAX_VERTEX_SHADER_TEMPS",
6355	"xMAX_FRAGMENT_SHADER_TEMPS",
6356	"xTEXTURE_OPS",
6357	"xSURFACEFMT_X8R8G8B8",
6358	"xSURFACEFMT_A8R8G8B8",
6359	"xSURFACEFMT_A2R10G10B10",
6360	"xSURFACEFMT_X1R5G5B5",
6361	"xSURFACEFMT_A1R5G5B5",
6362	"xSURFACEFMT_A4R4G4B4",
6363	"xSURFACEFMT_R5G6B5",
6364	"xSURFACEFMT_LUMINANCE16",
6365	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6366	"xSURFACEFMT_ALPHA8",
6367	"xSURFACEFMT_LUMINANCE8",
6368	"xSURFACEFMT_Z_D16",
6369	"xSURFACEFMT_Z_D24S8",
6370	"xSURFACEFMT_Z_D24X8",
6371	"xSURFACEFMT_DXT1",
6372	"xSURFACEFMT_DXT2",
6373	"xSURFACEFMT_DXT3",
6374	"xSURFACEFMT_DXT4",
6375	"xSURFACEFMT_DXT5",
6376	"xSURFACEFMT_BUMPX8L8V8U8",
6377	"xSURFACEFMT_A2W10V10U10",
6378	"xSURFACEFMT_BUMPU8V8",
6379	"xSURFACEFMT_Q8W8V8U8",
6380	"xSURFACEFMT_CxV8U8",
6381	"xSURFACEFMT_R_S10E5",
6382	"xSURFACEFMT_R_S23E8",
6383	"xSURFACEFMT_RG_S10E5",
6384	"xSURFACEFMT_RG_S23E8",
6385	"xSURFACEFMT_ARGB_S10E5",
6386	"xSURFACEFMT_ARGB_S23E8",
6387	"xMISSING62",
6388	"xMAX_VERTEX_SHADER_TEXTURES",
6389	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6390	"xSURFACEFMT_V16U16",
6391	"xSURFACEFMT_G16R16",
6392	"xSURFACEFMT_A16B16G16R16",
6393	"xSURFACEFMT_UYVY",
6394	"xSURFACEFMT_YUY2",
6395	"xMULTISAMPLE_NONMASKABLESAMPLES",
6396	"xMULTISAMPLE_MASKABLESAMPLES",
6397	"xALPHATOCOVERAGE",
6398	"xSUPERSAMPLE",
6399	"xAUTOGENMIPMAPS",
6400	"xSURFACEFMT_NV12",
6401	"xSURFACEFMT_AYUV",
6402	"xMAX_CONTEXT_IDS",
6403	"xMAX_SURFACE_IDS",
6404	"xSURFACEFMT_Z_DF16",
6405	"xSURFACEFMT_Z_DF24",
6406	"xSURFACEFMT_Z_D24S8_INT",
6407	"xSURFACEFMT_BC4_UNORM",
6408	"xSURFACEFMT_BC5_UNORM", /* 83 */
6409	};
6410
6411	/**
6412	* Initializes the host 3D capabilities in FIFO.
6413	*
6414	* @returns VBox status code.
6415	* @param pThis The shared VGA/VMSVGA instance data.
6416	* @param pThisCC The VGA/VMSVGA state for ring-3.
6417	*/
6418	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6419	{
6420	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6421	bool fSavedBuffering = RTLogRelSetBuffering(true);
6422	SVGA3dCapsRecord *pCaps;
6423	SVGA3dCapPair *pData;
6424	uint32_t idxCap = 0;
6425
6426	/* 3d hardware version; latest and greatest */
6427	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6428	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6429
6430	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6431	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6432	pData = (SVGA3dCapPair *)&pCaps->data;
6433
6434	/* Fill out all 3d capabilities. */
6435	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6436	{
6437	uint32_t val = 0;
6438
6439	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6440	if (RT_SUCCESS(rc))
6441	{
6442	pData[idxCap][0] = i;
6443	pData[idxCap][1] = val;
6444	idxCap++;
6445	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6446	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6447	else
6448	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6449	&g_apszVmSvgaDevCapNames[i][1]));
6450	}
6451	else
6452	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6453	}
6454	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6455	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6456
6457	/* Mark end of record array. */
6458	pCaps->header.length = 0;
6459
6460	RTLogRelSetBuffering(fSavedBuffering);
6461	}
6462
6463	# endif
6464
6465	/**
6466	* Resets the SVGA hardware state
6467	*
6468	* @returns VBox status code.
6469	* @param pDevIns The device instance.
6470	*/
6471	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6472	{
6473	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6474	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6475	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6476
6477	/* Reset before init? */
6478	if (!pSVGAState)
6479	return VINF_SUCCESS;
6480
6481	Log(("vmsvgaR3Reset\n"));
6482
6483	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6484	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6485	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6486
6487	/* Reset other stuff. */
6488	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6489	RT_ZERO(pThis->svga.au32ScratchRegion);
6490
6491	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6492	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6493
6494	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6495
6496	/* Initialize FIFO and register capabilities. */
6497	vmsvgaR3InitCaps(pThis, pThisCC);
6498
6499	# ifdef VBOX_WITH_VMSVGA3D
6500	if (pThis->svga.f3DEnabled)
6501	vmsvgaR3InitFifo3DCaps(pThisCC);
6502	# endif
6503
6504	/* VRAM tracking is enabled by default during bootup. */
6505	pThis->svga.fVRAMTracking = true;
6506	pThis->svga.fEnabled = false;
6507
6508	/* Invalidate current settings. */
6509	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6510	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6511	pThis->svga.uBpp = pThis->svga.uHostBpp;
6512	pThis->svga.cbScanline = 0;
6513	pThis->svga.u32PitchLock = 0;
6514
6515	return rc;
6516	}
6517
6518	/**
6519	* Cleans up the SVGA hardware state
6520	*
6521	* @returns VBox status code.
6522	* @param pDevIns The device instance.
6523	*/
6524	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6525	{
6526	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6527	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6528
6529	/*
6530	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6531	*/
6532	if (pThisCC->svga.pFIFOIOThread)
6533	{
6534	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6535	NULL /pvParam/, 30000 /ms/);
6536	AssertLogRelRC(rc);
6537
6538	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6539	AssertLogRelRC(rc);
6540	pThisCC->svga.pFIFOIOThread = NULL;
6541	}
6542
6543	/*
6544	* Destroy the special SVGA state.
6545	*/
6546	if (pThisCC->svga.pSvgaR3State)
6547	{
6548	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6549
6550	RTMemFree(pThisCC->svga.pSvgaR3State);
6551	pThisCC->svga.pSvgaR3State = NULL;
6552	}
6553
6554	/*
6555	* Free our resources residing in the VGA state.
6556	*/
6557	if (pThisCC->svga.pbVgaFrameBufferR3)
6558	{
6559	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6560	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6561	}
6562	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6563	{
6564	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6565	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6566	}
6567	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6568	{
6569	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6570	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6571	}
6572
6573	return VINF_SUCCESS;
6574	}
6575
6576	/**
6577	* Initialize the SVGA hardware state
6578	*
6579	* @returns VBox status code.
6580	* @param pDevIns The device instance.
6581	*/
6582	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6583	{
6584	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6585	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6586	PVMSVGAR3STATE pSVGAState;
6587	int rc;
6588
6589	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6590	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6591
6592	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6593
6594	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6595	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6596	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6597
6598	/* Create event semaphore. */
6599	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6600	AssertRCReturn(rc, rc);
6601
6602	/* Create event semaphore. */
6603	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6604	AssertRCReturn(rc, rc);
6605
6606	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6607	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6608
6609	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6610	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6611
6612	pSVGAState = pThisCC->svga.pSvgaR3State;
6613
6614	/* Initialize FIFO and register capabilities. */
6615	vmsvgaR3InitCaps(pThis, pThisCC);
6616
6617	# ifdef VBOX_WITH_VMSVGA3D
6618	if (pThis->svga.f3DEnabled)
6619	{
6620	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6621	if (RT_FAILURE(rc))
6622	{
6623	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6624	pThis->svga.f3DEnabled = false;
6625	}
6626	}
6627	# endif
6628	/* VRAM tracking is enabled by default during bootup. */
6629	pThis->svga.fVRAMTracking = true;
6630
6631	/* Set up the host bpp. This value is as a default for the programmable
6632	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6633	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6634	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6635	*
6636	* NB: The driver cBits value is currently constant for the lifetime of the
6637	* VM. If that changes, the host bpp logic might need revisiting.
6638	*/
6639	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6640
6641	/* Invalidate current settings. */
6642	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6643	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6644	pThis->svga.uBpp = pThis->svga.uHostBpp;
6645	pThis->svga.cbScanline = 0;
6646
6647	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6648	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6649	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6650	{
6651	pThis->svga.u32MaxWidth -= 256;
6652	pThis->svga.u32MaxHeight -= 256;
6653	}
6654	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6655
6656	# ifdef DEBUG_GMR_ACCESS
6657	/* Register the GMR access handler type. */
6658	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6659	vmsvgaR3GmrAccessHandler,
6660	NULL, NULL, NULL,
6661	NULL, NULL, NULL,
6662	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6663	AssertRCReturn(rc, rc);
6664	# endif
6665
6666	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6667	/* Register the FIFO access handler type. In addition to
6668	debugging FIFO access, this is also used to facilitate
6669	extended fifo thread sleeps. */
6670	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6671	# ifdef DEBUG_FIFO_ACCESS
6672	PGMPHYSHANDLERKIND_ALL,
6673	# else
6674	PGMPHYSHANDLERKIND_WRITE,
6675	# endif
6676	vmsvgaR3FifoAccessHandler,
6677	NULL, NULL, NULL,
6678	NULL, NULL, NULL,
6679	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6680	AssertRCReturn(rc, rc);
6681	# endif
6682
6683	/* Create the async IO thread. */
6684	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6685	RTTHREADTYPE_IO, "VMSVGA FIFO");
6686	if (RT_FAILURE(rc))
6687	{
6688	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6689	return rc;
6690	}
6691
6692	/*
6693	* Statistics.
6694	*/
6695	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6696	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6697	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6698	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6699	# ifdef VBOX_WITH_STATISTICS
6700	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6701	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6702	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6703	# endif
6704	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6705	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6706	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6707	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6708	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6709	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6710	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6711	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6712	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6713	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6714	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6715	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6716	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6717	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6718	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6719	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6720	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6721	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6722	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6723	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6724	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6725	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6726	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6727	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6728	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6729	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6730	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6731	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6732	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6733	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6734	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6735	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6736	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6737	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6738	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6739	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6740	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6741	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6742	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6743	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6744	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6745	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6746	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6747	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6748	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6749	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6750	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6751	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6752	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6753	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6754	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6755	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6756	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6757	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6758	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6759	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6760	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6761	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6762	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6763
6764	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6765	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6766	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6767	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6768	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6769	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6770	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6771	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6772	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6773	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6774	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6775	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6776	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6777	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6778	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6779	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6780	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6781	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6782	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6783	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6784	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6785	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6786	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6787	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6788	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6789	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6790	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6791	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6792	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6793	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6794	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6795	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6796	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6797	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6798	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6799
6800	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6801	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6802	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6803	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6804	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6805	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6806	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6807	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6808	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6809	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6810	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6811	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6812	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6813	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6814	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6815	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6816	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6817	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6818	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6819	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6820	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6821	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6822	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6823	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6824	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6825	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6826	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6827	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6828	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6829	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6830	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6831	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6832	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6833	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6834	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6835	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6836	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6837	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6838	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6839	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6840	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6841	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6842	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6843	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6844	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6845	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6846	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6847	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6848	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6849	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6850	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6851	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6852
6853	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6854	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6855	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6856	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6857	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6858	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6859	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6860	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6861	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6862	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6863	# endif
6864	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6865	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6866	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6867	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6868	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6869
6870	# undef REG_CNT
6871	# undef REG_PRF
6872
6873	/*
6874	* Info handlers.
6875	*/
6876	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6877	# ifdef VBOX_WITH_VMSVGA3D
6878	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6879	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6880	"VMSVGA 3d surface details. "
6881	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6882	vmsvgaR3Info3dSurface);
6883	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6884	"VMSVGA 3d surface details and bitmap: "
6885	"sid[>dir]",
6886	vmsvgaR3Info3dSurfaceBmp);
6887	# endif
6888
6889	return VINF_SUCCESS;
6890	}
6891
6892	/**
6893	* Power On notification.
6894	*
6895	* @returns VBox status code.
6896	* @param pDevIns The device instance data.
6897	*
6898	* @remarks Caller enters the device critical section.
6899	*/
6900	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6901	{
6902	# ifdef VBOX_WITH_VMSVGA3D
6903	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6904	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6905	if (pThis->svga.f3DEnabled)
6906	{
6907	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6908
6909	if (RT_SUCCESS(rc))
6910	{
6911	/* Initialize FIFO 3D capabilities. */
6912	vmsvgaR3InitFifo3DCaps(pThisCC);
6913	}
6914	}
6915	# else /* !VBOX_WITH_VMSVGA3D */
6916	RT_NOREF(pDevIns);
6917	# endif /* !VBOX_WITH_VMSVGA3D */
6918	}
6919
6920	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 84754

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