DevVGA-SVGA.cpp@ 85672

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DevVGA-SVGA.cpp: comment typo
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1	/* $Id: DevVGA-SVGA.cpp 85476 2020-07-27 18:09:47Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.virtualbox.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#define VMSVGA_USE_EMT_HALT_CODE
133	#include <VBox/vmm/pdmdev.h>
134	#include <VBox/version.h>
135	#include <VBox/err.h>
136	#include <VBox/log.h>
137	#include <VBox/vmm/pgm.h>
138	#ifdef VMSVGA_USE_EMT_HALT_CODE
139	# include <VBox/vmm/vmapi.h>
140	# include <VBox/vmm/vmcpuset.h>
141	#endif
142	#include <VBox/sup.h>
143
144	#include <iprt/assert.h>
145	#include <iprt/semaphore.h>
146	#include <iprt/uuid.h>
147	#ifdef IN_RING3
148	# include <iprt/ctype.h>
149	# include <iprt/mem.h>
150	# ifdef VBOX_STRICT
151	# include <iprt/time.h>
152	# endif
153	#endif
154
155	#include <VBox/AssertGuest.h>
156	#include <VBox/VMMDev.h>
157	#include <VBoxVideo.h>
158	#include <VBox/bioslogo.h>
159
160	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
161	#include "DevVGA.h"
162
163	#include "DevVGA-SVGA.h"
164	#include "vmsvga/svga_escape.h"
165	#include "vmsvga/svga_overlay.h"
166	#include "vmsvga/svga3d_caps.h"
167	#ifdef VBOX_WITH_VMSVGA3D
168	# include "DevVGA-SVGA3d.h"
169	# ifdef RT_OS_DARWIN
170	# include "DevVGA-SVGA3d-cocoa.h"
171	# endif
172	# ifdef RT_OS_LINUX
173	# ifdef IN_RING3
174	#include "DevVGA-SVGA3d-glLdr.h"
175	# endif
176	# endif
177	#endif
178
179
180	/*********************************************************************************************************************************
181	* Defined Constants And Macros *
182	*********************************************************************************************************************************/
183	/**
184	* Macro for checking if a fixed FIFO register is valid according to the
185	* current FIFO configuration.
186	*
187	* @returns true / false.
188	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
189	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
190	*/
191	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
192
193
194	/*********************************************************************************************************************************
195	* Structures and Typedefs *
196	*********************************************************************************************************************************/
197	/**
198	* 64-bit GMR descriptor.
199	*/
200	typedef struct
201	{
202	RTGCPHYS GCPhys;
203	uint64_t numPages;
204	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
205
206	/**
207	* GMR slot
208	*/
209	typedef struct
210	{
211	uint32_t cMaxPages;
212	uint32_t cbTotal;
213	uint32_t numDescriptors;
214	PVMSVGAGMRDESCRIPTOR paDesc;
215	} GMR, *PGMR;
216
217	#ifdef IN_RING3
218	/**
219	* Internal SVGA ring-3 only state.
220	*/
221	typedef struct VMSVGAR3STATE
222	{
223	GMR *paGMR; // [VMSVGAState::cGMR]
224	struct
225	{
226	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
227	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
228	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
229	} GMRFB;
230	struct
231	{
232	bool fActive;
233	uint32_t xHotspot;
234	uint32_t yHotspot;
235	uint32_t width;
236	uint32_t height;
237	uint32_t cbData;
238	void *pData;
239	} Cursor;
240	SVGAColorBGRX colorAnnotation;
241
242	# ifdef VMSVGA_USE_EMT_HALT_CODE
243	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
244	uint32_t volatile cBusyDelayedEmts;
245	/** Set of EMTs that are */
246	VMCPUSET BusyDelayedEmts;
247	# else
248	/** Number of EMTs waiting on hBusyDelayedEmts. */
249	uint32_t volatile cBusyDelayedEmts;
250	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
251	* busy (ugly). */
252	RTSEMEVENTMULTI hBusyDelayedEmts;
253	# endif
254
255	/** Information obout screens. */
256	VMSVGASCREENOBJECT aScreens[64];
257
258	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
259	STAMPROFILE StatBusyDelayEmts;
260
261	STAMPROFILE StatR3Cmd3dPresentProf;
262	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
263	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
264	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
265	STAMCOUNTER StatR3CmdDefineGmr2;
266	STAMCOUNTER StatR3CmdDefineGmr2Free;
267	STAMCOUNTER StatR3CmdDefineGmr2Modify;
268	STAMCOUNTER StatR3CmdRemapGmr2;
269	STAMCOUNTER StatR3CmdRemapGmr2Modify;
270	STAMCOUNTER StatR3CmdInvalidCmd;
271	STAMCOUNTER StatR3CmdFence;
272	STAMCOUNTER StatR3CmdUpdate;
273	STAMCOUNTER StatR3CmdUpdateVerbose;
274	STAMCOUNTER StatR3CmdDefineCursor;
275	STAMCOUNTER StatR3CmdDefineAlphaCursor;
276	STAMCOUNTER StatR3CmdMoveCursor;
277	STAMCOUNTER StatR3CmdDisplayCursor;
278	STAMCOUNTER StatR3CmdRectFill;
279	STAMCOUNTER StatR3CmdRectCopy;
280	STAMCOUNTER StatR3CmdRectRopCopy;
281	STAMCOUNTER StatR3CmdEscape;
282	STAMCOUNTER StatR3CmdDefineScreen;
283	STAMCOUNTER StatR3CmdDestroyScreen;
284	STAMCOUNTER StatR3CmdDefineGmrFb;
285	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
286	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
287	STAMCOUNTER StatR3CmdAnnotationFill;
288	STAMCOUNTER StatR3CmdAnnotationCopy;
289	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
290	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
291	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
292	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
293	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
294	STAMCOUNTER StatR3Cmd3dSurfaceDma;
295	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
296	STAMCOUNTER StatR3Cmd3dContextDefine;
297	STAMCOUNTER StatR3Cmd3dContextDestroy;
298	STAMCOUNTER StatR3Cmd3dSetTransform;
299	STAMCOUNTER StatR3Cmd3dSetZRange;
300	STAMCOUNTER StatR3Cmd3dSetRenderState;
301	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
302	STAMCOUNTER StatR3Cmd3dSetTextureState;
303	STAMCOUNTER StatR3Cmd3dSetMaterial;
304	STAMCOUNTER StatR3Cmd3dSetLightData;
305	STAMCOUNTER StatR3Cmd3dSetLightEnable;
306	STAMCOUNTER StatR3Cmd3dSetViewPort;
307	STAMCOUNTER StatR3Cmd3dSetClipPlane;
308	STAMCOUNTER StatR3Cmd3dClear;
309	STAMCOUNTER StatR3Cmd3dPresent;
310	STAMCOUNTER StatR3Cmd3dPresentReadBack;
311	STAMCOUNTER StatR3Cmd3dShaderDefine;
312	STAMCOUNTER StatR3Cmd3dShaderDestroy;
313	STAMCOUNTER StatR3Cmd3dSetShader;
314	STAMCOUNTER StatR3Cmd3dSetShaderConst;
315	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
316	STAMCOUNTER StatR3Cmd3dSetScissorRect;
317	STAMCOUNTER StatR3Cmd3dBeginQuery;
318	STAMCOUNTER StatR3Cmd3dEndQuery;
319	STAMCOUNTER StatR3Cmd3dWaitForQuery;
320	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
321	STAMCOUNTER StatR3Cmd3dActivateSurface;
322	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
323
324	STAMCOUNTER StatR3RegConfigDoneWr;
325	STAMCOUNTER StatR3RegGmrDescriptorWr;
326	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
327	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
328
329	STAMCOUNTER StatFifoCommands;
330	STAMCOUNTER StatFifoErrors;
331	STAMCOUNTER StatFifoUnkCmds;
332	STAMCOUNTER StatFifoTodoTimeout;
333	STAMCOUNTER StatFifoTodoWoken;
334	STAMPROFILE StatFifoStalls;
335	STAMPROFILE StatFifoExtendedSleep;
336	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
337	STAMCOUNTER StatFifoAccessHandler;
338	# endif
339	STAMCOUNTER StatFifoCursorFetchAgain;
340	STAMCOUNTER StatFifoCursorNoChange;
341	STAMCOUNTER StatFifoCursorPosition;
342	STAMCOUNTER StatFifoCursorVisiblity;
343	STAMCOUNTER StatFifoWatchdogWakeUps;
344	} VMSVGAR3STATE, *PVMSVGAR3STATE;
345	#endif /* IN_RING3 */
346
347
348	/*********************************************************************************************************************************
349	* Internal Functions *
350	*********************************************************************************************************************************/
351	#ifdef IN_RING3
352	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
353	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
354	# endif
355	# ifdef DEBUG_GMR_ACCESS
356	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
357	# endif
358	#endif
359
360
361	/*********************************************************************************************************************************
362	* Global Variables *
363	*********************************************************************************************************************************/
364	#ifdef IN_RING3
365
366	/**
367	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
368	*/
369	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
370	{
371	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
372	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
373	SSMFIELD_ENTRY_TERM()
374	};
375
376	/**
377	* SSM descriptor table for the GMR structure.
378	*/
379	static SSMFIELD const g_aGMRFields[] =
380	{
381	SSMFIELD_ENTRY( GMR, cMaxPages),
382	SSMFIELD_ENTRY( GMR, cbTotal),
383	SSMFIELD_ENTRY( GMR, numDescriptors),
384	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
385	SSMFIELD_ENTRY_TERM()
386	};
387
388	/**
389	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
390	*/
391	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
392	{
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
395	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
396	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
397	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
398	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
399	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
400	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
401	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
402	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
403	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
404	SSMFIELD_ENTRY_TERM()
405	};
406
407	/**
408	* SSM descriptor table for the VMSVGAR3STATE structure.
409	*/
410	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
411	{
412	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
413	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
414	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
415	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
416	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
417	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
418	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
419	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
420	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
421	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
422	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
423	#ifdef VMSVGA_USE_EMT_HALT_CODE
424	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
425	#else
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
427	#endif
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
488	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
491
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
493	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
496
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
501	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
503	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
504	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
505	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
506	# endif
507	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
508	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
509	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
510	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
511
512	SSMFIELD_ENTRY_TERM()
513	};
514
515	/**
516	* SSM descriptor table for the VGAState.svga structure.
517	*/
518	static SSMFIELD const g_aVGAStateSVGAFields[] =
519	{
520	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
521	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
522	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
523	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
524	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
525	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
526	SSMFIELD_ENTRY( VMSVGAState, fBusy),
527	SSMFIELD_ENTRY( VMSVGAState, fTraces),
528	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
529	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
530	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
531	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
532	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
533	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
534	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
535	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
536	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
537	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
538	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
539	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
540	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
541	SSMFIELD_ENTRY( VMSVGAState, uWidth),
542	SSMFIELD_ENTRY( VMSVGAState, uHeight),
543	SSMFIELD_ENTRY( VMSVGAState, uBpp),
544	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
545	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
546	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
547	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
548	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
549	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
550	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
551	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
552	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
553	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
554	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
555	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
556	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
557	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
558	SSMFIELD_ENTRY_TERM()
559	};
560	#endif /* IN_RING3 */
561
562
563	/*********************************************************************************************************************************
564	* Internal Functions *
565	*********************************************************************************************************************************/
566	#ifdef IN_RING3
567	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
568	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
569	uint32_t uVersion, uint32_t uPass);
570	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
571	# ifdef VBOX_WITH_VMSVGA3D
572	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
573	# endif /* VBOX_WITH_VMSVGA3D */
574	#endif /* IN_RING3 */
575
576
577
578	#ifdef IN_RING3
579	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
580	{
581	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
582	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
583	&& pSVGAState
584	&& pSVGAState->aScreens[idScreen].fDefined)
585	{
586	return &pSVGAState->aScreens[idScreen];
587	}
588	return NULL;
589	}
590
591	void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
592	{
593	# ifdef VBOX_WITH_VMSVGA3D
594	if (pThis->svga.f3DEnabled)
595	{
596	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
597	{
598	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
599	if (pScreen)
600	vmsvga3dDestroyScreen(pThisCC, pScreen);
601	}
602	}
603	# else
604	RT_NOREF(pThis, pThisCC);
605	# endif
606	}
607	#endif /* IN_RING3 */
608
609	#ifdef LOG_ENABLED
610
611	/**
612	* Index register string name lookup
613	*
614	* @returns Index register string or "UNKNOWN"
615	* @param pThis The shared VGA/VMSVGA state.
616	* @param idxReg The index register.
617	*/
618	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
619	{
620	switch (idxReg)
621	{
622	case SVGA_REG_ID: return "SVGA_REG_ID";
623	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
624	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
625	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
626	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
627	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
628	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
629	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
630	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
631	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
632	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
633	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
634	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
635	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
636	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
637	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
638	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
639	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
640	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
641	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
642	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
643	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
644	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
645	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
646	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
647	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
648	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
649	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
650	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
651	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
652	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
653	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
654	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
655	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
656	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
657	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
658	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
659	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
660	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
661	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
662	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
663	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
664	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
665	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
666	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
667	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
668	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
669	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
670	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
671	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
672
673	default:
674	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
675	return "SVGA_SCRATCH_BASE reg";
676	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
677	return "SVGA_PALETTE_BASE reg";
678	return "UNKNOWN";
679	}
680	}
681
682	#ifdef IN_RING3
683	/**
684	* FIFO command name lookup
685	*
686	* @returns FIFO command string or "UNKNOWN"
687	* @param u32Cmd FIFO command
688	*/
689	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
690	{
691	switch (u32Cmd)
692	{
693	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
694	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
695	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
696	case SVGA_CMD_RECT_ROP_COPY: return "SVGA_CMD_RECT_ROP_COPY";
697	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
698	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
699	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
700	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
701	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
702	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
703	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
704	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
705	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
706	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
707	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
708	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
709	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
710	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
711	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
712	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
713	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
714	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
715	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
716	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
717	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
718	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
719	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
720	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
721	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
722	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
723	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
724	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
725	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
726	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
727	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
728	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
729	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
730	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
731	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
732	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
733	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
734	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
735	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
736	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
737	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
738	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
739	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
740	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
741	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
742	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
743	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
744	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
745	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
746	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
747	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
748	default: return "UNKNOWN";
749	}
750	}
751	# endif /* IN_RING3 */
752
753	#endif /* LOG_ENABLED */
754	#ifdef IN_RING3
755
756	/**
757	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
758	*/
759	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
760	{
761	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
762	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
763
764	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
765	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
766
767	/** @todo Test how it interacts with multiple screen objects. */
768	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
769	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
770	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
771
772	if (x < uWidth)
773	{
774	pThis->svga.viewport.x = x;
775	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
776	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
777	}
778	else
779	{
780	pThis->svga.viewport.x = uWidth;
781	pThis->svga.viewport.cx = 0;
782	pThis->svga.viewport.xRight = uWidth;
783	}
784	if (y < uHeight)
785	{
786	pThis->svga.viewport.y = y;
787	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
788	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
789	pThis->svga.viewport.yHighWC = uHeight - y;
790	}
791	else
792	{
793	pThis->svga.viewport.y = uHeight;
794	pThis->svga.viewport.cy = 0;
795	pThis->svga.viewport.yLowWC = 0;
796	pThis->svga.viewport.yHighWC = 0;
797	}
798
799	# ifdef VBOX_WITH_VMSVGA3D
800	/*
801	* Now inform the 3D backend.
802	*/
803	if (pThis->svga.f3DEnabled)
804	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
805	# else
806	RT_NOREF(OldViewport);
807	# endif
808	}
809
810
811	/**
812	* Updating screen information in API
813	*
814	* @param pThis The The shared VGA/VMSVGA instance data.
815	* @param pThisCC The VGA/VMSVGA state for ring-3.
816	*/
817	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
818	{
819	int rc;
820
821	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
822
823	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
824	{
825	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
826	if (!pScreen->fModified)
827	continue;
828
829	pScreen->fModified = false;
830
831	VBVAINFOVIEW view;
832	RT_ZERO(view);
833	view.u32ViewIndex = pScreen->idScreen;
834	// view.u32ViewOffset = 0;
835	view.u32ViewSize = pThis->vram_size;
836	view.u32MaxScreenSize = pThis->vram_size;
837
838	VBVAINFOSCREEN screen;
839	RT_ZERO(screen);
840	screen.u32ViewIndex = pScreen->idScreen;
841
842	if (pScreen->fDefined)
843	{
844	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
845	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
846	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
847	{
848	Assert(pThis->svga.fGFBRegisters);
849	continue;
850	}
851
852	screen.i32OriginX = pScreen->xOrigin;
853	screen.i32OriginY = pScreen->yOrigin;
854	screen.u32StartOffset = pScreen->offVRAM;
855	screen.u32LineSize = pScreen->cbPitch;
856	screen.u32Width = pScreen->cWidth;
857	screen.u32Height = pScreen->cHeight;
858	screen.u16BitsPerPixel = pScreen->cBpp;
859	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
860	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
861	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
862	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
863	}
864	else
865	{
866	/* Screen is destroyed. */
867	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
868	}
869
870	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
871	AssertRC(rc);
872	}
873	}
874
875
876	/**
877	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
878	*
879	* Used to update screen offsets (positions) since appearently vmwgfx fails to
880	* pass correct offsets thru FIFO.
881	*/
882	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
883	{
884	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
885	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
886	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
887
888	AssertReturnVoid(pSVGAState);
889
890	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
891	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
892	for (uint32_t i = 0; i < cPositions; ++i)
893	{
894	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
895	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
896	continue;
897
898	if (pSVGAState->aScreens[i].xOrigin == -1)
899	continue;
900	if (pSVGAState->aScreens[i].yOrigin == -1)
901	continue;
902
903	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
904	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
905	pSVGAState->aScreens[i].fModified = true;
906	}
907
908	vmsvgaR3VBVAResize(pThis, pThisCC);
909	}
910
911	#endif /* IN_RING3 */
912
913	/**
914	* Read port register
915	*
916	* @returns VBox status code.
917	* @param pDevIns The device instance.
918	* @param pThis The shared VGA/VMSVGA state.
919	* @param pu32 Where to store the read value
920	*/
921	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
922	{
923	#ifdef IN_RING3
924	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
925	#endif
926	int rc = VINF_SUCCESS;
927	*pu32 = 0;
928
929	/* Rough index register validation. */
930	uint32_t idxReg = pThis->svga.u32IndexReg;
931	#if !defined(IN_RING3) && defined(VBOX_STRICT)
932	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
933	VINF_IOM_R3_IOPORT_READ);
934	#else
935	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
936	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
937	VINF_SUCCESS);
938	#endif
939	RT_UNTRUSTED_VALIDATED_FENCE();
940
941	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
942	if ( idxReg >= SVGA_REG_CAPABILITIES
943	&& pThis->svga.u32SVGAId == SVGA_ID_0)
944	{
945	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
946	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
947	}
948
949	switch (idxReg)
950	{
951	case SVGA_REG_ID:
952	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
953	*pu32 = pThis->svga.u32SVGAId;
954	break;
955
956	case SVGA_REG_ENABLE:
957	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
958	*pu32 = pThis->svga.fEnabled;
959	break;
960
961	case SVGA_REG_WIDTH:
962	{
963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
964	if ( pThis->svga.fEnabled
965	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
966	*pu32 = pThis->svga.uWidth;
967	else
968	{
969	#ifndef IN_RING3
970	rc = VINF_IOM_R3_IOPORT_READ;
971	#else
972	*pu32 = pThisCC->pDrv->cx;
973	#endif
974	}
975	break;
976	}
977
978	case SVGA_REG_HEIGHT:
979	{
980	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
981	if ( pThis->svga.fEnabled
982	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
983	*pu32 = pThis->svga.uHeight;
984	else
985	{
986	#ifndef IN_RING3
987	rc = VINF_IOM_R3_IOPORT_READ;
988	#else
989	*pu32 = pThisCC->pDrv->cy;
990	#endif
991	}
992	break;
993	}
994
995	case SVGA_REG_MAX_WIDTH:
996	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
997	*pu32 = pThis->svga.u32MaxWidth;
998	break;
999
1000	case SVGA_REG_MAX_HEIGHT:
1001	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1002	*pu32 = pThis->svga.u32MaxHeight;
1003	break;
1004
1005	case SVGA_REG_DEPTH:
1006	/* This returns the color depth of the current mode. */
1007	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1008	switch (pThis->svga.uBpp)
1009	{
1010	case 15:
1011	case 16:
1012	case 24:
1013	*pu32 = pThis->svga.uBpp;
1014	break;
1015
1016	default:
1017	case 32:
1018	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1019	break;
1020	}
1021	break;
1022
1023	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1024	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1025	*pu32 = pThis->svga.uHostBpp;
1026	break;
1027
1028	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1030	*pu32 = pThis->svga.uBpp;
1031	break;
1032
1033	case SVGA_REG_PSEUDOCOLOR:
1034	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1035	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1036	break;
1037
1038	case SVGA_REG_RED_MASK:
1039	case SVGA_REG_GREEN_MASK:
1040	case SVGA_REG_BLUE_MASK:
1041	{
1042	uint32_t uBpp;
1043
1044	if (pThis->svga.fEnabled)
1045	uBpp = pThis->svga.uBpp;
1046	else
1047	uBpp = pThis->svga.uHostBpp;
1048
1049	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1050	switch (uBpp)
1051	{
1052	case 8:
1053	u32RedMask = 0x07;
1054	u32GreenMask = 0x38;
1055	u32BlueMask = 0xc0;
1056	break;
1057
1058	case 15:
1059	u32RedMask = 0x0000001f;
1060	u32GreenMask = 0x000003e0;
1061	u32BlueMask = 0x00007c00;
1062	break;
1063
1064	case 16:
1065	u32RedMask = 0x0000001f;
1066	u32GreenMask = 0x000007e0;
1067	u32BlueMask = 0x0000f800;
1068	break;
1069
1070	case 24:
1071	case 32:
1072	default:
1073	u32RedMask = 0x00ff0000;
1074	u32GreenMask = 0x0000ff00;
1075	u32BlueMask = 0x000000ff;
1076	break;
1077	}
1078	switch (idxReg)
1079	{
1080	case SVGA_REG_RED_MASK:
1081	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1082	*pu32 = u32RedMask;
1083	break;
1084
1085	case SVGA_REG_GREEN_MASK:
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1087	*pu32 = u32GreenMask;
1088	break;
1089
1090	case SVGA_REG_BLUE_MASK:
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1092	*pu32 = u32BlueMask;
1093	break;
1094	}
1095	break;
1096	}
1097
1098	case SVGA_REG_BYTES_PER_LINE:
1099	{
1100	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1101	if ( pThis->svga.fEnabled
1102	&& pThis->svga.cbScanline)
1103	*pu32 = pThis->svga.cbScanline;
1104	else
1105	{
1106	#ifndef IN_RING3
1107	rc = VINF_IOM_R3_IOPORT_READ;
1108	#else
1109	*pu32 = pThisCC->pDrv->cbScanline;
1110	#endif
1111	}
1112	break;
1113	}
1114
1115	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1116	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1117	*pu32 = pThis->vram_size;
1118	break;
1119
1120	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1121	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1122	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1123	*pu32 = pThis->GCPhysVRAM;
1124	break;
1125
1126	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1127	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1128	/* Always zero in our case. */
1129	*pu32 = 0;
1130	break;
1131
1132	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1133	{
1134	#ifndef IN_RING3
1135	rc = VINF_IOM_R3_IOPORT_READ;
1136	#else
1137	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1138
1139	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1140	if ( pThis->svga.fEnabled
1141	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1142	{
1143	/* Hardware enabled; return real framebuffer size .*/
1144	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1145	}
1146	else
1147	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1148
1149	pu32 = RT_MIN(pThis->vram_size, pu32);
1150	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1151	#endif
1152	break;
1153	}
1154
1155	case SVGA_REG_CAPABILITIES:
1156	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1157	*pu32 = pThis->svga.u32RegCaps;
1158	break;
1159
1160	case SVGA_REG_MEM_START: /* FIFO start */
1161	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1162	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1163	*pu32 = pThis->svga.GCPhysFIFO;
1164	break;
1165
1166	case SVGA_REG_MEM_SIZE: /* FIFO size */
1167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1168	*pu32 = pThis->svga.cbFIFO;
1169	break;
1170
1171	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1172	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1173	*pu32 = pThis->svga.fConfigured;
1174	break;
1175
1176	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1177	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1178	*pu32 = 0;
1179	break;
1180
1181	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1183	if (pThis->svga.fBusy)
1184	{
1185	#ifndef IN_RING3
1186	/* Go to ring-3 and halt the CPU. */
1187	rc = VINF_IOM_R3_IOPORT_READ;
1188	RT_NOREF(pDevIns);
1189	break;
1190	#else
1191	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1192	/* The guest is basically doing a HLT via the device here, but with
1193	a special wake up condition on FIFO completion. */
1194	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1195	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1196	PVM pVM = PDMDevHlpGetVM(pDevIns);
1197	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1198	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1199	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1200	if (pThis->svga.fBusy)
1201	{
1202	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1203	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1204	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1205	}
1206	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1207	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1208	# else
1209
1210	/* Delay the EMT a bit so the FIFO and others can get some work done.
1211	This used to be a crude 50 ms sleep. The current code tries to be
1212	more efficient, but the consept is still very crude. */
1213	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1214	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1215	RTThreadYield();
1216	if (pThis->svga.fBusy)
1217	{
1218	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1219
1220	if (pThis->svga.fBusy && cRefs == 1)
1221	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1222	if (pThis->svga.fBusy)
1223	{
1224	/** @todo If this code is going to stay, we need to call into the halt/wait
1225	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1226	* suffer when the guest is polling on a busy FIFO. */
1227	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1228	if (cNsMaxWait >= RT_NS_100US)
1229	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1230	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1231	RT_MIN(cNsMaxWait, RT_NS_10MS));
1232	}
1233
1234	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1235	}
1236	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1237	# endif
1238	*pu32 = pThis->svga.fBusy != 0;
1239	#endif
1240	}
1241	else
1242	*pu32 = false;
1243	break;
1244
1245	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1246	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1247	*pu32 = pThis->svga.u32GuestId;
1248	break;
1249
1250	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1251	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1252	*pu32 = pThis->svga.cScratchRegion;
1253	break;
1254
1255	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1257	*pu32 = SVGA_FIFO_NUM_REGS;
1258	break;
1259
1260	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1261	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1262	*pu32 = pThis->svga.u32PitchLock;
1263	break;
1264
1265	case SVGA_REG_IRQMASK: /* Interrupt mask */
1266	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1267	*pu32 = pThis->svga.u32IrqMask;
1268	break;
1269
1270	/* See "Guest memory regions" below. */
1271	case SVGA_REG_GMR_ID:
1272	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1273	*pu32 = pThis->svga.u32CurrentGMRId;
1274	break;
1275
1276	case SVGA_REG_GMR_DESCRIPTOR:
1277	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1278	/* Write only */
1279	*pu32 = 0;
1280	break;
1281
1282	case SVGA_REG_GMR_MAX_IDS:
1283	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1284	*pu32 = pThis->svga.cGMR;
1285	break;
1286
1287	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1288	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1289	*pu32 = VMSVGA_MAX_GMR_PAGES;
1290	break;
1291
1292	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1293	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1294	*pu32 = pThis->svga.fTraces;
1295	break;
1296
1297	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1298	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1299	*pu32 = VMSVGA_MAX_GMR_PAGES;
1300	break;
1301
1302	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1303	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1304	*pu32 = VMSVGA_SURFACE_SIZE;
1305	break;
1306
1307	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1308	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1309	break;
1310
1311	/* Mouse cursor support. */
1312	case SVGA_REG_CURSOR_ID:
1313	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1314	*pu32 = pThis->svga.uCursorID;
1315	break;
1316
1317	case SVGA_REG_CURSOR_X:
1318	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1319	*pu32 = pThis->svga.uCursorX;
1320	break;
1321
1322	case SVGA_REG_CURSOR_Y:
1323	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1324	*pu32 = pThis->svga.uCursorY;
1325	break;
1326
1327	case SVGA_REG_CURSOR_ON:
1328	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1329	*pu32 = pThis->svga.uCursorOn;
1330	break;
1331
1332	/* Legacy multi-monitor support */
1333	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1334	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1335	*pu32 = 1;
1336	break;
1337
1338	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1339	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1340	*pu32 = 0;
1341	break;
1342
1343	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1344	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1345	*pu32 = 0;
1346	break;
1347
1348	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1349	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1350	*pu32 = 0;
1351	break;
1352
1353	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1354	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1355	*pu32 = 0;
1356	break;
1357
1358	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1359	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1360	*pu32 = pThis->svga.uWidth;
1361	break;
1362
1363	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1364	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1365	*pu32 = pThis->svga.uHeight;
1366	break;
1367
1368	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1369	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1370	/* We must return something sensible here otherwise the Linux driver
1371	will take a legacy code path without 3d support. This number also
1372	limits how many screens Linux guests will allow. */
1373	*pu32 = pThis->cMonitors;
1374	break;
1375
1376	default:
1377	{
1378	uint32_t offReg;
1379	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1380	{
1381	RT_UNTRUSTED_VALIDATED_FENCE();
1382	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1383	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1384	}
1385	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1386	{
1387	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1388	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1389	RT_UNTRUSTED_VALIDATED_FENCE();
1390	uint32_t u32 = pThis->last_palette[offReg / 3];
1391	switch (offReg % 3)
1392	{
1393	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1394	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1395	case 2: pu32 = u32 & 0xff; break; / blue */
1396	}
1397	}
1398	else
1399	{
1400	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1401	rc = VINF_IOM_R3_IOPORT_READ;
1402	#else
1403	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1404
1405	/* Do not assert. The guest might be reading all registers. */
1406	LogFunc(("Unknown reg=%#x\n", idxReg));
1407	#endif
1408	}
1409	break;
1410	}
1411	}
1412	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1413	return rc;
1414	}
1415
1416	#ifdef IN_RING3
1417	/**
1418	* Apply the current resolution settings to change the video mode.
1419	*
1420	* @returns VBox status code.
1421	* @param pThis The shared VGA state.
1422	* @param pThisCC The ring-3 VGA state.
1423	*/
1424	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1425	{
1426	/* Always do changemode on FIFO thread. */
1427	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1428
1429	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1430
1431	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1432
1433	if (pThis->svga.fGFBRegisters)
1434	{
1435	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1436	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1437	* deletes all screens other than screen #0, and redefines screen
1438	* #0 according to the specified mode. Drivers that use
1439	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1440	*/
1441
1442	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1443	pScreen->fDefined = true;
1444	pScreen->fModified = true;
1445	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1446	pScreen->idScreen = 0;
1447	pScreen->xOrigin = 0;
1448	pScreen->yOrigin = 0;
1449	pScreen->offVRAM = 0;
1450	pScreen->cbPitch = pThis->svga.cbScanline;
1451	pScreen->cWidth = pThis->svga.uWidth;
1452	pScreen->cHeight = pThis->svga.uHeight;
1453	pScreen->cBpp = pThis->svga.uBpp;
1454
1455	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1456	{
1457	/* Delete screen. */
1458	pScreen = &pSVGAState->aScreens[iScreen];
1459	if (pScreen->fDefined)
1460	{
1461	pScreen->fModified = true;
1462	pScreen->fDefined = false;
1463	}
1464	}
1465	}
1466	else
1467	{
1468	/* "If Screen Objects are supported, they can be used to fully
1469	* replace the functionality provided by the framebuffer registers
1470	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1471	*/
1472	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1473	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1474	pThis->svga.uBpp = pThis->svga.uHostBpp;
1475	}
1476
1477	vmsvgaR3VBVAResize(pThis, pThisCC);
1478
1479	/* Last stuff. For the VGA device screenshot. */
1480	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1481	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1482	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1483	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1484	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1485
1486	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1487	if ( pThis->svga.viewport.cx == 0
1488	&& pThis->svga.viewport.cy == 0)
1489	{
1490	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1491	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1492	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1493	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1494	pThis->svga.viewport.yLowWC = 0;
1495	}
1496
1497	return VINF_SUCCESS;
1498	}
1499
1500	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1501	{
1502	VBVACMDHDR cmd;
1503	cmd.x = (int16_t)(pScreen->xOrigin + x);
1504	cmd.y = (int16_t)(pScreen->yOrigin + y);
1505	cmd.w = (uint16_t)w;
1506	cmd.h = (uint16_t)h;
1507
1508	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1509	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1510	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1511	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1512
1513	return VINF_SUCCESS;
1514	}
1515
1516	#endif /* IN_RING3 */
1517	#if defined(IN_RING0) \|\| defined(IN_RING3)
1518
1519	/**
1520	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1521	*
1522	* @param pThis The shared VGA/VMSVGA instance data.
1523	* @param pThisCC The VGA/VMSVGA state for the current context.
1524	* @param fState The busy state.
1525	*/
1526	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1527	{
1528	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1529
1530	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1531	{
1532	/* Race / unfortunately scheduling. Highly unlikly. */
1533	uint32_t cLoops = 64;
1534	do
1535	{
1536	ASMNopPause();
1537	fState = (pThis->svga.fBusy != 0);
1538	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1539	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1540	}
1541	}
1542
1543
1544	/**
1545	* Update the scanline pitch in response to the guest changing mode
1546	* width/bpp.
1547	*
1548	* @param pThis The shared VGA/VMSVGA state.
1549	* @param pThisCC The VGA/VMSVGA state for the current context.
1550	*/
1551	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1552	{
1553	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1554	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1555	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1556	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1557
1558	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1559	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1560	* location but it has a different meaning.
1561	*/
1562	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1563	uFifoPitchLock = 0;
1564
1565	/* Sanitize values. */
1566	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1567	uFifoPitchLock = 0;
1568	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1569	uRegPitchLock = 0;
1570
1571	/* Prefer the register value to the FIFO value.*/
1572	if (uRegPitchLock)
1573	pThis->svga.cbScanline = uRegPitchLock;
1574	else if (uFifoPitchLock)
1575	pThis->svga.cbScanline = uFifoPitchLock;
1576	else
1577	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1578
1579	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1580	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1581	}
1582
1583	#endif /* IN_RING0 \|\| IN_RING3 */
1584
1585	#ifdef IN_RING3
1586
1587	/**
1588	* Sends cursor position and visibility information from legacy
1589	* SVGA registers to the front-end.
1590	*/
1591	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1592	{
1593	/*
1594	* Writing the X/Y/ID registers does not trigger changes; only writing the
1595	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1596	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1597	* register if they don't have to.
1598	*/
1599	uint32_t x, y, idScreen;
1600	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1601
1602	x = pThis->svga.uCursorX;
1603	y = pThis->svga.uCursorY;
1604	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1605
1606	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1607	* were extended as follows:
1608	*
1609	* SVGA_CURSOR_ON_HIDE 0
1610	* SVGA_CURSOR_ON_SHOW 1
1611	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1612	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1613	*
1614	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1615	* distinguish between the non-zero values but still remember them.
1616	*/
1617	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1618	{
1619	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1620	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1621	}
1622	pThis->svga.uCursorOn = uCursorOn;
1623	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1624	}
1625
1626
1627	/**
1628	* Copy a rectangle of pixels within guest VRAM.
1629	*/
1630	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1631	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1632	{
1633	if (!width \|\| !height)
1634	return; /* Nothing to do, don't even bother. */
1635
1636	/*
1637	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1638	* corresponding to the current display mode.
1639	*/
1640	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1641	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1642	uint8_t const *pSrc;
1643	uint8_t *pDst;
1644	unsigned const cbRectWidth = width * cbPixel;
1645	unsigned uMaxOffset;
1646
1647	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1648	if (uMaxOffset >= cbFrameBuffer)
1649	{
1650	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1651	return; /* Just don't listen to a bad guest. */
1652	}
1653
1654	pSrc = pDst = pThisCC->pbVRam;
1655	pSrc += srcY * cbScanline + srcX * cbPixel;
1656	pDst += dstY * cbScanline + dstX * cbPixel;
1657
1658	if (srcY >= dstY)
1659	{
1660	/* Source below destination, copy top to bottom. */
1661	for (; height > 0; height--)
1662	{
1663	memmove(pDst, pSrc, cbRectWidth);
1664	pSrc += cbScanline;
1665	pDst += cbScanline;
1666	}
1667	}
1668	else
1669	{
1670	/* Source above destination, copy bottom to top. */
1671	pSrc += cbScanline * (height - 1);
1672	pDst += cbScanline * (height - 1);
1673	for (; height > 0; height--)
1674	{
1675	memmove(pDst, pSrc, cbRectWidth);
1676	pSrc -= cbScanline;
1677	pDst -= cbScanline;
1678	}
1679	}
1680	}
1681
1682	#endif /* IN_RING3 */
1683
1684
1685	/**
1686	* Write port register
1687	*
1688	* @returns Strict VBox status code.
1689	* @param pDevIns The device instance.
1690	* @param pThis The shared VGA/VMSVGA state.
1691	* @param pThisCC The VGA/VMSVGA state for the current context.
1692	* @param u32 Value to write
1693	*/
1694	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1695	{
1696	#ifdef IN_RING3
1697	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1698	#endif
1699	VBOXSTRICTRC rc = VINF_SUCCESS;
1700	RT_NOREF(pThisCC);
1701
1702	/* Rough index register validation. */
1703	uint32_t idxReg = pThis->svga.u32IndexReg;
1704	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1705	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1706	VINF_IOM_R3_IOPORT_WRITE);
1707	#else
1708	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1709	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1710	VINF_SUCCESS);
1711	#endif
1712	RT_UNTRUSTED_VALIDATED_FENCE();
1713
1714	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1715	if ( idxReg >= SVGA_REG_CAPABILITIES
1716	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1717	{
1718	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1719	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1720	}
1721	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1722	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1723	switch (idxReg)
1724	{
1725	case SVGA_REG_WIDTH:
1726	case SVGA_REG_HEIGHT:
1727	case SVGA_REG_PITCHLOCK:
1728	case SVGA_REG_BITS_PER_PIXEL:
1729	pThis->svga.fGFBRegisters = true;
1730	break;
1731	default:
1732	break;
1733	}
1734
1735	switch (idxReg)
1736	{
1737	case SVGA_REG_ID:
1738	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1739	if ( u32 == SVGA_ID_0
1740	\|\| u32 == SVGA_ID_1
1741	\|\| u32 == SVGA_ID_2)
1742	pThis->svga.u32SVGAId = u32;
1743	else
1744	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1745	break;
1746
1747	case SVGA_REG_ENABLE:
1748	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1749	#ifdef IN_RING3
1750	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1751	&& pThis->svga.fEnabled == false)
1752	{
1753	/* Make a backup copy of the first 512kb in order to save font data etc. */
1754	/** @todo should probably swap here, rather than copy + zero */
1755	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1756	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1757	}
1758
1759	pThis->svga.fEnabled = u32;
1760	if (pThis->svga.fEnabled)
1761	{
1762	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1763	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1764	{
1765	/* Keep the current mode. */
1766	pThis->svga.uWidth = pThisCC->pDrv->cx;
1767	pThis->svga.uHeight = pThisCC->pDrv->cy;
1768	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1769	}
1770
1771	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1772	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1773	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1774	# ifdef LOG_ENABLED
1775	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1776	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1777	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1778	# endif
1779
1780	/* Disable or enable dirty page tracking according to the current fTraces value. */
1781	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1782
1783	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1784	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1785	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1786
1787	/* Make the cursor visible again as needed. */
1788	if (pSVGAState->Cursor.fActive)
1789	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1790	}
1791	else
1792	{
1793	/* Make sure the cursor is off. */
1794	if (pSVGAState->Cursor.fActive)
1795	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1796
1797	/* Restore the text mode backup. */
1798	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1799
1800	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1801
1802	/* Enable dirty page tracking again when going into legacy mode. */
1803	vmsvgaR3SetTraces(pDevIns, pThis, true);
1804
1805	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1806	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1807	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1808
1809	/* Clear the pitch lock. */
1810	pThis->svga.u32PitchLock = 0;
1811	}
1812	#else /* !IN_RING3 */
1813	rc = VINF_IOM_R3_IOPORT_WRITE;
1814	#endif /* !IN_RING3 */
1815	break;
1816
1817	case SVGA_REG_WIDTH:
1818	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1819	if (pThis->svga.uWidth != u32)
1820	{
1821	#if defined(IN_RING3) \|\| defined(IN_RING0)
1822	pThis->svga.uWidth = u32;
1823	vmsvgaHCUpdatePitch(pThis, pThisCC);
1824	if (pThis->svga.fEnabled)
1825	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1826	#else
1827	rc = VINF_IOM_R3_IOPORT_WRITE;
1828	#endif
1829	}
1830	/* else: nop */
1831	break;
1832
1833	case SVGA_REG_HEIGHT:
1834	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1835	if (pThis->svga.uHeight != u32)
1836	{
1837	pThis->svga.uHeight = u32;
1838	if (pThis->svga.fEnabled)
1839	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1840	}
1841	/* else: nop */
1842	break;
1843
1844	case SVGA_REG_DEPTH:
1845	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1846	/** @todo read-only?? */
1847	break;
1848
1849	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1850	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1851	if (pThis->svga.uBpp != u32)
1852	{
1853	#if defined(IN_RING3) \|\| defined(IN_RING0)
1854	pThis->svga.uBpp = u32;
1855	vmsvgaHCUpdatePitch(pThis, pThisCC);
1856	if (pThis->svga.fEnabled)
1857	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1858	#else
1859	rc = VINF_IOM_R3_IOPORT_WRITE;
1860	#endif
1861	}
1862	/* else: nop */
1863	break;
1864
1865	case SVGA_REG_PSEUDOCOLOR:
1866	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1867	break;
1868
1869	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1870	#ifdef IN_RING3
1871	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1872	pThis->svga.fConfigured = u32;
1873	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1874	if (!pThis->svga.fConfigured)
1875	pThis->svga.fTraces = true;
1876	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1877	#else
1878	rc = VINF_IOM_R3_IOPORT_WRITE;
1879	#endif
1880	break;
1881
1882	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1883	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1884	if ( pThis->svga.fEnabled
1885	&& pThis->svga.fConfigured)
1886	{
1887	#if defined(IN_RING3) \|\| defined(IN_RING0)
1888	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1889	/*
1890	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1891	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1892	*/
1893	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1894	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1895	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1896
1897	/* Kick the FIFO thread to start processing commands again. */
1898	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1899	#else
1900	rc = VINF_IOM_R3_IOPORT_WRITE;
1901	#endif
1902	}
1903	/* else nothing to do. */
1904	else
1905	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1906
1907	break;
1908
1909	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1910	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1911	break;
1912
1913	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1914	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1915	pThis->svga.u32GuestId = u32;
1916	break;
1917
1918	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1919	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1920	pThis->svga.u32PitchLock = u32;
1921	/* Should this also update the FIFO pitch lock? Unclear. */
1922	break;
1923
1924	case SVGA_REG_IRQMASK: /* Interrupt mask */
1925	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1926	pThis->svga.u32IrqMask = u32;
1927
1928	/* Irq pending after the above change? */
1929	if (pThis->svga.u32IrqStatus & u32)
1930	{
1931	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1932	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1933	}
1934	else
1935	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1936	break;
1937
1938	/* Mouse cursor support */
1939	case SVGA_REG_CURSOR_ID:
1940	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1941	pThis->svga.uCursorID = u32;
1942	break;
1943
1944	case SVGA_REG_CURSOR_X:
1945	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1946	pThis->svga.uCursorX = u32;
1947	break;
1948
1949	case SVGA_REG_CURSOR_Y:
1950	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1951	pThis->svga.uCursorY = u32;
1952	break;
1953
1954	case SVGA_REG_CURSOR_ON:
1955	#ifdef IN_RING3
1956	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1957	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1958	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1959	#else
1960	rc = VINF_IOM_R3_IOPORT_WRITE;
1961	#endif
1962	break;
1963
1964	/* Legacy multi-monitor support */
1965	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1967	break;
1968	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1970	break;
1971	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1973	break;
1974	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1976	break;
1977	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1979	break;
1980	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1982	break;
1983	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1984	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1985	break;
1986	#ifdef VBOX_WITH_VMSVGA3D
1987	/* See "Guest memory regions" below. */
1988	case SVGA_REG_GMR_ID:
1989	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1990	pThis->svga.u32CurrentGMRId = u32;
1991	break;
1992
1993	case SVGA_REG_GMR_DESCRIPTOR:
1994	# ifndef IN_RING3
1995	rc = VINF_IOM_R3_IOPORT_WRITE;
1996	break;
1997	# else /* IN_RING3 */
1998	{
1999	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2000
2001	/* Validate current GMR id. */
2002	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2003	AssertBreak(idGMR < pThis->svga.cGMR);
2004	RT_UNTRUSTED_VALIDATED_FENCE();
2005
2006	/* Free the old GMR if present. */
2007	vmsvgaR3GmrFree(pThisCC, idGMR);
2008
2009	/* Just undefine the GMR? */
2010	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2011	if (GCPhys == 0)
2012	{
2013	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2014	break;
2015	}
2016
2017
2018	/* Never cross a page boundary automatically. */
2019	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2020	uint32_t cPagesTotal = 0;
2021	uint32_t iDesc = 0;
2022	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2023	uint32_t cLoops = 0;
2024	RTGCPHYS GCPhysBase = GCPhys;
2025	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2026	{
2027	/* Read descriptor. */
2028	SVGAGuestMemDescriptor desc;
2029	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2030	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2031
2032	if (desc.numPages != 0)
2033	{
2034	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2035	cPagesTotal += desc.numPages;
2036	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2037
2038	if ((iDesc & 15) == 0)
2039	{
2040	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2041	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2042	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2043	}
2044
2045	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2046	paDescs[iDesc++].numPages = desc.numPages;
2047
2048	/* Continue with the next descriptor. */
2049	GCPhys += sizeof(desc);
2050	}
2051	else if (desc.ppn == 0)
2052	break; /* terminator */
2053	else /* Pointer to the next physical page of descriptors. */
2054	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2055
2056	cLoops++;
2057	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2058	}
2059
2060	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2061	if (RT_SUCCESS(rc))
2062	{
2063	/* Commit the GMR. */
2064	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2065	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2066	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2067	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2068	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2069	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2070	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2071	}
2072	else
2073	{
2074	RTMemFree(paDescs);
2075	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2076	}
2077	break;
2078	}
2079	# endif /* IN_RING3 */
2080	#endif // VBOX_WITH_VMSVGA3D
2081
2082	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2084	if (pThis->svga.fTraces == u32)
2085	break; /* nothing to do */
2086
2087	#ifdef IN_RING3
2088	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2089	#else
2090	rc = VINF_IOM_R3_IOPORT_WRITE;
2091	#endif
2092	break;
2093
2094	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2095	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2096	break;
2097
2098	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2099	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2100	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2101	break;
2102
2103	case SVGA_REG_FB_START:
2104	case SVGA_REG_MEM_START:
2105	case SVGA_REG_HOST_BITS_PER_PIXEL:
2106	case SVGA_REG_MAX_WIDTH:
2107	case SVGA_REG_MAX_HEIGHT:
2108	case SVGA_REG_VRAM_SIZE:
2109	case SVGA_REG_FB_SIZE:
2110	case SVGA_REG_CAPABILITIES:
2111	case SVGA_REG_MEM_SIZE:
2112	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2113	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2114	case SVGA_REG_BYTES_PER_LINE:
2115	case SVGA_REG_FB_OFFSET:
2116	case SVGA_REG_RED_MASK:
2117	case SVGA_REG_GREEN_MASK:
2118	case SVGA_REG_BLUE_MASK:
2119	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2120	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2121	case SVGA_REG_GMR_MAX_IDS:
2122	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2123	/* Read only - ignore. */
2124	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2125	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2126	break;
2127
2128	default:
2129	{
2130	uint32_t offReg;
2131	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2132	{
2133	RT_UNTRUSTED_VALIDATED_FENCE();
2134	pThis->svga.au32ScratchRegion[offReg] = u32;
2135	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2136	}
2137	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2138	{
2139	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2140	Btw, see rgb_to_pixel32. */
2141	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2142	u32 &= 0xff;
2143	RT_UNTRUSTED_VALIDATED_FENCE();
2144	uint32_t uRgb = pThis->last_palette[offReg / 3];
2145	switch (offReg % 3)
2146	{
2147	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2148	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2149	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2150	}
2151	pThis->last_palette[offReg / 3] = uRgb;
2152	}
2153	else
2154	{
2155	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2156	rc = VINF_IOM_R3_IOPORT_WRITE;
2157	#else
2158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2159	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2160	#endif
2161	}
2162	break;
2163	}
2164	}
2165	return rc;
2166	}
2167
2168	/**
2169	* @callback_method_impl{FNIOMIOPORTNEWIN}
2170	*/
2171	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2172	{
2173	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2174	RT_NOREF_PV(pvUser);
2175
2176	/* Only dword accesses. */
2177	if (cb == 4)
2178	{
2179	switch (offPort)
2180	{
2181	case SVGA_INDEX_PORT:
2182	*pu32 = pThis->svga.u32IndexReg;
2183	break;
2184
2185	case SVGA_VALUE_PORT:
2186	return vmsvgaReadPort(pDevIns, pThis, pu32);
2187
2188	case SVGA_BIOS_PORT:
2189	Log(("Ignoring BIOS port read\n"));
2190	*pu32 = 0;
2191	break;
2192
2193	case SVGA_IRQSTATUS_PORT:
2194	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2195	*pu32 = pThis->svga.u32IrqStatus;
2196	break;
2197
2198	default:
2199	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2200	*pu32 = UINT32_MAX;
2201	break;
2202	}
2203	}
2204	else
2205	{
2206	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2207	*pu32 = UINT32_MAX;
2208	}
2209	return VINF_SUCCESS;
2210	}
2211
2212	/**
2213	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2214	*/
2215	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2216	{
2217	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2218	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2219	RT_NOREF_PV(pvUser);
2220
2221	/* Only dword accesses. */
2222	if (cb == 4)
2223	switch (offPort)
2224	{
2225	case SVGA_INDEX_PORT:
2226	pThis->svga.u32IndexReg = u32;
2227	break;
2228
2229	case SVGA_VALUE_PORT:
2230	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2231
2232	case SVGA_BIOS_PORT:
2233	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2234	break;
2235
2236	case SVGA_IRQSTATUS_PORT:
2237	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2238	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2239	/* Clear the irq in case all events have been cleared. */
2240	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2241	{
2242	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2243	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2244	}
2245	break;
2246
2247	default:
2248	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2249	break;
2250	}
2251	else
2252	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2253
2254	return VINF_SUCCESS;
2255	}
2256
2257	#ifdef IN_RING3
2258
2259	# ifdef DEBUG_FIFO_ACCESS
2260	/**
2261	* Handle FIFO memory access.
2262	* @returns VBox status code.
2263	* @param pVM VM handle.
2264	* @param pThis The shared VGA/VMSVGA instance data.
2265	* @param GCPhys The access physical address.
2266	* @param fWriteAccess Read or write access
2267	*/
2268	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2269	{
2270	RT_NOREF(pVM);
2271	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2272	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2273
2274	switch (GCPhysOffset >> 2)
2275	{
2276	case SVGA_FIFO_MIN:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_MAX:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_NEXT_CMD:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_STOP:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_CAPABILITIES:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_FLAGS:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_FENCE:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_3D_HWVERSION:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_PITCHLOCK:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_CURSOR_ON:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_CURSOR_X:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_CURSOR_Y:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_CURSOR_COUNT:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_RESERVED:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_CURSOR_SCREEN_ID:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_DEAD:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_HWVERSION_REVISED:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_3D_CAPS_LAST:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_GUEST_3D_HWVERSION:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_FENCE_GOAL:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	case SVGA_FIFO_BUSY:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	default:
2592	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2593	break;
2594	}
2595
2596	return VINF_EM_RAW_EMULATE_INSTR;
2597	}
2598	# endif /* DEBUG_FIFO_ACCESS */
2599
2600	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2601	/**
2602	* HC access handler for the FIFO.
2603	*
2604	* @returns VINF_SUCCESS if the handler have carried out the operation.
2605	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2606	* @param pVM VM Handle.
2607	* @param pVCpu The cross context CPU structure for the calling EMT.
2608	* @param GCPhys The physical address the guest is writing to.
2609	* @param pvPhys The HC mapping of that address.
2610	* @param pvBuf What the guest is reading/writing.
2611	* @param cbBuf How much it's reading/writing.
2612	* @param enmAccessType The access type.
2613	* @param enmOrigin Who is making the access.
2614	* @param pvUser User argument.
2615	*/
2616	static DECLCALLBACK(VBOXSTRICTRC)
2617	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2618	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2619	{
2620	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2621	PVGASTATE pThis = (PVGASTATE)pvUser;
2622	AssertPtr(pThis);
2623
2624	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2625	/*
2626	* Wake up the FIFO thread as it might have work to do now.
2627	*/
2628	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2629	AssertLogRelRC(rc);
2630	# endif
2631
2632	# ifdef DEBUG_FIFO_ACCESS
2633	/*
2634	* When in debug-fifo-access mode, we do not disable the access handler,
2635	* but leave it on as we wish to catch all access.
2636	*/
2637	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2638	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2639	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2640	/*
2641	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2642	*/
2643	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2644	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2645	# endif
2646	if (RT_SUCCESS(rc))
2647	return VINF_PGM_HANDLER_DO_DEFAULT;
2648	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2649	return rc;
2650	}
2651	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2652
2653	#endif /* IN_RING3 */
2654
2655	#ifdef DEBUG_GMR_ACCESS
2656	# ifdef IN_RING3
2657
2658	/**
2659	* HC access handler for the FIFO.
2660	*
2661	* @returns VINF_SUCCESS if the handler have carried out the operation.
2662	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2663	* @param pVM VM Handle.
2664	* @param pVCpu The cross context CPU structure for the calling EMT.
2665	* @param GCPhys The physical address the guest is writing to.
2666	* @param pvPhys The HC mapping of that address.
2667	* @param pvBuf What the guest is reading/writing.
2668	* @param cbBuf How much it's reading/writing.
2669	* @param enmAccessType The access type.
2670	* @param enmOrigin Who is making the access.
2671	* @param pvUser User argument.
2672	*/
2673	static DECLCALLBACK(VBOXSTRICTRC)
2674	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2675	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2676	{
2677	PVGASTATE pThis = (PVGASTATE)pvUser;
2678	Assert(pThis);
2679	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2680	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2681
2682	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2683
2684	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2685	{
2686	PGMR pGMR = &pSVGAState->paGMR[i];
2687
2688	if (pGMR->numDescriptors)
2689	{
2690	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2691	{
2692	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2693	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2694	{
2695	/*
2696	* Turn off the write handler for this particular page and make it R/W.
2697	* Then return telling the caller to restart the guest instruction.
2698	*/
2699	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2700	AssertRC(rc);
2701	return VINF_PGM_HANDLER_DO_DEFAULT;
2702	}
2703	}
2704	}
2705	}
2706
2707	return VINF_PGM_HANDLER_DO_DEFAULT;
2708	}
2709
2710	/** Callback handler for VMR3ReqCallWaitU */
2711	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2712	{
2713	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2714	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2715	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2716	int rc;
2717
2718	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2719	{
2720	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2721	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2722	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2723	AssertRC(rc);
2724	}
2725	return VINF_SUCCESS;
2726	}
2727
2728	/** Callback handler for VMR3ReqCallWaitU */
2729	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2730	{
2731	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2732	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2733	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2734
2735	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2736	{
2737	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2738	AssertRC(rc);
2739	}
2740	return VINF_SUCCESS;
2741	}
2742
2743	/** Callback handler for VMR3ReqCallWaitU */
2744	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2745	{
2746	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2747
2748	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2749	{
2750	PGMR pGMR = &pSVGAState->paGMR[i];
2751
2752	if (pGMR->numDescriptors)
2753	{
2754	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2755	{
2756	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2757	AssertRC(rc);
2758	}
2759	}
2760	}
2761	return VINF_SUCCESS;
2762	}
2763
2764	# endif /* IN_RING3 */
2765	#endif /* DEBUG_GMR_ACCESS */
2766
2767	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2768
2769	#ifdef IN_RING3
2770
2771
2772	/**
2773	* Common worker for changing the pointer shape.
2774	*
2775	* @param pThisCC The VGA/VMSVGA state for ring-3.
2776	* @param pSVGAState The VMSVGA ring-3 instance data.
2777	* @param fAlpha Whether there is alpha or not.
2778	* @param xHot Hotspot x coordinate.
2779	* @param yHot Hotspot y coordinate.
2780	* @param cx Width.
2781	* @param cy Height.
2782	* @param pbData Heap copy of the cursor data. Consumed.
2783	* @param cbData The size of the data.
2784	*/
2785	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2786	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2787	{
2788	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2789	# ifdef LOG_ENABLED
2790	if (LogIs2Enabled())
2791	{
2792	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2793	if (!fAlpha)
2794	{
2795	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2796	for (uint32_t y = 0; y < cy; y++)
2797	{
2798	Log2(("%3u:", y));
2799	uint8_t const pbLine = &pbData[y cbAndLine];
2800	for (uint32_t x = 0; x < cx; x += 8)
2801	{
2802	uint8_t b = pbLine[x / 8];
2803	char szByte[12];
2804	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2805	szByte[1] = b & 0x40 ? '*' : ' ';
2806	szByte[2] = b & 0x20 ? '*' : ' ';
2807	szByte[3] = b & 0x10 ? '*' : ' ';
2808	szByte[4] = b & 0x08 ? '*' : ' ';
2809	szByte[5] = b & 0x04 ? '*' : ' ';
2810	szByte[6] = b & 0x02 ? '*' : ' ';
2811	szByte[7] = b & 0x01 ? '*' : ' ';
2812	szByte[8] = '\0';
2813	Log2(("%s", szByte));
2814	}
2815	Log2(("\n"));
2816	}
2817	}
2818
2819	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2820	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2821	for (uint32_t y = 0; y < cy; y++)
2822	{
2823	Log2(("%3u:", y));
2824	uint32_t const pu32Line = &pu32Xor[y cx];
2825	for (uint32_t x = 0; x < cx; x++)
2826	Log2((" %08x", pu32Line[x]));
2827	Log2(("\n"));
2828	}
2829	}
2830	# endif
2831
2832	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2833	AssertRC(rc);
2834
2835	if (pSVGAState->Cursor.fActive)
2836	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
2837
2838	pSVGAState->Cursor.fActive = true;
2839	pSVGAState->Cursor.xHotspot = xHot;
2840	pSVGAState->Cursor.yHotspot = yHot;
2841	pSVGAState->Cursor.width = cx;
2842	pSVGAState->Cursor.height = cy;
2843	pSVGAState->Cursor.cbData = cbData;
2844	pSVGAState->Cursor.pData = pbData;
2845	}
2846
2847
2848	/**
2849	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2850	*
2851	* @param pThis The shared VGA/VMSVGA state.
2852	* @param pThisCC The VGA/VMSVGA state for ring-3.
2853	* @param pSVGAState The VMSVGA ring-3 instance data.
2854	* @param pCursor The cursor.
2855	* @param pbSrcAndMask The AND mask.
2856	* @param cbSrcAndLine The scanline length of the AND mask.
2857	* @param pbSrcXorMask The XOR mask.
2858	* @param cbSrcXorLine The scanline length of the XOR mask.
2859	*/
2860	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2861	SVGAFifoCmdDefineCursor const *pCursor,
2862	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2863	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2864	{
2865	uint32_t const cx = pCursor->width;
2866	uint32_t const cy = pCursor->height;
2867
2868	/*
2869	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2870	* The AND data uses 8-bit aligned scanlines.
2871	* The XOR data must be starting on a 32-bit boundrary.
2872	*/
2873	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2874	uint32_t cbDstAndMask = cbDstAndLine * cy;
2875	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2876	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2877
2878	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2879	AssertReturnVoid(pbCopy);
2880
2881	/* Convert the AND mask. */
2882	uint8_t *pbDst = pbCopy;
2883	uint8_t const *pbSrc = pbSrcAndMask;
2884	switch (pCursor->andMaskDepth)
2885	{
2886	case 1:
2887	if (cbSrcAndLine == cbDstAndLine)
2888	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2889	else
2890	{
2891	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2892	for (uint32_t y = 0; y < cy; y++)
2893	{
2894	memcpy(pbDst, pbSrc, cbDstAndLine);
2895	pbDst += cbDstAndLine;
2896	pbSrc += cbSrcAndLine;
2897	}
2898	}
2899	break;
2900	/* Should take the XOR mask into account for the multi-bit AND mask. */
2901	case 8:
2902	for (uint32_t y = 0; y < cy; y++)
2903	{
2904	for (uint32_t x = 0; x < cx; )
2905	{
2906	uint8_t bDst = 0;
2907	uint8_t fBit = 0x80;
2908	do
2909	{
2910	uintptr_t const idxPal = pbSrc[x] * 3;
2911	if ((( pThis->last_palette[idxPal]
2912	\| (pThis->last_palette[idxPal] >> 8)
2913	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2914	bDst \|= fBit;
2915	fBit >>= 1;
2916	x++;
2917	} while (x < cx && (x & 7));
2918	pbDst[(x - 1) / 8] = bDst;
2919	}
2920	pbDst += cbDstAndLine;
2921	pbSrc += cbSrcAndLine;
2922	}
2923	break;
2924	case 15:
2925	for (uint32_t y = 0; y < cy; y++)
2926	{
2927	for (uint32_t x = 0; x < cx; )
2928	{
2929	uint8_t bDst = 0;
2930	uint8_t fBit = 0x80;
2931	do
2932	{
2933	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2934	bDst \|= fBit;
2935	fBit >>= 1;
2936	x++;
2937	} while (x < cx && (x & 7));
2938	pbDst[(x - 1) / 8] = bDst;
2939	}
2940	pbDst += cbDstAndLine;
2941	pbSrc += cbSrcAndLine;
2942	}
2943	break;
2944	case 16:
2945	for (uint32_t y = 0; y < cy; y++)
2946	{
2947	for (uint32_t x = 0; x < cx; )
2948	{
2949	uint8_t bDst = 0;
2950	uint8_t fBit = 0x80;
2951	do
2952	{
2953	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2954	bDst \|= fBit;
2955	fBit >>= 1;
2956	x++;
2957	} while (x < cx && (x & 7));
2958	pbDst[(x - 1) / 8] = bDst;
2959	}
2960	pbDst += cbDstAndLine;
2961	pbSrc += cbSrcAndLine;
2962	}
2963	break;
2964	case 24:
2965	for (uint32_t y = 0; y < cy; y++)
2966	{
2967	for (uint32_t x = 0; x < cx; )
2968	{
2969	uint8_t bDst = 0;
2970	uint8_t fBit = 0x80;
2971	do
2972	{
2973	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2974	bDst \|= fBit;
2975	fBit >>= 1;
2976	x++;
2977	} while (x < cx && (x & 7));
2978	pbDst[(x - 1) / 8] = bDst;
2979	}
2980	pbDst += cbDstAndLine;
2981	pbSrc += cbSrcAndLine;
2982	}
2983	break;
2984	case 32:
2985	for (uint32_t y = 0; y < cy; y++)
2986	{
2987	for (uint32_t x = 0; x < cx; )
2988	{
2989	uint8_t bDst = 0;
2990	uint8_t fBit = 0x80;
2991	do
2992	{
2993	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2994	bDst \|= fBit;
2995	fBit >>= 1;
2996	x++;
2997	} while (x < cx && (x & 7));
2998	pbDst[(x - 1) / 8] = bDst;
2999	}
3000	pbDst += cbDstAndLine;
3001	pbSrc += cbSrcAndLine;
3002	}
3003	break;
3004	default:
3005	RTMemFreeZ(pbCopy, cbCopy);
3006	AssertFailedReturnVoid();
3007	}
3008
3009	/* Convert the XOR mask. */
3010	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
3011	pbSrc = pbSrcXorMask;
3012	switch (pCursor->xorMaskDepth)
3013	{
3014	case 1:
3015	for (uint32_t y = 0; y < cy; y++)
3016	{
3017	for (uint32_t x = 0; x < cx; )
3018	{
3019	/* most significant bit is the left most one. */
3020	uint8_t bSrc = pbSrc[x / 8];
3021	do
3022	{
3023	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
3024	bSrc <<= 1;
3025	x++;
3026	} while ((x & 7) && x < cx);
3027	}
3028	pbSrc += cbSrcXorLine;
3029	}
3030	break;
3031	case 8:
3032	for (uint32_t y = 0; y < cy; y++)
3033	{
3034	for (uint32_t x = 0; x < cx; x++)
3035	{
3036	uint32_t u = pThis->last_palette[pbSrc[x]];
3037	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3038	}
3039	pbSrc += cbSrcXorLine;
3040	}
3041	break;
3042	case 15: /* Src: RGB-5-5-5 */
3043	for (uint32_t y = 0; y < cy; y++)
3044	{
3045	for (uint32_t x = 0; x < cx; x++)
3046	{
3047	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3048	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3049	((uValue >> 5) & 0x1f) << 3,
3050	((uValue >> 10) & 0x1f) << 3, 0);
3051	}
3052	pbSrc += cbSrcXorLine;
3053	}
3054	break;
3055	case 16: /* Src: RGB-5-6-5 */
3056	for (uint32_t y = 0; y < cy; y++)
3057	{
3058	for (uint32_t x = 0; x < cx; x++)
3059	{
3060	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3061	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3062	((uValue >> 5) & 0x3f) << 2,
3063	((uValue >> 11) & 0x1f) << 3, 0);
3064	}
3065	pbSrc += cbSrcXorLine;
3066	}
3067	break;
3068	case 24:
3069	for (uint32_t y = 0; y < cy; y++)
3070	{
3071	for (uint32_t x = 0; x < cx; x++)
3072	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3073	pbSrc += cbSrcXorLine;
3074	}
3075	break;
3076	case 32:
3077	for (uint32_t y = 0; y < cy; y++)
3078	{
3079	for (uint32_t x = 0; x < cx; x++)
3080	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3081	pbSrc += cbSrcXorLine;
3082	}
3083	break;
3084	default:
3085	RTMemFreeZ(pbCopy, cbCopy);
3086	AssertFailedReturnVoid();
3087	}
3088
3089	/*
3090	* Pass it to the frontend/whatever.
3091	*/
3092	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3093	}
3094
3095
3096	/**
3097	* Worker for vmsvgaR3FifoThread that handles an external command.
3098	*
3099	* @param pDevIns The device instance.
3100	* @param pThis The shared VGA/VMSVGA instance data.
3101	* @param pThisCC The VGA/VMSVGA state for ring-3.
3102	*/
3103	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3104	{
3105	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3106	switch (pThis->svga.u8FIFOExtCommand)
3107	{
3108	case VMSVGA_FIFO_EXTCMD_RESET:
3109	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3110	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3111
3112	vmsvgaR3ResetScreens(pThis, pThisCC);
3113	# ifdef VBOX_WITH_VMSVGA3D
3114	if (pThis->svga.f3DEnabled)
3115	{
3116	/* The 3d subsystem must be reset from the fifo thread. */
3117	vmsvga3dReset(pThisCC);
3118	}
3119	# endif
3120	break;
3121
3122	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3123	Log(("vmsvgaR3FifoLoop: power off.\n"));
3124	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3125
3126	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3127	vmsvgaR3ResetScreens(pThis, pThisCC);
3128	break;
3129
3130	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3131	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3132	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3133	# ifdef VBOX_WITH_VMSVGA3D
3134	if (pThis->svga.f3DEnabled)
3135	{
3136	/* The 3d subsystem must be shut down from the fifo thread. */
3137	vmsvga3dTerminate(pThisCC);
3138	}
3139	# endif
3140	break;
3141
3142	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3143	{
3144	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3145	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3146	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3147	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3148	# ifdef VBOX_WITH_VMSVGA3D
3149	if (pThis->svga.f3DEnabled)
3150	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3151	# endif
3152	break;
3153	}
3154
3155	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3156	{
3157	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3158	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3159	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3160	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3161	# ifdef VBOX_WITH_VMSVGA3D
3162	if (pThis->svga.f3DEnabled)
3163	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3164	# endif
3165	break;
3166	}
3167
3168	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3169	{
3170	# ifdef VBOX_WITH_VMSVGA3D
3171	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3172	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3173	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3174	# endif
3175	break;
3176	}
3177
3178
3179	default:
3180	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3181	break;
3182	}
3183
3184	/*
3185	* Signal the end of the external command.
3186	*/
3187	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3188	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3189	ASMMemoryFence(); /* paranoia^2 */
3190	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3191	AssertLogRelRC(rc);
3192	}
3193
3194	/**
3195	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3196	* doing a job on the FIFO thread (even when it's officially suspended).
3197	*
3198	* @returns VBox status code (fully asserted).
3199	* @param pDevIns The device instance.
3200	* @param pThis The shared VGA/VMSVGA instance data.
3201	* @param pThisCC The VGA/VMSVGA state for ring-3.
3202	* @param uExtCmd The command to execute on the FIFO thread.
3203	* @param pvParam Pointer to command parameters.
3204	* @param cMsWait The time to wait for the command, given in
3205	* milliseconds.
3206	*/
3207	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3208	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3209	{
3210	Assert(cMsWait >= RT_MS_1SEC * 5);
3211	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3212	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3213
3214	int rc;
3215	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3216	PDMTHREADSTATE enmState = pThread->enmState;
3217	if (enmState == PDMTHREADSTATE_SUSPENDED)
3218	{
3219	/*
3220	* The thread is suspended, we have to temporarily wake it up so it can
3221	* perform the task.
3222	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3223	*/
3224	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3225	/* Post the request. */
3226	pThis->svga.fFifoExtCommandWakeup = true;
3227	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3228	pThis->svga.u8FIFOExtCommand = uExtCmd;
3229	ASMMemoryFence(); /* paranoia^3 */
3230
3231	/* Resume the thread. */
3232	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3233	AssertLogRelRC(rc);
3234	if (RT_SUCCESS(rc))
3235	{
3236	/* Wait. Take care in case the semaphore was already posted (same as below). */
3237	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3238	if ( rc == VINF_SUCCESS
3239	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3240	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3241	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3242	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3243
3244	/* suspend the thread */
3245	pThis->svga.fFifoExtCommandWakeup = false;
3246	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3247	AssertLogRelRC(rc2);
3248	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3249	rc = rc2;
3250	}
3251	pThis->svga.fFifoExtCommandWakeup = false;
3252	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3253	}
3254	else if (enmState == PDMTHREADSTATE_RUNNING)
3255	{
3256	/*
3257	* The thread is running, should only happen during reset and vmsvga3dsfc.
3258	* We ASSUME not racing code here, both wrt thread state and ext commands.
3259	*/
3260	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3261	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
3262
3263	/* Post the request. */
3264	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3265	pThis->svga.u8FIFOExtCommand = uExtCmd;
3266	ASMMemoryFence(); /* paranoia^2 */
3267	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3268	AssertLogRelRC(rc);
3269
3270	/* Wait. Take care in case the semaphore was already posted (same as above). */
3271	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3272	if ( rc == VINF_SUCCESS
3273	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3274	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3275	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3276	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3277
3278	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3279	}
3280	else
3281	{
3282	/*
3283	* Something is wrong with the thread!
3284	*/
3285	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3286	rc = VERR_INVALID_STATE;
3287	}
3288	return rc;
3289	}
3290
3291
3292	/**
3293	* Marks the FIFO non-busy, notifying any waiting EMTs.
3294	*
3295	* @param pDevIns The device instance.
3296	* @param pThis The shared VGA/VMSVGA instance data.
3297	* @param pThisCC The VGA/VMSVGA state for ring-3.
3298	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3299	* @param offFifoMin The start byte offset of the command FIFO.
3300	*/
3301	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3302	{
3303	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3304	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3305	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3306
3307	/* Wake up any waiting EMTs. */
3308	if (pSVGAState->cBusyDelayedEmts > 0)
3309	{
3310	# ifdef VMSVGA_USE_EMT_HALT_CODE
3311	PVM pVM = PDMDevHlpGetVM(pDevIns);
3312	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3313	if (idCpu != NIL_VMCPUID)
3314	{
3315	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3316	while (idCpu-- > 0)
3317	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3318	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3319	}
3320	# else
3321	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3322	AssertRC(rc2);
3323	# endif
3324	}
3325	}
3326
3327	/**
3328	* Reads (more) payload into the command buffer.
3329	*
3330	* @returns pbBounceBuf on success
3331	* @retval (void *)1 if the thread was requested to stop.
3332	* @retval NULL on FIFO error.
3333	*
3334	* @param cbPayloadReq The number of bytes of payload requested.
3335	* @param pFIFO The FIFO.
3336	* @param offCurrentCmd The FIFO byte offset of the current command.
3337	* @param offFifoMin The start byte offset of the command FIFO.
3338	* @param offFifoMax The end byte offset of the command FIFO.
3339	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3340	* always sufficient size.
3341	* @param pcbAlreadyRead How much payload we've already read into the bounce
3342	* buffer. (We will NEVER re-read anything.)
3343	* @param pThread The calling PDM thread handle.
3344	* @param pThis The shared VGA/VMSVGA instance data.
3345	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3346	* statistics collection.
3347	* @param pDevIns The device instance.
3348	*/
3349	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3350	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3351	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3352	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3353	{
3354	Assert(pbBounceBuf);
3355	Assert(pcbAlreadyRead);
3356	Assert(offFifoMin < offFifoMax);
3357	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3358	Assert(offFifoMax <= pThis->svga.cbFIFO);
3359
3360	/*
3361	* Check if the requested payload size has already been satisfied .
3362	* .
3363	* When called to read more, the caller is responsible for making sure the .
3364	* new command size (cbRequsted) never is smaller than what has already .
3365	* been read.
3366	*/
3367	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3368	if (cbPayloadReq <= cbAlreadyRead)
3369	{
3370	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3371	return pbBounceBuf;
3372	}
3373
3374	/*
3375	* Commands bigger than the fifo buffer are invalid.
3376	*/
3377	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3378	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3379	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3380	NULL);
3381
3382	/*
3383	* Move offCurrentCmd past the command dword.
3384	*/
3385	offCurrentCmd += sizeof(uint32_t);
3386	if (offCurrentCmd >= offFifoMax)
3387	offCurrentCmd = offFifoMin;
3388
3389	/*
3390	* Do we have sufficient payload data available already?
3391	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3392	*/
3393	uint32_t cbAfter, cbBefore;
3394	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3395	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3396	if (offNextCmd >= offCurrentCmd)
3397	{
3398	if (RT_LIKELY(offNextCmd < offFifoMax))
3399	cbAfter = offNextCmd - offCurrentCmd;
3400	else
3401	{
3402	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3403	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3404	offNextCmd, offFifoMin, offFifoMax));
3405	cbAfter = offFifoMax - offCurrentCmd;
3406	}
3407	cbBefore = 0;
3408	}
3409	else
3410	{
3411	cbAfter = offFifoMax - offCurrentCmd;
3412	if (offNextCmd >= offFifoMin)
3413	cbBefore = offNextCmd - offFifoMin;
3414	else
3415	{
3416	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3417	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3418	offNextCmd, offFifoMin, offFifoMax));
3419	cbBefore = 0;
3420	}
3421	}
3422	if (cbAfter + cbBefore < cbPayloadReq)
3423	{
3424	/*
3425	* Insufficient, must wait for it to arrive.
3426	*/
3427	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3428	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3429	for (uint32_t i = 0;; i++)
3430	{
3431	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3432	{
3433	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3434	return (void *)(uintptr_t)1;
3435	}
3436	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3437	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3438
3439	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3440
3441	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3442	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3443	if (offNextCmd >= offCurrentCmd)
3444	{
3445	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3446	cbBefore = 0;
3447	}
3448	else
3449	{
3450	cbAfter = offFifoMax - offCurrentCmd;
3451	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3452	}
3453
3454	if (cbAfter + cbBefore >= cbPayloadReq)
3455	break;
3456	}
3457	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3458	}
3459
3460	/*
3461	* Copy out the memory and update what pcbAlreadyRead points to.
3462	*/
3463	if (cbAfter >= cbPayloadReq)
3464	memcpy(pbBounceBuf + cbAlreadyRead,
3465	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3466	cbPayloadReq - cbAlreadyRead);
3467	else
3468	{
3469	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3470	if (cbAlreadyRead < cbAfter)
3471	{
3472	memcpy(pbBounceBuf + cbAlreadyRead,
3473	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3474	cbAfter - cbAlreadyRead);
3475	cbAlreadyRead = cbAfter;
3476	}
3477	memcpy(pbBounceBuf + cbAlreadyRead,
3478	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3479	cbPayloadReq - cbAlreadyRead);
3480	}
3481	*pcbAlreadyRead = cbPayloadReq;
3482	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3483	return pbBounceBuf;
3484	}
3485
3486
3487	/**
3488	* Sends cursor position and visibility information from the FIFO to the front-end.
3489	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3490	*/
3491	static uint32_t
3492	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3493	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3494	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3495	{
3496	/*
3497	* Check if the cursor update counter has changed and try get a stable
3498	* set of values if it has. This is race-prone, especially consindering
3499	* the screen ID, but little we can do about that.
3500	*/
3501	uint32_t x, y, fVisible, idScreen;
3502	for (uint32_t i = 0; ; i++)
3503	{
3504	x = pFIFO[SVGA_FIFO_CURSOR_X];
3505	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3506	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3507	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3508	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3509	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3510	\|\| i > 3)
3511	break;
3512	if (i == 0)
3513	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3514	ASMNopPause();
3515	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3516	}
3517
3518	/*
3519	* Check if anything has changed, as calling into pDrv is not light-weight.
3520	*/
3521	if ( *pxLast == x
3522	&& *pyLast == y
3523	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3524	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3525	else
3526	{
3527	/*
3528	* Detected changes.
3529	*
3530	* We handle global, not per-screen visibility information by sending
3531	* pfnVBVAMousePointerShape without shape data.
3532	*/
3533	*pxLast = x;
3534	*pyLast = y;
3535	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3536	if (idScreen != SVGA_ID_INVALID)
3537	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3538	else if (*pfLastVisible != fVisible)
3539	{
3540	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3541	*pfLastVisible = fVisible;
3542	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3543	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3544	}
3545	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3546	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3547	}
3548
3549	/*
3550	* Update done. Signal this to the guest.
3551	*/
3552	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3553
3554	return uCursorUpdateCount;
3555	}
3556
3557
3558	/**
3559	* Checks if there is work to be done, either cursor updating or FIFO commands.
3560	*
3561	* @returns true if pending work, false if not.
3562	* @param pFIFO The FIFO to examine.
3563	* @param uLastCursorCount The last cursor update counter value.
3564	*/
3565	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3566	{
3567	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3568	return true;
3569
3570	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3571	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3572	return true;
3573
3574	return false;
3575	}
3576
3577
3578	/**
3579	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3580	*
3581	* @param pDevIns The device instance.
3582	* @param pThis The shared VGA/VMSVGA instance data.
3583	* @param pThisCC The VGA/VMSVGA state for ring-3.
3584	*/
3585	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3586	{
3587	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3588	to recheck it before doing the signalling. */
3589	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3590	AssertReturnVoid(pFIFO);
3591	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3592	&& pThis->svga.fFIFOThreadSleeping)
3593	{
3594	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3595	AssertRC(rc);
3596	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3597	}
3598	}
3599
3600
3601	/**
3602	* Called by the FIFO thread to process pending actions.
3603	*
3604	* @param pDevIns The device instance.
3605	* @param pThis The shared VGA/VMSVGA instance data.
3606	* @param pThisCC The VGA/VMSVGA state for ring-3.
3607	*/
3608	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3609	{
3610	RT_NOREF(pDevIns);
3611
3612	/* Currently just mode changes. */
3613	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3614	{
3615	vmsvgaR3ChangeMode(pThis, pThisCC);
3616	# ifdef VBOX_WITH_VMSVGA3D
3617	if (pThisCC->svga.p3dState != NULL)
3618	vmsvga3dChangeMode(pThisCC);
3619	# endif
3620	}
3621	}
3622
3623
3624	/*
3625	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3626	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3627	*/
3628	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3629	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3630	*
3631	* Will break out of the switch on failure.
3632	* Will restart and quit the loop if the thread was requested to stop.
3633	*
3634	* @param a_PtrVar Request variable pointer.
3635	* @param a_Type Request typedef (not pointer) for casting.
3636	* @param a_cbPayloadReq How much payload to fetch.
3637	* @remarks Accesses a bunch of variables in the current scope!
3638	*/
3639	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3640	if (1) { \
3641	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3642	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3643	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3644	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3645	} else do {} while (0)
3646	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3647	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3648	* buffer after figuring out the actual command size.
3649	*
3650	* Will break out of the switch on failure.
3651	*
3652	* @param a_PtrVar Request variable pointer.
3653	* @param a_Type Request typedef (not pointer) for casting.
3654	* @param a_cbPayloadReq How much payload to fetch.
3655	* @remarks Accesses a bunch of variables in the current scope!
3656	*/
3657	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3658	if (1) { \
3659	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3660	} else do {} while (0)
3661
3662	/**
3663	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3664	*/
3665	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3666	{
3667	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3668	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3669	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3670	int rc;
3671
3672	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
3673	if (pThis->svga.f3DEnabled)
3674	{
3675	/* The FIFO thread may use X API for accelerated screen output. */
3676	XInitThreads();
3677	}
3678	# endif
3679
3680	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3681	return VINF_SUCCESS;
3682
3683	/*
3684	* Special mode where we only execute an external command and the go back
3685	* to being suspended. Currently, all ext cmds ends up here, with the reset
3686	* one also being eligble for runtime execution further down as well.
3687	*/
3688	if (pThis->svga.fFifoExtCommandWakeup)
3689	{
3690	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3691	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3692	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3693	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3694	else
3695	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3696	return VINF_SUCCESS;
3697	}
3698
3699
3700	/*
3701	* Signal the semaphore to make sure we don't wait for 250ms after a
3702	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3703	*/
3704	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3705
3706	/*
3707	* Allocate a bounce buffer for command we get from the FIFO.
3708	* (All code must return via the end of the function to free this buffer.)
3709	*/
3710	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3711	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3712
3713	/*
3714	* Polling/sleep interval config.
3715	*
3716	* We wait for an a short interval if the guest has recently given us work
3717	* to do, but the interval increases the longer we're kept idle. Once we've
3718	* reached the refresh timer interval, we'll switch to extended waits,
3719	* depending on it or the guest to kick us into action when needed.
3720	*
3721	* Should the refresh time go fishing, we'll just continue increasing the
3722	* sleep length till we reaches the 250 ms max after about 16 seconds.
3723	*/
3724	RTMSINTERVAL const cMsMinSleep = 16;
3725	RTMSINTERVAL const cMsIncSleep = 2;
3726	RTMSINTERVAL const cMsMaxSleep = 250;
3727	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3728	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3729
3730	/*
3731	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3732	*
3733	* Initialize with values that will detect an update from the guest.
3734	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3735	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3736	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3737	*/
3738	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3739	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3740	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3741	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3742	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3743
3744	/*
3745	* The FIFO loop.
3746	*/
3747	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3748	bool fBadOrDisabledFifo = false;
3749	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3750	{
3751	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3752	/*
3753	* Should service the run loop every so often.
3754	*/
3755	if (pThis->svga.f3DEnabled)
3756	vmsvga3dCocoaServiceRunLoop();
3757	# endif
3758
3759	/* First check any pending actions. */
3760	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3761
3762	/*
3763	* Unless there's already work pending, go to sleep for a short while.
3764	* (See polling/sleep interval config above.)
3765	*/
3766	if ( fBadOrDisabledFifo
3767	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3768	{
3769	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3770	Assert(pThis->cMilliesRefreshInterval > 0);
3771	if (cMsSleep < pThis->cMilliesRefreshInterval)
3772	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3773	else
3774	{
3775	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3776	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3777	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3778	# endif
3779	if ( !fBadOrDisabledFifo
3780	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3781	rc = VINF_SUCCESS;
3782	else
3783	{
3784	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3785	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3786	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3787	}
3788	}
3789	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3790	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3791	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3792	{
3793	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3794	break;
3795	}
3796	}
3797	else
3798	rc = VINF_SUCCESS;
3799	fBadOrDisabledFifo = false;
3800	if (rc == VERR_TIMEOUT)
3801	{
3802	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3803	{
3804	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3805	continue;
3806	}
3807	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3808
3809	Log(("vmsvgaR3FifoLoop: timeout\n"));
3810	}
3811	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3812	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3813	cMsSleep = cMsMinSleep;
3814
3815	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3816	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3817	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3818
3819	/*
3820	* Handle external commands (currently only reset).
3821	*/
3822	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3823	{
3824	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3825	continue;
3826	}
3827
3828	/*
3829	* The device must be enabled and configured.
3830	*/
3831	if ( !pThis->svga.fEnabled
3832	\|\| !pThis->svga.fConfigured)
3833	{
3834	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3835	fBadOrDisabledFifo = true;
3836	cMsSleep = cMsMaxSleep; /* cheat */
3837	continue;
3838	}
3839
3840	/*
3841	* Get and check the min/max values. We ASSUME that they will remain
3842	* unchanged while we process requests. A further ASSUMPTION is that
3843	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3844	* we don't read it back while in the loop.
3845	*/
3846	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3847	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3848	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3849	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3850	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3851	\|\| offFifoMax <= offFifoMin
3852	\|\| offFifoMax > pThis->svga.cbFIFO
3853	\|\| (offFifoMax & 3) != 0
3854	\|\| (offFifoMin & 3) != 0
3855	\|\| offCurrentCmd < offFifoMin
3856	\|\| offCurrentCmd > offFifoMax))
3857	{
3858	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3859	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3860	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3861	fBadOrDisabledFifo = true;
3862	continue;
3863	}
3864	RT_UNTRUSTED_VALIDATED_FENCE();
3865	if (RT_UNLIKELY(offCurrentCmd & 3))
3866	{
3867	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3868	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3869	offCurrentCmd &= ~UINT32_C(3);
3870	}
3871
3872	/*
3873	* Update the cursor position before we start on the FIFO commands.
3874	*/
3875	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3876	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3877	{
3878	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3879	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3880	{ /* halfways likely */ }
3881	else
3882	{
3883	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3884	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3885	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3886	}
3887	}
3888
3889	/*
3890	* Mark the FIFO as busy.
3891	*/
3892	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
3893	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3894	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3895
3896	/*
3897	* Execute all queued FIFO commands.
3898	* Quit if pending external command or changes in the thread state.
3899	*/
3900	bool fDone = false;
3901	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3902	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3903	{
3904	uint32_t cbPayload = 0;
3905	uint32_t u32IrqStatus = 0;
3906
3907	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3908
3909	/* First check any pending actions. */
3910	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3911
3912	/* Check for pending external commands (reset). */
3913	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3914	break;
3915
3916	/*
3917	* Process the command.
3918	*/
3919	SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
3920	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3921	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3922	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3923	switch (enmCmdId)
3924	{
3925	case SVGA_CMD_INVALID_CMD:
3926	/* Nothing to do. */
3927	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3928	break;
3929
3930	case SVGA_CMD_FENCE:
3931	{
3932	SVGAFifoCmdFence *pCmdFence;
3933	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3934	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3935	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3936	{
3937	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3938	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3939
3940	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3941	{
3942	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3943	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3944	}
3945	else
3946	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3947	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3948	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3949	{
3950	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3951	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3952	}
3953	}
3954	else
3955	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3956	break;
3957	}
3958	case SVGA_CMD_UPDATE:
3959	case SVGA_CMD_UPDATE_VERBOSE:
3960	{
3961	SVGAFifoCmdUpdate *pUpdate;
3962	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3963	if (enmCmdId == SVGA_CMD_UPDATE)
3964	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3965	else
3966	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3967	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3968	/** @todo Multiple screens? */
3969	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3970	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3971	break;
3972	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3973	break;
3974	}
3975
3976	case SVGA_CMD_DEFINE_CURSOR:
3977	{
3978	/* Followed by bitmap data. */
3979	SVGAFifoCmdDefineCursor *pCursor;
3980	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3981	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3982
3983	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3984	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3985	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3986	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3987	AssertBreak(pCursor->andMaskDepth <= 32);
3988	AssertBreak(pCursor->xorMaskDepth <= 32);
3989	RT_UNTRUSTED_VALIDATED_FENCE();
3990
3991	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3992	uint32_t cbAndMask = cbAndLine * pCursor->height;
3993	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3994	uint32_t cbXorMask = cbXorLine * pCursor->height;
3995	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3996
3997	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3998	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
3999	break;
4000	}
4001
4002	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4003	{
4004	/* Followed by bitmap data. */
4005	uint32_t cbCursorShape, cbAndMask;
4006	uint8_t *pCursorCopy;
4007	uint32_t cbCmd;
4008
4009	SVGAFifoCmdDefineAlphaCursor *pCursor;
4010	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
4011	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
4012
4013	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
4014
4015	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
4016	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
4017	RT_UNTRUSTED_VALIDATED_FENCE();
4018
4019	/* Refetch the bitmap data as well. */
4020	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4021	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4022	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
4023
4024	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
4025	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
4026	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
4027	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
4028
4029	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
4030	AssertPtrBreak(pCursorCopy);
4031
4032	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
4033	memset(pCursorCopy, 0xff, cbAndMask);
4034	/* Colour data */
4035	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
4036
4037	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
4038	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
4039	break;
4040	}
4041
4042	case SVGA_CMD_MOVE_CURSOR:
4043	{
4044	/* Deprecated; there should be no driver which requires this command. However, if
4045	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4046	* alignment.
4047	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4048	*/
4049	SVGAFifoCmdMoveCursor *pMoveCursor;
4050	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
4051	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
4052
4053	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
4054	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4055	break;
4056	}
4057
4058	case SVGA_CMD_DISPLAY_CURSOR:
4059	{
4060	/* Deprecated; there should be no driver which requires this command. However, if
4061	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4062	* alignment.
4063	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4064	*/
4065	SVGAFifoCmdDisplayCursor *pDisplayCursor;
4066	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
4067	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
4068
4069	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
4070	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4071	break;
4072	}
4073
4074	case SVGA_CMD_RECT_FILL:
4075	{
4076	SVGAFifoCmdRectFill *pRectFill;
4077	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectFill, SVGAFifoCmdRectFill, sizeof(*pRectFill));
4078	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectFill);
4079
4080	Log(("vmsvgaR3FifoLoop: RECT FILL %08X @ %d,%d (%dx%d)\n", pRectFill->pixel, pRectFill->destX, pRectFill->destY, pRectFill->width, pRectFill->height));
4081	LogRelMax(4, ("Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4082	break;
4083	}
4084
4085	case SVGA_CMD_RECT_COPY:
4086	{
4087	SVGAFifoCmdRectCopy *pRectCopy;
4088	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectCopy, SVGAFifoCmdRectCopy, sizeof(*pRectCopy));
4089	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectCopy);
4090
4091	Log(("vmsvgaR3FifoLoop: RECT COPY %d,%d -> %d,%d (%dx%d)\n", pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height));
4092	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4093	AssertPtrBreak(pScreen);
4094
4095	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4096	AssertBreak(pRectCopy->srcX < pThis->svga.u32MaxWidth);
4097	AssertBreak(pRectCopy->destX < pThis->svga.u32MaxWidth);
4098	AssertBreak(pRectCopy->width < pThis->svga.u32MaxWidth);
4099	AssertBreak(pRectCopy->srcY < pThis->svga.u32MaxHeight);
4100	AssertBreak(pRectCopy->destY < pThis->svga.u32MaxHeight);
4101	AssertBreak(pRectCopy->height < pThis->svga.u32MaxHeight);
4102
4103	vmsvgaR3RectCopy(pThisCC, pScreen, pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY,
4104	pRectCopy->width, pRectCopy->height, pThis->vram_size);
4105	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height);
4106	break;
4107	}
4108
4109	case SVGA_CMD_RECT_ROP_COPY:
4110	{
4111	SVGAFifoCmdRectRopCopy *pRRCopy;
4112	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRRCopy, SVGAFifoCmdRectRopCopy, sizeof(*pRRCopy));
4113	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectRopCopy);
4114
4115	Log(("vmsvgaR3FifoLoop: RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4116	if (pRRCopy->rop != SVGA_ROP_COPY)
4117	{
4118	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4119	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4120	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4121	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4122	*/
4123	LogRelMax(4, ("RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4124	break;
4125	}
4126
4127	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4128	AssertPtrBreak(pScreen);
4129
4130	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4131	AssertBreak(pRRCopy->srcX < pThis->svga.u32MaxWidth);
4132	AssertBreak(pRRCopy->destX < pThis->svga.u32MaxWidth);
4133	AssertBreak(pRRCopy->width < pThis->svga.u32MaxWidth);
4134	AssertBreak(pRRCopy->srcY < pThis->svga.u32MaxHeight);
4135	AssertBreak(pRRCopy->destY < pThis->svga.u32MaxHeight);
4136	AssertBreak(pRRCopy->height < pThis->svga.u32MaxHeight);
4137
4138	vmsvgaR3RectCopy(pThisCC, pScreen, pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY,
4139	pRRCopy->width, pRRCopy->height, pThis->vram_size);
4140	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height);
4141	break;
4142	}
4143
4144	case SVGA_CMD_ESCAPE:
4145	{
4146	/* Followed by nsize bytes of data. */
4147	SVGAFifoCmdEscape *pEscape;
4148	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
4149	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
4150
4151	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
4152	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
4153	RT_UNTRUSTED_VALIDATED_FENCE();
4154	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
4155	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
4156
4157	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
4158	{
4159	AssertBreak(pEscape->size >= sizeof(uint32_t));
4160	RT_UNTRUSTED_VALIDATED_FENCE();
4161	uint32_t cmd = (uint32_t )(pEscape + 1);
4162	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
4163
4164	switch (cmd)
4165	{
4166	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4167	{
4168	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
4169	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
4170	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4171
4172	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
4173	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4174	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4175
4176	RT_NOREF_PV(pVideoCmd);
4177	break;
4178
4179	}
4180
4181	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4182	{
4183	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4184	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4185	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4186	RT_NOREF_PV(pVideoCmd);
4187	break;
4188	}
4189
4190	default:
4191	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4192	break;
4193	}
4194	}
4195	else
4196	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4197
4198	break;
4199	}
4200	# ifdef VBOX_WITH_VMSVGA3D
4201	case SVGA_CMD_DEFINE_GMR2:
4202	{
4203	SVGAFifoCmdDefineGMR2 *pCmd;
4204	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4205	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4206	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4207
4208	/* Validate current GMR id. */
4209	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4210	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4211	RT_UNTRUSTED_VALIDATED_FENCE();
4212
4213	if (!pCmd->numPages)
4214	{
4215	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4216	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4217	}
4218	else
4219	{
4220	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4221	if (pGMR->cMaxPages)
4222	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4223
4224	/* Not sure if we should always free the descriptor, but for simplicity
4225	we do so if the new size is smaller than the current. */
4226	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4227	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4228	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4229
4230	pGMR->cMaxPages = pCmd->numPages;
4231	/* The rest is done by the REMAP_GMR2 command. */
4232	}
4233	break;
4234	}
4235
4236	case SVGA_CMD_REMAP_GMR2:
4237	{
4238	/* Followed by page descriptors or guest ptr. */
4239	SVGAFifoCmdRemapGMR2 *pCmd;
4240	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4241	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4242
4243	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4244	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4245	RT_UNTRUSTED_VALIDATED_FENCE();
4246
4247	/* Calculate the size of what comes after next and fetch it. */
4248	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4249	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4250	cbCmd += sizeof(SVGAGuestPtr);
4251	else
4252	{
4253	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4254	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4255	{
4256	cbCmd += cbPageDesc;
4257	pCmd->numPages = 1;
4258	}
4259	else
4260	{
4261	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4262	cbCmd += cbPageDesc * pCmd->numPages;
4263	}
4264	}
4265	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4266
4267	/* Validate current GMR id and size. */
4268	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4269	RT_UNTRUSTED_VALIDATED_FENCE();
4270	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4271	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4272	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4273	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4274
4275	if (pCmd->numPages == 0)
4276	break;
4277
4278	/** @todo Move to a separate function vmsvgaGMRRemap() */
4279
4280	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4281	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4282
4283	/*
4284	* We flatten the existing descriptors into a page array, overwrite the
4285	* pages specified in this command and then recompress the descriptor.
4286	*/
4287	/** @todo Optimize the GMR remap algorithm! */
4288
4289	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4290	uint64_t *paNewPage64 = NULL;
4291	if (pGMR->paDesc)
4292	{
4293	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4294
4295	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4296	AssertPtrBreak(paNewPage64);
4297
4298	uint32_t idxPage = 0;
4299	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4300	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4301	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4302	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4303	RT_UNTRUSTED_VALIDATED_FENCE();
4304	}
4305
4306	/* Free the old GMR if present. */
4307	if (pGMR->paDesc)
4308	RTMemFree(pGMR->paDesc);
4309
4310	/* Allocate the maximum amount possible (everything non-continuous) */
4311	PVMSVGAGMRDESCRIPTOR paDescs;
4312	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4313	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4314
4315	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4316	{
4317	/** @todo */
4318	AssertFailed();
4319	pGMR->numDescriptors = 0;
4320	}
4321	else
4322	{
4323	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4324	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4325	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4326
4327	if (paNewPage64)
4328	{
4329	/* Overwrite the old page array with the new page values. */
4330	if (fGCPhys64)
4331	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4332	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4333	else
4334	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4335	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4336
4337	/* Use the updated page array instead of the command data. */
4338	fGCPhys64 = true;
4339	paPages64 = paNewPage64;
4340	pCmd->numPages = cNewTotalPages;
4341	}
4342
4343	/* The first page. */
4344	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4345	* applied to paNewPage64. */
4346	RTGCPHYS GCPhys;
4347	if (fGCPhys64)
4348	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4349	else
4350	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4351	paDescs[0].GCPhys = GCPhys;
4352	paDescs[0].numPages = 1;
4353
4354	/* Subsequent pages. */
4355	uint32_t iDescriptor = 0;
4356	for (uint32_t i = 1; i < pCmd->numPages; i++)
4357	{
4358	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4359	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4360	else
4361	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4362
4363	/* Continuous physical memory? */
4364	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4365	{
4366	Assert(paDescs[iDescriptor].numPages);
4367	paDescs[iDescriptor].numPages++;
4368	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4369	}
4370	else
4371	{
4372	iDescriptor++;
4373	paDescs[iDescriptor].GCPhys = GCPhys;
4374	paDescs[iDescriptor].numPages = 1;
4375	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4376	}
4377	}
4378
4379	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4380	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4381	pGMR->numDescriptors = iDescriptor + 1;
4382	}
4383
4384	if (paNewPage64)
4385	RTMemFree(paNewPage64);
4386
4387	# ifdef DEBUG_GMR_ACCESS
4388	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4389	# endif
4390	break;
4391	}
4392	# endif // VBOX_WITH_VMSVGA3D
4393	case SVGA_CMD_DEFINE_SCREEN:
4394	{
4395	/* The size of this command is specified by the guest and depends on capabilities. */
4396	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4397
4398	SVGAFifoCmdDefineScreen *pCmd;
4399	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4400	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4401	RT_UNTRUSTED_VALIDATED_FENCE();
4402
4403	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4404	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4405	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4406
4407	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4408	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4409	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4410
4411	uint32_t const idScreen = pCmd->screen.id;
4412	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4413
4414	uint32_t const uWidth = pCmd->screen.size.width;
4415	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4416
4417	uint32_t const uHeight = pCmd->screen.size.height;
4418	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4419
4420	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4421	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4422	AssertBreak(cbWidth <= cbPitch);
4423
4424	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4425	AssertBreak(uScreenOffset < pThis->vram_size);
4426
4427	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4428	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4429	AssertBreak( (uHeight == 0 && cbPitch == 0)
4430	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4431	RT_UNTRUSTED_VALIDATED_FENCE();
4432
4433	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4434
4435	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4436
4437	pScreen->fDefined = true;
4438	pScreen->fModified = true;
4439	pScreen->fuScreen = pCmd->screen.flags;
4440	pScreen->idScreen = idScreen;
4441	if (!fBlank)
4442	{
4443	AssertBreak(uWidth > 0 && uHeight > 0);
4444
4445	pScreen->xOrigin = pCmd->screen.root.x;
4446	pScreen->yOrigin = pCmd->screen.root.y;
4447	pScreen->cWidth = uWidth;
4448	pScreen->cHeight = uHeight;
4449	pScreen->offVRAM = uScreenOffset;
4450	pScreen->cbPitch = cbPitch;
4451	pScreen->cBpp = 32;
4452	}
4453	else
4454	{
4455	/* Keep old values. */
4456	}
4457
4458	pThis->svga.fGFBRegisters = false;
4459	vmsvgaR3ChangeMode(pThis, pThisCC);
4460
4461	# ifdef VBOX_WITH_VMSVGA3D
4462	if (RT_LIKELY(pThis->svga.f3DEnabled))
4463	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
4464	# endif
4465	break;
4466	}
4467
4468	case SVGA_CMD_DESTROY_SCREEN:
4469	{
4470	SVGAFifoCmdDestroyScreen *pCmd;
4471	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4472	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4473
4474	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4475
4476	uint32_t const idScreen = pCmd->screenId;
4477	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4478	RT_UNTRUSTED_VALIDATED_FENCE();
4479
4480	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4481	pScreen->fModified = true;
4482	pScreen->fDefined = false;
4483	pScreen->idScreen = idScreen;
4484
4485	# ifdef VBOX_WITH_VMSVGA3D
4486	if (RT_LIKELY(pThis->svga.f3DEnabled))
4487	vmsvga3dDestroyScreen(pThisCC, pScreen);
4488	# endif
4489	vmsvgaR3ChangeMode(pThis, pThisCC);
4490	break;
4491	}
4492
4493	case SVGA_CMD_DEFINE_GMRFB:
4494	{
4495	SVGAFifoCmdDefineGMRFB *pCmd;
4496	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4497	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4498
4499	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
4500	pSVGAState->GMRFB.ptr = pCmd->ptr;
4501	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4502	pSVGAState->GMRFB.format = pCmd->format;
4503	break;
4504	}
4505
4506	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4507	{
4508	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4509	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4510	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4511
4512	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4513	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4514
4515	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4516	RT_UNTRUSTED_VALIDATED_FENCE();
4517
4518	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4519	AssertPtrBreak(pScreen);
4520
4521	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4522	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4523
4524	/* Clip destRect to the screen dimensions. */
4525	SVGASignedRect screenRect;
4526	screenRect.left = 0;
4527	screenRect.top = 0;
4528	screenRect.right = pScreen->cWidth;
4529	screenRect.bottom = pScreen->cHeight;
4530	SVGASignedRect clipRect = pCmd->destRect;
4531	vmsvgaR3ClipRect(&screenRect, &clipRect);
4532	RT_UNTRUSTED_VALIDATED_FENCE();
4533
4534	uint32_t const width = clipRect.right - clipRect.left;
4535	uint32_t const height = clipRect.bottom - clipRect.top;
4536
4537	if ( width == 0
4538	\|\| height == 0)
4539	break; /* Nothing to do. */
4540
4541	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4542	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4543
4544	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4545	* Prepare parameters for vmsvgaR3GmrTransfer.
4546	*/
4547	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4548
4549	/* Destination: host buffer which describes the screen 0 VRAM.
4550	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4551	*/
4552	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4553	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4554	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4555	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4556	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4557	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4558	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4559	+ cbScanline * clipRect.top;
4560	int32_t const cbHstPitch = cbScanline;
4561
4562	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4563	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4564	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4565	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4566	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4567
4568	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4569	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4570	gstPtr, offGst, cbGstPitch,
4571	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4572	AssertRC(rc);
4573	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4574	break;
4575	}
4576
4577	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4578	{
4579	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4580	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4581	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4582
4583	/* Note! This can fetch 3d render results as well!! */
4584	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4585	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4586
4587	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4588	RT_UNTRUSTED_VALIDATED_FENCE();
4589
4590	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4591	AssertPtrBreak(pScreen);
4592
4593	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp? */
4594	AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pScreen->cBpp);
4595
4596	/* Clip destRect to the screen dimensions. */
4597	SVGASignedRect screenRect;
4598	screenRect.left = 0;
4599	screenRect.top = 0;
4600	screenRect.right = pScreen->cWidth;
4601	screenRect.bottom = pScreen->cHeight;
4602	SVGASignedRect clipRect = pCmd->srcRect;
4603	vmsvgaR3ClipRect(&screenRect, &clipRect);
4604	RT_UNTRUSTED_VALIDATED_FENCE();
4605
4606	uint32_t const width = clipRect.right - clipRect.left;
4607	uint32_t const height = clipRect.bottom - clipRect.top;
4608
4609	if ( width == 0
4610	\|\| height == 0)
4611	break; /* Nothing to do. */
4612
4613	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4614	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4615
4616	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4617	* Prepare parameters for vmsvgaR3GmrTransfer.
4618	*/
4619	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4620
4621	/* Source: host buffer which describes the screen 0 VRAM.
4622	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4623	*/
4624	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4625	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4626	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4627	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4628	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4629	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4630	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4631	+ cbScanline * clipRect.top;
4632	int32_t const cbHstPitch = cbScanline;
4633
4634	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4635	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4636	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.s.bitsPerPixel, 8)) / 8
4637	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4638	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4639
4640	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4641	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4642	gstPtr, offGst, cbGstPitch,
4643	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4644	AssertRC(rc);
4645	break;
4646	}
4647
4648	case SVGA_CMD_ANNOTATION_FILL:
4649	{
4650	SVGAFifoCmdAnnotationFill *pCmd;
4651	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4652	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4653
4654	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
4655	pSVGAState->colorAnnotation = pCmd->color;
4656	break;
4657	}
4658
4659	case SVGA_CMD_ANNOTATION_COPY:
4660	{
4661	SVGAFifoCmdAnnotationCopy *pCmd;
4662	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4663	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4664
4665	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4666	AssertFailed();
4667	break;
4668	}
4669
4670	default:
4671	# ifdef VBOX_WITH_VMSVGA3D
4672	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4673	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4674	{
4675	RT_UNTRUSTED_VALIDATED_FENCE();
4676
4677	/* All 3d commands start with a common header, which defines the size of the command. */
4678	SVGA3dCmdHeader *pHdr;
4679	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
4680	AssertBreak(pHdr->size < pThis->svga.cbFIFO);
4681	uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
4682	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
4683
4684	if (RT_LIKELY(pThis->svga.f3DEnabled))
4685	{ /* likely */ }
4686	else
4687	{
4688	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4689	break;
4690	}
4691
4692	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4693	* Check that the 3D command has at least a_cbMin of payload bytes after the
4694	* header. Will break out of the switch if it doesn't.
4695	*/
4696	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4697	if (1) { \
4698	AssertMsgBreak(pHdr->size >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin))); \
4699	RT_UNTRUSTED_VALIDATED_FENCE(); \
4700	} else do {} while (0)
4701	switch ((int)enmCmdId)
4702	{
4703	case SVGA_3D_CMD_SURFACE_DEFINE:
4704	{
4705	uint32_t cMipLevels;
4706	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )(pHdr + 1);
4707	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4708	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4709
4710	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4711	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4712	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4713	# ifdef DEBUG_GMR_ACCESS
4714	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4715	# endif
4716	break;
4717	}
4718
4719	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4720	{
4721	uint32_t cMipLevels;
4722	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )(pHdr + 1);
4723	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4724	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4725
4726	cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4727	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4728	pCmd->multisampleCount, pCmd->autogenFilter,
4729	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4730	break;
4731	}
4732
4733	case SVGA_3D_CMD_SURFACE_DESTROY:
4734	{
4735	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )(pHdr + 1);
4736	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4737	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4738	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4739	break;
4740	}
4741
4742	case SVGA_3D_CMD_SURFACE_COPY:
4743	{
4744	uint32_t cCopyBoxes;
4745	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )(pHdr + 1);
4746	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4747	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4748
4749	cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4750	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4751	break;
4752	}
4753
4754	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4755	{
4756	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )(pHdr + 1);
4757	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4758	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4759
4760	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4761	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4762	break;
4763	}
4764
4765	case SVGA_3D_CMD_SURFACE_DMA:
4766	{
4767	uint32_t cCopyBoxes;
4768	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )(pHdr + 1);
4769	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4770	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4771
4772	uint64_t u64NanoTS = 0;
4773	if (LogRelIs3Enabled())
4774	u64NanoTS = RTTimeNanoTS();
4775	cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4776	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4777	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4778	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4779	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4780	if (LogRelIs3Enabled())
4781	{
4782	if (cCopyBoxes)
4783	{
4784	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4785	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4786	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4787	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4788	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4789	}
4790	}
4791	break;
4792	}
4793
4794	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4795	{
4796	uint32_t cRects;
4797	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )(pHdr + 1);
4798	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4799	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4800
4801	static uint64_t u64FrameStartNanoTS = 0;
4802	static uint64_t u64ElapsedPerSecNano = 0;
4803	static int cFrames = 0;
4804	uint64_t u64NanoTS = 0;
4805	if (LogRelIs3Enabled())
4806	u64NanoTS = RTTimeNanoTS();
4807	cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4808	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4809	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4810	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4811	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4812	if (LogRelIs3Enabled())
4813	{
4814	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4815	u64ElapsedPerSecNano += u64ElapsedNano;
4816
4817	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4818	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4819	(u64ElapsedNano) / 1000ULL, cRects,
4820	pFirstRect->left, pFirstRect->top,
4821	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4822
4823	++cFrames;
4824	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4825	{
4826	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4827	cFrames, u64ElapsedPerSecNano / 1000ULL));
4828	u64FrameStartNanoTS = u64NanoTS;
4829	cFrames = 0;
4830	u64ElapsedPerSecNano = 0;
4831	}
4832	}
4833	break;
4834	}
4835
4836	case SVGA_3D_CMD_CONTEXT_DEFINE:
4837	{
4838	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )(pHdr + 1);
4839	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4840	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4841
4842	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4843	break;
4844	}
4845
4846	case SVGA_3D_CMD_CONTEXT_DESTROY:
4847	{
4848	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )(pHdr + 1);
4849	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4850	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4851
4852	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4853	break;
4854	}
4855
4856	case SVGA_3D_CMD_SETTRANSFORM:
4857	{
4858	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )(pHdr + 1);
4859	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4860	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4861
4862	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4863	break;
4864	}
4865
4866	case SVGA_3D_CMD_SETZRANGE:
4867	{
4868	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )(pHdr + 1);
4869	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4870	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4871
4872	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4873	break;
4874	}
4875
4876	case SVGA_3D_CMD_SETRENDERSTATE:
4877	{
4878	uint32_t cRenderStates;
4879	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )(pHdr + 1);
4880	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4881	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4882
4883	cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4884	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4885	break;
4886	}
4887
4888	case SVGA_3D_CMD_SETRENDERTARGET:
4889	{
4890	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )(pHdr + 1);
4891	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4892	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4893
4894	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4895	break;
4896	}
4897
4898	case SVGA_3D_CMD_SETTEXTURESTATE:
4899	{
4900	uint32_t cTextureStates;
4901	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )(pHdr + 1);
4902	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4903	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4904
4905	cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4906	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4907	break;
4908	}
4909
4910	case SVGA_3D_CMD_SETMATERIAL:
4911	{
4912	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )(pHdr + 1);
4913	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4914	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4915
4916	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4917	break;
4918	}
4919
4920	case SVGA_3D_CMD_SETLIGHTDATA:
4921	{
4922	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )(pHdr + 1);
4923	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4924	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4925
4926	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4927	break;
4928	}
4929
4930	case SVGA_3D_CMD_SETLIGHTENABLED:
4931	{
4932	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )(pHdr + 1);
4933	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4934	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4935
4936	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4937	break;
4938	}
4939
4940	case SVGA_3D_CMD_SETVIEWPORT:
4941	{
4942	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )(pHdr + 1);
4943	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4944	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4945
4946	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4947	break;
4948	}
4949
4950	case SVGA_3D_CMD_SETCLIPPLANE:
4951	{
4952	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )(pHdr + 1);
4953	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4954	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4955
4956	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4957	break;
4958	}
4959
4960	case SVGA_3D_CMD_CLEAR:
4961	{
4962	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )(pHdr + 1);
4963	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4964	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4965
4966	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4967	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4968	break;
4969	}
4970
4971	case SVGA_3D_CMD_PRESENT:
4972	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4973	{
4974	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )(pHdr + 1);
4975	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4976	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4977	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4978	else
4979	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4980
4981	uint32_t cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4982
4983	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4984	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4985	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4986	break;
4987	}
4988
4989	case SVGA_3D_CMD_SHADER_DEFINE:
4990	{
4991	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )(pHdr + 1);
4992	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4993	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4994
4995	uint32_t cbData = (pHdr->size - sizeof(*pCmd));
4996	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
4997	break;
4998	}
4999
5000	case SVGA_3D_CMD_SHADER_DESTROY:
5001	{
5002	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )(pHdr + 1);
5003	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5004	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
5005
5006	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
5007	break;
5008	}
5009
5010	case SVGA_3D_CMD_SET_SHADER:
5011	{
5012	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )(pHdr + 1);
5013	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5014	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
5015
5016	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
5017	break;
5018	}
5019
5020	case SVGA_3D_CMD_SET_SHADER_CONST:
5021	{
5022	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )(pHdr + 1);
5023	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5024	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
5025
5026	uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
5027	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
5028	break;
5029	}
5030
5031	case SVGA_3D_CMD_DRAW_PRIMITIVES:
5032	{
5033	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )(pHdr + 1);
5034	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5035	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
5036
5037	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
5038	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
5039	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
5040	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
5041	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= pHdr->size - sizeof(*pCmd));
5042
5043	uint32_t cVertexDivisor = (pHdr->size - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
5044	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
5045
5046	RT_UNTRUSTED_VALIDATED_FENCE();
5047
5048	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
5049	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
5050	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
5051
5052	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5053	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
5054	pNumRange, cVertexDivisor, pVertexDivisor);
5055	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5056	break;
5057	}
5058
5059	case SVGA_3D_CMD_SETSCISSORRECT:
5060	{
5061	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )(pHdr + 1);
5062	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5063	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
5064
5065	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
5066	break;
5067	}
5068
5069	case SVGA_3D_CMD_BEGIN_QUERY:
5070	{
5071	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )(pHdr + 1);
5072	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5073	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
5074
5075	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5076	break;
5077	}
5078
5079	case SVGA_3D_CMD_END_QUERY:
5080	{
5081	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )(pHdr + 1);
5082	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5083	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
5084
5085	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5086	break;
5087	}
5088
5089	case SVGA_3D_CMD_WAIT_FOR_QUERY:
5090	{
5091	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )(pHdr + 1);
5092	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5093	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
5094
5095	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5096	break;
5097	}
5098
5099	case SVGA_3D_CMD_GENERATE_MIPMAPS:
5100	{
5101	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )(pHdr + 1);
5102	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5103	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
5104
5105	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5106	break;
5107	}
5108
5109	case SVGA_3D_CMD_ACTIVATE_SURFACE:
5110	/* context id + surface id? */
5111	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
5112	break;
5113	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5114	/* context id + surface id? */
5115	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
5116	break;
5117
5118	default:
5119	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5120	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5121	break;
5122	}
5123	}
5124	else
5125	# endif // VBOX_WITH_VMSVGA3D
5126	{
5127	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5128	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5129	}
5130	}
5131
5132	/* Go to the next slot */
5133	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5134	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5135	if (offCurrentCmd >= offFifoMax)
5136	{
5137	offCurrentCmd -= offFifoMax - offFifoMin;
5138	Assert(offCurrentCmd >= offFifoMin);
5139	Assert(offCurrentCmd < offFifoMax);
5140	}
5141	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5142	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5143
5144	/*
5145	* Raise IRQ if required. Must enter the critical section here
5146	* before making final decisions here, otherwise cubebench and
5147	* others may end up waiting forever.
5148	*/
5149	if ( u32IrqStatus
5150	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5151	{
5152	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5153	AssertRC(rc2);
5154
5155	/* FIFO progress might trigger an interrupt. */
5156	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5157	{
5158	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5159	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5160	}
5161
5162	/* Unmasked IRQ pending? */
5163	if (pThis->svga.u32IrqMask & u32IrqStatus)
5164	{
5165	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5166	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5167	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5168	}
5169
5170	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5171	}
5172	}
5173
5174	/* If really done, clear the busy flag. */
5175	if (fDone)
5176	{
5177	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5178	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5179	}
5180	}
5181
5182	/*
5183	* Free the bounce buffer. (There are no returns above!)
5184	*/
5185	RTMemFree(pbBounceBuf);
5186
5187	return VINF_SUCCESS;
5188	}
5189
5190	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5191	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5192	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5193
5194	#ifdef VBOX_WITH_VMSVGA3D
5195	/**
5196	* Free the specified GMR
5197	*
5198	* @param pThisCC The VGA/VMSVGA state for ring-3.
5199	* @param idGMR GMR id
5200	*/
5201	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5202	{
5203	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5204
5205	/* Free the old descriptor if present. */
5206	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5207	if ( pGMR->numDescriptors
5208	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5209	{
5210	# ifdef DEBUG_GMR_ACCESS
5211	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5212	# endif
5213
5214	Assert(pGMR->paDesc);
5215	RTMemFree(pGMR->paDesc);
5216	pGMR->paDesc = NULL;
5217	pGMR->numDescriptors = 0;
5218	pGMR->cbTotal = 0;
5219	pGMR->cMaxPages = 0;
5220	}
5221	Assert(!pGMR->cMaxPages);
5222	Assert(!pGMR->cbTotal);
5223	}
5224	#endif /* VBOX_WITH_VMSVGA3D */
5225
5226	/**
5227	* Copy between a GMR and a host memory buffer.
5228	*
5229	* @returns VBox status code.
5230	* @param pThis The shared VGA/VMSVGA instance data.
5231	* @param pThisCC The VGA/VMSVGA state for ring-3.
5232	* @param enmTransferType Transfer type (read/write)
5233	* @param pbHstBuf Host buffer pointer (valid)
5234	* @param cbHstBuf Size of host buffer (valid)
5235	* @param offHst Host buffer offset of the first scanline
5236	* @param cbHstPitch Destination buffer pitch
5237	* @param gstPtr GMR description
5238	* @param offGst Guest buffer offset of the first scanline
5239	* @param cbGstPitch Guest buffer pitch
5240	* @param cbWidth Width in bytes to copy
5241	* @param cHeight Number of scanllines to copy
5242	*/
5243	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5244	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5245	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5246	uint32_t cbWidth, uint32_t cHeight)
5247	{
5248	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5249	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5250	int rc;
5251
5252	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5253	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5254	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5255	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5256	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5257
5258	PGMR pGMR;
5259	uint32_t cbGmr; /* The GMR size in bytes. */
5260	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5261	{
5262	pGMR = NULL;
5263	cbGmr = pThis->vram_size;
5264	}
5265	else
5266	{
5267	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5268	RT_UNTRUSTED_VALIDATED_FENCE();
5269	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5270	cbGmr = pGMR->cbTotal;
5271	}
5272
5273	/*
5274	* GMR
5275	*/
5276	/* Calculate GMR offset of the data to be copied. */
5277	AssertMsgReturn(gstPtr.offset < cbGmr,
5278	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5279	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5280	VERR_INVALID_PARAMETER);
5281	RT_UNTRUSTED_VALIDATED_FENCE();
5282	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5283	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5284	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5285	VERR_INVALID_PARAMETER);
5286	RT_UNTRUSTED_VALIDATED_FENCE();
5287	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5288
5289	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5290	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5291	AssertMsgReturn(cbGmrScanline != 0,
5292	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5293	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5294	VERR_INVALID_PARAMETER);
5295	RT_UNTRUSTED_VALIDATED_FENCE();
5296	AssertMsgReturn(cbWidth <= cbGmrScanline,
5297	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5298	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5299	VERR_INVALID_PARAMETER);
5300	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5301	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5302	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5303	VERR_INVALID_PARAMETER);
5304	RT_UNTRUSTED_VALIDATED_FENCE();
5305
5306	/* How many bytes are available for the data in the GMR. */
5307	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5308
5309	/* How many scanlines would fit into the available data. */
5310	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5311	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5312	if (cbWidth <= cbGmrLastScanline)
5313	++cGmrScanlines;
5314
5315	if (cHeight > cGmrScanlines)
5316	cHeight = cGmrScanlines;
5317
5318	AssertMsgReturn(cHeight > 0,
5319	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5320	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5321	VERR_INVALID_PARAMETER);
5322	RT_UNTRUSTED_VALIDATED_FENCE();
5323
5324	/*
5325	* Host buffer.
5326	*/
5327	AssertMsgReturn(offHst < cbHstBuf,
5328	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5329	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5330	VERR_INVALID_PARAMETER);
5331
5332	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5333	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5334	AssertMsgReturn(cbHstScanline != 0,
5335	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5336	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5337	VERR_INVALID_PARAMETER);
5338	AssertMsgReturn(cbWidth <= cbHstScanline,
5339	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5340	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5341	VERR_INVALID_PARAMETER);
5342	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5343	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5344	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5345	VERR_INVALID_PARAMETER);
5346
5347	/* How many bytes are available for the data in the buffer. */
5348	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5349
5350	/* How many scanlines would fit into the available data. */
5351	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5352	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5353	if (cbWidth <= cbHstLastScanline)
5354	++cHstScanlines;
5355
5356	if (cHeight > cHstScanlines)
5357	cHeight = cHstScanlines;
5358
5359	AssertMsgReturn(cHeight > 0,
5360	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5361	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5362	VERR_INVALID_PARAMETER);
5363
5364	uint8_t *pbHst = pbHstBuf + offHst;
5365
5366	/* Shortcut for the framebuffer. */
5367	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5368	{
5369	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5370
5371	uint8_t const *pbSrc;
5372	int32_t cbSrcPitch;
5373	uint8_t *pbDst;
5374	int32_t cbDstPitch;
5375
5376	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5377	{
5378	pbSrc = pbHst;
5379	cbSrcPitch = cbHstPitch;
5380	pbDst = pbGst;
5381	cbDstPitch = cbGstPitch;
5382	}
5383	else
5384	{
5385	pbSrc = pbGst;
5386	cbSrcPitch = cbGstPitch;
5387	pbDst = pbHst;
5388	cbDstPitch = cbHstPitch;
5389	}
5390
5391	if ( cbWidth == (uint32_t)cbGstPitch
5392	&& cbGstPitch == cbHstPitch)
5393	{
5394	/* Entire scanlines, positive pitch. */
5395	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5396	}
5397	else
5398	{
5399	for (uint32_t i = 0; i < cHeight; ++i)
5400	{
5401	memcpy(pbDst, pbSrc, cbWidth);
5402
5403	pbDst += cbDstPitch;
5404	pbSrc += cbSrcPitch;
5405	}
5406	}
5407	return VINF_SUCCESS;
5408	}
5409
5410	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5411	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5412
5413	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5414	uint32_t iDesc = 0; /* Index in the descriptor array. */
5415	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5416	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5417	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5418	for (uint32_t i = 0; i < cHeight; ++i)
5419	{
5420	uint32_t cbCurrentWidth = cbWidth;
5421	uint32_t offGmrCurrent = offGmrScanline;
5422	uint8_t *pbCurrentHost = pbHstScanline;
5423
5424	/* Find the right descriptor */
5425	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5426	{
5427	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5428	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5429	++iDesc;
5430	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5431	}
5432
5433	while (cbCurrentWidth)
5434	{
5435	uint32_t cbToCopy;
5436
5437	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5438	{
5439	cbToCopy = cbCurrentWidth;
5440	}
5441	else
5442	{
5443	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5444	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5445	}
5446
5447	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5448
5449	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5450
5451	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5452	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5453	else
5454	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5455	AssertRCBreak(rc);
5456
5457	cbCurrentWidth -= cbToCopy;
5458	offGmrCurrent += cbToCopy;
5459	pbCurrentHost += cbToCopy;
5460
5461	/* Go to the next descriptor if there's anything left. */
5462	if (cbCurrentWidth)
5463	{
5464	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5465	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5466	++iDesc;
5467	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5468	}
5469	}
5470
5471	offGmrScanline += cbGstPitch;
5472	pbHstScanline += cbHstPitch;
5473	}
5474
5475	return VINF_SUCCESS;
5476	}
5477
5478
5479	/**
5480	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5481	*
5482	* @param pSizeSrc Source surface dimensions.
5483	* @param pSizeDest Destination surface dimensions.
5484	* @param pBox Coordinates to be clipped.
5485	*/
5486	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5487	{
5488	/* Src x, w */
5489	if (pBox->srcx > pSizeSrc->width)
5490	pBox->srcx = pSizeSrc->width;
5491	if (pBox->w > pSizeSrc->width - pBox->srcx)
5492	pBox->w = pSizeSrc->width - pBox->srcx;
5493
5494	/* Src y, h */
5495	if (pBox->srcy > pSizeSrc->height)
5496	pBox->srcy = pSizeSrc->height;
5497	if (pBox->h > pSizeSrc->height - pBox->srcy)
5498	pBox->h = pSizeSrc->height - pBox->srcy;
5499
5500	/* Src z, d */
5501	if (pBox->srcz > pSizeSrc->depth)
5502	pBox->srcz = pSizeSrc->depth;
5503	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5504	pBox->d = pSizeSrc->depth - pBox->srcz;
5505
5506	/* Dest x, w */
5507	if (pBox->x > pSizeDest->width)
5508	pBox->x = pSizeDest->width;
5509	if (pBox->w > pSizeDest->width - pBox->x)
5510	pBox->w = pSizeDest->width - pBox->x;
5511
5512	/* Dest y, h */
5513	if (pBox->y > pSizeDest->height)
5514	pBox->y = pSizeDest->height;
5515	if (pBox->h > pSizeDest->height - pBox->y)
5516	pBox->h = pSizeDest->height - pBox->y;
5517
5518	/* Dest z, d */
5519	if (pBox->z > pSizeDest->depth)
5520	pBox->z = pSizeDest->depth;
5521	if (pBox->d > pSizeDest->depth - pBox->z)
5522	pBox->d = pSizeDest->depth - pBox->z;
5523	}
5524
5525	/**
5526	* Unsigned coordinates in pBox. Clip to [0; pSize).
5527	*
5528	* @param pSize Source surface dimensions.
5529	* @param pBox Coordinates to be clipped.
5530	*/
5531	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5532	{
5533	/* x, w */
5534	if (pBox->x > pSize->width)
5535	pBox->x = pSize->width;
5536	if (pBox->w > pSize->width - pBox->x)
5537	pBox->w = pSize->width - pBox->x;
5538
5539	/* y, h */
5540	if (pBox->y > pSize->height)
5541	pBox->y = pSize->height;
5542	if (pBox->h > pSize->height - pBox->y)
5543	pBox->h = pSize->height - pBox->y;
5544
5545	/* z, d */
5546	if (pBox->z > pSize->depth)
5547	pBox->z = pSize->depth;
5548	if (pBox->d > pSize->depth - pBox->z)
5549	pBox->d = pSize->depth - pBox->z;
5550	}
5551
5552	/**
5553	* Clip.
5554	*
5555	* @param pBound Bounding rectangle.
5556	* @param pRect Rectangle to be clipped.
5557	*/
5558	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5559	{
5560	int32_t left;
5561	int32_t top;
5562	int32_t right;
5563	int32_t bottom;
5564
5565	/* Right order. */
5566	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5567	if (pRect->left < pRect->right)
5568	{
5569	left = pRect->left;
5570	right = pRect->right;
5571	}
5572	else
5573	{
5574	left = pRect->right;
5575	right = pRect->left;
5576	}
5577	if (pRect->top < pRect->bottom)
5578	{
5579	top = pRect->top;
5580	bottom = pRect->bottom;
5581	}
5582	else
5583	{
5584	top = pRect->bottom;
5585	bottom = pRect->top;
5586	}
5587
5588	if (left < pBound->left)
5589	left = pBound->left;
5590	if (right < pBound->left)
5591	right = pBound->left;
5592
5593	if (left > pBound->right)
5594	left = pBound->right;
5595	if (right > pBound->right)
5596	right = pBound->right;
5597
5598	if (top < pBound->top)
5599	top = pBound->top;
5600	if (bottom < pBound->top)
5601	bottom = pBound->top;
5602
5603	if (top > pBound->bottom)
5604	top = pBound->bottom;
5605	if (bottom > pBound->bottom)
5606	bottom = pBound->bottom;
5607
5608	pRect->left = left;
5609	pRect->right = right;
5610	pRect->top = top;
5611	pRect->bottom = bottom;
5612	}
5613
5614	/**
5615	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5616	* Unblock the FIFO I/O thread so it can respond to a state change.}
5617	*/
5618	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5619	{
5620	RT_NOREF(pDevIns);
5621	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5622	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5623	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5624	}
5625
5626	/**
5627	* Enables or disables dirty page tracking for the framebuffer
5628	*
5629	* @param pDevIns The device instance.
5630	* @param pThis The shared VGA/VMSVGA instance data.
5631	* @param fTraces Enable/disable traces
5632	*/
5633	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5634	{
5635	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5636	&& !fTraces)
5637	{
5638	//Assert(pThis->svga.fTraces);
5639	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5640	return;
5641	}
5642
5643	pThis->svga.fTraces = fTraces;
5644	if (pThis->svga.fTraces)
5645	{
5646	unsigned cbFrameBuffer = pThis->vram_size;
5647
5648	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5649	/** @todo How does this work with screens? */
5650	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5651	{
5652	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5653	Assert(pThis->svga.cbScanline);
5654	# endif
5655	/* Hardware enabled; return real framebuffer size .*/
5656	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5657	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5658	}
5659
5660	if (!pThis->svga.fVRAMTracking)
5661	{
5662	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5663	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5664	pThis->svga.fVRAMTracking = true;
5665	}
5666	}
5667	else
5668	{
5669	if (pThis->svga.fVRAMTracking)
5670	{
5671	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5672	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5673	pThis->svga.fVRAMTracking = false;
5674	}
5675	}
5676	}
5677
5678	/**
5679	* @callback_method_impl{FNPCIIOREGIONMAP}
5680	*/
5681	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5682	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5683	{
5684	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5685	int rc;
5686	RT_NOREF(pPciDev);
5687	Assert(pPciDev == pDevIns->apPciDevs[0]);
5688
5689	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5690	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5691	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5692	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5693	, VERR_INTERNAL_ERROR);
5694	if (GCPhysAddress != NIL_RTGCPHYS)
5695	{
5696	/*
5697	* Mapping the FIFO RAM.
5698	*/
5699	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5700	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5701	AssertRC(rc);
5702
5703	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5704	if (RT_SUCCESS(rc))
5705	{
5706	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5707	# ifdef DEBUG_FIFO_ACCESS
5708	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5709	# else
5710	GCPhysAddress + PAGE_SIZE - 1,
5711	# endif
5712	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5713	"VMSVGA FIFO");
5714	AssertRC(rc);
5715	}
5716	# endif
5717	if (RT_SUCCESS(rc))
5718	{
5719	pThis->svga.GCPhysFIFO = GCPhysAddress;
5720	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5721	}
5722	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5723	}
5724	else
5725	{
5726	Assert(pThis->svga.GCPhysFIFO);
5727	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5728	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5729	AssertRC(rc);
5730	# else
5731	rc = VINF_SUCCESS;
5732	# endif
5733	pThis->svga.GCPhysFIFO = 0;
5734	}
5735	return rc;
5736	}
5737
5738	# ifdef VBOX_WITH_VMSVGA3D
5739
5740	/**
5741	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5742	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5743	*
5744	* @param pDevIns The device instance.
5745	* @param pThis The The shared VGA/VMSVGA instance data.
5746	* @param pThisCC The VGA/VMSVGA state for ring-3.
5747	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5748	* UINT32_MAX is used, all surfaces are processed.
5749	*/
5750	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5751	{
5752	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5753	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5754	}
5755
5756
5757	/**
5758	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5759	*/
5760	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5761	{
5762	/* There might be a specific surface ID at the start of the
5763	arguments, if not show all surfaces. */
5764	uint32_t sid = UINT32_MAX;
5765	if (pszArgs)
5766	pszArgs = RTStrStripL(pszArgs);
5767	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5768	sid = RTStrToUInt32(pszArgs);
5769
5770	/* Verbose or terse display, we default to verbose. */
5771	bool fVerbose = true;
5772	if (RTStrIStr(pszArgs, "terse"))
5773	fVerbose = false;
5774
5775	/* The size of the ascii art (x direction, y is 3/4 of x). */
5776	uint32_t cxAscii = 80;
5777	if (RTStrIStr(pszArgs, "gigantic"))
5778	cxAscii = 300;
5779	else if (RTStrIStr(pszArgs, "huge"))
5780	cxAscii = 180;
5781	else if (RTStrIStr(pszArgs, "big"))
5782	cxAscii = 132;
5783	else if (RTStrIStr(pszArgs, "normal"))
5784	cxAscii = 80;
5785	else if (RTStrIStr(pszArgs, "medium"))
5786	cxAscii = 64;
5787	else if (RTStrIStr(pszArgs, "small"))
5788	cxAscii = 48;
5789	else if (RTStrIStr(pszArgs, "tiny"))
5790	cxAscii = 24;
5791
5792	/* Y invert the image when producing the ASCII art. */
5793	bool fInvY = false;
5794	if (RTStrIStr(pszArgs, "invy"))
5795	fInvY = true;
5796
5797	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5798	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5799	}
5800
5801
5802	/**
5803	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5804	*/
5805	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5806	{
5807	/* pszArg = "sid[>dir]"
5808	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5809	*/
5810	char *pszBitmapPath = NULL;
5811	uint32_t sid = UINT32_MAX;
5812	if (pszArgs)
5813	pszArgs = RTStrStripL(pszArgs);
5814	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5815	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5816	if ( pszBitmapPath
5817	&& *pszBitmapPath == '>')
5818	++pszBitmapPath;
5819
5820	const bool fVerbose = true;
5821	const uint32_t cxAscii = 0; /* No ASCII */
5822	const bool fInvY = false; /* Do not invert. */
5823	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5824	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5825	}
5826
5827	/**
5828	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5829	*/
5830	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5831	{
5832	/* There might be a specific surface ID at the start of the
5833	arguments, if not show all contexts. */
5834	uint32_t sid = UINT32_MAX;
5835	if (pszArgs)
5836	pszArgs = RTStrStripL(pszArgs);
5837	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5838	sid = RTStrToUInt32(pszArgs);
5839
5840	/* Verbose or terse display, we default to verbose. */
5841	bool fVerbose = true;
5842	if (RTStrIStr(pszArgs, "terse"))
5843	fVerbose = false;
5844
5845	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5846	}
5847	# endif /* VBOX_WITH_VMSVGA3D */
5848
5849	/**
5850	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5851	*/
5852	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5853	{
5854	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5855	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5856	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5857	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5858	RT_NOREF(pszArgs);
5859
5860	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5861	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5862	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5863	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5864	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5865	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5866	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5867	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5868	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5869	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5870	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5871	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5872	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5873	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5874	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5875	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5876	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5877	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5878	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5879	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5880	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5881	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5882	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5883	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5884	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5885
5886	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5887	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5888	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5889	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5890
5891	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5892	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5893
5894	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5895	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5896
5897	# ifdef VBOX_WITH_VMSVGA3D
5898	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5899	# endif
5900	if (pThisCC->pDrv)
5901	{
5902	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5903	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5904	}
5905
5906	/* Dump screen information. */
5907	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5908	{
5909	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5910	if (pScreen)
5911	{
5912	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5913	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5914	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5915	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5916	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5917	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5918	{
5919	pHlp->pfnPrintf(pHlp, " (");
5920	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5921	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5922	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5923	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5924	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5925	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5926	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5927	pHlp->pfnPrintf(pHlp, " BLANKING");
5928	pHlp->pfnPrintf(pHlp, " )");
5929	}
5930	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5931	}
5932	}
5933
5934	}
5935
5936	/**
5937	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5938	*/
5939	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5940	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5941	{
5942	RT_NOREF(uPass);
5943
5944	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5945	int rc;
5946
5947	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5948	{
5949	uint32_t cScreens = 0;
5950	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5951	AssertRCReturn(rc, rc);
5952	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5953	("cScreens=%#x\n", cScreens),
5954	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5955
5956	for (uint32_t i = 0; i < cScreens; ++i)
5957	{
5958	VMSVGASCREENOBJECT screen;
5959	RT_ZERO(screen);
5960
5961	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5962	AssertLogRelRCReturn(rc, rc);
5963
5964	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5965	{
5966	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5967	*pScreen = screen;
5968	pScreen->fModified = true;
5969	}
5970	else
5971	{
5972	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5973	}
5974	}
5975	}
5976	else
5977	{
5978	/* Try to setup at least the first screen. */
5979	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5980	pScreen->fDefined = true;
5981	pScreen->fModified = true;
5982	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5983	pScreen->idScreen = 0;
5984	pScreen->xOrigin = 0;
5985	pScreen->yOrigin = 0;
5986	pScreen->offVRAM = pThis->svga.uScreenOffset;
5987	pScreen->cbPitch = pThis->svga.cbScanline;
5988	pScreen->cWidth = pThis->svga.uWidth;
5989	pScreen->cHeight = pThis->svga.uHeight;
5990	pScreen->cBpp = pThis->svga.uBpp;
5991	}
5992
5993	return VINF_SUCCESS;
5994	}
5995
5996	/**
5997	* @copydoc FNSSMDEVLOADEXEC
5998	*/
5999	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6000	{
6001	RT_NOREF(uPass);
6002	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6003	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6004	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6005	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6006	int rc;
6007
6008	/* Load our part of the VGAState */
6009	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6010	AssertRCReturn(rc, rc);
6011
6012	/* Load the VGA framebuffer. */
6013	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
6014	uint32_t cbVgaFramebuffer = _32K;
6015	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
6016	{
6017	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
6018	AssertRCReturn(rc, rc);
6019	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
6020	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
6021	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6022	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
6023	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
6024	}
6025	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
6026	AssertRCReturn(rc, rc);
6027	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
6028	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
6029	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
6030	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
6031
6032	/* Load the VMSVGA state. */
6033	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6034	AssertRCReturn(rc, rc);
6035
6036	/* Load the active cursor bitmaps. */
6037	if (pSVGAState->Cursor.fActive)
6038	{
6039	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
6040	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
6041
6042	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6043	AssertRCReturn(rc, rc);
6044	}
6045
6046	/* Load the GMR state. */
6047	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
6048	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
6049	{
6050	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
6051	AssertRCReturn(rc, rc);
6052	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
6053	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
6054	("cGMR=%#x - expected 256B..1MB\n", cGMR),
6055	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6056	}
6057
6058	if (pThis->svga.cGMR != cGMR)
6059	{
6060	/* Reallocate GMR array. */
6061	Assert(pSVGAState->paGMR != NULL);
6062	RTMemFree(pSVGAState->paGMR);
6063	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
6064	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6065	pThis->svga.cGMR = cGMR;
6066	}
6067
6068	for (uint32_t i = 0; i < cGMR; ++i)
6069	{
6070	PGMR pGMR = &pSVGAState->paGMR[i];
6071
6072	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6073	AssertRCReturn(rc, rc);
6074
6075	if (pGMR->numDescriptors)
6076	{
6077	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6078	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6079	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6080
6081	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6082	{
6083	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6084	AssertRCReturn(rc, rc);
6085	}
6086	}
6087	}
6088
6089	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6090	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
6091	# endif
6092
6093	VMSVGA_STATE_LOAD LoadState;
6094	LoadState.pSSM = pSSM;
6095	LoadState.uVersion = uVersion;
6096	LoadState.uPass = uPass;
6097	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6098	AssertLogRelRCReturn(rc, rc);
6099
6100	return VINF_SUCCESS;
6101	}
6102
6103	/**
6104	* Reinit the video mode after the state has been loaded.
6105	*/
6106	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6107	{
6108	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6109	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6110	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6111
6112	/* Set the active cursor. */
6113	if (pSVGAState->Cursor.fActive)
6114	{
6115	/* We don't store the alpha flag, but we can take a guess that if
6116	* the old register interface was used, the cursor was B&W.
6117	*/
6118	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6119
6120	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6121	true /fVisible/,
6122	fAlpha,
6123	pSVGAState->Cursor.xHotspot,
6124	pSVGAState->Cursor.yHotspot,
6125	pSVGAState->Cursor.width,
6126	pSVGAState->Cursor.height,
6127	pSVGAState->Cursor.pData);
6128	AssertRC(rc);
6129
6130	if (pThis->svga.uCursorOn)
6131	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6132	}
6133
6134	/* If the VRAM handler should not be registered, we have to explicitly
6135	* unregister it here!
6136	*/
6137	if (!pThis->svga.fVRAMTracking)
6138	{
6139	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6140	}
6141
6142	/* Let the FIFO thread deal with changing the mode. */
6143	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6144
6145	return VINF_SUCCESS;
6146	}
6147
6148	/**
6149	* Portion of SVGA state which must be saved in the FIFO thread.
6150	*/
6151	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6152	{
6153	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6154	int rc;
6155
6156	/* Save the screen objects. */
6157	/* Count defined screen object. */
6158	uint32_t cScreens = 0;
6159	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6160	{
6161	if (pSVGAState->aScreens[i].fDefined)
6162	++cScreens;
6163	}
6164
6165	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6166	AssertLogRelRCReturn(rc, rc);
6167
6168	for (uint32_t i = 0; i < cScreens; ++i)
6169	{
6170	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6171
6172	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6173	AssertLogRelRCReturn(rc, rc);
6174	}
6175	return VINF_SUCCESS;
6176	}
6177
6178	/**
6179	* @copydoc FNSSMDEVSAVEEXEC
6180	*/
6181	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6182	{
6183	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6184	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6185	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6186	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6187	int rc;
6188
6189	/* Save our part of the VGAState */
6190	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6191	AssertLogRelRCReturn(rc, rc);
6192
6193	/* Save the framebuffer backup. */
6194	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6195	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6196	AssertLogRelRCReturn(rc, rc);
6197
6198	/* Save the VMSVGA state. */
6199	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6200	AssertLogRelRCReturn(rc, rc);
6201
6202	/* Save the active cursor bitmaps. */
6203	if (pSVGAState->Cursor.fActive)
6204	{
6205	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6206	AssertLogRelRCReturn(rc, rc);
6207	}
6208
6209	/* Save the GMR state */
6210	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6211	AssertLogRelRCReturn(rc, rc);
6212	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6213	{
6214	PGMR pGMR = &pSVGAState->paGMR[i];
6215
6216	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6217	AssertLogRelRCReturn(rc, rc);
6218
6219	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6220	{
6221	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6222	AssertLogRelRCReturn(rc, rc);
6223	}
6224	}
6225
6226	/*
6227	* Must save some state (3D in particular) in the FIFO thread.
6228	*/
6229	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6230	AssertLogRelRCReturn(rc, rc);
6231
6232	return VINF_SUCCESS;
6233	}
6234
6235	/**
6236	* Destructor for PVMSVGAR3STATE structure.
6237	*
6238	* @param pThis The shared VGA/VMSVGA instance data.
6239	* @param pSVGAState Pointer to the structure. It is not deallocated.
6240	*/
6241	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6242	{
6243	# ifndef VMSVGA_USE_EMT_HALT_CODE
6244	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6245	{
6246	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6247	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6248	}
6249	# endif
6250
6251	if (pSVGAState->Cursor.fActive)
6252	{
6253	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6254	pSVGAState->Cursor.pData = NULL;
6255	pSVGAState->Cursor.fActive = false;
6256	}
6257
6258	if (pSVGAState->paGMR)
6259	{
6260	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6261	if (pSVGAState->paGMR[i].paDesc)
6262	RTMemFree(pSVGAState->paGMR[i].paDesc);
6263
6264	RTMemFree(pSVGAState->paGMR);
6265	pSVGAState->paGMR = NULL;
6266	}
6267	}
6268
6269	/**
6270	* Constructor for PVMSVGAR3STATE structure.
6271	*
6272	* @returns VBox status code.
6273	* @param pThis The shared VGA/VMSVGA instance data.
6274	* @param pSVGAState Pointer to the structure. It is already allocated.
6275	*/
6276	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6277	{
6278	int rc = VINF_SUCCESS;
6279	RT_ZERO(*pSVGAState);
6280
6281	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6282	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6283
6284	# ifndef VMSVGA_USE_EMT_HALT_CODE
6285	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6286	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6287	AssertRCReturn(rc, rc);
6288	# endif
6289
6290	return rc;
6291	}
6292
6293	/**
6294	* Initializes the host capabilities: registers and FIFO.
6295	*
6296	* @returns VBox status code.
6297	* @param pThis The shared VGA/VMSVGA instance data.
6298	* @param pThisCC The VGA/VMSVGA state for ring-3.
6299	*/
6300	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6301	{
6302	/* Register caps. */
6303	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6304	\| SVGA_CAP_GMR2
6305	\| SVGA_CAP_CURSOR
6306	\| SVGA_CAP_CURSOR_BYPASS
6307	\| SVGA_CAP_CURSOR_BYPASS_2
6308	\| SVGA_CAP_EXTENDED_FIFO
6309	\| SVGA_CAP_IRQMASK
6310	\| SVGA_CAP_PITCHLOCK
6311	\| SVGA_CAP_RECT_COPY
6312	\| SVGA_CAP_TRACES
6313	\| SVGA_CAP_SCREEN_OBJECT_2
6314	\| SVGA_CAP_ALPHA_CURSOR;
6315	# ifdef VBOX_WITH_VMSVGA3D
6316	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6317	# endif
6318
6319	/* Clear the FIFO. */
6320	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6321
6322	/* Setup FIFO capabilities. */
6323	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6324	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6325	\| SVGA_FIFO_CAP_GMR2
6326	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6327	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6328	\| SVGA_FIFO_CAP_RESERVE
6329	\| SVGA_FIFO_CAP_PITCHLOCK;
6330
6331	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6332	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6333	}
6334
6335	# ifdef VBOX_WITH_VMSVGA3D
6336	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6337	static const char * const g_apszVmSvgaDevCapNames[] =
6338	{
6339	"x3D", /* = 0 */
6340	"xMAX_LIGHTS",
6341	"xMAX_TEXTURES",
6342	"xMAX_CLIP_PLANES",
6343	"xVERTEX_SHADER_VERSION",
6344	"xVERTEX_SHADER",
6345	"xFRAGMENT_SHADER_VERSION",
6346	"xFRAGMENT_SHADER",
6347	"xMAX_RENDER_TARGETS",
6348	"xS23E8_TEXTURES",
6349	"xS10E5_TEXTURES",
6350	"xMAX_FIXED_VERTEXBLEND",
6351	"xD16_BUFFER_FORMAT",
6352	"xD24S8_BUFFER_FORMAT",
6353	"xD24X8_BUFFER_FORMAT",
6354	"xQUERY_TYPES",
6355	"xTEXTURE_GRADIENT_SAMPLING",
6356	"rMAX_POINT_SIZE",
6357	"xMAX_SHADER_TEXTURES",
6358	"xMAX_TEXTURE_WIDTH",
6359	"xMAX_TEXTURE_HEIGHT",
6360	"xMAX_VOLUME_EXTENT",
6361	"xMAX_TEXTURE_REPEAT",
6362	"xMAX_TEXTURE_ASPECT_RATIO",
6363	"xMAX_TEXTURE_ANISOTROPY",
6364	"xMAX_PRIMITIVE_COUNT",
6365	"xMAX_VERTEX_INDEX",
6366	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6367	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6368	"xMAX_VERTEX_SHADER_TEMPS",
6369	"xMAX_FRAGMENT_SHADER_TEMPS",
6370	"xTEXTURE_OPS",
6371	"xSURFACEFMT_X8R8G8B8",
6372	"xSURFACEFMT_A8R8G8B8",
6373	"xSURFACEFMT_A2R10G10B10",
6374	"xSURFACEFMT_X1R5G5B5",
6375	"xSURFACEFMT_A1R5G5B5",
6376	"xSURFACEFMT_A4R4G4B4",
6377	"xSURFACEFMT_R5G6B5",
6378	"xSURFACEFMT_LUMINANCE16",
6379	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6380	"xSURFACEFMT_ALPHA8",
6381	"xSURFACEFMT_LUMINANCE8",
6382	"xSURFACEFMT_Z_D16",
6383	"xSURFACEFMT_Z_D24S8",
6384	"xSURFACEFMT_Z_D24X8",
6385	"xSURFACEFMT_DXT1",
6386	"xSURFACEFMT_DXT2",
6387	"xSURFACEFMT_DXT3",
6388	"xSURFACEFMT_DXT4",
6389	"xSURFACEFMT_DXT5",
6390	"xSURFACEFMT_BUMPX8L8V8U8",
6391	"xSURFACEFMT_A2W10V10U10",
6392	"xSURFACEFMT_BUMPU8V8",
6393	"xSURFACEFMT_Q8W8V8U8",
6394	"xSURFACEFMT_CxV8U8",
6395	"xSURFACEFMT_R_S10E5",
6396	"xSURFACEFMT_R_S23E8",
6397	"xSURFACEFMT_RG_S10E5",
6398	"xSURFACEFMT_RG_S23E8",
6399	"xSURFACEFMT_ARGB_S10E5",
6400	"xSURFACEFMT_ARGB_S23E8",
6401	"xMISSING62",
6402	"xMAX_VERTEX_SHADER_TEXTURES",
6403	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6404	"xSURFACEFMT_V16U16",
6405	"xSURFACEFMT_G16R16",
6406	"xSURFACEFMT_A16B16G16R16",
6407	"xSURFACEFMT_UYVY",
6408	"xSURFACEFMT_YUY2",
6409	"xMULTISAMPLE_NONMASKABLESAMPLES",
6410	"xMULTISAMPLE_MASKABLESAMPLES",
6411	"xALPHATOCOVERAGE",
6412	"xSUPERSAMPLE",
6413	"xAUTOGENMIPMAPS",
6414	"xSURFACEFMT_NV12",
6415	"xSURFACEFMT_AYUV",
6416	"xMAX_CONTEXT_IDS",
6417	"xMAX_SURFACE_IDS",
6418	"xSURFACEFMT_Z_DF16",
6419	"xSURFACEFMT_Z_DF24",
6420	"xSURFACEFMT_Z_D24S8_INT",
6421	"xSURFACEFMT_BC4_UNORM",
6422	"xSURFACEFMT_BC5_UNORM", /* 83 */
6423	};
6424
6425	/**
6426	* Initializes the host 3D capabilities in FIFO.
6427	*
6428	* @returns VBox status code.
6429	* @param pThis The shared VGA/VMSVGA instance data.
6430	* @param pThisCC The VGA/VMSVGA state for ring-3.
6431	*/
6432	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6433	{
6434	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6435	bool fSavedBuffering = RTLogRelSetBuffering(true);
6436	SVGA3dCapsRecord *pCaps;
6437	SVGA3dCapPair *pData;
6438	uint32_t idxCap = 0;
6439
6440	/* 3d hardware version; latest and greatest */
6441	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6442	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6443
6444	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6445	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6446	pData = (SVGA3dCapPair *)&pCaps->data;
6447
6448	/* Fill out all 3d capabilities. */
6449	for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
6450	{
6451	uint32_t val = 0;
6452
6453	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6454	if (RT_SUCCESS(rc))
6455	{
6456	pData[idxCap][0] = i;
6457	pData[idxCap][1] = val;
6458	idxCap++;
6459	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6460	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6461	else
6462	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6463	&g_apszVmSvgaDevCapNames[i][1]));
6464	}
6465	else
6466	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6467	}
6468	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6469	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6470
6471	/* Mark end of record array. */
6472	pCaps->header.length = 0;
6473
6474	RTLogRelSetBuffering(fSavedBuffering);
6475	}
6476
6477	# endif
6478
6479	/**
6480	* Resets the SVGA hardware state
6481	*
6482	* @returns VBox status code.
6483	* @param pDevIns The device instance.
6484	*/
6485	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6486	{
6487	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6488	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6489	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6490
6491	/* Reset before init? */
6492	if (!pSVGAState)
6493	return VINF_SUCCESS;
6494
6495	Log(("vmsvgaR3Reset\n"));
6496
6497	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6498	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6499	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6500
6501	/* Reset other stuff. */
6502	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6503	RT_ZERO(pThis->svga.au32ScratchRegion);
6504
6505	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6506	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6507
6508	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6509
6510	/* Initialize FIFO and register capabilities. */
6511	vmsvgaR3InitCaps(pThis, pThisCC);
6512
6513	# ifdef VBOX_WITH_VMSVGA3D
6514	if (pThis->svga.f3DEnabled)
6515	vmsvgaR3InitFifo3DCaps(pThisCC);
6516	# endif
6517
6518	/* VRAM tracking is enabled by default during bootup. */
6519	pThis->svga.fVRAMTracking = true;
6520	pThis->svga.fEnabled = false;
6521
6522	/* Invalidate current settings. */
6523	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6524	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6525	pThis->svga.uBpp = pThis->svga.uHostBpp;
6526	pThis->svga.cbScanline = 0;
6527	pThis->svga.u32PitchLock = 0;
6528
6529	return rc;
6530	}
6531
6532	/**
6533	* Cleans up the SVGA hardware state
6534	*
6535	* @returns VBox status code.
6536	* @param pDevIns The device instance.
6537	*/
6538	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6539	{
6540	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6541	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6542
6543	/*
6544	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6545	*/
6546	if (pThisCC->svga.pFIFOIOThread)
6547	{
6548	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6549	NULL /pvParam/, 30000 /ms/);
6550	AssertLogRelRC(rc);
6551
6552	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6553	AssertLogRelRC(rc);
6554	pThisCC->svga.pFIFOIOThread = NULL;
6555	}
6556
6557	/*
6558	* Destroy the special SVGA state.
6559	*/
6560	if (pThisCC->svga.pSvgaR3State)
6561	{
6562	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6563
6564	RTMemFree(pThisCC->svga.pSvgaR3State);
6565	pThisCC->svga.pSvgaR3State = NULL;
6566	}
6567
6568	/*
6569	* Free our resources residing in the VGA state.
6570	*/
6571	if (pThisCC->svga.pbVgaFrameBufferR3)
6572	{
6573	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6574	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6575	}
6576	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6577	{
6578	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6579	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6580	}
6581	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6582	{
6583	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6584	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6585	}
6586
6587	return VINF_SUCCESS;
6588	}
6589
6590	/**
6591	* Initialize the SVGA hardware state
6592	*
6593	* @returns VBox status code.
6594	* @param pDevIns The device instance.
6595	*/
6596	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6597	{
6598	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6599	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6600	PVMSVGAR3STATE pSVGAState;
6601	int rc;
6602
6603	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6604	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6605
6606	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6607
6608	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6609	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6610	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6611
6612	/* Create event semaphore. */
6613	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6614	AssertRCReturn(rc, rc);
6615
6616	/* Create event semaphore. */
6617	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6618	AssertRCReturn(rc, rc);
6619
6620	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6621	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6622
6623	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6624	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6625
6626	pSVGAState = pThisCC->svga.pSvgaR3State;
6627
6628	/* Initialize FIFO and register capabilities. */
6629	vmsvgaR3InitCaps(pThis, pThisCC);
6630
6631	# ifdef VBOX_WITH_VMSVGA3D
6632	if (pThis->svga.f3DEnabled)
6633	{
6634	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6635	if (RT_FAILURE(rc))
6636	{
6637	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6638	pThis->svga.f3DEnabled = false;
6639	}
6640	}
6641	# endif
6642	/* VRAM tracking is enabled by default during bootup. */
6643	pThis->svga.fVRAMTracking = true;
6644
6645	/* Set up the host bpp. This value is as a default for the programmable
6646	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6647	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6648	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6649	*
6650	* NB: The driver cBits value is currently constant for the lifetime of the
6651	* VM. If that changes, the host bpp logic might need revisiting.
6652	*/
6653	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6654
6655	/* Invalidate current settings. */
6656	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6657	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6658	pThis->svga.uBpp = pThis->svga.uHostBpp;
6659	pThis->svga.cbScanline = 0;
6660
6661	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6662	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6663	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6664	{
6665	pThis->svga.u32MaxWidth -= 256;
6666	pThis->svga.u32MaxHeight -= 256;
6667	}
6668	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6669
6670	# ifdef DEBUG_GMR_ACCESS
6671	/* Register the GMR access handler type. */
6672	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6673	vmsvgaR3GmrAccessHandler,
6674	NULL, NULL, NULL,
6675	NULL, NULL, NULL,
6676	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6677	AssertRCReturn(rc, rc);
6678	# endif
6679
6680	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6681	/* Register the FIFO access handler type. In addition to
6682	debugging FIFO access, this is also used to facilitate
6683	extended fifo thread sleeps. */
6684	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6685	# ifdef DEBUG_FIFO_ACCESS
6686	PGMPHYSHANDLERKIND_ALL,
6687	# else
6688	PGMPHYSHANDLERKIND_WRITE,
6689	# endif
6690	vmsvgaR3FifoAccessHandler,
6691	NULL, NULL, NULL,
6692	NULL, NULL, NULL,
6693	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6694	AssertRCReturn(rc, rc);
6695	# endif
6696
6697	/* Create the async IO thread. */
6698	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6699	RTTHREADTYPE_IO, "VMSVGA FIFO");
6700	if (RT_FAILURE(rc))
6701	{
6702	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6703	return rc;
6704	}
6705
6706	/*
6707	* Statistics.
6708	*/
6709	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6710	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6711	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6712	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6713	# ifdef VBOX_WITH_STATISTICS
6714	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6715	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6716	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6717	# endif
6718	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6719	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6720	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6721	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6722	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6723	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6724	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6725	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6726	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6727	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6728	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6729	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6730	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6731	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6732	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6733	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6734	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6735	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6736	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6737	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6738	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6739	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6740	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6741	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6742	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6743	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6744	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6745	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6746	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6747	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6748	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6749	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6750	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6751	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6752	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6753	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6754	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6755	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6756	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6757	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6758	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6759	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6760	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6761	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6762	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6763	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6764	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6765	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6766	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6767	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6768	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6769	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6770	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6771	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6772	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6773	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6774	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6775	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6776	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6777
6778	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6779	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6780	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6781	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6782	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6783	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6784	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6785	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6786	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6787	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6788	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6789	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6790	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6791	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6792	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6793	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6794	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6795	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6796	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6797	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6798	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6799	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6800	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6801	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6802	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6803	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6804	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6805	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6806	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6807	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6808	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6809	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6810	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6811	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6812	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6813
6814	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6815	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6816	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6817	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6818	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6819	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6820	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6821	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6822	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6823	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6824	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6825	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6826	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6827	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6828	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6829	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6830	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6831	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6832	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6833	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6834	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6835	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6836	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6837	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6838	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6839	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6840	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6841	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6842	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6843	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6844	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6845	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6846	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6847	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6848	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6849	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6850	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6851	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6852	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6853	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6854	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6855	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6856	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6857	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6858	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6859	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6860	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6861	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6862	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6863	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6864	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6865	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6866
6867	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6868	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6869	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6870	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6871	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6872	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6873	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6874	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6875	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6876	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6877	# endif
6878	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6879	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6880	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6881	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6882	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6883
6884	# undef REG_CNT
6885	# undef REG_PRF
6886
6887	/*
6888	* Info handlers.
6889	*/
6890	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6891	# ifdef VBOX_WITH_VMSVGA3D
6892	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6893	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6894	"VMSVGA 3d surface details. "
6895	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6896	vmsvgaR3Info3dSurface);
6897	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6898	"VMSVGA 3d surface details and bitmap: "
6899	"sid[>dir]",
6900	vmsvgaR3Info3dSurfaceBmp);
6901	# endif
6902
6903	return VINF_SUCCESS;
6904	}
6905
6906	/**
6907	* Power On notification.
6908	*
6909	* @returns VBox status code.
6910	* @param pDevIns The device instance data.
6911	*
6912	* @remarks Caller enters the device critical section.
6913	*/
6914	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6915	{
6916	# ifdef VBOX_WITH_VMSVGA3D
6917	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6918	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6919	if (pThis->svga.f3DEnabled)
6920	{
6921	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6922
6923	if (RT_SUCCESS(rc))
6924	{
6925	/* Initialize FIFO 3D capabilities. */
6926	vmsvgaR3InitFifo3DCaps(pThisCC);
6927	}
6928	}
6929	# else /* !VBOX_WITH_VMSVGA3D */
6930	RT_NOREF(pDevIns);
6931	# endif /* !VBOX_WITH_VMSVGA3D */
6932	}
6933
6934	/**
6935	* Power Off notification.
6936	*
6937	* @param pDevIns The device instance data.
6938	*
6939	* @remarks Caller enters the device critical section.
6940	*/
6941	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6942	{
6943	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6944	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6945
6946	/*
6947	* Notify the FIFO thread.
6948	*/
6949	if (pThisCC->svga.pFIFOIOThread)
6950	{
6951	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6952	NULL /pvParam/, 30000 /ms/);
6953	AssertLogRelRC(rc);
6954	}
6955	}
6956
6957	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 85672

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