DevVGA-SVGA.cpp@ 86156

Last change on this file since 86156 was 86024, checked in by vboxsync, 4 years ago
Devices/Graphics: use current VMSVGA headers
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1	/* $Id: DevVGA-SVGA.cpp 86024 2020-09-03 14:37:31Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.virtualbox.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#define VMSVGA_USE_EMT_HALT_CODE
133	#include <VBox/vmm/pdmdev.h>
134	#include <VBox/version.h>
135	#include <VBox/err.h>
136	#include <VBox/log.h>
137	#include <VBox/vmm/pgm.h>
138	#ifdef VMSVGA_USE_EMT_HALT_CODE
139	# include <VBox/vmm/vmapi.h>
140	# include <VBox/vmm/vmcpuset.h>
141	#endif
142	#include <VBox/sup.h>
143
144	#include <iprt/assert.h>
145	#include <iprt/semaphore.h>
146	#include <iprt/uuid.h>
147	#ifdef IN_RING3
148	# include <iprt/ctype.h>
149	# include <iprt/mem.h>
150	# ifdef VBOX_STRICT
151	# include <iprt/time.h>
152	# endif
153	#endif
154
155	#include <VBox/AssertGuest.h>
156	#include <VBox/VMMDev.h>
157	#include <VBoxVideo.h>
158	#include <VBox/bioslogo.h>
159
160	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
161	#include "DevVGA.h"
162
163	#include "DevVGA-SVGA.h"
164	#ifdef VBOX_WITH_VMSVGA3D
165	# include "DevVGA-SVGA3d.h"
166	# ifdef RT_OS_DARWIN
167	# include "DevVGA-SVGA3d-cocoa.h"
168	# endif
169	# ifdef RT_OS_LINUX
170	# ifdef IN_RING3
171	#include "DevVGA-SVGA3d-glLdr.h"
172	# endif
173	# endif
174	#endif
175
176
177	/*********************************************************************************************************************************
178	* Defined Constants And Macros *
179	*********************************************************************************************************************************/
180	/**
181	* Macro for checking if a fixed FIFO register is valid according to the
182	* current FIFO configuration.
183	*
184	* @returns true / false.
185	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
186	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
187	*/
188	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
189
190
191	/*********************************************************************************************************************************
192	* Structures and Typedefs *
193	*********************************************************************************************************************************/
194	/**
195	* 64-bit GMR descriptor.
196	*/
197	typedef struct
198	{
199	RTGCPHYS GCPhys;
200	uint64_t numPages;
201	} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;
202
203	/**
204	* GMR slot
205	*/
206	typedef struct
207	{
208	uint32_t cMaxPages;
209	uint32_t cbTotal;
210	uint32_t numDescriptors;
211	PVMSVGAGMRDESCRIPTOR paDesc;
212	} GMR, *PGMR;
213
214	#ifdef IN_RING3
215	/**
216	* Internal SVGA ring-3 only state.
217	*/
218	typedef struct VMSVGAR3STATE
219	{
220	GMR *paGMR; // [VMSVGAState::cGMR]
221	struct
222	{
223	SVGAGuestPtr RT_UNTRUSTED_GUEST ptr;
224	uint32_t RT_UNTRUSTED_GUEST bytesPerLine;
225	SVGAGMRImageFormat RT_UNTRUSTED_GUEST format;
226	} GMRFB;
227	struct
228	{
229	bool fActive;
230	uint32_t xHotspot;
231	uint32_t yHotspot;
232	uint32_t width;
233	uint32_t height;
234	uint32_t cbData;
235	void *pData;
236	} Cursor;
237	SVGAColorBGRX colorAnnotation;
238
239	# ifdef VMSVGA_USE_EMT_HALT_CODE
240	/** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
241	uint32_t volatile cBusyDelayedEmts;
242	/** Set of EMTs that are */
243	VMCPUSET BusyDelayedEmts;
244	# else
245	/** Number of EMTs waiting on hBusyDelayedEmts. */
246	uint32_t volatile cBusyDelayedEmts;
247	/** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
248	* busy (ugly). */
249	RTSEMEVENTMULTI hBusyDelayedEmts;
250	# endif
251
252	/** Information obout screens. */
253	VMSVGASCREENOBJECT aScreens[64];
254
255	/** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
256	STAMPROFILE StatBusyDelayEmts;
257
258	STAMPROFILE StatR3Cmd3dPresentProf;
259	STAMPROFILE StatR3Cmd3dDrawPrimitivesProf;
260	STAMPROFILE StatR3Cmd3dSurfaceDmaProf;
261	STAMPROFILE StatR3Cmd3dBlitSurfaceToScreenProf;
262	STAMCOUNTER StatR3CmdDefineGmr2;
263	STAMCOUNTER StatR3CmdDefineGmr2Free;
264	STAMCOUNTER StatR3CmdDefineGmr2Modify;
265	STAMCOUNTER StatR3CmdRemapGmr2;
266	STAMCOUNTER StatR3CmdRemapGmr2Modify;
267	STAMCOUNTER StatR3CmdInvalidCmd;
268	STAMCOUNTER StatR3CmdFence;
269	STAMCOUNTER StatR3CmdUpdate;
270	STAMCOUNTER StatR3CmdUpdateVerbose;
271	STAMCOUNTER StatR3CmdDefineCursor;
272	STAMCOUNTER StatR3CmdDefineAlphaCursor;
273	STAMCOUNTER StatR3CmdMoveCursor;
274	STAMCOUNTER StatR3CmdDisplayCursor;
275	STAMCOUNTER StatR3CmdRectFill;
276	STAMCOUNTER StatR3CmdRectCopy;
277	STAMCOUNTER StatR3CmdRectRopCopy;
278	STAMCOUNTER StatR3CmdEscape;
279	STAMCOUNTER StatR3CmdDefineScreen;
280	STAMCOUNTER StatR3CmdDestroyScreen;
281	STAMCOUNTER StatR3CmdDefineGmrFb;
282	STAMCOUNTER StatR3CmdBlitGmrFbToScreen;
283	STAMCOUNTER StatR3CmdBlitScreentoGmrFb;
284	STAMCOUNTER StatR3CmdAnnotationFill;
285	STAMCOUNTER StatR3CmdAnnotationCopy;
286	STAMCOUNTER StatR3Cmd3dSurfaceDefine;
287	STAMCOUNTER StatR3Cmd3dSurfaceDefineV2;
288	STAMCOUNTER StatR3Cmd3dSurfaceDestroy;
289	STAMCOUNTER StatR3Cmd3dSurfaceCopy;
290	STAMCOUNTER StatR3Cmd3dSurfaceStretchBlt;
291	STAMCOUNTER StatR3Cmd3dSurfaceDma;
292	STAMCOUNTER StatR3Cmd3dSurfaceScreen;
293	STAMCOUNTER StatR3Cmd3dContextDefine;
294	STAMCOUNTER StatR3Cmd3dContextDestroy;
295	STAMCOUNTER StatR3Cmd3dSetTransform;
296	STAMCOUNTER StatR3Cmd3dSetZRange;
297	STAMCOUNTER StatR3Cmd3dSetRenderState;
298	STAMCOUNTER StatR3Cmd3dSetRenderTarget;
299	STAMCOUNTER StatR3Cmd3dSetTextureState;
300	STAMCOUNTER StatR3Cmd3dSetMaterial;
301	STAMCOUNTER StatR3Cmd3dSetLightData;
302	STAMCOUNTER StatR3Cmd3dSetLightEnable;
303	STAMCOUNTER StatR3Cmd3dSetViewPort;
304	STAMCOUNTER StatR3Cmd3dSetClipPlane;
305	STAMCOUNTER StatR3Cmd3dClear;
306	STAMCOUNTER StatR3Cmd3dPresent;
307	STAMCOUNTER StatR3Cmd3dPresentReadBack;
308	STAMCOUNTER StatR3Cmd3dShaderDefine;
309	STAMCOUNTER StatR3Cmd3dShaderDestroy;
310	STAMCOUNTER StatR3Cmd3dSetShader;
311	STAMCOUNTER StatR3Cmd3dSetShaderConst;
312	STAMCOUNTER StatR3Cmd3dDrawPrimitives;
313	STAMCOUNTER StatR3Cmd3dSetScissorRect;
314	STAMCOUNTER StatR3Cmd3dBeginQuery;
315	STAMCOUNTER StatR3Cmd3dEndQuery;
316	STAMCOUNTER StatR3Cmd3dWaitForQuery;
317	STAMCOUNTER StatR3Cmd3dGenerateMipmaps;
318	STAMCOUNTER StatR3Cmd3dActivateSurface;
319	STAMCOUNTER StatR3Cmd3dDeactivateSurface;
320
321	STAMCOUNTER StatR3RegConfigDoneWr;
322	STAMCOUNTER StatR3RegGmrDescriptorWr;
323	STAMCOUNTER StatR3RegGmrDescriptorWrErrors;
324	STAMCOUNTER StatR3RegGmrDescriptorWrFree;
325
326	STAMCOUNTER StatFifoCommands;
327	STAMCOUNTER StatFifoErrors;
328	STAMCOUNTER StatFifoUnkCmds;
329	STAMCOUNTER StatFifoTodoTimeout;
330	STAMCOUNTER StatFifoTodoWoken;
331	STAMPROFILE StatFifoStalls;
332	STAMPROFILE StatFifoExtendedSleep;
333	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
334	STAMCOUNTER StatFifoAccessHandler;
335	# endif
336	STAMCOUNTER StatFifoCursorFetchAgain;
337	STAMCOUNTER StatFifoCursorNoChange;
338	STAMCOUNTER StatFifoCursorPosition;
339	STAMCOUNTER StatFifoCursorVisiblity;
340	STAMCOUNTER StatFifoWatchdogWakeUps;
341	} VMSVGAR3STATE, *PVMSVGAR3STATE;
342	#endif /* IN_RING3 */
343
344
345	/*********************************************************************************************************************************
346	* Internal Functions *
347	*********************************************************************************************************************************/
348	#ifdef IN_RING3
349	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
350	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
351	# endif
352	# ifdef DEBUG_GMR_ACCESS
353	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
354	# endif
355	#endif
356
357
358	/*********************************************************************************************************************************
359	* Global Variables *
360	*********************************************************************************************************************************/
361	#ifdef IN_RING3
362
363	/**
364	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
365	*/
366	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
367	{
368	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
369	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
370	SSMFIELD_ENTRY_TERM()
371	};
372
373	/**
374	* SSM descriptor table for the GMR structure.
375	*/
376	static SSMFIELD const g_aGMRFields[] =
377	{
378	SSMFIELD_ENTRY( GMR, cMaxPages),
379	SSMFIELD_ENTRY( GMR, cbTotal),
380	SSMFIELD_ENTRY( GMR, numDescriptors),
381	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
382	SSMFIELD_ENTRY_TERM()
383	};
384
385	/**
386	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
387	*/
388	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
389	{
390	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
391	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
392	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
393	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
394	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
395	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
396	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
397	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
398	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
399	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
400	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
401	SSMFIELD_ENTRY_TERM()
402	};
403
404	/**
405	* SSM descriptor table for the VMSVGAR3STATE structure.
406	*/
407	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
408	{
409	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
410	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
411	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
412	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
413	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
414	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
415	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
416	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
417	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
418	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
419	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
420	#ifdef VMSVGA_USE_EMT_HALT_CODE
421	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
422	#else
423	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
424	#endif
425	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
426	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
427	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
428	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
429	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
430	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
431	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
432	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
433	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
434	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
435	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
436	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
437	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
438	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
439	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
440	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
441	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
442	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
443	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
444	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
445	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
446	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
447	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
448	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
449	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
450	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
451	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
452	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
453	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
454	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
455	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
456	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
457	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
458	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
459	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
460	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
461	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
462	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
463	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
464	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
465	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
466	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
467	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
468	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
469	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
470	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
471	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
472	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
473	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
474	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
475	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
476	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
477	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
478	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
479	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
480	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
481	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
482	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
483	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
484	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
485	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
486	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
487	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
488
489	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
490	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
491	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
492	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
493
494	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
495	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
496	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
497	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
498	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
499	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
500	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
501	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
502	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
503	# endif
504	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
505	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
506	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
507	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
508
509	SSMFIELD_ENTRY_TERM()
510	};
511
512	/**
513	* SSM descriptor table for the VGAState.svga structure.
514	*/
515	static SSMFIELD const g_aVGAStateSVGAFields[] =
516	{
517	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
518	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
519	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
520	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
521	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
522	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
523	SSMFIELD_ENTRY( VMSVGAState, fBusy),
524	SSMFIELD_ENTRY( VMSVGAState, fTraces),
525	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
526	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
527	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
528	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
529	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
530	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
531	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
532	SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),
533	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
534	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
535	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
536	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
537	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
538	SSMFIELD_ENTRY( VMSVGAState, uWidth),
539	SSMFIELD_ENTRY( VMSVGAState, uHeight),
540	SSMFIELD_ENTRY( VMSVGAState, uBpp),
541	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
542	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
543	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
544	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
545	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
546	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
547	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
548	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
549	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
550	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
551	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
552	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
553	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
554	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
555	SSMFIELD_ENTRY_TERM()
556	};
557	#endif /* IN_RING3 */
558
559
560	/*********************************************************************************************************************************
561	* Internal Functions *
562	*********************************************************************************************************************************/
563	#ifdef IN_RING3
564	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
565	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
566	uint32_t uVersion, uint32_t uPass);
567	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
568	# ifdef VBOX_WITH_VMSVGA3D
569	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR);
570	# endif /* VBOX_WITH_VMSVGA3D */
571	#endif /* IN_RING3 */
572
573
574
575	#ifdef IN_RING3
576	VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen)
577	{
578	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
579	if ( idScreen < (uint32_t)RT_ELEMENTS(pSVGAState->aScreens)
580	&& pSVGAState
581	&& pSVGAState->aScreens[idScreen].fDefined)
582	{
583	return &pSVGAState->aScreens[idScreen];
584	}
585	return NULL;
586	}
587
588	void vmsvgaR3ResetScreens(PVGASTATE pThis, PVGASTATECC pThisCC)
589	{
590	# ifdef VBOX_WITH_VMSVGA3D
591	if (pThis->svga.f3DEnabled)
592	{
593	for (uint32_t idScreen = 0; idScreen < (uint32_t)RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens); ++idScreen)
594	{
595	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
596	if (pScreen)
597	vmsvga3dDestroyScreen(pThisCC, pScreen);
598	}
599	}
600	# else
601	RT_NOREF(pThis, pThisCC);
602	# endif
603	}
604	#endif /* IN_RING3 */
605
606	#ifdef LOG_ENABLED
607
608	/**
609	* Index register string name lookup
610	*
611	* @returns Index register string or "UNKNOWN"
612	* @param pThis The shared VGA/VMSVGA state.
613	* @param idxReg The index register.
614	*/
615	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
616	{
617	switch (idxReg)
618	{
619	case SVGA_REG_ID: return "SVGA_REG_ID";
620	case SVGA_REG_ENABLE: return "SVGA_REG_ENABLE";
621	case SVGA_REG_WIDTH: return "SVGA_REG_WIDTH";
622	case SVGA_REG_HEIGHT: return "SVGA_REG_HEIGHT";
623	case SVGA_REG_MAX_WIDTH: return "SVGA_REG_MAX_WIDTH";
624	case SVGA_REG_MAX_HEIGHT: return "SVGA_REG_MAX_HEIGHT";
625	case SVGA_REG_DEPTH: return "SVGA_REG_DEPTH";
626	case SVGA_REG_BITS_PER_PIXEL: return "SVGA_REG_BITS_PER_PIXEL"; /* Current bpp in the guest */
627	case SVGA_REG_HOST_BITS_PER_PIXEL: return "SVGA_REG_HOST_BITS_PER_PIXEL"; /* (Deprecated) */
628	case SVGA_REG_PSEUDOCOLOR: return "SVGA_REG_PSEUDOCOLOR";
629	case SVGA_REG_RED_MASK: return "SVGA_REG_RED_MASK";
630	case SVGA_REG_GREEN_MASK: return "SVGA_REG_GREEN_MASK";
631	case SVGA_REG_BLUE_MASK: return "SVGA_REG_BLUE_MASK";
632	case SVGA_REG_BYTES_PER_LINE: return "SVGA_REG_BYTES_PER_LINE";
633	case SVGA_REG_VRAM_SIZE: return "SVGA_REG_VRAM_SIZE"; /* VRAM size */
634	case SVGA_REG_FB_START: return "SVGA_REG_FB_START"; /* Frame buffer physical address. */
635	case SVGA_REG_FB_OFFSET: return "SVGA_REG_FB_OFFSET"; /* Offset of the frame buffer in VRAM */
636	case SVGA_REG_FB_SIZE: return "SVGA_REG_FB_SIZE"; /* Frame buffer size */
637	case SVGA_REG_CAPABILITIES: return "SVGA_REG_CAPABILITIES";
638	case SVGA_REG_MEM_START: return "SVGA_REG_MEM_START"; /* FIFO start */
639	case SVGA_REG_MEM_SIZE: return "SVGA_REG_MEM_SIZE"; /* FIFO size */
640	case SVGA_REG_CONFIG_DONE: return "SVGA_REG_CONFIG_DONE"; /* Set when memory area configured */
641	case SVGA_REG_SYNC: return "SVGA_REG_SYNC"; /* See "FIFO Synchronization Registers" */
642	case SVGA_REG_BUSY: return "SVGA_REG_BUSY"; /* See "FIFO Synchronization Registers" */
643	case SVGA_REG_GUEST_ID: return "SVGA_REG_GUEST_ID"; /* Set guest OS identifier */
644	case SVGA_REG_SCRATCH_SIZE: return "SVGA_REG_SCRATCH_SIZE"; /* Number of scratch registers */
645	case SVGA_REG_MEM_REGS: return "SVGA_REG_MEM_REGS"; /* Number of FIFO registers */
646	case SVGA_REG_PITCHLOCK: return "SVGA_REG_PITCHLOCK"; /* Fixed pitch for all modes */
647	case SVGA_REG_IRQMASK: return "SVGA_REG_IRQMASK"; /* Interrupt mask */
648	case SVGA_REG_GMR_ID: return "SVGA_REG_GMR_ID";
649	case SVGA_REG_GMR_DESCRIPTOR: return "SVGA_REG_GMR_DESCRIPTOR";
650	case SVGA_REG_GMR_MAX_IDS: return "SVGA_REG_GMR_MAX_IDS";
651	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
652	case SVGA_REG_TRACES: return "SVGA_REG_TRACES"; /* Enable trace-based updates even when FIFO is on */
653	case SVGA_REG_GMRS_MAX_PAGES: return "SVGA_REG_GMRS_MAX_PAGES"; /* Maximum number of 4KB pages for all GMRs */
654	case SVGA_REG_MEMORY_SIZE: return "SVGA_REG_MEMORY_SIZE"; /* Total dedicated device memory excluding FIFO */
655	case SVGA_REG_TOP: return "SVGA_REG_TOP"; /* Must be 1 more than the last register */
656	case SVGA_PALETTE_BASE: return "SVGA_PALETTE_BASE"; /* Base of SVGA color map */
657	case SVGA_REG_CURSOR_ID: return "SVGA_REG_CURSOR_ID";
658	case SVGA_REG_CURSOR_X: return "SVGA_REG_CURSOR_X";
659	case SVGA_REG_CURSOR_Y: return "SVGA_REG_CURSOR_Y";
660	case SVGA_REG_CURSOR_ON: return "SVGA_REG_CURSOR_ON";
661	case SVGA_REG_NUM_GUEST_DISPLAYS: return "SVGA_REG_NUM_GUEST_DISPLAYS"; /* Number of guest displays in X/Y direction */
662	case SVGA_REG_DISPLAY_ID: return "SVGA_REG_DISPLAY_ID"; /* Display ID for the following display attributes */
663	case SVGA_REG_DISPLAY_IS_PRIMARY: return "SVGA_REG_DISPLAY_IS_PRIMARY"; /* Whether this is a primary display */
664	case SVGA_REG_DISPLAY_POSITION_X: return "SVGA_REG_DISPLAY_POSITION_X"; /* The display position x */
665	case SVGA_REG_DISPLAY_POSITION_Y: return "SVGA_REG_DISPLAY_POSITION_Y"; /* The display position y */
666	case SVGA_REG_DISPLAY_WIDTH: return "SVGA_REG_DISPLAY_WIDTH"; /* The display's width */
667	case SVGA_REG_DISPLAY_HEIGHT: return "SVGA_REG_DISPLAY_HEIGHT"; /* The display's height */
668	case SVGA_REG_NUM_DISPLAYS: return "SVGA_REG_NUM_DISPLAYS"; /* (Deprecated) */
669
670	default:
671	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
672	return "SVGA_SCRATCH_BASE reg";
673	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
674	return "SVGA_PALETTE_BASE reg";
675	return "UNKNOWN";
676	}
677	}
678
679	#ifdef IN_RING3
680	/**
681	* FIFO command name lookup
682	*
683	* @returns FIFO command string or "UNKNOWN"
684	* @param u32Cmd FIFO command
685	*/
686	static const char *vmsvgaR3FifoCmdToString(uint32_t u32Cmd)
687	{
688	switch (u32Cmd)
689	{
690	case SVGA_CMD_INVALID_CMD: return "SVGA_CMD_INVALID_CMD";
691	case SVGA_CMD_UPDATE: return "SVGA_CMD_UPDATE";
692	case SVGA_CMD_RECT_COPY: return "SVGA_CMD_RECT_COPY";
693	case SVGA_CMD_RECT_ROP_COPY: return "SVGA_CMD_RECT_ROP_COPY";
694	case SVGA_CMD_DEFINE_CURSOR: return "SVGA_CMD_DEFINE_CURSOR";
695	case SVGA_CMD_DISPLAY_CURSOR: return "SVGA_CMD_DISPLAY_CURSOR";
696	case SVGA_CMD_MOVE_CURSOR: return "SVGA_CMD_MOVE_CURSOR";
697	case SVGA_CMD_DEFINE_ALPHA_CURSOR: return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
698	case SVGA_CMD_UPDATE_VERBOSE: return "SVGA_CMD_UPDATE_VERBOSE";
699	case SVGA_CMD_FRONT_ROP_FILL: return "SVGA_CMD_FRONT_ROP_FILL";
700	case SVGA_CMD_FENCE: return "SVGA_CMD_FENCE";
701	case SVGA_CMD_ESCAPE: return "SVGA_CMD_ESCAPE";
702	case SVGA_CMD_DEFINE_SCREEN: return "SVGA_CMD_DEFINE_SCREEN";
703	case SVGA_CMD_DESTROY_SCREEN: return "SVGA_CMD_DESTROY_SCREEN";
704	case SVGA_CMD_DEFINE_GMRFB: return "SVGA_CMD_DEFINE_GMRFB";
705	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN: return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
706	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB: return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
707	case SVGA_CMD_ANNOTATION_FILL: return "SVGA_CMD_ANNOTATION_FILL";
708	case SVGA_CMD_ANNOTATION_COPY: return "SVGA_CMD_ANNOTATION_COPY";
709	case SVGA_CMD_DEFINE_GMR2: return "SVGA_CMD_DEFINE_GMR2";
710	case SVGA_CMD_REMAP_GMR2: return "SVGA_CMD_REMAP_GMR2";
711	case SVGA_3D_CMD_SURFACE_DEFINE: return "SVGA_3D_CMD_SURFACE_DEFINE";
712	case SVGA_3D_CMD_SURFACE_DESTROY: return "SVGA_3D_CMD_SURFACE_DESTROY";
713	case SVGA_3D_CMD_SURFACE_COPY: return "SVGA_3D_CMD_SURFACE_COPY";
714	case SVGA_3D_CMD_SURFACE_STRETCHBLT: return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
715	case SVGA_3D_CMD_SURFACE_DMA: return "SVGA_3D_CMD_SURFACE_DMA";
716	case SVGA_3D_CMD_CONTEXT_DEFINE: return "SVGA_3D_CMD_CONTEXT_DEFINE";
717	case SVGA_3D_CMD_CONTEXT_DESTROY: return "SVGA_3D_CMD_CONTEXT_DESTROY";
718	case SVGA_3D_CMD_SETTRANSFORM: return "SVGA_3D_CMD_SETTRANSFORM";
719	case SVGA_3D_CMD_SETZRANGE: return "SVGA_3D_CMD_SETZRANGE";
720	case SVGA_3D_CMD_SETRENDERSTATE: return "SVGA_3D_CMD_SETRENDERSTATE";
721	case SVGA_3D_CMD_SETRENDERTARGET: return "SVGA_3D_CMD_SETRENDERTARGET";
722	case SVGA_3D_CMD_SETTEXTURESTATE: return "SVGA_3D_CMD_SETTEXTURESTATE";
723	case SVGA_3D_CMD_SETMATERIAL: return "SVGA_3D_CMD_SETMATERIAL";
724	case SVGA_3D_CMD_SETLIGHTDATA: return "SVGA_3D_CMD_SETLIGHTDATA";
725	case SVGA_3D_CMD_SETLIGHTENABLED: return "SVGA_3D_CMD_SETLIGHTENABLED";
726	case SVGA_3D_CMD_SETVIEWPORT: return "SVGA_3D_CMD_SETVIEWPORT";
727	case SVGA_3D_CMD_SETCLIPPLANE: return "SVGA_3D_CMD_SETCLIPPLANE";
728	case SVGA_3D_CMD_CLEAR: return "SVGA_3D_CMD_CLEAR";
729	case SVGA_3D_CMD_PRESENT: return "SVGA_3D_CMD_PRESENT";
730	case SVGA_3D_CMD_SHADER_DEFINE: return "SVGA_3D_CMD_SHADER_DEFINE";
731	case SVGA_3D_CMD_SHADER_DESTROY: return "SVGA_3D_CMD_SHADER_DESTROY";
732	case SVGA_3D_CMD_SET_SHADER: return "SVGA_3D_CMD_SET_SHADER";
733	case SVGA_3D_CMD_SET_SHADER_CONST: return "SVGA_3D_CMD_SET_SHADER_CONST";
734	case SVGA_3D_CMD_DRAW_PRIMITIVES: return "SVGA_3D_CMD_DRAW_PRIMITIVES";
735	case SVGA_3D_CMD_SETSCISSORRECT: return "SVGA_3D_CMD_SETSCISSORRECT";
736	case SVGA_3D_CMD_BEGIN_QUERY: return "SVGA_3D_CMD_BEGIN_QUERY";
737	case SVGA_3D_CMD_END_QUERY: return "SVGA_3D_CMD_END_QUERY";
738	case SVGA_3D_CMD_WAIT_FOR_QUERY: return "SVGA_3D_CMD_WAIT_FOR_QUERY";
739	case SVGA_3D_CMD_PRESENT_READBACK: return "SVGA_3D_CMD_PRESENT_READBACK";
740	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
741	case SVGA_3D_CMD_SURFACE_DEFINE_V2: return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
742	case SVGA_3D_CMD_GENERATE_MIPMAPS: return "SVGA_3D_CMD_GENERATE_MIPMAPS";
743	case SVGA_3D_CMD_ACTIVATE_SURFACE: return "SVGA_3D_CMD_ACTIVATE_SURFACE";
744	case SVGA_3D_CMD_DEACTIVATE_SURFACE: return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
745	default: return "UNKNOWN";
746	}
747	}
748	# endif /* IN_RING3 */
749
750	#endif /* LOG_ENABLED */
751	#ifdef IN_RING3
752
753	/**
754	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
755	*/
756	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
757	{
758	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
759	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
760
761	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
762	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
763
764	/** @todo Test how it interacts with multiple screen objects. */
765	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
766	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
767	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
768
769	if (x < uWidth)
770	{
771	pThis->svga.viewport.x = x;
772	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
773	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
774	}
775	else
776	{
777	pThis->svga.viewport.x = uWidth;
778	pThis->svga.viewport.cx = 0;
779	pThis->svga.viewport.xRight = uWidth;
780	}
781	if (y < uHeight)
782	{
783	pThis->svga.viewport.y = y;
784	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
785	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
786	pThis->svga.viewport.yHighWC = uHeight - y;
787	}
788	else
789	{
790	pThis->svga.viewport.y = uHeight;
791	pThis->svga.viewport.cy = 0;
792	pThis->svga.viewport.yLowWC = 0;
793	pThis->svga.viewport.yHighWC = 0;
794	}
795
796	# ifdef VBOX_WITH_VMSVGA3D
797	/*
798	* Now inform the 3D backend.
799	*/
800	if (pThis->svga.f3DEnabled)
801	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
802	# else
803	RT_NOREF(OldViewport);
804	# endif
805	}
806
807
808	/**
809	* Updating screen information in API
810	*
811	* @param pThis The The shared VGA/VMSVGA instance data.
812	* @param pThisCC The VGA/VMSVGA state for ring-3.
813	*/
814	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
815	{
816	int rc;
817
818	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
819
820	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
821	{
822	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
823	if (!pScreen->fModified)
824	continue;
825
826	pScreen->fModified = false;
827
828	VBVAINFOVIEW view;
829	RT_ZERO(view);
830	view.u32ViewIndex = pScreen->idScreen;
831	// view.u32ViewOffset = 0;
832	view.u32ViewSize = pThis->vram_size;
833	view.u32MaxScreenSize = pThis->vram_size;
834
835	VBVAINFOSCREEN screen;
836	RT_ZERO(screen);
837	screen.u32ViewIndex = pScreen->idScreen;
838
839	if (pScreen->fDefined)
840	{
841	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
842	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
843	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
844	{
845	Assert(pThis->svga.fGFBRegisters);
846	continue;
847	}
848
849	screen.i32OriginX = pScreen->xOrigin;
850	screen.i32OriginY = pScreen->yOrigin;
851	screen.u32StartOffset = pScreen->offVRAM;
852	screen.u32LineSize = pScreen->cbPitch;
853	screen.u32Width = pScreen->cWidth;
854	screen.u32Height = pScreen->cHeight;
855	screen.u16BitsPerPixel = pScreen->cBpp;
856	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
857	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
858	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
859	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
860	}
861	else
862	{
863	/* Screen is destroyed. */
864	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
865	}
866
867	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pThisCC->pbVRam, /fResetInputMapping=/ true);
868	AssertRC(rc);
869	}
870	}
871
872
873	/**
874	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
875	*
876	* Used to update screen offsets (positions) since appearently vmwgfx fails to
877	* pass correct offsets thru FIFO.
878	*/
879	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
880	{
881	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
882	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
883	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
884
885	AssertReturnVoid(pSVGAState);
886
887	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
888	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
889	for (uint32_t i = 0; i < cPositions; ++i)
890	{
891	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
892	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
893	continue;
894
895	if (pSVGAState->aScreens[i].xOrigin == -1)
896	continue;
897	if (pSVGAState->aScreens[i].yOrigin == -1)
898	continue;
899
900	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
901	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
902	pSVGAState->aScreens[i].fModified = true;
903	}
904
905	vmsvgaR3VBVAResize(pThis, pThisCC);
906	}
907
908	#endif /* IN_RING3 */
909
910	/**
911	* Read port register
912	*
913	* @returns VBox status code.
914	* @param pDevIns The device instance.
915	* @param pThis The shared VGA/VMSVGA state.
916	* @param pu32 Where to store the read value
917	*/
918	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
919	{
920	#ifdef IN_RING3
921	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
922	#endif
923	int rc = VINF_SUCCESS;
924	*pu32 = 0;
925
926	/* Rough index register validation. */
927	uint32_t idxReg = pThis->svga.u32IndexReg;
928	#if !defined(IN_RING3) && defined(VBOX_STRICT)
929	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
930	VINF_IOM_R3_IOPORT_READ);
931	#else
932	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
933	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
934	VINF_SUCCESS);
935	#endif
936	RT_UNTRUSTED_VALIDATED_FENCE();
937
938	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
939	if ( idxReg >= SVGA_REG_CAPABILITIES
940	&& pThis->svga.u32SVGAId == SVGA_ID_0)
941	{
942	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
943	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
944	}
945
946	switch (idxReg)
947	{
948	case SVGA_REG_ID:
949	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
950	*pu32 = pThis->svga.u32SVGAId;
951	break;
952
953	case SVGA_REG_ENABLE:
954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
955	*pu32 = pThis->svga.fEnabled;
956	break;
957
958	case SVGA_REG_WIDTH:
959	{
960	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
961	if ( pThis->svga.fEnabled
962	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
963	*pu32 = pThis->svga.uWidth;
964	else
965	{
966	#ifndef IN_RING3
967	rc = VINF_IOM_R3_IOPORT_READ;
968	#else
969	*pu32 = pThisCC->pDrv->cx;
970	#endif
971	}
972	break;
973	}
974
975	case SVGA_REG_HEIGHT:
976	{
977	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
978	if ( pThis->svga.fEnabled
979	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
980	*pu32 = pThis->svga.uHeight;
981	else
982	{
983	#ifndef IN_RING3
984	rc = VINF_IOM_R3_IOPORT_READ;
985	#else
986	*pu32 = pThisCC->pDrv->cy;
987	#endif
988	}
989	break;
990	}
991
992	case SVGA_REG_MAX_WIDTH:
993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
994	*pu32 = pThis->svga.u32MaxWidth;
995	break;
996
997	case SVGA_REG_MAX_HEIGHT:
998	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
999	*pu32 = pThis->svga.u32MaxHeight;
1000	break;
1001
1002	case SVGA_REG_DEPTH:
1003	/* This returns the color depth of the current mode. */
1004	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1005	switch (pThis->svga.uBpp)
1006	{
1007	case 15:
1008	case 16:
1009	case 24:
1010	*pu32 = pThis->svga.uBpp;
1011	break;
1012
1013	default:
1014	case 32:
1015	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1016	break;
1017	}
1018	break;
1019
1020	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1021	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1022	*pu32 = pThis->svga.uHostBpp;
1023	break;
1024
1025	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1026	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1027	*pu32 = pThis->svga.uBpp;
1028	break;
1029
1030	case SVGA_REG_PSEUDOCOLOR:
1031	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1032	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1033	break;
1034
1035	case SVGA_REG_RED_MASK:
1036	case SVGA_REG_GREEN_MASK:
1037	case SVGA_REG_BLUE_MASK:
1038	{
1039	uint32_t uBpp;
1040
1041	if (pThis->svga.fEnabled)
1042	uBpp = pThis->svga.uBpp;
1043	else
1044	uBpp = pThis->svga.uHostBpp;
1045
1046	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1047	switch (uBpp)
1048	{
1049	case 8:
1050	u32RedMask = 0x07;
1051	u32GreenMask = 0x38;
1052	u32BlueMask = 0xc0;
1053	break;
1054
1055	case 15:
1056	u32RedMask = 0x0000001f;
1057	u32GreenMask = 0x000003e0;
1058	u32BlueMask = 0x00007c00;
1059	break;
1060
1061	case 16:
1062	u32RedMask = 0x0000001f;
1063	u32GreenMask = 0x000007e0;
1064	u32BlueMask = 0x0000f800;
1065	break;
1066
1067	case 24:
1068	case 32:
1069	default:
1070	u32RedMask = 0x00ff0000;
1071	u32GreenMask = 0x0000ff00;
1072	u32BlueMask = 0x000000ff;
1073	break;
1074	}
1075	switch (idxReg)
1076	{
1077	case SVGA_REG_RED_MASK:
1078	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1079	*pu32 = u32RedMask;
1080	break;
1081
1082	case SVGA_REG_GREEN_MASK:
1083	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1084	*pu32 = u32GreenMask;
1085	break;
1086
1087	case SVGA_REG_BLUE_MASK:
1088	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1089	*pu32 = u32BlueMask;
1090	break;
1091	}
1092	break;
1093	}
1094
1095	case SVGA_REG_BYTES_PER_LINE:
1096	{
1097	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1098	if ( pThis->svga.fEnabled
1099	&& pThis->svga.cbScanline)
1100	*pu32 = pThis->svga.cbScanline;
1101	else
1102	{
1103	#ifndef IN_RING3
1104	rc = VINF_IOM_R3_IOPORT_READ;
1105	#else
1106	*pu32 = pThisCC->pDrv->cbScanline;
1107	#endif
1108	}
1109	break;
1110	}
1111
1112	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1113	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1114	*pu32 = pThis->vram_size;
1115	break;
1116
1117	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1118	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1119	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1120	*pu32 = pThis->GCPhysVRAM;
1121	break;
1122
1123	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1124	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1125	/* Always zero in our case. */
1126	*pu32 = 0;
1127	break;
1128
1129	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1130	{
1131	#ifndef IN_RING3
1132	rc = VINF_IOM_R3_IOPORT_READ;
1133	#else
1134	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1135
1136	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1137	if ( pThis->svga.fEnabled
1138	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1139	{
1140	/* Hardware enabled; return real framebuffer size .*/
1141	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1142	}
1143	else
1144	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1145
1146	pu32 = RT_MIN(pThis->vram_size, pu32);
1147	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1148	#endif
1149	break;
1150	}
1151
1152	case SVGA_REG_CAPABILITIES:
1153	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1154	*pu32 = pThis->svga.u32RegCaps;
1155	break;
1156
1157	case SVGA_REG_MEM_START: /* FIFO start */
1158	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1159	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1160	*pu32 = pThis->svga.GCPhysFIFO;
1161	break;
1162
1163	case SVGA_REG_MEM_SIZE: /* FIFO size */
1164	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1165	*pu32 = pThis->svga.cbFIFO;
1166	break;
1167
1168	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1169	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1170	*pu32 = pThis->svga.fConfigured;
1171	break;
1172
1173	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1174	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1175	*pu32 = 0;
1176	break;
1177
1178	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1179	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1180	if (pThis->svga.fBusy)
1181	{
1182	#ifndef IN_RING3
1183	/* Go to ring-3 and halt the CPU. */
1184	rc = VINF_IOM_R3_IOPORT_READ;
1185	RT_NOREF(pDevIns);
1186	break;
1187	#else
1188	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1189	/* The guest is basically doing a HLT via the device here, but with
1190	a special wake up condition on FIFO completion. */
1191	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1192	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1193	PVM pVM = PDMDevHlpGetVM(pDevIns);
1194	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1195	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1196	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1197	if (pThis->svga.fBusy)
1198	{
1199	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1200	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1201	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1202	}
1203	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1204	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1205	# else
1206
1207	/* Delay the EMT a bit so the FIFO and others can get some work done.
1208	This used to be a crude 50 ms sleep. The current code tries to be
1209	more efficient, but the consept is still very crude. */
1210	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1211	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1212	RTThreadYield();
1213	if (pThis->svga.fBusy)
1214	{
1215	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1216
1217	if (pThis->svga.fBusy && cRefs == 1)
1218	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1219	if (pThis->svga.fBusy)
1220	{
1221	/** @todo If this code is going to stay, we need to call into the halt/wait
1222	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1223	* suffer when the guest is polling on a busy FIFO. */
1224	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns));
1225	if (cNsMaxWait >= RT_NS_100US)
1226	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1227	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1228	RT_MIN(cNsMaxWait, RT_NS_10MS));
1229	}
1230
1231	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1232	}
1233	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1234	# endif
1235	*pu32 = pThis->svga.fBusy != 0;
1236	#endif
1237	}
1238	else
1239	*pu32 = false;
1240	break;
1241
1242	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1243	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1244	*pu32 = pThis->svga.u32GuestId;
1245	break;
1246
1247	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1248	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1249	*pu32 = pThis->svga.cScratchRegion;
1250	break;
1251
1252	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1253	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1254	*pu32 = SVGA_FIFO_NUM_REGS;
1255	break;
1256
1257	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1258	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1259	*pu32 = pThis->svga.u32PitchLock;
1260	break;
1261
1262	case SVGA_REG_IRQMASK: /* Interrupt mask */
1263	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1264	*pu32 = pThis->svga.u32IrqMask;
1265	break;
1266
1267	/* See "Guest memory regions" below. */
1268	case SVGA_REG_GMR_ID:
1269	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1270	*pu32 = pThis->svga.u32CurrentGMRId;
1271	break;
1272
1273	case SVGA_REG_GMR_DESCRIPTOR:
1274	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1275	/* Write only */
1276	*pu32 = 0;
1277	break;
1278
1279	case SVGA_REG_GMR_MAX_IDS:
1280	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1281	*pu32 = pThis->svga.cGMR;
1282	break;
1283
1284	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1285	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1286	*pu32 = VMSVGA_MAX_GMR_PAGES;
1287	break;
1288
1289	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1290	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1291	*pu32 = pThis->svga.fTraces;
1292	break;
1293
1294	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1295	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1296	*pu32 = VMSVGA_MAX_GMR_PAGES;
1297	break;
1298
1299	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1300	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1301	*pu32 = VMSVGA_SURFACE_SIZE;
1302	break;
1303
1304	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1305	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1306	break;
1307
1308	/* Mouse cursor support. */
1309	case SVGA_REG_CURSOR_ID:
1310	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1311	*pu32 = pThis->svga.uCursorID;
1312	break;
1313
1314	case SVGA_REG_CURSOR_X:
1315	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1316	*pu32 = pThis->svga.uCursorX;
1317	break;
1318
1319	case SVGA_REG_CURSOR_Y:
1320	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1321	*pu32 = pThis->svga.uCursorY;
1322	break;
1323
1324	case SVGA_REG_CURSOR_ON:
1325	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1326	*pu32 = pThis->svga.uCursorOn;
1327	break;
1328
1329	/* Legacy multi-monitor support */
1330	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1331	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1332	*pu32 = 1;
1333	break;
1334
1335	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1336	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1337	*pu32 = 0;
1338	break;
1339
1340	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1342	*pu32 = 0;
1343	break;
1344
1345	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1347	*pu32 = 0;
1348	break;
1349
1350	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1352	*pu32 = 0;
1353	break;
1354
1355	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1357	*pu32 = pThis->svga.uWidth;
1358	break;
1359
1360	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1361	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1362	*pu32 = pThis->svga.uHeight;
1363	break;
1364
1365	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1367	/* We must return something sensible here otherwise the Linux driver
1368	will take a legacy code path without 3d support. This number also
1369	limits how many screens Linux guests will allow. */
1370	*pu32 = pThis->cMonitors;
1371	break;
1372
1373	default:
1374	{
1375	uint32_t offReg;
1376	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1377	{
1378	RT_UNTRUSTED_VALIDATED_FENCE();
1379	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1380	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1381	}
1382	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1383	{
1384	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1385	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1386	RT_UNTRUSTED_VALIDATED_FENCE();
1387	uint32_t u32 = pThis->last_palette[offReg / 3];
1388	switch (offReg % 3)
1389	{
1390	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1391	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1392	case 2: pu32 = u32 & 0xff; break; / blue */
1393	}
1394	}
1395	else
1396	{
1397	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1398	rc = VINF_IOM_R3_IOPORT_READ;
1399	#else
1400	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1401
1402	/* Do not assert. The guest might be reading all registers. */
1403	LogFunc(("Unknown reg=%#x\n", idxReg));
1404	#endif
1405	}
1406	break;
1407	}
1408	}
1409	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1410	return rc;
1411	}
1412
1413	#ifdef IN_RING3
1414	/**
1415	* Apply the current resolution settings to change the video mode.
1416	*
1417	* @returns VBox status code.
1418	* @param pThis The shared VGA state.
1419	* @param pThisCC The ring-3 VGA state.
1420	*/
1421	static int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1422	{
1423	/* Always do changemode on FIFO thread. */
1424	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1425
1426	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1427
1428	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1429
1430	if (pThis->svga.fGFBRegisters)
1431	{
1432	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1433	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1434	* deletes all screens other than screen #0, and redefines screen
1435	* #0 according to the specified mode. Drivers that use
1436	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1437	*/
1438
1439	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1440	pScreen->fDefined = true;
1441	pScreen->fModified = true;
1442	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1443	pScreen->idScreen = 0;
1444	pScreen->xOrigin = 0;
1445	pScreen->yOrigin = 0;
1446	pScreen->offVRAM = 0;
1447	pScreen->cbPitch = pThis->svga.cbScanline;
1448	pScreen->cWidth = pThis->svga.uWidth;
1449	pScreen->cHeight = pThis->svga.uHeight;
1450	pScreen->cBpp = pThis->svga.uBpp;
1451
1452	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1453	{
1454	/* Delete screen. */
1455	pScreen = &pSVGAState->aScreens[iScreen];
1456	if (pScreen->fDefined)
1457	{
1458	pScreen->fModified = true;
1459	pScreen->fDefined = false;
1460	}
1461	}
1462	}
1463	else
1464	{
1465	/* "If Screen Objects are supported, they can be used to fully
1466	* replace the functionality provided by the framebuffer registers
1467	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1468	*/
1469	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1470	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1471	pThis->svga.uBpp = pThis->svga.uHostBpp;
1472	}
1473
1474	vmsvgaR3VBVAResize(pThis, pThisCC);
1475
1476	/* Last stuff. For the VGA device screenshot. */
1477	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1478	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1479	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1480	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1481	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1482
1483	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1484	if ( pThis->svga.viewport.cx == 0
1485	&& pThis->svga.viewport.cy == 0)
1486	{
1487	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1488	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1489	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1490	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1491	pThis->svga.viewport.yLowWC = 0;
1492	}
1493
1494	return VINF_SUCCESS;
1495	}
1496
1497	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1498	{
1499	VBVACMDHDR cmd;
1500	cmd.x = (int16_t)(pScreen->xOrigin + x);
1501	cmd.y = (int16_t)(pScreen->yOrigin + y);
1502	cmd.w = (uint16_t)w;
1503	cmd.h = (uint16_t)h;
1504
1505	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1506	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1507	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1508	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1509
1510	return VINF_SUCCESS;
1511	}
1512
1513	#endif /* IN_RING3 */
1514	#if defined(IN_RING0) \|\| defined(IN_RING3)
1515
1516	/**
1517	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1518	*
1519	* @param pThis The shared VGA/VMSVGA instance data.
1520	* @param pThisCC The VGA/VMSVGA state for the current context.
1521	* @param fState The busy state.
1522	*/
1523	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1524	{
1525	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1526
1527	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1528	{
1529	/* Race / unfortunately scheduling. Highly unlikly. */
1530	uint32_t cLoops = 64;
1531	do
1532	{
1533	ASMNopPause();
1534	fState = (pThis->svga.fBusy != 0);
1535	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1536	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1537	}
1538	}
1539
1540
1541	/**
1542	* Update the scanline pitch in response to the guest changing mode
1543	* width/bpp.
1544	*
1545	* @param pThis The shared VGA/VMSVGA state.
1546	* @param pThisCC The VGA/VMSVGA state for the current context.
1547	*/
1548	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1549	{
1550	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1551	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1552	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1553	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1554
1555	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1556	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1557	* location but it has a different meaning.
1558	*/
1559	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1560	uFifoPitchLock = 0;
1561
1562	/* Sanitize values. */
1563	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1564	uFifoPitchLock = 0;
1565	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1566	uRegPitchLock = 0;
1567
1568	/* Prefer the register value to the FIFO value.*/
1569	if (uRegPitchLock)
1570	pThis->svga.cbScanline = uRegPitchLock;
1571	else if (uFifoPitchLock)
1572	pThis->svga.cbScanline = uFifoPitchLock;
1573	else
1574	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1575
1576	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1577	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1578	}
1579
1580	#endif /* IN_RING0 \|\| IN_RING3 */
1581
1582	#ifdef IN_RING3
1583
1584	/**
1585	* Sends cursor position and visibility information from legacy
1586	* SVGA registers to the front-end.
1587	*/
1588	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1589	{
1590	/*
1591	* Writing the X/Y/ID registers does not trigger changes; only writing the
1592	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1593	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1594	* register if they don't have to.
1595	*/
1596	uint32_t x, y, idScreen;
1597	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1598
1599	x = pThis->svga.uCursorX;
1600	y = pThis->svga.uCursorY;
1601	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1602
1603	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1604	* were extended as follows:
1605	*
1606	* SVGA_CURSOR_ON_HIDE 0
1607	* SVGA_CURSOR_ON_SHOW 1
1608	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1609	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1610	*
1611	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1612	* distinguish between the non-zero values but still remember them.
1613	*/
1614	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1615	{
1616	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1617	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1618	}
1619	pThis->svga.uCursorOn = uCursorOn;
1620	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1621	}
1622
1623
1624	/**
1625	* Copy a rectangle of pixels within guest VRAM.
1626	*/
1627	static void vmsvgaR3RectCopy(PVGASTATECC pThisCC, VMSVGASCREENOBJECT const *pScreen, uint32_t srcX, uint32_t srcY,
1628	uint32_t dstX, uint32_t dstY, uint32_t width, uint32_t height, unsigned cbFrameBuffer)
1629	{
1630	if (!width \|\| !height)
1631	return; /* Nothing to do, don't even bother. */
1632
1633	/*
1634	* The guest VRAM (aka GFB) is considered to be a bitmap in the format
1635	* corresponding to the current display mode.
1636	*/
1637	uint32_t const cbPixel = RT_ALIGN(pScreen->cBpp, 8) / 8;
1638	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch : width * cbPixel;
1639	uint8_t const *pSrc;
1640	uint8_t *pDst;
1641	unsigned const cbRectWidth = width * cbPixel;
1642	unsigned uMaxOffset;
1643
1644	uMaxOffset = (RT_MAX(srcY, dstY) + height) * cbScanline + (RT_MAX(srcX, dstX) + width) * cbPixel;
1645	if (uMaxOffset >= cbFrameBuffer)
1646	{
1647	Log(("Max offset (%u) too big for framebuffer (%u bytes), ignoring!\n", uMaxOffset, cbFrameBuffer));
1648	return; /* Just don't listen to a bad guest. */
1649	}
1650
1651	pSrc = pDst = pThisCC->pbVRam;
1652	pSrc += srcY * cbScanline + srcX * cbPixel;
1653	pDst += dstY * cbScanline + dstX * cbPixel;
1654
1655	if (srcY >= dstY)
1656	{
1657	/* Source below destination, copy top to bottom. */
1658	for (; height > 0; height--)
1659	{
1660	memmove(pDst, pSrc, cbRectWidth);
1661	pSrc += cbScanline;
1662	pDst += cbScanline;
1663	}
1664	}
1665	else
1666	{
1667	/* Source above destination, copy bottom to top. */
1668	pSrc += cbScanline * (height - 1);
1669	pDst += cbScanline * (height - 1);
1670	for (; height > 0; height--)
1671	{
1672	memmove(pDst, pSrc, cbRectWidth);
1673	pSrc -= cbScanline;
1674	pDst -= cbScanline;
1675	}
1676	}
1677	}
1678
1679	#endif /* IN_RING3 */
1680
1681
1682	/**
1683	* Write port register
1684	*
1685	* @returns Strict VBox status code.
1686	* @param pDevIns The device instance.
1687	* @param pThis The shared VGA/VMSVGA state.
1688	* @param pThisCC The VGA/VMSVGA state for the current context.
1689	* @param u32 Value to write
1690	*/
1691	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1692	{
1693	#ifdef IN_RING3
1694	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1695	#endif
1696	VBOXSTRICTRC rc = VINF_SUCCESS;
1697	RT_NOREF(pThisCC);
1698
1699	/* Rough index register validation. */
1700	uint32_t idxReg = pThis->svga.u32IndexReg;
1701	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1702	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1703	VINF_IOM_R3_IOPORT_WRITE);
1704	#else
1705	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1706	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1707	VINF_SUCCESS);
1708	#endif
1709	RT_UNTRUSTED_VALIDATED_FENCE();
1710
1711	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1712	if ( idxReg >= SVGA_REG_CAPABILITIES
1713	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1714	{
1715	idxReg += SVGA_PALETTE_BASE - SVGA_REG_CAPABILITIES;
1716	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1717	}
1718	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1719	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1720	switch (idxReg)
1721	{
1722	case SVGA_REG_WIDTH:
1723	case SVGA_REG_HEIGHT:
1724	case SVGA_REG_PITCHLOCK:
1725	case SVGA_REG_BITS_PER_PIXEL:
1726	pThis->svga.fGFBRegisters = true;
1727	break;
1728	default:
1729	break;
1730	}
1731
1732	switch (idxReg)
1733	{
1734	case SVGA_REG_ID:
1735	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1736	if ( u32 == SVGA_ID_0
1737	\|\| u32 == SVGA_ID_1
1738	\|\| u32 == SVGA_ID_2)
1739	pThis->svga.u32SVGAId = u32;
1740	else
1741	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1742	break;
1743
1744	case SVGA_REG_ENABLE:
1745	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1746	#ifdef IN_RING3
1747	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1748	&& pThis->svga.fEnabled == false)
1749	{
1750	/* Make a backup copy of the first 512kb in order to save font data etc. */
1751	/** @todo should probably swap here, rather than copy + zero */
1752	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1753	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1754	}
1755
1756	pThis->svga.fEnabled = u32;
1757	if (pThis->svga.fEnabled)
1758	{
1759	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1760	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1761	{
1762	/* Keep the current mode. */
1763	pThis->svga.uWidth = pThisCC->pDrv->cx;
1764	pThis->svga.uHeight = pThisCC->pDrv->cy;
1765	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1766	}
1767
1768	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1769	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1770	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1771	# ifdef LOG_ENABLED
1772	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1773	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1774	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1775	# endif
1776
1777	/* Disable or enable dirty page tracking according to the current fTraces value. */
1778	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1779
1780	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1781	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1782	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1783
1784	/* Make the cursor visible again as needed. */
1785	if (pSVGAState->Cursor.fActive)
1786	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1787	}
1788	else
1789	{
1790	/* Make sure the cursor is off. */
1791	if (pSVGAState->Cursor.fActive)
1792	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1793
1794	/* Restore the text mode backup. */
1795	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1796
1797	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1798
1799	/* Enable dirty page tracking again when going into legacy mode. */
1800	vmsvgaR3SetTraces(pDevIns, pThis, true);
1801
1802	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1803	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1804	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1805
1806	/* Clear the pitch lock. */
1807	pThis->svga.u32PitchLock = 0;
1808	}
1809	#else /* !IN_RING3 */
1810	rc = VINF_IOM_R3_IOPORT_WRITE;
1811	#endif /* !IN_RING3 */
1812	break;
1813
1814	case SVGA_REG_WIDTH:
1815	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1816	if (pThis->svga.uWidth != u32)
1817	{
1818	#if defined(IN_RING3) \|\| defined(IN_RING0)
1819	pThis->svga.uWidth = u32;
1820	vmsvgaHCUpdatePitch(pThis, pThisCC);
1821	if (pThis->svga.fEnabled)
1822	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1823	#else
1824	rc = VINF_IOM_R3_IOPORT_WRITE;
1825	#endif
1826	}
1827	/* else: nop */
1828	break;
1829
1830	case SVGA_REG_HEIGHT:
1831	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1832	if (pThis->svga.uHeight != u32)
1833	{
1834	pThis->svga.uHeight = u32;
1835	if (pThis->svga.fEnabled)
1836	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1837	}
1838	/* else: nop */
1839	break;
1840
1841	case SVGA_REG_DEPTH:
1842	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1843	/** @todo read-only?? */
1844	break;
1845
1846	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1847	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1848	if (pThis->svga.uBpp != u32)
1849	{
1850	#if defined(IN_RING3) \|\| defined(IN_RING0)
1851	pThis->svga.uBpp = u32;
1852	vmsvgaHCUpdatePitch(pThis, pThisCC);
1853	if (pThis->svga.fEnabled)
1854	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1855	#else
1856	rc = VINF_IOM_R3_IOPORT_WRITE;
1857	#endif
1858	}
1859	/* else: nop */
1860	break;
1861
1862	case SVGA_REG_PSEUDOCOLOR:
1863	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1864	break;
1865
1866	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1867	#ifdef IN_RING3
1868	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1869	pThis->svga.fConfigured = u32;
1870	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1871	if (!pThis->svga.fConfigured)
1872	pThis->svga.fTraces = true;
1873	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1874	#else
1875	rc = VINF_IOM_R3_IOPORT_WRITE;
1876	#endif
1877	break;
1878
1879	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1880	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1881	if ( pThis->svga.fEnabled
1882	&& pThis->svga.fConfigured)
1883	{
1884	#if defined(IN_RING3) \|\| defined(IN_RING0)
1885	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1886	/*
1887	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1888	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1889	*/
1890	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1891	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1892	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1893
1894	/* Kick the FIFO thread to start processing commands again. */
1895	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1896	#else
1897	rc = VINF_IOM_R3_IOPORT_WRITE;
1898	#endif
1899	}
1900	/* else nothing to do. */
1901	else
1902	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1903
1904	break;
1905
1906	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1907	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1908	break;
1909
1910	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1911	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1912	pThis->svga.u32GuestId = u32;
1913	break;
1914
1915	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1916	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1917	pThis->svga.u32PitchLock = u32;
1918	/* Should this also update the FIFO pitch lock? Unclear. */
1919	break;
1920
1921	case SVGA_REG_IRQMASK: /* Interrupt mask */
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1923	pThis->svga.u32IrqMask = u32;
1924
1925	/* Irq pending after the above change? */
1926	if (pThis->svga.u32IrqStatus & u32)
1927	{
1928	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
1929	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
1930	}
1931	else
1932	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
1933	break;
1934
1935	/* Mouse cursor support */
1936	case SVGA_REG_CURSOR_ID:
1937	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
1938	pThis->svga.uCursorID = u32;
1939	break;
1940
1941	case SVGA_REG_CURSOR_X:
1942	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
1943	pThis->svga.uCursorX = u32;
1944	break;
1945
1946	case SVGA_REG_CURSOR_Y:
1947	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
1948	pThis->svga.uCursorY = u32;
1949	break;
1950
1951	case SVGA_REG_CURSOR_ON:
1952	#ifdef IN_RING3
1953	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
1954	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
1955	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
1956	#else
1957	rc = VINF_IOM_R3_IOPORT_WRITE;
1958	#endif
1959	break;
1960
1961	/* Legacy multi-monitor support */
1962	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1963	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
1964	break;
1965	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1966	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
1967	break;
1968	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1969	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
1970	break;
1971	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1972	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
1973	break;
1974	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1975	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
1976	break;
1977	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1978	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
1979	break;
1980	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1981	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
1982	break;
1983	#ifdef VBOX_WITH_VMSVGA3D
1984	/* See "Guest memory regions" below. */
1985	case SVGA_REG_GMR_ID:
1986	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
1987	pThis->svga.u32CurrentGMRId = u32;
1988	break;
1989
1990	case SVGA_REG_GMR_DESCRIPTOR:
1991	# ifndef IN_RING3
1992	rc = VINF_IOM_R3_IOPORT_WRITE;
1993	break;
1994	# else /* IN_RING3 */
1995	{
1996	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
1997
1998	/* Validate current GMR id. */
1999	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2000	AssertBreak(idGMR < pThis->svga.cGMR);
2001	RT_UNTRUSTED_VALIDATED_FENCE();
2002
2003	/* Free the old GMR if present. */
2004	vmsvgaR3GmrFree(pThisCC, idGMR);
2005
2006	/* Just undefine the GMR? */
2007	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2008	if (GCPhys == 0)
2009	{
2010	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2011	break;
2012	}
2013
2014
2015	/* Never cross a page boundary automatically. */
2016	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2017	uint32_t cPagesTotal = 0;
2018	uint32_t iDesc = 0;
2019	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2020	uint32_t cLoops = 0;
2021	RTGCPHYS GCPhysBase = GCPhys;
2022	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2023	{
2024	/* Read descriptor. */
2025	SVGAGuestMemDescriptor desc;
2026	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2027	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2028
2029	if (desc.numPages != 0)
2030	{
2031	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2032	cPagesTotal += desc.numPages;
2033	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2034
2035	if ((iDesc & 15) == 0)
2036	{
2037	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2038	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2039	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2040	}
2041
2042	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2043	paDescs[iDesc++].numPages = desc.numPages;
2044
2045	/* Continue with the next descriptor. */
2046	GCPhys += sizeof(desc);
2047	}
2048	else if (desc.ppn == 0)
2049	break; /* terminator */
2050	else /* Pointer to the next physical page of descriptors. */
2051	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2052
2053	cLoops++;
2054	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2055	}
2056
2057	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2058	if (RT_SUCCESS(rc))
2059	{
2060	/* Commit the GMR. */
2061	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2062	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2063	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2064	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2065	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2066	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2067	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2068	}
2069	else
2070	{
2071	RTMemFree(paDescs);
2072	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2073	}
2074	break;
2075	}
2076	# endif /* IN_RING3 */
2077	#endif // VBOX_WITH_VMSVGA3D
2078
2079	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2080	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2081	if (pThis->svga.fTraces == u32)
2082	break; /* nothing to do */
2083
2084	#ifdef IN_RING3
2085	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2086	#else
2087	rc = VINF_IOM_R3_IOPORT_WRITE;
2088	#endif
2089	break;
2090
2091	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2092	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2093	break;
2094
2095	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2096	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2097	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2098	break;
2099
2100	case SVGA_REG_FB_START:
2101	case SVGA_REG_MEM_START:
2102	case SVGA_REG_HOST_BITS_PER_PIXEL:
2103	case SVGA_REG_MAX_WIDTH:
2104	case SVGA_REG_MAX_HEIGHT:
2105	case SVGA_REG_VRAM_SIZE:
2106	case SVGA_REG_FB_SIZE:
2107	case SVGA_REG_CAPABILITIES:
2108	case SVGA_REG_MEM_SIZE:
2109	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2110	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2111	case SVGA_REG_BYTES_PER_LINE:
2112	case SVGA_REG_FB_OFFSET:
2113	case SVGA_REG_RED_MASK:
2114	case SVGA_REG_GREEN_MASK:
2115	case SVGA_REG_BLUE_MASK:
2116	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2117	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2118	case SVGA_REG_GMR_MAX_IDS:
2119	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2120	/* Read only - ignore. */
2121	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2122	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2123	break;
2124
2125	default:
2126	{
2127	uint32_t offReg;
2128	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2129	{
2130	RT_UNTRUSTED_VALIDATED_FENCE();
2131	pThis->svga.au32ScratchRegion[offReg] = u32;
2132	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2133	}
2134	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2135	{
2136	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2137	Btw, see rgb_to_pixel32. */
2138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2139	u32 &= 0xff;
2140	RT_UNTRUSTED_VALIDATED_FENCE();
2141	uint32_t uRgb = pThis->last_palette[offReg / 3];
2142	switch (offReg % 3)
2143	{
2144	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2145	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2146	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2147	}
2148	pThis->last_palette[offReg / 3] = uRgb;
2149	}
2150	else
2151	{
2152	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2153	rc = VINF_IOM_R3_IOPORT_WRITE;
2154	#else
2155	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2156	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2157	#endif
2158	}
2159	break;
2160	}
2161	}
2162	return rc;
2163	}
2164
2165	/**
2166	* @callback_method_impl{FNIOMIOPORTNEWIN}
2167	*/
2168	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2169	{
2170	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2171	RT_NOREF_PV(pvUser);
2172
2173	/* Only dword accesses. */
2174	if (cb == 4)
2175	{
2176	switch (offPort)
2177	{
2178	case SVGA_INDEX_PORT:
2179	*pu32 = pThis->svga.u32IndexReg;
2180	break;
2181
2182	case SVGA_VALUE_PORT:
2183	return vmsvgaReadPort(pDevIns, pThis, pu32);
2184
2185	case SVGA_BIOS_PORT:
2186	Log(("Ignoring BIOS port read\n"));
2187	*pu32 = 0;
2188	break;
2189
2190	case SVGA_IRQSTATUS_PORT:
2191	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2192	*pu32 = pThis->svga.u32IrqStatus;
2193	break;
2194
2195	default:
2196	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2197	*pu32 = UINT32_MAX;
2198	break;
2199	}
2200	}
2201	else
2202	{
2203	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2204	*pu32 = UINT32_MAX;
2205	}
2206	return VINF_SUCCESS;
2207	}
2208
2209	/**
2210	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2211	*/
2212	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2213	{
2214	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2215	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2216	RT_NOREF_PV(pvUser);
2217
2218	/* Only dword accesses. */
2219	if (cb == 4)
2220	switch (offPort)
2221	{
2222	case SVGA_INDEX_PORT:
2223	pThis->svga.u32IndexReg = u32;
2224	break;
2225
2226	case SVGA_VALUE_PORT:
2227	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2228
2229	case SVGA_BIOS_PORT:
2230	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2231	break;
2232
2233	case SVGA_IRQSTATUS_PORT:
2234	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2235	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2236	/* Clear the irq in case all events have been cleared. */
2237	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2238	{
2239	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2240	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2241	}
2242	break;
2243
2244	default:
2245	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2246	break;
2247	}
2248	else
2249	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2250
2251	return VINF_SUCCESS;
2252	}
2253
2254	#ifdef IN_RING3
2255
2256	# ifdef DEBUG_FIFO_ACCESS
2257	/**
2258	* Handle FIFO memory access.
2259	* @returns VBox status code.
2260	* @param pVM VM handle.
2261	* @param pThis The shared VGA/VMSVGA instance data.
2262	* @param GCPhys The access physical address.
2263	* @param fWriteAccess Read or write access
2264	*/
2265	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2266	{
2267	RT_NOREF(pVM);
2268	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2269	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2270
2271	switch (GCPhysOffset >> 2)
2272	{
2273	case SVGA_FIFO_MIN:
2274	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2275	break;
2276	case SVGA_FIFO_MAX:
2277	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2278	break;
2279	case SVGA_FIFO_NEXT_CMD:
2280	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2281	break;
2282	case SVGA_FIFO_STOP:
2283	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2284	break;
2285	case SVGA_FIFO_CAPABILITIES:
2286	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2287	break;
2288	case SVGA_FIFO_FLAGS:
2289	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2290	break;
2291	case SVGA_FIFO_FENCE:
2292	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2293	break;
2294	case SVGA_FIFO_3D_HWVERSION:
2295	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2296	break;
2297	case SVGA_FIFO_PITCHLOCK:
2298	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2299	break;
2300	case SVGA_FIFO_CURSOR_ON:
2301	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2302	break;
2303	case SVGA_FIFO_CURSOR_X:
2304	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2305	break;
2306	case SVGA_FIFO_CURSOR_Y:
2307	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2308	break;
2309	case SVGA_FIFO_CURSOR_COUNT:
2310	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2311	break;
2312	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2313	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2314	break;
2315	case SVGA_FIFO_RESERVED:
2316	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2317	break;
2318	case SVGA_FIFO_CURSOR_SCREEN_ID:
2319	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2320	break;
2321	case SVGA_FIFO_DEAD:
2322	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2323	break;
2324	case SVGA_FIFO_3D_HWVERSION_REVISED:
2325	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2326	break;
2327	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2328	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2329	break;
2330	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2331	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2332	break;
2333	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2334	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2335	break;
2336	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2337	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2338	break;
2339	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2340	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2341	break;
2342	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2343	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2344	break;
2345	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2346	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2347	break;
2348	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2349	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2350	break;
2351	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2352	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2353	break;
2354	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2355	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2356	break;
2357	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2358	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2359	break;
2360	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2361	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2362	break;
2363	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2364	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2365	break;
2366	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2367	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2368	break;
2369	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2370	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2371	break;
2372	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2373	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2374	break;
2375	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2376	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2377	break;
2378	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2379	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2380	break;
2381	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2382	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2383	break;
2384	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2385	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2386	break;
2387	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2388	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2389	break;
2390	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2391	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2392	break;
2393	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2394	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2395	break;
2396	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2397	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2398	break;
2399	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2400	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2401	break;
2402	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2403	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2404	break;
2405	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2406	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2407	break;
2408	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2409	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2410	break;
2411	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2412	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2413	break;
2414	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2415	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2416	break;
2417	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2418	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2419	break;
2420	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2421	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2422	break;
2423	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2424	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2425	break;
2426	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2427	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2428	break;
2429	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2430	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2431	break;
2432	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2433	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2434	break;
2435	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2436	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2437	break;
2438	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2439	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2440	break;
2441	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2442	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2443	break;
2444	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2445	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2446	break;
2447	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2448	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2449	break;
2450	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2451	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2452	break;
2453	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2454	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2455	break;
2456	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2457	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2458	break;
2459	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2460	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2461	break;
2462	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2463	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2464	break;
2465	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2466	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2467	break;
2468	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2469	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2470	break;
2471	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2472	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2473	break;
2474	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2475	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2476	break;
2477	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2478	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2479	break;
2480	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2481	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2482	break;
2483	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2484	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2485	break;
2486	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2487	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2488	break;
2489	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2490	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2491	break;
2492	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2493	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2494	break;
2495	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2496	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2497	break;
2498	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2499	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2500	break;
2501	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2502	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2503	break;
2504	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2505	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2506	break;
2507	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2508	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2509	break;
2510	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2511	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2512	break;
2513	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2514	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2515	break;
2516	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2517	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2518	break;
2519	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2520	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2521	break;
2522	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2523	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2524	break;
2525	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2526	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2527	break;
2528	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2529	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2530	break;
2531	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2532	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2533	break;
2534	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
2535	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2536	break;
2537	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
2538	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2539	break;
2540	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
2541	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2542	break;
2543	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
2544	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2545	break;
2546	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2547	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2548	break;
2549	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2550	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2551	break;
2552	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
2553	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2554	break;
2555	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2556	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2557	break;
2558	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2559	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2560	break;
2561	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2562	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2563	break;
2564	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2565	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2566	break;
2567	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2568	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2569	break;
2570	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2571	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2572	break;
2573	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2574	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2575	break;
2576	case SVGA_FIFO_3D_CAPS_LAST:
2577	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2578	break;
2579	case SVGA_FIFO_GUEST_3D_HWVERSION:
2580	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2581	break;
2582	case SVGA_FIFO_FENCE_GOAL:
2583	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2584	break;
2585	case SVGA_FIFO_BUSY:
2586	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2587	break;
2588	default:
2589	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2590	break;
2591	}
2592
2593	return VINF_EM_RAW_EMULATE_INSTR;
2594	}
2595	# endif /* DEBUG_FIFO_ACCESS */
2596
2597	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2598	/**
2599	* HC access handler for the FIFO.
2600	*
2601	* @returns VINF_SUCCESS if the handler have carried out the operation.
2602	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2603	* @param pVM VM Handle.
2604	* @param pVCpu The cross context CPU structure for the calling EMT.
2605	* @param GCPhys The physical address the guest is writing to.
2606	* @param pvPhys The HC mapping of that address.
2607	* @param pvBuf What the guest is reading/writing.
2608	* @param cbBuf How much it's reading/writing.
2609	* @param enmAccessType The access type.
2610	* @param enmOrigin Who is making the access.
2611	* @param pvUser User argument.
2612	*/
2613	static DECLCALLBACK(VBOXSTRICTRC)
2614	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2615	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2616	{
2617	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2618	PVGASTATE pThis = (PVGASTATE)pvUser;
2619	AssertPtr(pThis);
2620
2621	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2622	/*
2623	* Wake up the FIFO thread as it might have work to do now.
2624	*/
2625	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2626	AssertLogRelRC(rc);
2627	# endif
2628
2629	# ifdef DEBUG_FIFO_ACCESS
2630	/*
2631	* When in debug-fifo-access mode, we do not disable the access handler,
2632	* but leave it on as we wish to catch all access.
2633	*/
2634	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2635	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2636	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2637	/*
2638	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2639	*/
2640	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2641	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2642	# endif
2643	if (RT_SUCCESS(rc))
2644	return VINF_PGM_HANDLER_DO_DEFAULT;
2645	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2646	return rc;
2647	}
2648	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2649
2650	#endif /* IN_RING3 */
2651
2652	#ifdef DEBUG_GMR_ACCESS
2653	# ifdef IN_RING3
2654
2655	/**
2656	* HC access handler for the FIFO.
2657	*
2658	* @returns VINF_SUCCESS if the handler have carried out the operation.
2659	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2660	* @param pVM VM Handle.
2661	* @param pVCpu The cross context CPU structure for the calling EMT.
2662	* @param GCPhys The physical address the guest is writing to.
2663	* @param pvPhys The HC mapping of that address.
2664	* @param pvBuf What the guest is reading/writing.
2665	* @param cbBuf How much it's reading/writing.
2666	* @param enmAccessType The access type.
2667	* @param enmOrigin Who is making the access.
2668	* @param pvUser User argument.
2669	*/
2670	static DECLCALLBACK(VBOXSTRICTRC)
2671	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2672	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2673	{
2674	PVGASTATE pThis = (PVGASTATE)pvUser;
2675	Assert(pThis);
2676	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2677	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2678
2679	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2680
2681	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2682	{
2683	PGMR pGMR = &pSVGAState->paGMR[i];
2684
2685	if (pGMR->numDescriptors)
2686	{
2687	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2688	{
2689	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2690	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2691	{
2692	/*
2693	* Turn off the write handler for this particular page and make it R/W.
2694	* Then return telling the caller to restart the guest instruction.
2695	*/
2696	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2697	AssertRC(rc);
2698	return VINF_PGM_HANDLER_DO_DEFAULT;
2699	}
2700	}
2701	}
2702	}
2703
2704	return VINF_PGM_HANDLER_DO_DEFAULT;
2705	}
2706
2707	/** Callback handler for VMR3ReqCallWaitU */
2708	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2709	{
2710	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2711	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2712	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2713	int rc;
2714
2715	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2716	{
2717	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2718	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2719	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2720	AssertRC(rc);
2721	}
2722	return VINF_SUCCESS;
2723	}
2724
2725	/** Callback handler for VMR3ReqCallWaitU */
2726	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2727	{
2728	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2729	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2730	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2731
2732	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2733	{
2734	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2735	AssertRC(rc);
2736	}
2737	return VINF_SUCCESS;
2738	}
2739
2740	/** Callback handler for VMR3ReqCallWaitU */
2741	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2742	{
2743	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2744
2745	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2746	{
2747	PGMR pGMR = &pSVGAState->paGMR[i];
2748
2749	if (pGMR->numDescriptors)
2750	{
2751	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2752	{
2753	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2754	AssertRC(rc);
2755	}
2756	}
2757	}
2758	return VINF_SUCCESS;
2759	}
2760
2761	# endif /* IN_RING3 */
2762	#endif /* DEBUG_GMR_ACCESS */
2763
2764	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2765
2766	#ifdef IN_RING3
2767
2768
2769	/**
2770	* Common worker for changing the pointer shape.
2771	*
2772	* @param pThisCC The VGA/VMSVGA state for ring-3.
2773	* @param pSVGAState The VMSVGA ring-3 instance data.
2774	* @param fAlpha Whether there is alpha or not.
2775	* @param xHot Hotspot x coordinate.
2776	* @param yHot Hotspot y coordinate.
2777	* @param cx Width.
2778	* @param cy Height.
2779	* @param pbData Heap copy of the cursor data. Consumed.
2780	* @param cbData The size of the data.
2781	*/
2782	static void vmsvgaR3InstallNewCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, bool fAlpha,
2783	uint32_t xHot, uint32_t yHot, uint32_t cx, uint32_t cy, uint8_t *pbData, uint32_t cbData)
2784	{
2785	LogRel2(("vmsvgaR3InstallNewCursor: cx=%d cy=%d xHot=%d yHot=%d fAlpha=%d cbData=%#x\n", cx, cy, xHot, yHot, fAlpha, cbData));
2786	# ifdef LOG_ENABLED
2787	if (LogIs2Enabled())
2788	{
2789	uint32_t cbAndLine = RT_ALIGN(cx, 8) / 8;
2790	if (!fAlpha)
2791	{
2792	Log2(("VMSVGA Cursor AND mask (%d,%d):\n", cx, cy));
2793	for (uint32_t y = 0; y < cy; y++)
2794	{
2795	Log2(("%3u:", y));
2796	uint8_t const pbLine = &pbData[y cbAndLine];
2797	for (uint32_t x = 0; x < cx; x += 8)
2798	{
2799	uint8_t b = pbLine[x / 8];
2800	char szByte[12];
2801	szByte[0] = b & 0x80 ? '' : ' '; / most significant bit first */
2802	szByte[1] = b & 0x40 ? '*' : ' ';
2803	szByte[2] = b & 0x20 ? '*' : ' ';
2804	szByte[3] = b & 0x10 ? '*' : ' ';
2805	szByte[4] = b & 0x08 ? '*' : ' ';
2806	szByte[5] = b & 0x04 ? '*' : ' ';
2807	szByte[6] = b & 0x02 ? '*' : ' ';
2808	szByte[7] = b & 0x01 ? '*' : ' ';
2809	szByte[8] = '\0';
2810	Log2(("%s", szByte));
2811	}
2812	Log2(("\n"));
2813	}
2814	}
2815
2816	Log2(("VMSVGA Cursor XOR mask (%d,%d):\n", cx, cy));
2817	uint32_t const pu32Xor = (uint32_t const )&pbData[RT_ALIGN_32(cbAndLine * cy, 4)];
2818	for (uint32_t y = 0; y < cy; y++)
2819	{
2820	Log2(("%3u:", y));
2821	uint32_t const pu32Line = &pu32Xor[y cx];
2822	for (uint32_t x = 0; x < cx; x++)
2823	Log2((" %08x", pu32Line[x]));
2824	Log2(("\n"));
2825	}
2826	}
2827	# endif
2828
2829	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, fAlpha, xHot, yHot, cx, cy, pbData);
2830	AssertRC(rc);
2831
2832	if (pSVGAState->Cursor.fActive)
2833	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
2834
2835	pSVGAState->Cursor.fActive = true;
2836	pSVGAState->Cursor.xHotspot = xHot;
2837	pSVGAState->Cursor.yHotspot = yHot;
2838	pSVGAState->Cursor.width = cx;
2839	pSVGAState->Cursor.height = cy;
2840	pSVGAState->Cursor.cbData = cbData;
2841	pSVGAState->Cursor.pData = pbData;
2842	}
2843
2844
2845	/**
2846	* Handles the SVGA_CMD_DEFINE_CURSOR command.
2847	*
2848	* @param pThis The shared VGA/VMSVGA state.
2849	* @param pThisCC The VGA/VMSVGA state for ring-3.
2850	* @param pSVGAState The VMSVGA ring-3 instance data.
2851	* @param pCursor The cursor.
2852	* @param pbSrcAndMask The AND mask.
2853	* @param cbSrcAndLine The scanline length of the AND mask.
2854	* @param pbSrcXorMask The XOR mask.
2855	* @param cbSrcXorLine The scanline length of the XOR mask.
2856	*/
2857	static void vmsvgaR3CmdDefineCursor(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState,
2858	SVGAFifoCmdDefineCursor const *pCursor,
2859	uint8_t const *pbSrcAndMask, uint32_t cbSrcAndLine,
2860	uint8_t const *pbSrcXorMask, uint32_t cbSrcXorLine)
2861	{
2862	uint32_t const cx = pCursor->width;
2863	uint32_t const cy = pCursor->height;
2864
2865	/*
2866	* Convert the input to 1-bit AND mask and a 32-bit BRGA XOR mask.
2867	* The AND data uses 8-bit aligned scanlines.
2868	* The XOR data must be starting on a 32-bit boundrary.
2869	*/
2870	uint32_t cbDstAndLine = RT_ALIGN_32(cx, 8) / 8;
2871	uint32_t cbDstAndMask = cbDstAndLine * cy;
2872	uint32_t cbDstXorMask = cx * sizeof(uint32_t) * cy;
2873	uint32_t cbCopy = RT_ALIGN_32(cbDstAndMask, 4) + cbDstXorMask;
2874
2875	uint8_t pbCopy = (uint8_t )RTMemAlloc(cbCopy);
2876	AssertReturnVoid(pbCopy);
2877
2878	/* Convert the AND mask. */
2879	uint8_t *pbDst = pbCopy;
2880	uint8_t const *pbSrc = pbSrcAndMask;
2881	switch (pCursor->andMaskDepth)
2882	{
2883	case 1:
2884	if (cbSrcAndLine == cbDstAndLine)
2885	memcpy(pbDst, pbSrc, cbSrcAndLine * cy);
2886	else
2887	{
2888	Assert(cbSrcAndLine > cbDstAndLine); /* lines are dword alined in source, but only byte in destination. */
2889	for (uint32_t y = 0; y < cy; y++)
2890	{
2891	memcpy(pbDst, pbSrc, cbDstAndLine);
2892	pbDst += cbDstAndLine;
2893	pbSrc += cbSrcAndLine;
2894	}
2895	}
2896	break;
2897	/* Should take the XOR mask into account for the multi-bit AND mask. */
2898	case 8:
2899	for (uint32_t y = 0; y < cy; y++)
2900	{
2901	for (uint32_t x = 0; x < cx; )
2902	{
2903	uint8_t bDst = 0;
2904	uint8_t fBit = 0x80;
2905	do
2906	{
2907	uintptr_t const idxPal = pbSrc[x] * 3;
2908	if ((( pThis->last_palette[idxPal]
2909	\| (pThis->last_palette[idxPal] >> 8)
2910	\| (pThis->last_palette[idxPal] >> 16)) & 0xff) > 0xfc)
2911	bDst \|= fBit;
2912	fBit >>= 1;
2913	x++;
2914	} while (x < cx && (x & 7));
2915	pbDst[(x - 1) / 8] = bDst;
2916	}
2917	pbDst += cbDstAndLine;
2918	pbSrc += cbSrcAndLine;
2919	}
2920	break;
2921	case 15:
2922	for (uint32_t y = 0; y < cy; y++)
2923	{
2924	for (uint32_t x = 0; x < cx; )
2925	{
2926	uint8_t bDst = 0;
2927	uint8_t fBit = 0x80;
2928	do
2929	{
2930	if ((pbSrc[x * 2] \| (pbSrc[x * 2 + 1] & 0x7f)) >= 0xfc)
2931	bDst \|= fBit;
2932	fBit >>= 1;
2933	x++;
2934	} while (x < cx && (x & 7));
2935	pbDst[(x - 1) / 8] = bDst;
2936	}
2937	pbDst += cbDstAndLine;
2938	pbSrc += cbSrcAndLine;
2939	}
2940	break;
2941	case 16:
2942	for (uint32_t y = 0; y < cy; y++)
2943	{
2944	for (uint32_t x = 0; x < cx; )
2945	{
2946	uint8_t bDst = 0;
2947	uint8_t fBit = 0x80;
2948	do
2949	{
2950	if ((pbSrc[x * 2] \| pbSrc[x * 2 + 1]) >= 0xfc)
2951	bDst \|= fBit;
2952	fBit >>= 1;
2953	x++;
2954	} while (x < cx && (x & 7));
2955	pbDst[(x - 1) / 8] = bDst;
2956	}
2957	pbDst += cbDstAndLine;
2958	pbSrc += cbSrcAndLine;
2959	}
2960	break;
2961	case 24:
2962	for (uint32_t y = 0; y < cy; y++)
2963	{
2964	for (uint32_t x = 0; x < cx; )
2965	{
2966	uint8_t bDst = 0;
2967	uint8_t fBit = 0x80;
2968	do
2969	{
2970	if ((pbSrc[x * 3] \| pbSrc[x * 3 + 1] \| pbSrc[x * 3 + 2]) >= 0xfc)
2971	bDst \|= fBit;
2972	fBit >>= 1;
2973	x++;
2974	} while (x < cx && (x & 7));
2975	pbDst[(x - 1) / 8] = bDst;
2976	}
2977	pbDst += cbDstAndLine;
2978	pbSrc += cbSrcAndLine;
2979	}
2980	break;
2981	case 32:
2982	for (uint32_t y = 0; y < cy; y++)
2983	{
2984	for (uint32_t x = 0; x < cx; )
2985	{
2986	uint8_t bDst = 0;
2987	uint8_t fBit = 0x80;
2988	do
2989	{
2990	if ((pbSrc[x * 4] \| pbSrc[x * 4 + 1] \| pbSrc[x * 4 + 2] \| pbSrc[x * 4 + 3]) >= 0xfc)
2991	bDst \|= fBit;
2992	fBit >>= 1;
2993	x++;
2994	} while (x < cx && (x & 7));
2995	pbDst[(x - 1) / 8] = bDst;
2996	}
2997	pbDst += cbDstAndLine;
2998	pbSrc += cbSrcAndLine;
2999	}
3000	break;
3001	default:
3002	RTMemFreeZ(pbCopy, cbCopy);
3003	AssertFailedReturnVoid();
3004	}
3005
3006	/* Convert the XOR mask. */
3007	uint32_t pu32Dst = (uint32_t )(pbCopy + RT_ALIGN_32(cbDstAndMask, 4));
3008	pbSrc = pbSrcXorMask;
3009	switch (pCursor->xorMaskDepth)
3010	{
3011	case 1:
3012	for (uint32_t y = 0; y < cy; y++)
3013	{
3014	for (uint32_t x = 0; x < cx; )
3015	{
3016	/* most significant bit is the left most one. */
3017	uint8_t bSrc = pbSrc[x / 8];
3018	do
3019	{
3020	*pu32Dst++ = bSrc & 0x80 ? UINT32_C(0x00ffffff) : 0;
3021	bSrc <<= 1;
3022	x++;
3023	} while ((x & 7) && x < cx);
3024	}
3025	pbSrc += cbSrcXorLine;
3026	}
3027	break;
3028	case 8:
3029	for (uint32_t y = 0; y < cy; y++)
3030	{
3031	for (uint32_t x = 0; x < cx; x++)
3032	{
3033	uint32_t u = pThis->last_palette[pbSrc[x]];
3034	*pu32Dst++ = u;//RT_MAKE_U32_FROM_U8(RT_BYTE1(u), RT_BYTE2(u), RT_BYTE3(u), 0);
3035	}
3036	pbSrc += cbSrcXorLine;
3037	}
3038	break;
3039	case 15: /* Src: RGB-5-5-5 */
3040	for (uint32_t y = 0; y < cy; y++)
3041	{
3042	for (uint32_t x = 0; x < cx; x++)
3043	{
3044	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3045	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3046	((uValue >> 5) & 0x1f) << 3,
3047	((uValue >> 10) & 0x1f) << 3, 0);
3048	}
3049	pbSrc += cbSrcXorLine;
3050	}
3051	break;
3052	case 16: /* Src: RGB-5-6-5 */
3053	for (uint32_t y = 0; y < cy; y++)
3054	{
3055	for (uint32_t x = 0; x < cx; x++)
3056	{
3057	uint32_t const uValue = RT_MAKE_U16(pbSrc[x * 2], pbSrc[x * 2 + 1]);
3058	*pu32Dst++ = RT_MAKE_U32_FROM_U8(( uValue & 0x1f) << 3,
3059	((uValue >> 5) & 0x3f) << 2,
3060	((uValue >> 11) & 0x1f) << 3, 0);
3061	}
3062	pbSrc += cbSrcXorLine;
3063	}
3064	break;
3065	case 24:
3066	for (uint32_t y = 0; y < cy; y++)
3067	{
3068	for (uint32_t x = 0; x < cx; x++)
3069	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x3], pbSrc[x3 + 1], pbSrc[x3 + 2], 0);
3070	pbSrc += cbSrcXorLine;
3071	}
3072	break;
3073	case 32:
3074	for (uint32_t y = 0; y < cy; y++)
3075	{
3076	for (uint32_t x = 0; x < cx; x++)
3077	pu32Dst++ = RT_MAKE_U32_FROM_U8(pbSrc[x4], pbSrc[x4 + 1], pbSrc[x4 + 2], 0);
3078	pbSrc += cbSrcXorLine;
3079	}
3080	break;
3081	default:
3082	RTMemFreeZ(pbCopy, cbCopy);
3083	AssertFailedReturnVoid();
3084	}
3085
3086	/*
3087	* Pass it to the frontend/whatever.
3088	*/
3089	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, false /fAlpha/, pCursor->hotspotX, pCursor->hotspotY, cx, cy, pbCopy, cbCopy);
3090	}
3091
3092
3093	/**
3094	* Worker for vmsvgaR3FifoThread that handles an external command.
3095	*
3096	* @param pDevIns The device instance.
3097	* @param pThis The shared VGA/VMSVGA instance data.
3098	* @param pThisCC The VGA/VMSVGA state for ring-3.
3099	*/
3100	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3101	{
3102	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3103	switch (pThis->svga.u8FIFOExtCommand)
3104	{
3105	case VMSVGA_FIFO_EXTCMD_RESET:
3106	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3107	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3108
3109	vmsvgaR3ResetScreens(pThis, pThisCC);
3110	# ifdef VBOX_WITH_VMSVGA3D
3111	if (pThis->svga.f3DEnabled)
3112	{
3113	/* The 3d subsystem must be reset from the fifo thread. */
3114	vmsvga3dReset(pThisCC);
3115	}
3116	# endif
3117	break;
3118
3119	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3120	Log(("vmsvgaR3FifoLoop: power off.\n"));
3121	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3122
3123	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3124	vmsvgaR3ResetScreens(pThis, pThisCC);
3125	break;
3126
3127	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3128	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3129	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3130	# ifdef VBOX_WITH_VMSVGA3D
3131	if (pThis->svga.f3DEnabled)
3132	{
3133	/* The 3d subsystem must be shut down from the fifo thread. */
3134	vmsvga3dTerminate(pThisCC);
3135	}
3136	# endif
3137	break;
3138
3139	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3140	{
3141	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3142	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3143	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3144	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3145	# ifdef VBOX_WITH_VMSVGA3D
3146	if (pThis->svga.f3DEnabled)
3147	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3148	# endif
3149	break;
3150	}
3151
3152	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3153	{
3154	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3155	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3156	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3157	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3158	# ifdef VBOX_WITH_VMSVGA3D
3159	if (pThis->svga.f3DEnabled)
3160	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3161	# endif
3162	break;
3163	}
3164
3165	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3166	{
3167	# ifdef VBOX_WITH_VMSVGA3D
3168	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3169	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3170	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3171	# endif
3172	break;
3173	}
3174
3175
3176	default:
3177	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3178	break;
3179	}
3180
3181	/*
3182	* Signal the end of the external command.
3183	*/
3184	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3185	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3186	ASMMemoryFence(); /* paranoia^2 */
3187	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3188	AssertLogRelRC(rc);
3189	}
3190
3191	/**
3192	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3193	* doing a job on the FIFO thread (even when it's officially suspended).
3194	*
3195	* @returns VBox status code (fully asserted).
3196	* @param pDevIns The device instance.
3197	* @param pThis The shared VGA/VMSVGA instance data.
3198	* @param pThisCC The VGA/VMSVGA state for ring-3.
3199	* @param uExtCmd The command to execute on the FIFO thread.
3200	* @param pvParam Pointer to command parameters.
3201	* @param cMsWait The time to wait for the command, given in
3202	* milliseconds.
3203	*/
3204	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3205	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3206	{
3207	Assert(cMsWait >= RT_MS_1SEC * 5);
3208	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3209	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3210
3211	int rc;
3212	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3213	PDMTHREADSTATE enmState = pThread->enmState;
3214	if (enmState == PDMTHREADSTATE_SUSPENDED)
3215	{
3216	/*
3217	* The thread is suspended, we have to temporarily wake it up so it can
3218	* perform the task.
3219	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3220	*/
3221	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3222	/* Post the request. */
3223	pThis->svga.fFifoExtCommandWakeup = true;
3224	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3225	pThis->svga.u8FIFOExtCommand = uExtCmd;
3226	ASMMemoryFence(); /* paranoia^3 */
3227
3228	/* Resume the thread. */
3229	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3230	AssertLogRelRC(rc);
3231	if (RT_SUCCESS(rc))
3232	{
3233	/* Wait. Take care in case the semaphore was already posted (same as below). */
3234	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3235	if ( rc == VINF_SUCCESS
3236	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3237	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3238	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3239	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3240
3241	/* suspend the thread */
3242	pThis->svga.fFifoExtCommandWakeup = false;
3243	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3244	AssertLogRelRC(rc2);
3245	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3246	rc = rc2;
3247	}
3248	pThis->svga.fFifoExtCommandWakeup = false;
3249	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3250	}
3251	else if (enmState == PDMTHREADSTATE_RUNNING)
3252	{
3253	/*
3254	* The thread is running, should only happen during reset and vmsvga3dsfc.
3255	* We ASSUME not racing code here, both wrt thread state and ext commands.
3256	*/
3257	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3258	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
3259
3260	/* Post the request. */
3261	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3262	pThis->svga.u8FIFOExtCommand = uExtCmd;
3263	ASMMemoryFence(); /* paranoia^2 */
3264	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3265	AssertLogRelRC(rc);
3266
3267	/* Wait. Take care in case the semaphore was already posted (same as above). */
3268	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3269	if ( rc == VINF_SUCCESS
3270	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3271	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
3272	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3273	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3274
3275	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3276	}
3277	else
3278	{
3279	/*
3280	* Something is wrong with the thread!
3281	*/
3282	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
3283	rc = VERR_INVALID_STATE;
3284	}
3285	return rc;
3286	}
3287
3288
3289	/**
3290	* Marks the FIFO non-busy, notifying any waiting EMTs.
3291	*
3292	* @param pDevIns The device instance.
3293	* @param pThis The shared VGA/VMSVGA instance data.
3294	* @param pThisCC The VGA/VMSVGA state for ring-3.
3295	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
3296	* @param offFifoMin The start byte offset of the command FIFO.
3297	*/
3298	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
3299	{
3300	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
3301	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3302	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
3303
3304	/* Wake up any waiting EMTs. */
3305	if (pSVGAState->cBusyDelayedEmts > 0)
3306	{
3307	# ifdef VMSVGA_USE_EMT_HALT_CODE
3308	PVM pVM = PDMDevHlpGetVM(pDevIns);
3309	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
3310	if (idCpu != NIL_VMCPUID)
3311	{
3312	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3313	while (idCpu-- > 0)
3314	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
3315	VMR3NotifyCpuDeviceReady(pVM, idCpu);
3316	}
3317	# else
3318	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
3319	AssertRC(rc2);
3320	# endif
3321	}
3322	}
3323
3324	/**
3325	* Reads (more) payload into the command buffer.
3326	*
3327	* @returns pbBounceBuf on success
3328	* @retval (void *)1 if the thread was requested to stop.
3329	* @retval NULL on FIFO error.
3330	*
3331	* @param cbPayloadReq The number of bytes of payload requested.
3332	* @param pFIFO The FIFO.
3333	* @param offCurrentCmd The FIFO byte offset of the current command.
3334	* @param offFifoMin The start byte offset of the command FIFO.
3335	* @param offFifoMax The end byte offset of the command FIFO.
3336	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
3337	* always sufficient size.
3338	* @param pcbAlreadyRead How much payload we've already read into the bounce
3339	* buffer. (We will NEVER re-read anything.)
3340	* @param pThread The calling PDM thread handle.
3341	* @param pThis The shared VGA/VMSVGA instance data.
3342	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
3343	* statistics collection.
3344	* @param pDevIns The device instance.
3345	*/
3346	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
3347	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
3348	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
3349	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
3350	{
3351	Assert(pbBounceBuf);
3352	Assert(pcbAlreadyRead);
3353	Assert(offFifoMin < offFifoMax);
3354	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
3355	Assert(offFifoMax <= pThis->svga.cbFIFO);
3356
3357	/*
3358	* Check if the requested payload size has already been satisfied .
3359	* .
3360	* When called to read more, the caller is responsible for making sure the .
3361	* new command size (cbRequsted) never is smaller than what has already .
3362	* been read.
3363	*/
3364	uint32_t cbAlreadyRead = *pcbAlreadyRead;
3365	if (cbPayloadReq <= cbAlreadyRead)
3366	{
3367	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
3368	return pbBounceBuf;
3369	}
3370
3371	/*
3372	* Commands bigger than the fifo buffer are invalid.
3373	*/
3374	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
3375	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
3376	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
3377	NULL);
3378
3379	/*
3380	* Move offCurrentCmd past the command dword.
3381	*/
3382	offCurrentCmd += sizeof(uint32_t);
3383	if (offCurrentCmd >= offFifoMax)
3384	offCurrentCmd = offFifoMin;
3385
3386	/*
3387	* Do we have sufficient payload data available already?
3388	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
3389	*/
3390	uint32_t cbAfter, cbBefore;
3391	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3392	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3393	if (offNextCmd >= offCurrentCmd)
3394	{
3395	if (RT_LIKELY(offNextCmd < offFifoMax))
3396	cbAfter = offNextCmd - offCurrentCmd;
3397	else
3398	{
3399	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3400	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3401	offNextCmd, offFifoMin, offFifoMax));
3402	cbAfter = offFifoMax - offCurrentCmd;
3403	}
3404	cbBefore = 0;
3405	}
3406	else
3407	{
3408	cbAfter = offFifoMax - offCurrentCmd;
3409	if (offNextCmd >= offFifoMin)
3410	cbBefore = offNextCmd - offFifoMin;
3411	else
3412	{
3413	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3414	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
3415	offNextCmd, offFifoMin, offFifoMax));
3416	cbBefore = 0;
3417	}
3418	}
3419	if (cbAfter + cbBefore < cbPayloadReq)
3420	{
3421	/*
3422	* Insufficient, must wait for it to arrive.
3423	*/
3424	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
3425	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
3426	for (uint32_t i = 0;; i++)
3427	{
3428	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3429	{
3430	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3431	return (void *)(uintptr_t)1;
3432	}
3433	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
3434	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
3435
3436	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
3437
3438	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
3439	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3440	if (offNextCmd >= offCurrentCmd)
3441	{
3442	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
3443	cbBefore = 0;
3444	}
3445	else
3446	{
3447	cbAfter = offFifoMax - offCurrentCmd;
3448	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
3449	}
3450
3451	if (cbAfter + cbBefore >= cbPayloadReq)
3452	break;
3453	}
3454	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
3455	}
3456
3457	/*
3458	* Copy out the memory and update what pcbAlreadyRead points to.
3459	*/
3460	if (cbAfter >= cbPayloadReq)
3461	memcpy(pbBounceBuf + cbAlreadyRead,
3462	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3463	cbPayloadReq - cbAlreadyRead);
3464	else
3465	{
3466	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
3467	if (cbAlreadyRead < cbAfter)
3468	{
3469	memcpy(pbBounceBuf + cbAlreadyRead,
3470	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
3471	cbAfter - cbAlreadyRead);
3472	cbAlreadyRead = cbAfter;
3473	}
3474	memcpy(pbBounceBuf + cbAlreadyRead,
3475	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
3476	cbPayloadReq - cbAlreadyRead);
3477	}
3478	*pcbAlreadyRead = cbPayloadReq;
3479	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3480	return pbBounceBuf;
3481	}
3482
3483
3484	/**
3485	* Sends cursor position and visibility information from the FIFO to the front-end.
3486	* @returns SVGA_FIFO_CURSOR_COUNT value used.
3487	*/
3488	static uint32_t
3489	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
3490	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
3491	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
3492	{
3493	/*
3494	* Check if the cursor update counter has changed and try get a stable
3495	* set of values if it has. This is race-prone, especially consindering
3496	* the screen ID, but little we can do about that.
3497	*/
3498	uint32_t x, y, fVisible, idScreen;
3499	for (uint32_t i = 0; ; i++)
3500	{
3501	x = pFIFO[SVGA_FIFO_CURSOR_X];
3502	y = pFIFO[SVGA_FIFO_CURSOR_Y];
3503	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
3504	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
3505	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
3506	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
3507	\|\| i > 3)
3508	break;
3509	if (i == 0)
3510	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
3511	ASMNopPause();
3512	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3513	}
3514
3515	/*
3516	* Check if anything has changed, as calling into pDrv is not light-weight.
3517	*/
3518	if ( *pxLast == x
3519	&& *pyLast == y
3520	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
3521	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
3522	else
3523	{
3524	/*
3525	* Detected changes.
3526	*
3527	* We handle global, not per-screen visibility information by sending
3528	* pfnVBVAMousePointerShape without shape data.
3529	*/
3530	*pxLast = x;
3531	*pyLast = y;
3532	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
3533	if (idScreen != SVGA_ID_INVALID)
3534	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
3535	else if (*pfLastVisible != fVisible)
3536	{
3537	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
3538	*pfLastVisible = fVisible;
3539	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
3540	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
3541	}
3542	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
3543	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
3544	}
3545
3546	/*
3547	* Update done. Signal this to the guest.
3548	*/
3549	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
3550
3551	return uCursorUpdateCount;
3552	}
3553
3554
3555	/**
3556	* Checks if there is work to be done, either cursor updating or FIFO commands.
3557	*
3558	* @returns true if pending work, false if not.
3559	* @param pFIFO The FIFO to examine.
3560	* @param uLastCursorCount The last cursor update counter value.
3561	*/
3562	DECLINLINE(bool) vmsvgaR3FifoHasWork(uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO, uint32_t uLastCursorCount)
3563	{
3564	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
3565	return true;
3566
3567	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
3568	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
3569	return true;
3570
3571	return false;
3572	}
3573
3574
3575	/**
3576	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
3577	*
3578	* @param pDevIns The device instance.
3579	* @param pThis The shared VGA/VMSVGA instance data.
3580	* @param pThisCC The VGA/VMSVGA state for ring-3.
3581	*/
3582	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3583	{
3584	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
3585	to recheck it before doing the signalling. */
3586	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3587	AssertReturnVoid(pFIFO);
3588	if ( vmsvgaR3FifoHasWork(pFIFO, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
3589	&& pThis->svga.fFIFOThreadSleeping)
3590	{
3591	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3592	AssertRC(rc);
3593	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
3594	}
3595	}
3596
3597
3598	/**
3599	* Called by the FIFO thread to process pending actions.
3600	*
3601	* @param pDevIns The device instance.
3602	* @param pThis The shared VGA/VMSVGA instance data.
3603	* @param pThisCC The VGA/VMSVGA state for ring-3.
3604	*/
3605	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3606	{
3607	RT_NOREF(pDevIns);
3608
3609	/* Currently just mode changes. */
3610	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
3611	{
3612	vmsvgaR3ChangeMode(pThis, pThisCC);
3613	# ifdef VBOX_WITH_VMSVGA3D
3614	if (pThisCC->svga.p3dState != NULL)
3615	vmsvga3dChangeMode(pThisCC);
3616	# endif
3617	}
3618	}
3619
3620
3621	/*
3622	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
3623	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
3624	*/
3625	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
3626	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
3627	*
3628	* Will break out of the switch on failure.
3629	* Will restart and quit the loop if the thread was requested to stop.
3630	*
3631	* @param a_PtrVar Request variable pointer.
3632	* @param a_Type Request typedef (not pointer) for casting.
3633	* @param a_cbPayloadReq How much payload to fetch.
3634	* @remarks Accesses a bunch of variables in the current scope!
3635	*/
3636	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3637	if (1) { \
3638	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
3639	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
3640	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
3641	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
3642	} else do {} while (0)
3643	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
3644	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
3645	* buffer after figuring out the actual command size.
3646	*
3647	* Will break out of the switch on failure.
3648	*
3649	* @param a_PtrVar Request variable pointer.
3650	* @param a_Type Request typedef (not pointer) for casting.
3651	* @param a_cbPayloadReq How much payload to fetch.
3652	* @remarks Accesses a bunch of variables in the current scope!
3653	*/
3654	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
3655	if (1) { \
3656	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
3657	} else do {} while (0)
3658
3659	/**
3660	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
3661	*/
3662	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3663	{
3664	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3665	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3666	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
3667	int rc;
3668
3669	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
3670	if (pThis->svga.f3DEnabled)
3671	{
3672	/* The FIFO thread may use X API for accelerated screen output. */
3673	XInitThreads();
3674	}
3675	# endif
3676
3677	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3678	return VINF_SUCCESS;
3679
3680	/*
3681	* Special mode where we only execute an external command and the go back
3682	* to being suspended. Currently, all ext cmds ends up here, with the reset
3683	* one also being eligble for runtime execution further down as well.
3684	*/
3685	if (pThis->svga.fFifoExtCommandWakeup)
3686	{
3687	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3688	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3689	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
3690	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
3691	else
3692	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3693	return VINF_SUCCESS;
3694	}
3695
3696
3697	/*
3698	* Signal the semaphore to make sure we don't wait for 250ms after a
3699	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
3700	*/
3701	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3702
3703	/*
3704	* Allocate a bounce buffer for command we get from the FIFO.
3705	* (All code must return via the end of the function to free this buffer.)
3706	*/
3707	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
3708	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
3709
3710	/*
3711	* Polling/sleep interval config.
3712	*
3713	* We wait for an a short interval if the guest has recently given us work
3714	* to do, but the interval increases the longer we're kept idle. Once we've
3715	* reached the refresh timer interval, we'll switch to extended waits,
3716	* depending on it or the guest to kick us into action when needed.
3717	*
3718	* Should the refresh time go fishing, we'll just continue increasing the
3719	* sleep length till we reaches the 250 ms max after about 16 seconds.
3720	*/
3721	RTMSINTERVAL const cMsMinSleep = 16;
3722	RTMSINTERVAL const cMsIncSleep = 2;
3723	RTMSINTERVAL const cMsMaxSleep = 250;
3724	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
3725	RTMSINTERVAL cMsSleep = cMsMaxSleep;
3726
3727	/*
3728	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
3729	*
3730	* Initialize with values that will detect an update from the guest.
3731	* Make sure that if the guest never updates the cursor position, then the device does not report it.
3732	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
3733	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
3734	*/
3735	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3736	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3737	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
3738	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
3739	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
3740
3741	/*
3742	* The FIFO loop.
3743	*/
3744	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
3745	bool fBadOrDisabledFifo = false;
3746	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3747	{
3748	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
3749	/*
3750	* Should service the run loop every so often.
3751	*/
3752	if (pThis->svga.f3DEnabled)
3753	vmsvga3dCocoaServiceRunLoop();
3754	# endif
3755
3756	/* First check any pending actions. */
3757	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3758
3759	/*
3760	* Unless there's already work pending, go to sleep for a short while.
3761	* (See polling/sleep interval config above.)
3762	*/
3763	if ( fBadOrDisabledFifo
3764	\|\| !vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3765	{
3766	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
3767	Assert(pThis->cMilliesRefreshInterval > 0);
3768	if (cMsSleep < pThis->cMilliesRefreshInterval)
3769	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
3770	else
3771	{
3772	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
3773	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
3774	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
3775	# endif
3776	if ( !fBadOrDisabledFifo
3777	&& vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3778	rc = VINF_SUCCESS;
3779	else
3780	{
3781	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
3782	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
3783	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
3784	}
3785	}
3786	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
3787	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
3788	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3789	{
3790	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
3791	break;
3792	}
3793	}
3794	else
3795	rc = VINF_SUCCESS;
3796	fBadOrDisabledFifo = false;
3797	if (rc == VERR_TIMEOUT)
3798	{
3799	if (!vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3800	{
3801	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
3802	continue;
3803	}
3804	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
3805
3806	Log(("vmsvgaR3FifoLoop: timeout\n"));
3807	}
3808	else if (vmsvgaR3FifoHasWork(pFIFO, pThis->svga.uLastCursorUpdateCount))
3809	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
3810	cMsSleep = cMsMinSleep;
3811
3812	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
3813	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
3814	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
3815
3816	/*
3817	* Handle external commands (currently only reset).
3818	*/
3819	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3820	{
3821	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
3822	continue;
3823	}
3824
3825	/*
3826	* The device must be enabled and configured.
3827	*/
3828	if ( !pThis->svga.fEnabled
3829	\|\| !pThis->svga.fConfigured)
3830	{
3831	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
3832	fBadOrDisabledFifo = true;
3833	cMsSleep = cMsMaxSleep; /* cheat */
3834	continue;
3835	}
3836
3837	/*
3838	* Get and check the min/max values. We ASSUME that they will remain
3839	* unchanged while we process requests. A further ASSUMPTION is that
3840	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
3841	* we don't read it back while in the loop.
3842	*/
3843	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3844	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
3845	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
3846	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3847	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
3848	\|\| offFifoMax <= offFifoMin
3849	\|\| offFifoMax > pThis->svga.cbFIFO
3850	\|\| (offFifoMax & 3) != 0
3851	\|\| (offFifoMin & 3) != 0
3852	\|\| offCurrentCmd < offFifoMin
3853	\|\| offCurrentCmd > offFifoMax))
3854	{
3855	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3856	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
3857	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
3858	fBadOrDisabledFifo = true;
3859	continue;
3860	}
3861	RT_UNTRUSTED_VALIDATED_FENCE();
3862	if (RT_UNLIKELY(offCurrentCmd & 3))
3863	{
3864	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
3865	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
3866	offCurrentCmd &= ~UINT32_C(3);
3867	}
3868
3869	/*
3870	* Update the cursor position before we start on the FIFO commands.
3871	*/
3872	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
3873	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
3874	{
3875	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
3876	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
3877	{ /* halfways likely */ }
3878	else
3879	{
3880	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
3881	&xLastCursor, &yLastCursor, &fLastCursorVisible);
3882	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
3883	}
3884	}
3885
3886	/*
3887	* Mark the FIFO as busy.
3888	*/
3889	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
3890	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
3891	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
3892
3893	/*
3894	* Execute all queued FIFO commands.
3895	* Quit if pending external command or changes in the thread state.
3896	*/
3897	bool fDone = false;
3898	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
3899	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
3900	{
3901	uint32_t cbPayload = 0;
3902	uint32_t u32IrqStatus = 0;
3903
3904	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
3905
3906	/* First check any pending actions. */
3907	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
3908
3909	/* Check for pending external commands (reset). */
3910	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3911	break;
3912
3913	/*
3914	* Process the command.
3915	*/
3916	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3917	* warning. Because we support some obsolete and deprecated commands, which are not included in
3918	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3919	*/
3920	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
3921	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
3922	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
3923	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
3924	switch (enmCmdId)
3925	{
3926	case SVGA_CMD_INVALID_CMD:
3927	/* Nothing to do. */
3928	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
3929	break;
3930
3931	case SVGA_CMD_FENCE:
3932	{
3933	SVGAFifoCmdFence *pCmdFence;
3934	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
3935	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
3936	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3937	{
3938	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
3939	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
3940
3941	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3942	{
3943	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
3944	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3945	}
3946	else
3947	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3948	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3949	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
3950	{
3951	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
3952	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3953	}
3954	}
3955	else
3956	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3957	break;
3958	}
3959	case SVGA_CMD_UPDATE:
3960	case SVGA_CMD_UPDATE_VERBOSE:
3961	{
3962	SVGAFifoCmdUpdate *pUpdate;
3963	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
3964	if (enmCmdId == SVGA_CMD_UPDATE)
3965	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdate);
3966	else
3967	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdUpdateVerbose);
3968	Log(("vmsvgaR3FifoLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
3969	/** @todo Multiple screens? */
3970	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
3971	if (!pScreen) /* Can happen if screen is not defined (aScreens[idScreen].fDefined == false) yet. */
3972	break;
3973	vmsvgaR3UpdateScreen(pThisCC, pScreen, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
3974	break;
3975	}
3976
3977	case SVGA_CMD_DEFINE_CURSOR:
3978	{
3979	/* Followed by bitmap data. */
3980	SVGAFifoCmdDefineCursor *pCursor;
3981	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
3982	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineCursor);
3983
3984	Log(("vmsvgaR3FifoLoop: CURSOR id=%d size (%d,%d) hotspot (%d,%d) andMaskDepth=%d xorMaskDepth=%d\n",
3985	pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY,
3986	pCursor->andMaskDepth, pCursor->xorMaskDepth));
3987	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
3988	AssertBreak(pCursor->andMaskDepth <= 32);
3989	AssertBreak(pCursor->xorMaskDepth <= 32);
3990	RT_UNTRUSTED_VALIDATED_FENCE();
3991
3992	uint32_t cbAndLine = RT_ALIGN_32(pCursor->width * (pCursor->andMaskDepth + (pCursor->andMaskDepth == 15)), 32) / 8;
3993	uint32_t cbAndMask = cbAndLine * pCursor->height;
3994	uint32_t cbXorLine = RT_ALIGN_32(pCursor->width * (pCursor->xorMaskDepth + (pCursor->xorMaskDepth == 15)), 32) / 8;
3995	uint32_t cbXorMask = cbXorLine * pCursor->height;
3996	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor) + cbAndMask + cbXorMask);
3997
3998	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pSVGAState, pCursor, (uint8_t const *)(pCursor + 1), cbAndLine,
3999	(uint8_t const *)(pCursor + 1) + cbAndMask, cbXorLine);
4000	break;
4001	}
4002
4003	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4004	{
4005	/* Followed by bitmap data. */
4006	uint32_t cbCursorShape, cbAndMask;
4007	uint8_t *pCursorCopy;
4008	uint32_t cbCmd;
4009
4010	SVGAFifoCmdDefineAlphaCursor *pCursor;
4011	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
4012	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineAlphaCursor);
4013
4014	Log(("vmsvgaR3FifoLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
4015
4016	/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
4017	AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
4018	RT_UNTRUSTED_VALIDATED_FENCE();
4019
4020	/* Refetch the bitmap data as well. */
4021	cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4022	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4023	/** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
4024
4025	/* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
4026	cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
4027	cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
4028	cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
4029
4030	pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
4031	AssertPtrBreak(pCursorCopy);
4032
4033	/* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
4034	memset(pCursorCopy, 0xff, cbAndMask);
4035	/* Colour data */
4036	memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
4037
4038	vmsvgaR3InstallNewCursor(pThisCC, pSVGAState, true /fAlpha/, pCursor->hotspotX, pCursor->hotspotY,
4039	pCursor->width, pCursor->height, pCursorCopy, cbCursorShape);
4040	break;
4041	}
4042
4043	case SVGA_CMD_MOVE_CURSOR:
4044	{
4045	/* Deprecated; there should be no driver which requires this command. However, if
4046	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4047	* alignment.
4048	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4049	*/
4050	SVGAFifoCmdMoveCursor *pMoveCursor;
4051	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pMoveCursor, SVGAFifoCmdMoveCursor, sizeof(*pMoveCursor));
4052	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdMoveCursor);
4053
4054	Log(("vmsvgaR3FifoLoop: MOVE CURSOR to %d,%d\n", pMoveCursor->pos.x, pMoveCursor->pos.y));
4055	LogRelMax(4, ("Unsupported SVGA_CMD_MOVE_CURSOR command ignored.\n"));
4056	break;
4057	}
4058
4059	case SVGA_CMD_DISPLAY_CURSOR:
4060	{
4061	/* Deprecated; there should be no driver which requires this command. However, if
4062	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4063	* alignment.
4064	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4065	*/
4066	SVGAFifoCmdDisplayCursor *pDisplayCursor;
4067	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pDisplayCursor, SVGAFifoCmdDisplayCursor, sizeof(*pDisplayCursor));
4068	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDisplayCursor);
4069
4070	Log(("vmsvgaR3FifoLoop: DISPLAY CURSOR id=%d state=%d\n", pDisplayCursor->id, pDisplayCursor->state));
4071	LogRelMax(4, ("Unsupported SVGA_CMD_DISPLAY_CURSOR command ignored.\n"));
4072	break;
4073	}
4074
4075	case SVGA_CMD_RECT_FILL:
4076	{
4077	SVGAFifoCmdRectFill *pRectFill;
4078	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectFill, SVGAFifoCmdRectFill, sizeof(*pRectFill));
4079	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectFill);
4080
4081	Log(("vmsvgaR3FifoLoop: RECT FILL %08X @ %d,%d (%dx%d)\n", pRectFill->pixel, pRectFill->destX, pRectFill->destY, pRectFill->width, pRectFill->height));
4082	LogRelMax(4, ("Unsupported SVGA_CMD_RECT_FILL command ignored.\n"));
4083	break;
4084	}
4085
4086	case SVGA_CMD_RECT_COPY:
4087	{
4088	SVGAFifoCmdRectCopy *pRectCopy;
4089	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRectCopy, SVGAFifoCmdRectCopy, sizeof(*pRectCopy));
4090	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectCopy);
4091
4092	Log(("vmsvgaR3FifoLoop: RECT COPY %d,%d -> %d,%d (%dx%d)\n", pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height));
4093	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4094	AssertPtrBreak(pScreen);
4095
4096	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4097	AssertBreak(pRectCopy->srcX < pThis->svga.u32MaxWidth);
4098	AssertBreak(pRectCopy->destX < pThis->svga.u32MaxWidth);
4099	AssertBreak(pRectCopy->width < pThis->svga.u32MaxWidth);
4100	AssertBreak(pRectCopy->srcY < pThis->svga.u32MaxHeight);
4101	AssertBreak(pRectCopy->destY < pThis->svga.u32MaxHeight);
4102	AssertBreak(pRectCopy->height < pThis->svga.u32MaxHeight);
4103
4104	vmsvgaR3RectCopy(pThisCC, pScreen, pRectCopy->srcX, pRectCopy->srcY, pRectCopy->destX, pRectCopy->destY,
4105	pRectCopy->width, pRectCopy->height, pThis->vram_size);
4106	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRectCopy->destX, pRectCopy->destY, pRectCopy->width, pRectCopy->height);
4107	break;
4108	}
4109
4110	case SVGA_CMD_RECT_ROP_COPY:
4111	{
4112	SVGAFifoCmdRectRopCopy *pRRCopy;
4113	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pRRCopy, SVGAFifoCmdRectRopCopy, sizeof(*pRRCopy));
4114	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRectRopCopy);
4115
4116	Log(("vmsvgaR3FifoLoop: RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4117	if (pRRCopy->rop != SVGA_ROP_COPY)
4118	{
4119	/* We only support the plain copy ROP which makes SVGA_CMD_RECT_ROP_COPY exactly the same
4120	* as SVGA_CMD_RECT_COPY. XFree86 4.1.0 and 4.2.0 drivers (driver version 10.4.0 and 10.7.0,
4121	* respectively) issue SVGA_CMD_RECT_ROP_COPY when SVGA_CAP_RECT_COPY is present even when
4122	* SVGA_CAP_RASTER_OP is not. However, the ROP will always be SVGA_ROP_COPY.
4123	*/
4124	LogRelMax(4, ("RECT ROP COPY %d,%d -> %d,%d (%dx%d) ROP %X unsupported\n", pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height, pRRCopy->rop));
4125	break;
4126	}
4127
4128	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, 0);
4129	AssertPtrBreak(pScreen);
4130
4131	/* Check that arguments aren't complete junk. A precise check is done in vmsvgaR3RectCopy(). */
4132	AssertBreak(pRRCopy->srcX < pThis->svga.u32MaxWidth);
4133	AssertBreak(pRRCopy->destX < pThis->svga.u32MaxWidth);
4134	AssertBreak(pRRCopy->width < pThis->svga.u32MaxWidth);
4135	AssertBreak(pRRCopy->srcY < pThis->svga.u32MaxHeight);
4136	AssertBreak(pRRCopy->destY < pThis->svga.u32MaxHeight);
4137	AssertBreak(pRRCopy->height < pThis->svga.u32MaxHeight);
4138
4139	vmsvgaR3RectCopy(pThisCC, pScreen, pRRCopy->srcX, pRRCopy->srcY, pRRCopy->destX, pRRCopy->destY,
4140	pRRCopy->width, pRRCopy->height, pThis->vram_size);
4141	vmsvgaR3UpdateScreen(pThisCC, pScreen, pRRCopy->destX, pRRCopy->destY, pRRCopy->width, pRRCopy->height);
4142	break;
4143	}
4144
4145	case SVGA_CMD_ESCAPE:
4146	{
4147	/* Followed by nsize bytes of data. */
4148	SVGAFifoCmdEscape *pEscape;
4149	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
4150	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdEscape);
4151
4152	/* Refetch the command buffer with the variable data; undo size increase (ugly) */
4153	AssertBreak(pEscape->size < pThis->svga.cbFIFO);
4154	RT_UNTRUSTED_VALIDATED_FENCE();
4155	uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
4156	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
4157
4158	if (pEscape->nsid == SVGA_ESCAPE_NSID_VMWARE)
4159	{
4160	AssertBreak(pEscape->size >= sizeof(uint32_t));
4161	RT_UNTRUSTED_VALIDATED_FENCE();
4162	uint32_t cmd = (uint32_t )(pEscape + 1);
4163	Log(("vmsvgaR3FifoLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
4164
4165	switch (cmd)
4166	{
4167	case SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS:
4168	{
4169	SVGAEscapeVideoSetRegs pVideoCmd = (SVGAEscapeVideoSetRegs )(pEscape + 1);
4170	AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
4171	uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
4172
4173	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
4174	for (uint32_t iReg = 0; iReg < cRegs; iReg++)
4175	Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
4176
4177	RT_NOREF_PV(pVideoCmd);
4178	break;
4179
4180	}
4181
4182	case SVGA_ESCAPE_VMWARE_VIDEO_FLUSH:
4183	{
4184	SVGAEscapeVideoFlush pVideoCmd = (SVGAEscapeVideoFlush )(pEscape + 1);
4185	AssertBreak(pEscape->size >= sizeof(*pVideoCmd));
4186	Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
4187	RT_NOREF_PV(pVideoCmd);
4188	break;
4189	}
4190
4191	default:
4192	Log(("SVGA_CMD_ESCAPE: Unknown vmware escape: %x\n", cmd));
4193	break;
4194	}
4195	}
4196	else
4197	Log(("vmsvgaR3FifoLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
4198
4199	break;
4200	}
4201	# ifdef VBOX_WITH_VMSVGA3D
4202	case SVGA_CMD_DEFINE_GMR2:
4203	{
4204	SVGAFifoCmdDefineGMR2 *pCmd;
4205	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4206	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
4207	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2);
4208
4209	/* Validate current GMR id. */
4210	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4211	AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
4212	RT_UNTRUSTED_VALIDATED_FENCE();
4213
4214	if (!pCmd->numPages)
4215	{
4216	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Free);
4217	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4218	}
4219	else
4220	{
4221	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4222	if (pGMR->cMaxPages)
4223	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmr2Modify);
4224
4225	/* Not sure if we should always free the descriptor, but for simplicity
4226	we do so if the new size is smaller than the current. */
4227	/** @todo always free the descriptor in SVGA_CMD_DEFINE_GMR2? */
4228	if (pGMR->cbTotal / X86_PAGE_SIZE > pGMR->cMaxPages)
4229	vmsvgaR3GmrFree(pThisCC, pCmd->gmrId);
4230
4231	pGMR->cMaxPages = pCmd->numPages;
4232	/* The rest is done by the REMAP_GMR2 command. */
4233	}
4234	break;
4235	}
4236
4237	case SVGA_CMD_REMAP_GMR2:
4238	{
4239	/* Followed by page descriptors or guest ptr. */
4240	SVGAFifoCmdRemapGMR2 *pCmd;
4241	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4242	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2);
4243
4244	Log(("vmsvgaR3FifoLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
4245	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4246	RT_UNTRUSTED_VALIDATED_FENCE();
4247
4248	/* Calculate the size of what comes after next and fetch it. */
4249	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4250	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4251	cbCmd += sizeof(SVGAGuestPtr);
4252	else
4253	{
4254	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4255	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4256	{
4257	cbCmd += cbPageDesc;
4258	pCmd->numPages = 1;
4259	}
4260	else
4261	{
4262	AssertBreak(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4263	cbCmd += cbPageDesc * pCmd->numPages;
4264	}
4265	}
4266	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4267
4268	/* Validate current GMR id and size. */
4269	AssertBreak(pCmd->gmrId < pThis->svga.cGMR);
4270	RT_UNTRUSTED_VALIDATED_FENCE();
4271	PGMR pGMR = &pSVGAState->paGMR[pCmd->gmrId];
4272	AssertBreak( (uint64_t)pCmd->offsetPages + pCmd->numPages
4273	<= RT_MIN(pGMR->cMaxPages, RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE)));
4274	AssertBreak(!pCmd->offsetPages \|\| pGMR->paDesc); /** @todo */
4275
4276	if (pCmd->numPages == 0)
4277	break;
4278
4279	/** @todo Move to a separate function vmsvgaGMRRemap() */
4280
4281	/* Calc new total page count so we can use it instead of cMaxPages for allocations below. */
4282	uint32_t const cNewTotalPages = RT_MAX(pGMR->cbTotal >> X86_PAGE_SHIFT, pCmd->offsetPages + pCmd->numPages);
4283
4284	/*
4285	* We flatten the existing descriptors into a page array, overwrite the
4286	* pages specified in this command and then recompress the descriptor.
4287	*/
4288	/** @todo Optimize the GMR remap algorithm! */
4289
4290	/* Save the old page descriptors as an array of page frame numbers (address >> X86_PAGE_SHIFT) */
4291	uint64_t *paNewPage64 = NULL;
4292	if (pGMR->paDesc)
4293	{
4294	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdRemapGmr2Modify);
4295
4296	paNewPage64 = (uint64_t )RTMemAllocZ(cNewTotalPages sizeof(uint64_t));
4297	AssertPtrBreak(paNewPage64);
4298
4299	uint32_t idxPage = 0;
4300	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
4301	for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
4302	paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * X86_PAGE_SIZE) >> X86_PAGE_SHIFT;
4303	AssertBreakStmt(idxPage == pGMR->cbTotal >> X86_PAGE_SHIFT, RTMemFree(paNewPage64));
4304	RT_UNTRUSTED_VALIDATED_FENCE();
4305	}
4306
4307	/* Free the old GMR if present. */
4308	if (pGMR->paDesc)
4309	RTMemFree(pGMR->paDesc);
4310
4311	/* Allocate the maximum amount possible (everything non-continuous) */
4312	PVMSVGAGMRDESCRIPTOR paDescs;
4313	pGMR->paDesc = paDescs = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cNewTotalPages * sizeof(VMSVGAGMRDESCRIPTOR));
4314	AssertBreakStmt(paDescs, RTMemFree(paNewPage64));
4315
4316	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4317	{
4318	/** @todo */
4319	AssertFailed();
4320	pGMR->numDescriptors = 0;
4321	}
4322	else
4323	{
4324	uint32_t paPages32 = (uint32_t )(pCmd + 1);
4325	uint64_t paPages64 = (uint64_t )(pCmd + 1);
4326	bool fGCPhys64 = RT_BOOL(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
4327
4328	if (paNewPage64)
4329	{
4330	/* Overwrite the old page array with the new page values. */
4331	if (fGCPhys64)
4332	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4333	paNewPage64[i] = paPages64[i - pCmd->offsetPages];
4334	else
4335	for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
4336	paNewPage64[i] = paPages32[i - pCmd->offsetPages];
4337
4338	/* Use the updated page array instead of the command data. */
4339	fGCPhys64 = true;
4340	paPages64 = paNewPage64;
4341	pCmd->numPages = cNewTotalPages;
4342	}
4343
4344	/* The first page. */
4345	/** @todo The 0x00000FFFFFFFFFFF mask limits to 44 bits and should not be
4346	* applied to paNewPage64. */
4347	RTGCPHYS GCPhys;
4348	if (fGCPhys64)
4349	GCPhys = (paPages64[0] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4350	else
4351	GCPhys = (RTGCPHYS)paPages32[0] << PAGE_SHIFT;
4352	paDescs[0].GCPhys = GCPhys;
4353	paDescs[0].numPages = 1;
4354
4355	/* Subsequent pages. */
4356	uint32_t iDescriptor = 0;
4357	for (uint32_t i = 1; i < pCmd->numPages; i++)
4358	{
4359	if (pCmd->flags & SVGA_REMAP_GMR2_PPN64)
4360	GCPhys = (paPages64[i] << X86_PAGE_SHIFT) & UINT64_C(0x00000FFFFFFFFFFF); /* Seeing rubbish in the top bits with certain linux guests. */
4361	else
4362	GCPhys = (RTGCPHYS)paPages32[i] << X86_PAGE_SHIFT;
4363
4364	/* Continuous physical memory? */
4365	if (GCPhys == paDescs[iDescriptor].GCPhys + paDescs[iDescriptor].numPages * X86_PAGE_SIZE)
4366	{
4367	Assert(paDescs[iDescriptor].numPages);
4368	paDescs[iDescriptor].numPages++;
4369	Log5Func(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
4370	}
4371	else
4372	{
4373	iDescriptor++;
4374	paDescs[iDescriptor].GCPhys = GCPhys;
4375	paDescs[iDescriptor].numPages = 1;
4376	Log5Func(("Page %x GCPhys=%RGp\n", i, paDescs[iDescriptor].GCPhys));
4377	}
4378	}
4379
4380	pGMR->cbTotal = cNewTotalPages << X86_PAGE_SHIFT;
4381	Log5Func(("Nr of descriptors %x; cbTotal=%#x\n", iDescriptor + 1, cNewTotalPages));
4382	pGMR->numDescriptors = iDescriptor + 1;
4383	}
4384
4385	if (paNewPage64)
4386	RTMemFree(paNewPage64);
4387
4388	# ifdef DEBUG_GMR_ACCESS
4389	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4390	# endif
4391	break;
4392	}
4393	# endif // VBOX_WITH_VMSVGA3D
4394	case SVGA_CMD_DEFINE_SCREEN:
4395	{
4396	/* The size of this command is specified by the guest and depends on capabilities. */
4397	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4398
4399	SVGAFifoCmdDefineScreen *pCmd;
4400	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4401	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4402	RT_UNTRUSTED_VALIDATED_FENCE();
4403
4404	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4405	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4406	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineScreen);
4407
4408	LogFunc(("SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d) %d:0x%x 0x%x\n",
4409	pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y,
4410	pCmd->screen.backingStore.ptr.gmrId, pCmd->screen.backingStore.ptr.offset, pCmd->screen.backingStore.pitch));
4411
4412	uint32_t const idScreen = pCmd->screen.id;
4413	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4414
4415	uint32_t const uWidth = pCmd->screen.size.width;
4416	AssertBreak(uWidth <= pThis->svga.u32MaxWidth);
4417
4418	uint32_t const uHeight = pCmd->screen.size.height;
4419	AssertBreak(uHeight <= pThis->svga.u32MaxHeight);
4420
4421	uint32_t const cbWidth = uWidth * ((32 + 7) / 8); /** @todo 32? */
4422	uint32_t const cbPitch = pCmd->screen.backingStore.pitch ? pCmd->screen.backingStore.pitch : cbWidth;
4423	AssertBreak(cbWidth <= cbPitch);
4424
4425	uint32_t const uScreenOffset = pCmd->screen.backingStore.ptr.offset;
4426	AssertBreak(uScreenOffset < pThis->vram_size);
4427
4428	uint32_t const cbVram = pThis->vram_size - uScreenOffset;
4429	/* If we have a not zero pitch, then height can't exceed the available VRAM. */
4430	AssertBreak( (uHeight == 0 && cbPitch == 0)
4431	\|\| (cbPitch > 0 && uHeight <= cbVram / cbPitch));
4432	RT_UNTRUSTED_VALIDATED_FENCE();
4433
4434	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4435
4436	bool const fBlank = RT_BOOL(pCmd->screen.flags & (SVGA_SCREEN_DEACTIVATE \| SVGA_SCREEN_BLANKING));
4437
4438	pScreen->fDefined = true;
4439	pScreen->fModified = true;
4440	pScreen->fuScreen = pCmd->screen.flags;
4441	pScreen->idScreen = idScreen;
4442	if (!fBlank)
4443	{
4444	AssertBreak(uWidth > 0 && uHeight > 0);
4445
4446	pScreen->xOrigin = pCmd->screen.root.x;
4447	pScreen->yOrigin = pCmd->screen.root.y;
4448	pScreen->cWidth = uWidth;
4449	pScreen->cHeight = uHeight;
4450	pScreen->offVRAM = uScreenOffset;
4451	pScreen->cbPitch = cbPitch;
4452	pScreen->cBpp = 32;
4453	}
4454	else
4455	{
4456	/* Keep old values. */
4457	}
4458
4459	pThis->svga.fGFBRegisters = false;
4460	vmsvgaR3ChangeMode(pThis, pThisCC);
4461
4462	# ifdef VBOX_WITH_VMSVGA3D
4463	if (RT_LIKELY(pThis->svga.f3DEnabled))
4464	vmsvga3dDefineScreen(pThis, pThisCC, pScreen);
4465	# endif
4466	break;
4467	}
4468
4469	case SVGA_CMD_DESTROY_SCREEN:
4470	{
4471	SVGAFifoCmdDestroyScreen *pCmd;
4472	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4473	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDestroyScreen);
4474
4475	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
4476
4477	uint32_t const idScreen = pCmd->screenId;
4478	AssertBreak(idScreen < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4479	RT_UNTRUSTED_VALIDATED_FENCE();
4480
4481	VMSVGASCREENOBJECT *pScreen = &pThisCC->svga.pSvgaR3State->aScreens[idScreen];
4482	pScreen->fModified = true;
4483	pScreen->fDefined = false;
4484	pScreen->idScreen = idScreen;
4485
4486	# ifdef VBOX_WITH_VMSVGA3D
4487	if (RT_LIKELY(pThis->svga.f3DEnabled))
4488	vmsvga3dDestroyScreen(pThisCC, pScreen);
4489	# endif
4490	vmsvgaR3ChangeMode(pThis, pThisCC);
4491	break;
4492	}
4493
4494	case SVGA_CMD_DEFINE_GMRFB:
4495	{
4496	SVGAFifoCmdDefineGMRFB *pCmd;
4497	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4498	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdDefineGmrFb);
4499
4500	Log(("vmsvgaR3FifoLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.bitsPerPixel, pCmd->format.colorDepth));
4501	pSVGAState->GMRFB.ptr = pCmd->ptr;
4502	pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
4503	pSVGAState->GMRFB.format = pCmd->format;
4504	break;
4505	}
4506
4507	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4508	{
4509	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4510	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4511	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitGmrFbToScreen);
4512
4513	LogFunc(("SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n",
4514	pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
4515
4516	AssertBreak(pCmd->destScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4517	RT_UNTRUSTED_VALIDATED_FENCE();
4518
4519	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->destScreenId);
4520	AssertPtrBreak(pScreen);
4521
4522	/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
4523	AssertBreak(pSVGAState->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4524
4525	/* Clip destRect to the screen dimensions. */
4526	SVGASignedRect screenRect;
4527	screenRect.left = 0;
4528	screenRect.top = 0;
4529	screenRect.right = pScreen->cWidth;
4530	screenRect.bottom = pScreen->cHeight;
4531	SVGASignedRect clipRect = pCmd->destRect;
4532	vmsvgaR3ClipRect(&screenRect, &clipRect);
4533	RT_UNTRUSTED_VALIDATED_FENCE();
4534
4535	uint32_t const width = clipRect.right - clipRect.left;
4536	uint32_t const height = clipRect.bottom - clipRect.top;
4537
4538	if ( width == 0
4539	\|\| height == 0)
4540	break; /* Nothing to do. */
4541
4542	int32_t const srcx = pCmd->srcOrigin.x + (clipRect.left - pCmd->destRect.left);
4543	int32_t const srcy = pCmd->srcOrigin.y + (clipRect.top - pCmd->destRect.top);
4544
4545	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4546	* Prepare parameters for vmsvgaR3GmrTransfer.
4547	*/
4548	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4549
4550	/* Destination: host buffer which describes the screen 0 VRAM.
4551	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4552	*/
4553	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4554	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4555	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4556	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4557	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4558	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4559	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4560	+ cbScanline * clipRect.top;
4561	int32_t const cbHstPitch = cbScanline;
4562
4563	/* Source: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4564	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4565	uint32_t const offGst = (srcx * RT_ALIGN(pSVGAState->GMRFB.format.bitsPerPixel, 8)) / 8
4566	+ pSVGAState->GMRFB.bytesPerLine * srcy;
4567	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4568
4569	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_WRITE_HOST_VRAM,
4570	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4571	gstPtr, offGst, cbGstPitch,
4572	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4573	AssertRC(rc);
4574	vmsvgaR3UpdateScreen(pThisCC, pScreen, clipRect.left, clipRect.top, width, height);
4575	break;
4576	}
4577
4578	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4579	{
4580	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4581	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4582	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdBlitScreentoGmrFb);
4583
4584	/* Note! This can fetch 3d render results as well!! */
4585	LogFunc(("SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n",
4586	pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
4587
4588	AssertBreak(pCmd->srcScreenId < RT_ELEMENTS(pThisCC->svga.pSvgaR3State->aScreens));
4589	RT_UNTRUSTED_VALIDATED_FENCE();
4590
4591	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, pCmd->srcScreenId);
4592	AssertPtrBreak(pScreen);
4593
4594	/** @todo Support GMRFB.format.bitsPerPixel != pThis->svga.uBpp? */
4595	AssertBreak(pSVGAState->GMRFB.format.bitsPerPixel == pScreen->cBpp);
4596
4597	/* Clip destRect to the screen dimensions. */
4598	SVGASignedRect screenRect;
4599	screenRect.left = 0;
4600	screenRect.top = 0;
4601	screenRect.right = pScreen->cWidth;
4602	screenRect.bottom = pScreen->cHeight;
4603	SVGASignedRect clipRect = pCmd->srcRect;
4604	vmsvgaR3ClipRect(&screenRect, &clipRect);
4605	RT_UNTRUSTED_VALIDATED_FENCE();
4606
4607	uint32_t const width = clipRect.right - clipRect.left;
4608	uint32_t const height = clipRect.bottom - clipRect.top;
4609
4610	if ( width == 0
4611	\|\| height == 0)
4612	break; /* Nothing to do. */
4613
4614	int32_t const dstx = pCmd->destOrigin.x + (clipRect.left - pCmd->srcRect.left);
4615	int32_t const dsty = pCmd->destOrigin.y + (clipRect.top - pCmd->srcRect.top);
4616
4617	/* Copy the defined by GMRFB image to the screen 0 VRAM area.
4618	* Prepare parameters for vmsvgaR3GmrTransfer.
4619	*/
4620	AssertBreak(pScreen->offVRAM < pThis->vram_size); /* Paranoia. Ensured by SVGA_CMD_DEFINE_SCREEN. */
4621
4622	/* Source: host buffer which describes the screen 0 VRAM.
4623	* Important are pbHstBuf and cbHstBuf. offHst and cbHstPitch are verified by vmsvgaR3GmrTransfer.
4624	*/
4625	uint8_t * const pbHstBuf = (uint8_t *)pThisCC->pbVRam + pScreen->offVRAM;
4626	uint32_t const cbScanline = pScreen->cbPitch ? pScreen->cbPitch :
4627	width * (RT_ALIGN(pScreen->cBpp, 8) / 8);
4628	uint32_t cbHstBuf = cbScanline * pScreen->cHeight;
4629	if (cbHstBuf > pThis->vram_size - pScreen->offVRAM)
4630	cbHstBuf = pThis->vram_size - pScreen->offVRAM; /* Paranoia. */
4631	uint32_t const offHst = (clipRect.left * RT_ALIGN(pScreen->cBpp, 8)) / 8
4632	+ cbScanline * clipRect.top;
4633	int32_t const cbHstPitch = cbScanline;
4634
4635	/* Destination: GMRFB. vmsvgaR3GmrTransfer ensures that no memory outside the GMR is read. */
4636	SVGAGuestPtr const gstPtr = pSVGAState->GMRFB.ptr;
4637	uint32_t const offGst = (dstx * RT_ALIGN(pSVGAState->GMRFB.format.bitsPerPixel, 8)) / 8
4638	+ pSVGAState->GMRFB.bytesPerLine * dsty;
4639	int32_t const cbGstPitch = pSVGAState->GMRFB.bytesPerLine;
4640
4641	rc = vmsvgaR3GmrTransfer(pThis, pThisCC, SVGA3D_READ_HOST_VRAM,
4642	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
4643	gstPtr, offGst, cbGstPitch,
4644	(width * RT_ALIGN(pScreen->cBpp, 8)) / 8, height);
4645	AssertRC(rc);
4646	break;
4647	}
4648
4649	case SVGA_CMD_ANNOTATION_FILL:
4650	{
4651	SVGAFifoCmdAnnotationFill *pCmd;
4652	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4653	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationFill);
4654
4655	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.r, pCmd->color.g, pCmd->color.b));
4656	pSVGAState->colorAnnotation = pCmd->color;
4657	break;
4658	}
4659
4660	case SVGA_CMD_ANNOTATION_COPY:
4661	{
4662	SVGAFifoCmdAnnotationCopy *pCmd;
4663	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4664	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdAnnotationCopy);
4665
4666	Log(("vmsvgaR3FifoLoop: SVGA_CMD_ANNOTATION_COPY\n"));
4667	AssertFailed();
4668	break;
4669	}
4670
4671	default:
4672	# ifdef VBOX_WITH_VMSVGA3D
4673	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4674	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4675	{
4676	RT_UNTRUSTED_VALIDATED_FENCE();
4677
4678	/* All 3d commands start with a common header, which defines the identifier and the size
4679	* of the command. The identifier has been already read from FIFO. Fetch the size.
4680	*/
4681	uint32_t *pcbCmd;
4682	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
4683	uint32_t const cbCmd = *pcbCmd;
4684	AssertBreak(cbCmd < pThis->svga.cbFIFO);
4685	uint32_t *pu32Cmd;
4686	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
4687	pu32Cmd++; /* Skip the command size. */
4688
4689	if (RT_LIKELY(pThis->svga.f3DEnabled))
4690	{ /* likely */ }
4691	else
4692	{
4693	LogRelMax(8, ("VMSVGA3d: 3D disabled, command %d skipped\n", enmCmdId));
4694	break;
4695	}
4696
4697	/** @def VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
4698	* Check that the 3D command has at least a_cbMin of payload bytes after the
4699	* header. Will break out of the switch if it doesn't.
4700	*/
4701	# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
4702	if (1) { \
4703	AssertMsgBreak(cbCmd >= (a_cbMin), ("size=%#x a_cbMin=%#zx\n", cbCmd, (size_t)(a_cbMin))); \
4704	RT_UNTRUSTED_VALIDATED_FENCE(); \
4705	} else do {} while (0)
4706	switch ((int)enmCmdId)
4707	{
4708	case SVGA_3D_CMD_SURFACE_DEFINE:
4709	{
4710	uint32_t cMipLevels;
4711	SVGA3dCmdDefineSurface pCmd = (SVGA3dCmdDefineSurface )pu32Cmd;
4712	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4713	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefine);
4714
4715	cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4716	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0,
4717	SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
4718	# ifdef DEBUG_GMR_ACCESS
4719	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3ResetGmrHandlers, 1, pThis);
4720	# endif
4721	break;
4722	}
4723
4724	case SVGA_3D_CMD_SURFACE_DEFINE_V2:
4725	{
4726	uint32_t cMipLevels;
4727	SVGA3dCmdDefineSurface_v2 pCmd = (SVGA3dCmdDefineSurface_v2 )pu32Cmd;
4728	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4729	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDefineV2);
4730
4731	cMipLevels = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dSize);
4732	rc = vmsvga3dSurfaceDefine(pThisCC, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face,
4733	pCmd->multisampleCount, pCmd->autogenFilter,
4734	cMipLevels, (SVGA3dSize *)(pCmd + 1));
4735	break;
4736	}
4737
4738	case SVGA_3D_CMD_SURFACE_DESTROY:
4739	{
4740	SVGA3dCmdDestroySurface pCmd = (SVGA3dCmdDestroySurface )pu32Cmd;
4741	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4742	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDestroy);
4743	rc = vmsvga3dSurfaceDestroy(pThisCC, pCmd->sid);
4744	break;
4745	}
4746
4747	case SVGA_3D_CMD_SURFACE_COPY:
4748	{
4749	uint32_t cCopyBoxes;
4750	SVGA3dCmdSurfaceCopy pCmd = (SVGA3dCmdSurfaceCopy )pu32Cmd;
4751	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4752	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceCopy);
4753
4754	cCopyBoxes = (cbCmd - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
4755	rc = vmsvga3dSurfaceCopy(pThisCC, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4756	break;
4757	}
4758
4759	case SVGA_3D_CMD_SURFACE_STRETCHBLT:
4760	{
4761	SVGA3dCmdSurfaceStretchBlt pCmd = (SVGA3dCmdSurfaceStretchBlt )pu32Cmd;
4762	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4763	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt);
4764
4765	rc = vmsvga3dSurfaceStretchBlt(pThis, pThisCC, &pCmd->dest, &pCmd->boxDest,
4766	&pCmd->src, &pCmd->boxSrc, pCmd->mode);
4767	break;
4768	}
4769
4770	case SVGA_3D_CMD_SURFACE_DMA:
4771	{
4772	uint32_t cCopyBoxes;
4773	SVGA3dCmdSurfaceDMA pCmd = (SVGA3dCmdSurfaceDMA )pu32Cmd;
4774	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4775	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceDma);
4776
4777	uint64_t u64NanoTS = 0;
4778	if (LogRelIs3Enabled())
4779	u64NanoTS = RTTimeNanoTS();
4780	cCopyBoxes = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
4781	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4782	rc = vmsvga3dSurfaceDMA(pThis, pThisCC, pCmd->guest, pCmd->host, pCmd->transfer,
4783	cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
4784	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, a);
4785	if (LogRelIs3Enabled())
4786	{
4787	if (cCopyBoxes)
4788	{
4789	SVGA3dCopyBox pFirstBox = (SVGA3dCopyBox )(pCmd + 1);
4790	LogRel3(("VMSVGA: SURFACE_DMA: %d us %d boxes %d,%d %dx%d%s\n",
4791	(RTTimeNanoTS() - u64NanoTS) / 1000ULL, cCopyBoxes,
4792	pFirstBox->x, pFirstBox->y, pFirstBox->w, pFirstBox->h,
4793	pCmd->transfer == SVGA3D_READ_HOST_VRAM ? " readback!!!" : ""));
4794	}
4795	}
4796	break;
4797	}
4798
4799	case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:
4800	{
4801	uint32_t cRects;
4802	SVGA3dCmdBlitSurfaceToScreen pCmd = (SVGA3dCmdBlitSurfaceToScreen )pu32Cmd;
4803	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4804	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSurfaceScreen);
4805
4806	static uint64_t u64FrameStartNanoTS = 0;
4807	static uint64_t u64ElapsedPerSecNano = 0;
4808	static int cFrames = 0;
4809	uint64_t u64NanoTS = 0;
4810	if (LogRelIs3Enabled())
4811	u64NanoTS = RTTimeNanoTS();
4812	cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGASignedRect);
4813	STAM_REL_PROFILE_START(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4814	rc = vmsvga3dSurfaceBlitToScreen(pThis, pThisCC, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage,
4815	pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
4816	STAM_REL_PROFILE_STOP(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, a);
4817	if (LogRelIs3Enabled())
4818	{
4819	uint64_t u64ElapsedNano = RTTimeNanoTS() - u64NanoTS;
4820	u64ElapsedPerSecNano += u64ElapsedNano;
4821
4822	SVGASignedRect pFirstRect = cRects ? (SVGASignedRect )(pCmd + 1) : &pCmd->destRect;
4823	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: %d us %d rects %d,%d %dx%d\n",
4824	(u64ElapsedNano) / 1000ULL, cRects,
4825	pFirstRect->left, pFirstRect->top,
4826	pFirstRect->right - pFirstRect->left, pFirstRect->bottom - pFirstRect->top));
4827
4828	++cFrames;
4829	if (u64NanoTS - u64FrameStartNanoTS >= UINT64_C(1000000000))
4830	{
4831	LogRel3(("VMSVGA: SURFACE_TO_SCREEN: FPS %d, elapsed %llu us\n",
4832	cFrames, u64ElapsedPerSecNano / 1000ULL));
4833	u64FrameStartNanoTS = u64NanoTS;
4834	cFrames = 0;
4835	u64ElapsedPerSecNano = 0;
4836	}
4837	}
4838	break;
4839	}
4840
4841	case SVGA_3D_CMD_CONTEXT_DEFINE:
4842	{
4843	SVGA3dCmdDefineContext pCmd = (SVGA3dCmdDefineContext )pu32Cmd;
4844	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4845	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDefine);
4846
4847	rc = vmsvga3dContextDefine(pThisCC, pCmd->cid);
4848	break;
4849	}
4850
4851	case SVGA_3D_CMD_CONTEXT_DESTROY:
4852	{
4853	SVGA3dCmdDestroyContext pCmd = (SVGA3dCmdDestroyContext )pu32Cmd;
4854	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4855	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dContextDestroy);
4856
4857	rc = vmsvga3dContextDestroy(pThisCC, pCmd->cid);
4858	break;
4859	}
4860
4861	case SVGA_3D_CMD_SETTRANSFORM:
4862	{
4863	SVGA3dCmdSetTransform pCmd = (SVGA3dCmdSetTransform )pu32Cmd;
4864	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4865	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTransform);
4866
4867	rc = vmsvga3dSetTransform(pThisCC, pCmd->cid, pCmd->type, pCmd->matrix);
4868	break;
4869	}
4870
4871	case SVGA_3D_CMD_SETZRANGE:
4872	{
4873	SVGA3dCmdSetZRange pCmd = (SVGA3dCmdSetZRange )pu32Cmd;
4874	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4875	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetZRange);
4876
4877	rc = vmsvga3dSetZRange(pThisCC, pCmd->cid, pCmd->zRange);
4878	break;
4879	}
4880
4881	case SVGA_3D_CMD_SETRENDERSTATE:
4882	{
4883	uint32_t cRenderStates;
4884	SVGA3dCmdSetRenderState pCmd = (SVGA3dCmdSetRenderState )pu32Cmd;
4885	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4886	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderState);
4887
4888	cRenderStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
4889	rc = vmsvga3dSetRenderState(pThisCC, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
4890	break;
4891	}
4892
4893	case SVGA_3D_CMD_SETRENDERTARGET:
4894	{
4895	SVGA3dCmdSetRenderTarget pCmd = (SVGA3dCmdSetRenderTarget )pu32Cmd;
4896	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4897	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetRenderTarget);
4898
4899	rc = vmsvga3dSetRenderTarget(pThisCC, pCmd->cid, pCmd->type, pCmd->target);
4900	break;
4901	}
4902
4903	case SVGA_3D_CMD_SETTEXTURESTATE:
4904	{
4905	uint32_t cTextureStates;
4906	SVGA3dCmdSetTextureState pCmd = (SVGA3dCmdSetTextureState )pu32Cmd;
4907	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4908	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetTextureState);
4909
4910	cTextureStates = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
4911	rc = vmsvga3dSetTextureState(pThisCC, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
4912	break;
4913	}
4914
4915	case SVGA_3D_CMD_SETMATERIAL:
4916	{
4917	SVGA3dCmdSetMaterial pCmd = (SVGA3dCmdSetMaterial )pu32Cmd;
4918	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4919	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetMaterial);
4920
4921	rc = vmsvga3dSetMaterial(pThisCC, pCmd->cid, pCmd->face, &pCmd->material);
4922	break;
4923	}
4924
4925	case SVGA_3D_CMD_SETLIGHTDATA:
4926	{
4927	SVGA3dCmdSetLightData pCmd = (SVGA3dCmdSetLightData )pu32Cmd;
4928	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4929	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightData);
4930
4931	rc = vmsvga3dSetLightData(pThisCC, pCmd->cid, pCmd->index, &pCmd->data);
4932	break;
4933	}
4934
4935	case SVGA_3D_CMD_SETLIGHTENABLED:
4936	{
4937	SVGA3dCmdSetLightEnabled pCmd = (SVGA3dCmdSetLightEnabled )pu32Cmd;
4938	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4939	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetLightEnable);
4940
4941	rc = vmsvga3dSetLightEnabled(pThisCC, pCmd->cid, pCmd->index, pCmd->enabled);
4942	break;
4943	}
4944
4945	case SVGA_3D_CMD_SETVIEWPORT:
4946	{
4947	SVGA3dCmdSetViewport pCmd = (SVGA3dCmdSetViewport )pu32Cmd;
4948	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4949	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetViewPort);
4950
4951	rc = vmsvga3dSetViewPort(pThisCC, pCmd->cid, &pCmd->rect);
4952	break;
4953	}
4954
4955	case SVGA_3D_CMD_SETCLIPPLANE:
4956	{
4957	SVGA3dCmdSetClipPlane pCmd = (SVGA3dCmdSetClipPlane )pu32Cmd;
4958	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4959	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetClipPlane);
4960
4961	rc = vmsvga3dSetClipPlane(pThisCC, pCmd->cid, pCmd->index, pCmd->plane);
4962	break;
4963	}
4964
4965	case SVGA_3D_CMD_CLEAR:
4966	{
4967	SVGA3dCmdClear pCmd = (SVGA3dCmdClear )pu32Cmd;
4968	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4969	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dClear);
4970
4971	uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dRect);
4972	rc = vmsvga3dCommandClear(pThisCC, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
4973	break;
4974	}
4975
4976	case SVGA_3D_CMD_PRESENT:
4977	case SVGA_3D_CMD_PRESENT_READBACK: /** @todo SVGA_3D_CMD_PRESENT_READBACK isn't quite the same as present... */
4978	{
4979	SVGA3dCmdPresent pCmd = (SVGA3dCmdPresent )pu32Cmd;
4980	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4981	if ((unsigned)enmCmdId == SVGA_3D_CMD_PRESENT)
4982	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresent);
4983	else
4984	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dPresentReadBack);
4985
4986	uint32_t cRects = (cbCmd - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
4987
4988	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dPresentProf, a);
4989	rc = vmsvga3dCommandPresent(pThis, pThisCC, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
4990	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dPresentProf, a);
4991	break;
4992	}
4993
4994	case SVGA_3D_CMD_SHADER_DEFINE:
4995	{
4996	SVGA3dCmdDefineShader pCmd = (SVGA3dCmdDefineShader )pu32Cmd;
4997	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
4998	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDefine);
4999
5000	uint32_t cbData = (cbCmd - sizeof(*pCmd));
5001	rc = vmsvga3dShaderDefine(pThisCC, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
5002	break;
5003	}
5004
5005	case SVGA_3D_CMD_SHADER_DESTROY:
5006	{
5007	SVGA3dCmdDestroyShader pCmd = (SVGA3dCmdDestroyShader )pu32Cmd;
5008	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5009	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dShaderDestroy);
5010
5011	rc = vmsvga3dShaderDestroy(pThisCC, pCmd->cid, pCmd->shid, pCmd->type);
5012	break;
5013	}
5014
5015	case SVGA_3D_CMD_SET_SHADER:
5016	{
5017	SVGA3dCmdSetShader pCmd = (SVGA3dCmdSetShader )pu32Cmd;
5018	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5019	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShader);
5020
5021	rc = vmsvga3dShaderSet(pThisCC, NULL, pCmd->cid, pCmd->type, pCmd->shid);
5022	break;
5023	}
5024
5025	case SVGA_3D_CMD_SET_SHADER_CONST:
5026	{
5027	SVGA3dCmdSetShaderConst pCmd = (SVGA3dCmdSetShaderConst )pu32Cmd;
5028	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5029	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetShaderConst);
5030
5031	uint32_t cRegisters = (cbCmd - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
5032	rc = vmsvga3dShaderSetConst(pThisCC, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
5033	break;
5034	}
5035
5036	case SVGA_3D_CMD_DRAW_PRIMITIVES:
5037	{
5038	SVGA3dCmdDrawPrimitives pCmd = (SVGA3dCmdDrawPrimitives )pu32Cmd;
5039	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5040	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDrawPrimitives);
5041
5042	AssertBreak(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
5043	AssertBreak(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
5044	uint32_t const cbRangesAndVertexDecls = pCmd->numVertexDecls * sizeof(SVGA3dVertexDecl)
5045	+ pCmd->numRanges * sizeof(SVGA3dPrimitiveRange);
5046	ASSERT_GUEST_BREAK(cbRangesAndVertexDecls <= cbCmd - sizeof(*pCmd));
5047
5048	uint32_t cVertexDivisor = (cbCmd - sizeof(*pCmd) - cbRangesAndVertexDecls) / sizeof(uint32_t);
5049	AssertBreak(!cVertexDivisor \|\| cVertexDivisor == pCmd->numVertexDecls);
5050
5051	RT_UNTRUSTED_VALIDATED_FENCE();
5052
5053	SVGA3dVertexDecl pVertexDecl = (SVGA3dVertexDecl )(pCmd + 1);
5054	SVGA3dPrimitiveRange pNumRange = (SVGA3dPrimitiveRange )&pVertexDecl[pCmd->numVertexDecls];
5055	SVGA3dVertexDivisor pVertexDivisor = cVertexDivisor ? (SVGA3dVertexDivisor )&pNumRange[pCmd->numRanges] : NULL;
5056
5057	STAM_PROFILE_START(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5058	rc = vmsvga3dDrawPrimitives(pThisCC, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges,
5059	pNumRange, cVertexDivisor, pVertexDivisor);
5060	STAM_PROFILE_STOP(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, a);
5061	break;
5062	}
5063
5064	case SVGA_3D_CMD_SETSCISSORRECT:
5065	{
5066	SVGA3dCmdSetScissorRect pCmd = (SVGA3dCmdSetScissorRect )pu32Cmd;
5067	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5068	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dSetScissorRect);
5069
5070	rc = vmsvga3dSetScissorRect(pThisCC, pCmd->cid, &pCmd->rect);
5071	break;
5072	}
5073
5074	case SVGA_3D_CMD_BEGIN_QUERY:
5075	{
5076	SVGA3dCmdBeginQuery pCmd = (SVGA3dCmdBeginQuery )pu32Cmd;
5077	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5078	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dBeginQuery);
5079
5080	rc = vmsvga3dQueryBegin(pThisCC, pCmd->cid, pCmd->type);
5081	break;
5082	}
5083
5084	case SVGA_3D_CMD_END_QUERY:
5085	{
5086	SVGA3dCmdEndQuery pCmd = (SVGA3dCmdEndQuery )pu32Cmd;
5087	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5088	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dEndQuery);
5089
5090	rc = vmsvga3dQueryEnd(pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5091	break;
5092	}
5093
5094	case SVGA_3D_CMD_WAIT_FOR_QUERY:
5095	{
5096	SVGA3dCmdWaitForQuery pCmd = (SVGA3dCmdWaitForQuery )pu32Cmd;
5097	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5098	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dWaitForQuery);
5099
5100	rc = vmsvga3dQueryWait(pThis, pThisCC, pCmd->cid, pCmd->type, pCmd->guestResult);
5101	break;
5102	}
5103
5104	case SVGA_3D_CMD_GENERATE_MIPMAPS:
5105	{
5106	SVGA3dCmdGenerateMipmaps pCmd = (SVGA3dCmdGenerateMipmaps )pu32Cmd;
5107	VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
5108	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dGenerateMipmaps);
5109
5110	rc = vmsvga3dGenerateMipmaps(pThisCC, pCmd->sid, pCmd->filter);
5111	break;
5112	}
5113
5114	case SVGA_3D_CMD_ACTIVATE_SURFACE:
5115	/* context id + surface id? */
5116	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dActivateSurface);
5117	break;
5118	case SVGA_3D_CMD_DEACTIVATE_SURFACE:
5119	/* context id + surface id? */
5120	STAM_REL_COUNTER_INC(&pSVGAState->StatR3Cmd3dDeactivateSurface);
5121	break;
5122
5123	default:
5124	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5125	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5126	break;
5127	}
5128	}
5129	else
5130	# endif // VBOX_WITH_VMSVGA3D
5131	{
5132	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
5133	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
5134	}
5135	}
5136
5137	/* Go to the next slot */
5138	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
5139	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
5140	if (offCurrentCmd >= offFifoMax)
5141	{
5142	offCurrentCmd -= offFifoMax - offFifoMin;
5143	Assert(offCurrentCmd >= offFifoMin);
5144	Assert(offCurrentCmd < offFifoMax);
5145	}
5146	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
5147	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
5148
5149	/*
5150	* Raise IRQ if required. Must enter the critical section here
5151	* before making final decisions here, otherwise cubebench and
5152	* others may end up waiting forever.
5153	*/
5154	if ( u32IrqStatus
5155	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
5156	{
5157	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
5158	AssertRC(rc2);
5159
5160	/* FIFO progress might trigger an interrupt. */
5161	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5162	{
5163	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5164	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5165	}
5166
5167	/* Unmasked IRQ pending? */
5168	if (pThis->svga.u32IrqMask & u32IrqStatus)
5169	{
5170	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5171	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5172	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5173	}
5174
5175	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5176	}
5177	}
5178
5179	/* If really done, clear the busy flag. */
5180	if (fDone)
5181	{
5182	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5183	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5184	}
5185	}
5186
5187	/*
5188	* Free the bounce buffer. (There are no returns above!)
5189	*/
5190	RTMemFree(pbBounceBuf);
5191
5192	return VINF_SUCCESS;
5193	}
5194
5195	#undef VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK
5196	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5197	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5198
5199	#ifdef VBOX_WITH_VMSVGA3D
5200	/**
5201	* Free the specified GMR
5202	*
5203	* @param pThisCC The VGA/VMSVGA state for ring-3.
5204	* @param idGMR GMR id
5205	*/
5206	static void vmsvgaR3GmrFree(PVGASTATECC pThisCC, uint32_t idGMR)
5207	{
5208	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5209
5210	/* Free the old descriptor if present. */
5211	PGMR pGMR = &pSVGAState->paGMR[idGMR];
5212	if ( pGMR->numDescriptors
5213	\|\| pGMR->paDesc /* needed till we implement SVGA_REMAP_GMR2_VIA_GMR */)
5214	{
5215	# ifdef DEBUG_GMR_ACCESS
5216	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pThisCC->pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3DeregisterGmr, 2, pDevIns, idGMR);
5217	# endif
5218
5219	Assert(pGMR->paDesc);
5220	RTMemFree(pGMR->paDesc);
5221	pGMR->paDesc = NULL;
5222	pGMR->numDescriptors = 0;
5223	pGMR->cbTotal = 0;
5224	pGMR->cMaxPages = 0;
5225	}
5226	Assert(!pGMR->cMaxPages);
5227	Assert(!pGMR->cbTotal);
5228	}
5229	#endif /* VBOX_WITH_VMSVGA3D */
5230
5231	/**
5232	* Copy between a GMR and a host memory buffer.
5233	*
5234	* @returns VBox status code.
5235	* @param pThis The shared VGA/VMSVGA instance data.
5236	* @param pThisCC The VGA/VMSVGA state for ring-3.
5237	* @param enmTransferType Transfer type (read/write)
5238	* @param pbHstBuf Host buffer pointer (valid)
5239	* @param cbHstBuf Size of host buffer (valid)
5240	* @param offHst Host buffer offset of the first scanline
5241	* @param cbHstPitch Destination buffer pitch
5242	* @param gstPtr GMR description
5243	* @param offGst Guest buffer offset of the first scanline
5244	* @param cbGstPitch Guest buffer pitch
5245	* @param cbWidth Width in bytes to copy
5246	* @param cHeight Number of scanllines to copy
5247	*/
5248	int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
5249	uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
5250	SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
5251	uint32_t cbWidth, uint32_t cHeight)
5252	{
5253	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5254	PPDMDEVINS pDevIns = pThisCC->pDevIns; /* simpler */
5255	int rc;
5256
5257	LogFunc(("%s host %p size=%d offset %d pitch=%d; guest gmr=%#x:%#x offset=%d pitch=%d cbWidth=%d cHeight=%d\n",
5258	enmTransferType == SVGA3D_READ_HOST_VRAM ? "WRITE" : "READ", /* GMR op: READ host VRAM means WRITE GMR */
5259	pbHstBuf, cbHstBuf, offHst, cbHstPitch,
5260	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cbWidth, cHeight));
5261	AssertReturn(cbWidth && cHeight, VERR_INVALID_PARAMETER);
5262
5263	PGMR pGMR;
5264	uint32_t cbGmr; /* The GMR size in bytes. */
5265	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5266	{
5267	pGMR = NULL;
5268	cbGmr = pThis->vram_size;
5269	}
5270	else
5271	{
5272	AssertReturn(gstPtr.gmrId < pThis->svga.cGMR, VERR_INVALID_PARAMETER);
5273	RT_UNTRUSTED_VALIDATED_FENCE();
5274	pGMR = &pSVGAState->paGMR[gstPtr.gmrId];
5275	cbGmr = pGMR->cbTotal;
5276	}
5277
5278	/*
5279	* GMR
5280	*/
5281	/* Calculate GMR offset of the data to be copied. */
5282	AssertMsgReturn(gstPtr.offset < cbGmr,
5283	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5284	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5285	VERR_INVALID_PARAMETER);
5286	RT_UNTRUSTED_VALIDATED_FENCE();
5287	AssertMsgReturn(offGst < cbGmr - gstPtr.offset,
5288	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5289	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5290	VERR_INVALID_PARAMETER);
5291	RT_UNTRUSTED_VALIDATED_FENCE();
5292	uint32_t const offGmr = offGst + gstPtr.offset; /* Offset in the GMR, where the first scanline is located. */
5293
5294	/* Verify that cbWidth is less than scanline and fits into the GMR. */
5295	uint32_t const cbGmrScanline = cbGstPitch > 0 ? cbGstPitch : -cbGstPitch;
5296	AssertMsgReturn(cbGmrScanline != 0,
5297	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5298	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5299	VERR_INVALID_PARAMETER);
5300	RT_UNTRUSTED_VALIDATED_FENCE();
5301	AssertMsgReturn(cbWidth <= cbGmrScanline,
5302	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5303	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5304	VERR_INVALID_PARAMETER);
5305	AssertMsgReturn(cbWidth <= cbGmr - offGmr,
5306	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5307	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5308	VERR_INVALID_PARAMETER);
5309	RT_UNTRUSTED_VALIDATED_FENCE();
5310
5311	/* How many bytes are available for the data in the GMR. */
5312	uint32_t const cbGmrLeft = cbGstPitch > 0 ? cbGmr - offGmr : offGmr + cbWidth;
5313
5314	/* How many scanlines would fit into the available data. */
5315	uint32_t cGmrScanlines = cbGmrLeft / cbGmrScanline;
5316	uint32_t const cbGmrLastScanline = cbGmrLeft - cGmrScanlines * cbGmrScanline; /* Slack space. */
5317	if (cbWidth <= cbGmrLastScanline)
5318	++cGmrScanlines;
5319
5320	if (cHeight > cGmrScanlines)
5321	cHeight = cGmrScanlines;
5322
5323	AssertMsgReturn(cHeight > 0,
5324	("gmr=%#x:%#x offGst=%#x cbGstPitch=%#x cHeight=%#x cbWidth=%#x cbGmr=%#x\n",
5325	gstPtr.gmrId, gstPtr.offset, offGst, cbGstPitch, cHeight, cbWidth, cbGmr),
5326	VERR_INVALID_PARAMETER);
5327	RT_UNTRUSTED_VALIDATED_FENCE();
5328
5329	/*
5330	* Host buffer.
5331	*/
5332	AssertMsgReturn(offHst < cbHstBuf,
5333	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5334	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5335	VERR_INVALID_PARAMETER);
5336
5337	/* Verify that cbWidth is less than scanline and fits into the buffer. */
5338	uint32_t const cbHstScanline = cbHstPitch > 0 ? cbHstPitch : -cbHstPitch;
5339	AssertMsgReturn(cbHstScanline != 0,
5340	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5341	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5342	VERR_INVALID_PARAMETER);
5343	AssertMsgReturn(cbWidth <= cbHstScanline,
5344	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5345	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5346	VERR_INVALID_PARAMETER);
5347	AssertMsgReturn(cbWidth <= cbHstBuf - offHst,
5348	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5349	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5350	VERR_INVALID_PARAMETER);
5351
5352	/* How many bytes are available for the data in the buffer. */
5353	uint32_t const cbHstLeft = cbHstPitch > 0 ? cbHstBuf - offHst : offHst + cbWidth;
5354
5355	/* How many scanlines would fit into the available data. */
5356	uint32_t cHstScanlines = cbHstLeft / cbHstScanline;
5357	uint32_t const cbHstLastScanline = cbHstLeft - cHstScanlines * cbHstScanline; /* Slack space. */
5358	if (cbWidth <= cbHstLastScanline)
5359	++cHstScanlines;
5360
5361	if (cHeight > cHstScanlines)
5362	cHeight = cHstScanlines;
5363
5364	AssertMsgReturn(cHeight > 0,
5365	("buffer=%p size %d offHst=%d cbHstPitch=%d cHeight=%d cbWidth=%d\n",
5366	pbHstBuf, cbHstBuf, offHst, cbHstPitch, cHeight, cbWidth),
5367	VERR_INVALID_PARAMETER);
5368
5369	uint8_t *pbHst = pbHstBuf + offHst;
5370
5371	/* Shortcut for the framebuffer. */
5372	if (gstPtr.gmrId == SVGA_GMR_FRAMEBUFFER)
5373	{
5374	uint8_t *pbGst = pThisCC->pbVRam + offGmr;
5375
5376	uint8_t const *pbSrc;
5377	int32_t cbSrcPitch;
5378	uint8_t *pbDst;
5379	int32_t cbDstPitch;
5380
5381	if (enmTransferType == SVGA3D_READ_HOST_VRAM)
5382	{
5383	pbSrc = pbHst;
5384	cbSrcPitch = cbHstPitch;
5385	pbDst = pbGst;
5386	cbDstPitch = cbGstPitch;
5387	}
5388	else
5389	{
5390	pbSrc = pbGst;
5391	cbSrcPitch = cbGstPitch;
5392	pbDst = pbHst;
5393	cbDstPitch = cbHstPitch;
5394	}
5395
5396	if ( cbWidth == (uint32_t)cbGstPitch
5397	&& cbGstPitch == cbHstPitch)
5398	{
5399	/* Entire scanlines, positive pitch. */
5400	memcpy(pbDst, pbSrc, cbWidth * cHeight);
5401	}
5402	else
5403	{
5404	for (uint32_t i = 0; i < cHeight; ++i)
5405	{
5406	memcpy(pbDst, pbSrc, cbWidth);
5407
5408	pbDst += cbDstPitch;
5409	pbSrc += cbSrcPitch;
5410	}
5411	}
5412	return VINF_SUCCESS;
5413	}
5414
5415	AssertPtrReturn(pGMR, VERR_INVALID_PARAMETER);
5416	AssertReturn(pGMR->numDescriptors > 0, VERR_INVALID_PARAMETER);
5417
5418	PVMSVGAGMRDESCRIPTOR const paDesc = pGMR->paDesc; /* Local copy of the pointer. */
5419	uint32_t iDesc = 0; /* Index in the descriptor array. */
5420	uint32_t offDesc = 0; /* GMR offset of the current descriptor. */
5421	uint32_t offGmrScanline = offGmr; /* GMR offset of the scanline which is being copied. */
5422	uint8_t pbHstScanline = pbHst; / Host address of the scanline which is being copied. */
5423	for (uint32_t i = 0; i < cHeight; ++i)
5424	{
5425	uint32_t cbCurrentWidth = cbWidth;
5426	uint32_t offGmrCurrent = offGmrScanline;
5427	uint8_t *pbCurrentHost = pbHstScanline;
5428
5429	/* Find the right descriptor */
5430	while (offDesc + paDesc[iDesc].numPages * PAGE_SIZE <= offGmrCurrent)
5431	{
5432	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5433	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
5434	++iDesc;
5435	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5436	}
5437
5438	while (cbCurrentWidth)
5439	{
5440	uint32_t cbToCopy;
5441
5442	if (offGmrCurrent + cbCurrentWidth <= offDesc + paDesc[iDesc].numPages * PAGE_SIZE)
5443	{
5444	cbToCopy = cbCurrentWidth;
5445	}
5446	else
5447	{
5448	cbToCopy = (offDesc + paDesc[iDesc].numPages * PAGE_SIZE - offGmrCurrent);
5449	AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
5450	}
5451
5452	RTGCPHYS const GCPhys = paDesc[iDesc].GCPhys + offGmrCurrent - offDesc;
5453
5454	Log5Func(("%s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", GCPhys));
5455
5456	if (enmTransferType == SVGA3D_WRITE_HOST_VRAM)
5457	rc = PDMDevHlpPhysRead(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5458	else
5459	rc = PDMDevHlpPhysWrite(pDevIns, GCPhys, pbCurrentHost, cbToCopy);
5460	AssertRCBreak(rc);
5461
5462	cbCurrentWidth -= cbToCopy;
5463	offGmrCurrent += cbToCopy;
5464	pbCurrentHost += cbToCopy;
5465
5466	/* Go to the next descriptor if there's anything left. */
5467	if (cbCurrentWidth)
5468	{
5469	offDesc += paDesc[iDesc].numPages * PAGE_SIZE;
5470	AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR);
5471	++iDesc;
5472	AssertReturn(iDesc < pGMR->numDescriptors, VERR_INTERNAL_ERROR);
5473	}
5474	}
5475
5476	offGmrScanline += cbGstPitch;
5477	pbHstScanline += cbHstPitch;
5478	}
5479
5480	return VINF_SUCCESS;
5481	}
5482
5483
5484	/**
5485	* Unsigned coordinates in pBox. Clip to [0; pSizeSrc), [0; pSizeDest).
5486	*
5487	* @param pSizeSrc Source surface dimensions.
5488	* @param pSizeDest Destination surface dimensions.
5489	* @param pBox Coordinates to be clipped.
5490	*/
5491	void vmsvgaR3ClipCopyBox(const SVGA3dSize pSizeSrc, const SVGA3dSize pSizeDest, SVGA3dCopyBox *pBox)
5492	{
5493	/* Src x, w */
5494	if (pBox->srcx > pSizeSrc->width)
5495	pBox->srcx = pSizeSrc->width;
5496	if (pBox->w > pSizeSrc->width - pBox->srcx)
5497	pBox->w = pSizeSrc->width - pBox->srcx;
5498
5499	/* Src y, h */
5500	if (pBox->srcy > pSizeSrc->height)
5501	pBox->srcy = pSizeSrc->height;
5502	if (pBox->h > pSizeSrc->height - pBox->srcy)
5503	pBox->h = pSizeSrc->height - pBox->srcy;
5504
5505	/* Src z, d */
5506	if (pBox->srcz > pSizeSrc->depth)
5507	pBox->srcz = pSizeSrc->depth;
5508	if (pBox->d > pSizeSrc->depth - pBox->srcz)
5509	pBox->d = pSizeSrc->depth - pBox->srcz;
5510
5511	/* Dest x, w */
5512	if (pBox->x > pSizeDest->width)
5513	pBox->x = pSizeDest->width;
5514	if (pBox->w > pSizeDest->width - pBox->x)
5515	pBox->w = pSizeDest->width - pBox->x;
5516
5517	/* Dest y, h */
5518	if (pBox->y > pSizeDest->height)
5519	pBox->y = pSizeDest->height;
5520	if (pBox->h > pSizeDest->height - pBox->y)
5521	pBox->h = pSizeDest->height - pBox->y;
5522
5523	/* Dest z, d */
5524	if (pBox->z > pSizeDest->depth)
5525	pBox->z = pSizeDest->depth;
5526	if (pBox->d > pSizeDest->depth - pBox->z)
5527	pBox->d = pSizeDest->depth - pBox->z;
5528	}
5529
5530	/**
5531	* Unsigned coordinates in pBox. Clip to [0; pSize).
5532	*
5533	* @param pSize Source surface dimensions.
5534	* @param pBox Coordinates to be clipped.
5535	*/
5536	void vmsvgaR3ClipBox(const SVGA3dSize pSize, SVGA3dBox pBox)
5537	{
5538	/* x, w */
5539	if (pBox->x > pSize->width)
5540	pBox->x = pSize->width;
5541	if (pBox->w > pSize->width - pBox->x)
5542	pBox->w = pSize->width - pBox->x;
5543
5544	/* y, h */
5545	if (pBox->y > pSize->height)
5546	pBox->y = pSize->height;
5547	if (pBox->h > pSize->height - pBox->y)
5548	pBox->h = pSize->height - pBox->y;
5549
5550	/* z, d */
5551	if (pBox->z > pSize->depth)
5552	pBox->z = pSize->depth;
5553	if (pBox->d > pSize->depth - pBox->z)
5554	pBox->d = pSize->depth - pBox->z;
5555	}
5556
5557	/**
5558	* Clip.
5559	*
5560	* @param pBound Bounding rectangle.
5561	* @param pRect Rectangle to be clipped.
5562	*/
5563	void vmsvgaR3ClipRect(SVGASignedRect const pBound, SVGASignedRect pRect)
5564	{
5565	int32_t left;
5566	int32_t top;
5567	int32_t right;
5568	int32_t bottom;
5569
5570	/* Right order. */
5571	Assert(pBound->left <= pBound->right && pBound->top <= pBound->bottom);
5572	if (pRect->left < pRect->right)
5573	{
5574	left = pRect->left;
5575	right = pRect->right;
5576	}
5577	else
5578	{
5579	left = pRect->right;
5580	right = pRect->left;
5581	}
5582	if (pRect->top < pRect->bottom)
5583	{
5584	top = pRect->top;
5585	bottom = pRect->bottom;
5586	}
5587	else
5588	{
5589	top = pRect->bottom;
5590	bottom = pRect->top;
5591	}
5592
5593	if (left < pBound->left)
5594	left = pBound->left;
5595	if (right < pBound->left)
5596	right = pBound->left;
5597
5598	if (left > pBound->right)
5599	left = pBound->right;
5600	if (right > pBound->right)
5601	right = pBound->right;
5602
5603	if (top < pBound->top)
5604	top = pBound->top;
5605	if (bottom < pBound->top)
5606	bottom = pBound->top;
5607
5608	if (top > pBound->bottom)
5609	top = pBound->bottom;
5610	if (bottom > pBound->bottom)
5611	bottom = pBound->bottom;
5612
5613	pRect->left = left;
5614	pRect->right = right;
5615	pRect->top = top;
5616	pRect->bottom = bottom;
5617	}
5618
5619	/**
5620	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5621	* Unblock the FIFO I/O thread so it can respond to a state change.}
5622	*/
5623	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5624	{
5625	RT_NOREF(pDevIns);
5626	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5627	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5628	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5629	}
5630
5631	/**
5632	* Enables or disables dirty page tracking for the framebuffer
5633	*
5634	* @param pDevIns The device instance.
5635	* @param pThis The shared VGA/VMSVGA instance data.
5636	* @param fTraces Enable/disable traces
5637	*/
5638	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5639	{
5640	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5641	&& !fTraces)
5642	{
5643	//Assert(pThis->svga.fTraces);
5644	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5645	return;
5646	}
5647
5648	pThis->svga.fTraces = fTraces;
5649	if (pThis->svga.fTraces)
5650	{
5651	unsigned cbFrameBuffer = pThis->vram_size;
5652
5653	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5654	/** @todo How does this work with screens? */
5655	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5656	{
5657	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5658	Assert(pThis->svga.cbScanline);
5659	# endif
5660	/* Hardware enabled; return real framebuffer size .*/
5661	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5662	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5663	}
5664
5665	if (!pThis->svga.fVRAMTracking)
5666	{
5667	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5668	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5669	pThis->svga.fVRAMTracking = true;
5670	}
5671	}
5672	else
5673	{
5674	if (pThis->svga.fVRAMTracking)
5675	{
5676	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5677	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5678	pThis->svga.fVRAMTracking = false;
5679	}
5680	}
5681	}
5682
5683	/**
5684	* @callback_method_impl{FNPCIIOREGIONMAP}
5685	*/
5686	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5687	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5688	{
5689	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5690	int rc;
5691	RT_NOREF(pPciDev);
5692	Assert(pPciDev == pDevIns->apPciDevs[0]);
5693
5694	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5695	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5696	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5697	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5698	, VERR_INTERNAL_ERROR);
5699	if (GCPhysAddress != NIL_RTGCPHYS)
5700	{
5701	/*
5702	* Mapping the FIFO RAM.
5703	*/
5704	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5705	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5706	AssertRC(rc);
5707
5708	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5709	if (RT_SUCCESS(rc))
5710	{
5711	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5712	# ifdef DEBUG_FIFO_ACCESS
5713	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5714	# else
5715	GCPhysAddress + PAGE_SIZE - 1,
5716	# endif
5717	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5718	"VMSVGA FIFO");
5719	AssertRC(rc);
5720	}
5721	# endif
5722	if (RT_SUCCESS(rc))
5723	{
5724	pThis->svga.GCPhysFIFO = GCPhysAddress;
5725	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5726	}
5727	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5728	}
5729	else
5730	{
5731	Assert(pThis->svga.GCPhysFIFO);
5732	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5733	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5734	AssertRC(rc);
5735	# else
5736	rc = VINF_SUCCESS;
5737	# endif
5738	pThis->svga.GCPhysFIFO = 0;
5739	}
5740	return rc;
5741	}
5742
5743	# ifdef VBOX_WITH_VMSVGA3D
5744
5745	/**
5746	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5747	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5748	*
5749	* @param pDevIns The device instance.
5750	* @param pThis The The shared VGA/VMSVGA instance data.
5751	* @param pThisCC The VGA/VMSVGA state for ring-3.
5752	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5753	* UINT32_MAX is used, all surfaces are processed.
5754	*/
5755	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5756	{
5757	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5758	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5759	}
5760
5761
5762	/**
5763	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5764	*/
5765	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5766	{
5767	/* There might be a specific surface ID at the start of the
5768	arguments, if not show all surfaces. */
5769	uint32_t sid = UINT32_MAX;
5770	if (pszArgs)
5771	pszArgs = RTStrStripL(pszArgs);
5772	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5773	sid = RTStrToUInt32(pszArgs);
5774
5775	/* Verbose or terse display, we default to verbose. */
5776	bool fVerbose = true;
5777	if (RTStrIStr(pszArgs, "terse"))
5778	fVerbose = false;
5779
5780	/* The size of the ascii art (x direction, y is 3/4 of x). */
5781	uint32_t cxAscii = 80;
5782	if (RTStrIStr(pszArgs, "gigantic"))
5783	cxAscii = 300;
5784	else if (RTStrIStr(pszArgs, "huge"))
5785	cxAscii = 180;
5786	else if (RTStrIStr(pszArgs, "big"))
5787	cxAscii = 132;
5788	else if (RTStrIStr(pszArgs, "normal"))
5789	cxAscii = 80;
5790	else if (RTStrIStr(pszArgs, "medium"))
5791	cxAscii = 64;
5792	else if (RTStrIStr(pszArgs, "small"))
5793	cxAscii = 48;
5794	else if (RTStrIStr(pszArgs, "tiny"))
5795	cxAscii = 24;
5796
5797	/* Y invert the image when producing the ASCII art. */
5798	bool fInvY = false;
5799	if (RTStrIStr(pszArgs, "invy"))
5800	fInvY = true;
5801
5802	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5803	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5804	}
5805
5806
5807	/**
5808	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5809	*/
5810	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5811	{
5812	/* pszArg = "sid[>dir]"
5813	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5814	*/
5815	char *pszBitmapPath = NULL;
5816	uint32_t sid = UINT32_MAX;
5817	if (pszArgs)
5818	pszArgs = RTStrStripL(pszArgs);
5819	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5820	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5821	if ( pszBitmapPath
5822	&& *pszBitmapPath == '>')
5823	++pszBitmapPath;
5824
5825	const bool fVerbose = true;
5826	const uint32_t cxAscii = 0; /* No ASCII */
5827	const bool fInvY = false; /* Do not invert. */
5828	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5829	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5830	}
5831
5832	/**
5833	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5834	*/
5835	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5836	{
5837	/* There might be a specific surface ID at the start of the
5838	arguments, if not show all contexts. */
5839	uint32_t sid = UINT32_MAX;
5840	if (pszArgs)
5841	pszArgs = RTStrStripL(pszArgs);
5842	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5843	sid = RTStrToUInt32(pszArgs);
5844
5845	/* Verbose or terse display, we default to verbose. */
5846	bool fVerbose = true;
5847	if (RTStrIStr(pszArgs, "terse"))
5848	fVerbose = false;
5849
5850	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5851	}
5852	# endif /* VBOX_WITH_VMSVGA3D */
5853
5854	/**
5855	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5856	*/
5857	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5858	{
5859	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5860	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5861	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5862	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5863	RT_NOREF(pszArgs);
5864
5865	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5866	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5867	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5868	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5869	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5870	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5871	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5872	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5873	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5874	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5875	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5876	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5877	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5878	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5879	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5880	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5881	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5882	pHlp->pfnPrintf(pHlp, "Capabilites reg: %#x\n", pThis->svga.u32RegCaps);
5883	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5884	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5885	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5886	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5887	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5888	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5889	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5890
5891	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5892	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5893	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5894	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5895
5896	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5897	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5898
5899	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5900	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5901
5902	# ifdef VBOX_WITH_VMSVGA3D
5903	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5904	# endif
5905	if (pThisCC->pDrv)
5906	{
5907	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5908	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5909	}
5910
5911	/* Dump screen information. */
5912	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5913	{
5914	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5915	if (pScreen)
5916	{
5917	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5918	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5919	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5920	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5921	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5922	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5923	{
5924	pHlp->pfnPrintf(pHlp, " (");
5925	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5926	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5927	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5928	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5929	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5930	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5931	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5932	pHlp->pfnPrintf(pHlp, " BLANKING");
5933	pHlp->pfnPrintf(pHlp, " )");
5934	}
5935	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5936	}
5937	}
5938
5939	}
5940
5941	/**
5942	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5943	*/
5944	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5945	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5946	{
5947	RT_NOREF(uPass);
5948
5949	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5950	int rc;
5951
5952	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5953	{
5954	uint32_t cScreens = 0;
5955	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5956	AssertRCReturn(rc, rc);
5957	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5958	("cScreens=%#x\n", cScreens),
5959	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5960
5961	for (uint32_t i = 0; i < cScreens; ++i)
5962	{
5963	VMSVGASCREENOBJECT screen;
5964	RT_ZERO(screen);
5965
5966	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5967	AssertLogRelRCReturn(rc, rc);
5968
5969	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5970	{
5971	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5972	*pScreen = screen;
5973	pScreen->fModified = true;
5974	}
5975	else
5976	{
5977	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5978	}
5979	}
5980	}
5981	else
5982	{
5983	/* Try to setup at least the first screen. */
5984	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5985	pScreen->fDefined = true;
5986	pScreen->fModified = true;
5987	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5988	pScreen->idScreen = 0;
5989	pScreen->xOrigin = 0;
5990	pScreen->yOrigin = 0;
5991	pScreen->offVRAM = pThis->svga.uScreenOffset;
5992	pScreen->cbPitch = pThis->svga.cbScanline;
5993	pScreen->cWidth = pThis->svga.uWidth;
5994	pScreen->cHeight = pThis->svga.uHeight;
5995	pScreen->cBpp = pThis->svga.uBpp;
5996	}
5997
5998	return VINF_SUCCESS;
5999	}
6000
6001	/**
6002	* @copydoc FNSSMDEVLOADEXEC
6003	*/
6004	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6005	{
6006	RT_NOREF(uPass);
6007	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6008	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6009	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6010	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6011	int rc;
6012
6013	/* Load our part of the VGAState */
6014	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6015	AssertRCReturn(rc, rc);
6016
6017	/* Load the VGA framebuffer. */
6018	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
6019	uint32_t cbVgaFramebuffer = _32K;
6020	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
6021	{
6022	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
6023	AssertRCReturn(rc, rc);
6024	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
6025	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
6026	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6027	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
6028	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
6029	}
6030	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
6031	AssertRCReturn(rc, rc);
6032	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
6033	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
6034	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
6035	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
6036
6037	/* Load the VMSVGA state. */
6038	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6039	AssertRCReturn(rc, rc);
6040
6041	/* Load the active cursor bitmaps. */
6042	if (pSVGAState->Cursor.fActive)
6043	{
6044	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
6045	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
6046
6047	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6048	AssertRCReturn(rc, rc);
6049	}
6050
6051	/* Load the GMR state. */
6052	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
6053	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
6054	{
6055	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
6056	AssertRCReturn(rc, rc);
6057	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
6058	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
6059	("cGMR=%#x - expected 256B..1MB\n", cGMR),
6060	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6061	}
6062
6063	if (pThis->svga.cGMR != cGMR)
6064	{
6065	/* Reallocate GMR array. */
6066	Assert(pSVGAState->paGMR != NULL);
6067	RTMemFree(pSVGAState->paGMR);
6068	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
6069	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6070	pThis->svga.cGMR = cGMR;
6071	}
6072
6073	for (uint32_t i = 0; i < cGMR; ++i)
6074	{
6075	PGMR pGMR = &pSVGAState->paGMR[i];
6076
6077	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6078	AssertRCReturn(rc, rc);
6079
6080	if (pGMR->numDescriptors)
6081	{
6082	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
6083	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
6084	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
6085
6086	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6087	{
6088	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6089	AssertRCReturn(rc, rc);
6090	}
6091	}
6092	}
6093
6094	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
6095	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
6096	# endif
6097
6098	VMSVGA_STATE_LOAD LoadState;
6099	LoadState.pSSM = pSSM;
6100	LoadState.uVersion = uVersion;
6101	LoadState.uPass = uPass;
6102	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
6103	AssertLogRelRCReturn(rc, rc);
6104
6105	return VINF_SUCCESS;
6106	}
6107
6108	/**
6109	* Reinit the video mode after the state has been loaded.
6110	*/
6111	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
6112	{
6113	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6114	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6115	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6116
6117	/* Set the active cursor. */
6118	if (pSVGAState->Cursor.fActive)
6119	{
6120	/* We don't store the alpha flag, but we can take a guess that if
6121	* the old register interface was used, the cursor was B&W.
6122	*/
6123	bool fAlpha = pThis->svga.uCursorOn ? false : true;
6124
6125	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
6126	true /fVisible/,
6127	fAlpha,
6128	pSVGAState->Cursor.xHotspot,
6129	pSVGAState->Cursor.yHotspot,
6130	pSVGAState->Cursor.width,
6131	pSVGAState->Cursor.height,
6132	pSVGAState->Cursor.pData);
6133	AssertRC(rc);
6134
6135	if (pThis->svga.uCursorOn)
6136	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
6137	}
6138
6139	/* If the VRAM handler should not be registered, we have to explicitly
6140	* unregister it here!
6141	*/
6142	if (!pThis->svga.fVRAMTracking)
6143	{
6144	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
6145	}
6146
6147	/* Let the FIFO thread deal with changing the mode. */
6148	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
6149
6150	return VINF_SUCCESS;
6151	}
6152
6153	/**
6154	* Portion of SVGA state which must be saved in the FIFO thread.
6155	*/
6156	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
6157	{
6158	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6159	int rc;
6160
6161	/* Save the screen objects. */
6162	/* Count defined screen object. */
6163	uint32_t cScreens = 0;
6164	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
6165	{
6166	if (pSVGAState->aScreens[i].fDefined)
6167	++cScreens;
6168	}
6169
6170	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
6171	AssertLogRelRCReturn(rc, rc);
6172
6173	for (uint32_t i = 0; i < cScreens; ++i)
6174	{
6175	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
6176
6177	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
6178	AssertLogRelRCReturn(rc, rc);
6179	}
6180	return VINF_SUCCESS;
6181	}
6182
6183	/**
6184	* @copydoc FNSSMDEVSAVEEXEC
6185	*/
6186	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6187	{
6188	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6189	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6190	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6191	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6192	int rc;
6193
6194	/* Save our part of the VGAState */
6195	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
6196	AssertLogRelRCReturn(rc, rc);
6197
6198	/* Save the framebuffer backup. */
6199	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
6200	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6201	AssertLogRelRCReturn(rc, rc);
6202
6203	/* Save the VMSVGA state. */
6204	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
6205	AssertLogRelRCReturn(rc, rc);
6206
6207	/* Save the active cursor bitmaps. */
6208	if (pSVGAState->Cursor.fActive)
6209	{
6210	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6211	AssertLogRelRCReturn(rc, rc);
6212	}
6213
6214	/* Save the GMR state */
6215	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
6216	AssertLogRelRCReturn(rc, rc);
6217	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
6218	{
6219	PGMR pGMR = &pSVGAState->paGMR[i];
6220
6221	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
6222	AssertLogRelRCReturn(rc, rc);
6223
6224	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
6225	{
6226	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
6227	AssertLogRelRCReturn(rc, rc);
6228	}
6229	}
6230
6231	/*
6232	* Must save some state (3D in particular) in the FIFO thread.
6233	*/
6234	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
6235	AssertLogRelRCReturn(rc, rc);
6236
6237	return VINF_SUCCESS;
6238	}
6239
6240	/**
6241	* Destructor for PVMSVGAR3STATE structure.
6242	*
6243	* @param pThis The shared VGA/VMSVGA instance data.
6244	* @param pSVGAState Pointer to the structure. It is not deallocated.
6245	*/
6246	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6247	{
6248	# ifndef VMSVGA_USE_EMT_HALT_CODE
6249	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
6250	{
6251	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
6252	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
6253	}
6254	# endif
6255
6256	if (pSVGAState->Cursor.fActive)
6257	{
6258	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
6259	pSVGAState->Cursor.pData = NULL;
6260	pSVGAState->Cursor.fActive = false;
6261	}
6262
6263	if (pSVGAState->paGMR)
6264	{
6265	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
6266	if (pSVGAState->paGMR[i].paDesc)
6267	RTMemFree(pSVGAState->paGMR[i].paDesc);
6268
6269	RTMemFree(pSVGAState->paGMR);
6270	pSVGAState->paGMR = NULL;
6271	}
6272	}
6273
6274	/**
6275	* Constructor for PVMSVGAR3STATE structure.
6276	*
6277	* @returns VBox status code.
6278	* @param pThis The shared VGA/VMSVGA instance data.
6279	* @param pSVGAState Pointer to the structure. It is already allocated.
6280	*/
6281	static int vmsvgaR3StateInit(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
6282	{
6283	int rc = VINF_SUCCESS;
6284	RT_ZERO(*pSVGAState);
6285
6286	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
6287	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
6288
6289	# ifndef VMSVGA_USE_EMT_HALT_CODE
6290	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
6291	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
6292	AssertRCReturn(rc, rc);
6293	# endif
6294
6295	return rc;
6296	}
6297
6298	/**
6299	* Initializes the host capabilities: registers and FIFO.
6300	*
6301	* @returns VBox status code.
6302	* @param pThis The shared VGA/VMSVGA instance data.
6303	* @param pThisCC The VGA/VMSVGA state for ring-3.
6304	*/
6305	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
6306	{
6307	/* Register caps. */
6308	pThis->svga.u32RegCaps = SVGA_CAP_GMR
6309	\| SVGA_CAP_GMR2
6310	\| SVGA_CAP_CURSOR
6311	\| SVGA_CAP_CURSOR_BYPASS
6312	\| SVGA_CAP_CURSOR_BYPASS_2
6313	\| SVGA_CAP_EXTENDED_FIFO
6314	\| SVGA_CAP_IRQMASK
6315	\| SVGA_CAP_PITCHLOCK
6316	\| SVGA_CAP_RECT_COPY
6317	\| SVGA_CAP_TRACES
6318	\| SVGA_CAP_SCREEN_OBJECT_2
6319	\| SVGA_CAP_ALPHA_CURSOR;
6320	# ifdef VBOX_WITH_VMSVGA3D
6321	pThis->svga.u32RegCaps \|= SVGA_CAP_3D;
6322	# endif
6323
6324	/* Clear the FIFO. */
6325	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
6326
6327	/* Setup FIFO capabilities. */
6328	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
6329	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
6330	\| SVGA_FIFO_CAP_GMR2
6331	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
6332	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2
6333	\| SVGA_FIFO_CAP_RESERVE
6334	\| SVGA_FIFO_CAP_PITCHLOCK;
6335
6336	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
6337	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
6338	}
6339
6340	# ifdef VBOX_WITH_VMSVGA3D
6341	/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
6342	static const char * const g_apszVmSvgaDevCapNames[] =
6343	{
6344	"x3D", /* = 0 */
6345	"xMAX_LIGHTS",
6346	"xMAX_TEXTURES",
6347	"xMAX_CLIP_PLANES",
6348	"xVERTEX_SHADER_VERSION",
6349	"xVERTEX_SHADER",
6350	"xFRAGMENT_SHADER_VERSION",
6351	"xFRAGMENT_SHADER",
6352	"xMAX_RENDER_TARGETS",
6353	"xS23E8_TEXTURES",
6354	"xS10E5_TEXTURES",
6355	"xMAX_FIXED_VERTEXBLEND",
6356	"xD16_BUFFER_FORMAT",
6357	"xD24S8_BUFFER_FORMAT",
6358	"xD24X8_BUFFER_FORMAT",
6359	"xQUERY_TYPES",
6360	"xTEXTURE_GRADIENT_SAMPLING",
6361	"rMAX_POINT_SIZE",
6362	"xMAX_SHADER_TEXTURES",
6363	"xMAX_TEXTURE_WIDTH",
6364	"xMAX_TEXTURE_HEIGHT",
6365	"xMAX_VOLUME_EXTENT",
6366	"xMAX_TEXTURE_REPEAT",
6367	"xMAX_TEXTURE_ASPECT_RATIO",
6368	"xMAX_TEXTURE_ANISOTROPY",
6369	"xMAX_PRIMITIVE_COUNT",
6370	"xMAX_VERTEX_INDEX",
6371	"xMAX_VERTEX_SHADER_INSTRUCTIONS",
6372	"xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
6373	"xMAX_VERTEX_SHADER_TEMPS",
6374	"xMAX_FRAGMENT_SHADER_TEMPS",
6375	"xTEXTURE_OPS",
6376	"xSURFACEFMT_X8R8G8B8",
6377	"xSURFACEFMT_A8R8G8B8",
6378	"xSURFACEFMT_A2R10G10B10",
6379	"xSURFACEFMT_X1R5G5B5",
6380	"xSURFACEFMT_A1R5G5B5",
6381	"xSURFACEFMT_A4R4G4B4",
6382	"xSURFACEFMT_R5G6B5",
6383	"xSURFACEFMT_LUMINANCE16",
6384	"xSURFACEFMT_LUMINANCE8_ALPHA8",
6385	"xSURFACEFMT_ALPHA8",
6386	"xSURFACEFMT_LUMINANCE8",
6387	"xSURFACEFMT_Z_D16",
6388	"xSURFACEFMT_Z_D24S8",
6389	"xSURFACEFMT_Z_D24X8",
6390	"xSURFACEFMT_DXT1",
6391	"xSURFACEFMT_DXT2",
6392	"xSURFACEFMT_DXT3",
6393	"xSURFACEFMT_DXT4",
6394	"xSURFACEFMT_DXT5",
6395	"xSURFACEFMT_BUMPX8L8V8U8",
6396	"xSURFACEFMT_A2W10V10U10",
6397	"xSURFACEFMT_BUMPU8V8",
6398	"xSURFACEFMT_Q8W8V8U8",
6399	"xSURFACEFMT_CxV8U8",
6400	"xSURFACEFMT_R_S10E5",
6401	"xSURFACEFMT_R_S23E8",
6402	"xSURFACEFMT_RG_S10E5",
6403	"xSURFACEFMT_RG_S23E8",
6404	"xSURFACEFMT_ARGB_S10E5",
6405	"xSURFACEFMT_ARGB_S23E8",
6406	"xMISSING62",
6407	"xMAX_VERTEX_SHADER_TEXTURES",
6408	"xMAX_SIMULTANEOUS_RENDER_TARGETS",
6409	"xSURFACEFMT_V16U16",
6410	"xSURFACEFMT_G16R16",
6411	"xSURFACEFMT_A16B16G16R16",
6412	"xSURFACEFMT_UYVY",
6413	"xSURFACEFMT_YUY2",
6414	"xMULTISAMPLE_NONMASKABLESAMPLES",
6415	"xMULTISAMPLE_MASKABLESAMPLES",
6416	"xALPHATOCOVERAGE",
6417	"xSUPERSAMPLE",
6418	"xAUTOGENMIPMAPS",
6419	"xSURFACEFMT_NV12",
6420	"xSURFACEFMT_AYUV",
6421	"xMAX_CONTEXT_IDS",
6422	"xMAX_SURFACE_IDS",
6423	"xSURFACEFMT_Z_DF16",
6424	"xSURFACEFMT_Z_DF24",
6425	"xSURFACEFMT_Z_D24S8_INT",
6426	"xSURFACEFMT_ATI1",
6427	"xSURFACEFMT_ATI2", /* 83 */
6428	};
6429
6430	/**
6431	* Initializes the host 3D capabilities in FIFO.
6432	*
6433	* @returns VBox status code.
6434	* @param pThis The shared VGA/VMSVGA instance data.
6435	* @param pThisCC The VGA/VMSVGA state for ring-3.
6436	*/
6437	static void vmsvgaR3InitFifo3DCaps(PVGASTATECC pThisCC)
6438	{
6439	/** @todo Probably query the capabilities once and cache in a memory buffer. */
6440	bool fSavedBuffering = RTLogRelSetBuffering(true);
6441	SVGA3dCapsRecord *pCaps;
6442	SVGA3dCapPair *pData;
6443	uint32_t idxCap = 0;
6444
6445	/* 3d hardware version; latest and greatest */
6446	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
6447	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
6448
6449	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
6450	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
6451	pData = (SVGA3dCapPair *)&pCaps->data;
6452
6453	/* Fill out all 3d capabilities. */
6454	/** @todo The current implementation stores the capabilities in the FIFO.
6455	* Newer VMSVGA uses SVGA_REG_DEV_CAP register to query 3d caps.
6456	* Prerequisite for the new interface is support for SVGA_CAP_GBOBJECTS.
6457	*/
6458	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
6459	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; i++)
6460	{
6461	uint32_t val = 0;
6462
6463	int rc = vmsvga3dQueryCaps(pThisCC, i, &val);
6464	if (RT_SUCCESS(rc))
6465	{
6466	pData[idxCap][0] = i;
6467	pData[idxCap][1] = val;
6468	idxCap++;
6469	if (g_apszVmSvgaDevCapNames[i][0] == 'x')
6470	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
6471	else
6472	LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)(float )&val, (unsigned)((float )&val * 10000) % 10000,
6473	&g_apszVmSvgaDevCapNames[i][1]));
6474	}
6475	else
6476	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
6477	}
6478	pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
6479	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
6480
6481	/* Mark end of record array. */
6482	pCaps->header.length = 0;
6483
6484	RTLogRelSetBuffering(fSavedBuffering);
6485	}
6486
6487	# endif
6488
6489	/**
6490	* Resets the SVGA hardware state
6491	*
6492	* @returns VBox status code.
6493	* @param pDevIns The device instance.
6494	*/
6495	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
6496	{
6497	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6498	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6499	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
6500
6501	/* Reset before init? */
6502	if (!pSVGAState)
6503	return VINF_SUCCESS;
6504
6505	Log(("vmsvgaR3Reset\n"));
6506
6507	/* Reset the FIFO processing as well as the 3d state (if we have one). */
6508	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
6509	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
6510
6511	/* Reset other stuff. */
6512	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6513	RT_ZERO(pThis->svga.au32ScratchRegion);
6514
6515	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6516	vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6517
6518	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
6519
6520	/* Initialize FIFO and register capabilities. */
6521	vmsvgaR3InitCaps(pThis, pThisCC);
6522
6523	# ifdef VBOX_WITH_VMSVGA3D
6524	if (pThis->svga.f3DEnabled)
6525	vmsvgaR3InitFifo3DCaps(pThisCC);
6526	# endif
6527
6528	/* VRAM tracking is enabled by default during bootup. */
6529	pThis->svga.fVRAMTracking = true;
6530	pThis->svga.fEnabled = false;
6531
6532	/* Invalidate current settings. */
6533	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6534	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6535	pThis->svga.uBpp = pThis->svga.uHostBpp;
6536	pThis->svga.cbScanline = 0;
6537	pThis->svga.u32PitchLock = 0;
6538
6539	return rc;
6540	}
6541
6542	/**
6543	* Cleans up the SVGA hardware state
6544	*
6545	* @returns VBox status code.
6546	* @param pDevIns The device instance.
6547	*/
6548	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
6549	{
6550	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6551	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6552
6553	/*
6554	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6555	*/
6556	if (pThisCC->svga.pFIFOIOThread)
6557	{
6558	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6559	NULL /pvParam/, 30000 /ms/);
6560	AssertLogRelRC(rc);
6561
6562	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6563	AssertLogRelRC(rc);
6564	pThisCC->svga.pFIFOIOThread = NULL;
6565	}
6566
6567	/*
6568	* Destroy the special SVGA state.
6569	*/
6570	if (pThisCC->svga.pSvgaR3State)
6571	{
6572	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6573
6574	RTMemFree(pThisCC->svga.pSvgaR3State);
6575	pThisCC->svga.pSvgaR3State = NULL;
6576	}
6577
6578	/*
6579	* Free our resources residing in the VGA state.
6580	*/
6581	if (pThisCC->svga.pbVgaFrameBufferR3)
6582	{
6583	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6584	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6585	}
6586	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6587	{
6588	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6589	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6590	}
6591	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6592	{
6593	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6594	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6595	}
6596
6597	return VINF_SUCCESS;
6598	}
6599
6600	/**
6601	* Initialize the SVGA hardware state
6602	*
6603	* @returns VBox status code.
6604	* @param pDevIns The device instance.
6605	*/
6606	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6607	{
6608	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6609	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6610	PVMSVGAR3STATE pSVGAState;
6611	int rc;
6612
6613	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6614	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6615
6616	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6617
6618	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6619	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6620	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6621
6622	/* Create event semaphore. */
6623	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6624	AssertRCReturn(rc, rc);
6625
6626	/* Create event semaphore. */
6627	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6628	AssertRCReturn(rc, rc);
6629
6630	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAlloc(sizeof(VMSVGAR3STATE));
6631	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6632
6633	rc = vmsvgaR3StateInit(pThis, pThisCC->svga.pSvgaR3State);
6634	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6635
6636	pSVGAState = pThisCC->svga.pSvgaR3State;
6637
6638	/* Initialize FIFO and register capabilities. */
6639	vmsvgaR3InitCaps(pThis, pThisCC);
6640
6641	# ifdef VBOX_WITH_VMSVGA3D
6642	if (pThis->svga.f3DEnabled)
6643	{
6644	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6645	if (RT_FAILURE(rc))
6646	{
6647	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6648	pThis->svga.f3DEnabled = false;
6649	}
6650	}
6651	# endif
6652	/* VRAM tracking is enabled by default during bootup. */
6653	pThis->svga.fVRAMTracking = true;
6654
6655	/* Set up the host bpp. This value is as a default for the programmable
6656	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6657	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6658	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6659	*
6660	* NB: The driver cBits value is currently constant for the lifetime of the
6661	* VM. If that changes, the host bpp logic might need revisiting.
6662	*/
6663	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6664
6665	/* Invalidate current settings. */
6666	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6667	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6668	pThis->svga.uBpp = pThis->svga.uHostBpp;
6669	pThis->svga.cbScanline = 0;
6670
6671	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6672	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6673	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6674	{
6675	pThis->svga.u32MaxWidth -= 256;
6676	pThis->svga.u32MaxHeight -= 256;
6677	}
6678	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6679
6680	# ifdef DEBUG_GMR_ACCESS
6681	/* Register the GMR access handler type. */
6682	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6683	vmsvgaR3GmrAccessHandler,
6684	NULL, NULL, NULL,
6685	NULL, NULL, NULL,
6686	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6687	AssertRCReturn(rc, rc);
6688	# endif
6689
6690	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6691	/* Register the FIFO access handler type. In addition to
6692	debugging FIFO access, this is also used to facilitate
6693	extended fifo thread sleeps. */
6694	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6695	# ifdef DEBUG_FIFO_ACCESS
6696	PGMPHYSHANDLERKIND_ALL,
6697	# else
6698	PGMPHYSHANDLERKIND_WRITE,
6699	# endif
6700	vmsvgaR3FifoAccessHandler,
6701	NULL, NULL, NULL,
6702	NULL, NULL, NULL,
6703	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6704	AssertRCReturn(rc, rc);
6705	# endif
6706
6707	/* Create the async IO thread. */
6708	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6709	RTTHREADTYPE_IO, "VMSVGA FIFO");
6710	if (RT_FAILURE(rc))
6711	{
6712	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6713	return rc;
6714	}
6715
6716	/*
6717	* Statistics.
6718	*/
6719	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6720	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6721	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6722	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6723	# ifdef VBOX_WITH_STATISTICS
6724	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6725	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6726	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6727	# endif
6728	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6729	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6730	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6731	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6732	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6733	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6734	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6735	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6736	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6737	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6738	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6739	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6740	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6741	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6742	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6743	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6744	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6745	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6746	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6747	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6748	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6749	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6750	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6751	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6752	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6753	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6754	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6755	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6756	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6757	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6758	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6759	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6760	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6761	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6762	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6763	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6764	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6765	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6766	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6767	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6768	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6769	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6770	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6771	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6772	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6773	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6774	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6775	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6776	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6777	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6778	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6779	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6780	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6781	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6782	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6783	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6784	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6785	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6786	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6787
6788	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6789	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6790	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6791	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6792	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6793	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6794	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6795	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6796	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_CURSOR_ID writes.");
6797	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6798	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6799	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6800	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6801	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6802	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6803	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6804	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6805	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6806	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6807	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6808	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6809	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6810	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6811	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6812	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6813	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6814	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6815	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6816	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6817	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6818	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6819	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6820	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6821	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6822	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6823
6824	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6825	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6826	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6827	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6828	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6829	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6830	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6831	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6832	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_CURSOR_ID reads.");
6833	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6834	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6835	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6836	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6837	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6838	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6839	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6840	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6841	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6842	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6843	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6844	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6845	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6846	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6847	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6848	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6849	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6850	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6851	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6852	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6853	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6854	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6855	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6856	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6857	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6858	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6859	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6860	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6861	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6862	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6863	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6864	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6865	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6866	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6867	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6868	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6869	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6870	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6871	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6872	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6873	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6874	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6875	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6876
6877	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6878	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6879	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6880	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6881	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6882	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6883	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6884	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6885	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6886	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6887	# endif
6888	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6889	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6890	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6891	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6892	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6893
6894	# undef REG_CNT
6895	# undef REG_PRF
6896
6897	/*
6898	* Info handlers.
6899	*/
6900	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6901	# ifdef VBOX_WITH_VMSVGA3D
6902	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6903	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6904	"VMSVGA 3d surface details. "
6905	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6906	vmsvgaR3Info3dSurface);
6907	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6908	"VMSVGA 3d surface details and bitmap: "
6909	"sid[>dir]",
6910	vmsvgaR3Info3dSurfaceBmp);
6911	# endif
6912
6913	return VINF_SUCCESS;
6914	}
6915
6916	/**
6917	* Power On notification.
6918	*
6919	* @returns VBox status code.
6920	* @param pDevIns The device instance data.
6921	*
6922	* @remarks Caller enters the device critical section.
6923	*/
6924	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6925	{
6926	# ifdef VBOX_WITH_VMSVGA3D
6927	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6928	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6929	if (pThis->svga.f3DEnabled)
6930	{
6931	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6932
6933	if (RT_SUCCESS(rc))
6934	{
6935	/* Initialize FIFO 3D capabilities. */
6936	vmsvgaR3InitFifo3DCaps(pThisCC);
6937	}
6938	}
6939	# else /* !VBOX_WITH_VMSVGA3D */
6940	RT_NOREF(pDevIns);
6941	# endif /* !VBOX_WITH_VMSVGA3D */
6942	}
6943
6944	/**
6945	* Power Off notification.
6946	*
6947	* @param pDevIns The device instance data.
6948	*
6949	* @remarks Caller enters the device critical section.
6950	*/
6951	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6952	{
6953	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6954	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6955
6956	/*
6957	* Notify the FIFO thread.
6958	*/
6959	if (pThisCC->svga.pFIFOIOThread)
6960	{
6961	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6962	NULL /pvParam/, 30000 /ms/);
6963	AssertLogRelRC(rc);
6964	}
6965	}
6966
6967	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 86156

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