DevVGA-SVGA.cpp@ 87979

Last change on this file since 87979 was 87633, checked in by vboxsync, 4 years ago
VMM/TM,VMM/HMVMX: Try avoid calling TMCpuTickGetDeadlineAndTscOffset as it is expensive. Current approach is a bit erratic wrt CPUID benchmark results, but it's generally better than before.
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File size: 286.9 KB

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1	/* $Id: DevVGA-SVGA.cpp 87633 2021-02-05 21:37:09Z vboxsync $ */
2	/** @file
3	* VMware SVGA device.
4	*
5	* Logging levels guidelines for this and related files:
6	* - Log() for normal bits.
7	* - LogFlow() for more info.
8	* - Log2 for hex dump of cursor data.
9	* - Log3 for hex dump of shader code.
10	* - Log4 for hex dumps of 3D data.
11	* - Log5 for info about GMR pages.
12	* - LogRel for the usual important stuff.
13	* - LogRel2 for cursor.
14	* - LogRel3 for 3D performance data.
15	* - LogRel4 for HW accelerated graphics output.
16	*/
17
18	/*
19	* Copyright (C) 2013-2020 Oracle Corporation
20	*
21	* This file is part of VirtualBox Open Source Edition (OSE), as
22	* available from http://www.virtualbox.org. This file is free software;
23	* you can redistribute it and/or modify it under the terms of the GNU
24	* General Public License (GPL) as published by the Free Software
25	* Foundation, in version 2 as it comes in the "COPYING" file of the
26	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
27	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
28	*/
29
30
31	/** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
32	*
33	* This device emulation was contributed by trivirt AG. It offers an
34	* alternative to our Bochs based VGA graphics and 3d emulations. This is
35	* valuable for Xorg based guests, as there is driver support shipping with Xorg
36	* since it forked from XFree86.
37	*
38	*
39	* @section sec_dev_vmsvga_sdk The VMware SDK
40	*
41	* This is officially deprecated now, however it's still quite useful,
42	* especially for getting the old features working:
43	* http://vmware-svga.sourceforge.net/
44	*
45	* They currently point developers at the following resources.
46	* - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
47	* - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
48	* - http://cgit.freedesktop.org/mesa/vmwgfx/
49	*
50	* @subsection subsec_dev_vmsvga_sdk_results Test results
51	*
52	* Test results:
53	* - 2dmark.img:
54	* + todo
55	* - backdoor-tclo.img:
56	* + todo
57	* - blit-cube.img:
58	* + todo
59	* - bunnies.img:
60	* + todo
61	* - cube.img:
62	* + todo
63	* - cubemark.img:
64	* + todo
65	* - dynamic-vertex-stress.img:
66	* + todo
67	* - dynamic-vertex.img:
68	* + todo
69	* - fence-stress.img:
70	* + todo
71	* - gmr-test.img:
72	* + todo
73	* - half-float-test.img:
74	* + todo
75	* - noscreen-cursor.img:
76	* - The CURSOR I/O and FIFO registers are not implemented, so the mouse
77	* cursor doesn't show. (Hacking the GUI a little, would make the cursor
78	* visible though.)
79	* - Cursor animation via the palette doesn't work.
80	* - During debugging, it turns out that the framebuffer content seems to
81	* be halfways ignore or something (memset(fb, 0xcc, lots)).
82	* - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
83	* grow it 0x10 fold (128KB -> 2MB like in WS10).
84	* - null.img:
85	* + todo
86	* - pong.img:
87	* + todo
88	* - presentReadback.img:
89	* + todo
90	* - resolution-set.img:
91	* + todo
92	* - rt-gamma-test.img:
93	* + todo
94	* - screen-annotation.img:
95	* + todo
96	* - screen-cursor.img:
97	* + todo
98	* - screen-dma-coalesce.img:
99	* + todo
100	* - screen-gmr-discontig.img:
101	* + todo
102	* - screen-gmr-remap.img:
103	* + todo
104	* - screen-multimon.img:
105	* + todo
106	* - screen-present-clip.img:
107	* + todo
108	* - screen-render-test.img:
109	* + todo
110	* - screen-simple.img:
111	* + todo
112	* - screen-text.img:
113	* + todo
114	* - simple-shaders.img:
115	* + todo
116	* - simple_blit.img:
117	* + todo
118	* - tiny-2d-updates.img:
119	* + todo
120	* - video-formats.img:
121	* + todo
122	* - video-sync.img:
123	* + todo
124	*
125	*/
126
127
128	/*********************************************************************************************************************************
129	* Header Files *
130	*********************************************************************************************************************************/
131	#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
132	#include <VBox/vmm/pdmdev.h>
133	#include <VBox/version.h>
134	#include <VBox/err.h>
135	#include <VBox/log.h>
136	#include <VBox/vmm/pgm.h>
137	#include <VBox/sup.h>
138
139	#include <iprt/assert.h>
140	#include <iprt/semaphore.h>
141	#include <iprt/uuid.h>
142	#ifdef IN_RING3
143	# include <iprt/ctype.h>
144	# include <iprt/mem.h>
145	# ifdef VBOX_STRICT
146	# include <iprt/time.h>
147	# endif
148	#endif
149
150	#include <VBox/AssertGuest.h>
151	#include <VBox/VMMDev.h>
152	#include <VBoxVideo.h>
153	#include <VBox/bioslogo.h>
154
155	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
156	#include "DevVGA.h"
157
158	/* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
159	#ifdef VBOX_WITH_VMSVGA3D
160	# include "DevVGA-SVGA3d.h"
161	# ifdef RT_OS_DARWIN
162	# include "DevVGA-SVGA3d-cocoa.h"
163	# endif
164	# ifdef RT_OS_LINUX
165	# ifdef IN_RING3
166	# include "DevVGA-SVGA3d-glLdr.h"
167	# endif
168	# endif
169	#endif
170	#ifdef IN_RING3
171	#include "DevVGA-SVGA-internal.h"
172	#endif
173
174
175	/*********************************************************************************************************************************
176	* Defined Constants And Macros *
177	*********************************************************************************************************************************/
178	/**
179	* Macro for checking if a fixed FIFO register is valid according to the
180	* current FIFO configuration.
181	*
182	* @returns true / false.
183	* @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
184	* @param a_offFifoMin A valid SVGA_FIFO_MIN value.
185	*/
186	#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
187
188
189	/*********************************************************************************************************************************
190	* Structures and Typedefs *
191	*********************************************************************************************************************************/
192
193
194	/*********************************************************************************************************************************
195	* Internal Functions *
196	*********************************************************************************************************************************/
197	#ifdef IN_RING3
198	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
199	static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
200	# endif
201	# ifdef DEBUG_GMR_ACCESS
202	static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
203	# endif
204	#endif
205
206
207	/*********************************************************************************************************************************
208	* Global Variables *
209	*********************************************************************************************************************************/
210	#ifdef IN_RING3
211
212	/**
213	* SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
214	*/
215	static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
216	{
217	SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
218	SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
219	SSMFIELD_ENTRY_TERM()
220	};
221
222	/**
223	* SSM descriptor table for the GMR structure.
224	*/
225	static SSMFIELD const g_aGMRFields[] =
226	{
227	SSMFIELD_ENTRY( GMR, cMaxPages),
228	SSMFIELD_ENTRY( GMR, cbTotal),
229	SSMFIELD_ENTRY( GMR, numDescriptors),
230	SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
231	SSMFIELD_ENTRY_TERM()
232	};
233
234	/**
235	* SSM descriptor table for the VMSVGASCREENOBJECT structure.
236	*/
237	static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
238	{
239	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
240	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
241	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
242	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
243	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
244	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
245	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
246	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
247	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
248	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
249	SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
250	SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
251	SSMFIELD_ENTRY_TERM()
252	};
253
254	/**
255	* SSM descriptor table for the VMSVGAR3STATE structure.
256	*/
257	static SSMFIELD const g_aVMSVGAR3STATEFields[] =
258	{
259	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
260	SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
261	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
262	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
263	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
264	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
265	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
266	SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
267	SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
268	SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
269	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
270	#ifdef VMSVGA_USE_EMT_HALT_CODE
271	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
272	#else
273	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
274	#endif
275	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
276	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
277	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
278	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
279	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
280	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
281	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
282	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
283	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
284	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
285	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
286	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
287	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
288	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
289	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
290	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
291	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
292	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
293	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
294	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
295	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
296	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
297	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
298	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
299	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
300	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
301	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
302	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
303	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
304	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
305	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
306	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
307	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
308	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
309	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
310	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
311	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
312	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
313	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
314	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
315	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
316	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
317	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
318	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
319	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
320	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
321	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
322	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
323	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
324	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
325	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
326	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
327	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
328	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
329	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
330	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
331	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
332	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
333	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
334	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
335	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
336	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
337	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
338
339	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
340	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
341	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
342	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
343
344	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
345	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
346	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
347	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
348	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
349	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
350	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
351	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
352	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
353	# endif
354	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
355	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
356	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
357	SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
358
359	SSMFIELD_ENTRY_TERM()
360	};
361
362	/**
363	* SSM descriptor table for the VGAState.svga structure.
364	*/
365	static SSMFIELD const g_aVGAStateSVGAFields[] =
366	{
367	SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
368	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
369	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
370	SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
371	SSMFIELD_ENTRY( VMSVGAState, fEnabled),
372	SSMFIELD_ENTRY( VMSVGAState, fConfigured),
373	SSMFIELD_ENTRY( VMSVGAState, fBusy),
374	SSMFIELD_ENTRY( VMSVGAState, fTraces),
375	SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
376	SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
377	SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
378	SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
379	SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
380	SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
381	SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
382	SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
383	SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
384	SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
385	SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
386	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
387	SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
388	SSMFIELD_ENTRY( VMSVGAState, uWidth),
389	SSMFIELD_ENTRY( VMSVGAState, uHeight),
390	SSMFIELD_ENTRY( VMSVGAState, uBpp),
391	SSMFIELD_ENTRY( VMSVGAState, cbScanline),
392	SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
393	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
394	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
395	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
396	SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
397	SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
398	SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
399	SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
400	SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
401	SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
402	SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
403	SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
404	SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
405	SSMFIELD_ENTRY_TERM()
406	};
407	#endif /* IN_RING3 */
408
409
410	/*********************************************************************************************************************************
411	* Internal Functions *
412	*********************************************************************************************************************************/
413	#ifdef IN_RING3
414	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
415	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
416	uint32_t uVersion, uint32_t uPass);
417	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
418	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
419	#endif /* IN_RING3 */
420
421
422	#define SVGA_CASE_ID2STR(idx) case idx: return #idx
423	#if defined(LOG_ENABLED)
424	/**
425	* Index register string name lookup
426	*
427	* @returns Index register string or "UNKNOWN"
428	* @param pThis The shared VGA/VMSVGA state.
429	* @param idxReg The index register.
430	*/
431	static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
432	{
433	AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
434	switch (idxReg)
435	{
436	SVGA_CASE_ID2STR(SVGA_REG_ID);
437	SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
438	SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
439	SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
440	SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
441	SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
442	SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
443	SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
444	SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
445	SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
446	SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
447	SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
448	SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
449	SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
450	SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
451	SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
452	SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
453
454	/* ID 0 implementation only had the above registers, then the palette */
455	SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
456	SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
457	SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
458	SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
459	SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
460	SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
461	SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
462	SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
463	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
464	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
465	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
466	SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
467	SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
468	SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
469	SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
470	SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
471	SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
472
473	/* Legacy multi-monitor support */
474	SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
475	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
476	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
477	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
478	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
479	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
480	SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
481
482	SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
483	SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
484	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
485	SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
486
487	SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
488	SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
489	SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
490	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
491	SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
492	SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
493	SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
494	SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
495	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
496	SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
497	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
498	SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
499	SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
500	SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
501	SVGA_CASE_ID2STR(SVGA_REG_CAP2);
502	SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
503	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
504	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
505	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
506	SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
507	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
508	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
509	SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
510	SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
511	SVGA_CASE_ID2STR(SVGA_REG_FENCE);
512	SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
513	SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
514	SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
515	SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
516	SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
517	SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
518	SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
519	SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
520
521	default:
522	if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
523	return "SVGA_SCRATCH_BASE reg";
524	if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
525	return "SVGA_PALETTE_BASE reg";
526	return "UNKNOWN";
527	}
528	}
529	#endif /* LOG_ENABLED */
530
531	#if defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
532	static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
533	{
534	AssertCompile(SVGA3D_DEVCAP_MAX == 260);
535	switch (idxDevCap)
536	{
537	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
538	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
539	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
540	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
541	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
542	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
543	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
544	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
545	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
546	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
547	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
548	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
549	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
550	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
551	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
552	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
553	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
554	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
555	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
556	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
557	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
558	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
559	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
560	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
561	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
562	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
563	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
564	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
565	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
566	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
567	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
568	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
569	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
570	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
571	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
572	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
573	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
574	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
575	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
576	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
577	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
578	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
579	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
580	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
581	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
582	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
583	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
584	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
585	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
586	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
587	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
588	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
589	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
590	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
591	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
592	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
593	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
594	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
595	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
596	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
597	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
598	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
599	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
600	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
601	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
602	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
603	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
604	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
605	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
606	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
607	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
608	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
609	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
610	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
611	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
612	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
613	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
614	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
615	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
616	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
617	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
618	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
619	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
620	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
621	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
622	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
623	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
624	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
625	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
626	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
627	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
628	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
629	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
630	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
631	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
632	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
633	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
634	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
635	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
636	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
637	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
638	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
639	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
640	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
641	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
642	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
643	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
644	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
645	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
646	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
647	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
648	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
649	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
650	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
651	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
652	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
653	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
654	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
655	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
656	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
657	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
658	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
659	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
660	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
661	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
662	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
663	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
664	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
665	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
666	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
667	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
668	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
669	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
670	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
671	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
672	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
673	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
674	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
675	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
676	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
677	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
678	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
679	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
680	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
681	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
682	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
683	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
684	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
685	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
686	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
687	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
688	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
689	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
690	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
691	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
692	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
693	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
694	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
695	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
696	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
697	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
698	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
699	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
700	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
701	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
702	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
703	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
704	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
705	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
706	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
707	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
708	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
709	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
710	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
711	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
712	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
713	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
714	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
715	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
716	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
717	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
718	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
719	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
720	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
721	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
722	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
723	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
724	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
725	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
726	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
727	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
728	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
729	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
730	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
731	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
732	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
733	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
734	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
735	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
736	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
737	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
738	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
739	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
740	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
741	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
742	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
743	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
744	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
745	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
746	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
747	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
748	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
749	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
750	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
751	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
752	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
753	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
754	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
755	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
756	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
757	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
758	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
759	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
760	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
761	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
762	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
763	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
764	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
765	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
766	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
767	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
768	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
769	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
770	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
771	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
772	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
773	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
774	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
775	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
776	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
777	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
778	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
779	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
780	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
781	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
782	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
783	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
784	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
785	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
786	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
787	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
788	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
789	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
790	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
791	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
792	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
793	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
794	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
795	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
796	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
797	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
798
799	SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
800
801	default:
802	break;
803	}
804	return "UNKNOWN";
805	}
806	#endif /* defined(LOG_ENABLED) \|\| (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
807	#undef SVGA_CASE_ID2STR
808
809
810	#ifdef IN_RING3
811
812	/**
813	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
814	*/
815	DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
816	{
817	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
818	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
819
820	Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
821	VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
822
823	/** @todo Test how it interacts with multiple screen objects. */
824	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
825	uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
826	uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
827
828	if (x < uWidth)
829	{
830	pThis->svga.viewport.x = x;
831	pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
832	pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
833	}
834	else
835	{
836	pThis->svga.viewport.x = uWidth;
837	pThis->svga.viewport.cx = 0;
838	pThis->svga.viewport.xRight = uWidth;
839	}
840	if (y < uHeight)
841	{
842	pThis->svga.viewport.y = y;
843	pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
844	pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
845	pThis->svga.viewport.yHighWC = uHeight - y;
846	}
847	else
848	{
849	pThis->svga.viewport.y = uHeight;
850	pThis->svga.viewport.cy = 0;
851	pThis->svga.viewport.yLowWC = 0;
852	pThis->svga.viewport.yHighWC = 0;
853	}
854
855	# ifdef VBOX_WITH_VMSVGA3D
856	/*
857	* Now inform the 3D backend.
858	*/
859	if (pThis->svga.f3DEnabled)
860	vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
861	# else
862	RT_NOREF(OldViewport);
863	# endif
864	}
865
866
867	/**
868	* Updating screen information in API
869	*
870	* @param pThis The The shared VGA/VMSVGA instance data.
871	* @param pThisCC The VGA/VMSVGA state for ring-3.
872	*/
873	void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
874	{
875	int rc;
876
877	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
878
879	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
880	{
881	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
882	if (!pScreen->fModified)
883	continue;
884
885	pScreen->fModified = false;
886
887	VBVAINFOVIEW view;
888	RT_ZERO(view);
889	view.u32ViewIndex = pScreen->idScreen;
890	// view.u32ViewOffset = 0;
891	view.u32ViewSize = pThis->vram_size;
892	view.u32MaxScreenSize = pThis->vram_size;
893
894	VBVAINFOSCREEN screen;
895	RT_ZERO(screen);
896	screen.u32ViewIndex = pScreen->idScreen;
897
898	if (pScreen->fDefined)
899	{
900	if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
901	\|\| pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
902	\|\| pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
903	{
904	Assert(pThis->svga.fGFBRegisters);
905	continue;
906	}
907
908	screen.i32OriginX = pScreen->xOrigin;
909	screen.i32OriginY = pScreen->yOrigin;
910	screen.u32StartOffset = pScreen->offVRAM;
911	screen.u32LineSize = pScreen->cbPitch;
912	screen.u32Width = pScreen->cWidth;
913	screen.u32Height = pScreen->cHeight;
914	screen.u16BitsPerPixel = pScreen->cBpp;
915	if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
916	screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
917	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
918	screen.u16Flags \|= VBVA_SCREEN_F_BLANK2;
919	}
920	else
921	{
922	/* Screen is destroyed. */
923	screen.u16Flags = VBVA_SCREEN_F_DISABLED;
924	}
925
926	void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
927	rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /fResetInputMapping=/ true);
928	AssertRC(rc);
929	}
930	}
931
932
933	/**
934	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
935	*
936	* Used to update screen offsets (positions) since appearently vmwgfx fails to
937	* pass correct offsets thru FIFO.
938	*/
939	DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
940	{
941	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
942	PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
943	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
944
945	AssertReturnVoid(pSVGAState);
946
947	/* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
948	cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
949	for (uint32_t i = 0; i < cPositions; ++i)
950	{
951	if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
952	&& pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
953	continue;
954
955	if (pSVGAState->aScreens[i].xOrigin == -1)
956	continue;
957	if (pSVGAState->aScreens[i].yOrigin == -1)
958	continue;
959
960	pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
961	pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
962	pSVGAState->aScreens[i].fModified = true;
963	}
964
965	vmsvgaR3VBVAResize(pThis, pThisCC);
966	}
967
968	#endif /* IN_RING3 */
969
970	/**
971	* Read port register
972	*
973	* @returns VBox status code.
974	* @param pDevIns The device instance.
975	* @param pThis The shared VGA/VMSVGA state.
976	* @param pu32 Where to store the read value
977	*/
978	static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
979	{
980	#ifdef IN_RING3
981	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
982	#endif
983	int rc = VINF_SUCCESS;
984	*pu32 = 0;
985
986	/* Rough index register validation. */
987	uint32_t idxReg = pThis->svga.u32IndexReg;
988	#if !defined(IN_RING3) && defined(VBOX_STRICT)
989	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
990	VINF_IOM_R3_IOPORT_READ);
991	#else
992	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
993	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
994	VINF_SUCCESS);
995	#endif
996	RT_UNTRUSTED_VALIDATED_FENCE();
997
998	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
999	if ( idxReg >= SVGA_REG_ID_0_TOP
1000	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1001	{
1002	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1003	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1004	}
1005
1006	switch (idxReg)
1007	{
1008	case SVGA_REG_ID:
1009	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
1010	*pu32 = pThis->svga.u32SVGAId;
1011	break;
1012
1013	case SVGA_REG_ENABLE:
1014	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
1015	*pu32 = pThis->svga.fEnabled;
1016	break;
1017
1018	case SVGA_REG_WIDTH:
1019	{
1020	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
1021	if ( pThis->svga.fEnabled
1022	&& pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
1023	*pu32 = pThis->svga.uWidth;
1024	else
1025	{
1026	#ifndef IN_RING3
1027	rc = VINF_IOM_R3_IOPORT_READ;
1028	#else
1029	*pu32 = pThisCC->pDrv->cx;
1030	#endif
1031	}
1032	break;
1033	}
1034
1035	case SVGA_REG_HEIGHT:
1036	{
1037	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
1038	if ( pThis->svga.fEnabled
1039	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1040	*pu32 = pThis->svga.uHeight;
1041	else
1042	{
1043	#ifndef IN_RING3
1044	rc = VINF_IOM_R3_IOPORT_READ;
1045	#else
1046	*pu32 = pThisCC->pDrv->cy;
1047	#endif
1048	}
1049	break;
1050	}
1051
1052	case SVGA_REG_MAX_WIDTH:
1053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
1054	*pu32 = pThis->svga.u32MaxWidth;
1055	break;
1056
1057	case SVGA_REG_MAX_HEIGHT:
1058	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
1059	*pu32 = pThis->svga.u32MaxHeight;
1060	break;
1061
1062	case SVGA_REG_DEPTH:
1063	/* This returns the color depth of the current mode. */
1064	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
1065	switch (pThis->svga.uBpp)
1066	{
1067	case 15:
1068	case 16:
1069	case 24:
1070	*pu32 = pThis->svga.uBpp;
1071	break;
1072
1073	default:
1074	case 32:
1075	pu32 = 24; / The upper 8 bits are either alpha bits or not used. */
1076	break;
1077	}
1078	break;
1079
1080	case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
1081	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
1082	*pu32 = pThis->svga.uHostBpp;
1083	break;
1084
1085	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1086	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
1087	*pu32 = pThis->svga.uBpp;
1088	break;
1089
1090	case SVGA_REG_PSEUDOCOLOR:
1091	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
1092	pu32 = pThis->svga.uBpp == 8; / See section 6 "Pseudocolor" in svga_interface.txt. */
1093	break;
1094
1095	case SVGA_REG_RED_MASK:
1096	case SVGA_REG_GREEN_MASK:
1097	case SVGA_REG_BLUE_MASK:
1098	{
1099	uint32_t uBpp;
1100
1101	if (pThis->svga.fEnabled)
1102	uBpp = pThis->svga.uBpp;
1103	else
1104	uBpp = pThis->svga.uHostBpp;
1105
1106	uint32_t u32RedMask, u32GreenMask, u32BlueMask;
1107	switch (uBpp)
1108	{
1109	case 8:
1110	u32RedMask = 0x07;
1111	u32GreenMask = 0x38;
1112	u32BlueMask = 0xc0;
1113	break;
1114
1115	case 15:
1116	u32RedMask = 0x0000001f;
1117	u32GreenMask = 0x000003e0;
1118	u32BlueMask = 0x00007c00;
1119	break;
1120
1121	case 16:
1122	u32RedMask = 0x0000001f;
1123	u32GreenMask = 0x000007e0;
1124	u32BlueMask = 0x0000f800;
1125	break;
1126
1127	case 24:
1128	case 32:
1129	default:
1130	u32RedMask = 0x00ff0000;
1131	u32GreenMask = 0x0000ff00;
1132	u32BlueMask = 0x000000ff;
1133	break;
1134	}
1135	switch (idxReg)
1136	{
1137	case SVGA_REG_RED_MASK:
1138	STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
1139	*pu32 = u32RedMask;
1140	break;
1141
1142	case SVGA_REG_GREEN_MASK:
1143	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
1144	*pu32 = u32GreenMask;
1145	break;
1146
1147	case SVGA_REG_BLUE_MASK:
1148	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
1149	*pu32 = u32BlueMask;
1150	break;
1151	}
1152	break;
1153	}
1154
1155	case SVGA_REG_BYTES_PER_LINE:
1156	{
1157	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
1158	if ( pThis->svga.fEnabled
1159	&& pThis->svga.cbScanline)
1160	*pu32 = pThis->svga.cbScanline;
1161	else
1162	{
1163	#ifndef IN_RING3
1164	rc = VINF_IOM_R3_IOPORT_READ;
1165	#else
1166	*pu32 = pThisCC->pDrv->cbScanline;
1167	#endif
1168	}
1169	break;
1170	}
1171
1172	case SVGA_REG_VRAM_SIZE: /* VRAM size */
1173	STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
1174	*pu32 = pThis->vram_size;
1175	break;
1176
1177	case SVGA_REG_FB_START: /* Frame buffer physical address. */
1178	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
1179	Assert(pThis->GCPhysVRAM <= 0xffffffff);
1180	*pu32 = pThis->GCPhysVRAM;
1181	break;
1182
1183	case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
1184	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
1185	/* Always zero in our case. */
1186	*pu32 = 0;
1187	break;
1188
1189	case SVGA_REG_FB_SIZE: /* Frame buffer size */
1190	{
1191	#ifndef IN_RING3
1192	rc = VINF_IOM_R3_IOPORT_READ;
1193	#else
1194	STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
1195
1196	/* VMWare testcases want at least 4 MB in case the hardware is disabled. */
1197	if ( pThis->svga.fEnabled
1198	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1199	{
1200	/* Hardware enabled; return real framebuffer size .*/
1201	pu32 = (uint32_t)pThis->svga.uHeight pThis->svga.cbScanline;
1202	}
1203	else
1204	pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy pThisCC->pDrv->cbScanline);
1205
1206	pu32 = RT_MIN(pThis->vram_size, pu32);
1207	Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
1208	#endif
1209	break;
1210	}
1211
1212	case SVGA_REG_CAPABILITIES:
1213	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
1214	*pu32 = pThis->svga.u32DeviceCaps;
1215	break;
1216
1217	case SVGA_REG_MEM_START: /* FIFO start */
1218	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
1219	Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
1220	*pu32 = pThis->svga.GCPhysFIFO;
1221	break;
1222
1223	case SVGA_REG_MEM_SIZE: /* FIFO size */
1224	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
1225	*pu32 = pThis->svga.cbFIFO;
1226	break;
1227
1228	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1229	STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
1230	*pu32 = pThis->svga.fConfigured;
1231	break;
1232
1233	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1234	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
1235	*pu32 = 0;
1236	break;
1237
1238	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
1239	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
1240	if (pThis->svga.fBusy)
1241	{
1242	#ifndef IN_RING3
1243	/* Go to ring-3 and halt the CPU. */
1244	rc = VINF_IOM_R3_IOPORT_READ;
1245	RT_NOREF(pDevIns);
1246	break;
1247	#else
1248	# if defined(VMSVGA_USE_EMT_HALT_CODE)
1249	/* The guest is basically doing a HLT via the device here, but with
1250	a special wake up condition on FIFO completion. */
1251	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1252	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1253	PVM pVM = PDMDevHlpGetVM(pDevIns);
1254	VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
1255	VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
1256	ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1257	if (pThis->svga.fBusy)
1258	{
1259	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
1260	rc = VMR3WaitForDeviceReady(pVM, idCpu);
1261	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
1262	}
1263	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1264	VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
1265	# else
1266
1267	/* Delay the EMT a bit so the FIFO and others can get some work done.
1268	This used to be a crude 50 ms sleep. The current code tries to be
1269	more efficient, but the consept is still very crude. */
1270	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1271	STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1272	RTThreadYield();
1273	if (pThis->svga.fBusy)
1274	{
1275	uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
1276
1277	if (pThis->svga.fBusy && cRefs == 1)
1278	RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
1279	if (pThis->svga.fBusy)
1280	{
1281	/** @todo If this code is going to stay, we need to call into the halt/wait
1282	* code in VMEmt.cpp here, otherwise all kind of EMT interaction will
1283	* suffer when the guest is polling on a busy FIFO. */
1284	uint64_t uIgnored1, uIgnored2;
1285	uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
1286	if (cNsMaxWait >= RT_NS_100US)
1287	RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
1288	RTSEMWAIT_FLAGS_NANOSECS \| RTSEMWAIT_FLAGS_RELATIVE \| RTSEMWAIT_FLAGS_NORESUME,
1289	RT_MIN(cNsMaxWait, RT_NS_10MS));
1290	}
1291
1292	ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
1293	}
1294	STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
1295	# endif
1296	*pu32 = pThis->svga.fBusy != 0;
1297	#endif
1298	}
1299	else
1300	*pu32 = false;
1301	break;
1302
1303	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1304	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
1305	*pu32 = pThis->svga.u32GuestId;
1306	break;
1307
1308	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
1309	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
1310	*pu32 = pThis->svga.cScratchRegion;
1311	break;
1312
1313	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
1314	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
1315	*pu32 = SVGA_FIFO_NUM_REGS;
1316	break;
1317
1318	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1319	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
1320	*pu32 = pThis->svga.u32PitchLock;
1321	break;
1322
1323	case SVGA_REG_IRQMASK: /* Interrupt mask */
1324	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
1325	*pu32 = pThis->svga.u32IrqMask;
1326	break;
1327
1328	/* See "Guest memory regions" below. */
1329	case SVGA_REG_GMR_ID:
1330	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
1331	*pu32 = pThis->svga.u32CurrentGMRId;
1332	break;
1333
1334	case SVGA_REG_GMR_DESCRIPTOR:
1335	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
1336	/* Write only */
1337	*pu32 = 0;
1338	break;
1339
1340	case SVGA_REG_GMR_MAX_IDS:
1341	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
1342	*pu32 = pThis->svga.cGMR;
1343	break;
1344
1345	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
1346	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
1347	*pu32 = VMSVGA_MAX_GMR_PAGES;
1348	break;
1349
1350	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
1351	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
1352	*pu32 = pThis->svga.fTraces;
1353	break;
1354
1355	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
1356	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
1357	*pu32 = VMSVGA_MAX_GMR_PAGES;
1358	break;
1359
1360	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
1361	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
1362	*pu32 = VMSVGA_SURFACE_SIZE;
1363	break;
1364
1365	case SVGA_REG_TOP: /* Must be 1 more than the last register */
1366	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
1367	break;
1368
1369	/* Mouse cursor support. */
1370	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
1371	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
1372	*pu32 = pThis->svga.uCursorID;
1373	break;
1374
1375	case SVGA_REG_CURSOR_X:
1376	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
1377	*pu32 = pThis->svga.uCursorX;
1378	break;
1379
1380	case SVGA_REG_CURSOR_Y:
1381	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
1382	*pu32 = pThis->svga.uCursorY;
1383	break;
1384
1385	case SVGA_REG_CURSOR_ON:
1386	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
1387	*pu32 = pThis->svga.uCursorOn;
1388	break;
1389
1390	/* Legacy multi-monitor support */
1391	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
1392	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
1393	*pu32 = 1;
1394	break;
1395
1396	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
1397	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
1398	*pu32 = 0;
1399	break;
1400
1401	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
1402	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
1403	*pu32 = 0;
1404	break;
1405
1406	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
1407	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
1408	*pu32 = 0;
1409	break;
1410
1411	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
1412	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
1413	*pu32 = 0;
1414	break;
1415
1416	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
1417	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
1418	*pu32 = pThis->svga.uWidth;
1419	break;
1420
1421	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
1422	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
1423	*pu32 = pThis->svga.uHeight;
1424	break;
1425
1426	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
1427	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
1428	/* We must return something sensible here otherwise the Linux driver
1429	will take a legacy code path without 3d support. This number also
1430	limits how many screens Linux guests will allow. */
1431	*pu32 = pThis->cMonitors;
1432	break;
1433
1434	/*
1435	* SVGA_CAP_GBOBJECTS+ registers.
1436	*/
1437	case SVGA_REG_COMMAND_LOW:
1438	/* Lower 32 bits of command buffer physical address. */
1439	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
1440	*pu32 = pThis->svga.u32RegCommandLow;
1441	break;
1442
1443	case SVGA_REG_COMMAND_HIGH:
1444	/* Upper 32 bits of command buffer PA. */
1445	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
1446	*pu32 = pThis->svga.u32RegCommandHigh;
1447	break;
1448
1449	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
1450	/* Max primary (screen) memory. */
1451	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
1452	pu32 = pThis->vram_size; /* @todo Maybe half VRAM? */
1453	break;
1454
1455	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
1456	/* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
1457	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
1458	*pu32 = pThis->vram_size / 1024;
1459	break;
1460
1461	case SVGA_REG_DEV_CAP:
1462	/* Write dev cap index, read value */
1463	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
1464	if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
1465	{
1466	RT_UNTRUSTED_VALIDATED_FENCE();
1467	*pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
1468	}
1469	else
1470	*pu32 = 0;
1471	break;
1472
1473	case SVGA_REG_CMD_PREPEND_LOW:
1474	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
1475	pu32 = 0; / Not supported. */
1476	break;
1477
1478	case SVGA_REG_CMD_PREPEND_HIGH:
1479	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
1480	pu32 = 0; / Not supported. */
1481	break;
1482
1483	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
1484	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
1485	*pu32 = pThis->svga.u32MaxWidth;
1486	break;
1487
1488	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
1489	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
1490	*pu32 = pThis->svga.u32MaxHeight;
1491	break;
1492
1493	case SVGA_REG_MOB_MAX_SIZE:
1494	/* Essentially the max texture size */
1495	STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
1496	pu32 = _128M; /* @todo Some actual value. Probably the mapped VRAM size. */
1497	break;
1498
1499	default:
1500	{
1501	uint32_t offReg;
1502	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
1503	{
1504	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
1505	RT_UNTRUSTED_VALIDATED_FENCE();
1506	*pu32 = pThis->svga.au32ScratchRegion[offReg];
1507	}
1508	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
1509	{
1510	/* Note! Using last_palette rather than palette here to preserve the VGA one. */
1511	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
1512	RT_UNTRUSTED_VALIDATED_FENCE();
1513	uint32_t u32 = pThis->last_palette[offReg / 3];
1514	switch (offReg % 3)
1515	{
1516	case 0: pu32 = (u32 >> 16) & 0xff; break; / red */
1517	case 1: pu32 = (u32 >> 8) & 0xff; break; / green */
1518	case 2: pu32 = u32 & 0xff; break; / blue */
1519	}
1520	}
1521	else
1522	{
1523	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1524	rc = VINF_IOM_R3_IOPORT_READ;
1525	#else
1526	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
1527
1528	/* Do not assert. The guest might be reading all registers. */
1529	LogFunc(("Unknown reg=%#x\n", idxReg));
1530	#endif
1531	}
1532	break;
1533	}
1534	}
1535	Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
1536	return rc;
1537	}
1538
1539	#ifdef IN_RING3
1540	/**
1541	* Apply the current resolution settings to change the video mode.
1542	*
1543	* @returns VBox status code.
1544	* @param pThis The shared VGA state.
1545	* @param pThisCC The ring-3 VGA state.
1546	*/
1547	int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
1548	{
1549	/* Always do changemode on FIFO thread. */
1550	Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
1551
1552	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1553
1554	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
1555
1556	if (pThis->svga.fGFBRegisters)
1557	{
1558	/* "For backwards compatibility, when the GFB mode registers (WIDTH,
1559	* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1560	* deletes all screens other than screen #0, and redefines screen
1561	* #0 according to the specified mode. Drivers that use
1562	* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
1563	*/
1564
1565	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
1566	pScreen->fDefined = true;
1567	pScreen->fModified = true;
1568	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
1569	pScreen->idScreen = 0;
1570	pScreen->xOrigin = 0;
1571	pScreen->yOrigin = 0;
1572	pScreen->offVRAM = 0;
1573	pScreen->cbPitch = pThis->svga.cbScanline;
1574	pScreen->cWidth = pThis->svga.uWidth;
1575	pScreen->cHeight = pThis->svga.uHeight;
1576	pScreen->cBpp = pThis->svga.uBpp;
1577
1578	for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
1579	{
1580	/* Delete screen. */
1581	pScreen = &pSVGAState->aScreens[iScreen];
1582	if (pScreen->fDefined)
1583	{
1584	pScreen->fModified = true;
1585	pScreen->fDefined = false;
1586	}
1587	}
1588	}
1589	else
1590	{
1591	/* "If Screen Objects are supported, they can be used to fully
1592	* replace the functionality provided by the framebuffer registers
1593	* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
1594	*/
1595	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
1596	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
1597	pThis->svga.uBpp = pThis->svga.uHostBpp;
1598	}
1599
1600	vmsvgaR3VBVAResize(pThis, pThisCC);
1601
1602	/* Last stuff. For the VGA device screenshot. */
1603	pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
1604	pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
1605	pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
1606	pThis->last_width = pSVGAState->aScreens[0].cWidth;
1607	pThis->last_height = pSVGAState->aScreens[0].cHeight;
1608
1609	/* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
1610	if ( pThis->svga.viewport.cx == 0
1611	&& pThis->svga.viewport.cy == 0)
1612	{
1613	pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
1614	pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
1615	pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
1616	pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
1617	pThis->svga.viewport.yLowWC = 0;
1618	}
1619
1620	return VINF_SUCCESS;
1621	}
1622
1623	int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
1624	{
1625	VBVACMDHDR cmd;
1626	cmd.x = (int16_t)(pScreen->xOrigin + x);
1627	cmd.y = (int16_t)(pScreen->yOrigin + y);
1628	cmd.w = (uint16_t)w;
1629	cmd.h = (uint16_t)h;
1630
1631	pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
1632	pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
1633	pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
1634	pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
1635
1636	return VINF_SUCCESS;
1637	}
1638
1639	#endif /* IN_RING3 */
1640	#if defined(IN_RING0) \|\| defined(IN_RING3)
1641
1642	/**
1643	* Safely updates the SVGA_FIFO_BUSY register (in shared memory).
1644	*
1645	* @param pThis The shared VGA/VMSVGA instance data.
1646	* @param pThisCC The VGA/VMSVGA state for the current context.
1647	* @param fState The busy state.
1648	*/
1649	DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
1650	{
1651	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
1652
1653	if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
1654	{
1655	/* Race / unfortunately scheduling. Highly unlikly. */
1656	uint32_t cLoops = 64;
1657	do
1658	{
1659	ASMNopPause();
1660	fState = (pThis->svga.fBusy != 0);
1661	ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
1662	} while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
1663	}
1664	}
1665
1666
1667	/**
1668	* Update the scanline pitch in response to the guest changing mode
1669	* width/bpp.
1670	*
1671	* @param pThis The shared VGA/VMSVGA state.
1672	* @param pThisCC The VGA/VMSVGA state for the current context.
1673	*/
1674	DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
1675	{
1676	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
1677	uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
1678	uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
1679	uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
1680
1681	/* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
1682	* it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
1683	* location but it has a different meaning.
1684	*/
1685	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1686	uFifoPitchLock = 0;
1687
1688	/* Sanitize values. */
1689	if ((uFifoPitchLock < 200) \|\| (uFifoPitchLock > 32768))
1690	uFifoPitchLock = 0;
1691	if ((uRegPitchLock < 200) \|\| (uRegPitchLock > 32768))
1692	uRegPitchLock = 0;
1693
1694	/* Prefer the register value to the FIFO value.*/
1695	if (uRegPitchLock)
1696	pThis->svga.cbScanline = uRegPitchLock;
1697	else if (uFifoPitchLock)
1698	pThis->svga.cbScanline = uFifoPitchLock;
1699	else
1700	pThis->svga.cbScanline = pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
1701
1702	if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
1703	pThis->svga.u32PitchLock = pThis->svga.cbScanline;
1704	}
1705
1706	#endif /* IN_RING0 \|\| IN_RING3 */
1707
1708	#ifdef IN_RING3
1709
1710	/**
1711	* Sends cursor position and visibility information from legacy
1712	* SVGA registers to the front-end.
1713	*/
1714	static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
1715	{
1716	/*
1717	* Writing the X/Y/ID registers does not trigger changes; only writing the
1718	* SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
1719	* We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
1720	* register if they don't have to.
1721	*/
1722	uint32_t x, y, idScreen;
1723	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
1724
1725	x = pThis->svga.uCursorX;
1726	y = pThis->svga.uCursorY;
1727	idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
1728
1729	/* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
1730	* were extended as follows:
1731	*
1732	* SVGA_CURSOR_ON_HIDE 0
1733	* SVGA_CURSOR_ON_SHOW 1
1734	* SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
1735	* SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
1736	*
1737	* Since we never draw the cursor into the guest's framebuffer, we do not need to
1738	* distinguish between the non-zero values but still remember them.
1739	*/
1740	if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
1741	{
1742	LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
1743	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
1744	}
1745	pThis->svga.uCursorOn = uCursorOn;
1746	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
1747	}
1748
1749	#endif /* IN_RING3 */
1750
1751
1752	/**
1753	* Write port register
1754	*
1755	* @returns Strict VBox status code.
1756	* @param pDevIns The device instance.
1757	* @param pThis The shared VGA/VMSVGA state.
1758	* @param pThisCC The VGA/VMSVGA state for the current context.
1759	* @param u32 Value to write
1760	*/
1761	static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
1762	{
1763	#ifdef IN_RING3
1764	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
1765	#endif
1766	VBOXSTRICTRC rc = VINF_SUCCESS;
1767	RT_NOREF(pThisCC);
1768
1769	/* Rough index register validation. */
1770	uint32_t idxReg = pThis->svga.u32IndexReg;
1771	#if !defined(IN_RING3) && defined(VBOX_STRICT)
1772	ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1773	VINF_IOM_R3_IOPORT_WRITE);
1774	#else
1775	ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
1776	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
1777	VINF_SUCCESS);
1778	#endif
1779	RT_UNTRUSTED_VALIDATED_FENCE();
1780
1781	/* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
1782	if ( idxReg >= SVGA_REG_ID_0_TOP
1783	&& pThis->svga.u32SVGAId == SVGA_ID_0)
1784	{
1785	idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
1786	Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
1787	}
1788	#ifdef LOG_ENABLED
1789	if (idxReg != SVGA_REG_DEV_CAP)
1790	Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
1791	else
1792	Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
1793	#endif
1794	/* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
1795	switch (idxReg)
1796	{
1797	case SVGA_REG_WIDTH:
1798	case SVGA_REG_HEIGHT:
1799	case SVGA_REG_PITCHLOCK:
1800	case SVGA_REG_BITS_PER_PIXEL:
1801	pThis->svga.fGFBRegisters = true;
1802	break;
1803	default:
1804	break;
1805	}
1806
1807	switch (idxReg)
1808	{
1809	case SVGA_REG_ID:
1810	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
1811	if ( u32 == SVGA_ID_0
1812	\|\| u32 == SVGA_ID_1
1813	\|\| u32 == SVGA_ID_2)
1814	pThis->svga.u32SVGAId = u32;
1815	else
1816	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
1817	break;
1818
1819	case SVGA_REG_ENABLE:
1820	STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
1821	#ifdef IN_RING3
1822	if ( (u32 & SVGA_REG_ENABLE_ENABLE)
1823	&& pThis->svga.fEnabled == false)
1824	{
1825	/* Make a backup copy of the first 512kb in order to save font data etc. */
1826	/** @todo should probably swap here, rather than copy + zero */
1827	memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
1828	memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
1829	}
1830
1831	pThis->svga.fEnabled = u32;
1832	if (pThis->svga.fEnabled)
1833	{
1834	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
1835	&& pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
1836	{
1837	/* Keep the current mode. */
1838	pThis->svga.uWidth = pThisCC->pDrv->cx;
1839	pThis->svga.uHeight = pThisCC->pDrv->cy;
1840	pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
1841	}
1842
1843	if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
1844	&& pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
1845	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1846	# ifdef LOG_ENABLED
1847	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
1848	Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
1849	Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
1850	# endif
1851
1852	/* Disable or enable dirty page tracking according to the current fTraces value. */
1853	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1854
1855	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1856	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1857	pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /pHostFlags/);
1858
1859	/* Make the cursor visible again as needed. */
1860	if (pSVGAState->Cursor.fActive)
1861	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /fVisible/, false, 0, 0, 0, 0, NULL);
1862	}
1863	else
1864	{
1865	/* Make sure the cursor is off. */
1866	if (pSVGAState->Cursor.fActive)
1867	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /fVisible/, false, 0, 0, 0, 0, NULL);
1868
1869	/* Restore the text mode backup. */
1870	memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
1871
1872	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
1873
1874	/* Enable dirty page tracking again when going into legacy mode. */
1875	vmsvgaR3SetTraces(pDevIns, pThis, true);
1876
1877	/* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
1878	for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
1879	pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
1880
1881	/* Clear the pitch lock. */
1882	pThis->svga.u32PitchLock = 0;
1883	}
1884	#else /* !IN_RING3 */
1885	rc = VINF_IOM_R3_IOPORT_WRITE;
1886	#endif /* !IN_RING3 */
1887	break;
1888
1889	case SVGA_REG_WIDTH:
1890	STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
1891	if (pThis->svga.uWidth != u32)
1892	{
1893	#if defined(IN_RING3) \|\| defined(IN_RING0)
1894	pThis->svga.uWidth = u32;
1895	vmsvgaHCUpdatePitch(pThis, pThisCC);
1896	if (pThis->svga.fEnabled)
1897	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1898	#else
1899	rc = VINF_IOM_R3_IOPORT_WRITE;
1900	#endif
1901	}
1902	/* else: nop */
1903	break;
1904
1905	case SVGA_REG_HEIGHT:
1906	STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
1907	if (pThis->svga.uHeight != u32)
1908	{
1909	pThis->svga.uHeight = u32;
1910	if (pThis->svga.fEnabled)
1911	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1912	}
1913	/* else: nop */
1914	break;
1915
1916	case SVGA_REG_DEPTH:
1917	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
1918	/** @todo read-only?? */
1919	break;
1920
1921	case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
1922	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
1923	if (pThis->svga.uBpp != u32)
1924	{
1925	#if defined(IN_RING3) \|\| defined(IN_RING0)
1926	pThis->svga.uBpp = u32;
1927	vmsvgaHCUpdatePitch(pThis, pThisCC);
1928	if (pThis->svga.fEnabled)
1929	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
1930	#else
1931	rc = VINF_IOM_R3_IOPORT_WRITE;
1932	#endif
1933	}
1934	/* else: nop */
1935	break;
1936
1937	case SVGA_REG_PSEUDOCOLOR:
1938	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
1939	break;
1940
1941	case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
1942	#ifdef IN_RING3
1943	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
1944	pThis->svga.fConfigured = u32;
1945	/* Disabling the FIFO enables tracing (dirty page detection) by default. */
1946	if (!pThis->svga.fConfigured)
1947	pThis->svga.fTraces = true;
1948	vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
1949	#else
1950	rc = VINF_IOM_R3_IOPORT_WRITE;
1951	#endif
1952	break;
1953
1954	case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
1955	STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
1956	if ( pThis->svga.fEnabled
1957	&& pThis->svga.fConfigured)
1958	{
1959	#if defined(IN_RING3) \|\| defined(IN_RING0)
1960	Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
1961	/*
1962	* The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
1963	* at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
1964	*/
1965	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE \| VMSVGA_BUSY_F_FIFO);
1966	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
1967	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
1968
1969	/* Kick the FIFO thread to start processing commands again. */
1970	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
1971	#else
1972	rc = VINF_IOM_R3_IOPORT_WRITE;
1973	#endif
1974	}
1975	/* else nothing to do. */
1976	else
1977	Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
1978
1979	break;
1980
1981	case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
1982	STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
1983	break;
1984
1985	case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
1986	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
1987	pThis->svga.u32GuestId = u32;
1988	break;
1989
1990	case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
1991	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
1992	pThis->svga.u32PitchLock = u32;
1993	/* Should this also update the FIFO pitch lock? Unclear. */
1994	break;
1995
1996	case SVGA_REG_IRQMASK: /* Interrupt mask */
1997	STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
1998	pThis->svga.u32IrqMask = u32;
1999
2000	/* Irq pending after the above change? */
2001	if (pThis->svga.u32IrqStatus & u32)
2002	{
2003	Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
2004	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
2005	}
2006	else
2007	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2008	break;
2009
2010	/* Mouse cursor support */
2011	case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
2012	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
2013	pThis->svga.uCursorID = u32;
2014	break;
2015
2016	case SVGA_REG_CURSOR_X:
2017	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
2018	pThis->svga.uCursorX = u32;
2019	break;
2020
2021	case SVGA_REG_CURSOR_Y:
2022	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
2023	pThis->svga.uCursorY = u32;
2024	break;
2025
2026	case SVGA_REG_CURSOR_ON:
2027	#ifdef IN_RING3
2028	/* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
2029	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
2030	vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
2031	#else
2032	rc = VINF_IOM_R3_IOPORT_WRITE;
2033	#endif
2034	break;
2035
2036	/* Legacy multi-monitor support */
2037	case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
2038	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
2039	break;
2040	case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
2041	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
2042	break;
2043	case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
2044	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
2045	break;
2046	case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
2047	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
2048	break;
2049	case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
2050	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
2051	break;
2052	case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
2053	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
2054	break;
2055	case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
2056	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
2057	break;
2058	#ifdef VBOX_WITH_VMSVGA3D
2059	/* See "Guest memory regions" below. */
2060	case SVGA_REG_GMR_ID:
2061	STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
2062	pThis->svga.u32CurrentGMRId = u32;
2063	break;
2064
2065	case SVGA_REG_GMR_DESCRIPTOR:
2066	# ifndef IN_RING3
2067	rc = VINF_IOM_R3_IOPORT_WRITE;
2068	break;
2069	# else /* IN_RING3 */
2070	{
2071	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
2072
2073	/* Validate current GMR id. */
2074	uint32_t idGMR = pThis->svga.u32CurrentGMRId;
2075	AssertBreak(idGMR < pThis->svga.cGMR);
2076	RT_UNTRUSTED_VALIDATED_FENCE();
2077
2078	/* Free the old GMR if present. */
2079	vmsvgaR3GmrFree(pThisCC, idGMR);
2080
2081	/* Just undefine the GMR? */
2082	RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
2083	if (GCPhys == 0)
2084	{
2085	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
2086	break;
2087	}
2088
2089
2090	/* Never cross a page boundary automatically. */
2091	const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
2092	uint32_t cPagesTotal = 0;
2093	uint32_t iDesc = 0;
2094	PVMSVGAGMRDESCRIPTOR paDescs = NULL;
2095	uint32_t cLoops = 0;
2096	RTGCPHYS GCPhysBase = GCPhys;
2097	while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
2098	{
2099	/* Read descriptor. */
2100	SVGAGuestMemDescriptor desc;
2101	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
2102	AssertRCBreak(VBOXSTRICTRC_VAL(rc));
2103
2104	if (desc.numPages != 0)
2105	{
2106	AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2107	cPagesTotal += desc.numPages;
2108	AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
2109
2110	if ((iDesc & 15) == 0)
2111	{
2112	void pvNew = RTMemRealloc(paDescs, (iDesc + 16) sizeof(VMSVGAGMRDESCRIPTOR));
2113	AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
2114	paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
2115	}
2116
2117	paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2118	paDescs[iDesc++].numPages = desc.numPages;
2119
2120	/* Continue with the next descriptor. */
2121	GCPhys += sizeof(desc);
2122	}
2123	else if (desc.ppn == 0)
2124	break; /* terminator */
2125	else /* Pointer to the next physical page of descriptors. */
2126	GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
2127
2128	cLoops++;
2129	AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
2130	}
2131
2132	AssertStmt(iDesc > 0 \|\| RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
2133	if (RT_SUCCESS(rc))
2134	{
2135	/* Commit the GMR. */
2136	pSVGAState->paGMR[idGMR].paDesc = paDescs;
2137	pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
2138	pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
2139	pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
2140	Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
2141	Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
2142	idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
2143	}
2144	else
2145	{
2146	RTMemFree(paDescs);
2147	STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
2148	}
2149	break;
2150	}
2151	# endif /* IN_RING3 */
2152	#endif // VBOX_WITH_VMSVGA3D
2153
2154	case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
2155	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
2156	if (pThis->svga.fTraces == u32)
2157	break; /* nothing to do */
2158
2159	#ifdef IN_RING3
2160	vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
2161	#else
2162	rc = VINF_IOM_R3_IOPORT_WRITE;
2163	#endif
2164	break;
2165
2166	case SVGA_REG_TOP: /* Must be 1 more than the last register */
2167	STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
2168	break;
2169
2170	case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
2171	STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
2172	Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
2173	break;
2174
2175	/*
2176	* SVGA_CAP_GBOBJECTS+ registers.
2177	*/
2178	case SVGA_REG_COMMAND_LOW:
2179	{
2180	/* Lower 32 bits of command buffer physical address and submit the command buffer. */
2181	#ifdef IN_RING3
2182	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
2183	pThis->svga.u32RegCommandLow = u32;
2184
2185	/* "lower 6 bits are used for the SVGACBContext" */
2186	RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
2187	GCPhysCB <<= 32;
2188	GCPhysCB \|= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
2189	SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
2190	vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
2191	#else
2192	rc = VINF_IOM_R3_IOPORT_WRITE;
2193	#endif
2194	break;
2195	}
2196
2197	case SVGA_REG_COMMAND_HIGH:
2198	/* Upper 32 bits of command buffer PA. */
2199	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
2200	pThis->svga.u32RegCommandHigh = u32;
2201	break;
2202
2203	case SVGA_REG_DEV_CAP:
2204	/* Write dev cap index, read value */
2205	STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
2206	pThis->svga.u32DevCapIndex = u32;
2207	break;
2208
2209	case SVGA_REG_CMD_PREPEND_LOW:
2210	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
2211	/* Not supported. */
2212	break;
2213
2214	case SVGA_REG_CMD_PREPEND_HIGH:
2215	STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
2216	/* Not supported. */
2217	break;
2218
2219	case SVGA_REG_FB_START:
2220	case SVGA_REG_MEM_START:
2221	case SVGA_REG_HOST_BITS_PER_PIXEL:
2222	case SVGA_REG_MAX_WIDTH:
2223	case SVGA_REG_MAX_HEIGHT:
2224	case SVGA_REG_VRAM_SIZE:
2225	case SVGA_REG_FB_SIZE:
2226	case SVGA_REG_CAPABILITIES:
2227	case SVGA_REG_MEM_SIZE:
2228	case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
2229	case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
2230	case SVGA_REG_BYTES_PER_LINE:
2231	case SVGA_REG_FB_OFFSET:
2232	case SVGA_REG_RED_MASK:
2233	case SVGA_REG_GREEN_MASK:
2234	case SVGA_REG_BLUE_MASK:
2235	case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
2236	case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
2237	case SVGA_REG_GMR_MAX_IDS:
2238	case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
2239	case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
2240	case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
2241	case SVGA_REG_SCREENTARGET_MAX_WIDTH:
2242	case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
2243	case SVGA_REG_MOB_MAX_SIZE:
2244	/* Read only - ignore. */
2245	Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
2246	STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
2247	break;
2248
2249	default:
2250	{
2251	uint32_t offReg;
2252	if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
2253	{
2254	RT_UNTRUSTED_VALIDATED_FENCE();
2255	pThis->svga.au32ScratchRegion[offReg] = u32;
2256	STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
2257	}
2258	else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
2259	{
2260	/* Note! Using last_palette rather than palette here to preserve the VGA one.
2261	Btw, see rgb_to_pixel32. */
2262	STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
2263	u32 &= 0xff;
2264	RT_UNTRUSTED_VALIDATED_FENCE();
2265	uint32_t uRgb = pThis->last_palette[offReg / 3];
2266	switch (offReg % 3)
2267	{
2268	case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) \| (u32 << 16); break; /* red */
2269	case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) \| (u32 << 8); break; /* green */
2270	case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) \| u32 ; break; /* blue */
2271	}
2272	pThis->last_palette[offReg / 3] = uRgb;
2273	}
2274	else
2275	{
2276	#if !defined(IN_RING3) && defined(VBOX_STRICT)
2277	rc = VINF_IOM_R3_IOPORT_WRITE;
2278	#else
2279	STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
2280	AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
2281	#endif
2282	}
2283	break;
2284	}
2285	}
2286	return rc;
2287	}
2288
2289	/**
2290	* @callback_method_impl{FNIOMIOPORTNEWIN}
2291	*/
2292	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2293	{
2294	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2295	RT_NOREF_PV(pvUser);
2296
2297	/* Only dword accesses. */
2298	if (cb == 4)
2299	{
2300	switch (offPort)
2301	{
2302	case SVGA_INDEX_PORT:
2303	*pu32 = pThis->svga.u32IndexReg;
2304	break;
2305
2306	case SVGA_VALUE_PORT:
2307	return vmsvgaReadPort(pDevIns, pThis, pu32);
2308
2309	case SVGA_BIOS_PORT:
2310	Log(("Ignoring BIOS port read\n"));
2311	*pu32 = 0;
2312	break;
2313
2314	case SVGA_IRQSTATUS_PORT:
2315	LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
2316	*pu32 = pThis->svga.u32IrqStatus;
2317	break;
2318
2319	default:
2320	ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
2321	*pu32 = UINT32_MAX;
2322	break;
2323	}
2324	}
2325	else
2326	{
2327	Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
2328	*pu32 = UINT32_MAX;
2329	}
2330	return VINF_SUCCESS;
2331	}
2332
2333	/**
2334	* @callback_method_impl{FNIOMIOPORTNEWOUT}
2335	*/
2336	DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2337	{
2338	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2339	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2340	RT_NOREF_PV(pvUser);
2341
2342	/* Only dword accesses. */
2343	if (cb == 4)
2344	switch (offPort)
2345	{
2346	case SVGA_INDEX_PORT:
2347	pThis->svga.u32IndexReg = u32;
2348	break;
2349
2350	case SVGA_VALUE_PORT:
2351	return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
2352
2353	case SVGA_BIOS_PORT:
2354	Log(("Ignoring BIOS port write (val=%x)\n", u32));
2355	break;
2356
2357	case SVGA_IRQSTATUS_PORT:
2358	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
2359	ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
2360	/* Clear the irq in case all events have been cleared. */
2361	if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
2362	{
2363	Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
2364	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
2365	}
2366	break;
2367
2368	default:
2369	ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
2370	break;
2371	}
2372	else
2373	Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
2374
2375	return VINF_SUCCESS;
2376	}
2377
2378	#ifdef IN_RING3
2379
2380	# ifdef DEBUG_FIFO_ACCESS
2381	/**
2382	* Handle FIFO memory access.
2383	* @returns VBox status code.
2384	* @param pVM VM handle.
2385	* @param pThis The shared VGA/VMSVGA instance data.
2386	* @param GCPhys The access physical address.
2387	* @param fWriteAccess Read or write access
2388	*/
2389	static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
2390	{
2391	RT_NOREF(pVM);
2392	RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
2393	uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
2394
2395	switch (GCPhysOffset >> 2)
2396	{
2397	case SVGA_FIFO_MIN:
2398	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2399	break;
2400	case SVGA_FIFO_MAX:
2401	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2402	break;
2403	case SVGA_FIFO_NEXT_CMD:
2404	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2405	break;
2406	case SVGA_FIFO_STOP:
2407	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2408	break;
2409	case SVGA_FIFO_CAPABILITIES:
2410	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2411	break;
2412	case SVGA_FIFO_FLAGS:
2413	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2414	break;
2415	case SVGA_FIFO_FENCE:
2416	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2417	break;
2418	case SVGA_FIFO_3D_HWVERSION:
2419	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2420	break;
2421	case SVGA_FIFO_PITCHLOCK:
2422	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2423	break;
2424	case SVGA_FIFO_CURSOR_ON:
2425	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2426	break;
2427	case SVGA_FIFO_CURSOR_X:
2428	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2429	break;
2430	case SVGA_FIFO_CURSOR_Y:
2431	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2432	break;
2433	case SVGA_FIFO_CURSOR_COUNT:
2434	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2435	break;
2436	case SVGA_FIFO_CURSOR_LAST_UPDATED:
2437	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2438	break;
2439	case SVGA_FIFO_RESERVED:
2440	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2441	break;
2442	case SVGA_FIFO_CURSOR_SCREEN_ID:
2443	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2444	break;
2445	case SVGA_FIFO_DEAD:
2446	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2447	break;
2448	case SVGA_FIFO_3D_HWVERSION_REVISED:
2449	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2450	break;
2451	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
2452	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2453	break;
2454	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
2455	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2456	break;
2457	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
2458	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2459	break;
2460	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
2461	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2462	break;
2463	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
2464	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2465	break;
2466	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
2467	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2468	break;
2469	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
2470	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2471	break;
2472	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
2473	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2474	break;
2475	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
2476	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2477	break;
2478	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
2479	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2480	break;
2481	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
2482	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2483	break;
2484	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
2485	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2486	break;
2487	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
2488	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2489	break;
2490	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
2491	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2492	break;
2493	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
2494	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2495	break;
2496	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
2497	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2498	break;
2499	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
2500	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2501	break;
2502	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
2503	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2504	break;
2505	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
2506	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2507	break;
2508	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
2509	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2510	break;
2511	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
2512	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2513	break;
2514	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
2515	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2516	break;
2517	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
2518	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2519	break;
2520	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
2521	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2522	break;
2523	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
2524	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2525	break;
2526	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
2527	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2528	break;
2529	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
2530	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2531	break;
2532	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
2533	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2534	break;
2535	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
2536	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2537	break;
2538	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
2539	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2540	break;
2541	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
2542	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2543	break;
2544	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
2545	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2546	break;
2547	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
2548	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2549	break;
2550	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
2551	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2552	break;
2553	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
2554	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2555	break;
2556	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
2557	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2558	break;
2559	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
2560	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2561	break;
2562	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
2563	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2564	break;
2565	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
2566	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2567	break;
2568	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
2569	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2570	break;
2571	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
2572	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2573	break;
2574	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
2575	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2576	break;
2577	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
2578	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2579	break;
2580	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
2581	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2582	break;
2583	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
2584	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2585	break;
2586	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
2587	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2588	break;
2589	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
2590	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2591	break;
2592	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
2593	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2594	break;
2595	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
2596	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2597	break;
2598	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
2599	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2600	break;
2601	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
2602	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2603	break;
2604	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
2605	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2606	break;
2607	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
2608	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2609	break;
2610	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
2611	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2612	break;
2613	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
2614	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2615	break;
2616	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
2617	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2618	break;
2619	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
2620	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2621	break;
2622	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
2623	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2624	break;
2625	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
2626	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2627	break;
2628	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
2629	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2630	break;
2631	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
2632	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2633	break;
2634	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
2635	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2636	break;
2637	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
2638	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2639	break;
2640	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
2641	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2642	break;
2643	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
2644	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2645	break;
2646	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
2647	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2648	break;
2649	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
2650	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2651	break;
2652	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
2653	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2654	break;
2655	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
2656	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2657	break;
2658	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
2659	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2660	break;
2661	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
2662	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2663	break;
2664	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
2665	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2666	break;
2667	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
2668	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2669	break;
2670	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
2671	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2672	break;
2673	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
2674	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2675	break;
2676	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
2677	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2678	break;
2679	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
2680	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2681	break;
2682	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
2683	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2684	break;
2685	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
2686	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2687	break;
2688	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
2689	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2690	break;
2691	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
2692	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2693	break;
2694	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
2695	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2696	break;
2697	case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
2698	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2699	break;
2700	case SVGA_FIFO_3D_CAPS_LAST:
2701	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2702	break;
2703	case SVGA_FIFO_GUEST_3D_HWVERSION:
2704	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2705	break;
2706	case SVGA_FIFO_FENCE_GOAL:
2707	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2708	break;
2709	case SVGA_FIFO_BUSY:
2710	Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
2711	break;
2712	default:
2713	Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
2714	break;
2715	}
2716
2717	return VINF_EM_RAW_EMULATE_INSTR;
2718	}
2719	# endif /* DEBUG_FIFO_ACCESS */
2720
2721	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
2722	/**
2723	* HC access handler for the FIFO.
2724	*
2725	* @returns VINF_SUCCESS if the handler have carried out the operation.
2726	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2727	* @param pVM VM Handle.
2728	* @param pVCpu The cross context CPU structure for the calling EMT.
2729	* @param GCPhys The physical address the guest is writing to.
2730	* @param pvPhys The HC mapping of that address.
2731	* @param pvBuf What the guest is reading/writing.
2732	* @param cbBuf How much it's reading/writing.
2733	* @param enmAccessType The access type.
2734	* @param enmOrigin Who is making the access.
2735	* @param pvUser User argument.
2736	*/
2737	static DECLCALLBACK(VBOXSTRICTRC)
2738	vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2739	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2740	{
2741	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
2742	PVGASTATE pThis = (PVGASTATE)pvUser;
2743	AssertPtr(pThis);
2744
2745	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
2746	/*
2747	* Wake up the FIFO thread as it might have work to do now.
2748	*/
2749	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
2750	AssertLogRelRC(rc);
2751	# endif
2752
2753	# ifdef DEBUG_FIFO_ACCESS
2754	/*
2755	* When in debug-fifo-access mode, we do not disable the access handler,
2756	* but leave it on as we wish to catch all access.
2757	*/
2758	Assert(GCPhys >= pThis->svga.GCPhysFIFO);
2759	rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
2760	# elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
2761	/*
2762	* Temporarily disable the access handler now that we've kicked the FIFO thread.
2763	*/
2764	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
2765	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
2766	# endif
2767	if (RT_SUCCESS(rc))
2768	return VINF_PGM_HANDLER_DO_DEFAULT;
2769	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
2770	return rc;
2771	}
2772	# endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER \|\| DEBUG_FIFO_ACCESS */
2773
2774	#endif /* IN_RING3 */
2775
2776	#ifdef DEBUG_GMR_ACCESS
2777	# ifdef IN_RING3
2778
2779	/**
2780	* HC access handler for GMRs.
2781	*
2782	* @returns VINF_SUCCESS if the handler have carried out the operation.
2783	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2784	* @param pVM VM Handle.
2785	* @param pVCpu The cross context CPU structure for the calling EMT.
2786	* @param GCPhys The physical address the guest is writing to.
2787	* @param pvPhys The HC mapping of that address.
2788	* @param pvBuf What the guest is reading/writing.
2789	* @param cbBuf How much it's reading/writing.
2790	* @param enmAccessType The access type.
2791	* @param enmOrigin Who is making the access.
2792	* @param pvUser User argument.
2793	*/
2794	static DECLCALLBACK(VBOXSTRICTRC)
2795	vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
2796	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2797	{
2798	PVGASTATE pThis = (PVGASTATE)pvUser;
2799	Assert(pThis);
2800	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2801	NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
2802
2803	Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
2804
2805	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2806	{
2807	PGMR pGMR = &pSVGAState->paGMR[i];
2808
2809	if (pGMR->numDescriptors)
2810	{
2811	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2812	{
2813	if ( GCPhys >= pGMR->paDesc[j].GCPhys
2814	&& GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
2815	{
2816	/*
2817	* Turn off the write handler for this particular page and make it R/W.
2818	* Then return telling the caller to restart the guest instruction.
2819	*/
2820	int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
2821	AssertRC(rc);
2822	return VINF_PGM_HANDLER_DO_DEFAULT;
2823	}
2824	}
2825	}
2826	}
2827
2828	return VINF_PGM_HANDLER_DO_DEFAULT;
2829	}
2830
2831	/** Callback handler for VMR3ReqCallWaitU */
2832	static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2833	{
2834	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2835	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2836	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2837	int rc;
2838
2839	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2840	{
2841	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
2842	pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
2843	pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
2844	AssertRC(rc);
2845	}
2846	return VINF_SUCCESS;
2847	}
2848
2849	/** Callback handler for VMR3ReqCallWaitU */
2850	static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
2851	{
2852	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2853	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2854	PGMR pGMR = &pSVGAState->paGMR[gmrId];
2855
2856	for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
2857	{
2858	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
2859	AssertRC(rc);
2860	}
2861	return VINF_SUCCESS;
2862	}
2863
2864	/** Callback handler for VMR3ReqCallWaitU */
2865	static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
2866	{
2867	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
2868
2869	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
2870	{
2871	PGMR pGMR = &pSVGAState->paGMR[i];
2872
2873	if (pGMR->numDescriptors)
2874	{
2875	for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
2876	{
2877	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
2878	AssertRC(rc);
2879	}
2880	}
2881	}
2882	return VINF_SUCCESS;
2883	}
2884
2885	# endif /* IN_RING3 */
2886	#endif /* DEBUG_GMR_ACCESS */
2887
2888	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
2889
2890	#ifdef IN_RING3
2891
2892
2893	/*
2894	*
2895	* Command buffer submission.
2896	*
2897	* Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
2898	*
2899	* EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
2900	* and wakes up the FIFO thread.
2901	*
2902	* FIFO thread fetches the command buffer from the queue, processes the commands and writes
2903	* the buffer header back to the guest memory.
2904	*
2905	* If buffers are preempted, then the EMT thread removes all buffers from the context queue.
2906	*
2907	*/
2908
2909
2910	/** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
2911	*
2912	* @param pDevIns The device instance.
2913	* @param GCPhysCB Guest physical address of the command buffer header.
2914	* @param status Command buffer status (SVGA_CB_STATUS_*).
2915	* @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
2916	* errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
2917	* @thread FIFO or EMT.
2918	*/
2919	static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
2920	{
2921	SVGACBHeader hdr;
2922	hdr.status = status;
2923	hdr.errorOffset = errorOffset;
2924	AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
2925	&& RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
2926	&& RT_OFFSETOF(SVGACBHeader, id) == 8);
2927	size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
2928	? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
2929	: RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
2930	PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
2931	}
2932
2933
2934	/** Raise an IRQ.
2935	*
2936	* @param pDevIns The device instance.
2937	* @param pThis The shared VGA/VMSVGA state.
2938	* @param u32IrqStatus SVGA_IRQFLAG_* bits.
2939	* @thread FIFO or EMT.
2940	*/
2941	static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
2942	{
2943	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
2944	AssertRC(rc);
2945
2946	if (pThis->svga.u32IrqMask & u32IrqStatus)
2947	{
2948	LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
2949	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
2950	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2951	}
2952
2953	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
2954	}
2955
2956
2957	/** Allocate a command buffer structure.
2958	*
2959	* @param pCmdBufCtx The command buffer context which must allocate the buffer.
2960	* @return Pointer to the allocated command buffer structure.
2961	*/
2962	static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
2963	{
2964	if (!pCmdBufCtx)
2965	return NULL;
2966
2967	PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
2968	if (pCmdBuf)
2969	{
2970	// RT_ZERO(pCmdBuf->nodeBuffer);
2971	pCmdBuf->pCmdBufCtx = pCmdBufCtx;
2972	// pCmdBuf->GCPhysCB = 0;
2973	// RT_ZERO(pCmdBuf->hdr);
2974	// pCmdBuf->pvCommands = NULL;
2975	}
2976
2977	return pCmdBuf;
2978	}
2979
2980
2981	/** Free a command buffer structure.
2982	*
2983	* @param pCmdBuf The command buffer pointer.
2984	*/
2985	static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
2986	{
2987	if (pCmdBuf)
2988	RTMemFree(pCmdBuf->pvCommands);
2989	RTMemFree(pCmdBuf);
2990	}
2991
2992
2993	/** Initialize a command buffer context.
2994	*
2995	* @param pCmdBufCtx The command buffer context.
2996	*/
2997	static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
2998	{
2999	RTListInit(&pCmdBufCtx->listSubmitted);
3000	pCmdBufCtx->cSubmitted = 0;
3001	}
3002
3003
3004	/** Destroy a command buffer context.
3005	*
3006	* @param pCmdBufCtx The command buffer context pointer.
3007	*/
3008	static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
3009	{
3010	if (!pCmdBufCtx)
3011	return;
3012
3013	if (pCmdBufCtx->listSubmitted.pNext)
3014	{
3015	/* If the list has been initialized. */
3016	PVMSVGACMDBUF pIter, pNext;
3017	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3018	{
3019	RTListNodeRemove(&pIter->nodeBuffer);
3020	--pCmdBufCtx->cSubmitted;
3021	vmsvgaR3CmdBufFree(pIter);
3022	}
3023	}
3024	Assert(pCmdBufCtx->cSubmitted == 0);
3025	pCmdBufCtx->cSubmitted = 0;
3026	}
3027
3028
3029	/** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
3030	*
3031	* @param pSvgaR3State VMSVGA R3 state.
3032	* @param pCmd The command data.
3033	* @return SVGACBStatus code.
3034	* @thread EMT
3035	*/
3036	static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
3037	{
3038	/* Create or destroy a regular command buffer context. */
3039	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3040	return SVGA_CB_STATUS_COMMAND_ERROR;
3041	RT_UNTRUSTED_VALIDATED_FENCE();
3042
3043	SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
3044
3045	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3046	AssertRC(rc);
3047	if (pCmd->enable)
3048	{
3049	pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
3050	if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
3051	vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3052	else
3053	CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
3054	}
3055	else
3056	{
3057	vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
3058	pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
3059	}
3060	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3061
3062	return CBStatus;
3063	}
3064
3065
3066	/** Handles SVGA_DC_CMD_PREEMPT command.
3067	*
3068	* @param pDevIns The device instance.
3069	* @param pSvgaR3State VMSVGA R3 state.
3070	* @param pCmd The command data.
3071	* @return SVGACBStatus code.
3072	* @thread EMT
3073	*/
3074	static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
3075	{
3076	/* Remove buffers from the processing queue of the specified context. */
3077	if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
3078	return SVGA_CB_STATUS_COMMAND_ERROR;
3079	RT_UNTRUSTED_VALIDATED_FENCE();
3080
3081	PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
3082	RTLISTANCHOR listPreempted;
3083
3084	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3085	AssertRC(rc);
3086	if (pCmd->ignoreIDZero)
3087	{
3088	RTListInit(&listPreempted);
3089
3090	PVMSVGACMDBUF pIter, pNext;
3091	RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3092	{
3093	if (pIter->hdr.id == 0)
3094	continue;
3095
3096	RTListNodeRemove(&pIter->nodeBuffer);
3097	--pCmdBufCtx->cSubmitted;
3098	RTListAppend(&listPreempted, &pIter->nodeBuffer);
3099	}
3100	}
3101	else
3102	{
3103	RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
3104	}
3105	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3106
3107	PVMSVGACMDBUF pIter, pNext;
3108	RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
3109	{
3110	RTListNodeRemove(&pIter->nodeBuffer);
3111	vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
3112	vmsvgaR3CmdBufFree(pIter);
3113	}
3114
3115	return SVGA_CB_STATUS_COMPLETED;
3116	}
3117
3118
3119	/** @def VMSVGA_INC_CMD_SIZE_BREAK
3120	* Increments the size of the command cbCmd by a_cbMore.
3121	* Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
3122	* Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
3123	*/
3124	#define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
3125	if (1) { \
3126	cbCmd += (a_cbMore); \
3127	ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
3128	RT_UNTRUSTED_VALIDATED_FENCE(); \
3129	} else do {} while (0)
3130
3131
3132	/** Processes Device Context command buffer.
3133	*
3134	* @param pDevIns The device instance.
3135	* @param pSvgaR3State VMSVGA R3 state.
3136	* @param pvCommands Pointer to the command buffer.
3137	* @param cbCommands Size of the command buffer.
3138	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3139	* @return SVGACBStatus code.
3140	* @thread EMT
3141	*/
3142	static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd)
3143	{
3144	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3145
3146	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3147	uint32_t cbRemain = cbCommands;
3148	while (cbRemain)
3149	{
3150	/* Command identifier is a 32 bit value. */
3151	if (cbRemain < sizeof(uint32_t))
3152	{
3153	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3154	break;
3155	}
3156
3157	/* Fetch the command id. */
3158	uint32_t const cmdId = (uint32_t )pu8Cmd;
3159	uint32_t cbCmd = sizeof(uint32_t);
3160	switch (cmdId)
3161	{
3162	case SVGA_DC_CMD_NOP:
3163	{
3164	/* NOP */
3165	break;
3166	}
3167
3168	case SVGA_DC_CMD_START_STOP_CONTEXT:
3169	{
3170	SVGADCCmdStartStop pCmd = (SVGADCCmdStartStop )&pu8Cmd[cbCmd];
3171	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3172	CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
3173	break;
3174	}
3175
3176	case SVGA_DC_CMD_PREEMPT:
3177	{
3178	SVGADCCmdPreempt pCmd = (SVGADCCmdPreempt )&pu8Cmd[cbCmd];
3179	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3180	CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
3181	break;
3182	}
3183
3184	default:
3185	{
3186	/* Unsupported command. */
3187	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3188	break;
3189	}
3190	}
3191
3192	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3193	break;
3194
3195	pu8Cmd += cbCmd;
3196	cbRemain -= cbCmd;
3197	}
3198
3199	Assert(cbRemain <= cbCommands);
3200	*poffNextCmd = cbCommands - cbRemain;
3201	return CBstatus;
3202	}
3203
3204
3205	/** Submits a device context command buffer for synchronous processing.
3206	*
3207	* @param pDevIns The device instance.
3208	* @param pThisCC The VGA/VMSVGA state for the current context.
3209	* @param ppCmdBuf Pointer to the command buffer pointer.
3210	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3211	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3212	* @return SVGACBStatus code.
3213	* @thread EMT
3214	*/
3215	static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF ppCmdBuf, uint32_t poffNextCmd)
3216	{
3217	/* Synchronously process the device context commands. */
3218	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3219	return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (ppCmdBuf)->pvCommands, (ppCmdBuf)->hdr.length, poffNextCmd);
3220	}
3221
3222	/** Submits a command buffer for asynchronous processing by the FIFO thread.
3223	*
3224	* @param pDevIns The device instance.
3225	* @param pThis The shared VGA/VMSVGA state.
3226	* @param pThisCC The VGA/VMSVGA state for the current context.
3227	* @param ppCmdBuf Pointer to the command buffer pointer.
3228	* The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
3229	* @return SVGACBStatus code.
3230	* @thread EMT
3231	*/
3232	static SVGACBStatus vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
3233	{
3234	/* Command buffer submission. */
3235	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3236
3237	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3238
3239	PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
3240	PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
3241
3242	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3243	AssertRC(rc);
3244
3245	if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
3246	{
3247	RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
3248	++pCmdBufCtx->cSubmitted;
3249	ppCmdBuf = NULL; / Consume the buffer. */
3250	ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
3251	}
3252	else
3253	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3254
3255	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3256
3257	/* Inform the FIFO thread. */
3258	if (*ppCmdBuf == NULL)
3259	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
3260
3261	return CBstatus;
3262	}
3263
3264
3265	/** SVGA_REG_COMMAND_LOW write handler.
3266	* Submits a command buffer to the FIFO thread or processes a device context command.
3267	*
3268	* @param pDevIns The device instance.
3269	* @param pThis The shared VGA/VMSVGA state.
3270	* @param pThisCC The VGA/VMSVGA state for the current context.
3271	* @param GCPhysCB Guest physical address of the command buffer header.
3272	* @param CBCtx Context the command buffer is submitted to.
3273	* @thread EMT
3274	*/
3275	static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
3276	{
3277	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3278
3279	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3280	uint32_t offNextCmd = 0;
3281	uint32_t fIRQ = 0;
3282
3283	/* Get the context if the device has the capability. */
3284	PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
3285	if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
3286	{
3287	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3288	pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
3289	else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
3290	pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
3291	RT_UNTRUSTED_VALIDATED_FENCE();
3292	}
3293
3294	/* Allocate a new command buffer. */
3295	PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
3296	if (RT_LIKELY(pCmdBuf))
3297	{
3298	pCmdBuf->GCPhysCB = GCPhysCB;
3299
3300	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
3301	if (RT_SUCCESS(rc))
3302	{
3303	/* Verify the command buffer header. */
3304	if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
3305	&& (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ)) == 0 /* No unexpected flags. */
3306	&& pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
3307	{
3308	RT_UNTRUSTED_VALIDATED_FENCE();
3309
3310	/* Read the command buffer content. */
3311	pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
3312	if (pCmdBuf->pvCommands)
3313	{
3314	RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
3315	rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
3316	if (RT_SUCCESS(rc))
3317	{
3318	/* Submit the buffer. Device context buffers will be processed synchronously. */
3319	if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
3320	/* This usually processes the CB async and sets pCmbBuf to NULL. */
3321	CBstatus = vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, &pCmdBuf);
3322	else
3323	CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
3324	}
3325	else
3326	{
3327	ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
3328	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3329	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3330	}
3331	}
3332	else
3333	{
3334	/* No memory for commands. */
3335	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3336	}
3337	}
3338	else
3339	{
3340	ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
3341	CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
3342	fIRQ = SVGA_IRQFLAG_ERROR \| SVGA_IRQFLAG_COMMAND_BUFFER;
3343	}
3344	}
3345	else
3346	{
3347	LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
3348	ASSERT_GUEST_FAILED();
3349	/* Do not attempt to write the status. */
3350	}
3351
3352	/* Free the buffer if pfnCmdBufSubmit did not consume it. */
3353	vmsvgaR3CmdBufFree(pCmdBuf);
3354	}
3355	else
3356	{
3357	LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
3358	ASSERT_GUEST_FAILED();
3359	CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
3360	}
3361
3362	if (CBstatus != SVGA_CB_STATUS_NONE)
3363	{
3364	LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf->hdr.length, fIRQ));
3365	vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
3366	if (fIRQ)
3367	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
3368	}
3369	}
3370
3371
3372	/** Checks if there are some buffers to be processed.
3373	*
3374	* @param pThisCC The VGA/VMSVGA state for the current context.
3375	* @return true if buffers must be processed.
3376	* @thread FIFO
3377	*/
3378	static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
3379	{
3380	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3381	return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
3382	}
3383
3384
3385	/** Processes a command buffer.
3386	*
3387	* @param pDevIns The device instance.
3388	* @param pThis The shared VGA/VMSVGA state.
3389	* @param pThisCC The VGA/VMSVGA state for the current context.
3390	* @param pvCommands Pointer to the command buffer.
3391	* @param cbCommands Size of the command buffer.
3392	* @param poffNextCmd Where to store the offset of the first unprocessed command.
3393	* @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
3394	* @return SVGACBStatus code.
3395	* @thread FIFO
3396	*/
3397	static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, void const pvCommands, uint32_t cbCommands, uint32_t poffNextCmd, uint32_t *pu32IrqStatus)
3398	{
3399	SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
3400	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3401
3402	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
3403
3404	uint8_t const pu8Cmd = (uint8_t )pvCommands;
3405	uint32_t cbRemain = cbCommands;
3406	while (cbRemain)
3407	{
3408	/* Command identifier is a 32 bit value. */
3409	if (cbRemain < sizeof(uint32_t))
3410	{
3411	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3412	break;
3413	}
3414
3415	/* Fetch the command id.
3416	* 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
3417	* warning. Because we support some obsolete and deprecated commands, which are not included in
3418	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
3419	*/
3420	uint32_t const cmdId = (uint32_t )pu8Cmd;
3421	uint32_t cbCmd = sizeof(uint32_t);
3422
3423	LogFlowFunc(("%s %d\n", vmsvgaR3FifoCmdToString(cmdId), cmdId));
3424
3425	/* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
3426	* I.e. pu8Cmd + cbCmd must point to the next command.
3427	* However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
3428	* the cbCmd value is ignored (and pu8Cmd still points to the failed command).
3429	*/
3430	/** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
3431	switch (cmdId)
3432	{
3433	case SVGA_CMD_INVALID_CMD:
3434	{
3435	/* Nothing to do. */
3436	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
3437	break;
3438	}
3439
3440	case SVGA_CMD_FENCE:
3441	{
3442	SVGAFifoCmdFence pCmd = (SVGAFifoCmdFence )&pu8Cmd[cbCmd];
3443	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3444	STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
3445	Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
3446
3447	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
3448	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
3449	{
3450	pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
3451
3452	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
3453	{
3454	Log(("any fence irq\n"));
3455	*pu32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
3456	}
3457	else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
3458	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
3459	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
3460	{
3461	Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
3462	*pu32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
3463	}
3464	}
3465	else
3466	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
3467	break;
3468	}
3469
3470	case SVGA_CMD_UPDATE:
3471	{
3472	SVGAFifoCmdUpdate pCmd = (SVGAFifoCmdUpdate )&pu8Cmd[cbCmd];
3473	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3474	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
3475	break;
3476	}
3477
3478	case SVGA_CMD_UPDATE_VERBOSE:
3479	{
3480	SVGAFifoCmdUpdateVerbose pCmd = (SVGAFifoCmdUpdateVerbose )&pu8Cmd[cbCmd];
3481	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3482	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
3483	break;
3484	}
3485
3486	case SVGA_CMD_DEFINE_CURSOR:
3487	{
3488	/* Followed by bitmap data. */
3489	SVGAFifoCmdDefineCursor pCmd = (SVGAFifoCmdDefineCursor )&pu8Cmd[cbCmd];
3490	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3491
3492	/* Figure out the size of the bitmap data. */
3493	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3494	ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3495	ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3496	RT_UNTRUSTED_VALIDATED_FENCE();
3497
3498	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
3499	uint32_t const cbAndMask = cbAndLine * pCmd->height;
3500	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
3501	uint32_t const cbXorMask = cbXorLine * pCmd->height;
3502
3503	VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
3504	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
3505	break;
3506	}
3507
3508	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
3509	{
3510	/* Followed by bitmap data. */
3511	SVGAFifoCmdDefineAlphaCursor pCmd = (SVGAFifoCmdDefineAlphaCursor )&pu8Cmd[cbCmd];
3512	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3513
3514	/* Figure out the size of the bitmap data. */
3515	ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3516
3517	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
3518	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
3519	break;
3520	}
3521
3522	case SVGA_CMD_MOVE_CURSOR:
3523	{
3524	/* Deprecated; there should be no driver which requires this command. However, if
3525	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3526	* alignment.
3527	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3528	*/
3529	SVGAFifoCmdMoveCursor pCmd = (SVGAFifoCmdMoveCursor )&pu8Cmd[cbCmd];
3530	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3531	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
3532	break;
3533	}
3534
3535	case SVGA_CMD_DISPLAY_CURSOR:
3536	{
3537	/* Deprecated; there should be no driver which requires this command. However, if
3538	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
3539	* alignment.
3540	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
3541	*/
3542	SVGAFifoCmdDisplayCursor pCmd = (SVGAFifoCmdDisplayCursor )&pu8Cmd[cbCmd];
3543	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3544	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
3545	break;
3546	}
3547
3548	case SVGA_CMD_RECT_FILL:
3549	{
3550	SVGAFifoCmdRectFill pCmd = (SVGAFifoCmdRectFill )&pu8Cmd[cbCmd];
3551	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3552	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
3553	break;
3554	}
3555
3556	case SVGA_CMD_RECT_COPY:
3557	{
3558	SVGAFifoCmdRectCopy pCmd = (SVGAFifoCmdRectCopy )&pu8Cmd[cbCmd];
3559	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3560	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
3561	break;
3562	}
3563
3564	case SVGA_CMD_RECT_ROP_COPY:
3565	{
3566	SVGAFifoCmdRectRopCopy pCmd = (SVGAFifoCmdRectRopCopy )&pu8Cmd[cbCmd];
3567	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3568	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
3569	break;
3570	}
3571
3572	case SVGA_CMD_ESCAPE:
3573	{
3574	/* Followed by 'size' bytes of data. */
3575	SVGAFifoCmdEscape pCmd = (SVGAFifoCmdEscape )&pu8Cmd[cbCmd];
3576	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3577
3578	ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3579	RT_UNTRUSTED_VALIDATED_FENCE();
3580
3581	VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
3582	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
3583	break;
3584	}
3585	# ifdef VBOX_WITH_VMSVGA3D
3586	case SVGA_CMD_DEFINE_GMR2:
3587	{
3588	SVGAFifoCmdDefineGMR2 pCmd = (SVGAFifoCmdDefineGMR2 )&pu8Cmd[cbCmd];
3589	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3590	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
3591	break;
3592	}
3593
3594	case SVGA_CMD_REMAP_GMR2:
3595	{
3596	/* Followed by page descriptors or guest ptr. */
3597	SVGAFifoCmdRemapGMR2 pCmd = (SVGAFifoCmdRemapGMR2 )&pu8Cmd[cbCmd];
3598	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3599
3600	/* Calculate the size of what comes after next and fetch it. */
3601	uint32_t cbMore = 0;
3602	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
3603	cbMore = sizeof(SVGAGuestPtr);
3604	else
3605	{
3606	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
3607	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
3608	{
3609	cbMore = cbPageDesc;
3610	pCmd->numPages = 1;
3611	}
3612	else
3613	{
3614	ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3615	cbMore = cbPageDesc * pCmd->numPages;
3616	}
3617	}
3618	VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
3619	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
3620	# ifdef DEBUG_GMR_ACCESS
3621	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
3622	# endif
3623	break;
3624	}
3625	# endif /* VBOX_WITH_VMSVGA3D */
3626	case SVGA_CMD_DEFINE_SCREEN:
3627	{
3628	/* The size of this command is specified by the guest and depends on capabilities. */
3629	SVGAFifoCmdDefineScreen pCmd = (SVGAFifoCmdDefineScreen )&pu8Cmd[cbCmd];
3630	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
3631	ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
3632	RT_UNTRUSTED_VALIDATED_FENCE();
3633
3634	VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
3635	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
3636	break;
3637	}
3638
3639	case SVGA_CMD_DESTROY_SCREEN:
3640	{
3641	SVGAFifoCmdDestroyScreen pCmd = (SVGAFifoCmdDestroyScreen )&pu8Cmd[cbCmd];
3642	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3643	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
3644	break;
3645	}
3646
3647	case SVGA_CMD_DEFINE_GMRFB:
3648	{
3649	SVGAFifoCmdDefineGMRFB pCmd = (SVGAFifoCmdDefineGMRFB )&pu8Cmd[cbCmd];
3650	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3651	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
3652	break;
3653	}
3654
3655	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
3656	{
3657	SVGAFifoCmdBlitGMRFBToScreen pCmd = (SVGAFifoCmdBlitGMRFBToScreen )&pu8Cmd[cbCmd];
3658	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3659	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
3660	break;
3661	}
3662
3663	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
3664	{
3665	SVGAFifoCmdBlitScreenToGMRFB pCmd = (SVGAFifoCmdBlitScreenToGMRFB )&pu8Cmd[cbCmd];
3666	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3667	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
3668	break;
3669	}
3670
3671	case SVGA_CMD_ANNOTATION_FILL:
3672	{
3673	SVGAFifoCmdAnnotationFill pCmd = (SVGAFifoCmdAnnotationFill )&pu8Cmd[cbCmd];
3674	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3675	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
3676	break;
3677	}
3678
3679	case SVGA_CMD_ANNOTATION_COPY:
3680	{
3681	SVGAFifoCmdAnnotationCopy pCmd = (SVGAFifoCmdAnnotationCopy )&pu8Cmd[cbCmd];
3682	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
3683	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
3684	break;
3685	}
3686
3687	default:
3688	{
3689	# ifdef VBOX_WITH_VMSVGA3D
3690	if ( cmdId >= SVGA_3D_CMD_BASE
3691	&& cmdId < SVGA_3D_CMD_MAX)
3692	{
3693	RT_UNTRUSTED_VALIDATED_FENCE();
3694
3695	/* All 3d commands start with a common header, which defines the identifier and the size
3696	* of the command. The identifier has been already read. Fetch the size.
3697	*/
3698	uint32_t const pcbMore = (uint32_t const )&pu8Cmd[cbCmd];
3699	VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
3700	VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
3701	if (RT_LIKELY(pThis->svga.f3DEnabled))
3702	{ /* likely */ }
3703	else
3704	{
3705	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
3706	break;
3707	}
3708
3709	/* Command data begins after the 32 bit command length. */
3710	int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
3711	if (RT_SUCCESS(rc))
3712	{ /* likely */ }
3713	else
3714	{
3715	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3716	break;
3717	}
3718	}
3719	else
3720	# endif /* VBOX_WITH_VMSVGA3D */
3721	{
3722	/* Unsupported command. */
3723	STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
3724	ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
3725	LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
3726	CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
3727	break;
3728	}
3729	}
3730	}
3731
3732	if (CBstatus != SVGA_CB_STATUS_COMPLETED)
3733	break;
3734
3735	pu8Cmd += cbCmd;
3736	cbRemain -= cbCmd;
3737
3738	/* If this is not the last command in the buffer, then generate IRQ, if required.
3739	* This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
3740	* in the buffer (usually the case).
3741	*/
3742	if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
3743	{ /* likely */ }
3744	else
3745	{
3746	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
3747	*pu32IrqStatus = 0;
3748	}
3749	}
3750
3751	Assert(cbRemain <= cbCommands);
3752	*poffNextCmd = cbCommands - cbRemain;
3753	return CBstatus;
3754	}
3755
3756
3757	/** Process command buffers.
3758	*
3759	* @param pDevIns The device instance.
3760	* @param pThis The shared VGA/VMSVGA state.
3761	* @param pThisCC The VGA/VMSVGA state for the current context.
3762	* @param pThread Handle of the FIFO thread.
3763	* @thread FIFO
3764	*/
3765	static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
3766	{
3767	PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
3768
3769	for (;;)
3770	{
3771	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
3772	break;
3773
3774	/* See if there is a submitted buffer. */
3775	PVMSVGACMDBUF pCmdBuf = NULL;
3776
3777	int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
3778	AssertRC(rc);
3779
3780	/* It seems that a higher queue index has a higher priority.
3781	* See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
3782	*/
3783	for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
3784	{
3785	PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
3786	if (pCmdBufCtx)
3787	{
3788	pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
3789	if (pCmdBuf)
3790	{
3791	Assert(pCmdBufCtx->cSubmitted > 0);
3792	--pCmdBufCtx->cSubmitted;
3793	break;
3794	}
3795	}
3796	}
3797
3798	if (!pCmdBuf)
3799	{
3800	ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
3801	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3802	break;
3803	}
3804
3805	RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
3806
3807	SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
3808	uint32_t offNextCmd = 0;
3809	uint32_t u32IrqStatus = 0;
3810
3811	/* Process one buffer. */
3812	CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
3813
3814	if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
3815	u32IrqStatus \|= SVGA_IRQFLAG_COMMAND_BUFFER;
3816	if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
3817	u32IrqStatus \|= SVGA_IRQFLAG_ERROR;
3818
3819	vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
3820	if (u32IrqStatus)
3821	vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
3822
3823	vmsvgaR3CmdBufFree(pCmdBuf);
3824	}
3825	}
3826
3827
3828	/**
3829	* Worker for vmsvgaR3FifoThread that handles an external command.
3830	*
3831	* @param pDevIns The device instance.
3832	* @param pThis The shared VGA/VMSVGA instance data.
3833	* @param pThisCC The VGA/VMSVGA state for ring-3.
3834	*/
3835	static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
3836	{
3837	uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
3838	switch (pThis->svga.u8FIFOExtCommand)
3839	{
3840	case VMSVGA_FIFO_EXTCMD_RESET:
3841	Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
3842	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3843
3844	vmsvgaR3ResetScreens(pThis, pThisCC);
3845	# ifdef VBOX_WITH_VMSVGA3D
3846	if (pThis->svga.f3DEnabled)
3847	{
3848	/* The 3d subsystem must be reset from the fifo thread. */
3849	vmsvga3dReset(pThisCC);
3850	}
3851	# endif
3852	break;
3853
3854	case VMSVGA_FIFO_EXTCMD_POWEROFF:
3855	Log(("vmsvgaR3FifoLoop: power off.\n"));
3856	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3857
3858	/* The screens must be reset on the FIFO thread, because they may use 3D resources. */
3859	vmsvgaR3ResetScreens(pThis, pThisCC);
3860	break;
3861
3862	case VMSVGA_FIFO_EXTCMD_TERMINATE:
3863	Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
3864	Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
3865	# ifdef VBOX_WITH_VMSVGA3D
3866	if (pThis->svga.f3DEnabled)
3867	{
3868	/* The 3d subsystem must be shut down from the fifo thread. */
3869	vmsvga3dTerminate(pThisCC);
3870	}
3871	# endif
3872	break;
3873
3874	case VMSVGA_FIFO_EXTCMD_SAVESTATE:
3875	{
3876	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3877	PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
3878	AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
3879	vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
3880	# ifdef VBOX_WITH_VMSVGA3D
3881	if (pThis->svga.f3DEnabled)
3882	vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
3883	# endif
3884	break;
3885	}
3886
3887	case VMSVGA_FIFO_EXTCMD_LOADSTATE:
3888	{
3889	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3890	PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
3891	AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
3892	vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3893	# ifdef VBOX_WITH_VMSVGA3D
3894	if (pThis->svga.f3DEnabled)
3895	vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3896	# endif
3897	break;
3898	}
3899
3900	case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
3901	{
3902	# ifdef VBOX_WITH_VMSVGA3D
3903	uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
3904	Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
3905	vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
3906	# endif
3907	break;
3908	}
3909
3910
3911	default:
3912	AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
3913	break;
3914	}
3915
3916	/*
3917	* Signal the end of the external command.
3918	*/
3919	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3920	pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3921	ASMMemoryFence(); /* paranoia^2 */
3922	int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
3923	AssertLogRelRC(rc);
3924	}
3925
3926	/**
3927	* Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
3928	* doing a job on the FIFO thread (even when it's officially suspended).
3929	*
3930	* @returns VBox status code (fully asserted).
3931	* @param pDevIns The device instance.
3932	* @param pThis The shared VGA/VMSVGA instance data.
3933	* @param pThisCC The VGA/VMSVGA state for ring-3.
3934	* @param uExtCmd The command to execute on the FIFO thread.
3935	* @param pvParam Pointer to command parameters.
3936	* @param cMsWait The time to wait for the command, given in
3937	* milliseconds.
3938	*/
3939	static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
3940	uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
3941	{
3942	Assert(cMsWait >= RT_MS_1SEC * 5);
3943	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
3944	("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
3945
3946	int rc;
3947	PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
3948	PDMTHREADSTATE enmState = pThread->enmState;
3949	if (enmState == PDMTHREADSTATE_SUSPENDED)
3950	{
3951	/*
3952	* The thread is suspended, we have to temporarily wake it up so it can
3953	* perform the task.
3954	* (We ASSUME not racing code here, both wrt thread state and ext commands.)
3955	*/
3956	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
3957	/* Post the request. */
3958	pThis->svga.fFifoExtCommandWakeup = true;
3959	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3960	pThis->svga.u8FIFOExtCommand = uExtCmd;
3961	ASMMemoryFence(); /* paranoia^3 */
3962
3963	/* Resume the thread. */
3964	rc = PDMDevHlpThreadResume(pDevIns, pThread);
3965	AssertLogRelRC(rc);
3966	if (RT_SUCCESS(rc))
3967	{
3968	/* Wait. Take care in case the semaphore was already posted (same as below). */
3969	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3970	if ( rc == VINF_SUCCESS
3971	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
3972	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
3973	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
3974	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
3975
3976	/* suspend the thread */
3977	pThis->svga.fFifoExtCommandWakeup = false;
3978	int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
3979	AssertLogRelRC(rc2);
3980	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
3981	rc = rc2;
3982	}
3983	pThis->svga.fFifoExtCommandWakeup = false;
3984	pThisCC->svga.pvFIFOExtCmdParam = NULL;
3985	}
3986	else if (enmState == PDMTHREADSTATE_RUNNING)
3987	{
3988	/*
3989	* The thread is running, should only happen during reset and vmsvga3dsfc.
3990	* We ASSUME not racing code here, both wrt thread state and ext commands.
3991	*/
3992	Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
3993	Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS \|\| uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
3994
3995	/* Post the request. */
3996	pThisCC->svga.pvFIFOExtCmdParam = pvParam;
3997	pThis->svga.u8FIFOExtCommand = uExtCmd;
3998	ASMMemoryFence(); /* paranoia^2 */
3999	rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4000	AssertLogRelRC(rc);
4001
4002	/* Wait. Take care in case the semaphore was already posted (same as above). */
4003	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
4004	if ( rc == VINF_SUCCESS
4005	&& pThis->svga.u8FIFOExtCommand == uExtCmd)
4006	rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
4007	AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd \|\| RT_FAILURE_NP(rc),
4008	("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
4009
4010	pThisCC->svga.pvFIFOExtCmdParam = NULL;
4011	}
4012	else
4013	{
4014	/*
4015	* Something is wrong with the thread!
4016	*/
4017	AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
4018	rc = VERR_INVALID_STATE;
4019	}
4020	return rc;
4021	}
4022
4023
4024	/**
4025	* Marks the FIFO non-busy, notifying any waiting EMTs.
4026	*
4027	* @param pDevIns The device instance.
4028	* @param pThis The shared VGA/VMSVGA instance data.
4029	* @param pThisCC The VGA/VMSVGA state for ring-3.
4030	* @param pSVGAState Pointer to the ring-3 only SVGA state data.
4031	* @param offFifoMin The start byte offset of the command FIFO.
4032	*/
4033	static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
4034	{
4035	ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO \| VMSVGA_BUSY_F_EMT_FORCE));
4036	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4037	vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
4038
4039	/* Wake up any waiting EMTs. */
4040	if (pSVGAState->cBusyDelayedEmts > 0)
4041	{
4042	# ifdef VMSVGA_USE_EMT_HALT_CODE
4043	PVM pVM = PDMDevHlpGetVM(pDevIns);
4044	VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
4045	if (idCpu != NIL_VMCPUID)
4046	{
4047	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4048	while (idCpu-- > 0)
4049	if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
4050	VMR3NotifyCpuDeviceReady(pVM, idCpu);
4051	}
4052	# else
4053	int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
4054	AssertRC(rc2);
4055	# endif
4056	}
4057	}
4058
4059	/**
4060	* Reads (more) payload into the command buffer.
4061	*
4062	* @returns pbBounceBuf on success
4063	* @retval (void *)1 if the thread was requested to stop.
4064	* @retval NULL on FIFO error.
4065	*
4066	* @param cbPayloadReq The number of bytes of payload requested.
4067	* @param pFIFO The FIFO.
4068	* @param offCurrentCmd The FIFO byte offset of the current command.
4069	* @param offFifoMin The start byte offset of the command FIFO.
4070	* @param offFifoMax The end byte offset of the command FIFO.
4071	* @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
4072	* always sufficient size.
4073	* @param pcbAlreadyRead How much payload we've already read into the bounce
4074	* buffer. (We will NEVER re-read anything.)
4075	* @param pThread The calling PDM thread handle.
4076	* @param pThis The shared VGA/VMSVGA instance data.
4077	* @param pSVGAState Pointer to the ring-3 only SVGA state data. For
4078	* statistics collection.
4079	* @param pDevIns The device instance.
4080	*/
4081	static void vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST pFIFO,
4082	uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
4083	uint8_t pbBounceBuf, uint32_t pcbAlreadyRead,
4084	PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
4085	{
4086	Assert(pbBounceBuf);
4087	Assert(pcbAlreadyRead);
4088	Assert(offFifoMin < offFifoMax);
4089	Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
4090	Assert(offFifoMax <= pThis->svga.cbFIFO);
4091
4092	/*
4093	* Check if the requested payload size has already been satisfied .
4094	* .
4095	* When called to read more, the caller is responsible for making sure the .
4096	* new command size (cbRequsted) never is smaller than what has already .
4097	* been read.
4098	*/
4099	uint32_t cbAlreadyRead = *pcbAlreadyRead;
4100	if (cbPayloadReq <= cbAlreadyRead)
4101	{
4102	AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
4103	return pbBounceBuf;
4104	}
4105
4106	/*
4107	* Commands bigger than the fifo buffer are invalid.
4108	*/
4109	uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
4110	AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
4111	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
4112	NULL);
4113
4114	/*
4115	* Move offCurrentCmd past the command dword.
4116	*/
4117	offCurrentCmd += sizeof(uint32_t);
4118	if (offCurrentCmd >= offFifoMax)
4119	offCurrentCmd = offFifoMin;
4120
4121	/*
4122	* Do we have sufficient payload data available already?
4123	* The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
4124	*/
4125	uint32_t cbAfter, cbBefore;
4126	uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4127	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4128	if (offNextCmd >= offCurrentCmd)
4129	{
4130	if (RT_LIKELY(offNextCmd < offFifoMax))
4131	cbAfter = offNextCmd - offCurrentCmd;
4132	else
4133	{
4134	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4135	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4136	offNextCmd, offFifoMin, offFifoMax));
4137	cbAfter = offFifoMax - offCurrentCmd;
4138	}
4139	cbBefore = 0;
4140	}
4141	else
4142	{
4143	cbAfter = offFifoMax - offCurrentCmd;
4144	if (offNextCmd >= offFifoMin)
4145	cbBefore = offNextCmd - offFifoMin;
4146	else
4147	{
4148	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4149	LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
4150	offNextCmd, offFifoMin, offFifoMax));
4151	cbBefore = 0;
4152	}
4153	}
4154	if (cbAfter + cbBefore < cbPayloadReq)
4155	{
4156	/*
4157	* Insufficient, must wait for it to arrive.
4158	*/
4159	/** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
4160	STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
4161	for (uint32_t i = 0;; i++)
4162	{
4163	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4164	{
4165	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4166	return (void *)(uintptr_t)1;
4167	}
4168	Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
4169	cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
4170
4171	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
4172
4173	offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
4174	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4175	if (offNextCmd >= offCurrentCmd)
4176	{
4177	cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
4178	cbBefore = 0;
4179	}
4180	else
4181	{
4182	cbAfter = offFifoMax - offCurrentCmd;
4183	cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
4184	}
4185
4186	if (cbAfter + cbBefore >= cbPayloadReq)
4187	break;
4188	}
4189	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
4190	}
4191
4192	/*
4193	* Copy out the memory and update what pcbAlreadyRead points to.
4194	*/
4195	if (cbAfter >= cbPayloadReq)
4196	memcpy(pbBounceBuf + cbAlreadyRead,
4197	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4198	cbPayloadReq - cbAlreadyRead);
4199	else
4200	{
4201	LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
4202	if (cbAlreadyRead < cbAfter)
4203	{
4204	memcpy(pbBounceBuf + cbAlreadyRead,
4205	(uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
4206	cbAfter - cbAlreadyRead);
4207	cbAlreadyRead = cbAfter;
4208	}
4209	memcpy(pbBounceBuf + cbAlreadyRead,
4210	(uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
4211	cbPayloadReq - cbAlreadyRead);
4212	}
4213	*pcbAlreadyRead = cbPayloadReq;
4214	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4215	return pbBounceBuf;
4216	}
4217
4218
4219	/**
4220	* Sends cursor position and visibility information from the FIFO to the front-end.
4221	* @returns SVGA_FIFO_CURSOR_COUNT value used.
4222	*/
4223	static uint32_t
4224	vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
4225	uint32_t offFifoMin, uint32_t uCursorUpdateCount,
4226	uint32_t pxLast, uint32_t pyLast, uint32_t *pfLastVisible)
4227	{
4228	/*
4229	* Check if the cursor update counter has changed and try get a stable
4230	* set of values if it has. This is race-prone, especially consindering
4231	* the screen ID, but little we can do about that.
4232	*/
4233	uint32_t x, y, fVisible, idScreen;
4234	for (uint32_t i = 0; ; i++)
4235	{
4236	x = pFIFO[SVGA_FIFO_CURSOR_X];
4237	y = pFIFO[SVGA_FIFO_CURSOR_Y];
4238	fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
4239	idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
4240	? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
4241	if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
4242	\|\| i > 3)
4243	break;
4244	if (i == 0)
4245	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
4246	ASMNopPause();
4247	uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4248	}
4249
4250	/*
4251	* Check if anything has changed, as calling into pDrv is not light-weight.
4252	*/
4253	if ( *pxLast == x
4254	&& *pyLast == y
4255	&& (idScreen != SVGA_ID_INVALID \|\| *pfLastVisible == fVisible))
4256	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
4257	else
4258	{
4259	/*
4260	* Detected changes.
4261	*
4262	* We handle global, not per-screen visibility information by sending
4263	* pfnVBVAMousePointerShape without shape data.
4264	*/
4265	*pxLast = x;
4266	*pyLast = y;
4267	uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
4268	if (idScreen != SVGA_ID_INVALID)
4269	fFlags \|= VBVA_CURSOR_SCREEN_RELATIVE;
4270	else if (*pfLastVisible != fVisible)
4271	{
4272	LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
4273	*pfLastVisible = fVisible;
4274	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
4275	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
4276	}
4277	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
4278	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
4279	}
4280
4281	/*
4282	* Update done. Signal this to the guest.
4283	*/
4284	pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
4285
4286	return uCursorUpdateCount;
4287	}
4288
4289
4290	/**
4291	* Checks if there is work to be done, either cursor updating or FIFO commands.
4292	*
4293	* @returns true if pending work, false if not.
4294	* @param pThisCC The VGA/VMSVGA state for ring-3.
4295	* @param uLastCursorCount The last cursor update counter value.
4296	*/
4297	DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
4298	{
4299	/* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
4300	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4301	AssertReturn(pFIFO, false);
4302
4303	if (vmsvgaR3CmdBufHasWork(pThisCC))
4304	return true;
4305
4306	if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
4307	return true;
4308
4309	if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
4310	&& VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
4311	return true;
4312
4313	return false;
4314	}
4315
4316
4317	/**
4318	* Called by the VGA refresh timer to wake up the FIFO thread when needed.
4319	*
4320	* @param pDevIns The device instance.
4321	* @param pThis The shared VGA/VMSVGA instance data.
4322	* @param pThisCC The VGA/VMSVGA state for ring-3.
4323	*/
4324	void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4325	{
4326	/* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
4327	to recheck it before doing the signalling. */
4328	if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
4329	&& pThis->svga.fFIFOThreadSleeping
4330	&& !ASMAtomicReadBool(&pThis->svga.fBadGuest))
4331	{
4332	int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4333	AssertRC(rc);
4334	STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
4335	}
4336	}
4337
4338
4339	/**
4340	* Called by the FIFO thread to process pending actions.
4341	*
4342	* @param pDevIns The device instance.
4343	* @param pThis The shared VGA/VMSVGA instance data.
4344	* @param pThisCC The VGA/VMSVGA state for ring-3.
4345	*/
4346	void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
4347	{
4348	RT_NOREF(pDevIns);
4349
4350	/* Currently just mode changes. */
4351	if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
4352	{
4353	vmsvgaR3ChangeMode(pThis, pThisCC);
4354	# ifdef VBOX_WITH_VMSVGA3D
4355	if (pThisCC->svga.p3dState != NULL)
4356	vmsvga3dChangeMode(pThisCC);
4357	# endif
4358	}
4359	}
4360
4361
4362	/*
4363	* These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
4364	* even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
4365	*/
4366	/** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
4367	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
4368	*
4369	* Will break out of the switch on failure.
4370	* Will restart and quit the loop if the thread was requested to stop.
4371	*
4372	* @param a_PtrVar Request variable pointer.
4373	* @param a_Type Request typedef (not pointer) for casting.
4374	* @param a_cbPayloadReq How much payload to fetch.
4375	* @remarks Accesses a bunch of variables in the current scope!
4376	*/
4377	# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4378	if (1) { \
4379	(a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
4380	pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
4381	if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
4382	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
4383	} else do {} while (0)
4384	/* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
4385	* Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
4386	* buffer after figuring out the actual command size.
4387	*
4388	* Will break out of the switch on failure.
4389	*
4390	* @param a_PtrVar Request variable pointer.
4391	* @param a_Type Request typedef (not pointer) for casting.
4392	* @param a_cbPayloadReq How much payload to fetch.
4393	* @remarks Accesses a bunch of variables in the current scope!
4394	*/
4395	# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
4396	if (1) { \
4397	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
4398	} else do {} while (0)
4399
4400	/**
4401	* @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
4402	*/
4403	static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4404	{
4405	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4406	PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4407	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
4408	int rc;
4409
4410	# if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
4411	if (pThis->svga.f3DEnabled)
4412	{
4413	/* The FIFO thread may use X API for accelerated screen output. */
4414	XInitThreads();
4415	}
4416	# endif
4417
4418	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4419	return VINF_SUCCESS;
4420
4421	/*
4422	* Special mode where we only execute an external command and the go back
4423	* to being suspended. Currently, all ext cmds ends up here, with the reset
4424	* one also being eligble for runtime execution further down as well.
4425	*/
4426	if (pThis->svga.fFifoExtCommandWakeup)
4427	{
4428	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4429	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4430	if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
4431	PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
4432	else
4433	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4434	return VINF_SUCCESS;
4435	}
4436
4437
4438	/*
4439	* Signal the semaphore to make sure we don't wait for 250ms after a
4440	* suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
4441	*/
4442	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4443
4444	/*
4445	* Allocate a bounce buffer for command we get from the FIFO.
4446	* (All code must return via the end of the function to free this buffer.)
4447	*/
4448	uint8_t pbBounceBuf = (uint8_t )RTMemAllocZ(pThis->svga.cbFIFO);
4449	AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
4450
4451	/*
4452	* Polling/sleep interval config.
4453	*
4454	* We wait for an a short interval if the guest has recently given us work
4455	* to do, but the interval increases the longer we're kept idle. Once we've
4456	* reached the refresh timer interval, we'll switch to extended waits,
4457	* depending on it or the guest to kick us into action when needed.
4458	*
4459	* Should the refresh time go fishing, we'll just continue increasing the
4460	* sleep length till we reaches the 250 ms max after about 16 seconds.
4461	*/
4462	RTMSINTERVAL const cMsMinSleep = 16;
4463	RTMSINTERVAL const cMsIncSleep = 2;
4464	RTMSINTERVAL const cMsMaxSleep = 250;
4465	RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
4466	RTMSINTERVAL cMsSleep = cMsMaxSleep;
4467
4468	/*
4469	* Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
4470	*
4471	* Initialize with values that will detect an update from the guest.
4472	* Make sure that if the guest never updates the cursor position, then the device does not report it.
4473	* The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
4474	* xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
4475	*/
4476	uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
4477	pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4478	uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
4479	uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
4480	uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
4481
4482	/*
4483	* The FIFO loop.
4484	*/
4485	LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
4486	bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4487	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4488	{
4489	# if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
4490	/*
4491	* Should service the run loop every so often.
4492	*/
4493	if (pThis->svga.f3DEnabled)
4494	vmsvga3dCocoaServiceRunLoop();
4495	# endif
4496
4497	/* First check any pending actions. */
4498	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4499
4500	/*
4501	* Unless there's already work pending, go to sleep for a short while.
4502	* (See polling/sleep interval config above.)
4503	*/
4504	if ( fBadOrDisabledFifo
4505	\|\| !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4506	{
4507	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
4508	Assert(pThis->cMilliesRefreshInterval > 0);
4509	if (cMsSleep < pThis->cMilliesRefreshInterval)
4510	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
4511	else
4512	{
4513	# ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
4514	int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
4515	AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
4516	# endif
4517	if ( !fBadOrDisabledFifo
4518	&& vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4519	rc = VINF_SUCCESS;
4520	else
4521	{
4522	STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
4523	rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
4524	STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
4525	}
4526	}
4527	ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
4528	AssertBreak(RT_SUCCESS(rc) \|\| rc == VERR_TIMEOUT \|\| rc == VERR_INTERRUPTED);
4529	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
4530	{
4531	LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
4532	break;
4533	}
4534	}
4535	else
4536	rc = VINF_SUCCESS;
4537	fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
4538	if (rc == VERR_TIMEOUT)
4539	{
4540	if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4541	{
4542	cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
4543	continue;
4544	}
4545	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
4546
4547	Log(("vmsvgaR3FifoLoop: timeout\n"));
4548	}
4549	else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
4550	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
4551	cMsSleep = cMsMinSleep;
4552
4553	Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
4554	Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
4555	Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
4556
4557	/*
4558	* Handle external commands (currently only reset).
4559	*/
4560	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4561	{
4562	vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
4563	continue;
4564	}
4565
4566	/*
4567	* If guest misbehaves, then do nothing.
4568	*/
4569	if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
4570	{
4571	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4572	cMsSleep = cMsExtendedSleep;
4573	LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
4574	continue;
4575	}
4576
4577	/*
4578	* The device must be enabled and configured.
4579	*/
4580	if ( !pThis->svga.fEnabled
4581	\|\| !pThis->svga.fConfigured)
4582	{
4583	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
4584	fBadOrDisabledFifo = true;
4585	cMsSleep = cMsMaxSleep; /* cheat */
4586	continue;
4587	}
4588
4589	/*
4590	* Get and check the min/max values. We ASSUME that they will remain
4591	* unchanged while we process requests. A further ASSUMPTION is that
4592	* the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
4593	* we don't read it back while in the loop.
4594	*/
4595	uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
4596	uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
4597	uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
4598	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4599	if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
4600	\|\| offFifoMax <= offFifoMin
4601	\|\| offFifoMax > pThis->svga.cbFIFO
4602	\|\| (offFifoMax & 3) != 0
4603	\|\| (offFifoMin & 3) != 0
4604	\|\| offCurrentCmd < offFifoMin
4605	\|\| offCurrentCmd > offFifoMax))
4606	{
4607	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4608	LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
4609	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
4610	fBadOrDisabledFifo = true;
4611	continue;
4612	}
4613	RT_UNTRUSTED_VALIDATED_FENCE();
4614	if (RT_UNLIKELY(offCurrentCmd & 3))
4615	{
4616	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
4617	LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
4618	offCurrentCmd &= ~UINT32_C(3);
4619	}
4620
4621	/*
4622	* Update the cursor position before we start on the FIFO commands.
4623	*/
4624	/** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
4625	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
4626	{
4627	uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
4628	if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
4629	{ /* halfways likely */ }
4630	else
4631	{
4632	uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
4633	&xLastCursor, &yLastCursor, &fLastCursorVisible);
4634	ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
4635	}
4636	}
4637
4638	/*
4639	* Mark the FIFO as busy.
4640	*/
4641	ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
4642	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
4643	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
4644
4645	/*
4646	* Process all submitted command buffers.
4647	*/
4648	vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
4649
4650	/*
4651	* Execute all queued FIFO commands.
4652	* Quit if pending external command or changes in the thread state.
4653	*/
4654	bool fDone = false;
4655	while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
4656	&& pThread->enmState == PDMTHREADSTATE_RUNNING)
4657	{
4658	uint32_t cbPayload = 0;
4659	uint32_t u32IrqStatus = 0;
4660
4661	Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
4662
4663	/* First check any pending actions. */
4664	vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
4665
4666	/* Check for pending external commands (reset). */
4667	if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
4668	break;
4669
4670	/*
4671	* Process the command.
4672	*/
4673	/* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
4674	* warning. Because we implement some obsolete and deprecated commands, which are not included in
4675	* the SVGAFifoCmdId enum in the VMSVGA headers anymore.
4676	*/
4677	uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
4678	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4679	LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
4680	offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
4681	switch (enmCmdId)
4682	{
4683	case SVGA_CMD_INVALID_CMD:
4684	/* Nothing to do. */
4685	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
4686	break;
4687
4688	case SVGA_CMD_FENCE:
4689	{
4690	SVGAFifoCmdFence *pCmdFence;
4691	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
4692	STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
4693	if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
4694	{
4695	Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
4696	pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
4697
4698	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
4699	{
4700	Log(("vmsvgaR3FifoLoop: any fence irq\n"));
4701	u32IrqStatus \|= SVGA_IRQFLAG_ANY_FENCE;
4702	}
4703	else
4704	if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
4705	&& (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
4706	&& pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
4707	{
4708	Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
4709	u32IrqStatus \|= SVGA_IRQFLAG_FENCE_GOAL;
4710	}
4711	}
4712	else
4713	Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
4714	break;
4715	}
4716
4717	case SVGA_CMD_UPDATE:
4718	{
4719	SVGAFifoCmdUpdate *pCmd;
4720	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
4721	vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
4722	break;
4723	}
4724
4725	case SVGA_CMD_UPDATE_VERBOSE:
4726	{
4727	SVGAFifoCmdUpdateVerbose *pCmd;
4728	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
4729	vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
4730	break;
4731	}
4732
4733	case SVGA_CMD_DEFINE_CURSOR:
4734	{
4735	/* Followed by bitmap data. */
4736	SVGAFifoCmdDefineCursor *pCmd;
4737	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
4738
4739	/* Figure out the size of the bitmap data. */
4740	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4741	ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
4742	ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
4743	RT_UNTRUSTED_VALIDATED_FENCE();
4744
4745	uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
4746	uint32_t const cbAndMask = cbAndLine * pCmd->height;
4747	uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
4748	uint32_t const cbXorMask = cbXorLine * pCmd->height;
4749
4750	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
4751	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
4752	vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
4753	break;
4754	}
4755
4756	case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4757	{
4758	/* Followed by bitmap data. */
4759	SVGAFifoCmdDefineAlphaCursor *pCmd;
4760	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
4761
4762	/* Figure out the size of the bitmap data. */
4763	ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
4764
4765	uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
4766	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
4767	vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
4768	break;
4769	}
4770
4771	case SVGA_CMD_MOVE_CURSOR:
4772	{
4773	/* Deprecated; there should be no driver which requires this command. However, if
4774	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4775	* alignment.
4776	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4777	*/
4778	SVGAFifoCmdMoveCursor *pCmd;
4779	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
4780	vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
4781	break;
4782	}
4783
4784	case SVGA_CMD_DISPLAY_CURSOR:
4785	{
4786	/* Deprecated; there should be no driver which requires this command. However, if
4787	* we do ecncounter this command, it might be useful to not get the FIFO completely out of
4788	* alignment.
4789	* May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
4790	*/
4791	SVGAFifoCmdDisplayCursor *pCmd;
4792	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
4793	vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
4794	break;
4795	}
4796
4797	case SVGA_CMD_RECT_FILL:
4798	{
4799	SVGAFifoCmdRectFill *pCmd;
4800	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
4801	vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
4802	break;
4803	}
4804
4805	case SVGA_CMD_RECT_COPY:
4806	{
4807	SVGAFifoCmdRectCopy *pCmd;
4808	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
4809	vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
4810	break;
4811	}
4812
4813	case SVGA_CMD_RECT_ROP_COPY:
4814	{
4815	SVGAFifoCmdRectRopCopy *pCmd;
4816	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
4817	vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
4818	break;
4819	}
4820
4821	case SVGA_CMD_ESCAPE:
4822	{
4823	/* Followed by 'size' bytes of data. */
4824	SVGAFifoCmdEscape *pCmd;
4825	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
4826
4827	ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
4828	RT_UNTRUSTED_VALIDATED_FENCE();
4829
4830	uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
4831	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
4832	vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
4833	break;
4834	}
4835	# ifdef VBOX_WITH_VMSVGA3D
4836	case SVGA_CMD_DEFINE_GMR2:
4837	{
4838	SVGAFifoCmdDefineGMR2 *pCmd;
4839	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
4840	vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
4841	break;
4842	}
4843
4844	case SVGA_CMD_REMAP_GMR2:
4845	{
4846	/* Followed by page descriptors or guest ptr. */
4847	SVGAFifoCmdRemapGMR2 *pCmd;
4848	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
4849
4850	/* Calculate the size of what comes after next and fetch it. */
4851	uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
4852	if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
4853	cbCmd += sizeof(SVGAGuestPtr);
4854	else
4855	{
4856	uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
4857	if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
4858	{
4859	cbCmd += cbPageDesc;
4860	pCmd->numPages = 1;
4861	}
4862	else
4863	{
4864	ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
4865	cbCmd += cbPageDesc * pCmd->numPages;
4866	}
4867	}
4868	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
4869	vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
4870	# ifdef DEBUG_GMR_ACCESS
4871	VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
4872	# endif
4873	break;
4874	}
4875	# endif // VBOX_WITH_VMSVGA3D
4876	case SVGA_CMD_DEFINE_SCREEN:
4877	{
4878	/* The size of this command is specified by the guest and depends on capabilities. */
4879	Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
4880
4881	SVGAFifoCmdDefineScreen *pCmd;
4882	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
4883	AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
4884	RT_UNTRUSTED_VALIDATED_FENCE();
4885
4886	RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
4887	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
4888	vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
4889	break;
4890	}
4891
4892	case SVGA_CMD_DESTROY_SCREEN:
4893	{
4894	SVGAFifoCmdDestroyScreen *pCmd;
4895	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
4896	vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
4897	break;
4898	}
4899
4900	case SVGA_CMD_DEFINE_GMRFB:
4901	{
4902	SVGAFifoCmdDefineGMRFB *pCmd;
4903	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
4904	vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
4905	break;
4906	}
4907
4908	case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
4909	{
4910	SVGAFifoCmdBlitGMRFBToScreen *pCmd;
4911	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
4912	vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
4913	break;
4914	}
4915
4916	case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
4917	{
4918	SVGAFifoCmdBlitScreenToGMRFB *pCmd;
4919	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
4920	vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
4921	break;
4922	}
4923
4924	case SVGA_CMD_ANNOTATION_FILL:
4925	{
4926	SVGAFifoCmdAnnotationFill *pCmd;
4927	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
4928	vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
4929	break;
4930	}
4931
4932	case SVGA_CMD_ANNOTATION_COPY:
4933	{
4934	SVGAFifoCmdAnnotationCopy *pCmd;
4935	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
4936	vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
4937	break;
4938	}
4939
4940	default:
4941	# ifdef VBOX_WITH_VMSVGA3D
4942	if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
4943	&& (int)enmCmdId < SVGA_3D_CMD_MAX)
4944	{
4945	RT_UNTRUSTED_VALIDATED_FENCE();
4946
4947	/* All 3d commands start with a common header, which defines the identifier and the size
4948	* of the command. The identifier has been already read from FIFO. Fetch the size.
4949	*/
4950	uint32_t *pcbCmd;
4951	VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
4952	uint32_t const cbCmd = *pcbCmd;
4953	AssertBreak(cbCmd < pThis->svga.cbFIFO);
4954	uint32_t *pu32Cmd;
4955	VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
4956	pu32Cmd++; /* Skip the command size. */
4957
4958	if (RT_LIKELY(pThis->svga.f3DEnabled))
4959	{ /* likely */ }
4960	else
4961	{
4962	LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
4963	break;
4964	}
4965
4966	vmsvgaR3Process3dCmd(pThis, pThisCC, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
4967	}
4968	else
4969	# endif // VBOX_WITH_VMSVGA3D
4970	{
4971	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
4972	AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
4973	LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
4974	}
4975	}
4976
4977	/* Go to the next slot */
4978	Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
4979	offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
4980	if (offCurrentCmd >= offFifoMax)
4981	{
4982	offCurrentCmd -= offFifoMax - offFifoMin;
4983	Assert(offCurrentCmd >= offFifoMin);
4984	Assert(offCurrentCmd < offFifoMax);
4985	}
4986	ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
4987	STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
4988
4989	/*
4990	* Raise IRQ if required. Must enter the critical section here
4991	* before making final decisions here, otherwise cubebench and
4992	* others may end up waiting forever.
4993	*/
4994	if ( u32IrqStatus
4995	\|\| (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
4996	{
4997	int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4998	AssertRC(rc2);
4999
5000	/* FIFO progress might trigger an interrupt. */
5001	if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
5002	{
5003	Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
5004	u32IrqStatus \|= SVGA_IRQFLAG_FIFO_PROGRESS;
5005	}
5006
5007	/* Unmasked IRQ pending? */
5008	if (pThis->svga.u32IrqMask & u32IrqStatus)
5009	{
5010	Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
5011	ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
5012	PDMDevHlpPCISetIrq(pDevIns, 0, 1);
5013	}
5014
5015	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5016	}
5017	}
5018
5019	/* If really done, clear the busy flag. */
5020	if (fDone)
5021	{
5022	Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
5023	vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
5024	}
5025	}
5026
5027	/*
5028	* Free the bounce buffer. (There are no returns above!)
5029	*/
5030	RTMemFree(pbBounceBuf);
5031
5032	return VINF_SUCCESS;
5033	}
5034
5035	#undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
5036	#undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
5037
5038	/**
5039	* @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
5040	* Unblock the FIFO I/O thread so it can respond to a state change.}
5041	*/
5042	static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5043	{
5044	RT_NOREF(pDevIns);
5045	PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
5046	Log(("vmsvgaR3FifoLoopWakeUp\n"));
5047	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
5048	}
5049
5050	/**
5051	* Enables or disables dirty page tracking for the framebuffer
5052	*
5053	* @param pDevIns The device instance.
5054	* @param pThis The shared VGA/VMSVGA instance data.
5055	* @param fTraces Enable/disable traces
5056	*/
5057	static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
5058	{
5059	if ( (!pThis->svga.fConfigured \|\| !pThis->svga.fEnabled)
5060	&& !fTraces)
5061	{
5062	//Assert(pThis->svga.fTraces);
5063	Log(("vmsvgaR3SetTraces: not allowed to disable dirty page tracking when the device is in legacy mode.\n"));
5064	return;
5065	}
5066
5067	pThis->svga.fTraces = fTraces;
5068	if (pThis->svga.fTraces)
5069	{
5070	unsigned cbFrameBuffer = pThis->vram_size;
5071
5072	Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
5073	/** @todo How does this work with screens? */
5074	if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
5075	{
5076	# ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
5077	Assert(pThis->svga.cbScanline);
5078	# endif
5079	/* Hardware enabled; return real framebuffer size .*/
5080	cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
5081	cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
5082	}
5083
5084	if (!pThis->svga.fVRAMTracking)
5085	{
5086	Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
5087	vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
5088	pThis->svga.fVRAMTracking = true;
5089	}
5090	}
5091	else
5092	{
5093	if (pThis->svga.fVRAMTracking)
5094	{
5095	Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
5096	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5097	pThis->svga.fVRAMTracking = false;
5098	}
5099	}
5100	}
5101
5102	/**
5103	* @callback_method_impl{FNPCIIOREGIONMAP}
5104	*/
5105	DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5106	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5107	{
5108	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5109	int rc;
5110	RT_NOREF(pPciDev);
5111	Assert(pPciDev == pDevIns->apPciDevs[0]);
5112
5113	Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5114	AssertReturn( iRegion == pThis->pciRegions.iFIFO
5115	&& ( enmType == PCI_ADDRESS_SPACE_MEM
5116	\|\| (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
5117	, VERR_INTERNAL_ERROR);
5118	if (GCPhysAddress != NIL_RTGCPHYS)
5119	{
5120	/*
5121	* Mapping the FIFO RAM.
5122	*/
5123	AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
5124	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
5125	AssertRC(rc);
5126
5127	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5128	if (RT_SUCCESS(rc))
5129	{
5130	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
5131	# ifdef DEBUG_FIFO_ACCESS
5132	GCPhysAddress + (pThis->svga.cbFIFO - 1),
5133	# else
5134	GCPhysAddress + PAGE_SIZE - 1,
5135	# endif
5136	pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
5137	"VMSVGA FIFO");
5138	AssertRC(rc);
5139	}
5140	# endif
5141	if (RT_SUCCESS(rc))
5142	{
5143	pThis->svga.GCPhysFIFO = GCPhysAddress;
5144	Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
5145	}
5146	rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
5147	}
5148	else
5149	{
5150	Assert(pThis->svga.GCPhysFIFO);
5151	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
5152	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
5153	AssertRC(rc);
5154	# else
5155	rc = VINF_SUCCESS;
5156	# endif
5157	pThis->svga.GCPhysFIFO = 0;
5158	}
5159	return rc;
5160	}
5161
5162	# ifdef VBOX_WITH_VMSVGA3D
5163
5164	/**
5165	* Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
5166	* surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
5167	*
5168	* @param pDevIns The device instance.
5169	* @param pThis The The shared VGA/VMSVGA instance data.
5170	* @param pThisCC The VGA/VMSVGA state for ring-3.
5171	* @param sid Either UINT32_MAX or the ID of a specific surface. If
5172	* UINT32_MAX is used, all surfaces are processed.
5173	*/
5174	void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
5175	{
5176	vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
5177	sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
5178	}
5179
5180
5181	/**
5182	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
5183	*/
5184	DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5185	{
5186	/* There might be a specific surface ID at the start of the
5187	arguments, if not show all surfaces. */
5188	uint32_t sid = UINT32_MAX;
5189	if (pszArgs)
5190	pszArgs = RTStrStripL(pszArgs);
5191	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5192	sid = RTStrToUInt32(pszArgs);
5193
5194	/* Verbose or terse display, we default to verbose. */
5195	bool fVerbose = true;
5196	if (RTStrIStr(pszArgs, "terse"))
5197	fVerbose = false;
5198
5199	/* The size of the ascii art (x direction, y is 3/4 of x). */
5200	uint32_t cxAscii = 80;
5201	if (RTStrIStr(pszArgs, "gigantic"))
5202	cxAscii = 300;
5203	else if (RTStrIStr(pszArgs, "huge"))
5204	cxAscii = 180;
5205	else if (RTStrIStr(pszArgs, "big"))
5206	cxAscii = 132;
5207	else if (RTStrIStr(pszArgs, "normal"))
5208	cxAscii = 80;
5209	else if (RTStrIStr(pszArgs, "medium"))
5210	cxAscii = 64;
5211	else if (RTStrIStr(pszArgs, "small"))
5212	cxAscii = 48;
5213	else if (RTStrIStr(pszArgs, "tiny"))
5214	cxAscii = 24;
5215
5216	/* Y invert the image when producing the ASCII art. */
5217	bool fInvY = false;
5218	if (RTStrIStr(pszArgs, "invy"))
5219	fInvY = true;
5220
5221	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5222	pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
5223	}
5224
5225
5226	/**
5227	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
5228	*/
5229	DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5230	{
5231	/* pszArg = "sid[>dir]"
5232	* Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
5233	*/
5234	char *pszBitmapPath = NULL;
5235	uint32_t sid = UINT32_MAX;
5236	if (pszArgs)
5237	pszArgs = RTStrStripL(pszArgs);
5238	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5239	RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
5240	if ( pszBitmapPath
5241	&& *pszBitmapPath == '>')
5242	++pszBitmapPath;
5243
5244	const bool fVerbose = true;
5245	const uint32_t cxAscii = 0; /* No ASCII */
5246	const bool fInvY = false; /* Do not invert. */
5247	vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
5248	pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
5249	}
5250
5251	/**
5252	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
5253	*/
5254	DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5255	{
5256	/* There might be a specific surface ID at the start of the
5257	arguments, if not show all contexts. */
5258	uint32_t sid = UINT32_MAX;
5259	if (pszArgs)
5260	pszArgs = RTStrStripL(pszArgs);
5261	if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
5262	sid = RTStrToUInt32(pszArgs);
5263
5264	/* Verbose or terse display, we default to verbose. */
5265	bool fVerbose = true;
5266	if (RTStrIStr(pszArgs, "terse"))
5267	fVerbose = false;
5268
5269	vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
5270	}
5271	# endif /* VBOX_WITH_VMSVGA3D */
5272
5273	/**
5274	* @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
5275	*/
5276	static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5277	{
5278	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5279	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5280	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5281	uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
5282	RT_NOREF(pszArgs);
5283
5284	pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
5285	pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
5286	pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
5287	pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
5288	? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
5289	pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
5290	pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
5291	pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
5292	pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
5293	pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
5294	pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
5295	pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
5296	pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
5297	pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
5298	pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
5299	pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
5300	pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
5301	pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
5302	pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
5303	pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
5304	pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
5305	pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
5306	pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
5307	pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
5308	pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
5309
5310	pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
5311	pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
5312	pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
5313	pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
5314
5315	pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
5316	pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
5317
5318	pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
5319	pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
5320
5321	# ifdef VBOX_WITH_VMSVGA3D
5322	pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
5323	# endif
5324	if (pThisCC->pDrv)
5325	{
5326	pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
5327	pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
5328	}
5329
5330	/* Dump screen information. */
5331	for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
5332	{
5333	VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
5334	if (pScreen)
5335	{
5336	pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
5337	pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
5338	pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
5339	pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
5340	pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
5341	if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
5342	{
5343	pHlp->pfnPrintf(pHlp, " (");
5344	if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
5345	pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
5346	if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
5347	pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
5348	if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
5349	pHlp->pfnPrintf(pHlp, " DEACTIVATE");
5350	if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
5351	pHlp->pfnPrintf(pHlp, " BLANKING");
5352	pHlp->pfnPrintf(pHlp, " )");
5353	}
5354	pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
5355	}
5356	}
5357
5358	}
5359
5360	/**
5361	* Portion of VMSVGA state which must be loaded oin the FIFO thread.
5362	*/
5363	static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
5364	PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5365	{
5366	RT_NOREF(uPass);
5367
5368	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5369	int rc;
5370
5371	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
5372	{
5373	uint32_t cScreens = 0;
5374	rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
5375	AssertRCReturn(rc, rc);
5376	AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
5377	("cScreens=%#x\n", cScreens),
5378	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5379
5380	for (uint32_t i = 0; i < cScreens; ++i)
5381	{
5382	VMSVGASCREENOBJECT screen;
5383	RT_ZERO(screen);
5384
5385	rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5386	AssertLogRelRCReturn(rc, rc);
5387
5388	if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
5389	{
5390	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
5391	*pScreen = screen;
5392	pScreen->fModified = true;
5393	}
5394	else
5395	{
5396	LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
5397	}
5398	}
5399	}
5400	else
5401	{
5402	/* Try to setup at least the first screen. */
5403	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
5404	pScreen->fDefined = true;
5405	pScreen->fModified = true;
5406	pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET \| SVGA_SCREEN_IS_PRIMARY;
5407	pScreen->idScreen = 0;
5408	pScreen->xOrigin = 0;
5409	pScreen->yOrigin = 0;
5410	pScreen->offVRAM = pThis->svga.uScreenOffset;
5411	pScreen->cbPitch = pThis->svga.cbScanline;
5412	pScreen->cWidth = pThis->svga.uWidth;
5413	pScreen->cHeight = pThis->svga.uHeight;
5414	pScreen->cBpp = pThis->svga.uBpp;
5415	}
5416
5417	return VINF_SUCCESS;
5418	}
5419
5420	/**
5421	* @copydoc FNSSMDEVLOADEXEC
5422	*/
5423	int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5424	{
5425	RT_NOREF(uPass);
5426	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5427	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5428	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5429	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5430	int rc;
5431
5432	/* Load our part of the VGAState */
5433	rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5434	AssertRCReturn(rc, rc);
5435
5436	/* Load the VGA framebuffer. */
5437	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
5438	uint32_t cbVgaFramebuffer = _32K;
5439	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
5440	{
5441	rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
5442	AssertRCReturn(rc, rc);
5443	AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
5444	("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
5445	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5446	AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
5447	AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
5448	}
5449	rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
5450	AssertRCReturn(rc, rc);
5451	if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
5452	pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
5453	else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
5454	RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
5455
5456	/* Load the VMSVGA state. */
5457	rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5458	AssertRCReturn(rc, rc);
5459
5460	/* Load the active cursor bitmaps. */
5461	if (pSVGAState->Cursor.fActive)
5462	{
5463	pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
5464	AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
5465
5466	rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5467	AssertRCReturn(rc, rc);
5468	}
5469
5470	/* Load the GMR state. */
5471	uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
5472	if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
5473	{
5474	rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
5475	AssertRCReturn(rc, rc);
5476	/* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
5477	AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
5478	("cGMR=%#x - expected 256B..1MB\n", cGMR),
5479	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
5480	}
5481
5482	if (pThis->svga.cGMR != cGMR)
5483	{
5484	/* Reallocate GMR array. */
5485	Assert(pSVGAState->paGMR != NULL);
5486	RTMemFree(pSVGAState->paGMR);
5487	pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
5488	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5489	pThis->svga.cGMR = cGMR;
5490	}
5491
5492	for (uint32_t i = 0; i < cGMR; ++i)
5493	{
5494	PGMR pGMR = &pSVGAState->paGMR[i];
5495
5496	rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5497	AssertRCReturn(rc, rc);
5498
5499	if (pGMR->numDescriptors)
5500	{
5501	Assert(pGMR->cMaxPages \|\| pGMR->cbTotal);
5502	pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
5503	AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
5504
5505	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5506	{
5507	rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5508	AssertRCReturn(rc, rc);
5509	}
5510	}
5511	}
5512
5513	# ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
5514	vmsvga3dPowerOn(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC));
5515	# endif
5516
5517	VMSVGA_STATE_LOAD LoadState;
5518	LoadState.pSSM = pSSM;
5519	LoadState.uVersion = uVersion;
5520	LoadState.uPass = uPass;
5521	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
5522	AssertLogRelRCReturn(rc, rc);
5523
5524	return VINF_SUCCESS;
5525	}
5526
5527	/**
5528	* Reinit the video mode after the state has been loaded.
5529	*/
5530	int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
5531	{
5532	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5533	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5534	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5535
5536	/* Set the active cursor. */
5537	if (pSVGAState->Cursor.fActive)
5538	{
5539	/* We don't store the alpha flag, but we can take a guess that if
5540	* the old register interface was used, the cursor was B&W.
5541	*/
5542	bool fAlpha = pThis->svga.uCursorOn ? false : true;
5543
5544	int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
5545	true /fVisible/,
5546	fAlpha,
5547	pSVGAState->Cursor.xHotspot,
5548	pSVGAState->Cursor.yHotspot,
5549	pSVGAState->Cursor.width,
5550	pSVGAState->Cursor.height,
5551	pSVGAState->Cursor.pData);
5552	AssertRC(rc);
5553
5554	if (pThis->svga.uCursorOn)
5555	pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
5556	}
5557
5558	/* If the VRAM handler should not be registered, we have to explicitly
5559	* unregister it here!
5560	*/
5561	if (!pThis->svga.fVRAMTracking)
5562	{
5563	vgaR3UnregisterVRAMHandler(pDevIns, pThis);
5564	}
5565
5566	/* Let the FIFO thread deal with changing the mode. */
5567	ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
5568
5569	return VINF_SUCCESS;
5570	}
5571
5572	/**
5573	* Portion of SVGA state which must be saved in the FIFO thread.
5574	*/
5575	static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
5576	{
5577	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5578	int rc;
5579
5580	/* Save the screen objects. */
5581	/* Count defined screen object. */
5582	uint32_t cScreens = 0;
5583	for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
5584	{
5585	if (pSVGAState->aScreens[i].fDefined)
5586	++cScreens;
5587	}
5588
5589	rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
5590	AssertLogRelRCReturn(rc, rc);
5591
5592	for (uint32_t i = 0; i < cScreens; ++i)
5593	{
5594	VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
5595
5596	rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
5597	AssertLogRelRCReturn(rc, rc);
5598	}
5599	return VINF_SUCCESS;
5600	}
5601
5602	/**
5603	* @copydoc FNSSMDEVSAVEEXEC
5604	*/
5605	int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5606	{
5607	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5608	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5609	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5610	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5611	int rc;
5612
5613	/* Save our part of the VGAState */
5614	rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
5615	AssertLogRelRCReturn(rc, rc);
5616
5617	/* Save the framebuffer backup. */
5618	rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
5619	rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5620	AssertLogRelRCReturn(rc, rc);
5621
5622	/* Save the VMSVGA state. */
5623	rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
5624	AssertLogRelRCReturn(rc, rc);
5625
5626	/* Save the active cursor bitmaps. */
5627	if (pSVGAState->Cursor.fActive)
5628	{
5629	rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5630	AssertLogRelRCReturn(rc, rc);
5631	}
5632
5633	/* Save the GMR state */
5634	rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
5635	AssertLogRelRCReturn(rc, rc);
5636	for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
5637	{
5638	PGMR pGMR = &pSVGAState->paGMR[i];
5639
5640	rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
5641	AssertLogRelRCReturn(rc, rc);
5642
5643	for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
5644	{
5645	rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
5646	AssertLogRelRCReturn(rc, rc);
5647	}
5648	}
5649
5650	/*
5651	* Must save some state (3D in particular) in the FIFO thread.
5652	*/
5653	rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
5654	AssertLogRelRCReturn(rc, rc);
5655
5656	return VINF_SUCCESS;
5657	}
5658
5659	/**
5660	* Destructor for PVMSVGAR3STATE structure.
5661	*
5662	* @param pThis The shared VGA/VMSVGA instance data.
5663	* @param pSVGAState Pointer to the structure. It is not deallocated.
5664	*/
5665	static void vmsvgaR3StateTerm(PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5666	{
5667	# ifndef VMSVGA_USE_EMT_HALT_CODE
5668	if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
5669	{
5670	RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
5671	pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
5672	}
5673	# endif
5674
5675	if (pSVGAState->Cursor.fActive)
5676	{
5677	RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
5678	pSVGAState->Cursor.pData = NULL;
5679	pSVGAState->Cursor.fActive = false;
5680	}
5681
5682	if (pSVGAState->paGMR)
5683	{
5684	for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
5685	if (pSVGAState->paGMR[i].paDesc)
5686	RTMemFree(pSVGAState->paGMR[i].paDesc);
5687
5688	RTMemFree(pSVGAState->paGMR);
5689	pSVGAState->paGMR = NULL;
5690	}
5691
5692	if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
5693	{
5694	RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
5695	for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
5696	{
5697	vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
5698	pSVGAState->apCmdBufCtxs[i] = NULL;
5699	}
5700	vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
5701	RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
5702	RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
5703	}
5704
5705	# ifdef VBOX_WITH_VMSVGA3D
5706	RTMemFree(pSVGAState->pFuncsMap);
5707	pSVGAState->pFuncsMap = NULL;
5708	RTMemFree(pSVGAState->pFuncsGBO);
5709	pSVGAState->pFuncsGBO = NULL;
5710	RTMemFree(pSVGAState->pFuncsDX);
5711	pSVGAState->pFuncsDX = NULL;
5712	# endif
5713	}
5714
5715	/**
5716	* Constructor for PVMSVGAR3STATE structure.
5717	*
5718	* @returns VBox status code.
5719	* @param pDevIns The PDM device instance.
5720	* @param pThis The shared VGA/VMSVGA instance data.
5721	* @param pSVGAState Pointer to the structure. It is already allocated.
5722	*/
5723	static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
5724	{
5725	int rc = VINF_SUCCESS;
5726
5727	pSVGAState->pDevIns = pDevIns;
5728
5729	pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
5730	AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
5731
5732	# ifndef VMSVGA_USE_EMT_HALT_CODE
5733	/* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
5734	rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
5735	AssertRCReturn(rc, rc);
5736	# endif
5737
5738	rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
5739	AssertRCReturn(rc, rc);
5740
5741	vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
5742
5743	RTListInit(&pSVGAState->MOBLRUList);
5744	return rc;
5745	}
5746
5747	# ifdef VBOX_WITH_VMSVGA3D
5748	/**
5749	* Initializes the optional host 3D backend interfaces.
5750	*
5751	* @returns VBox status code.
5752	* @param pThisCC The VGA/VMSVGA state for ring-3.
5753	*/
5754	static int vmsvgaR3Init3dInterfaces(PVGASTATECC pThisCC)
5755	{
5756	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5757
5758	int rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, NULL, sizeof(VMSVGA3DBACKENDFUNCSDX));
5759	if (RT_SUCCESS(rc))
5760	{
5761	pSVGAState->pFuncsDX = (VMSVGA3DBACKENDFUNCSDX *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSDX));
5762	AssertReturn(pSVGAState->pFuncsDX, VERR_NO_MEMORY);
5763
5764	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_DX, pSVGAState->pFuncsDX, sizeof(VMSVGA3DBACKENDFUNCSDX));
5765	}
5766
5767	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, NULL, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5768	if (RT_SUCCESS(rc))
5769	{
5770	pSVGAState->pFuncsMap = (VMSVGA3DBACKENDFUNCSMAP *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSMAP));
5771	AssertReturn(pSVGAState->pFuncsMap, VERR_NO_MEMORY);
5772
5773	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_MAP, pSVGAState->pFuncsMap, sizeof(VMSVGA3DBACKENDFUNCSMAP));
5774	}
5775
5776	rc = vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, NULL, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5777	if (RT_SUCCESS(rc))
5778	{
5779	pSVGAState->pFuncsGBO = (VMSVGA3DBACKENDFUNCSGBO *)RTMemAllocZ(sizeof(VMSVGA3DBACKENDFUNCSGBO));
5780	AssertReturn(pSVGAState->pFuncsGBO, VERR_NO_MEMORY);
5781
5782	vmsvga3dQueryInterface(pThisCC, VMSVGA3D_BACKEND_INTERFACE_NAME_GBO, pSVGAState->pFuncsGBO, sizeof(VMSVGA3DBACKENDFUNCSGBO));
5783	}
5784
5785	return VINF_SUCCESS;
5786	}
5787	# endif
5788
5789	/**
5790	* Initializes the host capabilities: device and FIFO.
5791	*
5792	* @returns VBox status code.
5793	* @param pThis The shared VGA/VMSVGA instance data.
5794	* @param pThisCC The VGA/VMSVGA state for ring-3.
5795	*/
5796	static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5797	{
5798	/* Device caps. */
5799	pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
5800	\| SVGA_CAP_GMR2
5801	\| SVGA_CAP_CURSOR
5802	\| SVGA_CAP_CURSOR_BYPASS
5803	\| SVGA_CAP_CURSOR_BYPASS_2
5804	\| SVGA_CAP_EXTENDED_FIFO
5805	\| SVGA_CAP_IRQMASK
5806	\| SVGA_CAP_PITCHLOCK
5807	\| SVGA_CAP_RECT_COPY
5808	\| SVGA_CAP_TRACES
5809	\| SVGA_CAP_SCREEN_OBJECT_2
5810	\| SVGA_CAP_ALPHA_CURSOR;
5811
5812	/* VGPU10 capabilities. */
5813	if (pThis->fVMSVGA10)
5814	{
5815	pThis->svga.u32DeviceCaps \|= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
5816	// \| SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
5817	;
5818
5819	# ifdef VBOX_WITH_VMSVGA3D
5820	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5821	if (pSVGAState->pFuncsGBO)
5822	pThis->svga.u32DeviceCaps \|= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
5823	if (pSVGAState->pFuncsDX)
5824	pThis->svga.u32DeviceCaps \|= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
5825	# endif
5826	}
5827
5828	# ifdef VBOX_WITH_VMSVGA3D
5829	pThis->svga.u32DeviceCaps \|= SVGA_CAP_3D;
5830	# endif
5831
5832	/* Clear the FIFO. */
5833	RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
5834
5835	/* Setup FIFO capabilities. */
5836	pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
5837	\| SVGA_FIFO_CAP_PITCHLOCK
5838	\| SVGA_FIFO_CAP_CURSOR_BYPASS_3
5839	\| SVGA_FIFO_CAP_RESERVE
5840	\| SVGA_FIFO_CAP_GMR2
5841	\| SVGA_FIFO_CAP_3D_HWVERSION_REVISED
5842	\| SVGA_FIFO_CAP_SCREEN_OBJECT_2;
5843
5844	/* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
5845	pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
5846	}
5847
5848	# ifdef VBOX_WITH_VMSVGA3D
5849	/**
5850	* Initializes the host 3D capabilities and writes them to FIFO memory.
5851	*
5852	* @returns VBox status code.
5853	* @param pThis The shared VGA/VMSVGA instance data.
5854	* @param pThisCC The VGA/VMSVGA state for ring-3.
5855	*/
5856	static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
5857	{
5858	/* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
5859	bool const fSavedBuffering = RTLogRelSetBuffering(true);
5860
5861	for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
5862	{
5863	uint32_t val = 0;
5864	int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
5865	if (RT_SUCCESS(rc))
5866	pThis->svga.au32DevCaps[i] = val;
5867	else
5868	pThis->svga.au32DevCaps[i] = 0;
5869
5870	/* LogRel the capability value. */
5871	if (i < SVGA3D_DEVCAP_MAX)
5872	{
5873	char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
5874	if (RT_SUCCESS(rc))
5875	{
5876	if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
5877	\|\| i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
5878	\|\| i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
5879	{
5880	float const fval = (float )&val;
5881	LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
5882	}
5883	else
5884	LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
5885	}
5886	else
5887	LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
5888	}
5889	else
5890	LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
5891	}
5892
5893	RTLogRelSetBuffering(fSavedBuffering);
5894
5895	/* 3d hardware version; latest and greatest */
5896	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
5897	pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
5898
5899	/* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
5900	* SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
5901	* If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
5902	* register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
5903	*/
5904	SVGA3dCapsRecord *pCaps;
5905	SVGA3dCapPair *pData;
5906
5907	pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
5908	pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
5909	pData = (SVGA3dCapPair *)&pCaps->data;
5910
5911	AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
5912	for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
5913	{
5914	pData[i][0] = i;
5915	pData[i][1] = pThis->svga.au32DevCaps[i];
5916	}
5917	pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
5918	pCaps = (SVGA3dCapsRecord )((uint32_t )pCaps + pCaps->header.length);
5919
5920	/* Mark end of record array (a zero word). */
5921	pCaps->header.length = 0;
5922	}
5923
5924	# endif
5925
5926	/**
5927	* Resets the SVGA hardware state
5928	*
5929	* @returns VBox status code.
5930	* @param pDevIns The device instance.
5931	*/
5932	int vmsvgaR3Reset(PPDMDEVINS pDevIns)
5933	{
5934	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5935	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5936	PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
5937
5938	/* Reset before init? */
5939	if (!pSVGAState)
5940	return VINF_SUCCESS;
5941
5942	Log(("vmsvgaR3Reset\n"));
5943
5944	/* Reset the FIFO processing as well as the 3d state (if we have one). */
5945	pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
5946	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /pvParam/, 10000 /ms/);
5947
5948	/* Reset other stuff. */
5949	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
5950	RT_ZERO(pThis->svga.au32ScratchRegion);
5951
5952	ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
5953
5954	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
5955	vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
5956
5957	RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
5958
5959	# ifdef VBOX_WITH_VMSVGA3D
5960	/* Device capabilities depend on this. */
5961	if (pThis->svga.f3DEnabled)
5962	vmsvgaR3Init3dInterfaces(pThisCC);
5963	# endif
5964
5965	/* Initialize FIFO and register capabilities. */
5966	vmsvgaR3InitCaps(pThis, pThisCC);
5967
5968	# ifdef VBOX_WITH_VMSVGA3D
5969	if (pThis->svga.f3DEnabled)
5970	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
5971	# endif
5972
5973	/* VRAM tracking is enabled by default during bootup. */
5974	pThis->svga.fVRAMTracking = true;
5975	pThis->svga.fEnabled = false;
5976
5977	/* Invalidate current settings. */
5978	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
5979	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
5980	pThis->svga.uBpp = pThis->svga.uHostBpp;
5981	pThis->svga.cbScanline = 0;
5982	pThis->svga.u32PitchLock = 0;
5983
5984	return rc;
5985	}
5986
5987	/**
5988	* Cleans up the SVGA hardware state
5989	*
5990	* @returns VBox status code.
5991	* @param pDevIns The device instance.
5992	*/
5993	int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
5994	{
5995	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5996	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5997
5998	/*
5999	* Ask the FIFO thread to terminate the 3d state and then terminate it.
6000	*/
6001	if (pThisCC->svga.pFIFOIOThread)
6002	{
6003	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
6004	NULL /pvParam/, 30000 /ms/);
6005	AssertLogRelRC(rc);
6006
6007	rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
6008	AssertLogRelRC(rc);
6009	pThisCC->svga.pFIFOIOThread = NULL;
6010	}
6011
6012	/*
6013	* Destroy the special SVGA state.
6014	*/
6015	if (pThisCC->svga.pSvgaR3State)
6016	{
6017	vmsvgaR3StateTerm(pThis, pThisCC->svga.pSvgaR3State);
6018
6019	RTMemFree(pThisCC->svga.pSvgaR3State);
6020	pThisCC->svga.pSvgaR3State = NULL;
6021	}
6022
6023	/*
6024	* Free our resources residing in the VGA state.
6025	*/
6026	if (pThisCC->svga.pbVgaFrameBufferR3)
6027	{
6028	RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
6029	pThisCC->svga.pbVgaFrameBufferR3 = NULL;
6030	}
6031	if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
6032	{
6033	RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
6034	pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
6035	}
6036	if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
6037	{
6038	PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
6039	pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
6040	}
6041
6042	return VINF_SUCCESS;
6043	}
6044
6045	/**
6046	* Initialize the SVGA hardware state
6047	*
6048	* @returns VBox status code.
6049	* @param pDevIns The device instance.
6050	*/
6051	int vmsvgaR3Init(PPDMDEVINS pDevIns)
6052	{
6053	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6054	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6055	PVMSVGAR3STATE pSVGAState;
6056	int rc;
6057
6058	pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
6059	memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
6060
6061	pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
6062
6063	/* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
6064	pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
6065	AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
6066
6067	/* Create event semaphore. */
6068	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
6069	AssertRCReturn(rc, rc);
6070
6071	/* Create event semaphore. */
6072	rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
6073	AssertRCReturn(rc, rc);
6074
6075	pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
6076	AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
6077
6078	rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
6079	AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
6080
6081	pSVGAState = pThisCC->svga.pSvgaR3State;
6082
6083	/* Register the write-protected GBO access handler type. */
6084	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6085	vmsvgaR3GboAccessHandler,
6086	NULL, NULL, NULL,
6087	NULL, NULL, NULL,
6088	"VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
6089	AssertRCReturn(rc, rc);
6090
6091	# ifdef VBOX_WITH_VMSVGA3D
6092	if (pThis->svga.f3DEnabled)
6093	{
6094	rc = vmsvga3dInit(pDevIns, pThis, pThisCC);
6095	if (RT_SUCCESS(rc))
6096	{
6097	/* Device capabilities depend on this. */
6098	vmsvgaR3Init3dInterfaces(pThisCC);
6099	}
6100	else
6101	{
6102	LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
6103	pThis->svga.f3DEnabled = false;
6104	}
6105	}
6106	# endif
6107
6108	/* Initialize FIFO and register capabilities. */
6109	vmsvgaR3InitCaps(pThis, pThisCC);
6110
6111	/* VRAM tracking is enabled by default during bootup. */
6112	pThis->svga.fVRAMTracking = true;
6113
6114	/* Set up the host bpp. This value is as a default for the programmable
6115	* bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
6116	* exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
6117	* separated as SVGA_REG_HOST_BITS_PER_PIXEL.
6118	*
6119	* NB: The driver cBits value is currently constant for the lifetime of the
6120	* VM. If that changes, the host bpp logic might need revisiting.
6121	*/
6122	pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
6123
6124	/* Invalidate current settings. */
6125	pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
6126	pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
6127	pThis->svga.uBpp = pThis->svga.uHostBpp;
6128	pThis->svga.cbScanline = 0;
6129
6130	pThis->svga.u32MaxWidth = VBE_DISPI_MAX_YRES;
6131	pThis->svga.u32MaxHeight = VBE_DISPI_MAX_XRES;
6132	while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
6133	{
6134	pThis->svga.u32MaxWidth -= 256;
6135	pThis->svga.u32MaxHeight -= 256;
6136	}
6137	Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
6138
6139	# ifdef DEBUG_GMR_ACCESS
6140	/* Register the GMR access handler type. */
6141	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
6142	vmsvgaR3GmrAccessHandler,
6143	NULL, NULL, NULL,
6144	NULL, NULL, NULL,
6145	"VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
6146	AssertRCReturn(rc, rc);
6147	# endif
6148
6149	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6150	/* Register the FIFO access handler type. In addition to
6151	debugging FIFO access, this is also used to facilitate
6152	extended fifo thread sleeps. */
6153	rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
6154	# ifdef DEBUG_FIFO_ACCESS
6155	PGMPHYSHANDLERKIND_ALL,
6156	# else
6157	PGMPHYSHANDLERKIND_WRITE,
6158	# endif
6159	vmsvgaR3FifoAccessHandler,
6160	NULL, NULL, NULL,
6161	NULL, NULL, NULL,
6162	"VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
6163	AssertRCReturn(rc, rc);
6164	# endif
6165
6166	/* Create the async IO thread. */
6167	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
6168	RTTHREADTYPE_IO, "VMSVGA FIFO");
6169	if (RT_FAILURE(rc))
6170	{
6171	AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
6172	return rc;
6173	}
6174
6175	/*
6176	* Statistics.
6177	*/
6178	# define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
6179	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
6180	# define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
6181	PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
6182	# ifdef VBOX_WITH_STATISTICS
6183	REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
6184	REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
6185	REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
6186	# endif
6187	REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
6188	REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
6189	REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
6190	REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
6191	REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
6192	REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
6193	REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
6194	REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
6195	REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
6196	REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
6197	REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
6198	REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
6199	REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
6200	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
6201	REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
6202	REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
6203	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
6204	REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
6205	REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
6206	REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
6207	REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
6208	REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
6209	REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
6210	REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
6211	REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
6212	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
6213	REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
6214	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
6215	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
6216	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
6217	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
6218	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
6219	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
6220	REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
6221	REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
6222	REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
6223	REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
6224	REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
6225	REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
6226	REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
6227	REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
6228	REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
6229	REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
6230	REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
6231	REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
6232	REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
6233	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
6234	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
6235	REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
6236	REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
6237	REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
6238	REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
6239	REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
6240	REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
6241	REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
6242	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
6243	REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
6244	REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
6245	REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
6246
6247	REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
6248	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
6249	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
6250	REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
6251	REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
6252	REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
6253	REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
6254	REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
6255	REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
6256	REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
6257	REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
6258	REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
6259	REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
6260	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
6261	REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
6262	REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
6263	REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
6264	REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
6265	REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
6266	REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
6267	REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
6268	REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
6269	REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
6270	REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
6271	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
6272	REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
6273	REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
6274	REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
6275	REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
6276	REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
6277	REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
6278	REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
6279	REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
6280	REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
6281	REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
6282	REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
6283	REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
6284	REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
6285	REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
6286	REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
6287
6288	REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
6289	REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
6290	REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
6291	REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
6292	REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
6293	REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
6294	REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
6295	REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
6296	REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
6297	REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
6298	REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
6299	REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
6300	REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
6301	REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
6302	REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
6303	REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
6304	REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
6305	REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
6306	REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
6307	REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
6308	REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
6309	REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
6310	REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
6311	REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
6312	REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
6313	REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
6314	REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
6315	REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
6316	REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
6317	REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
6318	REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
6319	REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
6320	REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
6321	REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
6322	REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
6323	REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
6324	REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
6325	REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
6326	REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
6327	REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
6328	REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
6329	REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
6330	REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
6331	REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
6332	REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
6333	REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
6334	REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
6335	REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
6336	REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
6337	REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
6338	REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
6339	REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
6340	REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
6341	REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
6342	REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
6343	REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
6344	REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
6345	REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
6346	REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
6347	REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
6348	REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
6349	REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
6350
6351	REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
6352	REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
6353	REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
6354	REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
6355	REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
6356	REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
6357	REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
6358	REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
6359	# if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) \|\| defined(DEBUG_FIFO_ACCESS)
6360	REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
6361	# endif
6362	REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
6363	REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
6364	REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
6365	REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
6366	REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
6367
6368	# undef REG_CNT
6369	# undef REG_PRF
6370
6371	/*
6372	* Info handlers.
6373	*/
6374	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
6375	# ifdef VBOX_WITH_VMSVGA3D
6376	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
6377	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
6378	"VMSVGA 3d surface details. "
6379	"Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
6380	vmsvgaR3Info3dSurface);
6381	PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
6382	"VMSVGA 3d surface details and bitmap: "
6383	"sid[>dir]",
6384	vmsvgaR3Info3dSurfaceBmp);
6385	# endif
6386
6387	return VINF_SUCCESS;
6388	}
6389
6390	/**
6391	* Power On notification.
6392	*
6393	* @returns VBox status code.
6394	* @param pDevIns The device instance data.
6395	*
6396	* @remarks Caller enters the device critical section.
6397	*/
6398	DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
6399	{
6400	# ifdef VBOX_WITH_VMSVGA3D
6401	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6402	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6403	if (pThis->svga.f3DEnabled)
6404	{
6405	int rc = vmsvga3dPowerOn(pDevIns, pThis, pThisCC);
6406	if (RT_SUCCESS(rc))
6407	{
6408	/* Initialize FIFO 3D capabilities. */
6409	vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
6410	}
6411	}
6412	# else /* !VBOX_WITH_VMSVGA3D */
6413	RT_NOREF(pDevIns);
6414	# endif /* !VBOX_WITH_VMSVGA3D */
6415	}
6416
6417	/**
6418	* Power Off notification.
6419	*
6420	* @param pDevIns The device instance data.
6421	*
6422	* @remarks Caller enters the device critical section.
6423	*/
6424	DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
6425	{
6426	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6427	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6428
6429	/*
6430	* Notify the FIFO thread.
6431	*/
6432	if (pThisCC->svga.pFIFOIOThread)
6433	{
6434	int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
6435	NULL /pvParam/, 30000 /ms/);
6436	AssertLogRelRC(rc);
6437	}
6438	}
6439
6440	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp@ 87979

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