1 | /* $Id: DevVGA-SVGA.cpp 89183 2021-05-19 20:41:10Z vboxsync $ */
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2 | /** @file
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3 | * VMware SVGA device.
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4 | *
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5 | * Logging levels guidelines for this and related files:
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6 | * - Log() for normal bits.
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7 | * - LogFlow() for more info.
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8 | * - Log2 for hex dump of cursor data.
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9 | * - Log3 for hex dump of shader code.
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10 | * - Log4 for hex dumps of 3D data.
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11 | * - Log5 for info about GMR pages.
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12 | * - Log6 for DX shaders.
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13 | * - Log7 for SVGA command dump.
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14 | * - LogRel for the usual important stuff.
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15 | * - LogRel2 for cursor.
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16 | * - LogRel3 for 3D performance data.
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17 | * - LogRel4 for HW accelerated graphics output.
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18 | */
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19 |
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20 | /*
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21 | * Copyright (C) 2013-2020 Oracle Corporation
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22 | *
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23 | * This file is part of VirtualBox Open Source Edition (OSE), as
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24 | * available from http://www.virtualbox.org. This file is free software;
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25 | * you can redistribute it and/or modify it under the terms of the GNU
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26 | * General Public License (GPL) as published by the Free Software
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27 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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28 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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29 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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30 | */
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31 |
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32 |
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33 | /** @page pg_dev_vmsvga VMSVGA - VMware SVGA II Device Emulation
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34 | *
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35 | * This device emulation was contributed by trivirt AG. It offers an
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36 | * alternative to our Bochs based VGA graphics and 3d emulations. This is
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37 | * valuable for Xorg based guests, as there is driver support shipping with Xorg
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38 | * since it forked from XFree86.
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39 | *
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40 | *
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41 | * @section sec_dev_vmsvga_sdk The VMware SDK
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42 | *
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43 | * This is officially deprecated now, however it's still quite useful,
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44 | * especially for getting the old features working:
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45 | * http://vmware-svga.sourceforge.net/
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46 | *
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47 | * They currently point developers at the following resources.
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48 | * - http://cgit.freedesktop.org/xorg/driver/xf86-video-vmware/
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49 | * - http://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/svga/
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50 | * - http://cgit.freedesktop.org/mesa/vmwgfx/
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51 | *
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52 | * @subsection subsec_dev_vmsvga_sdk_results Test results
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53 | *
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54 | * Test results:
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55 | * - 2dmark.img:
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56 | * + todo
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57 | * - backdoor-tclo.img:
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58 | * + todo
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59 | * - blit-cube.img:
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60 | * + todo
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61 | * - bunnies.img:
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62 | * + todo
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63 | * - cube.img:
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64 | * + todo
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65 | * - cubemark.img:
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66 | * + todo
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67 | * - dynamic-vertex-stress.img:
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68 | * + todo
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69 | * - dynamic-vertex.img:
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70 | * + todo
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71 | * - fence-stress.img:
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72 | * + todo
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73 | * - gmr-test.img:
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74 | * + todo
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75 | * - half-float-test.img:
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76 | * + todo
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77 | * - noscreen-cursor.img:
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78 | * - The CURSOR I/O and FIFO registers are not implemented, so the mouse
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79 | * cursor doesn't show. (Hacking the GUI a little, would make the cursor
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80 | * visible though.)
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81 | * - Cursor animation via the palette doesn't work.
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82 | * - During debugging, it turns out that the framebuffer content seems to
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83 | * be halfways ignore or something (memset(fb, 0xcc, lots)).
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84 | * - Trouble with way to small FIFO and the 256x256 cursor fails. Need to
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85 | * grow it 0x10 fold (128KB -> 2MB like in WS10).
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86 | * - null.img:
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87 | * + todo
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88 | * - pong.img:
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89 | * + todo
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90 | * - presentReadback.img:
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91 | * + todo
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92 | * - resolution-set.img:
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93 | * + todo
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94 | * - rt-gamma-test.img:
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95 | * + todo
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96 | * - screen-annotation.img:
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97 | * + todo
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98 | * - screen-cursor.img:
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99 | * + todo
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100 | * - screen-dma-coalesce.img:
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101 | * + todo
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102 | * - screen-gmr-discontig.img:
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103 | * + todo
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104 | * - screen-gmr-remap.img:
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105 | * + todo
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106 | * - screen-multimon.img:
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107 | * + todo
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108 | * - screen-present-clip.img:
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109 | * + todo
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110 | * - screen-render-test.img:
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111 | * + todo
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112 | * - screen-simple.img:
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113 | * + todo
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114 | * - screen-text.img:
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115 | * + todo
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116 | * - simple-shaders.img:
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117 | * + todo
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118 | * - simple_blit.img:
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119 | * + todo
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120 | * - tiny-2d-updates.img:
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121 | * + todo
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122 | * - video-formats.img:
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123 | * + todo
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124 | * - video-sync.img:
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125 | * + todo
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126 | *
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127 | */
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128 |
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129 |
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130 | /*********************************************************************************************************************************
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131 | * Header Files *
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132 | *********************************************************************************************************************************/
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133 | #define LOG_GROUP LOG_GROUP_DEV_VMSVGA
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134 | #include <VBox/vmm/pdmdev.h>
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135 | #include <VBox/version.h>
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136 | #include <VBox/err.h>
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137 | #include <VBox/log.h>
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138 | #include <VBox/vmm/pgm.h>
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139 | #include <VBox/sup.h>
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140 |
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141 | #include <iprt/assert.h>
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142 | #include <iprt/semaphore.h>
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143 | #include <iprt/uuid.h>
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144 | #ifdef IN_RING3
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145 | # include <iprt/ctype.h>
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146 | # include <iprt/mem.h>
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147 | # ifdef VBOX_STRICT
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148 | # include <iprt/time.h>
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149 | # endif
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150 | #endif
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151 |
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152 | #include <VBox/AssertGuest.h>
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153 | #include <VBox/VMMDev.h>
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154 | #include <VBoxVideo.h>
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155 | #include <VBox/bioslogo.h>
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156 |
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157 | #ifdef LOG_ENABLED
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158 | #include "svgadump/svga_dump.h"
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159 | #endif
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160 |
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161 | /* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
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162 | #include "DevVGA.h"
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163 |
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164 | /* Should be included after DevVGA.h/DevVGA-SVGA.h to pick all defines. */
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165 | #ifdef VBOX_WITH_VMSVGA3D
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166 | # include "DevVGA-SVGA3d.h"
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167 | # ifdef RT_OS_DARWIN
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168 | # include "DevVGA-SVGA3d-cocoa.h"
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169 | # endif
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170 | # ifdef RT_OS_LINUX
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171 | # ifdef IN_RING3
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172 | # include "DevVGA-SVGA3d-glLdr.h"
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173 | # endif
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174 | # endif
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175 | #endif
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176 | #ifdef IN_RING3
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177 | #include "DevVGA-SVGA-internal.h"
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178 | #endif
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179 |
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180 |
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181 | /*********************************************************************************************************************************
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182 | * Defined Constants And Macros *
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183 | *********************************************************************************************************************************/
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184 | /**
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185 | * Macro for checking if a fixed FIFO register is valid according to the
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186 | * current FIFO configuration.
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187 | *
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188 | * @returns true / false.
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189 | * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
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190 | * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
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191 | */
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192 | #define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
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193 |
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194 |
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195 | /*********************************************************************************************************************************
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196 | * Structures and Typedefs *
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197 | *********************************************************************************************************************************/
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198 |
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199 |
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200 | /*********************************************************************************************************************************
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201 | * Internal Functions *
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202 | *********************************************************************************************************************************/
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203 | #ifdef IN_RING3
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204 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
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205 | static FNPGMPHYSHANDLER vmsvgaR3FifoAccessHandler;
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206 | # endif
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207 | # ifdef DEBUG_GMR_ACCESS
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208 | static FNPGMPHYSHANDLER vmsvgaR3GmrAccessHandler;
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209 | # endif
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210 | #endif
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211 |
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212 |
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213 | /*********************************************************************************************************************************
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214 | * Global Variables *
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215 | *********************************************************************************************************************************/
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216 | #ifdef IN_RING3
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217 |
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218 | /**
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219 | * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
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220 | */
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221 | static SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
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222 | {
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223 | SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
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224 | SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),
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225 | SSMFIELD_ENTRY_TERM()
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226 | };
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227 |
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228 | /**
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229 | * SSM descriptor table for the GMR structure.
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230 | */
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231 | static SSMFIELD const g_aGMRFields[] =
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232 | {
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233 | SSMFIELD_ENTRY( GMR, cMaxPages),
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234 | SSMFIELD_ENTRY( GMR, cbTotal),
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235 | SSMFIELD_ENTRY( GMR, numDescriptors),
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236 | SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),
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237 | SSMFIELD_ENTRY_TERM()
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238 | };
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239 |
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240 | /**
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241 | * SSM descriptor table for the VMSVGASCREENOBJECT structure.
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242 | */
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243 | static SSMFIELD const g_aVMSVGASCREENOBJECTFields[] =
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244 | {
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245 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fuScreen),
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246 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, idScreen),
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247 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, xOrigin),
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248 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, yOrigin),
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249 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cWidth),
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250 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cHeight),
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251 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, offVRAM),
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252 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cbPitch),
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253 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, cBpp),
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254 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fDefined),
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255 | SSMFIELD_ENTRY( VMSVGASCREENOBJECT, fModified),
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256 | SSMFIELD_ENTRY_VER( VMSVGASCREENOBJECT, cDpi, VGA_SAVEDSTATE_VERSION_VMSVGA_MIPLEVELS),
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257 | SSMFIELD_ENTRY_TERM()
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258 | };
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259 |
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260 | /**
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261 | * SSM descriptor table for the VMSVGAR3STATE structure.
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262 | */
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263 | static SSMFIELD const g_aVMSVGAR3STATEFields[] =
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264 | {
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265 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, paGMR),
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266 | SSMFIELD_ENTRY( VMSVGAR3STATE, GMRFB),
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267 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.fActive),
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268 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.xHotspot),
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269 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.yHotspot),
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270 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.width),
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271 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.height),
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272 | SSMFIELD_ENTRY( VMSVGAR3STATE, Cursor.cbData),
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273 | SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAR3STATE, Cursor.pData),
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274 | SSMFIELD_ENTRY( VMSVGAR3STATE, colorAnnotation),
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275 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, cBusyDelayedEmts),
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276 | #ifdef VMSVGA_USE_EMT_HALT_CODE
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277 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, BusyDelayedEmts),
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278 | #else
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279 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, hBusyDelayedEmts),
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280 | #endif
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281 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatBusyDelayEmts),
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282 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentProf),
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283 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitivesProf),
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284 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDmaProf),
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285 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBlitSurfaceToScreenProf),
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286 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2),
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287 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Free),
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288 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmr2Modify),
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289 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2),
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290 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRemapGmr2Modify),
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291 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdInvalidCmd),
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292 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdFence),
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293 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdate),
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294 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdUpdateVerbose),
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295 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineCursor),
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296 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineAlphaCursor),
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297 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdMoveCursor),
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298 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDisplayCursor),
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299 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectFill),
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300 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectCopy),
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301 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdRectRopCopy),
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302 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdEscape),
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303 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineScreen),
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304 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDestroyScreen),
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305 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdDefineGmrFb),
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306 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitGmrFbToScreen),
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307 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdBlitScreentoGmrFb),
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308 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationFill),
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309 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3CmdAnnotationCopy),
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310 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefine),
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311 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDefineV2),
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312 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDestroy),
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313 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceCopy),
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314 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceStretchBlt),
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315 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceDma),
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316 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSurfaceScreen),
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317 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDefine),
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318 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dContextDestroy),
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319 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTransform),
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320 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetZRange),
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321 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderState),
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322 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetRenderTarget),
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323 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetTextureState),
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324 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetMaterial),
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325 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightData),
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326 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetLightEnable),
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327 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetViewPort),
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328 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetClipPlane),
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329 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dClear),
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330 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresent),
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331 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dPresentReadBack),
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332 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDefine),
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333 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dShaderDestroy),
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334 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShader),
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335 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetShaderConst),
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336 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDrawPrimitives),
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337 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dSetScissorRect),
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338 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dBeginQuery),
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339 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dEndQuery),
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340 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dWaitForQuery),
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341 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dGenerateMipmaps),
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342 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dActivateSurface),
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343 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3Cmd3dDeactivateSurface),
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344 |
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345 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegConfigDoneWr),
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346 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWr),
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347 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrErrors),
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348 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatR3RegGmrDescriptorWrFree),
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349 |
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350 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCommands),
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351 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoErrors),
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352 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoUnkCmds),
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353 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoTimeout),
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354 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoTodoWoken),
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355 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoStalls),
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356 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoExtendedSleep),
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357 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
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358 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoAccessHandler),
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359 | # endif
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360 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorFetchAgain),
|
---|
361 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorNoChange),
|
---|
362 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorPosition),
|
---|
363 | SSMFIELD_ENTRY_IGNORE( VMSVGAR3STATE, StatFifoCursorVisiblity),
|
---|
364 |
|
---|
365 | SSMFIELD_ENTRY_TERM()
|
---|
366 | };
|
---|
367 |
|
---|
368 | /**
|
---|
369 | * SSM descriptor table for the VGAState.svga structure.
|
---|
370 | */
|
---|
371 | static SSMFIELD const g_aVGAStateSVGAFields[] =
|
---|
372 | {
|
---|
373 | SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
|
---|
374 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),
|
---|
375 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFOConfig),
|
---|
376 | SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),
|
---|
377 | SSMFIELD_ENTRY( VMSVGAState, fEnabled),
|
---|
378 | SSMFIELD_ENTRY( VMSVGAState, fConfigured),
|
---|
379 | SSMFIELD_ENTRY( VMSVGAState, fBusy),
|
---|
380 | SSMFIELD_ENTRY( VMSVGAState, fTraces),
|
---|
381 | SSMFIELD_ENTRY( VMSVGAState, u32GuestId),
|
---|
382 | SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),
|
---|
383 | SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),
|
---|
384 | SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),
|
---|
385 | SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),
|
---|
386 | SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),
|
---|
387 | SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),
|
---|
388 | SSMFIELD_ENTRY( VMSVGAState, u32DeviceCaps),
|
---|
389 | SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),
|
---|
390 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, hFIFORequestSem),
|
---|
391 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, uLastCursorUpdateCount),
|
---|
392 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFIFOThreadSleeping),
|
---|
393 | SSMFIELD_ENTRY_VER( VMSVGAState, fGFBRegisters, VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS),
|
---|
394 | SSMFIELD_ENTRY( VMSVGAState, uWidth),
|
---|
395 | SSMFIELD_ENTRY( VMSVGAState, uHeight),
|
---|
396 | SSMFIELD_ENTRY( VMSVGAState, uBpp),
|
---|
397 | SSMFIELD_ENTRY( VMSVGAState, cbScanline),
|
---|
398 | SSMFIELD_ENTRY_VER( VMSVGAState, uScreenOffset, VGA_SAVEDSTATE_VERSION_VMSVGA),
|
---|
399 | SSMFIELD_ENTRY_VER( VMSVGAState, uCursorX, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
|
---|
400 | SSMFIELD_ENTRY_VER( VMSVGAState, uCursorY, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
|
---|
401 | SSMFIELD_ENTRY_VER( VMSVGAState, uCursorID, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
|
---|
402 | SSMFIELD_ENTRY_VER( VMSVGAState, uCursorOn, VGA_SAVEDSTATE_VERSION_VMSVGA_CURSOR),
|
---|
403 | SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),
|
---|
404 | SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),
|
---|
405 | SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),
|
---|
406 | SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),
|
---|
407 | SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),
|
---|
408 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
|
---|
409 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, fFifoExtCommandWakeup),
|
---|
410 | SSMFIELD_ENTRY_IGNORE( VMSVGAState, cGMR),
|
---|
411 | SSMFIELD_ENTRY_TERM()
|
---|
412 | };
|
---|
413 | #endif /* IN_RING3 */
|
---|
414 |
|
---|
415 |
|
---|
416 | /*********************************************************************************************************************************
|
---|
417 | * Internal Functions *
|
---|
418 | *********************************************************************************************************************************/
|
---|
419 | #ifdef IN_RING3
|
---|
420 | static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces);
|
---|
421 | static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC, PSSMHANDLE pSSM,
|
---|
422 | uint32_t uVersion, uint32_t uPass);
|
---|
423 | static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM);
|
---|
424 | static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx);
|
---|
425 | #endif /* IN_RING3 */
|
---|
426 |
|
---|
427 |
|
---|
428 | #define SVGA_CASE_ID2STR(idx) case idx: return #idx
|
---|
429 | #if defined(LOG_ENABLED)
|
---|
430 | /**
|
---|
431 | * Index register string name lookup
|
---|
432 | *
|
---|
433 | * @returns Index register string or "UNKNOWN"
|
---|
434 | * @param pThis The shared VGA/VMSVGA state.
|
---|
435 | * @param idxReg The index register.
|
---|
436 | */
|
---|
437 | static const char *vmsvgaIndexToString(PVGASTATE pThis, uint32_t idxReg)
|
---|
438 | {
|
---|
439 | AssertCompile(SVGA_REG_TOP == 77); /* Ensure that the correct headers are used. */
|
---|
440 | switch (idxReg)
|
---|
441 | {
|
---|
442 | SVGA_CASE_ID2STR(SVGA_REG_ID);
|
---|
443 | SVGA_CASE_ID2STR(SVGA_REG_ENABLE);
|
---|
444 | SVGA_CASE_ID2STR(SVGA_REG_WIDTH);
|
---|
445 | SVGA_CASE_ID2STR(SVGA_REG_HEIGHT);
|
---|
446 | SVGA_CASE_ID2STR(SVGA_REG_MAX_WIDTH);
|
---|
447 | SVGA_CASE_ID2STR(SVGA_REG_MAX_HEIGHT);
|
---|
448 | SVGA_CASE_ID2STR(SVGA_REG_DEPTH);
|
---|
449 | SVGA_CASE_ID2STR(SVGA_REG_BITS_PER_PIXEL); /* Current bpp in the guest */
|
---|
450 | SVGA_CASE_ID2STR(SVGA_REG_PSEUDOCOLOR);
|
---|
451 | SVGA_CASE_ID2STR(SVGA_REG_RED_MASK);
|
---|
452 | SVGA_CASE_ID2STR(SVGA_REG_GREEN_MASK);
|
---|
453 | SVGA_CASE_ID2STR(SVGA_REG_BLUE_MASK);
|
---|
454 | SVGA_CASE_ID2STR(SVGA_REG_BYTES_PER_LINE);
|
---|
455 | SVGA_CASE_ID2STR(SVGA_REG_FB_START); /* (Deprecated) */
|
---|
456 | SVGA_CASE_ID2STR(SVGA_REG_FB_OFFSET);
|
---|
457 | SVGA_CASE_ID2STR(SVGA_REG_VRAM_SIZE);
|
---|
458 | SVGA_CASE_ID2STR(SVGA_REG_FB_SIZE);
|
---|
459 |
|
---|
460 | /* ID 0 implementation only had the above registers, then the palette */
|
---|
461 | SVGA_CASE_ID2STR(SVGA_REG_CAPABILITIES);
|
---|
462 | SVGA_CASE_ID2STR(SVGA_REG_MEM_START); /* (Deprecated) */
|
---|
463 | SVGA_CASE_ID2STR(SVGA_REG_MEM_SIZE);
|
---|
464 | SVGA_CASE_ID2STR(SVGA_REG_CONFIG_DONE); /* Set when memory area configured */
|
---|
465 | SVGA_CASE_ID2STR(SVGA_REG_SYNC); /* See "FIFO Synchronization Registers" */
|
---|
466 | SVGA_CASE_ID2STR(SVGA_REG_BUSY); /* See "FIFO Synchronization Registers" */
|
---|
467 | SVGA_CASE_ID2STR(SVGA_REG_GUEST_ID); /* Set guest OS identifier */
|
---|
468 | SVGA_CASE_ID2STR(SVGA_REG_DEAD); /* (Deprecated) SVGA_REG_CURSOR_ID. */
|
---|
469 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_X); /* (Deprecated) */
|
---|
470 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_Y); /* (Deprecated) */
|
---|
471 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_ON); /* (Deprecated) */
|
---|
472 | SVGA_CASE_ID2STR(SVGA_REG_HOST_BITS_PER_PIXEL); /* (Deprecated) */
|
---|
473 | SVGA_CASE_ID2STR(SVGA_REG_SCRATCH_SIZE); /* Number of scratch registers */
|
---|
474 | SVGA_CASE_ID2STR(SVGA_REG_MEM_REGS); /* Number of FIFO registers */
|
---|
475 | SVGA_CASE_ID2STR(SVGA_REG_NUM_DISPLAYS); /* (Deprecated) */
|
---|
476 | SVGA_CASE_ID2STR(SVGA_REG_PITCHLOCK); /* Fixed pitch for all modes */
|
---|
477 | SVGA_CASE_ID2STR(SVGA_REG_IRQMASK); /* Interrupt mask */
|
---|
478 |
|
---|
479 | /* Legacy multi-monitor support */
|
---|
480 | SVGA_CASE_ID2STR(SVGA_REG_NUM_GUEST_DISPLAYS); /* Number of guest displays in X/Y direction */
|
---|
481 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_ID); /* Display ID for the following display attributes */
|
---|
482 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_IS_PRIMARY); /* Whether this is a primary display */
|
---|
483 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_X); /* The display position x */
|
---|
484 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_POSITION_Y); /* The display position y */
|
---|
485 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_WIDTH); /* The display's width */
|
---|
486 | SVGA_CASE_ID2STR(SVGA_REG_DISPLAY_HEIGHT); /* The display's height */
|
---|
487 |
|
---|
488 | SVGA_CASE_ID2STR(SVGA_REG_GMR_ID);
|
---|
489 | SVGA_CASE_ID2STR(SVGA_REG_GMR_DESCRIPTOR);
|
---|
490 | SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_IDS);
|
---|
491 | SVGA_CASE_ID2STR(SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
|
---|
492 |
|
---|
493 | SVGA_CASE_ID2STR(SVGA_REG_TRACES); /* Enable trace-based updates even when FIFO is on */
|
---|
494 | SVGA_CASE_ID2STR(SVGA_REG_GMRS_MAX_PAGES); /* Maximum number of 4KB pages for all GMRs */
|
---|
495 | SVGA_CASE_ID2STR(SVGA_REG_MEMORY_SIZE); /* Total dedicated device memory excluding FIFO */
|
---|
496 | SVGA_CASE_ID2STR(SVGA_REG_COMMAND_LOW); /* Lower 32 bits and submits commands */
|
---|
497 | SVGA_CASE_ID2STR(SVGA_REG_COMMAND_HIGH); /* Upper 32 bits of command buffer PA */
|
---|
498 | SVGA_CASE_ID2STR(SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); /* Max primary memory */
|
---|
499 | SVGA_CASE_ID2STR(SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); /* Suggested limit on mob mem */
|
---|
500 | SVGA_CASE_ID2STR(SVGA_REG_DEV_CAP); /* Write dev cap index, read value */
|
---|
501 | SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_LOW);
|
---|
502 | SVGA_CASE_ID2STR(SVGA_REG_CMD_PREPEND_HIGH);
|
---|
503 | SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_WIDTH);
|
---|
504 | SVGA_CASE_ID2STR(SVGA_REG_SCREENTARGET_MAX_HEIGHT);
|
---|
505 | SVGA_CASE_ID2STR(SVGA_REG_MOB_MAX_SIZE);
|
---|
506 | SVGA_CASE_ID2STR(SVGA_REG_BLANK_SCREEN_TARGETS);
|
---|
507 | SVGA_CASE_ID2STR(SVGA_REG_CAP2);
|
---|
508 | SVGA_CASE_ID2STR(SVGA_REG_DEVEL_CAP);
|
---|
509 | SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_ID);
|
---|
510 | SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION1);
|
---|
511 | SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION2);
|
---|
512 | SVGA_CASE_ID2STR(SVGA_REG_GUEST_DRIVER_VERSION3);
|
---|
513 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MOBID);
|
---|
514 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_BYTE_SIZE);
|
---|
515 | SVGA_CASE_ID2STR(SVGA_REG_CURSOR_MAX_DIMENSION);
|
---|
516 | SVGA_CASE_ID2STR(SVGA_REG_FIFO_CAPS);
|
---|
517 | SVGA_CASE_ID2STR(SVGA_REG_FENCE);
|
---|
518 | SVGA_CASE_ID2STR(SVGA_REG_RESERVED1);
|
---|
519 | SVGA_CASE_ID2STR(SVGA_REG_RESERVED2);
|
---|
520 | SVGA_CASE_ID2STR(SVGA_REG_RESERVED3);
|
---|
521 | SVGA_CASE_ID2STR(SVGA_REG_RESERVED4);
|
---|
522 | SVGA_CASE_ID2STR(SVGA_REG_RESERVED5);
|
---|
523 | SVGA_CASE_ID2STR(SVGA_REG_SCREENDMA);
|
---|
524 | SVGA_CASE_ID2STR(SVGA_REG_GBOBJECT_MEM_SIZE_KB);
|
---|
525 | SVGA_CASE_ID2STR(SVGA_REG_TOP); /* Must be 1 more than the last register */
|
---|
526 |
|
---|
527 | default:
|
---|
528 | if (idxReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
|
---|
529 | return "SVGA_SCRATCH_BASE reg";
|
---|
530 | if (idxReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
|
---|
531 | return "SVGA_PALETTE_BASE reg";
|
---|
532 | return "UNKNOWN";
|
---|
533 | }
|
---|
534 | }
|
---|
535 | #endif /* LOG_ENABLED */
|
---|
536 |
|
---|
537 | #if defined(LOG_ENABLED) || (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D))
|
---|
538 | static const char *vmsvgaDevCapIndexToString(SVGA3dDevCapIndex idxDevCap)
|
---|
539 | {
|
---|
540 | AssertCompile(SVGA3D_DEVCAP_MAX == 260);
|
---|
541 | switch (idxDevCap)
|
---|
542 | {
|
---|
543 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_INVALID);
|
---|
544 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_3D);
|
---|
545 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LIGHTS);
|
---|
546 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURES);
|
---|
547 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CLIP_PLANES);
|
---|
548 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER_VERSION);
|
---|
549 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_VERTEX_SHADER);
|
---|
550 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION);
|
---|
551 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_FRAGMENT_SHADER);
|
---|
552 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_RENDER_TARGETS);
|
---|
553 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S23E8_TEXTURES);
|
---|
554 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_S10E5_TEXTURES);
|
---|
555 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND);
|
---|
556 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D16_BUFFER_FORMAT);
|
---|
557 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT);
|
---|
558 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT);
|
---|
559 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_QUERY_TYPES);
|
---|
560 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING);
|
---|
561 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_POINT_SIZE);
|
---|
562 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SHADER_TEXTURES);
|
---|
563 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
|
---|
564 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
|
---|
565 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VOLUME_EXTENT);
|
---|
566 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT);
|
---|
567 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO);
|
---|
568 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY);
|
---|
569 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT);
|
---|
570 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_INDEX);
|
---|
571 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS);
|
---|
572 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS);
|
---|
573 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS);
|
---|
574 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS);
|
---|
575 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TEXTURE_OPS);
|
---|
576 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);
|
---|
577 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8);
|
---|
578 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10);
|
---|
579 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5);
|
---|
580 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5);
|
---|
581 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4);
|
---|
582 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R5G6B5);
|
---|
583 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16);
|
---|
584 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8);
|
---|
585 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ALPHA8);
|
---|
586 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8);
|
---|
587 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D16);
|
---|
588 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8);
|
---|
589 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8);
|
---|
590 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT1);
|
---|
591 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT2);
|
---|
592 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT3);
|
---|
593 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT4);
|
---|
594 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_DXT5);
|
---|
595 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8);
|
---|
596 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10);
|
---|
597 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8);
|
---|
598 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8);
|
---|
599 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_CxV8U8);
|
---|
600 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S10E5);
|
---|
601 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_R_S23E8);
|
---|
602 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5);
|
---|
603 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8);
|
---|
604 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5);
|
---|
605 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8);
|
---|
606 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MISSING62);
|
---|
607 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES);
|
---|
608 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS);
|
---|
609 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_V16U16);
|
---|
610 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_G16R16);
|
---|
611 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16);
|
---|
612 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_UYVY);
|
---|
613 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YUY2);
|
---|
614 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD4); /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
|
---|
615 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD5); /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
|
---|
616 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD7); /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
|
---|
617 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD6); /* SVGA3D_DEVCAP_SUPERSAMPLE */
|
---|
618 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_AUTOGENMIPMAPS);
|
---|
619 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_NV12);
|
---|
620 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD10); /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
|
---|
621 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);
|
---|
622 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_SURFACE_IDS);
|
---|
623 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF16);
|
---|
624 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_DF24);
|
---|
625 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT);
|
---|
626 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI1);
|
---|
627 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_ATI2);
|
---|
628 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD1);
|
---|
629 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD8); /* SVGA3D_DEVCAP_VIDEO_DECODE */
|
---|
630 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD9); /* SVGA3D_DEVCAP_VIDEO_PROCESS */
|
---|
631 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_AA);
|
---|
632 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LINE_STIPPLE);
|
---|
633 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_LINE_WIDTH);
|
---|
634 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH);
|
---|
635 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SURFACEFMT_YV12);
|
---|
636 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD3); /* Old SVGA3D_DEVCAP_LOGICOPS */
|
---|
637 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_TS_COLOR_KEY);
|
---|
638 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD2);
|
---|
639 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXCONTEXT);
|
---|
640 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DEAD11); /* SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE */
|
---|
641 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS);
|
---|
642 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS);
|
---|
643 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DX_PROVOKING_VERTEX);
|
---|
644 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);
|
---|
645 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8R8G8B8);
|
---|
646 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R5G6B5);
|
---|
647 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X1R5G5B5);
|
---|
648 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A1R5G5B5);
|
---|
649 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A4R4G4B4);
|
---|
650 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D32);
|
---|
651 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D16);
|
---|
652 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8);
|
---|
653 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D15S1);
|
---|
654 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8);
|
---|
655 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4);
|
---|
656 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE16);
|
---|
657 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8);
|
---|
658 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT1);
|
---|
659 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT2);
|
---|
660 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT3);
|
---|
661 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT4);
|
---|
662 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_DXT5);
|
---|
663 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPU8V8);
|
---|
664 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5);
|
---|
665 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8);
|
---|
666 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1);
|
---|
667 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5);
|
---|
668 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8);
|
---|
669 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2R10G10B10);
|
---|
670 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V8U8);
|
---|
671 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8);
|
---|
672 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_CxV8U8);
|
---|
673 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X8L8V8U8);
|
---|
674 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A2W10V10U10);
|
---|
675 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ALPHA8);
|
---|
676 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S10E5);
|
---|
677 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R_S23E8);
|
---|
678 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S10E5);
|
---|
679 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_RG_S23E8);
|
---|
680 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BUFFER);
|
---|
681 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24X8);
|
---|
682 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_V16U16);
|
---|
683 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G16R16);
|
---|
684 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A16B16G16R16);
|
---|
685 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_UYVY);
|
---|
686 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YUY2);
|
---|
687 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_NV12);
|
---|
688 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2); /* SVGA3D_DEVCAP_DXFMT_AYUV */
|
---|
689 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS);
|
---|
690 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT);
|
---|
691 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT);
|
---|
692 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS);
|
---|
693 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT);
|
---|
694 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT);
|
---|
695 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT);
|
---|
696 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS);
|
---|
697 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT);
|
---|
698 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM);
|
---|
699 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT);
|
---|
700 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS);
|
---|
701 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_UINT);
|
---|
702 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_SINT);
|
---|
703 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS);
|
---|
704 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT);
|
---|
705 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24);
|
---|
706 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT);
|
---|
707 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS);
|
---|
708 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT);
|
---|
709 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT);
|
---|
710 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS);
|
---|
711 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM);
|
---|
712 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB);
|
---|
713 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT);
|
---|
714 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT);
|
---|
715 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS);
|
---|
716 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UINT);
|
---|
717 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SINT);
|
---|
718 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS);
|
---|
719 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D32_FLOAT);
|
---|
720 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_UINT);
|
---|
721 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_SINT);
|
---|
722 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS);
|
---|
723 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT);
|
---|
724 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8);
|
---|
725 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT);
|
---|
726 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS);
|
---|
727 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM);
|
---|
728 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_UINT);
|
---|
729 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SINT);
|
---|
730 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS);
|
---|
731 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UNORM);
|
---|
732 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_UINT);
|
---|
733 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SNORM);
|
---|
734 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_SINT);
|
---|
735 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS);
|
---|
736 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UNORM);
|
---|
737 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_UINT);
|
---|
738 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SNORM);
|
---|
739 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8_SINT);
|
---|
740 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_P8);
|
---|
741 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP);
|
---|
742 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM);
|
---|
743 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM);
|
---|
744 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS);
|
---|
745 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB);
|
---|
746 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS);
|
---|
747 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB);
|
---|
748 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS);
|
---|
749 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB);
|
---|
750 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS);
|
---|
751 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI1);
|
---|
752 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_SNORM);
|
---|
753 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS);
|
---|
754 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_ATI2);
|
---|
755 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_SNORM);
|
---|
756 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM);
|
---|
757 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS);
|
---|
758 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB);
|
---|
759 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS);
|
---|
760 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB);
|
---|
761 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF16);
|
---|
762 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_DF24);
|
---|
763 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT);
|
---|
764 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_YV12);
|
---|
765 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT);
|
---|
766 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT);
|
---|
767 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM);
|
---|
768 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT);
|
---|
769 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM);
|
---|
770 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM);
|
---|
771 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT);
|
---|
772 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM);
|
---|
773 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM);
|
---|
774 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R32_FLOAT);
|
---|
775 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM);
|
---|
776 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_R16_FLOAT);
|
---|
777 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_D16_UNORM);
|
---|
778 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_A8_UNORM);
|
---|
779 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC1_UNORM);
|
---|
780 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC2_UNORM);
|
---|
781 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC3_UNORM);
|
---|
782 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM);
|
---|
783 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM);
|
---|
784 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM);
|
---|
785 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM);
|
---|
786 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC4_UNORM);
|
---|
787 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC5_UNORM);
|
---|
788 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM41);
|
---|
789 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_2X);
|
---|
790 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_4X);
|
---|
791 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MS_FULL_QUALITY);
|
---|
792 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGICOPS);
|
---|
793 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_LOGIC_BLENDOPS);
|
---|
794 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_1);
|
---|
795 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS);
|
---|
796 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_UF16);
|
---|
797 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC6H_SF16);
|
---|
798 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS);
|
---|
799 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM);
|
---|
800 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB);
|
---|
801 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_RESERVED_2);
|
---|
802 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_SM5);
|
---|
803 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MULTISAMPLE_8X);
|
---|
804 |
|
---|
805 | SVGA_CASE_ID2STR(SVGA3D_DEVCAP_MAX);
|
---|
806 |
|
---|
807 | default:
|
---|
808 | break;
|
---|
809 | }
|
---|
810 | return "UNKNOWN";
|
---|
811 | }
|
---|
812 | #endif /* defined(LOG_ENABLED) || (defined(IN_RING3) && defined(VBOX_WITH_VMSVGA3D)) */
|
---|
813 | #undef SVGA_CASE_ID2STR
|
---|
814 |
|
---|
815 |
|
---|
816 | #ifdef IN_RING3
|
---|
817 |
|
---|
818 | /**
|
---|
819 | * @interface_method_impl{PDMIDISPLAYPORT,pfnSetViewport}
|
---|
820 | */
|
---|
821 | DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t idScreen, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
|
---|
822 | {
|
---|
823 | PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
|
---|
824 | PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
|
---|
825 |
|
---|
826 | Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", idScreen, x, y, cx, cy));
|
---|
827 | VMSVGAVIEWPORT const OldViewport = pThis->svga.viewport;
|
---|
828 |
|
---|
829 | /** @todo Test how it interacts with multiple screen objects. */
|
---|
830 | VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, idScreen);
|
---|
831 | uint32_t const uWidth = pScreen ? pScreen->cWidth : 0;
|
---|
832 | uint32_t const uHeight = pScreen ? pScreen->cHeight : 0;
|
---|
833 |
|
---|
834 | if (x < uWidth)
|
---|
835 | {
|
---|
836 | pThis->svga.viewport.x = x;
|
---|
837 | pThis->svga.viewport.cx = RT_MIN(cx, uWidth - x);
|
---|
838 | pThis->svga.viewport.xRight = x + pThis->svga.viewport.cx;
|
---|
839 | }
|
---|
840 | else
|
---|
841 | {
|
---|
842 | pThis->svga.viewport.x = uWidth;
|
---|
843 | pThis->svga.viewport.cx = 0;
|
---|
844 | pThis->svga.viewport.xRight = uWidth;
|
---|
845 | }
|
---|
846 | if (y < uHeight)
|
---|
847 | {
|
---|
848 | pThis->svga.viewport.y = y;
|
---|
849 | pThis->svga.viewport.cy = RT_MIN(cy, uHeight - y);
|
---|
850 | pThis->svga.viewport.yLowWC = uHeight - y - pThis->svga.viewport.cy;
|
---|
851 | pThis->svga.viewport.yHighWC = uHeight - y;
|
---|
852 | }
|
---|
853 | else
|
---|
854 | {
|
---|
855 | pThis->svga.viewport.y = uHeight;
|
---|
856 | pThis->svga.viewport.cy = 0;
|
---|
857 | pThis->svga.viewport.yLowWC = 0;
|
---|
858 | pThis->svga.viewport.yHighWC = 0;
|
---|
859 | }
|
---|
860 |
|
---|
861 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
862 | /*
|
---|
863 | * Now inform the 3D backend.
|
---|
864 | */
|
---|
865 | if (pThis->svga.f3DEnabled)
|
---|
866 | vmsvga3dUpdateHostScreenViewport(pThisCC, idScreen, &OldViewport);
|
---|
867 | # else
|
---|
868 | RT_NOREF(OldViewport);
|
---|
869 | # endif
|
---|
870 | }
|
---|
871 |
|
---|
872 |
|
---|
873 | /**
|
---|
874 | * Updating screen information in API
|
---|
875 | *
|
---|
876 | * @param pThis The The shared VGA/VMSVGA instance data.
|
---|
877 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
878 | */
|
---|
879 | void vmsvgaR3VBVAResize(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
880 | {
|
---|
881 | int rc;
|
---|
882 |
|
---|
883 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
884 |
|
---|
885 | for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
|
---|
886 | {
|
---|
887 | VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[iScreen];
|
---|
888 | if (!pScreen->fModified)
|
---|
889 | continue;
|
---|
890 |
|
---|
891 | pScreen->fModified = false;
|
---|
892 |
|
---|
893 | VBVAINFOVIEW view;
|
---|
894 | RT_ZERO(view);
|
---|
895 | view.u32ViewIndex = pScreen->idScreen;
|
---|
896 | // view.u32ViewOffset = 0;
|
---|
897 | view.u32ViewSize = pThis->vram_size;
|
---|
898 | view.u32MaxScreenSize = pThis->vram_size;
|
---|
899 |
|
---|
900 | VBVAINFOSCREEN screen;
|
---|
901 | RT_ZERO(screen);
|
---|
902 | screen.u32ViewIndex = pScreen->idScreen;
|
---|
903 |
|
---|
904 | if (pScreen->fDefined)
|
---|
905 | {
|
---|
906 | if ( pScreen->cWidth == VMSVGA_VAL_UNINITIALIZED
|
---|
907 | || pScreen->cHeight == VMSVGA_VAL_UNINITIALIZED
|
---|
908 | || pScreen->cBpp == VMSVGA_VAL_UNINITIALIZED)
|
---|
909 | {
|
---|
910 | Assert(pThis->svga.fGFBRegisters);
|
---|
911 | continue;
|
---|
912 | }
|
---|
913 |
|
---|
914 | screen.i32OriginX = pScreen->xOrigin;
|
---|
915 | screen.i32OriginY = pScreen->yOrigin;
|
---|
916 | screen.u32StartOffset = pScreen->offVRAM;
|
---|
917 | screen.u32LineSize = pScreen->cbPitch;
|
---|
918 | screen.u32Width = pScreen->cWidth;
|
---|
919 | screen.u32Height = pScreen->cHeight;
|
---|
920 | screen.u16BitsPerPixel = pScreen->cBpp;
|
---|
921 | if (!(pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE))
|
---|
922 | screen.u16Flags = VBVA_SCREEN_F_ACTIVE;
|
---|
923 | if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
|
---|
924 | screen.u16Flags |= VBVA_SCREEN_F_BLANK2;
|
---|
925 | }
|
---|
926 | else
|
---|
927 | {
|
---|
928 | /* Screen is destroyed. */
|
---|
929 | screen.u16Flags = VBVA_SCREEN_F_DISABLED;
|
---|
930 | }
|
---|
931 |
|
---|
932 | void *pvVRAM = pScreen->pvScreenBitmap ? pScreen->pvScreenBitmap : pThisCC->pbVRam;
|
---|
933 | rc = pThisCC->pDrv->pfnVBVAResize(pThisCC->pDrv, &view, &screen, pvVRAM, /*fResetInputMapping=*/ true);
|
---|
934 | AssertRC(rc);
|
---|
935 | }
|
---|
936 | }
|
---|
937 |
|
---|
938 |
|
---|
939 | /**
|
---|
940 | * @interface_method_impl{PDMIDISPLAYPORT,pfnReportMonitorPositions}
|
---|
941 | *
|
---|
942 | * Used to update screen offsets (positions) since appearently vmwgfx fails to
|
---|
943 | * pass correct offsets thru FIFO.
|
---|
944 | */
|
---|
945 | DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions)
|
---|
946 | {
|
---|
947 | PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
|
---|
948 | PVGASTATE pThis = PDMDEVINS_2_DATA(pThisCC->pDevIns, PVGASTATE);
|
---|
949 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
950 |
|
---|
951 | AssertReturnVoid(pSVGAState);
|
---|
952 |
|
---|
953 | /* We assume cPositions is the # of outputs Xserver reports and paPositions is (-1, -1) for disabled monitors. */
|
---|
954 | cPositions = RT_MIN(cPositions, RT_ELEMENTS(pSVGAState->aScreens));
|
---|
955 | for (uint32_t i = 0; i < cPositions; ++i)
|
---|
956 | {
|
---|
957 | if ( pSVGAState->aScreens[i].xOrigin == paPositions[i].x
|
---|
958 | && pSVGAState->aScreens[i].yOrigin == paPositions[i].y)
|
---|
959 | continue;
|
---|
960 |
|
---|
961 | if (pSVGAState->aScreens[i].xOrigin == -1)
|
---|
962 | continue;
|
---|
963 | if (pSVGAState->aScreens[i].yOrigin == -1)
|
---|
964 | continue;
|
---|
965 |
|
---|
966 | pSVGAState->aScreens[i].xOrigin = paPositions[i].x;
|
---|
967 | pSVGAState->aScreens[i].yOrigin = paPositions[i].y;
|
---|
968 | pSVGAState->aScreens[i].fModified = true;
|
---|
969 | }
|
---|
970 |
|
---|
971 | vmsvgaR3VBVAResize(pThis, pThisCC);
|
---|
972 | }
|
---|
973 |
|
---|
974 | #endif /* IN_RING3 */
|
---|
975 |
|
---|
976 | /**
|
---|
977 | * Read port register
|
---|
978 | *
|
---|
979 | * @returns VBox status code.
|
---|
980 | * @param pDevIns The device instance.
|
---|
981 | * @param pThis The shared VGA/VMSVGA state.
|
---|
982 | * @param pu32 Where to store the read value
|
---|
983 | */
|
---|
984 | static int vmsvgaReadPort(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t *pu32)
|
---|
985 | {
|
---|
986 | #ifdef IN_RING3
|
---|
987 | PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
988 | #endif
|
---|
989 | int rc = VINF_SUCCESS;
|
---|
990 | *pu32 = 0;
|
---|
991 |
|
---|
992 | /* Rough index register validation. */
|
---|
993 | uint32_t idxReg = pThis->svga.u32IndexReg;
|
---|
994 | #if !defined(IN_RING3) && defined(VBOX_STRICT)
|
---|
995 | ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
|
---|
996 | VINF_IOM_R3_IOPORT_READ);
|
---|
997 | #else
|
---|
998 | ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
|
---|
999 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd),
|
---|
1000 | VINF_SUCCESS);
|
---|
1001 | #endif
|
---|
1002 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
1003 |
|
---|
1004 | /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
|
---|
1005 | if ( idxReg >= SVGA_REG_ID_0_TOP
|
---|
1006 | && pThis->svga.u32SVGAId == SVGA_ID_0)
|
---|
1007 | {
|
---|
1008 | idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
|
---|
1009 | Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
|
---|
1010 | }
|
---|
1011 |
|
---|
1012 | switch (idxReg)
|
---|
1013 | {
|
---|
1014 | case SVGA_REG_ID:
|
---|
1015 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdRd);
|
---|
1016 | *pu32 = pThis->svga.u32SVGAId;
|
---|
1017 | break;
|
---|
1018 |
|
---|
1019 | case SVGA_REG_ENABLE:
|
---|
1020 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableRd);
|
---|
1021 | *pu32 = pThis->svga.fEnabled;
|
---|
1022 | break;
|
---|
1023 |
|
---|
1024 | case SVGA_REG_WIDTH:
|
---|
1025 | {
|
---|
1026 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthRd);
|
---|
1027 | if ( pThis->svga.fEnabled
|
---|
1028 | && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)
|
---|
1029 | *pu32 = pThis->svga.uWidth;
|
---|
1030 | else
|
---|
1031 | {
|
---|
1032 | #ifndef IN_RING3
|
---|
1033 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1034 | #else
|
---|
1035 | *pu32 = pThisCC->pDrv->cx;
|
---|
1036 | #endif
|
---|
1037 | }
|
---|
1038 | break;
|
---|
1039 | }
|
---|
1040 |
|
---|
1041 | case SVGA_REG_HEIGHT:
|
---|
1042 | {
|
---|
1043 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightRd);
|
---|
1044 | if ( pThis->svga.fEnabled
|
---|
1045 | && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
|
---|
1046 | *pu32 = pThis->svga.uHeight;
|
---|
1047 | else
|
---|
1048 | {
|
---|
1049 | #ifndef IN_RING3
|
---|
1050 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1051 | #else
|
---|
1052 | *pu32 = pThisCC->pDrv->cy;
|
---|
1053 | #endif
|
---|
1054 | }
|
---|
1055 | break;
|
---|
1056 | }
|
---|
1057 |
|
---|
1058 | case SVGA_REG_MAX_WIDTH:
|
---|
1059 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxWidthRd);
|
---|
1060 | *pu32 = pThis->svga.u32MaxWidth;
|
---|
1061 | break;
|
---|
1062 |
|
---|
1063 | case SVGA_REG_MAX_HEIGHT:
|
---|
1064 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxHeightRd);
|
---|
1065 | *pu32 = pThis->svga.u32MaxHeight;
|
---|
1066 | break;
|
---|
1067 |
|
---|
1068 | case SVGA_REG_DEPTH:
|
---|
1069 | /* This returns the color depth of the current mode. */
|
---|
1070 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthRd);
|
---|
1071 | switch (pThis->svga.uBpp)
|
---|
1072 | {
|
---|
1073 | case 15:
|
---|
1074 | case 16:
|
---|
1075 | case 24:
|
---|
1076 | *pu32 = pThis->svga.uBpp;
|
---|
1077 | break;
|
---|
1078 |
|
---|
1079 | default:
|
---|
1080 | case 32:
|
---|
1081 | *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
|
---|
1082 | break;
|
---|
1083 | }
|
---|
1084 | break;
|
---|
1085 |
|
---|
1086 | case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
|
---|
1087 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegHostBitsPerPixelRd);
|
---|
1088 | *pu32 = pThis->svga.uHostBpp;
|
---|
1089 | break;
|
---|
1090 |
|
---|
1091 | case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
|
---|
1092 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelRd);
|
---|
1093 | *pu32 = pThis->svga.uBpp;
|
---|
1094 | break;
|
---|
1095 |
|
---|
1096 | case SVGA_REG_PSEUDOCOLOR:
|
---|
1097 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPsuedoColorRd);
|
---|
1098 | *pu32 = pThis->svga.uBpp == 8; /* See section 6 "Pseudocolor" in svga_interface.txt. */
|
---|
1099 | break;
|
---|
1100 |
|
---|
1101 | case SVGA_REG_RED_MASK:
|
---|
1102 | case SVGA_REG_GREEN_MASK:
|
---|
1103 | case SVGA_REG_BLUE_MASK:
|
---|
1104 | {
|
---|
1105 | uint32_t uBpp;
|
---|
1106 |
|
---|
1107 | if (pThis->svga.fEnabled)
|
---|
1108 | uBpp = pThis->svga.uBpp;
|
---|
1109 | else
|
---|
1110 | uBpp = pThis->svga.uHostBpp;
|
---|
1111 |
|
---|
1112 | uint32_t u32RedMask, u32GreenMask, u32BlueMask;
|
---|
1113 | switch (uBpp)
|
---|
1114 | {
|
---|
1115 | case 8:
|
---|
1116 | u32RedMask = 0x07;
|
---|
1117 | u32GreenMask = 0x38;
|
---|
1118 | u32BlueMask = 0xc0;
|
---|
1119 | break;
|
---|
1120 |
|
---|
1121 | case 15:
|
---|
1122 | u32RedMask = 0x0000001f;
|
---|
1123 | u32GreenMask = 0x000003e0;
|
---|
1124 | u32BlueMask = 0x00007c00;
|
---|
1125 | break;
|
---|
1126 |
|
---|
1127 | case 16:
|
---|
1128 | u32RedMask = 0x0000001f;
|
---|
1129 | u32GreenMask = 0x000007e0;
|
---|
1130 | u32BlueMask = 0x0000f800;
|
---|
1131 | break;
|
---|
1132 |
|
---|
1133 | case 24:
|
---|
1134 | case 32:
|
---|
1135 | default:
|
---|
1136 | u32RedMask = 0x00ff0000;
|
---|
1137 | u32GreenMask = 0x0000ff00;
|
---|
1138 | u32BlueMask = 0x000000ff;
|
---|
1139 | break;
|
---|
1140 | }
|
---|
1141 | switch (idxReg)
|
---|
1142 | {
|
---|
1143 | case SVGA_REG_RED_MASK:
|
---|
1144 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegRedMaskRd);
|
---|
1145 | *pu32 = u32RedMask;
|
---|
1146 | break;
|
---|
1147 |
|
---|
1148 | case SVGA_REG_GREEN_MASK:
|
---|
1149 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGreenMaskRd);
|
---|
1150 | *pu32 = u32GreenMask;
|
---|
1151 | break;
|
---|
1152 |
|
---|
1153 | case SVGA_REG_BLUE_MASK:
|
---|
1154 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBlueMaskRd);
|
---|
1155 | *pu32 = u32BlueMask;
|
---|
1156 | break;
|
---|
1157 | }
|
---|
1158 | break;
|
---|
1159 | }
|
---|
1160 |
|
---|
1161 | case SVGA_REG_BYTES_PER_LINE:
|
---|
1162 | {
|
---|
1163 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBytesPerLineRd);
|
---|
1164 | if ( pThis->svga.fEnabled
|
---|
1165 | && pThis->svga.cbScanline)
|
---|
1166 | *pu32 = pThis->svga.cbScanline;
|
---|
1167 | else
|
---|
1168 | {
|
---|
1169 | #ifndef IN_RING3
|
---|
1170 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1171 | #else
|
---|
1172 | *pu32 = pThisCC->pDrv->cbScanline;
|
---|
1173 | #endif
|
---|
1174 | }
|
---|
1175 | break;
|
---|
1176 | }
|
---|
1177 |
|
---|
1178 | case SVGA_REG_VRAM_SIZE: /* VRAM size */
|
---|
1179 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegVramSizeRd);
|
---|
1180 | *pu32 = pThis->vram_size;
|
---|
1181 | break;
|
---|
1182 |
|
---|
1183 | case SVGA_REG_FB_START: /* Frame buffer physical address. */
|
---|
1184 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbStartRd);
|
---|
1185 | Assert(pThis->GCPhysVRAM <= 0xffffffff);
|
---|
1186 | *pu32 = pThis->GCPhysVRAM;
|
---|
1187 | break;
|
---|
1188 |
|
---|
1189 | case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
|
---|
1190 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbOffsetRd);
|
---|
1191 | /* Always zero in our case. */
|
---|
1192 | *pu32 = 0;
|
---|
1193 | break;
|
---|
1194 |
|
---|
1195 | case SVGA_REG_FB_SIZE: /* Frame buffer size */
|
---|
1196 | {
|
---|
1197 | #ifndef IN_RING3
|
---|
1198 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1199 | #else
|
---|
1200 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegFbSizeRd);
|
---|
1201 |
|
---|
1202 | /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
|
---|
1203 | if ( pThis->svga.fEnabled
|
---|
1204 | && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
|
---|
1205 | {
|
---|
1206 | /* Hardware enabled; return real framebuffer size .*/
|
---|
1207 | *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
|
---|
1208 | }
|
---|
1209 | else
|
---|
1210 | *pu32 = RT_MAX(0x100000, (uint32_t)pThisCC->pDrv->cy * pThisCC->pDrv->cbScanline);
|
---|
1211 |
|
---|
1212 | *pu32 = RT_MIN(pThis->vram_size, *pu32);
|
---|
1213 | Log(("h=%d w=%d bpp=%d\n", pThisCC->pDrv->cy, pThisCC->pDrv->cx, pThisCC->pDrv->cBits));
|
---|
1214 | #endif
|
---|
1215 | break;
|
---|
1216 | }
|
---|
1217 |
|
---|
1218 | case SVGA_REG_CAPABILITIES:
|
---|
1219 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCapabilitesRd);
|
---|
1220 | *pu32 = pThis->svga.u32DeviceCaps;
|
---|
1221 | break;
|
---|
1222 |
|
---|
1223 | case SVGA_REG_MEM_START: /* FIFO start */
|
---|
1224 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemStartRd);
|
---|
1225 | Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);
|
---|
1226 | *pu32 = pThis->svga.GCPhysFIFO;
|
---|
1227 | break;
|
---|
1228 |
|
---|
1229 | case SVGA_REG_MEM_SIZE: /* FIFO size */
|
---|
1230 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemSizeRd);
|
---|
1231 | *pu32 = pThis->svga.cbFIFO;
|
---|
1232 | break;
|
---|
1233 |
|
---|
1234 | case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
|
---|
1235 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegConfigDoneRd);
|
---|
1236 | *pu32 = pThis->svga.fConfigured;
|
---|
1237 | break;
|
---|
1238 |
|
---|
1239 | case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
|
---|
1240 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncRd);
|
---|
1241 | *pu32 = 0;
|
---|
1242 | break;
|
---|
1243 |
|
---|
1244 | case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
|
---|
1245 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyRd);
|
---|
1246 | if (pThis->svga.fBusy)
|
---|
1247 | {
|
---|
1248 | #ifndef IN_RING3
|
---|
1249 | /* Go to ring-3 and halt the CPU. */
|
---|
1250 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1251 | RT_NOREF(pDevIns);
|
---|
1252 | break;
|
---|
1253 | #else
|
---|
1254 | # if defined(VMSVGA_USE_EMT_HALT_CODE)
|
---|
1255 | /* The guest is basically doing a HLT via the device here, but with
|
---|
1256 | a special wake up condition on FIFO completion. */
|
---|
1257 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
1258 | STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
|
---|
1259 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
1260 | VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pDevIns);
|
---|
1261 | VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
|
---|
1262 | ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
|
---|
1263 | if (pThis->svga.fBusy)
|
---|
1264 | {
|
---|
1265 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
|
---|
1266 | rc = VMR3WaitForDeviceReady(pVM, idCpu);
|
---|
1267 | PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
1268 | }
|
---|
1269 | ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
|
---|
1270 | VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
|
---|
1271 | # else
|
---|
1272 |
|
---|
1273 | /* Delay the EMT a bit so the FIFO and others can get some work done.
|
---|
1274 | This used to be a crude 50 ms sleep. The current code tries to be
|
---|
1275 | more efficient, but the consept is still very crude. */
|
---|
1276 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
1277 | STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
|
---|
1278 | RTThreadYield();
|
---|
1279 | if (pThis->svga.fBusy)
|
---|
1280 | {
|
---|
1281 | uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
|
---|
1282 |
|
---|
1283 | if (pThis->svga.fBusy && cRefs == 1)
|
---|
1284 | RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
|
---|
1285 | if (pThis->svga.fBusy)
|
---|
1286 | {
|
---|
1287 | /** @todo If this code is going to stay, we need to call into the halt/wait
|
---|
1288 | * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
|
---|
1289 | * suffer when the guest is polling on a busy FIFO. */
|
---|
1290 | uint64_t uIgnored1, uIgnored2;
|
---|
1291 | uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pDevIns), &uIgnored1, &uIgnored2);
|
---|
1292 | if (cNsMaxWait >= RT_NS_100US)
|
---|
1293 | RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
|
---|
1294 | RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
|
---|
1295 | RT_MIN(cNsMaxWait, RT_NS_10MS));
|
---|
1296 | }
|
---|
1297 |
|
---|
1298 | ASMAtomicDecU32(&pSVGAState->cBusyDelayedEmts);
|
---|
1299 | }
|
---|
1300 | STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
|
---|
1301 | # endif
|
---|
1302 | *pu32 = pThis->svga.fBusy != 0;
|
---|
1303 | #endif
|
---|
1304 | }
|
---|
1305 | else
|
---|
1306 | *pu32 = false;
|
---|
1307 | break;
|
---|
1308 |
|
---|
1309 | case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
|
---|
1310 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdRd);
|
---|
1311 | *pu32 = pThis->svga.u32GuestId;
|
---|
1312 | break;
|
---|
1313 |
|
---|
1314 | case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
|
---|
1315 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchSizeRd);
|
---|
1316 | *pu32 = pThis->svga.cScratchRegion;
|
---|
1317 | break;
|
---|
1318 |
|
---|
1319 | case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
|
---|
1320 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemRegsRd);
|
---|
1321 | *pu32 = SVGA_FIFO_NUM_REGS;
|
---|
1322 | break;
|
---|
1323 |
|
---|
1324 | case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
|
---|
1325 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockRd);
|
---|
1326 | *pu32 = pThis->svga.u32PitchLock;
|
---|
1327 | break;
|
---|
1328 |
|
---|
1329 | case SVGA_REG_IRQMASK: /* Interrupt mask */
|
---|
1330 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskRd);
|
---|
1331 | *pu32 = pThis->svga.u32IrqMask;
|
---|
1332 | break;
|
---|
1333 |
|
---|
1334 | /* See "Guest memory regions" below. */
|
---|
1335 | case SVGA_REG_GMR_ID:
|
---|
1336 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdRd);
|
---|
1337 | *pu32 = pThis->svga.u32CurrentGMRId;
|
---|
1338 | break;
|
---|
1339 |
|
---|
1340 | case SVGA_REG_GMR_DESCRIPTOR:
|
---|
1341 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegWriteOnlyRd);
|
---|
1342 | /* Write only */
|
---|
1343 | *pu32 = 0;
|
---|
1344 | break;
|
---|
1345 |
|
---|
1346 | case SVGA_REG_GMR_MAX_IDS:
|
---|
1347 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxIdsRd);
|
---|
1348 | *pu32 = pThis->svga.cGMR;
|
---|
1349 | break;
|
---|
1350 |
|
---|
1351 | case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
|
---|
1352 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrMaxDescriptorLengthRd);
|
---|
1353 | *pu32 = VMSVGA_MAX_GMR_PAGES;
|
---|
1354 | break;
|
---|
1355 |
|
---|
1356 | case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
|
---|
1357 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesRd);
|
---|
1358 | *pu32 = pThis->svga.fTraces;
|
---|
1359 | break;
|
---|
1360 |
|
---|
1361 | case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
|
---|
1362 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrsMaxPagesRd);
|
---|
1363 | *pu32 = VMSVGA_MAX_GMR_PAGES;
|
---|
1364 | break;
|
---|
1365 |
|
---|
1366 | case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
|
---|
1367 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMemorySizeRd);
|
---|
1368 | *pu32 = VMSVGA_SURFACE_SIZE;
|
---|
1369 | break;
|
---|
1370 |
|
---|
1371 | case SVGA_REG_TOP: /* Must be 1 more than the last register */
|
---|
1372 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopRd);
|
---|
1373 | break;
|
---|
1374 |
|
---|
1375 | /* Mouse cursor support. */
|
---|
1376 | case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
|
---|
1377 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdRd);
|
---|
1378 | *pu32 = pThis->svga.uCursorID;
|
---|
1379 | break;
|
---|
1380 |
|
---|
1381 | case SVGA_REG_CURSOR_X:
|
---|
1382 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXRd);
|
---|
1383 | *pu32 = pThis->svga.uCursorX;
|
---|
1384 | break;
|
---|
1385 |
|
---|
1386 | case SVGA_REG_CURSOR_Y:
|
---|
1387 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYRd);
|
---|
1388 | *pu32 = pThis->svga.uCursorY;
|
---|
1389 | break;
|
---|
1390 |
|
---|
1391 | case SVGA_REG_CURSOR_ON:
|
---|
1392 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnRd);
|
---|
1393 | *pu32 = pThis->svga.uCursorOn;
|
---|
1394 | break;
|
---|
1395 |
|
---|
1396 | /* Legacy multi-monitor support */
|
---|
1397 | case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
|
---|
1398 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysRd);
|
---|
1399 | *pu32 = 1;
|
---|
1400 | break;
|
---|
1401 |
|
---|
1402 | case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
|
---|
1403 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdRd);
|
---|
1404 | *pu32 = 0;
|
---|
1405 | break;
|
---|
1406 |
|
---|
1407 | case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
|
---|
1408 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryRd);
|
---|
1409 | *pu32 = 0;
|
---|
1410 | break;
|
---|
1411 |
|
---|
1412 | case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
|
---|
1413 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXRd);
|
---|
1414 | *pu32 = 0;
|
---|
1415 | break;
|
---|
1416 |
|
---|
1417 | case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
|
---|
1418 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYRd);
|
---|
1419 | *pu32 = 0;
|
---|
1420 | break;
|
---|
1421 |
|
---|
1422 | case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
|
---|
1423 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthRd);
|
---|
1424 | *pu32 = pThis->svga.uWidth;
|
---|
1425 | break;
|
---|
1426 |
|
---|
1427 | case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
|
---|
1428 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightRd);
|
---|
1429 | *pu32 = pThis->svga.uHeight;
|
---|
1430 | break;
|
---|
1431 |
|
---|
1432 | case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
|
---|
1433 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysRd);
|
---|
1434 | /* We must return something sensible here otherwise the Linux driver
|
---|
1435 | will take a legacy code path without 3d support. This number also
|
---|
1436 | limits how many screens Linux guests will allow. */
|
---|
1437 | *pu32 = pThis->cMonitors;
|
---|
1438 | break;
|
---|
1439 |
|
---|
1440 | /*
|
---|
1441 | * SVGA_CAP_GBOBJECTS+ registers.
|
---|
1442 | */
|
---|
1443 | case SVGA_REG_COMMAND_LOW:
|
---|
1444 | /* Lower 32 bits of command buffer physical address. */
|
---|
1445 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowRd);
|
---|
1446 | *pu32 = pThis->svga.u32RegCommandLow;
|
---|
1447 | break;
|
---|
1448 |
|
---|
1449 | case SVGA_REG_COMMAND_HIGH:
|
---|
1450 | /* Upper 32 bits of command buffer PA. */
|
---|
1451 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighRd);
|
---|
1452 | *pu32 = pThis->svga.u32RegCommandHigh;
|
---|
1453 | break;
|
---|
1454 |
|
---|
1455 | case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
|
---|
1456 | /* Max primary (screen) memory. */
|
---|
1457 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMaxPrimBBMemRd);
|
---|
1458 | *pu32 = pThis->vram_size; /** @todo Maybe half VRAM? */
|
---|
1459 | break;
|
---|
1460 |
|
---|
1461 | case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
|
---|
1462 | /* Suggested limit on mob mem (i.e. size of the guest mapped VRAM in KB) */
|
---|
1463 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGBMemSizeRd);
|
---|
1464 | *pu32 = pThis->vram_size / 1024;
|
---|
1465 | break;
|
---|
1466 |
|
---|
1467 | case SVGA_REG_DEV_CAP:
|
---|
1468 | /* Write dev cap index, read value */
|
---|
1469 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapRd);
|
---|
1470 | if (pThis->svga.u32DevCapIndex < RT_ELEMENTS(pThis->svga.au32DevCaps))
|
---|
1471 | {
|
---|
1472 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
1473 | *pu32 = pThis->svga.au32DevCaps[pThis->svga.u32DevCapIndex];
|
---|
1474 | }
|
---|
1475 | else
|
---|
1476 | *pu32 = 0;
|
---|
1477 | break;
|
---|
1478 |
|
---|
1479 | case SVGA_REG_CMD_PREPEND_LOW:
|
---|
1480 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowRd);
|
---|
1481 | *pu32 = 0; /* Not supported. */
|
---|
1482 | break;
|
---|
1483 |
|
---|
1484 | case SVGA_REG_CMD_PREPEND_HIGH:
|
---|
1485 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighRd);
|
---|
1486 | *pu32 = 0; /* Not supported. */
|
---|
1487 | break;
|
---|
1488 |
|
---|
1489 | case SVGA_REG_SCREENTARGET_MAX_WIDTH:
|
---|
1490 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxWidthRd);
|
---|
1491 | *pu32 = pThis->svga.u32MaxWidth;
|
---|
1492 | break;
|
---|
1493 |
|
---|
1494 | case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
|
---|
1495 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegScrnTgtMaxHeightRd);
|
---|
1496 | *pu32 = pThis->svga.u32MaxHeight;
|
---|
1497 | break;
|
---|
1498 |
|
---|
1499 | case SVGA_REG_MOB_MAX_SIZE:
|
---|
1500 | /* Essentially the max texture size */
|
---|
1501 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegMobMaxSizeRd);
|
---|
1502 | *pu32 = _128M; /** @todo Some actual value. Probably the mapped VRAM size. */
|
---|
1503 | break;
|
---|
1504 |
|
---|
1505 | default:
|
---|
1506 | {
|
---|
1507 | uint32_t offReg;
|
---|
1508 | if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
|
---|
1509 | {
|
---|
1510 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchRd);
|
---|
1511 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
1512 | *pu32 = pThis->svga.au32ScratchRegion[offReg];
|
---|
1513 | }
|
---|
1514 | else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
|
---|
1515 | {
|
---|
1516 | /* Note! Using last_palette rather than palette here to preserve the VGA one. */
|
---|
1517 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteRd);
|
---|
1518 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
1519 | uint32_t u32 = pThis->last_palette[offReg / 3];
|
---|
1520 | switch (offReg % 3)
|
---|
1521 | {
|
---|
1522 | case 0: *pu32 = (u32 >> 16) & 0xff; break; /* red */
|
---|
1523 | case 1: *pu32 = (u32 >> 8) & 0xff; break; /* green */
|
---|
1524 | case 2: *pu32 = u32 & 0xff; break; /* blue */
|
---|
1525 | }
|
---|
1526 | }
|
---|
1527 | else
|
---|
1528 | {
|
---|
1529 | #if !defined(IN_RING3) && defined(VBOX_STRICT)
|
---|
1530 | rc = VINF_IOM_R3_IOPORT_READ;
|
---|
1531 | #else
|
---|
1532 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownRd);
|
---|
1533 |
|
---|
1534 | /* Do not assert. The guest might be reading all registers. */
|
---|
1535 | LogFunc(("Unknown reg=%#x\n", idxReg));
|
---|
1536 | #endif
|
---|
1537 | }
|
---|
1538 | break;
|
---|
1539 | }
|
---|
1540 | }
|
---|
1541 | Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, *pu32, rc));
|
---|
1542 | return rc;
|
---|
1543 | }
|
---|
1544 |
|
---|
1545 | #ifdef IN_RING3
|
---|
1546 | /**
|
---|
1547 | * Apply the current resolution settings to change the video mode.
|
---|
1548 | *
|
---|
1549 | * @returns VBox status code.
|
---|
1550 | * @param pThis The shared VGA state.
|
---|
1551 | * @param pThisCC The ring-3 VGA state.
|
---|
1552 | */
|
---|
1553 | int vmsvgaR3ChangeMode(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
1554 | {
|
---|
1555 | /* Always do changemode on FIFO thread. */
|
---|
1556 | Assert(RTThreadSelf() == pThisCC->svga.pFIFOIOThread->Thread);
|
---|
1557 |
|
---|
1558 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
1559 |
|
---|
1560 | pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, true);
|
---|
1561 |
|
---|
1562 | if (pThis->svga.fGFBRegisters)
|
---|
1563 | {
|
---|
1564 | /* "For backwards compatibility, when the GFB mode registers (WIDTH,
|
---|
1565 | * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
|
---|
1566 | * deletes all screens other than screen #0, and redefines screen
|
---|
1567 | * #0 according to the specified mode. Drivers that use
|
---|
1568 | * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0."
|
---|
1569 | */
|
---|
1570 |
|
---|
1571 | VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
|
---|
1572 | pScreen->fDefined = true;
|
---|
1573 | pScreen->fModified = true;
|
---|
1574 | pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET | SVGA_SCREEN_IS_PRIMARY;
|
---|
1575 | pScreen->idScreen = 0;
|
---|
1576 | pScreen->xOrigin = 0;
|
---|
1577 | pScreen->yOrigin = 0;
|
---|
1578 | pScreen->offVRAM = 0;
|
---|
1579 | pScreen->cbPitch = pThis->svga.cbScanline;
|
---|
1580 | pScreen->cWidth = pThis->svga.uWidth;
|
---|
1581 | pScreen->cHeight = pThis->svga.uHeight;
|
---|
1582 | pScreen->cBpp = pThis->svga.uBpp;
|
---|
1583 |
|
---|
1584 | for (unsigned iScreen = 1; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
|
---|
1585 | {
|
---|
1586 | /* Delete screen. */
|
---|
1587 | pScreen = &pSVGAState->aScreens[iScreen];
|
---|
1588 | if (pScreen->fDefined)
|
---|
1589 | {
|
---|
1590 | pScreen->fModified = true;
|
---|
1591 | pScreen->fDefined = false;
|
---|
1592 | }
|
---|
1593 | }
|
---|
1594 | }
|
---|
1595 | else
|
---|
1596 | {
|
---|
1597 | /* "If Screen Objects are supported, they can be used to fully
|
---|
1598 | * replace the functionality provided by the framebuffer registers
|
---|
1599 | * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY."
|
---|
1600 | */
|
---|
1601 | pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
|
---|
1602 | pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
|
---|
1603 | pThis->svga.uBpp = pThis->svga.uHostBpp;
|
---|
1604 | }
|
---|
1605 |
|
---|
1606 | vmsvgaR3VBVAResize(pThis, pThisCC);
|
---|
1607 |
|
---|
1608 | /* Last stuff. For the VGA device screenshot. */
|
---|
1609 | pThis->last_bpp = pSVGAState->aScreens[0].cBpp;
|
---|
1610 | pThis->last_scr_width = pSVGAState->aScreens[0].cWidth;
|
---|
1611 | pThis->last_scr_height = pSVGAState->aScreens[0].cHeight;
|
---|
1612 | pThis->last_width = pSVGAState->aScreens[0].cWidth;
|
---|
1613 | pThis->last_height = pSVGAState->aScreens[0].cHeight;
|
---|
1614 |
|
---|
1615 | /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
|
---|
1616 | if ( pThis->svga.viewport.cx == 0
|
---|
1617 | && pThis->svga.viewport.cy == 0)
|
---|
1618 | {
|
---|
1619 | pThis->svga.viewport.cx = pSVGAState->aScreens[0].cWidth;
|
---|
1620 | pThis->svga.viewport.xRight = pSVGAState->aScreens[0].cWidth;
|
---|
1621 | pThis->svga.viewport.cy = pSVGAState->aScreens[0].cHeight;
|
---|
1622 | pThis->svga.viewport.yHighWC = pSVGAState->aScreens[0].cHeight;
|
---|
1623 | pThis->svga.viewport.yLowWC = 0;
|
---|
1624 | }
|
---|
1625 |
|
---|
1626 | return VINF_SUCCESS;
|
---|
1627 | }
|
---|
1628 |
|
---|
1629 | int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h)
|
---|
1630 | {
|
---|
1631 | VBVACMDHDR cmd;
|
---|
1632 | cmd.x = (int16_t)(pScreen->xOrigin + x);
|
---|
1633 | cmd.y = (int16_t)(pScreen->yOrigin + y);
|
---|
1634 | cmd.w = (uint16_t)w;
|
---|
1635 | cmd.h = (uint16_t)h;
|
---|
1636 |
|
---|
1637 | pThisCC->pDrv->pfnVBVAUpdateBegin(pThisCC->pDrv, pScreen->idScreen);
|
---|
1638 | pThisCC->pDrv->pfnVBVAUpdateProcess(pThisCC->pDrv, pScreen->idScreen, &cmd, sizeof(cmd));
|
---|
1639 | pThisCC->pDrv->pfnVBVAUpdateEnd(pThisCC->pDrv, pScreen->idScreen,
|
---|
1640 | pScreen->xOrigin + x, pScreen->yOrigin + y, w, h);
|
---|
1641 |
|
---|
1642 | return VINF_SUCCESS;
|
---|
1643 | }
|
---|
1644 |
|
---|
1645 | #endif /* IN_RING3 */
|
---|
1646 | #if defined(IN_RING0) || defined(IN_RING3)
|
---|
1647 |
|
---|
1648 | /**
|
---|
1649 | * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
|
---|
1650 | *
|
---|
1651 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
1652 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
1653 | * @param fState The busy state.
|
---|
1654 | */
|
---|
1655 | DECLINLINE(void) vmsvgaHCSafeFifoBusyRegUpdate(PVGASTATE pThis, PVGASTATECC pThisCC, bool fState)
|
---|
1656 | {
|
---|
1657 | ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState);
|
---|
1658 |
|
---|
1659 | if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
|
---|
1660 | {
|
---|
1661 | /* Race / unfortunately scheduling. Highly unlikly. */
|
---|
1662 | uint32_t cLoops = 64;
|
---|
1663 | do
|
---|
1664 | {
|
---|
1665 | ASMNopPause();
|
---|
1666 | fState = (pThis->svga.fBusy != 0);
|
---|
1667 | ASMAtomicWriteU32(&pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY], fState != 0);
|
---|
1668 | } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
|
---|
1669 | }
|
---|
1670 | }
|
---|
1671 |
|
---|
1672 |
|
---|
1673 | /**
|
---|
1674 | * Update the scanline pitch in response to the guest changing mode
|
---|
1675 | * width/bpp.
|
---|
1676 | *
|
---|
1677 | * @param pThis The shared VGA/VMSVGA state.
|
---|
1678 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
1679 | */
|
---|
1680 | DECLINLINE(void) vmsvgaHCUpdatePitch(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
1681 | {
|
---|
1682 | uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
|
---|
1683 | uint32_t uFifoPitchLock = pFIFO[SVGA_FIFO_PITCHLOCK];
|
---|
1684 | uint32_t uRegPitchLock = pThis->svga.u32PitchLock;
|
---|
1685 | uint32_t uFifoMin = pFIFO[SVGA_FIFO_MIN];
|
---|
1686 |
|
---|
1687 | /* The SVGA_FIFO_PITCHLOCK register is only valid if SVGA_FIFO_MIN points past
|
---|
1688 | * it. If SVGA_FIFO_MIN is small, there may well be data at the SVGA_FIFO_PITCHLOCK
|
---|
1689 | * location but it has a different meaning.
|
---|
1690 | */
|
---|
1691 | if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
|
---|
1692 | uFifoPitchLock = 0;
|
---|
1693 |
|
---|
1694 | /* Sanitize values. */
|
---|
1695 | if ((uFifoPitchLock < 200) || (uFifoPitchLock > 32768))
|
---|
1696 | uFifoPitchLock = 0;
|
---|
1697 | if ((uRegPitchLock < 200) || (uRegPitchLock > 32768))
|
---|
1698 | uRegPitchLock = 0;
|
---|
1699 |
|
---|
1700 | /* Prefer the register value to the FIFO value.*/
|
---|
1701 | if (uRegPitchLock)
|
---|
1702 | pThis->svga.cbScanline = uRegPitchLock;
|
---|
1703 | else if (uFifoPitchLock)
|
---|
1704 | pThis->svga.cbScanline = uFifoPitchLock;
|
---|
1705 | else
|
---|
1706 | pThis->svga.cbScanline = (uint32_t)pThis->svga.uWidth * (RT_ALIGN(pThis->svga.uBpp, 8) / 8);
|
---|
1707 |
|
---|
1708 | if ((uFifoMin / sizeof(uint32_t)) <= SVGA_FIFO_PITCHLOCK)
|
---|
1709 | pThis->svga.u32PitchLock = pThis->svga.cbScanline;
|
---|
1710 | }
|
---|
1711 |
|
---|
1712 | #endif /* IN_RING0 || IN_RING3 */
|
---|
1713 |
|
---|
1714 | #ifdef IN_RING3
|
---|
1715 |
|
---|
1716 | /**
|
---|
1717 | * Sends cursor position and visibility information from legacy
|
---|
1718 | * SVGA registers to the front-end.
|
---|
1719 | */
|
---|
1720 | static void vmsvgaR3RegUpdateCursor(PVGASTATECC pThisCC, PVGASTATE pThis, uint32_t uCursorOn)
|
---|
1721 | {
|
---|
1722 | /*
|
---|
1723 | * Writing the X/Y/ID registers does not trigger changes; only writing the
|
---|
1724 | * SVGA_REG_CURSOR_ON register does. That minimizes the overhead.
|
---|
1725 | * We boldly assume that guests aren't stupid and aren't writing the CURSOR_ON
|
---|
1726 | * register if they don't have to.
|
---|
1727 | */
|
---|
1728 | uint32_t x, y, idScreen;
|
---|
1729 | uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
|
---|
1730 |
|
---|
1731 | x = pThis->svga.uCursorX;
|
---|
1732 | y = pThis->svga.uCursorY;
|
---|
1733 | idScreen = SVGA_ID_INVALID; /* The old register interface is single screen only. */
|
---|
1734 |
|
---|
1735 | /* The original values for SVGA_REG_CURSOR_ON were off (0) and on (1); later, the values
|
---|
1736 | * were extended as follows:
|
---|
1737 | *
|
---|
1738 | * SVGA_CURSOR_ON_HIDE 0
|
---|
1739 | * SVGA_CURSOR_ON_SHOW 1
|
---|
1740 | * SVGA_CURSOR_ON_REMOVE_FROM_FB 2 - cursor on but not in the framebuffer
|
---|
1741 | * SVGA_CURSOR_ON_RESTORE_TO_FB 3 - cursor on, possibly in the framebuffer
|
---|
1742 | *
|
---|
1743 | * Since we never draw the cursor into the guest's framebuffer, we do not need to
|
---|
1744 | * distinguish between the non-zero values but still remember them.
|
---|
1745 | */
|
---|
1746 | if (RT_BOOL(pThis->svga.uCursorOn) != RT_BOOL(uCursorOn))
|
---|
1747 | {
|
---|
1748 | LogRel2(("vmsvgaR3RegUpdateCursor: uCursorOn %d prev CursorOn %d (%d,%d)\n", uCursorOn, pThis->svga.uCursorOn, x, y));
|
---|
1749 | pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(uCursorOn), false, 0, 0, 0, 0, NULL);
|
---|
1750 | }
|
---|
1751 | pThis->svga.uCursorOn = uCursorOn;
|
---|
1752 | pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
|
---|
1753 | }
|
---|
1754 |
|
---|
1755 | #endif /* IN_RING3 */
|
---|
1756 |
|
---|
1757 |
|
---|
1758 | /**
|
---|
1759 | * Write port register
|
---|
1760 | *
|
---|
1761 | * @returns Strict VBox status code.
|
---|
1762 | * @param pDevIns The device instance.
|
---|
1763 | * @param pThis The shared VGA/VMSVGA state.
|
---|
1764 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
1765 | * @param u32 Value to write
|
---|
1766 | */
|
---|
1767 | static VBOXSTRICTRC vmsvgaWritePort(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32)
|
---|
1768 | {
|
---|
1769 | #ifdef IN_RING3
|
---|
1770 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
1771 | #endif
|
---|
1772 | VBOXSTRICTRC rc = VINF_SUCCESS;
|
---|
1773 | RT_NOREF(pThisCC);
|
---|
1774 |
|
---|
1775 | /* Rough index register validation. */
|
---|
1776 | uint32_t idxReg = pThis->svga.u32IndexReg;
|
---|
1777 | #if !defined(IN_RING3) && defined(VBOX_STRICT)
|
---|
1778 | ASSERT_GUEST_MSG_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
|
---|
1779 | VINF_IOM_R3_IOPORT_WRITE);
|
---|
1780 | #else
|
---|
1781 | ASSERT_GUEST_MSG_STMT_RETURN(idxReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion, ("idxReg=%#x\n", idxReg),
|
---|
1782 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr),
|
---|
1783 | VINF_SUCCESS);
|
---|
1784 | #endif
|
---|
1785 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
1786 |
|
---|
1787 | /* We must adjust the register number if we're in SVGA_ID_0 mode because the PALETTE range moved. */
|
---|
1788 | if ( idxReg >= SVGA_REG_ID_0_TOP
|
---|
1789 | && pThis->svga.u32SVGAId == SVGA_ID_0)
|
---|
1790 | {
|
---|
1791 | idxReg += SVGA_PALETTE_BASE - SVGA_REG_ID_0_TOP;
|
---|
1792 | Log(("vmsvgaWritePort: SVGA_ID_0 reg adj %#x -> %#x\n", pThis->svga.u32IndexReg, idxReg));
|
---|
1793 | }
|
---|
1794 | #ifdef LOG_ENABLED
|
---|
1795 | if (idxReg != SVGA_REG_DEV_CAP)
|
---|
1796 | Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis, idxReg), idxReg, u32));
|
---|
1797 | else
|
---|
1798 | Log(("vmsvgaWritePort index=%s (%d) val=%s (%d)\n", vmsvgaIndexToString(pThis, idxReg), idxReg, vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)u32), u32));
|
---|
1799 | #endif
|
---|
1800 | /* Check if the guest uses legacy registers. See vmsvgaR3ChangeMode */
|
---|
1801 | switch (idxReg)
|
---|
1802 | {
|
---|
1803 | case SVGA_REG_WIDTH:
|
---|
1804 | case SVGA_REG_HEIGHT:
|
---|
1805 | case SVGA_REG_PITCHLOCK:
|
---|
1806 | case SVGA_REG_BITS_PER_PIXEL:
|
---|
1807 | pThis->svga.fGFBRegisters = true;
|
---|
1808 | break;
|
---|
1809 | default:
|
---|
1810 | break;
|
---|
1811 | }
|
---|
1812 |
|
---|
1813 | switch (idxReg)
|
---|
1814 | {
|
---|
1815 | case SVGA_REG_ID:
|
---|
1816 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegIdWr);
|
---|
1817 | if ( u32 == SVGA_ID_0
|
---|
1818 | || u32 == SVGA_ID_1
|
---|
1819 | || u32 == SVGA_ID_2)
|
---|
1820 | pThis->svga.u32SVGAId = u32;
|
---|
1821 | else
|
---|
1822 | PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Trying to set SVGA_REG_ID to %#x (%d)\n", u32, u32);
|
---|
1823 | break;
|
---|
1824 |
|
---|
1825 | case SVGA_REG_ENABLE:
|
---|
1826 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegEnableWr);
|
---|
1827 | #ifdef IN_RING3
|
---|
1828 | if ( (u32 & SVGA_REG_ENABLE_ENABLE)
|
---|
1829 | && pThis->svga.fEnabled == false)
|
---|
1830 | {
|
---|
1831 | /* Make a backup copy of the first 512kb in order to save font data etc. */
|
---|
1832 | /** @todo should probably swap here, rather than copy + zero */
|
---|
1833 | memcpy(pThisCC->svga.pbVgaFrameBufferR3, pThisCC->pbVRam, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
1834 | memset(pThisCC->pbVRam, 0, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
1835 | }
|
---|
1836 |
|
---|
1837 | pThis->svga.fEnabled = u32;
|
---|
1838 | if (pThis->svga.fEnabled)
|
---|
1839 | {
|
---|
1840 | if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
|
---|
1841 | && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED)
|
---|
1842 | {
|
---|
1843 | /* Keep the current mode. */
|
---|
1844 | pThis->svga.uWidth = pThisCC->pDrv->cx;
|
---|
1845 | pThis->svga.uHeight = pThisCC->pDrv->cy;
|
---|
1846 | pThis->svga.uBpp = (pThisCC->pDrv->cBits + 7) & ~7;
|
---|
1847 | }
|
---|
1848 |
|
---|
1849 | if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
|
---|
1850 | && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
|
---|
1851 | ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
|
---|
1852 | # ifdef LOG_ENABLED
|
---|
1853 | uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
|
---|
1854 | Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
|
---|
1855 | Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
|
---|
1856 | # endif
|
---|
1857 |
|
---|
1858 | /* Disable or enable dirty page tracking according to the current fTraces value. */
|
---|
1859 | vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
|
---|
1860 |
|
---|
1861 | /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
|
---|
1862 | for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
|
---|
1863 | pThisCC->pDrv->pfnVBVAEnable(pThisCC->pDrv, idScreen, NULL /*pHostFlags*/);
|
---|
1864 |
|
---|
1865 | /* Make the cursor visible again as needed. */
|
---|
1866 | if (pSVGAState->Cursor.fActive)
|
---|
1867 | pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, true /*fVisible*/, false, 0, 0, 0, 0, NULL);
|
---|
1868 | }
|
---|
1869 | else
|
---|
1870 | {
|
---|
1871 | /* Make sure the cursor is off. */
|
---|
1872 | if (pSVGAState->Cursor.fActive)
|
---|
1873 | pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false /*fVisible*/, false, 0, 0, 0, 0, NULL);
|
---|
1874 |
|
---|
1875 | /* Restore the text mode backup. */
|
---|
1876 | memcpy(pThisCC->pbVRam, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
1877 |
|
---|
1878 | pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, false);
|
---|
1879 |
|
---|
1880 | /* Enable dirty page tracking again when going into legacy mode. */
|
---|
1881 | vmsvgaR3SetTraces(pDevIns, pThis, true);
|
---|
1882 |
|
---|
1883 | /* bird: Whatever this is was added to make screenshot work, ask sunlover should explain... */
|
---|
1884 | for (uint32_t idScreen = 0; idScreen < pThis->cMonitors; ++idScreen)
|
---|
1885 | pThisCC->pDrv->pfnVBVADisable(pThisCC->pDrv, idScreen);
|
---|
1886 |
|
---|
1887 | /* Clear the pitch lock. */
|
---|
1888 | pThis->svga.u32PitchLock = 0;
|
---|
1889 | }
|
---|
1890 | #else /* !IN_RING3 */
|
---|
1891 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
1892 | #endif /* !IN_RING3 */
|
---|
1893 | break;
|
---|
1894 |
|
---|
1895 | case SVGA_REG_WIDTH:
|
---|
1896 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegWidthWr);
|
---|
1897 | if (u32 != pThis->svga.uWidth)
|
---|
1898 | {
|
---|
1899 | if (u32 <= pThis->svga.u32MaxWidth)
|
---|
1900 | {
|
---|
1901 | #if defined(IN_RING3) || defined(IN_RING0)
|
---|
1902 | pThis->svga.uWidth = u32;
|
---|
1903 | vmsvgaHCUpdatePitch(pThis, pThisCC);
|
---|
1904 | if (pThis->svga.fEnabled)
|
---|
1905 | ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
|
---|
1906 | #else
|
---|
1907 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
1908 | #endif
|
---|
1909 | }
|
---|
1910 | else
|
---|
1911 | Log(("SVGA_REG_WIDTH: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxWidth));
|
---|
1912 | }
|
---|
1913 | /* else: nop */
|
---|
1914 | break;
|
---|
1915 |
|
---|
1916 | case SVGA_REG_HEIGHT:
|
---|
1917 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegHeightWr);
|
---|
1918 | if (u32 != pThis->svga.uHeight)
|
---|
1919 | {
|
---|
1920 | if (u32 <= pThis->svga.u32MaxHeight)
|
---|
1921 | {
|
---|
1922 | pThis->svga.uHeight = u32;
|
---|
1923 | if (pThis->svga.fEnabled)
|
---|
1924 | ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
|
---|
1925 | }
|
---|
1926 | else
|
---|
1927 | Log(("SVGA_REG_HEIGHT: New value is out of bounds: %u, max %u\n", u32, pThis->svga.u32MaxHeight));
|
---|
1928 | }
|
---|
1929 | /* else: nop */
|
---|
1930 | break;
|
---|
1931 |
|
---|
1932 | case SVGA_REG_DEPTH:
|
---|
1933 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDepthWr);
|
---|
1934 | /** @todo read-only?? */
|
---|
1935 | break;
|
---|
1936 |
|
---|
1937 | case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
|
---|
1938 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBitsPerPixelWr);
|
---|
1939 | if (pThis->svga.uBpp != u32)
|
---|
1940 | {
|
---|
1941 | if (u32 <= 32)
|
---|
1942 | {
|
---|
1943 | #if defined(IN_RING3) || defined(IN_RING0)
|
---|
1944 | pThis->svga.uBpp = u32;
|
---|
1945 | vmsvgaHCUpdatePitch(pThis, pThisCC);
|
---|
1946 | if (pThis->svga.fEnabled)
|
---|
1947 | ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
|
---|
1948 | #else
|
---|
1949 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
1950 | #endif
|
---|
1951 | }
|
---|
1952 | else
|
---|
1953 | Log(("SVGA_REG_BITS_PER_PIXEL: New value is out of bounds: %u, max 32\n", u32));
|
---|
1954 | }
|
---|
1955 | /* else: nop */
|
---|
1956 | break;
|
---|
1957 |
|
---|
1958 | case SVGA_REG_PSEUDOCOLOR:
|
---|
1959 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPseudoColorWr);
|
---|
1960 | break;
|
---|
1961 |
|
---|
1962 | case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
|
---|
1963 | #ifdef IN_RING3
|
---|
1964 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegConfigDoneWr);
|
---|
1965 | pThis->svga.fConfigured = u32;
|
---|
1966 | /* Disabling the FIFO enables tracing (dirty page detection) by default. */
|
---|
1967 | if (!pThis->svga.fConfigured)
|
---|
1968 | pThis->svga.fTraces = true;
|
---|
1969 | vmsvgaR3SetTraces(pDevIns, pThis, !!pThis->svga.fTraces);
|
---|
1970 | #else
|
---|
1971 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
1972 | #endif
|
---|
1973 | break;
|
---|
1974 |
|
---|
1975 | case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
|
---|
1976 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegSyncWr);
|
---|
1977 | if ( pThis->svga.fEnabled
|
---|
1978 | && pThis->svga.fConfigured)
|
---|
1979 | {
|
---|
1980 | #if defined(IN_RING3) || defined(IN_RING0)
|
---|
1981 | Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThisCC->svga.pau32FIFO[SVGA_FIFO_BUSY]));
|
---|
1982 | /*
|
---|
1983 | * The VMSVGA_BUSY_F_EMT_FORCE flag makes sure we will check if the FIFO is empty
|
---|
1984 | * at least once; VMSVGA_BUSY_F_FIFO alone does not ensure that.
|
---|
1985 | */
|
---|
1986 | ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
|
---|
1987 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThisCC->svga.pau32FIFO[SVGA_FIFO_MIN]))
|
---|
1988 | vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, true);
|
---|
1989 |
|
---|
1990 | /* Kick the FIFO thread to start processing commands again. */
|
---|
1991 | PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
1992 | #else
|
---|
1993 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
1994 | #endif
|
---|
1995 | }
|
---|
1996 | /* else nothing to do. */
|
---|
1997 | else
|
---|
1998 | Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
|
---|
1999 |
|
---|
2000 | break;
|
---|
2001 |
|
---|
2002 | case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
|
---|
2003 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegBusyWr);
|
---|
2004 | break;
|
---|
2005 |
|
---|
2006 | case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
|
---|
2007 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGuestIdWr);
|
---|
2008 | pThis->svga.u32GuestId = u32;
|
---|
2009 | break;
|
---|
2010 |
|
---|
2011 | case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
|
---|
2012 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPitchLockWr);
|
---|
2013 | pThis->svga.u32PitchLock = u32;
|
---|
2014 | /* Should this also update the FIFO pitch lock? Unclear. */
|
---|
2015 | break;
|
---|
2016 |
|
---|
2017 | case SVGA_REG_IRQMASK: /* Interrupt mask */
|
---|
2018 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegIrqMaskWr);
|
---|
2019 | pThis->svga.u32IrqMask = u32;
|
---|
2020 |
|
---|
2021 | /* Irq pending after the above change? */
|
---|
2022 | if (pThis->svga.u32IrqStatus & u32)
|
---|
2023 | {
|
---|
2024 | Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
|
---|
2025 | PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
|
---|
2026 | }
|
---|
2027 | else
|
---|
2028 | PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
|
---|
2029 | break;
|
---|
2030 |
|
---|
2031 | /* Mouse cursor support */
|
---|
2032 | case SVGA_REG_DEAD: /* SVGA_REG_CURSOR_ID */
|
---|
2033 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorIdWr);
|
---|
2034 | pThis->svga.uCursorID = u32;
|
---|
2035 | break;
|
---|
2036 |
|
---|
2037 | case SVGA_REG_CURSOR_X:
|
---|
2038 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorXWr);
|
---|
2039 | pThis->svga.uCursorX = u32;
|
---|
2040 | break;
|
---|
2041 |
|
---|
2042 | case SVGA_REG_CURSOR_Y:
|
---|
2043 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorYWr);
|
---|
2044 | pThis->svga.uCursorY = u32;
|
---|
2045 | break;
|
---|
2046 |
|
---|
2047 | case SVGA_REG_CURSOR_ON:
|
---|
2048 | #ifdef IN_RING3
|
---|
2049 | /* The cursor is only updated when SVGA_REG_CURSOR_ON is written. */
|
---|
2050 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCursorOnWr);
|
---|
2051 | vmsvgaR3RegUpdateCursor(pThisCC, pThis, u32);
|
---|
2052 | #else
|
---|
2053 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2054 | #endif
|
---|
2055 | break;
|
---|
2056 |
|
---|
2057 | /* Legacy multi-monitor support */
|
---|
2058 | case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
|
---|
2059 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumGuestDisplaysWr);
|
---|
2060 | break;
|
---|
2061 | case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
|
---|
2062 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIdWr);
|
---|
2063 | break;
|
---|
2064 | case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
|
---|
2065 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayIsPrimaryWr);
|
---|
2066 | break;
|
---|
2067 | case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
|
---|
2068 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionXWr);
|
---|
2069 | break;
|
---|
2070 | case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
|
---|
2071 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayPositionYWr);
|
---|
2072 | break;
|
---|
2073 | case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
|
---|
2074 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayWidthWr);
|
---|
2075 | break;
|
---|
2076 | case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
|
---|
2077 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDisplayHeightWr);
|
---|
2078 | break;
|
---|
2079 | #ifdef VBOX_WITH_VMSVGA3D
|
---|
2080 | /* See "Guest memory regions" below. */
|
---|
2081 | case SVGA_REG_GMR_ID:
|
---|
2082 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegGmrIdWr);
|
---|
2083 | pThis->svga.u32CurrentGMRId = u32;
|
---|
2084 | break;
|
---|
2085 |
|
---|
2086 | case SVGA_REG_GMR_DESCRIPTOR:
|
---|
2087 | # ifndef IN_RING3
|
---|
2088 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2089 | break;
|
---|
2090 | # else /* IN_RING3 */
|
---|
2091 | {
|
---|
2092 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWr);
|
---|
2093 |
|
---|
2094 | /* Validate current GMR id. */
|
---|
2095 | uint32_t idGMR = pThis->svga.u32CurrentGMRId;
|
---|
2096 | AssertBreak(idGMR < pThis->svga.cGMR);
|
---|
2097 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
2098 |
|
---|
2099 | /* Free the old GMR if present. */
|
---|
2100 | vmsvgaR3GmrFree(pThisCC, idGMR);
|
---|
2101 |
|
---|
2102 | /* Just undefine the GMR? */
|
---|
2103 | RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;
|
---|
2104 | if (GCPhys == 0)
|
---|
2105 | {
|
---|
2106 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrFree);
|
---|
2107 | break;
|
---|
2108 | }
|
---|
2109 |
|
---|
2110 |
|
---|
2111 | /* Never cross a page boundary automatically. */
|
---|
2112 | const uint32_t cMaxPages = RT_MIN(VMSVGA_MAX_GMR_PAGES, UINT32_MAX / X86_PAGE_SIZE);
|
---|
2113 | uint32_t cPagesTotal = 0;
|
---|
2114 | uint32_t iDesc = 0;
|
---|
2115 | PVMSVGAGMRDESCRIPTOR paDescs = NULL;
|
---|
2116 | uint32_t cLoops = 0;
|
---|
2117 | RTGCPHYS GCPhysBase = GCPhys;
|
---|
2118 | while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
|
---|
2119 | {
|
---|
2120 | /* Read descriptor. */
|
---|
2121 | SVGAGuestMemDescriptor desc;
|
---|
2122 | rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &desc, sizeof(desc));
|
---|
2123 | AssertRCBreak(VBOXSTRICTRC_VAL(rc));
|
---|
2124 |
|
---|
2125 | if (desc.numPages != 0)
|
---|
2126 | {
|
---|
2127 | AssertBreakStmt(desc.numPages <= cMaxPages, rc = VERR_OUT_OF_RANGE);
|
---|
2128 | cPagesTotal += desc.numPages;
|
---|
2129 | AssertBreakStmt(cPagesTotal <= cMaxPages, rc = VERR_OUT_OF_RANGE);
|
---|
2130 |
|
---|
2131 | if ((iDesc & 15) == 0)
|
---|
2132 | {
|
---|
2133 | void *pvNew = RTMemRealloc(paDescs, (iDesc + 16) * sizeof(VMSVGAGMRDESCRIPTOR));
|
---|
2134 | AssertBreakStmt(pvNew, rc = VERR_NO_MEMORY);
|
---|
2135 | paDescs = (PVMSVGAGMRDESCRIPTOR)pvNew;
|
---|
2136 | }
|
---|
2137 |
|
---|
2138 | paDescs[iDesc].GCPhys = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
|
---|
2139 | paDescs[iDesc++].numPages = desc.numPages;
|
---|
2140 |
|
---|
2141 | /* Continue with the next descriptor. */
|
---|
2142 | GCPhys += sizeof(desc);
|
---|
2143 | }
|
---|
2144 | else if (desc.ppn == 0)
|
---|
2145 | break; /* terminator */
|
---|
2146 | else /* Pointer to the next physical page of descriptors. */
|
---|
2147 | GCPhys = GCPhysBase = (RTGCPHYS)desc.ppn << PAGE_SHIFT;
|
---|
2148 |
|
---|
2149 | cLoops++;
|
---|
2150 | AssertBreakStmt(cLoops < VMSVGA_MAX_GMR_DESC_LOOP_COUNT, rc = VERR_OUT_OF_RANGE);
|
---|
2151 | }
|
---|
2152 |
|
---|
2153 | AssertStmt(iDesc > 0 || RT_FAILURE_NP(rc), rc = VERR_OUT_OF_RANGE);
|
---|
2154 | if (RT_SUCCESS(rc))
|
---|
2155 | {
|
---|
2156 | /* Commit the GMR. */
|
---|
2157 | pSVGAState->paGMR[idGMR].paDesc = paDescs;
|
---|
2158 | pSVGAState->paGMR[idGMR].numDescriptors = iDesc;
|
---|
2159 | pSVGAState->paGMR[idGMR].cMaxPages = cPagesTotal;
|
---|
2160 | pSVGAState->paGMR[idGMR].cbTotal = cPagesTotal * PAGE_SIZE;
|
---|
2161 | Assert((pSVGAState->paGMR[idGMR].cbTotal >> PAGE_SHIFT) == cPagesTotal);
|
---|
2162 | Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x (%#x pages)\n",
|
---|
2163 | idGMR, iDesc, pSVGAState->paGMR[idGMR].cbTotal, cPagesTotal));
|
---|
2164 | }
|
---|
2165 | else
|
---|
2166 | {
|
---|
2167 | RTMemFree(paDescs);
|
---|
2168 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3RegGmrDescriptorWrErrors);
|
---|
2169 | }
|
---|
2170 | break;
|
---|
2171 | }
|
---|
2172 | # endif /* IN_RING3 */
|
---|
2173 | #endif // VBOX_WITH_VMSVGA3D
|
---|
2174 |
|
---|
2175 | case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
|
---|
2176 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegTracesWr);
|
---|
2177 | if (pThis->svga.fTraces == u32)
|
---|
2178 | break; /* nothing to do */
|
---|
2179 |
|
---|
2180 | #ifdef IN_RING3
|
---|
2181 | vmsvgaR3SetTraces(pDevIns, pThis, !!u32);
|
---|
2182 | #else
|
---|
2183 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2184 | #endif
|
---|
2185 | break;
|
---|
2186 |
|
---|
2187 | case SVGA_REG_TOP: /* Must be 1 more than the last register */
|
---|
2188 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegTopWr);
|
---|
2189 | break;
|
---|
2190 |
|
---|
2191 | case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */
|
---|
2192 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegNumDisplaysWr);
|
---|
2193 | Log(("Write to deprecated register %x - val %x ignored\n", idxReg, u32));
|
---|
2194 | break;
|
---|
2195 |
|
---|
2196 | /*
|
---|
2197 | * SVGA_CAP_GBOBJECTS+ registers.
|
---|
2198 | */
|
---|
2199 | case SVGA_REG_COMMAND_LOW:
|
---|
2200 | {
|
---|
2201 | /* Lower 32 bits of command buffer physical address and submit the command buffer. */
|
---|
2202 | #ifdef IN_RING3
|
---|
2203 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandLowWr);
|
---|
2204 | pThis->svga.u32RegCommandLow = u32;
|
---|
2205 |
|
---|
2206 | /* "lower 6 bits are used for the SVGACBContext" */
|
---|
2207 | RTGCPHYS GCPhysCB = pThis->svga.u32RegCommandHigh;
|
---|
2208 | GCPhysCB <<= 32;
|
---|
2209 | GCPhysCB |= pThis->svga.u32RegCommandLow & ~SVGA_CB_CONTEXT_MASK;
|
---|
2210 | SVGACBContext const CBCtx = (SVGACBContext)(pThis->svga.u32RegCommandLow & SVGA_CB_CONTEXT_MASK);
|
---|
2211 | vmsvgaR3CmdBufSubmit(pDevIns, pThis, pThisCC, GCPhysCB, CBCtx);
|
---|
2212 | #else
|
---|
2213 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2214 | #endif
|
---|
2215 | break;
|
---|
2216 | }
|
---|
2217 |
|
---|
2218 | case SVGA_REG_COMMAND_HIGH:
|
---|
2219 | /* Upper 32 bits of command buffer PA. */
|
---|
2220 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCommandHighWr);
|
---|
2221 | pThis->svga.u32RegCommandHigh = u32;
|
---|
2222 | break;
|
---|
2223 |
|
---|
2224 | case SVGA_REG_DEV_CAP:
|
---|
2225 | /* Write dev cap index, read value */
|
---|
2226 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegDevCapWr);
|
---|
2227 | pThis->svga.u32DevCapIndex = u32;
|
---|
2228 | break;
|
---|
2229 |
|
---|
2230 | case SVGA_REG_CMD_PREPEND_LOW:
|
---|
2231 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependLowWr);
|
---|
2232 | /* Not supported. */
|
---|
2233 | break;
|
---|
2234 |
|
---|
2235 | case SVGA_REG_CMD_PREPEND_HIGH:
|
---|
2236 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegCmdPrependHighWr);
|
---|
2237 | /* Not supported. */
|
---|
2238 | break;
|
---|
2239 |
|
---|
2240 | case SVGA_REG_FB_START:
|
---|
2241 | case SVGA_REG_MEM_START:
|
---|
2242 | case SVGA_REG_HOST_BITS_PER_PIXEL:
|
---|
2243 | case SVGA_REG_MAX_WIDTH:
|
---|
2244 | case SVGA_REG_MAX_HEIGHT:
|
---|
2245 | case SVGA_REG_VRAM_SIZE:
|
---|
2246 | case SVGA_REG_FB_SIZE:
|
---|
2247 | case SVGA_REG_CAPABILITIES:
|
---|
2248 | case SVGA_REG_MEM_SIZE:
|
---|
2249 | case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
|
---|
2250 | case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
|
---|
2251 | case SVGA_REG_BYTES_PER_LINE:
|
---|
2252 | case SVGA_REG_FB_OFFSET:
|
---|
2253 | case SVGA_REG_RED_MASK:
|
---|
2254 | case SVGA_REG_GREEN_MASK:
|
---|
2255 | case SVGA_REG_BLUE_MASK:
|
---|
2256 | case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
|
---|
2257 | case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
|
---|
2258 | case SVGA_REG_GMR_MAX_IDS:
|
---|
2259 | case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:
|
---|
2260 | case SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM:
|
---|
2261 | case SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB:
|
---|
2262 | case SVGA_REG_SCREENTARGET_MAX_WIDTH:
|
---|
2263 | case SVGA_REG_SCREENTARGET_MAX_HEIGHT:
|
---|
2264 | case SVGA_REG_MOB_MAX_SIZE:
|
---|
2265 | /* Read only - ignore. */
|
---|
2266 | Log(("Write to R/O register %x - val %x ignored\n", idxReg, u32));
|
---|
2267 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegReadOnlyWr);
|
---|
2268 | break;
|
---|
2269 |
|
---|
2270 | default:
|
---|
2271 | {
|
---|
2272 | uint32_t offReg;
|
---|
2273 | if ((offReg = idxReg - SVGA_SCRATCH_BASE) < pThis->svga.cScratchRegion)
|
---|
2274 | {
|
---|
2275 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
2276 | pThis->svga.au32ScratchRegion[offReg] = u32;
|
---|
2277 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegScratchWr);
|
---|
2278 | }
|
---|
2279 | else if ((offReg = idxReg - SVGA_PALETTE_BASE) < (uint32_t)SVGA_NUM_PALETTE_REGS)
|
---|
2280 | {
|
---|
2281 | /* Note! Using last_palette rather than palette here to preserve the VGA one.
|
---|
2282 | Btw, see rgb_to_pixel32. */
|
---|
2283 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegPaletteWr);
|
---|
2284 | u32 &= 0xff;
|
---|
2285 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
2286 | uint32_t uRgb = pThis->last_palette[offReg / 3];
|
---|
2287 | switch (offReg % 3)
|
---|
2288 | {
|
---|
2289 | case 0: uRgb = (uRgb & UINT32_C(0x0000ffff)) | (u32 << 16); break; /* red */
|
---|
2290 | case 1: uRgb = (uRgb & UINT32_C(0x00ff00ff)) | (u32 << 8); break; /* green */
|
---|
2291 | case 2: uRgb = (uRgb & UINT32_C(0x00ffff00)) | u32 ; break; /* blue */
|
---|
2292 | }
|
---|
2293 | pThis->last_palette[offReg / 3] = uRgb;
|
---|
2294 | }
|
---|
2295 | else
|
---|
2296 | {
|
---|
2297 | #if !defined(IN_RING3) && defined(VBOX_STRICT)
|
---|
2298 | rc = VINF_IOM_R3_IOPORT_WRITE;
|
---|
2299 | #else
|
---|
2300 | STAM_REL_COUNTER_INC(&pThis->svga.StatRegUnknownWr);
|
---|
2301 | AssertMsgFailed(("reg=%#x u32=%#x\n", idxReg, u32));
|
---|
2302 | #endif
|
---|
2303 | }
|
---|
2304 | break;
|
---|
2305 | }
|
---|
2306 | }
|
---|
2307 | return rc;
|
---|
2308 | }
|
---|
2309 |
|
---|
2310 | /**
|
---|
2311 | * @callback_method_impl{FNIOMIOPORTNEWIN}
|
---|
2312 | */
|
---|
2313 | DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
|
---|
2314 | {
|
---|
2315 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
2316 | RT_NOREF_PV(pvUser);
|
---|
2317 |
|
---|
2318 | /* Only dword accesses. */
|
---|
2319 | if (cb == 4)
|
---|
2320 | {
|
---|
2321 | switch (offPort)
|
---|
2322 | {
|
---|
2323 | case SVGA_INDEX_PORT:
|
---|
2324 | *pu32 = pThis->svga.u32IndexReg;
|
---|
2325 | break;
|
---|
2326 |
|
---|
2327 | case SVGA_VALUE_PORT:
|
---|
2328 | return vmsvgaReadPort(pDevIns, pThis, pu32);
|
---|
2329 |
|
---|
2330 | case SVGA_BIOS_PORT:
|
---|
2331 | Log(("Ignoring BIOS port read\n"));
|
---|
2332 | *pu32 = 0;
|
---|
2333 | break;
|
---|
2334 |
|
---|
2335 | case SVGA_IRQSTATUS_PORT:
|
---|
2336 | LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
|
---|
2337 | *pu32 = pThis->svga.u32IrqStatus;
|
---|
2338 | break;
|
---|
2339 |
|
---|
2340 | default:
|
---|
2341 | ASSERT_GUEST_MSG_FAILED(("vmsvgaIORead: Unknown register %u was read from.\n", offPort));
|
---|
2342 | *pu32 = UINT32_MAX;
|
---|
2343 | break;
|
---|
2344 | }
|
---|
2345 | }
|
---|
2346 | else
|
---|
2347 | {
|
---|
2348 | Log(("Ignoring non-dword I/O port read at %x cb=%d\n", offPort, cb));
|
---|
2349 | *pu32 = UINT32_MAX;
|
---|
2350 | }
|
---|
2351 | return VINF_SUCCESS;
|
---|
2352 | }
|
---|
2353 |
|
---|
2354 | /**
|
---|
2355 | * @callback_method_impl{FNIOMIOPORTNEWOUT}
|
---|
2356 | */
|
---|
2357 | DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
|
---|
2358 | {
|
---|
2359 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
2360 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
2361 | RT_NOREF_PV(pvUser);
|
---|
2362 |
|
---|
2363 | /* Only dword accesses. */
|
---|
2364 | if (cb == 4)
|
---|
2365 | switch (offPort)
|
---|
2366 | {
|
---|
2367 | case SVGA_INDEX_PORT:
|
---|
2368 | pThis->svga.u32IndexReg = u32;
|
---|
2369 | break;
|
---|
2370 |
|
---|
2371 | case SVGA_VALUE_PORT:
|
---|
2372 | return vmsvgaWritePort(pDevIns, pThis, pThisCC, u32);
|
---|
2373 |
|
---|
2374 | case SVGA_BIOS_PORT:
|
---|
2375 | Log(("Ignoring BIOS port write (val=%x)\n", u32));
|
---|
2376 | break;
|
---|
2377 |
|
---|
2378 | case SVGA_IRQSTATUS_PORT:
|
---|
2379 | Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
|
---|
2380 | ASMAtomicAndU32(&pThis->svga.u32IrqStatus, ~u32);
|
---|
2381 | /* Clear the irq in case all events have been cleared. */
|
---|
2382 | if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
|
---|
2383 | {
|
---|
2384 | Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT: clearing IRQ\n"));
|
---|
2385 | PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
|
---|
2386 | }
|
---|
2387 | break;
|
---|
2388 |
|
---|
2389 | default:
|
---|
2390 | ASSERT_GUEST_MSG_FAILED(("vmsvgaIOWrite: Unknown register %u was written to, value %#x LB %u.\n", offPort, u32, cb));
|
---|
2391 | break;
|
---|
2392 | }
|
---|
2393 | else
|
---|
2394 | Log(("Ignoring non-dword write at %x val=%x cb=%d\n", offPort, u32, cb));
|
---|
2395 |
|
---|
2396 | return VINF_SUCCESS;
|
---|
2397 | }
|
---|
2398 |
|
---|
2399 | #ifdef IN_RING3
|
---|
2400 |
|
---|
2401 | # ifdef DEBUG_FIFO_ACCESS
|
---|
2402 | /**
|
---|
2403 | * Handle FIFO memory access.
|
---|
2404 | * @returns VBox status code.
|
---|
2405 | * @param pVM VM handle.
|
---|
2406 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
2407 | * @param GCPhys The access physical address.
|
---|
2408 | * @param fWriteAccess Read or write access
|
---|
2409 | */
|
---|
2410 | static int vmsvgaR3DebugFifoAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
|
---|
2411 | {
|
---|
2412 | RT_NOREF(pVM);
|
---|
2413 | RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
|
---|
2414 | uint32_t *pFIFO = pThisCC->svga.pau32FIFO;
|
---|
2415 |
|
---|
2416 | switch (GCPhysOffset >> 2)
|
---|
2417 | {
|
---|
2418 | case SVGA_FIFO_MIN:
|
---|
2419 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2420 | break;
|
---|
2421 | case SVGA_FIFO_MAX:
|
---|
2422 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2423 | break;
|
---|
2424 | case SVGA_FIFO_NEXT_CMD:
|
---|
2425 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2426 | break;
|
---|
2427 | case SVGA_FIFO_STOP:
|
---|
2428 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2429 | break;
|
---|
2430 | case SVGA_FIFO_CAPABILITIES:
|
---|
2431 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2432 | break;
|
---|
2433 | case SVGA_FIFO_FLAGS:
|
---|
2434 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2435 | break;
|
---|
2436 | case SVGA_FIFO_FENCE:
|
---|
2437 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2438 | break;
|
---|
2439 | case SVGA_FIFO_3D_HWVERSION:
|
---|
2440 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2441 | break;
|
---|
2442 | case SVGA_FIFO_PITCHLOCK:
|
---|
2443 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2444 | break;
|
---|
2445 | case SVGA_FIFO_CURSOR_ON:
|
---|
2446 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2447 | break;
|
---|
2448 | case SVGA_FIFO_CURSOR_X:
|
---|
2449 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2450 | break;
|
---|
2451 | case SVGA_FIFO_CURSOR_Y:
|
---|
2452 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2453 | break;
|
---|
2454 | case SVGA_FIFO_CURSOR_COUNT:
|
---|
2455 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2456 | break;
|
---|
2457 | case SVGA_FIFO_CURSOR_LAST_UPDATED:
|
---|
2458 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2459 | break;
|
---|
2460 | case SVGA_FIFO_RESERVED:
|
---|
2461 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2462 | break;
|
---|
2463 | case SVGA_FIFO_CURSOR_SCREEN_ID:
|
---|
2464 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2465 | break;
|
---|
2466 | case SVGA_FIFO_DEAD:
|
---|
2467 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2468 | break;
|
---|
2469 | case SVGA_FIFO_3D_HWVERSION_REVISED:
|
---|
2470 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2471 | break;
|
---|
2472 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_3D:
|
---|
2473 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2474 | break;
|
---|
2475 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_LIGHTS:
|
---|
2476 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2477 | break;
|
---|
2478 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
|
---|
2479 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2480 | break;
|
---|
2481 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
|
---|
2482 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2483 | break;
|
---|
2484 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
|
---|
2485 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2486 | break;
|
---|
2487 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
|
---|
2488 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2489 | break;
|
---|
2490 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
|
---|
2491 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2492 | break;
|
---|
2493 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
|
---|
2494 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2495 | break;
|
---|
2496 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
|
---|
2497 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2498 | break;
|
---|
2499 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
|
---|
2500 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2501 | break;
|
---|
2502 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
|
---|
2503 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2504 | break;
|
---|
2505 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
|
---|
2506 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2507 | break;
|
---|
2508 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
|
---|
2509 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2510 | break;
|
---|
2511 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
|
---|
2512 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2513 | break;
|
---|
2514 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
|
---|
2515 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2516 | break;
|
---|
2517 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
|
---|
2518 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2519 | break;
|
---|
2520 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
|
---|
2521 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2522 | break;
|
---|
2523 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
|
---|
2524 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2525 | break;
|
---|
2526 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
|
---|
2527 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2528 | break;
|
---|
2529 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
|
---|
2530 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2531 | break;
|
---|
2532 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
|
---|
2533 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2534 | break;
|
---|
2535 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
|
---|
2536 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2537 | break;
|
---|
2538 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
|
---|
2539 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2540 | break;
|
---|
2541 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
|
---|
2542 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2543 | break;
|
---|
2544 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
|
---|
2545 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2546 | break;
|
---|
2547 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
|
---|
2548 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2549 | break;
|
---|
2550 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
|
---|
2551 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2552 | break;
|
---|
2553 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
|
---|
2554 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2555 | break;
|
---|
2556 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
|
---|
2557 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2558 | break;
|
---|
2559 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
|
---|
2560 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2561 | break;
|
---|
2562 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
|
---|
2563 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2564 | break;
|
---|
2565 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
|
---|
2566 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2567 | break;
|
---|
2568 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
|
---|
2569 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2570 | break;
|
---|
2571 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
|
---|
2572 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2573 | break;
|
---|
2574 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
|
---|
2575 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2576 | break;
|
---|
2577 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
|
---|
2578 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2579 | break;
|
---|
2580 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
|
---|
2581 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2582 | break;
|
---|
2583 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
|
---|
2584 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2585 | break;
|
---|
2586 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
|
---|
2587 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2588 | break;
|
---|
2589 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
|
---|
2590 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2591 | break;
|
---|
2592 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
|
---|
2593 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2594 | break;
|
---|
2595 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
|
---|
2596 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2597 | break;
|
---|
2598 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
|
---|
2599 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2600 | break;
|
---|
2601 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
|
---|
2602 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2603 | break;
|
---|
2604 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
|
---|
2605 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2606 | break;
|
---|
2607 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
|
---|
2608 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2609 | break;
|
---|
2610 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
|
---|
2611 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2612 | break;
|
---|
2613 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
|
---|
2614 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2615 | break;
|
---|
2616 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
|
---|
2617 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2618 | break;
|
---|
2619 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
|
---|
2620 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2621 | break;
|
---|
2622 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
|
---|
2623 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2624 | break;
|
---|
2625 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
|
---|
2626 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2627 | break;
|
---|
2628 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
|
---|
2629 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2630 | break;
|
---|
2631 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
|
---|
2632 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2633 | break;
|
---|
2634 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
|
---|
2635 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2636 | break;
|
---|
2637 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
|
---|
2638 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2639 | break;
|
---|
2640 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
|
---|
2641 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2642 | break;
|
---|
2643 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
|
---|
2644 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2645 | break;
|
---|
2646 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
|
---|
2647 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2648 | break;
|
---|
2649 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
|
---|
2650 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2651 | break;
|
---|
2652 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
|
---|
2653 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2654 | break;
|
---|
2655 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
|
---|
2656 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2657 | break;
|
---|
2658 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
|
---|
2659 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2660 | break;
|
---|
2661 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
|
---|
2662 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2663 | break;
|
---|
2664 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
|
---|
2665 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2666 | break;
|
---|
2667 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
|
---|
2668 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2669 | break;
|
---|
2670 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
|
---|
2671 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2672 | break;
|
---|
2673 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
|
---|
2674 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2675 | break;
|
---|
2676 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
|
---|
2677 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2678 | break;
|
---|
2679 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD4: /* SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES */
|
---|
2680 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD4 (SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2681 | break;
|
---|
2682 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD5: /* SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES */
|
---|
2683 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD5 (SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2684 | break;
|
---|
2685 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD7: /* SVGA3D_DEVCAP_ALPHATOCOVERAGE */
|
---|
2686 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD7 (SVGA3D_DEVCAP_ALPHATOCOVERAGE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2687 | break;
|
---|
2688 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD6: /* SVGA3D_DEVCAP_SUPERSAMPLE */
|
---|
2689 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD6 (SVGA3D_DEVCAP_SUPERSAMPLE) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2690 | break;
|
---|
2691 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
|
---|
2692 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2693 | break;
|
---|
2694 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
|
---|
2695 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2696 | break;
|
---|
2697 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_DEAD10: /* SVGA3D_DEVCAP_SURFACEFMT_AYUV */
|
---|
2698 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_DEAD10 (SVGA3D_DEVCAP_SURFACEFMT_AYUV) = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2699 | break;
|
---|
2700 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
|
---|
2701 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2702 | break;
|
---|
2703 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
|
---|
2704 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2705 | break;
|
---|
2706 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
|
---|
2707 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2708 | break;
|
---|
2709 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
|
---|
2710 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2711 | break;
|
---|
2712 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
|
---|
2713 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2714 | break;
|
---|
2715 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI1:
|
---|
2716 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2717 | break;
|
---|
2718 | case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ATI2:
|
---|
2719 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ATI2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2720 | break;
|
---|
2721 | case SVGA_FIFO_3D_CAPS_LAST:
|
---|
2722 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2723 | break;
|
---|
2724 | case SVGA_FIFO_GUEST_3D_HWVERSION:
|
---|
2725 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2726 | break;
|
---|
2727 | case SVGA_FIFO_FENCE_GOAL:
|
---|
2728 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2729 | break;
|
---|
2730 | case SVGA_FIFO_BUSY:
|
---|
2731 | Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
|
---|
2732 | break;
|
---|
2733 | default:
|
---|
2734 | Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
|
---|
2735 | break;
|
---|
2736 | }
|
---|
2737 |
|
---|
2738 | return VINF_EM_RAW_EMULATE_INSTR;
|
---|
2739 | }
|
---|
2740 | # endif /* DEBUG_FIFO_ACCESS */
|
---|
2741 |
|
---|
2742 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
|
---|
2743 | /**
|
---|
2744 | * HC access handler for the FIFO.
|
---|
2745 | *
|
---|
2746 | * @returns VINF_SUCCESS if the handler have carried out the operation.
|
---|
2747 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
|
---|
2748 | * @param pVM VM Handle.
|
---|
2749 | * @param pVCpu The cross context CPU structure for the calling EMT.
|
---|
2750 | * @param GCPhys The physical address the guest is writing to.
|
---|
2751 | * @param pvPhys The HC mapping of that address.
|
---|
2752 | * @param pvBuf What the guest is reading/writing.
|
---|
2753 | * @param cbBuf How much it's reading/writing.
|
---|
2754 | * @param enmAccessType The access type.
|
---|
2755 | * @param enmOrigin Who is making the access.
|
---|
2756 | * @param pvUser User argument.
|
---|
2757 | */
|
---|
2758 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
2759 | vmsvgaR3FifoAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
|
---|
2760 | PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
|
---|
2761 | {
|
---|
2762 | NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmOrigin); NOREF(enmAccessType); NOREF(GCPhys);
|
---|
2763 | PVGASTATE pThis = (PVGASTATE)pvUser;
|
---|
2764 | AssertPtr(pThis);
|
---|
2765 |
|
---|
2766 | # ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
|
---|
2767 | /*
|
---|
2768 | * Wake up the FIFO thread as it might have work to do now.
|
---|
2769 | */
|
---|
2770 | int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
2771 | AssertLogRelRC(rc);
|
---|
2772 | # endif
|
---|
2773 |
|
---|
2774 | # ifdef DEBUG_FIFO_ACCESS
|
---|
2775 | /*
|
---|
2776 | * When in debug-fifo-access mode, we do not disable the access handler,
|
---|
2777 | * but leave it on as we wish to catch all access.
|
---|
2778 | */
|
---|
2779 | Assert(GCPhys >= pThis->svga.GCPhysFIFO);
|
---|
2780 | rc = vmsvgaR3DebugFifoAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
|
---|
2781 | # elif defined(VMSVGA_USE_FIFO_ACCESS_HANDLER)
|
---|
2782 | /*
|
---|
2783 | * Temporarily disable the access handler now that we've kicked the FIFO thread.
|
---|
2784 | */
|
---|
2785 | STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoAccessHandler);
|
---|
2786 | rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->svga.GCPhysFIFO, pThis->svga.GCPhysFIFO);
|
---|
2787 | # endif
|
---|
2788 | if (RT_SUCCESS(rc))
|
---|
2789 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
2790 | AssertMsg(rc <= VINF_SUCCESS, ("rc=%Rrc\n", rc));
|
---|
2791 | return rc;
|
---|
2792 | }
|
---|
2793 | # endif /* VMSVGA_USE_FIFO_ACCESS_HANDLER || DEBUG_FIFO_ACCESS */
|
---|
2794 |
|
---|
2795 | #endif /* IN_RING3 */
|
---|
2796 |
|
---|
2797 | #ifdef DEBUG_GMR_ACCESS
|
---|
2798 | # ifdef IN_RING3
|
---|
2799 |
|
---|
2800 | /**
|
---|
2801 | * HC access handler for GMRs.
|
---|
2802 | *
|
---|
2803 | * @returns VINF_SUCCESS if the handler have carried out the operation.
|
---|
2804 | * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
|
---|
2805 | * @param pVM VM Handle.
|
---|
2806 | * @param pVCpu The cross context CPU structure for the calling EMT.
|
---|
2807 | * @param GCPhys The physical address the guest is writing to.
|
---|
2808 | * @param pvPhys The HC mapping of that address.
|
---|
2809 | * @param pvBuf What the guest is reading/writing.
|
---|
2810 | * @param cbBuf How much it's reading/writing.
|
---|
2811 | * @param enmAccessType The access type.
|
---|
2812 | * @param enmOrigin Who is making the access.
|
---|
2813 | * @param pvUser User argument.
|
---|
2814 | */
|
---|
2815 | static DECLCALLBACK(VBOXSTRICTRC)
|
---|
2816 | vmsvgaR3GmrAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf,
|
---|
2817 | PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
|
---|
2818 | {
|
---|
2819 | PVGASTATE pThis = (PVGASTATE)pvUser;
|
---|
2820 | Assert(pThis);
|
---|
2821 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
2822 | NOREF(pVCpu); NOREF(pvPhys); NOREF(pvBuf); NOREF(cbBuf); NOREF(enmAccessType); NOREF(enmOrigin);
|
---|
2823 |
|
---|
2824 | Log(("vmsvgaR3GmrAccessHandler: GMR access to page %RGp\n", GCPhys));
|
---|
2825 |
|
---|
2826 | for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
|
---|
2827 | {
|
---|
2828 | PGMR pGMR = &pSVGAState->paGMR[i];
|
---|
2829 |
|
---|
2830 | if (pGMR->numDescriptors)
|
---|
2831 | {
|
---|
2832 | for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
|
---|
2833 | {
|
---|
2834 | if ( GCPhys >= pGMR->paDesc[j].GCPhys
|
---|
2835 | && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
|
---|
2836 | {
|
---|
2837 | /*
|
---|
2838 | * Turn off the write handler for this particular page and make it R/W.
|
---|
2839 | * Then return telling the caller to restart the guest instruction.
|
---|
2840 | */
|
---|
2841 | int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
|
---|
2842 | AssertRC(rc);
|
---|
2843 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
2844 | }
|
---|
2845 | }
|
---|
2846 | }
|
---|
2847 | }
|
---|
2848 |
|
---|
2849 | return VINF_PGM_HANDLER_DO_DEFAULT;
|
---|
2850 | }
|
---|
2851 |
|
---|
2852 | /** Callback handler for VMR3ReqCallWaitU */
|
---|
2853 | static DECLCALLBACK(int) vmsvgaR3RegisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
|
---|
2854 | {
|
---|
2855 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
2856 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
2857 | PGMR pGMR = &pSVGAState->paGMR[gmrId];
|
---|
2858 | int rc;
|
---|
2859 |
|
---|
2860 | for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
|
---|
2861 | {
|
---|
2862 | rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
|
---|
2863 | pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
|
---|
2864 | pThis->svga.hGmrAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR, "VMSVGA GMR");
|
---|
2865 | AssertRC(rc);
|
---|
2866 | }
|
---|
2867 | return VINF_SUCCESS;
|
---|
2868 | }
|
---|
2869 |
|
---|
2870 | /** Callback handler for VMR3ReqCallWaitU */
|
---|
2871 | static DECLCALLBACK(int) vmsvgaR3DeregisterGmr(PPDMDEVINS pDevIns, uint32_t gmrId)
|
---|
2872 | {
|
---|
2873 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
2874 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
2875 | PGMR pGMR = &pSVGAState->paGMR[gmrId];
|
---|
2876 |
|
---|
2877 | for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
|
---|
2878 | {
|
---|
2879 | int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[i].GCPhys);
|
---|
2880 | AssertRC(rc);
|
---|
2881 | }
|
---|
2882 | return VINF_SUCCESS;
|
---|
2883 | }
|
---|
2884 |
|
---|
2885 | /** Callback handler for VMR3ReqCallWaitU */
|
---|
2886 | static DECLCALLBACK(int) vmsvgaR3ResetGmrHandlers(PVGASTATE pThis)
|
---|
2887 | {
|
---|
2888 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
2889 |
|
---|
2890 | for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
|
---|
2891 | {
|
---|
2892 | PGMR pGMR = &pSVGAState->paGMR[i];
|
---|
2893 |
|
---|
2894 | if (pGMR->numDescriptors)
|
---|
2895 | {
|
---|
2896 | for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
|
---|
2897 | {
|
---|
2898 | int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pGMR->paDesc[j].GCPhys);
|
---|
2899 | AssertRC(rc);
|
---|
2900 | }
|
---|
2901 | }
|
---|
2902 | }
|
---|
2903 | return VINF_SUCCESS;
|
---|
2904 | }
|
---|
2905 |
|
---|
2906 | # endif /* IN_RING3 */
|
---|
2907 | #endif /* DEBUG_GMR_ACCESS */
|
---|
2908 |
|
---|
2909 | /* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
|
---|
2910 |
|
---|
2911 | #ifdef IN_RING3
|
---|
2912 |
|
---|
2913 |
|
---|
2914 | /*
|
---|
2915 | *
|
---|
2916 | * Command buffer submission.
|
---|
2917 | *
|
---|
2918 | * Guest submits a buffer by writing to SVGA_REG_COMMAND_LOW register.
|
---|
2919 | *
|
---|
2920 | * EMT thread appends a command buffer to the context queue (VMSVGACMDBUFCTX::listSubmitted)
|
---|
2921 | * and wakes up the FIFO thread.
|
---|
2922 | *
|
---|
2923 | * FIFO thread fetches the command buffer from the queue, processes the commands and writes
|
---|
2924 | * the buffer header back to the guest memory.
|
---|
2925 | *
|
---|
2926 | * If buffers are preempted, then the EMT thread removes all buffers from the context queue.
|
---|
2927 | *
|
---|
2928 | */
|
---|
2929 |
|
---|
2930 |
|
---|
2931 | /** Update a command buffer header 'status' and 'errorOffset' fields in the guest memory.
|
---|
2932 | *
|
---|
2933 | * @param pDevIns The device instance.
|
---|
2934 | * @param GCPhysCB Guest physical address of the command buffer header.
|
---|
2935 | * @param status Command buffer status (SVGA_CB_STATUS_*).
|
---|
2936 | * @param errorOffset Offset to the first byte of the failing command for SVGA_CB_STATUS_COMMAND_ERROR.
|
---|
2937 | * errorOffset is ignored if the status is not SVGA_CB_STATUS_COMMAND_ERROR.
|
---|
2938 | * @thread FIFO or EMT.
|
---|
2939 | */
|
---|
2940 | static void vmsvgaR3CmdBufWriteStatus(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCB, SVGACBStatus status, uint32_t errorOffset)
|
---|
2941 | {
|
---|
2942 | SVGACBHeader hdr;
|
---|
2943 | hdr.status = status;
|
---|
2944 | hdr.errorOffset = errorOffset;
|
---|
2945 | AssertCompile( RT_OFFSETOF(SVGACBHeader, status) == 0
|
---|
2946 | && RT_OFFSETOF(SVGACBHeader, errorOffset) == 4
|
---|
2947 | && RT_OFFSETOF(SVGACBHeader, id) == 8);
|
---|
2948 | size_t const cbWrite = status == SVGA_CB_STATUS_COMMAND_ERROR
|
---|
2949 | ? RT_UOFFSET_AFTER(SVGACBHeader, errorOffset) /* Both 'status' and 'errorOffset' fields. */
|
---|
2950 | : RT_UOFFSET_AFTER(SVGACBHeader, status); /* Only 'status' field. */
|
---|
2951 | PDMDevHlpPCIPhysWrite(pDevIns, GCPhysCB, &hdr, cbWrite);
|
---|
2952 | }
|
---|
2953 |
|
---|
2954 |
|
---|
2955 | /** Raise an IRQ.
|
---|
2956 | *
|
---|
2957 | * @param pDevIns The device instance.
|
---|
2958 | * @param pThis The shared VGA/VMSVGA state.
|
---|
2959 | * @param u32IrqStatus SVGA_IRQFLAG_* bits.
|
---|
2960 | * @thread FIFO or EMT.
|
---|
2961 | */
|
---|
2962 | static void vmsvgaR3CmdBufRaiseIRQ(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t u32IrqStatus)
|
---|
2963 | {
|
---|
2964 | int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
2965 | AssertRC(rc);
|
---|
2966 |
|
---|
2967 | if (pThis->svga.u32IrqMask & u32IrqStatus)
|
---|
2968 | {
|
---|
2969 | LogFunc(("Trigger interrupt with status %#x\n", u32IrqStatus));
|
---|
2970 | ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
|
---|
2971 | PDMDevHlpPCISetIrq(pDevIns, 0, 1);
|
---|
2972 | }
|
---|
2973 |
|
---|
2974 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
2975 | }
|
---|
2976 |
|
---|
2977 |
|
---|
2978 | /** Allocate a command buffer structure.
|
---|
2979 | *
|
---|
2980 | * @param pCmdBufCtx The command buffer context which must allocate the buffer.
|
---|
2981 | * @return Pointer to the allocated command buffer structure.
|
---|
2982 | */
|
---|
2983 | static PVMSVGACMDBUF vmsvgaR3CmdBufAlloc(PVMSVGACMDBUFCTX pCmdBufCtx)
|
---|
2984 | {
|
---|
2985 | if (!pCmdBufCtx)
|
---|
2986 | return NULL;
|
---|
2987 |
|
---|
2988 | PVMSVGACMDBUF pCmdBuf = (PVMSVGACMDBUF)RTMemAllocZ(sizeof(*pCmdBuf));
|
---|
2989 | if (pCmdBuf)
|
---|
2990 | {
|
---|
2991 | // RT_ZERO(pCmdBuf->nodeBuffer);
|
---|
2992 | pCmdBuf->pCmdBufCtx = pCmdBufCtx;
|
---|
2993 | // pCmdBuf->GCPhysCB = 0;
|
---|
2994 | // RT_ZERO(pCmdBuf->hdr);
|
---|
2995 | // pCmdBuf->pvCommands = NULL;
|
---|
2996 | }
|
---|
2997 |
|
---|
2998 | return pCmdBuf;
|
---|
2999 | }
|
---|
3000 |
|
---|
3001 |
|
---|
3002 | /** Free a command buffer structure.
|
---|
3003 | *
|
---|
3004 | * @param pCmdBuf The command buffer pointer.
|
---|
3005 | */
|
---|
3006 | static void vmsvgaR3CmdBufFree(PVMSVGACMDBUF pCmdBuf)
|
---|
3007 | {
|
---|
3008 | if (pCmdBuf)
|
---|
3009 | RTMemFree(pCmdBuf->pvCommands);
|
---|
3010 | RTMemFree(pCmdBuf);
|
---|
3011 | }
|
---|
3012 |
|
---|
3013 |
|
---|
3014 | /** Initialize a command buffer context.
|
---|
3015 | *
|
---|
3016 | * @param pCmdBufCtx The command buffer context.
|
---|
3017 | */
|
---|
3018 | static void vmsvgaR3CmdBufCtxInit(PVMSVGACMDBUFCTX pCmdBufCtx)
|
---|
3019 | {
|
---|
3020 | RTListInit(&pCmdBufCtx->listSubmitted);
|
---|
3021 | pCmdBufCtx->cSubmitted = 0;
|
---|
3022 | }
|
---|
3023 |
|
---|
3024 |
|
---|
3025 | /** Destroy a command buffer context.
|
---|
3026 | *
|
---|
3027 | * @param pCmdBufCtx The command buffer context pointer.
|
---|
3028 | */
|
---|
3029 | static void vmsvgaR3CmdBufCtxTerm(PVMSVGACMDBUFCTX pCmdBufCtx)
|
---|
3030 | {
|
---|
3031 | if (!pCmdBufCtx)
|
---|
3032 | return;
|
---|
3033 |
|
---|
3034 | if (pCmdBufCtx->listSubmitted.pNext)
|
---|
3035 | {
|
---|
3036 | /* If the list has been initialized. */
|
---|
3037 | PVMSVGACMDBUF pIter, pNext;
|
---|
3038 | RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
|
---|
3039 | {
|
---|
3040 | RTListNodeRemove(&pIter->nodeBuffer);
|
---|
3041 | --pCmdBufCtx->cSubmitted;
|
---|
3042 | vmsvgaR3CmdBufFree(pIter);
|
---|
3043 | }
|
---|
3044 | }
|
---|
3045 | Assert(pCmdBufCtx->cSubmitted == 0);
|
---|
3046 | pCmdBufCtx->cSubmitted = 0;
|
---|
3047 | }
|
---|
3048 |
|
---|
3049 |
|
---|
3050 | /** Handles SVGA_DC_CMD_START_STOP_CONTEXT command.
|
---|
3051 | *
|
---|
3052 | * @param pSvgaR3State VMSVGA R3 state.
|
---|
3053 | * @param pCmd The command data.
|
---|
3054 | * @return SVGACBStatus code.
|
---|
3055 | * @thread EMT
|
---|
3056 | */
|
---|
3057 | static SVGACBStatus vmsvgaR3CmdBufDCStartStop(PVMSVGAR3STATE pSvgaR3State, SVGADCCmdStartStop const *pCmd)
|
---|
3058 | {
|
---|
3059 | /* Create or destroy a regular command buffer context. */
|
---|
3060 | if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
|
---|
3061 | return SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3062 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3063 |
|
---|
3064 | SVGACBStatus CBStatus = SVGA_CB_STATUS_COMPLETED;
|
---|
3065 |
|
---|
3066 | int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
|
---|
3067 | AssertRC(rc);
|
---|
3068 | if (pCmd->enable)
|
---|
3069 | {
|
---|
3070 | pSvgaR3State->apCmdBufCtxs[pCmd->context] = (PVMSVGACMDBUFCTX)RTMemAlloc(sizeof(VMSVGACMDBUFCTX));
|
---|
3071 | if (pSvgaR3State->apCmdBufCtxs[pCmd->context])
|
---|
3072 | vmsvgaR3CmdBufCtxInit(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
|
---|
3073 | else
|
---|
3074 | CBStatus = SVGA_CB_STATUS_QUEUE_FULL;
|
---|
3075 | }
|
---|
3076 | else
|
---|
3077 | {
|
---|
3078 | vmsvgaR3CmdBufCtxTerm(pSvgaR3State->apCmdBufCtxs[pCmd->context]);
|
---|
3079 | pSvgaR3State->apCmdBufCtxs[pCmd->context] = NULL;
|
---|
3080 | }
|
---|
3081 | RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
|
---|
3082 |
|
---|
3083 | return CBStatus;
|
---|
3084 | }
|
---|
3085 |
|
---|
3086 |
|
---|
3087 | /** Handles SVGA_DC_CMD_PREEMPT command.
|
---|
3088 | *
|
---|
3089 | * @param pDevIns The device instance.
|
---|
3090 | * @param pSvgaR3State VMSVGA R3 state.
|
---|
3091 | * @param pCmd The command data.
|
---|
3092 | * @return SVGACBStatus code.
|
---|
3093 | * @thread EMT
|
---|
3094 | */
|
---|
3095 | static SVGACBStatus vmsvgaR3CmdBufDCPreempt(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, SVGADCCmdPreempt const *pCmd)
|
---|
3096 | {
|
---|
3097 | /* Remove buffers from the processing queue of the specified context. */
|
---|
3098 | if (pCmd->context >= RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs))
|
---|
3099 | return SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3100 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3101 |
|
---|
3102 | PVMSVGACMDBUFCTX const pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[pCmd->context];
|
---|
3103 | RTLISTANCHOR listPreempted;
|
---|
3104 |
|
---|
3105 | int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
|
---|
3106 | AssertRC(rc);
|
---|
3107 | if (pCmd->ignoreIDZero)
|
---|
3108 | {
|
---|
3109 | RTListInit(&listPreempted);
|
---|
3110 |
|
---|
3111 | PVMSVGACMDBUF pIter, pNext;
|
---|
3112 | RTListForEachSafe(&pCmdBufCtx->listSubmitted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
|
---|
3113 | {
|
---|
3114 | if (pIter->hdr.id == 0)
|
---|
3115 | continue;
|
---|
3116 |
|
---|
3117 | RTListNodeRemove(&pIter->nodeBuffer);
|
---|
3118 | --pCmdBufCtx->cSubmitted;
|
---|
3119 | RTListAppend(&listPreempted, &pIter->nodeBuffer);
|
---|
3120 | }
|
---|
3121 | }
|
---|
3122 | else
|
---|
3123 | {
|
---|
3124 | RTListMove(&listPreempted, &pCmdBufCtx->listSubmitted);
|
---|
3125 | }
|
---|
3126 | RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
|
---|
3127 |
|
---|
3128 | PVMSVGACMDBUF pIter, pNext;
|
---|
3129 | RTListForEachSafe(&listPreempted, pIter, pNext, VMSVGACMDBUF, nodeBuffer)
|
---|
3130 | {
|
---|
3131 | RTListNodeRemove(&pIter->nodeBuffer);
|
---|
3132 | vmsvgaR3CmdBufWriteStatus(pDevIns, pIter->GCPhysCB, SVGA_CB_STATUS_PREEMPTED, 0);
|
---|
3133 | vmsvgaR3CmdBufFree(pIter);
|
---|
3134 | }
|
---|
3135 |
|
---|
3136 | return SVGA_CB_STATUS_COMPLETED;
|
---|
3137 | }
|
---|
3138 |
|
---|
3139 |
|
---|
3140 | /** @def VMSVGA_INC_CMD_SIZE_BREAK
|
---|
3141 | * Increments the size of the command cbCmd by a_cbMore.
|
---|
3142 | * Checks that the command buffer has at least cbCmd bytes. Will break out of the switch if it doesn't.
|
---|
3143 | * Used by vmsvgaR3CmdBufProcessDC and vmsvgaR3CmdBufProcessCommands.
|
---|
3144 | */
|
---|
3145 | #define VMSVGA_INC_CMD_SIZE_BREAK(a_cbMore) \
|
---|
3146 | if (1) { \
|
---|
3147 | cbCmd += (a_cbMore); \
|
---|
3148 | ASSERT_GUEST_MSG_STMT_BREAK(cbRemain >= cbCmd, ("size=%#x remain=%#zx\n", cbCmd, (size_t)cbRemain), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR); \
|
---|
3149 | RT_UNTRUSTED_VALIDATED_FENCE(); \
|
---|
3150 | } else do {} while (0)
|
---|
3151 |
|
---|
3152 |
|
---|
3153 | /** Processes Device Context command buffer.
|
---|
3154 | *
|
---|
3155 | * @param pDevIns The device instance.
|
---|
3156 | * @param pSvgaR3State VMSVGA R3 state.
|
---|
3157 | * @param pvCommands Pointer to the command buffer.
|
---|
3158 | * @param cbCommands Size of the command buffer.
|
---|
3159 | * @param poffNextCmd Where to store the offset of the first unprocessed command.
|
---|
3160 | * @return SVGACBStatus code.
|
---|
3161 | * @thread EMT
|
---|
3162 | */
|
---|
3163 | static SVGACBStatus vmsvgaR3CmdBufProcessDC(PPDMDEVINS pDevIns, PVMSVGAR3STATE pSvgaR3State, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd)
|
---|
3164 | {
|
---|
3165 | SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
|
---|
3166 |
|
---|
3167 | uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
|
---|
3168 | uint32_t cbRemain = cbCommands;
|
---|
3169 | while (cbRemain)
|
---|
3170 | {
|
---|
3171 | /* Command identifier is a 32 bit value. */
|
---|
3172 | if (cbRemain < sizeof(uint32_t))
|
---|
3173 | {
|
---|
3174 | CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3175 | break;
|
---|
3176 | }
|
---|
3177 |
|
---|
3178 | /* Fetch the command id. */
|
---|
3179 | uint32_t const cmdId = *(uint32_t *)pu8Cmd;
|
---|
3180 | uint32_t cbCmd = sizeof(uint32_t);
|
---|
3181 | switch (cmdId)
|
---|
3182 | {
|
---|
3183 | case SVGA_DC_CMD_NOP:
|
---|
3184 | {
|
---|
3185 | /* NOP */
|
---|
3186 | break;
|
---|
3187 | }
|
---|
3188 |
|
---|
3189 | case SVGA_DC_CMD_START_STOP_CONTEXT:
|
---|
3190 | {
|
---|
3191 | SVGADCCmdStartStop *pCmd = (SVGADCCmdStartStop *)&pu8Cmd[cbCmd];
|
---|
3192 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3193 | CBstatus = vmsvgaR3CmdBufDCStartStop(pSvgaR3State, pCmd);
|
---|
3194 | break;
|
---|
3195 | }
|
---|
3196 |
|
---|
3197 | case SVGA_DC_CMD_PREEMPT:
|
---|
3198 | {
|
---|
3199 | SVGADCCmdPreempt *pCmd = (SVGADCCmdPreempt *)&pu8Cmd[cbCmd];
|
---|
3200 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3201 | CBstatus = vmsvgaR3CmdBufDCPreempt(pDevIns, pSvgaR3State, pCmd);
|
---|
3202 | break;
|
---|
3203 | }
|
---|
3204 |
|
---|
3205 | default:
|
---|
3206 | {
|
---|
3207 | /* Unsupported command. */
|
---|
3208 | CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3209 | break;
|
---|
3210 | }
|
---|
3211 | }
|
---|
3212 |
|
---|
3213 | if (CBstatus != SVGA_CB_STATUS_COMPLETED)
|
---|
3214 | break;
|
---|
3215 |
|
---|
3216 | pu8Cmd += cbCmd;
|
---|
3217 | cbRemain -= cbCmd;
|
---|
3218 | }
|
---|
3219 |
|
---|
3220 | Assert(cbRemain <= cbCommands);
|
---|
3221 | *poffNextCmd = cbCommands - cbRemain;
|
---|
3222 | return CBstatus;
|
---|
3223 | }
|
---|
3224 |
|
---|
3225 |
|
---|
3226 | /** Submits a device context command buffer for synchronous processing.
|
---|
3227 | *
|
---|
3228 | * @param pDevIns The device instance.
|
---|
3229 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3230 | * @param ppCmdBuf Pointer to the command buffer pointer.
|
---|
3231 | * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
|
---|
3232 | * @param poffNextCmd Where to store the offset of the first unprocessed command.
|
---|
3233 | * @return SVGACBStatus code.
|
---|
3234 | * @thread EMT
|
---|
3235 | */
|
---|
3236 | static SVGACBStatus vmsvgaR3CmdBufSubmitDC(PPDMDEVINS pDevIns, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf, uint32_t *poffNextCmd)
|
---|
3237 | {
|
---|
3238 | /* Synchronously process the device context commands. */
|
---|
3239 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3240 | return vmsvgaR3CmdBufProcessDC(pDevIns, pSvgaR3State, (*ppCmdBuf)->pvCommands, (*ppCmdBuf)->hdr.length, poffNextCmd);
|
---|
3241 | }
|
---|
3242 |
|
---|
3243 | /** Submits a command buffer for asynchronous processing by the FIFO thread.
|
---|
3244 | *
|
---|
3245 | * @param pDevIns The device instance.
|
---|
3246 | * @param pThis The shared VGA/VMSVGA state.
|
---|
3247 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3248 | * @param ppCmdBuf Pointer to the command buffer pointer.
|
---|
3249 | * The function can set the command buffer pointer to NULL to prevent deallocation by the caller.
|
---|
3250 | * @return SVGACBStatus code.
|
---|
3251 | * @thread EMT
|
---|
3252 | */
|
---|
3253 | static SVGACBStatus vmsvgaR3CmdBufSubmitCtx(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGACMDBUF *ppCmdBuf)
|
---|
3254 | {
|
---|
3255 | /* Command buffer submission. */
|
---|
3256 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3257 |
|
---|
3258 | SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
|
---|
3259 |
|
---|
3260 | PVMSVGACMDBUF const pCmdBuf = *ppCmdBuf;
|
---|
3261 | PVMSVGACMDBUFCTX const pCmdBufCtx = pCmdBuf->pCmdBufCtx;
|
---|
3262 |
|
---|
3263 | int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
|
---|
3264 | AssertRC(rc);
|
---|
3265 |
|
---|
3266 | if (RT_LIKELY(pCmdBufCtx->cSubmitted < SVGA_CB_MAX_QUEUED_PER_CONTEXT))
|
---|
3267 | {
|
---|
3268 | RTListAppend(&pCmdBufCtx->listSubmitted, &pCmdBuf->nodeBuffer);
|
---|
3269 | ++pCmdBufCtx->cSubmitted;
|
---|
3270 | *ppCmdBuf = NULL; /* Consume the buffer. */
|
---|
3271 | ASMAtomicWriteU32(&pThisCC->svga.pSvgaR3State->fCmdBuf, 1);
|
---|
3272 | }
|
---|
3273 | else
|
---|
3274 | CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
|
---|
3275 |
|
---|
3276 | RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
|
---|
3277 |
|
---|
3278 | /* Inform the FIFO thread. */
|
---|
3279 | if (*ppCmdBuf == NULL)
|
---|
3280 | PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
3281 |
|
---|
3282 | return CBstatus;
|
---|
3283 | }
|
---|
3284 |
|
---|
3285 |
|
---|
3286 | /** SVGA_REG_COMMAND_LOW write handler.
|
---|
3287 | * Submits a command buffer to the FIFO thread or processes a device context command.
|
---|
3288 | *
|
---|
3289 | * @param pDevIns The device instance.
|
---|
3290 | * @param pThis The shared VGA/VMSVGA state.
|
---|
3291 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3292 | * @param GCPhysCB Guest physical address of the command buffer header.
|
---|
3293 | * @param CBCtx Context the command buffer is submitted to.
|
---|
3294 | * @thread EMT
|
---|
3295 | */
|
---|
3296 | static void vmsvgaR3CmdBufSubmit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS GCPhysCB, SVGACBContext CBCtx)
|
---|
3297 | {
|
---|
3298 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3299 |
|
---|
3300 | SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
|
---|
3301 | uint32_t offNextCmd = 0;
|
---|
3302 | uint32_t fIRQ = 0;
|
---|
3303 |
|
---|
3304 | /* Get the context if the device has the capability. */
|
---|
3305 | PVMSVGACMDBUFCTX pCmdBufCtx = NULL;
|
---|
3306 | if (pThis->svga.u32DeviceCaps & SVGA_CAP_COMMAND_BUFFERS)
|
---|
3307 | {
|
---|
3308 | if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
|
---|
3309 | pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[CBCtx];
|
---|
3310 | else if (CBCtx == SVGA_CB_CONTEXT_DEVICE)
|
---|
3311 | pCmdBufCtx = &pSvgaR3State->CmdBufCtxDC;
|
---|
3312 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3313 | }
|
---|
3314 |
|
---|
3315 | /* Allocate a new command buffer. */
|
---|
3316 | PVMSVGACMDBUF pCmdBuf = vmsvgaR3CmdBufAlloc(pCmdBufCtx);
|
---|
3317 | if (RT_LIKELY(pCmdBuf))
|
---|
3318 | {
|
---|
3319 | pCmdBuf->GCPhysCB = GCPhysCB;
|
---|
3320 |
|
---|
3321 | int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCB, &pCmdBuf->hdr, sizeof(pCmdBuf->hdr));
|
---|
3322 | if (RT_SUCCESS(rc))
|
---|
3323 | {
|
---|
3324 | /* Verify the command buffer header. */
|
---|
3325 | if (RT_LIKELY( pCmdBuf->hdr.status == SVGA_CB_STATUS_NONE
|
---|
3326 | && (pCmdBuf->hdr.flags & ~(SVGA_CB_FLAG_NO_IRQ | SVGA_CB_FLAG_DX_CONTEXT)) == 0 /* No unexpected flags. */
|
---|
3327 | && pCmdBuf->hdr.length <= SVGA_CB_MAX_SIZE))
|
---|
3328 | {
|
---|
3329 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3330 |
|
---|
3331 | /* Read the command buffer content. */
|
---|
3332 | pCmdBuf->pvCommands = RTMemAlloc(pCmdBuf->hdr.length);
|
---|
3333 | if (pCmdBuf->pvCommands)
|
---|
3334 | {
|
---|
3335 | RTGCPHYS const GCPhysCmd = (RTGCPHYS)pCmdBuf->hdr.ptr.pa;
|
---|
3336 | rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, pCmdBuf->pvCommands, pCmdBuf->hdr.length);
|
---|
3337 | if (RT_SUCCESS(rc))
|
---|
3338 | {
|
---|
3339 | /* Submit the buffer. Device context buffers will be processed synchronously. */
|
---|
3340 | if (RT_LIKELY(CBCtx < RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs)))
|
---|
3341 | /* This usually processes the CB async and sets pCmbBuf to NULL. */
|
---|
3342 | CBstatus = vmsvgaR3CmdBufSubmitCtx(pDevIns, pThis, pThisCC, &pCmdBuf);
|
---|
3343 | else
|
---|
3344 | CBstatus = vmsvgaR3CmdBufSubmitDC(pDevIns, pThisCC, &pCmdBuf, &offNextCmd);
|
---|
3345 | }
|
---|
3346 | else
|
---|
3347 | {
|
---|
3348 | ASSERT_GUEST_MSG_FAILED(("Failed to read commands at %RGp\n", GCPhysCmd));
|
---|
3349 | CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
|
---|
3350 | fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
|
---|
3351 | }
|
---|
3352 | }
|
---|
3353 | else
|
---|
3354 | {
|
---|
3355 | /* No memory for commands. */
|
---|
3356 | CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
|
---|
3357 | }
|
---|
3358 | }
|
---|
3359 | else
|
---|
3360 | {
|
---|
3361 | ASSERT_GUEST_MSG_FAILED(("Invalid buffer header\n"));
|
---|
3362 | CBstatus = SVGA_CB_STATUS_CB_HEADER_ERROR;
|
---|
3363 | fIRQ = SVGA_IRQFLAG_ERROR | SVGA_IRQFLAG_COMMAND_BUFFER;
|
---|
3364 | }
|
---|
3365 | }
|
---|
3366 | else
|
---|
3367 | {
|
---|
3368 | LogFunc(("Failed to read buffer header at %RGp\n", GCPhysCB));
|
---|
3369 | ASSERT_GUEST_FAILED();
|
---|
3370 | /* Do not attempt to write the status. */
|
---|
3371 | }
|
---|
3372 |
|
---|
3373 | /* Free the buffer if pfnCmdBufSubmit did not consume it. */
|
---|
3374 | vmsvgaR3CmdBufFree(pCmdBuf);
|
---|
3375 | }
|
---|
3376 | else
|
---|
3377 | {
|
---|
3378 | LogFunc(("Can't allocate buffer for context id %#x\n", CBCtx));
|
---|
3379 | ASSERT_GUEST_FAILED();
|
---|
3380 | CBstatus = SVGA_CB_STATUS_QUEUE_FULL;
|
---|
3381 | }
|
---|
3382 |
|
---|
3383 | if (CBstatus != SVGA_CB_STATUS_NONE)
|
---|
3384 | {
|
---|
3385 | LogFunc(("Write status %#x, offNextCmd %#x (of %#x), fIRQ %#x\n", CBstatus, offNextCmd, pCmdBuf ? pCmdBuf->hdr.length : 0, fIRQ));
|
---|
3386 | vmsvgaR3CmdBufWriteStatus(pDevIns, GCPhysCB, CBstatus, offNextCmd);
|
---|
3387 | if (fIRQ)
|
---|
3388 | vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, fIRQ);
|
---|
3389 | }
|
---|
3390 | }
|
---|
3391 |
|
---|
3392 |
|
---|
3393 | /** Checks if there are some buffers to be processed.
|
---|
3394 | *
|
---|
3395 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3396 | * @return true if buffers must be processed.
|
---|
3397 | * @thread FIFO
|
---|
3398 | */
|
---|
3399 | static bool vmsvgaR3CmdBufHasWork(PVGASTATECC pThisCC)
|
---|
3400 | {
|
---|
3401 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3402 | return RT_BOOL(ASMAtomicReadU32(&pSvgaR3State->fCmdBuf));
|
---|
3403 | }
|
---|
3404 |
|
---|
3405 |
|
---|
3406 | /** Processes a command buffer.
|
---|
3407 | *
|
---|
3408 | * @param pDevIns The device instance.
|
---|
3409 | * @param pThis The shared VGA/VMSVGA state.
|
---|
3410 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3411 | * @param idDXContext VGPU10 DX context of the commands or SVGA3D_INVALID_ID if they are not for a specific context.
|
---|
3412 | * @param pvCommands Pointer to the command buffer.
|
---|
3413 | * @param cbCommands Size of the command buffer.
|
---|
3414 | * @param poffNextCmd Where to store the offset of the first unprocessed command.
|
---|
3415 | * @param pu32IrqStatus Where to store SVGA_IRQFLAG_ if the IRQ is generated by the last command in the buffer.
|
---|
3416 | * @return SVGACBStatus code.
|
---|
3417 | * @thread FIFO
|
---|
3418 | */
|
---|
3419 | static SVGACBStatus vmsvgaR3CmdBufProcessCommands(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t idDXContext, void const *pvCommands, uint32_t cbCommands, uint32_t *poffNextCmd, uint32_t *pu32IrqStatus)
|
---|
3420 | {
|
---|
3421 | # ifndef VBOX_WITH_VMSVGA3D
|
---|
3422 | RT_NOREF(idDXContext);
|
---|
3423 | # endif
|
---|
3424 | SVGACBStatus CBstatus = SVGA_CB_STATUS_COMPLETED;
|
---|
3425 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3426 |
|
---|
3427 | uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
|
---|
3428 |
|
---|
3429 | uint8_t const *pu8Cmd = (uint8_t *)pvCommands;
|
---|
3430 | uint32_t cbRemain = cbCommands;
|
---|
3431 | while (cbRemain)
|
---|
3432 | {
|
---|
3433 | /* Command identifier is a 32 bit value. */
|
---|
3434 | if (cbRemain < sizeof(uint32_t))
|
---|
3435 | {
|
---|
3436 | CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3437 | break;
|
---|
3438 | }
|
---|
3439 |
|
---|
3440 | /* Fetch the command id.
|
---|
3441 | * 'cmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
|
---|
3442 | * warning. Because we support some obsolete and deprecated commands, which are not included in
|
---|
3443 | * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
|
---|
3444 | */
|
---|
3445 | uint32_t const cmdId = *(uint32_t *)pu8Cmd;
|
---|
3446 | uint32_t cbCmd = sizeof(uint32_t);
|
---|
3447 |
|
---|
3448 | LogFlowFunc(("[cid=%d] %s %d\n", (int32_t)idDXContext, vmsvgaR3FifoCmdToString(cmdId), cmdId));
|
---|
3449 | # ifdef LOG_ENABLED
|
---|
3450 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3451 | if (SVGA_3D_CMD_BASE <= cmdId && cmdId < SVGA_3D_CMD_MAX)
|
---|
3452 | {
|
---|
3453 | SVGA3dCmdHeader const *header = (SVGA3dCmdHeader *)pu8Cmd;
|
---|
3454 | svga_dump_command(cmdId, (uint8_t *)&header[1], header->size);
|
---|
3455 | }
|
---|
3456 | else if (cmdId == SVGA_CMD_FENCE)
|
---|
3457 | {
|
---|
3458 | Log7(("\tSVGA_CMD_FENCE\n"));
|
---|
3459 | Log7(("\t\t0x%08x\n", ((uint32_t *)pu8Cmd)[1]));
|
---|
3460 | }
|
---|
3461 | # endif
|
---|
3462 | # endif
|
---|
3463 |
|
---|
3464 | /* At the end of the switch cbCmd is equal to the total length of the command including the cmdId.
|
---|
3465 | * I.e. pu8Cmd + cbCmd must point to the next command.
|
---|
3466 | * However if CBstatus is set to anything but SVGA_CB_STATUS_COMPLETED in the switch, then
|
---|
3467 | * the cbCmd value is ignored (and pu8Cmd still points to the failed command).
|
---|
3468 | */
|
---|
3469 | /** @todo This code is very similar to the FIFO loop command processing. Think about merging. */
|
---|
3470 | switch (cmdId)
|
---|
3471 | {
|
---|
3472 | case SVGA_CMD_INVALID_CMD:
|
---|
3473 | {
|
---|
3474 | /* Nothing to do. */
|
---|
3475 | STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdInvalidCmd);
|
---|
3476 | break;
|
---|
3477 | }
|
---|
3478 |
|
---|
3479 | case SVGA_CMD_FENCE:
|
---|
3480 | {
|
---|
3481 | SVGAFifoCmdFence *pCmd = (SVGAFifoCmdFence *)&pu8Cmd[cbCmd];
|
---|
3482 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3483 | STAM_REL_COUNTER_INC(&pSvgaR3State->StatR3CmdFence);
|
---|
3484 | Log(("SVGA_CMD_FENCE %#x\n", pCmd->fence));
|
---|
3485 |
|
---|
3486 | uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
|
---|
3487 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
|
---|
3488 | {
|
---|
3489 | pFIFO[SVGA_FIFO_FENCE] = pCmd->fence;
|
---|
3490 |
|
---|
3491 | if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
|
---|
3492 | {
|
---|
3493 | Log(("any fence irq\n"));
|
---|
3494 | *pu32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
|
---|
3495 | }
|
---|
3496 | else if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
|
---|
3497 | && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
|
---|
3498 | && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmd->fence)
|
---|
3499 | {
|
---|
3500 | Log(("fence goal reached irq (fence=%#x)\n", pCmd->fence));
|
---|
3501 | *pu32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
|
---|
3502 | }
|
---|
3503 | }
|
---|
3504 | else
|
---|
3505 | Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
|
---|
3506 | break;
|
---|
3507 | }
|
---|
3508 |
|
---|
3509 | case SVGA_CMD_UPDATE:
|
---|
3510 | {
|
---|
3511 | SVGAFifoCmdUpdate *pCmd = (SVGAFifoCmdUpdate *)&pu8Cmd[cbCmd];
|
---|
3512 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3513 | vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
|
---|
3514 | break;
|
---|
3515 | }
|
---|
3516 |
|
---|
3517 | case SVGA_CMD_UPDATE_VERBOSE:
|
---|
3518 | {
|
---|
3519 | SVGAFifoCmdUpdateVerbose *pCmd = (SVGAFifoCmdUpdateVerbose *)&pu8Cmd[cbCmd];
|
---|
3520 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3521 | vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
|
---|
3522 | break;
|
---|
3523 | }
|
---|
3524 |
|
---|
3525 | case SVGA_CMD_DEFINE_CURSOR:
|
---|
3526 | {
|
---|
3527 | /* Followed by bitmap data. */
|
---|
3528 | SVGAFifoCmdDefineCursor *pCmd = (SVGAFifoCmdDefineCursor *)&pu8Cmd[cbCmd];
|
---|
3529 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3530 |
|
---|
3531 | /* Figure out the size of the bitmap data. */
|
---|
3532 | ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3533 | ASSERT_GUEST_STMT_BREAK(pCmd->andMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3534 | ASSERT_GUEST_STMT_BREAK(pCmd->xorMaskDepth <= 32, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3535 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3536 |
|
---|
3537 | uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
|
---|
3538 | uint32_t const cbAndMask = cbAndLine * pCmd->height;
|
---|
3539 | uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
|
---|
3540 | uint32_t const cbXorMask = cbXorLine * pCmd->height;
|
---|
3541 |
|
---|
3542 | VMSVGA_INC_CMD_SIZE_BREAK(cbAndMask + cbXorMask);
|
---|
3543 | vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
|
---|
3544 | break;
|
---|
3545 | }
|
---|
3546 |
|
---|
3547 | case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
---|
3548 | {
|
---|
3549 | /* Followed by bitmap data. */
|
---|
3550 | SVGAFifoCmdDefineAlphaCursor *pCmd = (SVGAFifoCmdDefineAlphaCursor *)&pu8Cmd[cbCmd];
|
---|
3551 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3552 |
|
---|
3553 | /* Figure out the size of the bitmap data. */
|
---|
3554 | ASSERT_GUEST_STMT_BREAK(pCmd->height < 2048 && pCmd->width < 2048, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3555 |
|
---|
3556 | VMSVGA_INC_CMD_SIZE_BREAK(pCmd->width * pCmd->height * sizeof(uint32_t)); /* 32-bit BRGA format */
|
---|
3557 | vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
|
---|
3558 | break;
|
---|
3559 | }
|
---|
3560 |
|
---|
3561 | case SVGA_CMD_MOVE_CURSOR:
|
---|
3562 | {
|
---|
3563 | /* Deprecated; there should be no driver which *requires* this command. However, if
|
---|
3564 | * we do ecncounter this command, it might be useful to not get the FIFO completely out of
|
---|
3565 | * alignment.
|
---|
3566 | * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
|
---|
3567 | */
|
---|
3568 | SVGAFifoCmdMoveCursor *pCmd = (SVGAFifoCmdMoveCursor *)&pu8Cmd[cbCmd];
|
---|
3569 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3570 | vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
|
---|
3571 | break;
|
---|
3572 | }
|
---|
3573 |
|
---|
3574 | case SVGA_CMD_DISPLAY_CURSOR:
|
---|
3575 | {
|
---|
3576 | /* Deprecated; there should be no driver which *requires* this command. However, if
|
---|
3577 | * we do ecncounter this command, it might be useful to not get the FIFO completely out of
|
---|
3578 | * alignment.
|
---|
3579 | * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
|
---|
3580 | */
|
---|
3581 | SVGAFifoCmdDisplayCursor *pCmd = (SVGAFifoCmdDisplayCursor *)&pu8Cmd[cbCmd];
|
---|
3582 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3583 | vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
|
---|
3584 | break;
|
---|
3585 | }
|
---|
3586 |
|
---|
3587 | case SVGA_CMD_RECT_FILL:
|
---|
3588 | {
|
---|
3589 | SVGAFifoCmdRectFill *pCmd = (SVGAFifoCmdRectFill *)&pu8Cmd[cbCmd];
|
---|
3590 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3591 | vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
|
---|
3592 | break;
|
---|
3593 | }
|
---|
3594 |
|
---|
3595 | case SVGA_CMD_RECT_COPY:
|
---|
3596 | {
|
---|
3597 | SVGAFifoCmdRectCopy *pCmd = (SVGAFifoCmdRectCopy *)&pu8Cmd[cbCmd];
|
---|
3598 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3599 | vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
|
---|
3600 | break;
|
---|
3601 | }
|
---|
3602 |
|
---|
3603 | case SVGA_CMD_RECT_ROP_COPY:
|
---|
3604 | {
|
---|
3605 | SVGAFifoCmdRectRopCopy *pCmd = (SVGAFifoCmdRectRopCopy *)&pu8Cmd[cbCmd];
|
---|
3606 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3607 | vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
|
---|
3608 | break;
|
---|
3609 | }
|
---|
3610 |
|
---|
3611 | case SVGA_CMD_ESCAPE:
|
---|
3612 | {
|
---|
3613 | /* Followed by 'size' bytes of data. */
|
---|
3614 | SVGAFifoCmdEscape *pCmd = (SVGAFifoCmdEscape *)&pu8Cmd[cbCmd];
|
---|
3615 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3616 |
|
---|
3617 | ASSERT_GUEST_STMT_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape), CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3618 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3619 |
|
---|
3620 | VMSVGA_INC_CMD_SIZE_BREAK(pCmd->size);
|
---|
3621 | vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
|
---|
3622 | break;
|
---|
3623 | }
|
---|
3624 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3625 | case SVGA_CMD_DEFINE_GMR2:
|
---|
3626 | {
|
---|
3627 | SVGAFifoCmdDefineGMR2 *pCmd = (SVGAFifoCmdDefineGMR2 *)&pu8Cmd[cbCmd];
|
---|
3628 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3629 | vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
|
---|
3630 | break;
|
---|
3631 | }
|
---|
3632 |
|
---|
3633 | case SVGA_CMD_REMAP_GMR2:
|
---|
3634 | {
|
---|
3635 | /* Followed by page descriptors or guest ptr. */
|
---|
3636 | SVGAFifoCmdRemapGMR2 *pCmd = (SVGAFifoCmdRemapGMR2 *)&pu8Cmd[cbCmd];
|
---|
3637 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3638 |
|
---|
3639 | /* Calculate the size of what comes after next and fetch it. */
|
---|
3640 | uint32_t cbMore = 0;
|
---|
3641 | if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
|
---|
3642 | cbMore = sizeof(SVGAGuestPtr);
|
---|
3643 | else
|
---|
3644 | {
|
---|
3645 | uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
|
---|
3646 | if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
|
---|
3647 | {
|
---|
3648 | cbMore = cbPageDesc;
|
---|
3649 | pCmd->numPages = 1;
|
---|
3650 | }
|
---|
3651 | else
|
---|
3652 | {
|
---|
3653 | ASSERT_GUEST_STMT_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3654 | cbMore = cbPageDesc * pCmd->numPages;
|
---|
3655 | }
|
---|
3656 | }
|
---|
3657 | VMSVGA_INC_CMD_SIZE_BREAK(cbMore);
|
---|
3658 | vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
|
---|
3659 | # ifdef DEBUG_GMR_ACCESS
|
---|
3660 | VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
|
---|
3661 | # endif
|
---|
3662 | break;
|
---|
3663 | }
|
---|
3664 | # endif /* VBOX_WITH_VMSVGA3D */
|
---|
3665 | case SVGA_CMD_DEFINE_SCREEN:
|
---|
3666 | {
|
---|
3667 | /* The size of this command is specified by the guest and depends on capabilities. */
|
---|
3668 | SVGAFifoCmdDefineScreen *pCmd = (SVGAFifoCmdDefineScreen *)&pu8Cmd[cbCmd];
|
---|
3669 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(pCmd->screen.structSize));
|
---|
3670 | ASSERT_GUEST_STMT_BREAK(pCmd->screen.structSize < pThis->svga.cbFIFO, CBstatus = SVGA_CB_STATUS_COMMAND_ERROR);
|
---|
3671 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3672 |
|
---|
3673 | VMSVGA_INC_CMD_SIZE_BREAK(RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize) - sizeof(pCmd->screen.structSize));
|
---|
3674 | vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
|
---|
3675 | break;
|
---|
3676 | }
|
---|
3677 |
|
---|
3678 | case SVGA_CMD_DESTROY_SCREEN:
|
---|
3679 | {
|
---|
3680 | SVGAFifoCmdDestroyScreen *pCmd = (SVGAFifoCmdDestroyScreen *)&pu8Cmd[cbCmd];
|
---|
3681 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3682 | vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
|
---|
3683 | break;
|
---|
3684 | }
|
---|
3685 |
|
---|
3686 | case SVGA_CMD_DEFINE_GMRFB:
|
---|
3687 | {
|
---|
3688 | SVGAFifoCmdDefineGMRFB *pCmd = (SVGAFifoCmdDefineGMRFB *)&pu8Cmd[cbCmd];
|
---|
3689 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3690 | vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
|
---|
3691 | break;
|
---|
3692 | }
|
---|
3693 |
|
---|
3694 | case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
|
---|
3695 | {
|
---|
3696 | SVGAFifoCmdBlitGMRFBToScreen *pCmd = (SVGAFifoCmdBlitGMRFBToScreen *)&pu8Cmd[cbCmd];
|
---|
3697 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3698 | vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
|
---|
3699 | break;
|
---|
3700 | }
|
---|
3701 |
|
---|
3702 | case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
|
---|
3703 | {
|
---|
3704 | SVGAFifoCmdBlitScreenToGMRFB *pCmd = (SVGAFifoCmdBlitScreenToGMRFB *)&pu8Cmd[cbCmd];
|
---|
3705 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3706 | vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
|
---|
3707 | break;
|
---|
3708 | }
|
---|
3709 |
|
---|
3710 | case SVGA_CMD_ANNOTATION_FILL:
|
---|
3711 | {
|
---|
3712 | SVGAFifoCmdAnnotationFill *pCmd = (SVGAFifoCmdAnnotationFill *)&pu8Cmd[cbCmd];
|
---|
3713 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3714 | vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
|
---|
3715 | break;
|
---|
3716 | }
|
---|
3717 |
|
---|
3718 | case SVGA_CMD_ANNOTATION_COPY:
|
---|
3719 | {
|
---|
3720 | SVGAFifoCmdAnnotationCopy *pCmd = (SVGAFifoCmdAnnotationCopy *)&pu8Cmd[cbCmd];
|
---|
3721 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pCmd));
|
---|
3722 | vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
|
---|
3723 | break;
|
---|
3724 | }
|
---|
3725 |
|
---|
3726 | default:
|
---|
3727 | {
|
---|
3728 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3729 | if ( cmdId >= SVGA_3D_CMD_BASE
|
---|
3730 | && cmdId < SVGA_3D_CMD_MAX)
|
---|
3731 | {
|
---|
3732 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
3733 |
|
---|
3734 | /* All 3d commands start with a common header, which defines the identifier and the size
|
---|
3735 | * of the command. The identifier has been already read. Fetch the size.
|
---|
3736 | */
|
---|
3737 | uint32_t const *pcbMore = (uint32_t const *)&pu8Cmd[cbCmd];
|
---|
3738 | VMSVGA_INC_CMD_SIZE_BREAK(sizeof(*pcbMore));
|
---|
3739 | VMSVGA_INC_CMD_SIZE_BREAK(*pcbMore);
|
---|
3740 | if (RT_LIKELY(pThis->svga.f3DEnabled))
|
---|
3741 | { /* likely */ }
|
---|
3742 | else
|
---|
3743 | {
|
---|
3744 | LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", cmdId));
|
---|
3745 | break;
|
---|
3746 | }
|
---|
3747 |
|
---|
3748 | /* Command data begins after the 32 bit command length. */
|
---|
3749 | int rc = vmsvgaR3Process3dCmd(pThis, pThisCC, idDXContext, (SVGAFifo3dCmdId)cmdId, *pcbMore, pcbMore + 1);
|
---|
3750 | if (RT_SUCCESS(rc))
|
---|
3751 | { /* likely */ }
|
---|
3752 | else
|
---|
3753 | {
|
---|
3754 | CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3755 | break;
|
---|
3756 | }
|
---|
3757 | }
|
---|
3758 | else
|
---|
3759 | # endif /* VBOX_WITH_VMSVGA3D */
|
---|
3760 | {
|
---|
3761 | /* Unsupported command. */
|
---|
3762 | STAM_REL_COUNTER_INC(&pSvgaR3State->StatFifoUnkCmds);
|
---|
3763 | ASSERT_GUEST_MSG_FAILED(("cmdId=%d\n", cmdId));
|
---|
3764 | LogRelMax(16, ("VMSVGA: unsupported command %d\n", cmdId));
|
---|
3765 | CBstatus = SVGA_CB_STATUS_COMMAND_ERROR;
|
---|
3766 | break;
|
---|
3767 | }
|
---|
3768 | }
|
---|
3769 | }
|
---|
3770 |
|
---|
3771 | if (CBstatus != SVGA_CB_STATUS_COMPLETED)
|
---|
3772 | break;
|
---|
3773 |
|
---|
3774 | pu8Cmd += cbCmd;
|
---|
3775 | cbRemain -= cbCmd;
|
---|
3776 |
|
---|
3777 | /* If this is not the last command in the buffer, then generate IRQ, if required.
|
---|
3778 | * This avoids a double call to vmsvgaR3CmdBufRaiseIRQ if FENCE is the last command
|
---|
3779 | * in the buffer (usually the case).
|
---|
3780 | */
|
---|
3781 | if (RT_LIKELY(!(cbRemain && *pu32IrqStatus)))
|
---|
3782 | { /* likely */ }
|
---|
3783 | else
|
---|
3784 | {
|
---|
3785 | vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, *pu32IrqStatus);
|
---|
3786 | *pu32IrqStatus = 0;
|
---|
3787 | }
|
---|
3788 | }
|
---|
3789 |
|
---|
3790 | Assert(cbRemain <= cbCommands);
|
---|
3791 | *poffNextCmd = cbCommands - cbRemain;
|
---|
3792 | return CBstatus;
|
---|
3793 | }
|
---|
3794 |
|
---|
3795 |
|
---|
3796 | /** Process command buffers.
|
---|
3797 | *
|
---|
3798 | * @param pDevIns The device instance.
|
---|
3799 | * @param pThis The shared VGA/VMSVGA state.
|
---|
3800 | * @param pThisCC The VGA/VMSVGA state for the current context.
|
---|
3801 | * @param pThread Handle of the FIFO thread.
|
---|
3802 | * @thread FIFO
|
---|
3803 | */
|
---|
3804 | static void vmsvgaR3CmdBufProcessBuffers(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PPDMTHREAD pThread)
|
---|
3805 | {
|
---|
3806 | PVMSVGAR3STATE const pSvgaR3State = pThisCC->svga.pSvgaR3State;
|
---|
3807 |
|
---|
3808 | for (;;)
|
---|
3809 | {
|
---|
3810 | if (pThread->enmState != PDMTHREADSTATE_RUNNING)
|
---|
3811 | break;
|
---|
3812 |
|
---|
3813 | /* See if there is a submitted buffer. */
|
---|
3814 | PVMSVGACMDBUF pCmdBuf = NULL;
|
---|
3815 |
|
---|
3816 | int rc = RTCritSectEnter(&pSvgaR3State->CritSectCmdBuf);
|
---|
3817 | AssertRC(rc);
|
---|
3818 |
|
---|
3819 | /* It seems that a higher queue index has a higher priority.
|
---|
3820 | * See SVGACBContext in svga_reg.h from latest vmwgfx Linux driver.
|
---|
3821 | */
|
---|
3822 | for (unsigned i = RT_ELEMENTS(pSvgaR3State->apCmdBufCtxs); i > 0; --i)
|
---|
3823 | {
|
---|
3824 | PVMSVGACMDBUFCTX pCmdBufCtx = pSvgaR3State->apCmdBufCtxs[i - 1];
|
---|
3825 | if (pCmdBufCtx)
|
---|
3826 | {
|
---|
3827 | pCmdBuf = RTListRemoveFirst(&pCmdBufCtx->listSubmitted, VMSVGACMDBUF, nodeBuffer);
|
---|
3828 | if (pCmdBuf)
|
---|
3829 | {
|
---|
3830 | Assert(pCmdBufCtx->cSubmitted > 0);
|
---|
3831 | --pCmdBufCtx->cSubmitted;
|
---|
3832 | break;
|
---|
3833 | }
|
---|
3834 | }
|
---|
3835 | }
|
---|
3836 |
|
---|
3837 | if (!pCmdBuf)
|
---|
3838 | {
|
---|
3839 | ASMAtomicWriteU32(&pSvgaR3State->fCmdBuf, 0);
|
---|
3840 | RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
|
---|
3841 | break;
|
---|
3842 | }
|
---|
3843 |
|
---|
3844 | RTCritSectLeave(&pSvgaR3State->CritSectCmdBuf);
|
---|
3845 |
|
---|
3846 | SVGACBStatus CBstatus = SVGA_CB_STATUS_NONE;
|
---|
3847 | uint32_t offNextCmd = 0;
|
---|
3848 | uint32_t u32IrqStatus = 0;
|
---|
3849 | uint32_t const idDXContext = RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_DX_CONTEXT)
|
---|
3850 | ? pCmdBuf->hdr.dxContext
|
---|
3851 | : SVGA3D_INVALID_ID;
|
---|
3852 | /* Process one buffer. */
|
---|
3853 | CBstatus = vmsvgaR3CmdBufProcessCommands(pDevIns, pThis, pThisCC, idDXContext, pCmdBuf->pvCommands, pCmdBuf->hdr.length, &offNextCmd, &u32IrqStatus);
|
---|
3854 |
|
---|
3855 | if (!RT_BOOL(pCmdBuf->hdr.flags & SVGA_CB_FLAG_NO_IRQ))
|
---|
3856 | u32IrqStatus |= SVGA_IRQFLAG_COMMAND_BUFFER;
|
---|
3857 | if (CBstatus == SVGA_CB_STATUS_COMMAND_ERROR)
|
---|
3858 | u32IrqStatus |= SVGA_IRQFLAG_ERROR;
|
---|
3859 |
|
---|
3860 | vmsvgaR3CmdBufWriteStatus(pDevIns, pCmdBuf->GCPhysCB, CBstatus, offNextCmd);
|
---|
3861 | if (u32IrqStatus)
|
---|
3862 | vmsvgaR3CmdBufRaiseIRQ(pDevIns, pThis, u32IrqStatus);
|
---|
3863 |
|
---|
3864 | vmsvgaR3CmdBufFree(pCmdBuf);
|
---|
3865 | }
|
---|
3866 | }
|
---|
3867 |
|
---|
3868 |
|
---|
3869 | /**
|
---|
3870 | * Worker for vmsvgaR3FifoThread that handles an external command.
|
---|
3871 | *
|
---|
3872 | * @param pDevIns The device instance.
|
---|
3873 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
3874 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
3875 | */
|
---|
3876 | static void vmsvgaR3FifoHandleExtCmd(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
3877 | {
|
---|
3878 | uint8_t uExtCmd = pThis->svga.u8FIFOExtCommand;
|
---|
3879 | switch (pThis->svga.u8FIFOExtCommand)
|
---|
3880 | {
|
---|
3881 | case VMSVGA_FIFO_EXTCMD_RESET:
|
---|
3882 | Log(("vmsvgaR3FifoLoop: reset the fifo thread.\n"));
|
---|
3883 | Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
|
---|
3884 |
|
---|
3885 | vmsvgaR3ResetScreens(pThis, pThisCC);
|
---|
3886 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3887 | if (pThis->svga.f3DEnabled)
|
---|
3888 | {
|
---|
3889 | /* The 3d subsystem must be reset from the fifo thread. */
|
---|
3890 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
3891 | pSVGAState->pFuncs3D->pfnReset(pThisCC);
|
---|
3892 | }
|
---|
3893 | # endif
|
---|
3894 | break;
|
---|
3895 |
|
---|
3896 | case VMSVGA_FIFO_EXTCMD_POWEROFF:
|
---|
3897 | Log(("vmsvgaR3FifoLoop: power off.\n"));
|
---|
3898 | Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
|
---|
3899 |
|
---|
3900 | /* The screens must be reset on the FIFO thread, because they may use 3D resources. */
|
---|
3901 | vmsvgaR3ResetScreens(pThis, pThisCC);
|
---|
3902 | break;
|
---|
3903 |
|
---|
3904 | case VMSVGA_FIFO_EXTCMD_TERMINATE:
|
---|
3905 | Log(("vmsvgaR3FifoLoop: terminate the fifo thread.\n"));
|
---|
3906 | Assert(pThisCC->svga.pvFIFOExtCmdParam == NULL);
|
---|
3907 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3908 | if (pThis->svga.f3DEnabled)
|
---|
3909 | {
|
---|
3910 | /* The 3d subsystem must be shut down from the fifo thread. */
|
---|
3911 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
3912 | pSVGAState->pFuncs3D->pfnTerminate(pThisCC);
|
---|
3913 | }
|
---|
3914 | # endif
|
---|
3915 | break;
|
---|
3916 |
|
---|
3917 | case VMSVGA_FIFO_EXTCMD_SAVESTATE:
|
---|
3918 | {
|
---|
3919 | Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
|
---|
3920 | PSSMHANDLE pSSM = (PSSMHANDLE)pThisCC->svga.pvFIFOExtCmdParam;
|
---|
3921 | AssertLogRelMsgBreak(RT_VALID_PTR(pSSM), ("pSSM=%p\n", pSSM));
|
---|
3922 | vmsvgaR3SaveExecFifo(pDevIns->pHlpR3, pThisCC, pSSM);
|
---|
3923 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3924 | if (pThis->svga.f3DEnabled)
|
---|
3925 | vmsvga3dSaveExec(pDevIns, pThisCC, pSSM);
|
---|
3926 | # endif
|
---|
3927 | break;
|
---|
3928 | }
|
---|
3929 |
|
---|
3930 | case VMSVGA_FIFO_EXTCMD_LOADSTATE:
|
---|
3931 | {
|
---|
3932 | Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
|
---|
3933 | PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThisCC->svga.pvFIFOExtCmdParam;
|
---|
3934 | AssertLogRelMsgBreak(RT_VALID_PTR(pLoadState), ("pLoadState=%p\n", pLoadState));
|
---|
3935 | vmsvgaR3LoadExecFifo(pDevIns->pHlpR3, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
|
---|
3936 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3937 | if (pThis->svga.f3DEnabled)
|
---|
3938 | {
|
---|
3939 | /* The following RT_OS_DARWIN code was in vmsvga3dLoadExec and therefore must be executed before each vmsvga3dLoadExec invocation. */
|
---|
3940 | # ifndef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA.cpp */
|
---|
3941 | /* Must initialize now as the recreation calls below rely on an initialized 3d subsystem. */
|
---|
3942 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
3943 | pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
|
---|
3944 | # endif
|
---|
3945 |
|
---|
3946 | vmsvga3dLoadExec(pDevIns, pThis, pThisCC, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
|
---|
3947 | }
|
---|
3948 | # endif
|
---|
3949 | break;
|
---|
3950 | }
|
---|
3951 |
|
---|
3952 | case VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS:
|
---|
3953 | {
|
---|
3954 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
3955 | uint32_t sid = (uint32_t)(uintptr_t)pThisCC->svga.pvFIFOExtCmdParam;
|
---|
3956 | Log(("vmsvgaR3FifoLoop: VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS sid=%#x\n", sid));
|
---|
3957 | vmsvga3dUpdateHeapBuffersForSurfaces(pThisCC, sid);
|
---|
3958 | # endif
|
---|
3959 | break;
|
---|
3960 | }
|
---|
3961 |
|
---|
3962 |
|
---|
3963 | default:
|
---|
3964 | AssertLogRelMsgFailed(("uExtCmd=%#x pvFIFOExtCmdParam=%p\n", uExtCmd, pThisCC->svga.pvFIFOExtCmdParam));
|
---|
3965 | break;
|
---|
3966 | }
|
---|
3967 |
|
---|
3968 | /*
|
---|
3969 | * Signal the end of the external command.
|
---|
3970 | */
|
---|
3971 | pThisCC->svga.pvFIFOExtCmdParam = NULL;
|
---|
3972 | pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
|
---|
3973 | ASMMemoryFence(); /* paranoia^2 */
|
---|
3974 | int rc = RTSemEventSignal(pThisCC->svga.hFIFOExtCmdSem);
|
---|
3975 | AssertLogRelRC(rc);
|
---|
3976 | }
|
---|
3977 |
|
---|
3978 | /**
|
---|
3979 | * Worker for vmsvgaR3Destruct, vmsvgaR3Reset, vmsvgaR3Save and vmsvgaR3Load for
|
---|
3980 | * doing a job on the FIFO thread (even when it's officially suspended).
|
---|
3981 | *
|
---|
3982 | * @returns VBox status code (fully asserted).
|
---|
3983 | * @param pDevIns The device instance.
|
---|
3984 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
3985 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
3986 | * @param uExtCmd The command to execute on the FIFO thread.
|
---|
3987 | * @param pvParam Pointer to command parameters.
|
---|
3988 | * @param cMsWait The time to wait for the command, given in
|
---|
3989 | * milliseconds.
|
---|
3990 | */
|
---|
3991 | static int vmsvgaR3RunExtCmdOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC,
|
---|
3992 | uint8_t uExtCmd, void *pvParam, RTMSINTERVAL cMsWait)
|
---|
3993 | {
|
---|
3994 | Assert(cMsWait >= RT_MS_1SEC * 5);
|
---|
3995 | AssertLogRelMsg(pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE,
|
---|
3996 | ("old=%d new=%d\n", pThis->svga.u8FIFOExtCommand, uExtCmd));
|
---|
3997 |
|
---|
3998 | int rc;
|
---|
3999 | PPDMTHREAD pThread = pThisCC->svga.pFIFOIOThread;
|
---|
4000 | PDMTHREADSTATE enmState = pThread->enmState;
|
---|
4001 | if (enmState == PDMTHREADSTATE_SUSPENDED)
|
---|
4002 | {
|
---|
4003 | /*
|
---|
4004 | * The thread is suspended, we have to temporarily wake it up so it can
|
---|
4005 | * perform the task.
|
---|
4006 | * (We ASSUME not racing code here, both wrt thread state and ext commands.)
|
---|
4007 | */
|
---|
4008 | Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=SUSPENDED\n", uExtCmd));
|
---|
4009 | /* Post the request. */
|
---|
4010 | pThis->svga.fFifoExtCommandWakeup = true;
|
---|
4011 | pThisCC->svga.pvFIFOExtCmdParam = pvParam;
|
---|
4012 | pThis->svga.u8FIFOExtCommand = uExtCmd;
|
---|
4013 | ASMMemoryFence(); /* paranoia^3 */
|
---|
4014 |
|
---|
4015 | /* Resume the thread. */
|
---|
4016 | rc = PDMDevHlpThreadResume(pDevIns, pThread);
|
---|
4017 | AssertLogRelRC(rc);
|
---|
4018 | if (RT_SUCCESS(rc))
|
---|
4019 | {
|
---|
4020 | /* Wait. Take care in case the semaphore was already posted (same as below). */
|
---|
4021 | rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
|
---|
4022 | if ( rc == VINF_SUCCESS
|
---|
4023 | && pThis->svga.u8FIFOExtCommand == uExtCmd)
|
---|
4024 | rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
|
---|
4025 | AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
|
---|
4026 | ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
|
---|
4027 |
|
---|
4028 | /* suspend the thread */
|
---|
4029 | pThis->svga.fFifoExtCommandWakeup = false;
|
---|
4030 | int rc2 = PDMDevHlpThreadSuspend(pDevIns, pThread);
|
---|
4031 | AssertLogRelRC(rc2);
|
---|
4032 | if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
|
---|
4033 | rc = rc2;
|
---|
4034 | }
|
---|
4035 | pThis->svga.fFifoExtCommandWakeup = false;
|
---|
4036 | pThisCC->svga.pvFIFOExtCmdParam = NULL;
|
---|
4037 | }
|
---|
4038 | else if (enmState == PDMTHREADSTATE_RUNNING)
|
---|
4039 | {
|
---|
4040 | /*
|
---|
4041 | * The thread is running, should only happen during reset and vmsvga3dsfc.
|
---|
4042 | * We ASSUME not racing code here, both wrt thread state and ext commands.
|
---|
4043 | */
|
---|
4044 | Log(("vmsvgaR3RunExtCmdOnFifoThread: uExtCmd=%d enmState=RUNNING\n", uExtCmd));
|
---|
4045 | Assert(uExtCmd == VMSVGA_FIFO_EXTCMD_RESET || uExtCmd == VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS || uExtCmd == VMSVGA_FIFO_EXTCMD_POWEROFF);
|
---|
4046 |
|
---|
4047 | /* Post the request. */
|
---|
4048 | pThisCC->svga.pvFIFOExtCmdParam = pvParam;
|
---|
4049 | pThis->svga.u8FIFOExtCommand = uExtCmd;
|
---|
4050 | ASMMemoryFence(); /* paranoia^2 */
|
---|
4051 | rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
4052 | AssertLogRelRC(rc);
|
---|
4053 |
|
---|
4054 | /* Wait. Take care in case the semaphore was already posted (same as above). */
|
---|
4055 | rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait);
|
---|
4056 | if ( rc == VINF_SUCCESS
|
---|
4057 | && pThis->svga.u8FIFOExtCommand == uExtCmd)
|
---|
4058 | rc = RTSemEventWait(pThisCC->svga.hFIFOExtCmdSem, cMsWait); /* it was already posted, retry the wait. */
|
---|
4059 | AssertLogRelMsg(pThis->svga.u8FIFOExtCommand != uExtCmd || RT_FAILURE_NP(rc),
|
---|
4060 | ("%#x %Rrc\n", pThis->svga.u8FIFOExtCommand, rc));
|
---|
4061 |
|
---|
4062 | pThisCC->svga.pvFIFOExtCmdParam = NULL;
|
---|
4063 | }
|
---|
4064 | else
|
---|
4065 | {
|
---|
4066 | /*
|
---|
4067 | * Something is wrong with the thread!
|
---|
4068 | */
|
---|
4069 | AssertLogRelMsgFailed(("uExtCmd=%d enmState=%d\n", uExtCmd, enmState));
|
---|
4070 | rc = VERR_INVALID_STATE;
|
---|
4071 | }
|
---|
4072 | return rc;
|
---|
4073 | }
|
---|
4074 |
|
---|
4075 |
|
---|
4076 | /**
|
---|
4077 | * Marks the FIFO non-busy, notifying any waiting EMTs.
|
---|
4078 | *
|
---|
4079 | * @param pDevIns The device instance.
|
---|
4080 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
4081 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
4082 | * @param pSVGAState Pointer to the ring-3 only SVGA state data.
|
---|
4083 | * @param offFifoMin The start byte offset of the command FIFO.
|
---|
4084 | */
|
---|
4085 | static void vmsvgaR3FifoSetNotBusy(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t offFifoMin)
|
---|
4086 | {
|
---|
4087 | ASMAtomicAndU32(&pThis->svga.fBusy, ~(VMSVGA_BUSY_F_FIFO | VMSVGA_BUSY_F_EMT_FORCE));
|
---|
4088 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
|
---|
4089 | vmsvgaHCSafeFifoBusyRegUpdate(pThis, pThisCC, pThis->svga.fBusy != 0);
|
---|
4090 |
|
---|
4091 | /* Wake up any waiting EMTs. */
|
---|
4092 | if (pSVGAState->cBusyDelayedEmts > 0)
|
---|
4093 | {
|
---|
4094 | # ifdef VMSVGA_USE_EMT_HALT_CODE
|
---|
4095 | PVM pVM = PDMDevHlpGetVM(pDevIns);
|
---|
4096 | VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
|
---|
4097 | if (idCpu != NIL_VMCPUID)
|
---|
4098 | {
|
---|
4099 | VMR3NotifyCpuDeviceReady(pVM, idCpu);
|
---|
4100 | while (idCpu-- > 0)
|
---|
4101 | if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
|
---|
4102 | VMR3NotifyCpuDeviceReady(pVM, idCpu);
|
---|
4103 | }
|
---|
4104 | # else
|
---|
4105 | int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
|
---|
4106 | AssertRC(rc2);
|
---|
4107 | # endif
|
---|
4108 | }
|
---|
4109 | }
|
---|
4110 |
|
---|
4111 | /**
|
---|
4112 | * Reads (more) payload into the command buffer.
|
---|
4113 | *
|
---|
4114 | * @returns pbBounceBuf on success
|
---|
4115 | * @retval (void *)1 if the thread was requested to stop.
|
---|
4116 | * @retval NULL on FIFO error.
|
---|
4117 | *
|
---|
4118 | * @param cbPayloadReq The number of bytes of payload requested.
|
---|
4119 | * @param pFIFO The FIFO.
|
---|
4120 | * @param offCurrentCmd The FIFO byte offset of the current command.
|
---|
4121 | * @param offFifoMin The start byte offset of the command FIFO.
|
---|
4122 | * @param offFifoMax The end byte offset of the command FIFO.
|
---|
4123 | * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
|
---|
4124 | * always sufficient size.
|
---|
4125 | * @param pcbAlreadyRead How much payload we've already read into the bounce
|
---|
4126 | * buffer. (We will NEVER re-read anything.)
|
---|
4127 | * @param pThread The calling PDM thread handle.
|
---|
4128 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
4129 | * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
|
---|
4130 | * statistics collection.
|
---|
4131 | * @param pDevIns The device instance.
|
---|
4132 | */
|
---|
4133 | static void *vmsvgaR3FifoGetCmdPayload(uint32_t cbPayloadReq, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
|
---|
4134 | uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
|
---|
4135 | uint8_t *pbBounceBuf, uint32_t *pcbAlreadyRead,
|
---|
4136 | PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState, PPDMDEVINS pDevIns)
|
---|
4137 | {
|
---|
4138 | Assert(pbBounceBuf);
|
---|
4139 | Assert(pcbAlreadyRead);
|
---|
4140 | Assert(offFifoMin < offFifoMax);
|
---|
4141 | Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
|
---|
4142 | Assert(offFifoMax <= pThis->svga.cbFIFO);
|
---|
4143 |
|
---|
4144 | /*
|
---|
4145 | * Check if the requested payload size has already been satisfied .
|
---|
4146 | * .
|
---|
4147 | * When called to read more, the caller is responsible for making sure the .
|
---|
4148 | * new command size (cbRequsted) never is smaller than what has already .
|
---|
4149 | * been read.
|
---|
4150 | */
|
---|
4151 | uint32_t cbAlreadyRead = *pcbAlreadyRead;
|
---|
4152 | if (cbPayloadReq <= cbAlreadyRead)
|
---|
4153 | {
|
---|
4154 | AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
|
---|
4155 | return pbBounceBuf;
|
---|
4156 | }
|
---|
4157 |
|
---|
4158 | /*
|
---|
4159 | * Commands bigger than the fifo buffer are invalid.
|
---|
4160 | */
|
---|
4161 | uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
|
---|
4162 | AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
|
---|
4163 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors),
|
---|
4164 | NULL);
|
---|
4165 |
|
---|
4166 | /*
|
---|
4167 | * Move offCurrentCmd past the command dword.
|
---|
4168 | */
|
---|
4169 | offCurrentCmd += sizeof(uint32_t);
|
---|
4170 | if (offCurrentCmd >= offFifoMax)
|
---|
4171 | offCurrentCmd = offFifoMin;
|
---|
4172 |
|
---|
4173 | /*
|
---|
4174 | * Do we have sufficient payload data available already?
|
---|
4175 | * The host should not read beyond [SVGA_FIFO_NEXT_CMD], therefore '>=' in the condition below.
|
---|
4176 | */
|
---|
4177 | uint32_t cbAfter, cbBefore;
|
---|
4178 | uint32_t offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
|
---|
4179 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
4180 | if (offNextCmd >= offCurrentCmd)
|
---|
4181 | {
|
---|
4182 | if (RT_LIKELY(offNextCmd < offFifoMax))
|
---|
4183 | cbAfter = offNextCmd - offCurrentCmd;
|
---|
4184 | else
|
---|
4185 | {
|
---|
4186 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
|
---|
4187 | LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
|
---|
4188 | offNextCmd, offFifoMin, offFifoMax));
|
---|
4189 | cbAfter = offFifoMax - offCurrentCmd;
|
---|
4190 | }
|
---|
4191 | cbBefore = 0;
|
---|
4192 | }
|
---|
4193 | else
|
---|
4194 | {
|
---|
4195 | cbAfter = offFifoMax - offCurrentCmd;
|
---|
4196 | if (offNextCmd >= offFifoMin)
|
---|
4197 | cbBefore = offNextCmd - offFifoMin;
|
---|
4198 | else
|
---|
4199 | {
|
---|
4200 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
|
---|
4201 | LogRelMax(16, ("vmsvgaR3FifoGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
|
---|
4202 | offNextCmd, offFifoMin, offFifoMax));
|
---|
4203 | cbBefore = 0;
|
---|
4204 | }
|
---|
4205 | }
|
---|
4206 | if (cbAfter + cbBefore < cbPayloadReq)
|
---|
4207 | {
|
---|
4208 | /*
|
---|
4209 | * Insufficient, must wait for it to arrive.
|
---|
4210 | */
|
---|
4211 | /** @todo Should clear the busy flag here to maybe encourage the guest to wake us up. */
|
---|
4212 | STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
|
---|
4213 | for (uint32_t i = 0;; i++)
|
---|
4214 | {
|
---|
4215 | if (pThread->enmState != PDMTHREADSTATE_RUNNING)
|
---|
4216 | {
|
---|
4217 | STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
|
---|
4218 | return (void *)(uintptr_t)1;
|
---|
4219 | }
|
---|
4220 | Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
|
---|
4221 | cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
|
---|
4222 |
|
---|
4223 | PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, i < 16 ? 1 : 2);
|
---|
4224 |
|
---|
4225 | offNextCmd = pFIFO[SVGA_FIFO_NEXT_CMD];
|
---|
4226 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
4227 | if (offNextCmd >= offCurrentCmd)
|
---|
4228 | {
|
---|
4229 | cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
|
---|
4230 | cbBefore = 0;
|
---|
4231 | }
|
---|
4232 | else
|
---|
4233 | {
|
---|
4234 | cbAfter = offFifoMax - offCurrentCmd;
|
---|
4235 | cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
|
---|
4236 | }
|
---|
4237 |
|
---|
4238 | if (cbAfter + cbBefore >= cbPayloadReq)
|
---|
4239 | break;
|
---|
4240 | }
|
---|
4241 | STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
|
---|
4242 | }
|
---|
4243 |
|
---|
4244 | /*
|
---|
4245 | * Copy out the memory and update what pcbAlreadyRead points to.
|
---|
4246 | */
|
---|
4247 | if (cbAfter >= cbPayloadReq)
|
---|
4248 | memcpy(pbBounceBuf + cbAlreadyRead,
|
---|
4249 | (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
|
---|
4250 | cbPayloadReq - cbAlreadyRead);
|
---|
4251 | else
|
---|
4252 | {
|
---|
4253 | LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
|
---|
4254 | if (cbAlreadyRead < cbAfter)
|
---|
4255 | {
|
---|
4256 | memcpy(pbBounceBuf + cbAlreadyRead,
|
---|
4257 | (uint8_t *)pFIFO + offCurrentCmd + cbAlreadyRead,
|
---|
4258 | cbAfter - cbAlreadyRead);
|
---|
4259 | cbAlreadyRead = cbAfter;
|
---|
4260 | }
|
---|
4261 | memcpy(pbBounceBuf + cbAlreadyRead,
|
---|
4262 | (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
|
---|
4263 | cbPayloadReq - cbAlreadyRead);
|
---|
4264 | }
|
---|
4265 | *pcbAlreadyRead = cbPayloadReq;
|
---|
4266 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
4267 | return pbBounceBuf;
|
---|
4268 | }
|
---|
4269 |
|
---|
4270 |
|
---|
4271 | /**
|
---|
4272 | * Sends cursor position and visibility information from the FIFO to the front-end.
|
---|
4273 | * @returns SVGA_FIFO_CURSOR_COUNT value used.
|
---|
4274 | */
|
---|
4275 | static uint32_t
|
---|
4276 | vmsvgaR3FifoUpdateCursor(PVGASTATECC pThisCC, PVMSVGAR3STATE pSVGAState, uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO,
|
---|
4277 | uint32_t offFifoMin, uint32_t uCursorUpdateCount,
|
---|
4278 | uint32_t *pxLast, uint32_t *pyLast, uint32_t *pfLastVisible)
|
---|
4279 | {
|
---|
4280 | /*
|
---|
4281 | * Check if the cursor update counter has changed and try get a stable
|
---|
4282 | * set of values if it has. This is race-prone, especially consindering
|
---|
4283 | * the screen ID, but little we can do about that.
|
---|
4284 | */
|
---|
4285 | uint32_t x, y, fVisible, idScreen;
|
---|
4286 | for (uint32_t i = 0; ; i++)
|
---|
4287 | {
|
---|
4288 | x = pFIFO[SVGA_FIFO_CURSOR_X];
|
---|
4289 | y = pFIFO[SVGA_FIFO_CURSOR_Y];
|
---|
4290 | fVisible = pFIFO[SVGA_FIFO_CURSOR_ON];
|
---|
4291 | idScreen = VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_SCREEN_ID, offFifoMin)
|
---|
4292 | ? pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID] : SVGA_ID_INVALID;
|
---|
4293 | if ( uCursorUpdateCount == pFIFO[SVGA_FIFO_CURSOR_COUNT]
|
---|
4294 | || i > 3)
|
---|
4295 | break;
|
---|
4296 | if (i == 0)
|
---|
4297 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorFetchAgain);
|
---|
4298 | ASMNopPause();
|
---|
4299 | uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
|
---|
4300 | }
|
---|
4301 |
|
---|
4302 | /*
|
---|
4303 | * Check if anything has changed, as calling into pDrv is not light-weight.
|
---|
4304 | */
|
---|
4305 | if ( *pxLast == x
|
---|
4306 | && *pyLast == y
|
---|
4307 | && (idScreen != SVGA_ID_INVALID || *pfLastVisible == fVisible))
|
---|
4308 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorNoChange);
|
---|
4309 | else
|
---|
4310 | {
|
---|
4311 | /*
|
---|
4312 | * Detected changes.
|
---|
4313 | *
|
---|
4314 | * We handle global, not per-screen visibility information by sending
|
---|
4315 | * pfnVBVAMousePointerShape without shape data.
|
---|
4316 | */
|
---|
4317 | *pxLast = x;
|
---|
4318 | *pyLast = y;
|
---|
4319 | uint32_t fFlags = VBVA_CURSOR_VALID_DATA;
|
---|
4320 | if (idScreen != SVGA_ID_INVALID)
|
---|
4321 | fFlags |= VBVA_CURSOR_SCREEN_RELATIVE;
|
---|
4322 | else if (*pfLastVisible != fVisible)
|
---|
4323 | {
|
---|
4324 | LogRel2(("vmsvgaR3FifoUpdateCursor: fVisible %d fLastVisible %d (%d,%d)\n", fVisible, *pfLastVisible, x, y));
|
---|
4325 | *pfLastVisible = fVisible;
|
---|
4326 | pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, RT_BOOL(fVisible), false, 0, 0, 0, 0, NULL);
|
---|
4327 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorVisiblity);
|
---|
4328 | }
|
---|
4329 | pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, fFlags, idScreen, x, y);
|
---|
4330 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCursorPosition);
|
---|
4331 | }
|
---|
4332 |
|
---|
4333 | /*
|
---|
4334 | * Update done. Signal this to the guest.
|
---|
4335 | */
|
---|
4336 | pFIFO[SVGA_FIFO_CURSOR_LAST_UPDATED] = uCursorUpdateCount;
|
---|
4337 |
|
---|
4338 | return uCursorUpdateCount;
|
---|
4339 | }
|
---|
4340 |
|
---|
4341 |
|
---|
4342 | /**
|
---|
4343 | * Checks if there is work to be done, either cursor updating or FIFO commands.
|
---|
4344 | *
|
---|
4345 | * @returns true if pending work, false if not.
|
---|
4346 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
4347 | * @param uLastCursorCount The last cursor update counter value.
|
---|
4348 | */
|
---|
4349 | DECLINLINE(bool) vmsvgaR3FifoHasWork(PVGASTATECC pThisCC, uint32_t uLastCursorCount)
|
---|
4350 | {
|
---|
4351 | /* If FIFO does not exist than there is nothing to do. Command buffers also require the enabled FIFO. */
|
---|
4352 | uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
|
---|
4353 | AssertReturn(pFIFO, false);
|
---|
4354 |
|
---|
4355 | if (vmsvgaR3CmdBufHasWork(pThisCC))
|
---|
4356 | return true;
|
---|
4357 |
|
---|
4358 | if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
|
---|
4359 | return true;
|
---|
4360 |
|
---|
4361 | if ( uLastCursorCount != pFIFO[SVGA_FIFO_CURSOR_COUNT]
|
---|
4362 | && VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, pFIFO[SVGA_FIFO_MIN]))
|
---|
4363 | return true;
|
---|
4364 |
|
---|
4365 | return false;
|
---|
4366 | }
|
---|
4367 |
|
---|
4368 |
|
---|
4369 | /**
|
---|
4370 | * Called by the VGA refresh timer to wake up the FIFO thread when needed.
|
---|
4371 | *
|
---|
4372 | * @param pDevIns The device instance.
|
---|
4373 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
4374 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
4375 | */
|
---|
4376 | void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
4377 | {
|
---|
4378 | /* Caller already checked pThis->svga.fFIFOThreadSleeping, so we only have
|
---|
4379 | to recheck it before doing the signalling. */
|
---|
4380 | if ( vmsvgaR3FifoHasWork(pThisCC, ASMAtomicReadU32(&pThis->svga.uLastCursorUpdateCount))
|
---|
4381 | && pThis->svga.fFIFOThreadSleeping
|
---|
4382 | && !ASMAtomicReadBool(&pThis->svga.fBadGuest))
|
---|
4383 | {
|
---|
4384 | int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
4385 | AssertRC(rc);
|
---|
4386 | STAM_REL_COUNTER_INC(&pThisCC->svga.pSvgaR3State->StatFifoWatchdogWakeUps);
|
---|
4387 | }
|
---|
4388 | }
|
---|
4389 |
|
---|
4390 |
|
---|
4391 | /**
|
---|
4392 | * Called by the FIFO thread to process pending actions.
|
---|
4393 | *
|
---|
4394 | * @param pDevIns The device instance.
|
---|
4395 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
4396 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
4397 | */
|
---|
4398 | void vmsvgaR3FifoPendingActions(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
4399 | {
|
---|
4400 | RT_NOREF(pDevIns);
|
---|
4401 |
|
---|
4402 | /* Currently just mode changes. */
|
---|
4403 | if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
|
---|
4404 | {
|
---|
4405 | vmsvgaR3ChangeMode(pThis, pThisCC);
|
---|
4406 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
4407 | if (pThisCC->svga.p3dState != NULL)
|
---|
4408 | vmsvga3dChangeMode(pThisCC);
|
---|
4409 | # endif
|
---|
4410 | }
|
---|
4411 | }
|
---|
4412 |
|
---|
4413 |
|
---|
4414 | /*
|
---|
4415 | * These two macros are put outside vmsvgaR3FifoLoop because doxygen gets confused,
|
---|
4416 | * even the latest version, and thinks we're documenting vmsvgaR3FifoLoop. Sigh.
|
---|
4417 | */
|
---|
4418 | /** @def VMSVGAFIFO_GET_CMD_BUFFER_BREAK
|
---|
4419 | * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload.
|
---|
4420 | *
|
---|
4421 | * Will break out of the switch on failure.
|
---|
4422 | * Will restart and quit the loop if the thread was requested to stop.
|
---|
4423 | *
|
---|
4424 | * @param a_PtrVar Request variable pointer.
|
---|
4425 | * @param a_Type Request typedef (not pointer) for casting.
|
---|
4426 | * @param a_cbPayloadReq How much payload to fetch.
|
---|
4427 | * @remarks Accesses a bunch of variables in the current scope!
|
---|
4428 | */
|
---|
4429 | # define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
|
---|
4430 | if (1) { \
|
---|
4431 | (a_PtrVar) = (a_Type *)vmsvgaR3FifoGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
|
---|
4432 | pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState, pDevIns); \
|
---|
4433 | if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
|
---|
4434 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE(); \
|
---|
4435 | } else do {} while (0)
|
---|
4436 | /* @def VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
|
---|
4437 | * Macro for shortening calls to vmsvgaR3FifoGetCmdPayload for refetching the
|
---|
4438 | * buffer after figuring out the actual command size.
|
---|
4439 | *
|
---|
4440 | * Will break out of the switch on failure.
|
---|
4441 | *
|
---|
4442 | * @param a_PtrVar Request variable pointer.
|
---|
4443 | * @param a_Type Request typedef (not pointer) for casting.
|
---|
4444 | * @param a_cbPayloadReq How much payload to fetch.
|
---|
4445 | * @remarks Accesses a bunch of variables in the current scope!
|
---|
4446 | */
|
---|
4447 | # define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
|
---|
4448 | if (1) { \
|
---|
4449 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
|
---|
4450 | } else do {} while (0)
|
---|
4451 |
|
---|
4452 | /**
|
---|
4453 | * @callback_method_impl{PFNPDMTHREADDEV, The async FIFO handling thread.}
|
---|
4454 | */
|
---|
4455 | static DECLCALLBACK(int) vmsvgaR3FifoLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
|
---|
4456 | {
|
---|
4457 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
4458 | PVGASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
4459 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
4460 | int rc;
|
---|
4461 |
|
---|
4462 | # if defined(VBOX_WITH_VMSVGA3D) && defined(RT_OS_LINUX)
|
---|
4463 | if (pThis->svga.f3DEnabled)
|
---|
4464 | {
|
---|
4465 | /* The FIFO thread may use X API for accelerated screen output. */
|
---|
4466 | XInitThreads();
|
---|
4467 | }
|
---|
4468 | # endif
|
---|
4469 |
|
---|
4470 | if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
|
---|
4471 | return VINF_SUCCESS;
|
---|
4472 |
|
---|
4473 | /*
|
---|
4474 | * Special mode where we only execute an external command and the go back
|
---|
4475 | * to being suspended. Currently, all ext cmds ends up here, with the reset
|
---|
4476 | * one also being eligble for runtime execution further down as well.
|
---|
4477 | */
|
---|
4478 | if (pThis->svga.fFifoExtCommandWakeup)
|
---|
4479 | {
|
---|
4480 | vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
|
---|
4481 | while (pThread->enmState == PDMTHREADSTATE_RUNNING)
|
---|
4482 | if (pThis->svga.u8FIFOExtCommand == VMSVGA_FIFO_EXTCMD_NONE)
|
---|
4483 | PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, RT_MS_1MIN);
|
---|
4484 | else
|
---|
4485 | vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
|
---|
4486 | return VINF_SUCCESS;
|
---|
4487 | }
|
---|
4488 |
|
---|
4489 |
|
---|
4490 | /*
|
---|
4491 | * Signal the semaphore to make sure we don't wait for 250ms after a
|
---|
4492 | * suspend & resume scenario (see vmsvgaR3FifoGetCmdPayload).
|
---|
4493 | */
|
---|
4494 | PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
4495 |
|
---|
4496 | /*
|
---|
4497 | * Allocate a bounce buffer for command we get from the FIFO.
|
---|
4498 | * (All code must return via the end of the function to free this buffer.)
|
---|
4499 | */
|
---|
4500 | uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(pThis->svga.cbFIFO);
|
---|
4501 | AssertReturn(pbBounceBuf, VERR_NO_MEMORY);
|
---|
4502 |
|
---|
4503 | /*
|
---|
4504 | * Polling/sleep interval config.
|
---|
4505 | *
|
---|
4506 | * We wait for an a short interval if the guest has recently given us work
|
---|
4507 | * to do, but the interval increases the longer we're kept idle. Once we've
|
---|
4508 | * reached the refresh timer interval, we'll switch to extended waits,
|
---|
4509 | * depending on it or the guest to kick us into action when needed.
|
---|
4510 | *
|
---|
4511 | * Should the refresh time go fishing, we'll just continue increasing the
|
---|
4512 | * sleep length till we reaches the 250 ms max after about 16 seconds.
|
---|
4513 | */
|
---|
4514 | RTMSINTERVAL const cMsMinSleep = 16;
|
---|
4515 | RTMSINTERVAL const cMsIncSleep = 2;
|
---|
4516 | RTMSINTERVAL const cMsMaxSleep = 250;
|
---|
4517 | RTMSINTERVAL const cMsExtendedSleep = 15 * RT_MS_1SEC; /* Regular paranoia dictates that this cannot be indefinite. */
|
---|
4518 | RTMSINTERVAL cMsSleep = cMsMaxSleep;
|
---|
4519 |
|
---|
4520 | /*
|
---|
4521 | * Cursor update state (SVGA_FIFO_CAP_CURSOR_BYPASS_3).
|
---|
4522 | *
|
---|
4523 | * Initialize with values that will detect an update from the guest.
|
---|
4524 | * Make sure that if the guest never updates the cursor position, then the device does not report it.
|
---|
4525 | * The guest has to change the value of uLastCursorUpdateCount, when the cursor position is actually updated.
|
---|
4526 | * xLastCursor, yLastCursor and fLastCursorVisible are set to report the first update.
|
---|
4527 | */
|
---|
4528 | uint32_t RT_UNTRUSTED_VOLATILE_GUEST * const pFIFO = pThisCC->svga.pau32FIFO;
|
---|
4529 | pThis->svga.uLastCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
|
---|
4530 | uint32_t xLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_X];
|
---|
4531 | uint32_t yLastCursor = ~pFIFO[SVGA_FIFO_CURSOR_Y];
|
---|
4532 | uint32_t fLastCursorVisible = ~pFIFO[SVGA_FIFO_CURSOR_ON];
|
---|
4533 |
|
---|
4534 | /*
|
---|
4535 | * The FIFO loop.
|
---|
4536 | */
|
---|
4537 | LogFlow(("vmsvgaR3FifoLoop: started loop\n"));
|
---|
4538 | bool fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
|
---|
4539 | while (pThread->enmState == PDMTHREADSTATE_RUNNING)
|
---|
4540 | {
|
---|
4541 | # if defined(RT_OS_DARWIN) && defined(VBOX_WITH_VMSVGA3D)
|
---|
4542 | /*
|
---|
4543 | * Should service the run loop every so often.
|
---|
4544 | */
|
---|
4545 | if (pThis->svga.f3DEnabled)
|
---|
4546 | vmsvga3dCocoaServiceRunLoop();
|
---|
4547 | # endif
|
---|
4548 |
|
---|
4549 | /* First check any pending actions. */
|
---|
4550 | vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
|
---|
4551 |
|
---|
4552 | /*
|
---|
4553 | * Unless there's already work pending, go to sleep for a short while.
|
---|
4554 | * (See polling/sleep interval config above.)
|
---|
4555 | */
|
---|
4556 | if ( fBadOrDisabledFifo
|
---|
4557 | || !vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
|
---|
4558 | {
|
---|
4559 | ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, true);
|
---|
4560 | Assert(pThis->cMilliesRefreshInterval > 0);
|
---|
4561 | if (cMsSleep < pThis->cMilliesRefreshInterval)
|
---|
4562 | rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsSleep);
|
---|
4563 | else
|
---|
4564 | {
|
---|
4565 | # ifdef VMSVGA_USE_FIFO_ACCESS_HANDLER
|
---|
4566 | int rc2 = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
|
---|
4567 | AssertRC(rc2); /* No break. Racing EMTs unmapping and remapping the region. */
|
---|
4568 | # endif
|
---|
4569 | if ( !fBadOrDisabledFifo
|
---|
4570 | && vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
|
---|
4571 | rc = VINF_SUCCESS;
|
---|
4572 | else
|
---|
4573 | {
|
---|
4574 | STAM_REL_PROFILE_START(&pSVGAState->StatFifoExtendedSleep, Acc);
|
---|
4575 | rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->svga.hFIFORequestSem, cMsExtendedSleep);
|
---|
4576 | STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoExtendedSleep, Acc);
|
---|
4577 | }
|
---|
4578 | }
|
---|
4579 | ASMAtomicWriteBool(&pThis->svga.fFIFOThreadSleeping, false);
|
---|
4580 | AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
|
---|
4581 | if (pThread->enmState != PDMTHREADSTATE_RUNNING)
|
---|
4582 | {
|
---|
4583 | LogFlow(("vmsvgaR3FifoLoop: thread state %x\n", pThread->enmState));
|
---|
4584 | break;
|
---|
4585 | }
|
---|
4586 | }
|
---|
4587 | else
|
---|
4588 | rc = VINF_SUCCESS;
|
---|
4589 | fBadOrDisabledFifo = ASMAtomicReadBool(&pThis->svga.fBadGuest);
|
---|
4590 | if (rc == VERR_TIMEOUT)
|
---|
4591 | {
|
---|
4592 | if (!vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
|
---|
4593 | {
|
---|
4594 | cMsSleep = RT_MIN(cMsSleep + cMsIncSleep, cMsMaxSleep);
|
---|
4595 | continue;
|
---|
4596 | }
|
---|
4597 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
|
---|
4598 |
|
---|
4599 | Log(("vmsvgaR3FifoLoop: timeout\n"));
|
---|
4600 | }
|
---|
4601 | else if (vmsvgaR3FifoHasWork(pThisCC, pThis->svga.uLastCursorUpdateCount))
|
---|
4602 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
|
---|
4603 | cMsSleep = cMsMinSleep;
|
---|
4604 |
|
---|
4605 | Log(("vmsvgaR3FifoLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pFIFO[SVGA_FIFO_BUSY]));
|
---|
4606 | Log(("vmsvgaR3FifoLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
|
---|
4607 | Log(("vmsvgaR3FifoLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
|
---|
4608 |
|
---|
4609 | /*
|
---|
4610 | * Handle external commands (currently only reset).
|
---|
4611 | */
|
---|
4612 | if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
|
---|
4613 | {
|
---|
4614 | vmsvgaR3FifoHandleExtCmd(pDevIns, pThis, pThisCC);
|
---|
4615 | continue;
|
---|
4616 | }
|
---|
4617 |
|
---|
4618 | /*
|
---|
4619 | * If guest misbehaves, then do nothing.
|
---|
4620 | */
|
---|
4621 | if (ASMAtomicReadBool(&pThis->svga.fBadGuest))
|
---|
4622 | {
|
---|
4623 | vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
|
---|
4624 | cMsSleep = cMsExtendedSleep;
|
---|
4625 | LogRelMax(1, ("VMSVGA: FIFO processing stopped because of the guest misbehavior\n"));
|
---|
4626 | continue;
|
---|
4627 | }
|
---|
4628 |
|
---|
4629 | /*
|
---|
4630 | * The device must be enabled and configured.
|
---|
4631 | */
|
---|
4632 | if ( !pThis->svga.fEnabled
|
---|
4633 | || !pThis->svga.fConfigured)
|
---|
4634 | {
|
---|
4635 | vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
|
---|
4636 | fBadOrDisabledFifo = true;
|
---|
4637 | cMsSleep = cMsMaxSleep; /* cheat */
|
---|
4638 | continue;
|
---|
4639 | }
|
---|
4640 |
|
---|
4641 | /*
|
---|
4642 | * Get and check the min/max values. We ASSUME that they will remain
|
---|
4643 | * unchanged while we process requests. A further ASSUMPTION is that
|
---|
4644 | * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
|
---|
4645 | * we don't read it back while in the loop.
|
---|
4646 | */
|
---|
4647 | uint32_t const offFifoMin = pFIFO[SVGA_FIFO_MIN];
|
---|
4648 | uint32_t const offFifoMax = pFIFO[SVGA_FIFO_MAX];
|
---|
4649 | uint32_t offCurrentCmd = pFIFO[SVGA_FIFO_STOP];
|
---|
4650 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
4651 | if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
|
---|
4652 | || offFifoMax <= offFifoMin
|
---|
4653 | || offFifoMax > pThis->svga.cbFIFO
|
---|
4654 | || (offFifoMax & 3) != 0
|
---|
4655 | || (offFifoMin & 3) != 0
|
---|
4656 | || offCurrentCmd < offFifoMin
|
---|
4657 | || offCurrentCmd > offFifoMax))
|
---|
4658 | {
|
---|
4659 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
|
---|
4660 | LogRelMax(8, ("vmsvgaR3FifoLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
|
---|
4661 | vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
|
---|
4662 | fBadOrDisabledFifo = true;
|
---|
4663 | continue;
|
---|
4664 | }
|
---|
4665 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
4666 | if (RT_UNLIKELY(offCurrentCmd & 3))
|
---|
4667 | {
|
---|
4668 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoErrors);
|
---|
4669 | LogRelMax(8, ("vmsvgaR3FifoLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
|
---|
4670 | offCurrentCmd &= ~UINT32_C(3);
|
---|
4671 | }
|
---|
4672 |
|
---|
4673 | /*
|
---|
4674 | * Update the cursor position before we start on the FIFO commands.
|
---|
4675 | */
|
---|
4676 | /** @todo do we need to check whether the guest disabled the SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability here? */
|
---|
4677 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_CURSOR_LAST_UPDATED, offFifoMin))
|
---|
4678 | {
|
---|
4679 | uint32_t const uCursorUpdateCount = pFIFO[SVGA_FIFO_CURSOR_COUNT];
|
---|
4680 | if (uCursorUpdateCount == pThis->svga.uLastCursorUpdateCount)
|
---|
4681 | { /* halfways likely */ }
|
---|
4682 | else
|
---|
4683 | {
|
---|
4684 | uint32_t const uNewCount = vmsvgaR3FifoUpdateCursor(pThisCC, pSVGAState, pFIFO, offFifoMin, uCursorUpdateCount,
|
---|
4685 | &xLastCursor, &yLastCursor, &fLastCursorVisible);
|
---|
4686 | ASMAtomicWriteU32(&pThis->svga.uLastCursorUpdateCount, uNewCount);
|
---|
4687 | }
|
---|
4688 | }
|
---|
4689 |
|
---|
4690 | /*
|
---|
4691 | * Mark the FIFO as busy.
|
---|
4692 | */
|
---|
4693 | ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO); // Clears VMSVGA_BUSY_F_EMT_FORCE!
|
---|
4694 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
|
---|
4695 | ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_BUSY], true);
|
---|
4696 |
|
---|
4697 | /*
|
---|
4698 | * Process all submitted command buffers.
|
---|
4699 | */
|
---|
4700 | vmsvgaR3CmdBufProcessBuffers(pDevIns, pThis, pThisCC, pThread);
|
---|
4701 |
|
---|
4702 | /*
|
---|
4703 | * Execute all queued FIFO commands.
|
---|
4704 | * Quit if pending external command or changes in the thread state.
|
---|
4705 | */
|
---|
4706 | bool fDone = false;
|
---|
4707 | while ( !(fDone = (pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd))
|
---|
4708 | && pThread->enmState == PDMTHREADSTATE_RUNNING)
|
---|
4709 | {
|
---|
4710 | uint32_t cbPayload = 0;
|
---|
4711 | uint32_t u32IrqStatus = 0;
|
---|
4712 |
|
---|
4713 | Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
|
---|
4714 |
|
---|
4715 | /* First check any pending actions. */
|
---|
4716 | vmsvgaR3FifoPendingActions(pDevIns, pThis, pThisCC);
|
---|
4717 |
|
---|
4718 | /* Check for pending external commands (reset). */
|
---|
4719 | if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
|
---|
4720 | break;
|
---|
4721 |
|
---|
4722 | /*
|
---|
4723 | * Process the command.
|
---|
4724 | */
|
---|
4725 | /* 'enmCmdId' is actually a SVGAFifoCmdId. It is treated as uint32_t in order to avoid a compiler
|
---|
4726 | * warning. Because we implement some obsolete and deprecated commands, which are not included in
|
---|
4727 | * the SVGAFifoCmdId enum in the VMSVGA headers anymore.
|
---|
4728 | */
|
---|
4729 | uint32_t const enmCmdId = pFIFO[offCurrentCmd / sizeof(uint32_t)];
|
---|
4730 | RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
|
---|
4731 | LogFlow(("vmsvgaR3FifoLoop: FIFO command (iCmd=0x%x) %s %d\n",
|
---|
4732 | offCurrentCmd / sizeof(uint32_t), vmsvgaR3FifoCmdToString(enmCmdId), enmCmdId));
|
---|
4733 | switch (enmCmdId)
|
---|
4734 | {
|
---|
4735 | case SVGA_CMD_INVALID_CMD:
|
---|
4736 | /* Nothing to do. */
|
---|
4737 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdInvalidCmd);
|
---|
4738 | break;
|
---|
4739 |
|
---|
4740 | case SVGA_CMD_FENCE:
|
---|
4741 | {
|
---|
4742 | SVGAFifoCmdFence *pCmdFence;
|
---|
4743 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
|
---|
4744 | STAM_REL_COUNTER_INC(&pSVGAState->StatR3CmdFence);
|
---|
4745 | if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
|
---|
4746 | {
|
---|
4747 | Log(("vmsvgaR3FifoLoop: SVGA_CMD_FENCE %#x\n", pCmdFence->fence));
|
---|
4748 | pFIFO[SVGA_FIFO_FENCE] = pCmdFence->fence;
|
---|
4749 |
|
---|
4750 | if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
|
---|
4751 | {
|
---|
4752 | Log(("vmsvgaR3FifoLoop: any fence irq\n"));
|
---|
4753 | u32IrqStatus |= SVGA_IRQFLAG_ANY_FENCE;
|
---|
4754 | }
|
---|
4755 | else
|
---|
4756 | if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
|
---|
4757 | && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
|
---|
4758 | && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
|
---|
4759 | {
|
---|
4760 | Log(("vmsvgaR3FifoLoop: fence goal reached irq (fence=%#x)\n", pCmdFence->fence));
|
---|
4761 | u32IrqStatus |= SVGA_IRQFLAG_FENCE_GOAL;
|
---|
4762 | }
|
---|
4763 | }
|
---|
4764 | else
|
---|
4765 | Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
|
---|
4766 | break;
|
---|
4767 | }
|
---|
4768 |
|
---|
4769 | case SVGA_CMD_UPDATE:
|
---|
4770 | {
|
---|
4771 | SVGAFifoCmdUpdate *pCmd;
|
---|
4772 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdate, sizeof(*pCmd));
|
---|
4773 | vmsvgaR3CmdUpdate(pThis, pThisCC, pCmd);
|
---|
4774 | break;
|
---|
4775 | }
|
---|
4776 |
|
---|
4777 | case SVGA_CMD_UPDATE_VERBOSE:
|
---|
4778 | {
|
---|
4779 | SVGAFifoCmdUpdateVerbose *pCmd;
|
---|
4780 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdUpdateVerbose, sizeof(*pCmd));
|
---|
4781 | vmsvgaR3CmdUpdateVerbose(pThis, pThisCC, pCmd);
|
---|
4782 | break;
|
---|
4783 | }
|
---|
4784 |
|
---|
4785 | case SVGA_CMD_DEFINE_CURSOR:
|
---|
4786 | {
|
---|
4787 | /* Followed by bitmap data. */
|
---|
4788 | SVGAFifoCmdDefineCursor *pCmd;
|
---|
4789 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, sizeof(*pCmd));
|
---|
4790 |
|
---|
4791 | /* Figure out the size of the bitmap data. */
|
---|
4792 | ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
|
---|
4793 | ASSERT_GUEST_BREAK(pCmd->andMaskDepth <= 32);
|
---|
4794 | ASSERT_GUEST_BREAK(pCmd->xorMaskDepth <= 32);
|
---|
4795 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
4796 |
|
---|
4797 | uint32_t const cbAndLine = RT_ALIGN_32(pCmd->width * (pCmd->andMaskDepth + (pCmd->andMaskDepth == 15)), 32) / 8;
|
---|
4798 | uint32_t const cbAndMask = cbAndLine * pCmd->height;
|
---|
4799 | uint32_t const cbXorLine = RT_ALIGN_32(pCmd->width * (pCmd->xorMaskDepth + (pCmd->xorMaskDepth == 15)), 32) / 8;
|
---|
4800 | uint32_t const cbXorMask = cbXorLine * pCmd->height;
|
---|
4801 |
|
---|
4802 | uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineCursor) + cbAndMask + cbXorMask;
|
---|
4803 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineCursor, cbCmd);
|
---|
4804 | vmsvgaR3CmdDefineCursor(pThis, pThisCC, pCmd);
|
---|
4805 | break;
|
---|
4806 | }
|
---|
4807 |
|
---|
4808 | case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
---|
4809 | {
|
---|
4810 | /* Followed by bitmap data. */
|
---|
4811 | SVGAFifoCmdDefineAlphaCursor *pCmd;
|
---|
4812 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCmd));
|
---|
4813 |
|
---|
4814 | /* Figure out the size of the bitmap data. */
|
---|
4815 | ASSERT_GUEST_BREAK(pCmd->height < 2048 && pCmd->width < 2048);
|
---|
4816 |
|
---|
4817 | uint32_t const cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCmd->width * pCmd->height * sizeof(uint32_t) /* 32-bit BRGA format */;
|
---|
4818 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineAlphaCursor, cbCmd);
|
---|
4819 | vmsvgaR3CmdDefineAlphaCursor(pThis, pThisCC, pCmd);
|
---|
4820 | break;
|
---|
4821 | }
|
---|
4822 |
|
---|
4823 | case SVGA_CMD_MOVE_CURSOR:
|
---|
4824 | {
|
---|
4825 | /* Deprecated; there should be no driver which *requires* this command. However, if
|
---|
4826 | * we do ecncounter this command, it might be useful to not get the FIFO completely out of
|
---|
4827 | * alignment.
|
---|
4828 | * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
|
---|
4829 | */
|
---|
4830 | SVGAFifoCmdMoveCursor *pCmd;
|
---|
4831 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdMoveCursor, sizeof(*pCmd));
|
---|
4832 | vmsvgaR3CmdMoveCursor(pThis, pThisCC, pCmd);
|
---|
4833 | break;
|
---|
4834 | }
|
---|
4835 |
|
---|
4836 | case SVGA_CMD_DISPLAY_CURSOR:
|
---|
4837 | {
|
---|
4838 | /* Deprecated; there should be no driver which *requires* this command. However, if
|
---|
4839 | * we do ecncounter this command, it might be useful to not get the FIFO completely out of
|
---|
4840 | * alignment.
|
---|
4841 | * May be issued by guest if SVGA_CAP_CURSOR_BYPASS is missing.
|
---|
4842 | */
|
---|
4843 | SVGAFifoCmdDisplayCursor *pCmd;
|
---|
4844 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDisplayCursor, sizeof(*pCmd));
|
---|
4845 | vmsvgaR3CmdDisplayCursor(pThis, pThisCC, pCmd);
|
---|
4846 | break;
|
---|
4847 | }
|
---|
4848 |
|
---|
4849 | case SVGA_CMD_RECT_FILL:
|
---|
4850 | {
|
---|
4851 | SVGAFifoCmdRectFill *pCmd;
|
---|
4852 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectFill, sizeof(*pCmd));
|
---|
4853 | vmsvgaR3CmdRectFill(pThis, pThisCC, pCmd);
|
---|
4854 | break;
|
---|
4855 | }
|
---|
4856 |
|
---|
4857 | case SVGA_CMD_RECT_COPY:
|
---|
4858 | {
|
---|
4859 | SVGAFifoCmdRectCopy *pCmd;
|
---|
4860 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectCopy, sizeof(*pCmd));
|
---|
4861 | vmsvgaR3CmdRectCopy(pThis, pThisCC, pCmd);
|
---|
4862 | break;
|
---|
4863 | }
|
---|
4864 |
|
---|
4865 | case SVGA_CMD_RECT_ROP_COPY:
|
---|
4866 | {
|
---|
4867 | SVGAFifoCmdRectRopCopy *pCmd;
|
---|
4868 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRectRopCopy, sizeof(*pCmd));
|
---|
4869 | vmsvgaR3CmdRectRopCopy(pThis, pThisCC, pCmd);
|
---|
4870 | break;
|
---|
4871 | }
|
---|
4872 |
|
---|
4873 | case SVGA_CMD_ESCAPE:
|
---|
4874 | {
|
---|
4875 | /* Followed by 'size' bytes of data. */
|
---|
4876 | SVGAFifoCmdEscape *pCmd;
|
---|
4877 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, sizeof(*pCmd));
|
---|
4878 |
|
---|
4879 | ASSERT_GUEST_BREAK(pCmd->size < pThis->svga.cbFIFO - sizeof(SVGAFifoCmdEscape));
|
---|
4880 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
4881 |
|
---|
4882 | uint32_t const cbCmd = sizeof(SVGAFifoCmdEscape) + pCmd->size;
|
---|
4883 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdEscape, cbCmd);
|
---|
4884 | vmsvgaR3CmdEscape(pThis, pThisCC, pCmd);
|
---|
4885 | break;
|
---|
4886 | }
|
---|
4887 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
4888 | case SVGA_CMD_DEFINE_GMR2:
|
---|
4889 | {
|
---|
4890 | SVGAFifoCmdDefineGMR2 *pCmd;
|
---|
4891 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
|
---|
4892 | vmsvgaR3CmdDefineGMR2(pThis, pThisCC, pCmd);
|
---|
4893 | break;
|
---|
4894 | }
|
---|
4895 |
|
---|
4896 | case SVGA_CMD_REMAP_GMR2:
|
---|
4897 | {
|
---|
4898 | /* Followed by page descriptors or guest ptr. */
|
---|
4899 | SVGAFifoCmdRemapGMR2 *pCmd;
|
---|
4900 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
|
---|
4901 |
|
---|
4902 | /* Calculate the size of what comes after next and fetch it. */
|
---|
4903 | uint32_t cbCmd = sizeof(SVGAFifoCmdRemapGMR2);
|
---|
4904 | if (pCmd->flags & SVGA_REMAP_GMR2_VIA_GMR)
|
---|
4905 | cbCmd += sizeof(SVGAGuestPtr);
|
---|
4906 | else
|
---|
4907 | {
|
---|
4908 | uint32_t const cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
|
---|
4909 | if (pCmd->flags & SVGA_REMAP_GMR2_SINGLE_PPN)
|
---|
4910 | {
|
---|
4911 | cbCmd += cbPageDesc;
|
---|
4912 | pCmd->numPages = 1;
|
---|
4913 | }
|
---|
4914 | else
|
---|
4915 | {
|
---|
4916 | ASSERT_GUEST_BREAK(pCmd->numPages <= pThis->svga.cbFIFO / cbPageDesc);
|
---|
4917 | cbCmd += cbPageDesc * pCmd->numPages;
|
---|
4918 | }
|
---|
4919 | }
|
---|
4920 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
|
---|
4921 | vmsvgaR3CmdRemapGMR2(pThis, pThisCC, pCmd);
|
---|
4922 | # ifdef DEBUG_GMR_ACCESS
|
---|
4923 | VMR3ReqCallWaitU(PDMDevHlpGetUVM(pDevIns), VMCPUID_ANY, (PFNRT)vmsvgaR3RegisterGmr, 2, pDevIns, pCmd->gmrId);
|
---|
4924 | # endif
|
---|
4925 | break;
|
---|
4926 | }
|
---|
4927 | # endif // VBOX_WITH_VMSVGA3D
|
---|
4928 | case SVGA_CMD_DEFINE_SCREEN:
|
---|
4929 | {
|
---|
4930 | /* The size of this command is specified by the guest and depends on capabilities. */
|
---|
4931 | Assert(pFIFO[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT_2);
|
---|
4932 |
|
---|
4933 | SVGAFifoCmdDefineScreen *pCmd;
|
---|
4934 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
|
---|
4935 | AssertBreak(pCmd->screen.structSize < pThis->svga.cbFIFO);
|
---|
4936 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
4937 |
|
---|
4938 | RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.id));
|
---|
4939 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
|
---|
4940 | vmsvgaR3CmdDefineScreen(pThis, pThisCC, pCmd);
|
---|
4941 | break;
|
---|
4942 | }
|
---|
4943 |
|
---|
4944 | case SVGA_CMD_DESTROY_SCREEN:
|
---|
4945 | {
|
---|
4946 | SVGAFifoCmdDestroyScreen *pCmd;
|
---|
4947 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
|
---|
4948 | vmsvgaR3CmdDestroyScreen(pThis, pThisCC, pCmd);
|
---|
4949 | break;
|
---|
4950 | }
|
---|
4951 |
|
---|
4952 | case SVGA_CMD_DEFINE_GMRFB:
|
---|
4953 | {
|
---|
4954 | SVGAFifoCmdDefineGMRFB *pCmd;
|
---|
4955 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
|
---|
4956 | vmsvgaR3CmdDefineGMRFB(pThis, pThisCC, pCmd);
|
---|
4957 | break;
|
---|
4958 | }
|
---|
4959 |
|
---|
4960 | case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:
|
---|
4961 | {
|
---|
4962 | SVGAFifoCmdBlitGMRFBToScreen *pCmd;
|
---|
4963 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
|
---|
4964 | vmsvgaR3CmdBlitGMRFBToScreen(pThis, pThisCC, pCmd);
|
---|
4965 | break;
|
---|
4966 | }
|
---|
4967 |
|
---|
4968 | case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:
|
---|
4969 | {
|
---|
4970 | SVGAFifoCmdBlitScreenToGMRFB *pCmd;
|
---|
4971 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
|
---|
4972 | vmsvgaR3CmdBlitScreenToGMRFB(pThis, pThisCC, pCmd);
|
---|
4973 | break;
|
---|
4974 | }
|
---|
4975 |
|
---|
4976 | case SVGA_CMD_ANNOTATION_FILL:
|
---|
4977 | {
|
---|
4978 | SVGAFifoCmdAnnotationFill *pCmd;
|
---|
4979 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
|
---|
4980 | vmsvgaR3CmdAnnotationFill(pThis, pThisCC, pCmd);
|
---|
4981 | break;
|
---|
4982 | }
|
---|
4983 |
|
---|
4984 | case SVGA_CMD_ANNOTATION_COPY:
|
---|
4985 | {
|
---|
4986 | SVGAFifoCmdAnnotationCopy *pCmd;
|
---|
4987 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
|
---|
4988 | vmsvgaR3CmdAnnotationCopy(pThis, pThisCC, pCmd);
|
---|
4989 | break;
|
---|
4990 | }
|
---|
4991 |
|
---|
4992 | default:
|
---|
4993 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
4994 | if ( (int)enmCmdId >= SVGA_3D_CMD_BASE
|
---|
4995 | && (int)enmCmdId < SVGA_3D_CMD_MAX)
|
---|
4996 | {
|
---|
4997 | RT_UNTRUSTED_VALIDATED_FENCE();
|
---|
4998 |
|
---|
4999 | /* All 3d commands start with a common header, which defines the identifier and the size
|
---|
5000 | * of the command. The identifier has been already read from FIFO. Fetch the size.
|
---|
5001 | */
|
---|
5002 | uint32_t *pcbCmd;
|
---|
5003 | VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pcbCmd, uint32_t, sizeof(*pcbCmd));
|
---|
5004 | uint32_t const cbCmd = *pcbCmd;
|
---|
5005 | AssertBreak(cbCmd < pThis->svga.cbFIFO);
|
---|
5006 | uint32_t *pu32Cmd;
|
---|
5007 | VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pu32Cmd, uint32_t, sizeof(*pcbCmd) + cbCmd);
|
---|
5008 | pu32Cmd++; /* Skip the command size. */
|
---|
5009 |
|
---|
5010 | if (RT_LIKELY(pThis->svga.f3DEnabled))
|
---|
5011 | { /* likely */ }
|
---|
5012 | else
|
---|
5013 | {
|
---|
5014 | LogRelMax(8, ("VMSVGA: 3D disabled, command %d skipped\n", enmCmdId));
|
---|
5015 | break;
|
---|
5016 | }
|
---|
5017 |
|
---|
5018 | vmsvgaR3Process3dCmd(pThis, pThisCC, SVGA3D_INVALID_ID, (SVGAFifo3dCmdId)enmCmdId, cbCmd, pu32Cmd);
|
---|
5019 | }
|
---|
5020 | else
|
---|
5021 | # endif // VBOX_WITH_VMSVGA3D
|
---|
5022 | {
|
---|
5023 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
|
---|
5024 | AssertMsgFailed(("enmCmdId=%d\n", enmCmdId));
|
---|
5025 | LogRelMax(16, ("VMSVGA: unsupported command %d\n", enmCmdId));
|
---|
5026 | }
|
---|
5027 | }
|
---|
5028 |
|
---|
5029 | /* Go to the next slot */
|
---|
5030 | Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
|
---|
5031 | offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
|
---|
5032 | if (offCurrentCmd >= offFifoMax)
|
---|
5033 | {
|
---|
5034 | offCurrentCmd -= offFifoMax - offFifoMin;
|
---|
5035 | Assert(offCurrentCmd >= offFifoMin);
|
---|
5036 | Assert(offCurrentCmd < offFifoMax);
|
---|
5037 | }
|
---|
5038 | ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
|
---|
5039 | STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
|
---|
5040 |
|
---|
5041 | /*
|
---|
5042 | * Raise IRQ if required. Must enter the critical section here
|
---|
5043 | * before making final decisions here, otherwise cubebench and
|
---|
5044 | * others may end up waiting forever.
|
---|
5045 | */
|
---|
5046 | if ( u32IrqStatus
|
---|
5047 | || (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS))
|
---|
5048 | {
|
---|
5049 | int rc2 = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
|
---|
5050 | AssertRC(rc2);
|
---|
5051 |
|
---|
5052 | /* FIFO progress might trigger an interrupt. */
|
---|
5053 | if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
|
---|
5054 | {
|
---|
5055 | Log(("vmsvgaR3FifoLoop: fifo progress irq\n"));
|
---|
5056 | u32IrqStatus |= SVGA_IRQFLAG_FIFO_PROGRESS;
|
---|
5057 | }
|
---|
5058 |
|
---|
5059 | /* Unmasked IRQ pending? */
|
---|
5060 | if (pThis->svga.u32IrqMask & u32IrqStatus)
|
---|
5061 | {
|
---|
5062 | Log(("vmsvgaR3FifoLoop: Trigger interrupt with status %x\n", u32IrqStatus));
|
---|
5063 | ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
|
---|
5064 | PDMDevHlpPCISetIrq(pDevIns, 0, 1);
|
---|
5065 | }
|
---|
5066 |
|
---|
5067 | PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
|
---|
5068 | }
|
---|
5069 | }
|
---|
5070 |
|
---|
5071 | /* If really done, clear the busy flag. */
|
---|
5072 | if (fDone)
|
---|
5073 | {
|
---|
5074 | Log(("vmsvgaR3FifoLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
|
---|
5075 | vmsvgaR3FifoSetNotBusy(pDevIns, pThis, pThisCC, pSVGAState, offFifoMin);
|
---|
5076 | }
|
---|
5077 | }
|
---|
5078 |
|
---|
5079 | /*
|
---|
5080 | * Free the bounce buffer. (There are no returns above!)
|
---|
5081 | */
|
---|
5082 | RTMemFree(pbBounceBuf);
|
---|
5083 |
|
---|
5084 | return VINF_SUCCESS;
|
---|
5085 | }
|
---|
5086 |
|
---|
5087 | #undef VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK
|
---|
5088 | #undef VMSVGAFIFO_GET_CMD_BUFFER_BREAK
|
---|
5089 |
|
---|
5090 | /**
|
---|
5091 | * @callback_method_impl{PFNPDMTHREADWAKEUPDEV,
|
---|
5092 | * Unblock the FIFO I/O thread so it can respond to a state change.}
|
---|
5093 | */
|
---|
5094 | static DECLCALLBACK(int) vmsvgaR3FifoLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
|
---|
5095 | {
|
---|
5096 | RT_NOREF(pDevIns);
|
---|
5097 | PVGASTATE pThis = (PVGASTATE)pThread->pvUser;
|
---|
5098 | Log(("vmsvgaR3FifoLoopWakeUp\n"));
|
---|
5099 | return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
5100 | }
|
---|
5101 |
|
---|
5102 | /**
|
---|
5103 | * Enables or disables dirty page tracking for the framebuffer
|
---|
5104 | *
|
---|
5105 | * @param pDevIns The device instance.
|
---|
5106 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
5107 | * @param fTraces Enable/disable traces
|
---|
5108 | */
|
---|
5109 | static void vmsvgaR3SetTraces(PPDMDEVINS pDevIns, PVGASTATE pThis, bool fTraces)
|
---|
5110 | {
|
---|
5111 | if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
|
---|
5112 | && !fTraces)
|
---|
5113 | {
|
---|
5114 | //Assert(pThis->svga.fTraces);
|
---|
5115 | Log(("vmsvgaR3SetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
|
---|
5116 | return;
|
---|
5117 | }
|
---|
5118 |
|
---|
5119 | pThis->svga.fTraces = fTraces;
|
---|
5120 | if (pThis->svga.fTraces)
|
---|
5121 | {
|
---|
5122 | unsigned cbFrameBuffer = pThis->vram_size;
|
---|
5123 |
|
---|
5124 | Log(("vmsvgaR3SetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
|
---|
5125 | /** @todo How does this work with screens? */
|
---|
5126 | if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
|
---|
5127 | {
|
---|
5128 | # ifndef DEBUG_bird /* BB-10.3.1 triggers this as it initializes everything to zero. Better just ignore it. */
|
---|
5129 | Assert(pThis->svga.cbScanline);
|
---|
5130 | # endif
|
---|
5131 | /* Hardware enabled; return real framebuffer size .*/
|
---|
5132 | cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
|
---|
5133 | cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
|
---|
5134 | }
|
---|
5135 |
|
---|
5136 | if (!pThis->svga.fVRAMTracking)
|
---|
5137 | {
|
---|
5138 | Log(("vmsvgaR3SetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
|
---|
5139 | vgaR3RegisterVRAMHandler(pDevIns, pThis, cbFrameBuffer);
|
---|
5140 | pThis->svga.fVRAMTracking = true;
|
---|
5141 | }
|
---|
5142 | }
|
---|
5143 | else
|
---|
5144 | {
|
---|
5145 | if (pThis->svga.fVRAMTracking)
|
---|
5146 | {
|
---|
5147 | Log(("vmsvgaR3SetTraces: disable frame buffer dirty page tracking\n"));
|
---|
5148 | vgaR3UnregisterVRAMHandler(pDevIns, pThis);
|
---|
5149 | pThis->svga.fVRAMTracking = false;
|
---|
5150 | }
|
---|
5151 | }
|
---|
5152 | }
|
---|
5153 |
|
---|
5154 | /**
|
---|
5155 | * @callback_method_impl{FNPCIIOREGIONMAP}
|
---|
5156 | */
|
---|
5157 | DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
|
---|
5158 | RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
|
---|
5159 | {
|
---|
5160 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
5161 | int rc;
|
---|
5162 | RT_NOREF(pPciDev);
|
---|
5163 | Assert(pPciDev == pDevIns->apPciDevs[0]);
|
---|
5164 |
|
---|
5165 | Log(("vmsvgaR3PciIORegionFifoMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
|
---|
5166 | AssertReturn( iRegion == pThis->pciRegions.iFIFO
|
---|
5167 | && ( enmType == PCI_ADDRESS_SPACE_MEM
|
---|
5168 | || (enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH /* got wrong in 6.1.0RC1 */ && pThis->fStateLoaded))
|
---|
5169 | , VERR_INTERNAL_ERROR);
|
---|
5170 | if (GCPhysAddress != NIL_RTGCPHYS)
|
---|
5171 | {
|
---|
5172 | /*
|
---|
5173 | * Mapping the FIFO RAM.
|
---|
5174 | */
|
---|
5175 | AssertLogRelMsg(cb == pThis->svga.cbFIFO, ("cb=%#RGp cbFIFO=%#x\n", cb, pThis->svga.cbFIFO));
|
---|
5176 | rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VmSvgaFifo, GCPhysAddress);
|
---|
5177 | AssertRC(rc);
|
---|
5178 |
|
---|
5179 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
|
---|
5180 | if (RT_SUCCESS(rc))
|
---|
5181 | {
|
---|
5182 | rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress,
|
---|
5183 | # ifdef DEBUG_FIFO_ACCESS
|
---|
5184 | GCPhysAddress + (pThis->svga.cbFIFO - 1),
|
---|
5185 | # else
|
---|
5186 | GCPhysAddress + PAGE_SIZE - 1,
|
---|
5187 | # endif
|
---|
5188 | pThis->svga.hFifoAccessHandlerType, pThis, NIL_RTR0PTR, NIL_RTRCPTR,
|
---|
5189 | "VMSVGA FIFO");
|
---|
5190 | AssertRC(rc);
|
---|
5191 | }
|
---|
5192 | # endif
|
---|
5193 | if (RT_SUCCESS(rc))
|
---|
5194 | {
|
---|
5195 | pThis->svga.GCPhysFIFO = GCPhysAddress;
|
---|
5196 | Log(("vmsvgaR3IORegionMap: GCPhysFIFO=%RGp cbFIFO=%#x\n", GCPhysAddress, pThis->svga.cbFIFO));
|
---|
5197 | }
|
---|
5198 | rc = VINF_PCI_MAPPING_DONE; /* caller only cares about this status, so it is okay that we overwrite errors here. */
|
---|
5199 | }
|
---|
5200 | else
|
---|
5201 | {
|
---|
5202 | Assert(pThis->svga.GCPhysFIFO);
|
---|
5203 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
|
---|
5204 | rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
|
---|
5205 | AssertRC(rc);
|
---|
5206 | # else
|
---|
5207 | rc = VINF_SUCCESS;
|
---|
5208 | # endif
|
---|
5209 | pThis->svga.GCPhysFIFO = 0;
|
---|
5210 | }
|
---|
5211 | return rc;
|
---|
5212 | }
|
---|
5213 |
|
---|
5214 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5215 |
|
---|
5216 | /**
|
---|
5217 | * Used by vmsvga3dInfoSurfaceWorker to make the FIFO thread to save one or all
|
---|
5218 | * surfaces to VMSVGA3DMIPMAPLEVEL::pSurfaceData heap buffers.
|
---|
5219 | *
|
---|
5220 | * @param pDevIns The device instance.
|
---|
5221 | * @param pThis The The shared VGA/VMSVGA instance data.
|
---|
5222 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
5223 | * @param sid Either UINT32_MAX or the ID of a specific surface. If
|
---|
5224 | * UINT32_MAX is used, all surfaces are processed.
|
---|
5225 | */
|
---|
5226 | void vmsvgaR33dSurfaceUpdateHeapBuffersOnFifoThread(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t sid)
|
---|
5227 | {
|
---|
5228 | vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS, (void *)(uintptr_t)sid,
|
---|
5229 | sid == UINT32_MAX ? 10 * RT_MS_1SEC : RT_MS_1MIN);
|
---|
5230 | }
|
---|
5231 |
|
---|
5232 |
|
---|
5233 | /**
|
---|
5234 | * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsfc"}
|
---|
5235 | */
|
---|
5236 | DECLCALLBACK(void) vmsvgaR3Info3dSurface(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
5237 | {
|
---|
5238 | /* There might be a specific surface ID at the start of the
|
---|
5239 | arguments, if not show all surfaces. */
|
---|
5240 | uint32_t sid = UINT32_MAX;
|
---|
5241 | if (pszArgs)
|
---|
5242 | pszArgs = RTStrStripL(pszArgs);
|
---|
5243 | if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
|
---|
5244 | sid = RTStrToUInt32(pszArgs);
|
---|
5245 |
|
---|
5246 | /* Verbose or terse display, we default to verbose. */
|
---|
5247 | bool fVerbose = true;
|
---|
5248 | if (RTStrIStr(pszArgs, "terse"))
|
---|
5249 | fVerbose = false;
|
---|
5250 |
|
---|
5251 | /* The size of the ascii art (x direction, y is 3/4 of x). */
|
---|
5252 | uint32_t cxAscii = 80;
|
---|
5253 | if (RTStrIStr(pszArgs, "gigantic"))
|
---|
5254 | cxAscii = 300;
|
---|
5255 | else if (RTStrIStr(pszArgs, "huge"))
|
---|
5256 | cxAscii = 180;
|
---|
5257 | else if (RTStrIStr(pszArgs, "big"))
|
---|
5258 | cxAscii = 132;
|
---|
5259 | else if (RTStrIStr(pszArgs, "normal"))
|
---|
5260 | cxAscii = 80;
|
---|
5261 | else if (RTStrIStr(pszArgs, "medium"))
|
---|
5262 | cxAscii = 64;
|
---|
5263 | else if (RTStrIStr(pszArgs, "small"))
|
---|
5264 | cxAscii = 48;
|
---|
5265 | else if (RTStrIStr(pszArgs, "tiny"))
|
---|
5266 | cxAscii = 24;
|
---|
5267 |
|
---|
5268 | /* Y invert the image when producing the ASCII art. */
|
---|
5269 | bool fInvY = false;
|
---|
5270 | if (RTStrIStr(pszArgs, "invy"))
|
---|
5271 | fInvY = true;
|
---|
5272 |
|
---|
5273 | vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
|
---|
5274 | pHlp, sid, fVerbose, cxAscii, fInvY, NULL);
|
---|
5275 | }
|
---|
5276 |
|
---|
5277 |
|
---|
5278 | /**
|
---|
5279 | * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dsurf"}
|
---|
5280 | */
|
---|
5281 | DECLCALLBACK(void) vmsvgaR3Info3dSurfaceBmp(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
5282 | {
|
---|
5283 | /* pszArg = "sid[>dir]"
|
---|
5284 | * Writes %dir%/info-S-sidI.bmp, where S - sequential bitmap number, I - decimal surface id.
|
---|
5285 | */
|
---|
5286 | char *pszBitmapPath = NULL;
|
---|
5287 | uint32_t sid = UINT32_MAX;
|
---|
5288 | if (pszArgs)
|
---|
5289 | pszArgs = RTStrStripL(pszArgs);
|
---|
5290 | if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
|
---|
5291 | RTStrToUInt32Ex(pszArgs, &pszBitmapPath, 0, &sid);
|
---|
5292 | if ( pszBitmapPath
|
---|
5293 | && *pszBitmapPath == '>')
|
---|
5294 | ++pszBitmapPath;
|
---|
5295 |
|
---|
5296 | const bool fVerbose = true;
|
---|
5297 | const uint32_t cxAscii = 0; /* No ASCII */
|
---|
5298 | const bool fInvY = false; /* Do not invert. */
|
---|
5299 | vmsvga3dInfoSurfaceWorker(pDevIns, PDMDEVINS_2_DATA(pDevIns, PVGASTATE), PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC),
|
---|
5300 | pHlp, sid, fVerbose, cxAscii, fInvY, pszBitmapPath);
|
---|
5301 | }
|
---|
5302 |
|
---|
5303 | /**
|
---|
5304 | * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga3dctx"}
|
---|
5305 | */
|
---|
5306 | DECLCALLBACK(void) vmsvgaR3Info3dContext(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
5307 | {
|
---|
5308 | /* There might be a specific surface ID at the start of the
|
---|
5309 | arguments, if not show all contexts. */
|
---|
5310 | uint32_t sid = UINT32_MAX;
|
---|
5311 | if (pszArgs)
|
---|
5312 | pszArgs = RTStrStripL(pszArgs);
|
---|
5313 | if (pszArgs && RT_C_IS_DIGIT(*pszArgs))
|
---|
5314 | sid = RTStrToUInt32(pszArgs);
|
---|
5315 |
|
---|
5316 | /* Verbose or terse display, we default to verbose. */
|
---|
5317 | bool fVerbose = true;
|
---|
5318 | if (RTStrIStr(pszArgs, "terse"))
|
---|
5319 | fVerbose = false;
|
---|
5320 |
|
---|
5321 | vmsvga3dInfoContextWorker(PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC), pHlp, sid, fVerbose);
|
---|
5322 | }
|
---|
5323 | # endif /* VBOX_WITH_VMSVGA3D */
|
---|
5324 |
|
---|
5325 | /**
|
---|
5326 | * @callback_method_impl{FNDBGFHANDLERDEV, "vmsvga"}
|
---|
5327 | */
|
---|
5328 | static DECLCALLBACK(void) vmsvgaR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
|
---|
5329 | {
|
---|
5330 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
5331 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
5332 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5333 | uint32_t RT_UNTRUSTED_VOLATILE_GUEST *pFIFO = pThisCC->svga.pau32FIFO;
|
---|
5334 | RT_NOREF(pszArgs);
|
---|
5335 |
|
---|
5336 | pHlp->pfnPrintf(pHlp, "Extension enabled: %RTbool\n", pThis->svga.fEnabled);
|
---|
5337 | pHlp->pfnPrintf(pHlp, "Configured: %RTbool\n", pThis->svga.fConfigured);
|
---|
5338 | pHlp->pfnPrintf(pHlp, "Base I/O port: %#x\n",
|
---|
5339 | pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE
|
---|
5340 | ? PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPortVmSvga) : UINT32_MAX);
|
---|
5341 | pHlp->pfnPrintf(pHlp, "FIFO address: %RGp\n", pThis->svga.GCPhysFIFO);
|
---|
5342 | pHlp->pfnPrintf(pHlp, "FIFO size: %u (%#x)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO);
|
---|
5343 | pHlp->pfnPrintf(pHlp, "FIFO external cmd: %#x\n", pThis->svga.u8FIFOExtCommand);
|
---|
5344 | pHlp->pfnPrintf(pHlp, "FIFO extcmd wakeup: %u\n", pThis->svga.fFifoExtCommandWakeup);
|
---|
5345 | pHlp->pfnPrintf(pHlp, "FIFO min/max: %u/%u\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]);
|
---|
5346 | pHlp->pfnPrintf(pHlp, "Busy: %#x\n", pThis->svga.fBusy);
|
---|
5347 | pHlp->pfnPrintf(pHlp, "Traces: %RTbool (effective: %RTbool)\n", pThis->svga.fTraces, pThis->svga.fVRAMTracking);
|
---|
5348 | pHlp->pfnPrintf(pHlp, "Guest ID: %#x (%d)\n", pThis->svga.u32GuestId, pThis->svga.u32GuestId);
|
---|
5349 | pHlp->pfnPrintf(pHlp, "IRQ status: %#x\n", pThis->svga.u32IrqStatus);
|
---|
5350 | pHlp->pfnPrintf(pHlp, "IRQ mask: %#x\n", pThis->svga.u32IrqMask);
|
---|
5351 | pHlp->pfnPrintf(pHlp, "Pitch lock: %#x (FIFO:%#x)\n", pThis->svga.u32PitchLock, pFIFO[SVGA_FIFO_PITCHLOCK]);
|
---|
5352 | pHlp->pfnPrintf(pHlp, "Current GMR ID: %#x\n", pThis->svga.u32CurrentGMRId);
|
---|
5353 | pHlp->pfnPrintf(pHlp, "Device Capabilites: %#x\n", pThis->svga.u32DeviceCaps);
|
---|
5354 | pHlp->pfnPrintf(pHlp, "Index reg: %#x\n", pThis->svga.u32IndexReg);
|
---|
5355 | pHlp->pfnPrintf(pHlp, "Action flags: %#x\n", pThis->svga.u32ActionFlags);
|
---|
5356 | pHlp->pfnPrintf(pHlp, "Max display size: %ux%u\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight);
|
---|
5357 | pHlp->pfnPrintf(pHlp, "Display size: %ux%u %ubpp\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
|
---|
5358 | pHlp->pfnPrintf(pHlp, "Scanline: %u (%#x)\n", pThis->svga.cbScanline, pThis->svga.cbScanline);
|
---|
5359 | pHlp->pfnPrintf(pHlp, "Viewport position: %ux%u\n", pThis->svga.viewport.x, pThis->svga.viewport.y);
|
---|
5360 | pHlp->pfnPrintf(pHlp, "Viewport size: %ux%u\n", pThis->svga.viewport.cx, pThis->svga.viewport.cy);
|
---|
5361 |
|
---|
5362 | pHlp->pfnPrintf(pHlp, "Cursor active: %RTbool\n", pSVGAState->Cursor.fActive);
|
---|
5363 | pHlp->pfnPrintf(pHlp, "Cursor hotspot: %ux%u\n", pSVGAState->Cursor.xHotspot, pSVGAState->Cursor.yHotspot);
|
---|
5364 | pHlp->pfnPrintf(pHlp, "Cursor size: %ux%u\n", pSVGAState->Cursor.width, pSVGAState->Cursor.height);
|
---|
5365 | pHlp->pfnPrintf(pHlp, "Cursor byte size: %u (%#x)\n", pSVGAState->Cursor.cbData, pSVGAState->Cursor.cbData);
|
---|
5366 |
|
---|
5367 | pHlp->pfnPrintf(pHlp, "FIFO cursor: state %u, screen %d\n", pFIFO[SVGA_FIFO_CURSOR_ON], pFIFO[SVGA_FIFO_CURSOR_SCREEN_ID]);
|
---|
5368 | pHlp->pfnPrintf(pHlp, "FIFO cursor at: %u,%u\n", pFIFO[SVGA_FIFO_CURSOR_X], pFIFO[SVGA_FIFO_CURSOR_Y]);
|
---|
5369 |
|
---|
5370 | pHlp->pfnPrintf(pHlp, "Legacy cursor: ID %u, state %u\n", pThis->svga.uCursorID, pThis->svga.uCursorOn);
|
---|
5371 | pHlp->pfnPrintf(pHlp, "Legacy cursor at: %u,%u\n", pThis->svga.uCursorX, pThis->svga.uCursorY);
|
---|
5372 |
|
---|
5373 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5374 | pHlp->pfnPrintf(pHlp, "3D enabled: %RTbool\n", pThis->svga.f3DEnabled);
|
---|
5375 | # endif
|
---|
5376 | if (pThisCC->pDrv)
|
---|
5377 | {
|
---|
5378 | pHlp->pfnPrintf(pHlp, "Driver mode: %ux%u %ubpp\n", pThisCC->pDrv->cx, pThisCC->pDrv->cy, pThisCC->pDrv->cBits);
|
---|
5379 | pHlp->pfnPrintf(pHlp, "Driver pitch: %u (%#x)\n", pThisCC->pDrv->cbScanline, pThisCC->pDrv->cbScanline);
|
---|
5380 | }
|
---|
5381 |
|
---|
5382 | /* Dump screen information. */
|
---|
5383 | for (unsigned iScreen = 0; iScreen < RT_ELEMENTS(pSVGAState->aScreens); ++iScreen)
|
---|
5384 | {
|
---|
5385 | VMSVGASCREENOBJECT *pScreen = vmsvgaR3GetScreenObject(pThisCC, iScreen);
|
---|
5386 | if (pScreen)
|
---|
5387 | {
|
---|
5388 | pHlp->pfnPrintf(pHlp, "Screen %u defined (ID %u):\n", iScreen, pScreen->idScreen);
|
---|
5389 | pHlp->pfnPrintf(pHlp, " %u x %u x %ubpp @ %u, %u\n", pScreen->cWidth, pScreen->cHeight,
|
---|
5390 | pScreen->cBpp, pScreen->xOrigin, pScreen->yOrigin);
|
---|
5391 | pHlp->pfnPrintf(pHlp, " Pitch %u bytes, VRAM offset %X\n", pScreen->cbPitch, pScreen->offVRAM);
|
---|
5392 | pHlp->pfnPrintf(pHlp, " Flags %X", pScreen->fuScreen);
|
---|
5393 | if (pScreen->fuScreen != SVGA_SCREEN_MUST_BE_SET)
|
---|
5394 | {
|
---|
5395 | pHlp->pfnPrintf(pHlp, " (");
|
---|
5396 | if (pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY)
|
---|
5397 | pHlp->pfnPrintf(pHlp, " IS_PRIMARY");
|
---|
5398 | if (pScreen->fuScreen & SVGA_SCREEN_FULLSCREEN_HINT)
|
---|
5399 | pHlp->pfnPrintf(pHlp, " FULLSCREEN_HINT");
|
---|
5400 | if (pScreen->fuScreen & SVGA_SCREEN_DEACTIVATE)
|
---|
5401 | pHlp->pfnPrintf(pHlp, " DEACTIVATE");
|
---|
5402 | if (pScreen->fuScreen & SVGA_SCREEN_BLANKING)
|
---|
5403 | pHlp->pfnPrintf(pHlp, " BLANKING");
|
---|
5404 | pHlp->pfnPrintf(pHlp, " )");
|
---|
5405 | }
|
---|
5406 | pHlp->pfnPrintf(pHlp, ", %smodified\n", pScreen->fModified ? "" : "not ");
|
---|
5407 | }
|
---|
5408 | }
|
---|
5409 |
|
---|
5410 | }
|
---|
5411 |
|
---|
5412 | /**
|
---|
5413 | * Portion of VMSVGA state which must be loaded oin the FIFO thread.
|
---|
5414 | */
|
---|
5415 | static int vmsvgaR3LoadExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PVGASTATECC pThisCC,
|
---|
5416 | PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
5417 | {
|
---|
5418 | RT_NOREF(uPass);
|
---|
5419 |
|
---|
5420 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5421 | int rc;
|
---|
5422 |
|
---|
5423 | if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_SCREENS)
|
---|
5424 | {
|
---|
5425 | uint32_t cScreens = 0;
|
---|
5426 | rc = pHlp->pfnSSMGetU32(pSSM, &cScreens);
|
---|
5427 | AssertRCReturn(rc, rc);
|
---|
5428 | AssertLogRelMsgReturn(cScreens <= _64K, /* big enough */
|
---|
5429 | ("cScreens=%#x\n", cScreens),
|
---|
5430 | VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
|
---|
5431 |
|
---|
5432 | for (uint32_t i = 0; i < cScreens; ++i)
|
---|
5433 | {
|
---|
5434 | VMSVGASCREENOBJECT screen;
|
---|
5435 | RT_ZERO(screen);
|
---|
5436 |
|
---|
5437 | rc = pHlp->pfnSSMGetStructEx(pSSM, &screen, sizeof(screen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
|
---|
5438 | AssertLogRelRCReturn(rc, rc);
|
---|
5439 |
|
---|
5440 | if (screen.idScreen < RT_ELEMENTS(pSVGAState->aScreens))
|
---|
5441 | {
|
---|
5442 | VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[screen.idScreen];
|
---|
5443 | *pScreen = screen;
|
---|
5444 | pScreen->fModified = true;
|
---|
5445 | }
|
---|
5446 | else
|
---|
5447 | {
|
---|
5448 | LogRel(("VGA: ignored screen object %d\n", screen.idScreen));
|
---|
5449 | }
|
---|
5450 | }
|
---|
5451 | }
|
---|
5452 | else
|
---|
5453 | {
|
---|
5454 | /* Try to setup at least the first screen. */
|
---|
5455 | VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[0];
|
---|
5456 | pScreen->fDefined = true;
|
---|
5457 | pScreen->fModified = true;
|
---|
5458 | pScreen->fuScreen = SVGA_SCREEN_MUST_BE_SET | SVGA_SCREEN_IS_PRIMARY;
|
---|
5459 | pScreen->idScreen = 0;
|
---|
5460 | pScreen->xOrigin = 0;
|
---|
5461 | pScreen->yOrigin = 0;
|
---|
5462 | pScreen->offVRAM = pThis->svga.uScreenOffset;
|
---|
5463 | pScreen->cbPitch = pThis->svga.cbScanline;
|
---|
5464 | pScreen->cWidth = pThis->svga.uWidth;
|
---|
5465 | pScreen->cHeight = pThis->svga.uHeight;
|
---|
5466 | pScreen->cBpp = pThis->svga.uBpp;
|
---|
5467 | }
|
---|
5468 |
|
---|
5469 | return VINF_SUCCESS;
|
---|
5470 | }
|
---|
5471 |
|
---|
5472 | /**
|
---|
5473 | * @copydoc FNSSMDEVLOADEXEC
|
---|
5474 | */
|
---|
5475 | int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
|
---|
5476 | {
|
---|
5477 | RT_NOREF(uPass);
|
---|
5478 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
5479 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
5480 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5481 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
5482 | int rc;
|
---|
5483 |
|
---|
5484 | /* Load our part of the VGAState */
|
---|
5485 | rc = pHlp->pfnSSMGetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
|
---|
5486 | AssertRCReturn(rc, rc);
|
---|
5487 |
|
---|
5488 | /* Load the VGA framebuffer. */
|
---|
5489 | AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE >= _32K);
|
---|
5490 | uint32_t cbVgaFramebuffer = _32K;
|
---|
5491 | if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_VGA_FB_FIX)
|
---|
5492 | {
|
---|
5493 | rc = pHlp->pfnSSMGetU32(pSSM, &cbVgaFramebuffer);
|
---|
5494 | AssertRCReturn(rc, rc);
|
---|
5495 | AssertLogRelMsgReturn(cbVgaFramebuffer <= _4M && cbVgaFramebuffer >= _32K && RT_IS_POWER_OF_TWO(cbVgaFramebuffer),
|
---|
5496 | ("cbVgaFramebuffer=%#x - expected 32KB..4MB, power of two\n", cbVgaFramebuffer),
|
---|
5497 | VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
|
---|
5498 | AssertCompile(VMSVGA_VGA_FB_BACKUP_SIZE <= _4M);
|
---|
5499 | AssertCompile(RT_IS_POWER_OF_TWO(VMSVGA_VGA_FB_BACKUP_SIZE));
|
---|
5500 | }
|
---|
5501 | rc = pHlp->pfnSSMGetMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, RT_MIN(cbVgaFramebuffer, VMSVGA_VGA_FB_BACKUP_SIZE));
|
---|
5502 | AssertRCReturn(rc, rc);
|
---|
5503 | if (cbVgaFramebuffer > VMSVGA_VGA_FB_BACKUP_SIZE)
|
---|
5504 | pHlp->pfnSSMSkip(pSSM, cbVgaFramebuffer - VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
5505 | else if (cbVgaFramebuffer < VMSVGA_VGA_FB_BACKUP_SIZE)
|
---|
5506 | RT_BZERO(&pThisCC->svga.pbVgaFrameBufferR3[cbVgaFramebuffer], VMSVGA_VGA_FB_BACKUP_SIZE - cbVgaFramebuffer);
|
---|
5507 |
|
---|
5508 | /* Load the VMSVGA state. */
|
---|
5509 | rc = pHlp->pfnSSMGetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
|
---|
5510 | AssertRCReturn(rc, rc);
|
---|
5511 |
|
---|
5512 | /* Load the active cursor bitmaps. */
|
---|
5513 | if (pSVGAState->Cursor.fActive)
|
---|
5514 | {
|
---|
5515 | pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
|
---|
5516 | AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
|
---|
5517 |
|
---|
5518 | rc = pHlp->pfnSSMGetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
|
---|
5519 | AssertRCReturn(rc, rc);
|
---|
5520 | }
|
---|
5521 |
|
---|
5522 | /* Load the GMR state. */
|
---|
5523 | uint32_t cGMR = 256; /* Hardcoded in previous saved state versions. */
|
---|
5524 | if (uVersion >= VGA_SAVEDSTATE_VERSION_VMSVGA_GMR_COUNT)
|
---|
5525 | {
|
---|
5526 | rc = pHlp->pfnSSMGetU32(pSSM, &cGMR);
|
---|
5527 | AssertRCReturn(rc, rc);
|
---|
5528 | /* Numbers of GMRs was never less than 256. 1MB is a large arbitrary limit. */
|
---|
5529 | AssertLogRelMsgReturn(cGMR <= _1M && cGMR >= 256,
|
---|
5530 | ("cGMR=%#x - expected 256B..1MB\n", cGMR),
|
---|
5531 | VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
|
---|
5532 | }
|
---|
5533 |
|
---|
5534 | if (pThis->svga.cGMR != cGMR)
|
---|
5535 | {
|
---|
5536 | /* Reallocate GMR array. */
|
---|
5537 | Assert(pSVGAState->paGMR != NULL);
|
---|
5538 | RTMemFree(pSVGAState->paGMR);
|
---|
5539 | pSVGAState->paGMR = (PGMR)RTMemAllocZ(cGMR * sizeof(GMR));
|
---|
5540 | AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
|
---|
5541 | pThis->svga.cGMR = cGMR;
|
---|
5542 | }
|
---|
5543 |
|
---|
5544 | for (uint32_t i = 0; i < cGMR; ++i)
|
---|
5545 | {
|
---|
5546 | PGMR pGMR = &pSVGAState->paGMR[i];
|
---|
5547 |
|
---|
5548 | rc = pHlp->pfnSSMGetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
|
---|
5549 | AssertRCReturn(rc, rc);
|
---|
5550 |
|
---|
5551 | if (pGMR->numDescriptors)
|
---|
5552 | {
|
---|
5553 | Assert(pGMR->cMaxPages || pGMR->cbTotal);
|
---|
5554 | pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->numDescriptors * sizeof(VMSVGAGMRDESCRIPTOR));
|
---|
5555 | AssertReturn(pGMR->paDesc, VERR_NO_MEMORY);
|
---|
5556 |
|
---|
5557 | for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
|
---|
5558 | {
|
---|
5559 | rc = pHlp->pfnSSMGetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
|
---|
5560 | AssertRCReturn(rc, rc);
|
---|
5561 | }
|
---|
5562 | }
|
---|
5563 | }
|
---|
5564 |
|
---|
5565 | # ifdef RT_OS_DARWIN /** @todo r=bird: this is normally done on the EMT, so for DARWIN we do that when loading saved state too now. See DevVGA-SVGA3d-shared.h. */
|
---|
5566 | if (pThis->svga.f3DEnabled)
|
---|
5567 | pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
|
---|
5568 | # endif
|
---|
5569 |
|
---|
5570 | VMSVGA_STATE_LOAD LoadState;
|
---|
5571 | LoadState.pSSM = pSSM;
|
---|
5572 | LoadState.uVersion = uVersion;
|
---|
5573 | LoadState.uPass = uPass;
|
---|
5574 | rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_LOADSTATE, &LoadState, RT_INDEFINITE_WAIT);
|
---|
5575 | AssertLogRelRCReturn(rc, rc);
|
---|
5576 |
|
---|
5577 | return VINF_SUCCESS;
|
---|
5578 | }
|
---|
5579 |
|
---|
5580 | /**
|
---|
5581 | * Reinit the video mode after the state has been loaded.
|
---|
5582 | */
|
---|
5583 | int vmsvgaR3LoadDone(PPDMDEVINS pDevIns)
|
---|
5584 | {
|
---|
5585 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
5586 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
5587 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5588 |
|
---|
5589 | /* Set the active cursor. */
|
---|
5590 | if (pSVGAState->Cursor.fActive)
|
---|
5591 | {
|
---|
5592 | /* We don't store the alpha flag, but we can take a guess that if
|
---|
5593 | * the old register interface was used, the cursor was B&W.
|
---|
5594 | */
|
---|
5595 | bool fAlpha = pThis->svga.uCursorOn ? false : true;
|
---|
5596 |
|
---|
5597 | int rc = pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv,
|
---|
5598 | true /*fVisible*/,
|
---|
5599 | fAlpha,
|
---|
5600 | pSVGAState->Cursor.xHotspot,
|
---|
5601 | pSVGAState->Cursor.yHotspot,
|
---|
5602 | pSVGAState->Cursor.width,
|
---|
5603 | pSVGAState->Cursor.height,
|
---|
5604 | pSVGAState->Cursor.pData);
|
---|
5605 | AssertRC(rc);
|
---|
5606 |
|
---|
5607 | if (pThis->svga.uCursorOn)
|
---|
5608 | pThisCC->pDrv->pfnVBVAReportCursorPosition(pThisCC->pDrv, VBVA_CURSOR_VALID_DATA, SVGA_ID_INVALID, pThis->svga.uCursorX, pThis->svga.uCursorY);
|
---|
5609 | }
|
---|
5610 |
|
---|
5611 | /* If the VRAM handler should not be registered, we have to explicitly
|
---|
5612 | * unregister it here!
|
---|
5613 | */
|
---|
5614 | if (!pThis->svga.fVRAMTracking)
|
---|
5615 | {
|
---|
5616 | vgaR3UnregisterVRAMHandler(pDevIns, pThis);
|
---|
5617 | }
|
---|
5618 |
|
---|
5619 | /* Let the FIFO thread deal with changing the mode. */
|
---|
5620 | ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
|
---|
5621 |
|
---|
5622 | return VINF_SUCCESS;
|
---|
5623 | }
|
---|
5624 |
|
---|
5625 | /**
|
---|
5626 | * Portion of SVGA state which must be saved in the FIFO thread.
|
---|
5627 | */
|
---|
5628 | static int vmsvgaR3SaveExecFifo(PCPDMDEVHLPR3 pHlp, PVGASTATECC pThisCC, PSSMHANDLE pSSM)
|
---|
5629 | {
|
---|
5630 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5631 | int rc;
|
---|
5632 |
|
---|
5633 | /* Save the screen objects. */
|
---|
5634 | /* Count defined screen object. */
|
---|
5635 | uint32_t cScreens = 0;
|
---|
5636 | for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aScreens); ++i)
|
---|
5637 | {
|
---|
5638 | if (pSVGAState->aScreens[i].fDefined)
|
---|
5639 | ++cScreens;
|
---|
5640 | }
|
---|
5641 |
|
---|
5642 | rc = pHlp->pfnSSMPutU32(pSSM, cScreens);
|
---|
5643 | AssertLogRelRCReturn(rc, rc);
|
---|
5644 |
|
---|
5645 | for (uint32_t i = 0; i < cScreens; ++i)
|
---|
5646 | {
|
---|
5647 | VMSVGASCREENOBJECT *pScreen = &pSVGAState->aScreens[i];
|
---|
5648 |
|
---|
5649 | rc = pHlp->pfnSSMPutStructEx(pSSM, pScreen, sizeof(*pScreen), 0, g_aVMSVGASCREENOBJECTFields, NULL);
|
---|
5650 | AssertLogRelRCReturn(rc, rc);
|
---|
5651 | }
|
---|
5652 | return VINF_SUCCESS;
|
---|
5653 | }
|
---|
5654 |
|
---|
5655 | /**
|
---|
5656 | * @copydoc FNSSMDEVSAVEEXEC
|
---|
5657 | */
|
---|
5658 | int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
|
---|
5659 | {
|
---|
5660 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
5661 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
5662 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5663 | PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
|
---|
5664 | int rc;
|
---|
5665 |
|
---|
5666 | /* Save our part of the VGAState */
|
---|
5667 | rc = pHlp->pfnSSMPutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
|
---|
5668 | AssertLogRelRCReturn(rc, rc);
|
---|
5669 |
|
---|
5670 | /* Save the framebuffer backup. */
|
---|
5671 | rc = pHlp->pfnSSMPutU32(pSSM, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
5672 | rc = pHlp->pfnSSMPutMem(pSSM, pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
5673 | AssertLogRelRCReturn(rc, rc);
|
---|
5674 |
|
---|
5675 | /* Save the VMSVGA state. */
|
---|
5676 | rc = pHlp->pfnSSMPutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGAR3STATEFields, NULL);
|
---|
5677 | AssertLogRelRCReturn(rc, rc);
|
---|
5678 |
|
---|
5679 | /* Save the active cursor bitmaps. */
|
---|
5680 | if (pSVGAState->Cursor.fActive)
|
---|
5681 | {
|
---|
5682 | rc = pHlp->pfnSSMPutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
|
---|
5683 | AssertLogRelRCReturn(rc, rc);
|
---|
5684 | }
|
---|
5685 |
|
---|
5686 | /* Save the GMR state */
|
---|
5687 | rc = pHlp->pfnSSMPutU32(pSSM, pThis->svga.cGMR);
|
---|
5688 | AssertLogRelRCReturn(rc, rc);
|
---|
5689 | for (uint32_t i = 0; i < pThis->svga.cGMR; ++i)
|
---|
5690 | {
|
---|
5691 | PGMR pGMR = &pSVGAState->paGMR[i];
|
---|
5692 |
|
---|
5693 | rc = pHlp->pfnSSMPutStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
|
---|
5694 | AssertLogRelRCReturn(rc, rc);
|
---|
5695 |
|
---|
5696 | for (uint32_t j = 0; j < pGMR->numDescriptors; ++j)
|
---|
5697 | {
|
---|
5698 | rc = pHlp->pfnSSMPutStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
|
---|
5699 | AssertLogRelRCReturn(rc, rc);
|
---|
5700 | }
|
---|
5701 | }
|
---|
5702 |
|
---|
5703 | /*
|
---|
5704 | * Must save some state (3D in particular) in the FIFO thread.
|
---|
5705 | */
|
---|
5706 | rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_SAVESTATE, pSSM, RT_INDEFINITE_WAIT);
|
---|
5707 | AssertLogRelRCReturn(rc, rc);
|
---|
5708 |
|
---|
5709 | return VINF_SUCCESS;
|
---|
5710 | }
|
---|
5711 |
|
---|
5712 | /**
|
---|
5713 | * Destructor for PVMSVGAR3STATE structure. The structure is not deallocated.
|
---|
5714 | *
|
---|
5715 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
5716 | * @param pThisCC The device context.
|
---|
5717 | */
|
---|
5718 | static void vmsvgaR3StateTerm(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
5719 | {
|
---|
5720 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5721 |
|
---|
5722 | # ifndef VMSVGA_USE_EMT_HALT_CODE
|
---|
5723 | if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
|
---|
5724 | {
|
---|
5725 | RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
|
---|
5726 | pSVGAState->hBusyDelayedEmts = NIL_RTSEMEVENT;
|
---|
5727 | }
|
---|
5728 | # endif
|
---|
5729 |
|
---|
5730 | if (pSVGAState->Cursor.fActive)
|
---|
5731 | {
|
---|
5732 | RTMemFreeZ(pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
|
---|
5733 | pSVGAState->Cursor.pData = NULL;
|
---|
5734 | pSVGAState->Cursor.fActive = false;
|
---|
5735 | }
|
---|
5736 |
|
---|
5737 | if (pSVGAState->paGMR)
|
---|
5738 | {
|
---|
5739 | for (unsigned i = 0; i < pThis->svga.cGMR; ++i)
|
---|
5740 | if (pSVGAState->paGMR[i].paDesc)
|
---|
5741 | RTMemFree(pSVGAState->paGMR[i].paDesc);
|
---|
5742 |
|
---|
5743 | RTMemFree(pSVGAState->paGMR);
|
---|
5744 | pSVGAState->paGMR = NULL;
|
---|
5745 | }
|
---|
5746 |
|
---|
5747 | if (RTCritSectIsInitialized(&pSVGAState->CritSectCmdBuf))
|
---|
5748 | {
|
---|
5749 | RTCritSectEnter(&pSVGAState->CritSectCmdBuf);
|
---|
5750 | for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->apCmdBufCtxs); ++i)
|
---|
5751 | {
|
---|
5752 | vmsvgaR3CmdBufCtxTerm(pSVGAState->apCmdBufCtxs[i]);
|
---|
5753 | pSVGAState->apCmdBufCtxs[i] = NULL;
|
---|
5754 | }
|
---|
5755 | vmsvgaR3CmdBufCtxTerm(&pSVGAState->CmdBufCtxDC);
|
---|
5756 | RTCritSectLeave(&pSVGAState->CritSectCmdBuf);
|
---|
5757 | RTCritSectDelete(&pSVGAState->CritSectCmdBuf);
|
---|
5758 | }
|
---|
5759 | }
|
---|
5760 |
|
---|
5761 | /**
|
---|
5762 | * Constructor for PVMSVGAR3STATE structure.
|
---|
5763 | *
|
---|
5764 | * @returns VBox status code.
|
---|
5765 | * @param pDevIns The PDM device instance.
|
---|
5766 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
5767 | * @param pSVGAState Pointer to the structure. It is already allocated.
|
---|
5768 | */
|
---|
5769 | static int vmsvgaR3StateInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVMSVGAR3STATE pSVGAState)
|
---|
5770 | {
|
---|
5771 | int rc = VINF_SUCCESS;
|
---|
5772 |
|
---|
5773 | pSVGAState->pDevIns = pDevIns;
|
---|
5774 |
|
---|
5775 | pSVGAState->paGMR = (PGMR)RTMemAllocZ(pThis->svga.cGMR * sizeof(GMR));
|
---|
5776 | AssertReturn(pSVGAState->paGMR, VERR_NO_MEMORY);
|
---|
5777 |
|
---|
5778 | # ifndef VMSVGA_USE_EMT_HALT_CODE
|
---|
5779 | /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
|
---|
5780 | rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
|
---|
5781 | AssertRCReturn(rc, rc);
|
---|
5782 | # endif
|
---|
5783 |
|
---|
5784 | rc = RTCritSectInit(&pSVGAState->CritSectCmdBuf);
|
---|
5785 | AssertRCReturn(rc, rc);
|
---|
5786 |
|
---|
5787 | vmsvgaR3CmdBufCtxInit(&pSVGAState->CmdBufCtxDC);
|
---|
5788 |
|
---|
5789 | RTListInit(&pSVGAState->MOBLRUList);
|
---|
5790 | return rc;
|
---|
5791 | }
|
---|
5792 |
|
---|
5793 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5794 | static void vmsvga3dR3Free3dInterfaces(PVGASTATECC pThisCC)
|
---|
5795 | {
|
---|
5796 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5797 |
|
---|
5798 | RTMemFree(pSVGAState->pFuncsMap);
|
---|
5799 | pSVGAState->pFuncsMap = NULL;
|
---|
5800 | RTMemFree(pSVGAState->pFuncsGBO);
|
---|
5801 | pSVGAState->pFuncsGBO = NULL;
|
---|
5802 | RTMemFree(pSVGAState->pFuncsDX);
|
---|
5803 | pSVGAState->pFuncsDX = NULL;
|
---|
5804 | RTMemFree(pSVGAState->pFuncsVGPU9);
|
---|
5805 | pSVGAState->pFuncsVGPU9 = NULL;
|
---|
5806 | RTMemFree(pSVGAState->pFuncs3D);
|
---|
5807 | pSVGAState->pFuncs3D = NULL;
|
---|
5808 | }
|
---|
5809 |
|
---|
5810 | /* This structure is used only by vmsvgaR3Init3dInterfaces */
|
---|
5811 | typedef struct VMSVGA3DINTERFACE
|
---|
5812 | {
|
---|
5813 | char const *pcszName;
|
---|
5814 | uint32_t cbFuncs;
|
---|
5815 | void **ppvFuncs;
|
---|
5816 | } VMSVGA3DINTERFACE;
|
---|
5817 |
|
---|
5818 | extern VMSVGA3DBACKENDDESC const g_BackendLegacy;
|
---|
5819 | #ifdef VMSVGA3D_DX
|
---|
5820 | extern VMSVGA3DBACKENDDESC const g_BackendDX;
|
---|
5821 | #endif
|
---|
5822 |
|
---|
5823 | /**
|
---|
5824 | * Initializes the optional host 3D backend interfaces.
|
---|
5825 | *
|
---|
5826 | * @returns VBox status code.
|
---|
5827 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
5828 | */
|
---|
5829 | static int vmsvgaR3Init3dInterfaces(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
5830 | {
|
---|
5831 | #ifndef VMSVGA3D_DX
|
---|
5832 | RT_NOREF(pThis);
|
---|
5833 | #endif
|
---|
5834 |
|
---|
5835 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5836 |
|
---|
5837 | #define ENTRY_3D_INTERFACE(a_Name, a_Field) { VMSVGA3D_BACKEND_INTERFACE_NAME_##a_Name, sizeof(VMSVGA3DBACKENDFUNCS##a_Name), (void **)&pSVGAState->a_Field }
|
---|
5838 | VMSVGA3DINTERFACE a3dInterface[] =
|
---|
5839 | {
|
---|
5840 | ENTRY_3D_INTERFACE(3D, pFuncs3D),
|
---|
5841 | ENTRY_3D_INTERFACE(VGPU9, pFuncsVGPU9),
|
---|
5842 | ENTRY_3D_INTERFACE(DX, pFuncsDX),
|
---|
5843 | ENTRY_3D_INTERFACE(MAP, pFuncsMap),
|
---|
5844 | ENTRY_3D_INTERFACE(GBO, pFuncsGBO),
|
---|
5845 | };
|
---|
5846 | #undef ENTRY_3D_INTERFACE
|
---|
5847 |
|
---|
5848 | VMSVGA3DBACKENDDESC const *pBackend = NULL;
|
---|
5849 | #ifdef VMSVGA3D_DX
|
---|
5850 | if (pThis->fVMSVGA10)
|
---|
5851 | pBackend = &g_BackendDX;
|
---|
5852 | else
|
---|
5853 | #endif
|
---|
5854 | pBackend = &g_BackendLegacy;
|
---|
5855 |
|
---|
5856 | int rc = VINF_SUCCESS;
|
---|
5857 | for (uint32_t i = 0; i < RT_ELEMENTS(a3dInterface); ++i)
|
---|
5858 | {
|
---|
5859 | VMSVGA3DINTERFACE *p = &a3dInterface[i];
|
---|
5860 |
|
---|
5861 | int rc2 = pBackend->pfnQueryInterface(pThisCC, p->pcszName, NULL, p->cbFuncs);
|
---|
5862 | if (RT_SUCCESS(rc2))
|
---|
5863 | {
|
---|
5864 | *p->ppvFuncs = RTMemAllocZ(p->cbFuncs);
|
---|
5865 | AssertBreakStmt(*p->ppvFuncs, rc = VERR_NO_MEMORY);
|
---|
5866 |
|
---|
5867 | pBackend->pfnQueryInterface(pThisCC, p->pcszName, *p->ppvFuncs, p->cbFuncs);
|
---|
5868 | }
|
---|
5869 | }
|
---|
5870 |
|
---|
5871 | if (RT_SUCCESS(rc))
|
---|
5872 | {
|
---|
5873 | /* 3D interface is required. */
|
---|
5874 | if (pSVGAState->pFuncs3D)
|
---|
5875 | {
|
---|
5876 | rc = pSVGAState->pFuncs3D->pfnInit(pDevIns, pThis, pThisCC);
|
---|
5877 | if (RT_SUCCESS(rc))
|
---|
5878 | return VINF_SUCCESS;
|
---|
5879 | }
|
---|
5880 | else
|
---|
5881 | rc = VERR_NOT_SUPPORTED;
|
---|
5882 | }
|
---|
5883 |
|
---|
5884 | vmsvga3dR3Free3dInterfaces(pThisCC);
|
---|
5885 | return rc;
|
---|
5886 | }
|
---|
5887 | # endif /* VBOX_WITH_VMSVGA3D */
|
---|
5888 |
|
---|
5889 | /**
|
---|
5890 | * Initializes the host capabilities: device and FIFO.
|
---|
5891 | *
|
---|
5892 | * @returns VBox status code.
|
---|
5893 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
5894 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
5895 | */
|
---|
5896 | static void vmsvgaR3InitCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
5897 | {
|
---|
5898 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5899 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
5900 | # endif
|
---|
5901 |
|
---|
5902 | /* Device caps. */
|
---|
5903 | pThis->svga.u32DeviceCaps = SVGA_CAP_GMR
|
---|
5904 | | SVGA_CAP_GMR2
|
---|
5905 | | SVGA_CAP_CURSOR
|
---|
5906 | | SVGA_CAP_CURSOR_BYPASS
|
---|
5907 | | SVGA_CAP_CURSOR_BYPASS_2
|
---|
5908 | | SVGA_CAP_EXTENDED_FIFO
|
---|
5909 | | SVGA_CAP_IRQMASK
|
---|
5910 | | SVGA_CAP_PITCHLOCK
|
---|
5911 | | SVGA_CAP_RECT_COPY
|
---|
5912 | | SVGA_CAP_TRACES
|
---|
5913 | | SVGA_CAP_SCREEN_OBJECT_2
|
---|
5914 | | SVGA_CAP_ALPHA_CURSOR;
|
---|
5915 |
|
---|
5916 | /* VGPU10 capabilities. */
|
---|
5917 | if (pThis->fVMSVGA10)
|
---|
5918 | {
|
---|
5919 | pThis->svga.u32DeviceCaps |= SVGA_CAP_COMMAND_BUFFERS /* Enable register based command buffer submission. */
|
---|
5920 | // | SVGA_CAP_CMD_BUFFERS_2 /* Support for SVGA_REG_CMD_PREPEND_LOW/HIGH */
|
---|
5921 | ;
|
---|
5922 |
|
---|
5923 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5924 | if (pSVGAState->pFuncsGBO)
|
---|
5925 | pThis->svga.u32DeviceCaps |= SVGA_CAP_GBOBJECTS; /* Enable guest-backed objects and surfaces. */
|
---|
5926 | if (pSVGAState->pFuncsDX)
|
---|
5927 | pThis->svga.u32DeviceCaps |= SVGA_CAP_DX; /* Enable support for DX commands, and command buffers in a mob. */
|
---|
5928 | # endif
|
---|
5929 | }
|
---|
5930 |
|
---|
5931 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5932 | if (pSVGAState->pFuncs3D)
|
---|
5933 | pThis->svga.u32DeviceCaps |= SVGA_CAP_3D;
|
---|
5934 | # endif
|
---|
5935 |
|
---|
5936 | /* Clear the FIFO. */
|
---|
5937 | RT_BZERO(pThisCC->svga.pau32FIFO, pThis->svga.cbFIFO);
|
---|
5938 |
|
---|
5939 | /* Setup FIFO capabilities. */
|
---|
5940 | pThisCC->svga.pau32FIFO[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE
|
---|
5941 | | SVGA_FIFO_CAP_PITCHLOCK
|
---|
5942 | | SVGA_FIFO_CAP_CURSOR_BYPASS_3
|
---|
5943 | | SVGA_FIFO_CAP_RESERVE
|
---|
5944 | | SVGA_FIFO_CAP_GMR2
|
---|
5945 | | SVGA_FIFO_CAP_3D_HWVERSION_REVISED
|
---|
5946 | | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
|
---|
5947 |
|
---|
5948 | /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
|
---|
5949 | pThisCC->svga.pau32FIFO[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
|
---|
5950 | }
|
---|
5951 |
|
---|
5952 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
5953 | /**
|
---|
5954 | * Initializes the host 3D capabilities and writes them to FIFO memory.
|
---|
5955 | *
|
---|
5956 | * @returns VBox status code.
|
---|
5957 | * @param pThis The shared VGA/VMSVGA instance data.
|
---|
5958 | * @param pThisCC The VGA/VMSVGA state for ring-3.
|
---|
5959 | */
|
---|
5960 | static void vmsvgaR3InitFifo3DCaps(PVGASTATE pThis, PVGASTATECC pThisCC)
|
---|
5961 | {
|
---|
5962 | /* Query the capabilities and store them in the pThis->svga.au32DevCaps array. */
|
---|
5963 | bool const fSavedBuffering = RTLogRelSetBuffering(true);
|
---|
5964 |
|
---|
5965 | for (unsigned i = 0; i < RT_ELEMENTS(pThis->svga.au32DevCaps); ++i)
|
---|
5966 | {
|
---|
5967 | uint32_t val = 0;
|
---|
5968 | int rc = vmsvga3dQueryCaps(pThisCC, (SVGA3dDevCapIndex)i, &val);
|
---|
5969 | if (RT_SUCCESS(rc))
|
---|
5970 | pThis->svga.au32DevCaps[i] = val;
|
---|
5971 | else
|
---|
5972 | pThis->svga.au32DevCaps[i] = 0;
|
---|
5973 |
|
---|
5974 | /* LogRel the capability value. */
|
---|
5975 | if (i < SVGA3D_DEVCAP_MAX)
|
---|
5976 | {
|
---|
5977 | char const *pszDevCapName = &vmsvgaDevCapIndexToString((SVGA3dDevCapIndex)i)[sizeof("SVGA3D_DEVCAP")];
|
---|
5978 | if (RT_SUCCESS(rc))
|
---|
5979 | {
|
---|
5980 | if ( i == SVGA3D_DEVCAP_MAX_POINT_SIZE
|
---|
5981 | || i == SVGA3D_DEVCAP_MAX_LINE_WIDTH
|
---|
5982 | || i == SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH)
|
---|
5983 | {
|
---|
5984 | float const fval = *(float *)&val;
|
---|
5985 | LogRel(("VMSVGA3d: cap[%u]=" FLOAT_FMT_STR " {%s}\n", i, FLOAT_FMT_ARGS(fval), pszDevCapName));
|
---|
5986 | }
|
---|
5987 | else
|
---|
5988 | LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, pszDevCapName));
|
---|
5989 | }
|
---|
5990 | else
|
---|
5991 | LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc {%s}\n", i, rc, pszDevCapName));
|
---|
5992 | }
|
---|
5993 | else
|
---|
5994 | LogRel(("VMSVGA3d: new cap[%u]=%#010x rc=%Rrc\n", i, val, rc));
|
---|
5995 | }
|
---|
5996 |
|
---|
5997 | RTLogRelSetBuffering(fSavedBuffering);
|
---|
5998 |
|
---|
5999 | /* 3d hardware version; latest and greatest */
|
---|
6000 | pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
|
---|
6001 | pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
|
---|
6002 |
|
---|
6003 | /* Fill out 3d capabilities up to SVGA3D_DEVCAP_SURFACEFMT_ATI2 in the FIFO memory.
|
---|
6004 | * SVGA3D_DEVCAP_SURFACEFMT_ATI2 is the last capabiltiy for pre-SVGA_CAP_GBOBJECTS hardware.
|
---|
6005 | * If the VMSVGA device supports SVGA_CAP_GBOBJECTS capability, then the guest has to use SVGA_REG_DEV_CAP
|
---|
6006 | * register to query the devcaps. Older guests will still try to read the devcaps from FIFO.
|
---|
6007 | */
|
---|
6008 | SVGA3dCapsRecord *pCaps;
|
---|
6009 | SVGA3dCapPair *pData;
|
---|
6010 |
|
---|
6011 | pCaps = (SVGA3dCapsRecord *)&pThisCC->svga.pau32FIFO[SVGA_FIFO_3D_CAPS];
|
---|
6012 | pCaps->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
|
---|
6013 | pData = (SVGA3dCapPair *)&pCaps->data;
|
---|
6014 |
|
---|
6015 | AssertCompile(SVGA3D_DEVCAP_DEAD1 == SVGA3D_DEVCAP_SURFACEFMT_ATI2 + 1);
|
---|
6016 | for (unsigned i = 0; i < SVGA3D_DEVCAP_DEAD1; ++i)
|
---|
6017 | {
|
---|
6018 | pData[i][0] = i;
|
---|
6019 | pData[i][1] = pThis->svga.au32DevCaps[i];
|
---|
6020 | }
|
---|
6021 | pCaps->header.length = (sizeof(pCaps->header) + SVGA3D_DEVCAP_DEAD1 * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
|
---|
6022 | pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
|
---|
6023 |
|
---|
6024 | /* Mark end of record array (a zero word). */
|
---|
6025 | pCaps->header.length = 0;
|
---|
6026 | }
|
---|
6027 |
|
---|
6028 | # endif
|
---|
6029 |
|
---|
6030 | /**
|
---|
6031 | * Resets the SVGA hardware state
|
---|
6032 | *
|
---|
6033 | * @returns VBox status code.
|
---|
6034 | * @param pDevIns The device instance.
|
---|
6035 | */
|
---|
6036 | int vmsvgaR3Reset(PPDMDEVINS pDevIns)
|
---|
6037 | {
|
---|
6038 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
6039 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
6040 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
6041 |
|
---|
6042 | /* Reset before init? */
|
---|
6043 | if (!pSVGAState)
|
---|
6044 | return VINF_SUCCESS;
|
---|
6045 |
|
---|
6046 | Log(("vmsvgaR3Reset\n"));
|
---|
6047 |
|
---|
6048 | /* Reset the FIFO processing as well as the 3d state (if we have one). */
|
---|
6049 | pThisCC->svga.pau32FIFO[SVGA_FIFO_NEXT_CMD] = pThisCC->svga.pau32FIFO[SVGA_FIFO_STOP] = 0; /** @todo should probably let the FIFO thread do this ... */
|
---|
6050 | int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_RESET, NULL /*pvParam*/, 10000 /*ms*/);
|
---|
6051 |
|
---|
6052 | /* Reset other stuff. */
|
---|
6053 | pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
|
---|
6054 | RT_ZERO(pThis->svga.au32ScratchRegion);
|
---|
6055 |
|
---|
6056 | ASMAtomicWriteBool(&pThis->svga.fBadGuest, false);
|
---|
6057 |
|
---|
6058 | vmsvgaR3StateTerm(pThis, pThisCC);
|
---|
6059 | vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
|
---|
6060 |
|
---|
6061 | RT_BZERO(pThisCC->svga.pbVgaFrameBufferR3, VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
6062 |
|
---|
6063 | /* Initialize FIFO and register capabilities. */
|
---|
6064 | vmsvgaR3InitCaps(pThis, pThisCC);
|
---|
6065 |
|
---|
6066 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
6067 | if (pThis->svga.f3DEnabled)
|
---|
6068 | vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
|
---|
6069 | # endif
|
---|
6070 |
|
---|
6071 | /* VRAM tracking is enabled by default during bootup. */
|
---|
6072 | pThis->svga.fVRAMTracking = true;
|
---|
6073 | pThis->svga.fEnabled = false;
|
---|
6074 |
|
---|
6075 | /* Invalidate current settings. */
|
---|
6076 | pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
|
---|
6077 | pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
|
---|
6078 | pThis->svga.uBpp = pThis->svga.uHostBpp;
|
---|
6079 | pThis->svga.cbScanline = 0;
|
---|
6080 | pThis->svga.u32PitchLock = 0;
|
---|
6081 |
|
---|
6082 | return rc;
|
---|
6083 | }
|
---|
6084 |
|
---|
6085 | /**
|
---|
6086 | * Cleans up the SVGA hardware state
|
---|
6087 | *
|
---|
6088 | * @returns VBox status code.
|
---|
6089 | * @param pDevIns The device instance.
|
---|
6090 | */
|
---|
6091 | int vmsvgaR3Destruct(PPDMDEVINS pDevIns)
|
---|
6092 | {
|
---|
6093 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
6094 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
6095 |
|
---|
6096 | /*
|
---|
6097 | * Ask the FIFO thread to terminate the 3d state and then terminate it.
|
---|
6098 | */
|
---|
6099 | if (pThisCC->svga.pFIFOIOThread)
|
---|
6100 | {
|
---|
6101 | int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_TERMINATE,
|
---|
6102 | NULL /*pvParam*/, 30000 /*ms*/);
|
---|
6103 | AssertLogRelRC(rc);
|
---|
6104 |
|
---|
6105 | rc = PDMDevHlpThreadDestroy(pDevIns, pThisCC->svga.pFIFOIOThread, NULL);
|
---|
6106 | AssertLogRelRC(rc);
|
---|
6107 | pThisCC->svga.pFIFOIOThread = NULL;
|
---|
6108 | }
|
---|
6109 |
|
---|
6110 | /*
|
---|
6111 | * Destroy the special SVGA state.
|
---|
6112 | */
|
---|
6113 | if (pThisCC->svga.pSvgaR3State)
|
---|
6114 | {
|
---|
6115 | vmsvgaR3StateTerm(pThis, pThisCC);
|
---|
6116 |
|
---|
6117 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
6118 | vmsvga3dR3Free3dInterfaces(pThisCC);
|
---|
6119 | # endif
|
---|
6120 |
|
---|
6121 | RTMemFree(pThisCC->svga.pSvgaR3State);
|
---|
6122 | pThisCC->svga.pSvgaR3State = NULL;
|
---|
6123 | }
|
---|
6124 |
|
---|
6125 | /*
|
---|
6126 | * Free our resources residing in the VGA state.
|
---|
6127 | */
|
---|
6128 | if (pThisCC->svga.pbVgaFrameBufferR3)
|
---|
6129 | {
|
---|
6130 | RTMemFree(pThisCC->svga.pbVgaFrameBufferR3);
|
---|
6131 | pThisCC->svga.pbVgaFrameBufferR3 = NULL;
|
---|
6132 | }
|
---|
6133 | if (pThisCC->svga.hFIFOExtCmdSem != NIL_RTSEMEVENT)
|
---|
6134 | {
|
---|
6135 | RTSemEventDestroy(pThisCC->svga.hFIFOExtCmdSem);
|
---|
6136 | pThisCC->svga.hFIFOExtCmdSem = NIL_RTSEMEVENT;
|
---|
6137 | }
|
---|
6138 | if (pThis->svga.hFIFORequestSem != NIL_SUPSEMEVENT)
|
---|
6139 | {
|
---|
6140 | PDMDevHlpSUPSemEventClose(pDevIns, pThis->svga.hFIFORequestSem);
|
---|
6141 | pThis->svga.hFIFORequestSem = NIL_SUPSEMEVENT;
|
---|
6142 | }
|
---|
6143 |
|
---|
6144 | return VINF_SUCCESS;
|
---|
6145 | }
|
---|
6146 |
|
---|
6147 | static DECLCALLBACK(size_t) vmsvga3dFloatFormat(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
|
---|
6148 | const char *pszType, void const *pvValue,
|
---|
6149 | int cchWidth, int cchPrecision, unsigned fFlags, void *pvUser)
|
---|
6150 | {
|
---|
6151 | RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
|
---|
6152 | double const v = *(double *)&pvValue;
|
---|
6153 | return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, FLOAT_FMT_STR, FLOAT_FMT_ARGS(v));
|
---|
6154 | }
|
---|
6155 |
|
---|
6156 | /**
|
---|
6157 | * Initialize the SVGA hardware state
|
---|
6158 | *
|
---|
6159 | * @returns VBox status code.
|
---|
6160 | * @param pDevIns The device instance.
|
---|
6161 | */
|
---|
6162 | int vmsvgaR3Init(PPDMDEVINS pDevIns)
|
---|
6163 | {
|
---|
6164 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
6165 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
6166 | PVMSVGAR3STATE pSVGAState;
|
---|
6167 | int rc;
|
---|
6168 |
|
---|
6169 | rc = RTStrFormatTypeRegister("float", vmsvga3dFloatFormat, NULL);
|
---|
6170 | AssertMsgReturn(RT_SUCCESS(rc) || rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
|
---|
6171 |
|
---|
6172 | pThis->svga.cScratchRegion = VMSVGA_SCRATCH_SIZE;
|
---|
6173 | memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
|
---|
6174 |
|
---|
6175 | pThis->svga.cGMR = VMSVGA_MAX_GMR_IDS;
|
---|
6176 |
|
---|
6177 | /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
|
---|
6178 | pThisCC->svga.pbVgaFrameBufferR3 = (uint8_t *)RTMemAllocZ(VMSVGA_VGA_FB_BACKUP_SIZE);
|
---|
6179 | AssertReturn(pThisCC->svga.pbVgaFrameBufferR3, VERR_NO_MEMORY);
|
---|
6180 |
|
---|
6181 | /* Create event semaphore. */
|
---|
6182 | rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->svga.hFIFORequestSem);
|
---|
6183 | AssertRCReturn(rc, rc);
|
---|
6184 |
|
---|
6185 | /* Create event semaphore. */
|
---|
6186 | rc = RTSemEventCreate(&pThisCC->svga.hFIFOExtCmdSem);
|
---|
6187 | AssertRCReturn(rc, rc);
|
---|
6188 |
|
---|
6189 | pThisCC->svga.pSvgaR3State = (PVMSVGAR3STATE)RTMemAllocZ(sizeof(VMSVGAR3STATE));
|
---|
6190 | AssertReturn(pThisCC->svga.pSvgaR3State, VERR_NO_MEMORY);
|
---|
6191 |
|
---|
6192 | rc = vmsvgaR3StateInit(pDevIns, pThis, pThisCC->svga.pSvgaR3State);
|
---|
6193 | AssertMsgRCReturn(rc, ("Failed to create pSvgaR3State.\n"), rc);
|
---|
6194 |
|
---|
6195 | pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
6196 |
|
---|
6197 | /* Register the write-protected GBO access handler type. */
|
---|
6198 | rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
|
---|
6199 | vmsvgaR3GboAccessHandler,
|
---|
6200 | NULL, NULL, NULL,
|
---|
6201 | NULL, NULL, NULL,
|
---|
6202 | "VMSVGA GBO", &pSVGAState->hGboAccessHandlerType);
|
---|
6203 | AssertRCReturn(rc, rc);
|
---|
6204 |
|
---|
6205 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
6206 | if (pThis->svga.f3DEnabled)
|
---|
6207 | {
|
---|
6208 | /* Load a 3D backend. */
|
---|
6209 | rc = vmsvgaR3Init3dInterfaces(pDevIns, pThis, pThisCC);
|
---|
6210 | if (RT_FAILURE(rc))
|
---|
6211 | {
|
---|
6212 | LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
|
---|
6213 | pThis->svga.f3DEnabled = false;
|
---|
6214 | }
|
---|
6215 | }
|
---|
6216 | # endif
|
---|
6217 |
|
---|
6218 | /* Initialize FIFO and register capabilities. */
|
---|
6219 | vmsvgaR3InitCaps(pThis, pThisCC);
|
---|
6220 |
|
---|
6221 | /* VRAM tracking is enabled by default during bootup. */
|
---|
6222 | pThis->svga.fVRAMTracking = true;
|
---|
6223 |
|
---|
6224 | /* Set up the host bpp. This value is as a default for the programmable
|
---|
6225 | * bpp value. On old implementations, SVGA_REG_HOST_BITS_PER_PIXEL did not
|
---|
6226 | * exist and SVGA_REG_BITS_PER_PIXEL was read-only, returning what was later
|
---|
6227 | * separated as SVGA_REG_HOST_BITS_PER_PIXEL.
|
---|
6228 | *
|
---|
6229 | * NB: The driver cBits value is currently constant for the lifetime of the
|
---|
6230 | * VM. If that changes, the host bpp logic might need revisiting.
|
---|
6231 | */
|
---|
6232 | pThis->svga.uHostBpp = (pThisCC->pDrv->cBits + 7) & ~7;
|
---|
6233 |
|
---|
6234 | /* Invalidate current settings. */
|
---|
6235 | pThis->svga.uWidth = VMSVGA_VAL_UNINITIALIZED;
|
---|
6236 | pThis->svga.uHeight = VMSVGA_VAL_UNINITIALIZED;
|
---|
6237 | pThis->svga.uBpp = pThis->svga.uHostBpp;
|
---|
6238 | pThis->svga.cbScanline = 0;
|
---|
6239 |
|
---|
6240 | pThis->svga.u32MaxWidth = VBE_DISPI_MAX_XRES;
|
---|
6241 | pThis->svga.u32MaxHeight = VBE_DISPI_MAX_YRES;
|
---|
6242 | while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
|
---|
6243 | {
|
---|
6244 | pThis->svga.u32MaxWidth -= 256;
|
---|
6245 | pThis->svga.u32MaxHeight -= 256;
|
---|
6246 | }
|
---|
6247 | Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
|
---|
6248 |
|
---|
6249 | # ifdef DEBUG_GMR_ACCESS
|
---|
6250 | /* Register the GMR access handler type. */
|
---|
6251 | rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns), PGMPHYSHANDLERKIND_WRITE,
|
---|
6252 | vmsvgaR3GmrAccessHandler,
|
---|
6253 | NULL, NULL, NULL,
|
---|
6254 | NULL, NULL, NULL,
|
---|
6255 | "VMSVGA GMR", &pThis->svga.hGmrAccessHandlerType);
|
---|
6256 | AssertRCReturn(rc, rc);
|
---|
6257 | # endif
|
---|
6258 |
|
---|
6259 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
|
---|
6260 | /* Register the FIFO access handler type. In addition to
|
---|
6261 | debugging FIFO access, this is also used to facilitate
|
---|
6262 | extended fifo thread sleeps. */
|
---|
6263 | rc = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pDevIns),
|
---|
6264 | # ifdef DEBUG_FIFO_ACCESS
|
---|
6265 | PGMPHYSHANDLERKIND_ALL,
|
---|
6266 | # else
|
---|
6267 | PGMPHYSHANDLERKIND_WRITE,
|
---|
6268 | # endif
|
---|
6269 | vmsvgaR3FifoAccessHandler,
|
---|
6270 | NULL, NULL, NULL,
|
---|
6271 | NULL, NULL, NULL,
|
---|
6272 | "VMSVGA FIFO", &pThis->svga.hFifoAccessHandlerType);
|
---|
6273 | AssertRCReturn(rc, rc);
|
---|
6274 | # endif
|
---|
6275 |
|
---|
6276 | /* Create the async IO thread. */
|
---|
6277 | rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->svga.pFIFOIOThread, pThis, vmsvgaR3FifoLoop, vmsvgaR3FifoLoopWakeUp, 0,
|
---|
6278 | RTTHREADTYPE_IO, "VMSVGA FIFO");
|
---|
6279 | if (RT_FAILURE(rc))
|
---|
6280 | {
|
---|
6281 | AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
|
---|
6282 | return rc;
|
---|
6283 | }
|
---|
6284 |
|
---|
6285 | /*
|
---|
6286 | * Statistics.
|
---|
6287 | */
|
---|
6288 | # define REG_CNT(a_pvSample, a_pszName, a_pszDesc) \
|
---|
6289 | PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_COUNTER, a_pszName, STAMUNIT_OCCURENCES, a_pszDesc)
|
---|
6290 | # define REG_PRF(a_pvSample, a_pszName, a_pszDesc) \
|
---|
6291 | PDMDevHlpSTAMRegister(pDevIns, (a_pvSample), STAMTYPE_PROFILE, a_pszName, STAMUNIT_TICKS_PER_CALL, a_pszDesc)
|
---|
6292 | # ifdef VBOX_WITH_STATISTICS
|
---|
6293 | REG_PRF(&pSVGAState->StatR3Cmd3dDrawPrimitivesProf, "VMSVGA/Cmd/3dDrawPrimitivesProf", "Profiling of SVGA_3D_CMD_DRAW_PRIMITIVES.");
|
---|
6294 | REG_PRF(&pSVGAState->StatR3Cmd3dPresentProf, "VMSVGA/Cmd/3dPresentProfBoth", "Profiling of SVGA_3D_CMD_PRESENT and SVGA_3D_CMD_PRESENT_READBACK.");
|
---|
6295 | REG_PRF(&pSVGAState->StatR3Cmd3dSurfaceDmaProf, "VMSVGA/Cmd/3dSurfaceDmaProf", "Profiling of SVGA_3D_CMD_SURFACE_DMA.");
|
---|
6296 | # endif
|
---|
6297 | REG_PRF(&pSVGAState->StatR3Cmd3dBlitSurfaceToScreenProf, "VMSVGA/Cmd/3dBlitSurfaceToScreenProf", "Profiling of SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN.");
|
---|
6298 | REG_CNT(&pSVGAState->StatR3Cmd3dActivateSurface, "VMSVGA/Cmd/3dActivateSurface", "SVGA_3D_CMD_ACTIVATE_SURFACE");
|
---|
6299 | REG_CNT(&pSVGAState->StatR3Cmd3dBeginQuery, "VMSVGA/Cmd/3dBeginQuery", "SVGA_3D_CMD_BEGIN_QUERY");
|
---|
6300 | REG_CNT(&pSVGAState->StatR3Cmd3dClear, "VMSVGA/Cmd/3dClear", "SVGA_3D_CMD_CLEAR");
|
---|
6301 | REG_CNT(&pSVGAState->StatR3Cmd3dContextDefine, "VMSVGA/Cmd/3dContextDefine", "SVGA_3D_CMD_CONTEXT_DEFINE");
|
---|
6302 | REG_CNT(&pSVGAState->StatR3Cmd3dContextDestroy, "VMSVGA/Cmd/3dContextDestroy", "SVGA_3D_CMD_CONTEXT_DESTROY");
|
---|
6303 | REG_CNT(&pSVGAState->StatR3Cmd3dDeactivateSurface, "VMSVGA/Cmd/3dDeactivateSurface", "SVGA_3D_CMD_DEACTIVATE_SURFACE");
|
---|
6304 | REG_CNT(&pSVGAState->StatR3Cmd3dDrawPrimitives, "VMSVGA/Cmd/3dDrawPrimitives", "SVGA_3D_CMD_DRAW_PRIMITIVES");
|
---|
6305 | REG_CNT(&pSVGAState->StatR3Cmd3dEndQuery, "VMSVGA/Cmd/3dEndQuery", "SVGA_3D_CMD_END_QUERY");
|
---|
6306 | REG_CNT(&pSVGAState->StatR3Cmd3dGenerateMipmaps, "VMSVGA/Cmd/3dGenerateMipmaps", "SVGA_3D_CMD_GENERATE_MIPMAPS");
|
---|
6307 | REG_CNT(&pSVGAState->StatR3Cmd3dPresent, "VMSVGA/Cmd/3dPresent", "SVGA_3D_CMD_PRESENT");
|
---|
6308 | REG_CNT(&pSVGAState->StatR3Cmd3dPresentReadBack, "VMSVGA/Cmd/3dPresentReadBack", "SVGA_3D_CMD_PRESENT_READBACK");
|
---|
6309 | REG_CNT(&pSVGAState->StatR3Cmd3dSetClipPlane, "VMSVGA/Cmd/3dSetClipPlane", "SVGA_3D_CMD_SETCLIPPLANE");
|
---|
6310 | REG_CNT(&pSVGAState->StatR3Cmd3dSetLightData, "VMSVGA/Cmd/3dSetLightData", "SVGA_3D_CMD_SETLIGHTDATA");
|
---|
6311 | REG_CNT(&pSVGAState->StatR3Cmd3dSetLightEnable, "VMSVGA/Cmd/3dSetLightEnable", "SVGA_3D_CMD_SETLIGHTENABLE");
|
---|
6312 | REG_CNT(&pSVGAState->StatR3Cmd3dSetMaterial, "VMSVGA/Cmd/3dSetMaterial", "SVGA_3D_CMD_SETMATERIAL");
|
---|
6313 | REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderState, "VMSVGA/Cmd/3dSetRenderState", "SVGA_3D_CMD_SETRENDERSTATE");
|
---|
6314 | REG_CNT(&pSVGAState->StatR3Cmd3dSetRenderTarget, "VMSVGA/Cmd/3dSetRenderTarget", "SVGA_3D_CMD_SETRENDERTARGET");
|
---|
6315 | REG_CNT(&pSVGAState->StatR3Cmd3dSetScissorRect, "VMSVGA/Cmd/3dSetScissorRect", "SVGA_3D_CMD_SETSCISSORRECT");
|
---|
6316 | REG_CNT(&pSVGAState->StatR3Cmd3dSetShader, "VMSVGA/Cmd/3dSetShader", "SVGA_3D_CMD_SET_SHADER");
|
---|
6317 | REG_CNT(&pSVGAState->StatR3Cmd3dSetShaderConst, "VMSVGA/Cmd/3dSetShaderConst", "SVGA_3D_CMD_SET_SHADER_CONST");
|
---|
6318 | REG_CNT(&pSVGAState->StatR3Cmd3dSetTextureState, "VMSVGA/Cmd/3dSetTextureState", "SVGA_3D_CMD_SETTEXTURESTATE");
|
---|
6319 | REG_CNT(&pSVGAState->StatR3Cmd3dSetTransform, "VMSVGA/Cmd/3dSetTransform", "SVGA_3D_CMD_SETTRANSFORM");
|
---|
6320 | REG_CNT(&pSVGAState->StatR3Cmd3dSetViewPort, "VMSVGA/Cmd/3dSetViewPort", "SVGA_3D_CMD_SETVIEWPORT");
|
---|
6321 | REG_CNT(&pSVGAState->StatR3Cmd3dSetZRange, "VMSVGA/Cmd/3dSetZRange", "SVGA_3D_CMD_SETZRANGE");
|
---|
6322 | REG_CNT(&pSVGAState->StatR3Cmd3dShaderDefine, "VMSVGA/Cmd/3dShaderDefine", "SVGA_3D_CMD_SHADER_DEFINE");
|
---|
6323 | REG_CNT(&pSVGAState->StatR3Cmd3dShaderDestroy, "VMSVGA/Cmd/3dShaderDestroy", "SVGA_3D_CMD_SHADER_DESTROY");
|
---|
6324 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceCopy, "VMSVGA/Cmd/3dSurfaceCopy", "SVGA_3D_CMD_SURFACE_COPY");
|
---|
6325 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefine, "VMSVGA/Cmd/3dSurfaceDefine", "SVGA_3D_CMD_SURFACE_DEFINE");
|
---|
6326 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDefineV2, "VMSVGA/Cmd/3dSurfaceDefineV2", "SVGA_3D_CMD_SURFACE_DEFINE_V2");
|
---|
6327 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDestroy, "VMSVGA/Cmd/3dSurfaceDestroy", "SVGA_3D_CMD_SURFACE_DESTROY");
|
---|
6328 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceDma, "VMSVGA/Cmd/3dSurfaceDma", "SVGA_3D_CMD_SURFACE_DMA");
|
---|
6329 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceScreen, "VMSVGA/Cmd/3dSurfaceScreen", "SVGA_3D_CMD_SURFACE_SCREEN");
|
---|
6330 | REG_CNT(&pSVGAState->StatR3Cmd3dSurfaceStretchBlt, "VMSVGA/Cmd/3dSurfaceStretchBlt", "SVGA_3D_CMD_SURFACE_STRETCHBLT");
|
---|
6331 | REG_CNT(&pSVGAState->StatR3Cmd3dWaitForQuery, "VMSVGA/Cmd/3dWaitForQuery", "SVGA_3D_CMD_WAIT_FOR_QUERY");
|
---|
6332 | REG_CNT(&pSVGAState->StatR3CmdAnnotationCopy, "VMSVGA/Cmd/AnnotationCopy", "SVGA_CMD_ANNOTATION_COPY");
|
---|
6333 | REG_CNT(&pSVGAState->StatR3CmdAnnotationFill, "VMSVGA/Cmd/AnnotationFill", "SVGA_CMD_ANNOTATION_FILL");
|
---|
6334 | REG_CNT(&pSVGAState->StatR3CmdBlitGmrFbToScreen, "VMSVGA/Cmd/BlitGmrFbToScreen", "SVGA_CMD_BLIT_GMRFB_TO_SCREEN");
|
---|
6335 | REG_CNT(&pSVGAState->StatR3CmdBlitScreentoGmrFb, "VMSVGA/Cmd/BlitScreentoGmrFb", "SVGA_CMD_BLIT_SCREEN_TO_GMRFB");
|
---|
6336 | REG_CNT(&pSVGAState->StatR3CmdDefineAlphaCursor, "VMSVGA/Cmd/DefineAlphaCursor", "SVGA_CMD_DEFINE_ALPHA_CURSOR");
|
---|
6337 | REG_CNT(&pSVGAState->StatR3CmdDefineCursor, "VMSVGA/Cmd/DefineCursor", "SVGA_CMD_DEFINE_CURSOR");
|
---|
6338 | REG_CNT(&pSVGAState->StatR3CmdMoveCursor, "VMSVGA/Cmd/MoveCursor", "SVGA_CMD_MOVE_CURSOR");
|
---|
6339 | REG_CNT(&pSVGAState->StatR3CmdDisplayCursor, "VMSVGA/Cmd/DisplayCursor", "SVGA_CMD_DISPLAY_CURSOR");
|
---|
6340 | REG_CNT(&pSVGAState->StatR3CmdRectFill, "VMSVGA/Cmd/RectFill", "SVGA_CMD_RECT_FILL");
|
---|
6341 | REG_CNT(&pSVGAState->StatR3CmdRectCopy, "VMSVGA/Cmd/RectCopy", "SVGA_CMD_RECT_COPY");
|
---|
6342 | REG_CNT(&pSVGAState->StatR3CmdRectRopCopy, "VMSVGA/Cmd/RectRopCopy", "SVGA_CMD_RECT_ROP_COPY");
|
---|
6343 | REG_CNT(&pSVGAState->StatR3CmdDefineGmr2, "VMSVGA/Cmd/DefineGmr2", "SVGA_CMD_DEFINE_GMR2");
|
---|
6344 | REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Free, "VMSVGA/Cmd/DefineGmr2/Free", "Number of SVGA_CMD_DEFINE_GMR2 commands that only frees.");
|
---|
6345 | REG_CNT(&pSVGAState->StatR3CmdDefineGmr2Modify, "VMSVGA/Cmd/DefineGmr2/Modify", "Number of SVGA_CMD_DEFINE_GMR2 commands that redefines a non-free GMR.");
|
---|
6346 | REG_CNT(&pSVGAState->StatR3CmdDefineGmrFb, "VMSVGA/Cmd/DefineGmrFb", "SVGA_CMD_DEFINE_GMRFB");
|
---|
6347 | REG_CNT(&pSVGAState->StatR3CmdDefineScreen, "VMSVGA/Cmd/DefineScreen", "SVGA_CMD_DEFINE_SCREEN");
|
---|
6348 | REG_CNT(&pSVGAState->StatR3CmdDestroyScreen, "VMSVGA/Cmd/DestroyScreen", "SVGA_CMD_DESTROY_SCREEN");
|
---|
6349 | REG_CNT(&pSVGAState->StatR3CmdEscape, "VMSVGA/Cmd/Escape", "SVGA_CMD_ESCAPE");
|
---|
6350 | REG_CNT(&pSVGAState->StatR3CmdFence, "VMSVGA/Cmd/Fence", "SVGA_CMD_FENCE");
|
---|
6351 | REG_CNT(&pSVGAState->StatR3CmdInvalidCmd, "VMSVGA/Cmd/InvalidCmd", "SVGA_CMD_INVALID_CMD");
|
---|
6352 | REG_CNT(&pSVGAState->StatR3CmdRemapGmr2, "VMSVGA/Cmd/RemapGmr2", "SVGA_CMD_REMAP_GMR2");
|
---|
6353 | REG_CNT(&pSVGAState->StatR3CmdRemapGmr2Modify, "VMSVGA/Cmd/RemapGmr2/Modify", "Number of SVGA_CMD_REMAP_GMR2 commands that modifies rather than complete the definition of a GMR.");
|
---|
6354 | REG_CNT(&pSVGAState->StatR3CmdUpdate, "VMSVGA/Cmd/Update", "SVGA_CMD_UPDATE");
|
---|
6355 | REG_CNT(&pSVGAState->StatR3CmdUpdateVerbose, "VMSVGA/Cmd/UpdateVerbose", "SVGA_CMD_UPDATE_VERBOSE");
|
---|
6356 |
|
---|
6357 | REG_CNT(&pSVGAState->StatR3RegConfigDoneWr, "VMSVGA/Reg/ConfigDoneWrite", "SVGA_REG_CONFIG_DONE writes");
|
---|
6358 | REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWr, "VMSVGA/Reg/GmrDescriptorWrite", "SVGA_REG_GMR_DESCRIPTOR writes");
|
---|
6359 | REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrErrors, "VMSVGA/Reg/GmrDescriptorWrite/Errors", "Number of erroneous SVGA_REG_GMR_DESCRIPTOR commands.");
|
---|
6360 | REG_CNT(&pSVGAState->StatR3RegGmrDescriptorWrFree, "VMSVGA/Reg/GmrDescriptorWrite/Free", "Number of SVGA_REG_GMR_DESCRIPTOR commands only freeing the GMR.");
|
---|
6361 | REG_CNT(&pThis->svga.StatRegBitsPerPixelWr, "VMSVGA/Reg/BitsPerPixelWrite", "SVGA_REG_BITS_PER_PIXEL writes.");
|
---|
6362 | REG_CNT(&pThis->svga.StatRegBusyWr, "VMSVGA/Reg/BusyWrite", "SVGA_REG_BUSY writes.");
|
---|
6363 | REG_CNT(&pThis->svga.StatRegCursorXWr, "VMSVGA/Reg/CursorXWrite", "SVGA_REG_CURSOR_X writes.");
|
---|
6364 | REG_CNT(&pThis->svga.StatRegCursorYWr, "VMSVGA/Reg/CursorYWrite", "SVGA_REG_CURSOR_Y writes.");
|
---|
6365 | REG_CNT(&pThis->svga.StatRegCursorIdWr, "VMSVGA/Reg/CursorIdWrite", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) writes.");
|
---|
6366 | REG_CNT(&pThis->svga.StatRegCursorOnWr, "VMSVGA/Reg/CursorOnWrite", "SVGA_REG_CURSOR_ON writes.");
|
---|
6367 | REG_CNT(&pThis->svga.StatRegDepthWr, "VMSVGA/Reg/DepthWrite", "SVGA_REG_DEPTH writes.");
|
---|
6368 | REG_CNT(&pThis->svga.StatRegDisplayHeightWr, "VMSVGA/Reg/DisplayHeightWrite", "SVGA_REG_DISPLAY_HEIGHT writes.");
|
---|
6369 | REG_CNT(&pThis->svga.StatRegDisplayIdWr, "VMSVGA/Reg/DisplayIdWrite", "SVGA_REG_DISPLAY_ID writes.");
|
---|
6370 | REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryWr, "VMSVGA/Reg/DisplayIsPrimaryWrite", "SVGA_REG_DISPLAY_IS_PRIMARY writes.");
|
---|
6371 | REG_CNT(&pThis->svga.StatRegDisplayPositionXWr, "VMSVGA/Reg/DisplayPositionXWrite", "SVGA_REG_DISPLAY_POSITION_X writes.");
|
---|
6372 | REG_CNT(&pThis->svga.StatRegDisplayPositionYWr, "VMSVGA/Reg/DisplayPositionYWrite", "SVGA_REG_DISPLAY_POSITION_Y writes.");
|
---|
6373 | REG_CNT(&pThis->svga.StatRegDisplayWidthWr, "VMSVGA/Reg/DisplayWidthWrite", "SVGA_REG_DISPLAY_WIDTH writes.");
|
---|
6374 | REG_CNT(&pThis->svga.StatRegEnableWr, "VMSVGA/Reg/EnableWrite", "SVGA_REG_ENABLE writes.");
|
---|
6375 | REG_CNT(&pThis->svga.StatRegGmrIdWr, "VMSVGA/Reg/GmrIdWrite", "SVGA_REG_GMR_ID writes.");
|
---|
6376 | REG_CNT(&pThis->svga.StatRegGuestIdWr, "VMSVGA/Reg/GuestIdWrite", "SVGA_REG_GUEST_ID writes.");
|
---|
6377 | REG_CNT(&pThis->svga.StatRegHeightWr, "VMSVGA/Reg/HeightWrite", "SVGA_REG_HEIGHT writes.");
|
---|
6378 | REG_CNT(&pThis->svga.StatRegIdWr, "VMSVGA/Reg/IdWrite", "SVGA_REG_ID writes.");
|
---|
6379 | REG_CNT(&pThis->svga.StatRegIrqMaskWr, "VMSVGA/Reg/IrqMaskWrite", "SVGA_REG_IRQMASK writes.");
|
---|
6380 | REG_CNT(&pThis->svga.StatRegNumDisplaysWr, "VMSVGA/Reg/NumDisplaysWrite", "SVGA_REG_NUM_DISPLAYS writes.");
|
---|
6381 | REG_CNT(&pThis->svga.StatRegNumGuestDisplaysWr, "VMSVGA/Reg/NumGuestDisplaysWrite", "SVGA_REG_NUM_GUEST_DISPLAYS writes.");
|
---|
6382 | REG_CNT(&pThis->svga.StatRegPaletteWr, "VMSVGA/Reg/PaletteWrite", "SVGA_PALETTE_XXXX writes.");
|
---|
6383 | REG_CNT(&pThis->svga.StatRegPitchLockWr, "VMSVGA/Reg/PitchLockWrite", "SVGA_REG_PITCHLOCK writes.");
|
---|
6384 | REG_CNT(&pThis->svga.StatRegPseudoColorWr, "VMSVGA/Reg/PseudoColorWrite", "SVGA_REG_PSEUDOCOLOR writes.");
|
---|
6385 | REG_CNT(&pThis->svga.StatRegReadOnlyWr, "VMSVGA/Reg/ReadOnlyWrite", "Read-only SVGA_REG_XXXX writes.");
|
---|
6386 | REG_CNT(&pThis->svga.StatRegScratchWr, "VMSVGA/Reg/ScratchWrite", "SVGA_REG_SCRATCH_XXXX writes.");
|
---|
6387 | REG_CNT(&pThis->svga.StatRegSyncWr, "VMSVGA/Reg/SyncWrite", "SVGA_REG_SYNC writes.");
|
---|
6388 | REG_CNT(&pThis->svga.StatRegTopWr, "VMSVGA/Reg/TopWrite", "SVGA_REG_TOP writes.");
|
---|
6389 | REG_CNT(&pThis->svga.StatRegTracesWr, "VMSVGA/Reg/TracesWrite", "SVGA_REG_TRACES writes.");
|
---|
6390 | REG_CNT(&pThis->svga.StatRegUnknownWr, "VMSVGA/Reg/UnknownWrite", "Writes to unknown register.");
|
---|
6391 | REG_CNT(&pThis->svga.StatRegWidthWr, "VMSVGA/Reg/WidthWrite", "SVGA_REG_WIDTH writes.");
|
---|
6392 | REG_CNT(&pThis->svga.StatRegCommandLowWr, "VMSVGA/Reg/CommandLowWrite", "SVGA_REG_COMMAND_LOW writes.");
|
---|
6393 | REG_CNT(&pThis->svga.StatRegCommandHighWr, "VMSVGA/Reg/CommandHighWrite", "SVGA_REG_COMMAND_HIGH writes.");
|
---|
6394 | REG_CNT(&pThis->svga.StatRegDevCapWr, "VMSVGA/Reg/DevCapWrite", "SVGA_REG_DEV_CAP writes.");
|
---|
6395 | REG_CNT(&pThis->svga.StatRegCmdPrependLowWr, "VMSVGA/Reg/CmdPrependLowWrite", "SVGA_REG_CMD_PREPEND_LOW writes.");
|
---|
6396 | REG_CNT(&pThis->svga.StatRegCmdPrependHighWr, "VMSVGA/Reg/CmdPrependHighWrite", "SVGA_REG_CMD_PREPEND_HIGH writes.");
|
---|
6397 |
|
---|
6398 | REG_CNT(&pThis->svga.StatRegBitsPerPixelRd, "VMSVGA/Reg/BitsPerPixelRead", "SVGA_REG_BITS_PER_PIXEL reads.");
|
---|
6399 | REG_CNT(&pThis->svga.StatRegBlueMaskRd, "VMSVGA/Reg/BlueMaskRead", "SVGA_REG_BLUE_MASK reads.");
|
---|
6400 | REG_CNT(&pThis->svga.StatRegBusyRd, "VMSVGA/Reg/BusyRead", "SVGA_REG_BUSY reads.");
|
---|
6401 | REG_CNT(&pThis->svga.StatRegBytesPerLineRd, "VMSVGA/Reg/BytesPerLineRead", "SVGA_REG_BYTES_PER_LINE reads.");
|
---|
6402 | REG_CNT(&pThis->svga.StatRegCapabilitesRd, "VMSVGA/Reg/CapabilitesRead", "SVGA_REG_CAPABILITIES reads.");
|
---|
6403 | REG_CNT(&pThis->svga.StatRegConfigDoneRd, "VMSVGA/Reg/ConfigDoneRead", "SVGA_REG_CONFIG_DONE reads.");
|
---|
6404 | REG_CNT(&pThis->svga.StatRegCursorXRd, "VMSVGA/Reg/CursorXRead", "SVGA_REG_CURSOR_X reads.");
|
---|
6405 | REG_CNT(&pThis->svga.StatRegCursorYRd, "VMSVGA/Reg/CursorYRead", "SVGA_REG_CURSOR_Y reads.");
|
---|
6406 | REG_CNT(&pThis->svga.StatRegCursorIdRd, "VMSVGA/Reg/CursorIdRead", "SVGA_REG_DEAD (SVGA_REG_CURSOR_ID) reads.");
|
---|
6407 | REG_CNT(&pThis->svga.StatRegCursorOnRd, "VMSVGA/Reg/CursorOnRead", "SVGA_REG_CURSOR_ON reads.");
|
---|
6408 | REG_CNT(&pThis->svga.StatRegDepthRd, "VMSVGA/Reg/DepthRead", "SVGA_REG_DEPTH reads.");
|
---|
6409 | REG_CNT(&pThis->svga.StatRegDisplayHeightRd, "VMSVGA/Reg/DisplayHeightRead", "SVGA_REG_DISPLAY_HEIGHT reads.");
|
---|
6410 | REG_CNT(&pThis->svga.StatRegDisplayIdRd, "VMSVGA/Reg/DisplayIdRead", "SVGA_REG_DISPLAY_ID reads.");
|
---|
6411 | REG_CNT(&pThis->svga.StatRegDisplayIsPrimaryRd, "VMSVGA/Reg/DisplayIsPrimaryRead", "SVGA_REG_DISPLAY_IS_PRIMARY reads.");
|
---|
6412 | REG_CNT(&pThis->svga.StatRegDisplayPositionXRd, "VMSVGA/Reg/DisplayPositionXRead", "SVGA_REG_DISPLAY_POSITION_X reads.");
|
---|
6413 | REG_CNT(&pThis->svga.StatRegDisplayPositionYRd, "VMSVGA/Reg/DisplayPositionYRead", "SVGA_REG_DISPLAY_POSITION_Y reads.");
|
---|
6414 | REG_CNT(&pThis->svga.StatRegDisplayWidthRd, "VMSVGA/Reg/DisplayWidthRead", "SVGA_REG_DISPLAY_WIDTH reads.");
|
---|
6415 | REG_CNT(&pThis->svga.StatRegEnableRd, "VMSVGA/Reg/EnableRead", "SVGA_REG_ENABLE reads.");
|
---|
6416 | REG_CNT(&pThis->svga.StatRegFbOffsetRd, "VMSVGA/Reg/FbOffsetRead", "SVGA_REG_FB_OFFSET reads.");
|
---|
6417 | REG_CNT(&pThis->svga.StatRegFbSizeRd, "VMSVGA/Reg/FbSizeRead", "SVGA_REG_FB_SIZE reads.");
|
---|
6418 | REG_CNT(&pThis->svga.StatRegFbStartRd, "VMSVGA/Reg/FbStartRead", "SVGA_REG_FB_START reads.");
|
---|
6419 | REG_CNT(&pThis->svga.StatRegGmrIdRd, "VMSVGA/Reg/GmrIdRead", "SVGA_REG_GMR_ID reads.");
|
---|
6420 | REG_CNT(&pThis->svga.StatRegGmrMaxDescriptorLengthRd, "VMSVGA/Reg/GmrMaxDescriptorLengthRead", "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH reads.");
|
---|
6421 | REG_CNT(&pThis->svga.StatRegGmrMaxIdsRd, "VMSVGA/Reg/GmrMaxIdsRead", "SVGA_REG_GMR_MAX_IDS reads.");
|
---|
6422 | REG_CNT(&pThis->svga.StatRegGmrsMaxPagesRd, "VMSVGA/Reg/GmrsMaxPagesRead", "SVGA_REG_GMRS_MAX_PAGES reads.");
|
---|
6423 | REG_CNT(&pThis->svga.StatRegGreenMaskRd, "VMSVGA/Reg/GreenMaskRead", "SVGA_REG_GREEN_MASK reads.");
|
---|
6424 | REG_CNT(&pThis->svga.StatRegGuestIdRd, "VMSVGA/Reg/GuestIdRead", "SVGA_REG_GUEST_ID reads.");
|
---|
6425 | REG_CNT(&pThis->svga.StatRegHeightRd, "VMSVGA/Reg/HeightRead", "SVGA_REG_HEIGHT reads.");
|
---|
6426 | REG_CNT(&pThis->svga.StatRegHostBitsPerPixelRd, "VMSVGA/Reg/HostBitsPerPixelRead", "SVGA_REG_HOST_BITS_PER_PIXEL reads.");
|
---|
6427 | REG_CNT(&pThis->svga.StatRegIdRd, "VMSVGA/Reg/IdRead", "SVGA_REG_ID reads.");
|
---|
6428 | REG_CNT(&pThis->svga.StatRegIrqMaskRd, "VMSVGA/Reg/IrqMaskRead", "SVGA_REG_IRQ_MASK reads.");
|
---|
6429 | REG_CNT(&pThis->svga.StatRegMaxHeightRd, "VMSVGA/Reg/MaxHeightRead", "SVGA_REG_MAX_HEIGHT reads.");
|
---|
6430 | REG_CNT(&pThis->svga.StatRegMaxWidthRd, "VMSVGA/Reg/MaxWidthRead", "SVGA_REG_MAX_WIDTH reads.");
|
---|
6431 | REG_CNT(&pThis->svga.StatRegMemorySizeRd, "VMSVGA/Reg/MemorySizeRead", "SVGA_REG_MEMORY_SIZE reads.");
|
---|
6432 | REG_CNT(&pThis->svga.StatRegMemRegsRd, "VMSVGA/Reg/MemRegsRead", "SVGA_REG_MEM_REGS reads.");
|
---|
6433 | REG_CNT(&pThis->svga.StatRegMemSizeRd, "VMSVGA/Reg/MemSizeRead", "SVGA_REG_MEM_SIZE reads.");
|
---|
6434 | REG_CNT(&pThis->svga.StatRegMemStartRd, "VMSVGA/Reg/MemStartRead", "SVGA_REG_MEM_START reads.");
|
---|
6435 | REG_CNT(&pThis->svga.StatRegNumDisplaysRd, "VMSVGA/Reg/NumDisplaysRead", "SVGA_REG_NUM_DISPLAYS reads.");
|
---|
6436 | REG_CNT(&pThis->svga.StatRegNumGuestDisplaysRd, "VMSVGA/Reg/NumGuestDisplaysRead", "SVGA_REG_NUM_GUEST_DISPLAYS reads.");
|
---|
6437 | REG_CNT(&pThis->svga.StatRegPaletteRd, "VMSVGA/Reg/PaletteRead", "SVGA_REG_PLAETTE_XXXX reads.");
|
---|
6438 | REG_CNT(&pThis->svga.StatRegPitchLockRd, "VMSVGA/Reg/PitchLockRead", "SVGA_REG_PITCHLOCK reads.");
|
---|
6439 | REG_CNT(&pThis->svga.StatRegPsuedoColorRd, "VMSVGA/Reg/PsuedoColorRead", "SVGA_REG_PSEUDOCOLOR reads.");
|
---|
6440 | REG_CNT(&pThis->svga.StatRegRedMaskRd, "VMSVGA/Reg/RedMaskRead", "SVGA_REG_RED_MASK reads.");
|
---|
6441 | REG_CNT(&pThis->svga.StatRegScratchRd, "VMSVGA/Reg/ScratchRead", "SVGA_REG_SCRATCH reads.");
|
---|
6442 | REG_CNT(&pThis->svga.StatRegScratchSizeRd, "VMSVGA/Reg/ScratchSizeRead", "SVGA_REG_SCRATCH_SIZE reads.");
|
---|
6443 | REG_CNT(&pThis->svga.StatRegSyncRd, "VMSVGA/Reg/SyncRead", "SVGA_REG_SYNC reads.");
|
---|
6444 | REG_CNT(&pThis->svga.StatRegTopRd, "VMSVGA/Reg/TopRead", "SVGA_REG_TOP reads.");
|
---|
6445 | REG_CNT(&pThis->svga.StatRegTracesRd, "VMSVGA/Reg/TracesRead", "SVGA_REG_TRACES reads.");
|
---|
6446 | REG_CNT(&pThis->svga.StatRegUnknownRd, "VMSVGA/Reg/UnknownRead", "SVGA_REG_UNKNOWN reads.");
|
---|
6447 | REG_CNT(&pThis->svga.StatRegVramSizeRd, "VMSVGA/Reg/VramSizeRead", "SVGA_REG_VRAM_SIZE reads.");
|
---|
6448 | REG_CNT(&pThis->svga.StatRegWidthRd, "VMSVGA/Reg/WidthRead", "SVGA_REG_WIDTH reads.");
|
---|
6449 | REG_CNT(&pThis->svga.StatRegWriteOnlyRd, "VMSVGA/Reg/WriteOnlyRead", "Write-only SVGA_REG_XXXX reads.");
|
---|
6450 | REG_CNT(&pThis->svga.StatRegCommandLowRd, "VMSVGA/Reg/CommandLowRead", "SVGA_REG_COMMAND_LOW reads.");
|
---|
6451 | REG_CNT(&pThis->svga.StatRegCommandHighRd, "VMSVGA/Reg/CommandHighRead", "SVGA_REG_COMMAND_HIGH reads.");
|
---|
6452 | REG_CNT(&pThis->svga.StatRegMaxPrimBBMemRd, "VMSVGA/Reg/MaxPrimBBMemRead", "SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM reads.");
|
---|
6453 | REG_CNT(&pThis->svga.StatRegGBMemSizeRd, "VMSVGA/Reg/GBMemSizeRead", "SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB reads.");
|
---|
6454 | REG_CNT(&pThis->svga.StatRegDevCapRd, "VMSVGA/Reg/DevCapRead", "SVGA_REG_DEV_CAP reads.");
|
---|
6455 | REG_CNT(&pThis->svga.StatRegCmdPrependLowRd, "VMSVGA/Reg/CmdPrependLowRead", "SVGA_REG_CMD_PREPEND_LOW reads.");
|
---|
6456 | REG_CNT(&pThis->svga.StatRegCmdPrependHighRd, "VMSVGA/Reg/CmdPrependHighRead", "SVGA_REG_CMD_PREPEND_HIGH reads.");
|
---|
6457 | REG_CNT(&pThis->svga.StatRegScrnTgtMaxWidthRd, "VMSVGA/Reg/ScrnTgtMaxWidthRead", "SVGA_REG_SCREENTARGET_MAX_WIDTH reads.");
|
---|
6458 | REG_CNT(&pThis->svga.StatRegScrnTgtMaxHeightRd, "VMSVGA/Reg/ScrnTgtMaxHeightRead", "SVGA_REG_SCREENTARGET_MAX_HEIGHT reads.");
|
---|
6459 | REG_CNT(&pThis->svga.StatRegMobMaxSizeRd, "VMSVGA/Reg/MobMaxSizeRead", "SVGA_REG_MOB_MAX_SIZE reads.");
|
---|
6460 |
|
---|
6461 | REG_PRF(&pSVGAState->StatBusyDelayEmts, "VMSVGA/EmtDelayOnBusyFifo", "Time we've delayed EMTs because of busy FIFO thread.");
|
---|
6462 | REG_CNT(&pSVGAState->StatFifoCommands, "VMSVGA/FifoCommands", "FIFO command counter.");
|
---|
6463 | REG_CNT(&pSVGAState->StatFifoErrors, "VMSVGA/FifoErrors", "FIFO error counter.");
|
---|
6464 | REG_CNT(&pSVGAState->StatFifoUnkCmds, "VMSVGA/FifoUnknownCommands", "FIFO unknown command counter.");
|
---|
6465 | REG_CNT(&pSVGAState->StatFifoTodoTimeout, "VMSVGA/FifoTodoTimeout", "Number of times we discovered pending work after a wait timeout.");
|
---|
6466 | REG_CNT(&pSVGAState->StatFifoTodoWoken, "VMSVGA/FifoTodoWoken", "Number of times we discovered pending work after being woken up.");
|
---|
6467 | REG_PRF(&pSVGAState->StatFifoStalls, "VMSVGA/FifoStalls", "Profiling of FIFO stalls (waiting for guest to finish copying data).");
|
---|
6468 | REG_PRF(&pSVGAState->StatFifoExtendedSleep, "VMSVGA/FifoExtendedSleep", "Profiling FIFO sleeps relying on the refresh timer and/or access handler.");
|
---|
6469 | # if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
|
---|
6470 | REG_CNT(&pSVGAState->StatFifoAccessHandler, "VMSVGA/FifoAccessHandler", "Number of times the FIFO access handler triggered.");
|
---|
6471 | # endif
|
---|
6472 | REG_CNT(&pSVGAState->StatFifoCursorFetchAgain, "VMSVGA/FifoCursorFetchAgain", "Times the cursor update counter changed while reading.");
|
---|
6473 | REG_CNT(&pSVGAState->StatFifoCursorNoChange, "VMSVGA/FifoCursorNoChange", "No cursor position change event though the update counter was modified.");
|
---|
6474 | REG_CNT(&pSVGAState->StatFifoCursorPosition, "VMSVGA/FifoCursorPosition", "Cursor position and visibility changes.");
|
---|
6475 | REG_CNT(&pSVGAState->StatFifoCursorVisiblity, "VMSVGA/FifoCursorVisiblity", "Cursor visibility changes.");
|
---|
6476 | REG_CNT(&pSVGAState->StatFifoWatchdogWakeUps, "VMSVGA/FifoWatchdogWakeUps", "Number of times the FIFO refresh poller/watchdog woke up the FIFO thread.");
|
---|
6477 |
|
---|
6478 | # undef REG_CNT
|
---|
6479 | # undef REG_PRF
|
---|
6480 |
|
---|
6481 | /*
|
---|
6482 | * Info handlers.
|
---|
6483 | */
|
---|
6484 | PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga", "Basic VMSVGA device state details", vmsvgaR3Info);
|
---|
6485 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
6486 | PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dctx", "VMSVGA 3d context details. Accepts 'terse'.", vmsvgaR3Info3dContext);
|
---|
6487 | PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsfc",
|
---|
6488 | "VMSVGA 3d surface details. "
|
---|
6489 | "Accepts 'terse', 'invy', and one of 'tiny', 'medium', 'normal', 'big', 'huge', or 'gigantic'.",
|
---|
6490 | vmsvgaR3Info3dSurface);
|
---|
6491 | PDMDevHlpDBGFInfoRegister(pDevIns, "vmsvga3dsurf",
|
---|
6492 | "VMSVGA 3d surface details and bitmap: "
|
---|
6493 | "sid[>dir]",
|
---|
6494 | vmsvgaR3Info3dSurfaceBmp);
|
---|
6495 | # endif
|
---|
6496 |
|
---|
6497 | return VINF_SUCCESS;
|
---|
6498 | }
|
---|
6499 |
|
---|
6500 | /**
|
---|
6501 | * Power On notification.
|
---|
6502 | *
|
---|
6503 | * @returns VBox status code.
|
---|
6504 | * @param pDevIns The device instance data.
|
---|
6505 | *
|
---|
6506 | * @remarks Caller enters the device critical section.
|
---|
6507 | */
|
---|
6508 | DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
|
---|
6509 | {
|
---|
6510 | # ifdef VBOX_WITH_VMSVGA3D
|
---|
6511 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
6512 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
6513 | if (pThis->svga.f3DEnabled)
|
---|
6514 | {
|
---|
6515 | PVMSVGAR3STATE pSVGAState = pThisCC->svga.pSvgaR3State;
|
---|
6516 | int rc = pSVGAState->pFuncs3D->pfnPowerOn(pDevIns, pThis, pThisCC);
|
---|
6517 | if (RT_SUCCESS(rc))
|
---|
6518 | {
|
---|
6519 | /* Initialize FIFO 3D capabilities. */
|
---|
6520 | vmsvgaR3InitFifo3DCaps(pThis, pThisCC);
|
---|
6521 | }
|
---|
6522 | else {
|
---|
6523 | LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dPowerOn -> %Rrc)\n", rc));
|
---|
6524 | pThis->svga.f3DEnabled = false;
|
---|
6525 | }
|
---|
6526 | }
|
---|
6527 | # else /* !VBOX_WITH_VMSVGA3D */
|
---|
6528 | RT_NOREF(pDevIns);
|
---|
6529 | # endif /* !VBOX_WITH_VMSVGA3D */
|
---|
6530 | }
|
---|
6531 |
|
---|
6532 | /**
|
---|
6533 | * Power Off notification.
|
---|
6534 | *
|
---|
6535 | * @param pDevIns The device instance data.
|
---|
6536 | *
|
---|
6537 | * @remarks Caller enters the device critical section.
|
---|
6538 | */
|
---|
6539 | DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns)
|
---|
6540 | {
|
---|
6541 | PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
|
---|
6542 | PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
|
---|
6543 |
|
---|
6544 | /*
|
---|
6545 | * Notify the FIFO thread.
|
---|
6546 | */
|
---|
6547 | if (pThisCC->svga.pFIFOIOThread)
|
---|
6548 | {
|
---|
6549 | int rc = vmsvgaR3RunExtCmdOnFifoThread(pDevIns, pThis, pThisCC, VMSVGA_FIFO_EXTCMD_POWEROFF,
|
---|
6550 | NULL /*pvParam*/, 30000 /*ms*/);
|
---|
6551 | AssertLogRelRC(rc);
|
---|
6552 | }
|
---|
6553 | }
|
---|
6554 |
|
---|
6555 | #endif /* IN_RING3 */
|
---|