VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h@ 84677

Last change on this file since 84677 was 83278, checked in by vboxsync, 5 years ago

VMSVGA: The SVGA_REG_BITS_PER_PIXEL must be initialized to the host bpp value and can't contain an invalid value, since it used to be read-only. Fixes old X11 drivers.
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File size: 17.9 KB
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1/* $Id: DevVGA-SVGA.h 83278 2020-03-13 11:43:47Z vboxsync $ */
2/** @file
3 * VMware SVGA device
4 */
5/*
6 * Copyright (C) 2013-2020 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 */
16
17#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h
18#define VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h
19#ifndef RT_WITHOUT_PRAGMA_ONCE
20# pragma once
21#endif
22
23#ifndef VBOX_WITH_VMSVGA
24# error "VBOX_WITH_VMSVGA is not defined"
25#endif
26
27#include <VBox/vmm/pdmthread.h>
28
29#include "vmsvga/svga3d_reg.h"
30
31/** Default FIFO size. */
32#define VMSVGA_FIFO_SIZE _2M
33/** The old FIFO size. */
34#define VMSVGA_FIFO_SIZE_OLD _128K
35
36/** Default scratch region size. */
37#define VMSVGA_SCRATCH_SIZE 0x100
38/** Surface memory available to the guest. */
39#define VMSVGA_SURFACE_SIZE (512*1024*1024)
40/** Maximum GMR pages. */
41#define VMSVGA_MAX_GMR_PAGES 0x100000
42/** Maximum nr of GMR ids. */
43#define VMSVGA_MAX_GMR_IDS _8K
44/** Maximum number of GMR descriptors. */
45#define VMSVGA_MAX_GMR_DESC_LOOP_COUNT VMSVGA_MAX_GMR_PAGES
46
47#define VMSVGA_VAL_UNINITIALIZED (unsigned)-1
48
49/** For validating X and width values.
50 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
51#define VMSVGA_MAX_X _1M
52/** For validating Y and height values.
53 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
54#define VMSVGA_MAX_Y _1M
55
56/* u32ActionFlags */
57#define VMSVGA_ACTION_CHANGEMODE_BIT 0
58#define VMSVGA_ACTION_CHANGEMODE RT_BIT(VMSVGA_ACTION_CHANGEMODE_BIT)
59
60
61#ifdef DEBUG
62/* Enable to log FIFO register accesses. */
63//# define DEBUG_FIFO_ACCESS
64/* Enable to log GMR page accesses. */
65//# define DEBUG_GMR_ACCESS
66#endif
67
68#define VMSVGA_FIFO_EXTCMD_NONE 0
69#define VMSVGA_FIFO_EXTCMD_TERMINATE 1
70#define VMSVGA_FIFO_EXTCMD_SAVESTATE 2
71#define VMSVGA_FIFO_EXTCMD_LOADSTATE 3
72#define VMSVGA_FIFO_EXTCMD_RESET 4
73#define VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS 5
74
75/** Size of the region to backup when switching into svga mode. */
76#define VMSVGA_VGA_FB_BACKUP_SIZE _512K
77
78/** @def VMSVGA_WITH_VGA_FB_BACKUP
79 * Enables correct VGA MMIO read/write handling when VMSVGA is enabled. It
80 * is SLOW and probably not entirely right, but it helps with getting 3dmark
81 * output and other stuff. */
82#define VMSVGA_WITH_VGA_FB_BACKUP 1
83
84/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
85 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3) */
86#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
87# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3 1
88#else
89# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
90#endif
91
92/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
93 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3) */
94#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
95# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ 1
96#else
97# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
98#endif
99
100
101typedef struct
102{
103 PSSMHANDLE pSSM;
104 uint32_t uVersion;
105 uint32_t uPass;
106} VMSVGA_STATE_LOAD;
107typedef VMSVGA_STATE_LOAD *PVMSVGA_STATE_LOAD;
108
109/** Host screen viewport.
110 * (4th quadrant with negated Y values - usual Windows and X11 world view.) */
111typedef struct VMSVGAVIEWPORT
112{
113 uint32_t x; /**< x coordinate (left). */
114 uint32_t y; /**< y coordinate (top). */
115 uint32_t cx; /**< width. */
116 uint32_t cy; /**< height. */
117 /** Right side coordinate (exclusive). Same as x + cx. */
118 uint32_t xRight;
119 /** First quadrant low y coordinate.
120 * Same as y + cy - 1 in window coordinates. */
121 uint32_t yLowWC;
122 /** First quadrant high y coordinate (exclusive) - yLowWC + cy.
123 * Same as y - 1 in window coordinates. */
124 uint32_t yHighWC;
125 /** Alignment padding. */
126 uint32_t uAlignment;
127} VMSVGAVIEWPORT;
128
129/**
130 * Screen object state.
131 */
132typedef struct VMSVGASCREENOBJECT
133{
134 /** SVGA_SCREEN_* flags. */
135 uint32_t fuScreen;
136 /** The screen object id. */
137 uint32_t idScreen;
138 /** The screen dimensions. */
139 int32_t xOrigin;
140 int32_t yOrigin;
141 uint32_t cWidth;
142 uint32_t cHeight;
143 /** Offset of the screen buffer in the guest VRAM. */
144 uint32_t offVRAM;
145 /** Scanline pitch. */
146 uint32_t cbPitch;
147 /** Bits per pixel. */
148 uint32_t cBpp;
149 bool fDefined;
150 bool fModified;
151} VMSVGASCREENOBJECT;
152
153/** Pointer to the private VMSVGA ring-3 state structure.
154 * @todo Still not entirely satisfired with the type name, but better than
155 * the previous lower/upper case only distinction. */
156typedef struct VMSVGAR3STATE *PVMSVGAR3STATE;
157/** Pointer to the private (implementation specific) VMSVGA3d state. */
158typedef struct VMSVGA3DSTATE *PVMSVGA3DSTATE;
159
160
161/**
162 * The VMSVGA device state.
163 *
164 * This instantatiated as VGASTATE::svga.
165 */
166typedef struct VMSVGAState
167{
168 /** Guest physical address of the FIFO memory range. */
169 RTGCPHYS GCPhysFIFO;
170 /** Size in bytes of the FIFO memory range.
171 * This may be smaller than cbFIFOConfig after restoring an old VM state. */
172 uint32_t cbFIFO;
173 /** The configured FIFO size. */
174 uint32_t cbFIFOConfig;
175 /** SVGA id. */
176 uint32_t u32SVGAId;
177 /** SVGA extensions enabled or not. */
178 uint32_t fEnabled;
179 /** SVGA memory area configured status. */
180 uint32_t fConfigured;
181 /** Device is busy handling FIFO requests (VMSVGA_BUSY_F_FIFO,
182 * VMSVGA_BUSY_F_EMT_FORCE). */
183 uint32_t volatile fBusy;
184#define VMSVGA_BUSY_F_FIFO RT_BIT_32(0) /**< The normal true/false busy FIFO bit. */
185#define VMSVGA_BUSY_F_EMT_FORCE RT_BIT_32(1) /**< Bit preventing race status flickering when EMT kicks the FIFO thread. */
186 /** Traces (dirty page detection) enabled or not. */
187 uint32_t fTraces;
188 /** Guest OS identifier. */
189 uint32_t u32GuestId;
190 /** Scratch region size (VMSVGAState::au32ScratchRegion). */
191 uint32_t cScratchRegion;
192 /** Irq status. */
193 uint32_t u32IrqStatus;
194 /** Irq mask. */
195 uint32_t u32IrqMask;
196 /** Pitch lock. */
197 uint32_t u32PitchLock;
198 /** Current GMR id. (SVGA_REG_GMR_ID) */
199 uint32_t u32CurrentGMRId;
200 /** Register caps. */
201 uint32_t u32RegCaps;
202 uint32_t Padding0; /* Used to be I/O port base address. */
203 /** Port io index register. */
204 uint32_t u32IndexReg;
205 /** FIFO request semaphore. */
206 SUPSEMEVENT hFIFORequestSem;
207 /** The last seen SVGA_FIFO_CURSOR_COUNT value.
208 * Used by the FIFO thread and its watchdog. */
209 uint32_t uLastCursorUpdateCount;
210 /** Indicates that the FIFO thread is sleeping and might need waking up. */
211 bool volatile fFIFOThreadSleeping;
212 /** The legacy GFB mode registers. If used, they correspond to screen 0. */
213 /** True when the guest modifies the GFB mode registers. */
214 bool fGFBRegisters;
215 bool afPadding[6];
216 uint32_t uWidth;
217 uint32_t uHeight;
218 uint32_t uBpp;
219 uint32_t cbScanline;
220 uint32_t uHostBpp;
221 /** Maximum width supported. */
222 uint32_t u32MaxWidth;
223 /** Maximum height supported. */
224 uint32_t u32MaxHeight;
225 /** Viewport rectangle, i.e. what's currently visible of the target host
226 * window. This is usually (0,0)(uWidth,uHeight), but if the window is
227 * shrunk and scrolling applied, both the origin and size may differ. */
228 VMSVGAVIEWPORT viewport;
229 /** Action flags */
230 uint32_t u32ActionFlags;
231 /** SVGA 3d extensions enabled or not. */
232 bool f3DEnabled;
233 /** VRAM page monitoring enabled or not. */
234 bool fVRAMTracking;
235 /** External command to be executed in the FIFO thread. */
236 uint8_t volatile u8FIFOExtCommand;
237 /** Set by vmsvgaR3RunExtCmdOnFifoThread when it temporarily resumes the FIFO
238 * thread and does not want it do anything but the command. */
239 bool volatile fFifoExtCommandWakeup;
240#ifdef DEBUG_GMR_ACCESS
241 /** GMR debug access handler type handle. */
242 PGMPHYSHANDLERTYPE hGmrAccessHandlerType;
243#endif
244#if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
245 /** FIFO debug access handler type handle. */
246 PGMPHYSHANDLERTYPE hFifoAccessHandlerType;
247#elif defined(DEBUG_GMR_ACCESS)
248 uint32_t uPadding1;
249#endif
250 /** Number of GMRs. */
251 uint32_t cGMR;
252 uint32_t uScreenOffset; /* Used only for loading older saved states. */
253
254 /** Legacy cursor state. */
255 uint32_t uCursorX;
256 uint32_t uCursorY;
257 uint32_t uCursorID;
258 uint32_t uCursorOn;
259
260 /** Scratch array.
261 * Putting this at the end since it's big it probably not . */
262 uint32_t au32ScratchRegion[VMSVGA_SCRATCH_SIZE];
263
264 STAMCOUNTER StatRegBitsPerPixelWr;
265 STAMCOUNTER StatRegBusyWr;
266 STAMCOUNTER StatRegCursorXWr;
267 STAMCOUNTER StatRegCursorYWr;
268 STAMCOUNTER StatRegCursorIdWr;
269 STAMCOUNTER StatRegCursorOnWr;
270 STAMCOUNTER StatRegDepthWr;
271 STAMCOUNTER StatRegDisplayHeightWr;
272 STAMCOUNTER StatRegDisplayIdWr;
273 STAMCOUNTER StatRegDisplayIsPrimaryWr;
274 STAMCOUNTER StatRegDisplayPositionXWr;
275 STAMCOUNTER StatRegDisplayPositionYWr;
276 STAMCOUNTER StatRegDisplayWidthWr;
277 STAMCOUNTER StatRegEnableWr;
278 STAMCOUNTER StatRegGmrIdWr;
279 STAMCOUNTER StatRegGuestIdWr;
280 STAMCOUNTER StatRegHeightWr;
281 STAMCOUNTER StatRegIdWr;
282 STAMCOUNTER StatRegIrqMaskWr;
283 STAMCOUNTER StatRegNumDisplaysWr;
284 STAMCOUNTER StatRegNumGuestDisplaysWr;
285 STAMCOUNTER StatRegPaletteWr;
286 STAMCOUNTER StatRegPitchLockWr;
287 STAMCOUNTER StatRegPseudoColorWr;
288 STAMCOUNTER StatRegReadOnlyWr;
289 STAMCOUNTER StatRegScratchWr;
290 STAMCOUNTER StatRegSyncWr;
291 STAMCOUNTER StatRegTopWr;
292 STAMCOUNTER StatRegTracesWr;
293 STAMCOUNTER StatRegUnknownWr;
294 STAMCOUNTER StatRegWidthWr;
295
296 STAMCOUNTER StatRegBitsPerPixelRd;
297 STAMCOUNTER StatRegBlueMaskRd;
298 STAMCOUNTER StatRegBusyRd;
299 STAMCOUNTER StatRegBytesPerLineRd;
300 STAMCOUNTER StatRegCapabilitesRd;
301 STAMCOUNTER StatRegConfigDoneRd;
302 STAMCOUNTER StatRegCursorXRd;
303 STAMCOUNTER StatRegCursorYRd;
304 STAMCOUNTER StatRegCursorIdRd;
305 STAMCOUNTER StatRegCursorOnRd;
306 STAMCOUNTER StatRegDepthRd;
307 STAMCOUNTER StatRegDisplayHeightRd;
308 STAMCOUNTER StatRegDisplayIdRd;
309 STAMCOUNTER StatRegDisplayIsPrimaryRd;
310 STAMCOUNTER StatRegDisplayPositionXRd;
311 STAMCOUNTER StatRegDisplayPositionYRd;
312 STAMCOUNTER StatRegDisplayWidthRd;
313 STAMCOUNTER StatRegEnableRd;
314 STAMCOUNTER StatRegFbOffsetRd;
315 STAMCOUNTER StatRegFbSizeRd;
316 STAMCOUNTER StatRegFbStartRd;
317 STAMCOUNTER StatRegGmrIdRd;
318 STAMCOUNTER StatRegGmrMaxDescriptorLengthRd;
319 STAMCOUNTER StatRegGmrMaxIdsRd;
320 STAMCOUNTER StatRegGmrsMaxPagesRd;
321 STAMCOUNTER StatRegGreenMaskRd;
322 STAMCOUNTER StatRegGuestIdRd;
323 STAMCOUNTER StatRegHeightRd;
324 STAMCOUNTER StatRegHostBitsPerPixelRd;
325 STAMCOUNTER StatRegIdRd;
326 STAMCOUNTER StatRegIrqMaskRd;
327 STAMCOUNTER StatRegMaxHeightRd;
328 STAMCOUNTER StatRegMaxWidthRd;
329 STAMCOUNTER StatRegMemorySizeRd;
330 STAMCOUNTER StatRegMemRegsRd;
331 STAMCOUNTER StatRegMemSizeRd;
332 STAMCOUNTER StatRegMemStartRd;
333 STAMCOUNTER StatRegNumDisplaysRd;
334 STAMCOUNTER StatRegNumGuestDisplaysRd;
335 STAMCOUNTER StatRegPaletteRd;
336 STAMCOUNTER StatRegPitchLockRd;
337 STAMCOUNTER StatRegPsuedoColorRd;
338 STAMCOUNTER StatRegRedMaskRd;
339 STAMCOUNTER StatRegScratchRd;
340 STAMCOUNTER StatRegScratchSizeRd;
341 STAMCOUNTER StatRegSyncRd;
342 STAMCOUNTER StatRegTopRd;
343 STAMCOUNTER StatRegTracesRd;
344 STAMCOUNTER StatRegUnknownRd;
345 STAMCOUNTER StatRegVramSizeRd;
346 STAMCOUNTER StatRegWidthRd;
347 STAMCOUNTER StatRegWriteOnlyRd;
348} VMSVGAState, VMSVGASTATE;
349
350
351/**
352 * The VMSVGA device state for ring-3
353 *
354 * This instantatiated as VGASTATER3::svga.
355 */
356typedef struct VMSVGASTATER3
357{
358 /** The R3 FIFO pointer. */
359 R3PTRTYPE(uint32_t *) pau32FIFO;
360 /** R3 Opaque pointer to svga state. */
361 R3PTRTYPE(PVMSVGAR3STATE) pSvgaR3State;
362 /** R3 Opaque pointer to 3d state. */
363 R3PTRTYPE(PVMSVGA3DSTATE) p3dState;
364 /** The separate VGA frame buffer in svga mode.
365 * Unlike the the boch-based VGA device implementation, VMSVGA seems to have a
366 * separate frame buffer for VGA and allows concurrent use of both. The SVGA
367 * SDK is making use of this to do VGA text output while testing other things in
368 * SVGA mode, displaying the result by switching back to VGA text mode. So,
369 * when entering SVGA mode we copy the first part of the frame buffer here and
370 * direct VGA accesses here instead. It is copied back when leaving SVGA mode. */
371 R3PTRTYPE(uint8_t *) pbVgaFrameBufferR3;
372 /** R3 Opaque pointer to an external fifo cmd parameter. */
373 R3PTRTYPE(void * volatile) pvFIFOExtCmdParam;
374
375 /** FIFO external command semaphore. */
376 R3PTRTYPE(RTSEMEVENT) hFIFOExtCmdSem;
377 /** FIFO IO Thread. */
378 R3PTRTYPE(PPDMTHREAD) pFIFOIOThread;
379} VMSVGASTATER3;
380
381
382/**
383 * The VMSVGA device state for ring-0
384 *
385 * This instantatiated as VGASTATER0::svga.
386 */
387typedef struct VMSVGASTATER0
388{
389 /** The R0 FIFO pointer.
390 * @note This only points to the _first_ _page_ of the FIFO! */
391 R0PTRTYPE(uint32_t *) pau32FIFO;
392} VMSVGASTATER0;
393
394
395typedef struct VGAState *PVGASTATE;
396typedef struct VGASTATER3 *PVGASTATER3;
397typedef struct VGASTATER0 *PVGASTATER0;
398typedef struct VGASTATERC *PVGASTATERC;
399typedef CTX_SUFF(PVGASTATE) PVGASTATECC;
400
401DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
402 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType);
403DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb);
404DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb);
405
406DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId,
407 uint32_t x, uint32_t y, uint32_t cx, uint32_t cy);
408DECLCALLBACK(void) vmsvgaR3PortReportMonitorPositions(PPDMIDISPLAYPORT pInterface, uint32_t cPositions, PCRTPOINT paPositions);
409
410int vmsvgaR3Init(PPDMDEVINS pDevIns);
411int vmsvgaR3Reset(PPDMDEVINS pDevIns);
412int vmsvgaR3Destruct(PPDMDEVINS pDevIns);
413int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
414int vmsvgaR3LoadDone(PPDMDEVINS pDevIns);
415int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
416DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns);
417DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns);
418void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
419
420#ifdef IN_RING3
421VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen);
422int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h);
423#endif
424
425int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
426 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
427 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
428 uint32_t cbWidth, uint32_t cHeight);
429
430void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox);
431void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox);
432void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect);
433
434#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h */
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