VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-dx-shader.cpp@ 91605

Last change on this file since 91605 was 91527, checked in by vboxsync, 3 years ago

Devices/Graphics: Build fix: bugref:9830
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 90.5 KB
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1/* $Id: DevVGA-SVGA3d-dx-shader.cpp 91527 2021-10-01 17:19:25Z vboxsync $ */
2/** @file
3 * DevVMWare - VMWare SVGA device - VGPU10+ (DX) shader utilities.
4 */
5
6/*
7 * Copyright (C) 2020-2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
23#include <VBox/AssertGuest.h>
24#include <VBox/log.h>
25
26#include <iprt/asm.h>
27#include <iprt/md5.h>
28#include <iprt/mem.h>
29#include <iprt/string.h>
30
31#include "DevVGA-SVGA3d-dx-shader.h"
32
33
34/*
35 *
36 * DXBC shader binary format definitions.
37 *
38 */
39
40/* DXBC container header. */
41typedef struct DXBCHeader
42{
43 uint32_t u32DXBC; /* 0x43425844 = 'D', 'X', 'B', 'C' */
44 uint8_t au8Hash[16]; /* Modified MD5 hash. See dxbcHash. */
45 uint32_t u32Version; /* 1 */
46 uint32_t cbTotal; /* Total size in bytes. Including the header. */
47 uint32_t cBlob; /* Number of entries in aBlobOffset array. */
48 uint32_t aBlobOffset[1]; /* Offsets of blobs from the start of DXBC header. */
49} DXBCHeader;
50
51#define DXBC_MAGIC RT_MAKE_U32_FROM_U8('D', 'X', 'B', 'C')
52
53/* DXBC blob header. */
54typedef struct DXBCBlobHeader
55{
56 uint32_t u32BlobType; /* FourCC code. DXBC_BLOB_TYPE_* */
57 uint32_t cbBlob; /* Size of the blob excluding the blob header. 4 bytes aligned. */
58 /* Followed by the blob's data. */
59} DXBCBlobHeader;
60
61/* DXBC blob types. */
62#define DXBC_BLOB_TYPE_ISGN RT_MAKE_U32_FROM_U8('I', 'S', 'G', 'N')
63#define DXBC_BLOB_TYPE_OSGN RT_MAKE_U32_FROM_U8('O', 'S', 'G', 'N')
64#define DXBC_BLOB_TYPE_SHDR RT_MAKE_U32_FROM_U8('S', 'H', 'D', 'R')
65/** @todo More... */
66
67/* 'SHDR' blob data format. */
68typedef struct DXBCBlobSHDR
69{
70 VGPU10ProgramToken programToken;
71 uint32_t cToken; /* Number of 32 bit tokens including programToken and cToken. */
72 uint32_t au32Token[1]; /* cToken - 2 number of tokens. */
73} DXBCBlobSHDR;
74
75/* Element of an input or output signature. */
76typedef struct DXBCBlobIOSGNElement
77{
78 uint32_t offElementName; /* Offset of the semantic's name relative to the start of the blob data. */
79 uint32_t idxSemantic; /* Semantic index. */
80 uint32_t enmSystemValue; /* SVGA3dDXSignatureSemanticName */
81 uint32_t enmComponentType; /* 1 - unsigned, 2 - integer, 3 - float. */
82 uint32_t idxRegister; /* Shader register index. Elements must be sorted by register index. */
83 uint32_t mask : 8; /* Component mask. Lower 4 bits represent X, Y, Z, W channels. */
84 uint32_t mask2 : 8; /* Which components are used in the shader. */
85 uint32_t pad : 16;
86} DXBCBlobIOSGNElement;
87
88/* 'ISGN' and 'OSGN' blob data format. */
89typedef struct DXBCBlobIOSGN
90{
91 uint32_t cElement; /* Number of signature elements. */
92 uint32_t offElement; /* Offset of the first element from the start of the blob. Equals to 8. */
93 DXBCBlobIOSGNElement aElement[1]; /* Signature elements. Size is cElement. */
94 /* Followed by ASCIIZ semantic names. */
95} DXBCBlobIOSGN;
96
97
98/*
99 * VGPU10 shader parser definitions.
100 */
101
102/* Parsed info about an operand index. */
103typedef struct VGPUOperandIndex
104{
105 uint32_t indexRepresentation; /* VGPU10_OPERAND_INDEX_REPRESENTATION */
106 uint64_t iOperandImmediate; /* Needs up to a qword. */
107 struct VGPUOperand *pOperandRelative; /* For VGPU10_OPERAND_INDEX_*RELATIVE */
108} VGPUOperandIndex;
109
110/* Parsed info about an operand. */
111typedef struct VGPUOperand
112{
113 uint32_t numComponents : 2; /* VGPU10_OPERAND_NUM_COMPONENTS */
114 uint32_t selectionMode : 2; /* VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE */
115 uint32_t mask : 4; /* 4-bits X, Y, Z, W mask for VGPU10_OPERAND_4_COMPONENT_MASK_MODE. */
116 uint32_t operandType : 8; /* VGPU10_OPERAND_TYPE */
117 uint32_t indexDimension : 2; /* VGPU10_OPERAND_INDEX_DIMENSION */
118 VGPUOperandIndex aOperandIndex[VGPU10_OPERAND_INDEX_3D]; /* Up to 3. */
119 uint32_t aImm[4]; /* Immediate values for VGPU10_OPERAND_TYPE_IMMEDIATE* */
120} VGPUOperand;
121
122/* Parsed info about an opcode. */
123typedef struct VGPUOpcode
124{
125 uint32_t cOpcodeToken; /* Number of tokens for this operation. */
126 uint32_t opcodeType; /* VGPU10_OPCODE_* */
127 uint32_t semanticName; /* SVGA3dDXSignatureSemanticName for system value declarations. */
128 uint32_t cOperand; /* Number of operands for this instruction. */
129 uint32_t aIdxOperand[8]; /* Indices of the instruction operands in the aValOperand array. */
130 /* 8 should be enough for everyone. */
131 VGPUOperand aValOperand[16]; /* Operands including VGPU10_OPERAND_INDEX_*RELATIVE if they are used: */
132 /* Operand1, VGPU10_OPERAND_INDEX_*RELATIVE for Operand1, ... */
133 /* ... */
134 /* OperandN, VGPU10_OPERAND_INDEX_*RELATIVE for OperandN, ... */
135 /* 16 probably should be enough for everyone. */
136} VGPUOpcode;
137
138typedef struct VGPUOpcodeInfo
139{
140 uint32_t cOperand; /* Number of operands for this opcode. */
141} VGPUOpcodeInfo;
142
143static VGPUOpcodeInfo const g_aOpcodeInfo[] =
144{
145 { 3 }, /* VGPU10_OPCODE_ADD */
146 { 3 }, /* VGPU10_OPCODE_AND */
147 { 0 }, /* VGPU10_OPCODE_BREAK */
148 { 1 }, /* VGPU10_OPCODE_BREAKC */
149 { 1 }, /* VGPU10_OPCODE_CALL */
150 { 2 }, /* VGPU10_OPCODE_CALLC */
151 { 1 }, /* VGPU10_OPCODE_CASE */
152 { 0 }, /* VGPU10_OPCODE_CONTINUE */
153 { 1 }, /* VGPU10_OPCODE_CONTINUEC */
154 { 0 }, /* VGPU10_OPCODE_CUT */
155 { 0 }, /* VGPU10_OPCODE_DEFAULT */
156 { 2 }, /* VGPU10_OPCODE_DERIV_RTX */
157 { 2 }, /* VGPU10_OPCODE_DERIV_RTY */
158 { 1 }, /* VGPU10_OPCODE_DISCARD */
159 { 3 }, /* VGPU10_OPCODE_DIV */
160 { 3 }, /* VGPU10_OPCODE_DP2 */
161 { 3 }, /* VGPU10_OPCODE_DP3 */
162 { 3 }, /* VGPU10_OPCODE_DP4 */
163 { 0 }, /* VGPU10_OPCODE_ELSE */
164 { 0 }, /* VGPU10_OPCODE_EMIT */
165 { 0 }, /* VGPU10_OPCODE_EMITTHENCUT */
166 { 0 }, /* VGPU10_OPCODE_ENDIF */
167 { 0 }, /* VGPU10_OPCODE_ENDLOOP */
168 { 0 }, /* VGPU10_OPCODE_ENDSWITCH */
169 { 3 }, /* VGPU10_OPCODE_EQ */
170 { 2 }, /* VGPU10_OPCODE_EXP */
171 { 2 }, /* VGPU10_OPCODE_FRC */
172 { 2 }, /* VGPU10_OPCODE_FTOI */
173 { 2 }, /* VGPU10_OPCODE_FTOU */
174 { 3 }, /* VGPU10_OPCODE_GE */
175 { 3 }, /* VGPU10_OPCODE_IADD */
176 { 1 }, /* VGPU10_OPCODE_IF */
177 { 3 }, /* VGPU10_OPCODE_IEQ */
178 { 3 }, /* VGPU10_OPCODE_IGE */
179 { 3 }, /* VGPU10_OPCODE_ILT */
180 { 4 }, /* VGPU10_OPCODE_IMAD */
181 { 3 }, /* VGPU10_OPCODE_IMAX */
182 { 3 }, /* VGPU10_OPCODE_IMIN */
183 { 4 }, /* VGPU10_OPCODE_IMUL */
184 { 3 }, /* VGPU10_OPCODE_INE */
185 { 2 }, /* VGPU10_OPCODE_INEG */
186 { 3 }, /* VGPU10_OPCODE_ISHL */
187 { 3 }, /* VGPU10_OPCODE_ISHR */
188 { 2 }, /* VGPU10_OPCODE_ITOF */
189 { 1 }, /* VGPU10_OPCODE_LABEL */
190 { 3 }, /* VGPU10_OPCODE_LD */
191 { 4 }, /* VGPU10_OPCODE_LD_MS */
192 { 2 }, /* VGPU10_OPCODE_LOG */
193 { 0 }, /* VGPU10_OPCODE_LOOP */
194 { 3 }, /* VGPU10_OPCODE_LT */
195 { 4 }, /* VGPU10_OPCODE_MAD */
196 { 3 }, /* VGPU10_OPCODE_MIN */
197 { 3 }, /* VGPU10_OPCODE_MAX */
198 { UINT32_MAX }, /* VGPU10_OPCODE_CUSTOMDATA: special opcode */
199 { 2 }, /* VGPU10_OPCODE_MOV */
200 { 4 }, /* VGPU10_OPCODE_MOVC */
201 { 3 }, /* VGPU10_OPCODE_MUL */
202 { 3 }, /* VGPU10_OPCODE_NE */
203 { 0 }, /* VGPU10_OPCODE_NOP */
204 { 2 }, /* VGPU10_OPCODE_NOT */
205 { 3 }, /* VGPU10_OPCODE_OR */
206 { 3 }, /* VGPU10_OPCODE_RESINFO */
207 { 0 }, /* VGPU10_OPCODE_RET */
208 { 1 }, /* VGPU10_OPCODE_RETC */
209 { 2 }, /* VGPU10_OPCODE_ROUND_NE */
210 { 2 }, /* VGPU10_OPCODE_ROUND_NI */
211 { 2 }, /* VGPU10_OPCODE_ROUND_PI */
212 { 2 }, /* VGPU10_OPCODE_ROUND_Z */
213 { 2 }, /* VGPU10_OPCODE_RSQ */
214 { 4 }, /* VGPU10_OPCODE_SAMPLE */
215 { 5 }, /* VGPU10_OPCODE_SAMPLE_C */
216 { 5 }, /* VGPU10_OPCODE_SAMPLE_C_LZ */
217 { 5 }, /* VGPU10_OPCODE_SAMPLE_L */
218 { 6 }, /* VGPU10_OPCODE_SAMPLE_D */
219 { 5 }, /* VGPU10_OPCODE_SAMPLE_B */
220 { 2 }, /* VGPU10_OPCODE_SQRT */
221 { 1 }, /* VGPU10_OPCODE_SWITCH */
222 { 3 }, /* VGPU10_OPCODE_SINCOS */
223 { 4 }, /* VGPU10_OPCODE_UDIV */
224 { 3 }, /* VGPU10_OPCODE_ULT */
225 { 3 }, /* VGPU10_OPCODE_UGE */
226 { 4 }, /* VGPU10_OPCODE_UMUL */
227 { 4 }, /* VGPU10_OPCODE_UMAD */
228 { 3 }, /* VGPU10_OPCODE_UMAX */
229 { 3 }, /* VGPU10_OPCODE_UMIN */
230 { 3 }, /* VGPU10_OPCODE_USHR */
231 { 2 }, /* VGPU10_OPCODE_UTOF */
232 { 3 }, /* VGPU10_OPCODE_XOR */
233 { 1 }, /* VGPU10_OPCODE_DCL_RESOURCE */
234 { 1 }, /* VGPU10_OPCODE_DCL_CONSTANT_BUFFER */
235 { 1 }, /* VGPU10_OPCODE_DCL_SAMPLER */
236 { 1 }, /* VGPU10_OPCODE_DCL_INDEX_RANGE */
237 { 0 }, /* VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY */
238 { 0 }, /* VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE */
239 { 0 }, /* VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT */
240 { 1 }, /* VGPU10_OPCODE_DCL_INPUT */
241 { 1 }, /* VGPU10_OPCODE_DCL_INPUT_SGV */
242 { 1 }, /* VGPU10_OPCODE_DCL_INPUT_SIV */
243 { 1 }, /* VGPU10_OPCODE_DCL_INPUT_PS */
244 { 1 }, /* VGPU10_OPCODE_DCL_INPUT_PS_SGV */
245 { 1 }, /* VGPU10_OPCODE_DCL_INPUT_PS_SIV */
246 { 1 }, /* VGPU10_OPCODE_DCL_OUTPUT */
247 { 1 }, /* VGPU10_OPCODE_DCL_OUTPUT_SGV */
248 { 1 }, /* VGPU10_OPCODE_DCL_OUTPUT_SIV */
249 { 0 }, /* VGPU10_OPCODE_DCL_TEMPS */
250 { 0 }, /* VGPU10_OPCODE_DCL_INDEXABLE_TEMP */
251 { 0 }, /* VGPU10_OPCODE_DCL_GLOBAL_FLAGS */
252 { UINT32_MAX }, /* VGPU10_OPCODE_VMWARE: special opcode */
253 { 4 }, /* VGPU10_OPCODE_LOD */
254 { 4 }, /* VGPU10_OPCODE_GATHER4 */
255 { 3 }, /* VGPU10_OPCODE_SAMPLE_POS */
256 { 2 }, /* VGPU10_OPCODE_SAMPLE_INFO */
257 { UINT32_MAX }, /* VGPU10_OPCODE_RESERVED1: special opcode */
258 { 0 }, /* VGPU10_OPCODE_HS_DECLS */
259 { 0 }, /* VGPU10_OPCODE_HS_CONTROL_POINT_PHASE */
260 { 0 }, /* VGPU10_OPCODE_HS_FORK_PHASE */
261 { 0 }, /* VGPU10_OPCODE_HS_JOIN_PHASE */
262 { 1 }, /* VGPU10_OPCODE_EMIT_STREAM */
263 { 1 }, /* VGPU10_OPCODE_CUT_STREAM */
264 { 1 }, /* VGPU10_OPCODE_EMITTHENCUT_STREAM */
265 { 1 }, /* VGPU10_OPCODE_INTERFACE_CALL */
266 { 2 }, /* VGPU10_OPCODE_BUFINFO */
267 { 2 }, /* VGPU10_OPCODE_DERIV_RTX_COARSE */
268 { 2 }, /* VGPU10_OPCODE_DERIV_RTX_FINE */
269 { 2 }, /* VGPU10_OPCODE_DERIV_RTY_COARSE */
270 { 2 }, /* VGPU10_OPCODE_DERIV_RTY_FINE */
271 { 5 }, /* VGPU10_OPCODE_GATHER4_C */
272 { 5 }, /* VGPU10_OPCODE_GATHER4_PO */
273 { 6 }, /* VGPU10_OPCODE_GATHER4_PO_C */
274 { 2 }, /* VGPU10_OPCODE_RCP */
275 { 2 }, /* VGPU10_OPCODE_F32TOF16 */
276 { 2 }, /* VGPU10_OPCODE_F16TOF32 */
277 { 4 }, /* VGPU10_OPCODE_UADDC */
278 { 4 }, /* VGPU10_OPCODE_USUBB */
279 { 2 }, /* VGPU10_OPCODE_COUNTBITS */
280 { 2 }, /* VGPU10_OPCODE_FIRSTBIT_HI */
281 { 2 }, /* VGPU10_OPCODE_FIRSTBIT_LO */
282 { 2 }, /* VGPU10_OPCODE_FIRSTBIT_SHI */
283 { 4 }, /* VGPU10_OPCODE_UBFE */
284 { 4 }, /* VGPU10_OPCODE_IBFE */
285 { 5 }, /* VGPU10_OPCODE_BFI */
286 { 2 }, /* VGPU10_OPCODE_BFREV */
287 { 5 }, /* VGPU10_OPCODE_SWAPC */
288 { 1 }, /* VGPU10_OPCODE_DCL_STREAM */
289 { 0 }, /* VGPU10_OPCODE_DCL_FUNCTION_BODY */
290 { 0 }, /* VGPU10_OPCODE_DCL_FUNCTION_TABLE */
291 { 0 }, /* VGPU10_OPCODE_DCL_INTERFACE */
292 { 0 }, /* VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT */
293 { 0 }, /* VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT */
294 { 0 }, /* VGPU10_OPCODE_DCL_TESS_DOMAIN */
295 { 0 }, /* VGPU10_OPCODE_DCL_TESS_PARTITIONING */
296 { 0 }, /* VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE */
297 { 0 }, /* VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR */
298 { 0 }, /* VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT */
299 { 0 }, /* VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT */
300 { 0 }, /* VGPU10_OPCODE_DCL_THREAD_GROUP */
301 { 1 }, /* VGPU10_OPCODE_DCL_UAV_TYPED */
302 { 1 }, /* VGPU10_OPCODE_DCL_UAV_RAW */
303 { 1 }, /* VGPU10_OPCODE_DCL_UAV_STRUCTURED */
304 { 1 }, /* VGPU10_OPCODE_DCL_TGSM_RAW */
305 { 1 }, /* VGPU10_OPCODE_DCL_TGSM_STRUCTURED */
306 { 1 }, /* VGPU10_OPCODE_DCL_RESOURCE_RAW */
307 { 1 }, /* VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED */
308 { 3 }, /* VGPU10_OPCODE_LD_UAV_TYPED */
309 { 3 }, /* VGPU10_OPCODE_STORE_UAV_TYPED */
310 { 3 }, /* VGPU10_OPCODE_LD_RAW */
311 { 3 }, /* VGPU10_OPCODE_STORE_RAW */
312 { 4 }, /* VGPU10_OPCODE_LD_STRUCTURED */
313 { 4 }, /* VGPU10_OPCODE_STORE_STRUCTURED */
314 { 3 }, /* VGPU10_OPCODE_ATOMIC_AND */
315 { 3 }, /* VGPU10_OPCODE_ATOMIC_OR */
316 { 3 }, /* VGPU10_OPCODE_ATOMIC_XOR */
317 { 4 }, /* VGPU10_OPCODE_ATOMIC_CMP_STORE */
318 { 3 }, /* VGPU10_OPCODE_ATOMIC_IADD */
319 { 3 }, /* VGPU10_OPCODE_ATOMIC_IMAX */
320 { 3 }, /* VGPU10_OPCODE_ATOMIC_IMIN */
321 { 3 }, /* VGPU10_OPCODE_ATOMIC_UMAX */
322 { 3 }, /* VGPU10_OPCODE_ATOMIC_UMIN */
323 { 2 }, /* VGPU10_OPCODE_IMM_ATOMIC_ALLOC */
324 { 2 }, /* VGPU10_OPCODE_IMM_ATOMIC_CONSUME */
325 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_IADD */
326 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_AND */
327 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_OR */
328 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_XOR */
329 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_EXCH */
330 { 5 }, /* VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH */
331 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_IMAX */
332 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_IMIN */
333 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_UMAX */
334 { 4 }, /* VGPU10_OPCODE_IMM_ATOMIC_UMIN */
335 { 0 }, /* VGPU10_OPCODE_SYNC */
336 { 3 }, /* VGPU10_OPCODE_DADD */
337 { 3 }, /* VGPU10_OPCODE_DMAX */
338 { 3 }, /* VGPU10_OPCODE_DMIN */
339 { 3 }, /* VGPU10_OPCODE_DMUL */
340 { 3 }, /* VGPU10_OPCODE_DEQ */
341 { 3 }, /* VGPU10_OPCODE_DGE */
342 { 3 }, /* VGPU10_OPCODE_DLT */
343 { 3 }, /* VGPU10_OPCODE_DNE */
344 { 2 }, /* VGPU10_OPCODE_DMOV */
345 { 4 }, /* VGPU10_OPCODE_DMOVC */
346 { 2 }, /* VGPU10_OPCODE_DTOF */
347 { 2 }, /* VGPU10_OPCODE_FTOD */
348 { 3 }, /* VGPU10_OPCODE_EVAL_SNAPPED */
349 { 3 }, /* VGPU10_OPCODE_EVAL_SAMPLE_INDEX */
350 { 2 }, /* VGPU10_OPCODE_EVAL_CENTROID */
351 { 0 }, /* VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT */
352 { 0 }, /* VGPU10_OPCODE_ABORT */
353 { 0 }, /* VGPU10_OPCODE_DEBUG_BREAK */
354 { 0 }, /* VGPU10_OPCODE_RESERVED0 */
355 { 3 }, /* VGPU10_OPCODE_DDIV */
356 { 4 }, /* VGPU10_OPCODE_DFMA */
357 { 2 }, /* VGPU10_OPCODE_DRCP */
358 { 4 }, /* VGPU10_OPCODE_MSAD */
359 { 2 }, /* VGPU10_OPCODE_DTOI */
360 { 2 }, /* VGPU10_OPCODE_DTOU */
361 { 2 }, /* VGPU10_OPCODE_ITOD */
362 { 2 }, /* VGPU10_OPCODE_UTOD */
363};
364AssertCompile(RT_ELEMENTS(g_aOpcodeInfo) == VGPU10_NUM_OPCODES);
365
366#ifdef LOG_ENABLED
367/*
368 *
369 * Helpers to translate a VGPU10 shader constant to a string.
370 *
371 */
372
373#define SVGA_CASE_ID2STR(idx) case idx: return #idx
374
375static const char *dxbcOpcodeToString(uint32_t opcodeType)
376{
377 VGPU10_OPCODE_TYPE enm = (VGPU10_OPCODE_TYPE)opcodeType;
378 switch (enm)
379 {
380 SVGA_CASE_ID2STR(VGPU10_OPCODE_ADD);
381 SVGA_CASE_ID2STR(VGPU10_OPCODE_AND);
382 SVGA_CASE_ID2STR(VGPU10_OPCODE_BREAK);
383 SVGA_CASE_ID2STR(VGPU10_OPCODE_BREAKC);
384 SVGA_CASE_ID2STR(VGPU10_OPCODE_CALL);
385 SVGA_CASE_ID2STR(VGPU10_OPCODE_CALLC);
386 SVGA_CASE_ID2STR(VGPU10_OPCODE_CASE);
387 SVGA_CASE_ID2STR(VGPU10_OPCODE_CONTINUE);
388 SVGA_CASE_ID2STR(VGPU10_OPCODE_CONTINUEC);
389 SVGA_CASE_ID2STR(VGPU10_OPCODE_CUT);
390 SVGA_CASE_ID2STR(VGPU10_OPCODE_DEFAULT);
391 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTX);
392 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTY);
393 SVGA_CASE_ID2STR(VGPU10_OPCODE_DISCARD);
394 SVGA_CASE_ID2STR(VGPU10_OPCODE_DIV);
395 SVGA_CASE_ID2STR(VGPU10_OPCODE_DP2);
396 SVGA_CASE_ID2STR(VGPU10_OPCODE_DP3);
397 SVGA_CASE_ID2STR(VGPU10_OPCODE_DP4);
398 SVGA_CASE_ID2STR(VGPU10_OPCODE_ELSE);
399 SVGA_CASE_ID2STR(VGPU10_OPCODE_EMIT);
400 SVGA_CASE_ID2STR(VGPU10_OPCODE_EMITTHENCUT);
401 SVGA_CASE_ID2STR(VGPU10_OPCODE_ENDIF);
402 SVGA_CASE_ID2STR(VGPU10_OPCODE_ENDLOOP);
403 SVGA_CASE_ID2STR(VGPU10_OPCODE_ENDSWITCH);
404 SVGA_CASE_ID2STR(VGPU10_OPCODE_EQ);
405 SVGA_CASE_ID2STR(VGPU10_OPCODE_EXP);
406 SVGA_CASE_ID2STR(VGPU10_OPCODE_FRC);
407 SVGA_CASE_ID2STR(VGPU10_OPCODE_FTOI);
408 SVGA_CASE_ID2STR(VGPU10_OPCODE_FTOU);
409 SVGA_CASE_ID2STR(VGPU10_OPCODE_GE);
410 SVGA_CASE_ID2STR(VGPU10_OPCODE_IADD);
411 SVGA_CASE_ID2STR(VGPU10_OPCODE_IF);
412 SVGA_CASE_ID2STR(VGPU10_OPCODE_IEQ);
413 SVGA_CASE_ID2STR(VGPU10_OPCODE_IGE);
414 SVGA_CASE_ID2STR(VGPU10_OPCODE_ILT);
415 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMAD);
416 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMAX);
417 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMIN);
418 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMUL);
419 SVGA_CASE_ID2STR(VGPU10_OPCODE_INE);
420 SVGA_CASE_ID2STR(VGPU10_OPCODE_INEG);
421 SVGA_CASE_ID2STR(VGPU10_OPCODE_ISHL);
422 SVGA_CASE_ID2STR(VGPU10_OPCODE_ISHR);
423 SVGA_CASE_ID2STR(VGPU10_OPCODE_ITOF);
424 SVGA_CASE_ID2STR(VGPU10_OPCODE_LABEL);
425 SVGA_CASE_ID2STR(VGPU10_OPCODE_LD);
426 SVGA_CASE_ID2STR(VGPU10_OPCODE_LD_MS);
427 SVGA_CASE_ID2STR(VGPU10_OPCODE_LOG);
428 SVGA_CASE_ID2STR(VGPU10_OPCODE_LOOP);
429 SVGA_CASE_ID2STR(VGPU10_OPCODE_LT);
430 SVGA_CASE_ID2STR(VGPU10_OPCODE_MAD);
431 SVGA_CASE_ID2STR(VGPU10_OPCODE_MIN);
432 SVGA_CASE_ID2STR(VGPU10_OPCODE_MAX);
433 SVGA_CASE_ID2STR(VGPU10_OPCODE_CUSTOMDATA);
434 SVGA_CASE_ID2STR(VGPU10_OPCODE_MOV);
435 SVGA_CASE_ID2STR(VGPU10_OPCODE_MOVC);
436 SVGA_CASE_ID2STR(VGPU10_OPCODE_MUL);
437 SVGA_CASE_ID2STR(VGPU10_OPCODE_NE);
438 SVGA_CASE_ID2STR(VGPU10_OPCODE_NOP);
439 SVGA_CASE_ID2STR(VGPU10_OPCODE_NOT);
440 SVGA_CASE_ID2STR(VGPU10_OPCODE_OR);
441 SVGA_CASE_ID2STR(VGPU10_OPCODE_RESINFO);
442 SVGA_CASE_ID2STR(VGPU10_OPCODE_RET);
443 SVGA_CASE_ID2STR(VGPU10_OPCODE_RETC);
444 SVGA_CASE_ID2STR(VGPU10_OPCODE_ROUND_NE);
445 SVGA_CASE_ID2STR(VGPU10_OPCODE_ROUND_NI);
446 SVGA_CASE_ID2STR(VGPU10_OPCODE_ROUND_PI);
447 SVGA_CASE_ID2STR(VGPU10_OPCODE_ROUND_Z);
448 SVGA_CASE_ID2STR(VGPU10_OPCODE_RSQ);
449 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE);
450 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_C);
451 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_C_LZ);
452 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_L);
453 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_D);
454 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_B);
455 SVGA_CASE_ID2STR(VGPU10_OPCODE_SQRT);
456 SVGA_CASE_ID2STR(VGPU10_OPCODE_SWITCH);
457 SVGA_CASE_ID2STR(VGPU10_OPCODE_SINCOS);
458 SVGA_CASE_ID2STR(VGPU10_OPCODE_UDIV);
459 SVGA_CASE_ID2STR(VGPU10_OPCODE_ULT);
460 SVGA_CASE_ID2STR(VGPU10_OPCODE_UGE);
461 SVGA_CASE_ID2STR(VGPU10_OPCODE_UMUL);
462 SVGA_CASE_ID2STR(VGPU10_OPCODE_UMAD);
463 SVGA_CASE_ID2STR(VGPU10_OPCODE_UMAX);
464 SVGA_CASE_ID2STR(VGPU10_OPCODE_UMIN);
465 SVGA_CASE_ID2STR(VGPU10_OPCODE_USHR);
466 SVGA_CASE_ID2STR(VGPU10_OPCODE_UTOF);
467 SVGA_CASE_ID2STR(VGPU10_OPCODE_XOR);
468 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_RESOURCE);
469 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_CONSTANT_BUFFER);
470 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_SAMPLER);
471 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INDEX_RANGE);
472 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY);
473 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE);
474 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT);
475 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT);
476 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_SGV);
477 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_SIV);
478 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_PS);
479 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_PS_SGV);
480 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_PS_SIV);
481 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_OUTPUT);
482 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_OUTPUT_SGV);
483 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_OUTPUT_SIV);
484 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TEMPS);
485 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INDEXABLE_TEMP);
486 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_GLOBAL_FLAGS);
487 SVGA_CASE_ID2STR(VGPU10_OPCODE_VMWARE);
488 SVGA_CASE_ID2STR(VGPU10_OPCODE_LOD);
489 SVGA_CASE_ID2STR(VGPU10_OPCODE_GATHER4);
490 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_POS);
491 SVGA_CASE_ID2STR(VGPU10_OPCODE_SAMPLE_INFO);
492 SVGA_CASE_ID2STR(VGPU10_OPCODE_RESERVED1);
493 SVGA_CASE_ID2STR(VGPU10_OPCODE_HS_DECLS);
494 SVGA_CASE_ID2STR(VGPU10_OPCODE_HS_CONTROL_POINT_PHASE);
495 SVGA_CASE_ID2STR(VGPU10_OPCODE_HS_FORK_PHASE);
496 SVGA_CASE_ID2STR(VGPU10_OPCODE_HS_JOIN_PHASE);
497 SVGA_CASE_ID2STR(VGPU10_OPCODE_EMIT_STREAM);
498 SVGA_CASE_ID2STR(VGPU10_OPCODE_CUT_STREAM);
499 SVGA_CASE_ID2STR(VGPU10_OPCODE_EMITTHENCUT_STREAM);
500 SVGA_CASE_ID2STR(VGPU10_OPCODE_INTERFACE_CALL);
501 SVGA_CASE_ID2STR(VGPU10_OPCODE_BUFINFO);
502 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTX_COARSE);
503 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTX_FINE);
504 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTY_COARSE);
505 SVGA_CASE_ID2STR(VGPU10_OPCODE_DERIV_RTY_FINE);
506 SVGA_CASE_ID2STR(VGPU10_OPCODE_GATHER4_C);
507 SVGA_CASE_ID2STR(VGPU10_OPCODE_GATHER4_PO);
508 SVGA_CASE_ID2STR(VGPU10_OPCODE_GATHER4_PO_C);
509 SVGA_CASE_ID2STR(VGPU10_OPCODE_RCP);
510 SVGA_CASE_ID2STR(VGPU10_OPCODE_F32TOF16);
511 SVGA_CASE_ID2STR(VGPU10_OPCODE_F16TOF32);
512 SVGA_CASE_ID2STR(VGPU10_OPCODE_UADDC);
513 SVGA_CASE_ID2STR(VGPU10_OPCODE_USUBB);
514 SVGA_CASE_ID2STR(VGPU10_OPCODE_COUNTBITS);
515 SVGA_CASE_ID2STR(VGPU10_OPCODE_FIRSTBIT_HI);
516 SVGA_CASE_ID2STR(VGPU10_OPCODE_FIRSTBIT_LO);
517 SVGA_CASE_ID2STR(VGPU10_OPCODE_FIRSTBIT_SHI);
518 SVGA_CASE_ID2STR(VGPU10_OPCODE_UBFE);
519 SVGA_CASE_ID2STR(VGPU10_OPCODE_IBFE);
520 SVGA_CASE_ID2STR(VGPU10_OPCODE_BFI);
521 SVGA_CASE_ID2STR(VGPU10_OPCODE_BFREV);
522 SVGA_CASE_ID2STR(VGPU10_OPCODE_SWAPC);
523 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_STREAM);
524 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_FUNCTION_BODY);
525 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_FUNCTION_TABLE);
526 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INTERFACE);
527 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_INPUT_CONTROL_POINT_COUNT);
528 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_OUTPUT_CONTROL_POINT_COUNT);
529 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TESS_DOMAIN);
530 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TESS_PARTITIONING);
531 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TESS_OUTPUT_PRIMITIVE);
532 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR);
533 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT);
534 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT);
535 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_THREAD_GROUP);
536 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_UAV_TYPED);
537 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_UAV_RAW);
538 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_UAV_STRUCTURED);
539 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TGSM_RAW);
540 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_TGSM_STRUCTURED);
541 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_RESOURCE_RAW);
542 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED);
543 SVGA_CASE_ID2STR(VGPU10_OPCODE_LD_UAV_TYPED);
544 SVGA_CASE_ID2STR(VGPU10_OPCODE_STORE_UAV_TYPED);
545 SVGA_CASE_ID2STR(VGPU10_OPCODE_LD_RAW);
546 SVGA_CASE_ID2STR(VGPU10_OPCODE_STORE_RAW);
547 SVGA_CASE_ID2STR(VGPU10_OPCODE_LD_STRUCTURED);
548 SVGA_CASE_ID2STR(VGPU10_OPCODE_STORE_STRUCTURED);
549 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_AND);
550 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_OR);
551 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_XOR);
552 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_CMP_STORE);
553 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_IADD);
554 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_IMAX);
555 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_IMIN);
556 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_UMAX);
557 SVGA_CASE_ID2STR(VGPU10_OPCODE_ATOMIC_UMIN);
558 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_ALLOC);
559 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_CONSUME);
560 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_IADD);
561 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_AND);
562 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_OR);
563 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_XOR);
564 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_EXCH);
565 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_CMP_EXCH);
566 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_IMAX);
567 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_IMIN);
568 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_UMAX);
569 SVGA_CASE_ID2STR(VGPU10_OPCODE_IMM_ATOMIC_UMIN);
570 SVGA_CASE_ID2STR(VGPU10_OPCODE_SYNC);
571 SVGA_CASE_ID2STR(VGPU10_OPCODE_DADD);
572 SVGA_CASE_ID2STR(VGPU10_OPCODE_DMAX);
573 SVGA_CASE_ID2STR(VGPU10_OPCODE_DMIN);
574 SVGA_CASE_ID2STR(VGPU10_OPCODE_DMUL);
575 SVGA_CASE_ID2STR(VGPU10_OPCODE_DEQ);
576 SVGA_CASE_ID2STR(VGPU10_OPCODE_DGE);
577 SVGA_CASE_ID2STR(VGPU10_OPCODE_DLT);
578 SVGA_CASE_ID2STR(VGPU10_OPCODE_DNE);
579 SVGA_CASE_ID2STR(VGPU10_OPCODE_DMOV);
580 SVGA_CASE_ID2STR(VGPU10_OPCODE_DMOVC);
581 SVGA_CASE_ID2STR(VGPU10_OPCODE_DTOF);
582 SVGA_CASE_ID2STR(VGPU10_OPCODE_FTOD);
583 SVGA_CASE_ID2STR(VGPU10_OPCODE_EVAL_SNAPPED);
584 SVGA_CASE_ID2STR(VGPU10_OPCODE_EVAL_SAMPLE_INDEX);
585 SVGA_CASE_ID2STR(VGPU10_OPCODE_EVAL_CENTROID);
586 SVGA_CASE_ID2STR(VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT);
587 SVGA_CASE_ID2STR(VGPU10_OPCODE_ABORT);
588 SVGA_CASE_ID2STR(VGPU10_OPCODE_DEBUG_BREAK);
589 SVGA_CASE_ID2STR(VGPU10_OPCODE_RESERVED0);
590 SVGA_CASE_ID2STR(VGPU10_OPCODE_DDIV);
591 SVGA_CASE_ID2STR(VGPU10_OPCODE_DFMA);
592 SVGA_CASE_ID2STR(VGPU10_OPCODE_DRCP);
593 SVGA_CASE_ID2STR(VGPU10_OPCODE_MSAD);
594 SVGA_CASE_ID2STR(VGPU10_OPCODE_DTOI);
595 SVGA_CASE_ID2STR(VGPU10_OPCODE_DTOU);
596 SVGA_CASE_ID2STR(VGPU10_OPCODE_ITOD);
597 SVGA_CASE_ID2STR(VGPU10_OPCODE_UTOD);
598 SVGA_CASE_ID2STR(VGPU10_NUM_OPCODES);
599 }
600 return NULL;
601}
602
603
604static const char *dxbcShaderTypeToString(uint32_t value)
605{
606 VGPU10_PROGRAM_TYPE enm = (VGPU10_PROGRAM_TYPE)value;
607 switch (enm)
608 {
609 SVGA_CASE_ID2STR(VGPU10_PIXEL_SHADER);
610 SVGA_CASE_ID2STR(VGPU10_VERTEX_SHADER);
611 SVGA_CASE_ID2STR(VGPU10_GEOMETRY_SHADER);
612 SVGA_CASE_ID2STR(VGPU10_HULL_SHADER);
613 SVGA_CASE_ID2STR(VGPU10_DOMAIN_SHADER);
614 SVGA_CASE_ID2STR(VGPU10_COMPUTE_SHADER);
615 }
616 return NULL;
617}
618
619
620static const char *dxbcCustomDataClassToString(uint32_t value)
621{
622 VGPU10_CUSTOMDATA_CLASS enm = (VGPU10_CUSTOMDATA_CLASS)value;
623 switch (enm)
624 {
625 SVGA_CASE_ID2STR(VGPU10_CUSTOMDATA_COMMENT);
626 SVGA_CASE_ID2STR(VGPU10_CUSTOMDATA_DEBUGINFO);
627 SVGA_CASE_ID2STR(VGPU10_CUSTOMDATA_OPAQUE);
628 SVGA_CASE_ID2STR(VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER);
629 }
630 return NULL;
631}
632
633
634static const char *dxbcSystemNameToString(uint32_t value)
635{
636 VGPU10_SYSTEM_NAME enm = (VGPU10_SYSTEM_NAME)value;
637 switch (enm)
638 {
639 SVGA_CASE_ID2STR(VGPU10_NAME_UNDEFINED);
640 SVGA_CASE_ID2STR(VGPU10_NAME_POSITION);
641 SVGA_CASE_ID2STR(VGPU10_NAME_CLIP_DISTANCE);
642 SVGA_CASE_ID2STR(VGPU10_NAME_CULL_DISTANCE);
643 SVGA_CASE_ID2STR(VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX);
644 SVGA_CASE_ID2STR(VGPU10_NAME_VIEWPORT_ARRAY_INDEX);
645 SVGA_CASE_ID2STR(VGPU10_NAME_VERTEX_ID);
646 SVGA_CASE_ID2STR(VGPU10_NAME_PRIMITIVE_ID);
647 SVGA_CASE_ID2STR(VGPU10_NAME_INSTANCE_ID);
648 SVGA_CASE_ID2STR(VGPU10_NAME_IS_FRONT_FACE);
649 SVGA_CASE_ID2STR(VGPU10_NAME_SAMPLE_INDEX);
650 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR);
651 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR);
652 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR);
653 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR);
654 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR);
655 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR);
656 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR);
657 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR);
658 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR);
659 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_TRI_INSIDE_TESSFACTOR);
660 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_LINE_DETAIL_TESSFACTOR);
661 SVGA_CASE_ID2STR(VGPU10_NAME_FINAL_LINE_DENSITY_TESSFACTOR);
662 }
663 return NULL;
664}
665
666
667static const char *dxbcOperandTypeToString(uint32_t value)
668{
669 VGPU10_OPERAND_TYPE enm = (VGPU10_OPERAND_TYPE)value;
670 switch (enm)
671 {
672 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_TEMP);
673 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT);
674 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT);
675 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INDEXABLE_TEMP);
676 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_IMMEDIATE32);
677 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_IMMEDIATE64);
678 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_SAMPLER);
679 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_RESOURCE);
680 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_CONSTANT_BUFFER);
681 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER);
682 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_LABEL);
683 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID);
684 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_DEPTH);
685 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_NULL);
686 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_RASTERIZER);
687 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK);
688 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_STREAM);
689 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_FUNCTION_BODY);
690 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_FUNCTION_TABLE);
691 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INTERFACE);
692 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_FUNCTION_INPUT);
693 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_FUNCTION_OUTPUT);
694 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT_ID);
695 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_FORK_INSTANCE_ID);
696 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_JOIN_INSTANCE_ID);
697 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_CONTROL_POINT);
698 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_CONTROL_POINT);
699 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_PATCH_CONSTANT);
700 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_DOMAIN_POINT);
701 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_THIS_POINTER);
702 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_UAV);
703 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_THREAD_GROUP_SHARED_MEMORY);
704 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_THREAD_ID);
705 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_THREAD_GROUP_ID);
706 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP);
707 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_COVERAGE_MASK);
708 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_THREAD_ID_IN_GROUP_FLATTENED);
709 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_INPUT_GS_INSTANCE_ID);
710 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_GREATER_EQUAL);
711 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_OUTPUT_DEPTH_LESS_EQUAL);
712 SVGA_CASE_ID2STR(VGPU10_OPERAND_TYPE_CYCLE_COUNTER);
713 SVGA_CASE_ID2STR(VGPU10_NUM_OPERANDS);
714 }
715 return NULL;
716}
717
718
719static const char *dxbcOperandNumComponentsToString(uint32_t value)
720{
721 VGPU10_OPERAND_NUM_COMPONENTS enm = (VGPU10_OPERAND_NUM_COMPONENTS)value;
722 switch (enm)
723 {
724 SVGA_CASE_ID2STR(VGPU10_OPERAND_0_COMPONENT);
725 SVGA_CASE_ID2STR(VGPU10_OPERAND_1_COMPONENT);
726 SVGA_CASE_ID2STR(VGPU10_OPERAND_4_COMPONENT);
727 SVGA_CASE_ID2STR(VGPU10_OPERAND_N_COMPONENT);
728 }
729 return NULL;
730}
731
732
733static const char *dxbcOperandComponentModeToString(uint32_t value)
734{
735 VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE enm = (VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE)value;
736 switch (enm)
737 {
738 SVGA_CASE_ID2STR(VGPU10_OPERAND_4_COMPONENT_MASK_MODE);
739 SVGA_CASE_ID2STR(VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE);
740 SVGA_CASE_ID2STR(VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE);
741 }
742 return NULL;
743}
744
745
746static const char *dxbcOperandComponentNameToString(uint32_t value)
747{
748 VGPU10_COMPONENT_NAME enm = (VGPU10_COMPONENT_NAME)value;
749 switch (enm)
750 {
751 SVGA_CASE_ID2STR(VGPU10_COMPONENT_X);
752 SVGA_CASE_ID2STR(VGPU10_COMPONENT_Y);
753 SVGA_CASE_ID2STR(VGPU10_COMPONENT_Z);
754 SVGA_CASE_ID2STR(VGPU10_COMPONENT_W);
755 }
756 return NULL;
757}
758
759
760static const char *dxbcOperandIndexDimensionToString(uint32_t value)
761{
762 VGPU10_OPERAND_INDEX_DIMENSION enm = (VGPU10_OPERAND_INDEX_DIMENSION)value;
763 switch (enm)
764 {
765 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_0D);
766 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_1D);
767 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_2D);
768 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_3D);
769 }
770 return NULL;
771}
772
773
774static const char *dxbcOperandIndexRepresentationToString(uint32_t value)
775{
776 VGPU10_OPERAND_INDEX_REPRESENTATION enm = (VGPU10_OPERAND_INDEX_REPRESENTATION)value;
777 switch (enm)
778 {
779 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_IMMEDIATE32);
780 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_IMMEDIATE64);
781 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_RELATIVE);
782 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE);
783 SVGA_CASE_ID2STR(VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE);
784 }
785 return NULL;
786}
787
788
789static const char *dxbcInterpolationModeToString(uint32_t value)
790{
791 VGPU10_INTERPOLATION_MODE enm = (VGPU10_INTERPOLATION_MODE)value;
792 switch (enm)
793 {
794 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_UNDEFINED);
795 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_CONSTANT);
796 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR);
797 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR_CENTROID);
798 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE);
799 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID);
800 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR_SAMPLE);
801 SVGA_CASE_ID2STR(VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE);
802 }
803 return NULL;
804}
805#endif /* LOG_ENABLED */
806
807/*
808 * MD5 from IPRT (alt-md5.cpp) for DXBC hash calculation.
809 * DXBC hash function uses a different padding for the data, see dxbcHash.
810 * Therefore RTMd5Final is not needed. Two functions have been renamed: dxbcRTMd5Update dxbcRTMd5Init.
811 */
812
813
814/* The four core functions - F1 is optimized somewhat */
815/* #define F1(x, y, z) (x & y | ~x & z) */
816#define F1(x, y, z) (z ^ (x & (y ^ z)))
817#define F2(x, y, z) F1(z, x, y)
818#define F3(x, y, z) (x ^ y ^ z)
819#define F4(x, y, z) (y ^ (x | ~z))
820
821
822/* This is the central step in the MD5 algorithm. */
823#define MD5STEP(f, w, x, y, z, data, s) \
824 ( w += f(x, y, z) + data, w = w<<s | w>>(32-s), w += x )
825
826
827/**
828 * The core of the MD5 algorithm, this alters an existing MD5 hash to reflect
829 * the addition of 16 longwords of new data. RTMd5Update blocks the data and
830 * converts bytes into longwords for this routine.
831 */
832static void rtMd5Transform(uint32_t buf[4], uint32_t const in[16])
833{
834 uint32_t a, b, c, d;
835
836 a = buf[0];
837 b = buf[1];
838 c = buf[2];
839 d = buf[3];
840
841 /* fn, w, x, y, z, data, s) */
842 MD5STEP(F1, a, b, c, d, in[ 0] + 0xd76aa478, 7);
843 MD5STEP(F1, d, a, b, c, in[ 1] + 0xe8c7b756, 12);
844 MD5STEP(F1, c, d, a, b, in[ 2] + 0x242070db, 17);
845 MD5STEP(F1, b, c, d, a, in[ 3] + 0xc1bdceee, 22);
846 MD5STEP(F1, a, b, c, d, in[ 4] + 0xf57c0faf, 7);
847 MD5STEP(F1, d, a, b, c, in[ 5] + 0x4787c62a, 12);
848 MD5STEP(F1, c, d, a, b, in[ 6] + 0xa8304613, 17);
849 MD5STEP(F1, b, c, d, a, in[ 7] + 0xfd469501, 22);
850 MD5STEP(F1, a, b, c, d, in[ 8] + 0x698098d8, 7);
851 MD5STEP(F1, d, a, b, c, in[ 9] + 0x8b44f7af, 12);
852 MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17);
853 MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22);
854 MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7);
855 MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12);
856 MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17);
857 MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22);
858
859 MD5STEP(F2, a, b, c, d, in[ 1] + 0xf61e2562, 5);
860 MD5STEP(F2, d, a, b, c, in[ 6] + 0xc040b340, 9);
861 MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14);
862 MD5STEP(F2, b, c, d, a, in[ 0] + 0xe9b6c7aa, 20);
863 MD5STEP(F2, a, b, c, d, in[ 5] + 0xd62f105d, 5);
864 MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9);
865 MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14);
866 MD5STEP(F2, b, c, d, a, in[ 4] + 0xe7d3fbc8, 20);
867 MD5STEP(F2, a, b, c, d, in[ 9] + 0x21e1cde6, 5);
868 MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9);
869 MD5STEP(F2, c, d, a, b, in[ 3] + 0xf4d50d87, 14);
870 MD5STEP(F2, b, c, d, a, in[ 8] + 0x455a14ed, 20);
871 MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5);
872 MD5STEP(F2, d, a, b, c, in[ 2] + 0xfcefa3f8, 9);
873 MD5STEP(F2, c, d, a, b, in[ 7] + 0x676f02d9, 14);
874 MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20);
875
876 MD5STEP(F3, a, b, c, d, in[ 5] + 0xfffa3942, 4);
877 MD5STEP(F3, d, a, b, c, in[ 8] + 0x8771f681, 11);
878 MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);
879 MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);
880 MD5STEP(F3, a, b, c, d, in[ 1] + 0xa4beea44, 4);
881 MD5STEP(F3, d, a, b, c, in[ 4] + 0x4bdecfa9, 11);
882 MD5STEP(F3, c, d, a, b, in[ 7] + 0xf6bb4b60, 16);
883 MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);
884 MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);
885 MD5STEP(F3, d, a, b, c, in[ 0] + 0xeaa127fa, 11);
886 MD5STEP(F3, c, d, a, b, in[ 3] + 0xd4ef3085, 16);
887 MD5STEP(F3, b, c, d, a, in[ 6] + 0x04881d05, 23);
888 MD5STEP(F3, a, b, c, d, in[ 9] + 0xd9d4d039, 4);
889 MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);
890 MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);
891 MD5STEP(F3, b, c, d, a, in[ 2] + 0xc4ac5665, 23);
892
893 MD5STEP(F4, a, b, c, d, in[ 0] + 0xf4292244, 6);
894 MD5STEP(F4, d, a, b, c, in[ 7] + 0x432aff97, 10);
895 MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);
896 MD5STEP(F4, b, c, d, a, in[ 5] + 0xfc93a039, 21);
897 MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);
898 MD5STEP(F4, d, a, b, c, in[ 3] + 0x8f0ccc92, 10);
899 MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);
900 MD5STEP(F4, b, c, d, a, in[ 1] + 0x85845dd1, 21);
901 MD5STEP(F4, a, b, c, d, in[ 8] + 0x6fa87e4f, 6);
902 MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);
903 MD5STEP(F4, c, d, a, b, in[ 6] + 0xa3014314, 15);
904 MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);
905 MD5STEP(F4, a, b, c, d, in[ 4] + 0xf7537e82, 6);
906 MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);
907 MD5STEP(F4, c, d, a, b, in[ 2] + 0x2ad7d2bb, 15);
908 MD5STEP(F4, b, c, d, a, in[ 9] + 0xeb86d391, 21);
909
910 buf[0] += a;
911 buf[1] += b;
912 buf[2] += c;
913 buf[3] += d;
914}
915
916
917#ifdef RT_BIG_ENDIAN
918/*
919 * Note: this code is harmless on little-endian machines.
920 */
921static void rtMd5ByteReverse(uint32_t *buf, unsigned int longs)
922{
923 uint32_t t;
924 do
925 {
926 t = *buf;
927 t = RT_LE2H_U32(t);
928 *buf = t;
929 buf++;
930 } while (--longs);
931}
932#else /* little endian - do nothing */
933# define rtMd5ByteReverse(buf, len) do { /* Nothing */ } while (0)
934#endif
935
936
937/*
938 * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious
939 * initialization constants.
940 */
941static void dxbcRTMd5Init(PRTMD5CONTEXT pCtx)
942{
943 pCtx->AltPrivate.buf[0] = 0x67452301;
944 pCtx->AltPrivate.buf[1] = 0xefcdab89;
945 pCtx->AltPrivate.buf[2] = 0x98badcfe;
946 pCtx->AltPrivate.buf[3] = 0x10325476;
947
948 pCtx->AltPrivate.bits[0] = 0;
949 pCtx->AltPrivate.bits[1] = 0;
950}
951
952
953/*
954 * Update context to reflect the concatenation of another buffer full
955 * of bytes.
956 */
957/** @todo Optimize this, because len is always a multiple of 64. */
958static void dxbcRTMd5Update(PRTMD5CONTEXT pCtx, const void *pvBuf, size_t len)
959{
960 const uint8_t *buf = (const uint8_t *)pvBuf;
961 uint32_t t;
962
963 /* Update bitcount */
964 t = pCtx->AltPrivate.bits[0];
965 if ((pCtx->AltPrivate.bits[0] = t + ((uint32_t) len << 3)) < t)
966 pCtx->AltPrivate.bits[1]++; /* Carry from low to high */
967 pCtx->AltPrivate.bits[1] += (uint32_t)(len >> 29);
968
969 t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */
970
971 /* Handle any leading odd-sized chunks */
972 if (t)
973 {
974 uint8_t *p = (uint8_t *) pCtx->AltPrivate.in + t;
975
976 t = 64 - t;
977 if (len < t)
978 {
979 memcpy(p, buf, len);
980 return;
981 }
982 memcpy(p, buf, t);
983 rtMd5ByteReverse(pCtx->AltPrivate.in, 16);
984 rtMd5Transform(pCtx->AltPrivate.buf, pCtx->AltPrivate.in);
985 buf += t;
986 len -= t;
987 }
988
989 /* Process data in 64-byte chunks */
990#ifndef RT_BIG_ENDIAN
991 if (!((uintptr_t)buf & 0x3))
992 {
993 while (len >= 64) {
994 rtMd5Transform(pCtx->AltPrivate.buf, (uint32_t const *)buf);
995 buf += 64;
996 len -= 64;
997 }
998 }
999 else
1000#endif
1001 {
1002 while (len >= 64) {
1003 memcpy(pCtx->AltPrivate.in, buf, 64);
1004 rtMd5ByteReverse(pCtx->AltPrivate.in, 16);
1005 rtMd5Transform(pCtx->AltPrivate.buf, pCtx->AltPrivate.in);
1006 buf += 64;
1007 len -= 64;
1008 }
1009 }
1010
1011 /* Handle any remaining bytes of data */
1012 memcpy(pCtx->AltPrivate.in, buf, len);
1013}
1014
1015
1016static void dxbcHash(void const *pvData, uint32_t cbData, uint8_t pabDigest[RTMD5HASHSIZE])
1017{
1018 size_t const kBlockSize = 64;
1019 uint8_t au8BlockBuffer[kBlockSize];
1020
1021 static uint8_t const s_au8Padding[kBlockSize] =
1022 {
1023 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1024 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1025 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1026 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1027 };
1028
1029 RTMD5CONTEXT Ctx;
1030 PRTMD5CONTEXT const pCtx = &Ctx;
1031 dxbcRTMd5Init(pCtx);
1032
1033 uint8_t const *pu8Data = (uint8_t *)pvData;
1034 size_t cbRemaining = cbData;
1035
1036 size_t const cbCompleteBlocks = cbData & ~ (kBlockSize - 1);
1037 dxbcRTMd5Update(pCtx, pu8Data, cbCompleteBlocks);
1038 pu8Data += cbCompleteBlocks;
1039 cbRemaining -= cbCompleteBlocks;
1040
1041 /* Custom padding. */
1042 if (cbRemaining >= kBlockSize - 2 * sizeof(uint32_t))
1043 {
1044 /* Two additional blocks. */
1045 memcpy(&au8BlockBuffer[0], pu8Data, cbRemaining);
1046 memcpy(&au8BlockBuffer[cbRemaining], s_au8Padding, kBlockSize - cbRemaining);
1047 dxbcRTMd5Update(pCtx, au8BlockBuffer, kBlockSize);
1048
1049 memset(&au8BlockBuffer[sizeof(uint32_t)], 0, kBlockSize - 2 * sizeof(uint32_t));
1050 }
1051 else
1052 {
1053 /* One additional block. */
1054 memcpy(&au8BlockBuffer[sizeof(uint32_t)], pu8Data, cbRemaining);
1055 memcpy(&au8BlockBuffer[sizeof(uint32_t) + cbRemaining], s_au8Padding, kBlockSize - cbRemaining - 2 * sizeof(uint32_t));
1056 }
1057
1058 /* Set the first and last dwords of the last block. */
1059 *(uint32_t *)&au8BlockBuffer[0] = cbData << 3;
1060 *(uint32_t *)&au8BlockBuffer[kBlockSize - sizeof(uint32_t)] = (cbData << 1) | 1;
1061 dxbcRTMd5Update(pCtx, au8BlockBuffer, kBlockSize);
1062
1063 AssertCompile(sizeof(pCtx->AltPrivate.buf) == RTMD5HASHSIZE);
1064 memcpy(pabDigest, pCtx->AltPrivate.buf, RTMD5HASHSIZE);
1065}
1066
1067
1068/*
1069 *
1070 * Shader token reader.
1071 *
1072 */
1073
1074typedef struct DXBCTokenReader
1075{
1076 uint32_t const *pToken; /* Next token to read. */
1077 uint32_t cToken; /* How many tokens total. */
1078 uint32_t cRemainingToken; /* How many tokens remain. */
1079} DXBCTokenReader;
1080
1081
1082#ifdef LOG_ENABLED
1083DECLINLINE(uint32_t) dxbcTokenReaderByteOffset(DXBCTokenReader *r)
1084{
1085 return (r->cToken - r->cRemainingToken) * 4;
1086}
1087#endif
1088
1089
1090#if 0 // Unused for now
1091DECLINLINE(uint32_t) dxbcTokenReaderRemaining(DXBCTokenReader *r)
1092{
1093 return r->cRemainingToken;
1094}
1095#endif
1096
1097
1098DECLINLINE(bool) dxbcTokenReaderCanRead(DXBCTokenReader *r, uint32_t cToken)
1099{
1100 return cToken <= r->cRemainingToken;
1101}
1102
1103
1104DECLINLINE(void) dxbcTokenReaderSkip(DXBCTokenReader *r, uint32_t cToken)
1105{
1106 AssertReturnVoid(r->cRemainingToken >= cToken);
1107 r->cRemainingToken -= cToken;
1108 r->pToken += cToken;
1109}
1110
1111
1112DECLINLINE(uint32_t) dxbcTokenReaderRead32(DXBCTokenReader *r)
1113{
1114 AssertReturn(r->cRemainingToken, 0);
1115 --r->cRemainingToken;
1116 return *(r->pToken++);
1117}
1118
1119
1120DECLINLINE(uint64_t) dxbcTokenReaderRead64(DXBCTokenReader *r)
1121{
1122 uint64_t const u64Low = dxbcTokenReaderRead32(r);
1123 uint64_t const u64High = dxbcTokenReaderRead32(r);
1124 return u64Low + (u64High << 32);
1125}
1126
1127
1128/*
1129 *
1130 * Byte writer.
1131 *
1132 */
1133
1134typedef struct DXBCByteWriter
1135{
1136 uint8_t *pu8ByteCodeBegin; /* First byte of the buffer. */
1137 uint8_t *pu8ByteCodePtr; /* Next free byte. */
1138 uint32_t cbAllocated; /* How many bytes allocated in the buffer. */
1139 uint32_t cbRemaining; /* How many bytes remain in the buffer. */
1140} DXBCByteWriter;
1141
1142
1143DECLINLINE(void *) dxbcByteWriterPtr(DXBCByteWriter *w)
1144{
1145 return w->pu8ByteCodePtr;
1146}
1147
1148
1149DECLINLINE(uint32_t) dxbcByteWriterSize(DXBCByteWriter *w)
1150{
1151 return (uint32_t)(w->pu8ByteCodePtr - w->pu8ByteCodeBegin);
1152}
1153
1154
1155DECLINLINE(void) dxbcByteWriterCommit(DXBCByteWriter *w, uint32_t cbCommit)
1156{
1157 Assert(cbCommit < w->cbRemaining);
1158 cbCommit = RT_MIN(cbCommit, w->cbRemaining);
1159 w->pu8ByteCodePtr += cbCommit;
1160 w->cbRemaining -= cbCommit;
1161}
1162
1163
1164DECLINLINE(bool) dxbcByteWriterCanWrite(DXBCByteWriter *w, uint32_t cbMore)
1165{
1166 if (cbMore <= w->cbRemaining)
1167 return true;
1168
1169 /* Do not allow to allocate more than 2 * SVGA3D_MAX_SHADER_MEMORY_BYTES */
1170 uint32_t const cbMax = 2 * SVGA3D_MAX_SHADER_MEMORY_BYTES;
1171 AssertReturn(cbMore < cbMax && RT_ALIGN_32(cbMore, 4096) <= cbMax - w->cbAllocated, false);
1172
1173 uint32_t cbNew = w->cbAllocated + RT_ALIGN_32(cbMore, 4096);
1174 void *pvNew = RTMemAllocZ(cbNew);
1175 if (!pvNew)
1176 return false;
1177
1178 uint32_t const cbCurrent = dxbcByteWriterSize(w);
1179 memcpy(pvNew, w->pu8ByteCodeBegin, cbCurrent);
1180 RTMemFree(w->pu8ByteCodeBegin);
1181
1182 w->pu8ByteCodeBegin = (uint8_t *)pvNew;
1183 w->pu8ByteCodePtr = w->pu8ByteCodeBegin + cbCurrent;
1184 w->cbAllocated = cbNew;
1185 w->cbRemaining = cbNew - cbCurrent;
1186
1187 return true;
1188}
1189
1190
1191DECLINLINE(bool) dxbcByteWriterInit(DXBCByteWriter *w, uint32_t cbInitial)
1192{
1193 RT_ZERO(*w);
1194 return dxbcByteWriterCanWrite(w, cbInitial);
1195}
1196
1197
1198DECLINLINE(void) dxbcByteWriterReset(DXBCByteWriter *w)
1199{
1200 RTMemFree(w->pu8ByteCodeBegin);
1201 RT_ZERO(*w);
1202}
1203
1204
1205DECLINLINE(void) dxbcByteWriterFetchData(DXBCByteWriter *w, void **ppv, uint32_t *pcb)
1206{
1207 *ppv = w->pu8ByteCodeBegin;
1208 *pcb = dxbcByteWriterSize(w);
1209
1210 w->pu8ByteCodeBegin = NULL;
1211 dxbcByteWriterReset(w);
1212}
1213
1214
1215/*
1216 *
1217 * VGPU10 shader parser.
1218 *
1219 */
1220
1221/* Parse an instruction operand. */
1222static int dxbcParseOperand(DXBCTokenReader *r, VGPUOperand *paOperand, uint32_t *pcOperandRemain)
1223{
1224 ASSERT_GUEST_RETURN(*pcOperandRemain > 0, VERR_NOT_SUPPORTED);
1225
1226 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1227
1228 VGPU10OperandToken0 operand0;
1229 operand0.value = dxbcTokenReaderRead32(r);
1230
1231 Log6((" %s(%d) %s(%d) %s(%d) %s(%d)\n",
1232 dxbcOperandNumComponentsToString(operand0.numComponents), operand0.numComponents,
1233 dxbcOperandComponentModeToString(operand0.selectionMode), operand0.selectionMode,
1234 dxbcOperandTypeToString(operand0.operandType), operand0.operandType,
1235 dxbcOperandIndexDimensionToString(operand0.indexDimension), operand0.indexDimension));
1236
1237 ASSERT_GUEST_RETURN(operand0.numComponents <= VGPU10_OPERAND_4_COMPONENT, VERR_INVALID_PARAMETER);
1238 if ( operand0.operandType != VGPU10_OPERAND_TYPE_IMMEDIATE32
1239 && operand0.operandType != VGPU10_OPERAND_TYPE_IMMEDIATE64)
1240 {
1241 if (operand0.numComponents == VGPU10_OPERAND_4_COMPONENT)
1242 {
1243 ASSERT_GUEST_RETURN(operand0.selectionMode <= VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE, VERR_INVALID_PARAMETER);
1244 switch (operand0.selectionMode)
1245 {
1246 case VGPU10_OPERAND_4_COMPONENT_MASK_MODE:
1247 Log6((" Mask %#x\n", operand0.mask));
1248 break;
1249 case VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE:
1250 Log6((" Swizzle %s(%d) %s(%d) %s(%d) %s(%d)\n",
1251 dxbcOperandComponentNameToString(operand0.swizzleX), operand0.swizzleX,
1252 dxbcOperandComponentNameToString(operand0.swizzleY), operand0.swizzleY,
1253 dxbcOperandComponentNameToString(operand0.swizzleZ), operand0.swizzleZ,
1254 dxbcOperandComponentNameToString(operand0.swizzleW), operand0.swizzleW));
1255 break;
1256 case VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE:
1257 Log6((" Select %s(%d)\n",
1258 dxbcOperandComponentNameToString(operand0.selectMask), operand0.selectMask));
1259 break;
1260 default: /* Never happens. */
1261 break;
1262 }
1263 }
1264 }
1265
1266 if (operand0.extended)
1267 {
1268 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1269
1270 VGPU10OperandToken1 operand1;
1271 operand1.value = dxbcTokenReaderRead32(r);
1272 }
1273
1274 ASSERT_GUEST_RETURN(operand0.operandType < VGPU10_NUM_OPERANDS, VERR_INVALID_PARAMETER);
1275
1276 if ( operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32
1277 || operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE64)
1278 {
1279 uint32_t cComponent = 0;
1280 if (operand0.numComponents == VGPU10_OPERAND_4_COMPONENT)
1281 cComponent = 4;
1282 else if (operand0.numComponents == VGPU10_OPERAND_1_COMPONENT)
1283 cComponent = 1;
1284
1285 for (uint32_t i = 0; i < cComponent; ++i)
1286 {
1287 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1288 paOperand->aImm[i] = dxbcTokenReaderRead32(r);
1289 }
1290 }
1291
1292 paOperand->numComponents = operand0.numComponents;
1293 paOperand->selectionMode = operand0.selectionMode;
1294 paOperand->mask = operand0.mask;
1295 paOperand->operandType = operand0.operandType;
1296 paOperand->indexDimension = operand0.indexDimension;
1297
1298 int rc = VINF_SUCCESS;
1299 /* 'indexDimension' tells the number of indices. 'i' is the array index, i.e. i = 0 for 1D, etc. */
1300 for (uint32_t i = 0; i < operand0.indexDimension; ++i)
1301 {
1302 if (i == 0) /* VGPU10_OPERAND_INDEX_1D */
1303 paOperand->aOperandIndex[i].indexRepresentation = operand0.index0Representation;
1304 else if (i == 1) /* VGPU10_OPERAND_INDEX_2D */
1305 paOperand->aOperandIndex[i].indexRepresentation = operand0.index1Representation;
1306 else /* VGPU10_OPERAND_INDEX_3D */
1307 continue; /* Skip because it is "rarely if ever used" and is not supported by VGPU10. */
1308
1309 uint32_t const indexRepresentation = paOperand->aOperandIndex[i].indexRepresentation;
1310 switch (indexRepresentation)
1311 {
1312 case VGPU10_OPERAND_INDEX_IMMEDIATE32:
1313 {
1314 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1315 paOperand->aOperandIndex[i].iOperandImmediate = dxbcTokenReaderRead32(r);
1316 break;
1317 }
1318 case VGPU10_OPERAND_INDEX_IMMEDIATE64:
1319 {
1320 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 2), VERR_INVALID_PARAMETER);
1321 paOperand->aOperandIndex[i].iOperandImmediate = dxbcTokenReaderRead64(r);
1322 break;
1323 }
1324 case VGPU10_OPERAND_INDEX_RELATIVE:
1325 {
1326 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1327 paOperand->aOperandIndex[i].pOperandRelative = &paOperand[1];
1328 Log6((" [operand index %d] parsing relative\n", i));
1329 rc = dxbcParseOperand(r, &paOperand[1], pcOperandRemain);
1330 break;
1331 }
1332 case VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE:
1333 {
1334 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 2), VERR_INVALID_PARAMETER);
1335 paOperand->aOperandIndex[i].iOperandImmediate = dxbcTokenReaderRead32(r);
1336 paOperand->aOperandIndex[i].pOperandRelative = &paOperand[1];
1337 Log6((" [operand index %d] parsing relative\n", i));
1338 rc = dxbcParseOperand(r, &paOperand[1], pcOperandRemain);
1339 break;
1340 }
1341 case VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE:
1342 {
1343 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 3), VERR_INVALID_PARAMETER);
1344 paOperand->aOperandIndex[i].iOperandImmediate = dxbcTokenReaderRead64(r);
1345 paOperand->aOperandIndex[i].pOperandRelative = &paOperand[1];
1346 Log6((" [operand index %d] parsing relative\n", i));
1347 rc = dxbcParseOperand(r, &paOperand[1], pcOperandRemain);
1348 break;
1349 }
1350 default:
1351 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
1352 }
1353 Log6((" [operand index %d] %s(%d): %#llx%s\n",
1354 i, dxbcOperandIndexRepresentationToString(indexRepresentation), indexRepresentation,
1355 paOperand->aOperandIndex[i].iOperandImmediate, paOperand->aOperandIndex[i].pOperandRelative ? " + relative" : ""));
1356 if (RT_FAILURE(rc))
1357 break;
1358 }
1359
1360 *pcOperandRemain -= 1;
1361 return VINF_SUCCESS;
1362}
1363
1364
1365/* Parse an instruction. */
1366static int dxbcParseOpcode(DXBCTokenReader *r, VGPUOpcode *pOpcode)
1367{
1368 RT_ZERO(*pOpcode);
1369 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1370
1371 VGPU10OpcodeToken0 opcode;
1372 opcode.value = dxbcTokenReaderRead32(r);
1373
1374 pOpcode->opcodeType = opcode.opcodeType;
1375 ASSERT_GUEST_RETURN(pOpcode->opcodeType < VGPU10_NUM_OPCODES, VERR_INVALID_PARAMETER);
1376
1377 uint32_t const cOperand = g_aOpcodeInfo[pOpcode->opcodeType].cOperand;
1378 if (cOperand != UINT32_MAX)
1379 {
1380 Log6(("[%#x] %s length %d %s\n",
1381 dxbcTokenReaderByteOffset(r) - 4, dxbcOpcodeToString(pOpcode->opcodeType), opcode.instructionLength, dxbcInterpolationModeToString(opcode.interpolationMode)));
1382
1383 ASSERT_GUEST_RETURN(cOperand < RT_ELEMENTS(pOpcode->aIdxOperand), VERR_INVALID_PARAMETER);
1384
1385 pOpcode->cOpcodeToken = opcode.instructionLength;
1386 if (opcode.extended)
1387 {
1388 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1389 if ( pOpcode->opcodeType == VGPU10_OPCODE_DCL_FUNCTION_BODY
1390 || pOpcode->opcodeType == VGPU10_OPCODE_DCL_FUNCTION_TABLE
1391 || pOpcode->opcodeType == VGPU10_OPCODE_DCL_INTERFACE
1392 || pOpcode->opcodeType == VGPU10_OPCODE_INTERFACE_CALL
1393 || pOpcode->opcodeType == VGPU10_OPCODE_DCL_THREAD_GROUP)
1394 {
1395 /* "next DWORD contains ... the actual instruction length in DWORD since it may not fit into 7 bits" */
1396 pOpcode->cOpcodeToken = dxbcTokenReaderRead32(r);
1397 }
1398 else
1399 AssertFailedReturn(VERR_NOT_IMPLEMENTED); /** @todo Anything else special for extended opcodes. */
1400 }
1401
1402 ASSERT_GUEST_RETURN(pOpcode->cOpcodeToken >= 1 && pOpcode->cOpcodeToken < 256, VERR_INVALID_PARAMETER);
1403 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, pOpcode->cOpcodeToken - 1), VERR_INVALID_PARAMETER);
1404
1405 /* Additional tokens before operands. */
1406 switch (pOpcode->opcodeType)
1407 {
1408 case VGPU10_OPCODE_INTERFACE_CALL:
1409 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1410 dxbcTokenReaderSkip(r, 1); /* Function index */
1411 break;
1412
1413 default:
1414 break;
1415 }
1416
1417 /* Operands. */
1418 uint32_t cOperandRemain = RT_ELEMENTS(pOpcode->aValOperand);
1419 for (uint32_t i = 0; i < cOperand; ++i)
1420 {
1421 Log6((" [operand %d]\n", i));
1422 uint32_t const idxOperand = RT_ELEMENTS(pOpcode->aValOperand) - cOperandRemain;
1423 pOpcode->aIdxOperand[i] = idxOperand;
1424 int rc = dxbcParseOperand(r, &pOpcode->aValOperand[idxOperand], &cOperandRemain);
1425 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), VERR_INVALID_PARAMETER);
1426 }
1427
1428 pOpcode->cOperand = cOperand;
1429
1430 /* Additional tokens after operands. */
1431 switch (pOpcode->opcodeType)
1432 {
1433 case VGPU10_OPCODE_DCL_INPUT_SIV:
1434 case VGPU10_OPCODE_DCL_INPUT_SGV:
1435 case VGPU10_OPCODE_DCL_INPUT_PS_SIV:
1436 case VGPU10_OPCODE_DCL_INPUT_PS_SGV:
1437 case VGPU10_OPCODE_DCL_OUTPUT_SIV:
1438 case VGPU10_OPCODE_DCL_OUTPUT_SGV:
1439 {
1440 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1441
1442 VGPU10NameToken name;
1443 name.value = dxbcTokenReaderRead32(r);
1444 Log6((" %s(%d)\n",
1445 dxbcSystemNameToString(name.name), name.name));
1446 pOpcode->semanticName = name.name;
1447 break;
1448 }
1449 case VGPU10_OPCODE_DCL_RESOURCE:
1450 {
1451 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1452 dxbcTokenReaderSkip(r, 1); /* ResourceReturnTypeToken */
1453 break;
1454 }
1455 case VGPU10_OPCODE_DCL_TEMPS:
1456 {
1457 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1458 dxbcTokenReaderSkip(r, 1); /* number of temps */
1459 break;
1460 }
1461 case VGPU10_OPCODE_DCL_INDEXABLE_TEMP:
1462 {
1463 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 3), VERR_INVALID_PARAMETER);
1464 dxbcTokenReaderSkip(r, 3); /* register index; number of registers; number of components */
1465 break;
1466 }
1467 case VGPU10_OPCODE_DCL_INDEX_RANGE:
1468 {
1469 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1470 dxbcTokenReaderSkip(r, 1); /* count of registers */
1471 break;
1472 }
1473 case VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT:
1474 {
1475 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1476 dxbcTokenReaderSkip(r, 1); /* maximum number of primitives */
1477 break;
1478 }
1479 case VGPU10_OPCODE_DCL_GS_INSTANCE_COUNT:
1480 {
1481 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1482 dxbcTokenReaderSkip(r, 1); /* number of instances */
1483 break;
1484 }
1485 case VGPU10_OPCODE_DCL_HS_MAX_TESSFACTOR:
1486 {
1487 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1488 dxbcTokenReaderSkip(r, 1); /* maximum TessFactor */
1489 break;
1490 }
1491 case VGPU10_OPCODE_DCL_HS_FORK_PHASE_INSTANCE_COUNT:
1492 case VGPU10_OPCODE_DCL_HS_JOIN_PHASE_INSTANCE_COUNT:
1493 {
1494 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1495 dxbcTokenReaderSkip(r, 1); /* number of instances of the current fork/join phase program to execute */
1496 break;
1497 }
1498 case VGPU10_OPCODE_DCL_THREAD_GROUP:
1499 {
1500 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 3), VERR_INVALID_PARAMETER);
1501 dxbcTokenReaderSkip(r, 3); /* Thread Group dimensions as UINT32: x, y, z */
1502 break;
1503 }
1504 case VGPU10_OPCODE_DCL_UAV_TYPED:
1505 {
1506 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1507 dxbcTokenReaderSkip(r, 1); /* ResourceReturnTypeToken */
1508 break;
1509 }
1510 case VGPU10_OPCODE_DCL_UAV_STRUCTURED:
1511 {
1512 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1513 dxbcTokenReaderSkip(r, 1); /* byte stride */
1514 break;
1515 }
1516 case VGPU10_OPCODE_DCL_TGSM_RAW:
1517 {
1518 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1519 dxbcTokenReaderSkip(r, 1); /* element count */
1520 break;
1521 }
1522 case VGPU10_OPCODE_DCL_TGSM_STRUCTURED:
1523 {
1524 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 2), VERR_INVALID_PARAMETER);
1525 dxbcTokenReaderSkip(r, 2); /* struct byte stride; struct count */
1526 break;
1527 }
1528 case VGPU10_OPCODE_DCL_RESOURCE_STRUCTURED:
1529 {
1530 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1531 dxbcTokenReaderSkip(r, 1); /* struct byte stride */
1532 break;
1533 }
1534 default:
1535 break;
1536 }
1537 }
1538 else
1539 {
1540 /* Special opcodes. */
1541 if (pOpcode->opcodeType == VGPU10_OPCODE_CUSTOMDATA)
1542 {
1543 Log6(("[%#x] %s %s\n",
1544 dxbcTokenReaderByteOffset(r), dxbcOpcodeToString(pOpcode->opcodeType), dxbcCustomDataClassToString(opcode.customDataClass)));
1545
1546 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, 1), VERR_INVALID_PARAMETER);
1547 pOpcode->cOpcodeToken = dxbcTokenReaderRead32(r);
1548
1549 if (pOpcode->cOpcodeToken < 2)
1550 pOpcode->cOpcodeToken = 2;
1551 ASSERT_GUEST_RETURN(dxbcTokenReaderCanRead(r, pOpcode->cOpcodeToken - 2), VERR_INVALID_PARAMETER);
1552
1553 dxbcTokenReaderSkip(r, pOpcode->cOpcodeToken - 2);
1554 }
1555 else if (pOpcode->opcodeType == VGPU10_OPCODE_VMWARE)
1556 {
1557 /** @todo implement */
1558 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
1559 }
1560 else
1561 ASSERT_GUEST_FAILED_RETURN(VERR_INVALID_PARAMETER);
1562
1563 // pOpcode->cOperand = 0;
1564 }
1565
1566 return VINF_SUCCESS;
1567}
1568
1569
1570/*
1571 * Parse and verify the shader byte code. Extract input and output signatures into pInfo.
1572 */
1573int DXShaderParse(void const *pvShaderCode, uint32_t cbShaderCode, DXShaderInfo *pInfo)
1574{
1575 if (pInfo)
1576 RT_ZERO(*pInfo);
1577
1578 ASSERT_GUEST_RETURN(cbShaderCode <= SVGA3D_MAX_SHADER_MEMORY_BYTES, VERR_INVALID_PARAMETER);
1579 ASSERT_GUEST_RETURN((cbShaderCode & 0x3) == 0, VERR_INVALID_PARAMETER); /* Aligned to the token size. */
1580 ASSERT_GUEST_RETURN(cbShaderCode >= 8, VERR_INVALID_PARAMETER); /* At least program and length tokens. */
1581
1582 uint32_t const *paToken = (uint32_t *)pvShaderCode;
1583
1584 VGPU10ProgramToken const *pProgramToken = (VGPU10ProgramToken *)&paToken[0];
1585 ASSERT_GUEST_RETURN( pProgramToken->majorVersion >= 4
1586 && pProgramToken->programType <= VGPU10_COMPUTE_SHADER, VERR_INVALID_PARAMETER);
1587 if (pInfo)
1588 pInfo->enmProgramType = (VGPU10_PROGRAM_TYPE)pProgramToken->programType;
1589
1590 uint32_t const cToken = paToken[1];
1591 Log6(("Shader version %d.%d type %s(%d) Length %d\n",
1592 pProgramToken->majorVersion, pProgramToken->minorVersion, dxbcShaderTypeToString(pProgramToken->programType), pProgramToken->programType, cToken));
1593 ASSERT_GUEST_RETURN(cbShaderCode / 4 == cToken, VERR_INVALID_PARAMETER); /* Declared length should be equal to the actual. */
1594
1595 DXBCTokenReader parser;
1596 RT_ZERO(parser);
1597
1598 DXBCTokenReader *r = &parser;
1599 r->pToken = &paToken[2];
1600 r->cToken = r->cRemainingToken = cToken - 2;
1601
1602 while (dxbcTokenReaderCanRead(r, 1))
1603 {
1604 VGPUOpcode opcode;
1605 int rc = dxbcParseOpcode(r, &opcode);
1606 ASSERT_GUEST_RETURN(RT_SUCCESS(rc), VERR_INVALID_PARAMETER);
1607
1608 if (pInfo)
1609 {
1610 /* Fetch signatures. */
1611 SVGA3dDXSignatureEntry *pSignatureEntry = NULL;
1612 switch (opcode.opcodeType)
1613 {
1614 case VGPU10_OPCODE_DCL_INPUT:
1615 case VGPU10_OPCODE_DCL_INPUT_PS:
1616 case VGPU10_OPCODE_DCL_INPUT_SIV:
1617 ASSERT_GUEST_RETURN(pInfo->cInputSignature < RT_ELEMENTS(pInfo->aInputSignature), VERR_INVALID_PARAMETER);
1618 pSignatureEntry = &pInfo->aInputSignature[pInfo->cInputSignature++];
1619 break;
1620 case VGPU10_OPCODE_DCL_OUTPUT:
1621 case VGPU10_OPCODE_DCL_OUTPUT_SIV:
1622 case VGPU10_OPCODE_DCL_OUTPUT_SGV:
1623 ASSERT_GUEST_RETURN(pInfo->cOutputSignature < RT_ELEMENTS(pInfo->aOutputSignature), VERR_INVALID_PARAMETER);
1624 pSignatureEntry = &pInfo->aOutputSignature[pInfo->cOutputSignature++];
1625 break;
1626 default:
1627 break;
1628 }
1629
1630 if (pSignatureEntry)
1631 {
1632 ASSERT_GUEST_RETURN( opcode.aValOperand[0].aOperandIndex[0].indexRepresentation == VGPU10_OPERAND_INDEX_IMMEDIATE32
1633 || opcode.aValOperand[0].aOperandIndex[0].indexRepresentation == VGPU10_OPERAND_INDEX_IMMEDIATE64,
1634 VERR_NOT_SUPPORTED);
1635
1636 uint32_t const indexDimension = opcode.aValOperand[0].indexDimension;
1637 if (indexDimension == VGPU10_OPERAND_INDEX_0D)
1638 {
1639 if (opcode.aValOperand[0].operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID)
1640 {
1641 pSignatureEntry->registerIndex = 0;
1642 pSignatureEntry->semanticName = SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID;
1643 }
1644 else if (opcode.aValOperand[0].operandType == VGPU10_OPERAND_TYPE_OUTPUT_DEPTH)
1645 {
1646 /* oDepth is always last in the signature. Register index is equal to 0xFFFFFFFF. */
1647 pSignatureEntry->registerIndex = 0xFFFFFFFF;
1648 pSignatureEntry->semanticName = SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED;
1649 }
1650 else
1651 ASSERT_GUEST_FAILED_RETURN(VERR_NOT_SUPPORTED);
1652 }
1653 else
1654 {
1655 ASSERT_GUEST_RETURN( indexDimension == VGPU10_OPERAND_INDEX_1D
1656 || indexDimension == VGPU10_OPERAND_INDEX_2D
1657 || indexDimension == VGPU10_OPERAND_INDEX_3D,
1658 VERR_NOT_SUPPORTED);
1659 /* The register index seems to be in the highest dimension. */
1660 pSignatureEntry->registerIndex = opcode.aValOperand[0].aOperandIndex[indexDimension - VGPU10_OPERAND_INDEX_1D].iOperandImmediate;
1661 pSignatureEntry->semanticName = opcode.semanticName;
1662 }
1663 pSignatureEntry->mask = opcode.aValOperand[0].mask;
1664 pSignatureEntry->componentType = SVGADX_SIGNATURE_REGISTER_COMPONENT_UNKNOWN; /// @todo Proper value? Seems that it is not important.
1665 pSignatureEntry->minPrecision = SVGADX_SIGNATURE_MIN_PRECISION_DEFAULT;
1666 }
1667 }
1668 }
1669
1670#ifdef LOG_ENABLED
1671 if (pInfo->cInputSignature)
1672 {
1673 Log6(("Input signatures:\n"));
1674 for (uint32_t i = 0; i < pInfo->cInputSignature; ++i)
1675 Log6((" [%u]: %u %u 0x%X\n", i, pInfo->aInputSignature[i].registerIndex, pInfo->aInputSignature[i].semanticName, pInfo->aInputSignature[i].mask));
1676 }
1677 if (pInfo->cOutputSignature)
1678 {
1679 Log6(("Output signatures:\n"));
1680 for (uint32_t i = 0; i < pInfo->cOutputSignature; ++i)
1681 Log6((" [%u]: %u %u 0x%X\n", i, pInfo->aOutputSignature[i].registerIndex, pInfo->aOutputSignature[i].semanticName, pInfo->aOutputSignature[i].mask));
1682 }
1683 if (pInfo->cPatchConstantSignature)
1684 {
1685 Log6(("Patch constant signatures:\n"));
1686 for (uint32_t i = 0; i < pInfo->cPatchConstantSignature; ++i)
1687 Log6((" [%u]: %u %u 0x%X\n", i, pInfo->aPatchConstantSignature[i].registerIndex, pInfo->aPatchConstantSignature[i].semanticName, pInfo->aPatchConstantSignature[i].mask));
1688 }
1689#endif
1690
1691 return VINF_SUCCESS;
1692}
1693
1694
1695#if 0 // Unused. Replaced with dxbcSemanticInfo.
1696static char const *dxbcSemanticName(SVGA3dDXSignatureSemanticName enmSemanticName)
1697{
1698 /* https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-semantics#system-value-semantics */
1699 switch (enmSemanticName)
1700 {
1701 case SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION: return "SV_Position";
1702 case SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE: return "SV_ClipDistance";
1703 case SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE: return "SV_CullDistance";
1704 case SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX: return "SV_RenderTargetArrayIndex";
1705 case SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX: return "SV_ViewportArrayIndex";
1706 case SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID: return "SV_VertexID";
1707 case SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID: return "SV_PrimitiveID";
1708 case SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID: return "SV_InstanceID";
1709 case SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE: return "SV_IsFrontFace";
1710 case SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX: return "SV_SampleIndex";
1711 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR: return "SV_FinalQuadUeq0EdgeTessFactor";
1712 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR: return "SV_FinalQuadVeq0EdgeTessFactor";
1713 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR: return "SV_FinalQuadUeq1EdgeTessFactor";
1714 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR: return "SV_FinalQuadVeq1EdgeTessFactor";
1715 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR: return "SV_FinalQuadUInsideTessFactor";
1716 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR: return "SV_FinalQuadVInsideTessFactor";
1717 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR: return "SV_FinalTriUeq0EdgeTessFactor";
1718 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR: return "SV_FinalTriVeq0EdgeTessFactor";
1719 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR: return "SV_FinalTriWeq0EdgeTessFactor";
1720 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR: return "SV_FinalTriInsideTessFactor";
1721 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR: return "SV_FinalLineDetailTessFactor";
1722 case SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR: return "SV_FinalLineDensityTessFactor";
1723 default:
1724 Assert(enmSemanticName == SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED);
1725 break;
1726 }
1727 /* Generic. Arbitrary name. It does not have any meaning. */
1728 return "ATTRIB";
1729}
1730#endif
1731
1732
1733/* https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-semantics#system-value-semantics
1734 * Type:
1735 * 0 - undefined
1736 * 1 - unsigned int
1737 * 2 - signed int
1738 * 3 - float
1739 */
1740typedef struct VGPUSemanticInfo
1741{
1742 char const *pszName;
1743 uint32_t u32Type;
1744} VGPUSemanticInfo;
1745
1746static VGPUSemanticInfo const g_aSemanticInfo[SVGADX_SIGNATURE_SEMANTIC_NAME_MAX] =
1747{
1748 { "ATTRIB", 0 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
1749 { "SV_Position", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
1750 { "SV_ClipDistance", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
1751 { "SV_CullDistance", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
1752 { "SV_RenderTargetArrayIndex", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
1753 { "SV_ViewportArrayIndex", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
1754 { "SV_VertexID", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
1755 { "SV_PrimitiveID", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
1756 { "SV_InstanceID", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
1757 { "SV_IsFrontFace", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
1758 { "SV_SampleIndex", 1 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
1759 /** @todo Is this a correct name for all TessFactors? */
1760 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
1761 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
1762 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
1763 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
1764 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
1765 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
1766 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
1767 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
1768 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
1769 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
1770 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
1771 { "SV_TessFactor", 3 }, // SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
1772};
1773
1774static VGPUSemanticInfo const g_SemanticPSOutput =
1775 { "SV_TARGET", 3 }; // SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
1776
1777
1778static VGPUSemanticInfo const *dxbcSemanticInfo(DXShaderInfo const *pInfo, SVGA3dDXSignatureSemanticName enmSemanticName, uint32_t u32BlobType)
1779{
1780 if (enmSemanticName < RT_ELEMENTS(g_aSemanticInfo))
1781 {
1782 if ( enmSemanticName == 0
1783 && pInfo->enmProgramType == VGPU10_PIXEL_SHADER
1784 && u32BlobType == DXBC_BLOB_TYPE_OSGN)
1785 return &g_SemanticPSOutput;
1786 return &g_aSemanticInfo[enmSemanticName];
1787 }
1788 return &g_aSemanticInfo[0];
1789}
1790
1791
1792static int dxbcCreateIOSGNBlob(DXShaderInfo const *pInfo, DXBCHeader *pHdr, uint32_t u32BlobType,
1793 uint32_t cSignature, SVGA3dDXSignatureEntry const *paSignature, DXBCByteWriter *w)
1794{
1795 /* aIdxSignature contains signature indices. aIdxSignature[0] = signature index for register 0. */
1796 uint32_t aIdxSignature[32];
1797 memset(aIdxSignature, 0xFF, sizeof(aIdxSignature));
1798 AssertReturn(cSignature <= RT_ELEMENTS(aIdxSignature), VERR_INTERNAL_ERROR);
1799 for (uint32_t i = 0; i < cSignature; ++i)
1800 {
1801 SVGA3dDXSignatureEntry const *src = &paSignature[i];
1802 if (src->registerIndex == 0xFFFFFFFF)
1803 {
1804 /* oDepth for PS output. */
1805 ASSERT_GUEST_RETURN(pInfo->enmProgramType == VGPU10_PIXEL_SHADER, VERR_INVALID_PARAMETER);
1806
1807 /* Must be placed last in the signature. */
1808 ASSERT_GUEST_RETURN(aIdxSignature[cSignature - 1] == 0xFFFFFFFF, VERR_INVALID_PARAMETER);
1809 aIdxSignature[cSignature - 1] = i;
1810 continue;
1811 }
1812
1813 ASSERT_GUEST_RETURN(src->registerIndex < RT_ELEMENTS(aIdxSignature), VERR_INVALID_PARAMETER);
1814 ASSERT_GUEST_RETURN(aIdxSignature[src->registerIndex] == 0xFFFFFFFF, VERR_INVALID_PARAMETER);
1815 aIdxSignature[src->registerIndex] = i;
1816 }
1817
1818 uint32_t cbBlob = RT_UOFFSETOF(DXBCBlobIOSGN, aElement[cSignature])
1819 + cSignature * RT_SIZEOFMEMB(DXBCBlobIOSGN, aElement[0]);
1820 if (!dxbcByteWriterCanWrite(w, sizeof(DXBCBlobHeader) + cbBlob))
1821 return VERR_NO_MEMORY;
1822
1823 DXBCBlobHeader *pHdrBlob = (DXBCBlobHeader *)dxbcByteWriterPtr(w);
1824 pHdrBlob->u32BlobType = u32BlobType;
1825 // pHdrBlob->cbBlob = 0;
1826
1827 DXBCBlobIOSGN *pHdrISGN = (DXBCBlobIOSGN *)&pHdrBlob[1];
1828 pHdrISGN->cElement = cSignature;
1829 pHdrISGN->offElement = RT_UOFFSETOF(DXBCBlobIOSGN, aElement[0]);
1830
1831 uint32_t aSemanticIdx[SVGADX_SIGNATURE_SEMANTIC_NAME_MAX];
1832 RT_ZERO(aSemanticIdx);
1833 uint32_t iSignature = 0;
1834 for (uint32_t iReg = 0; iReg < RT_ELEMENTS(aIdxSignature); ++iReg)
1835 {
1836 if (aIdxSignature[iReg] == 0xFFFFFFFF) /* This register is unused. */
1837 continue;
1838
1839 AssertReturn(iSignature < cSignature, VERR_INTERNAL_ERROR);
1840
1841 SVGA3dDXSignatureEntry const *src = &paSignature[aIdxSignature[iReg]];
1842 DXBCBlobIOSGNElement *dst = &pHdrISGN->aElement[iSignature];
1843
1844 ASSERT_GUEST_RETURN(src->semanticName < SVGADX_SIGNATURE_SEMANTIC_NAME_MAX, VERR_INVALID_PARAMETER);
1845 VGPUSemanticInfo const *pSemanticInfo = dxbcSemanticInfo(pInfo, src->semanticName, u32BlobType);
1846
1847 dst->offElementName = cbBlob; /* Offset of the semantic's name relative to the start of the blob (without hdr). */
1848 dst->idxSemantic = aSemanticIdx[src->semanticName]++;
1849 dst->enmSystemValue = src->semanticName;
1850 dst->enmComponentType = src->componentType ? src->componentType : pSemanticInfo->u32Type;
1851 dst->idxRegister = src->registerIndex;
1852 dst->mask = src->mask;
1853 if (u32BlobType == DXBC_BLOB_TYPE_OSGN)
1854 dst->mask2 = 0;
1855 else
1856 dst->mask2 = src->mask;
1857
1858 /* Figure out the semantic name for this element. */
1859 char const * const pszElementName = pSemanticInfo->pszName;
1860 uint32_t const cbElementName = (uint32_t)strlen(pszElementName) + 1;
1861
1862 if (!dxbcByteWriterCanWrite(w, cbBlob + cbElementName))
1863 return VERR_NO_MEMORY;
1864
1865 char *pszElementNameDst = (char *)pHdrISGN + dst->offElementName;
1866 memcpy(pszElementNameDst, pszElementName, cbElementName);
1867
1868 cbBlob += cbElementName;
1869 ++iSignature;
1870 }
1871
1872 /* Blobs are 4 bytes aligned. Commit the blob data. */
1873 cbBlob = RT_ALIGN_32(cbBlob, 4);
1874 pHdrBlob->cbBlob = cbBlob;
1875 pHdr->cbTotal += cbBlob + sizeof(DXBCBlobHeader);
1876 dxbcByteWriterCommit(w, cbBlob + sizeof(DXBCBlobHeader));
1877 return VINF_SUCCESS;
1878}
1879
1880
1881static int dxbcCreateSHDRBlob(DXBCHeader *pHdr, uint32_t u32BlobType,
1882 void const *pvShader, uint32_t cbShader, DXBCByteWriter *w)
1883{
1884 uint32_t cbBlob = cbShader;
1885 if (!dxbcByteWriterCanWrite(w, sizeof(DXBCBlobHeader) + cbBlob))
1886 return VERR_NO_MEMORY;
1887
1888 DXBCBlobHeader *pHdrBlob = (DXBCBlobHeader *)dxbcByteWriterPtr(w);
1889 pHdrBlob->u32BlobType = u32BlobType;
1890 // pHdrBlob->cbBlob = 0;
1891
1892 memcpy(&pHdrBlob[1], pvShader, cbShader);
1893
1894 /* Blobs are 4 bytes aligned. Commit the blob data. */
1895 cbBlob = RT_ALIGN_32(cbBlob, 4);
1896 pHdrBlob->cbBlob = cbBlob;
1897 pHdr->cbTotal += cbBlob + sizeof(DXBCBlobHeader);
1898 dxbcByteWriterCommit(w, cbBlob + sizeof(DXBCBlobHeader));
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/*
1904 * Create a DXBC container with signature and shader code data blobs.
1905 */
1906static int dxbcCreateFromInfo(DXShaderInfo const *pInfo, void const *pvShader, uint32_t cbShader, DXBCByteWriter *w)
1907{
1908 int rc;
1909
1910 /* Create a DXBC container with ISGN, OSGN and SHDR blobs. */
1911 uint32_t const cBlob = 3;
1912 uint32_t const cbHdr = RT_UOFFSETOF(DXBCHeader, aBlobOffset[cBlob]); /* Header with blob offsets. */
1913 if (!dxbcByteWriterCanWrite(w, cbHdr))
1914 return VERR_NO_MEMORY;
1915
1916 /* Container header. */
1917 DXBCHeader *pHdr = (DXBCHeader *)dxbcByteWriterPtr(w);
1918 pHdr->u32DXBC = DXBC_MAGIC;
1919 // RT_ZERO(pHdr->au8Hash);
1920 pHdr->u32Version = 1;
1921 pHdr->cbTotal = cbHdr;
1922 pHdr->cBlob = cBlob;
1923 //RT_ZERO(pHdr->aBlobOffset);
1924 dxbcByteWriterCommit(w, cbHdr);
1925
1926 /* Blobs. */
1927 uint32_t iBlob = 0;
1928
1929 pHdr->aBlobOffset[iBlob++] = dxbcByteWriterSize(w);
1930 rc = dxbcCreateIOSGNBlob(pInfo, pHdr, DXBC_BLOB_TYPE_ISGN, pInfo->cInputSignature, &pInfo->aInputSignature[0], w);
1931 AssertRCReturn(rc, rc);
1932
1933 pHdr->aBlobOffset[iBlob++] = dxbcByteWriterSize(w);
1934 rc = dxbcCreateIOSGNBlob(pInfo, pHdr, DXBC_BLOB_TYPE_OSGN, pInfo->cOutputSignature, &pInfo->aOutputSignature[0], w);
1935 AssertRCReturn(rc, rc);
1936
1937 pHdr->aBlobOffset[iBlob++] = dxbcByteWriterSize(w);
1938 rc = dxbcCreateSHDRBlob(pHdr, DXBC_BLOB_TYPE_SHDR, pvShader, cbShader, w);
1939 AssertRCReturn(rc, rc);
1940
1941 AssertCompile(RT_UOFFSETOF(DXBCHeader, u32Version) == 0x14);
1942 dxbcHash(&pHdr->u32Version, pHdr->cbTotal - RT_UOFFSETOF(DXBCHeader, u32Version), pHdr->au8Hash);
1943
1944 return VINF_SUCCESS;
1945}
1946
1947
1948int DXShaderCreateDXBC(DXShaderInfo const *pInfo, void const *pvShaderCode, uint32_t cbShaderCode, void **ppvDXBC, uint32_t *pcbDXBC)
1949{
1950 /* Build DXBC container. */
1951 int rc;
1952 DXBCByteWriter dxbcByteWriter;
1953 DXBCByteWriter *w = &dxbcByteWriter;
1954 if (dxbcByteWriterInit(w, 4096 + cbShaderCode))
1955 {
1956 rc = dxbcCreateFromInfo(pInfo, pvShaderCode, cbShaderCode, w);
1957 if (RT_SUCCESS(rc))
1958 dxbcByteWriterFetchData(w, ppvDXBC, pcbDXBC);
1959 }
1960 else
1961 rc = VERR_NO_MEMORY;
1962 return rc;
1963}
1964
1965
1966static char const *dxbcGetOutputSemanticName(DXShaderInfo const *pInfo, uint32_t idxRegister, uint32_t u32BlobType,
1967 uint32_t cSignature, SVGA3dDXSignatureEntry const *paSignature)
1968{
1969 for (uint32_t i = 0; i < cSignature; ++i)
1970 {
1971 SVGA3dDXSignatureEntry const *p = &paSignature[i];
1972 if (p->registerIndex == idxRegister)
1973 {
1974 AssertReturn(p->semanticName < SVGADX_SIGNATURE_SEMANTIC_NAME_MAX, NULL);
1975 VGPUSemanticInfo const *pSemanticInfo = dxbcSemanticInfo(pInfo, p->semanticName, u32BlobType);
1976 return pSemanticInfo->pszName;
1977 }
1978 }
1979 return NULL;
1980}
1981
1982char const *DXShaderGetOutputSemanticName(DXShaderInfo const *pInfo, uint32_t idxRegister)
1983{
1984 return dxbcGetOutputSemanticName(pInfo, idxRegister, DXBC_BLOB_TYPE_OSGN, pInfo->cOutputSignature, &pInfo->aOutputSignature[0]);
1985}
1986
1987
1988#ifdef DXBC_STANDALONE_TEST
1989static int dxbcCreateFromBytecode(void const *pvShaderCode, uint32_t cbShaderCode, void **ppvDXBC, uint32_t *pcbDXBC)
1990{
1991 /* Parse the shader bytecode and create DXBC container with resource, signature and shader bytecode blobs. */
1992 DXShaderInfo info;
1993 RT_ZERO(info);
1994 int rc = DXShaderParse(pvShaderCode, cbShaderCode, &info);
1995 if (RT_SUCCESS(rc))
1996 rc = DXShaderCreateDXBC(&info, pvShaderCode, cbShaderCode, ppvDXBC, pcbDXBC);
1997 return rc;
1998}
1999
2000static int parseShaderVM(void const *pvShaderCode, uint32_t cbShaderCode)
2001{
2002 void *pv = NULL;
2003 uint32_t cb = 0;
2004 int rc = dxbcCreateFromBytecode(pvShaderCode, cbShaderCode, &pv, &cb);
2005 if (RT_SUCCESS(rc))
2006 {
2007 /* Hexdump DXBC */
2008 printf("{\n");
2009 uint8_t *pu8 = (uint8_t *)pv;
2010 for (uint32_t i = 0; i < cb; ++i)
2011 {
2012 if ((i % 16) == 0)
2013 {
2014 if (i > 0)
2015 printf(",\n");
2016
2017 printf(" 0x%02x", pu8[i]);
2018 }
2019 else
2020 {
2021 printf(", 0x%02x", pu8[i]);
2022 }
2023 }
2024 printf("\n");
2025 printf("};\n");
2026
2027 RTMemFree(pv);
2028 }
2029
2030 return rc;
2031}
2032
2033static DXBCBlobHeader *dxbcFindBlob(DXBCHeader *pDXBCHeader, uint32_t u32BlobType)
2034{
2035 uint8_t const *pu8DXBCBegin = (uint8_t *)pDXBCHeader;
2036 for (uint32_t i = 0; i < pDXBCHeader->cBlob; ++i)
2037 {
2038 DXBCBlobHeader *pCurrentBlob = (DXBCBlobHeader *)&pu8DXBCBegin[pDXBCHeader->aBlobOffset[i]];
2039 if (pCurrentBlob->u32BlobType == u32BlobType)
2040 return pCurrentBlob;
2041 }
2042 return NULL;
2043}
2044
2045static int dxbcExtractShaderCode(DXBCHeader *pDXBCHeader, void **ppvCode, uint32_t *pcbCode)
2046{
2047 DXBCBlobHeader *pBlob = dxbcFindBlob(pDXBCHeader, DXBC_BLOB_TYPE_SHDR);
2048 AssertReturn(pBlob, VERR_NOT_IMPLEMENTED);
2049
2050 DXBCBlobSHDR *pSHDR = (DXBCBlobSHDR *)&pBlob[1];
2051 *pcbCode = pSHDR->cToken * 4;
2052 *ppvCode = RTMemAlloc(*pcbCode);
2053 AssertReturn(*ppvCode, VERR_NO_MEMORY);
2054
2055 memcpy(*ppvCode, pSHDR, *pcbCode);
2056 return VINF_SUCCESS;
2057}
2058
2059static int parseShaderDXBC(void const *pvDXBC)
2060{
2061 DXBCHeader *pDXBCHeader = (DXBCHeader *)pvDXBC;
2062 void *pvShaderCode = NULL;
2063 uint32_t cbShaderCode = 0;
2064 int rc = dxbcExtractShaderCode(pDXBCHeader, &pvShaderCode, &cbShaderCode);
2065 if (RT_SUCCESS(rc))
2066 {
2067 rc = parseShaderVM(pvShaderCode, cbShaderCode);
2068 RTMemFree(pvShaderCode);
2069 }
2070 return rc;
2071}
2072#endif /* DXBC_STANDALONE_TEST */
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