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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA3d-win-dx.cpp@ 86864

Last change on this file since 86864 was 86864, checked in by vboxsync, 4 years ago

Devices/Graphics: vmsvga3dQueryCaps for DX backend. bugref:9830
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1/* $Id: DevVGA-SVGA3d-win-dx.cpp 86864 2020-11-12 06:05:51Z vboxsync $ */
2/** @file
3 * DevVMWare - VMWare SVGA device
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_VMSVGA
23#include <VBox/AssertGuest.h>
24#include <VBox/log.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/vmm/pgm.h>
27
28#include <iprt/assert.h>
29#include <iprt/errcore.h>
30#include <iprt/mem.h>
31
32#include <VBoxVideo.h> /* required by DevVGA.h */
33#include <VBoxVideo3D.h>
34
35/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
36#include "DevVGA.h"
37
38#include "DevVGA-SVGA.h"
39#include "DevVGA-SVGA3d.h"
40#include "DevVGA-SVGA3d-internal.h"
41
42#include <d3d11.h>
43
44
45/* What kind of resource has been created for the VMSVGA3D surface. */
46typedef enum VMSVGA3DBACKRESTYPE
47{
48 VMSVGA3D_RESTYPE_NONE = 0,
49 VMSVGA3D_RESTYPE_SCREEN_TARGET = 1,
50 VMSVGA3D_RESTYPE_SURFACE = 2,
51 VMSVGA3D_RESTYPE_TEXTURE = 3,
52 VMSVGA3D_RESTYPE_CUBE_TEXTURE = 4,
53 VMSVGA3D_RESTYPE_VOLUME_TEXTURE = 5,
54 VMSVGA3D_RESTYPE_VERTEX_BUFFER = 6,
55 VMSVGA3D_RESTYPE_INDEX_BUFFER = 7,
56} VMSVGA3DBACKRESTYPE;
57
58struct VMSVGA3DBACKENDSURFACE
59{
60 VMSVGA3DBACKRESTYPE enmResType;
61 union
62 {
63 struct
64 {
65 ID3D11Texture2D *pTexture; /* The texture for the screen content. */
66 ID3D11Texture2D *pDynamicTexture; /* For screen updates from memory. */ /** @todo One for all screens. */
67 ID3D11Texture2D *pStagingTexture; /* For Reading the screen content. */ /** @todo One for all screens. */
68 } ScreenTarget;
69 struct
70 {
71 } Texture;
72 } u;
73} VMSVGA3DBACKENDSURFACE;
74
75typedef struct VMSVGAHWSCREEN
76{
77 ID3D11Texture2D *pTexture; /* Shared texture for the screen content. Only used as CopyResource target. */
78 IDXGIResource *pDxgiResource; /* Interface of the texture. */
79 IDXGIKeyedMutex *pDXGIKeyedMutex; /* Synchronization interface for the render device. */
80 HANDLE SharedHandle; /* The shared handle of this structure. */
81 uint32_t sidScreenTarget; /* The source surface for this screen. */
82} VMSVGAHWSCREEN;
83
84struct VMSVGA3DBACKEND
85{
86 RTLDRMOD hD3D11;
87 PFN_D3D11_CREATE_DEVICE pfnD3D11CreateDevice;
88
89 ID3D11Device *pDevice; /* Device for the VMSVGA3D context independent operation. */
90 ID3D11DeviceContext *pImmediateContext; /* Corresponding context. */
91 IDXGIFactory *pDxgiFactory; /* DXGI Factory. */
92 D3D_FEATURE_LEVEL FeatureLevel;
93} VMSVGA3DBACKEND;
94
95
96static DXGI_FORMAT vmsvgaDXScreenTargetFormat2Dxgi(SVGA3dSurfaceFormat format)
97{
98 switch (format)
99 {
100 /** @todo More formats required? */
101 case SVGA3D_X8R8G8B8: return DXGI_FORMAT_B8G8R8A8_UNORM;
102 case SVGA3D_A8R8G8B8: return DXGI_FORMAT_B8G8R8A8_UNORM;
103 default:
104 AssertFailed();
105 break;
106 }
107 return DXGI_FORMAT_UNKNOWN;
108}
109
110
111static DXGI_FORMAT vmsvgaDXSurfaceFormat2Dxgi(SVGA3dSurfaceFormat format)
112{
113#define DXGI_FORMAT_ DXGI_FORMAT_UNKNOWN
114 /** @todo More formats. */
115 switch (format)
116 {
117 case SVGA3D_X8R8G8B8: return DXGI_FORMAT_B8G8R8X8_UNORM;
118 case SVGA3D_A8R8G8B8: return DXGI_FORMAT_B8G8R8A8_UNORM;
119 case SVGA3D_R5G6B5: return DXGI_FORMAT_B5G6R5_UNORM;
120 case SVGA3D_X1R5G5B5: return DXGI_FORMAT_B5G5R5A1_UNORM;
121 case SVGA3D_A1R5G5B5: return DXGI_FORMAT_B5G5R5A1_UNORM;
122 case SVGA3D_A4R4G4B4: break; // 11.1 return DXGI_FORMAT_B4G4R4A4_UNORM;
123 case SVGA3D_Z_D32: break;
124 case SVGA3D_Z_D16: return DXGI_FORMAT_D16_UNORM;
125 case SVGA3D_Z_D24S8: return DXGI_FORMAT_D24_UNORM_S8_UINT;
126 case SVGA3D_Z_D15S1: break;
127 case SVGA3D_LUMINANCE8: return DXGI_FORMAT_;
128 case SVGA3D_LUMINANCE4_ALPHA4: return DXGI_FORMAT_;
129 case SVGA3D_LUMINANCE16: return DXGI_FORMAT_;
130 case SVGA3D_LUMINANCE8_ALPHA8: return DXGI_FORMAT_;
131 case SVGA3D_DXT1: return DXGI_FORMAT_;
132 case SVGA3D_DXT2: return DXGI_FORMAT_;
133 case SVGA3D_DXT3: return DXGI_FORMAT_;
134 case SVGA3D_DXT4: return DXGI_FORMAT_;
135 case SVGA3D_DXT5: return DXGI_FORMAT_;
136 case SVGA3D_BUMPU8V8: return DXGI_FORMAT_;
137 case SVGA3D_BUMPL6V5U5: return DXGI_FORMAT_;
138 case SVGA3D_BUMPX8L8V8U8: return DXGI_FORMAT_;
139 case SVGA3D_FORMAT_DEAD1: break;
140 case SVGA3D_ARGB_S10E5: return DXGI_FORMAT_;
141 case SVGA3D_ARGB_S23E8: return DXGI_FORMAT_;
142 case SVGA3D_A2R10G10B10: return DXGI_FORMAT_;
143 case SVGA3D_V8U8: return DXGI_FORMAT_;
144 case SVGA3D_Q8W8V8U8: return DXGI_FORMAT_;
145 case SVGA3D_CxV8U8: return DXGI_FORMAT_;
146 case SVGA3D_X8L8V8U8: return DXGI_FORMAT_;
147 case SVGA3D_A2W10V10U10: return DXGI_FORMAT_;
148 case SVGA3D_ALPHA8: return DXGI_FORMAT_;
149 case SVGA3D_R_S10E5: return DXGI_FORMAT_;
150 case SVGA3D_R_S23E8: return DXGI_FORMAT_;
151 case SVGA3D_RG_S10E5: return DXGI_FORMAT_;
152 case SVGA3D_RG_S23E8: return DXGI_FORMAT_;
153 case SVGA3D_BUFFER: return DXGI_FORMAT_;
154 case SVGA3D_Z_D24X8: return DXGI_FORMAT_;
155 case SVGA3D_V16U16: return DXGI_FORMAT_;
156 case SVGA3D_G16R16: return DXGI_FORMAT_;
157 case SVGA3D_A16B16G16R16: return DXGI_FORMAT_;
158 case SVGA3D_UYVY: return DXGI_FORMAT_;
159 case SVGA3D_YUY2: return DXGI_FORMAT_;
160 case SVGA3D_NV12: return DXGI_FORMAT_;
161 case SVGA3D_AYUV: return DXGI_FORMAT_;
162 case SVGA3D_R32G32B32A32_TYPELESS: return DXGI_FORMAT_R32G32B32A32_TYPELESS;
163 case SVGA3D_R32G32B32A32_UINT: return DXGI_FORMAT_R32G32B32A32_UINT;
164 case SVGA3D_R32G32B32A32_SINT: return DXGI_FORMAT_R32G32B32A32_SINT;
165 case SVGA3D_R32G32B32_TYPELESS: return DXGI_FORMAT_R32G32B32_TYPELESS;
166 case SVGA3D_R32G32B32_FLOAT: return DXGI_FORMAT_R32G32B32_FLOAT;
167 case SVGA3D_R32G32B32_UINT: return DXGI_FORMAT_R32G32B32_UINT;
168 case SVGA3D_R32G32B32_SINT: return DXGI_FORMAT_R32G32B32_SINT;
169 case SVGA3D_R16G16B16A16_TYPELESS: return DXGI_FORMAT_R16G16B16A16_TYPELESS;
170 case SVGA3D_R16G16B16A16_UINT: return DXGI_FORMAT_R16G16B16A16_UINT;
171 case SVGA3D_R16G16B16A16_SNORM: return DXGI_FORMAT_R16G16B16A16_SNORM;
172 case SVGA3D_R16G16B16A16_SINT: return DXGI_FORMAT_R16G16B16A16_SINT;
173 case SVGA3D_R32G32_TYPELESS: return DXGI_FORMAT_R32G32_TYPELESS;
174 case SVGA3D_R32G32_UINT: return DXGI_FORMAT_R32G32_UINT;
175 case SVGA3D_R32G32_SINT: return DXGI_FORMAT_R32G32_SINT;
176 case SVGA3D_R32G8X24_TYPELESS: return DXGI_FORMAT_R32G8X24_TYPELESS;
177 case SVGA3D_D32_FLOAT_S8X24_UINT: return DXGI_FORMAT_D32_FLOAT_S8X24_UINT;
178 case SVGA3D_R32_FLOAT_X8X24: return DXGI_FORMAT_R32_FLOAT_X8X24_TYPELESS;
179 case SVGA3D_X32_G8X24_UINT: return DXGI_FORMAT_X32_TYPELESS_G8X24_UINT;
180 case SVGA3D_R10G10B10A2_TYPELESS: return DXGI_FORMAT_R10G10B10A2_TYPELESS;
181 case SVGA3D_R10G10B10A2_UINT: return DXGI_FORMAT_R10G10B10A2_UINT;
182 case SVGA3D_R11G11B10_FLOAT: return DXGI_FORMAT_R11G11B10_FLOAT;
183 case SVGA3D_R8G8B8A8_TYPELESS: return DXGI_FORMAT_R8G8B8A8_TYPELESS;
184 case SVGA3D_R8G8B8A8_UNORM: return DXGI_FORMAT_R8G8B8A8_UNORM;
185 case SVGA3D_R8G8B8A8_UNORM_SRGB: return DXGI_FORMAT_R8G8B8A8_UNORM_SRGB;
186 case SVGA3D_R8G8B8A8_UINT: return DXGI_FORMAT_R8G8B8A8_UINT;
187 case SVGA3D_R8G8B8A8_SINT: return DXGI_FORMAT_R8G8B8A8_SINT;
188 case SVGA3D_R16G16_TYPELESS: return DXGI_FORMAT_R16G16_TYPELESS;
189 case SVGA3D_R16G16_UINT: return DXGI_FORMAT_R16G16_UINT;
190 case SVGA3D_R16G16_SINT: return DXGI_FORMAT_R16G16_SINT;
191 case SVGA3D_R32_TYPELESS: return DXGI_FORMAT_R32_TYPELESS;
192 case SVGA3D_D32_FLOAT: return DXGI_FORMAT_D32_FLOAT;
193 case SVGA3D_R32_UINT: return DXGI_FORMAT_R32_UINT;
194 case SVGA3D_R32_SINT: return DXGI_FORMAT_R32_SINT;
195 case SVGA3D_R24G8_TYPELESS: return DXGI_FORMAT_R24G8_TYPELESS;
196 case SVGA3D_D24_UNORM_S8_UINT: return DXGI_FORMAT_D24_UNORM_S8_UINT;
197 case SVGA3D_R24_UNORM_X8: return DXGI_FORMAT_R24_UNORM_X8_TYPELESS;
198 case SVGA3D_X24_G8_UINT: return DXGI_FORMAT_X24_TYPELESS_G8_UINT;
199 case SVGA3D_R8G8_TYPELESS: return DXGI_FORMAT_R8G8_TYPELESS;
200 case SVGA3D_R8G8_UNORM: return DXGI_FORMAT_R8G8_UNORM;
201 case SVGA3D_R8G8_UINT: return DXGI_FORMAT_R8G8_UINT;
202 case SVGA3D_R8G8_SINT: return DXGI_FORMAT_R8G8_SINT;
203 case SVGA3D_R16_TYPELESS: return DXGI_FORMAT_R16_TYPELESS;
204 case SVGA3D_R16_UNORM: return DXGI_FORMAT_R16_UNORM;
205 case SVGA3D_R16_UINT: return DXGI_FORMAT_R16_UINT;
206 case SVGA3D_R16_SNORM: return DXGI_FORMAT_R16_SNORM;
207 case SVGA3D_R16_SINT: return DXGI_FORMAT_R16_SINT;
208 case SVGA3D_R8_TYPELESS: return DXGI_FORMAT_R8_TYPELESS;
209 case SVGA3D_R8_UNORM: return DXGI_FORMAT_R8_UNORM;
210 case SVGA3D_R8_UINT: return DXGI_FORMAT_R8_UINT;
211 case SVGA3D_R8_SNORM: return DXGI_FORMAT_R8_SNORM;
212 case SVGA3D_R8_SINT: return DXGI_FORMAT_R8_SINT;
213 case SVGA3D_P8: break;
214 case SVGA3D_R9G9B9E5_SHAREDEXP: return DXGI_FORMAT_R9G9B9E5_SHAREDEXP;
215 case SVGA3D_R8G8_B8G8_UNORM: return DXGI_FORMAT_R8G8_B8G8_UNORM;
216 case SVGA3D_G8R8_G8B8_UNORM: return DXGI_FORMAT_G8R8_G8B8_UNORM;
217 case SVGA3D_BC1_TYPELESS: return DXGI_FORMAT_BC1_TYPELESS;
218 case SVGA3D_BC1_UNORM_SRGB: return DXGI_FORMAT_BC1_UNORM_SRGB;
219 case SVGA3D_BC2_TYPELESS: return DXGI_FORMAT_BC2_TYPELESS;
220 case SVGA3D_BC2_UNORM_SRGB: return DXGI_FORMAT_BC2_UNORM_SRGB;
221 case SVGA3D_BC3_TYPELESS: return DXGI_FORMAT_BC3_TYPELESS;
222 case SVGA3D_BC3_UNORM_SRGB: return DXGI_FORMAT_BC3_UNORM_SRGB;
223 case SVGA3D_BC4_TYPELESS: return DXGI_FORMAT_BC4_TYPELESS;
224 case SVGA3D_ATI1: break;
225 case SVGA3D_BC4_SNORM: return DXGI_FORMAT_BC4_SNORM;
226 case SVGA3D_BC5_TYPELESS: return DXGI_FORMAT_BC5_TYPELESS;
227 case SVGA3D_ATI2: break;
228 case SVGA3D_BC5_SNORM: return DXGI_FORMAT_BC5_SNORM;
229 case SVGA3D_R10G10B10_XR_BIAS_A2_UNORM: return DXGI_FORMAT_R10G10B10_XR_BIAS_A2_UNORM;
230 case SVGA3D_B8G8R8A8_TYPELESS: return DXGI_FORMAT_B8G8R8A8_TYPELESS;
231 case SVGA3D_B8G8R8A8_UNORM_SRGB: return DXGI_FORMAT_B8G8R8A8_UNORM_SRGB;
232 case SVGA3D_B8G8R8X8_TYPELESS: return DXGI_FORMAT_B8G8R8X8_TYPELESS;
233 case SVGA3D_B8G8R8X8_UNORM_SRGB: return DXGI_FORMAT_B8G8R8X8_UNORM_SRGB;
234 case SVGA3D_Z_DF16: break;
235 case SVGA3D_Z_DF24: break;
236 case SVGA3D_Z_D24S8_INT: return DXGI_FORMAT_D24_UNORM_S8_UINT;
237 case SVGA3D_YV12: break;
238 case SVGA3D_R32G32B32A32_FLOAT: return DXGI_FORMAT_R32G32B32A32_FLOAT;
239 case SVGA3D_R16G16B16A16_FLOAT: return DXGI_FORMAT_R16G16B16A16_FLOAT;
240 case SVGA3D_R16G16B16A16_UNORM: return DXGI_FORMAT_R16G16B16A16_UNORM;
241 case SVGA3D_R32G32_FLOAT: return DXGI_FORMAT_R32G32_FLOAT;
242 case SVGA3D_R10G10B10A2_UNORM: return DXGI_FORMAT_R10G10B10A2_UNORM;
243 case SVGA3D_R8G8B8A8_SNORM: return DXGI_FORMAT_R8G8B8A8_SNORM;
244 case SVGA3D_R16G16_FLOAT: return DXGI_FORMAT_R16G16_FLOAT;
245 case SVGA3D_R16G16_UNORM: return DXGI_FORMAT_R16G16_UNORM;
246 case SVGA3D_R16G16_SNORM: return DXGI_FORMAT_R16G16_SNORM;
247 case SVGA3D_R32_FLOAT: return DXGI_FORMAT_R32_FLOAT;
248 case SVGA3D_R8G8_SNORM: return DXGI_FORMAT_R8G8_SNORM;
249 case SVGA3D_R16_FLOAT: return DXGI_FORMAT_R16_FLOAT;
250 case SVGA3D_D16_UNORM: return DXGI_FORMAT_D16_UNORM;
251 case SVGA3D_A8_UNORM: return DXGI_FORMAT_A8_UNORM;
252 case SVGA3D_BC1_UNORM: return DXGI_FORMAT_BC1_UNORM;
253 case SVGA3D_BC2_UNORM: return DXGI_FORMAT_BC2_UNORM;
254 case SVGA3D_BC3_UNORM: return DXGI_FORMAT_BC3_UNORM;
255 case SVGA3D_B5G6R5_UNORM: return DXGI_FORMAT_B5G6R5_UNORM;
256 case SVGA3D_B5G5R5A1_UNORM: return DXGI_FORMAT_B5G5R5A1_UNORM;
257 case SVGA3D_B8G8R8A8_UNORM: return DXGI_FORMAT_B8G8R8A8_UNORM;
258 case SVGA3D_B8G8R8X8_UNORM: return DXGI_FORMAT_B8G8R8X8_UNORM;
259 case SVGA3D_BC4_UNORM: return DXGI_FORMAT_BC4_UNORM;
260 case SVGA3D_BC5_UNORM: return DXGI_FORMAT_BC5_UNORM;
261
262 case SVGA3D_FORMAT_INVALID:
263 case SVGA3D_FORMAT_MAX: break;
264 }
265 // AssertFailed();
266 return DXGI_FORMAT_UNKNOWN;
267#undef DXGI_FORMAT_
268}
269
270
271static SVGA3dSurfaceFormat vmsvgaDXDevCapSurfaceFmt2Format(SVGA3dDevCapIndex enmDevCap)
272{
273 switch (enmDevCap)
274 {
275 case SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8: return SVGA3D_X8R8G8B8;
276 case SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8: return SVGA3D_A8R8G8B8;
277 case SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10: return SVGA3D_A2R10G10B10;
278 case SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5: return SVGA3D_X1R5G5B5;
279 case SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5: return SVGA3D_A1R5G5B5;
280 case SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4: return SVGA3D_A4R4G4B4;
281 case SVGA3D_DEVCAP_SURFACEFMT_R5G6B5: return SVGA3D_R5G6B5;
282 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16: return SVGA3D_LUMINANCE16;
283 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8: return SVGA3D_LUMINANCE8_ALPHA8;
284 case SVGA3D_DEVCAP_SURFACEFMT_ALPHA8: return SVGA3D_ALPHA8;
285 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8: return SVGA3D_LUMINANCE8;
286 case SVGA3D_DEVCAP_SURFACEFMT_Z_D16: return SVGA3D_Z_D16;
287 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8: return SVGA3D_Z_D24S8;
288 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8: return SVGA3D_Z_D24X8;
289 case SVGA3D_DEVCAP_SURFACEFMT_DXT1: return SVGA3D_DXT1;
290 case SVGA3D_DEVCAP_SURFACEFMT_DXT2: return SVGA3D_DXT2;
291 case SVGA3D_DEVCAP_SURFACEFMT_DXT3: return SVGA3D_DXT3;
292 case SVGA3D_DEVCAP_SURFACEFMT_DXT4: return SVGA3D_DXT4;
293 case SVGA3D_DEVCAP_SURFACEFMT_DXT5: return SVGA3D_DXT5;
294 case SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8: return SVGA3D_BUMPX8L8V8U8;
295 case SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10: return SVGA3D_A2W10V10U10;
296 case SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8: return SVGA3D_BUMPU8V8;
297 case SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8: return SVGA3D_Q8W8V8U8;
298 case SVGA3D_DEVCAP_SURFACEFMT_CxV8U8: return SVGA3D_CxV8U8;
299 case SVGA3D_DEVCAP_SURFACEFMT_R_S10E5: return SVGA3D_R_S10E5;
300 case SVGA3D_DEVCAP_SURFACEFMT_R_S23E8: return SVGA3D_R_S23E8;
301 case SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5: return SVGA3D_RG_S10E5;
302 case SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8: return SVGA3D_RG_S23E8;
303 case SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5: return SVGA3D_ARGB_S10E5;
304 case SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8: return SVGA3D_ARGB_S23E8;
305 case SVGA3D_DEVCAP_SURFACEFMT_V16U16: return SVGA3D_V16U16;
306 case SVGA3D_DEVCAP_SURFACEFMT_G16R16: return SVGA3D_G16R16;
307 case SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16: return SVGA3D_A16B16G16R16;
308 case SVGA3D_DEVCAP_SURFACEFMT_UYVY: return SVGA3D_UYVY;
309 case SVGA3D_DEVCAP_SURFACEFMT_YUY2: return SVGA3D_YUY2;
310 case SVGA3D_DEVCAP_SURFACEFMT_NV12: return SVGA3D_NV12;
311 case SVGA3D_DEVCAP_SURFACEFMT_AYUV: return SVGA3D_AYUV;
312 case SVGA3D_DEVCAP_SURFACEFMT_Z_DF16: return SVGA3D_Z_DF16;
313 case SVGA3D_DEVCAP_SURFACEFMT_Z_DF24: return SVGA3D_Z_DF24;
314 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT: return SVGA3D_Z_D24S8_INT;
315 case SVGA3D_DEVCAP_SURFACEFMT_ATI1: return SVGA3D_ATI1;
316 case SVGA3D_DEVCAP_SURFACEFMT_ATI2: return SVGA3D_ATI2;
317 case SVGA3D_DEVCAP_SURFACEFMT_YV12: return SVGA3D_YV12;
318 default:
319 AssertFailed();
320 break;
321 }
322 return SVGA3D_FORMAT_INVALID;
323}
324
325
326static SVGA3dSurfaceFormat vmsvgaDXDevCapDxfmt2Format(SVGA3dDevCapIndex enmDevCap)
327{
328 switch (enmDevCap)
329 {
330 case SVGA3D_DEVCAP_DXFMT_X8R8G8B8: return SVGA3D_X8R8G8B8;
331 case SVGA3D_DEVCAP_DXFMT_A8R8G8B8: return SVGA3D_A8R8G8B8;
332 case SVGA3D_DEVCAP_DXFMT_R5G6B5: return SVGA3D_R5G6B5;
333 case SVGA3D_DEVCAP_DXFMT_X1R5G5B5: return SVGA3D_X1R5G5B5;
334 case SVGA3D_DEVCAP_DXFMT_A1R5G5B5: return SVGA3D_A1R5G5B5;
335 case SVGA3D_DEVCAP_DXFMT_A4R4G4B4: return SVGA3D_A4R4G4B4;
336 case SVGA3D_DEVCAP_DXFMT_Z_D32: return SVGA3D_Z_D32;
337 case SVGA3D_DEVCAP_DXFMT_Z_D16: return SVGA3D_Z_D16;
338 case SVGA3D_DEVCAP_DXFMT_Z_D24S8: return SVGA3D_Z_D24S8;
339 case SVGA3D_DEVCAP_DXFMT_Z_D15S1: return SVGA3D_Z_D15S1;
340 case SVGA3D_DEVCAP_DXFMT_LUMINANCE8: return SVGA3D_LUMINANCE8;
341 case SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4: return SVGA3D_LUMINANCE4_ALPHA4;
342 case SVGA3D_DEVCAP_DXFMT_LUMINANCE16: return SVGA3D_LUMINANCE16;
343 case SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8: return SVGA3D_LUMINANCE8_ALPHA8;
344 case SVGA3D_DEVCAP_DXFMT_DXT1: return SVGA3D_DXT1;
345 case SVGA3D_DEVCAP_DXFMT_DXT2: return SVGA3D_DXT2;
346 case SVGA3D_DEVCAP_DXFMT_DXT3: return SVGA3D_DXT3;
347 case SVGA3D_DEVCAP_DXFMT_DXT4: return SVGA3D_DXT4;
348 case SVGA3D_DEVCAP_DXFMT_DXT5: return SVGA3D_DXT5;
349 case SVGA3D_DEVCAP_DXFMT_BUMPU8V8: return SVGA3D_BUMPU8V8;
350 case SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5: return SVGA3D_BUMPL6V5U5;
351 case SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8: return SVGA3D_BUMPX8L8V8U8;
352 case SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1: return SVGA3D_FORMAT_DEAD1;
353 case SVGA3D_DEVCAP_DXFMT_ARGB_S10E5: return SVGA3D_ARGB_S10E5;
354 case SVGA3D_DEVCAP_DXFMT_ARGB_S23E8: return SVGA3D_ARGB_S23E8;
355 case SVGA3D_DEVCAP_DXFMT_A2R10G10B10: return SVGA3D_A2R10G10B10;
356 case SVGA3D_DEVCAP_DXFMT_V8U8: return SVGA3D_V8U8;
357 case SVGA3D_DEVCAP_DXFMT_Q8W8V8U8: return SVGA3D_Q8W8V8U8;
358 case SVGA3D_DEVCAP_DXFMT_CxV8U8: return SVGA3D_CxV8U8;
359 case SVGA3D_DEVCAP_DXFMT_X8L8V8U8: return SVGA3D_X8L8V8U8;
360 case SVGA3D_DEVCAP_DXFMT_A2W10V10U10: return SVGA3D_A2W10V10U10;
361 case SVGA3D_DEVCAP_DXFMT_ALPHA8: return SVGA3D_ALPHA8;
362 case SVGA3D_DEVCAP_DXFMT_R_S10E5: return SVGA3D_R_S10E5;
363 case SVGA3D_DEVCAP_DXFMT_R_S23E8: return SVGA3D_R_S23E8;
364 case SVGA3D_DEVCAP_DXFMT_RG_S10E5: return SVGA3D_RG_S10E5;
365 case SVGA3D_DEVCAP_DXFMT_RG_S23E8: return SVGA3D_RG_S23E8;
366 case SVGA3D_DEVCAP_DXFMT_BUFFER: return SVGA3D_BUFFER;
367 case SVGA3D_DEVCAP_DXFMT_Z_D24X8: return SVGA3D_Z_D24X8;
368 case SVGA3D_DEVCAP_DXFMT_V16U16: return SVGA3D_V16U16;
369 case SVGA3D_DEVCAP_DXFMT_G16R16: return SVGA3D_G16R16;
370 case SVGA3D_DEVCAP_DXFMT_A16B16G16R16: return SVGA3D_A16B16G16R16;
371 case SVGA3D_DEVCAP_DXFMT_UYVY: return SVGA3D_UYVY;
372 case SVGA3D_DEVCAP_DXFMT_YUY2: return SVGA3D_YUY2;
373 case SVGA3D_DEVCAP_DXFMT_NV12: return SVGA3D_NV12;
374 case SVGA3D_DEVCAP_DXFMT_AYUV: return SVGA3D_AYUV;
375 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS: return SVGA3D_R32G32B32A32_TYPELESS;
376 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT: return SVGA3D_R32G32B32A32_UINT;
377 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT: return SVGA3D_R32G32B32A32_SINT;
378 case SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS: return SVGA3D_R32G32B32_TYPELESS;
379 case SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT: return SVGA3D_R32G32B32_FLOAT;
380 case SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT: return SVGA3D_R32G32B32_UINT;
381 case SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT: return SVGA3D_R32G32B32_SINT;
382 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS: return SVGA3D_R16G16B16A16_TYPELESS;
383 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT: return SVGA3D_R16G16B16A16_UINT;
384 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM: return SVGA3D_R16G16B16A16_SNORM;
385 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT: return SVGA3D_R16G16B16A16_SINT;
386 case SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS: return SVGA3D_R32G32_TYPELESS;
387 case SVGA3D_DEVCAP_DXFMT_R32G32_UINT: return SVGA3D_R32G32_UINT;
388 case SVGA3D_DEVCAP_DXFMT_R32G32_SINT: return SVGA3D_R32G32_SINT;
389 case SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS: return SVGA3D_R32G8X24_TYPELESS;
390 case SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT: return SVGA3D_D32_FLOAT_S8X24_UINT;
391 case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS: return SVGA3D_R32_FLOAT_X8X24;
392 case SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT: return SVGA3D_X32_G8X24_UINT;
393 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS: return SVGA3D_R10G10B10A2_TYPELESS;
394 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT: return SVGA3D_R10G10B10A2_UINT;
395 case SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT: return SVGA3D_R11G11B10_FLOAT;
396 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS: return SVGA3D_R8G8B8A8_TYPELESS;
397 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM: return SVGA3D_R8G8B8A8_UNORM;
398 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB: return SVGA3D_R8G8B8A8_UNORM_SRGB;
399 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT: return SVGA3D_R8G8B8A8_UINT;
400 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT: return SVGA3D_R8G8B8A8_SINT;
401 case SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS: return SVGA3D_R16G16_TYPELESS;
402 case SVGA3D_DEVCAP_DXFMT_R16G16_UINT: return SVGA3D_R16G16_UINT;
403 case SVGA3D_DEVCAP_DXFMT_R16G16_SINT: return SVGA3D_R16G16_SINT;
404 case SVGA3D_DEVCAP_DXFMT_R32_TYPELESS: return SVGA3D_R32_TYPELESS;
405 case SVGA3D_DEVCAP_DXFMT_D32_FLOAT: return SVGA3D_D32_FLOAT;
406 case SVGA3D_DEVCAP_DXFMT_R32_UINT: return SVGA3D_R32_UINT;
407 case SVGA3D_DEVCAP_DXFMT_R32_SINT: return SVGA3D_R32_SINT;
408 case SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS: return SVGA3D_R24G8_TYPELESS;
409 case SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT: return SVGA3D_D24_UNORM_S8_UINT;
410 case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS: return SVGA3D_R24_UNORM_X8;
411 case SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT: return SVGA3D_X24_G8_UINT;
412 case SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS: return SVGA3D_R8G8_TYPELESS;
413 case SVGA3D_DEVCAP_DXFMT_R8G8_UNORM: return SVGA3D_R8G8_UNORM;
414 case SVGA3D_DEVCAP_DXFMT_R8G8_UINT: return SVGA3D_R8G8_UINT;
415 case SVGA3D_DEVCAP_DXFMT_R8G8_SINT: return SVGA3D_R8G8_SINT;
416 case SVGA3D_DEVCAP_DXFMT_R16_TYPELESS: return SVGA3D_R16_TYPELESS;
417 case SVGA3D_DEVCAP_DXFMT_R16_UNORM: return SVGA3D_R16_UNORM;
418 case SVGA3D_DEVCAP_DXFMT_R16_UINT: return SVGA3D_R16_UINT;
419 case SVGA3D_DEVCAP_DXFMT_R16_SNORM: return SVGA3D_R16_SNORM;
420 case SVGA3D_DEVCAP_DXFMT_R16_SINT: return SVGA3D_R16_SINT;
421 case SVGA3D_DEVCAP_DXFMT_R8_TYPELESS: return SVGA3D_R8_TYPELESS;
422 case SVGA3D_DEVCAP_DXFMT_R8_UNORM: return SVGA3D_R8_UNORM;
423 case SVGA3D_DEVCAP_DXFMT_R8_UINT: return SVGA3D_R8_UINT;
424 case SVGA3D_DEVCAP_DXFMT_R8_SNORM: return SVGA3D_R8_SNORM;
425 case SVGA3D_DEVCAP_DXFMT_R8_SINT: return SVGA3D_R8_SINT;
426 case SVGA3D_DEVCAP_DXFMT_P8: return SVGA3D_P8;
427 case SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP: return SVGA3D_R9G9B9E5_SHAREDEXP;
428 case SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM: return SVGA3D_R8G8_B8G8_UNORM;
429 case SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM: return SVGA3D_G8R8_G8B8_UNORM;
430 case SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS: return SVGA3D_BC1_TYPELESS;
431 case SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB: return SVGA3D_BC1_UNORM_SRGB;
432 case SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS: return SVGA3D_BC2_TYPELESS;
433 case SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB: return SVGA3D_BC2_UNORM_SRGB;
434 case SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS: return SVGA3D_BC3_TYPELESS;
435 case SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB: return SVGA3D_BC3_UNORM_SRGB;
436 case SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS: return SVGA3D_BC4_TYPELESS;
437 case SVGA3D_DEVCAP_DXFMT_ATI1: return SVGA3D_ATI1;
438 case SVGA3D_DEVCAP_DXFMT_BC4_SNORM: return SVGA3D_BC4_SNORM;
439 case SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS: return SVGA3D_BC5_TYPELESS;
440 case SVGA3D_DEVCAP_DXFMT_ATI2: return SVGA3D_ATI2;
441 case SVGA3D_DEVCAP_DXFMT_BC5_SNORM: return SVGA3D_BC5_SNORM;
442 case SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM: return SVGA3D_R10G10B10_XR_BIAS_A2_UNORM;
443 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS: return SVGA3D_B8G8R8A8_TYPELESS;
444 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB: return SVGA3D_B8G8R8A8_UNORM_SRGB;
445 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS: return SVGA3D_B8G8R8X8_TYPELESS;
446 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB: return SVGA3D_B8G8R8X8_UNORM_SRGB;
447 case SVGA3D_DEVCAP_DXFMT_Z_DF16: return SVGA3D_Z_DF16;
448 case SVGA3D_DEVCAP_DXFMT_Z_DF24: return SVGA3D_Z_DF24;
449 case SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT: return SVGA3D_Z_D24S8_INT;
450 case SVGA3D_DEVCAP_DXFMT_YV12: return SVGA3D_YV12;
451 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT: return SVGA3D_R32G32B32A32_FLOAT;
452 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT: return SVGA3D_R16G16B16A16_FLOAT;
453 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM: return SVGA3D_R16G16B16A16_UNORM;
454 case SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT: return SVGA3D_R32G32_FLOAT;
455 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM: return SVGA3D_R10G10B10A2_UNORM;
456 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM: return SVGA3D_R8G8B8A8_SNORM;
457 case SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT: return SVGA3D_R16G16_FLOAT;
458 case SVGA3D_DEVCAP_DXFMT_R16G16_UNORM: return SVGA3D_R16G16_UNORM;
459 case SVGA3D_DEVCAP_DXFMT_R16G16_SNORM: return SVGA3D_R16G16_SNORM;
460 case SVGA3D_DEVCAP_DXFMT_R32_FLOAT: return SVGA3D_R32_FLOAT;
461 case SVGA3D_DEVCAP_DXFMT_R8G8_SNORM: return SVGA3D_R8G8_SNORM;
462 case SVGA3D_DEVCAP_DXFMT_R16_FLOAT: return SVGA3D_R16_FLOAT;
463 case SVGA3D_DEVCAP_DXFMT_D16_UNORM: return SVGA3D_D16_UNORM;
464 case SVGA3D_DEVCAP_DXFMT_A8_UNORM: return SVGA3D_A8_UNORM;
465 case SVGA3D_DEVCAP_DXFMT_BC1_UNORM: return SVGA3D_BC1_UNORM;
466 case SVGA3D_DEVCAP_DXFMT_BC2_UNORM: return SVGA3D_BC2_UNORM;
467 case SVGA3D_DEVCAP_DXFMT_BC3_UNORM: return SVGA3D_BC3_UNORM;
468 case SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM: return SVGA3D_B5G6R5_UNORM;
469 case SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM: return SVGA3D_B5G5R5A1_UNORM;
470 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM: return SVGA3D_B8G8R8A8_UNORM;
471 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM: return SVGA3D_B8G8R8X8_UNORM;
472 case SVGA3D_DEVCAP_DXFMT_BC4_UNORM: return SVGA3D_BC4_UNORM;
473 case SVGA3D_DEVCAP_DXFMT_BC5_UNORM: return SVGA3D_BC5_UNORM;
474 default:
475 AssertFailed();
476 break;
477 }
478 return SVGA3D_FORMAT_INVALID;
479}
480
481
482static int vmsvgaDXCheckFormatSupportPreDX(PVMSVGA3DSTATE pState, SVGA3dSurfaceFormat enmFormat, uint32_t *pu32DevCap)
483{
484 int rc = VINF_SUCCESS;
485
486 *pu32DevCap = 0;
487
488 DXGI_FORMAT const dxgiFormat = vmsvgaDXSurfaceFormat2Dxgi(enmFormat);
489 if (dxgiFormat != DXGI_FORMAT_UNKNOWN)
490 {
491 RT_NOREF(pState);
492 /** @todo Implement */
493 }
494 else
495 rc = VERR_NOT_SUPPORTED;
496 return rc;
497}
498
499static int vmsvgaDXCheckFormatSupport(PVMSVGA3DSTATE pState, SVGA3dSurfaceFormat enmFormat, uint32_t *pu32DevCap)
500{
501 int rc = VINF_SUCCESS;
502
503 *pu32DevCap = 0;
504
505 DXGI_FORMAT const dxgiFormat = vmsvgaDXSurfaceFormat2Dxgi(enmFormat);
506 if (dxgiFormat != DXGI_FORMAT_UNKNOWN)
507 {
508 ID3D11Device *pDevice = pState->pBackend->pDevice;
509 UINT FormatSupport = 0;
510 HRESULT hr = pDevice->CheckFormatSupport(dxgiFormat, &FormatSupport);
511 if (SUCCEEDED(hr))
512 {
513 *pu32DevCap |= SVGA3D_DXFMT_SUPPORTED;
514
515 if (FormatSupport & D3D11_FORMAT_SUPPORT_SHADER_SAMPLE)
516 *pu32DevCap |= SVGA3D_DXFMT_SHADER_SAMPLE;
517
518 if (FormatSupport & D3D11_FORMAT_SUPPORT_RENDER_TARGET)
519 *pu32DevCap |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
520
521 if (FormatSupport & D3D11_FORMAT_SUPPORT_DEPTH_STENCIL)
522 *pu32DevCap |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
523
524 if (FormatSupport & D3D11_FORMAT_SUPPORT_BLENDABLE)
525 *pu32DevCap |= SVGA3D_DXFMT_BLENDABLE;
526
527 if (FormatSupport & D3D11_FORMAT_SUPPORT_MIP)
528 *pu32DevCap |= SVGA3D_DXFMT_MIPS;
529
530 if (FormatSupport & D3D11_FORMAT_SUPPORT_TEXTURECUBE)
531 *pu32DevCap |= SVGA3D_DXFMT_ARRAY;
532
533 if (FormatSupport & D3D11_FORMAT_SUPPORT_TEXTURE3D)
534 *pu32DevCap |= SVGA3D_DXFMT_VOLUME;
535
536 if (FormatSupport & D3D11_FORMAT_SUPPORT_IA_VERTEX_BUFFER)
537 *pu32DevCap |= SVGA3D_DXFMT_DX_VERTEX_BUFFER;
538
539 UINT NumQualityLevels;
540 hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 2, &NumQualityLevels);
541 if (SUCCEEDED(hr) && NumQualityLevels != 0)
542 *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_2;
543
544 hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 4, &NumQualityLevels);
545 if (SUCCEEDED(hr) && NumQualityLevels != 0)
546 *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_4;
547
548 hr = pDevice->CheckMultisampleQualityLevels(dxgiFormat, 8, &NumQualityLevels);
549 if (SUCCEEDED(hr) && NumQualityLevels != 0)
550 *pu32DevCap |= SVGADX_DXFMT_MULTISAMPLE_8;
551 }
552 else
553 rc = VERR_NOT_SUPPORTED;
554 }
555 else
556 rc = VERR_NOT_SUPPORTED;
557 return rc;
558}
559
560
561int vmsvga3dInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
562{
563 RT_NOREF(pDevIns, pThis);
564
565 PVMSVGA3DSTATE pState = (PVMSVGA3DSTATE)RTMemAllocZ(sizeof(VMSVGA3DSTATE));
566 AssertReturn(pState, VERR_NO_MEMORY);
567 pThisCC->svga.p3dState = pState;
568
569 PVMSVGA3DBACKEND pBackend = (PVMSVGA3DBACKEND)RTMemAllocZ(sizeof(VMSVGA3DBACKEND));
570 AssertReturn(pBackend, VERR_NO_MEMORY);
571 pState->pBackend = pBackend;
572
573 int rc = RTLdrLoadSystem("d3d11", /* fNoUnload = */ true, &pBackend->hD3D11);
574 AssertRC(rc);
575 if (RT_SUCCESS(rc))
576 {
577 rc = RTLdrGetSymbol(pBackend->hD3D11, "D3D11CreateDevice", (void **)&pBackend->pfnD3D11CreateDevice);
578 AssertRC(rc);
579 }
580
581 return rc;
582}
583
584
585int vmsvga3dPowerOn(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC)
586{
587 RT_NOREF(pDevIns, pThis);
588
589 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
590 AssertReturn(pState, VERR_INVALID_STATE);
591
592 PVMSVGA3DBACKEND pBackend = pState->pBackend;
593 AssertReturn(pBackend, VERR_INVALID_STATE);
594
595 int rc = VINF_SUCCESS;
596
597 IDXGIAdapter *pAdapter = NULL; /* Default adapter. */
598 static D3D_FEATURE_LEVEL const s_aFeatureLevels[] =
599 {
600 /// @todo Requires a Windows 8+ _SDKS: D3D_FEATURE_LEVEL_11_1,
601 D3D_FEATURE_LEVEL_11_0
602 };
603 UINT Flags = D3D11_CREATE_DEVICE_BGRA_SUPPORT;
604#ifdef DEBUG
605 Flags |= D3D11_CREATE_DEVICE_DEBUG;
606#endif
607
608 HRESULT hr = pBackend->pfnD3D11CreateDevice(pAdapter,
609 D3D_DRIVER_TYPE_HARDWARE,
610 NULL,
611 Flags,
612 s_aFeatureLevels,
613 RT_ELEMENTS(s_aFeatureLevels),
614 D3D11_SDK_VERSION,
615 &pBackend->pDevice,
616 &pBackend->FeatureLevel,
617 &pBackend->pImmediateContext);
618 if (SUCCEEDED(hr))
619 {
620 LogRel(("VMSVGA: Feature level %#x\n", pBackend->FeatureLevel));
621
622 IDXGIDevice *pDxgiDevice = 0;
623 hr = pBackend->pDevice->QueryInterface(__uuidof(IDXGIDevice), (void**)&pDxgiDevice);
624 if (SUCCEEDED(hr))
625 {
626 IDXGIAdapter *pDxgiAdapter = 0;
627 hr = pDxgiDevice->GetParent(__uuidof(IDXGIAdapter), (void**)&pDxgiAdapter);
628 if (SUCCEEDED(hr))
629 {
630 hr = pDxgiAdapter->GetParent(__uuidof(IDXGIFactory), (void**)&pBackend->pDxgiFactory);
631 D3D_RELEASE(pDxgiAdapter);
632 }
633
634 D3D_RELEASE(pDxgiDevice);
635 }
636 }
637
638 if (FAILED(hr))
639 rc = VERR_NOT_SUPPORTED;
640
641 return rc;
642}
643
644
645int vmsvga3dTerminate(PVGASTATECC pThisCC)
646{
647 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
648 AssertReturn(pState, VERR_INVALID_STATE);
649
650 if (pState->pBackend)
651 {
652 vmsvga3dReset(pThisCC);
653
654 RTMemFree(pState->pBackend);
655 pState->pBackend = NULL;
656 }
657
658 return VINF_SUCCESS;
659}
660
661
662int vmsvga3dReset(PVGASTATECC pThisCC)
663{
664 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
665 AssertReturn(pState, VERR_INVALID_STATE);
666
667 PVMSVGA3DBACKEND pBackend = pState->pBackend;
668 if (pBackend)
669 {
670 D3D_RELEASE(pBackend->pDevice);
671 D3D_RELEASE(pBackend->pImmediateContext);
672 D3D_RELEASE(pBackend->pDxgiFactory);
673 }
674
675 return VINF_SUCCESS;
676}
677
678
679static int vmsvga3dDrvNotifyDefineScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
680{
681 /** @todo Such structures must be in VBoxVideo3D.h */
682 typedef struct VBOX3DNOTIFYDEFINESCREEN
683 {
684 VBOX3DNOTIFY Core;
685 uint32_t cWidth;
686 uint32_t cHeight;
687 int32_t xRoot;
688 int32_t yRoot;
689 uint32_t fPrimary;
690 uint32_t cDpi;
691 } VBOX3DNOTIFYDEFINESCREEN;
692
693 VBOX3DNOTIFYDEFINESCREEN n;
694 n.Core.enmNotification = VBOX3D_NOTIFY_TYPE_HW_SCREEN_CREATED;
695 n.Core.iDisplay = pScreen->idScreen;
696 n.Core.u32Reserved = 0;
697 n.Core.cbData = sizeof(n) - RT_UOFFSETOF(VBOX3DNOTIFY, au8Data);
698 RT_ZERO(n.Core.au8Data);
699 n.cWidth = pScreen->cWidth;
700 n.cHeight = pScreen->cHeight;
701 n.xRoot = pScreen->xOrigin;
702 n.yRoot = pScreen->yOrigin;
703 n.fPrimary = RT_BOOL(pScreen->fuScreen & SVGA_SCREEN_IS_PRIMARY);
704 n.cDpi = pScreen->cDpi;
705
706 return pThisCC->pDrv->pfn3DNotifyProcess(pThisCC->pDrv, &n.Core);
707}
708
709
710static int vmsvga3dDrvNotifyDestroyScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
711{
712 VBOX3DNOTIFY n;
713 n.enmNotification = VBOX3D_NOTIFY_TYPE_HW_SCREEN_DESTROYED;
714 n.iDisplay = pScreen->idScreen;
715 n.u32Reserved = 0;
716 n.cbData = sizeof(n) - RT_UOFFSETOF(VBOX3DNOTIFY, au8Data);
717 RT_ZERO(n.au8Data);
718
719 return pThisCC->pDrv->pfn3DNotifyProcess(pThisCC->pDrv, &n);
720}
721
722
723static int vmsvga3dDrvNotifyBindSurface(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, HANDLE hSharedSurface)
724{
725 VBOX3DNOTIFY n;
726 n.enmNotification = VBOX3D_NOTIFY_TYPE_HW_SCREEN_BIND_SURFACE;
727 n.iDisplay = pScreen->idScreen;
728 n.u32Reserved = 0;
729 n.cbData = sizeof(n) - RT_UOFFSETOF(VBOX3DNOTIFY, au8Data);
730 *(uint64_t *)&n.au8Data[0] = (uint64_t)hSharedSurface;
731
732 return pThisCC->pDrv->pfn3DNotifyProcess(pThisCC->pDrv, &n);
733}
734
735
736static int vmsvga3dDrvNotifyUpdate(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen,
737 uint32_t x, uint32_t y, uint32_t w, uint32_t h)
738{
739 typedef struct VBOX3DNOTIFYUPDATE
740 {
741 VBOX3DNOTIFY Core;
742 uint32_t x;
743 uint32_t y;
744 uint32_t w;
745 uint32_t h;
746 } VBOX3DNOTIFYUPDATE;
747
748 VBOX3DNOTIFYUPDATE n;
749 n.Core.enmNotification = VBOX3D_NOTIFY_TYPE_HW_SCREEN_UPDATE_END;
750 n.Core.iDisplay = pScreen->idScreen;
751 n.Core.u32Reserved = 0;
752 n.Core.cbData = sizeof(n) - RT_UOFFSETOF(VBOX3DNOTIFY, au8Data);
753 RT_ZERO(n.Core.au8Data);
754 n.x = x;
755 n.y = y;
756 n.w = w;
757 n.h = h;
758
759 return pThisCC->pDrv->pfn3DNotifyProcess(pThisCC->pDrv, &n.Core);
760}
761
762static int vmsvga3dHwScreenCreate(PVMSVGA3DSTATE pState, uint32_t cWidth, uint32_t cHeight, VMSVGAHWSCREEN *p)
763{
764 PVMSVGA3DBACKEND pBackend = pState->pBackend;
765
766 D3D11_TEXTURE2D_DESC td;
767 RT_ZERO(td);
768 td.Width = cWidth;
769 td.Height = cHeight;
770 td.MipLevels = 1;
771 td.ArraySize = 1;
772 td.Format = DXGI_FORMAT_B8G8R8A8_UNORM;
773 td.SampleDesc.Count = 1;
774 td.SampleDesc.Quality = 0;
775 td.Usage = D3D11_USAGE_DEFAULT;
776 td.BindFlags = D3D11_BIND_RENDER_TARGET | D3D11_BIND_SHADER_RESOURCE;
777 td.CPUAccessFlags = 0;
778 td.MiscFlags = D3D11_RESOURCE_MISC_SHARED_KEYEDMUTEX;
779
780 HRESULT hr = pBackend->pDevice->CreateTexture2D(&td, 0, &p->pTexture);
781 if (SUCCEEDED(hr))
782 {
783 /* Get the shared handle. */
784 hr = p->pTexture->QueryInterface(__uuidof(IDXGIResource), (void**)&p->pDxgiResource);
785 if (SUCCEEDED(hr))
786 {
787 hr = p->pDxgiResource->GetSharedHandle(&p->SharedHandle);
788 if (SUCCEEDED(hr))
789 hr = p->pTexture->QueryInterface(__uuidof(IDXGIKeyedMutex), (void**)&p->pDXGIKeyedMutex);
790 }
791 }
792
793 if (SUCCEEDED(hr))
794 return VINF_SUCCESS;
795
796 AssertFailed();
797 return VERR_NOT_SUPPORTED;
798}
799
800
801static void vmsvga3dHwScreenDestroy(PVMSVGA3DSTATE pState, VMSVGAHWSCREEN *p)
802{
803 RT_NOREF(pState);
804 D3D_RELEASE(p->pDXGIKeyedMutex);
805 D3D_RELEASE(p->pDxgiResource);
806 D3D_RELEASE(p->pTexture);
807 p->SharedHandle = 0;
808 p->sidScreenTarget = SVGA_ID_INVALID;
809}
810
811
812int vmsvga3dBackDefineScreen(PVGASTATE pThis, PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
813{
814 RT_NOREF(pThis, pThisCC, pScreen);
815
816 LogRel4(("VMSVGA: vmsvga3dBackDefineScreen: screen %u\n", pScreen->idScreen));
817
818 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
819 AssertReturn(pState, VERR_INVALID_STATE);
820
821 PVMSVGA3DBACKEND pBackend = pState->pBackend;
822 AssertReturn(pBackend, VERR_INVALID_STATE);
823
824 Assert(pScreen->pHwScreen == NULL);
825
826 VMSVGAHWSCREEN *p = (VMSVGAHWSCREEN *)RTMemAllocZ(sizeof(VMSVGAHWSCREEN));
827 AssertPtrReturn(p, VERR_NO_MEMORY);
828
829 p->sidScreenTarget = SVGA_ID_INVALID;
830
831 int rc = vmsvga3dDrvNotifyDefineScreen(pThisCC, pScreen);
832 if (RT_SUCCESS(rc))
833 {
834 /* The frontend supports the screen. Create the actual resource. */
835 rc = vmsvga3dHwScreenCreate(pState, pScreen->cWidth, pScreen->cHeight, p);
836 if (RT_SUCCESS(rc))
837 LogRel4(("VMSVGA: vmsvga3dBackDefineScreen: created\n"));
838 }
839
840 if (RT_SUCCESS(rc))
841 {
842 LogRel(("VMSVGA: Using HW accelerated screen %u\n", pScreen->idScreen));
843 pScreen->pHwScreen = p;
844 }
845 else
846 {
847 LogRel4(("VMSVGA: vmsvga3dBackDefineScreen: %Rrc\n", rc));
848 vmsvga3dHwScreenDestroy(pState, p);
849 RTMemFree(p);
850 }
851
852 return rc;
853}
854
855
856int vmsvga3dBackDestroyScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen)
857{
858 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
859 AssertReturn(pState, VERR_INVALID_STATE);
860
861 vmsvga3dDrvNotifyDestroyScreen(pThisCC, pScreen);
862
863 if (pScreen->pHwScreen)
864 {
865 vmsvga3dHwScreenDestroy(pState, pScreen->pHwScreen);
866 RTMemFree(pScreen->pHwScreen);
867 pScreen->pHwScreen = NULL;
868 }
869
870 return VINF_SUCCESS;
871}
872
873
874int vmsvga3dBackSurfaceBlitToScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen,
875 SVGASignedRect destRect, SVGA3dSurfaceImageId srcImage,
876 SVGASignedRect srcRect, uint32_t cRects, SVGASignedRect *paRects)
877{
878 RT_NOREF(pThisCC, pScreen, destRect, srcImage, srcRect, cRects, paRects);
879
880 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
881 AssertReturn(pState, VERR_INVALID_STATE);
882
883 PVMSVGA3DBACKEND pBackend = pState->pBackend;
884 AssertReturn(pBackend, VERR_INVALID_STATE);
885
886 VMSVGAHWSCREEN *p = pScreen->pHwScreen;
887 AssertReturn(p, VERR_NOT_SUPPORTED);
888
889 PVMSVGA3DSURFACE pSurface;
890 int rc = vmsvga3dSurfaceFromSid(pState, srcImage.sid, &pSurface);
891 AssertRCReturn(rc, rc);
892
893 /** @todo Implement. */
894 AssertFailed();
895 return VERR_NOT_IMPLEMENTED;
896}
897
898
899int vmsvga3dSurfaceMap(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImage, SVGA3dBox const *pBox,
900 VMSVGA3D_SURFACE_MAP enmMapType, VMSVGA3D_MAPPED_SURFACE *pMap)
901{
902 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
903 AssertReturn(pState, VERR_INVALID_STATE);
904
905 PVMSVGA3DBACKEND pBackend = pState->pBackend;
906 AssertReturn(pBackend, VERR_INVALID_STATE);
907 AssertReturn(pBackend->pImmediateContext, VERR_INVALID_STATE);
908
909 PVMSVGA3DSURFACE pSurface;
910 int rc = vmsvga3dSurfaceFromSid(pState, pImage->sid, &pSurface);
911 AssertRCReturn(rc, rc);
912
913 PVMSVGA3DBACKENDSURFACE pBackendSurface = pSurface->pBackendSurface;
914 if (!pBackendSurface)
915 return VERR_INVALID_PARAMETER;
916
917 SVGA3dBox clipBox;
918 if (pBox)
919 {
920 clipBox = *pBox;
921 vmsvgaR3ClipBox(&pSurface->paMipmapLevels[0].mipmapSize, &clipBox);
922 ASSERT_GUEST_RETURN(clipBox.w && clipBox.h && clipBox.d, VERR_INVALID_PARAMETER);
923 }
924 else
925 {
926 clipBox.x = 0;
927 clipBox.y = 0;
928 clipBox.z = 0;
929 clipBox.w = pSurface->paMipmapLevels[0].mipmapSize.width;
930 clipBox.h = pSurface->paMipmapLevels[0].mipmapSize.height;
931 clipBox.d = pSurface->paMipmapLevels[0].mipmapSize.depth;
932 }
933
934 /** @todo D3D11_MAP_WRITE does not work with D3D11_USAGE_DYNAMIC resources. Probably VMSVGA3D_SURFACE_MAP_WRITE is not necessary. */
935 D3D11_MAP d3d11MapType;
936 switch (enmMapType)
937 {
938 case VMSVGA3D_SURFACE_MAP_READ: d3d11MapType = D3D11_MAP_READ; break;
939 case VMSVGA3D_SURFACE_MAP_WRITE: d3d11MapType = D3D11_MAP_WRITE; break;
940 case VMSVGA3D_SURFACE_MAP_READ_WRITE: d3d11MapType = D3D11_MAP_READ_WRITE; break;
941 case VMSVGA3D_SURFACE_MAP_WRITE_DISCARD: d3d11MapType = D3D11_MAP_WRITE_DISCARD; break;
942 default:
943 AssertFailed();
944 return VERR_INVALID_PARAMETER;
945 }
946
947 D3D11_MAPPED_SUBRESOURCE mappedResource;
948 RT_ZERO(mappedResource);
949
950 if (pBackendSurface->enmResType == VMSVGA3D_RESTYPE_SCREEN_TARGET)
951 {
952 ID3D11Texture2D *pMappedTexture;
953 if (enmMapType == VMSVGA3D_SURFACE_MAP_READ)
954 {
955 pMappedTexture = pBackendSurface->u.ScreenTarget.pStagingTexture;
956
957 /* Copy the texture content to the staging texture. */
958 pBackend->pImmediateContext->CopyResource(pBackendSurface->u.ScreenTarget.pStagingTexture, pBackendSurface->u.ScreenTarget.pTexture);
959 }
960 else
961 pMappedTexture = pBackendSurface->u.ScreenTarget.pDynamicTexture;
962
963 UINT const Subresource = 0; /* Screen target surfaces have only one subresource. */
964 HRESULT hr = pBackend->pImmediateContext->Map(pMappedTexture, Subresource,
965 d3d11MapType, /* MapFlags = */ 0, &mappedResource);
966 if (SUCCEEDED(hr))
967 {
968 pMap->enmMapType = enmMapType;
969 pMap->box = clipBox;
970 pMap->cbPixel = pSurface->cbBlock;
971 pMap->cbRowPitch = mappedResource.RowPitch;
972 pMap->cbDepthPitch = mappedResource.DepthPitch;
973 pMap->pvData = (uint8_t *)mappedResource.pData
974 + pMap->box.x * pMap->cbPixel
975 + pMap->box.y * pMap->cbRowPitch
976 + pMap->box.z * pMap->cbDepthPitch;
977 }
978 else
979 rc = VERR_NOT_SUPPORTED;
980 }
981 else
982 {
983 // UINT D3D11CalcSubresource(UINT MipSlice, UINT ArraySlice, UINT MipLevels);
984 /** @todo Implement. */
985 AssertFailed();
986 rc = VERR_NOT_IMPLEMENTED;
987 }
988
989 return rc;
990}
991
992
993int vmsvga3dSurfaceUnmap(PVGASTATECC pThisCC, SVGA3dSurfaceImageId const *pImage, VMSVGA3D_MAPPED_SURFACE *pMap, bool fWritten)
994{
995 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
996 AssertReturn(pState, VERR_INVALID_STATE);
997
998 PVMSVGA3DBACKEND pBackend = pState->pBackend;
999 AssertReturn(pBackend, VERR_INVALID_STATE);
1000 AssertReturn(pBackend->pImmediateContext, VERR_INVALID_STATE);
1001
1002 PVMSVGA3DSURFACE pSurface;
1003 int rc = vmsvga3dSurfaceFromSid(pState, pImage->sid, &pSurface);
1004 AssertRCReturn(rc, rc);
1005
1006 /* The called should not use the function for system memory surfaces. */
1007 PVMSVGA3DBACKENDSURFACE pBackendSurface = pSurface->pBackendSurface;
1008 AssertReturn(pBackendSurface, VERR_INVALID_PARAMETER);
1009
1010 if (pBackendSurface->enmResType == VMSVGA3D_RESTYPE_SCREEN_TARGET)
1011 {
1012 ID3D11Texture2D *pMappedTexture;
1013 if (pMap->enmMapType == VMSVGA3D_SURFACE_MAP_READ)
1014 pMappedTexture = pBackendSurface->u.ScreenTarget.pStagingTexture;
1015 else
1016 pMappedTexture = pBackendSurface->u.ScreenTarget.pDynamicTexture;
1017
1018 UINT const Subresource = 0; /* Screen target surfaces have only one subresource. */
1019 pBackend->pImmediateContext->Unmap(pMappedTexture, Subresource);
1020
1021 if ( fWritten
1022 && ( pMap->enmMapType == VMSVGA3D_SURFACE_MAP_WRITE
1023 || pMap->enmMapType == VMSVGA3D_SURFACE_MAP_READ_WRITE
1024 || pMap->enmMapType == VMSVGA3D_SURFACE_MAP_WRITE_DISCARD))
1025 {
1026 ID3D11Resource *pDstResource = pBackendSurface->u.ScreenTarget.pTexture;
1027 UINT DstSubresource = Subresource;
1028 UINT DstX = pMap->box.x;
1029 UINT DstY = pMap->box.y;
1030 UINT DstZ = pMap->box.z;
1031 ID3D11Resource *pSrcResource = pBackendSurface->u.ScreenTarget.pDynamicTexture;
1032 UINT SrcSubresource = Subresource;
1033 D3D11_BOX SrcBox;
1034 SrcBox.left = pMap->box.x;
1035 SrcBox.top = pMap->box.y;
1036 SrcBox.front = pMap->box.z;
1037 SrcBox.right = pMap->box.x + pMap->box.w;
1038 SrcBox.bottom = pMap->box.y + pMap->box.h;
1039 SrcBox.back = pMap->box.z + pMap->box.d;
1040 pBackend->pImmediateContext->CopySubresourceRegion(pDstResource, DstSubresource, DstX, DstY, DstZ,
1041 pSrcResource, SrcSubresource, &SrcBox);
1042 }
1043 }
1044 else
1045 {
1046 AssertFailed();
1047 rc = VERR_NOT_IMPLEMENTED;
1048 }
1049
1050 return rc;
1051}
1052
1053
1054int vmsvga3dBackSurfaceCreateScreenTarget(PVMSVGA3DSTATE pState, PVMSVGA3DSURFACE pSurface)
1055{
1056 PVMSVGA3DBACKEND pBackend = pState->pBackend;
1057 AssertReturn(pBackend, VERR_INVALID_STATE);
1058 AssertReturn(pBackend->pDevice, VERR_INVALID_STATE);
1059
1060 /* Surface must have SCREEN_TARGET flag. */
1061 ASSERT_GUEST_RETURN(RT_BOOL(pSurface->surfaceFlags & SVGA3D_SURFACE_SCREENTARGET), VERR_INVALID_PARAMETER);
1062
1063 if (VMSVGA3DSURFACE_HAS_HW_SURFACE(pSurface))
1064 {
1065 AssertFailed(); /* Should the function not be used like that? */
1066 vmsvga3dBackSurfaceDestroy(pState, pSurface);
1067 }
1068
1069 PVMSVGA3DBACKENDSURFACE pBackendSurface = (PVMSVGA3DBACKENDSURFACE)RTMemAllocZ(sizeof(VMSVGA3DBACKENDSURFACE));
1070 AssertPtrReturn(pBackendSurface, VERR_NO_MEMORY);
1071
1072 D3D11_TEXTURE2D_DESC td;
1073 RT_ZERO(td);
1074 td.Width = pSurface->paMipmapLevels[0].mipmapSize.width;
1075 td.Height = pSurface->paMipmapLevels[0].mipmapSize.height;
1076 Assert(pSurface->cLevels == 1);
1077 td.MipLevels = 1;
1078 td.ArraySize = 1;
1079 td.Format = vmsvgaDXScreenTargetFormat2Dxgi(pSurface->format); // DXGI_FORMAT_B8G8R8A8_UNORM;
1080 td.SampleDesc.Count = 1;
1081 td.SampleDesc.Quality = 0;
1082 td.Usage = D3D11_USAGE_DEFAULT;
1083 td.BindFlags = D3D11_BIND_RENDER_TARGET | D3D11_BIND_SHADER_RESOURCE;
1084 td.CPUAccessFlags = 0;
1085 td.MiscFlags = 0;
1086
1087 HRESULT hr = pBackend->pDevice->CreateTexture2D(&td, 0, &pBackendSurface->u.ScreenTarget.pTexture);
1088
1089 if (SUCCEEDED(hr))
1090 {
1091 /* Map-able texture. */
1092 td.Usage = D3D11_USAGE_DYNAMIC;
1093 td.BindFlags = D3D11_BIND_SHADER_RESOURCE; /* Have to specify a supported flag, otherwise E_INVALIDARG will be returned. */
1094 td.CPUAccessFlags = D3D11_CPU_ACCESS_WRITE;
1095 td.MiscFlags = 0;
1096 hr = pBackend->pDevice->CreateTexture2D(&td, 0, &pBackendSurface->u.ScreenTarget.pDynamicTexture);
1097 }
1098
1099 if (SUCCEEDED(hr))
1100 {
1101 /* Staging texture. */
1102 td.Usage = D3D11_USAGE_STAGING;
1103 td.BindFlags = 0; /* No flags allowed. */
1104 td.CPUAccessFlags = D3D11_CPU_ACCESS_READ;
1105 td.MiscFlags = 0;
1106 hr = pBackend->pDevice->CreateTexture2D(&td, 0, &pBackendSurface->u.ScreenTarget.pStagingTexture);
1107 }
1108
1109 if (SUCCEEDED(hr))
1110 {
1111 /*
1112 * Success.
1113 */
1114 pBackendSurface->enmResType = VMSVGA3D_RESTYPE_SCREEN_TARGET;
1115 pSurface->pBackendSurface = pBackendSurface;
1116 return VINF_SUCCESS;
1117 }
1118
1119 /* Failure. */
1120 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pStagingTexture);
1121 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pDynamicTexture);
1122 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pTexture);
1123 RTMemFree(pBackendSurface);
1124 return VERR_NO_MEMORY;
1125}
1126
1127
1128int vmsvga3dScreenTargetBind(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, uint32_t sid)
1129{
1130 int rc = VINF_SUCCESS;
1131
1132 PVMSVGA3DSURFACE pSurface;
1133 if (sid != SVGA_ID_INVALID)
1134 {
1135 /* Create the surface if does not yet exist. */
1136 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1137 AssertReturn(pState, VERR_INVALID_STATE);
1138
1139 rc = vmsvga3dSurfaceFromSid(pState, sid, &pSurface);
1140 AssertRCReturn(rc, rc);
1141
1142 if (!VMSVGA3DSURFACE_HAS_HW_SURFACE(pSurface))
1143 {
1144 /* Create the actual texture. */
1145 rc = vmsvga3dBackSurfaceCreateScreenTarget(pState, pSurface);
1146 AssertRCReturn(rc, rc);
1147 }
1148 }
1149 else
1150 pSurface = NULL;
1151
1152 /* Notify the HW accelerated screen if it is used. */
1153 VMSVGAHWSCREEN *pHwScreen = pScreen->pHwScreen;
1154 if (!pHwScreen)
1155 return VINF_SUCCESS;
1156
1157 /* Same surface -> do nothing. */
1158 if (pHwScreen->sidScreenTarget == sid)
1159 return VINF_SUCCESS;
1160
1161 if (sid != SVGA_ID_INVALID)
1162 {
1163 AssertReturn( pSurface->pBackendSurface
1164 && pSurface->pBackendSurface->enmResType == VMSVGA3D_RESTYPE_SCREEN_TARGET, VERR_INVALID_PARAMETER);
1165
1166 HANDLE const hSharedSurface = pHwScreen->SharedHandle;
1167 rc = vmsvga3dDrvNotifyBindSurface(pThisCC, pScreen, hSharedSurface);
1168 }
1169
1170 if (RT_SUCCESS(rc))
1171 {
1172 pHwScreen->sidScreenTarget = sid;
1173 }
1174
1175 return rc;
1176}
1177
1178
1179int vmsvga3dScreenTargetUpdate(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, SVGA3dRect const *pRect)
1180{
1181 VMSVGAHWSCREEN *pHwScreen = pScreen->pHwScreen;
1182 AssertReturn(pHwScreen, VERR_NOT_SUPPORTED);
1183
1184 if (pHwScreen->sidScreenTarget == SVGA_ID_INVALID)
1185 return VINF_SUCCESS; /* No surface bound. */
1186
1187 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1188 AssertReturn(pState, VERR_INVALID_STATE);
1189
1190 PVMSVGA3DBACKEND pBackend = pState->pBackend;
1191 AssertReturn(pBackend, VERR_INVALID_STATE);
1192
1193 PVMSVGA3DSURFACE pSurface;
1194 int rc = vmsvga3dSurfaceFromSid(pState, pHwScreen->sidScreenTarget, &pSurface);
1195 AssertRCReturn(rc, rc);
1196
1197 PVMSVGA3DBACKENDSURFACE pBackendSurface = pSurface->pBackendSurface;
1198 AssertReturn(pBackendSurface, VERR_INVALID_PARAMETER);
1199
1200 SVGA3dRect boundRect;
1201 boundRect.x = 0;
1202 boundRect.y = 0;
1203 boundRect.w = pSurface->paMipmapLevels[0].mipmapSize.width;
1204 boundRect.h = pSurface->paMipmapLevels[0].mipmapSize.height;
1205 SVGA3dRect clipRect = *pRect;
1206 vmsvgaR3Clip3dRect(&boundRect, &clipRect);
1207 ASSERT_GUEST_RETURN(clipRect.w && clipRect.h, VERR_INVALID_PARAMETER);
1208
1209 /* Copy the screen texture to the shared surface. */
1210 DWORD result = pHwScreen->pDXGIKeyedMutex->AcquireSync(0, 10000);
1211 if (result == WAIT_OBJECT_0)
1212 {
1213 ID3D11Query *pQuery = 0;
1214 D3D11_QUERY_DESC qd;
1215 RT_ZERO(qd);
1216 qd.Query = D3D11_QUERY_EVENT;
1217 HRESULT hr2 = pBackend->pDevice->CreateQuery(&qd, &pQuery);
1218 Assert(hr2 == S_OK); RT_NOREF(hr2);
1219
1220 pBackend->pImmediateContext->CopyResource(pHwScreen->pTexture, pBackendSurface->u.ScreenTarget.pTexture);
1221
1222 pBackend->pImmediateContext->Flush();
1223
1224 pBackend->pImmediateContext->End(pQuery);
1225
1226 BOOL queryData;
1227 while (pBackend->pImmediateContext->GetData(pQuery, &queryData, sizeof(queryData), 0) != S_OK)
1228 {
1229 RTThreadYield();
1230 }
1231 D3D_RELEASE(pQuery);
1232
1233 result = pHwScreen->pDXGIKeyedMutex->ReleaseSync(1);
1234 }
1235 else
1236 AssertFailed();
1237
1238 rc = vmsvga3dDrvNotifyUpdate(pThisCC, pScreen, pRect->x, pRect->y, pRect->w, pRect->h);
1239 return rc;
1240}
1241
1242
1243void vmsvga3dUpdateHostScreenViewport(PVGASTATECC pThisCC, uint32_t idScreen, VMSVGAVIEWPORT const *pOldViewport)
1244{
1245 RT_NOREF(pThisCC, idScreen, pOldViewport);
1246 /** @todo Scroll the screen content without requiring the guest to redraw. */
1247}
1248
1249
1250int vmsvga3dQueryCaps(PVGASTATECC pThisCC, SVGA3dDevCapIndex idx3dCaps, uint32_t *pu32Val)
1251{
1252 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1253 AssertReturn(pState, VERR_INVALID_STATE);
1254
1255 int rc = VINF_SUCCESS;
1256
1257 *pu32Val = 0;
1258
1259 /* Most values are taken from:
1260 * https://docs.microsoft.com/en-us/windows/win32/direct3d11/overviews-direct3d-11-devices-downlevel-intro
1261 *
1262 * Shader values are from
1263 * https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-models
1264 */
1265
1266 switch (idx3dCaps)
1267 {
1268 case SVGA3D_DEVCAP_3D:
1269 *pu32Val = 1;
1270 break;
1271
1272 case SVGA3D_DEVCAP_MAX_LIGHTS:
1273 *pu32Val = SVGA3D_NUM_LIGHTS; /* VGPU9. Not applicable to DX11. */
1274 break;
1275
1276 case SVGA3D_DEVCAP_MAX_TEXTURES:
1277 *pu32Val = SVGA3D_NUM_TEXTURE_UNITS; /* VGPU9. Not applicable to DX11. */
1278 break;
1279
1280 case SVGA3D_DEVCAP_MAX_CLIP_PLANES:
1281 *pu32Val = SVGA3D_NUM_CLIPPLANES;
1282 break;
1283
1284 case SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
1285 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1286 *pu32Val = SVGA3DVSVERSION_40;
1287 else
1288 *pu32Val = SVGA3DVSVERSION_30;
1289 break;
1290
1291 case SVGA3D_DEVCAP_VERTEX_SHADER:
1292 *pu32Val = 1;
1293 break;
1294
1295 case SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
1296 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1297 *pu32Val = SVGA3DPSVERSION_40;
1298 else
1299 *pu32Val = SVGA3DPSVERSION_30;
1300 break;
1301
1302 case SVGA3D_DEVCAP_FRAGMENT_SHADER:
1303 *pu32Val = 1;
1304 break;
1305
1306 case SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
1307 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1308 *pu32Val = 8;
1309 else
1310 *pu32Val = 4;
1311 break;
1312
1313 case SVGA3D_DEVCAP_S23E8_TEXTURES:
1314 case SVGA3D_DEVCAP_S10E5_TEXTURES:
1315 /* Must be obsolete by now; surface format caps specify the same thing. */
1316 break;
1317
1318 case SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
1319 /* Obsolete */
1320 break;
1321
1322 /*
1323 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
1324 * return TRUE. Even on physical hardware that does not support
1325 * these formats natively, the SVGA3D device will provide an emulation
1326 * which should be invisible to the guest OS.
1327 */
1328 case SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
1329 case SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
1330 case SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
1331 *pu32Val = 1;
1332 break;
1333
1334 case SVGA3D_DEVCAP_QUERY_TYPES:
1335 /* Obsolete */
1336 break;
1337
1338 case SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
1339 /* Obsolete */
1340 break;
1341
1342 case SVGA3D_DEVCAP_MAX_POINT_SIZE:
1343 AssertCompile(sizeof(uint32_t) == sizeof(float));
1344 *(float *)pu32Val = 256.0f; /* VGPU9. Not applicable to DX11. */
1345 break;
1346
1347 case SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
1348 /* Obsolete */
1349 break;
1350
1351 case SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
1352 case SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
1353 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_11_0)
1354 *pu32Val = 16384;
1355 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1356 *pu32Val = 8192;
1357 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_3)
1358 *pu32Val = 4096;
1359 else
1360 *pu32Val = 2048;
1361 break;
1362
1363 case SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
1364 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1365 *pu32Val = 2048;
1366 else
1367 *pu32Val = 256;
1368 break;
1369
1370 case SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
1371 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_11_0)
1372 *pu32Val = 16384;
1373 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_3)
1374 *pu32Val = 8192;
1375 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_2)
1376 *pu32Val = 2048;
1377 else
1378 *pu32Val = 128;
1379 break;
1380
1381 case SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
1382 /* Obsolete */
1383 break;
1384
1385 case SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
1386 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_2)
1387 *pu32Val = D3D11_REQ_MAXANISOTROPY;
1388 else
1389 *pu32Val = 2; // D3D_FL9_1_DEFAULT_MAX_ANISOTROPY;
1390 break;
1391
1392 case SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
1393 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1394 *pu32Val = UINT32_MAX;
1395 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_2)
1396 *pu32Val = 1048575; // D3D_FL9_2_IA_PRIMITIVE_MAX_COUNT;
1397 else
1398 *pu32Val = 65535; // D3D_FL9_1_IA_PRIMITIVE_MAX_COUNT;
1399 break;
1400
1401 case SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
1402 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1403 *pu32Val = UINT32_MAX;
1404 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_2)
1405 *pu32Val = 1048575;
1406 else
1407 *pu32Val = 65534;
1408 break;
1409
1410 case SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
1411 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1412 *pu32Val = UINT32_MAX;
1413 else
1414 *pu32Val = 512;
1415 break;
1416
1417 case SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
1418 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1419 *pu32Val = UINT32_MAX;
1420 else
1421 *pu32Val = 512;
1422 break;
1423
1424 case SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
1425 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1426 *pu32Val = 4096;
1427 else
1428 *pu32Val = 32;
1429 break;
1430
1431 case SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
1432 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1433 *pu32Val = 4096;
1434 else
1435 *pu32Val = 32;
1436 break;
1437
1438 case SVGA3D_DEVCAP_TEXTURE_OPS:
1439 /* Obsolete */
1440 break;
1441
1442 case SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
1443 case SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
1444 case SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
1445 case SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
1446 case SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
1447 case SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
1448 case SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
1449 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
1450 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
1451 case SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
1452 case SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
1453 case SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
1454 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
1455 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
1456 case SVGA3D_DEVCAP_SURFACEFMT_DXT1:
1457 case SVGA3D_DEVCAP_SURFACEFMT_DXT2:
1458 case SVGA3D_DEVCAP_SURFACEFMT_DXT3:
1459 case SVGA3D_DEVCAP_SURFACEFMT_DXT4:
1460 case SVGA3D_DEVCAP_SURFACEFMT_DXT5:
1461 case SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
1462 case SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
1463 case SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
1464 case SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
1465 case SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
1466 case SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
1467 case SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
1468 case SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
1469 case SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
1470 case SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
1471 case SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
1472 case SVGA3D_DEVCAP_SURFACEFMT_V16U16:
1473 case SVGA3D_DEVCAP_SURFACEFMT_G16R16:
1474 case SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
1475 case SVGA3D_DEVCAP_SURFACEFMT_UYVY:
1476 case SVGA3D_DEVCAP_SURFACEFMT_YUY2:
1477 case SVGA3D_DEVCAP_SURFACEFMT_NV12:
1478 case SVGA3D_DEVCAP_SURFACEFMT_AYUV:
1479 case SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
1480 case SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
1481 case SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
1482 case SVGA3D_DEVCAP_SURFACEFMT_ATI1:
1483 case SVGA3D_DEVCAP_SURFACEFMT_ATI2:
1484 case SVGA3D_DEVCAP_SURFACEFMT_YV12:
1485 {
1486 SVGA3dSurfaceFormat const enmFormat = vmsvgaDXDevCapSurfaceFmt2Format(idx3dCaps);
1487 rc = vmsvgaDXCheckFormatSupportPreDX(pState, enmFormat, pu32Val);
1488 break;
1489 }
1490
1491 case SVGA3D_DEVCAP_MISSING62:
1492 /* Unused */
1493 break;
1494
1495 case SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
1496 /* Obsolete */
1497 break;
1498
1499 case SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
1500 if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_10_0)
1501 *pu32Val = 8;
1502 else if (pState->pBackend->FeatureLevel >= D3D_FEATURE_LEVEL_9_3)
1503 *pu32Val = 4; // D3D_FL9_3_SIMULTANEOUS_RENDER_TARGET_COUNT
1504 else
1505 *pu32Val = 1; // D3D_FL9_1_SIMULTANEOUS_RENDER_TARGET_COUNT
1506 break;
1507
1508 case SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
1509 case SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
1510 *pu32Val = (1 << (2-1)) | (1 << (4-1)) | (1 << (8-1)); /* 2x, 4x, 8x */
1511 break;
1512
1513 case SVGA3D_DEVCAP_ALPHATOCOVERAGE:
1514 /* Obsolete? */
1515 break;
1516
1517 case SVGA3D_DEVCAP_SUPERSAMPLE:
1518 /* Obsolete? */
1519 break;
1520
1521 case SVGA3D_DEVCAP_AUTOGENMIPMAPS:
1522 *pu32Val = 1;
1523 break;
1524
1525 case SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
1526 *pu32Val = SVGA3D_MAX_CONTEXT_IDS;
1527 break;
1528
1529 case SVGA3D_DEVCAP_MAX_SURFACE_IDS:
1530 *pu32Val = SVGA3D_MAX_SURFACE_IDS;
1531 break;
1532
1533 case SVGA3D_DEVCAP_DEAD1:
1534 /* Obsolete */
1535 break;
1536
1537 case SVGA3D_DEVCAP_VIDEO_DECODE:
1538 /* Obsolete */
1539 break;
1540
1541 case SVGA3D_DEVCAP_VIDEO_PROCESS:
1542 /* Obsolete */
1543 break;
1544
1545 case SVGA3D_DEVCAP_LINE_AA:
1546 *pu32Val = 1;
1547 break;
1548
1549 case SVGA3D_DEVCAP_LINE_STIPPLE:
1550 *pu32Val = 0; /* DX11 does not seem to support this directly. */
1551 break;
1552
1553 case SVGA3D_DEVCAP_MAX_LINE_WIDTH:
1554 AssertCompile(sizeof(uint32_t) == sizeof(float));
1555 *(float *)pu32Val = 1.0f;
1556 break;
1557
1558 case SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH:
1559 AssertCompile(sizeof(uint32_t) == sizeof(float));
1560 *(float *)pu32Val = 1.0f;
1561 break;
1562
1563 case SVGA3D_DEVCAP_LOGICOPS:
1564 /* Deprecated. */
1565 AssertCompile(SVGA3D_DEVCAP_LOGICOPS == 92); /* Newer SVGA headers redefine this. */
1566 *pu32Val = 0; /* Supported starting with Direct3D 11.1 */
1567 break;
1568
1569 case SVGA3D_DEVCAP_TS_COLOR_KEY:
1570 *pu32Val = 0; /* DX11 does not seem to support this directly. */
1571 break;
1572
1573 case SVGA3D_DEVCAP_DEAD2:
1574 break;
1575
1576 case SVGA3D_DEVCAP_DX:
1577 *pu32Val = 1;
1578 break;
1579
1580 case SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE:
1581 *pu32Val = D3D11_REQ_TEXTURE2D_ARRAY_AXIS_DIMENSION;
1582 break;
1583
1584 case SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS:
1585 *pu32Val = D3D11_IA_VERTEX_INPUT_RESOURCE_SLOT_COUNT;
1586 break;
1587
1588 case SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS:
1589 *pu32Val = D3D11_COMMONSHADER_CONSTANT_BUFFER_HW_SLOT_COUNT;
1590 break;
1591
1592 case SVGA3D_DEVCAP_DX_PROVOKING_VERTEX:
1593 *pu32Val = 0; /* boolean */
1594 break;
1595
1596 case SVGA3D_DEVCAP_DXFMT_X8R8G8B8:
1597 case SVGA3D_DEVCAP_DXFMT_A8R8G8B8:
1598 case SVGA3D_DEVCAP_DXFMT_R5G6B5:
1599 case SVGA3D_DEVCAP_DXFMT_X1R5G5B5:
1600 case SVGA3D_DEVCAP_DXFMT_A1R5G5B5:
1601 case SVGA3D_DEVCAP_DXFMT_A4R4G4B4:
1602 case SVGA3D_DEVCAP_DXFMT_Z_D32:
1603 case SVGA3D_DEVCAP_DXFMT_Z_D16:
1604 case SVGA3D_DEVCAP_DXFMT_Z_D24S8:
1605 case SVGA3D_DEVCAP_DXFMT_Z_D15S1:
1606 case SVGA3D_DEVCAP_DXFMT_LUMINANCE8:
1607 case SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4:
1608 case SVGA3D_DEVCAP_DXFMT_LUMINANCE16:
1609 case SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8:
1610 case SVGA3D_DEVCAP_DXFMT_DXT1:
1611 case SVGA3D_DEVCAP_DXFMT_DXT2:
1612 case SVGA3D_DEVCAP_DXFMT_DXT3:
1613 case SVGA3D_DEVCAP_DXFMT_DXT4:
1614 case SVGA3D_DEVCAP_DXFMT_DXT5:
1615 case SVGA3D_DEVCAP_DXFMT_BUMPU8V8:
1616 case SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5:
1617 case SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8:
1618 case SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1:
1619 case SVGA3D_DEVCAP_DXFMT_ARGB_S10E5:
1620 case SVGA3D_DEVCAP_DXFMT_ARGB_S23E8:
1621 case SVGA3D_DEVCAP_DXFMT_A2R10G10B10:
1622 case SVGA3D_DEVCAP_DXFMT_V8U8:
1623 case SVGA3D_DEVCAP_DXFMT_Q8W8V8U8:
1624 case SVGA3D_DEVCAP_DXFMT_CxV8U8:
1625 case SVGA3D_DEVCAP_DXFMT_X8L8V8U8:
1626 case SVGA3D_DEVCAP_DXFMT_A2W10V10U10:
1627 case SVGA3D_DEVCAP_DXFMT_ALPHA8:
1628 case SVGA3D_DEVCAP_DXFMT_R_S10E5:
1629 case SVGA3D_DEVCAP_DXFMT_R_S23E8:
1630 case SVGA3D_DEVCAP_DXFMT_RG_S10E5:
1631 case SVGA3D_DEVCAP_DXFMT_RG_S23E8:
1632 case SVGA3D_DEVCAP_DXFMT_BUFFER:
1633 case SVGA3D_DEVCAP_DXFMT_Z_D24X8:
1634 case SVGA3D_DEVCAP_DXFMT_V16U16:
1635 case SVGA3D_DEVCAP_DXFMT_G16R16:
1636 case SVGA3D_DEVCAP_DXFMT_A16B16G16R16:
1637 case SVGA3D_DEVCAP_DXFMT_UYVY:
1638 case SVGA3D_DEVCAP_DXFMT_YUY2:
1639 case SVGA3D_DEVCAP_DXFMT_NV12:
1640 case SVGA3D_DEVCAP_DXFMT_AYUV:
1641 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS:
1642 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT:
1643 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT:
1644 case SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS:
1645 case SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT:
1646 case SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT:
1647 case SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT:
1648 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS:
1649 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT:
1650 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM:
1651 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT:
1652 case SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS:
1653 case SVGA3D_DEVCAP_DXFMT_R32G32_UINT:
1654 case SVGA3D_DEVCAP_DXFMT_R32G32_SINT:
1655 case SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS:
1656 case SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT:
1657 case SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24_TYPELESS:
1658 case SVGA3D_DEVCAP_DXFMT_X32_TYPELESS_G8X24_UINT:
1659 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS:
1660 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT:
1661 case SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT:
1662 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS:
1663 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM:
1664 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB:
1665 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT:
1666 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT:
1667 case SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS:
1668 case SVGA3D_DEVCAP_DXFMT_R16G16_UINT:
1669 case SVGA3D_DEVCAP_DXFMT_R16G16_SINT:
1670 case SVGA3D_DEVCAP_DXFMT_R32_TYPELESS:
1671 case SVGA3D_DEVCAP_DXFMT_D32_FLOAT:
1672 case SVGA3D_DEVCAP_DXFMT_R32_UINT:
1673 case SVGA3D_DEVCAP_DXFMT_R32_SINT:
1674 case SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS:
1675 case SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT:
1676 case SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8_TYPELESS:
1677 case SVGA3D_DEVCAP_DXFMT_X24_TYPELESS_G8_UINT:
1678 case SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS:
1679 case SVGA3D_DEVCAP_DXFMT_R8G8_UNORM:
1680 case SVGA3D_DEVCAP_DXFMT_R8G8_UINT:
1681 case SVGA3D_DEVCAP_DXFMT_R8G8_SINT:
1682 case SVGA3D_DEVCAP_DXFMT_R16_TYPELESS:
1683 case SVGA3D_DEVCAP_DXFMT_R16_UNORM:
1684 case SVGA3D_DEVCAP_DXFMT_R16_UINT:
1685 case SVGA3D_DEVCAP_DXFMT_R16_SNORM:
1686 case SVGA3D_DEVCAP_DXFMT_R16_SINT:
1687 case SVGA3D_DEVCAP_DXFMT_R8_TYPELESS:
1688 case SVGA3D_DEVCAP_DXFMT_R8_UNORM:
1689 case SVGA3D_DEVCAP_DXFMT_R8_UINT:
1690 case SVGA3D_DEVCAP_DXFMT_R8_SNORM:
1691 case SVGA3D_DEVCAP_DXFMT_R8_SINT:
1692 case SVGA3D_DEVCAP_DXFMT_P8:
1693 case SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP:
1694 case SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM:
1695 case SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM:
1696 case SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS:
1697 case SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB:
1698 case SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS:
1699 case SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB:
1700 case SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS:
1701 case SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB:
1702 case SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS:
1703 case SVGA3D_DEVCAP_DXFMT_ATI1:
1704 case SVGA3D_DEVCAP_DXFMT_BC4_SNORM:
1705 case SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS:
1706 case SVGA3D_DEVCAP_DXFMT_ATI2:
1707 case SVGA3D_DEVCAP_DXFMT_BC5_SNORM:
1708 case SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM:
1709 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS:
1710 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB:
1711 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS:
1712 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB:
1713 case SVGA3D_DEVCAP_DXFMT_Z_DF16:
1714 case SVGA3D_DEVCAP_DXFMT_Z_DF24:
1715 case SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT:
1716 case SVGA3D_DEVCAP_DXFMT_YV12:
1717 case SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT:
1718 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT:
1719 case SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM:
1720 case SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT:
1721 case SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM:
1722 case SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM:
1723 case SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT:
1724 case SVGA3D_DEVCAP_DXFMT_R16G16_UNORM:
1725 case SVGA3D_DEVCAP_DXFMT_R16G16_SNORM:
1726 case SVGA3D_DEVCAP_DXFMT_R32_FLOAT:
1727 case SVGA3D_DEVCAP_DXFMT_R8G8_SNORM:
1728 case SVGA3D_DEVCAP_DXFMT_R16_FLOAT:
1729 case SVGA3D_DEVCAP_DXFMT_D16_UNORM:
1730 case SVGA3D_DEVCAP_DXFMT_A8_UNORM:
1731 case SVGA3D_DEVCAP_DXFMT_BC1_UNORM:
1732 case SVGA3D_DEVCAP_DXFMT_BC2_UNORM:
1733 case SVGA3D_DEVCAP_DXFMT_BC3_UNORM:
1734 case SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM:
1735 case SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM:
1736 case SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM:
1737 case SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM:
1738 case SVGA3D_DEVCAP_DXFMT_BC4_UNORM:
1739 case SVGA3D_DEVCAP_DXFMT_BC5_UNORM:
1740 {
1741 SVGA3dSurfaceFormat const enmFormat = vmsvgaDXDevCapDxfmt2Format(idx3dCaps);
1742 rc = vmsvgaDXCheckFormatSupport(pState, enmFormat, pu32Val);
1743 break;
1744 }
1745
1746 case SVGA3D_DEVCAP_MAX:
1747 case SVGA3D_DEVCAP_INVALID:
1748 rc = VERR_NOT_SUPPORTED;
1749 break;
1750 }
1751
1752 return rc;
1753}
1754
1755
1756/* Handle resize */
1757int vmsvga3dChangeMode(PVGASTATECC pThisCC)
1758{
1759 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1760 AssertReturn(pState, VERR_INVALID_STATE);
1761
1762 return VINF_SUCCESS;
1763}
1764
1765
1766int vmsvga3dSurfaceCopy(PVGASTATECC pThisCC, SVGA3dSurfaceImageId dest, SVGA3dSurfaceImageId src,
1767 uint32_t cCopyBoxes, SVGA3dCopyBox *pBox)
1768{
1769 RT_NOREF(dest, src, cCopyBoxes, pBox);
1770
1771 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1772 AssertReturn(pState, VERR_INVALID_STATE);
1773
1774 AssertFailed();
1775 return VERR_NOT_IMPLEMENTED;
1776}
1777
1778
1779/**
1780 * Create a new 3d context
1781 *
1782 * @returns VBox status code.
1783 * @param pThisCC The VGA/VMSVGA state for ring-3.
1784 * @param cid Context id
1785 */
1786int vmsvga3dContextDefine(PVGASTATECC pThisCC, uint32_t cid)
1787{
1788 RT_NOREF(cid);
1789
1790 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1791 AssertReturn(pState, VERR_INVALID_STATE);
1792
1793 AssertFailed();
1794 return VERR_NOT_IMPLEMENTED;
1795}
1796
1797
1798/**
1799 * Destroy an existing 3d context
1800 *
1801 * @returns VBox status code.
1802 * @param pThisCC The VGA/VMSVGA state for ring-3.
1803 * @param cid Context id
1804 */
1805int vmsvga3dContextDestroy(PVGASTATECC pThisCC, uint32_t cid)
1806{
1807 RT_NOREF(cid);
1808
1809 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1810 AssertReturn(pState, VERR_INVALID_STATE);
1811
1812 AssertFailed();
1813 return VINF_SUCCESS;
1814}
1815
1816
1817int vmsvga3dSetTransform(PVGASTATECC pThisCC, uint32_t cid, SVGA3dTransformType type, float matrix[16])
1818{
1819 RT_NOREF(cid, type, matrix);
1820
1821 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1822 AssertReturn(pState, VERR_INVALID_STATE);
1823
1824 AssertFailed();
1825 return VINF_SUCCESS;
1826}
1827
1828
1829int vmsvga3dSetZRange(PVGASTATECC pThisCC, uint32_t cid, SVGA3dZRange zRange)
1830{
1831 RT_NOREF(cid, zRange);
1832
1833 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1834 AssertReturn(pState, VERR_INVALID_STATE);
1835
1836 AssertFailed();
1837 return VINF_SUCCESS;
1838}
1839
1840
1841int vmsvga3dSetRenderState(PVGASTATECC pThisCC, uint32_t cid, uint32_t cRenderStates, SVGA3dRenderState *pRenderState)
1842{
1843 RT_NOREF(cid, cRenderStates, pRenderState);
1844
1845 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1846 AssertReturn(pState, VERR_INVALID_STATE);
1847
1848 AssertFailed();
1849 return VINF_SUCCESS;
1850}
1851
1852
1853int vmsvga3dSetRenderTarget(PVGASTATECC pThisCC, uint32_t cid, SVGA3dRenderTargetType type, SVGA3dSurfaceImageId target)
1854{
1855 RT_NOREF(cid, type, target);
1856
1857 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1858 AssertReturn(pState, VERR_INVALID_STATE);
1859
1860 AssertFailed();
1861 return VINF_SUCCESS;
1862}
1863
1864
1865int vmsvga3dSetTextureState(PVGASTATECC pThisCC, uint32_t cid, uint32_t cTextureStates, SVGA3dTextureState *pTextureState)
1866{
1867 RT_NOREF(cid, cTextureStates, pTextureState);
1868
1869 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1870 AssertReturn(pState, VERR_INVALID_STATE);
1871
1872 AssertFailed();
1873 return VINF_SUCCESS;
1874}
1875
1876
1877int vmsvga3dSetMaterial(PVGASTATECC pThisCC, uint32_t cid, SVGA3dFace face, SVGA3dMaterial *pMaterial)
1878{
1879 RT_NOREF(cid, face, pMaterial);
1880
1881 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1882 AssertReturn(pState, VERR_INVALID_STATE);
1883
1884 AssertFailed();
1885 return VINF_SUCCESS;
1886}
1887
1888
1889int vmsvga3dSetLightData(PVGASTATECC pThisCC, uint32_t cid, uint32_t index, SVGA3dLightData *pData)
1890{
1891 RT_NOREF(cid, index, pData);
1892
1893 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1894 AssertReturn(pState, VERR_INVALID_STATE);
1895
1896 AssertFailed();
1897 return VINF_SUCCESS;
1898}
1899
1900
1901int vmsvga3dSetLightEnabled(PVGASTATECC pThisCC, uint32_t cid, uint32_t index, uint32_t enabled)
1902{
1903 RT_NOREF(cid, index, enabled);
1904
1905 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1906 AssertReturn(pState, VERR_INVALID_STATE);
1907
1908 AssertFailed();
1909 return VINF_SUCCESS;
1910}
1911
1912
1913int vmsvga3dSetViewPort(PVGASTATECC pThisCC, uint32_t cid, SVGA3dRect *pRect)
1914{
1915 RT_NOREF(cid, pRect);
1916
1917 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1918 AssertReturn(pState, VERR_INVALID_STATE);
1919
1920 AssertFailed();
1921 return VINF_SUCCESS;
1922}
1923
1924
1925int vmsvga3dSetClipPlane(PVGASTATECC pThisCC, uint32_t cid, uint32_t index, float plane[4])
1926{
1927 RT_NOREF(cid, index, plane);
1928
1929 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1930 AssertReturn(pState, VERR_INVALID_STATE);
1931
1932 AssertFailed();
1933 return VINF_SUCCESS;
1934}
1935
1936
1937int vmsvga3dCommandClear(PVGASTATECC pThisCC, uint32_t cid, SVGA3dClearFlag clearFlag, uint32_t color, float depth,
1938 uint32_t stencil, uint32_t cRects, SVGA3dRect *pRect)
1939{
1940 /* From SVGA3D_BeginClear comments:
1941 *
1942 * Clear is not affected by clipping, depth test, or other
1943 * render state which affects the fragment pipeline.
1944 *
1945 * Therefore this code must ignore the current scissor rect.
1946 */
1947
1948 RT_NOREF(cid, clearFlag, color, depth, stencil, cRects, pRect);
1949
1950 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1951 AssertReturn(pState, VERR_INVALID_STATE);
1952
1953 AssertFailed();
1954 return VINF_SUCCESS;
1955}
1956
1957
1958int vmsvga3dDrawPrimitives(PVGASTATECC pThisCC, uint32_t cid, uint32_t numVertexDecls, SVGA3dVertexDecl *pVertexDecl,
1959 uint32_t numRanges, SVGA3dPrimitiveRange *pRange,
1960 uint32_t cVertexDivisor, SVGA3dVertexDivisor *pVertexDivisor)
1961{
1962 RT_NOREF(cid, numVertexDecls, pVertexDecl, numRanges, pRange, cVertexDivisor, pVertexDivisor);
1963
1964 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1965 AssertReturn(pState, VERR_INVALID_STATE);
1966
1967 AssertFailed();
1968 return VINF_SUCCESS;
1969}
1970
1971
1972int vmsvga3dSetScissorRect(PVGASTATECC pThisCC, uint32_t cid, SVGA3dRect *pRect)
1973{
1974 RT_NOREF(cid, pRect);
1975
1976 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1977 AssertReturn(pState, VERR_INVALID_STATE);
1978
1979 AssertFailed();
1980 return VINF_SUCCESS;
1981}
1982
1983
1984int vmsvga3dGenerateMipmaps(PVGASTATECC pThisCC, uint32_t sid, SVGA3dTextureFilter filter)
1985{
1986 RT_NOREF(sid, filter);
1987
1988 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
1989 AssertReturn(pState, VERR_INVALID_STATE);
1990
1991 AssertFailed();
1992 return VINF_SUCCESS;
1993}
1994
1995
1996int vmsvga3dShaderDefine(PVGASTATECC pThisCC, uint32_t cid, uint32_t shid, SVGA3dShaderType type,
1997 uint32_t cbData, uint32_t *pShaderData)
1998{
1999 RT_NOREF(cid, shid, type, cbData, pShaderData);
2000
2001 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
2002 AssertReturn(pState, VERR_INVALID_STATE);
2003
2004 AssertFailed();
2005 return VINF_SUCCESS;
2006}
2007
2008
2009int vmsvga3dShaderDestroy(PVGASTATECC pThisCC, uint32_t cid, uint32_t shid, SVGA3dShaderType type)
2010{
2011 RT_NOREF(cid, shid, type);
2012
2013 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
2014 AssertReturn(pState, VERR_INVALID_STATE);
2015
2016 AssertFailed();
2017 return VINF_SUCCESS;
2018}
2019
2020
2021int vmsvga3dShaderSet(PVGASTATECC pThisCC, PVMSVGA3DCONTEXT pContext, uint32_t cid, SVGA3dShaderType type, uint32_t shid)
2022{
2023 RT_NOREF(pContext, cid, type, shid);
2024
2025 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
2026 AssertReturn(pState, VERR_INVALID_STATE);
2027
2028 AssertFailed();
2029 return VINF_SUCCESS;
2030}
2031
2032
2033int vmsvga3dShaderSetConst(PVGASTATECC pThisCC, uint32_t cid, uint32_t reg, SVGA3dShaderType type,
2034 SVGA3dShaderConstType ctype, uint32_t cRegisters, uint32_t *pValues)
2035{
2036 RT_NOREF(cid, reg, type, ctype, cRegisters, pValues);
2037
2038 PVMSVGA3DSTATE pState = pThisCC->svga.p3dState;
2039 AssertReturn(pState, VERR_INVALID_STATE);
2040
2041 AssertFailed();
2042 return VINF_SUCCESS;
2043}
2044
2045
2046/**
2047 * Destroy backend specific surface bits (part of SVGA_3D_CMD_SURFACE_DESTROY).
2048 *
2049 * @param pState The VMSVGA3d state.
2050 * @param pSurface The surface being destroyed.
2051 */
2052void vmsvga3dBackSurfaceDestroy(PVMSVGA3DSTATE pState, PVMSVGA3DSURFACE pSurface)
2053{
2054 PVMSVGA3DBACKEND pBackend = pState->pBackend;
2055 AssertReturnVoid(pBackend);
2056 AssertReturnVoid(pBackend->pImmediateContext);
2057
2058 /* The caller should not use the function for system memory surfaces. */
2059 PVMSVGA3DBACKENDSURFACE pBackendSurface = pSurface->pBackendSurface;
2060 AssertReturnVoid(pBackendSurface);
2061 pSurface->pBackendSurface = NULL;
2062
2063 if (pBackendSurface->enmResType == VMSVGA3D_RESTYPE_SCREEN_TARGET)
2064 {
2065 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pStagingTexture);
2066 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pDynamicTexture);
2067 D3D_RELEASE(pBackendSurface->u.ScreenTarget.pTexture);
2068 }
2069 else
2070 {
2071 AssertFailed();
2072 }
2073
2074 RTMemFree(pBackendSurface);
2075}
2076
2077
2078/**
2079 * Backend worker for implementing SVGA_3D_CMD_SURFACE_STRETCHBLT.
2080 *
2081 * @returns VBox status code.
2082 * @param pThis The VGA device instance.
2083 * @param pState The VMSVGA3d state.
2084 * @param pDstSurface The destination host surface.
2085 * @param uDstFace The destination face (valid).
2086 * @param uDstMipmap The destination mipmap level (valid).
2087 * @param pDstBox The destination box.
2088 * @param pSrcSurface The source host surface.
2089 * @param uSrcFace The destination face (valid).
2090 * @param uSrcMipmap The source mimap level (valid).
2091 * @param pSrcBox The source box.
2092 * @param enmMode The strecht blt mode .
2093 * @param pContext The VMSVGA3d context (already current for OGL).
2094 */
2095int vmsvga3dBackSurfaceStretchBlt(PVGASTATE pThis, PVMSVGA3DSTATE pState,
2096 PVMSVGA3DSURFACE pDstSurface, uint32_t uDstFace, uint32_t uDstMipmap, SVGA3dBox const *pDstBox,
2097 PVMSVGA3DSURFACE pSrcSurface, uint32_t uSrcFace, uint32_t uSrcMipmap, SVGA3dBox const *pSrcBox,
2098 SVGA3dStretchBltMode enmMode, PVMSVGA3DCONTEXT pContext)
2099{
2100 RT_NOREF(pThis, pState, pDstSurface, uDstFace, uDstMipmap, pDstBox,
2101 pSrcSurface, uSrcFace, uSrcMipmap, pSrcBox, enmMode, pContext);
2102
2103 AssertFailed();
2104 return VINF_SUCCESS;
2105}
2106
2107
2108/**
2109 * Backend worker for implementing SVGA_3D_CMD_SURFACE_DMA that copies one box.
2110 *
2111 * @returns Failure status code or @a rc.
2112 * @param pThis The shared VGA/VMSVGA instance data.
2113 * @param pThisCC The VGA/VMSVGA state for ring-3.
2114 * @param pState The VMSVGA3d state.
2115 * @param pSurface The host surface.
2116 * @param pMipLevel Mipmap level. The caller knows it already.
2117 * @param uHostFace The host face (valid).
2118 * @param uHostMipmap The host mipmap level (valid).
2119 * @param GuestPtr The guest pointer.
2120 * @param cbGuestPitch The guest pitch.
2121 * @param transfer The transfer direction.
2122 * @param pBox The box to copy (clipped, valid, except for guest's srcx, srcy, srcz).
2123 * @param pContext The context (for OpenGL).
2124 * @param rc The current rc for all boxes.
2125 * @param iBox The current box number (for Direct 3D).
2126 */
2127int vmsvga3dBackSurfaceDMACopyBox(PVGASTATE pThis, PVGASTATECC pThisCC, PVMSVGA3DSTATE pState, PVMSVGA3DSURFACE pSurface,
2128 PVMSVGA3DMIPMAPLEVEL pMipLevel, uint32_t uHostFace, uint32_t uHostMipmap,
2129 SVGAGuestPtr GuestPtr, uint32_t cbGuestPitch, SVGA3dTransferType transfer,
2130 SVGA3dCopyBox const *pBox, PVMSVGA3DCONTEXT pContext, int rc, int iBox)
2131{
2132 RT_NOREF(pState, pMipLevel, pContext, iBox);
2133
2134 /* The called should not use the function for system memory surfaces. */
2135 PVMSVGA3DBACKENDSURFACE pBackendSurface = pSurface->pBackendSurface;
2136 AssertReturn(pBackendSurface, VERR_INVALID_PARAMETER);
2137
2138 if (pBackendSurface->enmResType == VMSVGA3D_RESTYPE_SCREEN_TARGET)
2139 {
2140 /** @todo This is generic code and should be in DevVGA-SVGA3d.cpp for backends which support Map/Unmap. */
2141 AssertReturn(uHostFace == 0 && uHostMipmap == 0, VERR_INVALID_PARAMETER);
2142 AssertReturn(transfer == SVGA3D_WRITE_HOST_VRAM, VERR_NOT_IMPLEMENTED); /** @todo Implement */
2143
2144 uint32_t const u32GuestBlockX = pBox->srcx / pSurface->cxBlock;
2145 uint32_t const u32GuestBlockY = pBox->srcy / pSurface->cyBlock;
2146 Assert(u32GuestBlockX * pSurface->cxBlock == pBox->srcx);
2147 Assert(u32GuestBlockY * pSurface->cyBlock == pBox->srcy);
2148 uint32_t const cBlocksX = (pBox->w + pSurface->cxBlock - 1) / pSurface->cxBlock;
2149 uint32_t const cBlocksY = (pBox->h + pSurface->cyBlock - 1) / pSurface->cyBlock;
2150 AssertMsgReturn(cBlocksX && cBlocksY, ("Empty box %dx%d\n", pBox->w, pBox->h), VERR_INTERNAL_ERROR);
2151
2152 /* vmsvgaR3GmrTransfer verifies uGuestOffset.
2153 * srcx(u32GuestBlockX) and srcy(u32GuestBlockY) have been verified in vmsvga3dSurfaceDMA
2154 * to not cause 32 bit overflow when multiplied by cbBlock and cbGuestPitch.
2155 */
2156 uint64_t const uGuestOffset = u32GuestBlockX * pSurface->cbBlock + u32GuestBlockY * cbGuestPitch;
2157 AssertReturn(uGuestOffset < UINT32_MAX, VERR_INVALID_PARAMETER);
2158
2159 SVGA3dSurfaceImageId image;
2160 image.sid = pSurface->id;
2161 image.face = uHostFace;
2162 image.mipmap = uHostMipmap;
2163
2164 SVGA3dBox box;
2165 box.x = pBox->x;
2166 box.y = pBox->y;
2167 box.z = 0;
2168 box.w = pBox->w;
2169 box.h = pBox->h;
2170 box.d = 1;
2171
2172 VMSVGA3D_MAPPED_SURFACE map;
2173 rc = vmsvga3dSurfaceMap(pThisCC, &image, &box, VMSVGA3D_SURFACE_MAP_WRITE_DISCARD, &map);
2174 if (RT_SUCCESS(rc))
2175 {
2176 /* Prepare parameters for vmsvgaR3GmrTransfer, which needs the host buffer address, size
2177 * and offset of the first scanline.
2178 */
2179 uint32_t const cbLockedBuf = map.cbRowPitch * cBlocksY;
2180 uint8_t *pu8LockedBuf = (uint8_t *)map.pvData;
2181 uint32_t const offLockedBuf = 0;
2182
2183 rc = vmsvgaR3GmrTransfer(pThis,
2184 pThisCC,
2185 transfer,
2186 pu8LockedBuf,
2187 cbLockedBuf,
2188 offLockedBuf,
2189 map.cbRowPitch,
2190 GuestPtr,
2191 (uint32_t)uGuestOffset,
2192 cbGuestPitch,
2193 cBlocksX * pSurface->cbBlock,
2194 cBlocksY);
2195 AssertRC(rc);
2196
2197 // Log4(("first line:\n%.*Rhxd\n", cBlocksX * pSurface->cbBlock, LockedRect.pBits));
2198
2199 //vmsvga3dMapWriteBmpFile(&map, "Dynamic");
2200
2201 vmsvga3dSurfaceUnmap(pThisCC, &image, &map, /* fWritten = */ true);
2202 }
2203#if 0
2204//ASMBreakpoint();
2205 rc = vmsvga3dSurfaceMap(pThisCC, &image, NULL, VMSVGA3D_SURFACE_MAP_READ, &map);
2206 if (RT_SUCCESS(rc))
2207 {
2208 vmsvga3dMapWriteBmpFile(&map, "Staging");
2209
2210 vmsvga3dSurfaceUnmap(pThisCC, &image, &map, /* fWritten = */ false);
2211 }
2212#endif
2213 }
2214 else
2215 {
2216 AssertMsgFailed(("Unsupported surface type %d\n", pBackendSurface->enmResType));
2217 rc = VERR_NOT_IMPLEMENTED;
2218 }
2219
2220 return rc;
2221}
2222
2223
2224/**
2225 * Create D3D/OpenGL texture object for the specified surface.
2226 *
2227 * Surfaces are created when needed.
2228 *
2229 * @param pState The VMSVGA3d state.
2230 * @param pContext The context.
2231 * @param idAssociatedContext Probably the same as pContext->id.
2232 * @param pSurface The surface to create the texture for.
2233 */
2234int vmsvga3dBackCreateTexture(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext, uint32_t idAssociatedContext,
2235 PVMSVGA3DSURFACE pSurface)
2236
2237{
2238 RT_NOREF(pState, pContext, idAssociatedContext, pSurface);
2239
2240 AssertFailed();
2241 return VINF_SUCCESS;
2242}
2243
2244
2245int vmsvga3dOcclusionQueryCreate(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext)
2246{
2247 RT_NOREF(pState, pContext);
2248 AssertFailed();
2249 return VINF_SUCCESS;
2250}
2251
2252
2253int vmsvga3dOcclusionQueryBegin(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext)
2254{
2255 RT_NOREF(pState, pContext);
2256 AssertFailed();
2257 return VINF_SUCCESS;
2258}
2259
2260
2261int vmsvga3dOcclusionQueryEnd(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext)
2262{
2263 RT_NOREF(pState, pContext);
2264 AssertFailed();
2265 return VINF_SUCCESS;
2266}
2267
2268
2269int vmsvga3dOcclusionQueryGetData(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext, uint32_t *pu32Pixels)
2270{
2271 RT_NOREF(pState, pContext);
2272 *pu32Pixels = 0;
2273 AssertFailed();
2274 return VINF_SUCCESS;
2275}
2276
2277
2278int vmsvga3dOcclusionQueryDelete(PVMSVGA3DSTATE pState, PVMSVGA3DCONTEXT pContext)
2279{
2280 RT_NOREF(pState, pContext);
2281 AssertFailed();
2282 return VINF_SUCCESS;
2283}
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