VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.cpp@ 8483

Last change on this file since 8483 was 8170, checked in by vboxsync, 17 years ago

Rebranding: replacing more innotek strings.
  • Property svn:eol-style set to native
File size: 188.0 KB
Line 
1#ifdef VBOX
2/* $Id: $ */
3/** @file
4 * VBox VGA/VESA device
5 */
6
7/*
8 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19 * Clara, CA 95054 USA or visit http://www.sun.com if you need
20 * additional information or have any questions.
21 * --------------------------------------------------------------------
22 *
23 * This code is based on:
24 *
25 * QEMU VGA Emulator.
26 *
27 * Copyright (c) 2003 Fabrice Bellard
28 *
29 * Permission is hereby granted, free of charge, to any person obtaining a copy
30 * of this software and associated documentation files (the "Software"), to deal
31 * in the Software without restriction, including without limitation the rights
32 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
33 * copies of the Software, and to permit persons to whom the Software is
34 * furnished to do so, subject to the following conditions:
35 *
36 * The above copyright notice and this permission notice shall be included in
37 * all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
44 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45 * THE SOFTWARE.
46 */
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The default amount of VRAM. */
52#define VGA_VRAM_DEFAULT (_4M)
53/** The maximum amount of VRAM. */
54#define VGA_VRAM_MAX (128 * _1M)
55/** The minimum amount of VRAM. */
56#define VGA_VRAM_MIN (_1M)
57
58/** The size of the VGA GC mapping.
59 * This is supposed to be all the VGA memory accessible to the guest.
60 * The initial value was 256KB but NTAllInOne.iso appears to access more
61 * thus the limit was upped to 512KB.
62 *
63 * @todo Someone with some VGA knowhow should make a better guess at this value.
64 */
65#define VGA_MAPPING_SIZE _512K
66
67/** Converts a vga adaptor state pointer to a device instance pointer. */
68#define VGASTATE2DEVINS(pVgaState) ((pVgaState)->CTXSUFF(pDevIns))
69
70/** Use VBE bytewise I/O */
71#define VBE_BYTEWISE_IO
72
73/** Use VBE new dynamic mode list.
74 * If this is not defined, no checks are carried out to see if the modes all
75 * fit into the framebuffer! See the VRAM_SIZE_FIX define. */
76#define VBE_NEW_DYN_LIST
77
78/** Check that the video modes fit into virtual video memory.
79 * Only works when VBE_NEW_DYN_LIST is defined! */
80#define VRAM_SIZE_FIX
81
82/** Some fixes to ensure that logical scan-line lengths are not overwritten. */
83#define KEEP_SCAN_LINE_LENGTH
84
85
86/*******************************************************************************
87* Header Files *
88*******************************************************************************/
89#define LOG_GROUP LOG_GROUP_DEV_VGA
90#include <VBox/pdmdev.h>
91#include <VBox/pgm.h>
92#include <iprt/assert.h>
93#include <iprt/asm.h>
94#include <iprt/file.h>
95#include <iprt/string.h>
96
97#include <VBox/VBoxGuest.h>
98#include <VBox/VBoxVideo.h>
99#include <VBox/bioslogo.h>
100
101#if defined(VBE_NEW_DYN_LIST) && defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
102# include "DevVGAModes.h"
103# include <stdio.h> /* sscan */
104#endif
105
106#include "vl_vbox.h"
107#include "DevVGA.h"
108#include "Builtins.h"
109#include "Builtins2.h"
110
111
112/*******************************************************************************
113* Structures and Typedefs *
114*******************************************************************************/
115#pragma pack(1)
116
117/** BMP File Format Bitmap Header. */
118typedef struct
119{
120 uint16_t Type; /* File Type Identifier */
121 uint32_t FileSize; /* Size of File */
122 uint16_t Reserved1; /* Reserved (should be 0) */
123 uint16_t Reserved2; /* Reserved (should be 0) */
124 uint32_t Offset; /* Offset to bitmap data */
125} BMPINFO;
126
127/** Pointer to a bitmap header*/
128typedef BMPINFO *PBMPINFO;
129
130/** OS/2 1.x Information Header Format. */
131typedef struct
132{
133 uint32_t Size; /* Size of Remianing Header */
134 uint16_t Width; /* Width of Bitmap in Pixels */
135 uint16_t Height; /* Height of Bitmap in Pixels */
136 uint16_t Planes; /* Number of Planes */
137 uint16_t BitCount; /* Color Bits Per Pixel */
138} OS2HDR;
139
140/** Pointer to a OS/2 1.x header format */
141typedef OS2HDR *POS2HDR;
142
143/** OS/2 2.0 Information Header Format. */
144typedef struct
145{
146 uint32_t Size; /* Size of Remianing Header */
147 uint32_t Width; /* Width of Bitmap in Pixels */
148 uint32_t Height; /* Height of Bitmap in Pixels */
149 uint16_t Planes; /* Number of Planes */
150 uint16_t BitCount; /* Color Bits Per Pixel */
151 uint32_t Compression; /* Compression Scheme (0=none) */
152 uint32_t SizeImage; /* Size of bitmap in bytes */
153 uint32_t XPelsPerMeter; /* Horz. Resolution in Pixels/Meter */
154 uint32_t YPelsPerMeter; /* Vert. Resolution in Pixels/Meter */
155 uint32_t ClrUsed; /* Number of Colors in Color Table */
156 uint32_t ClrImportant; /* Number of Important Colors */
157 uint16_t Units; /* Resolution Mesaurement Used */
158 uint16_t Reserved; /* Reserved FIelds (always 0) */
159 uint16_t Recording; /* Orientation of Bitmap */
160 uint16_t Rendering; /* Halftone Algorithm Used on Image */
161 uint32_t Size1; /* Halftone Algorithm Data */
162 uint32_t Size2; /* Halftone Algorithm Data */
163 uint32_t ColorEncoding; /* Color Table Format (always 0) */
164 uint32_t Identifier; /* Misc. Field for Application Use */
165} OS22HDR;
166
167/** Pointer to a OS/2 2.0 header format */
168typedef OS22HDR *POS22HDR;
169
170/** Windows 3.x Information Header Format. */
171typedef struct
172{
173 uint32_t Size; /* Size of Remianing Header */
174 uint32_t Width; /* Width of Bitmap in Pixels */
175 uint32_t Height; /* Height of Bitmap in Pixels */
176 uint16_t Planes; /* Number of Planes */
177 uint16_t BitCount; /* Bits Per Pixel */
178 uint32_t Compression; /* Compression Scheme (0=none) */
179 uint32_t SizeImage; /* Size of bitmap in bytes */
180 uint32_t XPelsPerMeter; /* Horz. Resolution in Pixels/Meter */
181 uint32_t YPelsPerMeter; /* Vert. Resolution in Pixels/Meter */
182 uint32_t ClrUsed; /* Number of Colors in Color Table */
183 uint32_t ClrImportant; /* Number of Important Colors */
184} WINHDR;
185
186/** Pointer to a Windows 3.x header format */
187typedef WINHDR *PWINHDR;
188
189#pragma pack()
190
191#define BMP_ID 0x4D42
192
193/** @name BMP compressions.
194 * @{ */
195#define BMP_COMPRESS_NONE 0
196#define BMP_COMPRESS_RLE8 1
197#define BMP_COMPRESS_RLE4 2
198/** @} */
199
200/** @name BMP header sizes.
201 * @{ */
202#define BMP_HEADER_OS21 12
203#define BMP_HEADER_OS22 64
204#define BMP_HEADER_WIN3 40
205/** @} */
206
207/** The BIOS boot menu text position, X. */
208#define LOGO_F12TEXT_X 304
209/** The BIOS boot menu text position, Y. */
210#define LOGO_F12TEXT_Y 464
211
212/** Width of the "Press F12 to select boot device." bitmap.
213 Anything that exceeds the limit of F12BootText below is filled with
214 background. */
215#define LOGO_F12TEXT_WIDTH 286
216/** Height of the boot device selection bitmap, see LOGO_F12TEXT_WIDTH. */
217#define LOGO_F12TEXT_HEIGHT 12
218
219/** The BIOS logo delay time (msec). */
220#define LOGO_DELAY_TIME 2000
221
222#define LOGO_MAX_WIDTH 640
223#define LOGO_MAX_HEIGHT 480
224#define LOGO_MAX_SIZE LOGO_MAX_WIDTH * LOGO_MAX_HEIGHT * 4
225
226
227/*******************************************************************************
228* Global Variables *
229*******************************************************************************/
230/* "Press F12 to select boot device." bitmap. */
231static const uint8_t g_abLogoF12BootText[] =
232{
233#ifdef VBOX_OSE
234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x7C,
237 0xF8, 0xF0, 0x01, 0xE0, 0x81, 0x9F, 0x3F, 0x00, 0x70, 0xF8, 0x00, 0xE0, 0xC3,
238 0x07, 0x0F, 0x1F, 0x3E, 0x70, 0x00, 0xF0, 0xE1, 0xC3, 0x07, 0x0E, 0x00, 0x6E,
239 0x7C, 0x60, 0xE0, 0xE1, 0xC3, 0x07, 0xC6, 0x80, 0x81, 0x31, 0x63, 0xC6, 0x00,
240 0x30, 0x80, 0x61, 0x0C, 0x00, 0x36, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
241 0x18, 0x36, 0x00, 0xCC, 0x8C, 0x19, 0xC3, 0x06, 0xC0, 0x8C, 0x31, 0x3C, 0x30,
242 0x8C, 0x19, 0x83, 0x31, 0x60, 0x60, 0x00, 0x0C, 0x18, 0x00, 0x0C, 0x60, 0x18,
243 0x00, 0x80, 0xC1, 0x18, 0x00, 0x30, 0x06, 0x60, 0x18, 0x30, 0x80, 0x01, 0x00,
244 0x33, 0x63, 0xC6, 0x30, 0x00, 0x30, 0x63, 0x80, 0x19, 0x0C, 0x03, 0x06, 0x00,
245 0x0C, 0x18, 0x18, 0xC0, 0x81, 0x03, 0x00, 0x03, 0x18, 0x0C, 0x00, 0x60, 0x30,
246 0x06, 0x00, 0x87, 0x01, 0x18, 0x06, 0x0C, 0x60, 0x00, 0xC0, 0xCC, 0x98, 0x31,
247 0x0C, 0x00, 0xCC, 0x18, 0x30, 0x0C, 0xC3, 0x80, 0x01, 0x00, 0x03, 0x66, 0xFE,
248 0x18, 0x30, 0x00, 0xC0, 0x02, 0x06, 0x06, 0x00, 0x18, 0x8C, 0x01, 0x60, 0xE0,
249 0x0F, 0x86, 0x3F, 0x03, 0x18, 0x00, 0x30, 0x33, 0x66, 0x0C, 0x03, 0x00, 0x33,
250 0xFE, 0x0C, 0xC3, 0x30, 0xE0, 0x0F, 0xC0, 0x87, 0x9B, 0x31, 0x63, 0xC6, 0x00,
251 0xF0, 0x80, 0x01, 0x03, 0x00, 0x06, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
252 0x18, 0x06, 0x00, 0x6C, 0x8C, 0x19, 0xC3, 0x00, 0x80, 0x8D, 0x31, 0xC3, 0x30,
253 0x8C, 0x19, 0x03, 0x30, 0xB3, 0xC3, 0x87, 0x0F, 0x1F, 0x00, 0x2C, 0x60, 0x80,
254 0x01, 0xE0, 0x87, 0x0F, 0x00, 0x3E, 0x7C, 0x60, 0xF0, 0xE1, 0xE3, 0x07, 0x00,
255 0x0F, 0x3E, 0x7C, 0xFC, 0x00, 0xC0, 0xC3, 0xC7, 0x30, 0x0E, 0x3E, 0x7C, 0x00,
256 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x1E, 0xC0, 0x00, 0x60, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x00, 0x00,
258 0x0C, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0xC0, 0x0C, 0x87, 0x31, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x30,
261 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0xF8, 0x83, 0xC1, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00,
263 0x00, 0x04, 0x00, 0x0E, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x30,
264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
267#else
268 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
269 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
270 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xF8, 0xF0, 0x83,
271 0x07, 0x0F, 0xFE, 0x1F, 0x7E, 0x60, 0xC0, 0xFF, 0x8F, 0x07, 0xFF, 0x1F, 0x3C,
272 0xF8, 0xF0, 0xE0, 0xC1, 0x8F, 0xFF, 0x0F, 0x1E, 0x3C, 0xF8, 0xF1, 0xFF, 0x91,
273 0x83, 0x9F, 0x1F, 0x1E, 0x3C, 0xF8, 0x39, 0x7F, 0x7E, 0xCE, 0x9C, 0x39, 0xFF,
274 0xCF, 0x7F, 0x9E, 0xF3, 0xFF, 0xC9, 0x9C, 0xFF, 0x73, 0xE6, 0x7C, 0x9E, 0x33,
275 0xE7, 0xC9, 0xFF, 0x33, 0x73, 0xE6, 0x3C, 0xF9, 0x3F, 0x73, 0xCE, 0xC3, 0xCF,
276 0x73, 0xE6, 0x7C, 0xCE, 0x9F, 0x9F, 0xFF, 0xF3, 0xE7, 0xFF, 0xF3, 0x9F, 0xE7,
277 0xFF, 0x7F, 0x3E, 0xE7, 0xFF, 0xCF, 0xF9, 0x9F, 0xE7, 0xCF, 0x7F, 0xFE, 0xFF,
278 0xCC, 0x9C, 0x39, 0xCF, 0xFF, 0xCF, 0x9C, 0x7F, 0xE6, 0xF3, 0xFC, 0xF9, 0xFF,
279 0xF3, 0xE7, 0xE7, 0x3F, 0x7E, 0xFC, 0xFF, 0xFC, 0xE7, 0xF3, 0xFF, 0x9F, 0xCF,
280 0xF9, 0xFF, 0x78, 0xFE, 0xE7, 0xF9, 0xF3, 0x9F, 0xFF, 0x3F, 0x33, 0x67, 0xCE,
281 0xF3, 0xFF, 0x33, 0xE7, 0xCF, 0xF3, 0x3C, 0x7F, 0xFE, 0xFF, 0xFC, 0x99, 0x01,
282 0xE7, 0xCF, 0xFF, 0x3F, 0xFD, 0xF9, 0xF9, 0xFF, 0xE7, 0x73, 0xFE, 0x9F, 0x1F,
283 0xF0, 0x79, 0xC0, 0xFC, 0xE7, 0xFF, 0xCF, 0xCC, 0x99, 0xF3, 0xFC, 0xFF, 0xCC,
284 0x01, 0xF3, 0x3C, 0xCF, 0x1F, 0xF0, 0x3F, 0x78, 0x64, 0xCE, 0x9C, 0x39, 0xFF,
285 0x0F, 0x7F, 0xFE, 0xFC, 0xFF, 0xF9, 0x9C, 0xFF, 0x73, 0xE6, 0x7C, 0x9E, 0x33,
286 0xE7, 0xF9, 0xFF, 0x93, 0x73, 0xE6, 0x3C, 0xFF, 0x7F, 0x72, 0xCE, 0x3C, 0xCF,
287 0x73, 0xE6, 0xFC, 0xCF, 0x4C, 0x3C, 0x78, 0xF0, 0xE0, 0xFF, 0xD3, 0x9F, 0x7F,
288 0xFE, 0x1F, 0x78, 0xF0, 0xFF, 0xC1, 0x83, 0x9F, 0x0F, 0x1E, 0x1C, 0xF8, 0xFF,
289 0xF0, 0xC1, 0x83, 0x03, 0xFF, 0x3F, 0x3C, 0x38, 0xCF, 0xF1, 0xC1, 0x83, 0xFF,
290 0x33, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDC, 0xE1, 0x3F, 0xFF, 0x9F, 0xFF,
291 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0x9F, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF,
292 0xF3, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCC, 0xFF, 0xFF,
293 0xFF, 0xFF, 0xFF, 0x3F, 0xF3, 0x78, 0xCE, 0xFF, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF,
294 0xFF, 0xF9, 0xFF, 0xFF, 0xE7, 0xFF, 0xCF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xCF,
295 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0x1F, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
296 0x07, 0x7C, 0x3E, 0xF8, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0xFE, 0xFF,
297 0xFF, 0xFB, 0xFF, 0xF1, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, 0xCF,
298 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
299 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
300 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
301#endif
302};
303
304
305#ifndef VBOX_DEVICE_STRUCT_TESTCASE
306/*******************************************************************************
307* Internal Functions *
308*******************************************************************************/
309__BEGIN_DECLS
310
311PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
312PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
313PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
314PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
315PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
316PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
317PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems);
318PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
319PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
320#ifdef IN_GC
321PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
322#endif
323#ifdef IN_RING0
324PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
325#endif
326#ifdef IN_RING3
327# ifdef VBE_NEW_DYN_LIST
328PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
329PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
330# endif
331PDMBOTHCBDECL(int) vbeIOPortReadCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
332PDMBOTHCBDECL(int) vbeIOPortWriteCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
333#endif /* IN_RING3 */
334
335
336__END_DECLS
337
338
339/**
340 * Set a VRAM page dirty.
341 *
342 * @param pData VGA instance data.
343 * @param offVRAM The VRAM offset of the page to set.
344 */
345DECLINLINE(void) vga_set_dirty(VGAState *pData, RTGCPHYS offVRAM)
346{
347 AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
348 ASMBitSet(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
349 pData->fHaveDirtyBits = true;
350}
351
352/**
353 * Tests if a VRAM page is dirty.
354 *
355 * @returns true if dirty.
356 * @returns false if clean.
357 * @param pData VGA instance data.
358 * @param offVRAM The VRAM offset of the page to check.
359 */
360DECLINLINE(bool) vga_is_dirty(VGAState *pData, RTGCPHYS offVRAM)
361{
362 AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
363 return ASMBitTest(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
364}
365
366/**
367 * Reset dirty flags in a give range.
368 *
369 * @param pData VGA instance data.
370 * @param offVRAMStart Offset into the VRAM buffer of the first page.
371 * @param offVRAMEnd Offset into the VRAM buffer of the last page - exclusive.
372 */
373DECLINLINE(void) vga_reset_dirty(VGAState *pData, RTGCPHYS offVRAMStart, RTGCPHYS offVRAMEnd)
374{
375 Assert(offVRAMStart < pData->vram_size);
376 Assert(offVRAMEnd <= pData->vram_size);
377 Assert(offVRAMStart < offVRAMEnd);
378 ASMBitClearRange(&pData->au32DirtyBitmap[0], offVRAMStart >> PAGE_SHIFT, offVRAMEnd >> PAGE_SHIFT);
379}
380
381#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
382#endif /* VBOX */
383#ifndef VBOX_DEVICE_STRUCT_TESTCASE
384
385#ifndef VBOX
386#include "vl.h"
387#include "vga_int.h"
388#endif /* !VBOX */
389
390#ifdef LOG_ENABLED
391//#define DEBUG_VGA
392//#define DEBUG_VGA_MEM
393//#define DEBUG_VGA_REG
394
395#define DEBUG_BOCHS_VBE
396
397#endif
398
399/* force some bits to zero */
400#ifdef VBOX
401static
402#endif /* VBOX */
403const uint8_t sr_mask[8] = {
404 (uint8_t)~0xfc,
405 (uint8_t)~0xc2,
406 (uint8_t)~0xf0,
407 (uint8_t)~0xc0,
408 (uint8_t)~0xf1,
409 (uint8_t)~0xff,
410 (uint8_t)~0xff,
411 (uint8_t)~0x00,
412};
413
414#ifdef VBOX
415static
416#endif /* VBOX */
417const uint8_t gr_mask[16] = {
418 (uint8_t)~0xf0, /* 0x00 */
419 (uint8_t)~0xf0, /* 0x01 */
420 (uint8_t)~0xf0, /* 0x02 */
421 (uint8_t)~0xe0, /* 0x03 */
422 (uint8_t)~0xfc, /* 0x04 */
423 (uint8_t)~0x84, /* 0x05 */
424 (uint8_t)~0xf0, /* 0x06 */
425 (uint8_t)~0xf0, /* 0x07 */
426 (uint8_t)~0x00, /* 0x08 */
427 (uint8_t)~0xff, /* 0x09 */
428 (uint8_t)~0xff, /* 0x0a */
429 (uint8_t)~0xff, /* 0x0b */
430 (uint8_t)~0xff, /* 0x0c */
431 (uint8_t)~0xff, /* 0x0d */
432 (uint8_t)~0xff, /* 0x0e */
433 (uint8_t)~0xff, /* 0x0f */
434};
435
436#define cbswap_32(__x) \
437((uint32_t)( \
438 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
439 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
440 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
441 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
442
443#ifdef WORDS_BIGENDIAN
444#define PAT(x) cbswap_32(x)
445#else
446#define PAT(x) (x)
447#endif
448
449#ifdef WORDS_BIGENDIAN
450#define BIG 1
451#else
452#define BIG 0
453#endif
454
455#ifdef WORDS_BIGENDIAN
456#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
457#else
458#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
459#endif
460
461static const uint32_t mask16[16] = {
462 PAT(0x00000000),
463 PAT(0x000000ff),
464 PAT(0x0000ff00),
465 PAT(0x0000ffff),
466 PAT(0x00ff0000),
467 PAT(0x00ff00ff),
468 PAT(0x00ffff00),
469 PAT(0x00ffffff),
470 PAT(0xff000000),
471 PAT(0xff0000ff),
472 PAT(0xff00ff00),
473 PAT(0xff00ffff),
474 PAT(0xffff0000),
475 PAT(0xffff00ff),
476 PAT(0xffffff00),
477 PAT(0xffffffff),
478};
479
480#undef PAT
481
482#ifdef WORDS_BIGENDIAN
483#define PAT(x) (x)
484#else
485#define PAT(x) cbswap_32(x)
486#endif
487
488static const uint32_t dmask16[16] = {
489 PAT(0x00000000),
490 PAT(0x000000ff),
491 PAT(0x0000ff00),
492 PAT(0x0000ffff),
493 PAT(0x00ff0000),
494 PAT(0x00ff00ff),
495 PAT(0x00ffff00),
496 PAT(0x00ffffff),
497 PAT(0xff000000),
498 PAT(0xff0000ff),
499 PAT(0xff00ff00),
500 PAT(0xff00ffff),
501 PAT(0xffff0000),
502 PAT(0xffff00ff),
503 PAT(0xffffff00),
504 PAT(0xffffffff),
505};
506
507static const uint32_t dmask4[4] = {
508 PAT(0x00000000),
509 PAT(0x0000ffff),
510 PAT(0xffff0000),
511 PAT(0xffffffff),
512};
513
514#if defined(VBOX) && defined(IN_RING3)
515static uint32_t expand4[256];
516static uint16_t expand2[256];
517static uint8_t expand4to8[16];
518#endif /* VBOX && IN_RING3 */
519
520#ifndef VBOX
521VGAState *vga_state;
522int vga_io_memory;
523#endif /* !VBOX */
524
525static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
526{
527 VGAState *s = (VGAState*)opaque;
528 int val, index;
529
530 /* check port range access depending on color/monochrome mode */
531 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
532 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
533 val = 0xff;
534 Log(("VGA: following read ignored\n"));
535 } else {
536 switch(addr) {
537 case 0x3c0:
538 if (s->ar_flip_flop == 0) {
539 val = s->ar_index;
540 } else {
541 val = 0;
542 }
543 break;
544 case 0x3c1:
545 index = s->ar_index & 0x1f;
546 if (index < 21)
547 val = s->ar[index];
548 else
549 val = 0;
550 break;
551 case 0x3c2:
552 val = s->st00;
553 break;
554 case 0x3c4:
555 val = s->sr_index;
556 break;
557 case 0x3c5:
558 val = s->sr[s->sr_index];
559#ifdef DEBUG_VGA_REG
560 Log(("vga: read SR%x = 0x%02x\n", s->sr_index, val));
561#endif
562 break;
563 case 0x3c7:
564 val = s->dac_state;
565 break;
566 case 0x3c8:
567 val = s->dac_write_index;
568 break;
569 case 0x3c9:
570 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
571 if (++s->dac_sub_index == 3) {
572 s->dac_sub_index = 0;
573 s->dac_read_index++;
574 }
575 break;
576 case 0x3ca:
577 val = s->fcr;
578 break;
579 case 0x3cc:
580 val = s->msr;
581 break;
582 case 0x3ce:
583 val = s->gr_index;
584 break;
585 case 0x3cf:
586 val = s->gr[s->gr_index];
587#ifdef DEBUG_VGA_REG
588 Log(("vga: read GR%x = 0x%02x\n", s->gr_index, val));
589#endif
590 break;
591 case 0x3b4:
592 case 0x3d4:
593 val = s->cr_index;
594 break;
595 case 0x3b5:
596 case 0x3d5:
597 val = s->cr[s->cr_index];
598#ifdef DEBUG_VGA_REG
599 Log(("vga: read CR%x = 0x%02x\n", s->cr_index, val));
600#endif
601 break;
602 case 0x3ba:
603 case 0x3da:
604 /* just toggle to fool polling */
605 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
606 val = s->st01;
607 s->ar_flip_flop = 0;
608 break;
609 default:
610 val = 0x00;
611 break;
612 }
613 }
614#if defined(DEBUG_VGA)
615 Log(("VGA: read addr=0x%04x data=0x%02x\n", addr, val));
616#endif
617 return val;
618}
619
620static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
621{
622 VGAState *s = (VGAState*)opaque;
623 int index;
624
625#ifdef DEBUG_VGA
626 Log(("VGA: write addr=0x%04x data=0x%02x\n", addr, val));
627#endif
628
629 /* check port range access depending on color/monochrome mode */
630 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
631 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
632 Log(("VGA: previous write ignored\n"));
633 return;
634 }
635
636 switch(addr) {
637 case 0x3c0:
638 if (s->ar_flip_flop == 0) {
639 val &= 0x3f;
640 s->ar_index = val;
641 } else {
642 index = s->ar_index & 0x1f;
643 switch(index) {
644#ifndef VBOX
645 case 0x00 ... 0x0f:
646#else /* VBOX */
647 case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
648 case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
649#endif /* VBOX */
650 s->ar[index] = val & 0x3f;
651 break;
652 case 0x10:
653 s->ar[index] = val & ~0x10;
654 break;
655 case 0x11:
656 s->ar[index] = val;
657 break;
658 case 0x12:
659 s->ar[index] = val & ~0xc0;
660 break;
661 case 0x13:
662 s->ar[index] = val & ~0xf0;
663 break;
664 case 0x14:
665 s->ar[index] = val & ~0xf0;
666 break;
667 default:
668 break;
669 }
670 }
671 s->ar_flip_flop ^= 1;
672 break;
673 case 0x3c2:
674 s->msr = val & ~0x10;
675 break;
676 case 0x3c4:
677 s->sr_index = val & 7;
678 break;
679 case 0x3c5:
680#ifdef DEBUG_VGA_REG
681 Log(("vga: write SR%x = 0x%02x\n", s->sr_index, val));
682#endif
683 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
684 break;
685 case 0x3c7:
686 s->dac_read_index = val;
687 s->dac_sub_index = 0;
688 s->dac_state = 3;
689 break;
690 case 0x3c8:
691 s->dac_write_index = val;
692 s->dac_sub_index = 0;
693 s->dac_state = 0;
694 break;
695 case 0x3c9:
696 s->dac_cache[s->dac_sub_index] = val;
697 if (++s->dac_sub_index == 3) {
698 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
699 s->dac_sub_index = 0;
700 s->dac_write_index++;
701 }
702 break;
703 case 0x3ce:
704 s->gr_index = val & 0x0f;
705 break;
706 case 0x3cf:
707#ifdef DEBUG_VGA_REG
708 Log(("vga: write GR%x = 0x%02x\n", s->gr_index, val));
709#endif
710 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
711 break;
712 case 0x3b4:
713 case 0x3d4:
714 s->cr_index = val;
715 break;
716 case 0x3b5:
717 case 0x3d5:
718#ifdef DEBUG_VGA_REG
719 Log(("vga: write CR%x = 0x%02x\n", s->cr_index, val));
720#endif
721 /* handle CR0-7 protection */
722 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
723 /* can always write bit 4 of CR7 */
724 if (s->cr_index == 7)
725 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
726 return;
727 }
728 switch(s->cr_index) {
729 case 0x01: /* horizontal display end */
730 case 0x07:
731 case 0x09:
732 case 0x0c:
733 case 0x0d:
734 case 0x12: /* veritcal display end */
735 s->cr[s->cr_index] = val;
736 break;
737
738 default:
739 s->cr[s->cr_index] = val;
740 break;
741 }
742 break;
743 case 0x3ba:
744 case 0x3da:
745 s->fcr = val & 0x10;
746 break;
747 }
748}
749
750#ifdef CONFIG_BOCHS_VBE
751static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
752{
753 VGAState *s = (VGAState*)opaque;
754 uint32_t val;
755 val = s->vbe_index;
756 return val;
757}
758
759static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
760{
761 VGAState *s = (VGAState*)opaque;
762 uint32_t val;
763
764 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
765 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
766 switch(s->vbe_index) {
767 /* XXX: do not hardcode ? */
768 case VBE_DISPI_INDEX_XRES:
769 val = VBE_DISPI_MAX_XRES;
770 break;
771 case VBE_DISPI_INDEX_YRES:
772 val = VBE_DISPI_MAX_YRES;
773 break;
774 case VBE_DISPI_INDEX_BPP:
775 val = VBE_DISPI_MAX_BPP;
776 break;
777 default:
778 val = s->vbe_regs[s->vbe_index];
779 break;
780 }
781 } else if (s->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO) {
782 /* Reading from the port means that the old additions are requesting the number of monitors. */
783 val = 1;
784 } else {
785 val = s->vbe_regs[s->vbe_index];
786 }
787 } else {
788 val = 0;
789 }
790#ifdef DEBUG_BOCHS_VBE
791 Log(("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val));
792#endif
793 return val;
794}
795
796static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
797{
798 VGAState *s = (VGAState*)opaque;
799 s->vbe_index = val;
800}
801
802static int vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
803{
804 VGAState *s = (VGAState*)opaque;
805
806 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
807#ifdef DEBUG_BOCHS_VBE
808 Log(("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val));
809#endif
810 switch(s->vbe_index) {
811 case VBE_DISPI_INDEX_ID:
812 if (val == VBE_DISPI_ID0 ||
813 val == VBE_DISPI_ID1 ||
814 val == VBE_DISPI_ID2 ||
815 val == VBE_DISPI_ID3 ||
816 val == VBE_DISPI_ID4) {
817 s->vbe_regs[s->vbe_index] = val;
818 }
819#ifdef VBOX
820 if (val == VBE_DISPI_ID_VBOX_VIDEO) {
821 s->vbe_regs[s->vbe_index] = val;
822 }
823#endif /* VBOX */
824 break;
825 case VBE_DISPI_INDEX_XRES:
826 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
827 s->vbe_regs[s->vbe_index] = val;
828#ifdef KEEP_SCAN_LINE_LENGTH
829 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
830 s->vbe_line_offset = val >> 1;
831 else
832 s->vbe_line_offset = val * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
833 /* XXX: support weird bochs semantics ? */
834 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
835 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
836 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
837 s->vbe_start_addr = 0;
838#endif /* KEEP_SCAN_LINE_LENGTH defined */
839 }
840 break;
841 case VBE_DISPI_INDEX_YRES:
842 if (val <= VBE_DISPI_MAX_YRES) {
843 s->vbe_regs[s->vbe_index] = val;
844#ifdef KEEP_SCAN_LINE_LENGTH
845 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = val;
846 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
847 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
848 s->vbe_start_addr = 0;
849#endif /* KEEP_SCAN_LINE_LENGTH defined */
850 }
851 break;
852 case VBE_DISPI_INDEX_BPP:
853 if (val == 0)
854 val = 8;
855 if (val == 4 || val == 8 || val == 15 ||
856 val == 16 || val == 24 || val == 32) {
857 s->vbe_regs[s->vbe_index] = val;
858#ifdef KEEP_SCAN_LINE_LENGTH
859 if (val == 4)
860 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
861 else
862 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((val + 7) >> 3);
863 /* XXX: support weird bochs semantics ? */
864 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
865 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
866 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
867 s->vbe_start_addr = 0;
868#endif /* KEEP_SCAN_LINE_LENGTH defined */
869 }
870 break;
871 case VBE_DISPI_INDEX_BANK:
872 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
873 val &= (s->vbe_bank_mask >> 2);
874 } else {
875 val &= s->vbe_bank_mask;
876 }
877 val &= s->vbe_bank_mask;
878 s->vbe_regs[s->vbe_index] = val;
879 s->bank_offset = (val << 16);
880 break;
881 case VBE_DISPI_INDEX_ENABLE:
882#ifndef IN_RING3
883 return VINF_IOM_HC_IOPORT_WRITE;
884#else
885 if ((val & VBE_DISPI_ENABLED) &&
886 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
887 int h, shift_control;
888#ifdef VBOX
889 /* Check the values before we screw up with a resolution which is too big or small. */
890 size_t cb = s->vbe_regs[VBE_DISPI_INDEX_XRES];
891 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
892 cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
893 else
894 cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
895 cb *= s->vbe_regs[VBE_DISPI_INDEX_YRES];
896#ifndef KEEP_SCAN_LINE_LENGTH
897 if ( !s->vbe_regs[VBE_DISPI_INDEX_XRES]
898 || !s->vbe_regs[VBE_DISPI_INDEX_YRES]
899 || cb > s->vram_size)
900 {
901 AssertMsgFailed(("XRES=%d YRES=%d cb=%d vram_size=%d\n",
902 s->vbe_regs[VBE_DISPI_INDEX_XRES], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
903 return VINF_SUCCESS; /* Note: silent failure like before */
904 }
905#else /* KEEP_SCAN_LINE_LENGTH defined */
906 if ( !s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH]
907 || !s->vbe_regs[VBE_DISPI_INDEX_YRES]
908 || cb > s->vram_size)
909 {
910 AssertMsgFailed(("VIRT WIDTH=%d YRES=%d cb=%d vram_size=%d\n",
911 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
912 return VINF_SUCCESS; /* Note: silent failure like before */
913 }
914#endif /* KEEP_SCAN_LINE_LENGTH defined */
915#endif /* VBOX */
916
917#ifndef KEEP_SCAN_LINE_LENGTH
918 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
919 s->vbe_regs[VBE_DISPI_INDEX_XRES];
920 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
921 s->vbe_regs[VBE_DISPI_INDEX_YRES];
922 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
923 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
924
925 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
926 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
927 else
928 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
929 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
930 s->vbe_start_addr = 0;
931#endif /* KEEP_SCAN_LINE_LENGTH not defined */
932
933 /* clear the screen (should be done in BIOS) */
934 if (!(val & VBE_DISPI_NOCLEARMEM)) {
935#ifndef VBOX
936 memset(s->vram_ptr, 0,
937 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
938#else /* VBOX */
939 memset(CTXSUFF(s->vram_ptr), 0,
940 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
941#endif /* VBOX */
942 }
943
944 /* we initialize the VGA graphic mode (should be done
945 in BIOS) */
946 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
947 s->cr[0x17] |= 3; /* no CGA modes */
948 s->cr[0x13] = s->vbe_line_offset >> 3;
949 /* width */
950 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
951 /* height (only meaningful if < 1024) */
952 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
953 s->cr[0x12] = h;
954 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
955 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
956 /* line compare to 1023 */
957 s->cr[0x18] = 0xff;
958 s->cr[0x07] |= 0x10;
959 s->cr[0x09] |= 0x40;
960
961 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
962 shift_control = 0;
963 s->sr[0x01] &= ~8; /* no double line */
964 } else {
965 shift_control = 2;
966 s->sr[4] |= 0x08; /* set chain 4 mode */
967 s->sr[2] |= 0x0f; /* activate all planes */
968 }
969 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
970 s->cr[0x09] &= ~0x9f; /* no double scan */
971#ifdef VBOX
972 /* sunlover 30.05.2007
973 * The ar_index remains with bit 0x20 cleared after a switch from fullscreen
974 * DOS mode on Windows XP guest. That leads to GMODE_BLANK in vga_update_display.
975 * But the VBE mode is graphics, so not a blank anymore.
976 */
977 s->ar_index |= 0x20;
978#endif /* VBOX */
979 } else {
980 /* XXX: the bios should do that */
981#ifdef VBOX
982 /* sunlover 21.12.2006
983 * Here is probably more to reset. When this was executed in GC
984 * then the *update* functions could not detect a mode change.
985 * Or may be these update function should take the s->vbe_regs[s->vbe_index]
986 * into account when detecting a mode change.
987 *
988 * The 'mode reset not detected' problem is now fixed by executing the
989 * VBE_DISPI_INDEX_ENABLE case always in RING3 in order to call the
990 * LFBChange callback.
991 */
992#endif /* VBOX */
993 s->bank_offset = 0;
994 }
995 s->vbe_regs[s->vbe_index] = val;
996 /*
997 * LFB video mode is either disabled or changed. This notification
998 * is used by the display to disable VBVA.
999 */
1000 s->pDrv->pfnLFBModeChange(s->pDrv, (val & VBE_DISPI_ENABLED) != 0);
1001 break;
1002#endif /* IN_RING3 */
1003 case VBE_DISPI_INDEX_VIRT_WIDTH:
1004 {
1005 int w, h, line_offset;
1006
1007 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
1008 return VINF_SUCCESS;
1009 w = val;
1010 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
1011 line_offset = w >> 1;
1012 else
1013 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
1014 h = s->vram_size / line_offset;
1015 /* XXX: support weird bochs semantics ? */
1016 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
1017 return VINF_SUCCESS;
1018 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
1019 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
1020 s->vbe_line_offset = line_offset;
1021 }
1022 break;
1023 case VBE_DISPI_INDEX_X_OFFSET:
1024 case VBE_DISPI_INDEX_Y_OFFSET:
1025 {
1026 int x;
1027 s->vbe_regs[s->vbe_index] = val;
1028 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
1029 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
1030 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
1031 s->vbe_start_addr += x >> 1;
1032 else
1033 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
1034 s->vbe_start_addr >>= 2;
1035 }
1036 break;
1037 case VBE_DISPI_INDEX_VBOX_VIDEO:
1038#ifdef VBOX
1039#ifndef IN_RING3
1040 return VINF_IOM_HC_IOPORT_WRITE;
1041#else
1042 /* Changes in the VGA device are minimal. The device is bypassed. The driver does all work. */
1043 if (val == VBOX_VIDEO_DISABLE_ADAPTER_MEMORY)
1044 {
1045 s->pDrv->pfnProcessAdapterData(s->pDrv, NULL, 0);
1046 }
1047 else if (val == VBOX_VIDEO_INTERPRET_ADAPTER_MEMORY)
1048 {
1049 s->pDrv->pfnProcessAdapterData(s->pDrv, s->CTXSUFF(vram_ptr), s->vram_size);
1050 }
1051 else if ((val & 0xFFFF0000) == VBOX_VIDEO_INTERPRET_DISPLAY_MEMORY_BASE)
1052 {
1053 s->pDrv->pfnProcessDisplayData(s->pDrv, s->CTXSUFF(vram_ptr), val & 0xFFFF);
1054 }
1055#endif /* IN_RING3 */
1056#endif /* VBOX */
1057 break;
1058 default:
1059 break;
1060 }
1061 }
1062 return VINF_SUCCESS;
1063}
1064#endif
1065
1066/* called for accesses between 0xa0000 and 0xc0000 */
1067#ifdef VBOX
1068static
1069#endif /* VBOX */
1070uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
1071{
1072 VGAState *s = (VGAState*)opaque;
1073 int memory_map_mode, plane;
1074 uint32_t ret;
1075
1076#ifdef DEBUG_VGA_MEM
1077 Log(("vga: read [0x%x] -> ", addr));
1078#endif
1079 /* convert to VGA memory offset */
1080 memory_map_mode = (s->gr[6] >> 2) & 3;
1081 addr &= 0x1ffff;
1082 switch(memory_map_mode) {
1083 case 0:
1084 break;
1085 case 1:
1086 if (addr >= 0x10000)
1087 return 0xff;
1088 addr += s->bank_offset;
1089 break;
1090 case 2:
1091 addr -= 0x10000;
1092 if (addr >= 0x8000)
1093 return 0xff;
1094 break;
1095 default:
1096 case 3:
1097 addr -= 0x18000;
1098 if (addr >= 0x8000)
1099 return 0xff;
1100 break;
1101 }
1102
1103#ifdef IN_GC
1104 if (addr >= VGA_MAPPING_SIZE)
1105 return VINF_IOM_HC_MMIO_WRITE;
1106#endif
1107
1108 if (s->sr[4] & 0x08) {
1109 /* chain 4 mode : simplest access */
1110#ifndef VBOX
1111 ret = s->vram_ptr[addr];
1112#else /* VBOX */
1113 ret = s->CTXSUFF(vram_ptr)[addr];
1114#endif /* VBOX */
1115 } else if (!(s->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1116 /* odd/even mode (aka text mode mapping) */
1117 plane = (s->gr[4] & 2) | (addr & 1);
1118#ifndef VBOX
1119 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
1120#else /* VBOX */
1121 /* See the comment for a similar line in vga_mem_writeb. */
1122 ret = s->CTXSUFF(vram_ptr)[((addr & ~1) << 2) | plane];
1123#endif /* VBOX */
1124 } else {
1125 /* standard VGA latched access */
1126#ifndef VBOX
1127 s->latch = ((uint32_t *)s->vram_ptr)[addr];
1128#else /* VBOX && IN_GC */
1129 s->latch = ((uint32_t *)s->CTXSUFF(vram_ptr))[addr];
1130#endif /* VBOX && IN_GC */
1131
1132 if (!(s->gr[5] & 0x08)) {
1133 /* read mode 0 */
1134 plane = s->gr[4];
1135 ret = GET_PLANE(s->latch, plane);
1136 } else {
1137 /* read mode 1 */
1138 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
1139 ret |= ret >> 16;
1140 ret |= ret >> 8;
1141 ret = (~ret) & 0xff;
1142 }
1143 }
1144#ifdef DEBUG_VGA_MEM
1145 Log((" 0x%02x\n", ret));
1146#endif
1147 return ret;
1148}
1149
1150#ifndef VBOX
1151static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
1152{
1153 uint32_t v;
1154#ifdef TARGET_WORDS_BIGENDIAN
1155 v = vga_mem_readb(opaque, addr) << 8;
1156 v |= vga_mem_readb(opaque, addr + 1);
1157#else
1158 v = vga_mem_readb(opaque, addr);
1159 v |= vga_mem_readb(opaque, addr + 1) << 8;
1160#endif
1161 return v;
1162}
1163
1164static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
1165{
1166 uint32_t v;
1167#ifdef TARGET_WORDS_BIGENDIAN
1168 v = vga_mem_readb(opaque, addr) << 24;
1169 v |= vga_mem_readb(opaque, addr + 1) << 16;
1170 v |= vga_mem_readb(opaque, addr + 2) << 8;
1171 v |= vga_mem_readb(opaque, addr + 3);
1172#else
1173 v = vga_mem_readb(opaque, addr);
1174 v |= vga_mem_readb(opaque, addr + 1) << 8;
1175 v |= vga_mem_readb(opaque, addr + 2) << 16;
1176 v |= vga_mem_readb(opaque, addr + 3) << 24;
1177#endif
1178 return v;
1179}
1180#endif /* !VBOX */
1181
1182/* called for accesses between 0xa0000 and 0xc0000 */
1183#ifdef VBOX
1184static
1185#endif /* VBOX */
1186int vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1187{
1188 VGAState *s = (VGAState*)opaque;
1189 int memory_map_mode, plane, write_mode, b, func_select, mask;
1190 uint32_t write_mask, bit_mask, set_mask;
1191
1192#ifdef DEBUG_VGA_MEM
1193 Log(("vga: [0x%x] = 0x%02x\n", addr, val));
1194#endif
1195 /* convert to VGA memory offset */
1196 memory_map_mode = (s->gr[6] >> 2) & 3;
1197 addr &= 0x1ffff;
1198 switch(memory_map_mode) {
1199 case 0:
1200 break;
1201 case 1:
1202 if (addr >= 0x10000)
1203 return VINF_SUCCESS;
1204 addr += s->bank_offset;
1205 break;
1206 case 2:
1207 addr -= 0x10000;
1208 if (addr >= 0x8000)
1209 return VINF_SUCCESS;
1210 break;
1211 default:
1212 case 3:
1213 addr -= 0x18000;
1214 if (addr >= 0x8000)
1215 return VINF_SUCCESS;
1216 break;
1217 }
1218
1219 if (s->sr[4] & 0x08) {
1220 /* chain 4 mode : simplest access */
1221 plane = addr & 3;
1222 mask = (1 << plane);
1223 if (s->sr[2] & mask) {
1224#ifndef VBOX
1225 s->vram_ptr[addr] = val;
1226#else /* VBOX */
1227#ifdef IN_GC
1228 if (addr >= VGA_MAPPING_SIZE)
1229 return VINF_IOM_HC_MMIO_WRITE;
1230#else
1231 if (addr >= s->vram_size)
1232 {
1233 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1234 addr, s->bank_offset, memory_map_mode));
1235 return VINF_SUCCESS;
1236 }
1237#endif
1238 s->CTXSUFF(vram_ptr)[addr] = val;
1239#endif /* VBOX */
1240#ifdef DEBUG_VGA_MEM
1241 Log(("vga: chain4: [0x%x]\n", addr));
1242#endif
1243 s->plane_updated |= mask; /* only used to detect font change */
1244#ifndef VBOX
1245 cpu_physical_memory_set_dirty(s->vram_offset + addr);
1246#else /* VBOX */
1247 vga_set_dirty(s, addr);
1248#endif /* VBOX */
1249 }
1250 } else if (!(s->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1251 /* odd/even mode (aka text mode mapping) */
1252 plane = (s->gr[4] & 2) | (addr & 1);
1253 mask = (1 << plane);
1254 if (s->sr[2] & mask) {
1255#ifndef VBOX
1256 addr = ((addr & ~1) << 1) | plane;
1257#else
1258 /* 'addr' is offset in a plane, bit 0 selects the plane.
1259 * Mask the bit 0, convert plane index to vram offset,
1260 * that is multiply by the number of planes,
1261 * and select the plane byte in the vram offset.
1262 */
1263 addr = ((addr & ~1) << 2) | plane;
1264#endif /* VBOX */
1265#ifndef VBOX
1266 s->vram_ptr[addr] = val;
1267#else /* VBOX */
1268#ifdef IN_GC
1269 if (addr >= VGA_MAPPING_SIZE)
1270 return VINF_IOM_HC_MMIO_WRITE;
1271#else
1272 if (addr >= s->vram_size)
1273 {
1274 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1275 addr, s->bank_offset, memory_map_mode));
1276 return VINF_SUCCESS;
1277 }
1278#endif
1279 s->CTXSUFF(vram_ptr)[addr] = val;
1280#endif /* VBOX */
1281#ifdef DEBUG_VGA_MEM
1282 Log(("vga: odd/even: [0x%x]\n", addr));
1283#endif
1284 s->plane_updated |= mask; /* only used to detect font change */
1285#ifndef VBOX
1286 cpu_physical_memory_set_dirty(s->vram_offset + addr);
1287#else /* VBOX */
1288 vga_set_dirty(s, addr);
1289#endif /* VBOX */
1290 }
1291 } else {
1292#ifdef IN_GC
1293 if (addr * 4 >= VGA_MAPPING_SIZE)
1294 return VINF_IOM_HC_MMIO_WRITE;
1295#else
1296 if (addr * 4 >= s->vram_size)
1297 {
1298 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1299 addr * 4, s->bank_offset, memory_map_mode));
1300 return VINF_SUCCESS;
1301 }
1302#endif
1303
1304 /* standard VGA latched access */
1305 write_mode = s->gr[5] & 3;
1306 switch(write_mode) {
1307 default:
1308 case 0:
1309 /* rotate */
1310 b = s->gr[3] & 7;
1311 val = ((val >> b) | (val << (8 - b))) & 0xff;
1312 val |= val << 8;
1313 val |= val << 16;
1314
1315 /* apply set/reset mask */
1316 set_mask = mask16[s->gr[1]];
1317 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
1318 bit_mask = s->gr[8];
1319 break;
1320 case 1:
1321 val = s->latch;
1322 goto do_write;
1323 case 2:
1324 val = mask16[val & 0x0f];
1325 bit_mask = s->gr[8];
1326 break;
1327 case 3:
1328 /* rotate */
1329 b = s->gr[3] & 7;
1330 val = (val >> b) | (val << (8 - b));
1331
1332 bit_mask = s->gr[8] & val;
1333 val = mask16[s->gr[0]];
1334 break;
1335 }
1336
1337 /* apply logical operation */
1338 func_select = s->gr[3] >> 3;
1339 switch(func_select) {
1340 case 0:
1341 default:
1342 /* nothing to do */
1343 break;
1344 case 1:
1345 /* and */
1346 val &= s->latch;
1347 break;
1348 case 2:
1349 /* or */
1350 val |= s->latch;
1351 break;
1352 case 3:
1353 /* xor */
1354 val ^= s->latch;
1355 break;
1356 }
1357
1358 /* apply bit mask */
1359 bit_mask |= bit_mask << 8;
1360 bit_mask |= bit_mask << 16;
1361 val = (val & bit_mask) | (s->latch & ~bit_mask);
1362
1363 do_write:
1364 /* mask data according to sr[2] */
1365 mask = s->sr[2];
1366 s->plane_updated |= mask; /* only used to detect font change */
1367 write_mask = mask16[mask];
1368#ifndef VBOX
1369 ((uint32_t *)s->vram_ptr)[addr] =
1370 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
1371 (val & write_mask);
1372#else /* VBOX */
1373 ((uint32_t *)s->CTXSUFF(vram_ptr))[addr] =
1374 (((uint32_t *)s->CTXSUFF(vram_ptr))[addr] & ~write_mask) |
1375 (val & write_mask);
1376#endif /* VBOX */
1377#ifdef DEBUG_VGA_MEM
1378 Log(("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
1379 addr * 4, write_mask, val));
1380#endif
1381#ifndef VBOX
1382 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
1383#else /* VBOX */
1384 vga_set_dirty(s, (addr << 2));
1385#endif /* VBOX */
1386 }
1387
1388 return VINF_SUCCESS;
1389}
1390
1391#ifndef VBOX
1392static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1393{
1394#ifdef TARGET_WORDS_BIGENDIAN
1395 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1396 vga_mem_writeb(opaque, addr + 1, val & 0xff);
1397#else
1398 vga_mem_writeb(opaque, addr, val & 0xff);
1399 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1400#endif
1401}
1402
1403static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1404{
1405#ifdef TARGET_WORDS_BIGENDIAN
1406 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1407 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1408 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1409 vga_mem_writeb(opaque, addr + 3, val & 0xff);
1410#else
1411 vga_mem_writeb(opaque, addr, val & 0xff);
1412 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1413 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1414 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1415#endif
1416}
1417#endif /* !VBOX */
1418
1419#if !defined(VBOX) || defined(IN_RING3)
1420typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
1421 const uint8_t *font_ptr, int h,
1422 uint32_t fgcol, uint32_t bgcol);
1423typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
1424 const uint8_t *font_ptr, int h,
1425 uint32_t fgcol, uint32_t bgcol, int dup9);
1426typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
1427 const uint8_t *s, int width);
1428
1429static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
1430{
1431 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
1432}
1433
1434static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
1435{
1436 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
1437}
1438
1439static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
1440{
1441 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
1442}
1443
1444static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
1445{
1446 return (r << 16) | (g << 8) | b;
1447}
1448
1449#define DEPTH 8
1450#include "DevVGATmpl.h"
1451
1452#define DEPTH 15
1453#include "DevVGATmpl.h"
1454
1455#define DEPTH 16
1456#include "DevVGATmpl.h"
1457
1458#define DEPTH 32
1459#include "DevVGATmpl.h"
1460
1461static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1462{
1463 unsigned int col;
1464 col = rgb_to_pixel8(r, g, b);
1465 col |= col << 8;
1466 col |= col << 16;
1467 return col;
1468}
1469
1470static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1471{
1472 unsigned int col;
1473 col = rgb_to_pixel15(r, g, b);
1474 col |= col << 16;
1475 return col;
1476}
1477
1478static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1479{
1480 unsigned int col;
1481 col = rgb_to_pixel16(r, g, b);
1482 col |= col << 16;
1483 return col;
1484}
1485
1486static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1487{
1488 unsigned int col;
1489 col = rgb_to_pixel32(r, g, b);
1490 return col;
1491}
1492
1493/* return true if the palette was modified */
1494static int update_palette16(VGAState *s)
1495{
1496 int full_update, i;
1497 uint32_t v, col, *palette;
1498
1499 full_update = 0;
1500 palette = s->last_palette;
1501 for(i = 0; i < 16; i++) {
1502 v = s->ar[i];
1503 if (s->ar[0x10] & 0x80)
1504 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1505 else
1506 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1507 v = v * 3;
1508 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1509 c6_to_8(s->palette[v + 1]),
1510 c6_to_8(s->palette[v + 2]));
1511 if (col != palette[i]) {
1512 full_update = 1;
1513 palette[i] = col;
1514 }
1515 }
1516 return full_update;
1517}
1518
1519/* return true if the palette was modified */
1520static int update_palette256(VGAState *s)
1521{
1522 int full_update, i;
1523 uint32_t v, col, *palette;
1524 int wide_dac;
1525
1526 full_update = 0;
1527 palette = s->last_palette;
1528 v = 0;
1529 wide_dac = (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & (VBE_DISPI_ENABLED | VBE_DISPI_8BIT_DAC))
1530 == (VBE_DISPI_ENABLED | VBE_DISPI_8BIT_DAC);
1531 for(i = 0; i < 256; i++) {
1532 if (wide_dac)
1533 col = s->rgb_to_pixel(s->palette[v],
1534 s->palette[v + 1],
1535 s->palette[v + 2]);
1536 else
1537 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1538 c6_to_8(s->palette[v + 1]),
1539 c6_to_8(s->palette[v + 2]));
1540 if (col != palette[i]) {
1541 full_update = 1;
1542 palette[i] = col;
1543 }
1544 v += 3;
1545 }
1546 return full_update;
1547}
1548
1549static void vga_get_offsets(VGAState *s,
1550 uint32_t *pline_offset,
1551 uint32_t *pstart_addr,
1552 uint32_t *pline_compare)
1553{
1554 uint32_t start_addr, line_offset, line_compare;
1555#ifdef CONFIG_BOCHS_VBE
1556 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1557 line_offset = s->vbe_line_offset;
1558 start_addr = s->vbe_start_addr;
1559 line_compare = 65535;
1560 } else
1561#endif
1562 {
1563 /* compute line_offset in bytes */
1564 line_offset = s->cr[0x13];
1565 line_offset <<= 3;
1566#ifdef VBOX
1567 if (!(s->cr[0x14] & 0x40) && !(s->cr[0x17] & 0x40))
1568 {
1569 /* Word mode. Used for odd/even modes. */
1570 line_offset *= 2;
1571 }
1572#endif /* VBOX */
1573
1574 /* starting address */
1575 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1576
1577 /* line compare */
1578 line_compare = s->cr[0x18] |
1579 ((s->cr[0x07] & 0x10) << 4) |
1580 ((s->cr[0x09] & 0x40) << 3);
1581 }
1582 *pline_offset = line_offset;
1583 *pstart_addr = start_addr;
1584 *pline_compare = line_compare;
1585}
1586
1587/* update start_addr and line_offset. Return TRUE if modified */
1588static int update_basic_params(VGAState *s)
1589{
1590 int full_update;
1591 uint32_t start_addr, line_offset, line_compare;
1592
1593 full_update = 0;
1594
1595 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1596
1597 if (line_offset != s->line_offset ||
1598 start_addr != s->start_addr ||
1599 line_compare != s->line_compare) {
1600 s->line_offset = line_offset;
1601 s->start_addr = start_addr;
1602 s->line_compare = line_compare;
1603 full_update = 1;
1604 }
1605 return full_update;
1606}
1607
1608static inline int get_depth_index(int depth)
1609{
1610 switch(depth) {
1611 default:
1612 case 8:
1613 return 0;
1614 case 15:
1615 return 1;
1616 case 16:
1617 return 2;
1618 case 32:
1619 return 3;
1620 }
1621}
1622
1623static vga_draw_glyph8_func *vga_draw_glyph8_table[4] = {
1624 vga_draw_glyph8_8,
1625 vga_draw_glyph8_16,
1626 vga_draw_glyph8_16,
1627 vga_draw_glyph8_32,
1628};
1629
1630static vga_draw_glyph8_func *vga_draw_glyph16_table[4] = {
1631 vga_draw_glyph16_8,
1632 vga_draw_glyph16_16,
1633 vga_draw_glyph16_16,
1634 vga_draw_glyph16_32,
1635};
1636
1637static vga_draw_glyph9_func *vga_draw_glyph9_table[4] = {
1638 vga_draw_glyph9_8,
1639 vga_draw_glyph9_16,
1640 vga_draw_glyph9_16,
1641 vga_draw_glyph9_32,
1642};
1643
1644static const uint8_t cursor_glyph[32 * 4] = {
1645 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1646 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1647 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1648 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1649 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1650 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1651 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1652 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1653 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1654 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1655 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1656 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1657 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1658 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1659 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1660 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1661};
1662
1663/*
1664 * Text mode update
1665 * Missing:
1666 * - double scan
1667 * - double width
1668 * - underline
1669 * - flashing
1670 */
1671#ifndef VBOX
1672static void vga_draw_text(VGAState *s, int full_update)
1673#else
1674static int vga_draw_text(VGAState *s, int full_update)
1675#endif /* !VBOX */
1676{
1677 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1678 int cx_min, cx_max, linesize, x_incr;
1679 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1680 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1681 const uint8_t *font_ptr, *font_base[2];
1682 int dup9, line_offset, depth_index;
1683 uint32_t *palette;
1684 uint32_t *ch_attr_ptr;
1685 vga_draw_glyph8_func *vga_draw_glyph8;
1686 vga_draw_glyph9_func *vga_draw_glyph9;
1687
1688 full_update |= update_palette16(s);
1689 palette = s->last_palette;
1690
1691 /* compute font data address (in plane 2) */
1692 v = s->sr[3];
1693 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1694 if (offset != s->font_offsets[0]) {
1695 s->font_offsets[0] = offset;
1696 full_update = 1;
1697 }
1698#ifndef VBOX
1699 font_base[0] = s->vram_ptr + offset;
1700#else /* VBOX */
1701 font_base[0] = s->CTXSUFF(vram_ptr) + offset;
1702#endif /* VBOX */
1703
1704 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1705#ifndef VBOX
1706 font_base[1] = s->vram_ptr + offset;
1707#else /* VBOX */
1708 font_base[1] = s->CTXSUFF(vram_ptr) + offset;
1709#endif /* VBOX */
1710 if (offset != s->font_offsets[1]) {
1711 s->font_offsets[1] = offset;
1712 full_update = 1;
1713 }
1714 if (s->plane_updated & (1 << 2)) {
1715 /* if the plane 2 was modified since the last display, it
1716 indicates the font may have been modified */
1717 s->plane_updated = 0;
1718 full_update = 1;
1719 }
1720 full_update |= update_basic_params(s);
1721
1722 line_offset = s->line_offset;
1723#ifndef VBOX
1724 s1 = s->vram_ptr + (s->start_addr * 4);
1725#else /* VBOX */
1726 s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 8);
1727#endif /* VBOX */
1728
1729 /* total width & height */
1730 cheight = (s->cr[9] & 0x1f) + 1;
1731 cw = 8;
1732 if (!(s->sr[1] & 0x01))
1733 cw = 9;
1734 if (s->sr[1] & 0x08)
1735 cw = 16; /* NOTE: no 18 pixel wide */
1736#ifndef VBOX
1737 x_incr = cw * ((s->ds->depth + 7) >> 3);
1738#else /* VBOX */
1739 x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
1740#endif /* VBOX */
1741 width = (s->cr[0x01] + 1);
1742 if (s->cr[0x06] == 100) {
1743 /* ugly hack for CGA 160x100x16 - explain me the logic */
1744 height = 100;
1745 } else {
1746 height = s->cr[0x12] |
1747 ((s->cr[0x07] & 0x02) << 7) |
1748 ((s->cr[0x07] & 0x40) << 3);
1749 height = (height + 1) / cheight;
1750 }
1751 if ((height * width) > CH_ATTR_SIZE) {
1752 /* better than nothing: exit if transient size is too big */
1753#ifndef VBOX
1754 return;
1755#else
1756 return VINF_SUCCESS;
1757#endif /* VBOX */
1758 }
1759
1760 if (width != (int)s->last_width || height != (int)s->last_height ||
1761 cw != s->last_cw || cheight != s->last_ch) {
1762 s->last_scr_width = width * cw;
1763 s->last_scr_height = height * cheight;
1764#ifndef VBOX
1765 dpy_resize(s->ds, s->last_scr_width, s->last_scr_height);
1766 s->last_width = width;
1767 s->last_height = height;
1768 s->last_ch = cheight;
1769 s->last_cw = cw;
1770 full_update = 1;
1771#else /* VBOX */
1772 /* For text modes the direct use of guest VRAM is not implemented, so bpp and cbLine are 0 here. */
1773 int rc = s->pDrv->pfnResize(s->pDrv, 0, NULL, 0, s->last_scr_width, s->last_scr_height);
1774 s->last_width = width;
1775 s->last_height = height;
1776 s->last_ch = cheight;
1777 s->last_cw = cw;
1778 full_update = 1;
1779 if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1780 return rc;
1781 AssertRC(rc);
1782#endif /* VBOX */
1783 }
1784 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1785 if (cursor_offset != s->cursor_offset ||
1786 s->cr[0xa] != s->cursor_start ||
1787 s->cr[0xb] != s->cursor_end) {
1788 /* if the cursor position changed, we update the old and new
1789 chars */
1790 if (s->cursor_offset < CH_ATTR_SIZE)
1791 s->last_ch_attr[s->cursor_offset] = ~0;
1792 if (cursor_offset < CH_ATTR_SIZE)
1793 s->last_ch_attr[cursor_offset] = ~0;
1794 s->cursor_offset = cursor_offset;
1795 s->cursor_start = s->cr[0xa];
1796 s->cursor_end = s->cr[0xb];
1797 }
1798#ifndef VBOX
1799 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1800
1801 depth_index = get_depth_index(s->ds->depth);
1802#else /* VBOX */
1803 cursor_ptr = s->CTXSUFF(vram_ptr) + (s->start_addr + cursor_offset) * 8;
1804 depth_index = get_depth_index(s->pDrv->cBits);
1805#endif /* VBOX */
1806 if (cw == 16)
1807 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1808 else
1809 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1810 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1811
1812#ifndef VBOX
1813 dest = s->ds->data;
1814 linesize = s->ds->linesize;
1815#else /* VBOX */
1816 dest = s->pDrv->pu8Data;
1817 linesize = s->pDrv->cbScanline;
1818#endif /* VBOX */
1819 ch_attr_ptr = s->last_ch_attr;
1820
1821 for(cy = 0; cy < height; cy++) {
1822 d1 = dest;
1823 src = s1;
1824 cx_min = width;
1825 cx_max = -1;
1826 for(cx = 0; cx < width; cx++) {
1827 ch_attr = *(uint16_t *)src;
1828 if (full_update || ch_attr != (int)*ch_attr_ptr) {
1829 if (cx < cx_min)
1830 cx_min = cx;
1831 if (cx > cx_max)
1832 cx_max = cx;
1833 *ch_attr_ptr = ch_attr;
1834#ifdef WORDS_BIGENDIAN
1835 ch = ch_attr >> 8;
1836 cattr = ch_attr & 0xff;
1837#else
1838 ch = ch_attr & 0xff;
1839 cattr = ch_attr >> 8;
1840#endif
1841 font_ptr = font_base[(cattr >> 3) & 1];
1842 font_ptr += 32 * 4 * ch;
1843 bgcol = palette[cattr >> 4];
1844 fgcol = palette[cattr & 0x0f];
1845 if (cw != 9) {
1846 vga_draw_glyph8(d1, linesize,
1847 font_ptr, cheight, fgcol, bgcol);
1848 } else {
1849 dup9 = 0;
1850 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1851 dup9 = 1;
1852 vga_draw_glyph9(d1, linesize,
1853 font_ptr, cheight, fgcol, bgcol, dup9);
1854 }
1855 if (src == cursor_ptr &&
1856 !(s->cr[0x0a] & 0x20)) {
1857 int line_start, line_last, h;
1858 /* draw the cursor */
1859 line_start = s->cr[0x0a] & 0x1f;
1860 line_last = s->cr[0x0b] & 0x1f;
1861 /* XXX: check that */
1862 if (line_last > cheight - 1)
1863 line_last = cheight - 1;
1864 if (line_last >= line_start && line_start < cheight) {
1865 h = line_last - line_start + 1;
1866 d = d1 + linesize * line_start;
1867 if (cw != 9) {
1868 vga_draw_glyph8(d, linesize,
1869 cursor_glyph, h, fgcol, bgcol);
1870 } else {
1871 vga_draw_glyph9(d, linesize,
1872 cursor_glyph, h, fgcol, bgcol, 1);
1873 }
1874 }
1875 }
1876 }
1877 d1 += x_incr;
1878#ifndef VBOX
1879 src += 4;
1880#else
1881 src += 8; /* Every second byte of a plane is used in text mode. */
1882#endif
1883
1884 ch_attr_ptr++;
1885 }
1886#ifndef VBOX
1887 if (cx_max != -1) {
1888 dpy_update(s->ds, cx_min * cw, cy * cheight,
1889 (cx_max - cx_min + 1) * cw, cheight);
1890 }
1891#else
1892 if (cx_max != -1)
1893 s->pDrv->pfnUpdateRect(s->pDrv, cx_min * cw, cy * cheight, (cx_max - cx_min + 1) * cw, cheight);
1894#endif
1895 dest += linesize * cheight;
1896 s1 += line_offset;
1897 }
1898#ifdef VBOX
1899 return VINF_SUCCESS;
1900#endif /* VBOX */
1901}
1902
1903enum {
1904 VGA_DRAW_LINE2,
1905 VGA_DRAW_LINE2D2,
1906 VGA_DRAW_LINE4,
1907 VGA_DRAW_LINE4D2,
1908 VGA_DRAW_LINE8D2,
1909 VGA_DRAW_LINE8,
1910 VGA_DRAW_LINE15,
1911 VGA_DRAW_LINE16,
1912 VGA_DRAW_LINE24,
1913 VGA_DRAW_LINE32,
1914 VGA_DRAW_LINE_NB
1915};
1916
1917static vga_draw_line_func *vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = {
1918 vga_draw_line2_8,
1919 vga_draw_line2_16,
1920 vga_draw_line2_16,
1921 vga_draw_line2_32,
1922
1923 vga_draw_line2d2_8,
1924 vga_draw_line2d2_16,
1925 vga_draw_line2d2_16,
1926 vga_draw_line2d2_32,
1927
1928 vga_draw_line4_8,
1929 vga_draw_line4_16,
1930 vga_draw_line4_16,
1931 vga_draw_line4_32,
1932
1933 vga_draw_line4d2_8,
1934 vga_draw_line4d2_16,
1935 vga_draw_line4d2_16,
1936 vga_draw_line4d2_32,
1937
1938 vga_draw_line8d2_8,
1939 vga_draw_line8d2_16,
1940 vga_draw_line8d2_16,
1941 vga_draw_line8d2_32,
1942
1943 vga_draw_line8_8,
1944 vga_draw_line8_16,
1945 vga_draw_line8_16,
1946 vga_draw_line8_32,
1947
1948 vga_draw_line15_8,
1949 vga_draw_line15_15,
1950 vga_draw_line15_16,
1951 vga_draw_line15_32,
1952
1953 vga_draw_line16_8,
1954 vga_draw_line16_15,
1955 vga_draw_line16_16,
1956 vga_draw_line16_32,
1957
1958 vga_draw_line24_8,
1959 vga_draw_line24_15,
1960 vga_draw_line24_16,
1961 vga_draw_line24_32,
1962
1963 vga_draw_line32_8,
1964 vga_draw_line32_15,
1965 vga_draw_line32_16,
1966 vga_draw_line32_32,
1967};
1968
1969static int vga_get_bpp(VGAState *s)
1970{
1971 int ret;
1972#ifdef CONFIG_BOCHS_VBE
1973 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1974 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1975 } else
1976#endif
1977 {
1978 ret = 0;
1979 }
1980 return ret;
1981}
1982
1983static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1984{
1985 int width, height;
1986#ifdef CONFIG_BOCHS_VBE
1987 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1988 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1989 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1990 } else
1991#endif
1992 {
1993 width = (s->cr[0x01] + 1) * 8;
1994 height = s->cr[0x12] |
1995 ((s->cr[0x07] & 0x02) << 7) |
1996 ((s->cr[0x07] & 0x40) << 3);
1997 height = (height + 1);
1998 }
1999 *pwidth = width;
2000 *pheight = height;
2001}
2002
2003#ifndef VBOX
2004void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
2005{
2006 int y;
2007 if (y1 >= VGA_MAX_HEIGHT)
2008 return;
2009 if (y2 >= VGA_MAX_HEIGHT)
2010 y2 = VGA_MAX_HEIGHT;
2011 for(y = y1; y < y2; y++) {
2012 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
2013 }
2014}
2015#endif /* !VBOX*/
2016
2017#ifdef VBOX
2018/**
2019 * Performs the display driver resizing when in graphics mode.
2020 *
2021 * This will recalc / update any status data depending on the driver
2022 * properties (bit depth mostly).
2023 *
2024 * @returns VINF_SUCCESS on success.
2025 * @returns VINF_VGA_RESIZE_IN_PROGRESS if the operation wasn't complete.
2026 * @param s Pointer to the vga status.
2027 * @param cx The width.
2028 * @param cy The height.
2029 */
2030static int vga_resize_graphic(VGAState *s, int cx, int cy, int v)
2031{
2032 const unsigned cBits = s->get_bpp(s);
2033 /** @todo r=sunlover: If the guest changes VBE_DISPI_INDEX_X_OFFSET, VBE_DISPI_INDEX_Y_OFFSET
2034 * registers, then the third parameter of the following call should be
2035 * probably 's->CTXSUFF(vram_ptr) + s->vbe_start_addr'.
2036 */
2037 int rc = s->pDrv->pfnResize(s->pDrv, cBits, s->CTXSUFF(vram_ptr), s->line_offset, cx, cy);
2038
2039 /* last stuff */
2040 s->last_bpp = cBits;
2041 s->last_scr_width = cx;
2042 s->last_scr_height = cy;
2043 s->last_width = cx;
2044 s->last_height = cy;
2045
2046 if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
2047 return rc;
2048 AssertRC(rc);
2049
2050 /* update palette */
2051 switch (s->pDrv->cBits)
2052 {
2053 case 32: s->rgb_to_pixel = rgb_to_pixel32_dup; break;
2054 case 16:
2055 default: s->rgb_to_pixel = rgb_to_pixel16_dup; break;
2056 case 15: s->rgb_to_pixel = rgb_to_pixel15_dup; break;
2057 case 8: s->rgb_to_pixel = rgb_to_pixel8_dup; break;
2058 }
2059 if (s->shift_control == 0)
2060 update_palette16(s);
2061 else if (s->shift_control == 1)
2062 update_palette16(s);
2063 return VINF_SUCCESS;
2064}
2065#endif /* VBOX */
2066
2067/*
2068 * graphic modes
2069 */
2070#ifndef VBOX
2071static void vga_draw_graphic(VGAState *s, int full_update)
2072#else
2073static int vga_draw_graphic(VGAState *s, int full_update)
2074#endif /* !VBOX */
2075{
2076 int y1, y2, y, update, page_min, page_max, linesize, y_start, double_scan;
2077 int width, height, shift_control, line_offset, page0, page1, bwidth;
2078 int disp_width, multi_run;
2079 uint8_t *d;
2080 uint32_t v, addr1, addr;
2081 vga_draw_line_func *vga_draw_line;
2082 bool offsets_changed;
2083
2084 offsets_changed = update_basic_params(s);
2085
2086 full_update |= offsets_changed;
2087
2088 s->get_resolution(s, &width, &height);
2089 disp_width = width;
2090
2091 shift_control = (s->gr[0x05] >> 5) & 3;
2092 double_scan = (s->cr[0x09] >> 7);
2093 multi_run = double_scan;
2094 if (shift_control != s->shift_control ||
2095 double_scan != s->double_scan) {
2096 full_update = 1;
2097 s->shift_control = shift_control;
2098 s->double_scan = double_scan;
2099 }
2100
2101 if (shift_control == 0) {
2102 full_update |= update_palette16(s);
2103 if (s->sr[0x01] & 8) {
2104 v = VGA_DRAW_LINE4D2;
2105 disp_width <<= 1;
2106 } else {
2107 v = VGA_DRAW_LINE4;
2108 }
2109 } else if (shift_control == 1) {
2110 full_update |= update_palette16(s);
2111 if (s->sr[0x01] & 8) {
2112 v = VGA_DRAW_LINE2D2;
2113 disp_width <<= 1;
2114 } else {
2115 v = VGA_DRAW_LINE2;
2116 }
2117 } else {
2118 switch(s->get_bpp(s)) {
2119 default:
2120 case 0:
2121 full_update |= update_palette256(s);
2122 v = VGA_DRAW_LINE8D2;
2123 break;
2124 case 8:
2125 full_update |= update_palette256(s);
2126 v = VGA_DRAW_LINE8;
2127 break;
2128 case 15:
2129 v = VGA_DRAW_LINE15;
2130 break;
2131 case 16:
2132 v = VGA_DRAW_LINE16;
2133 break;
2134 case 24:
2135 v = VGA_DRAW_LINE24;
2136 break;
2137 case 32:
2138 v = VGA_DRAW_LINE32;
2139 break;
2140 }
2141 }
2142#ifndef VBOX
2143 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
2144
2145 if (disp_width != s->last_width ||
2146 height != s->last_height) {
2147 dpy_resize(s->ds, disp_width, height);
2148 s->last_scr_width = disp_width;
2149 s->last_scr_height = height;
2150 s->last_width = disp_width;
2151 s->last_height = height;
2152 full_update = 1;
2153 }
2154#else /* VBOX */
2155 if ( disp_width != (int)s->last_width
2156 || height != (int)s->last_height
2157 || s->get_bpp(s) != (int)s->last_bpp
2158 || offsets_changed)
2159 {
2160 int rc = vga_resize_graphic(s, disp_width, height, v);
2161 if (rc != VINF_SUCCESS) /* Return any rc, particularly VINF_VGA_RESIZE_IN_PROGRESS, to the caller. */
2162 return rc;
2163 full_update = 1;
2164 }
2165 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
2166
2167#endif /* VBOX */
2168 if (s->cursor_invalidate)
2169 s->cursor_invalidate(s);
2170
2171 line_offset = s->line_offset;
2172#if 0
2173 Log(("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
2174 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]));
2175#endif
2176 addr1 = (s->start_addr * 4);
2177#ifndef VBOX
2178 bwidth = width * 4;
2179#else /* VBOX */
2180 /* The width of VRAM scanline. */
2181 bwidth = s->line_offset;
2182 /* In some cases the variable is not yet set, probably due to incomplete
2183 * programming of the virtual hardware ports. Just return.
2184 */
2185 if (bwidth == 0) return VINF_SUCCESS;
2186#endif /* VBOX */
2187 y_start = -1;
2188 page_min = 0x7fffffff;
2189 page_max = -1;
2190#ifndef VBOX
2191 d = s->ds->data;
2192 linesize = s->ds->linesize;
2193#else /* VBOX */
2194 d = s->pDrv->pu8Data;
2195 linesize = s->pDrv->cbScanline;
2196#endif /* VBOX */
2197
2198 y1 = 0;
2199 y2 = s->cr[0x09] & 0x1F; /* starting row scan count */
2200 for(y = 0; y < height; y++) {
2201 addr = addr1;
2202 /* CGA/MDA compatibility. Note that these addresses are all
2203 * shifted left by two compared to VGA specs.
2204 */
2205 if (!(s->cr[0x17] & 1)) {
2206 addr = (addr & ~(1 << 15)) | ((y1 & 1) << 15);
2207 }
2208 if (!(s->cr[0x17] & 2)) {
2209 addr = (addr & ~(1 << 16)) | ((y1 & 2) << 15);
2210 }
2211#ifndef VBOX
2212 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
2213 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
2214 update = full_update |
2215 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
2216 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
2217 if ((page1 - page0) > TARGET_PAGE_SIZE) {
2218 /* if wide line, can use another page */
2219 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
2220 VGA_DIRTY_FLAG);
2221 }
2222#else /* VBOX */
2223 page0 = addr & TARGET_PAGE_MASK;
2224 page1 = (addr + bwidth - 1) & TARGET_PAGE_MASK;
2225 update = full_update | vga_is_dirty(s, page0) | vga_is_dirty(s, page1);
2226 if (page1 - page0 > TARGET_PAGE_SIZE) {
2227 /* if wide line, can use another page */
2228 update |= vga_is_dirty(s, page0 + TARGET_PAGE_SIZE);
2229 }
2230#endif /* VBOX */
2231 /* explicit invalidation for the hardware cursor */
2232 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2233 if (update) {
2234 if (y_start < 0)
2235 y_start = y;
2236 if (page0 < page_min)
2237 page_min = page0;
2238 if (page1 > page_max)
2239 page_max = page1;
2240#ifndef VBOX
2241 vga_draw_line(s, d, s->vram_ptr + addr, width);
2242#else /* VBOX */
2243 if (s->fRenderVRAM)
2244 vga_draw_line(s, d, s->CTXSUFF(vram_ptr) + addr, width);
2245#endif /* VBOX */
2246 if (s->cursor_draw_line)
2247 s->cursor_draw_line(s, d, y);
2248 } else {
2249 if (y_start >= 0) {
2250 /* flush to display */
2251#ifndef VBOX
2252 dpy_update(s->ds, 0, y_start,
2253 disp_width, y - y_start);
2254#else /* VBOX */
2255 s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2256#endif /* VBOX */
2257 y_start = -1;
2258 }
2259 }
2260 if (!multi_run) {
2261 y1++;
2262 multi_run = double_scan;
2263
2264 if (y2 == 0) {
2265 y2 = s->cr[0x09] & 0x1F;
2266 addr1 += line_offset;
2267 } else {
2268 --y2;
2269 }
2270 } else {
2271 multi_run--;
2272 }
2273 /* line compare acts on the displayed lines */
2274 if ((uint32_t)y == s->line_compare)
2275 addr1 = 0;
2276 d += linesize;
2277 }
2278 if (y_start >= 0) {
2279 /* flush to display */
2280#ifndef VBOX
2281 dpy_update(s->ds, 0, y_start,
2282 disp_width, y - y_start);
2283#else /* VBOX */
2284 s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2285#endif /* VBOX */
2286 }
2287 /* reset modified pages */
2288 if (page_max != -1) {
2289#ifndef VBOX
2290 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
2291 VGA_DIRTY_FLAG);
2292#else /* VBOX */
2293 vga_reset_dirty(s, page_min, page_max + TARGET_PAGE_SIZE);
2294#endif /* VBOX */
2295 }
2296 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
2297#ifdef VBOX
2298 return VINF_SUCCESS;
2299#endif /* VBOX */
2300}
2301
2302static void vga_draw_blank(VGAState *s, int full_update)
2303{
2304#ifndef VBOX
2305 int i, w, val;
2306 uint8_t *d;
2307
2308 if (!full_update)
2309 return;
2310 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
2311 return;
2312 if (s->ds->depth == 8)
2313 val = s->rgb_to_pixel(0, 0, 0);
2314 else
2315 val = 0;
2316 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
2317 d = s->ds->data;
2318 for(i = 0; i < s->last_scr_height; i++) {
2319 memset(d, val, w);
2320 d += s->ds->linesize;
2321 }
2322 dpy_update(s->ds, 0, 0,
2323 s->last_scr_width, s->last_scr_height);
2324#else /* VBOX */
2325
2326 int i, w, val;
2327 uint8_t *d;
2328 uint32_t cbScanline = s->pDrv->cbScanline;
2329
2330 if (s->pDrv->pu8Data == s->vram_ptrHC) /* Do not clear the VRAM itself. */
2331 return;
2332 if (!full_update)
2333 return;
2334 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
2335 return;
2336 if (s->pDrv->cBits == 8)
2337 val = s->rgb_to_pixel(0, 0, 0);
2338 else
2339 val = 0;
2340 w = s->last_scr_width * ((s->pDrv->cBits + 7) >> 3);
2341 d = s->pDrv->pu8Data;
2342 for(i = 0; i < (int)s->last_scr_height; i++) {
2343 memset(d, val, w);
2344 d += cbScanline;
2345 }
2346 s->pDrv->pfnUpdateRect(s->pDrv, 0, 0, s->last_scr_width, s->last_scr_height);
2347#endif /* VBOX */
2348}
2349
2350#define GMODE_TEXT 0
2351#define GMODE_GRAPH 1
2352#define GMODE_BLANK 2
2353
2354#ifndef VBOX
2355void vga_update_display(void)
2356{
2357 VGAState *s = vga_state;
2358#else /* VBOX */
2359static int vga_update_display(PVGASTATE s)
2360{
2361 int rc = VINF_SUCCESS;
2362#endif /* VBOX */
2363 int full_update, graphic_mode;
2364
2365#ifndef VBOX
2366 if (s->ds->depth == 0) {
2367#else /* VBOX */
2368 if (s->pDrv->cBits == 0) {
2369#endif /* VBOX */
2370 /* nothing to do */
2371 } else {
2372#ifndef VBOX
2373 switch(s->ds->depth) {
2374#else /* VBOX */
2375 switch(s->pDrv->cBits) {
2376#endif /* VBOX */
2377 case 8:
2378 s->rgb_to_pixel = rgb_to_pixel8_dup;
2379 break;
2380 case 15:
2381 s->rgb_to_pixel = rgb_to_pixel15_dup;
2382 break;
2383 default:
2384 case 16:
2385 s->rgb_to_pixel = rgb_to_pixel16_dup;
2386 break;
2387 case 32:
2388 s->rgb_to_pixel = rgb_to_pixel32_dup;
2389 break;
2390 }
2391
2392 full_update = 0;
2393 if (!(s->ar_index & 0x20)) {
2394 graphic_mode = GMODE_BLANK;
2395 } else {
2396 graphic_mode = s->gr[6] & 1;
2397 }
2398 if (graphic_mode != s->graphic_mode) {
2399 s->graphic_mode = graphic_mode;
2400 full_update = 1;
2401 }
2402 switch(graphic_mode) {
2403 case GMODE_TEXT:
2404#ifdef VBOX
2405 rc =
2406#endif /* VBOX */
2407 vga_draw_text(s, full_update);
2408 break;
2409 case GMODE_GRAPH:
2410#ifdef VBOX
2411 rc =
2412#endif /* VBOX */
2413 vga_draw_graphic(s, full_update);
2414 break;
2415 case GMODE_BLANK:
2416 default:
2417 vga_draw_blank(s, full_update);
2418 break;
2419 }
2420 }
2421#ifdef VBOX
2422 return rc;
2423#endif /* VBOX */
2424}
2425
2426/* force a full display refresh */
2427#ifndef VBOX
2428void vga_invalidate_display(void)
2429{
2430 VGAState *s = vga_state;
2431
2432 s->last_width = -1;
2433 s->last_height = -1;
2434}
2435#endif /* !VBOX */
2436
2437#ifndef VBOX /* see vgaR3Reset() */
2438static void vga_reset(VGAState *s)
2439{
2440 memset(s, 0, sizeof(VGAState));
2441 s->graphic_mode = -1; /* force full update */
2442}
2443#endif /* !VBOX */
2444
2445#ifndef VBOX
2446static CPUReadMemoryFunc *vga_mem_read[3] = {
2447 vga_mem_readb,
2448 vga_mem_readw,
2449 vga_mem_readl,
2450};
2451
2452static CPUWriteMemoryFunc *vga_mem_write[3] = {
2453 vga_mem_writeb,
2454 vga_mem_writew,
2455 vga_mem_writel,
2456};
2457#endif /* !VBOX */
2458
2459static void vga_save(QEMUFile *f, void *opaque)
2460{
2461 VGAState *s = (VGAState*)opaque;
2462 int i;
2463
2464 qemu_put_be32s(f, &s->latch);
2465 qemu_put_8s(f, &s->sr_index);
2466 qemu_put_buffer(f, s->sr, 8);
2467 qemu_put_8s(f, &s->gr_index);
2468 qemu_put_buffer(f, s->gr, 16);
2469 qemu_put_8s(f, &s->ar_index);
2470 qemu_put_buffer(f, s->ar, 21);
2471 qemu_put_be32s(f, &s->ar_flip_flop);
2472 qemu_put_8s(f, &s->cr_index);
2473 qemu_put_buffer(f, s->cr, 256);
2474 qemu_put_8s(f, &s->msr);
2475 qemu_put_8s(f, &s->fcr);
2476 qemu_put_8s(f, &s->st00);
2477 qemu_put_8s(f, &s->st01);
2478
2479 qemu_put_8s(f, &s->dac_state);
2480 qemu_put_8s(f, &s->dac_sub_index);
2481 qemu_put_8s(f, &s->dac_read_index);
2482 qemu_put_8s(f, &s->dac_write_index);
2483 qemu_put_buffer(f, s->dac_cache, 3);
2484 qemu_put_buffer(f, s->palette, 768);
2485
2486 qemu_put_be32s(f, &s->bank_offset);
2487#ifdef CONFIG_BOCHS_VBE
2488 qemu_put_byte(f, 1);
2489 qemu_put_be16s(f, &s->vbe_index);
2490 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2491 qemu_put_be16s(f, &s->vbe_regs[i]);
2492 qemu_put_be32s(f, &s->vbe_start_addr);
2493 qemu_put_be32s(f, &s->vbe_line_offset);
2494 qemu_put_be32s(f, &s->vbe_bank_mask);
2495#else
2496 qemu_put_byte(f, 0);
2497#endif
2498}
2499
2500static int vga_load(QEMUFile *f, void *opaque, int version_id)
2501{
2502 VGAState *s = (VGAState*)opaque;
2503 int is_vbe, i;
2504
2505 if (version_id != 1)
2506#ifndef VBOX
2507 return -EINVAL;
2508#else /* VBOX */
2509 {
2510 Log(("vga_load: version_id=%d - UNKNOWN\n", version_id));
2511 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2512 }
2513#endif /* VBOX */
2514
2515 qemu_get_be32s(f, &s->latch);
2516 qemu_get_8s(f, &s->sr_index);
2517 qemu_get_buffer(f, s->sr, 8);
2518 qemu_get_8s(f, &s->gr_index);
2519 qemu_get_buffer(f, s->gr, 16);
2520 qemu_get_8s(f, &s->ar_index);
2521 qemu_get_buffer(f, s->ar, 21);
2522 qemu_get_be32s(f, (uint32_t *)&s->ar_flip_flop);
2523 qemu_get_8s(f, &s->cr_index);
2524 qemu_get_buffer(f, s->cr, 256);
2525 qemu_get_8s(f, &s->msr);
2526 qemu_get_8s(f, &s->fcr);
2527 qemu_get_8s(f, &s->st00);
2528 qemu_get_8s(f, &s->st01);
2529
2530 qemu_get_8s(f, &s->dac_state);
2531 qemu_get_8s(f, &s->dac_sub_index);
2532 qemu_get_8s(f, &s->dac_read_index);
2533 qemu_get_8s(f, &s->dac_write_index);
2534 qemu_get_buffer(f, s->dac_cache, 3);
2535 qemu_get_buffer(f, s->palette, 768);
2536
2537 qemu_get_be32s(f, (uint32_t *)&s->bank_offset);
2538 is_vbe = qemu_get_byte(f);
2539#ifdef CONFIG_BOCHS_VBE
2540 if (!is_vbe)
2541#ifndef VBOX
2542 return -EINVAL;
2543#else /* VBOX */
2544 {
2545 Log(("vga_load: !is_vbe !!\n"));
2546 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2547 }
2548#endif /* VBOX */
2549 qemu_get_be16s(f, &s->vbe_index);
2550 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2551 qemu_get_be16s(f, &s->vbe_regs[i]);
2552 qemu_get_be32s(f, &s->vbe_start_addr);
2553 qemu_get_be32s(f, &s->vbe_line_offset);
2554 qemu_get_be32s(f, &s->vbe_bank_mask);
2555#else
2556 if (is_vbe)
2557#ifndef VBOX
2558 return -EINVAL;
2559#else /* VBOX */
2560 {
2561 Log(("vga_load: is_vbe !!\n"));
2562 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2563 }
2564#endif /* VBOX */
2565#endif
2566
2567 /* force refresh */
2568 s->graphic_mode = -1;
2569 return 0;
2570}
2571
2572#ifndef VBOX /* see vgaR3IORegionMap */
2573static void vga_map(PCIDevice *pci_dev, int region_num,
2574 uint32_t addr, uint32_t size, int type)
2575{
2576 VGAState *s = vga_state;
2577
2578 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2579}
2580#endif
2581
2582#ifndef VBOX /* see vgaR3Construct */
2583void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2584 unsigned long vga_ram_offset, int vga_ram_size)
2585#else
2586static void vga_init_expand(void)
2587#endif
2588{
2589 int i, j, v, b;
2590
2591 for(i = 0;i < 256; i++) {
2592 v = 0;
2593 for(j = 0; j < 8; j++) {
2594 v |= ((i >> j) & 1) << (j * 4);
2595 }
2596 expand4[i] = v;
2597
2598 v = 0;
2599 for(j = 0; j < 4; j++) {
2600 v |= ((i >> (2 * j)) & 3) << (j * 4);
2601 }
2602 expand2[i] = v;
2603 }
2604 for(i = 0; i < 16; i++) {
2605 v = 0;
2606 for(j = 0; j < 4; j++) {
2607 b = ((i >> j) & 1);
2608 v |= b << (2 * j);
2609 v |= b << (2 * j + 1);
2610 }
2611 expand4to8[i] = v;
2612 }
2613#ifdef VBOX
2614}
2615#else /* !VBOX */
2616 vga_reset(s);
2617
2618 s->vram_ptr = vga_ram_base;
2619 s->vram_offset = vga_ram_offset;
2620 s->vram_size = vga_ram_size;
2621 s->ds = ds;
2622 s->get_bpp = vga_get_bpp;
2623 s->get_offsets = vga_get_offsets;
2624 s->get_resolution = vga_get_resolution;
2625 /* XXX: currently needed for display */
2626 vga_state = s;
2627}
2628
2629
2630int vga_initialize(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2631 unsigned long vga_ram_offset, int vga_ram_size)
2632{
2633 VGAState *s;
2634
2635 s = qemu_mallocz(sizeof(VGAState));
2636 if (!s)
2637 return -1;
2638
2639 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2640
2641 register_savevm("vga", 0, 1, vga_save, vga_load, s);
2642
2643 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2644
2645 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2646 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2647 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2648 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2649
2650 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2651
2652 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2653 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2654 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2655 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2656 s->bank_offset = 0;
2657
2658#ifdef CONFIG_BOCHS_VBE
2659 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2660 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2661#if defined (TARGET_I386)
2662 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2663 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2664
2665 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2666 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2667
2668 /* old Bochs IO ports */
2669 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2670 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2671
2672 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2673 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2674#else
2675 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2676 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2677
2678 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2679 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2680#endif
2681#endif /* CONFIG_BOCHS_VBE */
2682
2683 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2684 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2685 vga_io_memory);
2686
2687 if (bus) {
2688 PCIDevice *d;
2689 uint8_t *pci_conf;
2690
2691 d = pci_register_device(bus, "VGA",
2692 sizeof(PCIDevice),
2693 -1, NULL, NULL);
2694 pci_conf = d->config;
2695 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2696 pci_conf[0x01] = 0x12;
2697 pci_conf[0x02] = 0x11;
2698 pci_conf[0x03] = 0x11;
2699 pci_conf[0x0a] = 0x00; // VGA controller
2700 pci_conf[0x0b] = 0x03;
2701 pci_conf[0x0e] = 0x00; // header_type
2702
2703 /* XXX: vga_ram_size must be a power of two */
2704 pci_register_io_region(d, 0, vga_ram_size,
2705 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2706 } else {
2707#ifdef CONFIG_BOCHS_VBE
2708 /* XXX: use optimized standard vga accesses */
2709 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2710 vga_ram_size, vga_ram_offset);
2711#endif
2712 }
2713 return 0;
2714}
2715#endif /* !VBOX */
2716
2717
2718#ifndef VBOX
2719/********************************************************/
2720/* vga screen dump */
2721
2722static int vga_save_w, vga_save_h;
2723
2724static void vga_save_dpy_update(DisplayState *s,
2725 int x, int y, int w, int h)
2726{
2727}
2728
2729static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2730{
2731 s->linesize = w * 4;
2732#ifndef VBOX
2733 s->data = qemu_malloc(h * s->linesize);
2734#else /* VBOX */
2735 if (!s->data)
2736 {
2737 PPDMDEVINS pDevIns = VGASTATE2DEVINS((PVGASTATE)s->pvVgaState);
2738 s->data = PDMDevHlpMMHeapAlloc(pDevIns, h * s->linesize);
2739 }
2740 else // (32-bpp buffer is allocated by the caller)
2741 s->linesize = ((w * 32 + 31) / 32) * 4;
2742#endif /* VBOX */
2743 vga_save_w = w;
2744 vga_save_h = h;
2745}
2746
2747static void vga_save_dpy_refresh(DisplayState *s)
2748{
2749}
2750
2751static int ppm_save(const char *filename, uint8_t *data,
2752 int w, int h, int linesize)
2753{
2754 FILE *f;
2755 uint8_t *d, *d1;
2756 unsigned int v;
2757 int y, x;
2758
2759 f = fopen(filename, "wb");
2760 if (!f)
2761 return -1;
2762 fprintf(f, "P6\n%d %d\n%d\n",
2763 w, h, 255);
2764 d1 = data;
2765 for(y = 0; y < h; y++) {
2766 d = d1;
2767 for(x = 0; x < w; x++) {
2768 v = *(uint32_t *)d;
2769 fputc((v >> 16) & 0xff, f);
2770 fputc((v >> 8) & 0xff, f);
2771 fputc((v) & 0xff, f);
2772 d += 4;
2773 }
2774 d1 += linesize;
2775 }
2776 fclose(f);
2777 return 0;
2778}
2779
2780/* save the vga display in a PPM image even if no display is
2781 available */
2782void vga_screen_dump(const char *filename)
2783{
2784 VGAState *s = vga_state;
2785 DisplayState *saved_ds, ds1, *ds = &ds1;
2786
2787 /* XXX: this is a little hackish */
2788 vga_invalidate_display();
2789 saved_ds = s->ds;
2790
2791 memset(ds, 0, sizeof(DisplayState));
2792 ds->dpy_update = vga_save_dpy_update;
2793 ds->dpy_resize = vga_save_dpy_resize;
2794 ds->dpy_refresh = vga_save_dpy_refresh;
2795 ds->depth = 32;
2796
2797 s->ds = ds;
2798 s->graphic_mode = -1;
2799 vga_update_display();
2800
2801 if (ds->data) {
2802 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2803 s->ds->linesize);
2804 qemu_free(ds->data);
2805 }
2806 s->ds = saved_ds;
2807}
2808#endif /* !VBOX */
2809
2810
2811#if 0 //def VBOX
2812/* copy the vga display contents to the given buffer. the size of the buffer
2813 must be sufficient to store the screen copy (see below). the width and height
2814 parameters determine the required dimensions of the copy. If they differ
2815 from the actual screen dimensions, then the returned copy is shrinked or
2816 stretched accordingly. The copy is always a 32-bit image, so the size of
2817 the buffer supplied must be at least (((width * 32 + 31) / 32) * 4) * height,
2818 i.e. dword-aligned. returns zero if the operation was successfull and -1
2819 otherwise. */
2820
2821static int vga_copy_screen_to(PVGASTATE s, uint8_t *buf, int width, int height)
2822{
2823 DisplayState *saved_ds, ds1, *ds = &ds1;
2824 if (!buf || width <= 0 || height <= 0)
2825 return -1;
2826
2827 /* XXX: this is a little hackish */
2828 vga_invalidate_display(s);
2829 saved_ds = s->ds;
2830
2831 memset(ds, 0, sizeof(DisplayState));
2832 ds->dpy_update = vga_save_dpy_update;
2833 ds->dpy_resize = vga_save_dpy_resize;
2834 ds->dpy_refresh = vga_save_dpy_refresh;
2835 ds->depth = 32;
2836 ds->data = buf;
2837 ds->pvVgaState = s;
2838
2839 s->ds = ds;
2840 s->graphic_mode = -1;
2841 vga_update_display(s);
2842
2843//@@TODO (dmik): implement stretching/shrinking!
2844
2845 s->ds = saved_ds;
2846 return 0;
2847}
2848
2849/* copy the given buffer to the vga display. width and height define the
2850 dimensions of the image in the buffer. x and y define the point on the
2851 vga display to copy the image to. the buffer is assumed to contain a 32-bit
2852 image, so the size of one scanline must be ((width * 32 + 31) / 32) * 4),
2853 i.e. dword-aligned. returns zero if the operation was successfull and -1
2854 otherwise. */
2855static int vga_copy_screen_from(PVGASTATE s, uint8_t *buf, int x, int y, int width, int height)
2856{
2857 int bpl = ((width * 32 + 31) / 32) * 4;
2858 int linesize = s->ds->linesize;
2859 uint8_t *dst;
2860 uint8_t *src;
2861 int bpp;
2862 vga_draw_line_func *vga_draw_line;
2863
2864 if (!buf || x < 0 || y < 0 || width <= 0 || height <= 0
2865 || x + width > s->ds->width || y + height > s->ds->height)
2866 return -1;
2867
2868 vga_draw_line = vga_draw_line_table[VGA_DRAW_LINE32 * 4 + get_depth_index(s->ds->depth)];
2869 switch (s->ds->depth) {
2870 case 8: bpp = 1; break;
2871 case 15:
2872 case 16: bpp = 2; break;
2873 case 32: bpp = 4; break;
2874 default: return -1;
2875 }
2876
2877 dst = s->ds->data + y * linesize + x * bpp;
2878 src = buf;
2879 for (y = 0; y < height; y ++)
2880 {
2881 vga_draw_line(s, dst, src, width);
2882 dst += linesize;
2883 src += bpl;
2884 }
2885
2886 return 0;
2887}
2888#endif
2889
2890#endif /* !VBOX || !IN_GC || !IN_RING0 */
2891
2892
2893
2894#ifdef VBOX /* VirtualBox code start */
2895
2896
2897/* -=-=-=-=-=- all contexts -=-=-=-=-=- */
2898
2899/**
2900 * Port I/O Handler for VGA OUT operations.
2901 *
2902 * @returns VBox status code.
2903 *
2904 * @param pDevIns The device instance.
2905 * @param pvUser User argument - ignored.
2906 * @param Port Port number used for the IN operation.
2907 * @param u32 The value to output.
2908 * @param cb The value size in bytes.
2909 */
2910PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2911{
2912 NOREF(pvUser);
2913 if (cb == 1)
2914 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
2915 else if (cb == 2)
2916 {
2917 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32 & 0xff);
2918 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1, u32 >> 8);
2919 }
2920 return VINF_SUCCESS;
2921}
2922
2923
2924/**
2925 * Port I/O Handler for VGA IN operations.
2926 *
2927 * @returns VBox status code.
2928 *
2929 * @param pDevIns The device instance.
2930 * @param pvUser User argument - ignored.
2931 * @param Port Port number used for the IN operation.
2932 * @param pu32 Where to store the result.
2933 * @param cb Number of bytes read.
2934 */
2935PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2936{
2937 NOREF(pvUser);
2938 if (cb == 1)
2939 {
2940 *pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port);
2941 return VINF_SUCCESS;
2942 }
2943 else if (cb == 2)
2944 {
2945 *pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port)
2946 | (vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1) << 8);
2947 return VINF_SUCCESS;
2948 }
2949 return VERR_IOM_IOPORT_UNUSED;
2950}
2951
2952
2953/**
2954 * Port I/O Handler for VBE OUT operations.
2955 *
2956 * @returns VBox status code.
2957 *
2958 * @param pDevIns The device instance.
2959 * @param pvUser User argument - ignored.
2960 * @param Port Port number used for the IN operation.
2961 * @param u32 The value to output.
2962 * @param cb The value size in bytes.
2963 */
2964PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2965{
2966 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2967
2968 NOREF(pvUser);
2969
2970#ifndef IN_RING3
2971 /*
2972 * This has to be done on the host in order to execute the connector callbacks.
2973 */
2974 if (s->vbe_index == VBE_DISPI_INDEX_ENABLE
2975 || s->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO)
2976 {
2977 Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE - Switching to host...\n"));
2978 return VINF_IOM_HC_IOPORT_WRITE;
2979 }
2980#endif
2981#ifdef VBE_BYTEWISE_IO
2982 if (cb == 1)
2983 {
2984 if (!s->fWriteVBEData)
2985 {
2986 if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
2987 && (u32 & VBE_DISPI_ENABLED))
2988 {
2989 s->fWriteVBEData = false;
2990 return vbe_ioport_write_data(s, Port, u32 & 0xFF);
2991 }
2992 else
2993 {
2994 s->cbWriteVBEData = u32 & 0xFF;
2995 s->fWriteVBEData = true;
2996 return VINF_SUCCESS;
2997 }
2998 }
2999 else
3000 {
3001 u32 = (s->cbWriteVBEData << 8) | (u32 & 0xFF);
3002 s->fWriteVBEData = false;
3003 cb = 2;
3004 }
3005 }
3006#endif
3007 if (cb == 2 || cb == 4)
3008 {
3009//#ifdef IN_GC
3010// /*
3011// * The VBE_DISPI_INDEX_ENABLE memsets the entire frame buffer.
3012// * Since we're not mapping the entire framebuffer any longer that
3013// * has to be done on the host.
3014// */
3015// if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
3016// && (u32 & VBE_DISPI_ENABLED))
3017// {
3018// Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE & VBE_DISPI_ENABLED - Switching to host...\n"));
3019// return VINF_IOM_HC_IOPORT_WRITE;
3020// }
3021//#endif
3022 return vbe_ioport_write_data(s, Port, u32);
3023 }
3024 else
3025 AssertMsgFailed(("vgaIOPortWriteVBEData: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3026 return VINF_SUCCESS;
3027}
3028
3029
3030/**
3031 * Port I/O Handler for VBE OUT operations.
3032 *
3033 * @returns VBox status code.
3034 *
3035 * @param pDevIns The device instance.
3036 * @param pvUser User argument - ignored.
3037 * @param Port Port number used for the IN operation.
3038 * @param u32 The value to output.
3039 * @param cb The value size in bytes.
3040 */
3041PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3042{
3043 NOREF(pvUser);
3044#ifdef VBE_BYTEWISE_IO
3045 if (cb == 1)
3046 {
3047 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3048 if (!s->fWriteVBEIndex)
3049 {
3050 s->cbWriteVBEIndex = u32 & 0x00FF;
3051 s->fWriteVBEIndex = true;
3052 return VINF_SUCCESS;
3053 }
3054 else
3055 {
3056 s->fWriteVBEIndex = false;
3057 vbe_ioport_write_index(s, Port, (s->cbWriteVBEIndex << 8) | (u32 & 0x00FF));
3058 return VINF_SUCCESS;
3059 }
3060 }
3061 else
3062#endif
3063 if (cb == 2)
3064 vbe_ioport_write_index(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
3065 else
3066 AssertMsgFailed(("vgaIOPortWriteVBEIndex: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3067 return VINF_SUCCESS;
3068}
3069
3070
3071/**
3072 * Port I/O Handler for VBE IN operations.
3073 *
3074 * @returns VBox status code.
3075 *
3076 * @param pDevIns The device instance.
3077 * @param pvUser User argument - ignored.
3078 * @param Port Port number used for the IN operation.
3079 * @param pu32 Where to store the result.
3080 * @param cb Number of bytes to read.
3081 */
3082PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3083{
3084 NOREF(pvUser);
3085#ifdef VBE_BYTEWISE_IO
3086 if (cb == 1)
3087 {
3088 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3089
3090 if (!s->fReadVBEData)
3091 {
3092 *pu32 = (vbe_ioport_read_data(s, Port) >> 8) & 0xFF;
3093 s->fReadVBEData = true;
3094 return VINF_SUCCESS;
3095 }
3096 else
3097 {
3098 *pu32 = vbe_ioport_read_data(s, Port) & 0xFF;
3099 s->fReadVBEData = false;
3100 return VINF_SUCCESS;
3101 }
3102 }
3103 else
3104#endif
3105 if (cb == 2)
3106 {
3107 *pu32 = vbe_ioport_read_data(PDMINS2DATA(pDevIns, PVGASTATE), Port);
3108 return VINF_SUCCESS;
3109 }
3110 else if (cb == 4)
3111 {
3112 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3113 /* Quick hack for getting the vram size. */
3114 *pu32 = s->vram_size;
3115 return VINF_SUCCESS;
3116 }
3117 AssertMsgFailed(("vgaIOPortReadVBEData: Port=%#x cb=%d\n", Port, cb));
3118 return VERR_IOM_IOPORT_UNUSED;
3119}
3120
3121
3122/**
3123 * Port I/O Handler for VBE IN operations.
3124 *
3125 * @returns VBox status code.
3126 *
3127 * @param pDevIns The device instance.
3128 * @param pvUser User argument - ignored.
3129 * @param Port Port number used for the IN operation.
3130 * @param pu32 Where to store the result.
3131 * @param cb Number of bytes to read.
3132 */
3133PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3134{
3135 NOREF(pvUser);
3136#ifdef VBE_BYTEWISE_IO
3137 if (cb == 1)
3138 {
3139 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3140
3141 if (!s->fReadVBEIndex)
3142 {
3143 *pu32 = (vbe_ioport_read_index(s, Port) >> 8) & 0xFF;
3144 s->fReadVBEIndex = true;
3145 return VINF_SUCCESS;
3146 }
3147 else
3148 {
3149 *pu32 = vbe_ioport_read_index(s, Port) & 0xFF;
3150 s->fReadVBEIndex = false;
3151 return VINF_SUCCESS;
3152 }
3153 }
3154 else
3155#endif
3156 if (cb == 2)
3157 {
3158 *pu32 = vbe_ioport_read_index(PDMINS2DATA(pDevIns, PVGASTATE), Port);
3159 return VINF_SUCCESS;
3160 }
3161 AssertMsgFailed(("vgaIOPortReadVBEIndex: Port=%#x cb=%d\n", Port, cb));
3162 return VERR_IOM_IOPORT_UNUSED;
3163}
3164
3165
3166
3167
3168
3169/* -=-=-=-=-=- Guest Context -=-=-=-=-=- */
3170
3171/*
3172 * Internal. For use inside VGAGCMemoryFillWrite only.
3173 * Macro for apply logical operation and bit mask.
3174 */
3175#define APPLY_LOGICAL_AND_MASK(s, val, bit_mask) \
3176 /* apply logical operation */ \
3177 switch(s->gr[3] >> 3) \
3178 { \
3179 case 0: \
3180 default: \
3181 /* nothing to do */ \
3182 break; \
3183 case 1: \
3184 /* and */ \
3185 val &= s->latch; \
3186 break; \
3187 case 2: \
3188 /* or */ \
3189 val |= s->latch; \
3190 break; \
3191 case 3: \
3192 /* xor */ \
3193 val ^= s->latch; \
3194 break; \
3195 } \
3196 /* apply bit mask */ \
3197 val = (val & bit_mask) | (s->latch & ~bit_mask)
3198
3199/**
3200 * Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM and from the inside of VGADeviceGC.cpp.
3201 * This is the advanced version of vga_mem_writeb function.
3202 *
3203 * @returns VBox status code.
3204 * @param pDevIns Pointer device instance.
3205 * @param pvUser User argument - ignored.
3206 * @param GCPhysAddr Physical address of memory to write.
3207 * @param u32Item Data to write, up to 4 bytes.
3208 * @param cbItem Size of data Item, only 1/2/4 bytes is allowed for now.
3209 * @param cItems Number of data items to write.
3210 */
3211PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems)
3212{
3213 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3214 uint32_t b;
3215 uint32_t write_mask, bit_mask, set_mask;
3216 uint32_t aVal[4]; /** @todo r=bird: Why is this an 32-bit array? */
3217 unsigned i;
3218 NOREF(pvUser);
3219 for (i = 0; i < cbItem; i++)
3220 {
3221 aVal[i] = u32Item & 0xff;
3222 u32Item >>= 8;
3223 }
3224
3225 /* convert to VGA memory offset */
3226 /// @todo add check for the end of region
3227 GCPhysAddr &= 0x1ffff;
3228 switch((pData->gr[6] >> 2) & 3) {
3229 case 0:
3230 break;
3231 case 1:
3232 if (GCPhysAddr >= 0x10000)
3233 return VINF_SUCCESS;
3234 GCPhysAddr += pData->bank_offset;
3235 break;
3236 case 2:
3237 GCPhysAddr -= 0x10000;
3238 if (GCPhysAddr >= 0x8000)
3239 return VINF_SUCCESS;
3240 break;
3241 default:
3242 case 3:
3243 GCPhysAddr -= 0x18000;
3244 if (GCPhysAddr >= 0x8000)
3245 return VINF_SUCCESS;
3246 break;
3247 }
3248
3249 if (pData->sr[4] & 0x08) {
3250 /* chain 4 mode : simplest access */
3251#ifdef IN_GC
3252 if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
3253 return VINF_IOM_HC_MMIO_WRITE;
3254#else
3255 if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
3256 {
3257 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3258 return VINF_SUCCESS;
3259 }
3260#endif
3261
3262 while (cItems-- > 0)
3263 for (i = 0; i < cbItem; i++)
3264 {
3265 if (pData->sr[2] & (1 << (GCPhysAddr & 3)))
3266 {
3267 CTXSUFF(pData->vram_ptr)[GCPhysAddr] = aVal[i];
3268 vga_set_dirty(pData, GCPhysAddr);
3269 }
3270 GCPhysAddr++;
3271 }
3272 } else if (pData->gr[5] & 0x10) {
3273 /* odd/even mode (aka text mode mapping) */
3274#ifdef IN_GC
3275 if (GCPhysAddr * 2 + cItems * cbItem >= VGA_MAPPING_SIZE)
3276 return VINF_IOM_HC_MMIO_WRITE;
3277#else
3278 if (GCPhysAddr * 2 + cItems * cbItem >= pData->vram_size)
3279 {
3280 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3281 return VINF_SUCCESS;
3282 }
3283#endif
3284 while (cItems-- > 0)
3285 for (i = 0; i < cbItem; i++)
3286 {
3287 unsigned plane = (pData->gr[4] & 2) | (GCPhysAddr & 1);
3288 if (pData->sr[2] & (1 << plane)) {
3289 RTGCPHYS PhysAddr2 = ((GCPhysAddr & ~1) << 2) | plane;
3290 CTXSUFF(pData->vram_ptr)[PhysAddr2] = aVal[i];
3291 vga_set_dirty(pData, PhysAddr2);
3292 }
3293 GCPhysAddr++;
3294 }
3295 } else {
3296#ifdef IN_GC
3297 if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
3298 return VINF_IOM_HC_MMIO_WRITE;
3299#else
3300 if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
3301 {
3302 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3303 return VINF_SUCCESS;
3304 }
3305#endif
3306
3307 /* standard VGA latched access */
3308 switch(pData->gr[5] & 3) {
3309 default:
3310 case 0:
3311 /* rotate */
3312 b = pData->gr[3] & 7;
3313 bit_mask = pData->gr[8];
3314 bit_mask |= bit_mask << 8;
3315 bit_mask |= bit_mask << 16;
3316 set_mask = mask16[pData->gr[1]];
3317
3318 for (i = 0; i < cbItem; i++)
3319 {
3320 aVal[i] = ((aVal[i] >> b) | (aVal[i] << (8 - b))) & 0xff;
3321 aVal[i] |= aVal[i] << 8;
3322 aVal[i] |= aVal[i] << 16;
3323
3324 /* apply set/reset mask */
3325 aVal[i] = (aVal[i] & ~set_mask) | (mask16[pData->gr[0]] & set_mask);
3326
3327 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3328 }
3329 break;
3330 case 1:
3331 for (i = 0; i < cbItem; i++)
3332 aVal[i] = pData->latch;
3333 break;
3334 case 2:
3335 bit_mask = pData->gr[8];
3336 bit_mask |= bit_mask << 8;
3337 bit_mask |= bit_mask << 16;
3338 for (i = 0; i < cbItem; i++)
3339 {
3340 aVal[i] = mask16[aVal[i] & 0x0f];
3341
3342 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3343 }
3344 break;
3345 case 3:
3346 /* rotate */
3347 b = pData->gr[3] & 7;
3348
3349 for (i = 0; i < cbItem; i++)
3350 {
3351 aVal[i] = (aVal[i] >> b) | (aVal[i] << (8 - b));
3352 bit_mask = pData->gr[8] & aVal[i];
3353 bit_mask |= bit_mask << 8;
3354 bit_mask |= bit_mask << 16;
3355 aVal[i] = mask16[pData->gr[0]];
3356
3357 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3358 }
3359 break;
3360 }
3361
3362 /* mask data according to sr[2] */
3363 write_mask = mask16[pData->sr[2]];
3364
3365 /* actually write data */
3366 if (cbItem == 1)
3367 {
3368 /* The most frequently case is 1 byte I/O. */
3369 while (cItems-- > 0)
3370 {
3371 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[0] & write_mask);
3372 vga_set_dirty(pData, GCPhysAddr << 2);
3373 GCPhysAddr++;
3374 }
3375 }
3376 else if (cbItem == 2)
3377 {
3378 /* The second case is 2 bytes I/O. */
3379 while (cItems-- > 0)
3380 {
3381 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[0] & write_mask);
3382 vga_set_dirty(pData, GCPhysAddr << 2);
3383 GCPhysAddr++;
3384
3385 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[1] & write_mask);
3386 vga_set_dirty(pData, GCPhysAddr << 2);
3387 GCPhysAddr++;
3388 }
3389 }
3390 else
3391 {
3392 /* And the rest is 4 bytes. */
3393 Assert(cbItem == 4);
3394 while (cItems-- > 0)
3395 for (i = 0; i < cbItem; i++)
3396 {
3397 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[i] & write_mask);
3398 vga_set_dirty(pData, GCPhysAddr << 2);
3399 GCPhysAddr++;
3400 }
3401 }
3402 }
3403 return VINF_SUCCESS;
3404}
3405#undef APPLY_LOGICAL_AND_MASK
3406
3407
3408/**
3409 * Legacy VGA memory (0xa0000 - 0xbffff) read hook, to be called from IOM.
3410 *
3411 * @returns VBox status code.
3412 * @param pDevIns Pointer device instance.
3413 * @param pvUser User argument - ignored.
3414 * @param GCPhysAddr Physical address of memory to read.
3415 * @param pv Where to store readed data.
3416 * @param cb Bytes to read.
3417 */
3418PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3419{
3420 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3421 STAM_PROFILE_START(&pData->StatGCMemoryRead, a);
3422 NOREF(pvUser);
3423 switch (cb)
3424 {
3425 case 1:
3426 *(uint8_t *)pv = vga_mem_readb(pData, GCPhysAddr); break;
3427 case 2:
3428 *(uint16_t *)pv = vga_mem_readb(pData, GCPhysAddr)
3429 | (vga_mem_readb(pData, GCPhysAddr + 1) << 8);
3430 break;
3431 case 4:
3432 *(uint32_t *)pv = vga_mem_readb(pData, GCPhysAddr)
3433 | (vga_mem_readb(pData, GCPhysAddr + 1) << 8)
3434 | (vga_mem_readb(pData, GCPhysAddr + 2) << 16)
3435 | (vga_mem_readb(pData, GCPhysAddr + 3) << 24);
3436 break;
3437
3438 default:
3439 {
3440 uint8_t *pu8Data = (uint8_t *)pv;
3441 while (cb-- > 0)
3442 *pu8Data++ = vga_mem_readb(pData, GCPhysAddr++);
3443 }
3444 }
3445 STAM_PROFILE_STOP(&pData->StatGCMemoryRead, a);
3446 return VINF_SUCCESS;
3447}
3448
3449/**
3450 * Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM.
3451 *
3452 * @returns VBox status code.
3453 * @param pDevIns Pointer device instance.
3454 * @param pvUser User argument - ignored.
3455 * @param GCPhysAddr Physical address of memory to write.
3456 * @param pv Pointer to data.
3457 * @param cb Bytes to write.
3458 */
3459PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3460{
3461 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3462 uint8_t *pu8 = (uint8_t *)pv;
3463 int rc = VINF_SUCCESS;
3464 STAM_PROFILE_START(&pData->StatGCMemoryWrite, a);
3465
3466 switch (cb)
3467 {
3468 case 1:
3469 rc = vga_mem_writeb(pData, GCPhysAddr, *pu8);
3470 break;
3471#if 1
3472 case 2:
3473 rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3474 if (RT_LIKELY(rc == VINF_SUCCESS))
3475 rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3476 break;
3477 case 4:
3478 rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3479 if (RT_LIKELY(rc == VINF_SUCCESS))
3480 rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3481 if (RT_LIKELY(rc == VINF_SUCCESS))
3482 rc = vga_mem_writeb(pData, GCPhysAddr + 2, pu8[2]);
3483 if (RT_LIKELY(rc == VINF_SUCCESS))
3484 rc = vga_mem_writeb(pData, GCPhysAddr + 3, pu8[3]);
3485 break;
3486#else
3487 case 2:
3488 rc = vgaMMIOFill(pDevIns, GCPhysAddr, *(uint16_t *)pv, 2, 1);
3489 break;
3490 case 4:
3491 rc = vgaMMIOFill(pDevIns, GCPhysAddr, *(uint32_t *)pv, 4, 1);
3492 break;
3493#endif
3494 default:
3495 while (cb-- > 0 && rc == VINF_SUCCESS)
3496 rc = vga_mem_writeb(pData, GCPhysAddr++, *pu8++);
3497 break;
3498
3499 }
3500 STAM_PROFILE_STOP(&pData->StatGCMemoryWrite, a);
3501 return rc;
3502}
3503
3504
3505/**
3506 * Handle LFB access.
3507 * @returns VBox status code.
3508 * @param pVM VM handle.
3509 * @param pData VGA device instance data.
3510 * @param GCPhys The access physical address.
3511 * @param GCPtr The access virtual address (only GC).
3512 */
3513static int vgaLFBAccess(PVM pVM, PVGASTATE pData, RTGCPHYS GCPhys, RTGCPTR GCPtr)
3514{
3515 int rc;
3516
3517 /*
3518 * Set page dirty bit.
3519 */
3520 vga_set_dirty(pData, GCPhys - pData->GCPhysVRAM);
3521 pData->fLFBUpdated = true;
3522
3523 /*
3524 * Turn of the write handler for this particular page and make it R/W.
3525 * Then return telling the caller to restart the guest instruction.
3526 * ASSUME: the guest always maps video memory RW.
3527 */
3528 rc = PGMHandlerPhysicalPageTempOff(pVM, pData->GCPhysVRAM, GCPhys);
3529 if (VBOX_SUCCESS(rc))
3530 {
3531#ifndef IN_RING3
3532 rc = PGMShwModifyPage(pVM, GCPtr, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
3533 if (VBOX_SUCCESS(rc))
3534 return VINF_SUCCESS;
3535 else
3536 AssertMsgFailed(("PGMShwModifyPage -> rc=%d\n", rc));
3537#else /* IN_RING3 : We don't have any virtual page address of the access here. */
3538 Assert(GCPtr == 0);
3539 return VINF_SUCCESS;
3540#endif
3541 }
3542 else
3543 AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", rc));
3544
3545 return rc;
3546}
3547
3548
3549#ifdef IN_GC
3550/**
3551 * #PF Handler for VBE LFB access.
3552 *
3553 * @returns VBox status code (appropriate for GC return).
3554 * @param pVM VM Handle.
3555 * @param uErrorCode CPU Error code.
3556 * @param pRegFrame Trap register frame.
3557 * @param pvFault The fault address (cr2).
3558 * @param GCPhysFault The GC physical address corresponding to pvFault.
3559 * @param pvUser User argument, ignored.
3560 */
3561PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3562{
3563 PVGASTATE pData = (PVGASTATE)pvUser;
3564 Assert(pData);
3565 Assert(GCPhysFault >= pData->GCPhysVRAM);
3566 AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3567
3568 return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3569}
3570
3571#elif IN_RING0
3572
3573/**
3574 * #PF Handler for VBE LFB access.
3575 *
3576 * @returns VBox status code (appropriate for GC return).
3577 * @param pVM VM Handle.
3578 * @param uErrorCode CPU Error code.
3579 * @param pRegFrame Trap register frame.
3580 * @param pvFault The fault address (cr2).
3581 * @param GCPhysFault The GC physical address corresponding to pvFault.
3582 * @param pvUser User argument, ignored.
3583 */
3584PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3585{
3586 PVGASTATE pData = (PVGASTATE)pvUser;
3587 Assert(pData);
3588 Assert(GCPhysFault >= pData->GCPhysVRAM);
3589 AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3590
3591 return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3592}
3593
3594#else /* IN_RING3 */
3595
3596/**
3597 * HC access handler for the LFB.
3598 *
3599 * @returns VINF_SUCCESS if the handler have carried out the operation.
3600 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3601 * @param pVM VM Handle.
3602 * @param GCPhys The physical address the guest is writing to.
3603 * @param pvPhys The HC mapping of that address.
3604 * @param pvBuf What the guest is reading/writing.
3605 * @param cbBuf How much it's reading/writing.
3606 * @param enmAccessType The access type.
3607 * @param pvUser User argument.
3608 */
3609static DECLCALLBACK(int) vgaR3LFBAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
3610{
3611 PVGASTATE pData = (PVGASTATE)pvUser;
3612 int rc;
3613 Assert(pData);
3614 Assert(GCPhys >= pData->GCPhysVRAM);
3615 rc = vgaLFBAccess(pVM, pData, GCPhys, 0);
3616 if (VBOX_SUCCESS(rc))
3617 return VINF_PGM_HANDLER_DO_DEFAULT;
3618 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Vrc\n", rc));
3619 return rc;
3620}
3621#endif /* IN_RING3 */
3622
3623
3624/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3625
3626#ifdef IN_RING3
3627
3628# ifdef VBE_NEW_DYN_LIST
3629/**
3630 * Port I/O Handler for VBE Extra OUT operations.
3631 *
3632 * @returns VBox status code.
3633 *
3634 * @param pDevIns The device instance.
3635 * @param pvUser User argument - ignored.
3636 * @param Port Port number used for the IN operation.
3637 * @param u32 The value to output.
3638 * @param cb The value size in bytes.
3639 */
3640PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3641{
3642 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3643 NOREF(pvUser);
3644 NOREF(Port);
3645
3646 if (cb == 2)
3647 {
3648 Log(("vbeIOPortWriteVBEExtra: addr=%#RX32\n", u32));
3649 pData->u16VBEExtraAddress = u32;
3650 return VINF_SUCCESS;
3651 }
3652
3653 Log(("vbeIOPortWriteVBEExtra: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
3654 return VINF_SUCCESS;
3655}
3656
3657
3658/**
3659 * Port I/O Handler for VBE Extra IN operations.
3660 *
3661 * @returns VBox status code.
3662 *
3663 * @param pDevIns The device instance.
3664 * @param pvUser User argument - ignored.
3665 * @param Port Port number used for the IN operation.
3666 * @param pu32 Where to store the result.
3667 * @param cb Number of bytes read.
3668 */
3669PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3670{
3671 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3672 NOREF(pvUser);
3673 NOREF(Port);
3674
3675 if (pData->u16VBEExtraAddress == 0xffff)
3676 {
3677 Log(("vbeIOPortReadVBEExtra: Requested number of 64k video banks\n"));
3678 *pu32 = pData->vram_size / _64K;
3679 return VINF_SUCCESS;
3680 }
3681
3682 if ( pData->u16VBEExtraAddress >= pData->cbVBEExtraData
3683 || pData->u16VBEExtraAddress + cb > pData->cbVBEExtraData)
3684 {
3685 *pu32 = 0;
3686 Log(("vbeIOPortReadVBEExtra: Requested address is out of VBE data!!! Address=%#x(%d) cbVBEExtraData=%#x(%d)\n",
3687 pData->u16VBEExtraAddress, pData->u16VBEExtraAddress, pData->cbVBEExtraData, pData->cbVBEExtraData));
3688 return VINF_SUCCESS;
3689 }
3690
3691 if (cb == 1)
3692 {
3693 *pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress] & 0xFF;
3694
3695 Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3696 return VINF_SUCCESS;
3697 }
3698
3699 if (cb == 2)
3700 {
3701 *pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress]
3702 | pData->pu8VBEExtraData[pData->u16VBEExtraAddress + 1] << 8;
3703
3704 Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3705 return VINF_SUCCESS;
3706 }
3707 Log(("vbeIOPortReadVBEExtra: Invalid cb=%d read from the VBE Extra port!!!\n", cb));
3708 return VERR_IOM_IOPORT_UNUSED;
3709}
3710# endif /* VBE_NEW_DYN_LIST */
3711
3712
3713/**
3714 * Parse the logo bitmap data at init time.
3715 *
3716 * @returns VBox status code.
3717 *
3718 * @param pData The VGA instance data.
3719 */
3720static int vbeParseBitmap(PVGASTATE pData)
3721{
3722 uint16_t i;
3723 PBMPINFO bmpInfo;
3724 POS2HDR pOs2Hdr;
3725 POS22HDR pOs22Hdr;
3726 PWINHDR pWinHdr;
3727
3728 /*
3729 * Get bitmap header data
3730 */
3731 bmpInfo = (PBMPINFO)(pData->pu8Logo + sizeof(LOGOHDR));
3732 pWinHdr = (PWINHDR)(pData->pu8Logo + sizeof(LOGOHDR) + sizeof(BMPINFO));
3733
3734 if (bmpInfo->Type == BMP_ID)
3735 {
3736 switch (pWinHdr->Size)
3737 {
3738 case BMP_HEADER_OS21:
3739 pOs2Hdr = (POS2HDR)pWinHdr;
3740 pData->cxLogo = pOs2Hdr->Width;
3741 pData->cyLogo = pOs2Hdr->Height;
3742 pData->cLogoPlanes = pOs2Hdr->Planes;
3743 pData->cLogoBits = pOs2Hdr->BitCount;
3744 pData->LogoCompression = BMP_COMPRESS_NONE;
3745 pData->cLogoUsedColors = 0;
3746 break;
3747
3748 case BMP_HEADER_OS22:
3749 pOs22Hdr = (POS22HDR)pWinHdr;
3750 pData->cxLogo = pOs22Hdr->Width;
3751 pData->cyLogo = pOs22Hdr->Height;
3752 pData->cLogoPlanes = pOs22Hdr->Planes;
3753 pData->cLogoBits = pOs22Hdr->BitCount;
3754 pData->LogoCompression = pOs22Hdr->Compression;
3755 pData->cLogoUsedColors = pOs22Hdr->ClrUsed;
3756 break;
3757
3758 case BMP_HEADER_WIN3:
3759 pData->cxLogo = pWinHdr->Width;
3760 pData->cyLogo = pWinHdr->Height;
3761 pData->cLogoPlanes = pWinHdr->Planes;
3762 pData->cLogoBits = pWinHdr->BitCount;
3763 pData->LogoCompression = pWinHdr->Compression;
3764 pData->cLogoUsedColors = pWinHdr->ClrUsed;
3765 break;
3766
3767 default:
3768 AssertMsgFailed(("Unsupported bitmap header.\n"));
3769 break;
3770 }
3771
3772 if (pData->cxLogo > LOGO_MAX_WIDTH || pData->cyLogo > LOGO_MAX_HEIGHT)
3773 {
3774 AssertMsgFailed(("Bitmap %ux%u is too big.\n", pData->cxLogo, pData->cyLogo));
3775 return VERR_INVALID_PARAMETER;
3776 }
3777
3778 if (pData->cLogoPlanes != 1)
3779 {
3780 AssertMsgFailed(("Bitmap planes %u != 1.\n", pData->cLogoPlanes));
3781 return VERR_INVALID_PARAMETER;
3782 }
3783
3784 if (pData->cLogoBits != 4 && pData->cLogoBits != 8 && pData->cLogoBits != 24)
3785 {
3786 AssertMsgFailed(("Unsupported %u depth.\n", pData->cLogoBits));
3787 return VERR_INVALID_PARAMETER;
3788 }
3789
3790 if (pData->cLogoUsedColors > 256)
3791 {
3792 AssertMsgFailed(("Unsupported %u colors.\n", pData->cLogoUsedColors));
3793 return VERR_INVALID_PARAMETER;
3794 }
3795
3796 if (pData->LogoCompression != BMP_COMPRESS_NONE)
3797 {
3798 AssertMsgFailed(("Unsupported %u compression.\n", pData->LogoCompression));
3799 return VERR_INVALID_PARAMETER;
3800 }
3801
3802 /*
3803 * Read bitmap palette
3804 */
3805 if (!pData->cLogoUsedColors)
3806 pData->cLogoPalEntries = 1 << (pData->cLogoPlanes * pData->cLogoBits);
3807 else
3808 pData->cLogoPalEntries = pData->cLogoUsedColors;
3809
3810 if (pData->cLogoPalEntries)
3811 {
3812 const uint8_t *pu8Pal = pData->pu8Logo + sizeof(LOGOHDR) + sizeof(BMPINFO) + pWinHdr->Size; /* ASSUMES Size location (safe) */
3813
3814 for (i = 0; i <= pData->cLogoPalEntries; i++)
3815 {
3816 uint16_t j;
3817 uint32_t u32Pal = 0;
3818
3819 for (j = 0; j < 3; j++)
3820 {
3821 uint8_t b = *pu8Pal++;
3822 u32Pal <<= 8;
3823 u32Pal |= b;
3824 }
3825
3826 pu8Pal++; /* skip unused byte */
3827 pData->au32LogoPalette[i] = u32Pal;
3828 }
3829 }
3830
3831 /*
3832 * Bitmap data offset
3833 */
3834 pData->pu8LogoBitmap = pData->pu8Logo + sizeof(LOGOHDR) + bmpInfo->Offset;
3835 }
3836
3837 return VINF_SUCCESS;
3838}
3839
3840
3841/**
3842 * Show logo bitmap data.
3843 *
3844 * @returns VBox status code.
3845 *
3846 * @param cbDepth Logo depth.
3847 * @param xLogo Logo X position.
3848 * @param yLogo Logo Y position.
3849 * @param cxLogo Logo width.
3850 * @param cyLogo Logo height.
3851 * @param iStep Fade in/fade out step.
3852 * @param pu32Palette Palette data.
3853 * @param pu8Src Source buffer.
3854 * @param pu8Dst Destination buffer.
3855 */
3856static void vbeShowBitmap(uint16_t cBits, uint16_t xLogo, uint16_t yLogo, uint16_t cxLogo, uint16_t cyLogo, uint8_t iStep,
3857 const uint32_t *pu32Palette, const uint8_t *pu8Src, uint8_t *pu8Dst)
3858{
3859 uint16_t i;
3860 size_t cbPadBytes = 0;
3861 size_t cbLineDst = LOGO_MAX_WIDTH * 4;
3862 uint16_t cyLeft = cyLogo;
3863
3864 pu8Dst += xLogo * 4 + yLogo * cbLineDst;
3865
3866 switch (cBits)
3867 {
3868 case 1:
3869 pu8Dst += cyLogo * cbLineDst;
3870 cbPadBytes = 0;
3871 break;
3872
3873 case 4:
3874 if (((cxLogo % 8) == 0) || ((cxLogo % 8) > 6))
3875 cbPadBytes = 0;
3876 else if ((cxLogo % 8) <= 2)
3877 cbPadBytes = 3;
3878 else if ((cxLogo % 8) <= 4)
3879 cbPadBytes = 2;
3880 else
3881 cbPadBytes = 1;
3882 break;
3883
3884 case 8:
3885 cbPadBytes = ((cxLogo % 4) == 0) ? 0 : (4 - (cxLogo % 4));
3886 break;
3887
3888 case 24:
3889 cbPadBytes = cxLogo % 4;
3890 break;
3891 }
3892
3893 uint8_t j = 0, c = 0;
3894
3895 while (cyLeft-- > 0)
3896 {
3897 uint8_t *pu8TmpPtr = pu8Dst;
3898
3899 if (cBits != 1)
3900 j = 0;
3901
3902 for (i = 0; i < cxLogo; i++)
3903 {
3904 uint8_t pix;
3905
3906 switch (cBits)
3907 {
3908 case 1:
3909 {
3910 if (!j)
3911 c = *pu8Src++;
3912
3913 pix = (c & 1) ? 0xFF : 0;
3914 c >>= 1;
3915
3916 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3917 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3918 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3919 *pu8TmpPtr++;
3920
3921 j = (j + 1) % 8;
3922 break;
3923 }
3924
3925 case 4:
3926 {
3927 if (!j)
3928 c = *pu8Src++;
3929
3930 pix = (c >> 4) & 0xF;
3931 c <<= 4;
3932
3933 uint32_t u32Pal = pu32Palette[pix];
3934
3935 pix = (u32Pal >> 16) & 0xFF;
3936 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3937 pix = (u32Pal >> 8) & 0xFF;
3938 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3939 pix = u32Pal & 0xFF;
3940 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3941 *pu8TmpPtr++;
3942
3943 j = (j + 1) % 2;
3944 break;
3945 }
3946
3947 case 8:
3948 {
3949 uint32_t u32Pal = pu32Palette[*pu8Src++];
3950
3951 pix = (u32Pal >> 16) & 0xFF;
3952 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3953 pix = (u32Pal >> 8) & 0xFF;
3954 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3955 pix = u32Pal & 0xFF;
3956 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3957 *pu8TmpPtr++;
3958 break;
3959 }
3960
3961 case 24:
3962 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3963 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3964 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3965 *pu8TmpPtr++;
3966 break;
3967 }
3968 }
3969
3970 pu8Dst -= cbLineDst;
3971 pu8Src += cbPadBytes;
3972 }
3973}
3974
3975
3976
3977
3978/**
3979 * Port I/O Handler for BIOS Logo OUT operations.
3980 *
3981 * @returns VBox status code.
3982 *
3983 * @param pDevIns The device instance.
3984 * @param pvUser User argument - ignored.
3985 * @param Port Port number used for the IN operation.
3986 * @param u32 The value to output.
3987 * @param cb The value size in bytes.
3988 */
3989PDMBOTHCBDECL(int) vbeIOPortWriteCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3990{
3991 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3992 NOREF(pvUser);
3993 NOREF(Port);
3994
3995 Log(("vbeIOPortWriteCMDLogo: cb=%d u32=%#04x(%#04d) (byte)\n", cb, u32, u32));
3996
3997 if (cb == 2)
3998 {
3999 /* Get the logo command */
4000 switch (u32 & 0xFF00)
4001 {
4002 case LOGO_CMD_SET_OFFSET:
4003 pData->offLogoData = u32 & 0xFF;
4004 break;
4005
4006 case LOGO_CMD_SHOW_BMP:
4007 {
4008 uint8_t iStep = u32 & 0xFF;
4009 const uint8_t *pu8Src = pData->pu8LogoBitmap;
4010 uint8_t *pu8Dst;
4011 PLOGOHDR pLogoHdr = (PLOGOHDR)pData->pu8Logo;
4012 uint32_t offDirty = 0;
4013 uint16_t xLogo = (LOGO_MAX_WIDTH - pData->cxLogo) / 2;
4014 uint16_t yLogo = LOGO_MAX_HEIGHT - (LOGO_MAX_HEIGHT - pData->cyLogo) / 2;
4015
4016 if (pData->vram_size >= LOGO_MAX_SIZE * 2)
4017 pu8Dst = pData->vram_ptrHC + LOGO_MAX_SIZE;
4018 else
4019 pu8Dst = pData->vram_ptrHC;
4020
4021 /* Clear screen - except on power on... */
4022 if (!pData->fLogoClearScreen)
4023 {
4024 uint32_t *pu32TmpPtr = (uint32_t *)pu8Dst;
4025
4026 /* Clear vram */
4027 for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4028 {
4029 for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4030 *pu32TmpPtr++ = 0;
4031 }
4032 pData->fLogoClearScreen = true;
4033 }
4034
4035 /* Show the bitmap. */
4036 vbeShowBitmap(pData->cLogoBits, xLogo, yLogo,
4037 pData->cxLogo, pData->cyLogo,
4038 iStep, &pData->au32LogoPalette[0],
4039 pu8Src, pu8Dst);
4040
4041 /* Show the 'Press F12...' text. */
4042 if (pLogoHdr->fu8ShowBootMenu == 2)
4043 vbeShowBitmap(1, LOGO_F12TEXT_X, LOGO_F12TEXT_Y,
4044 LOGO_F12TEXT_WIDTH, LOGO_F12TEXT_HEIGHT,
4045 iStep, &pData->au32LogoPalette[0],
4046 &g_abLogoF12BootText[0], pu8Dst);
4047
4048 /* Blit the offscreen buffer. */
4049 if (pData->vram_size >= LOGO_MAX_SIZE * 2)
4050 {
4051 uint32_t *pu32TmpDst = (uint32_t *)pData->vram_ptrHC;
4052 uint32_t *pu32TmpSrc = (uint32_t *)(pData->vram_ptrHC + LOGO_MAX_SIZE);
4053 for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4054 {
4055 for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4056 *pu32TmpDst++ = *pu32TmpSrc++;
4057 }
4058 }
4059
4060 /* Set the dirty flags. */
4061 while (offDirty <= LOGO_MAX_SIZE)
4062 {
4063 vga_set_dirty(pData, offDirty);
4064 offDirty += PAGE_SIZE;
4065 }
4066 break;
4067 }
4068
4069 default:
4070 Log(("vbeIOPortWriteCMDLogo: invalid command %d\n", u32));
4071 pData->LogoCommand = LOGO_CMD_NOP;
4072 break;
4073 }
4074
4075 return VINF_SUCCESS;
4076 }
4077
4078 Log(("vbeIOPortWriteCMDLogo: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
4079 return VINF_SUCCESS;
4080}
4081
4082
4083/**
4084 * Port I/O Handler for BIOS Logo IN operations.
4085 *
4086 * @returns VBox status code.
4087 *
4088 * @param pDevIns The device instance.
4089 * @param pvUser User argument - ignored.
4090 * @param Port Port number used for the IN operation.
4091 * @param pu32 Where to store the result.
4092 * @param cb Number of bytes read.
4093 */
4094PDMBOTHCBDECL(int) vbeIOPortReadCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
4095{
4096 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4097 NOREF(pvUser);
4098 NOREF(Port);
4099
4100 PRTUINT64U p;
4101
4102 if (pData->offLogoData + cb > pData->cbLogo)
4103 {
4104 Log(("vbeIOPortReadCMDLogo: Requested address is out of Logo data!!! offLogoData=%#x(%d) cbLogo=%#x(%d)\n",
4105 pData->offLogoData, pData->offLogoData, pData->cbLogo, pData->cbLogo));
4106 return VINF_SUCCESS;
4107 }
4108 p = (PRTUINT64U)&pData->pu8Logo[pData->offLogoData];
4109
4110 switch (cb)
4111 {
4112 case 1: *pu32 = p->au8[0]; break;
4113 case 2: *pu32 = p->au16[0]; break;
4114 case 4: *pu32 = p->au32[0]; break;
4115 //case 8: *pu32 = p->au64[0]; break;
4116 default: AssertFailed(); break;
4117 }
4118 Log(("vbeIOPortReadCMDLogo: LogoOffset=%#x(%d) cb=%#x %.*Vhxs\n", pData->offLogoData, pData->offLogoData, cb, cb, pu32));
4119
4120 pData->LogoCommand = LOGO_CMD_NOP;
4121 pData->offLogoData += cb;
4122
4123 return VINF_SUCCESS;
4124}
4125
4126
4127
4128
4129/* -=-=-=-=-=- Ring 3: VGA BIOS I/Os -=-=-=-=-=- */
4130
4131/**
4132 * Port I/O Handler for VGA BIOS IN operations.
4133 *
4134 * @returns VBox status code.
4135 *
4136 * @param pDevIns The device instance.
4137 * @param pvUser User argument - ignored.
4138 * @param Port Port number used for the IN operation.
4139 * @param pu32 Where to store the result.
4140 * @param cb Number of bytes read.
4141 */
4142static DECLCALLBACK(int) vgaIOPortReadBIOS(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
4143{
4144 NOREF(pDevIns);
4145 NOREF(pvUser);
4146 NOREF(Port);
4147 NOREF(pu32);
4148 NOREF(cb);
4149 return VERR_IOM_IOPORT_UNUSED;
4150}
4151
4152/**
4153 * Port I/O Handler for VGA BIOS OUT operations.
4154 *
4155 * @returns VBox status code.
4156 *
4157 * @param pDevIns The device instance.
4158 * @param pvUser User argument - ignored.
4159 * @param Port Port number used for the IN operation.
4160 * @param u32 The value to output.
4161 * @param cb The value size in bytes.
4162 */
4163static DECLCALLBACK(int) vgaIOPortWriteBIOS(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
4164{
4165 static int lastWasNotNewline = 0; /* We are only called in a single-threaded way */
4166 /*
4167 * VGA BIOS char printing.
4168 */
4169 if ( cb == 1
4170 && Port == VBE_PRINTF_PORT)
4171 {
4172#if 0
4173 switch (u32)
4174 {
4175 case '\r': Log(("vgabios: <return>\n")); break;
4176 case '\n': Log(("vgabios: <newline>\n")); break;
4177 case '\t': Log(("vgabios: <tab>\n")); break;
4178 default:
4179 Log(("vgabios: %c\n", u32));
4180 }
4181#else
4182 if (lastWasNotNewline == 0)
4183 Log(("vgabios: "));
4184 if (u32 != '\r') /* return - is only sent in conjunction with '\n' */
4185 Log(("%c", u32));
4186 if (u32 == '\n')
4187 lastWasNotNewline = 0;
4188 else
4189 lastWasNotNewline = 1;
4190#endif
4191 return VINF_SUCCESS;
4192 }
4193
4194 /* not in use. */
4195 return VINF_SUCCESS;
4196}
4197
4198
4199/* -=-=-=-=-=- Ring 3: IBase -=-=-=-=-=- */
4200
4201/**
4202 * Queries an interface to the driver.
4203 *
4204 * @returns Pointer to interface.
4205 * @returns NULL if the interface was not supported by the driver.
4206 * @param pInterface Pointer to this interface structure.
4207 * @param enmInterface The requested interface identification.
4208 * @thread Any thread.
4209 */
4210static DECLCALLBACK(void *) vgaPortQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
4211{
4212 PVGASTATE pData = (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Base));
4213 switch (enmInterface)
4214 {
4215 case PDMINTERFACE_BASE:
4216 return &pData->Base;
4217 case PDMINTERFACE_DISPLAY_PORT:
4218 return &pData->Port;
4219 default:
4220 return NULL;
4221 }
4222}
4223
4224
4225/* -=-=-=-=-=- Ring 3: Dummy IDisplayConnector -=-=-=-=-=- */
4226
4227/**
4228 * Resize the display.
4229 * This is called when the resolution changes. This usually happens on
4230 * request from the guest os, but may also happen as the result of a reset.
4231 *
4232 * @param pInterface Pointer to this interface.
4233 * @param cx New display width.
4234 * @param cy New display height
4235 * @thread The emulation thread.
4236 */
4237static DECLCALLBACK(int) vgaDummyResize(PPDMIDISPLAYCONNECTOR pInterface, uint32_t bpp, void *pvVRAM, uint32_t cbLine, uint32_t cx, uint32_t cy)
4238{
4239 return VINF_SUCCESS;
4240}
4241
4242
4243/**
4244 * Update a rectangle of the display.
4245 * PDMIDISPLAYPORT::pfnUpdateDisplay is the caller.
4246 *
4247 * @param pInterface Pointer to this interface.
4248 * @param x The upper left corner x coordinate of the rectangle.
4249 * @param y The upper left corner y coordinate of the rectangle.
4250 * @param cx The width of the rectangle.
4251 * @param cy The height of the rectangle.
4252 * @thread The emulation thread.
4253 */
4254static DECLCALLBACK(void) vgaDummyUpdateRect(PPDMIDISPLAYCONNECTOR pInterface, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4255{
4256}
4257
4258
4259/**
4260 * Refresh the display.
4261 *
4262 * The interval between these calls is set by
4263 * PDMIDISPLAYPORT::pfnSetRefreshRate(). The driver should call
4264 * PDMIDISPLAYPORT::pfnUpdateDisplay() if it wishes to refresh the
4265 * display. PDMIDISPLAYPORT::pfnUpdateDisplay calls pfnUpdateRect with
4266 * the changed rectangles.
4267 *
4268 * @param pInterface Pointer to this interface.
4269 * @thread The emulation thread.
4270 */
4271static DECLCALLBACK(void) vgaDummyRefresh(PPDMIDISPLAYCONNECTOR pInterface)
4272{
4273}
4274
4275
4276/* -=-=-=-=-=- Ring 3: IDisplayPort -=-=-=-=-=- */
4277
4278/** Converts a display port interface pointer to a vga state pointer. */
4279#define IDISPLAYPORT_2_VGASTATE(pInterface) ( (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Port)) )
4280
4281
4282/**
4283 * Update the display with any changed regions.
4284 *
4285 * @param pInterface Pointer to this interface.
4286 * @see PDMIKEYBOARDPORT::pfnUpdateDisplay() for details.
4287 */
4288static DECLCALLBACK(int) vgaPortUpdateDisplay(PPDMIDISPLAYPORT pInterface)
4289{
4290 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4291 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4292
4293#ifdef DEBUG_sunlover
4294 LogFlow(("vgaPortUpdateDisplay\n"));
4295#endif /* DEBUG_sunlover */
4296
4297 /* This should be called only in non VBVA mode. */
4298
4299 int rc = vga_update_display(pData);
4300 if (rc != VINF_SUCCESS)
4301 return rc;
4302
4303 if (pData->fHaveDirtyBits && pData->GCPhysVRAM && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4304 {
4305 PPDMDEVINS pDevIns = pData->pDevInsHC;
4306 PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4307 pData->fHaveDirtyBits = false;
4308 }
4309
4310 return VINF_SUCCESS;
4311}
4312
4313
4314/**
4315 * Update the entire display.
4316 *
4317 * @param pInterface Pointer to this interface.
4318 * @see PDMIKEYBOARDPORT::pfnUpdateDisplayAll() for details.
4319 */
4320static DECLCALLBACK(int) vgaPortUpdateDisplayAll(PPDMIDISPLAYPORT pInterface)
4321{
4322 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4323 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4324
4325 /* This is called both in VBVA mode and normal modes. */
4326
4327#ifdef DEBUG_sunlover
4328 LogFlow(("vgaPortUpdateDisplayAll\n"));
4329#endif /* DEBUG_sunlover */
4330
4331 pData->graphic_mode = -1; /* force full update */
4332
4333 int rc = vga_update_display(pData);
4334
4335 /* The dirty bits array has been just cleared, reset handlers as well. */
4336 if (pData->GCPhysVRAM && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4337 {
4338 PPDMDEVINS pDevIns = pData->pDevInsHC;
4339 PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4340 }
4341
4342 return rc;
4343}
4344
4345
4346/**
4347 * Sets the refresh rate and restart the timer.
4348 *
4349 * @returns VBox status code.
4350 * @param pInterface Pointer to this interface.
4351 * @param cMilliesInterval Number of millies between two refreshes.
4352 * @see PDMIKEYBOARDPORT::pfnSetRefreshRate() for details.
4353 */
4354static DECLCALLBACK(int) vgaPortSetRefreshRate(PPDMIDISPLAYPORT pInterface, uint32_t cMilliesInterval)
4355{
4356 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4357
4358 pData->cMilliesRefreshInterval = cMilliesInterval;
4359 if (cMilliesInterval)
4360 return TMTimerSetMillies(pData->RefreshTimer, cMilliesInterval);
4361 return TMTimerStop(pData->RefreshTimer);
4362}
4363
4364
4365/** @copydoc PDMIDISPLAYPORT::pfnQueryColorDepth */
4366static DECLCALLBACK(int) vgaPortQueryColorDepth(PPDMIDISPLAYPORT pInterface, uint32_t *pcBits)
4367{
4368 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4369
4370 if (!pcBits)
4371 return VERR_INVALID_PARAMETER;
4372 *pcBits = vga_get_bpp(pData);
4373 return VINF_SUCCESS;
4374}
4375
4376/**
4377 * Create a 32-bbp snapshot of the display.
4378 *
4379 * @param pInterface Pointer to this interface.
4380 * @param pvData Pointer the buffer to copy the bits to.
4381 * @param cbData Size of the buffer.
4382 * @param pcx Where to store the width of the bitmap. (optional)
4383 * @param pcy Where to store the height of the bitmap. (optional)
4384 * @param pcbData Where to store the actual size of the bitmap. (optional)
4385 * @see PDMIKEYBOARDPORT::pfnSnapshot() for details.
4386 */
4387static DECLCALLBACK(int) vgaPortSnapshot(PPDMIDISPLAYPORT pInterface, void *pvData, size_t cbData, uint32_t *pcx, uint32_t *pcy, size_t *pcbData)
4388{
4389 /* @todo r=sunlover: replace the method with a direct VRAM rendering like in vgaPortUpdateDisplayRect. */
4390 PPDMIDISPLAYCONNECTOR pConnector;
4391 PDMIDISPLAYCONNECTOR Connector;
4392 int32_t graphic_mode;
4393 uint32_t fRenderVRAM;
4394 size_t cbRequired;
4395 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4396 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4397 LogFlow(("vgaPortSnapshot: pvData=%p cbData=%d pcx=%p pcy=%p pcbData=%p\n", pvData, cbData, pcx, pcy, pcbData));
4398
4399 /*
4400 * Validate input.
4401 */
4402 if (!pvData)
4403 return VERR_INVALID_PARAMETER;
4404
4405 /*
4406 * Do a regular refresh first to resolve any pending resize issues.
4407 *
4408 * 20060317 It used to be pfnUpdateDisplay, but by VBVA design
4409 * only pfnUpdateDisplayAll is allowed to be called in VBVA mode.
4410 * Also since the goal here is to have updated display for screenshot,
4411 * the UpdateDisplayAll is even more logical to call. (sunlover)
4412 */
4413 pInterface->pfnUpdateDisplayAll(pInterface);
4414
4415 /*
4416 * Validate the buffer size.
4417 */
4418 cbRequired = RT_ALIGN_Z(pData->last_scr_width, 4) * pData->last_scr_height * 4;
4419 if (cbRequired > cbData)
4420 {
4421 Log(("vgaPortSnapshot: %d bytes are required, a buffer of %d bytes is profiled.\n", cbRequired, cbData));
4422 return VERR_BUFFER_OVERFLOW;
4423 }
4424
4425 /*
4426 * Temporarily replace the display connector interface with a fake one.
4427 */
4428 Connector.pu8Data = (uint8_t*)pvData;
4429 Connector.cBits = 32;
4430 Connector.cx = pData->pDrv->cx;
4431 Connector.cy = pData->pDrv->cy;
4432 Connector.cbScanline = RT_ALIGN_32(Connector.cx, 4) * 4;
4433 Connector.pfnRefresh = vgaDummyRefresh;
4434 Connector.pfnResize = vgaDummyResize;
4435 Connector.pfnUpdateRect = vgaDummyUpdateRect;
4436
4437 /* save & replace state data. */
4438 pConnector = pData->pDrv;
4439 pData->pDrv = &Connector;
4440 graphic_mode = pData->graphic_mode;
4441 pData->graphic_mode = -1; /* force a full refresh. */
4442 fRenderVRAM = pData->fRenderVRAM;
4443 pData->fRenderVRAM = 1; /* force the guest VRAM rendering to the given buffer. */
4444
4445 /* make the snapshot. */
4446 int rc = vga_update_display(pData);
4447
4448 /* restore */
4449 pData->pDrv = pConnector;
4450 pData->graphic_mode = graphic_mode;
4451 pData->fRenderVRAM = fRenderVRAM;
4452
4453 if (rc != VINF_SUCCESS)
4454 return rc;
4455
4456 /*
4457 * Return the result.
4458 */
4459 if (pcx)
4460 *pcx = Connector.cx;
4461 if (pcy)
4462 *pcy = Connector.cy;
4463 if (pcbData)
4464 *pcbData = cbRequired;
4465 LogFlow(("vgaPortSnapshot: returns VINF_SUCCESS (cx=%d cy=%d cbData=%d)\n", Connector.cx, Connector.cy, cbRequired));
4466 return VINF_SUCCESS;
4467}
4468
4469
4470/**
4471 * Copy bitmap to the display.
4472 *
4473 * @param pInterface Pointer to this interface.
4474 * @param pvData Pointer to the bitmap bits.
4475 * @param x The upper left corner x coordinate of the destination rectangle.
4476 * @param y The upper left corner y coordinate of the destination rectangle.
4477 * @param cx The width of the source and destination rectangles.
4478 * @param cy The height of the source and destination rectangles.
4479 * @see PDMIDISPLAYPORT::pfnDisplayBlt() for details.
4480 */
4481static DECLCALLBACK(int) vgaPortDisplayBlt(PPDMIDISPLAYPORT pInterface, const void *pvData, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4482{
4483 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4484 int rc = VINF_SUCCESS;
4485 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4486 LogFlow(("vgaPortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy));
4487
4488 /*
4489 * Validate input.
4490 */
4491 if ( pvData
4492 && x < pData->pDrv->cx
4493 && cx <= pData->pDrv->cx
4494 && cx + x <= pData->pDrv->cx
4495 && y < pData->pDrv->cy
4496 && cy <= pData->pDrv->cy
4497 && cy + y <= pData->pDrv->cy)
4498 {
4499 /*
4500 * Determin bytes per pixel in the destination buffer.
4501 */
4502 size_t cbPixelDst = 0;
4503 switch (pData->pDrv->cBits)
4504 {
4505 case 8:
4506 cbPixelDst = 1;
4507 break;
4508 case 15:
4509 case 16:
4510 cbPixelDst = 2;
4511 break;
4512 case 24:
4513 cbPixelDst = 3;
4514 break;
4515 case 32:
4516 cbPixelDst = 4;
4517 break;
4518 default:
4519 rc = VERR_INVALID_PARAMETER;
4520 break;
4521 }
4522 if (VBOX_SUCCESS(rc))
4523 {
4524 /*
4525 * The blitting loop.
4526 */
4527 size_t cbLineSrc = RT_ALIGN_Z(cx, 4) * 4;
4528 uint8_t *pu8Src = (uint8_t *)pvData;
4529 size_t cbLineDst = pData->pDrv->cbScanline;
4530 uint8_t *pu8Dst = pData->pDrv->pu8Data + y * cbLineDst + x * cbPixelDst;
4531 uint32_t cyLeft = cy;
4532 vga_draw_line_func *pfnVgaDrawLine = vga_draw_line_table[VGA_DRAW_LINE32 * 4 + get_depth_index(pData->pDrv->cBits)];
4533 Assert(pfnVgaDrawLine);
4534 while (cyLeft-- > 0)
4535 {
4536 pfnVgaDrawLine(pData, pu8Dst, pu8Src, cx);
4537 pu8Dst += cbLineDst;
4538 pu8Src += cbLineSrc;
4539 }
4540
4541 /*
4542 * Invalidate the area.
4543 */
4544 pData->pDrv->pfnUpdateRect(pData->pDrv, x, y, cx, cy);
4545 }
4546 }
4547 else
4548 rc = VERR_INVALID_PARAMETER;
4549
4550 LogFlow(("vgaPortDisplayBlt: returns %Vrc\n", rc));
4551 return rc;
4552}
4553
4554static DECLCALLBACK(void) vgaPortUpdateDisplayRect (PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t w, uint32_t h)
4555{
4556 uint32_t v;
4557 vga_draw_line_func *vga_draw_line;
4558
4559 uint32_t cbPixelDst;
4560 uint32_t cbLineDst;
4561 uint8_t *pu8Dst;
4562
4563 uint32_t cbPixelSrc;
4564 uint32_t cbLineSrc;
4565 uint8_t *pu8Src;
4566
4567 uint32_t u32OffsetSrc, u32Dummy;
4568
4569 PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
4570
4571#ifdef DEBUG_sunlover
4572 LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d\n", x, y, w, h));
4573#endif /* DEBUG_sunlover */
4574
4575 Assert(pInterface);
4576 Assert(s->pDrv);
4577 Assert(s->pDrv->pu8Data);
4578
4579 /* Check if there is something to do at all. */
4580 if (!s->fRenderVRAM)
4581 {
4582 /* The framebuffer uses the guest VRAM directly. */
4583#ifdef DEBUG_sunlover
4584 LogFlow(("vgaPortUpdateDisplayRect: nothing to do fRender is false.\n"));
4585#endif /* DEBUG_sunlover */
4586 return;
4587 }
4588
4589 /* Correct negative x and y coordinates. */
4590 if (x < 0)
4591 {
4592 x += w; /* Compute xRight which is also the new width. */
4593 w = (x < 0) ? 0 : x;
4594 x = 0;
4595 }
4596
4597 if (y < 0)
4598 {
4599 y += h; /* Compute yBottom, which is also the new height. */
4600 h = (y < 0) ? 0 : y;
4601 y = 0;
4602 }
4603
4604 /* Also check if coords are greater than the display resolution. */
4605 if (x + w > s->pDrv->cx)
4606 {
4607#ifndef VBOX
4608 w = s->pDrv->cx > x? s->pDrv->cx - x: 0;
4609#else
4610 // x < 0 is not possible here
4611 w = s->pDrv->cx > (uint32_t)x? s->pDrv->cx - x: 0;
4612#endif
4613 }
4614
4615 if (y + h > s->pDrv->cy)
4616 {
4617#ifndef VBOX
4618 h = s->pDrv->cy > y? s->pDrv->cy - y: 0;
4619#else
4620 // y < 0 is not possible here
4621 h = s->pDrv->cy > (uint32_t)y? s->pDrv->cy - y: 0;
4622#endif
4623 }
4624
4625#ifdef DEBUG_sunlover
4626 LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d (corrected coords)\n", x, y, w, h));
4627#endif /* DEBUG_sunlover */
4628
4629 /* Check if there is something to do at all. */
4630 if (w == 0 || h == 0)
4631 {
4632 /* Empty rectangle. */
4633#ifdef DEBUG_sunlover
4634 LogFlow(("vgaPortUpdateDisplayRect: nothing to do: %dx%d\n", w, h));
4635#endif /* DEBUG_sunlover */
4636 return;
4637 }
4638
4639 /** @todo This method should be made universal and not only for VBVA.
4640 * VGA_DRAW_LINE* must be selected and src/dst address calculation
4641 * changed.
4642 */
4643
4644 /* Choose the rendering function. */
4645 switch(s->get_bpp(s))
4646 {
4647 default:
4648 case 0:
4649 /* A LFB mode is already disabled, but the callback is still called
4650 * by Display because VBVA buffer is being flushed.
4651 * Nothing to do, just return.
4652 */
4653 return;
4654 case 8:
4655 v = VGA_DRAW_LINE8;
4656 break;
4657 case 15:
4658 v = VGA_DRAW_LINE15;
4659 break;
4660 case 16:
4661 v = VGA_DRAW_LINE16;
4662 break;
4663 case 24:
4664 v = VGA_DRAW_LINE24;
4665 break;
4666 case 32:
4667 v = VGA_DRAW_LINE32;
4668 break;
4669 }
4670
4671 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
4672
4673 /* Compute source and destination addresses and pitches. */
4674 cbPixelDst = (s->pDrv->cBits + 7) / 8;
4675 cbLineDst = s->pDrv->cbScanline;
4676 pu8Dst = s->pDrv->pu8Data + y * cbLineDst + x * cbPixelDst;
4677
4678 cbPixelSrc = (s->get_bpp(s) + 7) / 8;
4679 s->get_offsets (s, &cbLineSrc, &u32OffsetSrc, &u32Dummy);
4680
4681 /* Assume that rendering is performed only on visible part of VRAM.
4682 * This is true because coordinates were verified.
4683 */
4684 pu8Src = s->vram_ptrHC;
4685 pu8Src += u32OffsetSrc + y * cbLineSrc + x * cbPixelSrc;
4686
4687 /* Render VRAM to framebuffer. */
4688
4689#ifdef DEBUG_sunlover
4690 LogFlow(("vgaPortUpdateDisplayRect: dst: %p, %d, %d. src: %p, %d, %d\n", pu8Dst, cbLineDst, cbPixelDst, pu8Src, cbLineSrc, cbPixelSrc));
4691#endif /* DEBUG_sunlover */
4692
4693 while (h-- > 0)
4694 {
4695 vga_draw_line (s, pu8Dst, pu8Src, w);
4696 pu8Dst += cbLineDst;
4697 pu8Src += cbLineSrc;
4698 }
4699
4700#ifdef DEBUG_sunlover
4701 LogFlow(("vgaPortUpdateDisplayRect: completed.\n"));
4702#endif /* DEBUG_sunlover */
4703}
4704
4705static DECLCALLBACK(void) vgaPortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender)
4706{
4707 PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
4708
4709 LogFlow(("vgaPortSetRenderVRAM: fRender = %d\n", fRender));
4710
4711 s->fRenderVRAM = fRender;
4712}
4713
4714
4715static DECLCALLBACK(void) vgaTimerRefresh(PPDMDEVINS pDevIns, PTMTIMER pTimer)
4716{
4717 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4718 if (pData->pDrv)
4719 pData->pDrv->pfnRefresh(pData->pDrv);
4720 if (pData->cMilliesRefreshInterval)
4721 TMTimerSetMillies(pTimer, pData->cMilliesRefreshInterval);
4722}
4723
4724
4725/* -=-=-=-=-=- Ring 3: PCI Device -=-=-=-=-=- */
4726
4727/**
4728 * Callback function for unmapping and/or mapping the VRAM MMIO2 region (called by the PCI bus).
4729 *
4730 * @return VBox status code.
4731 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4732 * @param iRegion The region number.
4733 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4734 * I/O port, else it's a physical address.
4735 * This address is *NOT* relative to pci_mem_base like earlier!
4736 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4737 */
4738static DECLCALLBACK(int) vgaR3IORegionMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4739{
4740 int rc;
4741 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4742 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4743 LogFlow(("vgaR3IORegionMap: iRegion=%d GCPhysAddress=%VGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4744 AssertReturn(iRegion == 0 && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
4745
4746 if (GCPhysAddress != NIL_RTGCPHYS)
4747 {
4748 /*
4749 * Mapping the VRAM.
4750 */
4751 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
4752 AssertRC(rc);
4753 if (RT_SUCCESS(rc))
4754 {
4755 rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
4756 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
4757 GCPhysAddress, GCPhysAddress + (pData->vram_size - 1),
4758 vgaR3LFBAccessHandler, pData,
4759 g_DeviceVga.szR0Mod, "vgaR0LFBAccessHandler", pDevIns->pvInstanceDataR0,
4760 g_DeviceVga.szGCMod, "vgaGCLFBAccessHandler", pDevIns->pvInstanceDataGC,
4761 "VGA LFB");
4762 AssertRC(rc);
4763 if (RT_SUCCESS(rc))
4764 pData->GCPhysVRAM = GCPhysAddress;
4765 }
4766 }
4767 else
4768 {
4769 /*
4770 * Unmapping of the VRAM in progress.
4771 * Deregister the access handler so PGM doesn't get upset.
4772 */
4773 Assert(pData->GCPhysVRAM);
4774 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4775 AssertRC(rc);
4776 pData->GCPhysVRAM = 0;
4777 }
4778 return rc;
4779}
4780
4781
4782/* -=-=-=-=-=- Ring3: Misc Wrappers -=-=-=-=-=- */
4783
4784/**
4785 * Saves a state of the VGA device.
4786 *
4787 * @returns VBox status code.
4788 * @param pDevIns The device instance.
4789 * @param pSSMHandle The handle to save the state to.
4790 */
4791static DECLCALLBACK(int) vgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4792{
4793 vga_save(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE));
4794 return VINF_SUCCESS;
4795}
4796
4797
4798/**
4799 * Loads a saved VGA device state.
4800 *
4801 * @returns VBox status code.
4802 * @param pDevIns The device instance.
4803 * @param pSSMHandle The handle to the saved state.
4804 * @param u32Version The data unit version number.
4805 */
4806static DECLCALLBACK(int) vgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
4807{
4808 if (vga_load(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE), u32Version))
4809 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4810 return VINF_SUCCESS;
4811}
4812
4813
4814/* -=-=-=-=-=- Ring 3: Device callbacks -=-=-=-=-=- */
4815
4816/**
4817 * Reset notification.
4818 *
4819 * @returns VBox status.
4820 * @param pDevIns The device instance data.
4821 */
4822static DECLCALLBACK(void) vgaR3Reset(PPDMDEVINS pDevIns)
4823{
4824 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4825 char *pchStart;
4826 char *pchEnd;
4827 LogFlow(("vgaReset\n"));
4828
4829 /* Clear the VRAM ourselves. */
4830 if (pData->vram_ptrHC && pData->vram_size)
4831 {
4832#ifdef LOG_ENABLED /** @todo separate function. */
4833 /* First dump the textmode contents to the log; handy for capturing Windows blue screens. */
4834 uint8_t graphic_mode;
4835 VGAState *s = pData;
4836
4837 if (!(s->ar_index & 0x20)) {
4838 graphic_mode = GMODE_BLANK;
4839 } else {
4840 graphic_mode = s->gr[6] & 1;
4841 }
4842 switch(graphic_mode)
4843 case GMODE_TEXT:
4844 {
4845 int cw, height, width, cheight, cx_min, cx_max, cy, cx;
4846 int x_incr;
4847 uint8_t *s1, *src, ch, cattr;
4848 int line_offset;
4849 uint16_t ch_attr;
4850
4851 line_offset = s->line_offset;
4852 s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 4);
4853
4854 /* total width & height */
4855 cheight = (s->cr[9] & 0x1f) + 1;
4856 cw = 8;
4857 if (!(s->sr[1] & 0x01))
4858 cw = 9;
4859 if (s->sr[1] & 0x08)
4860 cw = 16; /* NOTE: no 18 pixel wide */
4861 x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
4862 width = (s->cr[0x01] + 1);
4863 if (s->cr[0x06] == 100) {
4864 /* ugly hack for CGA 160x100x16 - explain me the logic */
4865 height = 100;
4866 } else {
4867 height = s->cr[0x12] |
4868 ((s->cr[0x07] & 0x02) << 7) |
4869 ((s->cr[0x07] & 0x40) << 3);
4870 height = (height + 1) / cheight;
4871 }
4872 if ((height * width) > CH_ATTR_SIZE) {
4873 /* better than nothing: exit if transient size is too big */
4874 break;
4875 }
4876 RTLogPrintf("VGA textmode BEGIN (%dx%d):\n\n", height, width);
4877 for(cy = 0; cy < height; cy++) {
4878 src = s1;
4879 cx_min = width;
4880 cx_max = -1;
4881 for(cx = 0; cx < width; cx++) {
4882 ch_attr = *(uint16_t *)src;
4883 if (cx < cx_min)
4884 cx_min = cx;
4885 if (cx > cx_max)
4886 cx_max = cx;
4887# ifdef WORDS_BIGENDIAN
4888 ch = ch_attr >> 8;
4889 cattr = ch_attr & 0xff;
4890# else
4891 ch = ch_attr & 0xff;
4892 cattr = ch_attr >> 8;
4893# endif
4894 RTLogPrintf("%c", ch);
4895
4896 src += 4;
4897 }
4898 if (cx_max != -1)
4899 RTLogPrintf("\n");
4900
4901 s1 += line_offset;
4902 }
4903 RTLogPrintf("VGA textmode END:\n\n");
4904 }
4905
4906#endif /* LOG_ENABLED */
4907 memset(pData->vram_ptrHC, 0, pData->vram_size);
4908 }
4909
4910 /*
4911 * Zero most of it.
4912 *
4913 * Unlike vga_reset we're leaving out a few members which believe must
4914 * remain unchanged....
4915 */
4916 /* 1st part. */
4917 pchStart = (char *)&pData->latch;
4918 pchEnd = (char *)&pData->invalidated_y_table;
4919 memset(pchStart, 0, pchEnd - pchStart);
4920
4921 /* 2nd part. */
4922 pchStart = (char *)&pData->last_palette;
4923 pchEnd = (char *)&pData->u32Marker;
4924 memset(pchStart, 0, pchEnd - pchStart);
4925
4926
4927 /*
4928 * Restore and re-init some bits.
4929 */
4930 pData->get_bpp = vga_get_bpp;
4931 pData->get_offsets = vga_get_offsets;
4932 pData->get_resolution = vga_get_resolution;
4933 pData->graphic_mode = -1; /* Force full update. */
4934#ifdef CONFIG_BOCHS_VBE
4935 pData->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
4936 pData->vbe_regs[VBE_DISPI_INDEX_VBOX_VIDEO] = 0;
4937 pData->vbe_bank_mask = ((pData->vram_size >> 16) - 1);
4938#endif /* CONFIG_BOCHS_VBE */
4939
4940 /*
4941 * Reset the LBF mapping.
4942 */
4943 pData->fLFBUpdated = false;
4944 if ( ( pData->fGCEnabled
4945 || pData->fR0Enabled)
4946 && pData->GCPhysVRAM
4947 && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4948 {
4949 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4950 AssertRC(rc);
4951 }
4952
4953 /*
4954 * Reset the logo data.
4955 */
4956 pData->LogoCommand = LOGO_CMD_NOP;
4957 pData->offLogoData = 0;
4958
4959 /* notify port handler */
4960 if (pData->pDrv)
4961 pData->pDrv->pfnReset(pData->pDrv);
4962}
4963
4964
4965/**
4966 * Device relocation callback.
4967 *
4968 * @param pDevIns Pointer to the device instance.
4969 * @param offDelta The relocation delta relative to the old location.
4970 *
4971 * @see FNPDMDEVRELOCATE for details.
4972 */
4973static DECLCALLBACK(void) vgaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4974{
4975 if (offDelta)
4976 {
4977 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4978 LogFlow(("vgaRelocate: offDelta = %08X\n", offDelta));
4979
4980 pData->GCPtrLFBHandler += offDelta;
4981 pData->vram_ptrGC += offDelta;
4982 }
4983}
4984
4985
4986/**
4987 * Attach command.
4988 *
4989 * This is called to let the device attach to a driver for a specified LUN
4990 * during runtime. This is not called during VM construction, the device
4991 * constructor have to attach to all the available drivers.
4992 *
4993 * This is like plugging in the monitor after turning on the PC.
4994 *
4995 * @returns VBox status code.
4996 * @param pDevIns The device instance.
4997 * @param iLUN The logical unit which is being detached.
4998 */
4999static DECLCALLBACK(int) vgaAttach(PPDMDEVINS pDevIns, unsigned iLUN)
5000{
5001 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5002 switch (iLUN)
5003 {
5004 /* LUN #0: Display port. */
5005 case 0:
5006 {
5007 int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pData->Base, &pData->pDrvBase, "Display Port");
5008 if (VBOX_SUCCESS(rc))
5009 {
5010 pData->pDrv = (PDMIDISPLAYCONNECTOR*)pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_DISPLAY_CONNECTOR);
5011 if (pData->pDrv)
5012 {
5013 /* pData->pDrv->pu8Data can be NULL when there is no framebuffer. */
5014 if ( pData->pDrv->pfnRefresh
5015 && pData->pDrv->pfnResize
5016 && pData->pDrv->pfnUpdateRect)
5017 rc = VINF_SUCCESS;
5018 else
5019 {
5020 Assert(pData->pDrv->pfnRefresh);
5021 Assert(pData->pDrv->pfnResize);
5022 Assert(pData->pDrv->pfnUpdateRect);
5023 pData->pDrv = NULL;
5024 pData->pDrvBase = NULL;
5025 rc = VERR_INTERNAL_ERROR;
5026 }
5027 }
5028 else
5029 {
5030 AssertMsgFailed(("LUN #0 doesn't have a display connector interface! rc=%Vrc\n", rc));
5031 pData->pDrvBase = NULL;
5032 rc = VERR_PDM_MISSING_INTERFACE;
5033 }
5034 }
5035 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5036 {
5037 Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
5038 rc = VINF_SUCCESS;
5039 }
5040 else
5041 AssertMsgFailed(("Failed to attach LUN #0! rc=%Vrc\n", rc));
5042 return rc;
5043 }
5044
5045 default:
5046 AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
5047 return VERR_PDM_NO_SUCH_LUN;
5048 }
5049}
5050
5051
5052/**
5053 * Detach notification.
5054 *
5055 * This is called when a driver is detaching itself from a LUN of the device.
5056 * The device should adjust it's state to reflect this.
5057 *
5058 * This is like unplugging the monitor while the PC is still running.
5059 *
5060 * @param pDevIns The device instance.
5061 * @param iLUN The logical unit which is being detached.
5062 */
5063static DECLCALLBACK(void) vgaDetach(PPDMDEVINS pDevIns, unsigned iLUN)
5064{
5065 /*
5066 * Reset the interfaces and update the controller state.
5067 */
5068 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5069 switch (iLUN)
5070 {
5071 /* LUN #0: Display port. */
5072 case 0:
5073 pData->pDrv = NULL;
5074 pData->pDrvBase = NULL;
5075 break;
5076
5077 default:
5078 AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
5079 break;
5080 }
5081}
5082
5083
5084
5085/**
5086 * Construct a VGA device instance for a VM.
5087 *
5088 * @returns VBox status.
5089 * @param pDevIns The device instance data.
5090 * If the registration structure is needed, pDevIns->pDevReg points to it.
5091 * @param iInstance Instance number. Use this to figure out which registers and such to use.
5092 * The device number is also found in pDevIns->iInstance, but since it's
5093 * likely to be freqently used PDM passes it as parameter.
5094 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
5095 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
5096 * iInstance it's expected to be used a bit in this function.
5097 */
5098static DECLCALLBACK(int) vgaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
5099{
5100 static bool fExpandDone = false;
5101 bool f;
5102 int rc;
5103 unsigned i;
5104 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5105 PVM pVM = PDMDevHlpGetVM(pDevIns);
5106#ifdef VBE_NEW_DYN_LIST
5107 uint32_t cCustomModes;
5108 uint32_t cyReduction;
5109 PVBEHEADER pVBEDataHdr;
5110 ModeInfoListItem *pCurMode;
5111 unsigned cb;
5112#endif
5113 Assert(iInstance == 0);
5114 Assert(pVM);
5115
5116 /*
5117 * Init static data.
5118 */
5119 if (!fExpandDone)
5120 {
5121 fExpandDone = true;
5122 vga_init_expand();
5123 }
5124
5125 /*
5126 * Validate configuration.
5127 */
5128 if (!CFGMR3AreValuesValid(pCfgHandle, "VRamSize\0"
5129 "GCEnabled\0"
5130 "R0Enabled\0"
5131 "FadeIn\0"
5132 "FadeOut\0"
5133 "LogoTime\0"
5134 "LogoFile\0"
5135 "ShowBootMenu\0"
5136 "CustomVideoModes\0"
5137 "HeightReduction\0"
5138 "CustomVideoMode1\0"
5139 "CustomVideoMode2\0"
5140 "CustomVideoMode3\0"
5141 "CustomVideoMode4\0"
5142 "CustomVideoMode5\0"
5143 "CustomVideoMode6\0"
5144 "CustomVideoMode7\0"
5145 "CustomVideoMode8\0"
5146 "CustomVideoMode9\0"
5147 "CustomVideoMode10\0"
5148 "CustomVideoMode11\0"
5149 "CustomVideoMode12\0"
5150 "CustomVideoMode13\0"
5151 "CustomVideoMode14\0"
5152 "CustomVideoMode15\0"
5153 "CustomVideoMode16\0"))
5154 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5155 N_("Invalid configuration for vga device"));
5156
5157 /*
5158 * Init state data.
5159 */
5160 rc = CFGMR3QueryU32(pCfgHandle, "VRamSize", &pData->vram_size);
5161 if (VBOX_FAILURE(rc) || !pData->vram_size)
5162 pData->vram_size = VGA_VRAM_DEFAULT;
5163 else if (pData->vram_size > VGA_VRAM_MAX)
5164 {
5165 AssertMsgFailed(("vram_size=%d max=%d\n", pData->vram_size, VGA_VRAM_MAX));
5166 pData->vram_size = VGA_VRAM_MAX;
5167 }
5168 else if (pData->vram_size < VGA_VRAM_MIN)
5169 {
5170 AssertMsgFailed(("vram_size=%d min=%d\n", pData->vram_size, VGA_VRAM_MIN));
5171 pData->vram_size = RT_ALIGN_32(pData->vram_size, _1M);
5172 }
5173 Log(("VGA: VRamSize=%#x\n", pData->vram_size));
5174
5175 pData->fGCEnabled = true;
5176 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &f);
5177 if (VBOX_SUCCESS(rc) && !f)
5178 pData->fGCEnabled = false;
5179 Log(("VGA: fGCEnabled=%d\n", pData->fGCEnabled));
5180
5181 pData->fR0Enabled = true;
5182 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &f);
5183 if (VBOX_SUCCESS(rc) && !f)
5184 pData->fR0Enabled = false;
5185 Log(("VGA: fR0Enabled=%d\n", pData->fR0Enabled));
5186
5187 pData->pDevInsHC = pDevIns;
5188
5189 vgaR3Reset(pDevIns);
5190
5191 /* The PCI devices configuration. */
5192 pData->Dev.config[0x00] = 0xee; /* PCI vendor, just a free bogus value */
5193 pData->Dev.config[0x01] = 0x80;
5194
5195 pData->Dev.config[0x02] = 0xef; /* Device ID */
5196 pData->Dev.config[0x03] = 0xbe;
5197
5198 pData->Dev.config[0x0a] = 0x00; /* VGA controller */
5199 pData->Dev.config[0x0b] = 0x03;
5200 pData->Dev.config[0x0e] = 0x00; /* header_type */
5201
5202 /* The LBF access handler - error handling is better here than in the map function. */
5203 rc = PDMR3GetSymbolGCLazy(pVM, pDevIns->pDevReg->szGCMod, "vgaGCLFBAccessHandler", &pData->GCPtrLFBHandler);
5204 if (VBOX_FAILURE(rc))
5205 {
5206 AssertReleaseMsgFailed(("PDMR3GetSymbolGC(, %s, \"vgaGCLFBAccessHandler\",) -> %Vrc\n", pDevIns->pDevReg->szGCMod, rc));
5207 return rc;
5208 }
5209
5210 /* the interfaces. */
5211 pData->Base.pfnQueryInterface = vgaPortQueryInterface;
5212
5213 pData->Port.pfnUpdateDisplay = vgaPortUpdateDisplay;
5214 pData->Port.pfnUpdateDisplayAll = vgaPortUpdateDisplayAll;
5215 pData->Port.pfnQueryColorDepth = vgaPortQueryColorDepth;
5216 pData->Port.pfnSetRefreshRate = vgaPortSetRefreshRate;
5217 pData->Port.pfnSnapshot = vgaPortSnapshot;
5218 pData->Port.pfnDisplayBlt = vgaPortDisplayBlt;
5219 pData->Port.pfnUpdateDisplayRect = vgaPortUpdateDisplayRect;
5220 pData->Port.pfnSetRenderVRAM = vgaPortSetRenderVRAM;
5221
5222
5223 /*
5224 * Allocate the VRAM and map the first 256KB of it into GC so we can speed up VGA support.
5225 */
5226 rc = PDMDevHlpMMIO2Register(pDevIns, 0 /* iRegion */, pData->vram_size, 0, (void **)&pData->vram_ptrHC, "VRam");
5227 AssertMsgRC(rc, ("PDMDevHlpMMIO2Register(%#x,) -> %Rrc\n", pData->vram_size, rc));
5228
5229 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 0 /* iRegion */, 0 /* off */, VGA_MAPPING_SIZE, "VGA VRam", &pData->vram_ptrGC);
5230 AssertMsgRC(rc, ("MMR3HyperMapGCPhys(%#x,) -> %Rrc\n", pData->vram_size, rc));
5231
5232 /*
5233 * Register I/O ports, ROM and save state.
5234 */
5235 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3c0, 16, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3c0");
5236 if (VBOX_FAILURE(rc))
5237 return rc;
5238 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3b4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3b4");
5239 if (VBOX_FAILURE(rc))
5240 return rc;
5241 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3ba, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3ba");
5242 if (VBOX_FAILURE(rc))
5243 return rc;
5244 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3d4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3d4");
5245 if (VBOX_FAILURE(rc))
5246 return rc;
5247 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3da, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3da");
5248 if (VBOX_FAILURE(rc))
5249 return rc;
5250
5251#ifdef CONFIG_BOCHS_VBE
5252 rc = PDMDevHlpIOPortRegister(pDevIns, 0x1ce, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, NULL, NULL, "VGA/VBE - Index");
5253 if (VBOX_FAILURE(rc))
5254 return rc;
5255 rc = PDMDevHlpIOPortRegister(pDevIns, 0x1cf, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, NULL, NULL, "VGA/VBE - Data");
5256 if (VBOX_FAILURE(rc))
5257 return rc;
5258#if 0
5259 /* This now causes conflicts with Win2k & XP; it is not aware this range is taken
5260 and tries to map other devices there */
5261 /* Old Bochs. */
5262 rc = PDMDevHlpIOPortRegister(pDevIns, 0xff80, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, "VGA/VBE - Index Old");
5263 if (VBOX_FAILURE(rc))
5264 return rc;
5265 rc = PDMDevHlpIOPortRegister(pDevIns, 0xff81, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, "VGA/VBE - Data Old");
5266 if (VBOX_FAILURE(rc))
5267 return rc;
5268#endif
5269#endif /* CONFIG_BOCHS_VBE */
5270
5271 /* guest context extension */
5272 if (pData->fGCEnabled)
5273 {
5274 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
5275 if (VBOX_FAILURE(rc))
5276 return rc;
5277 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
5278 if (VBOX_FAILURE(rc))
5279 return rc;
5280 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
5281 if (VBOX_FAILURE(rc))
5282 return rc;
5283 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
5284 if (VBOX_FAILURE(rc))
5285 return rc;
5286 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
5287 if (VBOX_FAILURE(rc))
5288 return rc;
5289#ifdef CONFIG_BOCHS_VBE
5290 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
5291 if (VBOX_FAILURE(rc))
5292 return rc;
5293 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
5294 if (VBOX_FAILURE(rc))
5295 return rc;
5296
5297#if 0
5298 /* This now causes conflicts with Win2k & XP; they are not aware this range is taken
5299 and try to map other devices there */
5300 /* Old Bochs. */
5301 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
5302 if (VBOX_FAILURE(rc))
5303 return rc;
5304 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
5305 if (VBOX_FAILURE(rc))
5306 return rc;
5307#endif
5308
5309#endif /* CONFIG_BOCHS_VBE */
5310 }
5311
5312 /* R0 context extension */
5313 if (pData->fR0Enabled)
5314 {
5315 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
5316 if (VBOX_FAILURE(rc))
5317 return rc;
5318 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
5319 if (VBOX_FAILURE(rc))
5320 return rc;
5321 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
5322 if (VBOX_FAILURE(rc))
5323 return rc;
5324 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
5325 if (VBOX_FAILURE(rc))
5326 return rc;
5327 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
5328 if (VBOX_FAILURE(rc))
5329 return rc;
5330#ifdef CONFIG_BOCHS_VBE
5331 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
5332 if (VBOX_FAILURE(rc))
5333 return rc;
5334 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
5335 if (VBOX_FAILURE(rc))
5336 return rc;
5337
5338#if 0
5339 /* This now causes conflicts with Win2k & XP; they are not aware this range is taken
5340 and try to map other devices there */
5341 /* Old Bochs. */
5342 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
5343 if (VBOX_FAILURE(rc))
5344 return rc;
5345 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
5346 if (VBOX_FAILURE(rc))
5347 return rc;
5348#endif
5349
5350#endif /* CONFIG_BOCHS_VBE */
5351 }
5352
5353 /* vga mmio */
5354 rc = PDMDevHlpMMIORegister(pDevIns, 0x000a0000, 0x00020000, 0, vgaMMIOWrite, vgaMMIORead, vgaMMIOFill, "VGA - VGA Video Buffer");
5355 if (VBOX_FAILURE(rc))
5356 return rc;
5357 if (pData->fGCEnabled)
5358 {
5359 rc = PDMDevHlpMMIORegisterGC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");
5360 if (VBOX_FAILURE(rc))
5361 return rc;
5362 }
5363 if (pData->fR0Enabled)
5364 {
5365 rc = PDMDevHlpMMIORegisterR0(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");
5366 if (VBOX_FAILURE(rc))
5367 return rc;
5368 }
5369
5370 /* vga bios */
5371 rc = PDMDevHlpIOPortRegister(pDevIns, VBE_PRINTF_PORT, 1, NULL, vgaIOPortWriteBIOS, vgaIOPortReadBIOS, NULL, NULL, "VGA BIOS debug/panic");
5372 if (VBOX_FAILURE(rc))
5373 return rc;
5374 AssertReleaseMsg(g_cbVgaBiosBinary <= _64K && g_cbVgaBiosBinary >= 32*_1K, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
5375 AssertReleaseMsg(RT_ALIGN_Z(g_cbVgaBiosBinary, PAGE_SIZE) == g_cbVgaBiosBinary, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
5376 rc = PDMDevHlpROMRegister(pDevIns, 0x000c0000, g_cbVgaBiosBinary, &g_abVgaBiosBinary[0],
5377 false /* fShadow */, "VGA BIOS");
5378 if (VBOX_FAILURE(rc))
5379 return rc;
5380
5381 /* save */
5382 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */, sizeof(*pData),
5383 NULL, vgaR3SaveExec, NULL,
5384 NULL, vgaR3LoadExec, NULL);
5385 if (VBOX_FAILURE(rc))
5386 return rc;
5387
5388 /* PCI */
5389 rc = PDMDevHlpPCIRegister(pDevIns, &pData->Dev);
5390 if (VBOX_FAILURE(rc))
5391 return rc;
5392 /*AssertMsg(pData->Dev.devfn == 16 || iInstance != 0, ("pData->Dev.devfn=%d\n", pData->Dev.devfn));*/
5393 if (pData->Dev.devfn != 16 && iInstance == 0)
5394 Log(("!!WARNING!!: pData->dev.devfn=%d (ignore if testcase or not started by Main)\n", pData->Dev.devfn));
5395
5396 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0 /* iRegion */, pData->vram_size, PCI_ADDRESS_SPACE_MEM_PREFETCH, vgaR3IORegionMap);
5397 if (VBOX_FAILURE(rc))
5398 return rc;
5399
5400 /*
5401 * Create the refresh timer.
5402 */
5403 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_REAL, vgaTimerRefresh, "VGA Refresh Timer", &pData->RefreshTimer);
5404 if (VBOX_FAILURE(rc))
5405 return rc;
5406
5407 /*
5408 * Attach to the display.
5409 */
5410 rc = vgaAttach(pDevIns, 0 /* display LUN # */);
5411 if (VBOX_FAILURE(rc))
5412 return rc;
5413
5414#ifdef VBE_NEW_DYN_LIST
5415 /*
5416 * Compute buffer size for the VBE BIOS Extra Data.
5417 */
5418 cb = sizeof(mode_info_list) + sizeof(ModeInfoListItem);
5419
5420 rc = CFGMR3QueryU32(pCfgHandle, "HeightReduction", &cyReduction);
5421 if (VBOX_SUCCESS(rc) && cyReduction)
5422 cb *= 2; /* Default mode list will be twice long */
5423 else
5424 cyReduction = 0;
5425
5426 rc = CFGMR3QueryU32(pCfgHandle, "CustomVideoModes", &cCustomModes);
5427 if (VBOX_SUCCESS(rc) && cCustomModes)
5428 cb += sizeof(ModeInfoListItem) * cCustomModes;
5429 else
5430 cCustomModes = 0;
5431
5432 /*
5433 * Allocate and initialize buffer for the VBE BIOS Extra Data.
5434 */
5435 pData->cbVBEExtraData = sizeof(VBEHEADER) + cb;
5436 pData->pu8VBEExtraData = (uint8_t *)PDMDevHlpMMHeapAllocZ(pDevIns, pData->cbVBEExtraData);
5437 if (!pData->pu8VBEExtraData)
5438 return VERR_NO_MEMORY;
5439
5440 pVBEDataHdr = (PVBEHEADER)pData->pu8VBEExtraData;
5441 pVBEDataHdr->u16Signature = VBEHEADER_MAGIC;
5442 pVBEDataHdr->cbData = cb;
5443
5444#ifndef VRAM_SIZE_FIX
5445 pCurMode = memcpy(pVBEDataHdr + 1, &mode_info_list, sizeof(mode_info_list));
5446 pCurMode = (ModeInfoListItem *)((uintptr_t)pCurMode + sizeof(mode_info_list));
5447#else /* VRAM_SIZE_FIX defined */
5448 pCurMode = (ModeInfoListItem *)(pVBEDataHdr + 1);
5449 for (i = 0; i < MODE_INFO_SIZE; i++)
5450 {
5451 uint32_t pixelWidth, reqSize;
5452 if (mode_info_list[i].info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
5453 pixelWidth = 2;
5454 else
5455 pixelWidth = (mode_info_list[i].info.BitsPerPixel +7) / 8;
5456 reqSize = mode_info_list[i].info.XResolution
5457 * mode_info_list[i].info.YResolution
5458 * pixelWidth;
5459 if (reqSize >= pData->vram_size)
5460 continue;
5461 *pCurMode = mode_info_list[i];
5462 pCurMode++;
5463 }
5464#endif /* VRAM_SIZE_FIX defined */
5465
5466 /*
5467 * Copy default modes with subtractred YResolution.
5468 */
5469 if (cyReduction)
5470 {
5471 ModeInfoListItem *pDefMode = mode_info_list;
5472 Log(("vgaR3Construct: cyReduction=%u\n", cyReduction));
5473#ifndef VRAM_SIZE_FIX
5474 for (i = 0; i < MODE_INFO_SIZE; i++, pCurMode++, pDefMode++)
5475 {
5476 *pCurMode = *pDefMode;
5477 pCurMode->mode += 0x30;
5478 pCurMode->info.YResolution -= cyReduction;
5479 }
5480#else /* VRAM_SIZE_FIX defined */
5481 for (i = 0; i < MODE_INFO_SIZE; i++, pDefMode++)
5482 {
5483 uint32_t pixelWidth, reqSize;
5484 if (pDefMode->info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
5485 pixelWidth = 2;
5486 else
5487 pixelWidth = (pDefMode->info.BitsPerPixel + 7) / 8;
5488 reqSize = pDefMode->info.XResolution * pDefMode->info.YResolution * pixelWidth;
5489 if (reqSize >= pData->vram_size)
5490 continue;
5491 *pCurMode = *pDefMode;
5492 pCurMode->mode += 0x30;
5493 pCurMode->info.YResolution -= cyReduction;
5494 pCurMode++;
5495 }
5496#endif /* VRAM_SIZE_FIX defined */
5497 }
5498
5499
5500 /*
5501 * Add custom modes.
5502 */
5503 if (cCustomModes)
5504 {
5505 uint16_t u16CurMode = 0x160;
5506 for (i = 1; i <= cCustomModes; i++)
5507 {
5508 char szExtraDataKey[sizeof("CustomVideoModeXX")];
5509 char *pszExtraData = NULL;
5510
5511 /* query and decode the custom mode string. */
5512 RTStrPrintf(szExtraDataKey, sizeof(szExtraDataKey), "CustomVideoMode%d", i);
5513 rc = CFGMR3QueryStringAlloc(pCfgHandle, szExtraDataKey, &pszExtraData);
5514 if (VBOX_SUCCESS(rc))
5515 {
5516 ModeInfoListItem *pDefMode = mode_info_list;
5517 unsigned int cx, cy, cBits, cParams, j;
5518 uint16_t u16DefMode;
5519
5520 cParams = sscanf(pszExtraData, "%ux%ux%u", &cx, &cy, &cBits);
5521 if ( cParams != 3
5522 || (cBits != 16 && cBits != 24 && cBits != 32))
5523 {
5524 AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cBits=%d\n", pszExtraData, szExtraDataKey, cBits));
5525 return VERR_VGA_INVALID_CUSTOM_MODE;
5526 }
5527#ifdef VRAM_SIZE_FIX
5528 if (cx * cy * cBits / 8 >= pData->vram_size)
5529 {
5530 AssertMsgFailed(("Configuration error: custom video mode %dx%dx%dbits is too large for the virtual video memory of %dMb. Please increase the video memory size.\n",
5531 cx, cy, cBits, pData->vram_size / _1M));
5532 return VERR_VGA_INVALID_CUSTOM_MODE;
5533 }
5534#endif /* VRAM_SIZE_FIX defined */
5535 MMR3HeapFree(pszExtraData);
5536
5537 /* Use defaults from max@bpp mode. */
5538 switch (cBits)
5539 {
5540 case 16:
5541 u16DefMode = VBE_VESA_MODE_1024X768X565;
5542 break;
5543
5544 case 24:
5545 u16DefMode = VBE_VESA_MODE_1024X768X888;
5546 break;
5547
5548 case 32:
5549 u16DefMode = VBE_OWN_MODE_1024X768X8888;
5550 break;
5551
5552 default: /* gcc, shut up! */
5553 AssertMsgFailed(("gone postal!\n"));
5554 continue;
5555 }
5556
5557 /* mode_info_list is not terminated */
5558 for (j = 0; j < MODE_INFO_SIZE && pDefMode->mode != u16DefMode; j++)
5559 pDefMode++;
5560 Assert(j < MODE_INFO_SIZE);
5561
5562 *pCurMode = *pDefMode;
5563 pCurMode->mode = u16CurMode++;
5564
5565 /* adjust defaults */
5566 pCurMode->info.XResolution = cx;
5567 pCurMode->info.YResolution = cy;
5568
5569 switch (cBits)
5570 {
5571 case 16:
5572 pCurMode->info.BytesPerScanLine = cx * 2;
5573 pCurMode->info.LinBytesPerScanLine = cx * 2;
5574 break;
5575
5576 case 24:
5577 pCurMode->info.BytesPerScanLine = cx * 3;
5578 pCurMode->info.LinBytesPerScanLine = cx * 3;
5579 break;
5580
5581 case 32:
5582 pCurMode->info.BytesPerScanLine = cx * 4;
5583 pCurMode->info.LinBytesPerScanLine = cx * 4;
5584 break;
5585 }
5586
5587 /* commit it */
5588 pCurMode++;
5589 }
5590 else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
5591 {
5592 AssertMsgFailed(("CFGMR3QueryStringAlloc(,'%s',) -> %Vrc\n", szExtraDataKey, rc));
5593 return rc;
5594 }
5595 } /* foreach custom mode key */
5596 }
5597
5598 /*
5599 * Add the "End of list" mode.
5600 */
5601 memset(pCurMode, 0, sizeof(*pCurMode));
5602 pCurMode->mode = VBE_VESA_MODE_END_OF_LIST;
5603
5604 /*
5605 * Register I/O Port for the VBE BIOS Extra Data.
5606 */
5607 rc = PDMDevHlpIOPortRegister(pDevIns, VBE_EXTRA_PORT, 1, NULL, vbeIOPortWriteVBEExtra, vbeIOPortReadVBEExtra, NULL, NULL, "VBE BIOS Extra Data");
5608 if (VBOX_FAILURE(rc))
5609 return rc;
5610#endif
5611
5612 /*
5613 * Register I/O Port for the BIOS Logo.
5614 */
5615 rc = PDMDevHlpIOPortRegister(pDevIns, LOGO_IO_PORT, 1, NULL, vbeIOPortWriteCMDLogo, vbeIOPortReadCMDLogo, NULL, NULL, "BIOS Logo");
5616 if (VBOX_FAILURE(rc))
5617 return rc;
5618
5619 /*
5620 * Construct the logo header.
5621 */
5622 LOGOHDR LogoHdr = { LOGO_HDR_MAGIC, 0, 0, 0, 0, 0, 0 };
5623
5624 rc = CFGMR3QueryU8(pCfgHandle, "FadeIn", &LogoHdr.fu8FadeIn);
5625 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5626 LogoHdr.fu8FadeIn = 1;
5627 else if (VBOX_FAILURE(rc))
5628 return PDMDEV_SET_ERROR(pDevIns, rc,
5629 N_("Configuration error: Querying \"FadeIn\" as integer failed"));
5630
5631 rc = CFGMR3QueryU8(pCfgHandle, "FadeOut", &LogoHdr.fu8FadeOut);
5632 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5633 LogoHdr.fu8FadeOut = 1;
5634 else if (VBOX_FAILURE(rc))
5635 return PDMDEV_SET_ERROR(pDevIns, rc,
5636 N_("Configuration error: Querying \"FadeOut\" as integer failed"));
5637
5638 rc = CFGMR3QueryU16(pCfgHandle, "LogoTime", &LogoHdr.u16LogoMillies);
5639 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5640 LogoHdr.u16LogoMillies = 0;
5641 else if (VBOX_FAILURE(rc))
5642 return PDMDEV_SET_ERROR(pDevIns, rc,
5643 N_("Configuration error: Querying \"LogoTime\" as integer failed"));
5644
5645 /* Delay the logo a little bit */
5646 if (LogoHdr.fu8FadeIn && LogoHdr.fu8FadeOut && !LogoHdr.u16LogoMillies)
5647 LogoHdr.u16LogoMillies = RT_MAX(LogoHdr.u16LogoMillies, LOGO_DELAY_TIME);
5648
5649 rc = CFGMR3QueryU8(pCfgHandle, "ShowBootMenu", &LogoHdr.fu8ShowBootMenu);
5650 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5651 LogoHdr.fu8ShowBootMenu = 0;
5652 else if (VBOX_FAILURE(rc))
5653 return PDMDEV_SET_ERROR(pDevIns, rc,
5654 N_("Configuration error: Querying \"ShowBootMenu\" as integer failed"));
5655
5656 /*
5657 * Get the Logo file name.
5658 */
5659 rc = CFGMR3QueryStringAlloc(pCfgHandle, "LogoFile", &pData->pszLogoFile);
5660 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5661 pData->pszLogoFile = NULL;
5662 else if (VBOX_FAILURE(rc))
5663 return PDMDEV_SET_ERROR(pDevIns, rc,
5664 N_("Configuration error: Querying \"LogoFile\" as a string failed"));
5665 else if (!*pData->pszLogoFile)
5666 {
5667 MMR3HeapFree(pData->pszLogoFile);
5668 pData->pszLogoFile = NULL;
5669 }
5670
5671 /*
5672 * Determine the logo size, open any specified logo file in the process.
5673 */
5674 LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5675 RTFILE FileLogo = NIL_RTFILE;
5676 if (pData->pszLogoFile)
5677 {
5678 rc = RTFileOpen(&FileLogo, pData->pszLogoFile,
5679 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
5680 if (VBOX_SUCCESS(rc))
5681 {
5682 uint64_t cbFile;
5683 rc = RTFileGetSize(FileLogo, &cbFile);
5684 if (VBOX_SUCCESS(rc))
5685 {
5686 if (cbFile > 0 && cbFile < 32*_1M)
5687 LogoHdr.cbLogo = (uint32_t)cbFile;
5688 else
5689 rc = VERR_TOO_MUCH_DATA;
5690 }
5691 }
5692 if (VBOX_FAILURE(rc))
5693 {
5694 /*
5695 * Ignore failure and fall back to the default logo.
5696 */
5697 LogRel(("vgaR3Construct: Failed to open logo file '%s', rc=%Vrc!\n", pData->pszLogoFile, rc));
5698 if (FileLogo != NIL_RTFILE)
5699 RTFileClose(FileLogo);
5700 FileLogo = NIL_RTFILE;
5701 MMR3HeapFree(pData->pszLogoFile);
5702 pData->pszLogoFile = NULL;
5703 }
5704 }
5705
5706 /*
5707 * Allocate buffer for the logo data.
5708 * RT_MAX() is applied to let us fall back to default logo on read failure.
5709 */
5710 pData->cbLogo = sizeof(LogoHdr) + LogoHdr.cbLogo;
5711 pData->pu8Logo = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, RT_MAX(pData->cbLogo, g_cbVgaDefBiosLogo + sizeof(LogoHdr)));
5712 if (pData->pu8Logo)
5713 {
5714 /*
5715 * Write the logo header.
5716 */
5717 PLOGOHDR pLogoHdr = (PLOGOHDR)pData->pu8Logo;
5718 *pLogoHdr = LogoHdr;
5719
5720 /*
5721 * Write the logo bitmap.
5722 */
5723 if (pData->pszLogoFile)
5724 {
5725 rc = RTFileRead(FileLogo, pLogoHdr + 1, LogoHdr.cbLogo, NULL);
5726 if (VBOX_FAILURE(rc))
5727 {
5728 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Vrc\n", LogoHdr.cbLogo, rc));
5729 pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5730 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5731 }
5732 }
5733 else
5734 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5735
5736 rc = vbeParseBitmap(pData);
5737 if (VBOX_FAILURE(rc))
5738 {
5739 AssertMsgFailed(("vbeParseBitmap() -> %Vrc\n", rc));
5740 pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5741 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5742 }
5743
5744 rc = vbeParseBitmap(pData);
5745 if (VBOX_FAILURE(rc))
5746 AssertReleaseMsgFailed(("Internal bitmap failed! vbeParseBitmap() -> %Vrc\n", rc));
5747
5748 rc = VINF_SUCCESS;
5749 }
5750 else
5751 rc = VERR_NO_MEMORY;
5752
5753 /*
5754 * Cleanup.
5755 */
5756 if (FileLogo != NIL_RTFILE)
5757 RTFileClose(FileLogo);
5758
5759 /*
5760 * Statistics.
5761 */
5762 STAM_REG(pVM, &pData->StatGCMemoryRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
5763 STAM_REG(pVM, &pData->StatGCMemoryWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
5764 STAM_REG(pVM, &pData->StatGCIOPortRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortRead() body.");
5765 STAM_REG(pVM, &pData->StatGCIOPortWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortWrite() body.");
5766
5767 return rc;
5768}
5769
5770
5771/**
5772 * Destruct a device instance.
5773 *
5774 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5775 * resources can be freed correctly.
5776 *
5777 * @param pDevIns The device instance data.
5778 */
5779static DECLCALLBACK(int) vgaR3Destruct(PPDMDEVINS pDevIns)
5780{
5781#ifdef VBE_NEW_DYN_LIST
5782 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5783 LogFlow(("vgaR3Destruct:\n"));
5784
5785 /*
5786 * Free MM heap pointers.
5787 */
5788 if (pData->pu8VBEExtraData)
5789 {
5790 MMR3HeapFree(pData->pu8VBEExtraData);
5791 pData->pu8VBEExtraData = NULL;
5792 }
5793#endif
5794
5795 return VINF_SUCCESS;
5796}
5797
5798
5799/**
5800 * The device registration structure.
5801 */
5802const PDMDEVREG g_DeviceVga =
5803{
5804 /* u32Version */
5805 PDM_DEVREG_VERSION,
5806 /* szDeviceName */
5807 "vga",
5808 /* szGCMod */
5809 "VBoxDDGC.gc",
5810 /* szR0Mod */
5811 "VBoxDDR0.r0",
5812 /* pszDescription */
5813 "VGA Adaptor with VESA extensions.",
5814 /* fFlags */
5815 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
5816 /* fClass */
5817 PDM_DEVREG_CLASS_GRAPHICS,
5818 /* cMaxInstances */
5819 1,
5820 /* cbInstance */
5821 sizeof(VGASTATE),
5822 /* pfnConstruct */
5823 vgaR3Construct,
5824 /* pfnDestruct */
5825 vgaR3Destruct,
5826 /* pfnRelocate */
5827 vgaR3Relocate,
5828 /* pfnIOCtl */
5829 NULL,
5830 /* pfnPowerOn */
5831 NULL,
5832 /* pfnReset */
5833 vgaR3Reset,
5834 /* pfnSuspend */
5835 NULL,
5836 /* pfnResume */
5837 NULL,
5838 /* pfnAttach */
5839 vgaAttach,
5840 /* pfnDetach */
5841 vgaDetach,
5842 /* pfnQueryInterface */
5843 NULL,
5844 /* pfnInitComplete */
5845 NULL
5846};
5847
5848#endif /* !IN_RING3 */
5849#endif /* VBOX */
5850#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5851
5852/*
5853 * Local Variables:
5854 * nuke-trailing-whitespace-p:nil
5855 * End:
5856 */
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