DevVGA.cpp@ 2993

Last change on this file since 2993 was 2981, checked in by vboxsync, 18 years ago
InnoTek -> innotek: all the headers and comments.
Property svn:eol-style set to `native`
File size: 158.0 KB

Line
1	#ifdef VBOX
2	/** @file
3	*
4	* VBox VGA/VESA device
5	*/
6
7	/*
8	* Copyright (C) 2006-2007 innotek GmbH
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License as published by the Free Software Foundation,
14	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15	* distribution. VirtualBox OSE is distributed in the hope that it will
16	* be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* If you received this file as part of a commercial VirtualBox
19	* distribution, then only the terms of your commercial VirtualBox
20	* license agreement apply instead of the previous paragraph.
21	*
22	* --------------------------------------------------------------------
23	*
24	* This code is based on:
25	*
26	* QEMU VGA Emulator.
27	*
28	* Copyright (c) 2003 Fabrice Bellard
29	*
30	* Permission is hereby granted, free of charge, to any person obtaining a copy
31	* of this software and associated documentation files (the "Software"), to deal
32	* in the Software without restriction, including without limitation the rights
33	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
34	* copies of the Software, and to permit persons to whom the Software is
35	* furnished to do so, subject to the following conditions:
36	*
37	* The above copyright notice and this permission notice shall be included in
38	* all copies or substantial portions of the Software.
39	*
40	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
41	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
42	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
44	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
45	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
46	* THE SOFTWARE.
47	*/
48
49	/*******************************************************************************
50	* Defined Constants And Macros *
51	*******************************************************************************/
52	/** The default amount of VRAM. */
53	#define VGA_VRAM_DEFAULT (_4M)
54	/** The maximum amount of VRAM. */
55	#define VGA_VRAM_MAX (128 * _1M)
56	/** The minimum amount of VRAM. */
57	#define VGA_VRAM_MIN (_1M)
58	/** The maximum number of monitors. */
59	#define VGA_MONITORS_MAX 64
60
61	/** The size of the VGA GC mapping.
62	* This is supposed to be all the VGA memory accessible to the guest.
63	* The initial value was 256KB but NTAllInOne.iso appears to access more
64	* thus the limit was upped to 512KB.
65	*
66	* @todo Someone with some VGA knowhow should make a better guess at this value.
67	*/
68	#define VGA_MAPPING_SIZE _512K
69
70	/** Converts a vga adaptor state pointer to a device instance pointer. */
71	#define VGASTATE2DEVINS(pVgaState) ((pVgaState)->CTXSUFF(pDevIns))
72
73	/** Use VBE bytewise I/O */
74	#define VBE_BYTEWISE_IO
75
76	/** Use VBE new dynamic mode list.
77	* If this is not defined, no checks are carried out to see if the modes all
78	* fit into the framebuffer! See the VRAM_SIZE_FIX define. */
79	#define VBE_NEW_DYN_LIST
80
81	/** Check that the video modes fit into virtual video memory.
82	* Only works when VBE_NEW_DYN_LIST is defined! */
83	#define VRAM_SIZE_FIX
84
85	/** Some fixes to ensure that logical scan-line lengths are not overwritten. */
86	#define KEEP_SCAN_LINE_LENGTH
87
88
89	/*******************************************************************************
90	* Header Files *
91	*******************************************************************************/
92	#define LOG_GROUP LOG_GROUP_DEV_VGA
93	#include <VBox/pdm.h>
94	#include <VBox/stam.h>
95	#include <VBox/pgm.h>
96	#include <VBox/mm.h>
97	#include <VBox/err.h>
98
99	#include <VBox/log.h>
100	#include <iprt/assert.h>
101	#include <iprt/asm.h>
102	#include <iprt/string.h>
103
104	#include <VBox/VBoxGuest.h>
105
106	#if defined(VBE_NEW_DYN_LIST) && defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
107	# include "DevVGAModes.h"
108	# include <stdio.h> /* sscan */
109	#endif
110
111	#include "vl_vbox.h"
112	#include "DevVGA.h"
113	#include "Builtins.h"
114	#include "Builtins2.h"
115
116
117	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
118	/*******************************************************************************
119	* Internal Functions *
120	*******************************************************************************/
121	__BEGIN_DECLS
122
123	PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
124	PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
125	PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
126	PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
127	PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
128	PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
129	PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems);
130	PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
131	PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb);
132	#ifdef IN_GC
133	PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
134	#endif
135	#ifdef IN_RING0
136	PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
137	#endif
138	#ifdef IN_RING3
139	# ifdef VBE_NEW_DYN_LIST
140	PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb);
141	PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
142	# endif
143	#endif /* IN_RING3 */
144
145
146	__END_DECLS
147
148
149	/**
150	* Set a VRAM page dirty.
151	*
152	* @param pData VGA instance data.
153	* @param offVRAM The VRAM offset of the page to set.
154	*/
155	DECLINLINE(void) vga_set_dirty(VGAState *pData, RTGCPHYS offVRAM)
156	{
157	AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
158	ASMBitSet(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
159	pData->fHaveDirtyBits = true;
160	}
161
162	/**
163	* Tests if a VRAM page is dirty.
164	*
165	* @returns true if dirty.
166	* @returns false if clean.
167	* @param pData VGA instance data.
168	* @param offVRAM The VRAM offset of the page to check.
169	*/
170	DECLINLINE(bool) vga_is_dirty(VGAState *pData, RTGCPHYS offVRAM)
171	{
172	AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
173	return ASMBitTest(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
174	}
175
176	/**
177	* Reset dirty flags in a give range.
178	*
179	* @param pData VGA instance data.
180	* @param offVRAMStart Offset into the VRAM buffer of the first page.
181	* @param offVRAMEnd Offset into the VRAM buffer of the last page - exclusive.
182	*/
183	DECLINLINE(void) vga_reset_dirty(VGAState *pData, RTGCPHYS offVRAMStart, RTGCPHYS offVRAMEnd)
184	{
185	Assert(offVRAMStart < pData->vram_size);
186	Assert(offVRAMEnd <= pData->vram_size);
187	Assert(offVRAMStart < offVRAMEnd);
188	ASMBitClearRange(&pData->au32DirtyBitmap[0], offVRAMStart >> PAGE_SHIFT, offVRAMEnd >> PAGE_SHIFT);
189	}
190
191	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
192	#endif /* VBOX */
193	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
194
195	#ifndef VBOX
196	#include "vl.h"
197	#include "vga_int.h"
198	#endif /* !VBOX */
199
200	#ifdef LOG_ENABLED
201	//#define DEBUG_VGA
202	//#define DEBUG_VGA_MEM
203	//#define DEBUG_VGA_REG
204
205	#define DEBUG_BOCHS_VBE
206
207	#endif
208
209	/* force some bits to zero */
210	#ifdef VBOX
211	static
212	#endif /* VBOX */
213	const uint8_t sr_mask[8] = {
214	(uint8_t)~0xfc,
215	(uint8_t)~0xc2,
216	(uint8_t)~0xf0,
217	(uint8_t)~0xc0,
218	(uint8_t)~0xf1,
219	(uint8_t)~0xff,
220	(uint8_t)~0xff,
221	(uint8_t)~0x00,
222	};
223
224	#ifdef VBOX
225	static
226	#endif /* VBOX */
227	const uint8_t gr_mask[16] = {
228	(uint8_t)~0xf0, /* 0x00 */
229	(uint8_t)~0xf0, /* 0x01 */
230	(uint8_t)~0xf0, /* 0x02 */
231	(uint8_t)~0xe0, /* 0x03 */
232	(uint8_t)~0xfc, /* 0x04 */
233	(uint8_t)~0x84, /* 0x05 */
234	(uint8_t)~0xf0, /* 0x06 */
235	(uint8_t)~0xf0, /* 0x07 */
236	(uint8_t)~0x00, /* 0x08 */
237	(uint8_t)~0xff, /* 0x09 */
238	(uint8_t)~0xff, /* 0x0a */
239	(uint8_t)~0xff, /* 0x0b */
240	(uint8_t)~0xff, /* 0x0c */
241	(uint8_t)~0xff, /* 0x0d */
242	(uint8_t)~0xff, /* 0x0e */
243	(uint8_t)~0xff, /* 0x0f */
244	};
245
246	#define cbswap_32(__x) \
247	((uint32_t)( \
248	(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) \| \
249	(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) \| \
250	(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) \| \
251	(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
252
253	#ifdef WORDS_BIGENDIAN
254	#define PAT(x) cbswap_32(x)
255	#else
256	#define PAT(x) (x)
257	#endif
258
259	#ifdef WORDS_BIGENDIAN
260	#define BIG 1
261	#else
262	#define BIG 0
263	#endif
264
265	#ifdef WORDS_BIGENDIAN
266	#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
267	#else
268	#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
269	#endif
270
271	static const uint32_t mask16[16] = {
272	PAT(0x00000000),
273	PAT(0x000000ff),
274	PAT(0x0000ff00),
275	PAT(0x0000ffff),
276	PAT(0x00ff0000),
277	PAT(0x00ff00ff),
278	PAT(0x00ffff00),
279	PAT(0x00ffffff),
280	PAT(0xff000000),
281	PAT(0xff0000ff),
282	PAT(0xff00ff00),
283	PAT(0xff00ffff),
284	PAT(0xffff0000),
285	PAT(0xffff00ff),
286	PAT(0xffffff00),
287	PAT(0xffffffff),
288	};
289
290	#undef PAT
291
292	#ifdef WORDS_BIGENDIAN
293	#define PAT(x) (x)
294	#else
295	#define PAT(x) cbswap_32(x)
296	#endif
297
298	static const uint32_t dmask16[16] = {
299	PAT(0x00000000),
300	PAT(0x000000ff),
301	PAT(0x0000ff00),
302	PAT(0x0000ffff),
303	PAT(0x00ff0000),
304	PAT(0x00ff00ff),
305	PAT(0x00ffff00),
306	PAT(0x00ffffff),
307	PAT(0xff000000),
308	PAT(0xff0000ff),
309	PAT(0xff00ff00),
310	PAT(0xff00ffff),
311	PAT(0xffff0000),
312	PAT(0xffff00ff),
313	PAT(0xffffff00),
314	PAT(0xffffffff),
315	};
316
317	static const uint32_t dmask4[4] = {
318	PAT(0x00000000),
319	PAT(0x0000ffff),
320	PAT(0xffff0000),
321	PAT(0xffffffff),
322	};
323
324	#if defined(VBOX) && defined(IN_RING3)
325	static uint32_t expand4[256];
326	static uint16_t expand2[256];
327	static uint8_t expand4to8[16];
328	#endif /* VBOX && IN_RING3 */
329
330	#ifndef VBOX
331	VGAState *vga_state;
332	int vga_io_memory;
333	#endif /* !VBOX */
334
335	static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
336	{
337	VGAState s = (VGAState)opaque;
338	int val, index;
339
340	/* check port range access depending on color/monochrome mode */
341	if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) \|\|
342	(addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
343	val = 0xff;
344	} else {
345	switch(addr) {
346	case 0x3c0:
347	if (s->ar_flip_flop == 0) {
348	val = s->ar_index;
349	} else {
350	val = 0;
351	}
352	break;
353	case 0x3c1:
354	index = s->ar_index & 0x1f;
355	if (index < 21)
356	val = s->ar[index];
357	else
358	val = 0;
359	break;
360	case 0x3c2:
361	val = s->st00;
362	break;
363	case 0x3c4:
364	val = s->sr_index;
365	break;
366	case 0x3c5:
367	val = s->sr[s->sr_index];
368	#ifdef DEBUG_VGA_REG
369	Log(("vga: read SR%x = 0x%02x\n", s->sr_index, val));
370	#endif
371	break;
372	case 0x3c7:
373	val = s->dac_state;
374	break;
375	case 0x3c8:
376	val = s->dac_write_index;
377	break;
378	case 0x3c9:
379	val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
380	if (++s->dac_sub_index == 3) {
381	s->dac_sub_index = 0;
382	s->dac_read_index++;
383	}
384	break;
385	case 0x3ca:
386	val = s->fcr;
387	break;
388	case 0x3cc:
389	val = s->msr;
390	break;
391	case 0x3ce:
392	val = s->gr_index;
393	break;
394	case 0x3cf:
395	val = s->gr[s->gr_index];
396	#ifdef DEBUG_VGA_REG
397	Log(("vga: read GR%x = 0x%02x\n", s->gr_index, val));
398	#endif
399	break;
400	case 0x3b4:
401	case 0x3d4:
402	val = s->cr_index;
403	break;
404	case 0x3b5:
405	case 0x3d5:
406	val = s->cr[s->cr_index];
407	#ifdef DEBUG_VGA_REG
408	Log(("vga: read CR%x = 0x%02x\n", s->cr_index, val));
409	#endif
410	break;
411	case 0x3ba:
412	case 0x3da:
413	/* just toggle to fool polling */
414	s->st01 ^= ST01_V_RETRACE \| ST01_DISP_ENABLE;
415	val = s->st01;
416	s->ar_flip_flop = 0;
417	break;
418	default:
419	val = 0x00;
420	break;
421	}
422	}
423	#if defined(DEBUG_VGA)
424	Log(("VGA: read addr=0x%04x data=0x%02x\n", addr, val));
425	#endif
426	return val;
427	}
428
429	static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
430	{
431	VGAState s = (VGAState)opaque;
432	int index;
433
434	/* check port range access depending on color/monochrome mode */
435	if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) \|\|
436	(addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
437	return;
438
439	#ifdef DEBUG_VGA
440	Log(("VGA: write addr=0x%04x data=0x%02x\n", addr, val));
441	#endif
442
443	switch(addr) {
444	case 0x3c0:
445	if (s->ar_flip_flop == 0) {
446	val &= 0x3f;
447	s->ar_index = val;
448	} else {
449	index = s->ar_index & 0x1f;
450	switch(index) {
451	#ifndef VBOX
452	case 0x00 ... 0x0f:
453	#else /* VBOX */
454	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
455	case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
456	#endif /* VBOX */
457	s->ar[index] = val & 0x3f;
458	break;
459	case 0x10:
460	s->ar[index] = val & ~0x10;
461	break;
462	case 0x11:
463	s->ar[index] = val;
464	break;
465	case 0x12:
466	s->ar[index] = val & ~0xc0;
467	break;
468	case 0x13:
469	s->ar[index] = val & ~0xf0;
470	break;
471	case 0x14:
472	s->ar[index] = val & ~0xf0;
473	break;
474	default:
475	break;
476	}
477	}
478	s->ar_flip_flop ^= 1;
479	break;
480	case 0x3c2:
481	s->msr = val & ~0x10;
482	break;
483	case 0x3c4:
484	s->sr_index = val & 7;
485	break;
486	case 0x3c5:
487	#ifdef DEBUG_VGA_REG
488	Log(("vga: write SR%x = 0x%02x\n", s->sr_index, val));
489	#endif
490	s->sr[s->sr_index] = val & sr_mask[s->sr_index];
491	break;
492	case 0x3c7:
493	s->dac_read_index = val;
494	s->dac_sub_index = 0;
495	s->dac_state = 3;
496	break;
497	case 0x3c8:
498	s->dac_write_index = val;
499	s->dac_sub_index = 0;
500	s->dac_state = 0;
501	break;
502	case 0x3c9:
503	s->dac_cache[s->dac_sub_index] = val;
504	if (++s->dac_sub_index == 3) {
505	memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
506	s->dac_sub_index = 0;
507	s->dac_write_index++;
508	}
509	break;
510	case 0x3ce:
511	s->gr_index = val & 0x0f;
512	break;
513	case 0x3cf:
514	#ifdef DEBUG_VGA_REG
515	Log(("vga: write GR%x = 0x%02x\n", s->gr_index, val));
516	#endif
517	s->gr[s->gr_index] = val & gr_mask[s->gr_index];
518	break;
519	case 0x3b4:
520	case 0x3d4:
521	s->cr_index = val;
522	break;
523	case 0x3b5:
524	case 0x3d5:
525	#ifdef DEBUG_VGA_REG
526	Log(("vga: write CR%x = 0x%02x\n", s->cr_index, val));
527	#endif
528	/* handle CR0-7 protection */
529	if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
530	/* can always write bit 4 of CR7 */
531	if (s->cr_index == 7)
532	s->cr[7] = (s->cr[7] & ~0x10) \| (val & 0x10);
533	return;
534	}
535	switch(s->cr_index) {
536	case 0x01: /* horizontal display end */
537	case 0x07:
538	case 0x09:
539	case 0x0c:
540	case 0x0d:
541	case 0x12: /* veritcal display end */
542	s->cr[s->cr_index] = val;
543	break;
544
545	default:
546	s->cr[s->cr_index] = val;
547	break;
548	}
549	break;
550	case 0x3ba:
551	case 0x3da:
552	s->fcr = val & 0x10;
553	break;
554	}
555	}
556
557	#ifdef CONFIG_BOCHS_VBE
558	static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
559	{
560	VGAState s = (VGAState)opaque;
561	uint32_t val;
562	val = s->vbe_index;
563	return val;
564	}
565
566	static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
567	{
568	VGAState s = (VGAState)opaque;
569	uint32_t val;
570
571	if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
572	if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
573	switch(s->vbe_index) {
574	/* XXX: do not hardcode ? */
575	case VBE_DISPI_INDEX_XRES:
576	val = VBE_DISPI_MAX_XRES;
577	break;
578	case VBE_DISPI_INDEX_YRES:
579	val = VBE_DISPI_MAX_YRES;
580	break;
581	case VBE_DISPI_INDEX_BPP:
582	val = VBE_DISPI_MAX_BPP;
583	break;
584	default:
585	val = s->vbe_regs[s->vbe_index];
586	break;
587	}
588	} else if (s->vbe_index == VBE_DISPI_INDEX_CMONITORS) {
589	val = s->monitor_count;
590	} else {
591	val = s->vbe_regs[s->vbe_index];
592	}
593	} else {
594	val = 0;
595	}
596	#ifdef DEBUG_BOCHS_VBE
597	Log(("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val));
598	#endif
599	return val;
600	}
601
602	static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
603	{
604	VGAState s = (VGAState)opaque;
605	s->vbe_index = val;
606	}
607
608	static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
609	{
610	VGAState s = (VGAState)opaque;
611
612	if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
613	#ifdef DEBUG_BOCHS_VBE
614	Log(("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val));
615	#endif
616	switch(s->vbe_index) {
617	case VBE_DISPI_INDEX_ID:
618	if (val == VBE_DISPI_ID0 \|\|
619	val == VBE_DISPI_ID1 \|\|
620	val == VBE_DISPI_ID2) {
621	s->vbe_regs[s->vbe_index] = val;
622	}
623	break;
624	case VBE_DISPI_INDEX_XRES:
625	if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
626	s->vbe_regs[s->vbe_index] = val;
627	#ifdef KEEP_SCAN_LINE_LENGTH
628	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
629	s->vbe_line_offset = val >> 1;
630	else
631	s->vbe_line_offset = val * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
632	/* XXX: support weird bochs semantics ? */
633	s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
634	s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
635	s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
636	s->vbe_start_addr = 0;
637	#endif /* KEEP_SCAN_LINE_LENGTH defined */
638	}
639	break;
640	case VBE_DISPI_INDEX_YRES:
641	if (val <= VBE_DISPI_MAX_YRES) {
642	s->vbe_regs[s->vbe_index] = val;
643	#ifdef KEEP_SCAN_LINE_LENGTH
644	s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = val;
645	s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
646	s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
647	s->vbe_start_addr = 0;
648	#endif /* KEEP_SCAN_LINE_LENGTH defined */
649	}
650	break;
651	case VBE_DISPI_INDEX_BPP:
652	if (val == 0)
653	val = 8;
654	if (val == 4 \|\| val == 8 \|\| val == 15 \|\|
655	val == 16 \|\| val == 24 \|\| val == 32) {
656	s->vbe_regs[s->vbe_index] = val;
657	#ifdef KEEP_SCAN_LINE_LENGTH
658	if (val == 4)
659	s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
660	else
661	s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((val + 7) >> 3);
662	/* XXX: support weird bochs semantics ? */
663	s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
664	s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
665	s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
666	s->vbe_start_addr = 0;
667	#endif /* KEEP_SCAN_LINE_LENGTH defined */
668	}
669	break;
670	case VBE_DISPI_INDEX_BANK:
671	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
672	val &= (s->vbe_bank_mask >> 2);
673	} else {
674	val &= s->vbe_bank_mask;
675	}
676	val &= s->vbe_bank_mask;
677	s->vbe_regs[s->vbe_index] = val;
678	s->bank_offset = (val << 16);
679	break;
680	case VBE_DISPI_INDEX_ENABLE:
681	if (val & VBE_DISPI_ENABLED) {
682	int h, shift_control;
683	#ifdef VBOX
684	/* Check the values before we screw up with a resolution which is too big or small. */
685	size_t cb = s->vbe_regs[VBE_DISPI_INDEX_XRES];
686	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
687	cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
688	else
689	cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
690	cb *= s->vbe_regs[VBE_DISPI_INDEX_YRES];
691	#ifndef KEEP_SCAN_LINE_LENGTH
692	if ( !s->vbe_regs[VBE_DISPI_INDEX_XRES]
693	\|\| !s->vbe_regs[VBE_DISPI_INDEX_YRES]
694	\|\| cb > s->vram_size)
695	{
696	AssertMsgFailed(("XRES=%d YRES=%d cb=%d vram_size=%d\n",
697	s->vbe_regs[VBE_DISPI_INDEX_XRES], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
698	return;
699	}
700	#else /* KEEP_SCAN_LINE_LENGTH defined */
701	if ( !s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH]
702	\|\| !s->vbe_regs[VBE_DISPI_INDEX_YRES]
703	\|\| cb > s->vram_size)
704	{
705	AssertMsgFailed(("VIRT WIDTH=%d YRES=%d cb=%d vram_size=%d\n",
706	s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
707	return;
708	}
709	#endif /* KEEP_SCAN_LINE_LENGTH defined */
710	#endif /* VBOX */
711
712	#ifndef KEEP_SCAN_LINE_LENGTH
713	s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
714	s->vbe_regs[VBE_DISPI_INDEX_XRES];
715	s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
716	s->vbe_regs[VBE_DISPI_INDEX_YRES];
717	s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
718	s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
719
720	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
721	s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
722	else
723	s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
724	((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
725	s->vbe_start_addr = 0;
726	#endif /* KEEP_SCAN_LINE_LENGTH not defined */
727
728	/* clear the screen (should be done in BIOS) */
729	if (!(val & VBE_DISPI_NOCLEARMEM)) {
730	#ifndef VBOX
731	memset(s->vram_ptr, 0,
732	s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
733	#else /* VBOX */
734	memset(CTXSUFF(s->vram_ptr), 0,
735	s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
736	#endif /* VBOX */
737	}
738
739	/* we initialize the VGA graphic mode (should be done
740	in BIOS) */
741	s->gr[0x06] = (s->gr[0x06] & ~0x0c) \| 0x05; /* graphic mode + memory map 1 */
742	s->cr[0x17] \|= 3; /* no CGA modes */
743	s->cr[0x13] = s->vbe_line_offset >> 3;
744	/* width */
745	s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
746	/* height (only meaningful if < 1024) */
747	h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
748	s->cr[0x12] = h;
749	s->cr[0x07] = (s->cr[0x07] & ~0x42) \|
750	((h >> 7) & 0x02) \| ((h >> 3) & 0x40);
751	/* line compare to 1023 */
752	s->cr[0x18] = 0xff;
753	s->cr[0x07] \|= 0x10;
754	s->cr[0x09] \|= 0x40;
755
756	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
757	shift_control = 0;
758	s->sr[0x01] &= ~8; /* no double line */
759	} else {
760	shift_control = 2;
761	s->sr[4] \|= 0x08; /* set chain 4 mode */
762	s->sr[2] \|= 0x0f; /* activate all planes */
763	}
764	s->gr[0x05] = (s->gr[0x05] & ~0x60) \| (shift_control << 5);
765	s->cr[0x09] &= ~0x9f; /* no double scan */
766	#ifdef VBOX
767	/* sunlover 30.05.2007
768	* The ar_index remains with bit 0x20 cleared after a switch from fullscreen
769	* DOS mode on Windows XP guest. That leads to GMODE_BLANK in vga_update_display.
770	* But the VBE mode is graphics, so not a blank anymore.
771	*/
772	s->ar_index \|= 0x20;
773	#endif /* VBOX */
774	} else {
775	/* XXX: the bios should do that */
776	#ifdef VBOX
777	/* sunlover 21.12.2006
778	* Here is probably more to reset. When this was executed in GC
779	* then the update functions could not detect a mode change.
780	* Or may be these update function should take the s->vbe_regs[s->vbe_index]
781	* into account when detecting a mode change.
782	*
783	* The 'mode reset not detected' problem is now fixed by executing the
784	* VBE_DISPI_INDEX_ENABLE case always in RING3 in order to call the
785	* LFBChange callback.
786	*/
787	#endif /* VBOX */
788	s->bank_offset = 0;
789	}
790	s->vbe_regs[s->vbe_index] = val;
791	#ifdef VBOX
792	#ifdef IN_RING3
793	/*
794	* LFB video mode is either disabled or changed. This notification
795	* is used by the display to disable VBVA.
796	*/
797	s->pDrv->pfnLFBModeChange(s->pDrv, (val & VBE_DISPI_ENABLED) != 0);
798	#endif /* IN_RING3 */
799	#endif /* VBOX */
800	break;
801	case VBE_DISPI_INDEX_VIRT_WIDTH:
802	{
803	int w, h, line_offset;
804
805	if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
806	return;
807	w = val;
808	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
809	line_offset = w >> 1;
810	else
811	line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
812	h = s->vram_size / line_offset;
813	/* XXX: support weird bochs semantics ? */
814	if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
815	return;
816	s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
817	s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
818	s->vbe_line_offset = line_offset;
819	}
820	break;
821	case VBE_DISPI_INDEX_X_OFFSET:
822	case VBE_DISPI_INDEX_Y_OFFSET:
823	{
824	int x;
825	s->vbe_regs[s->vbe_index] = val;
826	s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
827	x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
828	if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
829	s->vbe_start_addr += x >> 1;
830	else
831	s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
832	s->vbe_start_addr >>= 2;
833	}
834	break;
835	default:
836	break;
837	}
838	}
839	}
840	#endif
841
842	/* called for accesses between 0xa0000 and 0xc0000 */
843	#ifdef VBOX
844	static
845	#endif /* VBOX */
846	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
847	{
848	VGAState s = (VGAState)opaque;
849	int memory_map_mode, plane;
850	uint32_t ret;
851
852	/* convert to VGA memory offset */
853	memory_map_mode = (s->gr[6] >> 2) & 3;
854	addr &= 0x1ffff;
855	switch(memory_map_mode) {
856	case 0:
857	break;
858	case 1:
859	if (addr >= 0x10000)
860	return 0xff;
861	addr += s->bank_offset;
862	break;
863	case 2:
864	addr -= 0x10000;
865	if (addr >= 0x8000)
866	return 0xff;
867	break;
868	default:
869	case 3:
870	addr -= 0x18000;
871	if (addr >= 0x8000)
872	return 0xff;
873	break;
874	}
875
876	#ifdef IN_GC
877	if (addr >= VGA_MAPPING_SIZE)
878	return VINF_IOM_HC_MMIO_WRITE;
879	#endif
880
881	if (s->sr[4] & 0x08) {
882	/* chain 4 mode : simplest access */
883	#ifndef VBOX
884	ret = s->vram_ptr[addr];
885	#else /* VBOX */
886	ret = s->CTXSUFF(vram_ptr)[addr];
887	#endif /* VBOX */
888	} else if (s->gr[5] & 0x10) {
889	/* odd/even mode (aka text mode mapping) */
890	plane = (s->gr[4] & 2) \| (addr & 1);
891	#ifndef VBOX
892	ret = s->vram_ptr[((addr & ~1) << 1) \| plane];
893	#else /* VBOX */
894	ret = s->CTXSUFF(vram_ptr)[((addr & ~1) << 1) \| plane];
895	#endif /* VBOX */
896	} else {
897	/* standard VGA latched access */
898	#ifndef VBOX
899	s->latch = ((uint32_t *)s->vram_ptr)[addr];
900	#else /* VBOX && IN_GC */
901	s->latch = ((uint32_t *)s->CTXSUFF(vram_ptr))[addr];
902	#endif /* VBOX && IN_GC */
903
904	if (!(s->gr[5] & 0x08)) {
905	/* read mode 0 */
906	plane = s->gr[4];
907	ret = GET_PLANE(s->latch, plane);
908	} else {
909	/* read mode 1 */
910	ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
911	ret \|= ret >> 16;
912	ret \|= ret >> 8;
913	ret = (~ret) & 0xff;
914	}
915	}
916	return ret;
917	}
918
919	#ifndef VBOX
920	static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
921	{
922	uint32_t v;
923	#ifdef TARGET_WORDS_BIGENDIAN
924	v = vga_mem_readb(opaque, addr) << 8;
925	v \|= vga_mem_readb(opaque, addr + 1);
926	#else
927	v = vga_mem_readb(opaque, addr);
928	v \|= vga_mem_readb(opaque, addr + 1) << 8;
929	#endif
930	return v;
931	}
932
933	static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
934	{
935	uint32_t v;
936	#ifdef TARGET_WORDS_BIGENDIAN
937	v = vga_mem_readb(opaque, addr) << 24;
938	v \|= vga_mem_readb(opaque, addr + 1) << 16;
939	v \|= vga_mem_readb(opaque, addr + 2) << 8;
940	v \|= vga_mem_readb(opaque, addr + 3);
941	#else
942	v = vga_mem_readb(opaque, addr);
943	v \|= vga_mem_readb(opaque, addr + 1) << 8;
944	v \|= vga_mem_readb(opaque, addr + 2) << 16;
945	v \|= vga_mem_readb(opaque, addr + 3) << 24;
946	#endif
947	return v;
948	}
949	#endif /* !VBOX */
950
951	/* called for accesses between 0xa0000 and 0xc0000 */
952	#ifdef VBOX
953	static
954	#endif /* VBOX */
955	int vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
956	{
957	VGAState s = (VGAState)opaque;
958	int memory_map_mode, plane, write_mode, b, func_select, mask;
959	uint32_t write_mask, bit_mask, set_mask;
960
961	#ifdef DEBUG_VGA_MEM
962	Log(("vga: [0x%x] = 0x%02x\n", addr, val));
963	#endif
964	/* convert to VGA memory offset */
965	memory_map_mode = (s->gr[6] >> 2) & 3;
966	addr &= 0x1ffff;
967	switch(memory_map_mode) {
968	case 0:
969	break;
970	case 1:
971	if (addr >= 0x10000)
972	return VINF_SUCCESS;
973	addr += s->bank_offset;
974	break;
975	case 2:
976	addr -= 0x10000;
977	if (addr >= 0x8000)
978	return VINF_SUCCESS;
979	break;
980	default:
981	case 3:
982	addr -= 0x18000;
983	if (addr >= 0x8000)
984	return VINF_SUCCESS;
985	break;
986	}
987
988	if (s->sr[4] & 0x08) {
989	/* chain 4 mode : simplest access */
990	plane = addr & 3;
991	mask = (1 << plane);
992	if (s->sr[2] & mask) {
993	#ifndef VBOX
994	s->vram_ptr[addr] = val;
995	#else /* VBOX */
996	#ifdef IN_GC
997	if (addr >= VGA_MAPPING_SIZE)
998	return VINF_IOM_HC_MMIO_WRITE;
999	#else
1000	if (addr >= s->vram_size)
1001	{
1002	AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1003	addr, s->bank_offset, memory_map_mode));
1004	return VINF_SUCCESS;
1005	}
1006	#endif
1007	s->CTXSUFF(vram_ptr)[addr] = val;
1008	#endif /* VBOX */
1009	#ifdef DEBUG_VGA_MEM
1010	Log(("vga: chain4: [0x%x]\n", addr));
1011	#endif
1012	s->plane_updated \|= mask; /* only used to detect font change */
1013	#ifndef VBOX
1014	cpu_physical_memory_set_dirty(s->vram_offset + addr);
1015	#else /* VBOX */
1016	vga_set_dirty(s, addr);
1017	#endif /* VBOX */
1018	}
1019	} else if (s->gr[5] & 0x10) {
1020	/* odd/even mode (aka text mode mapping) */
1021	plane = (s->gr[4] & 2) \| (addr & 1);
1022	mask = (1 << plane);
1023	if (s->sr[2] & mask) {
1024	addr = ((addr & ~1) << 1) \| plane;
1025	#ifndef VBOX
1026	s->vram_ptr[addr] = val;
1027	#else /* VBOX */
1028	#ifdef IN_GC
1029	if (addr >= VGA_MAPPING_SIZE)
1030	return VINF_IOM_HC_MMIO_WRITE;
1031	#else
1032	if (addr >= s->vram_size)
1033	{
1034	AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1035	addr, s->bank_offset, memory_map_mode));
1036	return VINF_SUCCESS;
1037	}
1038	#endif
1039	s->CTXSUFF(vram_ptr)[addr] = val;
1040	#endif /* VBOX */
1041	#ifdef DEBUG_VGA_MEM
1042	Log(("vga: odd/even: [0x%x]\n", addr));
1043	#endif
1044	s->plane_updated \|= mask; /* only used to detect font change */
1045	#ifndef VBOX
1046	cpu_physical_memory_set_dirty(s->vram_offset + addr);
1047	#else /* VBOX */
1048	vga_set_dirty(s, addr);
1049	#endif /* VBOX */
1050	}
1051	} else {
1052	#ifdef IN_GC
1053	if (addr * 4 >= VGA_MAPPING_SIZE)
1054	return VINF_IOM_HC_MMIO_WRITE;
1055	#else
1056	if (addr * 4 >= s->vram_size)
1057	{
1058	AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1059	addr * 4, s->bank_offset, memory_map_mode));
1060	return VINF_SUCCESS;
1061	}
1062	#endif
1063
1064	/* standard VGA latched access */
1065	write_mode = s->gr[5] & 3;
1066	switch(write_mode) {
1067	default:
1068	case 0:
1069	/* rotate */
1070	b = s->gr[3] & 7;
1071	val = ((val >> b) \| (val << (8 - b))) & 0xff;
1072	val \|= val << 8;
1073	val \|= val << 16;
1074
1075	/* apply set/reset mask */
1076	set_mask = mask16[s->gr[1]];
1077	val = (val & ~set_mask) \| (mask16[s->gr[0]] & set_mask);
1078	bit_mask = s->gr[8];
1079	break;
1080	case 1:
1081	val = s->latch;
1082	goto do_write;
1083	case 2:
1084	val = mask16[val & 0x0f];
1085	bit_mask = s->gr[8];
1086	break;
1087	case 3:
1088	/* rotate */
1089	b = s->gr[3] & 7;
1090	val = (val >> b) \| (val << (8 - b));
1091
1092	bit_mask = s->gr[8] & val;
1093	val = mask16[s->gr[0]];
1094	break;
1095	}
1096
1097	/* apply logical operation */
1098	func_select = s->gr[3] >> 3;
1099	switch(func_select) {
1100	case 0:
1101	default:
1102	/* nothing to do */
1103	break;
1104	case 1:
1105	/* and */
1106	val &= s->latch;
1107	break;
1108	case 2:
1109	/* or */
1110	val \|= s->latch;
1111	break;
1112	case 3:
1113	/* xor */
1114	val ^= s->latch;
1115	break;
1116	}
1117
1118	/* apply bit mask */
1119	bit_mask \|= bit_mask << 8;
1120	bit_mask \|= bit_mask << 16;
1121	val = (val & bit_mask) \| (s->latch & ~bit_mask);
1122
1123	do_write:
1124	/* mask data according to sr[2] */
1125	mask = s->sr[2];
1126	s->plane_updated \|= mask; /* only used to detect font change */
1127	write_mask = mask16[mask];
1128	#ifndef VBOX
1129	((uint32_t *)s->vram_ptr)[addr] =
1130	(((uint32_t *)s->vram_ptr)[addr] & ~write_mask) \|
1131	(val & write_mask);
1132	#else /* VBOX */
1133	((uint32_t *)s->CTXSUFF(vram_ptr))[addr] =
1134	(((uint32_t *)s->CTXSUFF(vram_ptr))[addr] & ~write_mask) \|
1135	(val & write_mask);
1136	#endif /* VBOX */
1137	#ifdef DEBUG_VGA_MEM
1138	Log(("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
1139	addr * 4, write_mask, val));
1140	#endif
1141	#ifndef VBOX
1142	cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
1143	#else /* VBOX */
1144	vga_set_dirty(s, (addr << 2));
1145	#endif /* VBOX */
1146	}
1147
1148	return VINF_SUCCESS;
1149	}
1150
1151	#ifndef VBOX
1152	static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1153	{
1154	#ifdef TARGET_WORDS_BIGENDIAN
1155	vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1156	vga_mem_writeb(opaque, addr + 1, val & 0xff);
1157	#else
1158	vga_mem_writeb(opaque, addr, val & 0xff);
1159	vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1160	#endif
1161	}
1162
1163	static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1164	{
1165	#ifdef TARGET_WORDS_BIGENDIAN
1166	vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1167	vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1168	vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1169	vga_mem_writeb(opaque, addr + 3, val & 0xff);
1170	#else
1171	vga_mem_writeb(opaque, addr, val & 0xff);
1172	vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1173	vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1174	vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1175	#endif
1176	}
1177	#endif /* !VBOX */
1178
1179	#if !defined(VBOX) \|\| defined(IN_RING3)
1180	typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
1181	const uint8_t *font_ptr, int h,
1182	uint32_t fgcol, uint32_t bgcol);
1183	typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
1184	const uint8_t *font_ptr, int h,
1185	uint32_t fgcol, uint32_t bgcol, int dup9);
1186	typedef void vga_draw_line_func(VGAState s1, uint8_t d,
1187	const uint8_t *s, int width);
1188
1189	static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
1190	{
1191	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
1192	}
1193
1194	static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
1195	{
1196	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
1197	}
1198
1199	static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
1200	{
1201	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
1202	}
1203
1204	static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
1205	{
1206	return (r << 16) \| (g << 8) \| b;
1207	}
1208
1209	#define DEPTH 8
1210	#include "DevVGATmpl.h"
1211
1212	#define DEPTH 15
1213	#include "DevVGATmpl.h"
1214
1215	#define DEPTH 16
1216	#include "DevVGATmpl.h"
1217
1218	#define DEPTH 32
1219	#include "DevVGATmpl.h"
1220
1221	static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1222	{
1223	unsigned int col;
1224	col = rgb_to_pixel8(r, g, b);
1225	col \|= col << 8;
1226	col \|= col << 16;
1227	return col;
1228	}
1229
1230	static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1231	{
1232	unsigned int col;
1233	col = rgb_to_pixel15(r, g, b);
1234	col \|= col << 16;
1235	return col;
1236	}
1237
1238	static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1239	{
1240	unsigned int col;
1241	col = rgb_to_pixel16(r, g, b);
1242	col \|= col << 16;
1243	return col;
1244	}
1245
1246	static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1247	{
1248	unsigned int col;
1249	col = rgb_to_pixel32(r, g, b);
1250	return col;
1251	}
1252
1253	/* return true if the palette was modified */
1254	static int update_palette16(VGAState *s)
1255	{
1256	int full_update, i;
1257	uint32_t v, col, *palette;
1258
1259	full_update = 0;
1260	palette = s->last_palette;
1261	for(i = 0; i < 16; i++) {
1262	v = s->ar[i];
1263	if (s->ar[0x10] & 0x80)
1264	v = ((s->ar[0x14] & 0xf) << 4) \| (v & 0xf);
1265	else
1266	v = ((s->ar[0x14] & 0xc) << 4) \| (v & 0x3f);
1267	v = v * 3;
1268	col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1269	c6_to_8(s->palette[v + 1]),
1270	c6_to_8(s->palette[v + 2]));
1271	if (col != palette[i]) {
1272	full_update = 1;
1273	palette[i] = col;
1274	}
1275	}
1276	return full_update;
1277	}
1278
1279	/* return true if the palette was modified */
1280	static int update_palette256(VGAState *s)
1281	{
1282	int full_update, i;
1283	uint32_t v, col, *palette;
1284
1285	full_update = 0;
1286	palette = s->last_palette;
1287	v = 0;
1288	for(i = 0; i < 256; i++) {
1289	col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1290	c6_to_8(s->palette[v + 1]),
1291	c6_to_8(s->palette[v + 2]));
1292	if (col != palette[i]) {
1293	full_update = 1;
1294	palette[i] = col;
1295	}
1296	v += 3;
1297	}
1298	return full_update;
1299	}
1300
1301	static void vga_get_offsets(VGAState *s,
1302	uint32_t *pline_offset,
1303	uint32_t *pstart_addr,
1304	uint32_t *pline_compare)
1305	{
1306	uint32_t start_addr, line_offset, line_compare;
1307	#ifdef CONFIG_BOCHS_VBE
1308	if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1309	line_offset = s->vbe_line_offset;
1310	start_addr = s->vbe_start_addr;
1311	line_compare = 65535;
1312	} else
1313	#endif
1314	{
1315	/* compute line_offset in bytes */
1316	line_offset = s->cr[0x13];
1317	line_offset <<= 3;
1318
1319	/* starting address */
1320	start_addr = s->cr[0x0d] \| (s->cr[0x0c] << 8);
1321
1322	/* line compare */
1323	line_compare = s->cr[0x18] \|
1324	((s->cr[0x07] & 0x10) << 4) \|
1325	((s->cr[0x09] & 0x40) << 3);
1326	}
1327	*pline_offset = line_offset;
1328	*pstart_addr = start_addr;
1329	*pline_compare = line_compare;
1330	}
1331
1332	/* update start_addr and line_offset. Return TRUE if modified */
1333	static int update_basic_params(VGAState *s)
1334	{
1335	int full_update;
1336	uint32_t start_addr, line_offset, line_compare;
1337
1338	full_update = 0;
1339
1340	s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1341
1342	if (line_offset != s->line_offset \|\|
1343	start_addr != s->start_addr \|\|
1344	line_compare != s->line_compare) {
1345	s->line_offset = line_offset;
1346	s->start_addr = start_addr;
1347	s->line_compare = line_compare;
1348	full_update = 1;
1349	}
1350	return full_update;
1351	}
1352
1353	static inline int get_depth_index(int depth)
1354	{
1355	switch(depth) {
1356	default:
1357	case 8:
1358	return 0;
1359	case 15:
1360	return 1;
1361	case 16:
1362	return 2;
1363	case 32:
1364	return 3;
1365	}
1366	}
1367
1368	static vga_draw_glyph8_func *vga_draw_glyph8_table[4] = {
1369	vga_draw_glyph8_8,
1370	vga_draw_glyph8_16,
1371	vga_draw_glyph8_16,
1372	vga_draw_glyph8_32,
1373	};
1374
1375	static vga_draw_glyph8_func *vga_draw_glyph16_table[4] = {
1376	vga_draw_glyph16_8,
1377	vga_draw_glyph16_16,
1378	vga_draw_glyph16_16,
1379	vga_draw_glyph16_32,
1380	};
1381
1382	static vga_draw_glyph9_func *vga_draw_glyph9_table[4] = {
1383	vga_draw_glyph9_8,
1384	vga_draw_glyph9_16,
1385	vga_draw_glyph9_16,
1386	vga_draw_glyph9_32,
1387	};
1388
1389	static const uint8_t cursor_glyph[32 * 4] = {
1390	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1391	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1392	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1393	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1394	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1395	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1396	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1397	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1398	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1399	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1400	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1401	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1402	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1403	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1404	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1405	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1406	};
1407
1408	/*
1409	* Text mode update
1410	* Missing:
1411	* - double scan
1412	* - double width
1413	* - underline
1414	* - flashing
1415	*/
1416	#ifndef VBOX
1417	static void vga_draw_text(VGAState *s, int full_update)
1418	#else
1419	static int vga_draw_text(VGAState *s, int full_update)
1420	#endif /* !VBOX */
1421	{
1422	int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1423	int cx_min, cx_max, linesize, x_incr;
1424	uint32_t offset, fgcol, bgcol, v, cursor_offset;
1425	uint8_t d1, d, src, s1, dest, cursor_ptr;
1426	const uint8_t font_ptr, font_base[2];
1427	int dup9, line_offset, depth_index;
1428	uint32_t *palette;
1429	uint32_t *ch_attr_ptr;
1430	vga_draw_glyph8_func *vga_draw_glyph8;
1431	vga_draw_glyph9_func *vga_draw_glyph9;
1432
1433	full_update \|= update_palette16(s);
1434	palette = s->last_palette;
1435
1436	/* compute font data address (in plane 2) */
1437	v = s->sr[3];
1438	offset = (((v >> 4) & 1) \| ((v << 1) & 6)) * 8192 * 4 + 2;
1439	if (offset != s->font_offsets[0]) {
1440	s->font_offsets[0] = offset;
1441	full_update = 1;
1442	}
1443	#ifndef VBOX
1444	font_base[0] = s->vram_ptr + offset;
1445	#else /* VBOX */
1446	font_base[0] = s->CTXSUFF(vram_ptr) + offset;
1447	#endif /* VBOX */
1448
1449	offset = (((v >> 5) & 1) \| ((v >> 1) & 6)) * 8192 * 4 + 2;
1450	#ifndef VBOX
1451	font_base[1] = s->vram_ptr + offset;
1452	#else /* VBOX */
1453	font_base[1] = s->CTXSUFF(vram_ptr) + offset;
1454	#endif /* VBOX */
1455	if (offset != s->font_offsets[1]) {
1456	s->font_offsets[1] = offset;
1457	full_update = 1;
1458	}
1459	if (s->plane_updated & (1 << 2)) {
1460	/* if the plane 2 was modified since the last display, it
1461	indicates the font may have been modified */
1462	s->plane_updated = 0;
1463	full_update = 1;
1464	}
1465	full_update \|= update_basic_params(s);
1466
1467	line_offset = s->line_offset;
1468	#ifndef VBOX
1469	s1 = s->vram_ptr + (s->start_addr * 4);
1470	#else /* VBOX */
1471	s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 4);
1472	#endif /* VBOX */
1473
1474	/* total width & height */
1475	cheight = (s->cr[9] & 0x1f) + 1;
1476	cw = 8;
1477	if (!(s->sr[1] & 0x01))
1478	cw = 9;
1479	if (s->sr[1] & 0x08)
1480	cw = 16; /* NOTE: no 18 pixel wide */
1481	#ifndef VBOX
1482	x_incr = cw * ((s->ds->depth + 7) >> 3);
1483	#else /* VBOX */
1484	x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
1485	#endif /* VBOX */
1486	width = (s->cr[0x01] + 1);
1487	if (s->cr[0x06] == 100) {
1488	/* ugly hack for CGA 160x100x16 - explain me the logic */
1489	height = 100;
1490	} else {
1491	height = s->cr[0x12] \|
1492	((s->cr[0x07] & 0x02) << 7) \|
1493	((s->cr[0x07] & 0x40) << 3);
1494	height = (height + 1) / cheight;
1495	}
1496	if ((height * width) > CH_ATTR_SIZE) {
1497	/* better than nothing: exit if transient size is too big */
1498	#ifndef VBOX
1499	return;
1500	#else
1501	return VINF_SUCCESS;
1502	#endif /* VBOX */
1503	}
1504
1505	if (width != (int)s->last_width \|\| height != (int)s->last_height \|\|
1506	cw != s->last_cw \|\| cheight != s->last_ch) {
1507	s->last_scr_width = width * cw;
1508	s->last_scr_height = height * cheight;
1509	#ifndef VBOX
1510	dpy_resize(s->ds, s->last_scr_width, s->last_scr_height);
1511	s->last_width = width;
1512	s->last_height = height;
1513	s->last_ch = cheight;
1514	s->last_cw = cw;
1515	full_update = 1;
1516	#else /* VBOX */
1517	/* For text modes the direct use of guest VRAM is not implemented, so bpp and cbLine are 0 here. */
1518	int rc = s->pDrv->pfnResize(s->pDrv, 0, NULL, 0, s->last_scr_width, s->last_scr_height);
1519	s->last_width = width;
1520	s->last_height = height;
1521	s->last_ch = cheight;
1522	s->last_cw = cw;
1523	full_update = 1;
1524	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1525	return rc;
1526	AssertRC(rc);
1527	#endif /* VBOX */
1528	}
1529	cursor_offset = ((s->cr[0x0e] << 8) \| s->cr[0x0f]) - s->start_addr;
1530	if (cursor_offset != s->cursor_offset \|\|
1531	s->cr[0xa] != s->cursor_start \|\|
1532	s->cr[0xb] != s->cursor_end) {
1533	/* if the cursor position changed, we update the old and new
1534	chars */
1535	if (s->cursor_offset < CH_ATTR_SIZE)
1536	s->last_ch_attr[s->cursor_offset] = ~0;
1537	if (cursor_offset < CH_ATTR_SIZE)
1538	s->last_ch_attr[cursor_offset] = ~0;
1539	s->cursor_offset = cursor_offset;
1540	s->cursor_start = s->cr[0xa];
1541	s->cursor_end = s->cr[0xb];
1542	}
1543	#ifndef VBOX
1544	cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1545
1546	depth_index = get_depth_index(s->ds->depth);
1547	#else /* VBOX */
1548	cursor_ptr = s->CTXSUFF(vram_ptr) + (s->start_addr + cursor_offset) * 4;
1549	depth_index = get_depth_index(s->pDrv->cBits);
1550	#endif /* VBOX */
1551	if (cw == 16)
1552	vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1553	else
1554	vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1555	vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1556
1557	#ifndef VBOX
1558	dest = s->ds->data;
1559	linesize = s->ds->linesize;
1560	#else /* VBOX */
1561	dest = s->pDrv->pu8Data;
1562	linesize = s->pDrv->cbScanline;
1563	#endif /* VBOX */
1564	ch_attr_ptr = s->last_ch_attr;
1565
1566	for(cy = 0; cy < height; cy++) {
1567	d1 = dest;
1568	src = s1;
1569	cx_min = width;
1570	cx_max = -1;
1571	for(cx = 0; cx < width; cx++) {
1572	ch_attr = (uint16_t )src;
1573	if (full_update \|\| ch_attr != (int)*ch_attr_ptr) {
1574	if (cx < cx_min)
1575	cx_min = cx;
1576	if (cx > cx_max)
1577	cx_max = cx;
1578	*ch_attr_ptr = ch_attr;
1579	#ifdef WORDS_BIGENDIAN
1580	ch = ch_attr >> 8;
1581	cattr = ch_attr & 0xff;
1582	#else
1583	ch = ch_attr & 0xff;
1584	cattr = ch_attr >> 8;
1585	#endif
1586	font_ptr = font_base[(cattr >> 3) & 1];
1587	font_ptr += 32 * 4 * ch;
1588	bgcol = palette[cattr >> 4];
1589	fgcol = palette[cattr & 0x0f];
1590	if (cw != 9) {
1591	vga_draw_glyph8(d1, linesize,
1592	font_ptr, cheight, fgcol, bgcol);
1593	} else {
1594	dup9 = 0;
1595	if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1596	dup9 = 1;
1597	vga_draw_glyph9(d1, linesize,
1598	font_ptr, cheight, fgcol, bgcol, dup9);
1599	}
1600	if (src == cursor_ptr &&
1601	!(s->cr[0x0a] & 0x20)) {
1602	int line_start, line_last, h;
1603	/* draw the cursor */
1604	line_start = s->cr[0x0a] & 0x1f;
1605	line_last = s->cr[0x0b] & 0x1f;
1606	/* XXX: check that */
1607	if (line_last > cheight - 1)
1608	line_last = cheight - 1;
1609	if (line_last >= line_start && line_start < cheight) {
1610	h = line_last - line_start + 1;
1611	d = d1 + linesize * line_start;
1612	if (cw != 9) {
1613	vga_draw_glyph8(d, linesize,
1614	cursor_glyph, h, fgcol, bgcol);
1615	} else {
1616	vga_draw_glyph9(d, linesize,
1617	cursor_glyph, h, fgcol, bgcol, 1);
1618	}
1619	}
1620	}
1621	}
1622	d1 += x_incr;
1623	src += 4;
1624	ch_attr_ptr++;
1625	}
1626	#ifndef VBOX
1627	if (cx_max != -1) {
1628	dpy_update(s->ds, cx_min * cw, cy * cheight,
1629	(cx_max - cx_min + 1) * cw, cheight);
1630	}
1631	#else
1632	if (cx_max != -1)
1633	s->pDrv->pfnUpdateRect(s->pDrv, cx_min * cw, cy * cheight, (cx_max - cx_min + 1) * cw, cheight);
1634	#endif
1635	dest += linesize * cheight;
1636	s1 += line_offset;
1637	}
1638	#ifdef VBOX
1639	return VINF_SUCCESS;
1640	#endif /* VBOX */
1641	}
1642
1643	enum {
1644	VGA_DRAW_LINE2,
1645	VGA_DRAW_LINE2D2,
1646	VGA_DRAW_LINE4,
1647	VGA_DRAW_LINE4D2,
1648	VGA_DRAW_LINE8D2,
1649	VGA_DRAW_LINE8,
1650	VGA_DRAW_LINE15,
1651	VGA_DRAW_LINE16,
1652	VGA_DRAW_LINE24,
1653	VGA_DRAW_LINE32,
1654	VGA_DRAW_LINE_NB
1655	};
1656
1657	static vga_draw_line_func vga_draw_line_table[4 VGA_DRAW_LINE_NB] = {
1658	vga_draw_line2_8,
1659	vga_draw_line2_16,
1660	vga_draw_line2_16,
1661	vga_draw_line2_32,
1662
1663	vga_draw_line2d2_8,
1664	vga_draw_line2d2_16,
1665	vga_draw_line2d2_16,
1666	vga_draw_line2d2_32,
1667
1668	vga_draw_line4_8,
1669	vga_draw_line4_16,
1670	vga_draw_line4_16,
1671	vga_draw_line4_32,
1672
1673	vga_draw_line4d2_8,
1674	vga_draw_line4d2_16,
1675	vga_draw_line4d2_16,
1676	vga_draw_line4d2_32,
1677
1678	vga_draw_line8d2_8,
1679	vga_draw_line8d2_16,
1680	vga_draw_line8d2_16,
1681	vga_draw_line8d2_32,
1682
1683	vga_draw_line8_8,
1684	vga_draw_line8_16,
1685	vga_draw_line8_16,
1686	vga_draw_line8_32,
1687
1688	vga_draw_line15_8,
1689	vga_draw_line15_15,
1690	vga_draw_line15_16,
1691	vga_draw_line15_32,
1692
1693	vga_draw_line16_8,
1694	vga_draw_line16_15,
1695	vga_draw_line16_16,
1696	vga_draw_line16_32,
1697
1698	vga_draw_line24_8,
1699	vga_draw_line24_15,
1700	vga_draw_line24_16,
1701	vga_draw_line24_32,
1702
1703	vga_draw_line32_8,
1704	vga_draw_line32_15,
1705	vga_draw_line32_16,
1706	vga_draw_line32_32,
1707	};
1708
1709	static int vga_get_bpp(VGAState *s)
1710	{
1711	int ret;
1712	#ifdef CONFIG_BOCHS_VBE
1713	if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1714	ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1715	} else
1716	#endif
1717	{
1718	ret = 0;
1719	}
1720	return ret;
1721	}
1722
1723	static void vga_get_resolution(VGAState s, int pwidth, int *pheight)
1724	{
1725	int width, height;
1726	#ifdef CONFIG_BOCHS_VBE
1727	if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1728	width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1729	height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1730	} else
1731	#endif
1732	{
1733	width = (s->cr[0x01] + 1) * 8;
1734	height = s->cr[0x12] \|
1735	((s->cr[0x07] & 0x02) << 7) \|
1736	((s->cr[0x07] & 0x40) << 3);
1737	height = (height + 1);
1738	}
1739	*pwidth = width;
1740	*pheight = height;
1741	}
1742
1743	#ifndef VBOX
1744	void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1745	{
1746	int y;
1747	if (y1 >= VGA_MAX_HEIGHT)
1748	return;
1749	if (y2 >= VGA_MAX_HEIGHT)
1750	y2 = VGA_MAX_HEIGHT;
1751	for(y = y1; y < y2; y++) {
1752	s->invalidated_y_table[y >> 5] \|= 1 << (y & 0x1f);
1753	}
1754	}
1755	#endif /* !VBOX*/
1756
1757	#ifdef VBOX
1758	/**
1759	* Performs the display driver resizing when in graphics mode.
1760	*
1761	* This will recalc / update any status data depending on the driver
1762	* properties (bit depth mostly).
1763	*
1764	* @returns VINF_SUCCESS on success.
1765	* @returns VINF_VGA_RESIZE_IN_PROGRESS if the operation wasn't complete.
1766	* @param s Pointer to the vga status.
1767	* @param cx The width.
1768	* @param cy The height.
1769	*/
1770	static int vga_resize_graphic(VGAState *s, int cx, int cy, int v)
1771	{
1772	const unsigned cBits = s->get_bpp(s);
1773	/** @todo r=sunlover: If the guest changes VBE_DISPI_INDEX_X_OFFSET, VBE_DISPI_INDEX_Y_OFFSET
1774	* registers, then the third parameter of the following call should be
1775	* probably 's->CTXSUFF(vram_ptr) + s->vbe_start_addr'.
1776	*/
1777	int rc = s->pDrv->pfnResize(s->pDrv, cBits, s->CTXSUFF(vram_ptr), s->line_offset, cx, cy);
1778
1779	/* last stuff */
1780	s->last_bpp = cBits;
1781	s->last_scr_width = cx;
1782	s->last_scr_height = cy;
1783	s->last_width = cx;
1784	s->last_height = cy;
1785
1786	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1787	return rc;
1788	AssertRC(rc);
1789
1790	/* update palette */
1791	switch (s->pDrv->cBits)
1792	{
1793	case 32: s->rgb_to_pixel = rgb_to_pixel32_dup; break;
1794	case 16:
1795	default: s->rgb_to_pixel = rgb_to_pixel16_dup; break;
1796	case 15: s->rgb_to_pixel = rgb_to_pixel15_dup; break;
1797	case 8: s->rgb_to_pixel = rgb_to_pixel8_dup; break;
1798	}
1799	if (s->shift_control == 0)
1800	update_palette16(s);
1801	else if (s->shift_control == 1)
1802	update_palette16(s);
1803	return VINF_SUCCESS;
1804	}
1805	#endif /* VBOX */
1806
1807	/*
1808	* graphic modes
1809	*/
1810	#ifndef VBOX
1811	static void vga_draw_graphic(VGAState *s, int full_update)
1812	#else
1813	static int vga_draw_graphic(VGAState *s, int full_update)
1814	#endif /* !VBOX */
1815	{
1816	int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask;
1817	int width, height, shift_control, line_offset, page0, page1, bwidth;
1818	int disp_width, multi_scan, multi_run;
1819	uint8_t *d;
1820	uint32_t v, addr1, addr;
1821	vga_draw_line_func *vga_draw_line;
1822	bool offsets_changed;
1823
1824	offsets_changed = update_basic_params(s);
1825
1826	full_update \|= offsets_changed;
1827
1828	s->get_resolution(s, &width, &height);
1829	disp_width = width;
1830
1831	shift_control = (s->gr[0x05] >> 5) & 3;
1832	double_scan = (s->cr[0x09] >> 7);
1833	if (shift_control != 1) {
1834	multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1835	} else {
1836	/* in CGA modes, multi_scan is ignored */
1837	/* XXX: is it correct ? */
1838	multi_scan = double_scan;
1839	}
1840	multi_run = multi_scan;
1841	if (shift_control != s->shift_control \|\|
1842	double_scan != s->double_scan) {
1843	full_update = 1;
1844	s->shift_control = shift_control;
1845	s->double_scan = double_scan;
1846	}
1847
1848	if (shift_control == 0) {
1849	full_update \|= update_palette16(s);
1850	if (s->sr[0x01] & 8) {
1851	v = VGA_DRAW_LINE4D2;
1852	disp_width <<= 1;
1853	} else {
1854	v = VGA_DRAW_LINE4;
1855	}
1856	} else if (shift_control == 1) {
1857	full_update \|= update_palette16(s);
1858	if (s->sr[0x01] & 8) {
1859	v = VGA_DRAW_LINE2D2;
1860	disp_width <<= 1;
1861	} else {
1862	v = VGA_DRAW_LINE2;
1863	}
1864	} else {
1865	switch(s->get_bpp(s)) {
1866	default:
1867	case 0:
1868	full_update \|= update_palette256(s);
1869	v = VGA_DRAW_LINE8D2;
1870	break;
1871	case 8:
1872	full_update \|= update_palette256(s);
1873	v = VGA_DRAW_LINE8;
1874	break;
1875	case 15:
1876	v = VGA_DRAW_LINE15;
1877	break;
1878	case 16:
1879	v = VGA_DRAW_LINE16;
1880	break;
1881	case 24:
1882	v = VGA_DRAW_LINE24;
1883	break;
1884	case 32:
1885	v = VGA_DRAW_LINE32;
1886	break;
1887	}
1888	}
1889	#ifndef VBOX
1890	vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
1891
1892	if (disp_width != s->last_width \|\|
1893	height != s->last_height) {
1894	dpy_resize(s->ds, disp_width, height);
1895	s->last_scr_width = disp_width;
1896	s->last_scr_height = height;
1897	s->last_width = disp_width;
1898	s->last_height = height;
1899	full_update = 1;
1900	}
1901	#else /* VBOX */
1902	if ( disp_width != (int)s->last_width
1903	\|\| height != (int)s->last_height
1904	\|\| s->get_bpp(s) != (int)s->last_bpp
1905	\|\| offsets_changed)
1906	{
1907	int rc = vga_resize_graphic(s, disp_width, height, v);
1908	if (rc != VINF_SUCCESS) /* Return any rc, particularly VINF_VGA_RESIZE_IN_PROGRESS, to the caller. */
1909	return rc;
1910	full_update = 1;
1911	}
1912	vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
1913
1914	#endif /* VBOX */
1915	if (s->cursor_invalidate)
1916	s->cursor_invalidate(s);
1917
1918	line_offset = s->line_offset;
1919	#if 0
1920	Log(("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1921	width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]));
1922	#endif
1923	addr1 = (s->start_addr * 4);
1924	#ifndef VBOX
1925	bwidth = width * 4;
1926	#else /* VBOX */
1927	/* The width of VRAM scanline. */
1928	bwidth = s->line_offset;
1929	/* In some cases the variable is not yet set, probably due to incomplete
1930	* programming of the virtual hardware ports. Just return.
1931	*/
1932	if (bwidth == 0) return VINF_SUCCESS;
1933	#endif /* VBOX */
1934	y_start = -1;
1935	page_min = 0x7fffffff;
1936	page_max = -1;
1937	#ifndef VBOX
1938	d = s->ds->data;
1939	linesize = s->ds->linesize;
1940	#else /* VBOX */
1941	d = s->pDrv->pu8Data;
1942	linesize = s->pDrv->cbScanline;
1943	#endif /* VBOX */
1944
1945	y1 = 0;
1946	for(y = 0; y < height; y++) {
1947	addr = addr1;
1948	if (!(s->cr[0x17] & 1)) {
1949	int shift;
1950	/* CGA compatibility handling */
1951	shift = 14 + ((s->cr[0x17] >> 6) & 1);
1952	addr = (addr & ~(1 << shift)) \| ((y1 & 1) << shift);
1953	}
1954	if (!(s->cr[0x17] & 2)) {
1955	addr = (addr & ~0x8000) \| ((y1 & 2) << 14);
1956	}
1957	#ifndef VBOX
1958	page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1959	page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1960	update = full_update \|
1961	cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) \|
1962	cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1963	if ((page1 - page0) > TARGET_PAGE_SIZE) {
1964	/* if wide line, can use another page */
1965	update \|= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1966	VGA_DIRTY_FLAG);
1967	}
1968	#else /* VBOX */
1969	page0 = addr & TARGET_PAGE_MASK;
1970	page1 = (addr + bwidth - 1) & TARGET_PAGE_MASK;
1971	update = full_update \| vga_is_dirty(s, page0) \| vga_is_dirty(s, page1);
1972	if (page1 - page0 > TARGET_PAGE_SIZE) {
1973	/* if wide line, can use another page */
1974	update \|= vga_is_dirty(s, page0 + TARGET_PAGE_SIZE);
1975	}
1976	#endif /* VBOX */
1977	/* explicit invalidation for the hardware cursor */
1978	update \|= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1979	if (update) {
1980	if (y_start < 0)
1981	y_start = y;
1982	if (page0 < page_min)
1983	page_min = page0;
1984	if (page1 > page_max)
1985	page_max = page1;
1986	#ifndef VBOX
1987	vga_draw_line(s, d, s->vram_ptr + addr, width);
1988	#else /* VBOX */
1989	if (s->fRenderVRAM)
1990	vga_draw_line(s, d, s->CTXSUFF(vram_ptr) + addr, width);
1991	#endif /* VBOX */
1992	if (s->cursor_draw_line)
1993	s->cursor_draw_line(s, d, y);
1994	} else {
1995	if (y_start >= 0) {
1996	/* flush to display */
1997	#ifndef VBOX
1998	dpy_update(s->ds, 0, y_start,
1999	disp_width, y - y_start);
2000	#else /* VBOX */
2001	s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2002	#endif /* VBOX */
2003	y_start = -1;
2004	}
2005	}
2006	if (!multi_run) {
2007	mask = (s->cr[0x17] & 3) ^ 3;
2008	if ((y1 & mask) == mask)
2009	addr1 += line_offset;
2010	y1++;
2011	multi_run = multi_scan;
2012	} else {
2013	multi_run--;
2014	}
2015	/* line compare acts on the displayed lines */
2016	if ((uint32_t)y == s->line_compare)
2017	addr1 = 0;
2018	d += linesize;
2019	}
2020	if (y_start >= 0) {
2021	/* flush to display */
2022	#ifndef VBOX
2023	dpy_update(s->ds, 0, y_start,
2024	disp_width, y - y_start);
2025	#else /* VBOX */
2026	s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2027	#endif /* VBOX */
2028	}
2029	/* reset modified pages */
2030	if (page_max != -1) {
2031	#ifndef VBOX
2032	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
2033	VGA_DIRTY_FLAG);
2034	#else /* VBOX */
2035	vga_reset_dirty(s, page_min, page_max + TARGET_PAGE_SIZE);
2036	#endif /* VBOX */
2037	}
2038	memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
2039	#ifdef VBOX
2040	return VINF_SUCCESS;
2041	#endif /* VBOX */
2042	}
2043
2044	static void vga_draw_blank(VGAState *s, int full_update)
2045	{
2046	#ifndef VBOX
2047	int i, w, val;
2048	uint8_t *d;
2049
2050	if (!full_update)
2051	return;
2052	if (s->last_scr_width <= 0 \|\| s->last_scr_height <= 0)
2053	return;
2054	if (s->ds->depth == 8)
2055	val = s->rgb_to_pixel(0, 0, 0);
2056	else
2057	val = 0;
2058	w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
2059	d = s->ds->data;
2060	for(i = 0; i < s->last_scr_height; i++) {
2061	memset(d, val, w);
2062	d += s->ds->linesize;
2063	}
2064	dpy_update(s->ds, 0, 0,
2065	s->last_scr_width, s->last_scr_height);
2066	#else /* VBOX */
2067
2068	int i, w, val;
2069	uint8_t *d;
2070	uint32_t cbScanline = s->pDrv->cbScanline;
2071
2072	if (!full_update)
2073	return;
2074	if (s->last_scr_width <= 0 \|\| s->last_scr_height <= 0)
2075	return;
2076	if (s->pDrv->cBits == 8)
2077	val = s->rgb_to_pixel(0, 0, 0);
2078	else
2079	val = 0;
2080	w = s->last_scr_width * ((s->pDrv->cBits + 7) >> 3);
2081	d = s->pDrv->pu8Data;
2082	for(i = 0; i < (int)s->last_scr_height; i++) {
2083	memset(d, val, w);
2084	d += cbScanline;
2085	}
2086	s->pDrv->pfnUpdateRect(s->pDrv, 0, 0, s->last_scr_width, s->last_scr_height);
2087	#endif /* VBOX */
2088	}
2089
2090	#define GMODE_TEXT 0
2091	#define GMODE_GRAPH 1
2092	#define GMODE_BLANK 2
2093
2094	#ifndef VBOX
2095	void vga_update_display(void)
2096	{
2097	VGAState *s = vga_state;
2098	#else /* VBOX */
2099	static int vga_update_display(PVGASTATE s)
2100	{
2101	int rc = VINF_SUCCESS;
2102	#endif /* VBOX */
2103	int full_update, graphic_mode;
2104
2105	#ifndef VBOX
2106	if (s->ds->depth == 0) {
2107	#else /* VBOX */
2108	if (s->pDrv->cBits == 0) {
2109	#endif /* VBOX */
2110	/* nothing to do */
2111	} else {
2112	#ifndef VBOX
2113	switch(s->ds->depth) {
2114	#else /* VBOX */
2115	switch(s->pDrv->cBits) {
2116	#endif /* VBOX */
2117	case 8:
2118	s->rgb_to_pixel = rgb_to_pixel8_dup;
2119	break;
2120	case 15:
2121	s->rgb_to_pixel = rgb_to_pixel15_dup;
2122	break;
2123	default:
2124	case 16:
2125	s->rgb_to_pixel = rgb_to_pixel16_dup;
2126	break;
2127	case 32:
2128	s->rgb_to_pixel = rgb_to_pixel32_dup;
2129	break;
2130	}
2131
2132	full_update = 0;
2133	if (!(s->ar_index & 0x20)) {
2134	graphic_mode = GMODE_BLANK;
2135	} else {
2136	graphic_mode = s->gr[6] & 1;
2137	}
2138	if (graphic_mode != s->graphic_mode) {
2139	s->graphic_mode = graphic_mode;
2140	full_update = 1;
2141	}
2142	switch(graphic_mode) {
2143	case GMODE_TEXT:
2144	#ifdef VBOX
2145	rc =
2146	#endif /* VBOX */
2147	vga_draw_text(s, full_update);
2148	break;
2149	case GMODE_GRAPH:
2150	#ifdef VBOX
2151	rc =
2152	#endif /* VBOX */
2153	vga_draw_graphic(s, full_update);
2154	break;
2155	case GMODE_BLANK:
2156	default:
2157	vga_draw_blank(s, full_update);
2158	break;
2159	}
2160	}
2161	#ifdef VBOX
2162	return rc;
2163	#endif /* VBOX */
2164	}
2165
2166	/* force a full display refresh */
2167	#ifndef VBOX
2168	void vga_invalidate_display(void)
2169	{
2170	VGAState *s = vga_state;
2171
2172	s->last_width = -1;
2173	s->last_height = -1;
2174	}
2175	#endif /* !VBOX */
2176
2177	#ifndef VBOX /* see vgaR3Reset() */
2178	static void vga_reset(VGAState *s)
2179	{
2180	memset(s, 0, sizeof(VGAState));
2181	s->graphic_mode = -1; /* force full update */
2182	}
2183	#endif /* !VBOX */
2184
2185	#ifndef VBOX
2186	static CPUReadMemoryFunc *vga_mem_read[3] = {
2187	vga_mem_readb,
2188	vga_mem_readw,
2189	vga_mem_readl,
2190	};
2191
2192	static CPUWriteMemoryFunc *vga_mem_write[3] = {
2193	vga_mem_writeb,
2194	vga_mem_writew,
2195	vga_mem_writel,
2196	};
2197	#endif /* !VBOX */
2198
2199	static void vga_save(QEMUFile f, void opaque)
2200	{
2201	VGAState s = (VGAState)opaque;
2202	int i;
2203
2204	qemu_put_be32s(f, &s->latch);
2205	qemu_put_8s(f, &s->sr_index);
2206	qemu_put_buffer(f, s->sr, 8);
2207	qemu_put_8s(f, &s->gr_index);
2208	qemu_put_buffer(f, s->gr, 16);
2209	qemu_put_8s(f, &s->ar_index);
2210	qemu_put_buffer(f, s->ar, 21);
2211	qemu_put_be32s(f, &s->ar_flip_flop);
2212	qemu_put_8s(f, &s->cr_index);
2213	qemu_put_buffer(f, s->cr, 256);
2214	qemu_put_8s(f, &s->msr);
2215	qemu_put_8s(f, &s->fcr);
2216	qemu_put_8s(f, &s->st00);
2217	qemu_put_8s(f, &s->st01);
2218
2219	qemu_put_8s(f, &s->dac_state);
2220	qemu_put_8s(f, &s->dac_sub_index);
2221	qemu_put_8s(f, &s->dac_read_index);
2222	qemu_put_8s(f, &s->dac_write_index);
2223	qemu_put_buffer(f, s->dac_cache, 3);
2224	qemu_put_buffer(f, s->palette, 768);
2225
2226	qemu_put_be32s(f, &s->bank_offset);
2227	#ifdef CONFIG_BOCHS_VBE
2228	qemu_put_byte(f, 1);
2229	qemu_put_be16s(f, &s->vbe_index);
2230	for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2231	qemu_put_be16s(f, &s->vbe_regs[i]);
2232	qemu_put_be32s(f, &s->vbe_start_addr);
2233	qemu_put_be32s(f, &s->vbe_line_offset);
2234	qemu_put_be32s(f, &s->vbe_bank_mask);
2235	#else
2236	qemu_put_byte(f, 0);
2237	#endif
2238	}
2239
2240	static int vga_load(QEMUFile f, void opaque, int version_id)
2241	{
2242	VGAState s = (VGAState)opaque;
2243	int is_vbe, i;
2244
2245	if (version_id != 1)
2246	#ifndef VBOX
2247	return -EINVAL;
2248	#else /* VBOX */
2249	{
2250	Log(("vga_load: version_id=%d - UNKNOWN\n", version_id));
2251	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2252	}
2253	#endif /* VBOX */
2254
2255	qemu_get_be32s(f, &s->latch);
2256	qemu_get_8s(f, &s->sr_index);
2257	qemu_get_buffer(f, s->sr, 8);
2258	qemu_get_8s(f, &s->gr_index);
2259	qemu_get_buffer(f, s->gr, 16);
2260	qemu_get_8s(f, &s->ar_index);
2261	qemu_get_buffer(f, s->ar, 21);
2262	qemu_get_be32s(f, (uint32_t *)&s->ar_flip_flop);
2263	qemu_get_8s(f, &s->cr_index);
2264	qemu_get_buffer(f, s->cr, 256);
2265	qemu_get_8s(f, &s->msr);
2266	qemu_get_8s(f, &s->fcr);
2267	qemu_get_8s(f, &s->st00);
2268	qemu_get_8s(f, &s->st01);
2269
2270	qemu_get_8s(f, &s->dac_state);
2271	qemu_get_8s(f, &s->dac_sub_index);
2272	qemu_get_8s(f, &s->dac_read_index);
2273	qemu_get_8s(f, &s->dac_write_index);
2274	qemu_get_buffer(f, s->dac_cache, 3);
2275	qemu_get_buffer(f, s->palette, 768);
2276
2277	qemu_get_be32s(f, (uint32_t *)&s->bank_offset);
2278	is_vbe = qemu_get_byte(f);
2279	#ifdef CONFIG_BOCHS_VBE
2280	if (!is_vbe)
2281	#ifndef VBOX
2282	return -EINVAL;
2283	#else /* VBOX */
2284	{
2285	Log(("vga_load: !is_vbe !!\n"));
2286	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2287	}
2288	#endif /* VBOX */
2289	qemu_get_be16s(f, &s->vbe_index);
2290	for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2291	qemu_get_be16s(f, &s->vbe_regs[i]);
2292	qemu_get_be32s(f, &s->vbe_start_addr);
2293	qemu_get_be32s(f, &s->vbe_line_offset);
2294	qemu_get_be32s(f, &s->vbe_bank_mask);
2295	#else
2296	if (is_vbe)
2297	#ifndef VBOX
2298	return -EINVAL;
2299	#else /* VBOX */
2300	{
2301	Log(("vga_load: is_vbe !!\n"));
2302	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2303	}
2304	#endif /* VBOX */
2305	#endif
2306
2307	/* force refresh */
2308	s->graphic_mode = -1;
2309	return 0;
2310	}
2311
2312	#ifndef VBOX /* see vgaR3IORegionMap */
2313	static void vga_map(PCIDevice *pci_dev, int region_num,
2314	uint32_t addr, uint32_t size, int type)
2315	{
2316	VGAState *s = vga_state;
2317
2318	cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2319	}
2320	#endif
2321
2322	#ifndef VBOX /* see vgaR3Construct */
2323	void vga_common_init(VGAState s, DisplayState ds, uint8_t *vga_ram_base,
2324	unsigned long vga_ram_offset, int vga_ram_size)
2325	#else
2326	static void vga_init_expand(void)
2327	#endif
2328	{
2329	int i, j, v, b;
2330
2331	for(i = 0;i < 256; i++) {
2332	v = 0;
2333	for(j = 0; j < 8; j++) {
2334	v \|= ((i >> j) & 1) << (j * 4);
2335	}
2336	expand4[i] = v;
2337
2338	v = 0;
2339	for(j = 0; j < 4; j++) {
2340	v \|= ((i >> (2 * j)) & 3) << (j * 4);
2341	}
2342	expand2[i] = v;
2343	}
2344	for(i = 0; i < 16; i++) {
2345	v = 0;
2346	for(j = 0; j < 4; j++) {
2347	b = ((i >> j) & 1);
2348	v \|= b << (2 * j);
2349	v \|= b << (2 * j + 1);
2350	}
2351	expand4to8[i] = v;
2352	}
2353	#ifdef VBOX
2354	}
2355	#else /* !VBOX */
2356	vga_reset(s);
2357
2358	s->vram_ptr = vga_ram_base;
2359	s->vram_offset = vga_ram_offset;
2360	s->vram_size = vga_ram_size;
2361	s->ds = ds;
2362	s->get_bpp = vga_get_bpp;
2363	s->get_offsets = vga_get_offsets;
2364	s->get_resolution = vga_get_resolution;
2365	/* XXX: currently needed for display */
2366	vga_state = s;
2367	}
2368
2369
2370	int vga_initialize(PCIBus bus, DisplayState ds, uint8_t *vga_ram_base,
2371	unsigned long vga_ram_offset, int vga_ram_size)
2372	{
2373	VGAState *s;
2374
2375	s = qemu_mallocz(sizeof(VGAState));
2376	if (!s)
2377	return -1;
2378
2379	vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2380
2381	register_savevm("vga", 0, 1, vga_save, vga_load, s);
2382
2383	register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2384
2385	register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2386	register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2387	register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2388	register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2389
2390	register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2391
2392	register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2393	register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2394	register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2395	register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2396	s->bank_offset = 0;
2397
2398	#ifdef CONFIG_BOCHS_VBE
2399	s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2400	s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2401	#if defined (TARGET_I386)
2402	register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2403	register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2404
2405	register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2406	register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2407
2408	/* old Bochs IO ports */
2409	register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2410	register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2411
2412	register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2413	register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2414	#else
2415	register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2416	register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2417
2418	register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2419	register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2420	#endif
2421	#endif /* CONFIG_BOCHS_VBE */
2422
2423	vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2424	cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2425	vga_io_memory);
2426
2427	if (bus) {
2428	PCIDevice *d;
2429	uint8_t *pci_conf;
2430
2431	d = pci_register_device(bus, "VGA",
2432	sizeof(PCIDevice),
2433	-1, NULL, NULL);
2434	pci_conf = d->config;
2435	pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2436	pci_conf[0x01] = 0x12;
2437	pci_conf[0x02] = 0x11;
2438	pci_conf[0x03] = 0x11;
2439	pci_conf[0x0a] = 0x00; // VGA controller
2440	pci_conf[0x0b] = 0x03;
2441	pci_conf[0x0e] = 0x00; // header_type
2442
2443	/* XXX: vga_ram_size must be a power of two */
2444	pci_register_io_region(d, 0, vga_ram_size,
2445	PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2446	} else {
2447	#ifdef CONFIG_BOCHS_VBE
2448	/* XXX: use optimized standard vga accesses */
2449	cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2450	vga_ram_size, vga_ram_offset);
2451	#endif
2452	}
2453	return 0;
2454	}
2455	#endif /* !VBOX */
2456
2457
2458	#ifndef VBOX
2459	/********************************************************/
2460	/* vga screen dump */
2461
2462	static int vga_save_w, vga_save_h;
2463
2464	static void vga_save_dpy_update(DisplayState *s,
2465	int x, int y, int w, int h)
2466	{
2467	}
2468
2469	static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2470	{
2471	s->linesize = w * 4;
2472	#ifndef VBOX
2473	s->data = qemu_malloc(h * s->linesize);
2474	#else /* VBOX */
2475	if (!s->data)
2476	{
2477	PPDMDEVINS pDevIns = VGASTATE2DEVINS((PVGASTATE)s->pvVgaState);
2478	s->data = PDMDevHlpMMHeapAlloc(pDevIns, h * s->linesize);
2479	}
2480	else // (32-bpp buffer is allocated by the caller)
2481	s->linesize = ((w * 32 + 31) / 32) * 4;
2482	#endif /* VBOX */
2483	vga_save_w = w;
2484	vga_save_h = h;
2485	}
2486
2487	static void vga_save_dpy_refresh(DisplayState *s)
2488	{
2489	}
2490
2491	static int ppm_save(const char filename, uint8_t data,
2492	int w, int h, int linesize)
2493	{
2494	FILE *f;
2495	uint8_t d, d1;
2496	unsigned int v;
2497	int y, x;
2498
2499	f = fopen(filename, "wb");
2500	if (!f)
2501	return -1;
2502	fprintf(f, "P6\n%d %d\n%d\n",
2503	w, h, 255);
2504	d1 = data;
2505	for(y = 0; y < h; y++) {
2506	d = d1;
2507	for(x = 0; x < w; x++) {
2508	v = (uint32_t )d;
2509	fputc((v >> 16) & 0xff, f);
2510	fputc((v >> 8) & 0xff, f);
2511	fputc((v) & 0xff, f);
2512	d += 4;
2513	}
2514	d1 += linesize;
2515	}
2516	fclose(f);
2517	return 0;
2518	}
2519
2520	/* save the vga display in a PPM image even if no display is
2521	available */
2522	void vga_screen_dump(const char *filename)
2523	{
2524	VGAState *s = vga_state;
2525	DisplayState saved_ds, ds1, ds = &ds1;
2526
2527	/* XXX: this is a little hackish */
2528	vga_invalidate_display();
2529	saved_ds = s->ds;
2530
2531	memset(ds, 0, sizeof(DisplayState));
2532	ds->dpy_update = vga_save_dpy_update;
2533	ds->dpy_resize = vga_save_dpy_resize;
2534	ds->dpy_refresh = vga_save_dpy_refresh;
2535	ds->depth = 32;
2536
2537	s->ds = ds;
2538	s->graphic_mode = -1;
2539	vga_update_display();
2540
2541	if (ds->data) {
2542	ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2543	s->ds->linesize);
2544	qemu_free(ds->data);
2545	}
2546	s->ds = saved_ds;
2547	}
2548	#endif /* !VBOX */
2549
2550
2551	#if 0 //def VBOX
2552	/* copy the vga display contents to the given buffer. the size of the buffer
2553	must be sufficient to store the screen copy (see below). the width and height
2554	parameters determine the required dimensions of the copy. If they differ
2555	from the actual screen dimensions, then the returned copy is shrinked or
2556	stretched accordingly. The copy is always a 32-bit image, so the size of
2557	the buffer supplied must be at least (((width * 32 + 31) / 32) * 4) * height,
2558	i.e. dword-aligned. returns zero if the operation was successfull and -1
2559	otherwise. */
2560
2561	static int vga_copy_screen_to(PVGASTATE s, uint8_t *buf, int width, int height)
2562	{
2563	DisplayState saved_ds, ds1, ds = &ds1;
2564	if (!buf \|\| width <= 0 \|\| height <= 0)
2565	return -1;
2566
2567	/* XXX: this is a little hackish */
2568	vga_invalidate_display(s);
2569	saved_ds = s->ds;
2570
2571	memset(ds, 0, sizeof(DisplayState));
2572	ds->dpy_update = vga_save_dpy_update;
2573	ds->dpy_resize = vga_save_dpy_resize;
2574	ds->dpy_refresh = vga_save_dpy_refresh;
2575	ds->depth = 32;
2576	ds->data = buf;
2577	ds->pvVgaState = s;
2578
2579	s->ds = ds;
2580	s->graphic_mode = -1;
2581	vga_update_display(s);
2582
2583	//@@TODO (dmik): implement stretching/shrinking!
2584
2585	s->ds = saved_ds;
2586	return 0;
2587	}
2588
2589	/* copy the given buffer to the vga display. width and height define the
2590	dimensions of the image in the buffer. x and y define the point on the
2591	vga display to copy the image to. the buffer is assumed to contain a 32-bit
2592	image, so the size of one scanline must be ((width * 32 + 31) / 32) * 4),
2593	i.e. dword-aligned. returns zero if the operation was successfull and -1
2594	otherwise. */
2595	static int vga_copy_screen_from(PVGASTATE s, uint8_t *buf, int x, int y, int width, int height)
2596	{
2597	int bpl = ((width * 32 + 31) / 32) * 4;
2598	int linesize = s->ds->linesize;
2599	uint8_t *dst;
2600	uint8_t *src;
2601	int bpp;
2602	vga_draw_line_func *vga_draw_line;
2603
2604	if (!buf \|\| x < 0 \|\| y < 0 \|\| width <= 0 \|\| height <= 0
2605	\|\| x + width > s->ds->width \|\| y + height > s->ds->height)
2606	return -1;
2607
2608	vga_draw_line = vga_draw_line_table[VGA_DRAW_LINE32 * 4 + get_depth_index(s->ds->depth)];
2609	switch (s->ds->depth) {
2610	case 8: bpp = 1; break;
2611	case 15:
2612	case 16: bpp = 2; break;
2613	case 32: bpp = 4; break;
2614	default: return -1;
2615	}
2616
2617	dst = s->ds->data + y * linesize + x * bpp;
2618	src = buf;
2619	for (y = 0; y < height; y ++)
2620	{
2621	vga_draw_line(s, dst, src, width);
2622	dst += linesize;
2623	src += bpl;
2624	}
2625
2626	return 0;
2627	}
2628	#endif
2629
2630	#endif /* !VBOX \|\| !IN_GC \|\| !IN_RING0 */
2631
2632
2633
2634	#ifdef VBOX /* innotek code start */
2635
2636
2637	/* -=-=-=-=-=- all contexts -=-=-=-=-=- */
2638
2639	/**
2640	* Port I/O Handler for VGA OUT operations.
2641	*
2642	* @returns VBox status code.
2643	*
2644	* @param pDevIns The device instance.
2645	* @param pvUser User argument - ignored.
2646	* @param Port Port number used for the IN operation.
2647	* @param u32 The value to output.
2648	* @param cb The value size in bytes.
2649	*/
2650	PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2651	{
2652	NOREF(pvUser);
2653	if (cb == 1)
2654	vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
2655	else if (cb == 2)
2656	{
2657	vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32 & 0xff);
2658	vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1, u32 >> 8);
2659	}
2660	return VINF_SUCCESS;
2661	}
2662
2663
2664	/**
2665	* Port I/O Handler for VGA IN operations.
2666	*
2667	* @returns VBox status code.
2668	*
2669	* @param pDevIns The device instance.
2670	* @param pvUser User argument - ignored.
2671	* @param Port Port number used for the IN operation.
2672	* @param pu32 Where to store the result.
2673	* @param cb Number of bytes read.
2674	*/
2675	PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2676	{
2677	NOREF(pvUser);
2678	if (cb == 1)
2679	{
2680	*pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port);
2681	return VINF_SUCCESS;
2682	}
2683	else if (cb == 2)
2684	{
2685	*pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port)
2686	\| (vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1) << 8);
2687	return VINF_SUCCESS;
2688	}
2689	return VERR_IOM_IOPORT_UNUSED;
2690	}
2691
2692
2693	/**
2694	* Port I/O Handler for VBE OUT operations.
2695	*
2696	* @returns VBox status code.
2697	*
2698	* @param pDevIns The device instance.
2699	* @param pvUser User argument - ignored.
2700	* @param Port Port number used for the IN operation.
2701	* @param u32 The value to output.
2702	* @param cb The value size in bytes.
2703	*/
2704	PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2705	{
2706	VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2707
2708	NOREF(pvUser);
2709
2710	#ifdef IN_GC
2711	/*
2712	* The VBE_DISPI_INDEX_ENABLE has to be done on the host in order to call pfnLFBModeChange callback.
2713	*/
2714	if (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
2715	{
2716	Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE - Switching to host...\n"));
2717	return VINF_IOM_HC_IOPORT_WRITE;
2718	}
2719	#endif
2720	#ifdef VBE_BYTEWISE_IO
2721	if (cb == 1)
2722	{
2723	if (!s->fWriteVBEData)
2724	{
2725	if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
2726	&& (u32 & VBE_DISPI_ENABLED))
2727	{
2728	s->fWriteVBEData = false;
2729	vbe_ioport_write_data(s, Port, u32 & 0xFF);
2730	return VINF_SUCCESS;
2731	}
2732	else
2733	{
2734	s->cbWriteVBEData = u32 & 0xFF;
2735	s->fWriteVBEData = true;
2736	return VINF_SUCCESS;
2737	}
2738	}
2739	else
2740	{
2741	u32 = (s->cbWriteVBEData << 8) \| (u32 & 0xFF);
2742	s->fWriteVBEData = false;
2743	cb = 2;
2744	}
2745	}
2746	#endif
2747	if (cb == 2)
2748	{
2749	//#ifdef IN_GC
2750	// /*
2751	// * The VBE_DISPI_INDEX_ENABLE memsets the entire frame buffer.
2752	// * Since we're not mapping the entire framebuffer any longer that
2753	// * has to be done on the host.
2754	// */
2755	// if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
2756	// && (u32 & VBE_DISPI_ENABLED))
2757	// {
2758	// Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE & VBE_DISPI_ENABLED - Switching to host...\n"));
2759	// return VINF_IOM_HC_IOPORT_WRITE;
2760	// }
2761	//#endif
2762	vbe_ioport_write_data(s, Port, u32);
2763	}
2764	else
2765	AssertMsgFailed(("vgaIOPortWriteVBEData: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
2766	return VINF_SUCCESS;
2767	}
2768
2769
2770	/**
2771	* Port I/O Handler for VBE OUT operations.
2772	*
2773	* @returns VBox status code.
2774	*
2775	* @param pDevIns The device instance.
2776	* @param pvUser User argument - ignored.
2777	* @param Port Port number used for the IN operation.
2778	* @param u32 The value to output.
2779	* @param cb The value size in bytes.
2780	*/
2781	PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2782	{
2783	NOREF(pvUser);
2784	#ifdef VBE_BYTEWISE_IO
2785	if (cb == 1)
2786	{
2787	VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2788	if (!s->fWriteVBEIndex)
2789	{
2790	s->cbWriteVBEIndex = u32 & 0x00FF;
2791	s->fWriteVBEIndex = true;
2792	return VINF_SUCCESS;
2793	}
2794	else
2795	{
2796	s->fWriteVBEIndex = false;
2797	vbe_ioport_write_index(s, Port, (s->cbWriteVBEIndex << 8) \| (u32 & 0x00FF));
2798	return VINF_SUCCESS;
2799	}
2800	}
2801	else
2802	#endif
2803	if (cb == 2)
2804	vbe_ioport_write_index(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
2805	else
2806	AssertMsgFailed(("vgaIOPortWriteVBEIndex: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
2807	return VINF_SUCCESS;
2808	}
2809
2810
2811	/**
2812	* Port I/O Handler for VBE IN operations.
2813	*
2814	* @returns VBox status code.
2815	*
2816	* @param pDevIns The device instance.
2817	* @param pvUser User argument - ignored.
2818	* @param Port Port number used for the IN operation.
2819	* @param pu32 Where to store the result.
2820	* @param cb Number of bytes to read.
2821	*/
2822	PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2823	{
2824	NOREF(pvUser);
2825	#ifdef VBE_BYTEWISE_IO
2826	if (cb == 1)
2827	{
2828	VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2829
2830	if (!s->fReadVBEData)
2831	{
2832	*pu32 = (vbe_ioport_read_data(s, Port) >> 8) & 0xFF;
2833	s->fReadVBEData = true;
2834	return VINF_SUCCESS;
2835	}
2836	else
2837	{
2838	*pu32 = vbe_ioport_read_data(s, Port) & 0xFF;
2839	s->fReadVBEData = false;
2840	return VINF_SUCCESS;
2841	}
2842	}
2843	else
2844	#endif
2845	if (cb == 2)
2846	{
2847	*pu32 = vbe_ioport_read_data(PDMINS2DATA(pDevIns, PVGASTATE), Port);
2848	return VINF_SUCCESS;
2849	}
2850	else if (cb == 4)
2851	{
2852	/* Quick hack for getting the vram size. */
2853	VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2854	*pu32 = s->vram_size;
2855	return VINF_SUCCESS;
2856	}
2857	AssertMsgFailed(("vgaIOPortReadVBEData: Port=%#x cb=%d\n", Port, cb));
2858	return VERR_IOM_IOPORT_UNUSED;
2859	}
2860
2861
2862	/**
2863	* Port I/O Handler for VBE IN operations.
2864	*
2865	* @returns VBox status code.
2866	*
2867	* @param pDevIns The device instance.
2868	* @param pvUser User argument - ignored.
2869	* @param Port Port number used for the IN operation.
2870	* @param pu32 Where to store the result.
2871	* @param cb Number of bytes to read.
2872	*/
2873	PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
2874	{
2875	NOREF(pvUser);
2876	#ifdef VBE_BYTEWISE_IO
2877	if (cb == 1)
2878	{
2879	VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2880
2881	if (!s->fReadVBEIndex)
2882	{
2883	*pu32 = (vbe_ioport_read_index(s, Port) >> 8) & 0xFF;
2884	s->fReadVBEIndex = true;
2885	return VINF_SUCCESS;
2886	}
2887	else
2888	{
2889	*pu32 = vbe_ioport_read_index(s, Port) & 0xFF;
2890	s->fReadVBEIndex = false;
2891	return VINF_SUCCESS;
2892	}
2893	}
2894	else
2895	#endif
2896	if (cb == 2)
2897	{
2898	*pu32 = vbe_ioport_read_index(PDMINS2DATA(pDevIns, PVGASTATE), Port);
2899	return VINF_SUCCESS;
2900	}
2901	AssertMsgFailed(("vgaIOPortReadVBEIndex: Port=%#x cb=%d\n", Port, cb));
2902	return VERR_IOM_IOPORT_UNUSED;
2903	}
2904
2905
2906
2907
2908
2909	/* -=-=-=-=-=- Guest Context -=-=-=-=-=- */
2910
2911	/*
2912	* Internal. For use inside VGAGCMemoryFillWrite only.
2913	* Macro for apply logical operation and bit mask.
2914	*/
2915	#define APPLY_LOGICAL_AND_MASK(s, val, bit_mask) \
2916	/* apply logical operation */ \
2917	switch(s->gr[3] >> 3) \
2918	{ \
2919	case 0: \
2920	default: \
2921	/* nothing to do */ \
2922	break; \
2923	case 1: \
2924	/* and */ \
2925	val &= s->latch; \
2926	break; \
2927	case 2: \
2928	/* or */ \
2929	val \|= s->latch; \
2930	break; \
2931	case 3: \
2932	/* xor */ \
2933	val ^= s->latch; \
2934	break; \
2935	} \
2936	/* apply bit mask */ \
2937	val = (val & bit_mask) \| (s->latch & ~bit_mask)
2938
2939	/**
2940	* Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM and from the inside of VGADeviceGC.cpp.
2941	* This is the advanced version of vga_mem_writeb function.
2942	*
2943	* @returns VBox status code.
2944	* @param pDevIns Pointer device instance.
2945	* @param pvUser User argument - ignored.
2946	* @param GCPhysAddr Physical address of memory to write.
2947	* @param u32Item Data to write, up to 4 bytes.
2948	* @param cbItem Size of data Item, only 1/2/4 bytes is allowed for now.
2949	* @param cItems Number of data items to write.
2950	*/
2951	PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems)
2952	{
2953	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
2954	uint32_t b;
2955	uint32_t write_mask, bit_mask, set_mask;
2956	uint32_t aVal[4]; /** @todo r=bird: Why is this an 32-bit array? */
2957	unsigned i;
2958	NOREF(pvUser);
2959	for (i = 0; i < cbItem; i++)
2960	{
2961	aVal[i] = u32Item & 0xff;
2962	u32Item >>= 8;
2963	}
2964
2965	/* convert to VGA memory offset */
2966	/// @todo add check for the end of region
2967	GCPhysAddr &= 0x1ffff;
2968	switch((pData->gr[6] >> 2) & 3) {
2969	case 0:
2970	break;
2971	case 1:
2972	if (GCPhysAddr >= 0x10000)
2973	return VINF_SUCCESS;
2974	GCPhysAddr += pData->bank_offset;
2975	break;
2976	case 2:
2977	GCPhysAddr -= 0x10000;
2978	if (GCPhysAddr >= 0x8000)
2979	return VINF_SUCCESS;
2980	break;
2981	default:
2982	case 3:
2983	GCPhysAddr -= 0x18000;
2984	if (GCPhysAddr >= 0x8000)
2985	return VINF_SUCCESS;
2986	break;
2987	}
2988
2989	if (pData->sr[4] & 0x08) {
2990	/* chain 4 mode : simplest access */
2991	#ifdef IN_GC
2992	if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
2993	return VINF_IOM_HC_MMIO_WRITE;
2994	#else
2995	if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
2996	{
2997	AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
2998	return VINF_SUCCESS;
2999	}
3000	#endif
3001
3002	while (cItems-- > 0)
3003	for (i = 0; i < cbItem; i++)
3004	{
3005	if (pData->sr[2] & (1 << (GCPhysAddr & 3)))
3006	{
3007	CTXSUFF(pData->vram_ptr)[GCPhysAddr] = aVal[i];
3008	vga_set_dirty(pData, GCPhysAddr);
3009	}
3010	GCPhysAddr++;
3011	}
3012	} else if (pData->gr[5] & 0x10) {
3013	/* odd/even mode (aka text mode mapping) */
3014	#ifdef IN_GC
3015	if (GCPhysAddr * 2 + cItems * cbItem >= VGA_MAPPING_SIZE)
3016	return VINF_IOM_HC_MMIO_WRITE;
3017	#else
3018	if (GCPhysAddr * 2 + cItems * cbItem >= pData->vram_size)
3019	{
3020	AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3021	return VINF_SUCCESS;
3022	}
3023	#endif
3024	while (cItems-- > 0)
3025	for (i = 0; i < cbItem; i++)
3026	{
3027	unsigned plane = (pData->gr[4] & 2) \| (GCPhysAddr & 1);
3028	if (pData->sr[2] & (1 << plane)) {
3029	RTGCPHYS PhysAddr2 = ((GCPhysAddr & ~1) << 1) \| plane;
3030	CTXSUFF(pData->vram_ptr)[PhysAddr2] = aVal[i];
3031	vga_set_dirty(pData, PhysAddr2);
3032	}
3033	GCPhysAddr++;
3034	}
3035	} else {
3036	#ifdef IN_GC
3037	if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
3038	return VINF_IOM_HC_MMIO_WRITE;
3039	#else
3040	if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
3041	{
3042	AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3043	return VINF_SUCCESS;
3044	}
3045	#endif
3046
3047	/* standard VGA latched access */
3048	switch(pData->gr[5] & 3) {
3049	default:
3050	case 0:
3051	/* rotate */
3052	b = pData->gr[3] & 7;
3053	bit_mask = pData->gr[8];
3054	bit_mask \|= bit_mask << 8;
3055	bit_mask \|= bit_mask << 16;
3056	set_mask = mask16[pData->gr[1]];
3057
3058	for (i = 0; i < cbItem; i++)
3059	{
3060	aVal[i] = ((aVal[i] >> b) \| (aVal[i] << (8 - b))) & 0xff;
3061	aVal[i] \|= aVal[i] << 8;
3062	aVal[i] \|= aVal[i] << 16;
3063
3064	/* apply set/reset mask */
3065	aVal[i] = (aVal[i] & ~set_mask) \| (mask16[pData->gr[0]] & set_mask);
3066
3067	APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3068	}
3069	break;
3070	case 1:
3071	for (i = 0; i < cbItem; i++)
3072	aVal[i] = pData->latch;
3073	break;
3074	case 2:
3075	bit_mask = pData->gr[8];
3076	bit_mask \|= bit_mask << 8;
3077	bit_mask \|= bit_mask << 16;
3078	for (i = 0; i < cbItem; i++)
3079	{
3080	aVal[i] = mask16[aVal[i] & 0x0f];
3081
3082	APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3083	}
3084	break;
3085	case 3:
3086	/* rotate */
3087	b = pData->gr[3] & 7;
3088
3089	for (i = 0; i < cbItem; i++)
3090	{
3091	aVal[i] = (aVal[i] >> b) \| (aVal[i] << (8 - b));
3092	bit_mask = pData->gr[8] & aVal[i];
3093	bit_mask \|= bit_mask << 8;
3094	bit_mask \|= bit_mask << 16;
3095	aVal[i] = mask16[pData->gr[0]];
3096
3097	APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3098	}
3099	break;
3100	}
3101
3102	/* mask data according to sr[2] */
3103	write_mask = mask16[pData->sr[2]];
3104
3105	/* actually write data */
3106	if (cbItem == 1)
3107	{
3108	/* The most frequently case is 1 byte I/O. */
3109	while (cItems-- > 0)
3110	{
3111	((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3112	vga_set_dirty(pData, GCPhysAddr << 2);
3113	GCPhysAddr++;
3114	}
3115	}
3116	else if (cbItem == 2)
3117	{
3118	/* The second case is 2 bytes I/O. */
3119	while (cItems-- > 0)
3120	{
3121	((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3122	vga_set_dirty(pData, GCPhysAddr << 2);
3123	GCPhysAddr++;
3124
3125	((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) \| (aVal[1] & write_mask);
3126	vga_set_dirty(pData, GCPhysAddr << 2);
3127	GCPhysAddr++;
3128	}
3129	}
3130	else
3131	{
3132	/* And the rest is 4 bytes. */
3133	Assert(cbItem == 4);
3134	while (cItems-- > 0)
3135	for (i = 0; i < cbItem; i++)
3136	{
3137	((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t )pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) \| (aVal[i] & write_mask);
3138	vga_set_dirty(pData, GCPhysAddr << 2);
3139	GCPhysAddr++;
3140	}
3141	}
3142	}
3143	return VINF_SUCCESS;
3144	}
3145	#undef APPLY_LOGICAL_AND_MASK
3146
3147
3148	/**
3149	* Legacy VGA memory (0xa0000 - 0xbffff) read hook, to be called from IOM.
3150	*
3151	* @returns VBox status code.
3152	* @param pDevIns Pointer device instance.
3153	* @param pvUser User argument - ignored.
3154	* @param GCPhysAddr Physical address of memory to read.
3155	* @param pv Where to store readed data.
3156	* @param cb Bytes to read.
3157	*/
3158	PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3159	{
3160	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3161	STAM_PROFILE_START(&pData->StatGCMemoryRead, a);
3162	NOREF(pvUser);
3163	switch (cb)
3164	{
3165	case 1:
3166	(uint8_t )pv = vga_mem_readb(pData, GCPhysAddr); break;
3167	case 2:
3168	(uint16_t )pv = vga_mem_readb(pData, GCPhysAddr)
3169	\| (vga_mem_readb(pData, GCPhysAddr + 1) << 8);
3170	break;
3171	case 4:
3172	(uint32_t )pv = vga_mem_readb(pData, GCPhysAddr)
3173	\| (vga_mem_readb(pData, GCPhysAddr + 1) << 8)
3174	\| (vga_mem_readb(pData, GCPhysAddr + 2) << 16)
3175	\| (vga_mem_readb(pData, GCPhysAddr + 3) << 24);
3176	break;
3177
3178	default:
3179	{
3180	uint8_t pu8Data = (uint8_t )pv;
3181	while (cb-- > 0)
3182	*pu8Data++ = vga_mem_readb(pData, GCPhysAddr++);
3183	}
3184	}
3185	STAM_PROFILE_STOP(&pData->StatGCMemoryRead, a);
3186	return VINF_SUCCESS;
3187	}
3188
3189	/**
3190	* Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM.
3191	*
3192	* @returns VBox status code.
3193	* @param pDevIns Pointer device instance.
3194	* @param pvUser User argument - ignored.
3195	* @param GCPhysAddr Physical address of memory to write.
3196	* @param pv Pointer to data.
3197	* @param cb Bytes to write.
3198	*/
3199	PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3200	{
3201	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3202	uint8_t pu8 = (uint8_t )pv;
3203	int rc = VINF_SUCCESS;
3204	STAM_PROFILE_START(&pData->StatGCMemoryWrite, a);
3205
3206	switch (cb)
3207	{
3208	case 1:
3209	rc = vga_mem_writeb(pData, GCPhysAddr, *pu8);
3210	break;
3211	#if 1
3212	case 2:
3213	rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3214	if (RT_LIKELY(rc == VINF_SUCCESS))
3215	rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3216	break;
3217	case 4:
3218	rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3219	if (RT_LIKELY(rc == VINF_SUCCESS))
3220	rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3221	if (RT_LIKELY(rc == VINF_SUCCESS))
3222	rc = vga_mem_writeb(pData, GCPhysAddr + 2, pu8[2]);
3223	if (RT_LIKELY(rc == VINF_SUCCESS))
3224	rc = vga_mem_writeb(pData, GCPhysAddr + 3, pu8[3]);
3225	break;
3226	#else
3227	case 2:
3228	rc = vgaMMIOFill(pDevIns, GCPhysAddr, (uint16_t )pv, 2, 1);
3229	break;
3230	case 4:
3231	rc = vgaMMIOFill(pDevIns, GCPhysAddr, (uint32_t )pv, 4, 1);
3232	break;
3233	#endif
3234	default:
3235	while (cb-- > 0 && rc == VINF_SUCCESS)
3236	rc = vga_mem_writeb(pData, GCPhysAddr++, *pu8++);
3237	break;
3238
3239	}
3240	STAM_PROFILE_STOP(&pData->StatGCMemoryWrite, a);
3241	return rc;
3242	}
3243
3244
3245	/**
3246	* Handle LFB access.
3247	* @returns VBox status code.
3248	* @param pVM VM handle.
3249	* @param pData VGA device instance data.
3250	* @param GCPhys The access physical address.
3251	* @param GCPtr The access virtual address (only GC).
3252	*/
3253	static int vgaLFBAccess(PVM pVM, PVGASTATE pData, RTGCPHYS GCPhys, RTGCPTR GCPtr)
3254	{
3255	int rc;
3256
3257	/*
3258	* Set page dirty bit.
3259	*/
3260	vga_set_dirty(pData, GCPhys - pData->GCPhysVRAM);
3261	pData->fLFBUpdated = true;
3262
3263	/*
3264	* Turn of the write handler for this particular page and make it R/W.
3265	* Then return telling the caller to restart the guest instruction.
3266	* ASSUME: the guest always maps video memory RW.
3267	*/
3268	rc = PGMHandlerPhysicalPageTempOff(pVM, pData->GCPhysVRAM, GCPhys);
3269	if (VBOX_SUCCESS(rc))
3270	{
3271	#ifndef IN_RING3
3272	rc = PGMShwModifyPage(pVM, GCPtr, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
3273	if (VBOX_SUCCESS(rc))
3274	return VINF_SUCCESS;
3275	else
3276	AssertMsgFailed(("PGMShwModifyPage -> rc=%d\n", rc));
3277	#else /* IN_RING3 : We don't have any virtual page address of the access here. */
3278	Assert(GCPtr == 0);
3279	return VINF_SUCCESS;
3280	#endif
3281	}
3282	else
3283	AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", rc));
3284
3285	return rc;
3286	}
3287
3288
3289	#ifdef IN_GC
3290	/**
3291	* #PF Handler for VBE LFB access.
3292	*
3293	* @returns VBox status code (appropriate for GC return).
3294	* @param pVM VM Handle.
3295	* @param uErrorCode CPU Error code.
3296	* @param pRegFrame Trap register frame.
3297	* @param pvFault The fault address (cr2).
3298	* @param GCPhysFault The GC physical address corresponding to pvFault.
3299	* @param pvUser User argument, ignored.
3300	*/
3301	PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3302	{
3303	PVGASTATE pData = (PVGASTATE)pvUser;
3304	Assert(pData);
3305	Assert(GCPhysFault >= pData->GCPhysVRAM);
3306	AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3307
3308	return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3309	}
3310
3311	#elif IN_RING0
3312
3313	/**
3314	* #PF Handler for VBE LFB access.
3315	*
3316	* @returns VBox status code (appropriate for GC return).
3317	* @param pVM VM Handle.
3318	* @param uErrorCode CPU Error code.
3319	* @param pRegFrame Trap register frame.
3320	* @param pvFault The fault address (cr2).
3321	* @param GCPhysFault The GC physical address corresponding to pvFault.
3322	* @param pvUser User argument, ignored.
3323	*/
3324	PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3325	{
3326	PVGASTATE pData = (PVGASTATE)pvUser;
3327	Assert(pData);
3328	Assert(GCPhysFault >= pData->GCPhysVRAM);
3329	AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3330
3331	return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3332	}
3333
3334	#else /* IN_RING3 */
3335
3336	/**
3337	* HC access handler for the LFB.
3338	*
3339	* @returns VINF_SUCCESS if the handler have carried out the operation.
3340	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3341	* @param pVM VM Handle.
3342	* @param GCPhys The physical address the guest is writing to.
3343	* @param pvPhys The HC mapping of that address.
3344	* @param pvBuf What the guest is reading/writing.
3345	* @param cbBuf How much it's reading/writing.
3346	* @param enmAccessType The access type.
3347	* @param pvUser User argument.
3348	*/
3349	static DECLCALLBACK(int) vgaR3LFBAccessHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
3350	{
3351	PVGASTATE pData = (PVGASTATE)pvUser;
3352	int rc;
3353	Assert(pData);
3354	Assert(GCPhys >= pData->GCPhysVRAM);
3355	rc = vgaLFBAccess(pVM, pData, GCPhys, 0);
3356	if (VBOX_SUCCESS(rc))
3357	return VINF_PGM_HANDLER_DO_DEFAULT;
3358	AssertMsg(rc <= VINF_SUCCESS, ("rc=%Vrc\n", rc));
3359	return rc;
3360	}
3361	#endif /* IN_RING3 */
3362
3363
3364	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3365
3366	#ifdef IN_RING3
3367
3368	# ifdef VBE_NEW_DYN_LIST
3369	/**
3370	* Port I/O Handler for VBE Extra OUT operations.
3371	*
3372	* @returns VBox status code.
3373	*
3374	* @param pDevIns The device instance.
3375	* @param pvUser User argument - ignored.
3376	* @param Port Port number used for the IN operation.
3377	* @param u32 The value to output.
3378	* @param cb The value size in bytes.
3379	*/
3380	PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3381	{
3382	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3383	NOREF(pvUser);
3384	NOREF(Port);
3385
3386	if (cb == 2)
3387	{
3388	Log(("vbeIOPortWriteVBEExtra: addr=%#RX32\n", u32));
3389	pData->u16VBEExtraAddress = u32;
3390	return VINF_SUCCESS;
3391	}
3392
3393	Log(("vbeIOPortWriteVBEExtra: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
3394	return VINF_SUCCESS;
3395	}
3396
3397
3398	/**
3399	* Port I/O Handler for VBE Extra IN operations.
3400	*
3401	* @returns VBox status code.
3402	*
3403	* @param pDevIns The device instance.
3404	* @param pvUser User argument - ignored.
3405	* @param Port Port number used for the IN operation.
3406	* @param pu32 Where to store the result.
3407	* @param cb Number of bytes read.
3408	*/
3409	PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
3410	{
3411	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3412	NOREF(pvUser);
3413	NOREF(Port);
3414
3415	if (pData->u16VBEExtraAddress == 0xffff)
3416	{
3417	Log(("vbeIOPortReadVBEExtra: Requested number of 64k video banks\n"));
3418	*pu32 = pData->vram_size / _64K;
3419	return VINF_SUCCESS;
3420	}
3421
3422	if ( pData->u16VBEExtraAddress >= pData->cbVBEExtraData
3423	\|\| pData->u16VBEExtraAddress + cb > pData->cbVBEExtraData)
3424	{
3425	*pu32 = 0;
3426	Log(("vbeIOPortReadVBEExtra: Requested address is out of VBE data!!! Address=%#x(%d) cbVBEExtraData=%#x(%d)\n",
3427	pData->u16VBEExtraAddress, pData->u16VBEExtraAddress, pData->cbVBEExtraData, pData->cbVBEExtraData));
3428	return VINF_SUCCESS;
3429	}
3430
3431	if (cb == 1)
3432	{
3433	*pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress] & 0xFF;
3434
3435	Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3436	return VINF_SUCCESS;
3437	}
3438
3439	if (cb == 2)
3440	{
3441	*pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress]
3442	\| pData->pu8VBEExtraData[pData->u16VBEExtraAddress + 1] << 8;
3443
3444	Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3445	return VINF_SUCCESS;
3446	}
3447	Log(("vbeIOPortReadVBEExtra: Invalid cb=%d read from the VBE Extra port!!!\n", cb));
3448	return VERR_IOM_IOPORT_UNUSED;
3449	}
3450	# endif /* VBE_NEW_DYN_LIST */
3451
3452
3453
3454
3455	/* -=-=-=-=-=- Ring 3: VGA BIOS I/Os -=-=-=-=-=- */
3456
3457	/**
3458	* Port I/O Handler for VGA BIOS IN operations.
3459	*
3460	* @returns VBox status code.
3461	*
3462	* @param pDevIns The device instance.
3463	* @param pvUser User argument - ignored.
3464	* @param Port Port number used for the IN operation.
3465	* @param pu32 Where to store the result.
3466	* @param cb Number of bytes read.
3467	*/
3468	static DECLCALLBACK(int) vgaIOPortReadBIOS(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
3469	{
3470	NOREF(pDevIns);
3471	NOREF(pvUser);
3472	NOREF(Port);
3473	NOREF(pu32);
3474	NOREF(cb);
3475	return VERR_IOM_IOPORT_UNUSED;
3476	}
3477
3478	/**
3479	* Port I/O Handler for VGA BIOS OUT operations.
3480	*
3481	* @returns VBox status code.
3482	*
3483	* @param pDevIns The device instance.
3484	* @param pvUser User argument - ignored.
3485	* @param Port Port number used for the IN operation.
3486	* @param u32 The value to output.
3487	* @param cb The value size in bytes.
3488	*/
3489	static DECLCALLBACK(int) vgaIOPortWriteBIOS(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3490	{
3491	static int lastWasNotNewline = 0; /* We are only called in a single-threaded way */
3492	/*
3493	* VGA BIOS char printing.
3494	*/
3495	if ( cb == 1
3496	&& Port == VBE_PRINTF_PORT)
3497	{
3498	#if 0
3499	switch (u32)
3500	{
3501	case '\r': Log(("vgabios: <return>\n")); break;
3502	case '\n': Log(("vgabios: <newline>\n")); break;
3503	case '\t': Log(("vgabios: <tab>\n")); break;
3504	default:
3505	Log(("vgabios: %c\n", u32));
3506	}
3507	#else
3508	if (lastWasNotNewline == 0)
3509	Log(("vgabios: "));
3510	if (u32 != '\r') /* return - is only sent in conjunction with '\n' */
3511	Log(("%c", u32));
3512	if (u32 == '\n')
3513	lastWasNotNewline = 0;
3514	else
3515	lastWasNotNewline = 1;
3516	#endif
3517	return VINF_SUCCESS;
3518	}
3519
3520	/* not in use. */
3521	return VINF_SUCCESS;
3522	}
3523
3524
3525	/* -=-=-=-=-=- Ring 3: IBase -=-=-=-=-=- */
3526
3527	/**
3528	* Queries an interface to the driver.
3529	*
3530	* @returns Pointer to interface.
3531	* @returns NULL if the interface was not supported by the driver.
3532	* @param pInterface Pointer to this interface structure.
3533	* @param enmInterface The requested interface identification.
3534	* @thread Any thread.
3535	*/
3536	static DECLCALLBACK(void *) vgaPortQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
3537	{
3538	PVGASTATE pData = (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Base));
3539	switch (enmInterface)
3540	{
3541	case PDMINTERFACE_BASE:
3542	return &pData->Base;
3543	case PDMINTERFACE_DISPLAY_PORT:
3544	return &pData->Port;
3545	default:
3546	return NULL;
3547	}
3548	}
3549
3550
3551	/* -=-=-=-=-=- Ring 3: Dummy IDisplayConnector -=-=-=-=-=- */
3552
3553	/**
3554	* Resize the display.
3555	* This is called when the resolution changes. This usually happens on
3556	* request from the guest os, but may also happen as the result of a reset.
3557	*
3558	* @param pInterface Pointer to this interface.
3559	* @param cx New display width.
3560	* @param cy New display height
3561	* @thread The emulation thread.
3562	*/
3563	static DECLCALLBACK(int) vgaDummyResize(PPDMIDISPLAYCONNECTOR pInterface, uint32_t bpp, void *pvVRAM, uint32_t cbLine, uint32_t cx, uint32_t cy)
3564	{
3565	return VINF_SUCCESS;
3566	}
3567
3568
3569	/**
3570	* Update a rectangle of the display.
3571	* PDMIDISPLAYPORT::pfnUpdateDisplay is the caller.
3572	*
3573	* @param pInterface Pointer to this interface.
3574	* @param x The upper left corner x coordinate of the rectangle.
3575	* @param y The upper left corner y coordinate of the rectangle.
3576	* @param cx The width of the rectangle.
3577	* @param cy The height of the rectangle.
3578	* @thread The emulation thread.
3579	*/
3580	static DECLCALLBACK(void) vgaDummyUpdateRect(PPDMIDISPLAYCONNECTOR pInterface, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
3581	{
3582	}
3583
3584
3585	/**
3586	* Refresh the display.
3587	*
3588	* The interval between these calls is set by
3589	* PDMIDISPLAYPORT::pfnSetRefreshRate(). The driver should call
3590	* PDMIDISPLAYPORT::pfnUpdateDisplay() if it wishes to refresh the
3591	* display. PDMIDISPLAYPORT::pfnUpdateDisplay calls pfnUpdateRect with
3592	* the changed rectangles.
3593	*
3594	* @param pInterface Pointer to this interface.
3595	* @thread The emulation thread.
3596	*/
3597	static DECLCALLBACK(void) vgaDummyRefresh(PPDMIDISPLAYCONNECTOR pInterface)
3598	{
3599	}
3600
3601
3602	/* -=-=-=-=-=- Ring 3: IDisplayPort -=-=-=-=-=- */
3603
3604	/** Converts a display port interface pointer to a vga state pointer. */
3605	#define IDISPLAYPORT_2_VGASTATE(pInterface) ( (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Port)) )
3606
3607
3608	/**
3609	* Update the display with any changed regions.
3610	*
3611	* @param pInterface Pointer to this interface.
3612	* @see PDMIKEYBOARDPORT::pfnUpdateDisplay() for details.
3613	*/
3614	static DECLCALLBACK(int) vgaPortUpdateDisplay(PPDMIDISPLAYPORT pInterface)
3615	{
3616	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3617	PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
3618
3619	#ifdef DEBUG_sunlover
3620	LogFlow(("vgaPortUpdateDisplay\n"));
3621	#endif /* DEBUG_sunlover */
3622
3623	/* This should be called only in non VBVA mode. */
3624
3625	int rc = vga_update_display(pData);
3626	if (rc != VINF_SUCCESS)
3627	return rc;
3628
3629	if (pData->fHaveDirtyBits)
3630	{
3631	PPDMDEVINS pDevIns = pData->pDevInsHC;
3632	PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
3633	pData->fHaveDirtyBits = false;
3634	}
3635
3636	return VINF_SUCCESS;
3637	}
3638
3639
3640	/**
3641	* Update the entire display.
3642	*
3643	* @param pInterface Pointer to this interface.
3644	* @see PDMIKEYBOARDPORT::pfnUpdateDisplayAll() for details.
3645	*/
3646	static DECLCALLBACK(int) vgaPortUpdateDisplayAll(PPDMIDISPLAYPORT pInterface)
3647	{
3648	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3649	PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
3650
3651	/* This is called both in VBVA mode and normal modes. */
3652
3653	#ifdef DEBUG_sunlover
3654	LogFlow(("vgaPortUpdateDisplayAll\n"));
3655	#endif /* DEBUG_sunlover */
3656
3657	pData->graphic_mode = -1; /* force full update */
3658	return vga_update_display(pData);
3659	}
3660
3661
3662	/**
3663	* Sets the refresh rate and restart the timer.
3664	*
3665	* @returns VBox status code.
3666	* @param pInterface Pointer to this interface.
3667	* @param cMilliesInterval Number of millies between two refreshes.
3668	* @see PDMIKEYBOARDPORT::pfnSetRefreshRate() for details.
3669	*/
3670	static DECLCALLBACK(int) vgaPortSetRefreshRate(PPDMIDISPLAYPORT pInterface, uint32_t cMilliesInterval)
3671	{
3672	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3673
3674	pData->cMilliesRefreshInterval = cMilliesInterval;
3675	if (cMilliesInterval)
3676	return TMTimerSetMillies(pData->RefreshTimer, cMilliesInterval);
3677	return TMTimerStop(pData->RefreshTimer);
3678	}
3679
3680
3681	/** @copydoc PDMIDISPLAYPORT::pfnQueryColorDepth */
3682	static DECLCALLBACK(int) vgaPortQueryColorDepth(PPDMIDISPLAYPORT pInterface, uint32_t *pcBits)
3683	{
3684	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3685
3686	if (!pcBits)
3687	return VERR_INVALID_PARAMETER;
3688	*pcBits = vga_get_bpp(pData);
3689	return VINF_SUCCESS;
3690	}
3691
3692
3693	/**
3694	* Create a 32-bbp snapshot of the display.
3695	*
3696	* @param pInterface Pointer to this interface.
3697	* @param pvData Pointer the buffer to copy the bits to.
3698	* @param cbData Size of the buffer.
3699	* @param pcx Where to store the width of the bitmap. (optional)
3700	* @param pcy Where to store the height of the bitmap. (optional)
3701	* @param pcbData Where to store the actual size of the bitmap. (optional)
3702	* @see PDMIKEYBOARDPORT::pfnSnapshot() for details.
3703	*/
3704	static DECLCALLBACK(int) vgaPortSnapshot(PPDMIDISPLAYPORT pInterface, void pvData, size_t cbData, uint32_t pcx, uint32_t pcy, size_t pcbData)
3705	{
3706	/* @todo r=sunlover: replace the method with a direct VRAM rendering like in vgaPortUpdateDisplayRect. */
3707	PPDMIDISPLAYCONNECTOR pConnector;
3708	PDMIDISPLAYCONNECTOR Connector;
3709	int32_t graphic_mode;
3710	uint32_t fRenderVRAM;
3711	size_t cbRequired;
3712	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3713	PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
3714	LogFlow(("vgaPortSnapshot: pvData=%p cbData=%d pcx=%p pcy=%p pcbData=%p\n", pvData, cbData, pcx, pcy, pcbData));
3715
3716	/*
3717	* Validate input.
3718	*/
3719	if (!pvData)
3720	return VERR_INVALID_PARAMETER;
3721
3722	/*
3723	* Do a regular refresh first to resolve any pending resize issues.
3724	*
3725	* 20060317 It used to be pfnUpdateDisplay, but by VBVA design
3726	* only pfnUpdateDisplayAll is allowed to be called in VBVA mode.
3727	* Also since the goal here is to have updated display for screenshot,
3728	* the UpdateDisplayAll is even more logical to call. (sunlover)
3729	*/
3730	pInterface->pfnUpdateDisplayAll(pInterface);
3731
3732	/*
3733	* Validate the buffer size.
3734	*/
3735	cbRequired = RT_ALIGN_Z(pData->last_scr_width, 4) * pData->last_scr_height * 4;
3736	if (cbRequired > cbData)
3737	{
3738	Log(("vgaPortSnapshot: %d bytes are required, a buffer of %d bytes is profiled.\n", cbRequired, cbData));
3739	return VERR_BUFFER_OVERFLOW;
3740	}
3741
3742	/*
3743	* Temporarily replace the display connector interface with a fake one.
3744	*/
3745	Connector.pu8Data = (uint8_t*)pvData;
3746	Connector.cBits = 32;
3747	Connector.cx = pData->pDrv->cx;
3748	Connector.cy = pData->pDrv->cy;
3749	Connector.cbScanline = RT_ALIGN_32(Connector.cx, 4) * 4;
3750	Connector.pfnRefresh = vgaDummyRefresh;
3751	Connector.pfnResize = vgaDummyResize;
3752	Connector.pfnUpdateRect = vgaDummyUpdateRect;
3753
3754	/* save & replace state data. */
3755	pConnector = pData->pDrv;
3756	pData->pDrv = &Connector;
3757	graphic_mode = pData->graphic_mode;
3758	pData->graphic_mode = -1; /* force a full refresh. */
3759	fRenderVRAM = pData->fRenderVRAM;
3760	pData->fRenderVRAM = 1; /* force the guest VRAM rendering to the given buffer. */
3761
3762	/* make the snapshot. */
3763	int rc = vga_update_display(pData);
3764
3765	/* restore */
3766	pData->pDrv = pConnector;
3767	pData->graphic_mode = graphic_mode;
3768	pData->fRenderVRAM = fRenderVRAM;
3769
3770	if (rc != VINF_SUCCESS)
3771	return rc;
3772
3773	/*
3774	* Return the result.
3775	*/
3776	if (pcx)
3777	*pcx = Connector.cx;
3778	if (pcy)
3779	*pcy = Connector.cy;
3780	if (pcbData)
3781	*pcbData = cbRequired;
3782	LogFlow(("vgaPortSnapshot: returns VINF_SUCCESS (cx=%d cy=%d cbData=%d)\n", Connector.cx, Connector.cy, cbRequired));
3783	return VINF_SUCCESS;
3784	}
3785
3786
3787	/**
3788	* Copy bitmap to the display.
3789	*
3790	* @param pInterface Pointer to this interface.
3791	* @param pvData Pointer to the bitmap bits.
3792	* @param x The upper left corner x coordinate of the destination rectangle.
3793	* @param y The upper left corner y coordinate of the destination rectangle.
3794	* @param cx The width of the source and destination rectangles.
3795	* @param cy The height of the source and destination rectangles.
3796	* @see PDMIDISPLAYPORT::pfnDisplayBlt() for details.
3797	*/
3798	static DECLCALLBACK(int) vgaPortDisplayBlt(PPDMIDISPLAYPORT pInterface, const void *pvData, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
3799	{
3800	PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
3801	int rc = VINF_SUCCESS;
3802	PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
3803	LogFlow(("vgaPortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy));
3804
3805	/*
3806	* Validate input.
3807	*/
3808	if ( pvData
3809	&& x < pData->pDrv->cx
3810	&& cx <= pData->pDrv->cx
3811	&& cx + x <= pData->pDrv->cx
3812	&& y < pData->pDrv->cy
3813	&& cy <= pData->pDrv->cy
3814	&& cy + y <= pData->pDrv->cy)
3815	{
3816	/*
3817	* Determin bytes per pixel in the destination buffer.
3818	*/
3819	size_t cbPixelDst = 0;
3820	switch (pData->pDrv->cBits)
3821	{
3822	case 8:
3823	cbPixelDst = 1;
3824	break;
3825	case 15:
3826	case 16:
3827	cbPixelDst = 2;
3828	break;
3829	case 24:
3830	cbPixelDst = 3;
3831	break;
3832	case 32:
3833	cbPixelDst = 4;
3834	break;
3835	default:
3836	rc = VERR_INVALID_PARAMETER;
3837	break;
3838	}
3839	if (VBOX_SUCCESS(rc))
3840	{
3841	/*
3842	* The blitting loop.
3843	*/
3844	size_t cbLineSrc = RT_ALIGN_Z(cx, 4) * 4;
3845	uint8_t pu8Src = (uint8_t )pvData;
3846	size_t cbLineDst = pData->pDrv->cbScanline;
3847	uint8_t pu8Dst = pData->pDrv->pu8Data + y cbLineDst + x * cbPixelDst;
3848	uint32_t cyLeft = cy;
3849	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[VGA_DRAW_LINE32 4 + get_depth_index(pData->pDrv->cBits)];
3850	Assert(pfnVgaDrawLine);
3851	while (cyLeft-- > 0)
3852	{
3853	pfnVgaDrawLine(pData, pu8Dst, pu8Src, cx);
3854	pu8Dst += cbLineDst;
3855	pu8Src += cbLineSrc;
3856	}
3857
3858	/*
3859	* Invalidate the area.
3860	*/
3861	pData->pDrv->pfnUpdateRect(pData->pDrv, x, y, cx, cy);
3862	}
3863	}
3864	else
3865	rc = VERR_INVALID_PARAMETER;
3866
3867	LogFlow(("vgaPortDisplayBlt: returns %Vrc\n", rc));
3868	return rc;
3869	}
3870
3871	static DECLCALLBACK(void) vgaPortUpdateDisplayRect (PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t w, uint32_t h)
3872	{
3873	uint32_t v;
3874	vga_draw_line_func *vga_draw_line;
3875
3876	uint32_t cbPixelDst;
3877	uint32_t cbLineDst;
3878	uint8_t *pu8Dst;
3879
3880	uint32_t cbPixelSrc;
3881	uint32_t cbLineSrc;
3882	uint8_t *pu8Src;
3883
3884	uint32_t u32OffsetSrc, u32Dummy;
3885
3886	PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
3887
3888	#ifdef DEBUG_sunlover
3889	LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d\n", x, y, w, h));
3890	#endif /* DEBUG_sunlover */
3891
3892	Assert(pInterface);
3893	Assert(s->pDrv);
3894	Assert(s->pDrv->pu8Data);
3895
3896	/* Check if there is something to do at all. */
3897	if (!s->fRenderVRAM)
3898	{
3899	/* The framebuffer uses the guest VRAM directly. */
3900	#ifdef DEBUG_sunlover
3901	LogFlow(("vgaPortUpdateDisplayRect: nothing to do fRender is false.\n"));
3902	#endif /* DEBUG_sunlover */
3903	return;
3904	}
3905
3906	/* Correct negative x and y coordinates. */
3907	if (x < 0)
3908	{
3909	x += w; /* Compute xRight which is also the new width. */
3910	w = (x < 0) ? 0 : x;
3911	x = 0;
3912	}
3913
3914	if (y < 0)
3915	{
3916	y += h; /* Compute yBottom, which is also the new height. */
3917	h = (y < 0) ? 0 : y;
3918	y = 0;
3919	}
3920
3921	/* Also check if coords are greater than the display resolution. */
3922	if (x + w > s->pDrv->cx)
3923	{
3924	#ifndef VBOX
3925	w = s->pDrv->cx > x? s->pDrv->cx - x: 0;
3926	#else
3927	// x < 0 is not possible here
3928	w = s->pDrv->cx > (uint32_t)x? s->pDrv->cx - x: 0;
3929	#endif
3930	}
3931
3932	if (y + h > s->pDrv->cy)
3933	{
3934	#ifndef VBOX
3935	h = s->pDrv->cy > y? s->pDrv->cy - y: 0;
3936	#else
3937	// y < 0 is not possible here
3938	h = s->pDrv->cy > (uint32_t)y? s->pDrv->cy - y: 0;
3939	#endif
3940	}
3941
3942	#ifdef DEBUG_sunlover
3943	LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d (corrected coords)\n", x, y, w, h));
3944	#endif /* DEBUG_sunlover */
3945
3946	/* Check if there is something to do at all. */
3947	if (w == 0 \|\| h == 0)
3948	{
3949	/* Empty rectangle. */
3950	#ifdef DEBUG_sunlover
3951	LogFlow(("vgaPortUpdateDisplayRect: nothing to do: %dx%d\n", w, h));
3952	#endif /* DEBUG_sunlover */
3953	return;
3954	}
3955
3956	/** @todo This method should be made universal and not only for VBVA.
3957	* VGA_DRAW_LINE* must be selected and src/dst address calculation
3958	* changed.
3959	*/
3960
3961	/* Choose the rendering function. */
3962	switch(s->get_bpp(s))
3963	{
3964	default:
3965	case 0:
3966	AssertMsgFailed(("Unsupported BPP %d\n", s->get_bpp (s)));
3967	return;
3968	case 8:
3969	v = VGA_DRAW_LINE8;
3970	break;
3971	case 15:
3972	v = VGA_DRAW_LINE15;
3973	break;
3974	case 16:
3975	v = VGA_DRAW_LINE16;
3976	break;
3977	case 24:
3978	v = VGA_DRAW_LINE24;
3979	break;
3980	case 32:
3981	v = VGA_DRAW_LINE32;
3982	break;
3983	}
3984
3985	vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
3986
3987	/* Compute source and destination addresses and pitches. */
3988	cbPixelDst = (s->pDrv->cBits + 7) / 8;
3989	cbLineDst = s->pDrv->cbScanline;
3990	pu8Dst = s->pDrv->pu8Data + y * cbLineDst + x * cbPixelDst;
3991
3992	cbPixelSrc = (s->get_bpp(s) + 7) / 8;
3993	s->get_offsets (s, &cbLineSrc, &u32OffsetSrc, &u32Dummy);
3994
3995	/* Assume that rendering is performed only on visible part of VRAM.
3996	* This is true because coordinates were verified.
3997	*/
3998	pu8Src = s->vram_ptrHC;
3999	pu8Src += u32OffsetSrc + y * cbLineSrc + x * cbPixelSrc;
4000
4001	/* Render VRAM to framebuffer. */
4002
4003	#ifdef DEBUG_sunlover
4004	LogFlow(("vgaPortUpdateDisplayRect: dst: %p, %d, %d. src: %p, %d, %d\n", pu8Dst, cbLineDst, cbPixelDst, pu8Src, cbLineSrc, cbPixelSrc));
4005	#endif /* DEBUG_sunlover */
4006
4007	while (h-- > 0)
4008	{
4009	vga_draw_line (s, pu8Dst, pu8Src, w);
4010	pu8Dst += cbLineDst;
4011	pu8Src += cbLineSrc;
4012	}
4013
4014	#ifdef DEBUG_sunlover
4015	LogFlow(("vgaPortUpdateDisplayRect: completed.\n"));
4016	#endif /* DEBUG_sunlover */
4017	}
4018
4019	static DECLCALLBACK(void) vgaPortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender)
4020	{
4021	PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
4022
4023	LogFlow(("vgaPortSetRenderVRAM: fRender = %d\n", fRender));
4024
4025	s->fRenderVRAM = fRender;
4026	}
4027
4028
4029	static DECLCALLBACK(void) vgaTimerRefresh(PPDMDEVINS pDevIns, PTMTIMER pTimer)
4030	{
4031	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4032	if (pData->pDrv)
4033	pData->pDrv->pfnRefresh(pData->pDrv);
4034	if (pData->cMilliesRefreshInterval)
4035	TMTimerSetMillies(pTimer, pData->cMilliesRefreshInterval);
4036	}
4037
4038
4039	/* -=-=-=-=-=- Ring 3: PCI Device -=-=-=-=-=- */
4040
4041	/**
4042	* Callback function for mapping an PCI I/O region.
4043	*
4044	* @return VBox status code.
4045	* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4046	* @param iRegion The region number.
4047	* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4048	* I/O port, else it's a physical address.
4049	* This address is NOT relative to pci_mem_base like earlier!
4050	* @param enmType One of the PCI_ADDRESS_SPACE_* values.
4051	*/
4052	static DECLCALLBACK(int) vgaR3IORegionMap(PPCIDEVICE pPciDev, /unsigned/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4053	{
4054	int rc;
4055	PVGASTATE pData = PDMINS2DATA(pPciDev->pDevIns, PVGASTATE);
4056	LogFlow(("vgaR3IORegionMap: iRegion=%d GCPhysAddress=%VGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4057
4058	/*
4059	* VRam mapping.
4060	*/
4061	if (iRegion == 0 && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH)
4062	{
4063	/*
4064	* Register and lock the VRAM.
4065	*
4066	* Windows usually re-initializes the PCI devices, so we have to check whether the memory was
4067	* already registered before trying to do that all over again.
4068	*/
4069	PVM pVM = PDMDevHlpGetVM(pPciDev->pDevIns);
4070	if (pData->GCPhysVRAM)
4071	{
4072	AssertMsg(pData->GCPhysVRAM == GCPhysAddress,
4073	("The Guest OS relocated our LFB! old GCPhysVRAM=%VGp new GCPhysAddress=%VGp\n",
4074	pData->GCPhysVRAM, GCPhysAddress));
4075	rc = VINF_SUCCESS;
4076	}
4077	else
4078	{
4079	/*
4080	* Register and lock the VRAM.
4081	*/
4082	rc = MMR3PhysRegister(pVM, pData->vram_ptrHC, GCPhysAddress, pData->vram_size, MM_RAM_FLAGS_MMIO2, "VRam");
4083	if (VBOX_SUCCESS(rc))
4084	{
4085	if (!pData->GCPhysVRAM)
4086	rc = PGMR3HandlerPhysicalRegister(pVM, PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
4087	GCPhysAddress, GCPhysAddress + (pData->vram_size - 1),
4088	vgaR3LFBAccessHandler, pData,
4089	g_DeviceVga.szR0Mod, "vgaR0LFBAccessHandler", pData->pDevInsHC->pvInstanceDataR0,
4090	g_DeviceVga.szGCMod, "vgaGCLFBAccessHandler", pData->pDevInsHC->pvInstanceDataGC,
4091	"VGA LFB");
4092	if (VBOX_SUCCESS(rc))
4093	{
4094	/*
4095	* Map the first 256KB of the VRAM into GC for GC VGA support.
4096	*/
4097	RTGCPTR GCPtr;
4098	rc = MMR3HyperMapGCPhys(pVM, GCPhysAddress, VGA_MAPPING_SIZE, "VGA VRam", &GCPtr);
4099	if (VBOX_SUCCESS(rc))
4100	{
4101	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
4102
4103	pData->vram_ptrGC = GCPtr;
4104	pData->GCPhysVRAM = GCPhysAddress;
4105	return VINF_SUCCESS;
4106	}
4107	AssertMsgFailed(("MMR3HyperMapGCPhys failed, rc=%Vrc\n", rc));
4108	}
4109	else
4110	AssertMsgFailed(("Failed to register write handler for VRAM! rc=%Vrc\n", rc));
4111	}
4112	else
4113	AssertReleaseMsgFailed(("Failed to register VRAM! rc=%Vra\n", rc));
4114	}
4115	return rc;
4116	}
4117	else
4118	AssertReleaseMsgFailed(("Huh!?! iRegion=%d enmType=%d\n", iRegion, enmType));
4119	return VERR_INTERNAL_ERROR;
4120	}
4121
4122
4123	/* -=-=-=-=-=- Ring3: Misc Wrappers -=-=-=-=-=- */
4124
4125	/**
4126	* Saves a state of the VGA device.
4127	*
4128	* @returns VBox status code.
4129	* @param pDevIns The device instance.
4130	* @param pSSMHandle The handle to save the state to.
4131	*/
4132	static DECLCALLBACK(int) vgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4133	{
4134	vga_save(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE));
4135	return VINF_SUCCESS;
4136	}
4137
4138
4139	/**
4140	* Loads a saved VGA device state.
4141	*
4142	* @returns VBox status code.
4143	* @param pDevIns The device instance.
4144	* @param pSSMHandle The handle to the saved state.
4145	* @param u32Version The data unit version number.
4146	*/
4147	static DECLCALLBACK(int) vgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
4148	{
4149	if (vga_load(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE), u32Version))
4150	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4151	return VINF_SUCCESS;
4152	}
4153
4154
4155	/* -=-=-=-=-=- Ring 3: Device callbacks -=-=-=-=-=- */
4156
4157	/**
4158	* Reset notification.
4159	*
4160	* @returns VBox status.
4161	* @param pDevIns The device instance data.
4162	*/
4163	static DECLCALLBACK(void) vgaR3Reset(PPDMDEVINS pDevIns)
4164	{
4165	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4166	char *pchStart;
4167	char *pchEnd;
4168	LogFlow(("vgaReset\n"));
4169
4170	/* Clear the VRAM ourselves. */
4171	if (pData->vram_ptrHC && pData->vram_size)
4172	{
4173	#ifdef LOG_ENABLED /** @todo separate function. */
4174	/* First dump the textmode contents to the log; handy for capturing Windows blue screens. */
4175	uint8_t graphic_mode;
4176	VGAState *s = pData;
4177
4178	if (!(s->ar_index & 0x20)) {
4179	graphic_mode = GMODE_BLANK;
4180	} else {
4181	graphic_mode = s->gr[6] & 1;
4182	}
4183	switch(graphic_mode)
4184	case GMODE_TEXT:
4185	{
4186	int cw, height, width, cheight, cx_min, cx_max, cy, cx;
4187	int x_incr;
4188	uint8_t s1, src, ch, cattr;
4189	int line_offset;
4190	uint16_t ch_attr;
4191
4192	line_offset = s->line_offset;
4193	s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 4);
4194
4195	/* total width & height */
4196	cheight = (s->cr[9] & 0x1f) + 1;
4197	cw = 8;
4198	if (!(s->sr[1] & 0x01))
4199	cw = 9;
4200	if (s->sr[1] & 0x08)
4201	cw = 16; /* NOTE: no 18 pixel wide */
4202	x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
4203	width = (s->cr[0x01] + 1);
4204	if (s->cr[0x06] == 100) {
4205	/* ugly hack for CGA 160x100x16 - explain me the logic */
4206	height = 100;
4207	} else {
4208	height = s->cr[0x12] \|
4209	((s->cr[0x07] & 0x02) << 7) \|
4210	((s->cr[0x07] & 0x40) << 3);
4211	height = (height + 1) / cheight;
4212	}
4213	if ((height * width) > CH_ATTR_SIZE) {
4214	/* better than nothing: exit if transient size is too big */
4215	break;
4216	}
4217	RTLogPrintf("VGA textmode BEGIN (%dx%d):\n\n", height, width);
4218	for(cy = 0; cy < height; cy++) {
4219	src = s1;
4220	cx_min = width;
4221	cx_max = -1;
4222	for(cx = 0; cx < width; cx++) {
4223	ch_attr = (uint16_t )src;
4224	if (cx < cx_min)
4225	cx_min = cx;
4226	if (cx > cx_max)
4227	cx_max = cx;
4228	# ifdef WORDS_BIGENDIAN
4229	ch = ch_attr >> 8;
4230	cattr = ch_attr & 0xff;
4231	# else
4232	ch = ch_attr & 0xff;
4233	cattr = ch_attr >> 8;
4234	# endif
4235	RTLogPrintf("%c", ch);
4236
4237	src += 4;
4238	}
4239	if (cx_max != -1)
4240	RTLogPrintf("\n");
4241
4242	s1 += line_offset;
4243	}
4244	RTLogPrintf("VGA textmode END:\n\n");
4245	}
4246
4247	#endif
4248	memset(pData->vram_ptrHC, 0, pData->vram_size);
4249	}
4250
4251	/*
4252	* Zero most of it.
4253	*
4254	* Unlike vga_reset we're leaving out a few members which believe must
4255	* remain unchanged....
4256	*/
4257	/* 1st part. */
4258	pchStart = (char *)&pData->latch;
4259	pchEnd = (char *)&pData->invalidated_y_table;
4260	memset(pchStart, 0, pchEnd - pchStart);
4261
4262	/* 2nd part. */
4263	pchStart = (char *)&pData->last_palette;
4264	pchEnd = (char *)&pData->u32Marker;
4265	memset(pchStart, 0, pchEnd - pchStart);
4266
4267
4268	/*
4269	* Restore and re-init some bits.
4270	*/
4271	pData->get_bpp = vga_get_bpp;
4272	pData->get_offsets = vga_get_offsets;
4273	pData->get_resolution = vga_get_resolution;
4274	pData->graphic_mode = -1; /* Force full update. */
4275	#ifdef CONFIG_BOCHS_VBE
4276	pData->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
4277	pData->vbe_regs[VBE_DISPI_INDEX_CMONITORS] = pData->monitor_count;
4278	pData->vbe_bank_mask = ((pData->vram_size >> 16) - 1);
4279	#endif /* CONFIG_BOCHS_VBE */
4280
4281	/*
4282	* Reset the LBF mapping.
4283	*/
4284	pData->fLFBUpdated = false;
4285	if ( ( pData->fGCEnabled
4286	\|\| pData->fR0Enabled)
4287	&& pData->GCPhysVRAM)
4288	{
4289	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4290	AssertRC(rc);
4291	}
4292
4293	/* notify port handler */
4294	if (pData->pDrv)
4295	pData->pDrv->pfnReset(pData->pDrv);
4296	}
4297
4298
4299	/**
4300	* Device relocation callback.
4301	*
4302	* @param pDevIns Pointer to the device instance.
4303	* @param offDelta The relocation delta relative to the old location.
4304	*
4305	* @see FNPDMDEVRELOCATE for details.
4306	*/
4307	static DECLCALLBACK(void) vgaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4308	{
4309	if (offDelta)
4310	{
4311	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4312	LogFlow(("vgaRelocate: offDelta = %08X\n", offDelta));
4313
4314	pData->GCPtrLFBHandler += offDelta;
4315	pData->vram_ptrGC += offDelta;
4316	}
4317	}
4318
4319
4320	/**
4321	* Attach command.
4322	*
4323	* This is called to let the device attach to a driver for a specified LUN
4324	* during runtime. This is not called during VM construction, the device
4325	* constructor have to attach to all the available drivers.
4326	*
4327	* This is like plugging in the monitor after turning on the PC.
4328	*
4329	* @returns VBox status code.
4330	* @param pDevIns The device instance.
4331	* @param iLUN The logical unit which is being detached.
4332	*/
4333	static DECLCALLBACK(int) vgaAttach(PPDMDEVINS pDevIns, unsigned iLUN)
4334	{
4335	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4336	switch (iLUN)
4337	{
4338	/* LUN #0: Display port. */
4339	case 0:
4340	{
4341	int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pData->Base, &pData->pDrvBase, "Display Port");
4342	if (VBOX_SUCCESS(rc))
4343	{
4344	pData->pDrv = (PDMIDISPLAYCONNECTOR*)pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_DISPLAY_CONNECTOR);
4345	if (pData->pDrv)
4346	{
4347	if ( pData->pDrv->pu8Data
4348	&& pData->pDrv->pfnRefresh
4349	&& pData->pDrv->pfnResize
4350	&& pData->pDrv->pfnUpdateRect)
4351	rc = VINF_SUCCESS;
4352	else
4353	{
4354	Assert(pData->pDrv->pu8Data);
4355	Assert(pData->pDrv->pfnRefresh);
4356	Assert(pData->pDrv->pfnResize);
4357	Assert(pData->pDrv->pfnUpdateRect);
4358	pData->pDrv = NULL;
4359	pData->pDrvBase = NULL;
4360	rc = VERR_INTERNAL_ERROR;
4361	}
4362	}
4363	else
4364	{
4365	AssertMsgFailed(("LUN #0 doesn't have a display connector interface! rc=%Vrc\n", rc));
4366	pData->pDrvBase = NULL;
4367	rc = VERR_PDM_MISSING_INTERFACE;
4368	}
4369	}
4370	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4371	{
4372	Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
4373	rc = VINF_SUCCESS;
4374	}
4375	else
4376	AssertMsgFailed(("Failed to attach LUN #0! rc=%Vrc\n", rc));
4377	return rc;
4378	}
4379
4380	default:
4381	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
4382	return VERR_PDM_NO_SUCH_LUN;
4383	}
4384	}
4385
4386
4387	/**
4388	* Detach notification.
4389	*
4390	* This is called when a driver is detaching itself from a LUN of the device.
4391	* The device should adjust it's state to reflect this.
4392	*
4393	* This is like unplugging the monitor while the PC is still running.
4394	*
4395	* @param pDevIns The device instance.
4396	* @param iLUN The logical unit which is being detached.
4397	*/
4398	static DECLCALLBACK(void) vgaDetach(PPDMDEVINS pDevIns, unsigned iLUN)
4399	{
4400	/*
4401	* Reset the interfaces and update the controller state.
4402	*/
4403	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4404	switch (iLUN)
4405	{
4406	/* LUN #0: Display port. */
4407	case 0:
4408	pData->pDrv = NULL;
4409	pData->pDrvBase = NULL;
4410	break;
4411
4412	default:
4413	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
4414	break;
4415	}
4416	}
4417
4418
4419
4420	/**
4421	* Construct a VGA device instance for a VM.
4422	*
4423	* @returns VBox status.
4424	* @param pDevIns The device instance data.
4425	* If the registration structure is needed, pDevIns->pDevReg points to it.
4426	* @param iInstance Instance number. Use this to figure out which registers and such to use.
4427	* The device number is also found in pDevIns->iInstance, but since it's
4428	* likely to be freqently used PDM passes it as parameter.
4429	* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
4430	* of the device instance. It's also found in pDevIns->pCfgHandle, but like
4431	* iInstance it's expected to be used a bit in this function.
4432	*/
4433	static DECLCALLBACK(int) vgaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4434	{
4435	static bool fExpandDone = false;
4436	bool f;
4437	int rc;
4438	unsigned i;
4439	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4440	PVM pVM = PDMDevHlpGetVM(pDevIns);
4441	#ifdef VBE_NEW_DYN_LIST
4442	uint32_t cCustomModes;
4443	uint32_t cyReduction;
4444	PVBEHEADER pVBEDataHdr;
4445	ModeInfoListItem *pCurMode;
4446	unsigned cb;
4447	#endif
4448	Assert(iInstance == 0);
4449	Assert(pVM);
4450
4451	/*
4452	* Init static data.
4453	*/
4454	if (!fExpandDone)
4455	{
4456	fExpandDone = true;
4457	vga_init_expand();
4458	}
4459
4460	/*
4461	* Validate configuration.
4462	*/
4463	if (!CFGMR3AreValuesValid(pCfgHandle, "VRamSize\0"
4464	"MonitorCount\0"
4465	"GCEnabled\0"
4466	"R0Enabled\0"
4467	"CustomVideoModes\0"
4468	"HeightReduction\0"
4469	"CustomVideoMode1\0"
4470	"CustomVideoMode2\0"
4471	"CustomVideoMode3\0"
4472	"CustomVideoMode4\0"
4473	"CustomVideoMode5\0"
4474	"CustomVideoMode6\0"
4475	"CustomVideoMode7\0"
4476	"CustomVideoMode8\0"
4477	"CustomVideoMode9\0"
4478	"CustomVideoMode10\0"
4479	"CustomVideoMode11\0"
4480	"CustomVideoMode12\0"
4481	"CustomVideoMode13\0"
4482	"CustomVideoMode14\0"
4483	"CustomVideoMode15\0"
4484	"CustomVideoMode16\0"))
4485	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4486	N_("Invalid configuration for vga device"));
4487
4488	/*
4489	* Init state data.
4490	*/
4491	rc = CFGMR3QueryU32(pCfgHandle, "VRamSize", &pData->vram_size);
4492	if (VBOX_FAILURE(rc) \|\| !pData->vram_size)
4493	pData->vram_size = VGA_VRAM_DEFAULT;
4494	else if (pData->vram_size > VGA_VRAM_MAX)
4495	{
4496	AssertMsgFailed(("vram_size=%d max=%d\n", pData->vram_size, VGA_VRAM_MAX));
4497	pData->vram_size = VGA_VRAM_MAX;
4498	}
4499	else if (pData->vram_size < VGA_VRAM_MIN)
4500	{
4501	AssertMsgFailed(("vram_size=%d min=%d\n", pData->vram_size, VGA_VRAM_MIN));
4502	pData->vram_size = RT_ALIGN_32(pData->vram_size, _1M);
4503	}
4504	Log(("VGA: VRamSize=%#x\n", pData->vram_size));
4505
4506	rc = CFGMR3QueryU32(pCfgHandle, "MonitorCount", &pData->monitor_count);
4507	if (VBOX_FAILURE(rc) \|\| !pData->monitor_count)
4508	pData->monitor_count = 1;
4509	else if (pData->monitor_count > VGA_MONITORS_MAX)
4510	{
4511	AssertMsgFailed(("monitor_count=%d max=%d\n", pData->monitor_count, VGA_MONITORS_MAX));
4512	pData->monitor_count = 1;
4513	}
4514	pData->vbe_regs[VBE_DISPI_INDEX_CMONITORS] = pData->monitor_count;
4515	Log(("VGA: MonitorCount=%d\n", pData->monitor_count));
4516
4517	pData->fGCEnabled = true;
4518	rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &f);
4519	if (VBOX_SUCCESS(rc) && !f)
4520	pData->fGCEnabled = false;
4521	Log(("VGA: fGCEnabled=%d\n", pData->fGCEnabled));
4522
4523	pData->fR0Enabled = true;
4524	rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &f);
4525	if (VBOX_SUCCESS(rc) && !f)
4526	pData->fR0Enabled = false;
4527	Log(("VGA: fR0Enabled=%d\n", pData->fR0Enabled));
4528
4529	pData->pDevInsHC = pDevIns;
4530
4531	vgaR3Reset(pDevIns);
4532
4533	/* The PCI devices configuration. */
4534	pData->Dev.config[0x00] = 0xee; /* PCI vendor, just a free bogus value */
4535	pData->Dev.config[0x01] = 0x80;
4536
4537	pData->Dev.config[0x02] = 0xef; /* Device ID */
4538	pData->Dev.config[0x03] = 0xbe;
4539
4540	pData->Dev.config[0x0a] = 0x00; /* VGA controller */
4541	pData->Dev.config[0x0b] = 0x03;
4542	pData->Dev.config[0x0e] = 0x00; /* header_type */
4543
4544	/* The LBF access handler - error handling is better here than in the map function. */
4545	rc = PDMR3GetSymbolGCLazy(pVM, pDevIns->pDevReg->szGCMod, "vgaGCLFBAccessHandler", &pData->GCPtrLFBHandler);
4546	if (VBOX_FAILURE(rc))
4547	{
4548	AssertReleaseMsgFailed(("PDMR3GetSymbolGC(, %s, \"vgaGCLFBAccessHandler\",) -> %Vrc\n", pDevIns->pDevReg->szGCMod, rc));
4549	return rc;
4550	}
4551
4552	/* the interfaces. */
4553	pData->Base.pfnQueryInterface = vgaPortQueryInterface;
4554
4555	pData->Port.pfnUpdateDisplay = vgaPortUpdateDisplay;
4556	pData->Port.pfnUpdateDisplayAll = vgaPortUpdateDisplayAll;
4557	pData->Port.pfnQueryColorDepth = vgaPortQueryColorDepth;
4558	pData->Port.pfnSetRefreshRate = vgaPortSetRefreshRate;
4559	pData->Port.pfnSnapshot = vgaPortSnapshot;
4560	pData->Port.pfnDisplayBlt = vgaPortDisplayBlt;
4561	pData->Port.pfnUpdateDisplayRect= vgaPortUpdateDisplayRect;
4562	pData->Port.pfnSetRenderVRAM = vgaPortSetRenderVRAM;
4563
4564
4565	/*
4566	* Register I/O ports, ROM and save state.
4567	*/
4568	rc = PDMDevHlpIOPortRegister(pDevIns, 0x3c0, 16, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3c0");
4569	if (VBOX_FAILURE(rc))
4570	return rc;
4571	rc = PDMDevHlpIOPortRegister(pDevIns, 0x3b4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3b4");
4572	if (VBOX_FAILURE(rc))
4573	return rc;
4574	rc = PDMDevHlpIOPortRegister(pDevIns, 0x3ba, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3ba");
4575	if (VBOX_FAILURE(rc))
4576	return rc;
4577	rc = PDMDevHlpIOPortRegister(pDevIns, 0x3d4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3d4");
4578	if (VBOX_FAILURE(rc))
4579	return rc;
4580	rc = PDMDevHlpIOPortRegister(pDevIns, 0x3da, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3da");
4581	if (VBOX_FAILURE(rc))
4582	return rc;
4583
4584	#ifdef CONFIG_BOCHS_VBE
4585	rc = PDMDevHlpIOPortRegister(pDevIns, 0x1ce, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, NULL, NULL, "VGA/VBE - Index");
4586	if (VBOX_FAILURE(rc))
4587	return rc;
4588	rc = PDMDevHlpIOPortRegister(pDevIns, 0x1cf, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, NULL, NULL, "VGA/VBE - Data");
4589	if (VBOX_FAILURE(rc))
4590	return rc;
4591	#if 0
4592	/* This now causes conflicts with Win2k & XP; it is not aware this range is taken
4593	and tries to map other devices there */
4594	/* Old Bochs. */
4595	rc = PDMDevHlpIOPortRegister(pDevIns, 0xff80, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, "VGA/VBE - Index Old");
4596	if (VBOX_FAILURE(rc))
4597	return rc;
4598	rc = PDMDevHlpIOPortRegister(pDevIns, 0xff81, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, "VGA/VBE - Data Old");
4599	if (VBOX_FAILURE(rc))
4600	return rc;
4601	#endif
4602	#endif /* CONFIG_BOCHS_VBE */
4603
4604	/* guest context extension */
4605	if (pData->fGCEnabled)
4606	{
4607	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
4608	if (VBOX_FAILURE(rc))
4609	return rc;
4610	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
4611	if (VBOX_FAILURE(rc))
4612	return rc;
4613	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
4614	if (VBOX_FAILURE(rc))
4615	return rc;
4616	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
4617	if (VBOX_FAILURE(rc))
4618	return rc;
4619	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
4620	if (VBOX_FAILURE(rc))
4621	return rc;
4622	#ifdef CONFIG_BOCHS_VBE
4623	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
4624	if (VBOX_FAILURE(rc))
4625	return rc;
4626	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
4627	if (VBOX_FAILURE(rc))
4628	return rc;
4629
4630	#if 0
4631	/* This now causes conflicts with Win2k & XP; it is not aware this range is taken
4632	and tries to map other devices there */
4633	/* Old Bochs. */
4634	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
4635	if (VBOX_FAILURE(rc))
4636	return rc;
4637	rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
4638	if (VBOX_FAILURE(rc))
4639	return rc;
4640	#endif
4641
4642	#endif /* CONFIG_BOCHS_VBE */
4643	}
4644
4645	/* R0 context extension */
4646	if (pData->fR0Enabled)
4647	{
4648	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
4649	if (VBOX_FAILURE(rc))
4650	return rc;
4651	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
4652	if (VBOX_FAILURE(rc))
4653	return rc;
4654	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
4655	if (VBOX_FAILURE(rc))
4656	return rc;
4657	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
4658	if (VBOX_FAILURE(rc))
4659	return rc;
4660	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
4661	if (VBOX_FAILURE(rc))
4662	return rc;
4663	#ifdef CONFIG_BOCHS_VBE
4664	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
4665	if (VBOX_FAILURE(rc))
4666	return rc;
4667	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
4668	if (VBOX_FAILURE(rc))
4669	return rc;
4670
4671	#if 0
4672	/* This now causes conflicts with Win2k & XP; it is not aware this range is taken
4673	and tries to map other devices there */
4674	/* Old Bochs. */
4675	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
4676	if (VBOX_FAILURE(rc))
4677	return rc;
4678	rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
4679	if (VBOX_FAILURE(rc))
4680	return rc;
4681	#endif
4682
4683	#endif /* CONFIG_BOCHS_VBE */
4684	}
4685
4686	/* vga mmio */
4687	rc = PDMDevHlpMMIORegister(pDevIns, 0x000a0000, 0x00020000, 0, vgaMMIOWrite, vgaMMIORead, vgaMMIOFill, "VGA - VGA Video Buffer");
4688	if (VBOX_FAILURE(rc))
4689	return rc;
4690	if (pData->fGCEnabled)
4691	{
4692	rc = PDMDevHlpMMIORegisterGC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill", "VGA - VGA Video Buffer");
4693	if (VBOX_FAILURE(rc))
4694	return rc;
4695	}
4696	if (pData->fR0Enabled)
4697	{
4698	rc = PDMDevHlpMMIORegisterR0(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill", "VGA - VGA Video Buffer");
4699	if (VBOX_FAILURE(rc))
4700	return rc;
4701	}
4702
4703	/* vga bios */
4704	rc = PDMDevHlpIOPortRegister(pDevIns, VBE_PRINTF_PORT, 1, NULL, vgaIOPortWriteBIOS, vgaIOPortReadBIOS, NULL, NULL, "VGA BIOS debug/panic");
4705	if (VBOX_FAILURE(rc))
4706	return rc;
4707	AssertReleaseMsg(g_cbVgaBiosBinary <= _64K && g_cbVgaBiosBinary >= 32*_1K, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
4708	AssertReleaseMsg(RT_ALIGN_Z(g_cbVgaBiosBinary, PAGE_SIZE) == g_cbVgaBiosBinary, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
4709	rc = PDMDevHlpROMRegister(pDevIns, 0x000c0000, g_cbVgaBiosBinary, &g_abVgaBiosBinary[0], "VGA BIOS");
4710	if (VBOX_FAILURE(rc))
4711	return rc;
4712
4713	/* save */
4714	rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version /, sizeof(pData),
4715	NULL, vgaR3SaveExec, NULL,
4716	NULL, vgaR3LoadExec, NULL);
4717	if (VBOX_FAILURE(rc))
4718	return rc;
4719
4720	/* PCI */
4721	rc = PDMDevHlpPCIRegister(pDevIns, &pData->Dev);
4722	if (VBOX_FAILURE(rc))
4723	return rc;
4724	/AssertMsg(pData->Dev.devfn == 16 \|\| iInstance != 0, ("pData->Dev.devfn=%d\n", pData->Dev.devfn));/
4725	if (pData->Dev.devfn != 16 && iInstance == 0)
4726	Log(("!!WARNING!!: pData->dev.devfn=%d (ignore if testcase or no started by Main)\n", pData->Dev.devfn));
4727	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, pData->vram_size, PCI_ADDRESS_SPACE_MEM_PREFETCH, vgaR3IORegionMap);
4728	if (VBOX_FAILURE(rc))
4729	return rc;
4730
4731	/*
4732	* Create the refresh timer.
4733	*/
4734	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_REAL, vgaTimerRefresh, "VGA Refresh Timer", &pData->RefreshTimer);
4735	if (VBOX_FAILURE(rc))
4736	return rc;
4737
4738	/*
4739	* Attach to the display.
4740	*/
4741	rc = vgaAttach(pDevIns, 0 /* display LUN # */);
4742	if (VBOX_FAILURE(rc))
4743	return rc;
4744
4745	/*
4746	* Allocate the VRAM.
4747	*/
4748	rc = SUPPageAlloc(pData->vram_size >> PAGE_SHIFT, (void **)&pData->vram_ptrHC);
4749	if (VBOX_FAILURE(rc))
4750	{
4751	AssertMsgFailed(("SUPPageAlloc(%#x,) -> %d\n", pData->vram_size, rc));
4752	return rc;
4753	}
4754
4755	#ifdef VBE_NEW_DYN_LIST
4756	/*
4757	* Compute buffer size for the VBE BIOS Extra Data.
4758	*/
4759	cb = sizeof(mode_info_list) + sizeof(ModeInfoListItem);
4760
4761	rc = CFGMR3QueryU32(pCfgHandle, "HeightReduction", &cyReduction);
4762	if (VBOX_SUCCESS(rc) && cyReduction)
4763	cb = 2; / Default mode list will be twice long */
4764	else
4765	cyReduction = 0;
4766
4767	rc = CFGMR3QueryU32(pCfgHandle, "CustomVideoModes", &cCustomModes);
4768	if (VBOX_SUCCESS(rc) && cCustomModes)
4769	cb += sizeof(ModeInfoListItem) * cCustomModes;
4770	else
4771	cCustomModes = 0;
4772
4773	/*
4774	* Allocate and initialize buffer for the VBE BIOS Extra Data.
4775	*/
4776	pData->cbVBEExtraData = sizeof(VBEHEADER) + cb;
4777	pData->pu8VBEExtraData = (uint8_t *)PDMDevHlpMMHeapAllocZ(pDevIns, pData->cbVBEExtraData);
4778	if (!pData->pu8VBEExtraData)
4779	return VERR_NO_MEMORY;
4780
4781	pVBEDataHdr = (PVBEHEADER)pData->pu8VBEExtraData;
4782	pVBEDataHdr->u16Signature = VBEHEADER_MAGIC;
4783	pVBEDataHdr->cbData = cb;
4784
4785	#ifndef VRAM_SIZE_FIX
4786	pCurMode = memcpy(pVBEDataHdr + 1, &mode_info_list, sizeof(mode_info_list));
4787	pCurMode = (ModeInfoListItem *)((uintptr_t)pCurMode + sizeof(mode_info_list));
4788	#else /* VRAM_SIZE_FIX defined */
4789	pCurMode = (ModeInfoListItem *)(pVBEDataHdr + 1);
4790	for (i = 0; i < MODE_INFO_SIZE; i++)
4791	{
4792	uint32_t pixelWidth, reqSize;
4793	if (mode_info_list[i].info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
4794	pixelWidth = 2;
4795	else
4796	pixelWidth = mode_info_list[i].info.BitsPerPixel / 8;
4797	reqSize = mode_info_list[i].info.XResolution
4798	* mode_info_list[i].info.YResolution
4799	* pixelWidth;
4800	if (reqSize >= pData->vram_size)
4801	continue;
4802	*pCurMode = mode_info_list[i];
4803	pCurMode++;
4804	}
4805	#endif /* VRAM_SIZE_FIX defined */
4806
4807	/*
4808	* Copy default modes with subtractred YResolution.
4809	*/
4810	if (cyReduction)
4811	{
4812	ModeInfoListItem *pDefMode = mode_info_list;
4813	Log(("vgaR3Construct: cyReduction=%u\n", cyReduction));
4814	#ifndef VRAM_SIZE_FIX
4815	for (i = 0; i < MODE_INFO_SIZE; i++, pCurMode++, pDefMode++)
4816	{
4817	pCurMode = pDefMode;
4818	pCurMode->mode += 0x30;
4819	pCurMode->info.YResolution -= cyReduction;
4820	}
4821	#else /* VRAM_SIZE_FIX defined */
4822	for (i = 0; i < MODE_INFO_SIZE; i++, pDefMode++)
4823	{
4824	uint32_t pixelWidth, reqSize;
4825	if (pDefMode->info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
4826	pixelWidth = 2;
4827	else
4828	pixelWidth = pDefMode->info.BitsPerPixel / 8;
4829	reqSize = pDefMode->info.XResolution * pDefMode->info.YResolution * pixelWidth;
4830	if (reqSize >= pData->vram_size)
4831	continue;
4832	pCurMode = pDefMode;
4833	pCurMode->mode += 0x30;
4834	pCurMode->info.YResolution -= cyReduction;
4835	pCurMode++;
4836	}
4837	#endif /* VRAM_SIZE_FIX defined */
4838	}
4839
4840
4841	/*
4842	* Add custom modes.
4843	*/
4844	if (cCustomModes)
4845	{
4846	uint16_t u16CurMode = 0x160;
4847	for (i = 1; i <= cCustomModes; i++)
4848	{
4849	char szExtraDataKey[sizeof("CustomVideoModeXX")];
4850	char *pszExtraData = NULL;
4851
4852	/* query and decode the custom mode string. */
4853	RTStrPrintf(szExtraDataKey, sizeof(szExtraDataKey), "CustomVideoMode%d", i);
4854	rc = CFGMR3QueryStringAlloc(pCfgHandle, szExtraDataKey, &pszExtraData);
4855	if (VBOX_SUCCESS(rc))
4856	{
4857	ModeInfoListItem *pDefMode = mode_info_list;
4858	unsigned int cx, cy, cBits, cParams;
4859	uint16_t u16DefMode;
4860
4861	cParams = sscanf(pszExtraData, "%ux%ux%u", &cx, &cy, &cBits);
4862	if ( cParams != 3
4863	\|\| (cBits != 16 && cBits != 24 && cBits != 32))
4864	{
4865	AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cBits=%d\n", pszExtraData, szExtraDataKey, cBits));
4866	return VERR_VGA_INVALID_CUSTOM_MODE;
4867	}
4868	#ifdef VRAM_SIZE_FIX
4869	if (cx * cy * cBits / 8 >= pData->vram_size)
4870	{
4871	AssertMsgFailed(("Configuration error: custom video mode %dx%dx%dbits is too large for the virtual video memory of %dMb. Please increase the video memory size.\n",
4872	cx, cy, cBits, pData->vram_size / _1M));
4873	return VERR_VGA_INVALID_CUSTOM_MODE;
4874	}
4875	#endif /* VRAM_SIZE_FIX defined */
4876	MMR3HeapFree(pszExtraData);
4877
4878	/* Use defaults from max@bpp mode. */
4879	switch (cBits)
4880	{
4881	case 16:
4882	u16DefMode = VBE_VESA_MODE_1024X768X565;
4883	break;
4884
4885	case 24:
4886	u16DefMode = VBE_VESA_MODE_1024X768X888;
4887	break;
4888
4889	case 32:
4890	u16DefMode = VBE_OWN_MODE_1024X768X8888;
4891	break;
4892
4893	default: /* gcc, shut up! */
4894	AssertMsgFailed(("gone postal!\n"));
4895	continue;
4896	}
4897
4898	while ( pDefMode->mode != u16DefMode
4899	&& pDefMode->mode != VBE_VESA_MODE_END_OF_LIST)
4900	pDefMode++;
4901	Assert(pDefMode->mode != VBE_VESA_MODE_END_OF_LIST);
4902
4903	pCurMode = pDefMode;
4904	pCurMode->mode = u16CurMode++;
4905
4906	/* adjust defaults */
4907	pCurMode->info.XResolution = cx;
4908	pCurMode->info.YResolution = cy;
4909
4910	switch (cBits)
4911	{
4912	case 16:
4913	pCurMode->info.BytesPerScanLine = cx * 2;
4914	pCurMode->info.LinBytesPerScanLine = cx * 2;
4915	break;
4916
4917	case 24:
4918	pCurMode->info.BytesPerScanLine = cx * 3;
4919	pCurMode->info.LinBytesPerScanLine = cx * 3;
4920	break;
4921
4922	case 32:
4923	pCurMode->info.BytesPerScanLine = cx * 4;
4924	pCurMode->info.LinBytesPerScanLine = cx * 4;
4925	break;
4926	}
4927
4928	/* commit it */
4929	pCurMode++;
4930	}
4931	else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
4932	{
4933	AssertMsgFailed(("CFGMR3QueryStringAlloc(,'%s',) -> %Vrc\n", szExtraDataKey, rc));
4934	return rc;
4935	}
4936	} /* foreach custom mode key */
4937	}
4938
4939	/*
4940	* Add the "End of list" mode.
4941	*/
4942	memset(pCurMode, 0, sizeof(*pCurMode));
4943	pCurMode->mode = VBE_VESA_MODE_END_OF_LIST;
4944
4945	/*
4946	* Register I/O Port for the VBE BIOS Extra Data.
4947	*/
4948	rc = PDMDevHlpIOPortRegister(pDevIns, VBE_EXTRA_PORT, 1, NULL, vbeIOPortWriteVBEExtra, vbeIOPortReadVBEExtra, NULL, NULL, "VBE BIOS Extra Data");
4949	if (VBOX_FAILURE(rc))
4950	return rc;
4951	#endif
4952
4953	/*
4954	* Statistics.
4955	*/
4956	STAM_REG(pVM, &pData->StatGCMemoryRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
4957	STAM_REG(pVM, &pData->StatGCMemoryWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
4958	STAM_REG(pVM, &pData->StatGCIOPortRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortRead() body.");
4959	STAM_REG(pVM, &pData->StatGCIOPortWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortWrite() body.");
4960
4961	return VINF_SUCCESS;
4962	}
4963
4964
4965	/**
4966	* Destruct a device instance.
4967	*
4968	* Most VM resources are freed by the VM. This callback is provided so that any non-VM
4969	* resources can be freed correctly.
4970	*
4971	* @param pDevIns The device instance data.
4972	*/
4973	static DECLCALLBACK(int) vgaR3Destruct(PPDMDEVINS pDevIns)
4974	{
4975	#ifdef VBE_NEW_DYN_LIST
4976	PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4977	LogFlow(("vgaR3Destruct:\n"));
4978
4979	/*
4980	* Free MM heap pointers.
4981	*/
4982	if (pData->pu8VBEExtraData)
4983	{
4984	MMR3HeapFree(pData->pu8VBEExtraData);
4985	pData->pu8VBEExtraData = NULL;
4986	}
4987	#endif
4988
4989	#if 0 /** @todo r=bird: We can't free the buffer here because it's still locked.
4990	* (That's the reason why we didn't do it earlier.) */
4991	/*
4992	* Free the VRAM.
4993	*/
4994	int rc = SUPPageFree(pData->vram_ptrHC, pData->vram_size >> PAGE_SHIFT);
4995	if (VBOX_FAILURE(rc))
4996	{
4997	AssertMsgFailed(("SUPPageFree(%p, %#x) -> %d\n", pData->vram_ptrHC, pData->vram_size, rc));
4998	return rc;
4999	}
5000	pData->vram_ptrHC = NULL;
5001	#endif
5002
5003	return VINF_SUCCESS;
5004	}
5005
5006
5007	/**
5008	* The device registration structure.
5009	*/
5010	const PDMDEVREG g_DeviceVga =
5011	{
5012	/* u32Version */
5013	PDM_DEVREG_VERSION,
5014	/* szDeviceName */
5015	"vga",
5016	/* szGCMod */
5017	"VBoxDDGC.gc",
5018	/* szR0Mod */
5019	"VBoxDDR0.r0",
5020	/* pszDescription */
5021	"VGA Adaptor with VESA extensions.",
5022	/* fFlags */
5023	PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT \| PDM_DEVREG_FLAGS_GC \| PDM_DEVREG_FLAGS_R0,
5024	/* fClass */
5025	PDM_DEVREG_CLASS_GRAPHICS,
5026	/* cMaxInstances */
5027	1,
5028	/* cbInstance */
5029	sizeof(VGASTATE),
5030	/* pfnConstruct */
5031	vgaR3Construct,
5032	/* pfnDestruct */
5033	vgaR3Destruct,
5034	/* pfnRelocate */
5035	vgaR3Relocate,
5036	/* pfnIOCtl */
5037	NULL,
5038	/* pfnPowerOn */
5039	NULL,
5040	/* pfnReset */
5041	vgaR3Reset,
5042	/* pfnSuspend */
5043	NULL,
5044	/* pfnResume */
5045	NULL,
5046	/* pfnAttach */
5047	vgaAttach,
5048	/* pfnDetach */
5049	vgaDetach,
5050	/* pfnQueryInterface */
5051	NULL,
5052	/* pfnInitComplete */
5053	NULL
5054	};
5055
5056	#endif /* !IN_RING3 */
5057	#endif /* VBOX */
5058	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5059
5060	/*
5061	* Local Variables:
5062	* nuke-trailing-whitespace-p:nil
5063	* End:
5064	*/

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.cpp@ 2993

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