DevVGA.cpp@ 87979

Last change on this file since 87979 was 87904, checked in by vboxsync, 4 years ago
DevVGA,DisplayImpl.cpp,pdmifs.h: Don't require EMT for pfnUpdateDisplayAll and pfnCopyRect. (Prep for moving real clock timers to thread.) bugref:9943
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1	/* $Id: DevVGA.cpp 87904 2021-03-01 18:14:51Z vboxsync $ */
2	/** @file
3	* DevVGA - VBox VGA/VESA device.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU VGA Emulator.
21	*
22	* Copyright (c) 2003 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Defined Constants And Macros *
46	*********************************************************************************************************************************/
47
48	/* WARNING!!! All defines that affect VGAState should be placed in DevVGA.h !!!
49	* NEVER place them here as this would lead to VGASTATE inconsistency
50	* across different .cpp files !!!
51	*/
52
53	#ifdef VBOX_WITH_HGSMI
54	#define PCIDEV_2_VGASTATE(pPciDev) ((PVGASTATE)((uintptr_t)pPciDev - RT_OFFSETOF(VGASTATE, Dev)))
55	#endif /* VBOX_WITH_HGSMI */
56
57	/* VGA text mode blinking constants (cursor and blinking chars). */
58	#define VGA_BLINK_PERIOD_FULL (RT_NS_100MS * 4) /*< Blink cycle length. /
59	#define VGA_BLINK_PERIOD_ON (RT_NS_100MS * 2) /*< How long cursor/text is visible. /
60
61	/* EGA compatible switch values (in high nibble).
62	* XENIX 2.1.x/2.2.x is known to rely on the switch values.
63	*/
64	#define EGA_SWITCHES 0x90 /* Off-on-on-off, high-res color EGA display. */
65
66
67	/*********************************************************************************************************************************
68	* Header Files *
69	*********************************************************************************************************************************/
70	#define LOG_GROUP LOG_GROUP_DEV_VGA
71	#include <VBox/vmm/pdmdev.h>
72	#include <VBox/vmm/pgm.h>
73	#include <VBox/AssertGuest.h>
74	#ifdef IN_RING3
75	# include <iprt/mem.h>
76	# include <iprt/ctype.h>
77	#endif /* IN_RING3 */
78	#include <iprt/assert.h>
79	#include <iprt/asm.h>
80	#include <iprt/file.h>
81	#include <iprt/time.h>
82	#include <iprt/string.h>
83	#include <iprt/uuid.h>
84
85	#include <iprt/formats/bmp.h>
86
87	#include <VBox/VMMDev.h>
88	#include <VBoxVideo.h>
89	#include <VBox/bioslogo.h>
90
91	/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
92	#include "DevVGA.h"
93
94	#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
95	# include "DevVGAModes.h"
96	# include <stdio.h> /* sscan */
97	#endif
98
99	#include "VBoxDD.h"
100	#include "VBoxDD2.h"
101
102	#ifdef VBOX_WITH_VMSVGA
103	#include "DevVGA-SVGA.h"
104	#endif
105
106
107	/*********************************************************************************************************************************
108	* Structures and Typedefs *
109	*********************************************************************************************************************************/
110
111	/** The BIOS boot menu text position, X. */
112	#define LOGO_F12TEXT_X 304
113	/** The BIOS boot menu text position, Y. */
114	#define LOGO_F12TEXT_Y 460
115
116	/** Width of the "Press F12 to select boot device." bitmap.
117	Anything that exceeds the limit of F12BootText below is filled with
118	background. */
119	#define LOGO_F12TEXT_WIDTH 286
120	/** Height of the boot device selection bitmap, see LOGO_F12TEXT_WIDTH. */
121	#define LOGO_F12TEXT_HEIGHT 12
122
123	/** The BIOS logo delay time (msec). */
124	#define LOGO_DELAY_TIME 2000
125
126	#define LOGO_MAX_WIDTH 640
127	#define LOGO_MAX_HEIGHT 480
128	#define LOGO_MAX_SIZE LOGO_MAX_WIDTH * LOGO_MAX_HEIGHT * 4
129
130
131	/*********************************************************************************************************************************
132	* Global Variables *
133	*********************************************************************************************************************************/
134	#ifdef IN_RING3
135	/* "Press F12 to select boot device." bitmap. */
136	static const uint8_t g_abLogoF12BootText[] =
137	{
138	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
139	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
140	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x7C,
141	0xF8, 0xF0, 0x01, 0xE0, 0x81, 0x9F, 0x3F, 0x00, 0x70, 0xF8, 0x00, 0xE0, 0xC3,
142	0x07, 0x0F, 0x1F, 0x3E, 0x70, 0x00, 0xF0, 0xE1, 0xC3, 0x07, 0x0E, 0x00, 0x6E,
143	0x7C, 0x60, 0xE0, 0xE1, 0xC3, 0x07, 0xC6, 0x80, 0x81, 0x31, 0x63, 0xC6, 0x00,
144	0x30, 0x80, 0x61, 0x0C, 0x00, 0x36, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
145	0x18, 0x36, 0x00, 0xCC, 0x8C, 0x19, 0xC3, 0x06, 0xC0, 0x8C, 0x31, 0x3C, 0x30,
146	0x8C, 0x19, 0x83, 0x31, 0x60, 0x60, 0x00, 0x0C, 0x18, 0x00, 0x0C, 0x60, 0x18,
147	0x00, 0x80, 0xC1, 0x18, 0x00, 0x30, 0x06, 0x60, 0x18, 0x30, 0x80, 0x01, 0x00,
148	0x33, 0x63, 0xC6, 0x30, 0x00, 0x30, 0x63, 0x80, 0x19, 0x0C, 0x03, 0x06, 0x00,
149	0x0C, 0x18, 0x18, 0xC0, 0x81, 0x03, 0x00, 0x03, 0x18, 0x0C, 0x00, 0x60, 0x30,
150	0x06, 0x00, 0x87, 0x01, 0x18, 0x06, 0x0C, 0x60, 0x00, 0xC0, 0xCC, 0x98, 0x31,
151	0x0C, 0x00, 0xCC, 0x18, 0x30, 0x0C, 0xC3, 0x80, 0x01, 0x00, 0x03, 0x66, 0xFE,
152	0x18, 0x30, 0x00, 0xC0, 0x02, 0x06, 0x06, 0x00, 0x18, 0x8C, 0x01, 0x60, 0xE0,
153	0x0F, 0x86, 0x3F, 0x03, 0x18, 0x00, 0x30, 0x33, 0x66, 0x0C, 0x03, 0x00, 0x33,
154	0xFE, 0x0C, 0xC3, 0x30, 0xE0, 0x0F, 0xC0, 0x87, 0x9B, 0x31, 0x63, 0xC6, 0x00,
155	0xF0, 0x80, 0x01, 0x03, 0x00, 0x06, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
156	0x18, 0x06, 0x00, 0x6C, 0x8C, 0x19, 0xC3, 0x00, 0x80, 0x8D, 0x31, 0xC3, 0x30,
157	0x8C, 0x19, 0x03, 0x30, 0xB3, 0xC3, 0x87, 0x0F, 0x1F, 0x00, 0x2C, 0x60, 0x80,
158	0x01, 0xE0, 0x87, 0x0F, 0x00, 0x3E, 0x7C, 0x60, 0xF0, 0xE1, 0xE3, 0x07, 0x00,
159	0x0F, 0x3E, 0x7C, 0xFC, 0x00, 0xC0, 0xC3, 0xC7, 0x30, 0x0E, 0x3E, 0x7C, 0x00,
160	0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x1E, 0xC0, 0x00, 0x60, 0x00,
161	0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x00, 0x00,
162	0x0C, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00,
163	0x00, 0x00, 0x00, 0xC0, 0x0C, 0x87, 0x31, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
164	0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x30,
165	0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
166	0xF8, 0x83, 0xC1, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00,
167	0x00, 0x04, 0x00, 0x0E, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x30,
168	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
169	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
170	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
171	};
172	#endif /* IN_RING3 */
173
174	#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* Till the end of the file - doesn't count indent wise. */
175
176	#ifdef _MSC_VER
177	# pragma warning(push)
178	# pragma warning(disable:4310 4245) /* Buggy warnings: cast truncates constant value; conversion from 'int' to 'const uint8_t', signed/unsigned mismatch */
179	#endif
180
181	/* force some bits to zero */
182	static const uint8_t sr_mask[8] = {
183	(uint8_t)~0xfc,
184	(uint8_t)~0xc2,
185	(uint8_t)~0xf0,
186	(uint8_t)~0xc0,
187	(uint8_t)~0xf1,
188	(uint8_t)~0xff,
189	(uint8_t)~0xff,
190	(uint8_t)~0x01,
191	};
192
193	static const uint8_t gr_mask[16] = {
194	(uint8_t)~0xf0, /* 0x00 */
195	(uint8_t)~0xf0, /* 0x01 */
196	(uint8_t)~0xf0, /* 0x02 */
197	(uint8_t)~0xe0, /* 0x03 */
198	(uint8_t)~0xfc, /* 0x04 */
199	(uint8_t)~0x84, /* 0x05 */
200	(uint8_t)~0xf0, /* 0x06 */
201	(uint8_t)~0xf0, /* 0x07 */
202	(uint8_t)~0x00, /* 0x08 */
203	(uint8_t)~0xff, /* 0x09 */
204	(uint8_t)~0xff, /* 0x0a */
205	(uint8_t)~0xff, /* 0x0b */
206	(uint8_t)~0xff, /* 0x0c */
207	(uint8_t)~0xff, /* 0x0d */
208	(uint8_t)~0xff, /* 0x0e */
209	(uint8_t)~0xff, /* 0x0f */
210	};
211
212	#ifdef _MSC_VER
213	# pragma warning(pop)
214	#endif
215
216	#define cbswap_32(__x) \
217	((uint32_t)((((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) \| \
218	(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) \| \
219	(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) \| \
220	(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
221
222	#ifdef WORDS_BIGENDIAN
223	# define PAT(x) cbswap_32(x)
224	#else
225	# define PAT(x) (x)
226	#endif
227
228	#ifdef WORDS_BIGENDIAN
229	# define BIG 1
230	#else
231	# define BIG 0
232	#endif
233
234	#ifdef WORDS_BIGENDIAN
235	#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
236	#else
237	#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
238	#endif
239
240	static const uint32_t mask16[16] = {
241	PAT(0x00000000),
242	PAT(0x000000ff),
243	PAT(0x0000ff00),
244	PAT(0x0000ffff),
245	PAT(0x00ff0000),
246	PAT(0x00ff00ff),
247	PAT(0x00ffff00),
248	PAT(0x00ffffff),
249	PAT(0xff000000),
250	PAT(0xff0000ff),
251	PAT(0xff00ff00),
252	PAT(0xff00ffff),
253	PAT(0xffff0000),
254	PAT(0xffff00ff),
255	PAT(0xffffff00),
256	PAT(0xffffffff),
257	};
258
259	#undef PAT
260
261	#ifdef WORDS_BIGENDIAN
262	# define PAT(x) (x)
263	#else
264	# define PAT(x) cbswap_32(x)
265	#endif
266
267	#ifdef IN_RING3
268
269	static const uint32_t dmask16[16] = {
270	PAT(0x00000000),
271	PAT(0x000000ff),
272	PAT(0x0000ff00),
273	PAT(0x0000ffff),
274	PAT(0x00ff0000),
275	PAT(0x00ff00ff),
276	PAT(0x00ffff00),
277	PAT(0x00ffffff),
278	PAT(0xff000000),
279	PAT(0xff0000ff),
280	PAT(0xff00ff00),
281	PAT(0xff00ffff),
282	PAT(0xffff0000),
283	PAT(0xffff00ff),
284	PAT(0xffffff00),
285	PAT(0xffffffff),
286	};
287
288	static const uint32_t dmask4[4] = {
289	PAT(0x00000000),
290	PAT(0x0000ffff),
291	PAT(0xffff0000),
292	PAT(0xffffffff),
293	};
294
295	static uint32_t expand4[256];
296	static uint16_t expand2[256];
297	static uint8_t expand4to8[16];
298
299	#endif /* IN_RING3 */
300
301
302	/**
303	* Set a VRAM page dirty.
304	*
305	* @param pThis VGA instance data.
306	* @param offVRAM The VRAM offset of the page to set.
307	*/
308	DECLINLINE(void) vgaR3MarkDirty(PVGASTATE pThis, RTGCPHYS offVRAM)
309	{
310	AssertMsg(offVRAM < pThis->vram_size, ("offVRAM = %p, pThis->vram_size = %p\n", offVRAM, pThis->vram_size));
311	ASMBitSet(&pThis->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
312	pThis->fHasDirtyBits = true;
313	}
314
315	/**
316	* Tests if a VRAM page is dirty.
317	*
318	* @returns true if dirty.
319	* @returns false if clean.
320	* @param pThis VGA instance data.
321	* @param offVRAM The VRAM offset of the page to check.
322	*/
323	DECLINLINE(bool) vgaIsDirty(PVGASTATE pThis, RTGCPHYS offVRAM)
324	{
325	AssertMsg(offVRAM < pThis->vram_size, ("offVRAM = %p, pThis->vram_size = %p\n", offVRAM, pThis->vram_size));
326	return ASMBitTest(&pThis->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
327	}
328
329	#ifdef IN_RING3
330	/**
331	* Reset dirty flags in a give range.
332	*
333	* @param pThis VGA instance data.
334	* @param offVRAMStart Offset into the VRAM buffer of the first page.
335	* @param offVRAMEnd Offset into the VRAM buffer of the last page - exclusive.
336	*/
337	DECLINLINE(void) vgaR3ResetDirty(PVGASTATE pThis, RTGCPHYS offVRAMStart, RTGCPHYS offVRAMEnd)
338	{
339	Assert(offVRAMStart < pThis->vram_size);
340	Assert(offVRAMEnd <= pThis->vram_size);
341	Assert(offVRAMStart < offVRAMEnd);
342	ASMBitClearRange(&pThis->au32DirtyBitmap[0], offVRAMStart >> PAGE_SHIFT, offVRAMEnd >> PAGE_SHIFT);
343	}
344	#endif /* IN_RING3 */
345
346	/* Update the values needed for calculating Vertical Retrace and
347	* Display Enable status bits more or less accurately. The Display Enable
348	* bit is set (indicating disabled display signal) when either the
349	* horizontal (hblank) or vertical (vblank) blanking is active. The
350	* Vertical Retrace bit is set when vertical retrace (vsync) is active.
351	* Unless the CRTC is horribly misprogrammed, vsync implies vblank.
352	*/
353	static void vga_update_retrace_state(PVGASTATE pThis)
354	{
355	unsigned htotal_cclks, vtotal_lines, chars_per_sec;
356	unsigned hblank_start_cclk, hblank_end_cclk, hblank_width, hblank_skew_cclks;
357	unsigned vsync_start_line, vsync_end, vsync_width;
358	unsigned vblank_start_line, vblank_end, vblank_width;
359	unsigned char_dots, clock_doubled, clock_index;
360	const int clocks[] = {25175000, 28322000, 25175000, 25175000};
361	vga_retrace_s *r = &pThis->retrace_state;
362
363	/* For horizontal timings, we only care about the blanking start/end. */
364	htotal_cclks = pThis->cr[0x00] + 5;
365	hblank_start_cclk = pThis->cr[0x02];
366	hblank_end_cclk = (pThis->cr[0x03] & 0x1f) + ((pThis->cr[0x05] & 0x80) >> 2);
367	hblank_skew_cclks = (pThis->cr[0x03] >> 5) & 3;
368
369	/* For vertical timings, we need both the blanking start/end... */
370	vtotal_lines = pThis->cr[0x06] + ((pThis->cr[0x07] & 1) << 8) + ((pThis->cr[0x07] & 0x20) << 4) + 2;
371	vblank_start_line = pThis->cr[0x15] + ((pThis->cr[0x07] & 8) << 5) + ((pThis->cr[0x09] & 0x20) << 4);
372	vblank_end = pThis->cr[0x16];
373	/* ... and the vertical retrace (vsync) start/end. */
374	vsync_start_line = pThis->cr[0x10] + ((pThis->cr[0x07] & 4) << 6) + ((pThis->cr[0x07] & 0x80) << 2);
375	vsync_end = pThis->cr[0x11] & 0xf;
376
377	/* Calculate the blanking and sync widths. The way it's implemented in
378	* the VGA with limited-width compare counters is quite a piece of work.
379	*/
380	hblank_width = (hblank_end_cclk - hblank_start_cclk) & 0x3f;/* 6 bits */
381	vblank_width = (vblank_end - vblank_start_line) & 0xff; /* 8 bits */
382	vsync_width = (vsync_end - vsync_start_line) & 0xf; /* 4 bits */
383
384	/* Calculate the dot and character clock rates. */
385	clock_doubled = (pThis->sr[0x01] >> 3) & 1; /* Clock doubling bit. */
386	clock_index = (pThis->msr >> 2) & 3;
387	char_dots = (pThis->sr[0x01] & 1) ? 8 : 9; /* 8 or 9 dots per cclk. */
388
389	chars_per_sec = clocks[clock_index] / char_dots;
390	Assert(chars_per_sec); /* Can't possibly be zero. */
391
392	htotal_cclks <<= clock_doubled;
393
394	/* Calculate the number of cclks per entire frame. */
395	r->frame_cclks = vtotal_lines * htotal_cclks;
396	Assert(r->frame_cclks); /* Can't possibly be zero. */
397
398	if (r->v_freq_hz) { /* Could be set to emulate a specific rate. */
399	r->cclk_ns = 1000000000 / (r->frame_cclks * r->v_freq_hz);
400	} else {
401	r->cclk_ns = 1000000000 / chars_per_sec;
402	}
403	Assert(r->cclk_ns);
404	r->frame_ns = r->frame_cclks * r->cclk_ns;
405
406	/* Calculate timings in cclks/lines. Stored but not directly used. */
407	r->hb_start = hblank_start_cclk + hblank_skew_cclks;
408	r->hb_end = hblank_start_cclk + hblank_width + hblank_skew_cclks;
409	r->h_total = htotal_cclks;
410	Assert(r->h_total); /* Can't possibly be zero. */
411
412	r->vb_start = vblank_start_line;
413	r->vb_end = vblank_start_line + vblank_width + 1;
414	r->vs_start = vsync_start_line;
415	r->vs_end = vsync_start_line + vsync_width + 1;
416
417	/* Calculate timings in nanoseconds. For easier comparisons, the frame
418	* is considered to start at the beginning of the vertical and horizontal
419	* blanking period.
420	*/
421	r->h_total_ns = htotal_cclks * r->cclk_ns;
422	r->hb_end_ns = hblank_width * r->cclk_ns;
423	r->vb_end_ns = vblank_width * r->h_total_ns;
424	r->vs_start_ns = (r->vs_start - r->vb_start) * r->h_total_ns;
425	r->vs_end_ns = (r->vs_end - r->vb_start) * r->h_total_ns;
426	Assert(r->h_total_ns); /* See h_total. */
427	}
428
429	static uint8_t vga_retrace(PPDMDEVINS pDevIns, PVGASTATE pThis)
430	{
431	vga_retrace_s *r = &pThis->retrace_state;
432
433	if (r->frame_ns) {
434	uint8_t val = pThis->st01 & ~(ST01_V_RETRACE \| ST01_DISP_ENABLE);
435	unsigned cur_frame_ns, cur_line_ns;
436	uint64_t time_ns;
437
438	time_ns = PDMDevHlpTMTimeVirtGetNano(pDevIns);
439
440	/* Determine the time within the frame. */
441	cur_frame_ns = time_ns % r->frame_ns;
442
443	/* See if we're in the vertical blanking period... */
444	if (cur_frame_ns < r->vb_end_ns) {
445	val \|= ST01_DISP_ENABLE;
446	/* ... and additionally in the vertical sync period. */
447	if (cur_frame_ns >= r->vs_start_ns && cur_frame_ns <= r->vs_end_ns)
448	val \|= ST01_V_RETRACE;
449	} else {
450	/* Determine the time within the current scanline. */
451	cur_line_ns = cur_frame_ns % r->h_total_ns;
452	/* See if we're in the horizontal blanking period. */
453	if (cur_line_ns < r->hb_end_ns)
454	val \|= ST01_DISP_ENABLE;
455	}
456	return val;
457	} else {
458	return pThis->st01 ^ (ST01_V_RETRACE \| ST01_DISP_ENABLE);
459	}
460	}
461
462	int vga_ioport_invalid(PVGASTATE pThis, uint32_t addr)
463	{
464	if (pThis->msr & MSR_COLOR_EMULATION) {
465	/* Color */
466	return (addr >= 0x3b0 && addr <= 0x3bf);
467	} else {
468	/* Monochrome */
469	return (addr >= 0x3d0 && addr <= 0x3df);
470	}
471	}
472
473	static uint32_t vga_ioport_read(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t addr)
474	{
475	int val, index;
476
477	/* check port range access depending on color/monochrome mode */
478	if (vga_ioport_invalid(pThis, addr)) {
479	val = 0xff;
480	Log(("VGA: following read ignored\n"));
481	} else {
482	switch(addr) {
483	case 0x3c0:
484	if (pThis->ar_flip_flop == 0) {
485	val = pThis->ar_index;
486	} else {
487	val = 0;
488	}
489	break;
490	case 0x3c1:
491	index = pThis->ar_index & 0x1f;
492	if (index < 21)
493	val = pThis->ar[index];
494	else
495	val = 0;
496	break;
497	case 0x3c2:
498	val = pThis->st00;
499	break;
500	case 0x3c4:
501	val = pThis->sr_index;
502	break;
503	case 0x3c5:
504	val = pThis->sr[pThis->sr_index];
505	Log2(("vga: read SR%x = 0x%02x\n", pThis->sr_index, val));
506	break;
507	case 0x3c7:
508	val = pThis->dac_state;
509	break;
510	case 0x3c8:
511	val = pThis->dac_write_index;
512	break;
513	case 0x3c9:
514	Assert(pThis->dac_sub_index < 3);
515	val = pThis->palette[pThis->dac_read_index * 3 + pThis->dac_sub_index];
516	if (++pThis->dac_sub_index == 3) {
517	pThis->dac_sub_index = 0;
518	pThis->dac_read_index++;
519	}
520	break;
521	case 0x3ca:
522	val = pThis->fcr;
523	break;
524	case 0x3cc:
525	val = pThis->msr;
526	break;
527	case 0x3ce:
528	val = pThis->gr_index;
529	break;
530	case 0x3cf:
531	val = pThis->gr[pThis->gr_index];
532	Log2(("vga: read GR%x = 0x%02x\n", pThis->gr_index, val));
533	break;
534	case 0x3b4:
535	case 0x3d4:
536	val = pThis->cr_index;
537	break;
538	case 0x3b5:
539	case 0x3d5:
540	val = pThis->cr[pThis->cr_index];
541	Log2(("vga: read CR%x = 0x%02x\n", pThis->cr_index, val));
542	break;
543	case 0x3ba:
544	case 0x3da:
545	val = pThis->st01 = vga_retrace(pDevIns, pThis);
546	pThis->ar_flip_flop = 0;
547	break;
548	default:
549	val = 0x00;
550	break;
551	}
552	}
553	Log(("VGA: read addr=0x%04x data=0x%02x\n", addr, val));
554	return val;
555	}
556
557	static void vga_ioport_write(PPDMDEVINS pDevIns, PVGASTATE pThis, uint32_t addr, uint32_t val)
558	{
559	int index;
560
561	Log(("VGA: write addr=0x%04x data=0x%02x\n", addr, val));
562
563	/* check port range access depending on color/monochrome mode */
564	if (vga_ioport_invalid(pThis, addr)) {
565	Log(("VGA: previous write ignored\n"));
566	return;
567	}
568
569	switch(addr) {
570	case 0x3c0:
571	case 0x3c1:
572	if (pThis->ar_flip_flop == 0) {
573	val &= 0x3f;
574	pThis->ar_index = val;
575	} else {
576	index = pThis->ar_index & 0x1f;
577	switch(index) {
578	case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
579	case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
580	pThis->ar[index] = val & 0x3f;
581	break;
582	case 0x10:
583	pThis->ar[index] = val & ~0x10;
584	break;
585	case 0x11:
586	pThis->ar[index] = val;
587	break;
588	case 0x12:
589	pThis->ar[index] = val & ~0xc0;
590	break;
591	case 0x13:
592	pThis->ar[index] = val & ~0xf0;
593	break;
594	case 0x14:
595	pThis->ar[index] = val & ~0xf0;
596	break;
597	default:
598	break;
599	}
600	}
601	pThis->ar_flip_flop ^= 1;
602	break;
603	case 0x3c2:
604	pThis->msr = val & ~0x10;
605	if (pThis->fRealRetrace)
606	vga_update_retrace_state(pThis);
607	/* The two clock select bits also determine which of the four switches
608	* is reflected in bit 4 of Input Status Register 0.
609	* This is EGA compatible behavior. See the IBM EGA Tech Ref.
610	*/
611	pThis->st00 = (pThis->st00 & ~0x10) \| ((EGA_SWITCHES >> ((val >> 2) & 0x3) & 0x10));
612	break;
613	case 0x3c4:
614	pThis->sr_index = val & 7;
615	break;
616	case 0x3c5:
617	Log2(("vga: write SR%x = 0x%02x\n", pThis->sr_index, val));
618	pThis->sr[pThis->sr_index] = val & sr_mask[pThis->sr_index];
619	/* Allow SR07 to disable VBE. */
620	if (pThis->sr_index == 0x07 && !(val & 1))
621	{
622	pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] = VBE_DISPI_DISABLED;
623	pThis->bank_offset = 0;
624	}
625	if (pThis->fRealRetrace && pThis->sr_index == 0x01)
626	vga_update_retrace_state(pThis);
627	#ifndef IN_RC
628	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
629	if ( pThis->sr_index == 4 /* mode */
630	\|\| pThis->sr_index == 2 /* plane mask */)
631	{
632	if (pThis->fRemappedVGA)
633	{
634	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
635	pThis->fRemappedVGA = false;
636	}
637	}
638	#endif
639	break;
640	case 0x3c7:
641	pThis->dac_read_index = val;
642	pThis->dac_sub_index = 0;
643	pThis->dac_state = 3;
644	break;
645	case 0x3c8:
646	pThis->dac_write_index = val;
647	pThis->dac_sub_index = 0;
648	pThis->dac_state = 0;
649	break;
650	case 0x3c9:
651	Assert(pThis->dac_sub_index < 3);
652	pThis->dac_cache[pThis->dac_sub_index] = val;
653	if (++pThis->dac_sub_index == 3) {
654	memcpy(&pThis->palette[pThis->dac_write_index * 3], pThis->dac_cache, 3);
655	pThis->dac_sub_index = 0;
656	pThis->dac_write_index++;
657	}
658	break;
659	case 0x3ce:
660	pThis->gr_index = val & 0x0f;
661	break;
662	case 0x3cf:
663	Log2(("vga: write GR%x = 0x%02x\n", pThis->gr_index, val));
664	Assert(pThis->gr_index < RT_ELEMENTS(gr_mask));
665	pThis->gr[pThis->gr_index] = val & gr_mask[pThis->gr_index];
666
667	#ifndef IN_RC
668	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
669	if (pThis->gr_index == 6 /* memory map mode */)
670	{
671	if (pThis->fRemappedVGA)
672	{
673	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
674	pThis->fRemappedVGA = false;
675	}
676	}
677	#endif
678	break;
679
680	case 0x3b4:
681	case 0x3d4:
682	pThis->cr_index = val;
683	break;
684	case 0x3b5:
685	case 0x3d5:
686	Log2(("vga: write CR%x = 0x%02x\n", pThis->cr_index, val));
687	/* handle CR0-7 protection */
688	if ((pThis->cr[0x11] & 0x80) && pThis->cr_index <= 7) {
689	/* can always write bit 4 of CR7 */
690	if (pThis->cr_index == 7)
691	pThis->cr[7] = (pThis->cr[7] & ~0x10) \| (val & 0x10);
692	return;
693	}
694	pThis->cr[pThis->cr_index] = val;
695
696	if (pThis->fRealRetrace) {
697	/* The following registers are only updated during a mode set. */
698	switch(pThis->cr_index) {
699	case 0x00:
700	case 0x02:
701	case 0x03:
702	case 0x05:
703	case 0x06:
704	case 0x07:
705	case 0x09:
706	case 0x10:
707	case 0x11:
708	case 0x15:
709	case 0x16:
710	vga_update_retrace_state(pThis);
711	break;
712	}
713	}
714	break;
715	case 0x3ba:
716	case 0x3da:
717	pThis->fcr = val & 0x10;
718	break;
719	}
720	}
721
722	#ifdef CONFIG_BOCHS_VBE
723
724	static uint32_t vbe_read_cfg(PVGASTATE pThis)
725	{
726	const uint16_t u16Cfg = pThis->vbe_regs[VBE_DISPI_INDEX_CFG];
727	const uint16_t u16Id = u16Cfg & VBE_DISPI_CFG_MASK_ID;
728	const bool fQuerySupport = RT_BOOL(u16Cfg & VBE_DISPI_CFG_MASK_SUPPORT);
729
730	uint32_t val = 0;
731	switch (u16Id)
732	{
733	case VBE_DISPI_CFG_ID_VERSION: val = 1; break;
734	case VBE_DISPI_CFG_ID_VRAM_SIZE: val = pThis->vram_size; break;
735	case VBE_DISPI_CFG_ID_3D: val = pThis->f3DEnabled; break;
736	# ifdef VBOX_WITH_VMSVGA
737	case VBE_DISPI_CFG_ID_VMSVGA: val = pThis->fVMSVGAEnabled; break;
738	# endif
739	default:
740	return 0; /* Not supported. */
741	}
742
743	return fQuerySupport ? 1 : val;
744	}
745
746	static uint32_t vbe_ioport_read_index(PVGASTATE pThis, uint32_t addr)
747	{
748	uint32_t val = pThis->vbe_index;
749	NOREF(addr);
750	return val;
751	}
752
753	static uint32_t vbe_ioport_read_data(PVGASTATE pThis, uint32_t addr)
754	{
755	uint32_t val;
756	NOREF(addr);
757
758	uint16_t const idxVbe = pThis->vbe_index;
759	if (idxVbe < VBE_DISPI_INDEX_NB)
760	{
761	RT_UNTRUSTED_VALIDATED_FENCE();
762	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS)
763	{
764	switch (idxVbe)
765	{
766	/* XXX: do not hardcode ? */
767	case VBE_DISPI_INDEX_XRES:
768	val = VBE_DISPI_MAX_XRES;
769	break;
770	case VBE_DISPI_INDEX_YRES:
771	val = VBE_DISPI_MAX_YRES;
772	break;
773	case VBE_DISPI_INDEX_BPP:
774	val = VBE_DISPI_MAX_BPP;
775	break;
776	default:
777	Assert(idxVbe < VBE_DISPI_INDEX_NB);
778	val = pThis->vbe_regs[idxVbe];
779	break;
780	}
781	}
782	else
783	{
784	switch (idxVbe)
785	{
786	case VBE_DISPI_INDEX_VBOX_VIDEO:
787	/* Reading from the port means that the old additions are requesting the number of monitors. */
788	val = 1;
789	break;
790	case VBE_DISPI_INDEX_CFG:
791	val = vbe_read_cfg(pThis);
792	break;
793	default:
794	Assert(idxVbe < VBE_DISPI_INDEX_NB);
795	val = pThis->vbe_regs[idxVbe];
796	break;
797	}
798	}
799	}
800	else
801	val = 0;
802	Log(("VBE: read index=0x%x val=0x%x\n", idxVbe, val));
803	return val;
804	}
805
806	# define VBE_PITCH_ALIGN 4 /* Align pitch to 32 bits - Qt requires that. */
807
808	/* Calculate scanline pitch based on bit depth and width in pixels. */
809	static uint32_t calc_line_pitch(uint16_t bpp, uint16_t width)
810	{
811	uint32_t pitch, aligned_pitch;
812
813	if (bpp <= 4)
814	pitch = width >> 1;
815	else
816	pitch = width * ((bpp + 7) >> 3);
817
818	/* Align the pitch to some sensible value. */
819	aligned_pitch = (pitch + (VBE_PITCH_ALIGN - 1)) & ~(VBE_PITCH_ALIGN - 1);
820	if (aligned_pitch != pitch)
821	Log(("VBE: Line pitch %d aligned to %d bytes\n", pitch, aligned_pitch));
822
823	return aligned_pitch;
824	}
825
826	static void recalculate_data(PVGASTATE pThis)
827	{
828	uint16_t cBPP = pThis->vbe_regs[VBE_DISPI_INDEX_BPP];
829	uint16_t cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
830	uint16_t cX = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
831	if (!cBPP \|\| !cX)
832	return; /* Not enough data has been set yet. */
833	uint32_t cbLinePitch = calc_line_pitch(cBPP, cVirtWidth);
834	if (!cbLinePitch)
835	cbLinePitch = calc_line_pitch(cBPP, cX);
836	if (!cbLinePitch)
837	return;
838	uint32_t cVirtHeight = pThis->vram_size / cbLinePitch;
839	uint16_t offX = pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
840	uint16_t offY = pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
841	uint32_t offStart = cbLinePitch * offY;
842	if (cBPP == 4)
843	offStart += offX >> 1;
844	else
845	offStart += offX * ((cBPP + 7) >> 3);
846	offStart >>= 2;
847	pThis->vbe_line_offset = RT_MIN(cbLinePitch, pThis->vram_size);
848	pThis->vbe_start_addr = RT_MIN(offStart, pThis->vram_size);
849
850	/* The VBE_DISPI_INDEX_VIRT_HEIGHT is used to prevent setting resolution bigger than
851	* the VRAM size permits. It is used instead of VBE_DISPI_INDEX_YRES only in case
852	* pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] < pThis->vbe_regs[VBE_DISPI_INDEX_YRES].
853	* Note that VBE_DISPI_INDEX_VIRT_HEIGHT has to be clipped to UINT16_MAX, which happens
854	* with small resolutions and big VRAM. */
855	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = cVirtHeight >= UINT16_MAX ? UINT16_MAX : (uint16_t)cVirtHeight;
856	}
857
858	static void vbe_ioport_write_index(PVGASTATE pThis, uint32_t addr, uint32_t val)
859	{
860	pThis->vbe_index = val;
861	NOREF(addr);
862	}
863
864	static VBOXSTRICTRC vbe_ioport_write_data(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t addr, uint32_t val)
865	{
866	uint32_t max_bank;
867	RT_NOREF(pThisCC, addr);
868
869	if (pThis->vbe_index <= VBE_DISPI_INDEX_NB) {
870	bool fRecalculate = false;
871	Log(("VBE: write index=0x%x val=0x%x\n", pThis->vbe_index, val));
872	switch(pThis->vbe_index) {
873	case VBE_DISPI_INDEX_ID:
874	if (val == VBE_DISPI_ID0 \|\|
875	val == VBE_DISPI_ID1 \|\|
876	val == VBE_DISPI_ID2 \|\|
877	val == VBE_DISPI_ID3 \|\|
878	val == VBE_DISPI_ID4 \|\|
879	/* VBox extensions. */
880	val == VBE_DISPI_ID_VBOX_VIDEO \|\|
881	val == VBE_DISPI_ID_ANYX \|\|
882	# ifdef VBOX_WITH_HGSMI
883	val == VBE_DISPI_ID_HGSMI \|\|
884	# endif
885	val == VBE_DISPI_ID_CFG)
886	{
887	pThis->vbe_regs[pThis->vbe_index] = val;
888	}
889	break;
890	case VBE_DISPI_INDEX_XRES:
891	if (val <= VBE_DISPI_MAX_XRES)
892	{
893	pThis->vbe_regs[pThis->vbe_index] = val;
894	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = val;
895	fRecalculate = true;
896	}
897	break;
898	case VBE_DISPI_INDEX_YRES:
899	if (val <= VBE_DISPI_MAX_YRES)
900	pThis->vbe_regs[pThis->vbe_index] = val;
901	break;
902	case VBE_DISPI_INDEX_BPP:
903	if (val == 0)
904	val = 8;
905	if (val == 4 \|\| val == 8 \|\| val == 15 \|\|
906	val == 16 \|\| val == 24 \|\| val == 32) {
907	pThis->vbe_regs[pThis->vbe_index] = val;
908	fRecalculate = true;
909	}
910	break;
911	case VBE_DISPI_INDEX_BANK:
912	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] <= 4)
913	max_bank = pThis->vbe_bank_max >> 2; /* Each bank really covers 256K */
914	else
915	max_bank = pThis->vbe_bank_max;
916	/* Old software may pass garbage in the high byte of bank. If the maximum
917	* bank fits into a single byte, toss the high byte the user supplied.
918	*/
919	if (max_bank < 0x100)
920	val &= 0xff;
921	if (val > max_bank)
922	val = max_bank;
923	pThis->vbe_regs[pThis->vbe_index] = val;
924	pThis->bank_offset = (val << 16);
925
926	# ifndef IN_RC
927	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
928	if (pThis->fRemappedVGA)
929	{
930	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
931	pThis->fRemappedVGA = false;
932	}
933	# endif
934	break;
935
936	case VBE_DISPI_INDEX_ENABLE:
937	# ifndef IN_RING3
938	return VINF_IOM_R3_IOPORT_WRITE;
939	# else
940	{
941	if ((val & VBE_DISPI_ENABLED) &&
942	!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
943	int h, shift_control;
944	/* Check the values before we screw up with a resolution which is too big or small. */
945	size_t cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
946	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
947	cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
948	else
949	cb = pThis->vbe_regs[VBE_DISPI_INDEX_XRES] * ((pThis->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
950	cb *= pThis->vbe_regs[VBE_DISPI_INDEX_YRES];
951	uint16_t cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
952	if (!cVirtWidth)
953	cVirtWidth = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
954	if ( !cVirtWidth
955	\|\| !pThis->vbe_regs[VBE_DISPI_INDEX_YRES]
956	\|\| cb > pThis->vram_size)
957	{
958	AssertMsgFailed(("VIRT WIDTH=%d YRES=%d cb=%d vram_size=%d\n",
959	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], pThis->vbe_regs[VBE_DISPI_INDEX_YRES], cb, pThis->vram_size));
960	return VINF_SUCCESS; /* Note: silent failure like before */
961	}
962
963	/* When VBE interface is enabled, it is reset. */
964	pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
965	pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
966	fRecalculate = true;
967
968	/* clear the screen (should be done in BIOS) */
969	if (!(val & VBE_DISPI_NOCLEARMEM)) {
970	uint16_t cY = RT_MIN(pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
971	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
972	uint16_t cbLinePitch = pThis->vbe_line_offset;
973	memset(pThisCC->pbVRam, 0,
974	cY * cbLinePitch);
975	}
976
977	/* we initialize the VGA graphic mode (should be done
978	in BIOS) */
979	pThis->gr[0x06] = (pThis->gr[0x06] & ~0x0c) \| 0x05; /* graphic mode + memory map 1 */
980	pThis->cr[0x17] \|= 3; /* no CGA modes */
981	pThis->cr[0x13] = pThis->vbe_line_offset >> 3;
982	/* width */
983	pThis->cr[0x01] = (cVirtWidth >> 3) - 1;
984	/* height (only meaningful if < 1024) */
985	h = pThis->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
986	pThis->cr[0x12] = h;
987	pThis->cr[0x07] = (pThis->cr[0x07] & ~0x42) \|
988	((h >> 7) & 0x02) \| ((h >> 3) & 0x40);
989	/* line compare to 1023 */
990	pThis->cr[0x18] = 0xff;
991	pThis->cr[0x07] \|= 0x10;
992	pThis->cr[0x09] \|= 0x40;
993
994	if (pThis->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
995	shift_control = 0;
996	pThis->sr[0x01] &= ~8; /* no double line */
997	} else {
998	shift_control = 2;
999	pThis->sr[4] \|= 0x08; /* set chain 4 mode */
1000	pThis->sr[2] \|= 0x0f; /* activate all planes */
1001	/* Indicate non-VGA mode in SR07. */
1002	pThis->sr[7] \|= 1;
1003	}
1004	pThis->gr[0x05] = (pThis->gr[0x05] & ~0x60) \| (shift_control << 5);
1005	pThis->cr[0x09] &= ~0x9f; /* no double scan */
1006	/* sunlover 30.05.2007
1007	* The ar_index remains with bit 0x20 cleared after a switch from fullscreen
1008	* DOS mode on Windows XP guest. That leads to GMODE_BLANK in vgaR3UpdateDisplay.
1009	* But the VBE mode is graphics, so not a blank anymore.
1010	*/
1011	pThis->ar_index \|= 0x20;
1012	} else {
1013	/* XXX: the bios should do that */
1014	/* sunlover 21.12.2006
1015	* Here is probably more to reset. When this was executed in GC
1016	* then the update functions could not detect a mode change.
1017	* Or may be these update function should take the pThis->vbe_regs[pThis->vbe_index]
1018	* into account when detecting a mode change.
1019	*
1020	* The 'mode reset not detected' problem is now fixed by executing the
1021	* VBE_DISPI_INDEX_ENABLE case always in RING3 in order to call the
1022	* LFBChange callback.
1023	*/
1024	pThis->bank_offset = 0;
1025	}
1026	pThis->vbe_regs[pThis->vbe_index] = val;
1027	/*
1028	* LFB video mode is either disabled or changed. Notify the display
1029	* and reset VBVA.
1030	*/
1031	pThisCC->pDrv->pfnLFBModeChange(pThisCC->pDrv, (val & VBE_DISPI_ENABLED) != 0);
1032	# ifdef VBOX_WITH_HGSMI
1033	VBVAOnVBEChanged(pThis, pThisCC);
1034	# endif
1035
1036	/* The VGA region is (could be) affected by this change; reset all aliases we've created. */
1037	if (pThis->fRemappedVGA)
1038	{
1039	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
1040	pThis->fRemappedVGA = false;
1041	}
1042	break;
1043	}
1044	# endif /* IN_RING3 */
1045	case VBE_DISPI_INDEX_VIRT_WIDTH:
1046	case VBE_DISPI_INDEX_X_OFFSET:
1047	case VBE_DISPI_INDEX_Y_OFFSET:
1048	{
1049	pThis->vbe_regs[pThis->vbe_index] = val;
1050	fRecalculate = true;
1051	}
1052	break;
1053	case VBE_DISPI_INDEX_VBOX_VIDEO:
1054	# ifndef IN_RING3
1055	return VINF_IOM_R3_IOPORT_WRITE;
1056	# else
1057	/* Changes in the VGA device are minimal. The device is bypassed. The driver does all work. */
1058	if (val == VBOX_VIDEO_DISABLE_ADAPTER_MEMORY)
1059	pThisCC->pDrv->pfnProcessAdapterData(pThisCC->pDrv, NULL, 0);
1060	else if (val == VBOX_VIDEO_INTERPRET_ADAPTER_MEMORY)
1061	pThisCC->pDrv->pfnProcessAdapterData(pThisCC->pDrv, pThisCC->pbVRam, pThis->vram_size);
1062	else if ((val & 0xFFFF0000) == VBOX_VIDEO_INTERPRET_DISPLAY_MEMORY_BASE)
1063	pThisCC->pDrv->pfnProcessDisplayData(pThisCC->pDrv, pThisCC->pbVRam, val & 0xFFFF);
1064	# endif /* IN_RING3 */
1065	break;
1066	case VBE_DISPI_INDEX_CFG:
1067	pThis->vbe_regs[pThis->vbe_index] = val;
1068	break;
1069	default:
1070	break;
1071	}
1072
1073	if (fRecalculate)
1074	recalculate_data(pThis);
1075	}
1076	return VINF_SUCCESS;
1077	}
1078
1079	#endif /* CONFIG_BOCHS_VBE */
1080
1081	/* called for accesses between 0xa0000 and 0xc0000 */
1082	static uint32_t vga_mem_readb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS addr, int *prc)
1083	{
1084	int plane;
1085	uint32_t ret;
1086
1087	Log3(("vga: read [0x%x] -> ", addr));
1088
1089	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
1090	/* VMSVGA keeps the VGA and SVGA framebuffers separate unlike this boch-based
1091	VGA implementation, so we fake it by going to ring-3 and using a heap buffer. */
1092	if (!pThis->svga.fEnabled)
1093	{ /likely/ }
1094	else
1095	{
1096	*prc = VINF_IOM_R3_MMIO_READ;
1097	return 0;
1098	}
1099	#endif
1100
1101
1102	/* convert to VGA memory offset */
1103	#ifndef IN_RC
1104	RTGCPHYS GCPhys = addr; /* save original address */
1105	#endif
1106	addr &= 0x1ffff;
1107
1108	int const memory_map_mode = (pThis->gr[6] >> 2) & 3;
1109	switch(memory_map_mode) {
1110	case 0:
1111	break;
1112	case 1:
1113	if (addr >= 0x10000)
1114	return 0xff;
1115	addr += pThis->bank_offset;
1116	break;
1117	case 2:
1118	addr -= 0x10000;
1119	if (addr >= 0x8000)
1120	return 0xff;
1121	break;
1122	default:
1123	case 3:
1124	addr -= 0x18000;
1125	if (addr >= 0x8000)
1126	return 0xff;
1127	break;
1128	}
1129
1130	if (pThis->sr[4] & 0x08) {
1131	/* chain 4 mode : simplest access */
1132	#ifndef IN_RC
1133	/* If all planes are accessible, then map the page to the frame buffer and make it writable. */
1134	if ( (pThis->sr[2] & 3) == 3
1135	&& !vgaIsDirty(pThis, addr)
1136	&& pThis->GCPhysVRAM)
1137	{
1138	/** @todo only allow read access (doesn't work now) */
1139	STAM_COUNTER_INC(&pThis->StatMapPage);
1140	IOMMmioMapMmio2Page(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy, GCPhys - 0xa0000,
1141	pThis->hMmio2VRam, addr, X86_PTE_RW \| X86_PTE_P);
1142	/* Set as dirty as write accesses won't be noticed now. */
1143	vgaR3MarkDirty(pThis, addr);
1144	pThis->fRemappedVGA = true;
1145	}
1146	#endif /* !IN_RC */
1147	VERIFY_VRAM_READ_OFF_RETURN(pThis, addr, *prc);
1148	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1149	ret = !pThis->svga.fEnabled ? pThisCC->pbVRam[addr]
1150	: addr < VMSVGA_VGA_FB_BACKUP_SIZE ? pThisCC->svga.pbVgaFrameBufferR3[addr] : 0xff;
1151	#else
1152	ret = pThisCC->pbVRam[addr];
1153	#endif
1154	} else if (!(pThis->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1155	/* odd/even mode (aka text mode mapping) */
1156	plane = (pThis->gr[4] & 2) \| (addr & 1);
1157	/* See the comment for a similar line in vga_mem_writeb. */
1158	RTGCPHYS off = ((addr & ~1) * 4) \| plane;
1159	VERIFY_VRAM_READ_OFF_RETURN(pThis, off, *prc);
1160	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1161	ret = !pThis->svga.fEnabled ? pThisCC->pbVRam[off]
1162	: off < VMSVGA_VGA_FB_BACKUP_SIZE ? pThisCC->svga.pbVgaFrameBufferR3[off] : 0xff;
1163	#else
1164	ret = pThisCC->pbVRam[off];
1165	#endif
1166	} else {
1167	/* standard VGA latched access */
1168	VERIFY_VRAM_READ_OFF_RETURN(pThis, addr * 4 + 3, *prc);
1169	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1170	pThis->latch = !pThis->svga.fEnabled ? ((uint32_t *)pThisCC->pbVRam)[addr]
1171	: addr < VMSVGA_VGA_FB_BACKUP_SIZE ? ((uint32_t *)pThisCC->svga.pbVgaFrameBufferR3)[addr] : UINT32_MAX;
1172	#else
1173	pThis->latch = ((uint32_t *)pThisCC->pbVRam)[addr];
1174	#endif
1175	if (!(pThis->gr[5] & 0x08)) {
1176	/* read mode 0 */
1177	plane = pThis->gr[4];
1178	ret = GET_PLANE(pThis->latch, plane);
1179	} else {
1180	/* read mode 1 */
1181	ret = (pThis->latch ^ mask16[pThis->gr[2]]) & mask16[pThis->gr[7]];
1182	ret \|= ret >> 16;
1183	ret \|= ret >> 8;
1184	ret = (~ret) & 0xff;
1185	}
1186	}
1187	Log3((" 0x%02x\n", ret));
1188	return ret;
1189	}
1190
1191	/**
1192	* called for accesses between 0xa0000 and 0xc0000
1193	*/
1194	static VBOXSTRICTRC vga_mem_writeb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, RTGCPHYS addr, uint32_t val)
1195	{
1196	int plane, write_mode, b, func_select, mask;
1197	uint32_t write_mask, bit_mask, set_mask;
1198
1199	Log3(("vga: [0x%x] = 0x%02x\n", addr, val));
1200
1201	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
1202	/* VMSVGA keeps the VGA and SVGA framebuffers separate unlike this boch-based
1203	VGA implementation, so we fake it by going to ring-3 and using a heap buffer. */
1204	if (!pThis->svga.fEnabled) { /likely/ }
1205	else return VINF_IOM_R3_MMIO_WRITE;
1206	#endif
1207
1208	/* convert to VGA memory offset */
1209	#ifndef IN_RC
1210	RTGCPHYS const GCPhys = addr; /* save original address */
1211	#endif
1212	addr &= 0x1ffff;
1213
1214	int const memory_map_mode = (pThis->gr[6] >> 2) & 3;
1215	switch(memory_map_mode) {
1216	case 0:
1217	break;
1218	case 1:
1219	if (addr >= 0x10000)
1220	return VINF_SUCCESS;
1221	addr += pThis->bank_offset;
1222	break;
1223	case 2:
1224	addr -= 0x10000;
1225	if (addr >= 0x8000)
1226	return VINF_SUCCESS;
1227	break;
1228	default:
1229	case 3:
1230	addr -= 0x18000;
1231	if (addr >= 0x8000)
1232	return VINF_SUCCESS;
1233	break;
1234	}
1235
1236	if (pThis->sr[4] & 0x08) {
1237	/* chain 4 mode : simplest access */
1238	plane = addr & 3;
1239	mask = (1 << plane);
1240	if (pThis->sr[2] & mask) {
1241	#ifndef IN_RC
1242	/* If all planes are accessible, then map the page to the frame buffer and make it writable. */
1243	if ( (pThis->sr[2] & 3) == 3
1244	&& !vgaIsDirty(pThis, addr)
1245	&& pThis->GCPhysVRAM)
1246	{
1247	STAM_COUNTER_INC(&pThis->StatMapPage);
1248	IOMMmioMapMmio2Page(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy, GCPhys - 0xa0000,
1249	pThis->hMmio2VRam, addr, X86_PTE_RW \| X86_PTE_P);
1250	pThis->fRemappedVGA = true;
1251	}
1252	#endif /* !IN_RC */
1253
1254	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr);
1255	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1256	if (!pThis->svga.fEnabled)
1257	pThisCC->pbVRam[addr] = val;
1258	else if (addr < VMSVGA_VGA_FB_BACKUP_SIZE)
1259	pThisCC->svga.pbVgaFrameBufferR3[addr] = val;
1260	else
1261	{
1262	Log(("vga: chain4: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1263	return VINF_SUCCESS;
1264	}
1265	#else
1266	pThisCC->pbVRam[addr] = val;
1267	#endif
1268	Log3(("vga: chain4: [0x%x]\n", addr));
1269	pThis->plane_updated \|= mask; /* only used to detect font change */
1270	vgaR3MarkDirty(pThis, addr);
1271	}
1272	} else if (!(pThis->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1273	/* odd/even mode (aka text mode mapping) */
1274	plane = (pThis->gr[4] & 2) \| (addr & 1);
1275	mask = (1 << plane);
1276	if (pThis->sr[2] & mask) {
1277	/* 'addr' is offset in a plane, bit 0 selects the plane.
1278	* Mask the bit 0, convert plane index to vram offset,
1279	* that is multiply by the number of planes,
1280	* and select the plane byte in the vram offset.
1281	*/
1282	addr = ((addr & ~1) * 4) \| plane;
1283	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr);
1284	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1285	if (!pThis->svga.fEnabled)
1286	pThisCC->pbVRam[addr] = val;
1287	else if (addr < VMSVGA_VGA_FB_BACKUP_SIZE)
1288	pThisCC->svga.pbVgaFrameBufferR3[addr] = val;
1289	else
1290	{
1291	Log(("vga: odd/even: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1292	return VINF_SUCCESS;
1293	}
1294	#else
1295	pThisCC->pbVRam[addr] = val;
1296	#endif
1297	Log3(("vga: odd/even: [0x%x]\n", addr));
1298	pThis->plane_updated \|= mask; /* only used to detect font change */
1299	vgaR3MarkDirty(pThis, addr);
1300	}
1301	} else {
1302	/* standard VGA latched access */
1303	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, addr * 4 + 3);
1304
1305	write_mode = pThis->gr[5] & 3;
1306	switch(write_mode) {
1307	default:
1308	case 0:
1309	/* rotate */
1310	b = pThis->gr[3] & 7;
1311	val = ((val >> b) \| (val << (8 - b))) & 0xff;
1312	val \|= val << 8;
1313	val \|= val << 16;
1314
1315	/* apply set/reset mask */
1316	set_mask = mask16[pThis->gr[1]];
1317	val = (val & ~set_mask) \| (mask16[pThis->gr[0]] & set_mask);
1318	bit_mask = pThis->gr[8];
1319	break;
1320	case 1:
1321	val = pThis->latch;
1322	goto do_write;
1323	case 2:
1324	val = mask16[val & 0x0f];
1325	bit_mask = pThis->gr[8];
1326	break;
1327	case 3:
1328	/* rotate */
1329	b = pThis->gr[3] & 7;
1330	val = (val >> b) \| (val << (8 - b));
1331
1332	bit_mask = pThis->gr[8] & val;
1333	val = mask16[pThis->gr[0]];
1334	break;
1335	}
1336
1337	/* apply logical operation */
1338	func_select = pThis->gr[3] >> 3;
1339	switch(func_select) {
1340	case 0:
1341	default:
1342	/* nothing to do */
1343	break;
1344	case 1:
1345	/* and */
1346	val &= pThis->latch;
1347	break;
1348	case 2:
1349	/* or */
1350	val \|= pThis->latch;
1351	break;
1352	case 3:
1353	/* xor */
1354	val ^= pThis->latch;
1355	break;
1356	}
1357
1358	/* apply bit mask */
1359	bit_mask \|= bit_mask << 8;
1360	bit_mask \|= bit_mask << 16;
1361	val = (val & bit_mask) \| (pThis->latch & ~bit_mask);
1362
1363	do_write:
1364	/* mask data according to sr[2] */
1365	mask = pThis->sr[2];
1366	pThis->plane_updated \|= mask; /* only used to detect font change */
1367	write_mask = mask16[mask];
1368	#ifdef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
1369	uint32_t *pu32Dst;
1370	if (!pThis->svga.fEnabled)
1371	pu32Dst = &((uint32_t *)pThisCC->pbVRam)[addr];
1372	else if (addr * 4 + 3 < VMSVGA_VGA_FB_BACKUP_SIZE)
1373	pu32Dst = &((uint32_t *)pThisCC->svga.pbVgaFrameBufferR3)[addr];
1374	else
1375	{
1376	Log(("vga: latch: out of vmsvga VGA framebuffer bounds! addr=%#x\n", addr));
1377	return VINF_SUCCESS;
1378	}
1379	pu32Dst = (pu32Dst & ~write_mask) \| (val & write_mask);
1380	#else
1381	((uint32_t )pThisCC->pbVRam)[addr] = (((uint32_t )pThisCC->pbVRam)[addr] & ~write_mask)
1382	\| (val & write_mask);
1383	#endif
1384	Log3(("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n", addr * 4, write_mask, val));
1385	vgaR3MarkDirty(pThis, (addr * 4));
1386	}
1387
1388	return VINF_SUCCESS;
1389	}
1390
1391	#ifdef IN_RING3
1392
1393	typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
1394	const uint8_t *font_ptr, int h,
1395	uint32_t fgcol, uint32_t bgcol,
1396	int dscan);
1397	typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
1398	const uint8_t *font_ptr, int h,
1399	uint32_t fgcol, uint32_t bgcol, int dup9);
1400	typedef void vga_draw_line_func(PVGASTATE pThis, PVGASTATECC pThisCC, uint8_t pbDst, const uint8_t pbSrc, int width);
1401
1402	static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
1403	{
1404	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
1405	}
1406
1407	static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
1408	{
1409	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
1410	}
1411
1412	static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
1413	{
1414	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
1415	}
1416
1417	static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
1418	{
1419	return (r << 16) \| (g << 8) \| b;
1420	}
1421
1422	#define DEPTH 8
1423	#include "DevVGATmpl.h"
1424
1425	#define DEPTH 15
1426	#include "DevVGATmpl.h"
1427
1428	#define DEPTH 16
1429	#include "DevVGATmpl.h"
1430
1431	#define DEPTH 32
1432	#include "DevVGATmpl.h"
1433
1434	static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1435	{
1436	unsigned int col;
1437	col = rgb_to_pixel8(r, g, b);
1438	col \|= col << 8;
1439	col \|= col << 16;
1440	return col;
1441	}
1442
1443	static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1444	{
1445	unsigned int col;
1446	col = rgb_to_pixel15(r, g, b);
1447	col \|= col << 16;
1448	return col;
1449	}
1450
1451	static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1452	{
1453	unsigned int col;
1454	col = rgb_to_pixel16(r, g, b);
1455	col \|= col << 16;
1456	return col;
1457	}
1458
1459	static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1460	{
1461	return rgb_to_pixel32(r, g, b);
1462	}
1463
1464	/** return true if the palette was modified */
1465	static bool vgaR3UpdatePalette16(PVGASTATE pThis, PVGASTATER3 pThisCC)
1466	{
1467	bool full_update = false;
1468	int i;
1469	uint32_t v, col, *palette;
1470
1471	palette = pThis->last_palette;
1472	for(i = 0; i < 16; i++) {
1473	v = pThis->ar[i];
1474	if (pThis->ar[0x10] & 0x80)
1475	v = ((pThis->ar[0x14] & 0xf) << 4) \| (v & 0xf);
1476	else
1477	v = ((pThis->ar[0x14] & 0xc) << 4) \| (v & 0x3f);
1478	v = v * 3;
1479	col = pThisCC->rgb_to_pixel(c6_to_8(pThis->palette[v]),
1480	c6_to_8(pThis->palette[v + 1]),
1481	c6_to_8(pThis->palette[v + 2]));
1482	if (col != palette[i]) {
1483	full_update = true;
1484	palette[i] = col;
1485	}
1486	}
1487	return full_update;
1488	}
1489
1490	/** return true if the palette was modified */
1491	static bool vgaR3UpdatePalette256(PVGASTATE pThis, PVGASTATER3 pThisCC)
1492	{
1493	bool full_update = false;
1494	int i;
1495	uint32_t v, col, *palette;
1496	int wide_dac;
1497
1498	palette = pThis->last_palette;
1499	v = 0;
1500	wide_dac = (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & (VBE_DISPI_ENABLED \| VBE_DISPI_8BIT_DAC))
1501	== (VBE_DISPI_ENABLED \| VBE_DISPI_8BIT_DAC);
1502	for(i = 0; i < 256; i++) {
1503	if (wide_dac)
1504	col = pThisCC->rgb_to_pixel(pThis->palette[v],
1505	pThis->palette[v + 1],
1506	pThis->palette[v + 2]);
1507	else
1508	col = pThisCC->rgb_to_pixel(c6_to_8(pThis->palette[v]),
1509	c6_to_8(pThis->palette[v + 1]),
1510	c6_to_8(pThis->palette[v + 2]));
1511	if (col != palette[i]) {
1512	full_update = true;
1513	palette[i] = col;
1514	}
1515	v += 3;
1516	}
1517	return full_update;
1518	}
1519
1520	static void vgaR3GetOffsets(PVGASTATE pThis,
1521	uint32_t *pline_offset,
1522	uint32_t *pstart_addr,
1523	uint32_t *pline_compare)
1524	{
1525	uint32_t start_addr, line_offset, line_compare;
1526	#ifdef CONFIG_BOCHS_VBE
1527	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1528	line_offset = pThis->vbe_line_offset;
1529	start_addr = pThis->vbe_start_addr;
1530	line_compare = 65535;
1531	} else
1532	#endif
1533	{
1534	/* compute line_offset in bytes */
1535	line_offset = pThis->cr[0x13];
1536	line_offset <<= 3;
1537	if (!(pThis->cr[0x14] & 0x40) && !(pThis->cr[0x17] & 0x40))
1538	{
1539	/* Word mode. Used for odd/even modes. */
1540	line_offset *= 2;
1541	}
1542
1543	/* starting address */
1544	start_addr = pThis->cr[0x0d] \| (pThis->cr[0x0c] << 8);
1545
1546	/* line compare */
1547	line_compare = pThis->cr[0x18] \|
1548	((pThis->cr[0x07] & 0x10) << 4) \|
1549	((pThis->cr[0x09] & 0x40) << 3);
1550	}
1551	*pline_offset = line_offset;
1552	*pstart_addr = start_addr;
1553	*pline_compare = line_compare;
1554	}
1555
1556	/** update start_addr and line_offset. Return TRUE if modified */
1557	static bool vgaR3UpdateBasicParams(PVGASTATE pThis, PVGASTATER3 pThisCC)
1558	{
1559	bool full_update = false;
1560	uint32_t start_addr, line_offset, line_compare;
1561
1562	pThisCC->get_offsets(pThis, &line_offset, &start_addr, &line_compare);
1563
1564	if (line_offset != pThis->line_offset \|\|
1565	start_addr != pThis->start_addr \|\|
1566	line_compare != pThis->line_compare) {
1567	pThis->line_offset = line_offset;
1568	pThis->start_addr = start_addr;
1569	pThis->line_compare = line_compare;
1570	full_update = true;
1571	}
1572	return full_update;
1573	}
1574
1575	static inline int vgaR3GetDepthIndex(int depth)
1576	{
1577	switch(depth) {
1578	default:
1579	case 8:
1580	return 0;
1581	case 15:
1582	return 1;
1583	case 16:
1584	return 2;
1585	case 32:
1586	return 3;
1587	}
1588	}
1589
1590	static vga_draw_glyph8_func * const vga_draw_glyph8_table[4] = {
1591	vga_draw_glyph8_8,
1592	vga_draw_glyph8_16,
1593	vga_draw_glyph8_16,
1594	vga_draw_glyph8_32,
1595	};
1596
1597	static vga_draw_glyph8_func * const vga_draw_glyph16_table[4] = {
1598	vga_draw_glyph16_8,
1599	vga_draw_glyph16_16,
1600	vga_draw_glyph16_16,
1601	vga_draw_glyph16_32,
1602	};
1603
1604	static vga_draw_glyph9_func * const vga_draw_glyph9_table[4] = {
1605	vga_draw_glyph9_8,
1606	vga_draw_glyph9_16,
1607	vga_draw_glyph9_16,
1608	vga_draw_glyph9_32,
1609	};
1610
1611	static const uint8_t cursor_glyph[32 * 4] = {
1612	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1613	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1614	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1615	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1616	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1617	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1618	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1619	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1620	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1621	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1622	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1623	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1624	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1625	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1626	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1627	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1628	};
1629
1630	static const uint8_t empty_glyph[32 * 4] = { 0 };
1631
1632	/**
1633	* Text mode update
1634	* Missing:
1635	* - underline
1636	*/
1637	static int vgaR3DrawText(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update,
1638	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
1639	{
1640	int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1641	int cx_min, cx_max, linesize, x_incr;
1642	int cx_min_upd, cx_max_upd, cy_start;
1643	uint32_t offset, fgcol, bgcol, v, cursor_offset;
1644	uint8_t d1, d, src, s1, dest, cursor_ptr;
1645	const uint8_t font_ptr, font_base[2];
1646	int dup9, line_offset, depth_index, dscan;
1647	uint32_t *palette;
1648	uint32_t *ch_attr_ptr;
1649	vga_draw_glyph8_func *vga_draw_glyph8;
1650	vga_draw_glyph9_func *vga_draw_glyph9;
1651	uint64_t time_ns;
1652	bool blink_on, chr_blink_flip, cur_blink_flip;
1653	bool blink_enabled, blink_do_redraw;
1654
1655	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
1656	palette = pThis->last_palette;
1657
1658	/* compute font data address (in plane 2) */
1659	v = pThis->sr[3];
1660	offset = (((v >> 4) & 1) \| ((v << 1) & 6)) * 8192 * 4 + 2;
1661	if (offset != pThis->font_offsets[0]) {
1662	pThis->font_offsets[0] = offset;
1663	full_update = true;
1664	}
1665	font_base[0] = pThisCC->pbVRam + offset;
1666
1667	offset = (((v >> 5) & 1) \| ((v >> 1) & 6)) * 8192 * 4 + 2;
1668	font_base[1] = pThisCC->pbVRam + offset;
1669	if (offset != pThis->font_offsets[1]) {
1670	pThis->font_offsets[1] = offset;
1671	full_update = true;
1672	}
1673	if (pThis->plane_updated & (1 << 2)) {
1674	/* if the plane 2 was modified since the last display, it
1675	indicates the font may have been modified */
1676	pThis->plane_updated = 0;
1677	full_update = true;
1678	}
1679	full_update \|= vgaR3UpdateBasicParams(pThis, pThisCC);
1680
1681	line_offset = pThis->line_offset;
1682	s1 = pThisCC->pbVRam + (pThis->start_addr * 8); /** @todo r=bird: Add comment why we do 8 instead of 4, it's not so obvious... */
1683
1684	/* double scanning - not for 9-wide modes */
1685	dscan = (pThis->cr[9] >> 7) & 1;
1686
1687	/* total width & height */
1688	cheight = (pThis->cr[9] & 0x1f) + 1;
1689	cw = 8;
1690	if (!(pThis->sr[1] & 0x01))
1691	cw = 9;
1692	if (pThis->sr[1] & 0x08)
1693	cw = 16; /* NOTE: no 18 pixel wide */
1694	x_incr = cw * ((pDrv->cBits + 7) >> 3);
1695	width = (pThis->cr[0x01] + 1);
1696	if (pThis->cr[0x06] == 100) {
1697	/* ugly hack for CGA 160x100x16 - explain me the logic */
1698	height = 100;
1699	} else {
1700	height = pThis->cr[0x12] \|
1701	((pThis->cr[0x07] & 0x02) << 7) \|
1702	((pThis->cr[0x07] & 0x40) << 3);
1703	height = (height + 1) / cheight;
1704	}
1705	if ((height * width) > CH_ATTR_SIZE) {
1706	/* better than nothing: exit if transient size is too big */
1707	return VINF_SUCCESS;
1708	}
1709
1710	if (width != (int)pThis->last_width \|\| height != (int)pThis->last_height \|\|
1711	cw != pThis->last_cw \|\| cheight != pThis->last_ch) {
1712	if (fFailOnResize)
1713	{
1714	/* The caller does not want to call the pfnResize. */
1715	return VERR_TRY_AGAIN;
1716	}
1717	pThis->last_scr_width = width * cw;
1718	pThis->last_scr_height = height * cheight;
1719	/* For text modes the direct use of guest VRAM is not implemented, so bpp and cbLine are 0 here. */
1720	int rc = pDrv->pfnResize(pDrv, 0, NULL, 0, pThis->last_scr_width, pThis->last_scr_height);
1721	pThis->last_width = width;
1722	pThis->last_height = height;
1723	pThis->last_ch = cheight;
1724	pThis->last_cw = cw;
1725	full_update = true;
1726	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1727	return rc;
1728	AssertRC(rc);
1729	}
1730	cursor_offset = ((pThis->cr[0x0e] << 8) \| pThis->cr[0x0f]) - pThis->start_addr;
1731	if (cursor_offset != pThis->cursor_offset \|\|
1732	pThis->cr[0xa] != pThis->cursor_start \|\|
1733	pThis->cr[0xb] != pThis->cursor_end) {
1734	/* if the cursor position changed, we update the old and new
1735	chars */
1736	if (pThis->cursor_offset < CH_ATTR_SIZE)
1737	pThis->last_ch_attr[pThis->cursor_offset] = UINT32_MAX;
1738	if (cursor_offset < CH_ATTR_SIZE)
1739	pThis->last_ch_attr[cursor_offset] = UINT32_MAX;
1740	pThis->cursor_offset = cursor_offset;
1741	pThis->cursor_start = pThis->cr[0xa];
1742	pThis->cursor_end = pThis->cr[0xb];
1743	}
1744	cursor_ptr = pThisCC->pbVRam + (pThis->start_addr + cursor_offset) * 8;
1745	depth_index = vgaR3GetDepthIndex(pDrv->cBits);
1746	if (cw == 16)
1747	vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1748	else
1749	vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1750	vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1751
1752	dest = pDrv->pbData;
1753	linesize = pDrv->cbScanline;
1754	ch_attr_ptr = pThis->last_ch_attr;
1755	cy_start = -1;
1756	cx_max_upd = -1;
1757	cx_min_upd = width;
1758
1759	/* Figure out if we're in the visible period of the blink cycle. */
1760	time_ns = PDMDevHlpTMTimeVirtGetNano(pDevIns);
1761	blink_on = (time_ns % VGA_BLINK_PERIOD_FULL) < VGA_BLINK_PERIOD_ON;
1762	chr_blink_flip = false;
1763	cur_blink_flip = false;
1764	if (pThis->last_chr_blink != blink_on)
1765	{
1766	/* Currently cursor and characters blink at the same rate, but they might not. */
1767	pThis->last_chr_blink = blink_on;
1768	pThis->last_cur_blink = blink_on;
1769	chr_blink_flip = true;
1770	cur_blink_flip = true;
1771	}
1772	blink_enabled = !!(pThis->ar[0x10] & 0x08); /* Attribute controller blink enable. */
1773
1774	for(cy = 0; cy < (height - dscan); cy = cy + (1 << dscan)) {
1775	d1 = dest;
1776	src = s1;
1777	cx_min = width;
1778	cx_max = -1;
1779	for(cx = 0; cx < width; cx++) {
1780	ch_attr = (uint16_t )src;
1781	/* Figure out if character needs redrawing due to blink state change. */
1782	blink_do_redraw = blink_enabled && chr_blink_flip && (ch_attr & 0x8000);
1783	if (full_update \|\| ch_attr != (int)*ch_attr_ptr \|\| blink_do_redraw \|\| (src == cursor_ptr && cur_blink_flip)) {
1784	if (cx < cx_min)
1785	cx_min = cx;
1786	if (cx > cx_max)
1787	cx_max = cx;
1788	if (reset_dirty)
1789	*ch_attr_ptr = ch_attr;
1790	#ifdef WORDS_BIGENDIAN
1791	ch = ch_attr >> 8;
1792	cattr = ch_attr & 0xff;
1793	#else
1794	ch = ch_attr & 0xff;
1795	cattr = ch_attr >> 8;
1796	#endif
1797	font_ptr = font_base[(cattr >> 3) & 1];
1798	font_ptr += 32 * 4 * ch;
1799	bgcol = palette[cattr >> 4];
1800	fgcol = palette[cattr & 0x0f];
1801
1802	if (blink_enabled && (cattr & 0x80))
1803	{
1804	bgcol = palette[(cattr >> 4) & 7];
1805	if (!blink_on)
1806	font_ptr = empty_glyph;
1807	}
1808
1809	if (cw != 9) {
1810	if (pThis->fRenderVRAM)
1811	vga_draw_glyph8(d1, linesize, font_ptr, cheight, fgcol, bgcol, dscan);
1812	} else {
1813	dup9 = 0;
1814	if (ch >= 0xb0 && ch <= 0xdf && (pThis->ar[0x10] & 0x04))
1815	dup9 = 1;
1816	if (pThis->fRenderVRAM)
1817	vga_draw_glyph9(d1, linesize, font_ptr, cheight, fgcol, bgcol, dup9);
1818	}
1819	if (src == cursor_ptr &&
1820	!(pThis->cr[0x0a] & 0x20)) {
1821	int line_start, line_last, h;
1822
1823	/* draw the cursor if within the visible period */
1824	if (blink_on) {
1825	line_start = pThis->cr[0x0a] & 0x1f;
1826	line_last = pThis->cr[0x0b] & 0x1f;
1827	/* XXX: check that */
1828	if (line_last > cheight - 1)
1829	line_last = cheight - 1;
1830	if (line_last >= line_start && line_start < cheight) {
1831	h = line_last - line_start + 1;
1832	d = d1 + (linesize * line_start << dscan);
1833	if (cw != 9) {
1834	if (pThis->fRenderVRAM)
1835	vga_draw_glyph8(d, linesize, cursor_glyph, h, fgcol, bgcol, dscan);
1836	} else {
1837	if (pThis->fRenderVRAM)
1838	vga_draw_glyph9(d, linesize, cursor_glyph, h, fgcol, bgcol, 1);
1839	}
1840	}
1841	}
1842	}
1843	}
1844	d1 += x_incr;
1845	src += 8; /* Every second byte of a plane is used in text mode. */
1846	ch_attr_ptr++;
1847	}
1848	if (cx_max != -1) {
1849	/* Keep track of the bounding rectangle for updates. */
1850	if (cy_start == -1)
1851	cy_start = cy;
1852	if (cx_min_upd > cx_min)
1853	cx_min_upd = cx_min;
1854	if (cx_max_upd < cx_max)
1855	cx_max_upd = cx_max;
1856	} else if (cy_start >= 0) {
1857	/* Flush updates to display. */
1858	pDrv->pfnUpdateRect(pDrv, cx_min_upd * cw, cy_start * cheight,
1859	(cx_max_upd - cx_min_upd + 1) * cw, (cy - cy_start) * cheight);
1860	cy_start = -1;
1861	cx_max_upd = -1;
1862	cx_min_upd = width;
1863	}
1864	dest += linesize * cheight << dscan;
1865	s1 += line_offset;
1866	}
1867	if (cy_start >= 0)
1868	/* Flush any remaining changes to display. */
1869	pDrv->pfnUpdateRect(pDrv, cx_min_upd * cw, cy_start * cheight,
1870	(cx_max_upd - cx_min_upd + 1) * cw, (cy - cy_start) * cheight);
1871	return VINF_SUCCESS;
1872	}
1873
1874	enum {
1875	VGA_DRAW_LINE2,
1876	VGA_DRAW_LINE2D2,
1877	VGA_DRAW_LINE4,
1878	VGA_DRAW_LINE4D2,
1879	VGA_DRAW_LINE8D2,
1880	VGA_DRAW_LINE8,
1881	VGA_DRAW_LINE15,
1882	VGA_DRAW_LINE16,
1883	VGA_DRAW_LINE24,
1884	VGA_DRAW_LINE32,
1885	VGA_DRAW_LINE_NB
1886	};
1887
1888	static vga_draw_line_func * const vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = {
1889	vga_draw_line2_8,
1890	vga_draw_line2_16,
1891	vga_draw_line2_16,
1892	vga_draw_line2_32,
1893
1894	vga_draw_line2d2_8,
1895	vga_draw_line2d2_16,
1896	vga_draw_line2d2_16,
1897	vga_draw_line2d2_32,
1898
1899	vga_draw_line4_8,
1900	vga_draw_line4_16,
1901	vga_draw_line4_16,
1902	vga_draw_line4_32,
1903
1904	vga_draw_line4d2_8,
1905	vga_draw_line4d2_16,
1906	vga_draw_line4d2_16,
1907	vga_draw_line4d2_32,
1908
1909	vga_draw_line8d2_8,
1910	vga_draw_line8d2_16,
1911	vga_draw_line8d2_16,
1912	vga_draw_line8d2_32,
1913
1914	vga_draw_line8_8,
1915	vga_draw_line8_16,
1916	vga_draw_line8_16,
1917	vga_draw_line8_32,
1918
1919	vga_draw_line15_8,
1920	vga_draw_line15_15,
1921	vga_draw_line15_16,
1922	vga_draw_line15_32,
1923
1924	vga_draw_line16_8,
1925	vga_draw_line16_15,
1926	vga_draw_line16_16,
1927	vga_draw_line16_32,
1928
1929	vga_draw_line24_8,
1930	vga_draw_line24_15,
1931	vga_draw_line24_16,
1932	vga_draw_line24_32,
1933
1934	vga_draw_line32_8,
1935	vga_draw_line32_15,
1936	vga_draw_line32_16,
1937	vga_draw_line32_32,
1938	};
1939
1940	static int vgaR3GetBpp(PVGASTATE pThis)
1941	{
1942	int ret;
1943	#ifdef CONFIG_BOCHS_VBE
1944	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1945	ret = pThis->vbe_regs[VBE_DISPI_INDEX_BPP];
1946	} else
1947	#endif
1948	{
1949	ret = 0;
1950	}
1951	return ret;
1952	}
1953
1954	static void vgaR3GetResolution(PVGASTATE pThis, int pwidth, int pheight)
1955	{
1956	int width, height;
1957	#ifdef CONFIG_BOCHS_VBE
1958	if (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1959	width = pThis->vbe_regs[VBE_DISPI_INDEX_XRES];
1960	height = RT_MIN(pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
1961	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
1962	} else
1963	#endif
1964	{
1965	width = (pThis->cr[0x01] + 1) * 8;
1966	height = pThis->cr[0x12] \|
1967	((pThis->cr[0x07] & 0x02) << 7) \|
1968	((pThis->cr[0x07] & 0x40) << 3);
1969	height = (height + 1);
1970	}
1971	*pwidth = width;
1972	*pheight = height;
1973	}
1974
1975
1976	/**
1977	* Performs the display driver resizing when in graphics mode.
1978	*
1979	* This will recalc / update any status data depending on the driver
1980	* properties (bit depth mostly).
1981	*
1982	* @returns VINF_SUCCESS on success.
1983	* @returns VINF_VGA_RESIZE_IN_PROGRESS if the operation wasn't complete.
1984	* @param pThis Pointer to the shared VGA state.
1985	* @param pThisCC Pointer to the ring-3 VGA state.
1986	* @param cx The width.
1987	* @param cy The height.
1988	* @param pDrv The display connector.
1989	*/
1990	static int vgaR3ResizeGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, int cx, int cy, PDMIDISPLAYCONNECTOR *pDrv)
1991	{
1992	const unsigned cBits = pThisCC->get_bpp(pThis);
1993
1994	int rc;
1995	AssertReturn(cx, VERR_INVALID_PARAMETER);
1996	AssertReturn(cy, VERR_INVALID_PARAMETER);
1997	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1998
1999	if (!pThis->line_offset)
2000	return VERR_INTERNAL_ERROR;
2001
2002	#if 0 //def VBOX_WITH_VDMA
2003	/** @todo we get a second resize here when VBVA is on, while we actually should not */
2004	/* do not do pfnResize in case VBVA is on since all mode changes are performed over VBVA
2005	* we are checking for VDMA state here to ensure this code works only for WDDM driver,
2006	* although we should avoid calling pfnResize for XPDM as well, since pfnResize is actually an extra resize
2007	* event and generally only pfnVBVAxxx calls should be used with HGSMI + VBVA
2008	*
2009	* The reason for doing this for WDDM driver only now is to avoid regressions of the current code */
2010	PVBOXVDMAHOST pVdma = pThisCC->pVdma;
2011	if (pVdma && vboxVDMAIsEnabled(pVdma))
2012	rc = VINF_SUCCESS;
2013	else
2014	#endif
2015	{
2016	/* Skip the resize if the values are not valid. */
2017	if (pThis->start_addr * 4 + pThis->line_offset * cy < pThis->vram_size)
2018	/* Take into account the programmed start address (in DWORDs) of the visible screen. */
2019	rc = pDrv->pfnResize(pDrv, cBits, pThisCC->pbVRam + pThis->start_addr * 4, pThis->line_offset, cx, cy);
2020	else
2021	{
2022	/* Change nothing in the VGA state. Lets hope the guest will eventually programm correct values. */
2023	return VERR_TRY_AGAIN;
2024	}
2025	}
2026
2027	/* last stuff */
2028	pThis->last_bpp = cBits;
2029	pThis->last_scr_width = cx;
2030	pThis->last_scr_height = cy;
2031	pThis->last_width = cx;
2032	pThis->last_height = cy;
2033
2034	if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
2035	return rc;
2036	AssertRC(rc);
2037
2038	/* update palette */
2039	switch (pDrv->cBits)
2040	{
2041	case 32: pThisCC->rgb_to_pixel = rgb_to_pixel32_dup; break;
2042	case 16:
2043	default: pThisCC->rgb_to_pixel = rgb_to_pixel16_dup; break;
2044	case 15: pThisCC->rgb_to_pixel = rgb_to_pixel15_dup; break;
2045	case 8: pThisCC->rgb_to_pixel = rgb_to_pixel8_dup; break;
2046	}
2047	if (pThis->shift_control == 0)
2048	vgaR3UpdatePalette16(pThis, pThisCC);
2049	else if (pThis->shift_control == 1)
2050	vgaR3UpdatePalette16(pThis, pThisCC);
2051	return VINF_SUCCESS;
2052	}
2053
2054	# ifdef VBOX_WITH_VMSVGA
2055
2056	# if 0 /* unused? */
2057	int vgaR3UpdateDisplay(PVGASTATE pThis, PVGASTATER3 pThisCC, unsigned xStart, unsigned yStart, unsigned cx, unsigned cy, PDMIDISPLAYCONNECTOR *pDrv)
2058	{
2059	uint32_t v;
2060	vga_draw_line_func *vga_draw_line;
2061
2062	if (!pThis->fRenderVRAM)
2063	{
2064	pDrv->pfnUpdateRect(pDrv, xStart, yStart, cx, cy);
2065	return VINF_SUCCESS;
2066	}
2067	/** @todo might crash if a blit follows a resolution change very quickly (seen this many times!) */
2068
2069	if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
2070	\|\| pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED
2071	\|\| pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)
2072	{
2073	/* Intermediate state; skip redraws. */
2074	AssertFailed();
2075	return VINF_SUCCESS;
2076	}
2077
2078	uint32_t cBits;
2079	switch (pThis->svga.uBpp) {
2080	default:
2081	case 0:
2082	case 8:
2083	AssertFailed();
2084	return VERR_NOT_IMPLEMENTED;
2085	case 15:
2086	v = VGA_DRAW_LINE15;
2087	cBits = 16;
2088	break;
2089	case 16:
2090	v = VGA_DRAW_LINE16;
2091	cBits = 16;
2092	break;
2093	case 24:
2094	v = VGA_DRAW_LINE24;
2095	cBits = 24;
2096	break;
2097	case 32:
2098	v = VGA_DRAW_LINE32;
2099	cBits = 32;
2100	break;
2101	}
2102	vga_draw_line = vga_draw_line_table[v * 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2103
2104	uint32_t offSrc = (xStart * cBits) / 8 + pThis->svga.cbScanline * yStart;
2105	uint32_t offDst = (xStart * RT_ALIGN(pDrv->cBits, 8)) / 8 + pDrv->cbScanline * yStart;
2106
2107	uint8_t *pbDst = pDrv->pbData + offDst;
2108	uint8_t const *pbSrc = pThisCC->pbVRam + offSrc;
2109
2110	for (unsigned y = yStart; y < yStart + cy; y++)
2111	{
2112	vga_draw_line(pThis, pThisCC, pbDst, pbSrc, cx);
2113
2114	pbDst += pDrv->cbScanline;
2115	pbSrc += pThis->svga.cbScanline;
2116	}
2117	pDrv->pfnUpdateRect(pDrv, xStart, yStart, cx, cy);
2118
2119	return VINF_SUCCESS;
2120	}
2121	# endif
2122
2123	/**
2124	* graphic modes
2125	*/
2126	static int vmsvgaR3DrawGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, bool fFullUpdate,
2127	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
2128	{
2129	RT_NOREF1(fFailOnResize);
2130
2131	uint32_t const cx = pThis->last_scr_width;
2132	uint32_t const cxDisplay = cx;
2133	uint32_t const cy = pThis->last_scr_height;
2134	uint32_t cBits = pThis->last_bpp;
2135
2136	if ( cx == VMSVGA_VAL_UNINITIALIZED
2137	\|\| cx == 0
2138	\|\| cy == VMSVGA_VAL_UNINITIALIZED
2139	\|\| cy == 0
2140	\|\| cBits == VMSVGA_VAL_UNINITIALIZED
2141	\|\| cBits == 0)
2142	{
2143	/* Intermediate state; skip redraws. */
2144	return VINF_SUCCESS;
2145	}
2146
2147	unsigned v;
2148	switch (cBits)
2149	{
2150	case 8:
2151	/* Note! experimental, not sure if this really works... */
2152	/** @todo fFullUpdate \|= vgaR3UpdatePalette256(pThis); - need fFullUpdate but not
2153	* copying anything to last_palette. */
2154	v = VGA_DRAW_LINE8;
2155	break;
2156	case 15:
2157	v = VGA_DRAW_LINE15;
2158	cBits = 16;
2159	break;
2160	case 16:
2161	v = VGA_DRAW_LINE16;
2162	break;
2163	case 24:
2164	v = VGA_DRAW_LINE24;
2165	break;
2166	case 32:
2167	v = VGA_DRAW_LINE32;
2168	break;
2169	default:
2170	case 0:
2171	AssertFailed();
2172	return VERR_NOT_IMPLEMENTED;
2173	}
2174	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2175
2176	Assert(!pThisCC->cursor_invalidate);
2177	Assert(!pThisCC->cursor_draw_line);
2178	//not used// if (pThisCC->cursor_invalidate)
2179	//not used// pThisCC->cursor_invalidate(pThis);
2180
2181	uint8_t *pbDst = pDrv->pbData;
2182	uint32_t cbDstScanline = pDrv->cbScanline;
2183	uint32_t offSrcStart = 0; /* always start at the beginning of the framebuffer */
2184	uint32_t cbScanline = (cx * cBits + 7) / 8; /* The visible width of a scanline. */
2185	uint32_t yUpdateRectTop = UINT32_MAX;
2186	uint32_t offPageMin = UINT32_MAX;
2187	int32_t offPageMax = -1;
2188	uint32_t y;
2189	for (y = 0; y < cy; y++)
2190	{
2191	uint32_t offSrcLine = offSrcStart + y * cbScanline;
2192	uint32_t offPage0 = offSrcLine & ~PAGE_OFFSET_MASK;
2193	uint32_t offPage1 = (offSrcLine + cbScanline - 1) & ~PAGE_OFFSET_MASK;
2194	/** @todo r=klaus this assumes that a line is fully covered by 3 pages,
2195	* irrespective of alignment. Not guaranteed for high res modes, i.e.
2196	* anything wider than 2050 pixels @32bpp. Need to check all pages
2197	* between the first and last one. */
2198	bool fUpdate = fFullUpdate \| vgaIsDirty(pThis, offPage0) \| vgaIsDirty(pThis, offPage1);
2199	if (offPage1 - offPage0 > PAGE_SIZE)
2200	/* if wide line, can use another page */
2201	fUpdate \|= vgaIsDirty(pThis, offPage0 + PAGE_SIZE);
2202	/* explicit invalidation for the hardware cursor */
2203	fUpdate \|= (pThis->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2204	if (fUpdate)
2205	{
2206	if (yUpdateRectTop == UINT32_MAX)
2207	yUpdateRectTop = y;
2208	if (offPage0 < offPageMin)
2209	offPageMin = offPage0;
2210	if ((int32_t)offPage1 > offPageMax)
2211	offPageMax = offPage1;
2212	if (pThis->fRenderVRAM)
2213	pfnVgaDrawLine(pThis, pThisCC, pbDst, pThisCC->pbVRam + offSrcLine, cx);
2214	//not used// if (pThisCC->cursor_draw_line)
2215	//not used// pThisCC->cursor_draw_line(pThis, pbDst, y);
2216	}
2217	else if (yUpdateRectTop != UINT32_MAX)
2218	{
2219	/* flush to display */
2220	Log(("Flush to display (%d,%d)(%d,%d)\n", 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop));
2221	pDrv->pfnUpdateRect(pDrv, 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop);
2222	yUpdateRectTop = UINT32_MAX;
2223	}
2224	pbDst += cbDstScanline;
2225	}
2226	if (yUpdateRectTop != UINT32_MAX)
2227	{
2228	/* flush to display */
2229	Log(("Flush to display (%d,%d)(%d,%d)\n", 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop));
2230	pDrv->pfnUpdateRect(pDrv, 0, yUpdateRectTop, cxDisplay, y - yUpdateRectTop);
2231	}
2232
2233	/* reset modified pages */
2234	if (offPageMax != -1 && reset_dirty)
2235	vgaR3ResetDirty(pThis, offPageMin, offPageMax + PAGE_SIZE);
2236	memset(pThis->invalidated_y_table, 0, ((cy + 31) >> 5) * 4);
2237
2238	return VINF_SUCCESS;
2239	}
2240
2241	# endif /* VBOX_WITH_VMSVGA */
2242
2243	/**
2244	* graphic modes
2245	*/
2246	static int vgaR3DrawGraphic(PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update, bool fFailOnResize, bool reset_dirty,
2247	PDMIDISPLAYCONNECTOR *pDrv)
2248	{
2249	int y1, y2, y, page_min, page_max, linesize, y_start, double_scan;
2250	int width, height, shift_control, line_offset, page0, page1, bwidth, bits;
2251	int disp_width, multi_run;
2252	uint8_t *d;
2253	uint32_t v, addr1, addr;
2254	vga_draw_line_func *pfnVgaDrawLine;
2255
2256	bool offsets_changed = vgaR3UpdateBasicParams(pThis, pThisCC);
2257
2258	full_update \|= offsets_changed;
2259
2260	pThisCC->get_resolution(pThis, &width, &height);
2261	disp_width = width;
2262
2263	shift_control = (pThis->gr[0x05] >> 5) & 3;
2264	double_scan = (pThis->cr[0x09] >> 7);
2265	multi_run = double_scan;
2266	if (shift_control != pThis->shift_control \|\|
2267	double_scan != pThis->double_scan) {
2268	full_update = true;
2269	pThis->shift_control = shift_control;
2270	pThis->double_scan = double_scan;
2271	}
2272
2273	if (shift_control == 0) {
2274	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
2275	if (pThis->sr[0x01] & 8) {
2276	v = VGA_DRAW_LINE4D2;
2277	disp_width <<= 1;
2278	} else {
2279	v = VGA_DRAW_LINE4;
2280	}
2281	bits = 4;
2282	} else if (shift_control == 1) {
2283	full_update \|= vgaR3UpdatePalette16(pThis, pThisCC);
2284	if (pThis->sr[0x01] & 8) {
2285	v = VGA_DRAW_LINE2D2;
2286	disp_width <<= 1;
2287	} else {
2288	v = VGA_DRAW_LINE2;
2289	}
2290	bits = 4;
2291	} else {
2292	switch(pThisCC->get_bpp(pThis)) {
2293	default:
2294	case 0:
2295	full_update \|= vgaR3UpdatePalette256(pThis, pThisCC);
2296	v = VGA_DRAW_LINE8D2;
2297	bits = 4;
2298	break;
2299	case 8:
2300	full_update \|= vgaR3UpdatePalette256(pThis, pThisCC);
2301	v = VGA_DRAW_LINE8;
2302	bits = 8;
2303	break;
2304	case 15:
2305	v = VGA_DRAW_LINE15;
2306	bits = 16;
2307	break;
2308	case 16:
2309	v = VGA_DRAW_LINE16;
2310	bits = 16;
2311	break;
2312	case 24:
2313	v = VGA_DRAW_LINE24;
2314	bits = 24;
2315	break;
2316	case 32:
2317	v = VGA_DRAW_LINE32;
2318	bits = 32;
2319	break;
2320	}
2321	}
2322	if ( disp_width != (int)pThis->last_width
2323	\|\| height != (int)pThis->last_height
2324	\|\| pThisCC->get_bpp(pThis) != (int)pThis->last_bpp
2325	\|\| (offsets_changed && !pThis->fRenderVRAM))
2326	{
2327	if (fFailOnResize)
2328	{
2329	/* The caller does not want to call the pfnResize. */
2330	return VERR_TRY_AGAIN;
2331	}
2332	int rc = vgaR3ResizeGraphic(pThis, pThisCC, disp_width, height, pDrv);
2333	if (rc != VINF_SUCCESS) /* Return any rc, particularly VINF_VGA_RESIZE_IN_PROGRESS, to the caller. */
2334	return rc;
2335	full_update = true;
2336	}
2337
2338	if (pThis->fRenderVRAM)
2339	{
2340	/* Do not update the destination buffer if it is not big enough.
2341	* Can happen if the resize request was ignored by the driver.
2342	* Compare with 'disp_width', because it is what the framebuffer has been resized to.
2343	*/
2344	if ( pDrv->cx != (uint32_t)disp_width
2345	\|\| pDrv->cy != (uint32_t)height)
2346	{
2347	LogRel(("Framebuffer mismatch: vga %dx%d, drv %dx%d!!!\n",
2348	disp_width, height,
2349	pDrv->cx, pDrv->cy));
2350	return VINF_SUCCESS;
2351	}
2352	}
2353
2354	pfnVgaDrawLine = vga_draw_line_table[v * 4 + vgaR3GetDepthIndex(pDrv->cBits)];
2355
2356	if (pThisCC->cursor_invalidate)
2357	pThisCC->cursor_invalidate(pThis);
2358
2359	line_offset = pThis->line_offset;
2360	#if 0
2361	Log(("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
2362	width, height, v, line_offset, pThis->cr[9], pThis->cr[0x17], pThis->line_compare, pThis->sr[0x01]));
2363	#endif
2364	addr1 = (pThis->start_addr * 4);
2365	bwidth = (width * bits + 7) / 8; /* The visible width of a scanline. */
2366	y_start = -1;
2367	page_min = 0x7fffffff;
2368	page_max = -1;
2369	d = pDrv->pbData;
2370	linesize = pDrv->cbScanline;
2371
2372	if (!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED))
2373	pThis->vga_addr_mask = 0x3ffff;
2374	else
2375	pThis->vga_addr_mask = UINT32_MAX;
2376
2377	y1 = 0;
2378	y2 = pThis->cr[0x09] & 0x1F; /* starting row scan count */
2379	for(y = 0; y < height; y++) {
2380	addr = addr1;
2381	/* CGA/MDA compatibility. Note that these addresses are all
2382	* shifted left by two compared to VGA specs.
2383	*/
2384	if (!(pThis->cr[0x17] & 1)) {
2385	addr = (addr & ~(1 << 15)) \| ((y1 & 1) << 15);
2386	}
2387	if (!(pThis->cr[0x17] & 2)) {
2388	addr = (addr & ~(1 << 16)) \| ((y1 & 2) << 15);
2389	}
2390	addr &= pThis->vga_addr_mask;
2391	page0 = addr & ~PAGE_OFFSET_MASK;
2392	page1 = (addr + bwidth - 1) & ~PAGE_OFFSET_MASK;
2393	/** @todo r=klaus this assumes that a line is fully covered by 3 pages,
2394	* irrespective of alignment. Not guaranteed for high res modes, i.e.
2395	* anything wider than 2050 pixels @32bpp. Need to check all pages
2396	* between the first and last one. */
2397	bool update = full_update \| vgaIsDirty(pThis, page0) \| vgaIsDirty(pThis, page1);
2398	if (page1 - page0 > PAGE_SIZE) {
2399	/* if wide line, can use another page */
2400	update \|= vgaIsDirty(pThis, page0 + PAGE_SIZE);
2401	}
2402	/* explicit invalidation for the hardware cursor */
2403	update \|= (pThis->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2404	if (update) {
2405	if (y_start < 0)
2406	y_start = y;
2407	if (page0 < page_min)
2408	page_min = page0;
2409	if (page1 > page_max)
2410	page_max = page1;
2411	if (pThis->fRenderVRAM)
2412	pfnVgaDrawLine(pThis, pThisCC, d, pThisCC->pbVRam + addr, width);
2413	if (pThisCC->cursor_draw_line)
2414	pThisCC->cursor_draw_line(pThis, d, y);
2415	} else {
2416	if (y_start >= 0) {
2417	/* flush to display */
2418	pDrv->pfnUpdateRect(pDrv, 0, y_start, disp_width, y - y_start);
2419	y_start = -1;
2420	}
2421	}
2422	if (!multi_run) {
2423	y1++;
2424	multi_run = double_scan;
2425
2426	if (y2 == 0) {
2427	y2 = pThis->cr[0x09] & 0x1F;
2428	addr1 += line_offset;
2429	} else {
2430	--y2;
2431	}
2432	} else {
2433	multi_run--;
2434	}
2435	/* line compare acts on the displayed lines */
2436	if ((uint32_t)y == pThis->line_compare)
2437	addr1 = 0;
2438	d += linesize;
2439	}
2440	if (y_start >= 0) {
2441	/* flush to display */
2442	pDrv->pfnUpdateRect(pDrv, 0, y_start, disp_width, y - y_start);
2443	}
2444	/* reset modified pages */
2445	if (page_max != -1 && reset_dirty) {
2446	vgaR3ResetDirty(pThis, page_min, page_max + PAGE_SIZE);
2447	}
2448	memset(pThis->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
2449	return VINF_SUCCESS;
2450	}
2451
2452	/**
2453	* blanked modes
2454	*/
2455	static int vgaR3DrawBlank(PVGASTATE pThis, PVGASTATER3 pThisCC, bool full_update,
2456	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR *pDrv)
2457	{
2458	int i, w, val;
2459	uint8_t *d;
2460	uint32_t cbScanline = pDrv->cbScanline;
2461	uint32_t page_min, page_max;
2462
2463	if (pThis->last_width != 0)
2464	{
2465	if (fFailOnResize)
2466	{
2467	/* The caller does not want to call the pfnResize. */
2468	return VERR_TRY_AGAIN;
2469	}
2470	pThis->last_width = 0;
2471	pThis->last_height = 0;
2472	/* For blanking signal width=0, height=0, bpp=0 and cbLine=0 here.
2473	* There is no screen content, which distinguishes it from text mode. */
2474	pDrv->pfnResize(pDrv, 0, NULL, 0, 0, 0);
2475	}
2476	/* reset modified pages, i.e. everything */
2477	if (reset_dirty && pThis->last_scr_height > 0)
2478	{
2479	page_min = (pThis->start_addr * 4) & ~PAGE_OFFSET_MASK;
2480	/* round up page_max by one page, as otherwise this can be -PAGE_SIZE,
2481	* which causes assertion trouble in vgaR3ResetDirty. */
2482	page_max = ( pThis->start_addr * 4 + pThis->line_offset * pThis->last_scr_height
2483	- 1 + PAGE_SIZE) & ~PAGE_OFFSET_MASK;
2484	vgaR3ResetDirty(pThis, page_min, page_max + PAGE_SIZE);
2485	}
2486	if (pDrv->pbData == pThisCC->pbVRam) /* Do not clear the VRAM itself. */
2487	return VINF_SUCCESS;
2488	if (!full_update)
2489	return VINF_SUCCESS;
2490	if (pThis->last_scr_width <= 0 \|\| pThis->last_scr_height <= 0)
2491	return VINF_SUCCESS;
2492	if (pDrv->cBits == 8)
2493	val = pThisCC->rgb_to_pixel(0, 0, 0);
2494	else
2495	val = 0;
2496	w = pThis->last_scr_width * ((pDrv->cBits + 7) >> 3);
2497	d = pDrv->pbData;
2498	if (pThis->fRenderVRAM)
2499	{
2500	for(i = 0; i < (int)pThis->last_scr_height; i++) {
2501	memset(d, val, w);
2502	d += cbScanline;
2503	}
2504	}
2505	pDrv->pfnUpdateRect(pDrv, 0, 0, pThis->last_scr_width, pThis->last_scr_height);
2506	return VINF_SUCCESS;
2507	}
2508
2509
2510	#define GMODE_TEXT 0
2511	#define GMODE_GRAPH 1
2512	#define GMODE_BLANK 2
2513	#ifdef VBOX_WITH_VMSVGA
2514	#define GMODE_SVGA 3
2515	#endif
2516
2517	/**
2518	* Worker for vgaR3PortUpdateDisplay(), vboxR3UpdateDisplayAllInternal() and
2519	* vgaR3PortTakeScreenshot().
2520	*/
2521	static int vgaR3UpdateDisplay(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATER3 pThisCC, bool fUpdateAll,
2522	bool fFailOnResize, bool reset_dirty, PDMIDISPLAYCONNECTOR pDrv, int32_t pcur_graphic_mode)
2523	{
2524	int rc = VINF_SUCCESS;
2525	int graphic_mode;
2526
2527	if (pDrv->cBits == 0) {
2528	/* nothing to do */
2529	} else {
2530	switch(pDrv->cBits) {
2531	case 8:
2532	pThisCC->rgb_to_pixel = rgb_to_pixel8_dup;
2533	break;
2534	case 15:
2535	pThisCC->rgb_to_pixel = rgb_to_pixel15_dup;
2536	break;
2537	default:
2538	case 16:
2539	pThisCC->rgb_to_pixel = rgb_to_pixel16_dup;
2540	break;
2541	case 32:
2542	pThisCC->rgb_to_pixel = rgb_to_pixel32_dup;
2543	break;
2544	}
2545
2546	#ifdef VBOX_WITH_VMSVGA
2547	if (pThis->svga.fEnabled) {
2548	graphic_mode = GMODE_SVGA;
2549	}
2550	else
2551	#endif
2552	if (!(pThis->ar_index & 0x20) \|\| (pThis->sr[0x01] & 0x20)) {
2553	graphic_mode = GMODE_BLANK;
2554	} else {
2555	graphic_mode = pThis->gr[6] & 1 ? GMODE_GRAPH : GMODE_TEXT;
2556	}
2557	bool full_update = fUpdateAll \|\| graphic_mode != *pcur_graphic_mode;
2558	if (full_update) {
2559	*pcur_graphic_mode = graphic_mode;
2560	}
2561	switch(graphic_mode) {
2562	case GMODE_TEXT:
2563	rc = vgaR3DrawText(pDevIns, pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2564	break;
2565	case GMODE_GRAPH:
2566	rc = vgaR3DrawGraphic(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2567	break;
2568	#ifdef VBOX_WITH_VMSVGA
2569	case GMODE_SVGA:
2570	rc = vmsvgaR3DrawGraphic(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2571	break;
2572	#endif
2573	case GMODE_BLANK:
2574	default:
2575	rc = vgaR3DrawBlank(pThis, pThisCC, full_update, fFailOnResize, reset_dirty, pDrv);
2576	break;
2577	}
2578	}
2579	return rc;
2580	}
2581
2582	/**
2583	* Worker for vgaR3SaveExec().
2584	*/
2585	static void vga_save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PVGASTATE pThis)
2586	{
2587	int i;
2588
2589	pHlp->pfnSSMPutU32(pSSM, pThis->latch);
2590	pHlp->pfnSSMPutU8(pSSM, pThis->sr_index);
2591	pHlp->pfnSSMPutMem(pSSM, pThis->sr, 8);
2592	pHlp->pfnSSMPutU8(pSSM, pThis->gr_index);
2593	pHlp->pfnSSMPutMem(pSSM, pThis->gr, 16);
2594	pHlp->pfnSSMPutU8(pSSM, pThis->ar_index);
2595	pHlp->pfnSSMPutMem(pSSM, pThis->ar, 21);
2596	pHlp->pfnSSMPutU32(pSSM, pThis->ar_flip_flop);
2597	pHlp->pfnSSMPutU8(pSSM, pThis->cr_index);
2598	pHlp->pfnSSMPutMem(pSSM, pThis->cr, 256);
2599	pHlp->pfnSSMPutU8(pSSM, pThis->msr);
2600	pHlp->pfnSSMPutU8(pSSM, pThis->fcr);
2601	pHlp->pfnSSMPutU8(pSSM, pThis->st00);
2602	pHlp->pfnSSMPutU8(pSSM, pThis->st01);
2603
2604	pHlp->pfnSSMPutU8(pSSM, pThis->dac_state);
2605	pHlp->pfnSSMPutU8(pSSM, pThis->dac_sub_index);
2606	pHlp->pfnSSMPutU8(pSSM, pThis->dac_read_index);
2607	pHlp->pfnSSMPutU8(pSSM, pThis->dac_write_index);
2608	pHlp->pfnSSMPutMem(pSSM, pThis->dac_cache, 3);
2609	pHlp->pfnSSMPutMem(pSSM, pThis->palette, 768);
2610
2611	pHlp->pfnSSMPutU32(pSSM, pThis->bank_offset);
2612	#ifdef CONFIG_BOCHS_VBE
2613	AssertCompile(RT_ELEMENTS(pThis->vbe_regs) < 256);
2614	pHlp->pfnSSMPutU8(pSSM, (uint8_t)RT_ELEMENTS(pThis->vbe_regs));
2615	pHlp->pfnSSMPutU16(pSSM, pThis->vbe_index);
2616	for(i = 0; i < (int)RT_ELEMENTS(pThis->vbe_regs); i++)
2617	pHlp->pfnSSMPutU16(pSSM, pThis->vbe_regs[i]);
2618	pHlp->pfnSSMPutU32(pSSM, pThis->vbe_start_addr);
2619	pHlp->pfnSSMPutU32(pSSM, pThis->vbe_line_offset);
2620	#else
2621	pHlp->pfnSSMPutU8(pSSM, 0);
2622	#endif
2623	}
2624
2625
2626	/**
2627	* Worker for vgaR3LoadExec().
2628	*/
2629	static int vga_load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM, PVGASTATE pThis, int version_id)
2630	{
2631	int is_vbe, i;
2632	uint32_t u32Dummy;
2633	uint8_t u8;
2634
2635	pHlp->pfnSSMGetU32(pSSM, &pThis->latch);
2636	pHlp->pfnSSMGetU8(pSSM, &pThis->sr_index);
2637	pHlp->pfnSSMGetMem(pSSM, pThis->sr, 8);
2638	pHlp->pfnSSMGetU8(pSSM, &pThis->gr_index);
2639	pHlp->pfnSSMGetMem(pSSM, pThis->gr, 16);
2640	pHlp->pfnSSMGetU8(pSSM, &pThis->ar_index);
2641	pHlp->pfnSSMGetMem(pSSM, pThis->ar, 21);
2642	pHlp->pfnSSMGetS32(pSSM, &pThis->ar_flip_flop);
2643	pHlp->pfnSSMGetU8(pSSM, &pThis->cr_index);
2644	pHlp->pfnSSMGetMem(pSSM, pThis->cr, 256);
2645	pHlp->pfnSSMGetU8(pSSM, &pThis->msr);
2646	pHlp->pfnSSMGetU8(pSSM, &pThis->fcr);
2647	pHlp->pfnSSMGetU8(pSSM, &pThis->st00);
2648	pHlp->pfnSSMGetU8(pSSM, &pThis->st01);
2649
2650	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_state);
2651	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_sub_index);
2652	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_read_index);
2653	pHlp->pfnSSMGetU8(pSSM, &pThis->dac_write_index);
2654	pHlp->pfnSSMGetMem(pSSM, pThis->dac_cache, 3);
2655	pHlp->pfnSSMGetMem(pSSM, pThis->palette, 768);
2656
2657	pHlp->pfnSSMGetS32(pSSM, &pThis->bank_offset);
2658	pHlp->pfnSSMGetU8(pSSM, &u8);
2659	is_vbe = !!u8;
2660	#ifdef CONFIG_BOCHS_VBE
2661	if (!is_vbe)
2662	{
2663	Log(("vga_load: !is_vbe !!\n"));
2664	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2665	}
2666
2667	if (u8 == 1)
2668	u8 = VBE_DISPI_INDEX_NB_SAVED; /* Used to save so many registers. */
2669	if (u8 > RT_ELEMENTS(pThis->vbe_regs))
2670	{
2671	Log(("vga_load: saved %d, expected %d!!\n", u8, RT_ELEMENTS(pThis->vbe_regs)));
2672	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2673	}
2674
2675	pHlp->pfnSSMGetU16(pSSM, &pThis->vbe_index);
2676	for(i = 0; i < (int)u8; i++)
2677	pHlp->pfnSSMGetU16(pSSM, &pThis->vbe_regs[i]);
2678	if (version_id <= VGA_SAVEDSTATE_VERSION_INV_VHEIGHT)
2679	recalculate_data(pThis); /* <- re-calculate the pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] since it might be invalid */
2680	pHlp->pfnSSMGetU32(pSSM, &pThis->vbe_start_addr);
2681	pHlp->pfnSSMGetU32(pSSM, &pThis->vbe_line_offset);
2682	if (version_id < 2)
2683	pHlp->pfnSSMGetU32(pSSM, &u32Dummy);
2684	pThis->vbe_bank_max = (pThis->vram_size >> 16) - 1;
2685	#else
2686	if (is_vbe)
2687	{
2688	Log(("vga_load: is_vbe !!\n"));
2689	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2690	}
2691	#endif
2692
2693	/* force refresh */
2694	pThis->graphic_mode = -1;
2695	return 0;
2696	}
2697
2698
2699	/**
2700	* Worker for vgaR3Construct().
2701	*/
2702	static void vgaR3InitExpand(void)
2703	{
2704	int i, j, v, b;
2705
2706	for(i = 0;i < 256; i++) {
2707	v = 0;
2708	for(j = 0; j < 8; j++) {
2709	v \|= ((i >> j) & 1) << (j * 4);
2710	}
2711	expand4[i] = v;
2712
2713	v = 0;
2714	for(j = 0; j < 4; j++) {
2715	v \|= ((i >> (2 * j)) & 3) << (j * 4);
2716	}
2717	expand2[i] = v;
2718	}
2719	for(i = 0; i < 16; i++) {
2720	v = 0;
2721	for(j = 0; j < 4; j++) {
2722	b = ((i >> j) & 1);
2723	v \|= b << (2 * j);
2724	v \|= b << (2 * j + 1);
2725	}
2726	expand4to8[i] = v;
2727	}
2728	}
2729
2730	#endif /* IN_RING3 */
2731
2732
2733
2734	/* -=-=-=-=-=- all contexts -=-=-=-=-=- */
2735
2736	#define VGA_IOPORT_WRITE_PLACEHOLDER(a_uPort, a_cPorts) do {\
2737	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); \
2738	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
2739	AssertCompile(RT_IS_POWER_OF_TWO(a_cPorts)); \
2740	Assert((unsigned)offPort - (unsigned)(a_uPort) < (unsigned)(a_cPorts)); \
2741	NOREF(pvUser); \
2742	if (cb == 1) \
2743	vga_ioport_write(pDevIns, pThis, offPort, u32); \
2744	else if (cb == 2) \
2745	{ \
2746	vga_ioport_write(pDevIns, pThis, offPort, u32 & 0xff); \
2747	vga_ioport_write(pDevIns, pThis, offPort + 1, u32 >> 8); \
2748	} \
2749	return VINF_SUCCESS; \
2750	} while (0)
2751
2752	#define VGA_IOPORT_READ_PLACEHOLDER(a_uPort, a_cPorts) do {\
2753	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); \
2754	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
2755	AssertCompile(RT_IS_POWER_OF_TWO(a_cPorts)); \
2756	Assert((unsigned)offPort - (unsigned)(a_uPort) < (unsigned)(a_cPorts)); \
2757	NOREF(pvUser); \
2758	if (cb == 1) \
2759	*pu32 = vga_ioport_read(pDevIns, pThis, offPort); \
2760	else if (cb == 2) \
2761	{ \
2762	uint32_t u32 = vga_ioport_read(pDevIns, pThis, offPort); \
2763	u32 \|= vga_ioport_read(pDevIns, pThis, offPort + 1) << 8; \
2764	*pu32 = u32; \
2765	} \
2766	else \
2767	return VERR_IOM_IOPORT_UNUSED; \
2768	return VINF_SUCCESS; \
2769	} while (0)
2770
2771	/**
2772	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c0-0x3c1 Attribute Controller.}
2773	*/
2774	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortArWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2775	{
2776	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c0, 2);
2777	}
2778
2779	/**
2780	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c0-0x3c1 Attribute Controller.}
2781	*/
2782	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortArRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2783	{
2784	VGA_IOPORT_READ_PLACEHOLDER(0x3c0, 2);
2785	}
2786
2787
2788	/**
2789	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c2 Miscellaneous Register.}
2790	*/
2791	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMsrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2792	{
2793	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c2, 1);
2794	}
2795
2796	/**
2797	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c2 Status register 0.}
2798	*/
2799	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSt00Read(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2800	{
2801	VGA_IOPORT_READ_PLACEHOLDER(0x3c2, 1);
2802	}
2803
2804
2805	/**
2806	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c3 Unused.}
2807	*/
2808	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortUnusedWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2809	{
2810	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c3, 1);
2811	}
2812
2813	/**
2814	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c3 Unused.}
2815	*/
2816	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortUnusedRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2817	{
2818	VGA_IOPORT_READ_PLACEHOLDER(0x3c3, 1);
2819	}
2820
2821
2822	/**
2823	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c4-0x3c5 Sequencer.}
2824	*/
2825	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2826	{
2827	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c4, 2);
2828	}
2829
2830	/**
2831	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c4-0x3c5 Sequencer.}
2832	*/
2833	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortSrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2834	{
2835	VGA_IOPORT_READ_PLACEHOLDER(0x3c4, 2);
2836	}
2837
2838
2839	/**
2840	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3c6-0x3c9 DAC.}
2841	*/
2842	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortDacWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2843	{
2844	VGA_IOPORT_WRITE_PLACEHOLDER(0x3c6, 4);
2845	}
2846
2847	/**
2848	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3c6-0x3c9 DAC.}
2849	*/
2850	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortDacRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2851	{
2852	VGA_IOPORT_READ_PLACEHOLDER(0x3c6, 4);
2853	}
2854
2855
2856	/**
2857	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ca-0x3cd Graphics Position?}
2858	*/
2859	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortPosWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2860	{
2861	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ca, 4);
2862	}
2863
2864	/**
2865	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ca-0x3cd Graphics Position?}
2866	*/
2867	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortPosRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2868	{
2869	VGA_IOPORT_READ_PLACEHOLDER(0x3ca, 4);
2870	}
2871
2872
2873	/**
2874	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ce-0x3cf Graphics Controller.}
2875	*/
2876	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortGrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2877	{
2878	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ce, 2);
2879	}
2880
2881	/**
2882	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ca-0x3cf Graphics Controller.}
2883	*/
2884	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortGrRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2885	{
2886	VGA_IOPORT_READ_PLACEHOLDER(0x3ce, 2);
2887	}
2888
2889
2890	/**
2891	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3b4-0x3b5 MDA CRT control.}
2892	*/
2893	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaCrtWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2894	{
2895	/** @todo do vga_ioport_invalid here */
2896	VGA_IOPORT_WRITE_PLACEHOLDER(0x3b4, 2);
2897	}
2898
2899	/**
2900	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3b4-0x3b5 MDA CRT control.}
2901	*/
2902	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaCrtRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2903	{
2904	/** @todo do vga_ioport_invalid here */
2905	VGA_IOPORT_READ_PLACEHOLDER(0x3b4, 2);
2906	}
2907
2908
2909	/**
2910	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3ba MDA feature/status.}
2911	*/
2912	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaFcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2913	{
2914	/** @todo do vga_ioport_invalid here */
2915	VGA_IOPORT_WRITE_PLACEHOLDER(0x3ba, 1);
2916	}
2917
2918	/**
2919	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3ba MDA feature/status.}
2920	*/
2921	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortMdaStRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2922	{
2923	/** @todo do vga_ioport_invalid here */
2924	VGA_IOPORT_READ_PLACEHOLDER(0x3ba, 1);
2925	}
2926
2927
2928	/**
2929	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3d4-0x3d5 CGA CRT control.}
2930	*/
2931	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaCrtWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2932	{
2933	/** @todo do vga_ioport_invalid here */
2934	VGA_IOPORT_WRITE_PLACEHOLDER(0x3d4, 2);
2935	}
2936
2937	/**
2938	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3d4-0x3d5 CGA CRT control.}
2939	*/
2940	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaCrtRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2941	{
2942	/** @todo do vga_ioport_invalid here */
2943	VGA_IOPORT_READ_PLACEHOLDER(0x3d4, 2);
2944	}
2945
2946
2947	/**
2948	* @callback_method_impl{FNIOMIOPORTNEWOUT,0x3da CGA feature/status.}
2949	*/
2950	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaFcrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2951	{
2952	/** @todo do vga_ioport_invalid here */
2953	VGA_IOPORT_WRITE_PLACEHOLDER(0x3da, 1);
2954	}
2955
2956	/**
2957	* @callback_method_impl{FNIOMIOPORTNEWIN,0x3da CGA feature/status.}
2958	*/
2959	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortCgaStRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
2960	{
2961	/** @todo do vga_ioport_invalid here */
2962	VGA_IOPORT_READ_PLACEHOLDER(0x3da, 1);
2963	}
2964
2965
2966	/**
2967	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Data Port OUT handler (0x1ce).}
2968	*/
2969	static DECLCALLBACK(VBOXSTRICTRC)
2970	vgaIoPortWriteVbeData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
2971	{
2972	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
2973	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
2974	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
2975
2976	NOREF(pvUser);
2977
2978	#ifndef IN_RING3
2979	/*
2980	* This has to be done on the host in order to execute the connector callbacks.
2981	*/
2982	if ( pThis->vbe_index == VBE_DISPI_INDEX_ENABLE
2983	\|\| pThis->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO)
2984	{
2985	Log(("vgaIoPortWriteVbeData: VBE_DISPI_INDEX_ENABLE - Switching to host...\n"));
2986	return VINF_IOM_R3_IOPORT_WRITE;
2987	}
2988	#endif
2989	#ifdef VBE_BYTEWISE_IO
2990	if (cb == 1)
2991	{
2992	if (!pThis->fWriteVBEData)
2993	{
2994	if ( (pThis->vbe_index == VBE_DISPI_INDEX_ENABLE)
2995	&& (u32 & VBE_DISPI_ENABLED))
2996	{
2997	pThis->fWriteVBEData = false;
2998	return vbe_ioport_write_data(pDevIns, pThis, pThisCC, offPort, u32 & 0xFF);
2999	}
3000
3001	pThis->cbWriteVBEData = u32 & 0xFF;
3002	pThis->fWriteVBEData = true;
3003	return VINF_SUCCESS;
3004	}
3005
3006	u32 = (pThis->cbWriteVBEData << 8) \| (u32 & 0xFF);
3007	pThis->fWriteVBEData = false;
3008	cb = 2;
3009	}
3010	#endif
3011	if (cb == 2 \|\| cb == 4)
3012	return vbe_ioport_write_data(pDevIns, pThis, pThisCC, offPort, u32);
3013	AssertMsgFailed(("vgaIoPortWriteVbeData: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3014
3015	return VINF_SUCCESS;
3016	}
3017
3018
3019	/**
3020	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Index Port OUT handler (0x1ce).}
3021	*/
3022	static DECLCALLBACK(VBOXSTRICTRC)
3023	vgaIoPortWriteVbeIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3024	{
3025	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser);
3026	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3027
3028	#ifdef VBE_BYTEWISE_IO
3029	if (cb == 1)
3030	{
3031	if (!pThis->fWriteVBEIndex)
3032	{
3033	pThis->cbWriteVBEIndex = u32 & 0x00FF;
3034	pThis->fWriteVBEIndex = true;
3035	return VINF_SUCCESS;
3036	}
3037	pThis->fWriteVBEIndex = false;
3038	vbe_ioport_write_index(pThis, offPort, (pThis->cbWriteVBEIndex << 8) \| (u32 & 0x00FF));
3039	return VINF_SUCCESS;
3040	}
3041	#endif
3042
3043	if (cb == 2)
3044	vbe_ioport_write_index(pThis, offPort, u32);
3045	else
3046	ASSERT_GUEST_MSG_FAILED(("vgaIoPortWriteVbeIndex: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3047	return VINF_SUCCESS;
3048	}
3049
3050
3051	/**
3052	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Data Port IN handler (0x1cf).}
3053	*/
3054	static DECLCALLBACK(VBOXSTRICTRC)
3055	vgaIoPortReadVbeData(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3056	{
3057	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE); NOREF(pvUser);
3058	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3059
3060	#ifdef VBE_BYTEWISE_IO
3061	if (cb == 1)
3062	{
3063	if (!pThis->fReadVBEData)
3064	{
3065	*pu32 = (vbe_ioport_read_data(pThis, offPort) >> 8) & 0xFF;
3066	pThis->fReadVBEData = true;
3067	return VINF_SUCCESS;
3068	}
3069	*pu32 = vbe_ioport_read_data(pThis, offPort) & 0xFF;
3070	pThis->fReadVBEData = false;
3071	return VINF_SUCCESS;
3072	}
3073	#endif
3074	if (cb == 2)
3075	{
3076	*pu32 = vbe_ioport_read_data(pThis, offPort);
3077	return VINF_SUCCESS;
3078	}
3079	if (cb == 4)
3080	{
3081	if (pThis->vbe_regs[VBE_DISPI_INDEX_ID] == VBE_DISPI_ID_CFG)
3082	pu32 = vbe_ioport_read_data(pThis, offPort); / New interface. */
3083	else
3084	pu32 = pThis->vram_size; / Quick hack for getting the vram size. */
3085	return VINF_SUCCESS;
3086	}
3087	AssertMsgFailed(("vgaIoPortReadVbeData: offPort=%#x cb=%d\n", offPort, cb));
3088	return VERR_IOM_IOPORT_UNUSED;
3089	}
3090
3091
3092	/**
3093	* @callback_method_impl{FNIOMIOPORTNEWOUT,VBE Index Port IN handler (0x1cf).}
3094	*/
3095	static DECLCALLBACK(VBOXSTRICTRC)
3096	vgaIoPortReadVbeIndex(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3097	{
3098	NOREF(pvUser);
3099	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3100	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3101
3102	#ifdef VBE_BYTEWISE_IO
3103	if (cb == 1)
3104	{
3105	if (!pThis->fReadVBEIndex)
3106	{
3107	*pu32 = (vbe_ioport_read_index(pThis, offPort) >> 8) & 0xFF;
3108	pThis->fReadVBEIndex = true;
3109	return VINF_SUCCESS;
3110	}
3111	*pu32 = vbe_ioport_read_index(pThis, offPort) & 0xFF;
3112	pThis->fReadVBEIndex = false;
3113	return VINF_SUCCESS;
3114	}
3115	#endif
3116	if (cb == 2)
3117	{
3118	*pu32 = vbe_ioport_read_index(pThis, offPort);
3119	return VINF_SUCCESS;
3120	}
3121	AssertMsgFailed(("vgaIoPortReadVbeIndex: offPort=%#x cb=%d\n", offPort, cb));
3122	return VERR_IOM_IOPORT_UNUSED;
3123	}
3124
3125	#if defined(VBOX_WITH_HGSMI) && defined(IN_RING3)
3126
3127	/**
3128	* @callback_method_impl{FNIOMIOPORTNEWOUT,HGSMI OUT handler.}
3129	*/
3130	static DECLCALLBACK(VBOXSTRICTRC)
3131	vgaR3IOPortHgsmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3132	{
3133	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3134	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3135	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3136	LogFlowFunc(("offPort=0x%x u32=0x%x cb=%u\n", offPort, u32, cb));
3137
3138	NOREF(pvUser);
3139
3140	if (cb == 4)
3141	{
3142	switch (offPort)
3143	{
3144	case VGA_PORT_HGSMI_HOST: /* Host */
3145	{
3146	# if defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM)
3147	if (u32 == HGSMIOFFSET_VOID)
3148	{
3149	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSectIRQ, VERR_SEM_BUSY);
3150
3151	if (pThis->fu32PendingGuestFlags == 0)
3152	{
3153	PDMDevHlpPCISetIrqNoWait(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3154	HGSMIClearHostGuestFlags(pThisCC->pHGSMI,
3155	HGSMIHOSTFLAGS_IRQ
3156	\| HGSMIHOSTFLAGS_VSYNC
3157	\| HGSMIHOSTFLAGS_HOTPLUG
3158	\| HGSMIHOSTFLAGS_CURSOR_CAPABILITIES);
3159	}
3160	else
3161	{
3162	HGSMISetHostGuestFlags(pThisCC->pHGSMI, HGSMIHOSTFLAGS_IRQ \| pThis->fu32PendingGuestFlags);
3163	pThis->fu32PendingGuestFlags = 0;
3164	/* Keep the IRQ unchanged. */
3165	}
3166
3167	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSectIRQ);
3168	}
3169	else
3170	# endif
3171	{
3172	HGSMIHostWrite(pThisCC->pHGSMI, u32);
3173	}
3174	break;
3175	}
3176
3177	case VGA_PORT_HGSMI_GUEST: /* Guest */
3178	HGSMIGuestWrite(pThisCC->pHGSMI, u32);
3179	break;
3180
3181	default:
3182	# ifdef DEBUG_sunlover
3183	AssertMsgFailed(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3184	# endif
3185	break;
3186	}
3187	}
3188	else
3189	{
3190	/** @todo r=bird: According to Ralf Brown, one and two byte accesses to the
3191	* 0x3b0-0x3b1 and 0x3b2-0x3b3 I/O port pairs should work the same as
3192	* 0x3b4-0x3b5 (MDA CRT control). */
3193	Log(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x - possible valid MDA CRT access\n", offPort, cb, u32));
3194	# ifdef DEBUG_sunlover
3195	AssertMsgFailed(("vgaR3IOPortHgsmiWrite: offPort=%#x cb=%d u32=%#x\n", offPort, cb, u32));
3196	# endif
3197	STAM_REL_COUNTER_INC(&pThis->StatHgsmiMdaCgaAccesses);
3198	}
3199
3200	return VINF_SUCCESS;
3201	}
3202
3203
3204	/**
3205	* @callback_method_impl{FNIOMIOPORTNEWOUT,HGSMI IN handler.}
3206	*/
3207	static DECLCALLBACK(VBOXSTRICTRC)
3208	vgaR3IOPortHgmsiRead(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3209	{
3210	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3211	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3212	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3213	LogFlowFunc(("offPort=0x%x cb=%d\n", offPort, cb));
3214
3215	NOREF(pvUser);
3216
3217	VBOXSTRICTRC rc = VINF_SUCCESS;
3218	if (cb == 4)
3219	{
3220	switch (offPort)
3221	{
3222	case VGA_PORT_HGSMI_HOST: /* Host */
3223	*pu32 = HGSMIHostRead(pThisCC->pHGSMI);
3224	break;
3225	case VGA_PORT_HGSMI_GUEST: /* Guest */
3226	*pu32 = HGSMIGuestRead(pThisCC->pHGSMI);
3227	break;
3228	default:
3229	rc = VERR_IOM_IOPORT_UNUSED;
3230	break;
3231	}
3232	}
3233	else
3234	{
3235	/** @todo r=bird: According to Ralf Brown, one and two byte accesses to the
3236	* 0x3b0-0x3b1 and 0x3b2-0x3b3 I/O port pairs should work the same as
3237	* 0x3b4-0x3b5 (MDA CRT control). */
3238	Log(("vgaR3IOPortHgmsiRead: offPort=%#x cb=%d - possible valid MDA CRT access\n", offPort, cb));
3239	STAM_REL_COUNTER_INC(&pThis->StatHgsmiMdaCgaAccesses);
3240	rc = VERR_IOM_IOPORT_UNUSED;
3241	}
3242
3243	return rc;
3244	}
3245
3246	#endif /* VBOX_WITH_HGSMI && IN_RING3*/
3247
3248
3249
3250
3251	/* -=-=-=-=-=- All Contexts -=-=-=-=-=- */
3252
3253	/**
3254	* @internal. For use inside VGAGCMemoryFillWrite only.
3255	* Macro for apply logical operation and bit mask.
3256	*/
3257	#define APPLY_LOGICAL_AND_MASK(pThis, val, bit_mask) \
3258	/* apply logical operation */ \
3259	switch (pThis->gr[3] >> 3)\
3260	{ \
3261	case 0: \
3262	default:\
3263	/* nothing to do */ \
3264	break; \
3265	case 1: \
3266	/* and */ \
3267	val &= pThis->latch; \
3268	break; \
3269	case 2: \
3270	/* or */ \
3271	val \|= pThis->latch; \
3272	break; \
3273	case 3: \
3274	/* xor */ \
3275	val ^= pThis->latch; \
3276	break; \
3277	} \
3278	/* apply bit mask */ \
3279	val = (val & bit_mask) \| (pThis->latch & ~bit_mask)
3280
3281	/**
3282	* Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM and from the inside of VGADeviceGC.cpp.
3283	* This is the advanced version of vga_mem_writeb function.
3284	*
3285	* @returns VBox status code.
3286	* @param pThis The shared VGA instance data.
3287	* @param pThisCC The VGA instance data for the current context.
3288	* @param pvUser User argument - ignored.
3289	* @param GCPhysAddr Physical address of memory to write.
3290	* @param u32Item Data to write, up to 4 bytes.
3291	* @param cbItem Size of data Item, only 1/2/4 bytes is allowed for now.
3292	* @param cItems Number of data items to write.
3293	*/
3294	static int vgaInternalMMIOFill(PVGASTATE pThis, PVGASTATECC pThisCC, void *pvUser, RTGCPHYS GCPhysAddr,
3295	uint32_t u32Item, unsigned cbItem, unsigned cItems)
3296	{
3297	uint32_t b;
3298	uint32_t write_mask, bit_mask, set_mask;
3299	uint32_t aVal[4];
3300	unsigned i;
3301	NOREF(pvUser);
3302
3303	for (i = 0; i < cbItem; i++)
3304	{
3305	aVal[i] = u32Item & 0xff;
3306	u32Item >>= 8;
3307	}
3308
3309	/* convert to VGA memory offset */
3310	/// @todo add check for the end of region
3311	GCPhysAddr &= 0x1ffff;
3312	switch((pThis->gr[6] >> 2) & 3) {
3313	case 0:
3314	break;
3315	case 1:
3316	if (GCPhysAddr >= 0x10000)
3317	return VINF_SUCCESS;
3318	GCPhysAddr += pThis->bank_offset;
3319	break;
3320	case 2:
3321	GCPhysAddr -= 0x10000;
3322	if (GCPhysAddr >= 0x8000)
3323	return VINF_SUCCESS;
3324	break;
3325	default:
3326	case 3:
3327	GCPhysAddr -= 0x18000;
3328	if (GCPhysAddr >= 0x8000)
3329	return VINF_SUCCESS;
3330	break;
3331	}
3332
3333	if (pThis->sr[4] & 0x08) {
3334	/* chain 4 mode : simplest access */
3335	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, GCPhysAddr + cItems * cbItem - 1);
3336
3337	while (cItems-- > 0)
3338	for (i = 0; i < cbItem; i++)
3339	{
3340	if (pThis->sr[2] & (1 << (GCPhysAddr & 3)))
3341	{
3342	pThisCC->pbVRam[GCPhysAddr] = aVal[i];
3343	vgaR3MarkDirty(pThis, GCPhysAddr);
3344	}
3345	GCPhysAddr++;
3346	}
3347	} else if (pThis->gr[5] & 0x10) {
3348	/* odd/even mode (aka text mode mapping) */
3349	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, (GCPhysAddr + cItems * cbItem) * 4 - 1);
3350	while (cItems-- > 0)
3351	for (i = 0; i < cbItem; i++)
3352	{
3353	unsigned plane = (pThis->gr[4] & 2) \| (GCPhysAddr & 1);
3354	if (pThis->sr[2] & (1 << plane)) {
3355	RTGCPHYS PhysAddr2 = ((GCPhysAddr & ~1) * 4) \| plane;
3356	pThisCC->pbVRam[PhysAddr2] = aVal[i];
3357	vgaR3MarkDirty(pThis, PhysAddr2);
3358	}
3359	GCPhysAddr++;
3360	}
3361	} else {
3362	/* standard VGA latched access */
3363	VERIFY_VRAM_WRITE_OFF_RETURN(pThis, (GCPhysAddr + cItems * cbItem) * 4 - 1);
3364
3365	switch(pThis->gr[5] & 3) {
3366	default:
3367	case 0:
3368	/* rotate */
3369	b = pThis->gr[3] & 7;
3370	bit_mask = pThis->gr[8];
3371	bit_mask \|= bit_mask << 8;
3372	bit_mask \|= bit_mask << 16;
3373	set_mask = mask16[pThis->gr[1]];
3374
3375	for (i = 0; i < cbItem; i++)
3376	{
3377	aVal[i] = ((aVal[i] >> b) \| (aVal[i] << (8 - b))) & 0xff;
3378	aVal[i] \|= aVal[i] << 8;
3379	aVal[i] \|= aVal[i] << 16;
3380
3381	/* apply set/reset mask */
3382	aVal[i] = (aVal[i] & ~set_mask) \| (mask16[pThis->gr[0]] & set_mask);
3383
3384	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3385	}
3386	break;
3387	case 1:
3388	for (i = 0; i < cbItem; i++)
3389	aVal[i] = pThis->latch;
3390	break;
3391	case 2:
3392	bit_mask = pThis->gr[8];
3393	bit_mask \|= bit_mask << 8;
3394	bit_mask \|= bit_mask << 16;
3395	for (i = 0; i < cbItem; i++)
3396	{
3397	aVal[i] = mask16[aVal[i] & 0x0f];
3398
3399	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3400	}
3401	break;
3402	case 3:
3403	/* rotate */
3404	b = pThis->gr[3] & 7;
3405
3406	for (i = 0; i < cbItem; i++)
3407	{
3408	aVal[i] = (aVal[i] >> b) \| (aVal[i] << (8 - b));
3409	bit_mask = pThis->gr[8] & aVal[i];
3410	bit_mask \|= bit_mask << 8;
3411	bit_mask \|= bit_mask << 16;
3412	aVal[i] = mask16[pThis->gr[0]];
3413
3414	APPLY_LOGICAL_AND_MASK(pThis, aVal[i], bit_mask);
3415	}
3416	break;
3417	}
3418
3419	/* mask data according to sr[2] */
3420	write_mask = mask16[pThis->sr[2]];
3421
3422	/* actually write data */
3423	if (cbItem == 1)
3424	{
3425	/* The most frequently case is 1 byte I/O. */
3426	while (cItems-- > 0)
3427	{
3428	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3429	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3430	GCPhysAddr++;
3431	}
3432	}
3433	else if (cbItem == 2)
3434	{
3435	/* The second case is 2 bytes I/O. */
3436	while (cItems-- > 0)
3437	{
3438	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[0] & write_mask);
3439	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3440	GCPhysAddr++;
3441
3442	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[1] & write_mask);
3443	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3444	GCPhysAddr++;
3445	}
3446	}
3447	else
3448	{
3449	/* And the rest is 4 bytes. */
3450	Assert(cbItem == 4);
3451	while (cItems-- > 0)
3452	for (i = 0; i < cbItem; i++)
3453	{
3454	((uint32_t )pThisCC->pbVRam)[GCPhysAddr] = (((uint32_t )pThisCC->pbVRam)[GCPhysAddr] & ~write_mask) \| (aVal[i] & write_mask);
3455	vgaR3MarkDirty(pThis, GCPhysAddr * 4);
3456	GCPhysAddr++;
3457	}
3458	}
3459	}
3460	return VINF_SUCCESS;
3461	}
3462
3463	#undef APPLY_LOGICAL_AND_MASK
3464
3465	/**
3466	* @callback_method_impl{FNIOMMMIONEWFILL,
3467	* Legacy VGA memory (0xa0000 - 0xbffff) write hook\, to be called from IOM and
3468	* from the inside of VGADeviceGC.cpp. This is the advanced version of
3469	* vga_mem_writeb function.}
3470	*/
3471	static DECLCALLBACK(VBOXSTRICTRC)
3472	vgaMmioFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, uint32_t u32Item, unsigned cbItem, unsigned cItems)
3473	{
3474	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3475	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3476	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3477
3478	return vgaInternalMMIOFill(pThis, pThisCC, pvUser, off, u32Item, cbItem, cItems);
3479	}
3480
3481
3482	/**
3483	* @callback_method_impl{FNIOMMMIONEWREAD,
3484	* Legacy VGA memory (0xa0000 - 0xbffff) read hook\, to be called from IOM.}
3485	*/
3486	static DECLCALLBACK(VBOXSTRICTRC) vgaMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3487	{
3488	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3489	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3490	STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryRead), a);
3491	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3492	NOREF(pvUser);
3493
3494	int rc = VINF_SUCCESS;
3495	switch (cb)
3496	{
3497	case 1:
3498	(uint8_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc);
3499	break;
3500	case 2:
3501	/** @todo This and the wider accesses maybe misbehave when accessing bytes
3502	* crossing the 512KB VRAM boundrary if the access is handled in
3503	* ring-0 and operating in latched mode. */
3504	(uint16_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3505	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8);
3506	break;
3507	case 4:
3508	(uint32_t )pv = vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3509	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8)
3510	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 2, &rc) << 16)
3511	\| (vga_mem_readb(pDevIns, pThis, pThisCC, off + 3, &rc) << 24);
3512	break;
3513
3514	case 8:
3515	(uint64_t )pv = (uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off, &rc)
3516	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 1, &rc) << 8)
3517	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 2, &rc) << 16)
3518	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 3, &rc) << 24)
3519	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 4, &rc) << 32)
3520	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 5, &rc) << 40)
3521	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 6, &rc) << 48)
3522	\| ((uint64_t)vga_mem_readb(pDevIns, pThis, pThisCC, off + 7, &rc) << 56);
3523	break;
3524
3525	default:
3526	{
3527	uint8_t pbData = (uint8_t )pv;
3528	while (cb-- > 0)
3529	{
3530	*pbData++ = vga_mem_readb(pDevIns, pThis, pThisCC, off++, &rc);
3531	if (RT_UNLIKELY(rc != VINF_SUCCESS))
3532	break;
3533	}
3534	}
3535	}
3536
3537	STAM_PROFILE_STOP(&pThis->CTX_MID_Z(Stat,MemoryRead), a);
3538	return rc;
3539	}
3540
3541	/**
3542	* @callback_method_impl{FNIOMMMIONEWWRITE,
3543	* Legacy VGA memory (0xa0000 - 0xbffff) write hook\, to be called from IOM.}
3544	*/
3545	static DECLCALLBACK(VBOXSTRICTRC) vgaMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3546	{
3547	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3548	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3549	uint8_t const pbSrc = (uint8_t const )pv;
3550	NOREF(pvUser);
3551	STAM_PROFILE_START(&pThis->CTX_MID_Z(Stat,MemoryWrite), a);
3552	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3553
3554	VBOXSTRICTRC rc;
3555	switch (cb)
3556	{
3557	case 1:
3558	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off, *pbSrc);
3559	break;
3560	#if 1
3561	case 2:
3562	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3563	if (RT_LIKELY(rc == VINF_SUCCESS))
3564	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3565	break;
3566	case 4:
3567	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3568	if (RT_LIKELY(rc == VINF_SUCCESS))
3569	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3570	if (RT_LIKELY(rc == VINF_SUCCESS))
3571	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 2, pbSrc[2]);
3572	if (RT_LIKELY(rc == VINF_SUCCESS))
3573	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 3, pbSrc[3]);
3574	break;
3575	case 8:
3576	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 0, pbSrc[0]);
3577	if (RT_LIKELY(rc == VINF_SUCCESS))
3578	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 1, pbSrc[1]);
3579	if (RT_LIKELY(rc == VINF_SUCCESS))
3580	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 2, pbSrc[2]);
3581	if (RT_LIKELY(rc == VINF_SUCCESS))
3582	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 3, pbSrc[3]);
3583	if (RT_LIKELY(rc == VINF_SUCCESS))
3584	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 4, pbSrc[4]);
3585	if (RT_LIKELY(rc == VINF_SUCCESS))
3586	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 5, pbSrc[5]);
3587	if (RT_LIKELY(rc == VINF_SUCCESS))
3588	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 6, pbSrc[6]);
3589	if (RT_LIKELY(rc == VINF_SUCCESS))
3590	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off + 7, pbSrc[7]);
3591	break;
3592	#else
3593	case 2:
3594	rc = vgaMmioFill(pDevIns, off, (uint16_t )pv, 2, 1);
3595	break;
3596	case 4:
3597	rc = vgaMmioFill(pDevIns, off, (uint32_t )pv, 4, 1);
3598	break;
3599	case 8:
3600	rc = vgaMmioFill(pDevIns, off, (uint64_t )pv, 8, 1);
3601	break;
3602	#endif
3603	default:
3604	rc = VINF_SUCCESS;
3605	while (cb-- > 0 && rc == VINF_SUCCESS)
3606	rc = vga_mem_writeb(pDevIns, pThis, pThisCC, off++, *pbSrc++);
3607	break;
3608
3609	}
3610	STAM_PROFILE_STOP(&pThis->CTX_MID_Z(Stat,MemoryWrite), a);
3611	return rc;
3612	}
3613
3614
3615	/**
3616	* Handle LFB access.
3617	*
3618	* @returns Strict VBox status code.
3619	* @param pVM VM handle.
3620	* @param pDevIns The device instance.
3621	* @param pThis The shared VGA instance data.
3622	* @param GCPhys The access physical address.
3623	* @param GCPtr The access virtual address (only GC).
3624	*/
3625	static VBOXSTRICTRC vgaLFBAccess(PVMCC pVM, PPDMDEVINS pDevIns, PVGASTATE pThis, RTGCPHYS GCPhys, RTGCPTR GCPtr)
3626	{
3627	VBOXSTRICTRC rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_EM_RAW_EMULATE_INSTR);
3628	if (rc == VINF_SUCCESS)
3629	{
3630	/*
3631	* Set page dirty bit.
3632	*/
3633	vgaR3MarkDirty(pThis, GCPhys - pThis->GCPhysVRAM);
3634	pThis->fLFBUpdated = true;
3635
3636	/*
3637	* Turn of the write handler for this particular page and make it R/W.
3638	* Then return telling the caller to restart the guest instruction.
3639	* ASSUME: the guest always maps video memory RW.
3640	*/
3641	rc = PGMHandlerPhysicalPageTempOff(pVM, pThis->GCPhysVRAM, GCPhys);
3642	if (RT_SUCCESS(rc))
3643	{
3644	#ifndef IN_RING3
3645	rc = PGMShwMakePageWritable(PDMDevHlpGetVMCPU(pDevIns), GCPtr,
3646	PGM_MK_PG_IS_MMIO2 \| PGM_MK_PG_IS_WRITE_FAULT);
3647	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3648	AssertMsgReturn( rc == VINF_SUCCESS
3649	/* In the SMP case the page table might be removed while we wait for the PGM lock in the trap handler. */
3650	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
3651	\|\| rc == VERR_PAGE_NOT_PRESENT,
3652	("PGMShwModifyPage -> GCPtr=%RGv rc=%d\n", GCPtr, VBOXSTRICTRC_VAL(rc)),
3653	rc);
3654	#else /* IN_RING3 - We don't have any virtual page address of the access here. */
3655	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3656	Assert(GCPtr == 0);
3657	RT_NOREF1(GCPtr);
3658	#endif
3659	return VINF_SUCCESS;
3660	}
3661
3662	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
3663	AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", VBOXSTRICTRC_VAL(rc)));
3664	}
3665	return rc;
3666	}
3667
3668
3669	#ifndef IN_RING3
3670	/**
3671	* @callback_method_impl{FNPGMRCPHYSHANDLER, \#PF Handler for VBE LFB access.}
3672	*/
3673	PDMBOTHCBDECL(VBOXSTRICTRC) vgaLbfAccessPfHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,
3674	RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3675	{
3676	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3677	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3678	//PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3679	Assert(GCPhysFault >= pThis->GCPhysVRAM);
3680	AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3681	RT_NOREF3(pVCpu, pRegFrame, uErrorCode);
3682
3683	return vgaLFBAccess(pVM, pDevIns, pThis, GCPhysFault, pvFault);
3684	}
3685	#endif /* !IN_RING3 */
3686
3687
3688	/**
3689	* @callback_method_impl{FNPGMPHYSHANDLER,
3690	* VBE LFB write access handler for the dirty tracking.}
3691	*/
3692	PGM_ALL_CB_DECL(VBOXSTRICTRC) vgaLFBAccessHandler(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, void *pvPhys,
3693	void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
3694	PGMACCESSORIGIN enmOrigin, void *pvUser)
3695	{
3696	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3697	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3698	//PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3699	Assert(GCPhys >= pThis->GCPhysVRAM);
3700	RT_NOREF(pVCpu, pvPhys, pvBuf, cbBuf, enmAccessType, enmOrigin);
3701
3702	VBOXSTRICTRC rc = vgaLFBAccess(pVM, pDevIns, pThis, GCPhys, 0);
3703	if (rc == VINF_SUCCESS)
3704	rc = VINF_PGM_HANDLER_DO_DEFAULT;
3705	#ifdef IN_RING3
3706	else
3707	AssertMsg(rc < VINF_SUCCESS, ("rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
3708	#endif
3709	return rc;
3710	}
3711
3712
3713	/* -=-=-=-=-=- All rings: VGA BIOS I/Os -=-=-=-=-=- */
3714
3715	/**
3716	* @callback_method_impl{FNIOMIOPORTNEWIN,
3717	* Port I/O Handler for VGA BIOS IN operations.}
3718	*/
3719	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortReadBios(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3720	{
3721	RT_NOREF(pDevIns, pvUser, offPort, pu32, cb);
3722	return VERR_IOM_IOPORT_UNUSED;
3723	}
3724
3725	/**
3726	* @callback_method_impl{FNIOMIOPORTNEWOUT,
3727	* Port I/O Handler for VGA BIOS IN operations.}
3728	*/
3729	static DECLCALLBACK(VBOXSTRICTRC) vgaIoPortWriteBios(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3730	{
3731	RT_NOREF2(pDevIns, pvUser);
3732	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3733	Assert(offPort == 0); RT_NOREF(offPort);
3734
3735	/*
3736	* VGA BIOS char printing.
3737	*/
3738	if (cb == 1)
3739	{
3740	#if 0
3741	switch (u32)
3742	{
3743	case '\r': Log(("vgabios: <return>\n")); break;
3744	case '\n': Log(("vgabios: <newline>\n")); break;
3745	case '\t': Log(("vgabios: <tab>\n")); break;
3746	default:
3747	Log(("vgabios: %c\n", u32));
3748	}
3749	#else
3750	static int s_fLastWasNotNewline = 0; /* We are only called in a single-threaded way */
3751	if (s_fLastWasNotNewline == 0)
3752	Log(("vgabios: "));
3753	if (u32 != '\r') /* return - is only sent in conjunction with '\n' */
3754	Log(("%c", u32));
3755	if (u32 == '\n')
3756	s_fLastWasNotNewline = 0;
3757	else
3758	s_fLastWasNotNewline = 1;
3759	#endif
3760	return VINF_SUCCESS;
3761	}
3762
3763	/* not in use. */
3764	return VERR_IOM_IOPORT_UNUSED;
3765	}
3766
3767
3768	/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3769
3770	#ifdef IN_RING3
3771
3772	/**
3773	* @callback_method_impl{FNIOMIOPORTNEWOUT,
3774	* Port I/O Handler for VBE Extra OUT operations.}
3775	*/
3776	static DECLCALLBACK(VBOXSTRICTRC)
3777	vbeR3IOPortWriteVbeExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
3778	{
3779	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3780	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3781	RT_NOREF(offPort, pvUser);
3782
3783	if (cb == 2)
3784	{
3785	Log(("vbeR3IOPortWriteVbeExtra: addr=%#RX32\n", u32));
3786	pThisCC->u16VBEExtraAddress = u32;
3787	}
3788	else
3789	Log(("vbeR3IOPortWriteVbeExtra: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
3790
3791	return VINF_SUCCESS;
3792	}
3793
3794
3795	/**
3796	* @callback_method_impl{FNIOMIOPORTNEWIN,
3797	* Port I/O Handler for VBE Extra IN operations.}
3798	*/
3799	static DECLCALLBACK(VBOXSTRICTRC)
3800	vbeR3IoPortReadVbeExtra(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
3801	{
3802	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
3803	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
3804	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo)));
3805	RT_NOREF(offPort, pvUser);
3806
3807	int rc = VINF_SUCCESS;
3808	if (pThisCC->u16VBEExtraAddress == 0xffff)
3809	{
3810	Log(("vbeR3IoPortReadVbeExtra: Requested number of 64k video banks\n"));
3811	*pu32 = pThis->vram_size / _64K;
3812	}
3813	else if ( pThisCC->u16VBEExtraAddress >= pThisCC->cbVBEExtraData
3814	\|\| pThisCC->u16VBEExtraAddress + cb > pThisCC->cbVBEExtraData)
3815	{
3816	*pu32 = 0;
3817	Log(("vbeR3IoPortReadVbeExtra: Requested address is out of VBE data!!! Address=%#x(%d) cbVBEExtraData=%#x(%d)\n",
3818	pThisCC->u16VBEExtraAddress, pThisCC->u16VBEExtraAddress, pThisCC->cbVBEExtraData, pThisCC->cbVBEExtraData));
3819	}
3820	else
3821	{
3822	RT_UNTRUSTED_VALIDATED_FENCE();
3823	if (cb == 1)
3824	{
3825	*pu32 = pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress] & 0xFF;
3826
3827	Log(("vbeR3IoPortReadVbeExtra: cb=%#x %.*Rhxs\n", cb, cb, pu32));
3828	}
3829	else if (cb == 2)
3830	{
3831	*pu32 = pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress]
3832	\| (uint32_t)pThisCC->pbVBEExtraData[pThisCC->u16VBEExtraAddress + 1] << 8;
3833
3834	Log(("vbeR3IoPortReadVbeExtra: cb=%#x %.*Rhxs\n", cb, cb, pu32));
3835	}
3836	else
3837	{
3838	Log(("vbeR3IoPortReadVbeExtra: Invalid cb=%d read from the VBE Extra port!!!\n", cb));
3839	rc = VERR_IOM_IOPORT_UNUSED;
3840	}
3841	}
3842
3843	return rc;
3844	}
3845
3846
3847	/**
3848	* Parse the logo bitmap data at init time.
3849	*
3850	* @returns VBox status code.
3851	*
3852	* @param pThisCC The VGA instance data for ring-3.
3853	*/
3854	static int vbeR3ParseBitmap(PVGASTATECC pThisCC)
3855	{
3856	/*
3857	* Get bitmap header data
3858	*/
3859	PBMPFILEHDR pFileHdr = (PBMPFILEHDR)(pThisCC->pbLogo + sizeof(LOGOHDR));
3860	PBMPWIN3XINFOHDR pCoreHdr = (PBMPWIN3XINFOHDR)(pThisCC->pbLogo + sizeof(LOGOHDR) + sizeof(BMPFILEHDR));
3861
3862	if (pFileHdr->uType == BMP_HDR_MAGIC)
3863	{
3864	switch (pCoreHdr->cbSize)
3865	{
3866	case BMP_HDR_SIZE_OS21:
3867	{
3868	PBMPOS2COREHDR pOs2Hdr = (PBMPOS2COREHDR)pCoreHdr;
3869	pThisCC->cxLogo = pOs2Hdr->uWidth;
3870	pThisCC->cyLogo = pOs2Hdr->uHeight;
3871	pThisCC->cLogoPlanes = pOs2Hdr->cPlanes;
3872	pThisCC->cLogoBits = pOs2Hdr->cBits;
3873	pThisCC->LogoCompression = BMP_COMPRESSION_TYPE_NONE;
3874	pThisCC->cLogoUsedColors = 0;
3875	break;
3876	}
3877
3878	case BMP_HDR_SIZE_OS22:
3879	{
3880	PBMPOS2COREHDR2 pOs22Hdr = (PBMPOS2COREHDR2)pCoreHdr;
3881	pThisCC->cxLogo = pOs22Hdr->uWidth;
3882	pThisCC->cyLogo = pOs22Hdr->uHeight;
3883	pThisCC->cLogoPlanes = pOs22Hdr->cPlanes;
3884	pThisCC->cLogoBits = pOs22Hdr->cBits;
3885	pThisCC->LogoCompression = pOs22Hdr->enmCompression;
3886	pThisCC->cLogoUsedColors = pOs22Hdr->cClrUsed;
3887	break;
3888	}
3889
3890	case BMP_HDR_SIZE_WIN3X:
3891	pThisCC->cxLogo = pCoreHdr->uWidth;
3892	pThisCC->cyLogo = pCoreHdr->uHeight;
3893	pThisCC->cLogoPlanes = pCoreHdr->cPlanes;
3894	pThisCC->cLogoBits = pCoreHdr->cBits;
3895	pThisCC->LogoCompression = pCoreHdr->enmCompression;
3896	pThisCC->cLogoUsedColors = pCoreHdr->cClrUsed;
3897	break;
3898
3899	default:
3900	AssertLogRelMsgFailedReturn(("Unsupported bitmap header size %u.\n", pCoreHdr->cbSize),
3901	VERR_INVALID_PARAMETER);
3902	break;
3903	}
3904
3905	AssertLogRelMsgReturn(pThisCC->cxLogo <= LOGO_MAX_WIDTH && pThisCC->cyLogo <= LOGO_MAX_HEIGHT,
3906	("Bitmap %ux%u is too big.\n", pThisCC->cxLogo, pThisCC->cyLogo),
3907	VERR_INVALID_PARAMETER);
3908
3909	AssertLogRelMsgReturn(pThisCC->cLogoPlanes == 1,
3910	("Bitmap planes %u != 1.\n", pThisCC->cLogoPlanes),
3911	VERR_INVALID_PARAMETER);
3912
3913	AssertLogRelMsgReturn(pThisCC->cLogoBits == 4 \|\| pThisCC->cLogoBits == 8 \|\| pThisCC->cLogoBits == 24,
3914	("Unsupported %u depth.\n", pThisCC->cLogoBits),
3915	VERR_INVALID_PARAMETER);
3916
3917	AssertLogRelMsgReturn(pThisCC->cLogoUsedColors <= 256,
3918	("Unsupported %u colors.\n", pThisCC->cLogoUsedColors),
3919	VERR_INVALID_PARAMETER);
3920
3921	AssertLogRelMsgReturn(pThisCC->LogoCompression == BMP_COMPRESSION_TYPE_NONE,
3922	("Unsupported %u compression.\n", pThisCC->LogoCompression),
3923	VERR_INVALID_PARAMETER);
3924
3925	/*
3926	* Read bitmap palette
3927	*/
3928	if (!pThisCC->cLogoUsedColors)
3929	pThisCC->cLogoPalEntries = 1 << (pThisCC->cLogoPlanes * pThisCC->cLogoBits);
3930	else
3931	pThisCC->cLogoPalEntries = pThisCC->cLogoUsedColors;
3932
3933	if (pThisCC->cLogoPalEntries)
3934	{
3935	const uint8_t pbPal = pThisCC->pbLogo + sizeof(LOGOHDR) + sizeof(BMPFILEHDR) + pCoreHdr->cbSize; / ASSUMES Size location (safe) */
3936
3937	for (uint16_t i = 0; i < pThisCC->cLogoPalEntries; i++)
3938	{
3939	uint16_t j;
3940	uint32_t u32Pal = 0;
3941
3942	for (j = 0; j < 3; j++)
3943	{
3944	uint8_t b = *pbPal++;
3945	u32Pal <<= 8;
3946	u32Pal \|= b;
3947	}
3948
3949	pbPal++; /* skip unused byte */
3950	pThisCC->au32LogoPalette[i] = u32Pal;
3951	}
3952	}
3953
3954	/*
3955	* Bitmap data offset
3956	*/
3957	pThisCC->pbLogoBitmap = pThisCC->pbLogo + sizeof(LOGOHDR) + pFileHdr->offBits;
3958	}
3959	else
3960	AssertLogRelMsgFailedReturn(("Not a BMP file.\n"), VERR_INVALID_PARAMETER);
3961
3962	return VINF_SUCCESS;
3963	}
3964
3965
3966	/**
3967	* Show logo bitmap data.
3968	*
3969	* @returns VBox status code.
3970	*
3971	* @param cBits Logo depth.
3972	* @param xLogo Logo X position.
3973	* @param yLogo Logo Y position.
3974	* @param cxLogo Logo width.
3975	* @param cyLogo Logo height.
3976	* @param fInverse True if the bitmask is black on white (only for 1bpp)
3977	* @param iStep Fade in/fade out step.
3978	* @param pu32Palette Palette data.
3979	* @param pbSrc Source buffer.
3980	* @param pbDst Destination buffer.
3981	*/
3982	static void vbeR3ShowBitmap(uint16_t cBits, uint16_t xLogo, uint16_t yLogo, uint16_t cxLogo, uint16_t cyLogo,
3983	bool fInverse, uint8_t iStep, const uint32_t pu32Palette, const uint8_t pbSrc, uint8_t *pbDst)
3984	{
3985	uint16_t i;
3986	size_t cbPadBytes = 0;
3987	size_t cbLineDst = LOGO_MAX_WIDTH * 4;
3988	uint16_t cyLeft = cyLogo;
3989
3990	pbDst += xLogo * 4 + yLogo * cbLineDst;
3991
3992	switch (cBits)
3993	{
3994	case 1:
3995	pbDst += cyLogo * cbLineDst;
3996	cbPadBytes = 0;
3997	break;
3998
3999	case 4:
4000	if (((cxLogo % 8) == 0) \|\| ((cxLogo % 8) > 6))
4001	cbPadBytes = 0;
4002	else if ((cxLogo % 8) <= 2)
4003	cbPadBytes = 3;
4004	else if ((cxLogo % 8) <= 4)
4005	cbPadBytes = 2;
4006	else
4007	cbPadBytes = 1;
4008	break;
4009
4010	case 8:
4011	cbPadBytes = ((cxLogo % 4) == 0) ? 0 : (4 - (cxLogo % 4));
4012	break;
4013
4014	case 24:
4015	cbPadBytes = cxLogo % 4;
4016	break;
4017	}
4018
4019	uint8_t j = 0, c = 0;
4020
4021	while (cyLeft-- > 0)
4022	{
4023	uint8_t *pbTmpDst = pbDst;
4024
4025	if (cBits != 1)
4026	j = 0;
4027
4028	for (i = 0; i < cxLogo; i++)
4029	{
4030	switch (cBits)
4031	{
4032	case 1:
4033	{
4034	if (!j)
4035	c = *pbSrc++;
4036
4037	if (c & 1)
4038	{
4039	if (fInverse)
4040	{
4041	*pbTmpDst++ = 0;
4042	*pbTmpDst++ = 0;
4043	*pbTmpDst++ = 0;
4044	pbTmpDst++;
4045	}
4046	else
4047	{
4048	uint8_t pix = 0xFF * iStep / LOGO_SHOW_STEPS;
4049	*pbTmpDst++ = pix;
4050	*pbTmpDst++ = pix;
4051	*pbTmpDst++ = pix;
4052	pbTmpDst++;
4053	}
4054	}
4055	else
4056	pbTmpDst += 4;
4057	c >>= 1;
4058	j = (j + 1) % 8;
4059	break;
4060	}
4061
4062	case 4:
4063	{
4064	if (!j)
4065	c = *pbSrc++;
4066
4067	uint8_t pix = (c >> 4) & 0xF;
4068	c <<= 4;
4069
4070	uint32_t u32Pal = pu32Palette[pix];
4071
4072	pix = (u32Pal >> 16) & 0xFF;
4073	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4074	pix = (u32Pal >> 8) & 0xFF;
4075	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4076	pix = u32Pal & 0xFF;
4077	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4078	pbTmpDst++;
4079
4080	j = (j + 1) % 2;
4081	break;
4082	}
4083
4084	case 8:
4085	{
4086	uint32_t u32Pal = pu32Palette[*pbSrc++];
4087
4088	uint8_t pix = (u32Pal >> 16) & 0xFF;
4089	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4090	pix = (u32Pal >> 8) & 0xFF;
4091	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4092	pix = u32Pal & 0xFF;
4093	pbTmpDst++ = pix iStep / LOGO_SHOW_STEPS;
4094	pbTmpDst++;
4095	break;
4096	}
4097
4098	case 24:
4099	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4100	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4101	pbTmpDst++ = pbSrc++ * iStep / LOGO_SHOW_STEPS;
4102	pbTmpDst++;
4103	break;
4104	}
4105	}
4106
4107	pbDst -= cbLineDst;
4108	pbSrc += cbPadBytes;
4109	}
4110	}
4111
4112
4113	/**
4114	* @callback_method_impl{FNIOMIOPORTNEWOUT,
4115	* Port I/O Handler for BIOS Logo OUT operations.}
4116	*/
4117	static DECLCALLBACK(VBOXSTRICTRC)
4118	vbeR3IoPortWriteCmdLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
4119	{
4120	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4121	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4122	RT_NOREF(pvUser, offPort);
4123
4124	Log(("vbeR3IoPortWriteCmdLogo: cb=%d u32=%#04x(%#04d) (byte)\n", cb, u32, u32));
4125
4126	if (cb == 2)
4127	{
4128	/* Get the logo command */
4129	switch (u32 & 0xFF00)
4130	{
4131	case LOGO_CMD_SET_OFFSET:
4132	pThisCC->offLogoData = u32 & 0xFF;
4133	break;
4134
4135	case LOGO_CMD_SHOW_BMP:
4136	{
4137	uint8_t iStep = u32 & 0xFF;
4138	const uint8_t *pbSrc = pThisCC->pbLogoBitmap;
4139	uint8_t *pbDst;
4140	PCLOGOHDR pLogoHdr = (PCLOGOHDR)pThisCC->pbLogo;
4141	uint32_t offDirty = 0;
4142	uint16_t xLogo = (LOGO_MAX_WIDTH - pThisCC->cxLogo) / 2;
4143	uint16_t yLogo = LOGO_MAX_HEIGHT - (LOGO_MAX_HEIGHT - pThisCC->cyLogo) / 2;
4144
4145	/* Check VRAM size */
4146	if (pThis->vram_size < LOGO_MAX_SIZE)
4147	break;
4148
4149	if (pThis->vram_size >= LOGO_MAX_SIZE * 2)
4150	pbDst = pThisCC->pbVRam + LOGO_MAX_SIZE;
4151	else
4152	pbDst = pThisCC->pbVRam;
4153
4154	/* Clear screen - except on power on... */
4155	if (!pThisCC->fLogoClearScreen)
4156	{
4157	/* Clear vram */
4158	uint32_t pu32Dst = (uint32_t )pbDst;
4159	for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4160	for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4161	*pu32Dst++ = 0;
4162	pThisCC->fLogoClearScreen = true;
4163	}
4164
4165	/* Show the bitmap. */
4166	vbeR3ShowBitmap(pThisCC->cLogoBits, xLogo, yLogo,
4167	pThisCC->cxLogo, pThisCC->cyLogo,
4168	false, iStep, &pThisCC->au32LogoPalette[0],
4169	pbSrc, pbDst);
4170
4171	/* Show the 'Press F12...' text. */
4172	if (pLogoHdr->fu8ShowBootMenu == 2)
4173	vbeR3ShowBitmap(1, LOGO_F12TEXT_X, LOGO_F12TEXT_Y,
4174	LOGO_F12TEXT_WIDTH, LOGO_F12TEXT_HEIGHT,
4175	pThisCC->fBootMenuInverse, iStep, &pThisCC->au32LogoPalette[0],
4176	&g_abLogoF12BootText[0], pbDst);
4177
4178	/* Blit the offscreen buffer. */
4179	if (pThis->vram_size >= LOGO_MAX_SIZE * 2)
4180	{
4181	uint32_t pu32TmpDst = (uint32_t )pThisCC->pbVRam;
4182	uint32_t pu32TmpSrc = (uint32_t )(pThisCC->pbVRam + LOGO_MAX_SIZE);
4183	for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4184	{
4185	for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4186	pu32TmpDst++ = pu32TmpSrc++;
4187	}
4188	}
4189
4190	/* Set the dirty flags. */
4191	while (offDirty <= LOGO_MAX_SIZE)
4192	{
4193	vgaR3MarkDirty(pThis, offDirty);
4194	offDirty += PAGE_SIZE;
4195	}
4196	break;
4197	}
4198
4199	default:
4200	Log(("vbeR3IoPortWriteCmdLogo: invalid command %d\n", u32));
4201	pThisCC->LogoCommand = LOGO_CMD_NOP;
4202	break;
4203	}
4204
4205	return VINF_SUCCESS;
4206	}
4207
4208	Log(("vbeR3IoPortWriteCmdLogo: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
4209	return VINF_SUCCESS;
4210	}
4211
4212
4213	/**
4214	* @callback_method_impl{FNIOMIOPORTIN,
4215	* Port I/O Handler for BIOS Logo IN operations.}
4216	*/
4217	static DECLCALLBACK(VBOXSTRICTRC)
4218	vbeR3IoPortReadCmdLogo(PPDMDEVINS pDevIns, void pvUser, RTIOPORT offPort, uint32_t pu32, unsigned cb)
4219	{
4220	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4221	RT_NOREF(pvUser, offPort);
4222
4223	if (pThisCC->offLogoData + cb > pThisCC->cbLogo)
4224	{
4225	Log(("vbeR3IoPortReadCmdLogo: Requested address is out of Logo data!!! offLogoData=%#x(%d) cbLogo=%#x(%d)\n",
4226	pThisCC->offLogoData, pThisCC->offLogoData, pThisCC->cbLogo, pThisCC->cbLogo));
4227	return VINF_SUCCESS;
4228	}
4229	RT_UNTRUSTED_VALIDATED_FENCE();
4230
4231	PCRTUINT64U p = (PCRTUINT64U)&pThisCC->pbLogo[pThisCC->offLogoData];
4232	switch (cb)
4233	{
4234	case 1: *pu32 = p->au8[0]; break;
4235	case 2: *pu32 = p->au16[0]; break;
4236	case 4: *pu32 = p->au32[0]; break;
4237	//case 8: *pu32 = p->au64[0]; break;
4238	default: AssertFailed(); break;
4239	}
4240	Log(("vbeR3IoPortReadCmdLogo: LogoOffset=%#x(%d) cb=%#x %.*Rhxs\n", pThisCC->offLogoData, pThisCC->offLogoData, cb, cb, pu32));
4241
4242	pThisCC->LogoCommand = LOGO_CMD_NOP;
4243	pThisCC->offLogoData += cb;
4244
4245	return VINF_SUCCESS;
4246	}
4247
4248
4249	/* -=-=-=-=-=- Ring 3: Debug Info Handlers -=-=-=-=-=- */
4250
4251	/**
4252	* @callback_method_impl{FNDBGFHANDLERDEV,
4253	* Dumps several interesting bits of the VGA state that are difficult to
4254	* decode from the registers.}
4255	*/
4256	static DECLCALLBACK(void) vgaR3InfoState(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4257	{
4258	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4259	int is_graph, double_scan;
4260	int w, h, char_height, char_dots;
4261	int val, vfreq_hz, hfreq_hz;
4262	vga_retrace_s *r = &pThis->retrace_state;
4263	const char *clocks[] = { "25.175 MHz", "28.322 MHz", "External", "Reserved?!" };
4264	NOREF(pszArgs);
4265
4266	is_graph = pThis->gr[6] & 1;
4267	char_dots = (pThis->sr[0x01] & 1) ? 8 : 9;
4268	double_scan = pThis->cr[9] >> 7;
4269	pHlp->pfnPrintf(pHlp, "pixel clock: %s\n", clocks[(pThis->msr >> 2) & 3]);
4270	pHlp->pfnPrintf(pHlp, "double scanning %s\n", double_scan ? "on" : "off");
4271	pHlp->pfnPrintf(pHlp, "double clocking %s\n", pThis->sr[1] & 0x08 ? "on" : "off");
4272	val = pThis->cr[0] + 5;
4273	pHlp->pfnPrintf(pHlp, "htotal: %d px (%d cclk)\n", val * char_dots, val);
4274	val = pThis->cr[6] + ((pThis->cr[7] & 1) << 8) + ((pThis->cr[7] & 0x20) << 4) + 2;
4275	pHlp->pfnPrintf(pHlp, "vtotal: %d px\n", val);
4276	val = pThis->cr[1] + 1;
4277	w = val * char_dots;
4278	pHlp->pfnPrintf(pHlp, "hdisp : %d px (%d cclk)\n", w, val);
4279	val = pThis->cr[0x12] + ((pThis->cr[7] & 2) << 7) + ((pThis->cr[7] & 0x40) << 4) + 1;
4280	h = val;
4281	pHlp->pfnPrintf(pHlp, "vdisp : %d px\n", val);
4282	val = ((pThis->cr[9] & 0x40) << 3) + ((pThis->cr[7] & 0x10) << 4) + pThis->cr[0x18];
4283	pHlp->pfnPrintf(pHlp, "split : %d ln\n", val);
4284	val = (pThis->cr[0xc] << 8) + pThis->cr[0xd];
4285	pHlp->pfnPrintf(pHlp, "start : %#x\n", val);
4286	if (!is_graph)
4287	{
4288	val = (pThis->cr[9] & 0x1f) + 1;
4289	char_height = val;
4290	pHlp->pfnPrintf(pHlp, "char height %d\n", val);
4291	pHlp->pfnPrintf(pHlp, "text mode %dx%d\n", w / char_dots, h / (char_height << double_scan));
4292
4293	uint32_t cbLine;
4294	uint32_t offStart;
4295	uint32_t uLineCompareIgn;
4296	vgaR3GetOffsets(pThis, &cbLine, &offStart, &uLineCompareIgn);
4297	if (!cbLine)
4298	cbLine = 80 * 8;
4299	offStart *= 8;
4300	pHlp->pfnPrintf(pHlp, "cbLine: %#x\n", cbLine);
4301	pHlp->pfnPrintf(pHlp, "offStart: %#x (line %#x)\n", offStart, offStart / cbLine);
4302	}
4303	if (pThis->fRealRetrace)
4304	{
4305	val = r->hb_start;
4306	pHlp->pfnPrintf(pHlp, "hblank start: %d px (%d cclk)\n", val * char_dots, val);
4307	val = r->hb_end;
4308	pHlp->pfnPrintf(pHlp, "hblank end : %d px (%d cclk)\n", val * char_dots, val);
4309	pHlp->pfnPrintf(pHlp, "vblank start: %d px, end: %d px\n", r->vb_start, r->vb_end);
4310	pHlp->pfnPrintf(pHlp, "vsync start : %d px, end: %d px\n", r->vs_start, r->vs_end);
4311	pHlp->pfnPrintf(pHlp, "cclks per frame: %d\n", r->frame_cclks);
4312	pHlp->pfnPrintf(pHlp, "cclk time (ns) : %d\n", r->cclk_ns);
4313	if (r->frame_ns && r->h_total_ns) /* Careful in case state is temporarily invalid. */
4314	{
4315	vfreq_hz = 1000000000 / r->frame_ns;
4316	hfreq_hz = 1000000000 / r->h_total_ns;
4317	pHlp->pfnPrintf(pHlp, "vfreq: %d Hz, hfreq: %d.%03d kHz\n",
4318	vfreq_hz, hfreq_hz / 1000, hfreq_hz % 1000);
4319	}
4320	}
4321	pHlp->pfnPrintf(pHlp, "display refresh interval: %u ms\n", pThis->cMilliesRefreshInterval);
4322
4323	# ifdef VBOX_WITH_VMSVGA
4324	if (pThis->svga.fEnabled)
4325	pHlp->pfnPrintf(pHlp, pThis->svga.f3DEnabled ? "VMSVGA 3D enabled: %ux%ux%u\n" : "VMSVGA enabled: %ux%ux%u",
4326	pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp);
4327	# endif
4328	}
4329
4330
4331	/**
4332	* Prints a separator line.
4333	*
4334	* @param pHlp Callback functions for doing output.
4335	* @param cCols The number of columns.
4336	* @param pszTitle The title text, NULL if none.
4337	*/
4338	static void vgaR3InfoTextPrintSeparatorLine(PCDBGFINFOHLP pHlp, size_t cCols, const char *pszTitle)
4339	{
4340	if (pszTitle)
4341	{
4342	size_t cchTitle = strlen(pszTitle);
4343	if (cchTitle + 6 >= cCols)
4344	{
4345	pHlp->pfnPrintf(pHlp, "-- %s --", pszTitle);
4346	cCols = 0;
4347	}
4348	else
4349	{
4350	size_t cchLeft = (cCols - cchTitle - 2) / 2;
4351	cCols -= cchLeft + cchTitle + 2;
4352	while (cchLeft-- > 0)
4353	pHlp->pfnPrintf(pHlp, "-");
4354	pHlp->pfnPrintf(pHlp, " %s ", pszTitle);
4355	}
4356	}
4357
4358	while (cCols-- > 0)
4359	pHlp->pfnPrintf(pHlp, "-");
4360	pHlp->pfnPrintf(pHlp, "\n");
4361	}
4362
4363
4364	/**
4365	* Worker for vgaR3InfoText.
4366	*
4367	* @param pThis The shared VGA state.
4368	* @param pThisCC The VGA state for ring-3.
4369	* @param pHlp Callback functions for doing output.
4370	* @param offStart Where to start dumping (relative to the VRAM).
4371	* @param cbLine The source line length (aka line_offset).
4372	* @param cCols The number of columns on the screen.
4373	* @param cRows The number of rows to dump.
4374	* @param iScrBegin The row at which the current screen output starts.
4375	* @param iScrEnd The row at which the current screen output end
4376	* (exclusive).
4377	*/
4378	static void vgaR3InfoTextWorker(PVGASTATE pThis, PVGASTATER3 pThisCC, PCDBGFINFOHLP pHlp,
4379	uint32_t offStart, uint32_t cbLine,
4380	uint32_t cCols, uint32_t cRows,
4381	uint32_t iScrBegin, uint32_t iScrEnd)
4382	{
4383	/* Title, */
4384	char szTitle[32];
4385	if (iScrBegin \|\| iScrEnd < cRows)
4386	RTStrPrintf(szTitle, sizeof(szTitle), "%ux%u (+%u before, +%u after)",
4387	cCols, iScrEnd - iScrBegin, iScrBegin, cRows - iScrEnd);
4388	else
4389	RTStrPrintf(szTitle, sizeof(szTitle), "%ux%u", cCols, iScrEnd - iScrBegin);
4390
4391	/* Do the dumping. */
4392	uint8_t const *pbSrcOuter = pThisCC->pbVRam + offStart;
4393	uint32_t iRow;
4394	for (iRow = 0; iRow < cRows; iRow++, pbSrcOuter += cbLine)
4395	{
4396	if ((uintptr_t)(pbSrcOuter + cbLine - pThisCC->pbVRam) > pThis->vram_size) {
4397	pHlp->pfnPrintf(pHlp, "The last %u row/rows is/are outside the VRAM.\n", cRows - iRow);
4398	break;
4399	}
4400
4401	if (iRow == 0)
4402	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, szTitle);
4403	else if (iRow == iScrBegin)
4404	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, "screen start");
4405	else if (iRow == iScrEnd)
4406	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, "screen end");
4407
4408	uint8_t const *pbSrc = pbSrcOuter;
4409	for (uint32_t iCol = 0; iCol < cCols; ++iCol)
4410	{
4411	if (RT_C_IS_PRINT(*pbSrc))
4412	pHlp->pfnPrintf(pHlp, "%c", *pbSrc);
4413	else
4414	pHlp->pfnPrintf(pHlp, ".");
4415	pbSrc += 8; /* chars are spaced 8 bytes apart */
4416	}
4417	pHlp->pfnPrintf(pHlp, "\n");
4418	}
4419
4420	/* Final separator. */
4421	vgaR3InfoTextPrintSeparatorLine(pHlp, cCols, NULL);
4422	}
4423
4424
4425	/**
4426	* @callback_method_impl{FNDBGFHANDLERDEV,
4427	* Dumps VGA memory formatted as ASCII text\, no attributes. Only looks at
4428	* the first page.}
4429	*/
4430	static DECLCALLBACK(void) vgaR3InfoText(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4431	{
4432	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4433	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
4434
4435	/*
4436	* Parse args.
4437	*/
4438	bool fAll = true;
4439	if (pszArgs && *pszArgs)
4440	{
4441	if (!strcmp(pszArgs, "all"))
4442	fAll = true;
4443	else if (!strcmp(pszArgs, "scr") \|\| !strcmp(pszArgs, "screen"))
4444	fAll = false;
4445	else
4446	{
4447	pHlp->pfnPrintf(pHlp, "Invalid argument: '%s'\n", pszArgs);
4448	return;
4449	}
4450	}
4451
4452	/*
4453	* Check that we're in text mode and that the VRAM is accessible.
4454	*/
4455	if (!(pThis->gr[6] & 1))
4456	{
4457	uint8_t *pbSrc = pThisCC->pbVRam;
4458	if (pbSrc)
4459	{
4460	/*
4461	* Figure out the display size and where the text is.
4462	*
4463	* Note! We're cutting quite a few corners here and this code could
4464	* do with some brushing up. Dumping from the start of the
4465	* frame buffer is done intentionally so that we're more
4466	* likely to obtain the full scrollback of a linux panic.
4467	* windbg> .printf "------ start -----\n"; .for (r $t0 = 0; @$t0 < 25; r $t0 = @$t0 + 1) { .for (r $t1 = 0; @$t1 < 80; r $t1 = @$t1 + 1) { .printf "%c", by( (@$t0 * 80 + @$t1) * 8 + 100f0000) }; .printf "\n" }; .printf "------ end -----\n";
4468	*/
4469	uint32_t cbLine;
4470	uint32_t offStart;
4471	uint32_t uLineCompareIgn;
4472	vgaR3GetOffsets(pThis, &cbLine, &offStart, &uLineCompareIgn);
4473	if (!cbLine)
4474	cbLine = 80 * 8;
4475	offStart *= 8;
4476
4477	uint32_t uVDisp = pThis->cr[0x12] + ((pThis->cr[7] & 2) << 7) + ((pThis->cr[7] & 0x40) << 4) + 1;
4478	uint32_t uCharHeight = (pThis->cr[9] & 0x1f) + 1;
4479	uint32_t uDblScan = pThis->cr[9] >> 7;
4480	uint32_t cScrRows = uVDisp / (uCharHeight << uDblScan);
4481	if (cScrRows < 25)
4482	cScrRows = 25;
4483	uint32_t iScrBegin = offStart / cbLine;
4484	uint32_t cRows = iScrBegin + cScrRows;
4485	uint32_t cCols = cbLine / 8;
4486
4487	if (fAll)
4488	vgaR3InfoTextWorker(pThis, pThisCC, pHlp, offStart - iScrBegin * cbLine, cbLine,
4489	cCols, cRows, iScrBegin, iScrBegin + cScrRows);
4490	else
4491	vgaR3InfoTextWorker(pThis, pThisCC, pHlp, offStart, cbLine, cCols, cScrRows, 0, cScrRows);
4492	}
4493	else
4494	pHlp->pfnPrintf(pHlp, "VGA memory not available!\n");
4495	}
4496	else
4497	pHlp->pfnPrintf(pHlp, "Not in text mode!\n");
4498	}
4499
4500
4501	/**
4502	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA Sequencer registers.}
4503	*/
4504	static DECLCALLBACK(void) vgaR3InfoSR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4505	{
4506	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4507	NOREF(pszArgs);
4508
4509	pHlp->pfnPrintf(pHlp, "VGA Sequencer (3C5): SR index 3C4:%02X\n", pThis->sr_index);
4510	Assert(sizeof(pThis->sr) >= 8);
4511	for (unsigned i = 0; i < 8; ++i)
4512	pHlp->pfnPrintf(pHlp, " SR%02X:%02X", i, pThis->sr[i]);
4513	pHlp->pfnPrintf(pHlp, "\n");
4514	}
4515
4516
4517	/**
4518	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA CRTC registers.}
4519	*/
4520	static DECLCALLBACK(void) vgaR3InfoCR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4521	{
4522	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4523	unsigned i;
4524	NOREF(pszArgs);
4525
4526	pHlp->pfnPrintf(pHlp, "VGA CRTC (3D5): CRTC index 3D4:%02X\n", pThis->cr_index);
4527	Assert(sizeof(pThis->cr) >= 24);
4528	for (i = 0; i < 10; ++i)
4529	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4530	pHlp->pfnPrintf(pHlp, "\n");
4531	for (i = 10; i < 20; ++i)
4532	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4533	pHlp->pfnPrintf(pHlp, "\n");
4534	for (i = 20; i < 25; ++i)
4535	pHlp->pfnPrintf(pHlp, " CR%02X:%02X", i, pThis->cr[i]);
4536	pHlp->pfnPrintf(pHlp, "\n");
4537	}
4538
4539
4540	/**
4541	* @callback_method_impl{FNDBGFHANDLERDEV,
4542	* Dumps VGA Graphics Controller registers.}
4543	*/
4544	static DECLCALLBACK(void) vgaR3InfoGR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4545	{
4546	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4547	NOREF(pszArgs);
4548
4549	pHlp->pfnPrintf(pHlp, "VGA Graphics Controller (3CF): GR index 3CE:%02X\n", pThis->gr_index);
4550	Assert(sizeof(pThis->gr) >= 9);
4551	for (unsigned i = 0; i < 9; ++i)
4552	pHlp->pfnPrintf(pHlp, " GR%02X:%02X", i, pThis->gr[i]);
4553	pHlp->pfnPrintf(pHlp, "\n");
4554	}
4555
4556
4557	/**
4558	* @callback_method_impl{FNDBGFHANDLERDEV,
4559	* Dumps VGA Attribute Controller registers.}
4560	*/
4561	static DECLCALLBACK(void) vgaR3InfoAR(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4562	{
4563	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4564	unsigned i;
4565	NOREF(pszArgs);
4566
4567	pHlp->pfnPrintf(pHlp, "VGA Attribute Controller (3C0): index reg %02X, flip-flop: %d (%s)\n",
4568	pThis->ar_index, pThis->ar_flip_flop, pThis->ar_flip_flop ? "data" : "index" );
4569	Assert(sizeof(pThis->ar) >= 0x14);
4570	pHlp->pfnPrintf(pHlp, " Palette:");
4571	for (i = 0; i < 0x10; ++i)
4572	pHlp->pfnPrintf(pHlp, " %02X", pThis->ar[i]);
4573	pHlp->pfnPrintf(pHlp, "\n");
4574	for (i = 0x10; i <= 0x14; ++i)
4575	pHlp->pfnPrintf(pHlp, " AR%02X:%02X", i, pThis->ar[i]);
4576	pHlp->pfnPrintf(pHlp, "\n");
4577	}
4578
4579
4580	/**
4581	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VGA DAC registers.}
4582	*/
4583	static DECLCALLBACK(void) vgaR3InfoDAC(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4584	{
4585	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4586	NOREF(pszArgs);
4587
4588	pHlp->pfnPrintf(pHlp, "VGA DAC contents:\n");
4589	for (unsigned i = 0; i < 0x100; ++i)
4590	pHlp->pfnPrintf(pHlp, " %02X: %02X %02X %02X\n",
4591	i, pThis->palette[i3+0], pThis->palette[i3+1], pThis->palette[i*3+2]);
4592	}
4593
4594
4595	/**
4596	* @callback_method_impl{FNDBGFHANDLERDEV, Dumps VBE registers.}
4597	*/
4598	static DECLCALLBACK(void) vgaR3InfoVBE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4599	{
4600	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4601	NOREF(pszArgs);
4602
4603	pHlp->pfnPrintf(pHlp, "LFB at %RGp\n", pThis->GCPhysVRAM);
4604	if (!(pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED))
4605	pHlp->pfnPrintf(pHlp, "VBE disabled\n");
4606	else
4607	{
4608	pHlp->pfnPrintf(pHlp, "VBE state (chip ID 0x%04x):\n", pThis->vbe_regs[VBE_DISPI_INDEX_ID]);
4609	pHlp->pfnPrintf(pHlp, " Display resolution: %d x %d @ %dbpp\n",
4610	pThis->vbe_regs[VBE_DISPI_INDEX_XRES], pThis->vbe_regs[VBE_DISPI_INDEX_YRES],
4611	pThis->vbe_regs[VBE_DISPI_INDEX_BPP]);
4612	pHlp->pfnPrintf(pHlp, " Virtual resolution: %d x %d\n",
4613	pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], pThis->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT]);
4614	pHlp->pfnPrintf(pHlp, " Display start addr: %d, %d\n",
4615	pThis->vbe_regs[VBE_DISPI_INDEX_X_OFFSET], pThis->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET]);
4616	pHlp->pfnPrintf(pHlp, " Linear scanline pitch: 0x%04x\n", pThis->vbe_line_offset);
4617	pHlp->pfnPrintf(pHlp, " Linear display start : 0x%04x\n", pThis->vbe_start_addr);
4618	pHlp->pfnPrintf(pHlp, " Selected bank: 0x%04x\n", pThis->vbe_regs[VBE_DISPI_INDEX_BANK]);
4619	}
4620	}
4621
4622
4623	/**
4624	* @callback_method_impl{FNDBGFHANDLERDEV,
4625	* Dumps register state relevant to 16-color planar graphics modes (GR/SR)
4626	* in human-readable form.}
4627	*/
4628	static DECLCALLBACK(void) vgaR3InfoPlanar(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4629	{
4630	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4631	NOREF(pszArgs);
4632
4633	unsigned val1 = (pThis->gr[5] >> 3) & 1;
4634	unsigned val2 = pThis->gr[5] & 3;
4635	pHlp->pfnPrintf(pHlp, "read mode : %u write mode: %u\n", val1, val2);
4636	val1 = pThis->gr[0];
4637	val2 = pThis->gr[1];
4638	pHlp->pfnPrintf(pHlp, "set/reset data: %02X S/R enable: %02X\n", val1, val2);
4639	val1 = pThis->gr[2];
4640	val2 = pThis->gr[4] & 3;
4641	pHlp->pfnPrintf(pHlp, "color compare : %02X read map : %u\n", val1, val2);
4642	val1 = pThis->gr[3] & 7;
4643	val2 = (pThis->gr[3] >> 3) & 3;
4644	pHlp->pfnPrintf(pHlp, "rotate : %u function : %u\n", val1, val2);
4645	val1 = pThis->gr[7];
4646	val2 = pThis->gr[8];
4647	pHlp->pfnPrintf(pHlp, "don't care : %02X bit mask : %02X\n", val1, val2);
4648	val1 = pThis->sr[2];
4649	val2 = pThis->sr[4] & 8;
4650	pHlp->pfnPrintf(pHlp, "seq plane mask: %02X chain-4 : %s\n", val1, val2 ? "on" : "off");
4651	}
4652
4653
4654	/* -=-=-=-=-=- Ring 3: IBase -=-=-=-=-=- */
4655
4656	/**
4657	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4658	*/
4659	static DECLCALLBACK(void ) vgaR3PortQueryInterface(PPDMIBASE pInterface, const char pszIID)
4660	{
4661	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IBase);
4662	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4663	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIDISPLAYPORT, &pThisCC->IPort);
4664	# if defined(VBOX_WITH_HGSMI) && defined(VBOX_WITH_VIDEOHWACCEL)
4665	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIDISPLAYVBVACALLBACKS, &pThisCC->IVBVACallbacks);
4666	# endif
4667	PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
4668	return NULL;
4669	}
4670
4671
4672	/* -=-=-=-=-=- Ring 3: ILeds -=-=-=-=-=- */
4673
4674	/**
4675	* @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
4676	*/
4677	static DECLCALLBACK(int) vgaR3PortQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4678	{
4679	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, ILeds);
4680	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4681	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4682	switch (iLUN)
4683	{
4684	/* LUN #0 is the only one for which we have a status LED. */
4685	case 0:
4686	{
4687	*ppLed = &pThis->Led3D;
4688	Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
4689	return VINF_SUCCESS;
4690	}
4691
4692	default:
4693	AssertMsgFailed(("Invalid LUN #%u\n", iLUN));
4694	return VERR_PDM_NO_SUCH_LUN;
4695	}
4696	}
4697
4698
4699	/* -=-=-=-=-=- Ring 3: Dummy IDisplayConnector -=-=-=-=-=- */
4700
4701	/**
4702	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnResize}
4703	*/
4704	static DECLCALLBACK(int) vgaR3DummyResize(PPDMIDISPLAYCONNECTOR pInterface, uint32_t cBits, void *pvVRAM,
4705	uint32_t cbLine, uint32_t cx, uint32_t cy)
4706	{
4707	RT_NOREF(pInterface, cBits, pvVRAM, cbLine, cx, cy);
4708	return VINF_SUCCESS;
4709	}
4710
4711
4712	/**
4713	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnUpdateRect}
4714	*/
4715	static DECLCALLBACK(void) vgaR3DummyUpdateRect(PPDMIDISPLAYCONNECTOR pInterface, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4716	{
4717	RT_NOREF(pInterface, x, y, cx, cy);
4718	}
4719
4720
4721	/**
4722	* @interface_method_impl{PDMIDISPLAYCONNECTOR,pfnRefresh}
4723	*/
4724	static DECLCALLBACK(void) vgaR3DummyRefresh(PPDMIDISPLAYCONNECTOR pInterface)
4725	{
4726	NOREF(pInterface);
4727	}
4728
4729
4730	/* -=-=-=-=-=- Ring 3: IDisplayPort -=-=-=-=-=- */
4731
4732	/**
4733	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplay}
4734	*/
4735	static DECLCALLBACK(int) vgaR3PortUpdateDisplay(PPDMIDISPLAYPORT pInterface)
4736	{
4737	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4738	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4739	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4740
4741	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4742	AssertRC(rc);
4743
4744	# ifdef VBOX_WITH_VMSVGA
4745	if ( pThis->svga.fEnabled
4746	&& !pThis->svga.fTraces)
4747	{
4748	/* Nothing to do as the guest will explicitely update us about frame buffer changes. */
4749	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4750	return VINF_SUCCESS;
4751	}
4752	#endif
4753
4754	# ifndef VBOX_WITH_HGSMI
4755	/* This should be called only in non VBVA mode. */
4756	# else
4757	if (VBVAUpdateDisplay(pThis, pThisCC) == VINF_SUCCESS)
4758	{
4759	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4760	return VINF_SUCCESS;
4761	}
4762	# endif /* VBOX_WITH_HGSMI */
4763
4764	STAM_COUNTER_INC(&pThis->StatUpdateDisp);
4765	if (pThis->fHasDirtyBits && pThis->GCPhysVRAM && pThis->GCPhysVRAM != NIL_RTGCPHYS)
4766	{
4767	PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
4768	pThis->fHasDirtyBits = false;
4769	}
4770	if (pThis->fRemappedVGA)
4771	{
4772	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
4773	pThis->fRemappedVGA = false;
4774	}
4775
4776	rc = vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, false /fUpdateAll/, false /fFailOnResize/, true /reset_dirty/,
4777	pThisCC->pDrv, &pThis->graphic_mode);
4778	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4779	return rc;
4780	}
4781
4782
4783	/**
4784	* Internal vgaR3PortUpdateDisplayAll worker called under pThis->CritSect.
4785	*/
4786	/** @todo Why the 'vboxR3' prefix? */
4787	static int vboxR3UpdateDisplayAllInternal(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, bool fFailOnResize)
4788	{
4789	# ifdef VBOX_WITH_VMSVGA
4790	if ( !pThis->svga.fEnabled
4791	\|\| pThis->svga.fTraces)
4792	# endif
4793	{
4794	/* The dirty bits array has been just cleared, reset handlers as well. */
4795	if (pThis->GCPhysVRAM && pThis->GCPhysVRAM != NIL_RTGCPHYS)
4796	PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
4797	}
4798	if (pThis->fRemappedVGA)
4799	{
4800	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
4801	pThis->fRemappedVGA = false;
4802	}
4803
4804	pThis->graphic_mode = -1; /* force full update */
4805
4806	return vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, true /fUpdateAll/, fFailOnResize,
4807	true /reset_dirty/, pThisCC->pDrv, &pThis->graphic_mode);
4808	}
4809
4810
4811	/**
4812	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplayAll}
4813	*/
4814	static DECLCALLBACK(int) vgaR3PortUpdateDisplayAll(PPDMIDISPLAYPORT pInterface, bool fFailOnResize)
4815	{
4816	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4817	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4818	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4819
4820	/* This is called both in VBVA mode and normal modes. */
4821
4822	# ifdef DEBUG_sunlover
4823	LogFlow(("vgaR3PortUpdateDisplayAll\n"));
4824	# endif /* DEBUG_sunlover */
4825
4826	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4827	AssertRC(rc);
4828
4829	rc = vboxR3UpdateDisplayAllInternal(pDevIns, pThis, pThisCC, fFailOnResize);
4830
4831	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4832	return rc;
4833	}
4834
4835
4836	/**
4837	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetRefreshRate}
4838	*/
4839	static DECLCALLBACK(int) vgaR3PortSetRefreshRate(PPDMIDISPLAYPORT pInterface, uint32_t cMilliesInterval)
4840	{
4841	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4842	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4843	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4844
4845	/*
4846	* Update the interval, notify the VMSVGA FIFO thread if sleeping,
4847	* then restart or stop the timer.
4848	*/
4849	ASMAtomicWriteU32(&pThis->cMilliesRefreshInterval, cMilliesInterval);
4850
4851	# ifdef VBOX_WITH_VMSVGA
4852	if (pThis->svga.fFIFOThreadSleeping)
4853	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->svga.hFIFORequestSem);
4854	# endif
4855
4856	if (cMilliesInterval)
4857	return PDMDevHlpTimerSetMillies(pDevIns, pThis->hRefreshTimer, cMilliesInterval);
4858	return PDMDevHlpTimerStop(pDevIns, pThis->hRefreshTimer);
4859	}
4860
4861
4862	/**
4863	* @interface_method_impl{PDMIDISPLAYPORT,pfnQueryVideoMode}
4864	*/
4865	static DECLCALLBACK(int) vgaR3PortQueryVideoMode(PPDMIDISPLAYPORT pInterface, uint32_t pcBits, uint32_t pcx, uint32_t *pcy)
4866	{
4867	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4868	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4869	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4870
4871	AssertReturn(pcBits, VERR_INVALID_PARAMETER);
4872
4873	*pcBits = vgaR3GetBpp(pThis);
4874	if (pcx)
4875	*pcx = pThis->last_scr_width;
4876	if (pcy)
4877	*pcy = pThis->last_scr_height;
4878	return VINF_SUCCESS;
4879	}
4880
4881
4882	/**
4883	* @interface_method_impl{PDMIDISPLAYPORT,pfnTakeScreenshot}
4884	*/
4885	static DECLCALLBACK(int) vgaR3PortTakeScreenshot(PPDMIDISPLAYPORT pInterface, uint8_t *ppbData, size_t pcbData,
4886	uint32_t pcx, uint32_t pcy)
4887	{
4888	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
4889	PPDMDEVINS pDevIns = pThisCC->pDevIns;
4890	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
4891	PDMDEV_ASSERT_EMT(pDevIns);
4892
4893	LogFlow(("vgaR3PortTakeScreenshot: ppbData=%p pcbData=%p pcx=%p pcy=%p\n", ppbData, pcbData, pcx, pcy));
4894
4895	/*
4896	* Validate input.
4897	*/
4898	if (!RT_VALID_PTR(ppbData) \|\| !RT_VALID_PTR(pcbData) \|\| !RT_VALID_PTR(pcx) \|\| !RT_VALID_PTR(pcy))
4899	return VERR_INVALID_PARAMETER;
4900
4901	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
4902	AssertRCReturn(rc, rc);
4903
4904	/*
4905	* Get screenshot. This function will fail if a resize is required.
4906	* So there is not need to do a 'vboxR3UpdateDisplayAllInternal' before taking screenshot.
4907	*/
4908
4909	/*
4910	* Allocate the buffer for 32 bits per pixel bitmap
4911	*
4912	* Note! The size can't be zero or greater than the size of the VRAM.
4913	* Inconsistent VGA device state can cause the incorrect size values.
4914	*/
4915	size_t cbRequired = pThis->last_scr_width * 4 * pThis->last_scr_height;
4916	if (cbRequired && cbRequired <= pThis->vram_size)
4917	{
4918	uint8_t pbData = (uint8_t )RTMemAlloc(cbRequired);
4919	if (pbData != NULL)
4920	{
4921	/*
4922	* Only 3 methods, assigned below, will be called during the screenshot update.
4923	* All other are already set to NULL.
4924	*/
4925	/* The display connector interface is temporarily replaced with the fake one. */
4926	PDMIDISPLAYCONNECTOR Connector;
4927	RT_ZERO(Connector);
4928	Connector.pbData = pbData;
4929	Connector.cBits = 32;
4930	Connector.cx = pThis->last_scr_width;
4931	Connector.cy = pThis->last_scr_height;
4932	Connector.cbScanline = Connector.cx * 4;
4933	Connector.pfnRefresh = vgaR3DummyRefresh;
4934	Connector.pfnResize = vgaR3DummyResize;
4935	Connector.pfnUpdateRect = vgaR3DummyUpdateRect;
4936
4937	int32_t cur_graphic_mode = -1;
4938
4939	bool fSavedRenderVRAM = pThis->fRenderVRAM;
4940	pThis->fRenderVRAM = true;
4941
4942	/*
4943	* Take the screenshot.
4944	*
4945	* The second parameter is 'false' because the current display state is being rendered to an
4946	* external buffer using a fake connector. That is if display is blanked, we expect a black
4947	* screen in the external buffer.
4948	* If there is a pending resize, the function will fail.
4949	*/
4950	rc = vgaR3UpdateDisplay(pDevIns, pThis, pThisCC, false /fUpdateAll/, true /fFailOnResize/,
4951	false /reset_dirty/, &Connector, &cur_graphic_mode);
4952
4953	pThis->fRenderVRAM = fSavedRenderVRAM;
4954
4955	if (rc == VINF_SUCCESS)
4956	{
4957	/*
4958	* Return the result.
4959	*/
4960	*ppbData = pbData;
4961	*pcbData = cbRequired;
4962	*pcx = Connector.cx;
4963	*pcy = Connector.cy;
4964	}
4965	else
4966	{
4967	/* If we do not return a success, then the data buffer must be freed. */
4968	RTMemFree(pbData);
4969	if (RT_SUCCESS_NP(rc))
4970	{
4971	AssertMsgFailed(("%Rrc\n", rc));
4972	rc = VERR_INTERNAL_ERROR_5;
4973	}
4974	}
4975	}
4976	else
4977	rc = VERR_NO_MEMORY;
4978	}
4979	else
4980	rc = VERR_NOT_SUPPORTED;
4981
4982	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4983
4984	LogFlow(("vgaR3PortTakeScreenshot: returns %Rrc (cbData=%d cx=%d cy=%d)\n", rc, pcbData, pcx, *pcy));
4985	return rc;
4986	}
4987
4988
4989	/**
4990	* @interface_method_impl{PDMIDISPLAYPORT,pfnFreeScreenshot}
4991	*/
4992	static DECLCALLBACK(void) vgaR3PortFreeScreenshot(PPDMIDISPLAYPORT pInterface, uint8_t *pbData)
4993	{
4994	NOREF(pInterface);
4995
4996	LogFlow(("vgaR3PortFreeScreenshot: pbData=%p\n", pbData));
4997
4998	RTMemFree(pbData);
4999	}
5000
5001
5002	/**
5003	* @interface_method_impl{PDMIDISPLAYPORT,pfnDisplayBlt}
5004	*/
5005	static DECLCALLBACK(int) vgaR3PortDisplayBlt(PPDMIDISPLAYPORT pInterface, const void *pvData,
5006	uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
5007	{
5008	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5009	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5010	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5011	PDMDEV_ASSERT_EMT(pDevIns);
5012	LogFlow(("vgaR3PortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy));
5013
5014	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5015	AssertRC(rc);
5016
5017	/*
5018	* Validate input.
5019	*/
5020	if ( pvData
5021	&& x < pThisCC->pDrv->cx
5022	&& cx <= pThisCC->pDrv->cx
5023	&& cx + x <= pThisCC->pDrv->cx
5024	&& y < pThisCC->pDrv->cy
5025	&& cy <= pThisCC->pDrv->cy
5026	&& cy + y <= pThisCC->pDrv->cy)
5027	{
5028	/*
5029	* Determine bytes per pixel in the destination buffer.
5030	*/
5031	size_t cbPixelDst = 0;
5032	switch (pThisCC->pDrv->cBits)
5033	{
5034	case 8:
5035	cbPixelDst = 1;
5036	break;
5037	case 15:
5038	case 16:
5039	cbPixelDst = 2;
5040	break;
5041	case 24:
5042	cbPixelDst = 3;
5043	break;
5044	case 32:
5045	cbPixelDst = 4;
5046	break;
5047	default:
5048	rc = VERR_INVALID_PARAMETER;
5049	break;
5050	}
5051	if (RT_SUCCESS(rc))
5052	{
5053	/*
5054	* The blitting loop.
5055	*/
5056	size_t cbLineSrc = cx * 4; /* 32 bits per pixel. */
5057	uint8_t pbSrc = (uint8_t )pvData;
5058	size_t cbLineDst = pThisCC->pDrv->cbScanline;
5059	uint8_t pbDst = pThisCC->pDrv->pbData + y cbLineDst + x * cbPixelDst;
5060	uint32_t cyLeft = cy;
5061	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[VGA_DRAW_LINE32 4 + vgaR3GetDepthIndex(pThisCC->pDrv->cBits)];
5062	Assert(pfnVgaDrawLine);
5063	while (cyLeft-- > 0)
5064	{
5065	pfnVgaDrawLine(pThis, pThisCC, pbDst, pbSrc, cx);
5066	pbDst += cbLineDst;
5067	pbSrc += cbLineSrc;
5068	}
5069
5070	/*
5071	* Invalidate the area.
5072	*/
5073	pThisCC->pDrv->pfnUpdateRect(pThisCC->pDrv, x, y, cx, cy);
5074	}
5075	}
5076	else
5077	rc = VERR_INVALID_PARAMETER;
5078
5079	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5080
5081	LogFlow(("vgaR3PortDisplayBlt: returns %Rrc\n", rc));
5082	return rc;
5083	}
5084
5085
5086	/**
5087	* @interface_method_impl{PDMIDISPLAYPORT,pfnUpdateDisplayRect}
5088	*/
5089	static DECLCALLBACK(void) vgaR3PortUpdateDisplayRect(PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t cx, uint32_t cy)
5090	{
5091	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5092	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5093	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5094	uint32_t v;
5095
5096	uint32_t cbPixelDst;
5097	uint32_t cbLineDst;
5098	uint8_t *pbDst;
5099
5100	uint32_t cbPixelSrc;
5101	uint32_t cbLineSrc;
5102	uint8_t *pbSrc;
5103
5104
5105	# ifdef DEBUG_sunlover
5106	LogFlow(("vgaR3PortUpdateDisplayRect: %d,%d %dx%d\n", x, y, cx, cy));
5107	# endif /* DEBUG_sunlover */
5108
5109	Assert(pInterface);
5110
5111	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5112	AssertRC(rc);
5113
5114	/* Check if there is something to do at all. */
5115	if (!pThis->fRenderVRAM)
5116	{
5117	/* The framebuffer uses the guest VRAM directly. */
5118	# ifdef DEBUG_sunlover
5119	LogFlow(("vgaR3PortUpdateDisplayRect: nothing to do fRender is false.\n"));
5120	# endif /* DEBUG_sunlover */
5121	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5122	return;
5123	}
5124
5125	Assert(pThisCC->pDrv);
5126	Assert(pThisCC->pDrv->pbData);
5127
5128	/* Correct negative x and y coordinates. */
5129	if (x < 0)
5130	{
5131	x += cx; /* Compute xRight which is also the new width. */
5132	cx = (x < 0) ? 0 : x;
5133	x = 0;
5134	}
5135
5136	if (y < 0)
5137	{
5138	y += cy; /* Compute yBottom, which is also the new height. */
5139	cy = (y < 0) ? 0 : y;
5140	y = 0;
5141	}
5142
5143	/* Also check if coords are greater than the display resolution. */
5144	if (x + cx > pThisCC->pDrv->cx)
5145	{
5146	// x < 0 is not possible here
5147	cx = pThisCC->pDrv->cx > (uint32_t)x? pThisCC->pDrv->cx - x: 0;
5148	}
5149
5150	if (y + cy > pThisCC->pDrv->cy)
5151	{
5152	// y < 0 is not possible here
5153	cy = pThisCC->pDrv->cy > (uint32_t)y? pThisCC->pDrv->cy - y: 0;
5154	}
5155
5156	# ifdef DEBUG_sunlover
5157	LogFlow(("vgaR3PortUpdateDisplayRect: %d,%d %dx%d (corrected coords)\n", x, y, cx, cy));
5158	# endif
5159
5160	/* Check if there is something to do at all. */
5161	if (cx == 0 \|\| cy == 0)
5162	{
5163	/* Empty rectangle. */
5164	# ifdef DEBUG_sunlover
5165	LogFlow(("vgaR3PortUpdateDisplayRect: nothing to do: %dx%d\n", cx, cy));
5166	#endif
5167	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5168	return;
5169	}
5170
5171	/** @todo This method should be made universal and not only for VBVA.
5172	* VGA_DRAW_LINE* must be selected and src/dst address calculation
5173	* changed.
5174	*/
5175
5176	/* Choose the rendering function. */
5177	switch(pThisCC->get_bpp(pThis))
5178	{
5179	default:
5180	case 0:
5181	/* A LFB mode is already disabled, but the callback is still called
5182	* by Display because VBVA buffer is being flushed.
5183	* Nothing to do, just return.
5184	*/
5185	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5186	return;
5187	case 8:
5188	v = VGA_DRAW_LINE8;
5189	break;
5190	case 15:
5191	v = VGA_DRAW_LINE15;
5192	break;
5193	case 16:
5194	v = VGA_DRAW_LINE16;
5195	break;
5196	case 24:
5197	v = VGA_DRAW_LINE24;
5198	break;
5199	case 32:
5200	v = VGA_DRAW_LINE32;
5201	break;
5202	}
5203
5204	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(pThisCC->pDrv->cBits)];
5205
5206	/* Compute source and destination addresses and pitches. */
5207	cbPixelDst = (pThisCC->pDrv->cBits + 7) / 8;
5208	cbLineDst = pThisCC->pDrv->cbScanline;
5209	pbDst = pThisCC->pDrv->pbData + y * cbLineDst + x * cbPixelDst;
5210
5211	cbPixelSrc = (pThisCC->get_bpp(pThis) + 7) / 8;
5212	uint32_t offSrc, u32Dummy;
5213	pThisCC->get_offsets(pThis, &cbLineSrc, &offSrc, &u32Dummy);
5214
5215	/* Assume that rendering is performed only on visible part of VRAM.
5216	* This is true because coordinates were verified.
5217	*/
5218	pbSrc = pThisCC->pbVRam;
5219	pbSrc += offSrc * 4 + y * cbLineSrc + x * cbPixelSrc;
5220
5221	/* Render VRAM to framebuffer. */
5222
5223	# ifdef DEBUG_sunlover
5224	LogFlow(("vgaR3PortUpdateDisplayRect: dst: %p, %d, %d. src: %p, %d, %d\n", pbDst, cbLineDst, cbPixelDst, pbSrc, cbLineSrc, cbPixelSrc));
5225	# endif
5226
5227	while (cy-- > 0)
5228	{
5229	pfnVgaDrawLine(pThis, pThisCC, pbDst, pbSrc, cx);
5230	pbDst += cbLineDst;
5231	pbSrc += cbLineSrc;
5232	}
5233
5234	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5235	# ifdef DEBUG_sunlover
5236	LogFlow(("vgaR3PortUpdateDisplayRect: completed.\n"));
5237	# endif
5238	}
5239
5240
5241	/**
5242	* @interface_method_impl{PDMIDISPLAYPORT,pfnCopyRect}
5243	*/
5244	static DECLCALLBACK(int)
5245	vgaR3PortCopyRect(PPDMIDISPLAYPORT pInterface,
5246	uint32_t cx, uint32_t cy,
5247	const uint8_t *pbSrc, int32_t xSrc, int32_t ySrc, uint32_t cxSrc, uint32_t cySrc,
5248	uint32_t cbSrcLine, uint32_t cSrcBitsPerPixel,
5249	uint8_t *pbDst, int32_t xDst, int32_t yDst, uint32_t cxDst, uint32_t cyDst,
5250	uint32_t cbDstLine, uint32_t cDstBitsPerPixel)
5251	{
5252	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5253	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5254	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5255	uint32_t v;
5256
5257	# ifdef DEBUG_sunlover
5258	LogFlow(("vgaR3PortCopyRect: %d,%d %dx%d -> %d,%d\n", xSrc, ySrc, cx, cy, xDst, yDst));
5259	# endif
5260
5261	Assert(pInterface);
5262	Assert(pThisCC->pDrv);
5263
5264	int32_t xSrcCorrected = xSrc;
5265	int32_t ySrcCorrected = ySrc;
5266	uint32_t cxCorrected = cx;
5267	uint32_t cyCorrected = cy;
5268
5269	/* Correct source coordinates to be within the source bitmap. */
5270	if (xSrcCorrected < 0)
5271	{
5272	xSrcCorrected += cxCorrected; /* Compute xRight which is also the new width. */
5273	cxCorrected = (xSrcCorrected < 0) ? 0 : xSrcCorrected;
5274	xSrcCorrected = 0;
5275	}
5276
5277	if (ySrcCorrected < 0)
5278	{
5279	ySrcCorrected += cyCorrected; /* Compute yBottom, which is also the new height. */
5280	cyCorrected = (ySrcCorrected < 0) ? 0 : ySrcCorrected;
5281	ySrcCorrected = 0;
5282	}
5283
5284	/* Also check if coords are greater than the display resolution. */
5285	if (xSrcCorrected + cxCorrected > cxSrc)
5286	{
5287	/* xSrcCorrected < 0 is not possible here */
5288	cxCorrected = cxSrc > (uint32_t)xSrcCorrected ? cxSrc - xSrcCorrected : 0;
5289	}
5290
5291	if (ySrcCorrected + cyCorrected > cySrc)
5292	{
5293	/* y < 0 is not possible here */
5294	cyCorrected = cySrc > (uint32_t)ySrcCorrected ? cySrc - ySrcCorrected : 0;
5295	}
5296
5297	# ifdef DEBUG_sunlover
5298	LogFlow(("vgaR3PortCopyRect: %d,%d %dx%d (corrected coords)\n", xSrcCorrected, ySrcCorrected, cxCorrected, cyCorrected));
5299	# endif
5300
5301	/* Check if there is something to do at all. */
5302	if (cxCorrected == 0 \|\| cyCorrected == 0)
5303	{
5304	/* Empty rectangle. */
5305	# ifdef DEBUG_sunlover
5306	LogFlow(("vgaPortUpdateDisplayRectEx: nothing to do: %dx%d\n", cxCorrected, cyCorrected));
5307	# endif
5308	return VINF_SUCCESS;
5309	}
5310
5311	/* Check that the corrected source rectangle is within the destination.
5312	* Note: source rectangle is adjusted, but the target must be large enough.
5313	*/
5314	if ( xDst < 0
5315	\|\| yDst < 0
5316	\|\| xDst + cxCorrected > cxDst
5317	\|\| yDst + cyCorrected > cyDst)
5318	{
5319	return VERR_INVALID_PARAMETER;
5320	}
5321
5322	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5323	AssertRC(rc);
5324
5325	/* This method only works if the VGA device is in a VBE mode or not paused VBVA mode.
5326	* VGA modes are reported to the caller by returning VERR_INVALID_STATE.
5327	*
5328	* If VBE_DISPI_ENABLED is set, then it is a VBE or VBE compatible VBVA mode. Both of them can be handled.
5329	*
5330	* If VBE_DISPI_ENABLED is clear, then it is either a VGA mode or a VBVA mode set by guest additions
5331	* which have VBVACAPS_USE_VBVA_ONLY capability.
5332	* When VBE_DISPI_ENABLED is being cleared and VBVACAPS_USE_VBVA_ONLY is not set (i.e. guest wants a VGA mode),
5333	* then VBVAOnVBEChanged makes sure that VBVA is paused.
5334	* That is a not paused VBVA means that the video mode can be handled even if VBE_DISPI_ENABLED is clear.
5335	*/
5336	if ( (pThis->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) == 0
5337	&& VBVAIsPaused(pThisCC)
5338	# ifdef VBOX_WITH_VMSVGA
5339	&& !pThis->svga.fEnabled
5340	# endif
5341	)
5342	{
5343	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5344	return VERR_INVALID_STATE;
5345	}
5346
5347	/* Choose the rendering function. */
5348	switch (cSrcBitsPerPixel)
5349	{
5350	default:
5351	case 0:
5352	/* Nothing to do, just return. */
5353	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5354	return VINF_SUCCESS;
5355	case 8:
5356	v = VGA_DRAW_LINE8;
5357	break;
5358	case 15:
5359	v = VGA_DRAW_LINE15;
5360	break;
5361	case 16:
5362	v = VGA_DRAW_LINE16;
5363	break;
5364	case 24:
5365	v = VGA_DRAW_LINE24;
5366	break;
5367	case 32:
5368	v = VGA_DRAW_LINE32;
5369	break;
5370	}
5371
5372	vga_draw_line_func pfnVgaDrawLine = vga_draw_line_table[v 4 + vgaR3GetDepthIndex(cDstBitsPerPixel)];
5373
5374	/* Compute source and destination addresses and pitches. */
5375	uint32_t cbPixelDst = (cDstBitsPerPixel + 7) / 8;
5376	uint32_t cbLineDst = cbDstLine;
5377	uint8_t pbDstCur = pbDst + yDst cbLineDst + xDst * cbPixelDst;
5378
5379	uint32_t cbPixelSrc = (cSrcBitsPerPixel + 7) / 8;
5380	uint32_t cbLineSrc = cbSrcLine;
5381	const uint8_t pbSrcCur = pbSrc + ySrcCorrected cbLineSrc + xSrcCorrected * cbPixelSrc;
5382
5383	# ifdef DEBUG_sunlover
5384	LogFlow(("vgaR3PortCopyRect: dst: %p, %d, %d. src: %p, %d, %d\n", pbDstCur, cbLineDst, cbPixelDst, pbSrcCur, cbLineSrc, cbPixelSrc));
5385	# endif
5386
5387	while (cyCorrected-- > 0)
5388	{
5389	pfnVgaDrawLine(pThis, pThisCC, pbDstCur, pbSrcCur, cxCorrected);
5390	pbDstCur += cbLineDst;
5391	pbSrcCur += cbLineSrc;
5392	}
5393
5394	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5395	# ifdef DEBUG_sunlover
5396	LogFlow(("vgaR3PortCopyRect: completed.\n"));
5397	# endif
5398	return VINF_SUCCESS;
5399	}
5400
5401
5402	/**
5403	* @interface_method_impl{PDMIDISPLAYPORT,pfnSetRenderVRAM}
5404	*/
5405	static DECLCALLBACK(void) vgaR3PortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender)
5406	{
5407	PVGASTATECC pThisCC = RT_FROM_MEMBER(pInterface, VGASTATECC, IPort);
5408	PPDMDEVINS pDevIns = pThisCC->pDevIns;
5409	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5410
5411	LogFlow(("vgaR3PortSetRenderVRAM: fRender = %d\n", fRender));
5412
5413	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_SEM_BUSY);
5414	AssertRC(rc);
5415
5416	pThis->fRenderVRAM = fRender;
5417
5418	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
5419	}
5420
5421
5422	/**
5423	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportHostCursorCapabilities}
5424	*/
5425	static DECLCALLBACK(void) vgaR3PortReportHostCursorCapabilities(PPDMIDISPLAYPORT pInterface, bool fSupportsRenderCursor,
5426	bool fSupportsMoveCursor)
5427	{
5428	RT_NOREF(pInterface, fSupportsRenderCursor, fSupportsMoveCursor);
5429	}
5430
5431
5432	/**
5433	* @interface_method_impl{PDMIDISPLAYPORT,pfnReportHostCursorPosition}
5434	*/
5435	static DECLCALLBACK(void) vgaR3PortReportHostCursorPosition(PPDMIDISPLAYPORT pInterface, uint32_t x, uint32_t y, bool fOutOfRange)
5436	{
5437	RT_NOREF(pInterface, x, y, fOutOfRange);
5438	}
5439
5440
5441	/**
5442	* @callback_method_impl{FNTMTIMERDEV, VGA Refresh Timer}
5443	*/
5444	static DECLCALLBACK(void) vgaR3TimerRefresh(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
5445	{
5446	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5447	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5448	RT_NOREF(pvUser);
5449
5450	if (pThis->fScanLineCfg & VBVASCANLINECFG_ENABLE_VSYNC_IRQ)
5451	VBVARaiseIrq(pDevIns, pThis, pThisCC, HGSMIHOSTFLAGS_VSYNC);
5452
5453	if (pThisCC->pDrv)
5454	pThisCC->pDrv->pfnRefresh(pThisCC->pDrv);
5455
5456	if (pThis->cMilliesRefreshInterval)
5457	PDMDevHlpTimerSetMillies(pDevIns, hTimer, pThis->cMilliesRefreshInterval);
5458
5459	# ifdef VBOX_WITH_VIDEOHWACCEL
5460	vbvaTimerCb(pDevIns, pThis, pThisCC);
5461	# endif
5462
5463	# ifdef VBOX_WITH_VMSVGA
5464	/*
5465	* Call the VMSVGA FIFO poller/watchdog so we can wake up the thread if
5466	* there is work to be done.
5467	*/
5468	if (pThis->svga.fFIFOThreadSleeping && pThis->svga.fEnabled && pThis->svga.fConfigured)
5469	vmsvgaR3FifoWatchdogTimer(pDevIns, pThis, pThisCC);
5470	# endif
5471	}
5472
5473	# ifdef VBOX_WITH_VMSVGA
5474
5475	/**
5476	* Helper for VMSVGA.
5477	*/
5478	int vgaR3RegisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis, uint64_t cbFrameBuffer)
5479	{
5480	Assert(pThis->GCPhysVRAM);
5481	int rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
5482	pThis->GCPhysVRAM, pThis->GCPhysVRAM + (cbFrameBuffer - 1),
5483	pThis->hLfbAccessHandlerType, pDevIns, pDevIns->pDevInsR0RemoveMe,
5484	pDevIns->pDevInsForRC, "VGA LFB");
5485
5486	AssertRC(rc);
5487	return rc;
5488	}
5489
5490
5491	/**
5492	* Helper for VMSVGA.
5493	*/
5494	int vgaR3UnregisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis)
5495	{
5496	Assert(pThis->GCPhysVRAM);
5497	int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
5498	AssertRC(rc);
5499	return rc;
5500	}
5501
5502	# endif /* VBOX_WITH_VMSVGA */
5503
5504
5505	/* -=-=-=-=-=- Ring 3: PCI Device -=-=-=-=-=- */
5506
5507	/**
5508	* @callback_method_impl{FNPCIIOREGIONMAP, Mapping/unmapping the VRAM MMI2 region}
5509	*/
5510	static DECLCALLBACK(int) vgaR3PciIORegionVRamMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5511	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5512	{
5513	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5514	Log(("vgaR3PciIORegionVRamMapUnmap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
5515	RT_NOREF(pPciDev, cb);
5516
5517	# ifdef VBOX_WITH_VMSVGA
5518	AssertReturn( iRegion == pThis->pciRegions.iVRAM
5519	&& ( enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH
5520	\|\| (enmType == PCI_ADDRESS_SPACE_MEM && pThis->fVMSVGAEnabled && pThis->fStateLoaded)), VERR_INTERNAL_ERROR);
5521	# else
5522	AssertReturn( iRegion == pThis->pciRegions.iVRAM
5523	&& enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
5524	# endif
5525
5526	Assert(pPciDev == pDevIns->apPciDevs[0]);
5527
5528	/* Note! We cannot take the device lock here as that would create a lock order
5529	problem as the caller has taken the PDM lock prior to calling us. If
5530	we did, we will get trouble later when raising interrupts while owning
5531	the device lock (e.g. vmsvgaR3FifoLoop). */
5532
5533	int rc;
5534	if (GCPhysAddress != NIL_RTGCPHYS)
5535	{
5536	/*
5537	* Mapping the VRAM.
5538	*/
5539	rc = PDMDevHlpMmio2Map(pDevIns, pThis->hMmio2VRam, GCPhysAddress);
5540	AssertLogRelRC(rc);
5541	if (RT_SUCCESS(rc))
5542	{
5543	# ifdef VBOX_WITH_VMSVGA
5544	if ( !pThis->svga.fEnabled
5545	\|\| ( pThis->svga.fEnabled
5546	&& pThis->svga.fVRAMTracking
5547	)
5548	)
5549	# endif
5550	{
5551	rc = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns), GCPhysAddress, GCPhysAddress + (pThis->vram_size - 1),
5552	pThis->hLfbAccessHandlerType, pDevIns, pDevIns->pDevInsR0RemoveMe,
5553	pDevIns->pDevInsForRC, "VGA LFB");
5554	AssertLogRelRC(rc);
5555	}
5556
5557	pThis->GCPhysVRAM = GCPhysAddress;
5558	pThis->vbe_regs[VBE_DISPI_INDEX_FB_BASE_HI] = GCPhysAddress >> 16;
5559
5560	rc = VINF_PCI_MAPPING_DONE; /* caller doesn't care about any other status, so no problem overwriting error here */
5561	}
5562	}
5563	else
5564	{
5565	/*
5566	* Unmapping of the VRAM in progress (caller will do that).
5567	* Deregister the access handler so PGM doesn't get upset.
5568	*/
5569	Assert(pThis->GCPhysVRAM);
5570	# ifdef VBOX_WITH_VMSVGA
5571	if ( !pThis->svga.fEnabled
5572	\|\| ( pThis->svga.fEnabled
5573	&& pThis->svga.fVRAMTracking
5574	)
5575	)
5576	# endif
5577	{
5578	rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
5579	AssertRC(rc);
5580	}
5581	# ifdef VBOX_WITH_VMSVGA
5582	else
5583	rc = VINF_SUCCESS;
5584	# endif
5585	pThis->GCPhysVRAM = 0;
5586	/* NB: VBE_DISPI_INDEX_FB_BASE_HI is left unchanged here. */
5587	}
5588	return rc;
5589	}
5590
5591
5592	# ifdef VBOX_WITH_VMSVGA /* Currently not needed in the non-VMSVGA mode, but keeping it flexible for later. */
5593	/**
5594	* @interface_method_impl{PDMPCIDEV,pfnRegionLoadChangeHookR3}
5595	*/
5596	static DECLCALLBACK(int) vgaR3PciRegionLoadChangeHook(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5597	uint64_t cbRegion, PCIADDRESSSPACE enmType,
5598	PFNPCIIOREGIONOLDSETTER pfnOldSetter, PFNPCIIOREGIONSWAP pfnSwapRegions)
5599	{
5600	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5601
5602	# ifdef VBOX_WITH_VMSVGA
5603	if (pThis->fVMSVGAEnabled)
5604	{
5605	/*
5606	* We messed up BAR order for the hybrid devices in 6.0 (see #9359).
5607	* It should have been compatible with the VBox VGA device and had the
5608	* VRAM region first and I/O second, but instead the I/O region ended
5609	* up first and VRAM second like the VMSVGA device.
5610	*
5611	* So, we have to detect that here and reconfigure the memory regions.
5612	* Region numbers are used in our (and the PCI bus') interfaction with
5613	* PGM, so PGM needs to be informed too.
5614	*/
5615	if ( iRegion == 0
5616	&& iRegion == pThis->pciRegions.iVRAM
5617	&& (enmType & PCI_ADDRESS_SPACE_IO))
5618	{
5619	LogRel(("VGA: Detected old BAR config, making adjustments.\n"));
5620
5621	/* Update the entries. */
5622	pThis->pciRegions.iIO = 0;
5623	pThis->pciRegions.iVRAM = 1;
5624
5625	/* Update PGM on the region number change so it won't barf when restoring state. */
5626	AssertLogRelReturn(pDevIns->CTX_SUFF(pHlp)->pfnMmio2ChangeRegionNo, VERR_VERSION_MISMATCH);
5627	int rc = pDevIns->CTX_SUFF(pHlp)->pfnMmio2ChangeRegionNo(pDevIns, pThis->hMmio2VRam, 1);
5628	AssertLogRelRCReturn(rc, rc);
5629	/** @todo Update the I/O port too, only currently we don't give a hoot about
5630	* the region number in the I/O port registrations so it can wait...
5631	* (Only visible in the 'info ioport' output IIRC). */
5632
5633	/* Update the calling PCI device. */
5634	AssertLogRelReturn(pfnSwapRegions, VERR_INTERNAL_ERROR_2);
5635	rc = pfnSwapRegions(pPciDev, 0, 1);
5636	AssertLogRelRCReturn(rc, rc);
5637
5638	return rc;
5639	}
5640
5641	/*
5642	* The VMSVGA changed the default FIFO size from 128KB to 2MB after 5.1.
5643	*/
5644	if (iRegion == pThis->pciRegions.iFIFO)
5645	{
5646	/* Make sure it's still 32-bit memory. Ignore fluxtuations in the prefetch flag. */
5647	AssertLogRelMsgReturn(!(enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64)), ("enmType=%#x\n", enmType),
5648	VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE);
5649
5650	/* If the size didn't change we're fine, so just return already. */
5651	if (cbRegion == pThis->svga.cbFIFO)
5652	return VINF_SUCCESS;
5653
5654	/* If the size is larger than the current configuration, refuse to load. */
5655	AssertLogRelMsgReturn(cbRegion <= pThis->svga.cbFIFOConfig,
5656	("cbRegion=%#RGp cbFIFOConfig=%#x cbFIFO=%#x\n",
5657	cbRegion, pThis->svga.cbFIFOConfig, pThis->svga.cbFIFO),
5658	VERR_SSM_LOAD_CONFIG_MISMATCH);
5659
5660	/* Adjust the size down. */
5661	int rc = PDMDevHlpMmio2Reduce(pDevIns, pThis->hMmio2VmSvgaFifo, cbRegion);
5662	AssertLogRelMsgRCReturn(rc,
5663	("cbRegion=%#RGp cbFIFOConfig=%#x cbFIFO=%#x: %Rrc\n",
5664	cbRegion, pThis->svga.cbFIFOConfig, pThis->svga.cbFIFO, rc),
5665	rc);
5666	pThis->svga.cbFIFO = cbRegion;
5667	return rc;
5668
5669	}
5670
5671	/*
5672	* VRAM used to be non-prefetchable till 6.1.0, so we end up here when restoring
5673	* states older than that with 6.1.0 and later. We just have to check that
5674	* the size and basic type matches, then return VINF_SUCCESS to ACK it.
5675	*/
5676	if (iRegion == pThis->pciRegions.iVRAM)
5677	{
5678	/* Make sure it's still 32-bit memory. Ignore fluxtuations in the prefetch flag. */
5679	AssertLogRelMsgReturn(!(enmType & (PCI_ADDRESS_SPACE_IO \| PCI_ADDRESS_SPACE_BAR64)), ("enmType=%#x\n", enmType),
5680	VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE);
5681	/* The size must be the same. */
5682	AssertLogRelMsgReturn(cbRegion == pThis->vram_size,
5683	("cbRegion=%#RGp vram_size=%#x\n", cbRegion, pThis->vram_size),
5684	VERR_SSM_LOAD_CONFIG_MISMATCH);
5685	return VINF_SUCCESS;
5686	}
5687
5688	/* Emulate callbacks for 5.1 and older saved states by recursion. */
5689	if (iRegion == UINT32_MAX)
5690	{
5691	int rc = vgaR3PciRegionLoadChangeHook(pDevIns, pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD,
5692	PCI_ADDRESS_SPACE_MEM, NULL, NULL);
5693	if (RT_SUCCESS(rc))
5694	rc = pfnOldSetter(pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM);
5695	return rc;
5696	}
5697	}
5698	# endif /* VBOX_WITH_VMSVGA */
5699
5700	return VERR_VGA_UNEXPECTED_PCI_REGION_LOAD_CHANGE;
5701	}
5702	# endif /* VBOX_WITH_VMSVGA */
5703
5704
5705	/* -=-=-=-=-=- Ring3: Misc Wrappers & Sidekicks -=-=-=-=-=- */
5706
5707	/**
5708	* Saves a important bits of the VGA device config.
5709	*
5710	* @param pHlp The device helpers (for SSM functions).
5711	* @param pThis The shared VGA instance data.
5712	* @param pSSM The saved state handle.
5713	*/
5714	static void vgaR3SaveConfig(PCPDMDEVHLPR3 pHlp, PVGASTATE pThis, PSSMHANDLE pSSM)
5715	{
5716	pHlp->pfnSSMPutU32(pSSM, pThis->vram_size);
5717	pHlp->pfnSSMPutU32(pSSM, pThis->cMonitors);
5718	}
5719
5720
5721	/**
5722	* @callback_method_impl{FNSSMDEVLIVEEXEC}
5723	*/
5724	static DECLCALLBACK(int) vgaR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5725	{
5726	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5727	Assert(uPass == 0); NOREF(uPass);
5728	vgaR3SaveConfig(pDevIns->pHlpR3, pThis, pSSM);
5729	return VINF_SSM_DONT_CALL_AGAIN;
5730	}
5731
5732
5733	/**
5734	* @callback_method_impl{FNSSMDEVSAVEPREP}
5735	*/
5736	static DECLCALLBACK(int) vgaR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5737	{
5738	# ifdef VBOX_WITH_VIDEOHWACCEL
5739	RT_NOREF(pSSM);
5740	return vboxVBVASaveStatePrep(pDevIns);
5741	# else
5742	RT_NOREF(pDevIns, pSSM);
5743	return VINF_SUCCESS;
5744	# endif
5745	}
5746
5747
5748	/**
5749	* @callback_method_impl{FNSSMDEVSAVEDONE}
5750	*/
5751	static DECLCALLBACK(int) vgaR3SaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5752	{
5753	# ifdef VBOX_WITH_VIDEOHWACCEL
5754	RT_NOREF(pSSM);
5755	return vboxVBVASaveStateDone(pDevIns);
5756	# else
5757	RT_NOREF(pDevIns, pSSM);
5758	return VINF_SUCCESS;
5759	# endif
5760	}
5761
5762
5763	/**
5764	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5765	*/
5766	static DECLCALLBACK(int) vgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5767	{
5768	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5769	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5770	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5771
5772	# ifdef VBOX_WITH_VDMA
5773	vboxVDMASaveStateExecPrep(pThisCC->pVdma);
5774	# endif
5775
5776	vgaR3SaveConfig(pHlp, pThis, pSSM);
5777	vga_save(pHlp, pSSM, PDMDEVINS_2_DATA(pDevIns, PVGASTATE));
5778
5779	VGA_SAVED_STATE_PUT_MARKER(pSSM, 1);
5780	# ifdef VBOX_WITH_HGSMI
5781	pHlp->pfnSSMPutBool(pSSM, true);
5782	int rc = vboxVBVASaveStateExec(pDevIns, pSSM);
5783	# else
5784	int rc = pHlp->pfnSSMPutBool(pSSM, false);
5785	# endif
5786
5787	AssertRCReturn(rc, rc);
5788
5789	VGA_SAVED_STATE_PUT_MARKER(pSSM, 3);
5790	# ifdef VBOX_WITH_VDMA
5791	rc = pHlp->pfnSSMPutU32(pSSM, 1);
5792	AssertRCReturn(rc, rc);
5793	rc = vboxVDMASaveStateExecPerform(pHlp, pThisCC->pVdma, pSSM);
5794	# else
5795	rc = pHlp->pfnSSMPutU32(pSSM, 0);
5796	# endif
5797	AssertRCReturn(rc, rc);
5798
5799	# ifdef VBOX_WITH_VDMA
5800	vboxVDMASaveStateExecDone(pThisCC->pVdma);
5801	# endif
5802
5803	VGA_SAVED_STATE_PUT_MARKER(pSSM, 5);
5804	# ifdef VBOX_WITH_VMSVGA
5805	if (pThis->fVMSVGAEnabled)
5806	{
5807	rc = vmsvgaR3SaveExec(pDevIns, pSSM);
5808	AssertRCReturn(rc, rc);
5809	}
5810	# endif
5811	VGA_SAVED_STATE_PUT_MARKER(pSSM, 6);
5812
5813	return rc;
5814	}
5815
5816
5817	/**
5818	* @callback_method_impl{FNSSMDEVLOADPREP}
5819	*/
5820	static DECLCALLBACK(int) vgaR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5821	{
5822	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5823	RT_NOREF(pSSM);
5824	pThis->fStateLoaded = true;
5825	return VINF_SUCCESS;
5826	}
5827
5828
5829	/**
5830	* @callback_method_impl{FNSSMDEVLOADEXEC}
5831	*/
5832	static DECLCALLBACK(int) vgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5833	{
5834	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5835	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5836	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5837	int rc;
5838
5839	pThis->fStateLoaded = true;
5840
5841	if (uVersion < VGA_SAVEDSTATE_VERSION_ANCIENT \|\| uVersion > VGA_SAVEDSTATE_VERSION)
5842	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5843
5844	if (uVersion > VGA_SAVEDSTATE_VERSION_HGSMI)
5845	{
5846	/* Check the config */
5847	uint32_t cbVRam;
5848	rc = pHlp->pfnSSMGetU32(pSSM, &cbVRam);
5849	AssertRCReturn(rc, rc);
5850	if (pThis->vram_size != cbVRam)
5851	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("VRAM size changed: config=%#x state=%#x"), pThis->vram_size, cbVRam);
5852
5853	uint32_t cMonitors;
5854	rc = pHlp->pfnSSMGetU32(pSSM, &cMonitors);
5855	AssertRCReturn(rc, rc);
5856	if (pThis->cMonitors != cMonitors)
5857	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Monitor count changed: config=%u state=%u"), pThis->cMonitors, cMonitors);
5858	}
5859
5860	if (uPass == SSM_PASS_FINAL)
5861	{
5862	rc = vga_load(pHlp, pSSM, pThis, uVersion);
5863	if (RT_FAILURE(rc))
5864	return rc;
5865
5866	/*
5867	* Restore the HGSMI state, if present.
5868	*/
5869	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 1);
5870	bool fWithHgsmi = uVersion == VGA_SAVEDSTATE_VERSION_HGSMI;
5871	if (uVersion > VGA_SAVEDSTATE_VERSION_HGSMI)
5872	{
5873	rc = pHlp->pfnSSMGetBool(pSSM, &fWithHgsmi);
5874	AssertRCReturn(rc, rc);
5875	}
5876	if (fWithHgsmi)
5877	{
5878	# ifdef VBOX_WITH_HGSMI
5879	rc = vboxVBVALoadStateExec(pDevIns, pSSM, uVersion);
5880	AssertRCReturn(rc, rc);
5881	# else
5882	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("HGSMI is not compiled in, but it is present in the saved state"));
5883	# endif
5884	}
5885
5886	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 3);
5887	if (uVersion >= VGA_SAVEDSTATE_VERSION_3D)
5888	{
5889	uint32_t u32;
5890	rc = pHlp->pfnSSMGetU32(pSSM, &u32);
5891	if (u32)
5892	{
5893	# ifdef VBOX_WITH_VDMA
5894	if (u32 == 1)
5895	{
5896	rc = vboxVDMASaveLoadExecPerform(pHlp, pThisCC->pVdma, pSSM, uVersion);
5897	AssertRCReturn(rc, rc);
5898	}
5899	else
5900	# endif
5901	{
5902	LogRel(("invalid CmdVbva version info\n"));
5903	return VERR_VERSION_MISMATCH;
5904	}
5905	}
5906	}
5907
5908	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 5);
5909	# ifdef VBOX_WITH_VMSVGA
5910	if (pThis->fVMSVGAEnabled)
5911	{
5912	rc = vmsvgaR3LoadExec(pDevIns, pSSM, uVersion, uPass);
5913	AssertRCReturn(rc, rc);
5914	}
5915	# endif
5916	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pSSM, uVersion, 6);
5917	}
5918	return VINF_SUCCESS;
5919	}
5920
5921
5922	/**
5923	* @@callback_method_impl{FNSSMDEVLOADDONE}
5924	*/
5925	static DECLCALLBACK(int) vgaR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5926	{
5927	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5928	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5929	int rc;
5930	RT_NOREF(pThisCC, pThis, pSSM);
5931
5932	# ifdef VBOX_WITH_HGSMI
5933	rc = vboxVBVALoadStateDone(pDevIns);
5934	AssertRCReturn(rc, rc);
5935	# ifdef VBOX_WITH_VDMA
5936	rc = vboxVDMASaveLoadDone(pThisCC->pVdma);
5937	AssertRCReturn(rc, rc);
5938	# endif
5939	/* Now update the current VBVA state which depends on VBE registers. vboxVBVALoadStateDone cleared the state. */
5940	VBVAOnVBEChanged(pThis, pThisCC);
5941	# endif
5942	# ifdef VBOX_WITH_VMSVGA
5943	if (pThis->fVMSVGAEnabled)
5944	{
5945	rc = vmsvgaR3LoadDone(pDevIns);
5946	AssertRCReturn(rc, rc);
5947	}
5948	# endif
5949	return VINF_SUCCESS;
5950	}
5951
5952
5953	/* -=-=-=-=-=- Ring 3: Device callbacks -=-=-=-=-=- */
5954
5955	/**
5956	* @interface_method_impl{PDMDEVREG,pfnResume}
5957	*/
5958	static DECLCALLBACK(void) vgaR3Resume(PPDMDEVINS pDevIns)
5959	{
5960	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5961	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5962	VBVAOnResume(pDevIns, pThis, pThisCC);
5963	}
5964
5965
5966	/**
5967	* @interface_method_impl{PDMDEVREG,pfnReset}
5968	*/
5969	static DECLCALLBACK(void) vgaR3Reset(PPDMDEVINS pDevIns)
5970	{
5971	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
5972	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
5973	char *pchStart;
5974	char *pchEnd;
5975	LogFlow(("vgaReset\n"));
5976
5977	if (pThisCC->pVdma)
5978	vboxVDMAReset(pThisCC->pVdma);
5979
5980	# ifdef VBOX_WITH_VMSVGA
5981	if (pThis->fVMSVGAEnabled)
5982	vmsvgaR3Reset(pDevIns);
5983	# endif
5984
5985	# ifdef VBOX_WITH_HGSMI
5986	VBVAReset(pDevIns, pThis, pThisCC);
5987	# endif
5988
5989
5990	/* Clear the VRAM ourselves. */
5991	if (pThisCC->pbVRam && pThis->vram_size)
5992	memset(pThisCC->pbVRam, 0, pThis->vram_size);
5993
5994	/*
5995	* Zero most of it.
5996	*
5997	* Unlike vga_reset we're leaving out a few members which we believe
5998	* must remain unchanged....
5999	*/
6000	/* 1st part. */
6001	pchStart = (char *)&pThis->latch;
6002	pchEnd = (char *)&pThis->invalidated_y_table;
6003	memset(pchStart, 0, pchEnd - pchStart);
6004
6005	/* 2nd part. */
6006	pchStart = (char *)&pThis->last_palette;
6007	pchEnd = (char *)&pThis->u32Marker;
6008	memset(pchStart, 0, pchEnd - pchStart);
6009
6010
6011	/*
6012	* Restore and re-init some bits.
6013	*/
6014	pThisCC->get_bpp = vgaR3GetBpp;
6015	pThisCC->get_offsets = vgaR3GetOffsets;
6016	pThisCC->get_resolution = vgaR3GetResolution;
6017	pThis->graphic_mode = -1; /* Force full update. */
6018	# ifdef CONFIG_BOCHS_VBE
6019	pThis->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
6020	pThis->vbe_regs[VBE_DISPI_INDEX_VBOX_VIDEO] = 0;
6021	pThis->vbe_regs[VBE_DISPI_INDEX_FB_BASE_HI] = pThis->GCPhysVRAM >> 16;
6022	pThis->vbe_bank_max = (pThis->vram_size >> 16) - 1;
6023	# endif /* CONFIG_BOCHS_VBE */
6024	pThis->st00 = 0x70; /* Static except for bit 4. */
6025
6026	/*
6027	* Reset the LFB mapping.
6028	*/
6029	pThis->fLFBUpdated = false;
6030	if ( ( pDevIns->fRCEnabled
6031	\|\| pDevIns->fR0Enabled)
6032	&& pThis->GCPhysVRAM
6033	&& pThis->GCPhysVRAM != NIL_RTGCPHYS)
6034	{
6035	int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pThis->GCPhysVRAM);
6036	AssertRC(rc);
6037	}
6038	if (pThis->fRemappedVGA)
6039	{
6040	IOMMmioResetRegion(PDMDevHlpGetVM(pDevIns), pDevIns, pThis->hMmioLegacy);
6041	pThis->fRemappedVGA = false;
6042	}
6043
6044	/*
6045	* Reset the logo data.
6046	*/
6047	pThisCC->LogoCommand = LOGO_CMD_NOP;
6048	pThisCC->offLogoData = 0;
6049
6050	/* notify port handler */
6051	if (pThisCC->pDrv)
6052	{
6053	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect); /* hack around lock order issue. */
6054	pThisCC->pDrv->pfnReset(pThisCC->pDrv);
6055	pThisCC->pDrv->pfnVBVAMousePointerShape(pThisCC->pDrv, false, false, 0, 0, 0, 0, NULL);
6056	PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
6057	}
6058
6059	/* Reset latched access mask. */
6060	pThis->uMaskLatchAccess = 0x3ff;
6061	pThis->cLatchAccesses = 0;
6062	pThis->u64LastLatchedAccess = 0;
6063	pThis->iMask = 0;
6064
6065	/* Reset retrace emulation. */
6066	memset(&pThis->retrace_state, 0, sizeof(pThis->retrace_state));
6067	}
6068
6069
6070	/**
6071	* @interface_method_impl{PDMDEVREG,pfnPowerOn}
6072	*/
6073	static DECLCALLBACK(void) vgaR3PowerOn(PPDMDEVINS pDevIns)
6074	{
6075	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6076	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6077	# ifdef VBOX_WITH_VMSVGA
6078	vmsvgaR3PowerOn(pDevIns);
6079	# endif
6080	VBVAOnResume(pDevIns, pThis, pThisCC);
6081	}
6082
6083
6084	/**
6085	* @interface_method_impl{PDMDEVREG,pfnPowerOff}
6086	*/
6087	static DECLCALLBACK(void) vgaR3PowerOff(PPDMDEVINS pDevIns)
6088	{
6089	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6090	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6091	RT_NOREF(pThis, pThisCC);
6092	# ifdef VBOX_WITH_VMSVGA
6093	vmsvgaR3PowerOff(pDevIns);
6094	# endif
6095	}
6096
6097
6098	/**
6099	* @interface_method_impl{PDMDEVREG,pfnRelocate}
6100	*/
6101	static DECLCALLBACK(void) vgaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
6102	{
6103	# ifdef VBOX_WITH_RAW_MODE_KEEP
6104	if (offDelta)
6105	{
6106	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6107	LogFlow(("vgaRelocate: offDelta = %08X\n", offDelta));
6108
6109	pThisRC->pbVRam += offDelta;
6110	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6111	}
6112	# else
6113	RT_NOREF(pDevIns, offDelta);
6114	# endif
6115	}
6116
6117
6118	/**
6119	* @interface_method_impl{PDMDEVREG,pfnAttach}
6120	*
6121	* This is like plugging in the monitor after turning on the PC.
6122	*/
6123	static DECLCALLBACK(int) vgaAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6124	{
6125	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6126	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6127
6128	RT_NOREF(pThis);
6129
6130	AssertMsgReturn(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG,
6131	("VGA device does not support hotplugging\n"),
6132	VERR_INVALID_PARAMETER);
6133
6134	switch (iLUN)
6135	{
6136	/* LUN #0: Display port. */
6137	case 0:
6138	{
6139	int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pThisCC->IBase, &pThisCC->pDrvBase, "Display Port");
6140	if (RT_SUCCESS(rc))
6141	{
6142	pThisCC->pDrv = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIDISPLAYCONNECTOR);
6143	if (pThisCC->pDrv)
6144	{
6145	/* pThisCC->pDrv->pbData can be NULL when there is no framebuffer. */
6146	if ( pThisCC->pDrv->pfnRefresh
6147	&& pThisCC->pDrv->pfnResize
6148	&& pThisCC->pDrv->pfnUpdateRect)
6149	rc = VINF_SUCCESS;
6150	else
6151	{
6152	Assert(pThisCC->pDrv->pfnRefresh);
6153	Assert(pThisCC->pDrv->pfnResize);
6154	Assert(pThisCC->pDrv->pfnUpdateRect);
6155	pThisCC->pDrv = NULL;
6156	pThisCC->pDrvBase = NULL;
6157	rc = VERR_INTERNAL_ERROR;
6158	}
6159	# ifdef VBOX_WITH_VIDEOHWACCEL
6160	if(rc == VINF_SUCCESS)
6161	{
6162	rc = vbvaVHWAConstruct(pDevIns, pThis, pThisCC);
6163	if (rc != VERR_NOT_IMPLEMENTED)
6164	AssertRC(rc);
6165	}
6166	# endif
6167	}
6168	else
6169	{
6170	AssertMsgFailed(("LUN #0 doesn't have a display connector interface! rc=%Rrc\n", rc));
6171	pThisCC->pDrvBase = NULL;
6172	rc = VERR_PDM_MISSING_INTERFACE;
6173	}
6174	}
6175	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6176	{
6177	Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
6178	rc = VINF_SUCCESS;
6179	}
6180	else
6181	AssertLogRelMsgFailed(("Failed to attach LUN #0! rc=%Rrc\n", rc));
6182	return rc;
6183	}
6184
6185	default:
6186	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
6187	return VERR_PDM_NO_SUCH_LUN;
6188	}
6189	}
6190
6191
6192	/**
6193	* @interface_method_impl{PDMDEVREG,pfnDetach}
6194	*
6195	* This is like unplugging the monitor while the PC is still running.
6196	*/
6197	static DECLCALLBACK(void) vgaDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
6198	{
6199	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6200	AssertMsg(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG, ("VGA device does not support hotplugging\n"));
6201	RT_NOREF(fFlags);
6202
6203	/*
6204	* Reset the interfaces and update the controller state.
6205	*/
6206	switch (iLUN)
6207	{
6208	/* LUN #0: Display port. */
6209	case 0:
6210	pThisCC->pDrv = NULL;
6211	pThisCC->pDrvBase = NULL;
6212	break;
6213
6214	default:
6215	AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
6216	break;
6217	}
6218	}
6219
6220
6221	/**
6222	* @interface_method_impl{PDMDEVREG,pfnDestruct}
6223	*/
6224	static DECLCALLBACK(int) vgaR3Destruct(PPDMDEVINS pDevIns)
6225	{
6226	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6227	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6228	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6229	LogFlow(("vgaR3Destruct:\n"));
6230
6231	# ifdef VBOX_WITH_VDMA
6232	if (pThisCC->pVdma)
6233	vboxVDMADestruct(pThisCC->pVdma);
6234	# endif
6235
6236	# ifdef VBOX_WITH_VMSVGA
6237	if (pThis->fVMSVGAEnabled)
6238	vmsvgaR3Destruct(pDevIns);
6239	# endif
6240
6241	# ifdef VBOX_WITH_HGSMI
6242	VBVADestroy(pThisCC);
6243	# endif
6244
6245	/*
6246	* Free MM heap pointers.
6247	*/
6248	if (pThisCC->pbVBEExtraData)
6249	{
6250	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVBEExtraData);
6251	pThisCC->pbVBEExtraData = NULL;
6252	}
6253	if (pThisCC->pbVgaBios)
6254	{
6255	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVgaBios);
6256	pThisCC->pbVgaBios = NULL;
6257	}
6258
6259	if (pThisCC->pszVgaBiosFile)
6260	{
6261	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6262	pThisCC->pszVgaBiosFile = NULL;
6263	}
6264
6265	if (pThisCC->pszLogoFile)
6266	{
6267	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
6268	pThisCC->pszLogoFile = NULL;
6269	}
6270
6271	if (pThisCC->pbLogo)
6272	{
6273	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbLogo);
6274	pThisCC->pbLogo = NULL;
6275	}
6276
6277	# if defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM)
6278	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSectIRQ);
6279	# endif
6280	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
6281	return VINF_SUCCESS;
6282	}
6283
6284
6285	/**
6286	* Adjust VBE mode information
6287	*
6288	* Depending on the configured VRAM size, certain parts of VBE mode
6289	* information must be updated.
6290	*
6291	* @param pThis The device instance data.
6292	* @param pMode The mode information structure.
6293	*/
6294	static void vgaR3AdjustModeInfo(PVGASTATE pThis, ModeInfoListItem *pMode)
6295	{
6296	/* For 4bpp modes, the planes are "stacked" on top of each other. */
6297	unsigned bpl = pMode->info.BytesPerScanLine * pMode->info.NumberOfPlanes;
6298	/* The "number of image pages" is really the max page index... */
6299	unsigned maxPage = pThis->vram_size / (pMode->info.YResolution * bpl) - 1;
6300	if (maxPage > 255)
6301	maxPage = 255; /* 8-bit value. */
6302	pMode->info.NumberOfImagePages = maxPage;
6303	pMode->info.LinNumberOfPages = maxPage;
6304	}
6305
6306
6307	/**
6308	* @interface_method_impl{PDMDEVREG,pfnConstruct}
6309	*/
6310	static DECLCALLBACK(int) vgaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6311	{
6312	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6313	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
6314	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
6315	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6316	int rc;
6317	unsigned i;
6318	uint32_t cCustomModes;
6319	uint32_t cyReduction;
6320	uint32_t cbPitch;
6321	PVBEHEADER pVBEDataHdr;
6322	ModeInfoListItem *pCurMode;
6323	unsigned cb;
6324
6325	Assert(iInstance == 0);
6326
6327	/*
6328	* Init static data.
6329	*/
6330	static bool s_fExpandDone = false;
6331	if (!s_fExpandDone)
6332	{
6333	s_fExpandDone = true;
6334	vgaR3InitExpand();
6335	}
6336
6337	/*
6338	* Validate configuration.
6339	*/
6340	static const char s_szMscWorkaround[] = "VRamSize"
6341	"\|MonitorCount"
6342	"\|FadeIn"
6343	"\|FadeOut"
6344	"\|LogoTime"
6345	"\|LogoFile"
6346	"\|ShowBootMenu"
6347	"\|BiosRom"
6348	"\|RealRetrace"
6349	"\|CustomVideoModes"
6350	"\|HeightReduction"
6351	"\|CustomVideoMode1"
6352	"\|CustomVideoMode2"
6353	"\|CustomVideoMode3"
6354	"\|CustomVideoMode4"
6355	"\|CustomVideoMode5"
6356	"\|CustomVideoMode6"
6357	"\|CustomVideoMode7"
6358	"\|CustomVideoMode8"
6359	"\|CustomVideoMode9"
6360	"\|CustomVideoMode10"
6361	"\|CustomVideoMode11"
6362	"\|CustomVideoMode12"
6363	"\|CustomVideoMode13"
6364	"\|CustomVideoMode14"
6365	"\|CustomVideoMode15"
6366	"\|CustomVideoMode16"
6367	"\|MaxBiosXRes"
6368	"\|MaxBiosYRes"
6369	# ifdef VBOX_WITH_VMSVGA
6370	"\|VMSVGAEnabled"
6371	"\|VMSVGA10"
6372	"\|VMSVGAPciId"
6373	"\|VMSVGAPciBarLayout"
6374	"\|VMSVGAFifoSize"
6375	# endif
6376	# ifdef VBOX_WITH_VMSVGA3D
6377	"\|VMSVGA3dEnabled"
6378	"\|VMSVGA3dOverlayEnabled"
6379	# endif
6380	"\|SuppressNewYearSplash"
6381	"\|3DEnabled";
6382
6383	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, s_szMscWorkaround, "");
6384
6385	/*
6386	* Init state data.
6387	*/
6388	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "VRamSize", &pThis->vram_size, VGA_VRAM_DEFAULT);
6389	AssertLogRelRCReturn(rc, rc);
6390	if (pThis->vram_size > VGA_VRAM_MAX)
6391	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6392	"VRamSize is too large, %#x, max %#x", pThis->vram_size, VGA_VRAM_MAX);
6393	if (pThis->vram_size < VGA_VRAM_MIN)
6394	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6395	"VRamSize is too small, %#x, max %#x", pThis->vram_size, VGA_VRAM_MIN);
6396	if (pThis->vram_size & (_256K - 1)) /* Make sure there are no partial banks even in planar modes. */
6397	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
6398	"VRamSize is not a multiple of 256K (%#x)", pThis->vram_size);
6399
6400	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "MonitorCount", &pThis->cMonitors, 1);
6401	AssertLogRelRCReturn(rc, rc);
6402
6403	Log(("VGA: VRamSize=%#x fGCenabled=%RTbool fR0Enabled=%RTbool\n", pThis->vram_size, pDevIns->fRCEnabled, pDevIns->fR0Enabled));
6404
6405	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "3DEnabled", &pThis->f3DEnabled, false);
6406	AssertLogRelRCReturn(rc, rc);
6407	Log(("VGA: f3DEnabled=%RTbool\n", pThis->f3DEnabled));
6408
6409	# ifdef VBOX_WITH_VMSVGA
6410	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAEnabled", &pThis->fVMSVGAEnabled, false);
6411	AssertLogRelRCReturn(rc, rc);
6412	Log(("VMSVGA: VMSVGAEnabled = %d\n", pThis->fVMSVGAEnabled));
6413
6414	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA10", &pThis->fVMSVGA10, false);
6415	AssertLogRelRCReturn(rc, rc);
6416	Log(("VMSVGA: VMSVGA10 = %d\n", pThis->fVMSVGA10));
6417
6418	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAPciId", &pThis->fVMSVGAPciId, false);
6419	AssertLogRelRCReturn(rc, rc);
6420	Log(("VMSVGA: VMSVGAPciId = %d\n", pThis->fVMSVGAPciId));
6421
6422	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGAPciBarLayout", &pThis->fVMSVGAPciBarLayout, pThis->fVMSVGAPciId);
6423	AssertLogRelRCReturn(rc, rc);
6424	Log(("VMSVGA: VMSVGAPciBarLayout = %d\n", pThis->fVMSVGAPciBarLayout));
6425
6426	rc = pHlp->pfnCFGMQueryU32Def(pCfg, "VMSVGAFifoSize", &pThis->svga.cbFIFO, VMSVGA_FIFO_SIZE);
6427	AssertLogRelRCReturn(rc, rc);
6428	AssertLogRelMsgReturn(pThis->svga.cbFIFO >= _128K, ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_OUT_OF_RANGE);
6429	AssertLogRelMsgReturn(pThis->svga.cbFIFO <= _16M, ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_OUT_OF_RANGE);
6430	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pThis->svga.cbFIFO), ("cbFIFO=%#x\n", pThis->svga.cbFIFO), VERR_NOT_POWER_OF_TWO);
6431	pThis->svga.cbFIFOConfig = pThis->svga.cbFIFO;
6432	Log(("VMSVGA: VMSVGAFifoSize = %#x (%'u)\n", pThis->svga.cbFIFO, pThis->svga.cbFIFO));
6433	# endif
6434	# ifdef VBOX_WITH_VMSVGA3D
6435	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA3dEnabled", &pThis->svga.f3DEnabled, false);
6436	AssertLogRelRCReturn(rc, rc);
6437	Log(("VMSVGA: VMSVGA3dEnabled = %d\n", pThis->svga.f3DEnabled));
6438
6439	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "VMSVGA3dOverlayEnabled", &pThis->svga.f3DOverlayEnabled, false);
6440	AssertLogRelRCReturn(rc, rc);
6441	Log(("VMSVGA: VMSVGA3dOverlayEnabled = %d\n", pThis->svga.f3DOverlayEnabled));
6442	# endif
6443
6444	# ifdef VBOX_WITH_VMSVGA
6445	if (pThis->fVMSVGAPciBarLayout)
6446	{
6447	pThis->pciRegions.iIO = 0;
6448	pThis->pciRegions.iVRAM = 1;
6449	}
6450	else
6451	{
6452	pThis->pciRegions.iVRAM = 0;
6453	pThis->pciRegions.iIO = 1;
6454	}
6455	pThis->pciRegions.iFIFO = 2;
6456	# else
6457	pThis->pciRegions.iVRAM = 0;
6458	# endif
6459
6460	pThisCC->pDevIns = pDevIns;
6461
6462	vgaR3Reset(pDevIns);
6463
6464	/* The PCI devices configuration. */
6465	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6466	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6467
6468	# ifdef VBOX_WITH_VMSVGA
6469	if (pThis->fVMSVGAEnabled)
6470	{
6471	/* Extend our VGA device with VMWare SVGA functionality. */
6472	if (pThis->fVMSVGAPciId)
6473	{
6474	PDMPciDevSetVendorId(pPciDev, PCI_VENDOR_ID_VMWARE);
6475	PDMPciDevSetDeviceId(pPciDev, PCI_DEVICE_ID_VMWARE_SVGA2);
6476	}
6477	else
6478	{
6479	PDMPciDevSetVendorId(pPciDev, 0x80ee); /* PCI vendor, just a free bogus value */
6480	PDMPciDevSetDeviceId(pPciDev, 0xbeef);
6481	}
6482	PDMPciDevSetSubSystemVendorId(pPciDev, PCI_VENDOR_ID_VMWARE);
6483	PDMPciDevSetSubSystemId(pPciDev, PCI_DEVICE_ID_VMWARE_SVGA2);
6484	}
6485	else
6486	# endif /* VBOX_WITH_VMSVGA */
6487	{
6488	PDMPciDevSetVendorId(pPciDev, 0x80ee); /* PCI vendor, just a free bogus value */
6489	PDMPciDevSetDeviceId(pPciDev, 0xbeef);
6490	}
6491	PDMPciDevSetClassSub(pPciDev, 0x00); /* VGA controller */
6492	PDMPciDevSetClassBase(pPciDev, 0x03);
6493	PDMPciDevSetHeaderType(pPciDev, 0x00);
6494	# if defined(VBOX_WITH_HGSMI) && (defined(VBOX_WITH_VIDEOHWACCEL) \|\| defined(VBOX_WITH_VDMA) \|\| defined(VBOX_WITH_WDDM))
6495	PDMPciDevSetInterruptPin(pPciDev, 1);
6496	# endif
6497
6498	/* the interfaces. */
6499	pThisCC->IBase.pfnQueryInterface = vgaR3PortQueryInterface;
6500
6501	pThisCC->IPort.pfnUpdateDisplay = vgaR3PortUpdateDisplay;
6502	pThisCC->IPort.pfnUpdateDisplayAll = vgaR3PortUpdateDisplayAll;
6503	pThisCC->IPort.pfnQueryVideoMode = vgaR3PortQueryVideoMode;
6504	pThisCC->IPort.pfnSetRefreshRate = vgaR3PortSetRefreshRate;
6505	pThisCC->IPort.pfnTakeScreenshot = vgaR3PortTakeScreenshot;
6506	pThisCC->IPort.pfnFreeScreenshot = vgaR3PortFreeScreenshot;
6507	pThisCC->IPort.pfnDisplayBlt = vgaR3PortDisplayBlt;
6508	pThisCC->IPort.pfnUpdateDisplayRect = vgaR3PortUpdateDisplayRect;
6509	pThisCC->IPort.pfnCopyRect = vgaR3PortCopyRect;
6510	pThisCC->IPort.pfnSetRenderVRAM = vgaR3PortSetRenderVRAM;
6511	pThisCC->IPort.pfnSetViewport = NULL;
6512	pThisCC->IPort.pfnReportMonitorPositions = NULL;
6513	# ifdef VBOX_WITH_VMSVGA
6514	if (pThis->fVMSVGAEnabled)
6515	{
6516	pThisCC->IPort.pfnSetViewport = vmsvgaR3PortSetViewport;
6517	pThisCC->IPort.pfnReportMonitorPositions = vmsvgaR3PortReportMonitorPositions;
6518	}
6519	# endif
6520	pThisCC->IPort.pfnSendModeHint = vbvaR3PortSendModeHint;
6521	pThisCC->IPort.pfnReportHostCursorCapabilities = vgaR3PortReportHostCursorCapabilities;
6522	pThisCC->IPort.pfnReportHostCursorPosition = vgaR3PortReportHostCursorPosition;
6523
6524	# if defined(VBOX_WITH_HGSMI) && defined(VBOX_WITH_VIDEOHWACCEL)
6525	pThisCC->IVBVACallbacks.pfnVHWACommandCompleteAsync = vbvaR3VHWACommandCompleteAsync;
6526	# endif
6527
6528	pThisCC->ILeds.pfnQueryStatusLed = vgaR3PortQueryStatusLed;
6529	pThis->Led3D.u32Magic = PDMLED_MAGIC;
6530
6531	/*
6532	* We use our own critical section to avoid unncessary pointer indirections
6533	* in interface methods (as well as for historical reasons).
6534	*/
6535	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "VGA#%u", iInstance);
6536	AssertRCReturn(rc, rc);
6537	rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
6538	AssertRCReturn(rc, rc);
6539
6540	# ifdef VBOX_WITH_HGSMI
6541	/*
6542	* This critical section is used by vgaR3IOPortHgsmiWrite, VBVARaiseIrq and VBVAOnResume
6543	* for some IRQ related synchronization.
6544	*/
6545	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectIRQ, RT_SRC_POS, "VGA#%u_IRQ", iInstance);
6546	AssertRCReturn(rc, rc);
6547	# endif
6548
6549	/*
6550	* PCI device registration.
6551	*/
6552	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6553	if (RT_FAILURE(rc))
6554	return rc;
6555	/AssertMsg(pThis->Dev.uDevFn == 16 \|\| iInstance != 0, ("pThis->Dev.uDevFn=%d\n", pThis->Dev.uDevFn));/
6556	if (pPciDev->uDevFn != 16 && iInstance == 0)
6557	Log(("!!WARNING!!: pThis->dev.uDevFn=%d (ignore if testcase or not started by Main)\n", pPciDev->uDevFn));
6558
6559	# ifdef VBOX_WITH_VMSVGA
6560	pThis->hIoPortVmSvga = NIL_IOMIOPORTHANDLE;
6561	pThis->hMmio2VmSvgaFifo = NIL_PGMMMIO2HANDLE;
6562	if (pThis->fVMSVGAEnabled)
6563	{
6564	/* Register the io command ports. */
6565	rc = PDMDevHlpPCIIORegionCreateIo(pDevIns, pThis->pciRegions.iIO, 0x10, vmsvgaIOWrite, vmsvgaIORead, NULL /pvUser/,
6566	"VMSVGA", NULL /paExtDescs/, &pThis->hIoPortVmSvga);
6567	AssertRCReturn(rc, rc);
6568
6569	rc = PDMDevHlpPCIIORegionCreateMmio2Ex(pDevIns, pThis->pciRegions.iFIFO, pThis->svga.cbFIFO,
6570	PCI_ADDRESS_SPACE_MEM, 0 /fFlags/, vmsvgaR3PciIORegionFifoMapUnmap,
6571	"VMSVGA-FIFO", (void **)&pThisCC->svga.pau32FIFO, &pThis->hMmio2VmSvgaFifo);
6572	AssertRCReturn(rc, PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6573	N_("Failed to create VMSVGA FIFO (%u bytes)"), pThis->svga.cbFIFO));
6574
6575	pPciDev->pfnRegionLoadChangeHookR3 = vgaR3PciRegionLoadChangeHook;
6576	}
6577	# endif /* VBOX_WITH_VMSVGA */
6578
6579	/*
6580	* Allocate VRAM and create a PCI region for it.
6581	*/
6582	rc = PDMDevHlpPCIIORegionCreateMmio2Ex(pDevIns, pThis->pciRegions.iVRAM, pThis->vram_size,
6583	PCI_ADDRESS_SPACE_MEM_PREFETCH, 0 /fFlags/, vgaR3PciIORegionVRamMapUnmap,
6584	"VRam", (void **)&pThisCC->pbVRam, &pThis->hMmio2VRam);
6585	AssertLogRelRCReturn(rc, PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
6586	N_("Failed to allocate %u bytes of VRAM"), pThis->vram_size));
6587
6588	/*
6589	* Register access handler types for tracking dirty VRAM pages.
6590	*/
6591	rc = PDMDevHlpPGMHandlerPhysicalTypeRegister(pDevIns, PGMPHYSHANDLERKIND_WRITE,
6592	vgaLFBAccessHandler,
6593	"vgaLFBAccessHandler", "vgaLbfAccessPfHandler",
6594	"vgaLFBAccessHandler", "vgaLbfAccessPfHandler",
6595	"VGA LFB", &pThis->hLfbAccessHandlerType);
6596	AssertRCReturn(rc, rc);
6597
6598	/*
6599	* Register I/O ports.
6600	*/
6601	# define REG_PORT(a_uPort, a_cPorts, a_pfnWrite, a_pfnRead, a_szDesc, a_phIoPort) do { \
6602	rc = PDMDevHlpIoPortCreateFlagsAndMap(pDevIns, a_uPort, a_cPorts, IOM_IOPORT_F_ABS, \
6603	a_pfnWrite, a_pfnRead, "VGA - " a_szDesc, NULL /paExtDescs/, a_phIoPort); \
6604	AssertRCReturn(rc, rc); \
6605	} while (0)
6606	REG_PORT(0x3c0, 2, vgaIoPortArWrite, vgaIoPortArRead, "Attribute Controller", &pThis->hIoPortAr);
6607	REG_PORT(0x3c2, 1, vgaIoPortMsrWrite, vgaIoPortSt00Read, "MSR / ST00", &pThis->hIoPortMsrSt00);
6608	REG_PORT(0x3c3, 1, vgaIoPortUnusedWrite, vgaIoPortUnusedRead, "0x3c3", &pThis->hIoPort3c3);
6609	REG_PORT(0x3c4, 2, vgaIoPortSrWrite, vgaIoPortSrRead, "Sequencer", &pThis->hIoPortSr);
6610	REG_PORT(0x3c6, 4, vgaIoPortDacWrite, vgaIoPortDacRead, "DAC", &pThis->hIoPortDac);
6611	REG_PORT(0x3ca, 4, vgaIoPortPosWrite, vgaIoPortPosRead, "Graphics Position", /?/ &pThis->hIoPortPos);
6612	REG_PORT(0x3ce, 2, vgaIoPortGrWrite, vgaIoPortGrRead, "Graphics Controller", &pThis->hIoPortGr);
6613
6614	/* Note! Ralf Brown lists 0x3b0-0x3b1, 0x3b2-0x3b3 and 0x3b6-0x3b7 as "the same as" 0x3b4-0x3b5. */
6615	REG_PORT(0x3b4, 2, vgaIoPortMdaCrtWrite, vgaIoPortMdaCrtRead, "MDA CRT control", &pThis->hIoPortMdaCrt);
6616	REG_PORT(0x3ba, 1, vgaIoPortMdaFcrWrite, vgaIoPortMdaStRead, "MDA feature/status", &pThis->hIoPortMdaFcrSt);
6617	REG_PORT(0x3d4, 2, vgaIoPortCgaCrtWrite, vgaIoPortCgaCrtRead, "CGA CRT control", &pThis->hIoPortCgaCrt);
6618	REG_PORT(0x3da, 1, vgaIoPortCgaFcrWrite, vgaIoPortCgaStRead, "CGA Feature / status", &pThis->hIoPortCgaFcrSt);
6619
6620	# ifdef CONFIG_BOCHS_VBE
6621	REG_PORT(0x1ce, 1, vgaIoPortWriteVbeIndex, vgaIoPortReadVbeIndex, "VBE Index", &pThis->hIoPortVbeIndex);
6622	REG_PORT(0x1cf, 1, vgaIoPortWriteVbeData, vgaIoPortReadVbeData, "VBE Data", &pThis->hIoPortVbeData);
6623	# endif /* CONFIG_BOCHS_VBE */
6624
6625	# ifdef VBOX_WITH_HGSMI
6626	/* Use reserved VGA IO ports for HGSMI. */
6627	REG_PORT(VGA_PORT_HGSMI_HOST, 4, vgaR3IOPortHgsmiWrite, vgaR3IOPortHgmsiRead, "HGSMI host (3b0-3b3)", &pThis->hIoPortHgsmiHost);
6628	REG_PORT(VGA_PORT_HGSMI_GUEST, 4, vgaR3IOPortHgsmiWrite, vgaR3IOPortHgmsiRead, "HGSMI guest (3d0-3d3)", &pThis->hIoPortHgsmiGuest);
6629	# endif /* VBOX_WITH_HGSMI */
6630
6631	# undef REG_PORT
6632
6633	/* vga bios */
6634	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, VBE_PRINTF_PORT, 1 /cPorts/, vgaIoPortWriteBios, vgaIoPortReadBios,
6635	"VGA BIOS debug/panic", NULL /paExtDescs/, &pThis->hIoPortBios);
6636	AssertRCReturn(rc, rc);
6637
6638	/*
6639	* The MDA/CGA/EGA/VGA/whatever fixed MMIO area.
6640	*/
6641	rc = PDMDevHlpMmioCreateExAndMap(pDevIns, 0x000a0000, 0x00020000,
6642	IOMMMIO_FLAGS_READ_PASSTHRU \| IOMMMIO_FLAGS_WRITE_PASSTHRU \| IOMMMIO_FLAGS_ABS,
6643	NULL /pPciDev/, UINT32_MAX /iPciRegion/,
6644	vgaMmioWrite, vgaMmioRead, vgaMmioFill, NULL /pvUser/,
6645	"VGA - VGA Video Buffer", &pThis->hMmioLegacy);
6646	AssertRCReturn(rc, rc);
6647
6648	/*
6649	* Get the VGA BIOS ROM file name.
6650	*/
6651	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "BiosRom", &pThisCC->pszVgaBiosFile);
6652	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
6653	{
6654	pThisCC->pszVgaBiosFile = NULL;
6655	rc = VINF_SUCCESS;
6656	}
6657	else if (RT_FAILURE(rc))
6658	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"BiosRom\" as a string failed"));
6659	else if (!*pThisCC->pszVgaBiosFile)
6660	{
6661	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6662	pThisCC->pszVgaBiosFile = NULL;
6663	}
6664
6665	/*
6666	* Determine the VGA BIOS ROM size, open specified ROM file in the process.
6667	*/
6668	RTFILE FileVgaBios = NIL_RTFILE;
6669	if (pThisCC->pszVgaBiosFile)
6670	{
6671	rc = RTFileOpen(&FileVgaBios, pThisCC->pszVgaBiosFile, RTFILE_O_READ \| RTFILE_O_OPEN \| RTFILE_O_DENY_WRITE);
6672	if (RT_SUCCESS(rc))
6673	{
6674	rc = RTFileQuerySize(FileVgaBios, &pThisCC->cbVgaBios);
6675	if (RT_SUCCESS(rc))
6676	{
6677	if ( RT_ALIGN(pThisCC->cbVgaBios, _4K) != pThisCC->cbVgaBios
6678	\|\| pThisCC->cbVgaBios > _64K
6679	\|\| pThisCC->cbVgaBios < 16 * _1K)
6680	rc = VERR_TOO_MUCH_DATA;
6681	}
6682	}
6683	if (RT_FAILURE(rc))
6684	{
6685	/*
6686	* In case of failure simply fall back to the built-in VGA BIOS ROM.
6687	*/
6688	Log(("vgaConstruct: Failed to open VGA BIOS ROM file '%s', rc=%Rrc!\n", pThisCC->pszVgaBiosFile, rc));
6689	RTFileClose(FileVgaBios);
6690	FileVgaBios = NIL_RTFILE;
6691	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszVgaBiosFile);
6692	pThisCC->pszVgaBiosFile = NULL;
6693	}
6694	}
6695
6696	/*
6697	* Attempt to get the VGA BIOS ROM data from file.
6698	*/
6699	if (pThisCC->pszVgaBiosFile)
6700	{
6701	/*
6702	* Allocate buffer for the VGA BIOS ROM data.
6703	*/
6704	pThisCC->pbVgaBios = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, pThisCC->cbVgaBios);
6705	if (pThisCC->pbVgaBios)
6706	{
6707	rc = RTFileRead(FileVgaBios, pThisCC->pbVgaBios, pThisCC->cbVgaBios, NULL);
6708	if (RT_FAILURE(rc))
6709	{
6710	AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Rrc\n", pThisCC->cbVgaBios, rc));
6711	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pbVgaBios);
6712	pThisCC->pbVgaBios = NULL;
6713	}
6714	rc = VINF_SUCCESS;
6715	}
6716	else
6717	rc = VERR_NO_MEMORY;
6718	}
6719	else
6720	pThisCC->pbVgaBios = NULL;
6721
6722	/* cleanup */
6723	if (FileVgaBios != NIL_RTFILE)
6724	RTFileClose(FileVgaBios);
6725
6726	/* If we were unable to get the data from file for whatever reason, fall
6727	back to the built-in ROM image. */
6728	const uint8_t *pbVgaBiosBinary;
6729	uint64_t cbVgaBiosBinary;
6730	uint32_t fFlags = 0;
6731	if (pThisCC->pbVgaBios == NULL)
6732	{
6733	CPUMMICROARCH enmMicroarch = PDMDevHlpCpuGetGuestMicroarch(pDevIns);
6734	if ( enmMicroarch == kCpumMicroarch_Intel_8086
6735	\|\| enmMicroarch == kCpumMicroarch_Intel_80186
6736	\|\| enmMicroarch == kCpumMicroarch_NEC_V20
6737	\|\| enmMicroarch == kCpumMicroarch_NEC_V30)
6738	{
6739	pbVgaBiosBinary = g_abVgaBiosBinary8086;
6740	cbVgaBiosBinary = g_cbVgaBiosBinary8086;
6741	LogRel(("VGA: Using the 8086 BIOS image!\n"));
6742	}
6743	else if (enmMicroarch == kCpumMicroarch_Intel_80286)
6744	{
6745	pbVgaBiosBinary = g_abVgaBiosBinary286;
6746	cbVgaBiosBinary = g_cbVgaBiosBinary286;
6747	LogRel(("VGA: Using the 286 BIOS image!\n"));
6748	}
6749	else
6750	{
6751	pbVgaBiosBinary = g_abVgaBiosBinary386;
6752	cbVgaBiosBinary = g_cbVgaBiosBinary386;
6753	LogRel(("VGA: Using the 386+ BIOS image.\n"));
6754	}
6755	fFlags = PGMPHYS_ROM_FLAGS_PERMANENT_BINARY;
6756	}
6757	else
6758	{
6759	pbVgaBiosBinary = pThisCC->pbVgaBios;
6760	cbVgaBiosBinary = pThisCC->cbVgaBios;
6761	}
6762
6763	AssertReleaseMsg(cbVgaBiosBinary <= _64K && cbVgaBiosBinary >= 32*_1K, ("cbVgaBiosBinary=%#x\n", cbVgaBiosBinary));
6764	AssertReleaseMsg(RT_ALIGN_Z(cbVgaBiosBinary, PAGE_SIZE) == cbVgaBiosBinary, ("cbVgaBiosBinary=%#x\n", cbVgaBiosBinary));
6765	/* Note! Because of old saved states we'll always register at least 36KB of ROM. */
6766	rc = PDMDevHlpROMRegister(pDevIns, 0x000c0000, RT_MAX(cbVgaBiosBinary, 36*_1K), pbVgaBiosBinary, cbVgaBiosBinary,
6767	fFlags, "VGA BIOS");
6768	AssertRCReturn(rc, rc);
6769
6770	/*
6771	* Saved state.
6772	*/
6773	rc = PDMDevHlpSSMRegisterEx(pDevIns, VGA_SAVEDSTATE_VERSION, sizeof(*pThis), NULL,
6774	NULL, vgaR3LiveExec, NULL,
6775	vgaR3SavePrep, vgaR3SaveExec, vgaR3SaveDone,
6776	vgaR3LoadPrep, vgaR3LoadExec, vgaR3LoadDone);
6777	AssertRCReturn(rc, rc);
6778
6779	/*
6780	* Create the refresh timer.
6781	*/
6782	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_REAL, vgaR3TimerRefresh, NULL,
6783	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_NO_RING0, "VGA Refresh", &pThis->hRefreshTimer);
6784	AssertRCReturn(rc, rc);
6785
6786	/*
6787	* Attach to the display.
6788	*/
6789	rc = vgaAttach(pDevIns, 0 /* display LUN # */, PDM_TACH_FLAGS_NOT_HOT_PLUG);
6790	AssertRCReturn(rc, rc);
6791
6792	/*
6793	* Initialize the retrace flag.
6794	*/
6795	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RealRetrace", &pThis->fRealRetrace, false);
6796	AssertLogRelRCReturn(rc, rc);
6797
6798	uint16_t maxBiosXRes;
6799	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxBiosXRes", &maxBiosXRes, UINT16_MAX);
6800	AssertLogRelRCReturn(rc, rc);
6801	uint16_t maxBiosYRes;
6802	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxBiosYRes", &maxBiosYRes, UINT16_MAX);
6803	AssertLogRelRCReturn(rc, rc);
6804
6805	/*
6806	* Compute buffer size for the VBE BIOS Extra Data.
6807	*/
6808	cb = sizeof(mode_info_list) + sizeof(ModeInfoListItem);
6809
6810	rc = pHlp->pfnCFGMQueryU32(pCfg, "HeightReduction", &cyReduction);
6811	if (RT_SUCCESS(rc) && cyReduction)
6812	cb = 2; / Default mode list will be twice long */
6813	else
6814	cyReduction = 0;
6815
6816	rc = pHlp->pfnCFGMQueryU32(pCfg, "CustomVideoModes", &cCustomModes);
6817	if (RT_SUCCESS(rc) && cCustomModes)
6818	cb += sizeof(ModeInfoListItem) * cCustomModes;
6819	else
6820	cCustomModes = 0;
6821
6822	/*
6823	* Allocate and initialize buffer for the VBE BIOS Extra Data.
6824	*/
6825	AssertRelease(sizeof(VBEHEADER) + cb < 65536);
6826	pThisCC->cbVBEExtraData = (uint16_t)(sizeof(VBEHEADER) + cb);
6827	pThisCC->pbVBEExtraData = (uint8_t *)PDMDevHlpMMHeapAllocZ(pDevIns, pThisCC->cbVBEExtraData);
6828	if (!pThisCC->pbVBEExtraData)
6829	return VERR_NO_MEMORY;
6830
6831	pVBEDataHdr = (PVBEHEADER)pThisCC->pbVBEExtraData;
6832	pVBEDataHdr->u16Signature = VBEHEADER_MAGIC;
6833	pVBEDataHdr->cbData = cb;
6834
6835	pCurMode = (ModeInfoListItem *)(pVBEDataHdr + 1);
6836	for (i = 0; i < MODE_INFO_SIZE; i++)
6837	{
6838	uint32_t pixelWidth, reqSize;
6839	if (mode_info_list[i].info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
6840	pixelWidth = 2;
6841	else
6842	pixelWidth = (mode_info_list[i].info.BitsPerPixel +7) / 8;
6843	reqSize = mode_info_list[i].info.XResolution
6844	* mode_info_list[i].info.YResolution
6845	* pixelWidth;
6846	if (reqSize >= pThis->vram_size)
6847	continue;
6848	if (!reqSize)
6849	continue;
6850	if ( mode_info_list[i].info.XResolution > maxBiosXRes
6851	\|\| mode_info_list[i].info.YResolution > maxBiosYRes)
6852	continue;
6853	*pCurMode = mode_info_list[i];
6854	vgaR3AdjustModeInfo(pThis, pCurMode);
6855	pCurMode++;
6856	}
6857
6858	/*
6859	* Copy default modes with subtracted YResolution.
6860	*/
6861	if (cyReduction)
6862	{
6863	ModeInfoListItem *pDefMode = mode_info_list;
6864	Log(("vgaR3Construct: cyReduction=%u\n", cyReduction));
6865	for (i = 0; i < MODE_INFO_SIZE; i++, pDefMode++)
6866	{
6867	uint32_t pixelWidth, reqSize;
6868	if (pDefMode->info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
6869	pixelWidth = 2;
6870	else
6871	pixelWidth = (pDefMode->info.BitsPerPixel + 7) / 8;
6872	reqSize = pDefMode->info.XResolution * pDefMode->info.YResolution * pixelWidth;
6873	if (reqSize >= pThis->vram_size)
6874	continue;
6875	if ( pDefMode->info.XResolution > maxBiosXRes
6876	\|\| pDefMode->info.YResolution - cyReduction > maxBiosYRes)
6877	continue;
6878	pCurMode = pDefMode;
6879	pCurMode->mode += 0x30;
6880	pCurMode->info.YResolution -= cyReduction;
6881	pCurMode++;
6882	}
6883	}
6884
6885
6886	/*
6887	* Add custom modes.
6888	*/
6889	if (cCustomModes)
6890	{
6891	uint16_t u16CurMode = VBE_VBOX_MODE_CUSTOM1;
6892	for (i = 1; i <= cCustomModes; i++)
6893	{
6894	char szExtraDataKey[sizeof("CustomVideoModeXX")];
6895	char *pszExtraData = NULL;
6896
6897	/* query and decode the custom mode string. */
6898	RTStrPrintf(szExtraDataKey, sizeof(szExtraDataKey), "CustomVideoMode%d", i);
6899	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, szExtraDataKey, &pszExtraData);
6900	if (RT_SUCCESS(rc))
6901	{
6902	ModeInfoListItem *pDefMode = mode_info_list;
6903	unsigned int cx, cy, cBits, cParams, j;
6904	uint16_t u16DefMode;
6905
6906	cParams = sscanf(pszExtraData, "%ux%ux%u", &cx, &cy, &cBits);
6907	if ( cParams != 3
6908	\|\| (cBits != 8 && cBits != 16 && cBits != 24 && cBits != 32))
6909	{
6910	AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cBits=%d\n", pszExtraData, szExtraDataKey, cBits));
6911	return VERR_VGA_INVALID_CUSTOM_MODE;
6912	}
6913	if (!cx \|\| !cy)
6914	{
6915	AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cx=%u, cy=%u\n", pszExtraData, szExtraDataKey, cx, cy));
6916	return VERR_VGA_INVALID_CUSTOM_MODE;
6917	}
6918	cbPitch = calc_line_pitch(cBits, cx);
6919	if (cy * cbPitch >= pThis->vram_size)
6920	{
6921	AssertMsgFailed(("Configuration error: custom video mode %dx%dx%dbits is too large for the virtual video memory of %dMb. Please increase the video memory size.\n",
6922	cx, cy, cBits, pThis->vram_size / _1M));
6923	return VERR_VGA_INVALID_CUSTOM_MODE;
6924	}
6925	PDMDevHlpMMHeapFree(pDevIns, pszExtraData);
6926
6927	/* Use defaults from max@bpp mode. */
6928	switch (cBits)
6929	{
6930	case 8:
6931	u16DefMode = VBE_VESA_MODE_1024X768X8;
6932	break;
6933
6934	case 16:
6935	u16DefMode = VBE_VESA_MODE_1024X768X565;
6936	break;
6937
6938	case 24:
6939	u16DefMode = VBE_VESA_MODE_1024X768X888;
6940	break;
6941
6942	case 32:
6943	u16DefMode = VBE_OWN_MODE_1024X768X8888;
6944	break;
6945
6946	default: /* gcc, shut up! */
6947	AssertMsgFailed(("gone postal!\n"));
6948	continue;
6949	}
6950
6951	/* mode_info_list is not terminated */
6952	for (j = 0; j < MODE_INFO_SIZE && pDefMode->mode != u16DefMode; j++)
6953	pDefMode++;
6954	Assert(j < MODE_INFO_SIZE);
6955
6956	pCurMode = pDefMode;
6957	pCurMode->mode = u16CurMode++;
6958
6959	/* adjust defaults */
6960	pCurMode->info.XResolution = cx;
6961	pCurMode->info.YResolution = cy;
6962	pCurMode->info.BytesPerScanLine = cbPitch;
6963	pCurMode->info.LinBytesPerScanLine = cbPitch;
6964	vgaR3AdjustModeInfo(pThis, pCurMode);
6965
6966	/* commit it */
6967	pCurMode++;
6968	}
6969	else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
6970	{
6971	AssertMsgFailed(("pHlp->pfnCFGMQueryStringAlloc(,'%s',) -> %Rrc\n", szExtraDataKey, rc));
6972	return rc;
6973	}
6974	} /* foreach custom mode key */
6975	}
6976
6977	/*
6978	* Add the "End of list" mode.
6979	*/
6980	memset(pCurMode, 0, sizeof(*pCurMode));
6981	pCurMode->mode = VBE_VESA_MODE_END_OF_LIST;
6982
6983	/*
6984	* Register I/O Port for the VBE BIOS Extra Data.
6985	*/
6986	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, VBE_EXTRA_PORT, 1 /cPorts/, vbeR3IOPortWriteVbeExtra, vbeR3IoPortReadVbeExtra,
6987	"VBE BIOS Extra Data", NULL /paExtDesc/, &pThis->hIoPortVbeExtra);
6988	AssertRCReturn(rc, rc);
6989
6990	/*
6991	* Register I/O Port for the BIOS Logo.
6992	*/
6993	rc = PDMDevHlpIoPortCreateAndMap(pDevIns, LOGO_IO_PORT, 1 /cPorts/, vbeR3IoPortWriteCmdLogo, vbeR3IoPortReadCmdLogo,
6994	"BIOS Logo", NULL /paExtDesc/, &pThis->hIoPortCmdLogo);
6995	AssertRCReturn(rc, rc);
6996
6997	/*
6998	* Register debugger info callbacks.
6999	*/
7000	PDMDevHlpDBGFInfoRegister(pDevIns, "vga", "Display basic VGA state.", vgaR3InfoState);
7001	PDMDevHlpDBGFInfoRegister(pDevIns, "vgatext", "Display VGA memory formatted as text.", vgaR3InfoText);
7002	PDMDevHlpDBGFInfoRegister(pDevIns, "vgacr", "Dump VGA CRTC registers.", vgaR3InfoCR);
7003	PDMDevHlpDBGFInfoRegister(pDevIns, "vgagr", "Dump VGA Graphics Controller registers.", vgaR3InfoGR);
7004	PDMDevHlpDBGFInfoRegister(pDevIns, "vgasr", "Dump VGA Sequencer registers.", vgaR3InfoSR);
7005	PDMDevHlpDBGFInfoRegister(pDevIns, "vgaar", "Dump VGA Attribute Controller registers.", vgaR3InfoAR);
7006	PDMDevHlpDBGFInfoRegister(pDevIns, "vgapl", "Dump planar graphics state.", vgaR3InfoPlanar);
7007	PDMDevHlpDBGFInfoRegister(pDevIns, "vgadac", "Dump VGA DAC registers.", vgaR3InfoDAC);
7008	PDMDevHlpDBGFInfoRegister(pDevIns, "vbe", "Dump VGA VBE registers.", vgaR3InfoVBE);
7009
7010	/*
7011	* Construct the logo header.
7012	*/
7013	LOGOHDR LogoHdr = { LOGO_HDR_MAGIC, 0, 0, 0, 0, 0, 0 };
7014
7015	rc = pHlp->pfnCFGMQueryU8(pCfg, "FadeIn", &LogoHdr.fu8FadeIn);
7016	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7017	LogoHdr.fu8FadeIn = 1;
7018	else if (RT_FAILURE(rc))
7019	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"FadeIn\" as integer failed"));
7020
7021	rc = pHlp->pfnCFGMQueryU8(pCfg, "FadeOut", &LogoHdr.fu8FadeOut);
7022	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7023	LogoHdr.fu8FadeOut = 1;
7024	else if (RT_FAILURE(rc))
7025	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"FadeOut\" as integer failed"));
7026
7027	rc = pHlp->pfnCFGMQueryU16(pCfg, "LogoTime", &LogoHdr.u16LogoMillies);
7028	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7029	LogoHdr.u16LogoMillies = 0;
7030	else if (RT_FAILURE(rc))
7031	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"LogoTime\" as integer failed"));
7032
7033	rc = pHlp->pfnCFGMQueryU8(pCfg, "ShowBootMenu", &LogoHdr.fu8ShowBootMenu);
7034	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7035	LogoHdr.fu8ShowBootMenu = 0;
7036	else if (RT_FAILURE(rc))
7037	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Querying \"ShowBootMenu\" as integer failed"));
7038
7039	# if defined(DEBUG) && !defined(DEBUG_sunlover) && !defined(DEBUG_michael)
7040	/* Disable the logo abd menu if all default settings. */
7041	if ( LogoHdr.fu8FadeIn
7042	&& LogoHdr.fu8FadeOut
7043	&& LogoHdr.u16LogoMillies == 0
7044	&& LogoHdr.fu8ShowBootMenu == 2)
7045	{
7046	LogoHdr.fu8FadeIn = LogoHdr.fu8FadeOut = 0;
7047	LogoHdr.u16LogoMillies = 500;
7048	}
7049	# endif
7050
7051	/* Delay the logo a little bit */
7052	if (LogoHdr.fu8FadeIn && LogoHdr.fu8FadeOut && !LogoHdr.u16LogoMillies)
7053	LogoHdr.u16LogoMillies = RT_MAX(LogoHdr.u16LogoMillies, LOGO_DELAY_TIME);
7054
7055	/*
7056	* Get the Logo file name.
7057	*/
7058	rc = pHlp->pfnCFGMQueryStringAlloc(pCfg, "LogoFile", &pThisCC->pszLogoFile);
7059	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
7060	pThisCC->pszLogoFile = NULL;
7061	else if (RT_FAILURE(rc))
7062	return PDMDEV_SET_ERROR(pDevIns, rc,
7063	N_("Configuration error: Querying \"LogoFile\" as a string failed"));
7064	else if (!*pThisCC->pszLogoFile)
7065	{
7066	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
7067	pThisCC->pszLogoFile = NULL;
7068	}
7069
7070	/*
7071	* Determine the logo size, open any specified logo file in the process.
7072	*/
7073	LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
7074	RTFILE FileLogo = NIL_RTFILE;
7075	if (pThisCC->pszLogoFile)
7076	{
7077	rc = RTFileOpen(&FileLogo, pThisCC->pszLogoFile,
7078	RTFILE_O_READ \| RTFILE_O_OPEN \| RTFILE_O_DENY_WRITE);
7079	if (RT_SUCCESS(rc))
7080	{
7081	uint64_t cbFile;
7082	rc = RTFileQuerySize(FileLogo, &cbFile);
7083	if (RT_SUCCESS(rc))
7084	{
7085	if (cbFile > 0 && cbFile < 32*_1M)
7086	LogoHdr.cbLogo = (uint32_t)cbFile;
7087	else
7088	rc = VERR_TOO_MUCH_DATA;
7089	}
7090	}
7091	if (RT_FAILURE(rc))
7092	{
7093	/*
7094	* Ignore failure and fall back to the default logo.
7095	*/
7096	LogRel(("vgaR3Construct: Failed to open logo file '%s', rc=%Rrc!\n", pThisCC->pszLogoFile, rc));
7097	if (FileLogo != NIL_RTFILE)
7098	RTFileClose(FileLogo);
7099	FileLogo = NIL_RTFILE;
7100	PDMDevHlpMMHeapFree(pDevIns, pThisCC->pszLogoFile);
7101	pThisCC->pszLogoFile = NULL;
7102	}
7103	}
7104
7105	/*
7106	* Disable graphic splash screen if it doesn't fit into VRAM.
7107	*/
7108	if (pThis->vram_size < LOGO_MAX_SIZE)
7109	LogoHdr.fu8FadeIn = LogoHdr.fu8FadeOut = LogoHdr.u16LogoMillies = 0;
7110
7111	/*
7112	* Allocate buffer for the logo data.
7113	* Let us fall back to default logo on read failure.
7114	*/
7115	pThisCC->cbLogo = LogoHdr.cbLogo;
7116	if (g_cbVgaDefBiosLogo)
7117	pThisCC->cbLogo = g_cbVgaDefBiosLogo;
7118	# ifndef VBOX_OSE
7119	if (g_cbVgaDefBiosLogoNY)
7120	pThisCC->cbLogo = g_cbVgaDefBiosLogoNY;
7121	# endif
7122	pThisCC->cbLogo += sizeof(LogoHdr);
7123
7124	pThisCC->pbLogo = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, pThisCC->cbLogo);
7125	if (pThisCC->pbLogo)
7126	{
7127	/*
7128	* Write the logo header.
7129	*/
7130	PLOGOHDR pLogoHdr = (PLOGOHDR)pThisCC->pbLogo;
7131	*pLogoHdr = LogoHdr;
7132
7133	/*
7134	* Write the logo bitmap.
7135	*/
7136	if (pThisCC->pszLogoFile)
7137	{
7138	rc = RTFileRead(FileLogo, pLogoHdr + 1, LogoHdr.cbLogo, NULL);
7139	if (RT_SUCCESS(rc))
7140	rc = vbeR3ParseBitmap(pThisCC);
7141	if (RT_FAILURE(rc))
7142	{
7143	LogRel(("Error %Rrc reading logo file '%s', using internal logo\n",
7144	rc, pThisCC->pszLogoFile));
7145	pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
7146	}
7147	}
7148	if ( !pThisCC->pszLogoFile
7149	\|\| RT_FAILURE(rc))
7150	{
7151	# ifndef VBOX_OSE
7152	RTTIMESPEC Now;
7153	RTTimeLocalNow(&Now);
7154	RTTIME T;
7155	RTTimeLocalExplode(&T, &Now);
7156	bool fSuppressNewYearSplash = false;
7157	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "SuppressNewYearSplash", &fSuppressNewYearSplash, true);
7158	if ( !fSuppressNewYearSplash
7159	&& (T.u16YearDay > 353 \|\| T.u16YearDay < 10))
7160	{
7161	pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogoNY;
7162	memcpy(pLogoHdr + 1, g_abVgaDefBiosLogoNY, LogoHdr.cbLogo);
7163	pThisCC->fBootMenuInverse = true;
7164	}
7165	else
7166	# endif
7167	memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
7168	rc = vbeR3ParseBitmap(pThisCC);
7169	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("Parsing of internal bitmap failed! vbeR3ParseBitmap() -> %Rrc\n", rc), rc);
7170	}
7171
7172	rc = VINF_SUCCESS;
7173	}
7174	else
7175	rc = VERR_NO_MEMORY;
7176
7177	/*
7178	* Cleanup.
7179	*/
7180	if (FileLogo != NIL_RTFILE)
7181	RTFileClose(FileLogo);
7182
7183	# ifdef VBOX_WITH_HGSMI
7184	VBVAInit(pDevIns, pThis, pThisCC);
7185	# endif
7186
7187	# ifdef VBOX_WITH_VDMA
7188	if (rc == VINF_SUCCESS)
7189	{
7190	rc = vboxVDMAConstruct(pThis, pThisCC, 1024);
7191	AssertRC(rc);
7192	}
7193	# endif
7194
7195	# ifdef VBOX_WITH_VMSVGA
7196	if ( rc == VINF_SUCCESS
7197	&& pThis->fVMSVGAEnabled)
7198	rc = vmsvgaR3Init(pDevIns);
7199	# endif
7200
7201	/*
7202	* Statistics.
7203	*/
7204	# ifdef VBOX_WITH_STATISTICS
7205	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRZMemoryRead, STAMTYPE_PROFILE, "RZ/MMIO-Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
7206	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatR3MemoryRead, STAMTYPE_PROFILE, "R3/MMIO-Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
7207	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRZMemoryWrite, STAMTYPE_PROFILE, "RZ/MMIO-Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
7208	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatR3MemoryWrite, STAMTYPE_PROFILE, "R3/MMIO-Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
7209	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMapPage, STAMTYPE_COUNTER, "MapPageCalls", STAMUNIT_OCCURENCES, "Calls to IOMMmioMapMmio2Page.");
7210	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatUpdateDisp, STAMTYPE_COUNTER, "UpdateDisplay", STAMUNIT_OCCURENCES, "Calls to vgaR3PortUpdateDisplay().");
7211	# endif
7212	# ifdef VBOX_WITH_HGSMI
7213	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatHgsmiMdaCgaAccesses, STAMTYPE_COUNTER, "HgmsiMdaCgaAccesses", STAMUNIT_OCCURENCES, "Number of non-HGMSI accesses for 03b0-3b3 and 03d0-3d3.");
7214	# endif
7215
7216	/* Init latched access mask. */
7217	pThis->uMaskLatchAccess = 0x3ff;
7218
7219	if (RT_SUCCESS(rc))
7220	{
7221	PPDMIBASE pBase;
7222	/*
7223	* Attach status driver (optional).
7224	*/
7225	rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
7226	if (RT_SUCCESS(rc))
7227	pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7228	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
7229	{
7230	Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pReg->szName, pDevIns->iInstance));
7231	rc = VINF_SUCCESS;
7232	}
7233	else
7234	{
7235	AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
7236	rc = PDMDEV_SET_ERROR(pDevIns, rc, N_("VGA cannot attach to status driver"));
7237	}
7238	}
7239	return rc;
7240	}
7241
7242	#else /* !IN_RING3 */
7243
7244	/**
7245	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7246	*/
7247	static DECLCALLBACK(int) vgaRZConstruct(PPDMDEVINS pDevIns)
7248	{
7249	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7250	PVGASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PVGASTATE);
7251	PVGASTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PVGASTATECC);
7252
7253	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, &pThis->CritSect);
7254	AssertRCReturn(rc, rc);
7255
7256	/*
7257	* Set I/O port callbacks for this context.
7258	* We just copy the ring-3 registration bits and remove the '&' before the handle.
7259	*/
7260	# define REG_PORT(a_uPort, a_cPorts, a_pfnWrite, a_pfnRead, a_szDesc, a_hIoPort) do { \
7261	rc = PDMDevHlpIoPortSetUpContext(pDevIns, a_hIoPort, a_pfnWrite, a_pfnRead, NULL /pvUser/); \
7262	AssertRCReturn(rc, rc); \
7263	} while (0)
7264
7265	REG_PORT(0x3c0, 2, vgaIoPortArWrite, vgaIoPortArRead, "Attribute Controller", pThis->hIoPortAr);
7266	REG_PORT(0x3c2, 1, vgaIoPortMsrWrite, vgaIoPortSt00Read, "MSR / ST00", pThis->hIoPortMsrSt00);
7267	REG_PORT(0x3c3, 1, vgaIoPortUnusedWrite, vgaIoPortUnusedRead, "0x3c3", pThis->hIoPort3c3);
7268	REG_PORT(0x3c4, 2, vgaIoPortSrWrite, vgaIoPortSrRead, "Sequencer", pThis->hIoPortSr);
7269	REG_PORT(0x3c6, 4, vgaIoPortDacWrite, vgaIoPortDacRead, "DAC", pThis->hIoPortDac);
7270	REG_PORT(0x3ca, 4, vgaIoPortPosWrite, vgaIoPortPosRead, "Graphics Position", /?/ pThis->hIoPortPos);
7271	REG_PORT(0x3ce, 2, vgaIoPortGrWrite, vgaIoPortGrRead, "Graphics Controller", pThis->hIoPortGr);
7272
7273	REG_PORT(0x3b4, 2, vgaIoPortMdaCrtWrite, vgaIoPortMdaCrtRead, "MDA CRT control", pThis->hIoPortMdaCrt);
7274	REG_PORT(0x3ba, 1, vgaIoPortMdaFcrWrite, vgaIoPortMdaStRead, "MDA feature/status", pThis->hIoPortMdaFcrSt);
7275	REG_PORT(0x3d4, 2, vgaIoPortCgaCrtWrite, vgaIoPortCgaCrtRead, "CGA CRT control", pThis->hIoPortCgaCrt);
7276	REG_PORT(0x3da, 1, vgaIoPortCgaFcrWrite, vgaIoPortCgaStRead, "CGA Feature / status", pThis->hIoPortCgaFcrSt);
7277
7278	# ifdef CONFIG_BOCHS_VBE
7279	REG_PORT(0x1ce, 1, vgaIoPortWriteVbeIndex, vgaIoPortReadVbeIndex, "VBE Index", pThis->hIoPortVbeIndex);
7280	REG_PORT(0x1cf, 1, vgaIoPortWriteVbeData, vgaIoPortReadVbeData, "VBE Data", pThis->hIoPortVbeData);
7281	# endif /* CONFIG_BOCHS_VBE */
7282
7283	# undef REG_PORT
7284
7285	/* BIOS port: */
7286	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortBios, vgaIoPortWriteBios, vgaIoPortReadBios, NULL /pvUser/);
7287	AssertRCReturn(rc, rc);
7288
7289	# ifdef VBOX_WITH_VMSVGA
7290	if (pThis->hIoPortVmSvga != NIL_IOMIOPORTHANDLE)
7291	{
7292	AssertReturn(pThis->fVMSVGAEnabled, VERR_INVALID_STATE);
7293	rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPortVmSvga, vmsvgaIOWrite, vmsvgaIORead, NULL /pvUser/);
7294	AssertRCReturn(rc, rc);
7295	}
7296	else
7297	AssertReturn(!pThis->fVMSVGAEnabled, VERR_INVALID_STATE);
7298	# endif
7299
7300	/*
7301	* MMIO.
7302	*/
7303	rc = PDMDevHlpMmioSetUpContextEx(pDevIns, pThis->hMmioLegacy, vgaMmioWrite, vgaMmioRead, vgaMmioFill, NULL /pvUser/);
7304	AssertRCReturn(rc, rc);
7305
7306	/*
7307	* Map the start of the VRAM into this context.
7308	*/
7309	# if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
7310	rc = PDMDevHlpMmio2SetUpContext(pDevIns, pThis->hMmio2VRam, 0 /* off /, VGA_MAPPING_SIZE, (void *)&pThisCC->pbVRam);
7311	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMmio2SetUpContext(,VRAM,0,%#x,) -> %Rrc\n", VGA_MAPPING_SIZE, rc), rc);
7312	# endif
7313
7314	/*
7315	* Map the first page of the VMSVGA FIFO into this context (not raw-mode).
7316	* We currently only access SVGA_FIFO_MIN, SVGA_FIFO_PITCHLOCK, and SVGA_FIFO_BUSY.
7317	*/
7318	# if defined(VBOX_WITH_VMSVGA) && !defined(IN_RC)
7319	AssertCompile((RT_MAX(SVGA_FIFO_MIN, RT_MAX(SVGA_FIFO_PITCHLOCK, SVGA_FIFO_BUSY)) + 1) * sizeof(uint32_t) < PAGE_SIZE);
7320	if (pThis->fVMSVGAEnabled)
7321	{
7322	rc = PDMDevHlpMmio2SetUpContext(pDevIns, pThis->hMmio2VmSvgaFifo, 0 /* off */, PAGE_SIZE,
7323	(void **)&pThisCC->svga.pau32FIFO);
7324	AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMapMMIO2IntoR0(%#x,) -> %Rrc\n", pThis->svga.cbFIFO, rc), rc);
7325	}
7326	else
7327	AssertReturn(pThis->hMmio2VmSvgaFifo == NIL_PGMMMIO2HANDLE, VERR_INVALID_STATE);
7328	# endif
7329
7330	return VINF_SUCCESS;
7331	}
7332
7333	#endif /* !IN_RING3 */
7334
7335	/**
7336	* The device registration structure.
7337	*/
7338	const PDMDEVREG g_DeviceVga =
7339	{
7340	/* .u32Version = */ PDM_DEVREG_VERSION,
7341	/* .uReserved0 = */ 0,
7342	/* .szName = */ "vga",
7343	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
7344	/* .fClass = */ PDM_DEVREG_CLASS_GRAPHICS,
7345	/* .cMaxInstances = */ 1,
7346	/* .uSharedVersion = */ 42,
7347	/* .cbInstanceShared = */ sizeof(VGASTATE),
7348	/* .cbInstanceCC = */ sizeof(VGASTATECC),
7349	/* .cbInstanceRC = */ sizeof(VGASTATERC),
7350	/* .cMaxPciDevices = */ 1,
7351	/* .cMaxMsixVectors = */ 0,
7352	/* .pszDescription = */ "VGA Adaptor with VESA extensions.",
7353	#if defined(IN_RING3)
7354	/* .pszRCMod = */ "VBoxDDRC.rc",
7355	/* .pszR0Mod = */ "VBoxDDR0.r0",
7356	/* .pfnConstruct = */ vgaR3Construct,
7357	/* .pfnDestruct = */ vgaR3Destruct,
7358	/* .pfnRelocate = */ vgaR3Relocate,
7359	/* .pfnMemSetup = */ NULL,
7360	/* .pfnPowerOn = */ vgaR3PowerOn,
7361	/* .pfnReset = */ vgaR3Reset,
7362	/* .pfnSuspend = */ NULL,
7363	/* .pfnResume = */ vgaR3Resume,
7364	/* .pfnAttach = */ vgaAttach,
7365	/* .pfnDetach = */ vgaDetach,
7366	/* .pfnQueryInterface = */ NULL,
7367	/* .pfnInitComplete = */ NULL,
7368	/* .pfnPowerOff = */ vgaR3PowerOff,
7369	/* .pfnSoftReset = */ NULL,
7370	/* .pfnReserved0 = */ NULL,
7371	/* .pfnReserved1 = */ NULL,
7372	/* .pfnReserved2 = */ NULL,
7373	/* .pfnReserved3 = */ NULL,
7374	/* .pfnReserved4 = */ NULL,
7375	/* .pfnReserved5 = */ NULL,
7376	/* .pfnReserved6 = */ NULL,
7377	/* .pfnReserved7 = */ NULL,
7378	#elif defined(IN_RING0)
7379	/* .pfnEarlyConstruct = */ NULL,
7380	/* .pfnConstruct = */ vgaRZConstruct,
7381	/* .pfnDestruct = */ NULL,
7382	/* .pfnFinalDestruct = */ NULL,
7383	/* .pfnRequest = */ NULL,
7384	/* .pfnReserved0 = */ NULL,
7385	/* .pfnReserved1 = */ NULL,
7386	/* .pfnReserved2 = */ NULL,
7387	/* .pfnReserved3 = */ NULL,
7388	/* .pfnReserved4 = */ NULL,
7389	/* .pfnReserved5 = */ NULL,
7390	/* .pfnReserved6 = */ NULL,
7391	/* .pfnReserved7 = */ NULL,
7392	#elif defined(IN_RC)
7393	/* .pfnConstruct = */ vgaRZConstruct,
7394	/* .pfnReserved0 = */ NULL,
7395	/* .pfnReserved1 = */ NULL,
7396	/* .pfnReserved2 = */ NULL,
7397	/* .pfnReserved3 = */ NULL,
7398	/* .pfnReserved4 = */ NULL,
7399	/* .pfnReserved5 = */ NULL,
7400	/* .pfnReserved6 = */ NULL,
7401	/* .pfnReserved7 = */ NULL,
7402	#else
7403	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7404	#endif
7405	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
7406	};
7407
7408	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7409
7410	/*
7411	* Local Variables:
7412	* nuke-trailing-whitespace-p:nil
7413	* End:
7414	*/

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.cpp@ 87979

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