VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.cpp@ 9515

Last change on this file since 9515 was 9213, checked in by vboxsync, 17 years ago

Assertion triggers with GC_ARCH_BITS == 32
  • Property svn:eol-style set to native
File size: 188.4 KB
Line 
1#ifdef VBOX
2/* $Id: $ */
3/** @file
4 * VBox VGA/VESA device
5 */
6
7/*
8 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
19 * Clara, CA 95054 USA or visit http://www.sun.com if you need
20 * additional information or have any questions.
21 * --------------------------------------------------------------------
22 *
23 * This code is based on:
24 *
25 * QEMU VGA Emulator.
26 *
27 * Copyright (c) 2003 Fabrice Bellard
28 *
29 * Permission is hereby granted, free of charge, to any person obtaining a copy
30 * of this software and associated documentation files (the "Software"), to deal
31 * in the Software without restriction, including without limitation the rights
32 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
33 * copies of the Software, and to permit persons to whom the Software is
34 * furnished to do so, subject to the following conditions:
35 *
36 * The above copyright notice and this permission notice shall be included in
37 * all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
42 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
44 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
45 * THE SOFTWARE.
46 */
47
48/*******************************************************************************
49* Defined Constants And Macros *
50*******************************************************************************/
51/** The default amount of VRAM. */
52#define VGA_VRAM_DEFAULT (_4M)
53/** The maximum amount of VRAM. */
54#define VGA_VRAM_MAX (128 * _1M)
55/** The minimum amount of VRAM. */
56#define VGA_VRAM_MIN (_1M)
57
58/** The size of the VGA GC mapping.
59 * This is supposed to be all the VGA memory accessible to the guest.
60 * The initial value was 256KB but NTAllInOne.iso appears to access more
61 * thus the limit was upped to 512KB.
62 *
63 * @todo Someone with some VGA knowhow should make a better guess at this value.
64 */
65#define VGA_MAPPING_SIZE _512K
66
67/** Converts a vga adaptor state pointer to a device instance pointer. */
68#define VGASTATE2DEVINS(pVgaState) ((pVgaState)->CTXSUFF(pDevIns))
69
70/** Use VBE bytewise I/O */
71#define VBE_BYTEWISE_IO
72
73/** Use VBE new dynamic mode list.
74 * If this is not defined, no checks are carried out to see if the modes all
75 * fit into the framebuffer! See the VRAM_SIZE_FIX define. */
76#define VBE_NEW_DYN_LIST
77
78/** Check that the video modes fit into virtual video memory.
79 * Only works when VBE_NEW_DYN_LIST is defined! */
80#define VRAM_SIZE_FIX
81
82/** Some fixes to ensure that logical scan-line lengths are not overwritten. */
83#define KEEP_SCAN_LINE_LENGTH
84
85
86/*******************************************************************************
87* Header Files *
88*******************************************************************************/
89#define LOG_GROUP LOG_GROUP_DEV_VGA
90#include <VBox/pdmdev.h>
91#include <VBox/pgm.h>
92#include <iprt/assert.h>
93#include <iprt/asm.h>
94#include <iprt/file.h>
95#include <iprt/string.h>
96
97#include <VBox/VBoxGuest.h>
98#include <VBox/VBoxVideo.h>
99#include <VBox/bioslogo.h>
100
101#if defined(VBE_NEW_DYN_LIST) && defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
102# include "DevVGAModes.h"
103# include <stdio.h> /* sscan */
104#endif
105
106#include "vl_vbox.h"
107#include "DevVGA.h"
108#include "Builtins.h"
109#include "Builtins2.h"
110
111
112/*******************************************************************************
113* Structures and Typedefs *
114*******************************************************************************/
115#pragma pack(1)
116
117/** BMP File Format Bitmap Header. */
118typedef struct
119{
120 uint16_t Type; /* File Type Identifier */
121 uint32_t FileSize; /* Size of File */
122 uint16_t Reserved1; /* Reserved (should be 0) */
123 uint16_t Reserved2; /* Reserved (should be 0) */
124 uint32_t Offset; /* Offset to bitmap data */
125} BMPINFO;
126
127/** Pointer to a bitmap header*/
128typedef BMPINFO *PBMPINFO;
129
130/** OS/2 1.x Information Header Format. */
131typedef struct
132{
133 uint32_t Size; /* Size of Remianing Header */
134 uint16_t Width; /* Width of Bitmap in Pixels */
135 uint16_t Height; /* Height of Bitmap in Pixels */
136 uint16_t Planes; /* Number of Planes */
137 uint16_t BitCount; /* Color Bits Per Pixel */
138} OS2HDR;
139
140/** Pointer to a OS/2 1.x header format */
141typedef OS2HDR *POS2HDR;
142
143/** OS/2 2.0 Information Header Format. */
144typedef struct
145{
146 uint32_t Size; /* Size of Remianing Header */
147 uint32_t Width; /* Width of Bitmap in Pixels */
148 uint32_t Height; /* Height of Bitmap in Pixels */
149 uint16_t Planes; /* Number of Planes */
150 uint16_t BitCount; /* Color Bits Per Pixel */
151 uint32_t Compression; /* Compression Scheme (0=none) */
152 uint32_t SizeImage; /* Size of bitmap in bytes */
153 uint32_t XPelsPerMeter; /* Horz. Resolution in Pixels/Meter */
154 uint32_t YPelsPerMeter; /* Vert. Resolution in Pixels/Meter */
155 uint32_t ClrUsed; /* Number of Colors in Color Table */
156 uint32_t ClrImportant; /* Number of Important Colors */
157 uint16_t Units; /* Resolution Mesaurement Used */
158 uint16_t Reserved; /* Reserved FIelds (always 0) */
159 uint16_t Recording; /* Orientation of Bitmap */
160 uint16_t Rendering; /* Halftone Algorithm Used on Image */
161 uint32_t Size1; /* Halftone Algorithm Data */
162 uint32_t Size2; /* Halftone Algorithm Data */
163 uint32_t ColorEncoding; /* Color Table Format (always 0) */
164 uint32_t Identifier; /* Misc. Field for Application Use */
165} OS22HDR;
166
167/** Pointer to a OS/2 2.0 header format */
168typedef OS22HDR *POS22HDR;
169
170/** Windows 3.x Information Header Format. */
171typedef struct
172{
173 uint32_t Size; /* Size of Remianing Header */
174 uint32_t Width; /* Width of Bitmap in Pixels */
175 uint32_t Height; /* Height of Bitmap in Pixels */
176 uint16_t Planes; /* Number of Planes */
177 uint16_t BitCount; /* Bits Per Pixel */
178 uint32_t Compression; /* Compression Scheme (0=none) */
179 uint32_t SizeImage; /* Size of bitmap in bytes */
180 uint32_t XPelsPerMeter; /* Horz. Resolution in Pixels/Meter */
181 uint32_t YPelsPerMeter; /* Vert. Resolution in Pixels/Meter */
182 uint32_t ClrUsed; /* Number of Colors in Color Table */
183 uint32_t ClrImportant; /* Number of Important Colors */
184} WINHDR;
185
186/** Pointer to a Windows 3.x header format */
187typedef WINHDR *PWINHDR;
188
189#pragma pack()
190
191#define BMP_ID 0x4D42
192
193/** @name BMP compressions.
194 * @{ */
195#define BMP_COMPRESS_NONE 0
196#define BMP_COMPRESS_RLE8 1
197#define BMP_COMPRESS_RLE4 2
198/** @} */
199
200/** @name BMP header sizes.
201 * @{ */
202#define BMP_HEADER_OS21 12
203#define BMP_HEADER_OS22 64
204#define BMP_HEADER_WIN3 40
205/** @} */
206
207/** The BIOS boot menu text position, X. */
208#define LOGO_F12TEXT_X 304
209/** The BIOS boot menu text position, Y. */
210#define LOGO_F12TEXT_Y 464
211
212/** Width of the "Press F12 to select boot device." bitmap.
213 Anything that exceeds the limit of F12BootText below is filled with
214 background. */
215#define LOGO_F12TEXT_WIDTH 286
216/** Height of the boot device selection bitmap, see LOGO_F12TEXT_WIDTH. */
217#define LOGO_F12TEXT_HEIGHT 12
218
219/** The BIOS logo delay time (msec). */
220#define LOGO_DELAY_TIME 2000
221
222#define LOGO_MAX_WIDTH 640
223#define LOGO_MAX_HEIGHT 480
224#define LOGO_MAX_SIZE LOGO_MAX_WIDTH * LOGO_MAX_HEIGHT * 4
225
226
227/*******************************************************************************
228* Global Variables *
229*******************************************************************************/
230/* "Press F12 to select boot device." bitmap. */
231static const uint8_t g_abLogoF12BootText[] =
232{
233#ifdef VBOX_OSE
234 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
236 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 0x0F, 0x7C,
237 0xF8, 0xF0, 0x01, 0xE0, 0x81, 0x9F, 0x3F, 0x00, 0x70, 0xF8, 0x00, 0xE0, 0xC3,
238 0x07, 0x0F, 0x1F, 0x3E, 0x70, 0x00, 0xF0, 0xE1, 0xC3, 0x07, 0x0E, 0x00, 0x6E,
239 0x7C, 0x60, 0xE0, 0xE1, 0xC3, 0x07, 0xC6, 0x80, 0x81, 0x31, 0x63, 0xC6, 0x00,
240 0x30, 0x80, 0x61, 0x0C, 0x00, 0x36, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
241 0x18, 0x36, 0x00, 0xCC, 0x8C, 0x19, 0xC3, 0x06, 0xC0, 0x8C, 0x31, 0x3C, 0x30,
242 0x8C, 0x19, 0x83, 0x31, 0x60, 0x60, 0x00, 0x0C, 0x18, 0x00, 0x0C, 0x60, 0x18,
243 0x00, 0x80, 0xC1, 0x18, 0x00, 0x30, 0x06, 0x60, 0x18, 0x30, 0x80, 0x01, 0x00,
244 0x33, 0x63, 0xC6, 0x30, 0x00, 0x30, 0x63, 0x80, 0x19, 0x0C, 0x03, 0x06, 0x00,
245 0x0C, 0x18, 0x18, 0xC0, 0x81, 0x03, 0x00, 0x03, 0x18, 0x0C, 0x00, 0x60, 0x30,
246 0x06, 0x00, 0x87, 0x01, 0x18, 0x06, 0x0C, 0x60, 0x00, 0xC0, 0xCC, 0x98, 0x31,
247 0x0C, 0x00, 0xCC, 0x18, 0x30, 0x0C, 0xC3, 0x80, 0x01, 0x00, 0x03, 0x66, 0xFE,
248 0x18, 0x30, 0x00, 0xC0, 0x02, 0x06, 0x06, 0x00, 0x18, 0x8C, 0x01, 0x60, 0xE0,
249 0x0F, 0x86, 0x3F, 0x03, 0x18, 0x00, 0x30, 0x33, 0x66, 0x0C, 0x03, 0x00, 0x33,
250 0xFE, 0x0C, 0xC3, 0x30, 0xE0, 0x0F, 0xC0, 0x87, 0x9B, 0x31, 0x63, 0xC6, 0x00,
251 0xF0, 0x80, 0x01, 0x03, 0x00, 0x06, 0x63, 0x00, 0x8C, 0x19, 0x83, 0x61, 0xCC,
252 0x18, 0x06, 0x00, 0x6C, 0x8C, 0x19, 0xC3, 0x00, 0x80, 0x8D, 0x31, 0xC3, 0x30,
253 0x8C, 0x19, 0x03, 0x30, 0xB3, 0xC3, 0x87, 0x0F, 0x1F, 0x00, 0x2C, 0x60, 0x80,
254 0x01, 0xE0, 0x87, 0x0F, 0x00, 0x3E, 0x7C, 0x60, 0xF0, 0xE1, 0xE3, 0x07, 0x00,
255 0x0F, 0x3E, 0x7C, 0xFC, 0x00, 0xC0, 0xC3, 0xC7, 0x30, 0x0E, 0x3E, 0x7C, 0x00,
256 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x1E, 0xC0, 0x00, 0x60, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x00, 0x00,
258 0x0C, 0x00, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0xC0, 0x0C, 0x87, 0x31, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x06, 0x00, 0x00, 0x18, 0x00, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x30,
261 0x00, 0x00, 0xC0, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0xF8, 0x83, 0xC1, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x01, 0x00,
263 0x00, 0x04, 0x00, 0x0E, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x30,
264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
267#else
268 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
269 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
270 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0xF8, 0xF0, 0x83,
271 0x07, 0x0F, 0xFE, 0x1F, 0x7E, 0x60, 0xC0, 0xFF, 0x8F, 0x07, 0xFF, 0x1F, 0x3C,
272 0xF8, 0xF0, 0xE0, 0xC1, 0x8F, 0xFF, 0x0F, 0x1E, 0x3C, 0xF8, 0xF1, 0xFF, 0x91,
273 0x83, 0x9F, 0x1F, 0x1E, 0x3C, 0xF8, 0x39, 0x7F, 0x7E, 0xCE, 0x9C, 0x39, 0xFF,
274 0xCF, 0x7F, 0x9E, 0xF3, 0xFF, 0xC9, 0x9C, 0xFF, 0x73, 0xE6, 0x7C, 0x9E, 0x33,
275 0xE7, 0xC9, 0xFF, 0x33, 0x73, 0xE6, 0x3C, 0xF9, 0x3F, 0x73, 0xCE, 0xC3, 0xCF,
276 0x73, 0xE6, 0x7C, 0xCE, 0x9F, 0x9F, 0xFF, 0xF3, 0xE7, 0xFF, 0xF3, 0x9F, 0xE7,
277 0xFF, 0x7F, 0x3E, 0xE7, 0xFF, 0xCF, 0xF9, 0x9F, 0xE7, 0xCF, 0x7F, 0xFE, 0xFF,
278 0xCC, 0x9C, 0x39, 0xCF, 0xFF, 0xCF, 0x9C, 0x7F, 0xE6, 0xF3, 0xFC, 0xF9, 0xFF,
279 0xF3, 0xE7, 0xE7, 0x3F, 0x7E, 0xFC, 0xFF, 0xFC, 0xE7, 0xF3, 0xFF, 0x9F, 0xCF,
280 0xF9, 0xFF, 0x78, 0xFE, 0xE7, 0xF9, 0xF3, 0x9F, 0xFF, 0x3F, 0x33, 0x67, 0xCE,
281 0xF3, 0xFF, 0x33, 0xE7, 0xCF, 0xF3, 0x3C, 0x7F, 0xFE, 0xFF, 0xFC, 0x99, 0x01,
282 0xE7, 0xCF, 0xFF, 0x3F, 0xFD, 0xF9, 0xF9, 0xFF, 0xE7, 0x73, 0xFE, 0x9F, 0x1F,
283 0xF0, 0x79, 0xC0, 0xFC, 0xE7, 0xFF, 0xCF, 0xCC, 0x99, 0xF3, 0xFC, 0xFF, 0xCC,
284 0x01, 0xF3, 0x3C, 0xCF, 0x1F, 0xF0, 0x3F, 0x78, 0x64, 0xCE, 0x9C, 0x39, 0xFF,
285 0x0F, 0x7F, 0xFE, 0xFC, 0xFF, 0xF9, 0x9C, 0xFF, 0x73, 0xE6, 0x7C, 0x9E, 0x33,
286 0xE7, 0xF9, 0xFF, 0x93, 0x73, 0xE6, 0x3C, 0xFF, 0x7F, 0x72, 0xCE, 0x3C, 0xCF,
287 0x73, 0xE6, 0xFC, 0xCF, 0x4C, 0x3C, 0x78, 0xF0, 0xE0, 0xFF, 0xD3, 0x9F, 0x7F,
288 0xFE, 0x1F, 0x78, 0xF0, 0xFF, 0xC1, 0x83, 0x9F, 0x0F, 0x1E, 0x1C, 0xF8, 0xFF,
289 0xF0, 0xC1, 0x83, 0x03, 0xFF, 0x3F, 0x3C, 0x38, 0xCF, 0xF1, 0xC1, 0x83, 0xFF,
290 0x33, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDC, 0xE1, 0x3F, 0xFF, 0x9F, 0xFF,
291 0xFF, 0xFF, 0xFF, 0xFF, 0xE7, 0xFF, 0xFF, 0x9F, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF,
292 0xF3, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xCC, 0xFF, 0xFF,
293 0xFF, 0xFF, 0xFF, 0x3F, 0xF3, 0x78, 0xCE, 0xFF, 0xE7, 0xFF, 0xFF, 0xFF, 0xFF,
294 0xFF, 0xF9, 0xFF, 0xFF, 0xE7, 0xFF, 0xCF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xCF,
295 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0xFF, 0x1F, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
296 0x07, 0x7C, 0x3E, 0xF8, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0xFE, 0xFF,
297 0xFF, 0xFB, 0xFF, 0xF1, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, 0xCF,
298 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
299 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
300 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
301#endif
302};
303
304
305#ifndef VBOX_DEVICE_STRUCT_TESTCASE
306/*******************************************************************************
307* Internal Functions *
308*******************************************************************************/
309__BEGIN_DECLS
310
311PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
312PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
313PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
314PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
315PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
316PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
317PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems);
318PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
319PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
320#ifdef IN_GC
321PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
322#endif
323#ifdef IN_RING0
324PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
325#endif
326#ifdef IN_RING3
327# ifdef VBE_NEW_DYN_LIST
328PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
329PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
330# endif
331PDMBOTHCBDECL(int) vbeIOPortReadCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
332PDMBOTHCBDECL(int) vbeIOPortWriteCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
333#endif /* IN_RING3 */
334
335
336__END_DECLS
337
338
339/**
340 * Set a VRAM page dirty.
341 *
342 * @param pData VGA instance data.
343 * @param offVRAM The VRAM offset of the page to set.
344 */
345DECLINLINE(void) vga_set_dirty(VGAState *pData, RTGCPHYS offVRAM)
346{
347 AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
348 ASMBitSet(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
349 pData->fHaveDirtyBits = true;
350}
351
352/**
353 * Tests if a VRAM page is dirty.
354 *
355 * @returns true if dirty.
356 * @returns false if clean.
357 * @param pData VGA instance data.
358 * @param offVRAM The VRAM offset of the page to check.
359 */
360DECLINLINE(bool) vga_is_dirty(VGAState *pData, RTGCPHYS offVRAM)
361{
362 AssertMsg(offVRAM < pData->vram_size, ("offVRAM = %p, pData->vram_size = %p\n", offVRAM, pData->vram_size));
363 return ASMBitTest(&pData->au32DirtyBitmap[0], offVRAM >> PAGE_SHIFT);
364}
365
366/**
367 * Reset dirty flags in a give range.
368 *
369 * @param pData VGA instance data.
370 * @param offVRAMStart Offset into the VRAM buffer of the first page.
371 * @param offVRAMEnd Offset into the VRAM buffer of the last page - exclusive.
372 */
373DECLINLINE(void) vga_reset_dirty(VGAState *pData, RTGCPHYS offVRAMStart, RTGCPHYS offVRAMEnd)
374{
375 Assert(offVRAMStart < pData->vram_size);
376 Assert(offVRAMEnd <= pData->vram_size);
377 Assert(offVRAMStart < offVRAMEnd);
378 ASMBitClearRange(&pData->au32DirtyBitmap[0], offVRAMStart >> PAGE_SHIFT, offVRAMEnd >> PAGE_SHIFT);
379}
380
381#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
382#endif /* VBOX */
383#ifndef VBOX_DEVICE_STRUCT_TESTCASE
384
385#ifndef VBOX
386#include "vl.h"
387#include "vga_int.h"
388#endif /* !VBOX */
389
390#ifdef LOG_ENABLED
391//#define DEBUG_VGA
392//#define DEBUG_VGA_MEM
393//#define DEBUG_VGA_REG
394
395#define DEBUG_BOCHS_VBE
396
397#endif
398
399/* force some bits to zero */
400#ifdef VBOX
401static
402#endif /* VBOX */
403const uint8_t sr_mask[8] = {
404 (uint8_t)~0xfc,
405 (uint8_t)~0xc2,
406 (uint8_t)~0xf0,
407 (uint8_t)~0xc0,
408 (uint8_t)~0xf1,
409 (uint8_t)~0xff,
410 (uint8_t)~0xff,
411 (uint8_t)~0x00,
412};
413
414#ifdef VBOX
415static
416#endif /* VBOX */
417const uint8_t gr_mask[16] = {
418 (uint8_t)~0xf0, /* 0x00 */
419 (uint8_t)~0xf0, /* 0x01 */
420 (uint8_t)~0xf0, /* 0x02 */
421 (uint8_t)~0xe0, /* 0x03 */
422 (uint8_t)~0xfc, /* 0x04 */
423 (uint8_t)~0x84, /* 0x05 */
424 (uint8_t)~0xf0, /* 0x06 */
425 (uint8_t)~0xf0, /* 0x07 */
426 (uint8_t)~0x00, /* 0x08 */
427 (uint8_t)~0xff, /* 0x09 */
428 (uint8_t)~0xff, /* 0x0a */
429 (uint8_t)~0xff, /* 0x0b */
430 (uint8_t)~0xff, /* 0x0c */
431 (uint8_t)~0xff, /* 0x0d */
432 (uint8_t)~0xff, /* 0x0e */
433 (uint8_t)~0xff, /* 0x0f */
434};
435
436#define cbswap_32(__x) \
437((uint32_t)( \
438 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
439 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
440 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
441 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
442
443#ifdef WORDS_BIGENDIAN
444#define PAT(x) cbswap_32(x)
445#else
446#define PAT(x) (x)
447#endif
448
449#ifdef WORDS_BIGENDIAN
450#define BIG 1
451#else
452#define BIG 0
453#endif
454
455#ifdef WORDS_BIGENDIAN
456#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
457#else
458#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
459#endif
460
461static const uint32_t mask16[16] = {
462 PAT(0x00000000),
463 PAT(0x000000ff),
464 PAT(0x0000ff00),
465 PAT(0x0000ffff),
466 PAT(0x00ff0000),
467 PAT(0x00ff00ff),
468 PAT(0x00ffff00),
469 PAT(0x00ffffff),
470 PAT(0xff000000),
471 PAT(0xff0000ff),
472 PAT(0xff00ff00),
473 PAT(0xff00ffff),
474 PAT(0xffff0000),
475 PAT(0xffff00ff),
476 PAT(0xffffff00),
477 PAT(0xffffffff),
478};
479
480#undef PAT
481
482#ifdef WORDS_BIGENDIAN
483#define PAT(x) (x)
484#else
485#define PAT(x) cbswap_32(x)
486#endif
487
488static const uint32_t dmask16[16] = {
489 PAT(0x00000000),
490 PAT(0x000000ff),
491 PAT(0x0000ff00),
492 PAT(0x0000ffff),
493 PAT(0x00ff0000),
494 PAT(0x00ff00ff),
495 PAT(0x00ffff00),
496 PAT(0x00ffffff),
497 PAT(0xff000000),
498 PAT(0xff0000ff),
499 PAT(0xff00ff00),
500 PAT(0xff00ffff),
501 PAT(0xffff0000),
502 PAT(0xffff00ff),
503 PAT(0xffffff00),
504 PAT(0xffffffff),
505};
506
507static const uint32_t dmask4[4] = {
508 PAT(0x00000000),
509 PAT(0x0000ffff),
510 PAT(0xffff0000),
511 PAT(0xffffffff),
512};
513
514#if defined(VBOX) && defined(IN_RING3)
515static uint32_t expand4[256];
516static uint16_t expand2[256];
517static uint8_t expand4to8[16];
518#endif /* VBOX && IN_RING3 */
519
520#ifndef VBOX
521VGAState *vga_state;
522int vga_io_memory;
523#endif /* !VBOX */
524
525static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
526{
527 VGAState *s = (VGAState*)opaque;
528 int val, index;
529
530 /* check port range access depending on color/monochrome mode */
531 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
532 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
533 val = 0xff;
534 Log(("VGA: following read ignored\n"));
535 } else {
536 switch(addr) {
537 case 0x3c0:
538 if (s->ar_flip_flop == 0) {
539 val = s->ar_index;
540 } else {
541 val = 0;
542 }
543 break;
544 case 0x3c1:
545 index = s->ar_index & 0x1f;
546 if (index < 21)
547 val = s->ar[index];
548 else
549 val = 0;
550 break;
551 case 0x3c2:
552 val = s->st00;
553 break;
554 case 0x3c4:
555 val = s->sr_index;
556 break;
557 case 0x3c5:
558 val = s->sr[s->sr_index];
559#ifdef DEBUG_VGA_REG
560 Log(("vga: read SR%x = 0x%02x\n", s->sr_index, val));
561#endif
562 break;
563 case 0x3c7:
564 val = s->dac_state;
565 break;
566 case 0x3c8:
567 val = s->dac_write_index;
568 break;
569 case 0x3c9:
570 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
571 if (++s->dac_sub_index == 3) {
572 s->dac_sub_index = 0;
573 s->dac_read_index++;
574 }
575 break;
576 case 0x3ca:
577 val = s->fcr;
578 break;
579 case 0x3cc:
580 val = s->msr;
581 break;
582 case 0x3ce:
583 val = s->gr_index;
584 break;
585 case 0x3cf:
586 val = s->gr[s->gr_index];
587#ifdef DEBUG_VGA_REG
588 Log(("vga: read GR%x = 0x%02x\n", s->gr_index, val));
589#endif
590 break;
591 case 0x3b4:
592 case 0x3d4:
593 val = s->cr_index;
594 break;
595 case 0x3b5:
596 case 0x3d5:
597 val = s->cr[s->cr_index];
598#ifdef DEBUG_VGA_REG
599 Log(("vga: read CR%x = 0x%02x\n", s->cr_index, val));
600#endif
601 break;
602 case 0x3ba:
603 case 0x3da:
604 /* just toggle to fool polling */
605 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
606 val = s->st01;
607 s->ar_flip_flop = 0;
608 break;
609 default:
610 val = 0x00;
611 break;
612 }
613 }
614#if defined(DEBUG_VGA)
615 Log(("VGA: read addr=0x%04x data=0x%02x\n", addr, val));
616#endif
617 return val;
618}
619
620static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
621{
622 VGAState *s = (VGAState*)opaque;
623 int index;
624
625#ifdef DEBUG_VGA
626 Log(("VGA: write addr=0x%04x data=0x%02x\n", addr, val));
627#endif
628
629 /* check port range access depending on color/monochrome mode */
630 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
631 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
632 Log(("VGA: previous write ignored\n"));
633 return;
634 }
635
636 switch(addr) {
637 case 0x3c0:
638 if (s->ar_flip_flop == 0) {
639 val &= 0x3f;
640 s->ar_index = val;
641 } else {
642 index = s->ar_index & 0x1f;
643 switch(index) {
644#ifndef VBOX
645 case 0x00 ... 0x0f:
646#else /* VBOX */
647 case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07:
648 case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f:
649#endif /* VBOX */
650 s->ar[index] = val & 0x3f;
651 break;
652 case 0x10:
653 s->ar[index] = val & ~0x10;
654 break;
655 case 0x11:
656 s->ar[index] = val;
657 break;
658 case 0x12:
659 s->ar[index] = val & ~0xc0;
660 break;
661 case 0x13:
662 s->ar[index] = val & ~0xf0;
663 break;
664 case 0x14:
665 s->ar[index] = val & ~0xf0;
666 break;
667 default:
668 break;
669 }
670 }
671 s->ar_flip_flop ^= 1;
672 break;
673 case 0x3c2:
674 s->msr = val & ~0x10;
675 break;
676 case 0x3c4:
677 s->sr_index = val & 7;
678 break;
679 case 0x3c5:
680#ifdef DEBUG_VGA_REG
681 Log(("vga: write SR%x = 0x%02x\n", s->sr_index, val));
682#endif
683 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
684 break;
685 case 0x3c7:
686 s->dac_read_index = val;
687 s->dac_sub_index = 0;
688 s->dac_state = 3;
689 break;
690 case 0x3c8:
691 s->dac_write_index = val;
692 s->dac_sub_index = 0;
693 s->dac_state = 0;
694 break;
695 case 0x3c9:
696 s->dac_cache[s->dac_sub_index] = val;
697 if (++s->dac_sub_index == 3) {
698 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
699 s->dac_sub_index = 0;
700 s->dac_write_index++;
701 }
702 break;
703 case 0x3ce:
704 s->gr_index = val & 0x0f;
705 break;
706 case 0x3cf:
707#ifdef DEBUG_VGA_REG
708 Log(("vga: write GR%x = 0x%02x\n", s->gr_index, val));
709#endif
710 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
711 break;
712 case 0x3b4:
713 case 0x3d4:
714 s->cr_index = val;
715 break;
716 case 0x3b5:
717 case 0x3d5:
718#ifdef DEBUG_VGA_REG
719 Log(("vga: write CR%x = 0x%02x\n", s->cr_index, val));
720#endif
721 /* handle CR0-7 protection */
722 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
723 /* can always write bit 4 of CR7 */
724 if (s->cr_index == 7)
725 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
726 return;
727 }
728 switch(s->cr_index) {
729 case 0x01: /* horizontal display end */
730 case 0x07:
731 case 0x09:
732 case 0x0c:
733 case 0x0d:
734 case 0x12: /* veritcal display end */
735 s->cr[s->cr_index] = val;
736 break;
737
738 default:
739 s->cr[s->cr_index] = val;
740 break;
741 }
742 break;
743 case 0x3ba:
744 case 0x3da:
745 s->fcr = val & 0x10;
746 break;
747 }
748}
749
750#ifdef CONFIG_BOCHS_VBE
751static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
752{
753 VGAState *s = (VGAState*)opaque;
754 uint32_t val;
755 val = s->vbe_index;
756 return val;
757}
758
759static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
760{
761 VGAState *s = (VGAState*)opaque;
762 uint32_t val;
763
764 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
765 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
766 switch(s->vbe_index) {
767 /* XXX: do not hardcode ? */
768 case VBE_DISPI_INDEX_XRES:
769 val = VBE_DISPI_MAX_XRES;
770 break;
771 case VBE_DISPI_INDEX_YRES:
772 val = VBE_DISPI_MAX_YRES;
773 break;
774 case VBE_DISPI_INDEX_BPP:
775 val = VBE_DISPI_MAX_BPP;
776 break;
777 default:
778 val = s->vbe_regs[s->vbe_index];
779 break;
780 }
781 } else if (s->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO) {
782 /* Reading from the port means that the old additions are requesting the number of monitors. */
783 val = 1;
784 } else {
785 val = s->vbe_regs[s->vbe_index];
786 }
787 } else {
788 val = 0;
789 }
790#ifdef DEBUG_BOCHS_VBE
791 Log(("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val));
792#endif
793 return val;
794}
795
796static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
797{
798 VGAState *s = (VGAState*)opaque;
799 s->vbe_index = val;
800}
801
802static int vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
803{
804 VGAState *s = (VGAState*)opaque;
805
806 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
807#ifdef DEBUG_BOCHS_VBE
808 Log(("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val));
809#endif
810 switch(s->vbe_index) {
811 case VBE_DISPI_INDEX_ID:
812 if (val == VBE_DISPI_ID0 ||
813 val == VBE_DISPI_ID1 ||
814 val == VBE_DISPI_ID2 ||
815 val == VBE_DISPI_ID3 ||
816 val == VBE_DISPI_ID4) {
817 s->vbe_regs[s->vbe_index] = val;
818 }
819#ifdef VBOX
820 if (val == VBE_DISPI_ID_VBOX_VIDEO) {
821 s->vbe_regs[s->vbe_index] = val;
822 }
823#endif /* VBOX */
824 break;
825 case VBE_DISPI_INDEX_XRES:
826 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
827 s->vbe_regs[s->vbe_index] = val;
828#ifdef KEEP_SCAN_LINE_LENGTH
829 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
830 s->vbe_line_offset = val >> 1;
831 else
832 s->vbe_line_offset = val * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
833 /* XXX: support weird bochs semantics ? */
834 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
835 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
836 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
837 s->vbe_start_addr = 0;
838#endif /* KEEP_SCAN_LINE_LENGTH defined */
839 }
840 break;
841 case VBE_DISPI_INDEX_YRES:
842 if (val <= VBE_DISPI_MAX_YRES) {
843 s->vbe_regs[s->vbe_index] = val;
844#ifdef KEEP_SCAN_LINE_LENGTH
845 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = val;
846 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
847 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
848 s->vbe_start_addr = 0;
849#endif /* KEEP_SCAN_LINE_LENGTH defined */
850 }
851 break;
852 case VBE_DISPI_INDEX_BPP:
853 if (val == 0)
854 val = 8;
855 if (val == 4 || val == 8 || val == 15 ||
856 val == 16 || val == 24 || val == 32) {
857 s->vbe_regs[s->vbe_index] = val;
858#ifdef KEEP_SCAN_LINE_LENGTH
859 if (val == 4)
860 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
861 else
862 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((val + 7) >> 3);
863 /* XXX: support weird bochs semantics ? */
864 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = s->vbe_line_offset;
865 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
866 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
867 s->vbe_start_addr = 0;
868#endif /* KEEP_SCAN_LINE_LENGTH defined */
869 }
870 break;
871 case VBE_DISPI_INDEX_BANK:
872 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
873 val &= (s->vbe_bank_mask >> 2);
874 } else {
875 val &= s->vbe_bank_mask;
876 }
877 val &= s->vbe_bank_mask;
878 s->vbe_regs[s->vbe_index] = val;
879 s->bank_offset = (val << 16);
880 break;
881 case VBE_DISPI_INDEX_ENABLE:
882#ifndef IN_RING3
883 return VINF_IOM_HC_IOPORT_WRITE;
884#else
885 if ((val & VBE_DISPI_ENABLED) &&
886 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
887 int h, shift_control;
888#ifdef VBOX
889 /* Check the values before we screw up with a resolution which is too big or small. */
890 size_t cb = s->vbe_regs[VBE_DISPI_INDEX_XRES];
891 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
892 cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
893 else
894 cb = s->vbe_regs[VBE_DISPI_INDEX_XRES] * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
895 cb *= s->vbe_regs[VBE_DISPI_INDEX_YRES];
896#ifndef KEEP_SCAN_LINE_LENGTH
897 if ( !s->vbe_regs[VBE_DISPI_INDEX_XRES]
898 || !s->vbe_regs[VBE_DISPI_INDEX_YRES]
899 || cb > s->vram_size)
900 {
901 AssertMsgFailed(("XRES=%d YRES=%d cb=%d vram_size=%d\n",
902 s->vbe_regs[VBE_DISPI_INDEX_XRES], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
903 return VINF_SUCCESS; /* Note: silent failure like before */
904 }
905#else /* KEEP_SCAN_LINE_LENGTH defined */
906 if ( !s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH]
907 || !s->vbe_regs[VBE_DISPI_INDEX_YRES]
908 || cb > s->vram_size)
909 {
910 AssertMsgFailed(("VIRT WIDTH=%d YRES=%d cb=%d vram_size=%d\n",
911 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH], s->vbe_regs[VBE_DISPI_INDEX_YRES], cb, s->vram_size));
912 return VINF_SUCCESS; /* Note: silent failure like before */
913 }
914#endif /* KEEP_SCAN_LINE_LENGTH defined */
915#endif /* VBOX */
916
917#ifndef KEEP_SCAN_LINE_LENGTH
918 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
919 s->vbe_regs[VBE_DISPI_INDEX_XRES];
920 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
921 s->vbe_regs[VBE_DISPI_INDEX_YRES];
922 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
923 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
924
925 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
926 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
927 else
928 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
929 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
930 s->vbe_start_addr = 0;
931#endif /* KEEP_SCAN_LINE_LENGTH not defined */
932
933 /* clear the screen (should be done in BIOS) */
934 if (!(val & VBE_DISPI_NOCLEARMEM)) {
935#ifndef VBOX
936 memset(s->vram_ptr, 0,
937 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
938#else /* VBOX */
939 memset(CTXSUFF(s->vram_ptr), 0,
940 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
941#endif /* VBOX */
942 }
943
944 /* we initialize the VGA graphic mode (should be done
945 in BIOS) */
946 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
947 s->cr[0x17] |= 3; /* no CGA modes */
948 s->cr[0x13] = s->vbe_line_offset >> 3;
949 /* width */
950 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
951 /* height (only meaningful if < 1024) */
952 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
953 s->cr[0x12] = h;
954 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
955 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
956 /* line compare to 1023 */
957 s->cr[0x18] = 0xff;
958 s->cr[0x07] |= 0x10;
959 s->cr[0x09] |= 0x40;
960
961 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
962 shift_control = 0;
963 s->sr[0x01] &= ~8; /* no double line */
964 } else {
965 shift_control = 2;
966 s->sr[4] |= 0x08; /* set chain 4 mode */
967 s->sr[2] |= 0x0f; /* activate all planes */
968 }
969 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
970 s->cr[0x09] &= ~0x9f; /* no double scan */
971#ifdef VBOX
972 /* sunlover 30.05.2007
973 * The ar_index remains with bit 0x20 cleared after a switch from fullscreen
974 * DOS mode on Windows XP guest. That leads to GMODE_BLANK in vga_update_display.
975 * But the VBE mode is graphics, so not a blank anymore.
976 */
977 s->ar_index |= 0x20;
978#endif /* VBOX */
979 } else {
980 /* XXX: the bios should do that */
981#ifdef VBOX
982 /* sunlover 21.12.2006
983 * Here is probably more to reset. When this was executed in GC
984 * then the *update* functions could not detect a mode change.
985 * Or may be these update function should take the s->vbe_regs[s->vbe_index]
986 * into account when detecting a mode change.
987 *
988 * The 'mode reset not detected' problem is now fixed by executing the
989 * VBE_DISPI_INDEX_ENABLE case always in RING3 in order to call the
990 * LFBChange callback.
991 */
992#endif /* VBOX */
993 s->bank_offset = 0;
994 }
995 s->vbe_regs[s->vbe_index] = val;
996 /*
997 * LFB video mode is either disabled or changed. This notification
998 * is used by the display to disable VBVA.
999 */
1000 s->pDrv->pfnLFBModeChange(s->pDrv, (val & VBE_DISPI_ENABLED) != 0);
1001 break;
1002#endif /* IN_RING3 */
1003 case VBE_DISPI_INDEX_VIRT_WIDTH:
1004 {
1005 int w, h, line_offset;
1006
1007 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
1008 return VINF_SUCCESS;
1009 w = val;
1010 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
1011 line_offset = w >> 1;
1012 else
1013 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
1014 h = s->vram_size / line_offset;
1015 /* XXX: support weird bochs semantics ? */
1016 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
1017 return VINF_SUCCESS;
1018 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
1019 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
1020 s->vbe_line_offset = line_offset;
1021 }
1022 break;
1023 case VBE_DISPI_INDEX_X_OFFSET:
1024 case VBE_DISPI_INDEX_Y_OFFSET:
1025 {
1026 int x;
1027 s->vbe_regs[s->vbe_index] = val;
1028 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
1029 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
1030 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
1031 s->vbe_start_addr += x >> 1;
1032 else
1033 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
1034 s->vbe_start_addr >>= 2;
1035 }
1036 break;
1037 case VBE_DISPI_INDEX_VBOX_VIDEO:
1038#ifdef VBOX
1039#ifndef IN_RING3
1040 return VINF_IOM_HC_IOPORT_WRITE;
1041#else
1042 /* Changes in the VGA device are minimal. The device is bypassed. The driver does all work. */
1043 if (val == VBOX_VIDEO_DISABLE_ADAPTER_MEMORY)
1044 {
1045 s->pDrv->pfnProcessAdapterData(s->pDrv, NULL, 0);
1046 }
1047 else if (val == VBOX_VIDEO_INTERPRET_ADAPTER_MEMORY)
1048 {
1049 s->pDrv->pfnProcessAdapterData(s->pDrv, s->CTXSUFF(vram_ptr), s->vram_size);
1050 }
1051 else if ((val & 0xFFFF0000) == VBOX_VIDEO_INTERPRET_DISPLAY_MEMORY_BASE)
1052 {
1053 s->pDrv->pfnProcessDisplayData(s->pDrv, s->CTXSUFF(vram_ptr), val & 0xFFFF);
1054 }
1055#endif /* IN_RING3 */
1056#endif /* VBOX */
1057 break;
1058 default:
1059 break;
1060 }
1061 }
1062 return VINF_SUCCESS;
1063}
1064#endif
1065
1066/* called for accesses between 0xa0000 and 0xc0000 */
1067#ifdef VBOX
1068static
1069#endif /* VBOX */
1070uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
1071{
1072 VGAState *s = (VGAState*)opaque;
1073 int memory_map_mode, plane;
1074 uint32_t ret;
1075
1076#ifdef DEBUG_VGA_MEM
1077 Log(("vga: read [0x%x] -> ", addr));
1078#endif
1079 /* convert to VGA memory offset */
1080 memory_map_mode = (s->gr[6] >> 2) & 3;
1081 addr &= 0x1ffff;
1082 switch(memory_map_mode) {
1083 case 0:
1084 break;
1085 case 1:
1086 if (addr >= 0x10000)
1087 return 0xff;
1088 addr += s->bank_offset;
1089 break;
1090 case 2:
1091 addr -= 0x10000;
1092 if (addr >= 0x8000)
1093 return 0xff;
1094 break;
1095 default:
1096 case 3:
1097 addr -= 0x18000;
1098 if (addr >= 0x8000)
1099 return 0xff;
1100 break;
1101 }
1102
1103#ifdef IN_GC
1104 if (addr >= VGA_MAPPING_SIZE)
1105 return VINF_IOM_HC_MMIO_WRITE;
1106#endif
1107
1108 if (s->sr[4] & 0x08) {
1109 /* chain 4 mode : simplest access */
1110#ifndef VBOX
1111 ret = s->vram_ptr[addr];
1112#else /* VBOX */
1113 ret = s->CTXSUFF(vram_ptr)[addr];
1114#endif /* VBOX */
1115 } else if (!(s->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1116 /* odd/even mode (aka text mode mapping) */
1117 plane = (s->gr[4] & 2) | (addr & 1);
1118#ifndef VBOX
1119 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
1120#else /* VBOX */
1121 /* See the comment for a similar line in vga_mem_writeb. */
1122 ret = s->CTXSUFF(vram_ptr)[((addr & ~1) << 2) | plane];
1123#endif /* VBOX */
1124 } else {
1125 /* standard VGA latched access */
1126#ifndef VBOX
1127 s->latch = ((uint32_t *)s->vram_ptr)[addr];
1128#else /* VBOX && IN_GC */
1129 s->latch = ((uint32_t *)s->CTXSUFF(vram_ptr))[addr];
1130#endif /* VBOX && IN_GC */
1131
1132 if (!(s->gr[5] & 0x08)) {
1133 /* read mode 0 */
1134 plane = s->gr[4];
1135 ret = GET_PLANE(s->latch, plane);
1136 } else {
1137 /* read mode 1 */
1138 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
1139 ret |= ret >> 16;
1140 ret |= ret >> 8;
1141 ret = (~ret) & 0xff;
1142 }
1143 }
1144#ifdef DEBUG_VGA_MEM
1145 Log((" 0x%02x\n", ret));
1146#endif
1147 return ret;
1148}
1149
1150#ifndef VBOX
1151static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
1152{
1153 uint32_t v;
1154#ifdef TARGET_WORDS_BIGENDIAN
1155 v = vga_mem_readb(opaque, addr) << 8;
1156 v |= vga_mem_readb(opaque, addr + 1);
1157#else
1158 v = vga_mem_readb(opaque, addr);
1159 v |= vga_mem_readb(opaque, addr + 1) << 8;
1160#endif
1161 return v;
1162}
1163
1164static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
1165{
1166 uint32_t v;
1167#ifdef TARGET_WORDS_BIGENDIAN
1168 v = vga_mem_readb(opaque, addr) << 24;
1169 v |= vga_mem_readb(opaque, addr + 1) << 16;
1170 v |= vga_mem_readb(opaque, addr + 2) << 8;
1171 v |= vga_mem_readb(opaque, addr + 3);
1172#else
1173 v = vga_mem_readb(opaque, addr);
1174 v |= vga_mem_readb(opaque, addr + 1) << 8;
1175 v |= vga_mem_readb(opaque, addr + 2) << 16;
1176 v |= vga_mem_readb(opaque, addr + 3) << 24;
1177#endif
1178 return v;
1179}
1180#endif /* !VBOX */
1181
1182/* called for accesses between 0xa0000 and 0xc0000 */
1183#ifdef VBOX
1184static
1185#endif /* VBOX */
1186int vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1187{
1188 VGAState *s = (VGAState*)opaque;
1189 int memory_map_mode, plane, write_mode, b, func_select, mask;
1190 uint32_t write_mask, bit_mask, set_mask;
1191
1192#ifdef DEBUG_VGA_MEM
1193 Log(("vga: [0x%x] = 0x%02x\n", addr, val));
1194#endif
1195 /* convert to VGA memory offset */
1196 memory_map_mode = (s->gr[6] >> 2) & 3;
1197 addr &= 0x1ffff;
1198 switch(memory_map_mode) {
1199 case 0:
1200 break;
1201 case 1:
1202 if (addr >= 0x10000)
1203 return VINF_SUCCESS;
1204 addr += s->bank_offset;
1205 break;
1206 case 2:
1207 addr -= 0x10000;
1208 if (addr >= 0x8000)
1209 return VINF_SUCCESS;
1210 break;
1211 default:
1212 case 3:
1213 addr -= 0x18000;
1214 if (addr >= 0x8000)
1215 return VINF_SUCCESS;
1216 break;
1217 }
1218
1219 if (s->sr[4] & 0x08) {
1220 /* chain 4 mode : simplest access */
1221 plane = addr & 3;
1222 mask = (1 << plane);
1223 if (s->sr[2] & mask) {
1224#ifndef VBOX
1225 s->vram_ptr[addr] = val;
1226#else /* VBOX */
1227#ifdef IN_GC
1228 if (addr >= VGA_MAPPING_SIZE)
1229 return VINF_IOM_HC_MMIO_WRITE;
1230#else
1231 if (addr >= s->vram_size)
1232 {
1233 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1234 addr, s->bank_offset, memory_map_mode));
1235 return VINF_SUCCESS;
1236 }
1237#endif
1238 s->CTXSUFF(vram_ptr)[addr] = val;
1239#endif /* VBOX */
1240#ifdef DEBUG_VGA_MEM
1241 Log(("vga: chain4: [0x%x]\n", addr));
1242#endif
1243 s->plane_updated |= mask; /* only used to detect font change */
1244#ifndef VBOX
1245 cpu_physical_memory_set_dirty(s->vram_offset + addr);
1246#else /* VBOX */
1247 vga_set_dirty(s, addr);
1248#endif /* VBOX */
1249 }
1250 } else if (!(s->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
1251 /* odd/even mode (aka text mode mapping) */
1252 plane = (s->gr[4] & 2) | (addr & 1);
1253 mask = (1 << plane);
1254 if (s->sr[2] & mask) {
1255#ifndef VBOX
1256 addr = ((addr & ~1) << 1) | plane;
1257#else
1258 /* 'addr' is offset in a plane, bit 0 selects the plane.
1259 * Mask the bit 0, convert plane index to vram offset,
1260 * that is multiply by the number of planes,
1261 * and select the plane byte in the vram offset.
1262 */
1263 addr = ((addr & ~1) << 2) | plane;
1264#endif /* VBOX */
1265#ifndef VBOX
1266 s->vram_ptr[addr] = val;
1267#else /* VBOX */
1268#ifdef IN_GC
1269 if (addr >= VGA_MAPPING_SIZE)
1270 return VINF_IOM_HC_MMIO_WRITE;
1271#else
1272 if (addr >= s->vram_size)
1273 {
1274 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1275 addr, s->bank_offset, memory_map_mode));
1276 return VINF_SUCCESS;
1277 }
1278#endif
1279 s->CTXSUFF(vram_ptr)[addr] = val;
1280#endif /* VBOX */
1281#ifdef DEBUG_VGA_MEM
1282 Log(("vga: odd/even: [0x%x]\n", addr));
1283#endif
1284 s->plane_updated |= mask; /* only used to detect font change */
1285#ifndef VBOX
1286 cpu_physical_memory_set_dirty(s->vram_offset + addr);
1287#else /* VBOX */
1288 vga_set_dirty(s, addr);
1289#endif /* VBOX */
1290 }
1291 } else {
1292#ifdef IN_GC
1293 if (addr * 4 >= VGA_MAPPING_SIZE)
1294 return VINF_IOM_HC_MMIO_WRITE;
1295#else
1296 if (addr * 4 >= s->vram_size)
1297 {
1298 AssertMsgFailed(("addr=%VGp - this needs to be done in HC! bank_offset=%08x memory_map_mode=%d\n",
1299 addr * 4, s->bank_offset, memory_map_mode));
1300 return VINF_SUCCESS;
1301 }
1302#endif
1303
1304 /* standard VGA latched access */
1305 write_mode = s->gr[5] & 3;
1306 switch(write_mode) {
1307 default:
1308 case 0:
1309 /* rotate */
1310 b = s->gr[3] & 7;
1311 val = ((val >> b) | (val << (8 - b))) & 0xff;
1312 val |= val << 8;
1313 val |= val << 16;
1314
1315 /* apply set/reset mask */
1316 set_mask = mask16[s->gr[1]];
1317 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
1318 bit_mask = s->gr[8];
1319 break;
1320 case 1:
1321 val = s->latch;
1322 goto do_write;
1323 case 2:
1324 val = mask16[val & 0x0f];
1325 bit_mask = s->gr[8];
1326 break;
1327 case 3:
1328 /* rotate */
1329 b = s->gr[3] & 7;
1330 val = (val >> b) | (val << (8 - b));
1331
1332 bit_mask = s->gr[8] & val;
1333 val = mask16[s->gr[0]];
1334 break;
1335 }
1336
1337 /* apply logical operation */
1338 func_select = s->gr[3] >> 3;
1339 switch(func_select) {
1340 case 0:
1341 default:
1342 /* nothing to do */
1343 break;
1344 case 1:
1345 /* and */
1346 val &= s->latch;
1347 break;
1348 case 2:
1349 /* or */
1350 val |= s->latch;
1351 break;
1352 case 3:
1353 /* xor */
1354 val ^= s->latch;
1355 break;
1356 }
1357
1358 /* apply bit mask */
1359 bit_mask |= bit_mask << 8;
1360 bit_mask |= bit_mask << 16;
1361 val = (val & bit_mask) | (s->latch & ~bit_mask);
1362
1363 do_write:
1364 /* mask data according to sr[2] */
1365 mask = s->sr[2];
1366 s->plane_updated |= mask; /* only used to detect font change */
1367 write_mask = mask16[mask];
1368#ifndef VBOX
1369 ((uint32_t *)s->vram_ptr)[addr] =
1370 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
1371 (val & write_mask);
1372#else /* VBOX */
1373 ((uint32_t *)s->CTXSUFF(vram_ptr))[addr] =
1374 (((uint32_t *)s->CTXSUFF(vram_ptr))[addr] & ~write_mask) |
1375 (val & write_mask);
1376#endif /* VBOX */
1377#ifdef DEBUG_VGA_MEM
1378 Log(("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
1379 addr * 4, write_mask, val));
1380#endif
1381#ifndef VBOX
1382 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
1383#else /* VBOX */
1384 vga_set_dirty(s, (addr << 2));
1385#endif /* VBOX */
1386 }
1387
1388 return VINF_SUCCESS;
1389}
1390
1391#ifndef VBOX
1392static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1393{
1394#ifdef TARGET_WORDS_BIGENDIAN
1395 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1396 vga_mem_writeb(opaque, addr + 1, val & 0xff);
1397#else
1398 vga_mem_writeb(opaque, addr, val & 0xff);
1399 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1400#endif
1401}
1402
1403static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1404{
1405#ifdef TARGET_WORDS_BIGENDIAN
1406 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1407 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1408 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1409 vga_mem_writeb(opaque, addr + 3, val & 0xff);
1410#else
1411 vga_mem_writeb(opaque, addr, val & 0xff);
1412 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1413 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1414 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1415#endif
1416}
1417#endif /* !VBOX */
1418
1419#if !defined(VBOX) || defined(IN_RING3)
1420typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
1421 const uint8_t *font_ptr, int h,
1422 uint32_t fgcol, uint32_t bgcol);
1423typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
1424 const uint8_t *font_ptr, int h,
1425 uint32_t fgcol, uint32_t bgcol, int dup9);
1426typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
1427 const uint8_t *s, int width);
1428
1429static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
1430{
1431 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
1432}
1433
1434static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
1435{
1436 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
1437}
1438
1439static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
1440{
1441 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
1442}
1443
1444static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
1445{
1446 return (r << 16) | (g << 8) | b;
1447}
1448
1449#define DEPTH 8
1450#include "DevVGATmpl.h"
1451
1452#define DEPTH 15
1453#include "DevVGATmpl.h"
1454
1455#define DEPTH 16
1456#include "DevVGATmpl.h"
1457
1458#define DEPTH 32
1459#include "DevVGATmpl.h"
1460
1461static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1462{
1463 unsigned int col;
1464 col = rgb_to_pixel8(r, g, b);
1465 col |= col << 8;
1466 col |= col << 16;
1467 return col;
1468}
1469
1470static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1471{
1472 unsigned int col;
1473 col = rgb_to_pixel15(r, g, b);
1474 col |= col << 16;
1475 return col;
1476}
1477
1478static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1479{
1480 unsigned int col;
1481 col = rgb_to_pixel16(r, g, b);
1482 col |= col << 16;
1483 return col;
1484}
1485
1486static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1487{
1488 unsigned int col;
1489 col = rgb_to_pixel32(r, g, b);
1490 return col;
1491}
1492
1493/* return true if the palette was modified */
1494static int update_palette16(VGAState *s)
1495{
1496 int full_update, i;
1497 uint32_t v, col, *palette;
1498
1499 full_update = 0;
1500 palette = s->last_palette;
1501 for(i = 0; i < 16; i++) {
1502 v = s->ar[i];
1503 if (s->ar[0x10] & 0x80)
1504 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1505 else
1506 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1507 v = v * 3;
1508 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1509 c6_to_8(s->palette[v + 1]),
1510 c6_to_8(s->palette[v + 2]));
1511 if (col != palette[i]) {
1512 full_update = 1;
1513 palette[i] = col;
1514 }
1515 }
1516 return full_update;
1517}
1518
1519/* return true if the palette was modified */
1520static int update_palette256(VGAState *s)
1521{
1522 int full_update, i;
1523 uint32_t v, col, *palette;
1524 int wide_dac;
1525
1526 full_update = 0;
1527 palette = s->last_palette;
1528 v = 0;
1529 wide_dac = (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & (VBE_DISPI_ENABLED | VBE_DISPI_8BIT_DAC))
1530 == (VBE_DISPI_ENABLED | VBE_DISPI_8BIT_DAC);
1531 for(i = 0; i < 256; i++) {
1532 if (wide_dac)
1533 col = s->rgb_to_pixel(s->palette[v],
1534 s->palette[v + 1],
1535 s->palette[v + 2]);
1536 else
1537 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1538 c6_to_8(s->palette[v + 1]),
1539 c6_to_8(s->palette[v + 2]));
1540 if (col != palette[i]) {
1541 full_update = 1;
1542 palette[i] = col;
1543 }
1544 v += 3;
1545 }
1546 return full_update;
1547}
1548
1549static void vga_get_offsets(VGAState *s,
1550 uint32_t *pline_offset,
1551 uint32_t *pstart_addr,
1552 uint32_t *pline_compare)
1553{
1554 uint32_t start_addr, line_offset, line_compare;
1555#ifdef CONFIG_BOCHS_VBE
1556 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1557 line_offset = s->vbe_line_offset;
1558 start_addr = s->vbe_start_addr;
1559 line_compare = 65535;
1560 } else
1561#endif
1562 {
1563 /* compute line_offset in bytes */
1564 line_offset = s->cr[0x13];
1565 line_offset <<= 3;
1566#ifdef VBOX
1567 if (!(s->cr[0x14] & 0x40) && !(s->cr[0x17] & 0x40))
1568 {
1569 /* Word mode. Used for odd/even modes. */
1570 line_offset *= 2;
1571 }
1572#endif /* VBOX */
1573
1574 /* starting address */
1575 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1576
1577 /* line compare */
1578 line_compare = s->cr[0x18] |
1579 ((s->cr[0x07] & 0x10) << 4) |
1580 ((s->cr[0x09] & 0x40) << 3);
1581 }
1582 *pline_offset = line_offset;
1583 *pstart_addr = start_addr;
1584 *pline_compare = line_compare;
1585}
1586
1587/* update start_addr and line_offset. Return TRUE if modified */
1588static int update_basic_params(VGAState *s)
1589{
1590 int full_update;
1591 uint32_t start_addr, line_offset, line_compare;
1592
1593 full_update = 0;
1594
1595 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1596
1597 if (line_offset != s->line_offset ||
1598 start_addr != s->start_addr ||
1599 line_compare != s->line_compare) {
1600 s->line_offset = line_offset;
1601 s->start_addr = start_addr;
1602 s->line_compare = line_compare;
1603 full_update = 1;
1604 }
1605 return full_update;
1606}
1607
1608static inline int get_depth_index(int depth)
1609{
1610 switch(depth) {
1611 default:
1612 case 8:
1613 return 0;
1614 case 15:
1615 return 1;
1616 case 16:
1617 return 2;
1618 case 32:
1619 return 3;
1620 }
1621}
1622
1623static vga_draw_glyph8_func *vga_draw_glyph8_table[4] = {
1624 vga_draw_glyph8_8,
1625 vga_draw_glyph8_16,
1626 vga_draw_glyph8_16,
1627 vga_draw_glyph8_32,
1628};
1629
1630static vga_draw_glyph8_func *vga_draw_glyph16_table[4] = {
1631 vga_draw_glyph16_8,
1632 vga_draw_glyph16_16,
1633 vga_draw_glyph16_16,
1634 vga_draw_glyph16_32,
1635};
1636
1637static vga_draw_glyph9_func *vga_draw_glyph9_table[4] = {
1638 vga_draw_glyph9_8,
1639 vga_draw_glyph9_16,
1640 vga_draw_glyph9_16,
1641 vga_draw_glyph9_32,
1642};
1643
1644static const uint8_t cursor_glyph[32 * 4] = {
1645 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1646 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1647 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1648 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1649 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1650 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1651 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1652 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1653 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1654 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1655 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1656 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1657 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1658 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1659 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1660 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1661};
1662
1663/*
1664 * Text mode update
1665 * Missing:
1666 * - double scan
1667 * - double width
1668 * - underline
1669 * - flashing
1670 */
1671#ifndef VBOX
1672static void vga_draw_text(VGAState *s, int full_update)
1673#else
1674static int vga_draw_text(VGAState *s, int full_update)
1675#endif /* !VBOX */
1676{
1677 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1678 int cx_min, cx_max, linesize, x_incr;
1679 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1680 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1681 const uint8_t *font_ptr, *font_base[2];
1682 int dup9, line_offset, depth_index;
1683 uint32_t *palette;
1684 uint32_t *ch_attr_ptr;
1685 vga_draw_glyph8_func *vga_draw_glyph8;
1686 vga_draw_glyph9_func *vga_draw_glyph9;
1687
1688 full_update |= update_palette16(s);
1689 palette = s->last_palette;
1690
1691 /* compute font data address (in plane 2) */
1692 v = s->sr[3];
1693 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1694 if (offset != s->font_offsets[0]) {
1695 s->font_offsets[0] = offset;
1696 full_update = 1;
1697 }
1698#ifndef VBOX
1699 font_base[0] = s->vram_ptr + offset;
1700#else /* VBOX */
1701 font_base[0] = s->CTXSUFF(vram_ptr) + offset;
1702#endif /* VBOX */
1703
1704 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1705#ifndef VBOX
1706 font_base[1] = s->vram_ptr + offset;
1707#else /* VBOX */
1708 font_base[1] = s->CTXSUFF(vram_ptr) + offset;
1709#endif /* VBOX */
1710 if (offset != s->font_offsets[1]) {
1711 s->font_offsets[1] = offset;
1712 full_update = 1;
1713 }
1714 if (s->plane_updated & (1 << 2)) {
1715 /* if the plane 2 was modified since the last display, it
1716 indicates the font may have been modified */
1717 s->plane_updated = 0;
1718 full_update = 1;
1719 }
1720 full_update |= update_basic_params(s);
1721
1722 line_offset = s->line_offset;
1723#ifndef VBOX
1724 s1 = s->vram_ptr + (s->start_addr * 4);
1725#else /* VBOX */
1726 s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 8);
1727#endif /* VBOX */
1728
1729 /* total width & height */
1730 cheight = (s->cr[9] & 0x1f) + 1;
1731 cw = 8;
1732 if (!(s->sr[1] & 0x01))
1733 cw = 9;
1734 if (s->sr[1] & 0x08)
1735 cw = 16; /* NOTE: no 18 pixel wide */
1736#ifndef VBOX
1737 x_incr = cw * ((s->ds->depth + 7) >> 3);
1738#else /* VBOX */
1739 x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
1740#endif /* VBOX */
1741 width = (s->cr[0x01] + 1);
1742 if (s->cr[0x06] == 100) {
1743 /* ugly hack for CGA 160x100x16 - explain me the logic */
1744 height = 100;
1745 } else {
1746 height = s->cr[0x12] |
1747 ((s->cr[0x07] & 0x02) << 7) |
1748 ((s->cr[0x07] & 0x40) << 3);
1749 height = (height + 1) / cheight;
1750 }
1751 if ((height * width) > CH_ATTR_SIZE) {
1752 /* better than nothing: exit if transient size is too big */
1753#ifndef VBOX
1754 return;
1755#else
1756 return VINF_SUCCESS;
1757#endif /* VBOX */
1758 }
1759
1760 if (width != (int)s->last_width || height != (int)s->last_height ||
1761 cw != s->last_cw || cheight != s->last_ch) {
1762 s->last_scr_width = width * cw;
1763 s->last_scr_height = height * cheight;
1764#ifndef VBOX
1765 dpy_resize(s->ds, s->last_scr_width, s->last_scr_height);
1766 s->last_width = width;
1767 s->last_height = height;
1768 s->last_ch = cheight;
1769 s->last_cw = cw;
1770 full_update = 1;
1771#else /* VBOX */
1772 /* For text modes the direct use of guest VRAM is not implemented, so bpp and cbLine are 0 here. */
1773 int rc = s->pDrv->pfnResize(s->pDrv, 0, NULL, 0, s->last_scr_width, s->last_scr_height);
1774 s->last_width = width;
1775 s->last_height = height;
1776 s->last_ch = cheight;
1777 s->last_cw = cw;
1778 full_update = 1;
1779 if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
1780 return rc;
1781 AssertRC(rc);
1782#endif /* VBOX */
1783 }
1784 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1785 if (cursor_offset != s->cursor_offset ||
1786 s->cr[0xa] != s->cursor_start ||
1787 s->cr[0xb] != s->cursor_end) {
1788 /* if the cursor position changed, we update the old and new
1789 chars */
1790 if (s->cursor_offset < CH_ATTR_SIZE)
1791 s->last_ch_attr[s->cursor_offset] = ~0;
1792 if (cursor_offset < CH_ATTR_SIZE)
1793 s->last_ch_attr[cursor_offset] = ~0;
1794 s->cursor_offset = cursor_offset;
1795 s->cursor_start = s->cr[0xa];
1796 s->cursor_end = s->cr[0xb];
1797 }
1798#ifndef VBOX
1799 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1800
1801 depth_index = get_depth_index(s->ds->depth);
1802#else /* VBOX */
1803 cursor_ptr = s->CTXSUFF(vram_ptr) + (s->start_addr + cursor_offset) * 8;
1804 depth_index = get_depth_index(s->pDrv->cBits);
1805#endif /* VBOX */
1806 if (cw == 16)
1807 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1808 else
1809 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1810 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1811
1812#ifndef VBOX
1813 dest = s->ds->data;
1814 linesize = s->ds->linesize;
1815#else /* VBOX */
1816 dest = s->pDrv->pu8Data;
1817 linesize = s->pDrv->cbScanline;
1818#endif /* VBOX */
1819 ch_attr_ptr = s->last_ch_attr;
1820
1821 for(cy = 0; cy < height; cy++) {
1822 d1 = dest;
1823 src = s1;
1824 cx_min = width;
1825 cx_max = -1;
1826 for(cx = 0; cx < width; cx++) {
1827 ch_attr = *(uint16_t *)src;
1828 if (full_update || ch_attr != (int)*ch_attr_ptr) {
1829 if (cx < cx_min)
1830 cx_min = cx;
1831 if (cx > cx_max)
1832 cx_max = cx;
1833 *ch_attr_ptr = ch_attr;
1834#ifdef WORDS_BIGENDIAN
1835 ch = ch_attr >> 8;
1836 cattr = ch_attr & 0xff;
1837#else
1838 ch = ch_attr & 0xff;
1839 cattr = ch_attr >> 8;
1840#endif
1841 font_ptr = font_base[(cattr >> 3) & 1];
1842 font_ptr += 32 * 4 * ch;
1843 bgcol = palette[cattr >> 4];
1844 fgcol = palette[cattr & 0x0f];
1845 if (cw != 9) {
1846 vga_draw_glyph8(d1, linesize,
1847 font_ptr, cheight, fgcol, bgcol);
1848 } else {
1849 dup9 = 0;
1850 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1851 dup9 = 1;
1852 vga_draw_glyph9(d1, linesize,
1853 font_ptr, cheight, fgcol, bgcol, dup9);
1854 }
1855 if (src == cursor_ptr &&
1856 !(s->cr[0x0a] & 0x20)) {
1857 int line_start, line_last, h;
1858 /* draw the cursor */
1859 line_start = s->cr[0x0a] & 0x1f;
1860 line_last = s->cr[0x0b] & 0x1f;
1861 /* XXX: check that */
1862 if (line_last > cheight - 1)
1863 line_last = cheight - 1;
1864 if (line_last >= line_start && line_start < cheight) {
1865 h = line_last - line_start + 1;
1866 d = d1 + linesize * line_start;
1867 if (cw != 9) {
1868 vga_draw_glyph8(d, linesize,
1869 cursor_glyph, h, fgcol, bgcol);
1870 } else {
1871 vga_draw_glyph9(d, linesize,
1872 cursor_glyph, h, fgcol, bgcol, 1);
1873 }
1874 }
1875 }
1876 }
1877 d1 += x_incr;
1878#ifndef VBOX
1879 src += 4;
1880#else
1881 src += 8; /* Every second byte of a plane is used in text mode. */
1882#endif
1883
1884 ch_attr_ptr++;
1885 }
1886#ifndef VBOX
1887 if (cx_max != -1) {
1888 dpy_update(s->ds, cx_min * cw, cy * cheight,
1889 (cx_max - cx_min + 1) * cw, cheight);
1890 }
1891#else
1892 if (cx_max != -1)
1893 s->pDrv->pfnUpdateRect(s->pDrv, cx_min * cw, cy * cheight, (cx_max - cx_min + 1) * cw, cheight);
1894#endif
1895 dest += linesize * cheight;
1896 s1 += line_offset;
1897 }
1898#ifdef VBOX
1899 return VINF_SUCCESS;
1900#endif /* VBOX */
1901}
1902
1903enum {
1904 VGA_DRAW_LINE2,
1905 VGA_DRAW_LINE2D2,
1906 VGA_DRAW_LINE4,
1907 VGA_DRAW_LINE4D2,
1908 VGA_DRAW_LINE8D2,
1909 VGA_DRAW_LINE8,
1910 VGA_DRAW_LINE15,
1911 VGA_DRAW_LINE16,
1912 VGA_DRAW_LINE24,
1913 VGA_DRAW_LINE32,
1914 VGA_DRAW_LINE_NB
1915};
1916
1917static vga_draw_line_func *vga_draw_line_table[4 * VGA_DRAW_LINE_NB] = {
1918 vga_draw_line2_8,
1919 vga_draw_line2_16,
1920 vga_draw_line2_16,
1921 vga_draw_line2_32,
1922
1923 vga_draw_line2d2_8,
1924 vga_draw_line2d2_16,
1925 vga_draw_line2d2_16,
1926 vga_draw_line2d2_32,
1927
1928 vga_draw_line4_8,
1929 vga_draw_line4_16,
1930 vga_draw_line4_16,
1931 vga_draw_line4_32,
1932
1933 vga_draw_line4d2_8,
1934 vga_draw_line4d2_16,
1935 vga_draw_line4d2_16,
1936 vga_draw_line4d2_32,
1937
1938 vga_draw_line8d2_8,
1939 vga_draw_line8d2_16,
1940 vga_draw_line8d2_16,
1941 vga_draw_line8d2_32,
1942
1943 vga_draw_line8_8,
1944 vga_draw_line8_16,
1945 vga_draw_line8_16,
1946 vga_draw_line8_32,
1947
1948 vga_draw_line15_8,
1949 vga_draw_line15_15,
1950 vga_draw_line15_16,
1951 vga_draw_line15_32,
1952
1953 vga_draw_line16_8,
1954 vga_draw_line16_15,
1955 vga_draw_line16_16,
1956 vga_draw_line16_32,
1957
1958 vga_draw_line24_8,
1959 vga_draw_line24_15,
1960 vga_draw_line24_16,
1961 vga_draw_line24_32,
1962
1963 vga_draw_line32_8,
1964 vga_draw_line32_15,
1965 vga_draw_line32_16,
1966 vga_draw_line32_32,
1967};
1968
1969static int vga_get_bpp(VGAState *s)
1970{
1971 int ret;
1972#ifdef CONFIG_BOCHS_VBE
1973 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1974 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1975 } else
1976#endif
1977 {
1978 ret = 0;
1979 }
1980 return ret;
1981}
1982
1983static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1984{
1985 int width, height;
1986#ifdef CONFIG_BOCHS_VBE
1987 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1988 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1989 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1990 } else
1991#endif
1992 {
1993 width = (s->cr[0x01] + 1) * 8;
1994 height = s->cr[0x12] |
1995 ((s->cr[0x07] & 0x02) << 7) |
1996 ((s->cr[0x07] & 0x40) << 3);
1997 height = (height + 1);
1998 }
1999 *pwidth = width;
2000 *pheight = height;
2001}
2002
2003#ifndef VBOX
2004void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
2005{
2006 int y;
2007 if (y1 >= VGA_MAX_HEIGHT)
2008 return;
2009 if (y2 >= VGA_MAX_HEIGHT)
2010 y2 = VGA_MAX_HEIGHT;
2011 for(y = y1; y < y2; y++) {
2012 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
2013 }
2014}
2015#endif /* !VBOX*/
2016
2017#ifdef VBOX
2018/**
2019 * Performs the display driver resizing when in graphics mode.
2020 *
2021 * This will recalc / update any status data depending on the driver
2022 * properties (bit depth mostly).
2023 *
2024 * @returns VINF_SUCCESS on success.
2025 * @returns VINF_VGA_RESIZE_IN_PROGRESS if the operation wasn't complete.
2026 * @param s Pointer to the vga status.
2027 * @param cx The width.
2028 * @param cy The height.
2029 */
2030static int vga_resize_graphic(VGAState *s, int cx, int cy, int v)
2031{
2032 const unsigned cBits = s->get_bpp(s);
2033 /** @todo r=sunlover: If the guest changes VBE_DISPI_INDEX_X_OFFSET, VBE_DISPI_INDEX_Y_OFFSET
2034 * registers, then the third parameter of the following call should be
2035 * probably 's->CTXSUFF(vram_ptr) + s->vbe_start_addr'.
2036 */
2037 int rc = s->pDrv->pfnResize(s->pDrv, cBits, s->CTXSUFF(vram_ptr), s->line_offset, cx, cy);
2038
2039 /* last stuff */
2040 s->last_bpp = cBits;
2041 s->last_scr_width = cx;
2042 s->last_scr_height = cy;
2043 s->last_width = cx;
2044 s->last_height = cy;
2045
2046 if (rc == VINF_VGA_RESIZE_IN_PROGRESS)
2047 return rc;
2048 AssertRC(rc);
2049
2050 /* update palette */
2051 switch (s->pDrv->cBits)
2052 {
2053 case 32: s->rgb_to_pixel = rgb_to_pixel32_dup; break;
2054 case 16:
2055 default: s->rgb_to_pixel = rgb_to_pixel16_dup; break;
2056 case 15: s->rgb_to_pixel = rgb_to_pixel15_dup; break;
2057 case 8: s->rgb_to_pixel = rgb_to_pixel8_dup; break;
2058 }
2059 if (s->shift_control == 0)
2060 update_palette16(s);
2061 else if (s->shift_control == 1)
2062 update_palette16(s);
2063 return VINF_SUCCESS;
2064}
2065#endif /* VBOX */
2066
2067/*
2068 * graphic modes
2069 */
2070#ifndef VBOX
2071static void vga_draw_graphic(VGAState *s, int full_update)
2072#else
2073static int vga_draw_graphic(VGAState *s, int full_update)
2074#endif /* !VBOX */
2075{
2076 int y1, y2, y, update, page_min, page_max, linesize, y_start, double_scan;
2077 int width, height, shift_control, line_offset, page0, page1, bwidth;
2078 int disp_width, multi_run;
2079 uint8_t *d;
2080 uint32_t v, addr1, addr;
2081 vga_draw_line_func *vga_draw_line;
2082 bool offsets_changed;
2083
2084 offsets_changed = update_basic_params(s);
2085
2086 full_update |= offsets_changed;
2087
2088 s->get_resolution(s, &width, &height);
2089 disp_width = width;
2090
2091 shift_control = (s->gr[0x05] >> 5) & 3;
2092 double_scan = (s->cr[0x09] >> 7);
2093 multi_run = double_scan;
2094 if (shift_control != s->shift_control ||
2095 double_scan != s->double_scan) {
2096 full_update = 1;
2097 s->shift_control = shift_control;
2098 s->double_scan = double_scan;
2099 }
2100
2101 if (shift_control == 0) {
2102 full_update |= update_palette16(s);
2103 if (s->sr[0x01] & 8) {
2104 v = VGA_DRAW_LINE4D2;
2105 disp_width <<= 1;
2106 } else {
2107 v = VGA_DRAW_LINE4;
2108 }
2109 } else if (shift_control == 1) {
2110 full_update |= update_palette16(s);
2111 if (s->sr[0x01] & 8) {
2112 v = VGA_DRAW_LINE2D2;
2113 disp_width <<= 1;
2114 } else {
2115 v = VGA_DRAW_LINE2;
2116 }
2117 } else {
2118 switch(s->get_bpp(s)) {
2119 default:
2120 case 0:
2121 full_update |= update_palette256(s);
2122 v = VGA_DRAW_LINE8D2;
2123 break;
2124 case 8:
2125 full_update |= update_palette256(s);
2126 v = VGA_DRAW_LINE8;
2127 break;
2128 case 15:
2129 v = VGA_DRAW_LINE15;
2130 break;
2131 case 16:
2132 v = VGA_DRAW_LINE16;
2133 break;
2134 case 24:
2135 v = VGA_DRAW_LINE24;
2136 break;
2137 case 32:
2138 v = VGA_DRAW_LINE32;
2139 break;
2140 }
2141 }
2142#ifndef VBOX
2143 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->ds->depth)];
2144
2145 if (disp_width != s->last_width ||
2146 height != s->last_height) {
2147 dpy_resize(s->ds, disp_width, height);
2148 s->last_scr_width = disp_width;
2149 s->last_scr_height = height;
2150 s->last_width = disp_width;
2151 s->last_height = height;
2152 full_update = 1;
2153 }
2154#else /* VBOX */
2155 if ( disp_width != (int)s->last_width
2156 || height != (int)s->last_height
2157 || s->get_bpp(s) != (int)s->last_bpp
2158 || offsets_changed)
2159 {
2160 int rc = vga_resize_graphic(s, disp_width, height, v);
2161 if (rc != VINF_SUCCESS) /* Return any rc, particularly VINF_VGA_RESIZE_IN_PROGRESS, to the caller. */
2162 return rc;
2163 full_update = 1;
2164 }
2165 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
2166
2167#endif /* VBOX */
2168 if (s->cursor_invalidate)
2169 s->cursor_invalidate(s);
2170
2171 line_offset = s->line_offset;
2172#if 0
2173 Log(("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
2174 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]));
2175#endif
2176 addr1 = (s->start_addr * 4);
2177#ifndef VBOX
2178 bwidth = width * 4;
2179#else /* VBOX */
2180 /* The width of VRAM scanline. */
2181 bwidth = s->line_offset;
2182 /* In some cases the variable is not yet set, probably due to incomplete
2183 * programming of the virtual hardware ports. Just return.
2184 */
2185 if (bwidth == 0) return VINF_SUCCESS;
2186#endif /* VBOX */
2187 y_start = -1;
2188 page_min = 0x7fffffff;
2189 page_max = -1;
2190#ifndef VBOX
2191 d = s->ds->data;
2192 linesize = s->ds->linesize;
2193#else /* VBOX */
2194 d = s->pDrv->pu8Data;
2195 linesize = s->pDrv->cbScanline;
2196#endif /* VBOX */
2197
2198 y1 = 0;
2199 y2 = s->cr[0x09] & 0x1F; /* starting row scan count */
2200 for(y = 0; y < height; y++) {
2201 addr = addr1;
2202 /* CGA/MDA compatibility. Note that these addresses are all
2203 * shifted left by two compared to VGA specs.
2204 */
2205 if (!(s->cr[0x17] & 1)) {
2206 addr = (addr & ~(1 << 15)) | ((y1 & 1) << 15);
2207 }
2208 if (!(s->cr[0x17] & 2)) {
2209 addr = (addr & ~(1 << 16)) | ((y1 & 2) << 15);
2210 }
2211#ifndef VBOX
2212 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
2213 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
2214 update = full_update |
2215 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
2216 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
2217 if ((page1 - page0) > TARGET_PAGE_SIZE) {
2218 /* if wide line, can use another page */
2219 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
2220 VGA_DIRTY_FLAG);
2221 }
2222#else /* VBOX */
2223 page0 = addr & TARGET_PAGE_MASK;
2224 page1 = (addr + bwidth - 1) & TARGET_PAGE_MASK;
2225 update = full_update | vga_is_dirty(s, page0) | vga_is_dirty(s, page1);
2226 if (page1 - page0 > TARGET_PAGE_SIZE) {
2227 /* if wide line, can use another page */
2228 update |= vga_is_dirty(s, page0 + TARGET_PAGE_SIZE);
2229 }
2230#endif /* VBOX */
2231 /* explicit invalidation for the hardware cursor */
2232 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
2233 if (update) {
2234 if (y_start < 0)
2235 y_start = y;
2236 if (page0 < page_min)
2237 page_min = page0;
2238 if (page1 > page_max)
2239 page_max = page1;
2240#ifndef VBOX
2241 vga_draw_line(s, d, s->vram_ptr + addr, width);
2242#else /* VBOX */
2243 if (s->fRenderVRAM)
2244 vga_draw_line(s, d, s->CTXSUFF(vram_ptr) + addr, width);
2245#endif /* VBOX */
2246 if (s->cursor_draw_line)
2247 s->cursor_draw_line(s, d, y);
2248 } else {
2249 if (y_start >= 0) {
2250 /* flush to display */
2251#ifndef VBOX
2252 dpy_update(s->ds, 0, y_start,
2253 disp_width, y - y_start);
2254#else /* VBOX */
2255 s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2256#endif /* VBOX */
2257 y_start = -1;
2258 }
2259 }
2260 if (!multi_run) {
2261 y1++;
2262 multi_run = double_scan;
2263
2264 if (y2 == 0) {
2265 y2 = s->cr[0x09] & 0x1F;
2266 addr1 += line_offset;
2267 } else {
2268 --y2;
2269 }
2270 } else {
2271 multi_run--;
2272 }
2273 /* line compare acts on the displayed lines */
2274 if ((uint32_t)y == s->line_compare)
2275 addr1 = 0;
2276 d += linesize;
2277 }
2278 if (y_start >= 0) {
2279 /* flush to display */
2280#ifndef VBOX
2281 dpy_update(s->ds, 0, y_start,
2282 disp_width, y - y_start);
2283#else /* VBOX */
2284 s->pDrv->pfnUpdateRect(s->pDrv, 0, y_start, disp_width, y - y_start);
2285#endif /* VBOX */
2286 }
2287 /* reset modified pages */
2288 if (page_max != -1) {
2289#ifndef VBOX
2290 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
2291 VGA_DIRTY_FLAG);
2292#else /* VBOX */
2293 vga_reset_dirty(s, page_min, page_max + TARGET_PAGE_SIZE);
2294#endif /* VBOX */
2295 }
2296 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
2297#ifdef VBOX
2298 return VINF_SUCCESS;
2299#endif /* VBOX */
2300}
2301
2302static void vga_draw_blank(VGAState *s, int full_update)
2303{
2304#ifndef VBOX
2305 int i, w, val;
2306 uint8_t *d;
2307
2308 if (!full_update)
2309 return;
2310 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
2311 return;
2312 if (s->ds->depth == 8)
2313 val = s->rgb_to_pixel(0, 0, 0);
2314 else
2315 val = 0;
2316 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
2317 d = s->ds->data;
2318 for(i = 0; i < s->last_scr_height; i++) {
2319 memset(d, val, w);
2320 d += s->ds->linesize;
2321 }
2322 dpy_update(s->ds, 0, 0,
2323 s->last_scr_width, s->last_scr_height);
2324#else /* VBOX */
2325
2326 int i, w, val;
2327 uint8_t *d;
2328 uint32_t cbScanline = s->pDrv->cbScanline;
2329
2330 if (s->pDrv->pu8Data == s->vram_ptrHC) /* Do not clear the VRAM itself. */
2331 return;
2332 if (!full_update)
2333 return;
2334 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
2335 return;
2336 if (s->pDrv->cBits == 8)
2337 val = s->rgb_to_pixel(0, 0, 0);
2338 else
2339 val = 0;
2340 w = s->last_scr_width * ((s->pDrv->cBits + 7) >> 3);
2341 d = s->pDrv->pu8Data;
2342 for(i = 0; i < (int)s->last_scr_height; i++) {
2343 memset(d, val, w);
2344 d += cbScanline;
2345 }
2346 s->pDrv->pfnUpdateRect(s->pDrv, 0, 0, s->last_scr_width, s->last_scr_height);
2347#endif /* VBOX */
2348}
2349
2350#define GMODE_TEXT 0
2351#define GMODE_GRAPH 1
2352#define GMODE_BLANK 2
2353
2354#ifndef VBOX
2355void vga_update_display(void)
2356{
2357 VGAState *s = vga_state;
2358#else /* VBOX */
2359static int vga_update_display(PVGASTATE s)
2360{
2361 int rc = VINF_SUCCESS;
2362#endif /* VBOX */
2363 int full_update, graphic_mode;
2364
2365#ifndef VBOX
2366 if (s->ds->depth == 0) {
2367#else /* VBOX */
2368 if (s->pDrv->cBits == 0) {
2369#endif /* VBOX */
2370 /* nothing to do */
2371 } else {
2372#ifndef VBOX
2373 switch(s->ds->depth) {
2374#else /* VBOX */
2375 switch(s->pDrv->cBits) {
2376#endif /* VBOX */
2377 case 8:
2378 s->rgb_to_pixel = rgb_to_pixel8_dup;
2379 break;
2380 case 15:
2381 s->rgb_to_pixel = rgb_to_pixel15_dup;
2382 break;
2383 default:
2384 case 16:
2385 s->rgb_to_pixel = rgb_to_pixel16_dup;
2386 break;
2387 case 32:
2388 s->rgb_to_pixel = rgb_to_pixel32_dup;
2389 break;
2390 }
2391
2392 full_update = 0;
2393 if (!(s->ar_index & 0x20)) {
2394 graphic_mode = GMODE_BLANK;
2395 } else {
2396 graphic_mode = s->gr[6] & 1;
2397 }
2398 if (graphic_mode != s->graphic_mode) {
2399 s->graphic_mode = graphic_mode;
2400 full_update = 1;
2401 }
2402 switch(graphic_mode) {
2403 case GMODE_TEXT:
2404#ifdef VBOX
2405 rc =
2406#endif /* VBOX */
2407 vga_draw_text(s, full_update);
2408 break;
2409 case GMODE_GRAPH:
2410#ifdef VBOX
2411 rc =
2412#endif /* VBOX */
2413 vga_draw_graphic(s, full_update);
2414 break;
2415 case GMODE_BLANK:
2416 default:
2417 vga_draw_blank(s, full_update);
2418 break;
2419 }
2420 }
2421#ifdef VBOX
2422 return rc;
2423#endif /* VBOX */
2424}
2425
2426/* force a full display refresh */
2427#ifndef VBOX
2428void vga_invalidate_display(void)
2429{
2430 VGAState *s = vga_state;
2431
2432 s->last_width = -1;
2433 s->last_height = -1;
2434}
2435#endif /* !VBOX */
2436
2437#ifndef VBOX /* see vgaR3Reset() */
2438static void vga_reset(VGAState *s)
2439{
2440 memset(s, 0, sizeof(VGAState));
2441 s->graphic_mode = -1; /* force full update */
2442}
2443#endif /* !VBOX */
2444
2445#ifndef VBOX
2446static CPUReadMemoryFunc *vga_mem_read[3] = {
2447 vga_mem_readb,
2448 vga_mem_readw,
2449 vga_mem_readl,
2450};
2451
2452static CPUWriteMemoryFunc *vga_mem_write[3] = {
2453 vga_mem_writeb,
2454 vga_mem_writew,
2455 vga_mem_writel,
2456};
2457#endif /* !VBOX */
2458
2459static void vga_save(QEMUFile *f, void *opaque)
2460{
2461 VGAState *s = (VGAState*)opaque;
2462 int i;
2463
2464 qemu_put_be32s(f, &s->latch);
2465 qemu_put_8s(f, &s->sr_index);
2466 qemu_put_buffer(f, s->sr, 8);
2467 qemu_put_8s(f, &s->gr_index);
2468 qemu_put_buffer(f, s->gr, 16);
2469 qemu_put_8s(f, &s->ar_index);
2470 qemu_put_buffer(f, s->ar, 21);
2471 qemu_put_be32s(f, &s->ar_flip_flop);
2472 qemu_put_8s(f, &s->cr_index);
2473 qemu_put_buffer(f, s->cr, 256);
2474 qemu_put_8s(f, &s->msr);
2475 qemu_put_8s(f, &s->fcr);
2476 qemu_put_8s(f, &s->st00);
2477 qemu_put_8s(f, &s->st01);
2478
2479 qemu_put_8s(f, &s->dac_state);
2480 qemu_put_8s(f, &s->dac_sub_index);
2481 qemu_put_8s(f, &s->dac_read_index);
2482 qemu_put_8s(f, &s->dac_write_index);
2483 qemu_put_buffer(f, s->dac_cache, 3);
2484 qemu_put_buffer(f, s->palette, 768);
2485
2486 qemu_put_be32s(f, &s->bank_offset);
2487#ifdef CONFIG_BOCHS_VBE
2488 qemu_put_byte(f, 1);
2489 qemu_put_be16s(f, &s->vbe_index);
2490 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2491 qemu_put_be16s(f, &s->vbe_regs[i]);
2492 qemu_put_be32s(f, &s->vbe_start_addr);
2493 qemu_put_be32s(f, &s->vbe_line_offset);
2494 qemu_put_be32s(f, &s->vbe_bank_mask);
2495#else
2496 qemu_put_byte(f, 0);
2497#endif
2498}
2499
2500static int vga_load(QEMUFile *f, void *opaque, int version_id)
2501{
2502 VGAState *s = (VGAState*)opaque;
2503 int is_vbe, i;
2504
2505 if (version_id != 1)
2506#ifndef VBOX
2507 return -EINVAL;
2508#else /* VBOX */
2509 {
2510 Log(("vga_load: version_id=%d - UNKNOWN\n", version_id));
2511 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2512 }
2513#endif /* VBOX */
2514
2515 qemu_get_be32s(f, &s->latch);
2516 qemu_get_8s(f, &s->sr_index);
2517 qemu_get_buffer(f, s->sr, 8);
2518 qemu_get_8s(f, &s->gr_index);
2519 qemu_get_buffer(f, s->gr, 16);
2520 qemu_get_8s(f, &s->ar_index);
2521 qemu_get_buffer(f, s->ar, 21);
2522 qemu_get_be32s(f, (uint32_t *)&s->ar_flip_flop);
2523 qemu_get_8s(f, &s->cr_index);
2524 qemu_get_buffer(f, s->cr, 256);
2525 qemu_get_8s(f, &s->msr);
2526 qemu_get_8s(f, &s->fcr);
2527 qemu_get_8s(f, &s->st00);
2528 qemu_get_8s(f, &s->st01);
2529
2530 qemu_get_8s(f, &s->dac_state);
2531 qemu_get_8s(f, &s->dac_sub_index);
2532 qemu_get_8s(f, &s->dac_read_index);
2533 qemu_get_8s(f, &s->dac_write_index);
2534 qemu_get_buffer(f, s->dac_cache, 3);
2535 qemu_get_buffer(f, s->palette, 768);
2536
2537 qemu_get_be32s(f, (uint32_t *)&s->bank_offset);
2538 is_vbe = qemu_get_byte(f);
2539#ifdef CONFIG_BOCHS_VBE
2540 if (!is_vbe)
2541#ifndef VBOX
2542 return -EINVAL;
2543#else /* VBOX */
2544 {
2545 Log(("vga_load: !is_vbe !!\n"));
2546 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2547 }
2548#endif /* VBOX */
2549 qemu_get_be16s(f, &s->vbe_index);
2550 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2551 qemu_get_be16s(f, &s->vbe_regs[i]);
2552 qemu_get_be32s(f, &s->vbe_start_addr);
2553 qemu_get_be32s(f, &s->vbe_line_offset);
2554 qemu_get_be32s(f, &s->vbe_bank_mask);
2555#else
2556 if (is_vbe)
2557#ifndef VBOX
2558 return -EINVAL;
2559#else /* VBOX */
2560 {
2561 Log(("vga_load: is_vbe !!\n"));
2562 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2563 }
2564#endif /* VBOX */
2565#endif
2566
2567 /* force refresh */
2568 s->graphic_mode = -1;
2569 return 0;
2570}
2571
2572#ifndef VBOX /* see vgaR3IORegionMap */
2573static void vga_map(PCIDevice *pci_dev, int region_num,
2574 uint32_t addr, uint32_t size, int type)
2575{
2576 VGAState *s = vga_state;
2577
2578 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2579}
2580#endif
2581
2582#ifndef VBOX /* see vgaR3Construct */
2583void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2584 unsigned long vga_ram_offset, int vga_ram_size)
2585#else
2586static void vga_init_expand(void)
2587#endif
2588{
2589 int i, j, v, b;
2590
2591 for(i = 0;i < 256; i++) {
2592 v = 0;
2593 for(j = 0; j < 8; j++) {
2594 v |= ((i >> j) & 1) << (j * 4);
2595 }
2596 expand4[i] = v;
2597
2598 v = 0;
2599 for(j = 0; j < 4; j++) {
2600 v |= ((i >> (2 * j)) & 3) << (j * 4);
2601 }
2602 expand2[i] = v;
2603 }
2604 for(i = 0; i < 16; i++) {
2605 v = 0;
2606 for(j = 0; j < 4; j++) {
2607 b = ((i >> j) & 1);
2608 v |= b << (2 * j);
2609 v |= b << (2 * j + 1);
2610 }
2611 expand4to8[i] = v;
2612 }
2613#ifdef VBOX
2614}
2615#else /* !VBOX */
2616 vga_reset(s);
2617
2618 s->vram_ptr = vga_ram_base;
2619 s->vram_offset = vga_ram_offset;
2620 s->vram_size = vga_ram_size;
2621 s->ds = ds;
2622 s->get_bpp = vga_get_bpp;
2623 s->get_offsets = vga_get_offsets;
2624 s->get_resolution = vga_get_resolution;
2625 /* XXX: currently needed for display */
2626 vga_state = s;
2627}
2628
2629
2630int vga_initialize(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2631 unsigned long vga_ram_offset, int vga_ram_size)
2632{
2633 VGAState *s;
2634
2635 s = qemu_mallocz(sizeof(VGAState));
2636 if (!s)
2637 return -1;
2638
2639 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2640
2641 register_savevm("vga", 0, 1, vga_save, vga_load, s);
2642
2643 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2644
2645 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2646 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2647 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2648 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2649
2650 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2651
2652 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2653 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2654 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2655 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2656 s->bank_offset = 0;
2657
2658#ifdef CONFIG_BOCHS_VBE
2659 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2660 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2661#if defined (TARGET_I386)
2662 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2663 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2664
2665 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2666 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2667
2668 /* old Bochs IO ports */
2669 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2670 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2671
2672 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2673 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2674#else
2675 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2676 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2677
2678 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2679 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2680#endif
2681#endif /* CONFIG_BOCHS_VBE */
2682
2683 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2684 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2685 vga_io_memory);
2686
2687 if (bus) {
2688 PCIDevice *d;
2689 uint8_t *pci_conf;
2690
2691 d = pci_register_device(bus, "VGA",
2692 sizeof(PCIDevice),
2693 -1, NULL, NULL);
2694 pci_conf = d->config;
2695 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2696 pci_conf[0x01] = 0x12;
2697 pci_conf[0x02] = 0x11;
2698 pci_conf[0x03] = 0x11;
2699 pci_conf[0x0a] = 0x00; // VGA controller
2700 pci_conf[0x0b] = 0x03;
2701 pci_conf[0x0e] = 0x00; // header_type
2702
2703 /* XXX: vga_ram_size must be a power of two */
2704 pci_register_io_region(d, 0, vga_ram_size,
2705 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2706 } else {
2707#ifdef CONFIG_BOCHS_VBE
2708 /* XXX: use optimized standard vga accesses */
2709 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2710 vga_ram_size, vga_ram_offset);
2711#endif
2712 }
2713 return 0;
2714}
2715#endif /* !VBOX */
2716
2717
2718#ifndef VBOX
2719/********************************************************/
2720/* vga screen dump */
2721
2722static int vga_save_w, vga_save_h;
2723
2724static void vga_save_dpy_update(DisplayState *s,
2725 int x, int y, int w, int h)
2726{
2727}
2728
2729static void vga_save_dpy_resize(DisplayState *s, int w, int h)
2730{
2731 s->linesize = w * 4;
2732#ifndef VBOX
2733 s->data = qemu_malloc(h * s->linesize);
2734#else /* VBOX */
2735 if (!s->data)
2736 {
2737 PPDMDEVINS pDevIns = VGASTATE2DEVINS((PVGASTATE)s->pvVgaState);
2738 s->data = PDMDevHlpMMHeapAlloc(pDevIns, h * s->linesize);
2739 }
2740 else // (32-bpp buffer is allocated by the caller)
2741 s->linesize = ((w * 32 + 31) / 32) * 4;
2742#endif /* VBOX */
2743 vga_save_w = w;
2744 vga_save_h = h;
2745}
2746
2747static void vga_save_dpy_refresh(DisplayState *s)
2748{
2749}
2750
2751static int ppm_save(const char *filename, uint8_t *data,
2752 int w, int h, int linesize)
2753{
2754 FILE *f;
2755 uint8_t *d, *d1;
2756 unsigned int v;
2757 int y, x;
2758
2759 f = fopen(filename, "wb");
2760 if (!f)
2761 return -1;
2762 fprintf(f, "P6\n%d %d\n%d\n",
2763 w, h, 255);
2764 d1 = data;
2765 for(y = 0; y < h; y++) {
2766 d = d1;
2767 for(x = 0; x < w; x++) {
2768 v = *(uint32_t *)d;
2769 fputc((v >> 16) & 0xff, f);
2770 fputc((v >> 8) & 0xff, f);
2771 fputc((v) & 0xff, f);
2772 d += 4;
2773 }
2774 d1 += linesize;
2775 }
2776 fclose(f);
2777 return 0;
2778}
2779
2780/* save the vga display in a PPM image even if no display is
2781 available */
2782void vga_screen_dump(const char *filename)
2783{
2784 VGAState *s = vga_state;
2785 DisplayState *saved_ds, ds1, *ds = &ds1;
2786
2787 /* XXX: this is a little hackish */
2788 vga_invalidate_display();
2789 saved_ds = s->ds;
2790
2791 memset(ds, 0, sizeof(DisplayState));
2792 ds->dpy_update = vga_save_dpy_update;
2793 ds->dpy_resize = vga_save_dpy_resize;
2794 ds->dpy_refresh = vga_save_dpy_refresh;
2795 ds->depth = 32;
2796
2797 s->ds = ds;
2798 s->graphic_mode = -1;
2799 vga_update_display();
2800
2801 if (ds->data) {
2802 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2803 s->ds->linesize);
2804 qemu_free(ds->data);
2805 }
2806 s->ds = saved_ds;
2807}
2808#endif /* !VBOX */
2809
2810
2811#if 0 //def VBOX
2812/* copy the vga display contents to the given buffer. the size of the buffer
2813 must be sufficient to store the screen copy (see below). the width and height
2814 parameters determine the required dimensions of the copy. If they differ
2815 from the actual screen dimensions, then the returned copy is shrinked or
2816 stretched accordingly. The copy is always a 32-bit image, so the size of
2817 the buffer supplied must be at least (((width * 32 + 31) / 32) * 4) * height,
2818 i.e. dword-aligned. returns zero if the operation was successfull and -1
2819 otherwise. */
2820
2821static int vga_copy_screen_to(PVGASTATE s, uint8_t *buf, int width, int height)
2822{
2823 DisplayState *saved_ds, ds1, *ds = &ds1;
2824 if (!buf || width <= 0 || height <= 0)
2825 return -1;
2826
2827 /* XXX: this is a little hackish */
2828 vga_invalidate_display(s);
2829 saved_ds = s->ds;
2830
2831 memset(ds, 0, sizeof(DisplayState));
2832 ds->dpy_update = vga_save_dpy_update;
2833 ds->dpy_resize = vga_save_dpy_resize;
2834 ds->dpy_refresh = vga_save_dpy_refresh;
2835 ds->depth = 32;
2836 ds->data = buf;
2837 ds->pvVgaState = s;
2838
2839 s->ds = ds;
2840 s->graphic_mode = -1;
2841 vga_update_display(s);
2842
2843//@@TODO (dmik): implement stretching/shrinking!
2844
2845 s->ds = saved_ds;
2846 return 0;
2847}
2848
2849/* copy the given buffer to the vga display. width and height define the
2850 dimensions of the image in the buffer. x and y define the point on the
2851 vga display to copy the image to. the buffer is assumed to contain a 32-bit
2852 image, so the size of one scanline must be ((width * 32 + 31) / 32) * 4),
2853 i.e. dword-aligned. returns zero if the operation was successfull and -1
2854 otherwise. */
2855static int vga_copy_screen_from(PVGASTATE s, uint8_t *buf, int x, int y, int width, int height)
2856{
2857 int bpl = ((width * 32 + 31) / 32) * 4;
2858 int linesize = s->ds->linesize;
2859 uint8_t *dst;
2860 uint8_t *src;
2861 int bpp;
2862 vga_draw_line_func *vga_draw_line;
2863
2864 if (!buf || x < 0 || y < 0 || width <= 0 || height <= 0
2865 || x + width > s->ds->width || y + height > s->ds->height)
2866 return -1;
2867
2868 vga_draw_line = vga_draw_line_table[VGA_DRAW_LINE32 * 4 + get_depth_index(s->ds->depth)];
2869 switch (s->ds->depth) {
2870 case 8: bpp = 1; break;
2871 case 15:
2872 case 16: bpp = 2; break;
2873 case 32: bpp = 4; break;
2874 default: return -1;
2875 }
2876
2877 dst = s->ds->data + y * linesize + x * bpp;
2878 src = buf;
2879 for (y = 0; y < height; y ++)
2880 {
2881 vga_draw_line(s, dst, src, width);
2882 dst += linesize;
2883 src += bpl;
2884 }
2885
2886 return 0;
2887}
2888#endif
2889
2890#endif /* !VBOX || !IN_GC || !IN_RING0 */
2891
2892
2893
2894#ifdef VBOX /* VirtualBox code start */
2895
2896
2897/* -=-=-=-=-=- all contexts -=-=-=-=-=- */
2898
2899/**
2900 * Port I/O Handler for VGA OUT operations.
2901 *
2902 * @returns VBox status code.
2903 *
2904 * @param pDevIns The device instance.
2905 * @param pvUser User argument - ignored.
2906 * @param Port Port number used for the IN operation.
2907 * @param u32 The value to output.
2908 * @param cb The value size in bytes.
2909 */
2910PDMBOTHCBDECL(int) vgaIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2911{
2912 NOREF(pvUser);
2913 if (cb == 1)
2914 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
2915 else if (cb == 2)
2916 {
2917 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32 & 0xff);
2918 vga_ioport_write(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1, u32 >> 8);
2919 }
2920 return VINF_SUCCESS;
2921}
2922
2923
2924/**
2925 * Port I/O Handler for VGA IN operations.
2926 *
2927 * @returns VBox status code.
2928 *
2929 * @param pDevIns The device instance.
2930 * @param pvUser User argument - ignored.
2931 * @param Port Port number used for the IN operation.
2932 * @param pu32 Where to store the result.
2933 * @param cb Number of bytes read.
2934 */
2935PDMBOTHCBDECL(int) vgaIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
2936{
2937 NOREF(pvUser);
2938 if (cb == 1)
2939 {
2940 *pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port);
2941 return VINF_SUCCESS;
2942 }
2943 else if (cb == 2)
2944 {
2945 *pu32 = vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port)
2946 | (vga_ioport_read(PDMINS2DATA(pDevIns, PVGASTATE), Port + 1) << 8);
2947 return VINF_SUCCESS;
2948 }
2949 return VERR_IOM_IOPORT_UNUSED;
2950}
2951
2952
2953/**
2954 * Port I/O Handler for VBE OUT operations.
2955 *
2956 * @returns VBox status code.
2957 *
2958 * @param pDevIns The device instance.
2959 * @param pvUser User argument - ignored.
2960 * @param Port Port number used for the IN operation.
2961 * @param u32 The value to output.
2962 * @param cb The value size in bytes.
2963 */
2964PDMBOTHCBDECL(int) vgaIOPortWriteVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
2965{
2966 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
2967
2968 NOREF(pvUser);
2969
2970#ifndef IN_RING3
2971 /*
2972 * This has to be done on the host in order to execute the connector callbacks.
2973 */
2974 if (s->vbe_index == VBE_DISPI_INDEX_ENABLE
2975 || s->vbe_index == VBE_DISPI_INDEX_VBOX_VIDEO)
2976 {
2977 Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE - Switching to host...\n"));
2978 return VINF_IOM_HC_IOPORT_WRITE;
2979 }
2980#endif
2981#ifdef VBE_BYTEWISE_IO
2982 if (cb == 1)
2983 {
2984 if (!s->fWriteVBEData)
2985 {
2986 if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
2987 && (u32 & VBE_DISPI_ENABLED))
2988 {
2989 s->fWriteVBEData = false;
2990 return vbe_ioport_write_data(s, Port, u32 & 0xFF);
2991 }
2992 else
2993 {
2994 s->cbWriteVBEData = u32 & 0xFF;
2995 s->fWriteVBEData = true;
2996 return VINF_SUCCESS;
2997 }
2998 }
2999 else
3000 {
3001 u32 = (s->cbWriteVBEData << 8) | (u32 & 0xFF);
3002 s->fWriteVBEData = false;
3003 cb = 2;
3004 }
3005 }
3006#endif
3007 if (cb == 2 || cb == 4)
3008 {
3009//#ifdef IN_GC
3010// /*
3011// * The VBE_DISPI_INDEX_ENABLE memsets the entire frame buffer.
3012// * Since we're not mapping the entire framebuffer any longer that
3013// * has to be done on the host.
3014// */
3015// if ( (s->vbe_index == VBE_DISPI_INDEX_ENABLE)
3016// && (u32 & VBE_DISPI_ENABLED))
3017// {
3018// Log(("vgaIOPortWriteVBEData: VBE_DISPI_INDEX_ENABLE & VBE_DISPI_ENABLED - Switching to host...\n"));
3019// return VINF_IOM_HC_IOPORT_WRITE;
3020// }
3021//#endif
3022 return vbe_ioport_write_data(s, Port, u32);
3023 }
3024 else
3025 AssertMsgFailed(("vgaIOPortWriteVBEData: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3026 return VINF_SUCCESS;
3027}
3028
3029
3030/**
3031 * Port I/O Handler for VBE OUT operations.
3032 *
3033 * @returns VBox status code.
3034 *
3035 * @param pDevIns The device instance.
3036 * @param pvUser User argument - ignored.
3037 * @param Port Port number used for the IN operation.
3038 * @param u32 The value to output.
3039 * @param cb The value size in bytes.
3040 */
3041PDMBOTHCBDECL(int) vgaIOPortWriteVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3042{
3043 NOREF(pvUser);
3044#ifdef VBE_BYTEWISE_IO
3045 if (cb == 1)
3046 {
3047 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3048 if (!s->fWriteVBEIndex)
3049 {
3050 s->cbWriteVBEIndex = u32 & 0x00FF;
3051 s->fWriteVBEIndex = true;
3052 return VINF_SUCCESS;
3053 }
3054 else
3055 {
3056 s->fWriteVBEIndex = false;
3057 vbe_ioport_write_index(s, Port, (s->cbWriteVBEIndex << 8) | (u32 & 0x00FF));
3058 return VINF_SUCCESS;
3059 }
3060 }
3061 else
3062#endif
3063 if (cb == 2)
3064 vbe_ioport_write_index(PDMINS2DATA(pDevIns, PVGASTATE), Port, u32);
3065 else
3066 AssertMsgFailed(("vgaIOPortWriteVBEIndex: Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
3067 return VINF_SUCCESS;
3068}
3069
3070
3071/**
3072 * Port I/O Handler for VBE IN operations.
3073 *
3074 * @returns VBox status code.
3075 *
3076 * @param pDevIns The device instance.
3077 * @param pvUser User argument - ignored.
3078 * @param Port Port number used for the IN operation.
3079 * @param pu32 Where to store the result.
3080 * @param cb Number of bytes to read.
3081 */
3082PDMBOTHCBDECL(int) vgaIOPortReadVBEData(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3083{
3084 NOREF(pvUser);
3085#ifdef VBE_BYTEWISE_IO
3086 if (cb == 1)
3087 {
3088 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3089
3090 if (!s->fReadVBEData)
3091 {
3092 *pu32 = (vbe_ioport_read_data(s, Port) >> 8) & 0xFF;
3093 s->fReadVBEData = true;
3094 return VINF_SUCCESS;
3095 }
3096 else
3097 {
3098 *pu32 = vbe_ioport_read_data(s, Port) & 0xFF;
3099 s->fReadVBEData = false;
3100 return VINF_SUCCESS;
3101 }
3102 }
3103 else
3104#endif
3105 if (cb == 2)
3106 {
3107 *pu32 = vbe_ioport_read_data(PDMINS2DATA(pDevIns, PVGASTATE), Port);
3108 return VINF_SUCCESS;
3109 }
3110 else if (cb == 4)
3111 {
3112 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3113 /* Quick hack for getting the vram size. */
3114 *pu32 = s->vram_size;
3115 return VINF_SUCCESS;
3116 }
3117 AssertMsgFailed(("vgaIOPortReadVBEData: Port=%#x cb=%d\n", Port, cb));
3118 return VERR_IOM_IOPORT_UNUSED;
3119}
3120
3121
3122/**
3123 * Port I/O Handler for VBE IN operations.
3124 *
3125 * @returns VBox status code.
3126 *
3127 * @param pDevIns The device instance.
3128 * @param pvUser User argument - ignored.
3129 * @param Port Port number used for the IN operation.
3130 * @param pu32 Where to store the result.
3131 * @param cb Number of bytes to read.
3132 */
3133PDMBOTHCBDECL(int) vgaIOPortReadVBEIndex(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3134{
3135 NOREF(pvUser);
3136#ifdef VBE_BYTEWISE_IO
3137 if (cb == 1)
3138 {
3139 VGAState *s = PDMINS2DATA(pDevIns, PVGASTATE);
3140
3141 if (!s->fReadVBEIndex)
3142 {
3143 *pu32 = (vbe_ioport_read_index(s, Port) >> 8) & 0xFF;
3144 s->fReadVBEIndex = true;
3145 return VINF_SUCCESS;
3146 }
3147 else
3148 {
3149 *pu32 = vbe_ioport_read_index(s, Port) & 0xFF;
3150 s->fReadVBEIndex = false;
3151 return VINF_SUCCESS;
3152 }
3153 }
3154 else
3155#endif
3156 if (cb == 2)
3157 {
3158 *pu32 = vbe_ioport_read_index(PDMINS2DATA(pDevIns, PVGASTATE), Port);
3159 return VINF_SUCCESS;
3160 }
3161 AssertMsgFailed(("vgaIOPortReadVBEIndex: Port=%#x cb=%d\n", Port, cb));
3162 return VERR_IOM_IOPORT_UNUSED;
3163}
3164
3165
3166
3167
3168
3169/* -=-=-=-=-=- Guest Context -=-=-=-=-=- */
3170
3171/*
3172 * Internal. For use inside VGAGCMemoryFillWrite only.
3173 * Macro for apply logical operation and bit mask.
3174 */
3175#define APPLY_LOGICAL_AND_MASK(s, val, bit_mask) \
3176 /* apply logical operation */ \
3177 switch(s->gr[3] >> 3) \
3178 { \
3179 case 0: \
3180 default: \
3181 /* nothing to do */ \
3182 break; \
3183 case 1: \
3184 /* and */ \
3185 val &= s->latch; \
3186 break; \
3187 case 2: \
3188 /* or */ \
3189 val |= s->latch; \
3190 break; \
3191 case 3: \
3192 /* xor */ \
3193 val ^= s->latch; \
3194 break; \
3195 } \
3196 /* apply bit mask */ \
3197 val = (val & bit_mask) | (s->latch & ~bit_mask)
3198
3199/**
3200 * Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM and from the inside of VGADeviceGC.cpp.
3201 * This is the advanced version of vga_mem_writeb function.
3202 *
3203 * @returns VBox status code.
3204 * @param pDevIns Pointer device instance.
3205 * @param pvUser User argument - ignored.
3206 * @param GCPhysAddr Physical address of memory to write.
3207 * @param u32Item Data to write, up to 4 bytes.
3208 * @param cbItem Size of data Item, only 1/2/4 bytes is allowed for now.
3209 * @param cItems Number of data items to write.
3210 */
3211PDMBOTHCBDECL(int) vgaMMIOFill(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, uint32_t u32Item, unsigned cbItem, unsigned cItems)
3212{
3213 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3214 uint32_t b;
3215 uint32_t write_mask, bit_mask, set_mask;
3216 uint32_t aVal[4]; /** @todo r=bird: Why is this an 32-bit array? */
3217 unsigned i;
3218 NOREF(pvUser);
3219 for (i = 0; i < cbItem; i++)
3220 {
3221 aVal[i] = u32Item & 0xff;
3222 u32Item >>= 8;
3223 }
3224
3225 /* convert to VGA memory offset */
3226 /// @todo add check for the end of region
3227 GCPhysAddr &= 0x1ffff;
3228 switch((pData->gr[6] >> 2) & 3) {
3229 case 0:
3230 break;
3231 case 1:
3232 if (GCPhysAddr >= 0x10000)
3233 return VINF_SUCCESS;
3234 GCPhysAddr += pData->bank_offset;
3235 break;
3236 case 2:
3237 GCPhysAddr -= 0x10000;
3238 if (GCPhysAddr >= 0x8000)
3239 return VINF_SUCCESS;
3240 break;
3241 default:
3242 case 3:
3243 GCPhysAddr -= 0x18000;
3244 if (GCPhysAddr >= 0x8000)
3245 return VINF_SUCCESS;
3246 break;
3247 }
3248
3249 if (pData->sr[4] & 0x08) {
3250 /* chain 4 mode : simplest access */
3251#ifdef IN_GC
3252 if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
3253 return VINF_IOM_HC_MMIO_WRITE;
3254#else
3255 if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
3256 {
3257 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3258 return VINF_SUCCESS;
3259 }
3260#endif
3261
3262 while (cItems-- > 0)
3263 for (i = 0; i < cbItem; i++)
3264 {
3265 if (pData->sr[2] & (1 << (GCPhysAddr & 3)))
3266 {
3267 CTXSUFF(pData->vram_ptr)[GCPhysAddr] = aVal[i];
3268 vga_set_dirty(pData, GCPhysAddr);
3269 }
3270 GCPhysAddr++;
3271 }
3272 } else if (pData->gr[5] & 0x10) {
3273 /* odd/even mode (aka text mode mapping) */
3274#ifdef IN_GC
3275 if (GCPhysAddr * 2 + cItems * cbItem >= VGA_MAPPING_SIZE)
3276 return VINF_IOM_HC_MMIO_WRITE;
3277#else
3278 if (GCPhysAddr * 2 + cItems * cbItem >= pData->vram_size)
3279 {
3280 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3281 return VINF_SUCCESS;
3282 }
3283#endif
3284 while (cItems-- > 0)
3285 for (i = 0; i < cbItem; i++)
3286 {
3287 unsigned plane = (pData->gr[4] & 2) | (GCPhysAddr & 1);
3288 if (pData->sr[2] & (1 << plane)) {
3289 RTGCPHYS PhysAddr2 = ((GCPhysAddr & ~1) << 2) | plane;
3290 CTXSUFF(pData->vram_ptr)[PhysAddr2] = aVal[i];
3291 vga_set_dirty(pData, PhysAddr2);
3292 }
3293 GCPhysAddr++;
3294 }
3295 } else {
3296#ifdef IN_GC
3297 if (GCPhysAddr + cItems * cbItem >= VGA_MAPPING_SIZE)
3298 return VINF_IOM_HC_MMIO_WRITE;
3299#else
3300 if (GCPhysAddr + cItems * cbItem >= pData->vram_size)
3301 {
3302 AssertMsgFailed(("GCPhysAddr=%VGp cItems=%#x cbItem=%d\n", GCPhysAddr, cItems, cbItem));
3303 return VINF_SUCCESS;
3304 }
3305#endif
3306
3307 /* standard VGA latched access */
3308 switch(pData->gr[5] & 3) {
3309 default:
3310 case 0:
3311 /* rotate */
3312 b = pData->gr[3] & 7;
3313 bit_mask = pData->gr[8];
3314 bit_mask |= bit_mask << 8;
3315 bit_mask |= bit_mask << 16;
3316 set_mask = mask16[pData->gr[1]];
3317
3318 for (i = 0; i < cbItem; i++)
3319 {
3320 aVal[i] = ((aVal[i] >> b) | (aVal[i] << (8 - b))) & 0xff;
3321 aVal[i] |= aVal[i] << 8;
3322 aVal[i] |= aVal[i] << 16;
3323
3324 /* apply set/reset mask */
3325 aVal[i] = (aVal[i] & ~set_mask) | (mask16[pData->gr[0]] & set_mask);
3326
3327 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3328 }
3329 break;
3330 case 1:
3331 for (i = 0; i < cbItem; i++)
3332 aVal[i] = pData->latch;
3333 break;
3334 case 2:
3335 bit_mask = pData->gr[8];
3336 bit_mask |= bit_mask << 8;
3337 bit_mask |= bit_mask << 16;
3338 for (i = 0; i < cbItem; i++)
3339 {
3340 aVal[i] = mask16[aVal[i] & 0x0f];
3341
3342 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3343 }
3344 break;
3345 case 3:
3346 /* rotate */
3347 b = pData->gr[3] & 7;
3348
3349 for (i = 0; i < cbItem; i++)
3350 {
3351 aVal[i] = (aVal[i] >> b) | (aVal[i] << (8 - b));
3352 bit_mask = pData->gr[8] & aVal[i];
3353 bit_mask |= bit_mask << 8;
3354 bit_mask |= bit_mask << 16;
3355 aVal[i] = mask16[pData->gr[0]];
3356
3357 APPLY_LOGICAL_AND_MASK(pData, aVal[i], bit_mask);
3358 }
3359 break;
3360 }
3361
3362 /* mask data according to sr[2] */
3363 write_mask = mask16[pData->sr[2]];
3364
3365 /* actually write data */
3366 if (cbItem == 1)
3367 {
3368 /* The most frequently case is 1 byte I/O. */
3369 while (cItems-- > 0)
3370 {
3371 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[0] & write_mask);
3372 vga_set_dirty(pData, GCPhysAddr << 2);
3373 GCPhysAddr++;
3374 }
3375 }
3376 else if (cbItem == 2)
3377 {
3378 /* The second case is 2 bytes I/O. */
3379 while (cItems-- > 0)
3380 {
3381 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[0] & write_mask);
3382 vga_set_dirty(pData, GCPhysAddr << 2);
3383 GCPhysAddr++;
3384
3385 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[1] & write_mask);
3386 vga_set_dirty(pData, GCPhysAddr << 2);
3387 GCPhysAddr++;
3388 }
3389 }
3390 else
3391 {
3392 /* And the rest is 4 bytes. */
3393 Assert(cbItem == 4);
3394 while (cItems-- > 0)
3395 for (i = 0; i < cbItem; i++)
3396 {
3397 ((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] = (((uint32_t *)pData->CTXSUFF(vram_ptr))[GCPhysAddr] & ~write_mask) | (aVal[i] & write_mask);
3398 vga_set_dirty(pData, GCPhysAddr << 2);
3399 GCPhysAddr++;
3400 }
3401 }
3402 }
3403 return VINF_SUCCESS;
3404}
3405#undef APPLY_LOGICAL_AND_MASK
3406
3407
3408/**
3409 * Legacy VGA memory (0xa0000 - 0xbffff) read hook, to be called from IOM.
3410 *
3411 * @returns VBox status code.
3412 * @param pDevIns Pointer device instance.
3413 * @param pvUser User argument - ignored.
3414 * @param GCPhysAddr Physical address of memory to read.
3415 * @param pv Where to store readed data.
3416 * @param cb Bytes to read.
3417 */
3418PDMBOTHCBDECL(int) vgaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3419{
3420 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3421 STAM_PROFILE_START(&pData->StatGCMemoryRead, a);
3422 NOREF(pvUser);
3423 switch (cb)
3424 {
3425 case 1:
3426 *(uint8_t *)pv = vga_mem_readb(pData, GCPhysAddr); break;
3427 case 2:
3428 *(uint16_t *)pv = vga_mem_readb(pData, GCPhysAddr)
3429 | (vga_mem_readb(pData, GCPhysAddr + 1) << 8);
3430 break;
3431 case 4:
3432 *(uint32_t *)pv = vga_mem_readb(pData, GCPhysAddr)
3433 | (vga_mem_readb(pData, GCPhysAddr + 1) << 8)
3434 | (vga_mem_readb(pData, GCPhysAddr + 2) << 16)
3435 | (vga_mem_readb(pData, GCPhysAddr + 3) << 24);
3436 break;
3437
3438 default:
3439 {
3440 uint8_t *pu8Data = (uint8_t *)pv;
3441 while (cb-- > 0)
3442 *pu8Data++ = vga_mem_readb(pData, GCPhysAddr++);
3443 }
3444 }
3445 STAM_PROFILE_STOP(&pData->StatGCMemoryRead, a);
3446 return VINF_SUCCESS;
3447}
3448
3449/**
3450 * Legacy VGA memory (0xa0000 - 0xbffff) write hook, to be called from IOM.
3451 *
3452 * @returns VBox status code.
3453 * @param pDevIns Pointer device instance.
3454 * @param pvUser User argument - ignored.
3455 * @param GCPhysAddr Physical address of memory to write.
3456 * @param pv Pointer to data.
3457 * @param cb Bytes to write.
3458 */
3459PDMBOTHCBDECL(int) vgaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3460{
3461 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3462 uint8_t *pu8 = (uint8_t *)pv;
3463 int rc = VINF_SUCCESS;
3464 STAM_PROFILE_START(&pData->StatGCMemoryWrite, a);
3465
3466 switch (cb)
3467 {
3468 case 1:
3469 rc = vga_mem_writeb(pData, GCPhysAddr, *pu8);
3470 break;
3471#if 1
3472 case 2:
3473 rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3474 if (RT_LIKELY(rc == VINF_SUCCESS))
3475 rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3476 break;
3477 case 4:
3478 rc = vga_mem_writeb(pData, GCPhysAddr + 0, pu8[0]);
3479 if (RT_LIKELY(rc == VINF_SUCCESS))
3480 rc = vga_mem_writeb(pData, GCPhysAddr + 1, pu8[1]);
3481 if (RT_LIKELY(rc == VINF_SUCCESS))
3482 rc = vga_mem_writeb(pData, GCPhysAddr + 2, pu8[2]);
3483 if (RT_LIKELY(rc == VINF_SUCCESS))
3484 rc = vga_mem_writeb(pData, GCPhysAddr + 3, pu8[3]);
3485 break;
3486#else
3487 case 2:
3488 rc = vgaMMIOFill(pDevIns, GCPhysAddr, *(uint16_t *)pv, 2, 1);
3489 break;
3490 case 4:
3491 rc = vgaMMIOFill(pDevIns, GCPhysAddr, *(uint32_t *)pv, 4, 1);
3492 break;
3493#endif
3494 default:
3495 while (cb-- > 0 && rc == VINF_SUCCESS)
3496 rc = vga_mem_writeb(pData, GCPhysAddr++, *pu8++);
3497 break;
3498
3499 }
3500 STAM_PROFILE_STOP(&pData->StatGCMemoryWrite, a);
3501 return rc;
3502}
3503
3504
3505/**
3506 * Handle LFB access.
3507 * @returns VBox status code.
3508 * @param pVM VM handle.
3509 * @param pData VGA device instance data.
3510 * @param GCPhys The access physical address.
3511 * @param GCPtr The access virtual address (only GC).
3512 */
3513static int vgaLFBAccess(PVM pVM, PVGASTATE pData, RTGCPHYS GCPhys, RTGCPTR GCPtr)
3514{
3515 int rc;
3516
3517 /*
3518 * Set page dirty bit.
3519 */
3520 vga_set_dirty(pData, GCPhys - pData->GCPhysVRAM);
3521 pData->fLFBUpdated = true;
3522
3523 /*
3524 * Turn of the write handler for this particular page and make it R/W.
3525 * Then return telling the caller to restart the guest instruction.
3526 * ASSUME: the guest always maps video memory RW.
3527 */
3528 rc = PGMHandlerPhysicalPageTempOff(pVM, pData->GCPhysVRAM, GCPhys);
3529 if (VBOX_SUCCESS(rc))
3530 {
3531#ifndef IN_RING3
3532 rc = PGMShwModifyPage(pVM, GCPtr, 1, X86_PTE_RW, ~(uint64_t)X86_PTE_RW);
3533 if (VBOX_SUCCESS(rc))
3534 return VINF_SUCCESS;
3535 else
3536 AssertMsgFailed(("PGMShwModifyPage -> rc=%d\n", rc));
3537#else /* IN_RING3 : We don't have any virtual page address of the access here. */
3538 Assert(GCPtr == 0);
3539 return VINF_SUCCESS;
3540#endif
3541 }
3542 else
3543 AssertMsgFailed(("PGMHandlerPhysicalPageTempOff -> rc=%d\n", rc));
3544
3545 return rc;
3546}
3547
3548
3549#ifdef IN_GC
3550/**
3551 * #PF Handler for VBE LFB access.
3552 *
3553 * @returns VBox status code (appropriate for GC return).
3554 * @param pVM VM Handle.
3555 * @param uErrorCode CPU Error code.
3556 * @param pRegFrame Trap register frame.
3557 * @param pvFault The fault address (cr2).
3558 * @param GCPhysFault The GC physical address corresponding to pvFault.
3559 * @param pvUser User argument, ignored.
3560 */
3561PDMBOTHCBDECL(int) vgaGCLFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3562{
3563 PVGASTATE pData = (PVGASTATE)pvUser;
3564 Assert(pData);
3565 Assert(GCPhysFault >= pData->GCPhysVRAM);
3566 AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3567
3568 return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3569}
3570
3571#elif IN_RING0
3572
3573/**
3574 * #PF Handler for VBE LFB access.
3575 *
3576 * @returns VBox status code (appropriate for GC return).
3577 * @param pVM VM Handle.
3578 * @param uErrorCode CPU Error code.
3579 * @param pRegFrame Trap register frame.
3580 * @param pvFault The fault address (cr2).
3581 * @param GCPhysFault The GC physical address corresponding to pvFault.
3582 * @param pvUser User argument, ignored.
3583 */
3584PDMBOTHCBDECL(int) vgaR0LFBAccessHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)
3585{
3586 PVGASTATE pData = (PVGASTATE)pvUser;
3587 Assert(pData);
3588 Assert(GCPhysFault >= pData->GCPhysVRAM);
3589 AssertMsg(uErrorCode & X86_TRAP_PF_RW, ("uErrorCode=%#x\n", uErrorCode));
3590
3591 return vgaLFBAccess(pVM, pData, GCPhysFault, pvFault);
3592}
3593
3594#else /* IN_RING3 */
3595
3596/**
3597 * HC access handler for the LFB.
3598 *
3599 * @returns VINF_SUCCESS if the handler have carried out the operation.
3600 * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
3601 * @param pVM VM Handle.
3602 * @param GCPhys The physical address the guest is writing to.
3603 * @param pvPhys The HC mapping of that address.
3604 * @param pvBuf What the guest is reading/writing.
3605 * @param cbBuf How much it's reading/writing.
3606 * @param enmAccessType The access type.
3607 * @param pvUser User argument.
3608 */
3609static DECLCALLBACK(int) vgaR3LFBAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
3610{
3611 PVGASTATE pData = (PVGASTATE)pvUser;
3612 int rc;
3613 Assert(pData);
3614 Assert(GCPhys >= pData->GCPhysVRAM);
3615 rc = vgaLFBAccess(pVM, pData, GCPhys, 0);
3616 if (VBOX_SUCCESS(rc))
3617 return VINF_PGM_HANDLER_DO_DEFAULT;
3618 AssertMsg(rc <= VINF_SUCCESS, ("rc=%Vrc\n", rc));
3619 return rc;
3620}
3621#endif /* IN_RING3 */
3622
3623
3624/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
3625
3626#ifdef IN_RING3
3627
3628# ifdef VBE_NEW_DYN_LIST
3629/**
3630 * Port I/O Handler for VBE Extra OUT operations.
3631 *
3632 * @returns VBox status code.
3633 *
3634 * @param pDevIns The device instance.
3635 * @param pvUser User argument - ignored.
3636 * @param Port Port number used for the IN operation.
3637 * @param u32 The value to output.
3638 * @param cb The value size in bytes.
3639 */
3640PDMBOTHCBDECL(int) vbeIOPortWriteVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3641{
3642 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3643 NOREF(pvUser);
3644 NOREF(Port);
3645
3646 if (cb == 2)
3647 {
3648 Log(("vbeIOPortWriteVBEExtra: addr=%#RX32\n", u32));
3649 pData->u16VBEExtraAddress = u32;
3650 return VINF_SUCCESS;
3651 }
3652
3653 Log(("vbeIOPortWriteVBEExtra: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
3654 return VINF_SUCCESS;
3655}
3656
3657
3658/**
3659 * Port I/O Handler for VBE Extra IN operations.
3660 *
3661 * @returns VBox status code.
3662 *
3663 * @param pDevIns The device instance.
3664 * @param pvUser User argument - ignored.
3665 * @param Port Port number used for the IN operation.
3666 * @param pu32 Where to store the result.
3667 * @param cb Number of bytes read.
3668 */
3669PDMBOTHCBDECL(int) vbeIOPortReadVBEExtra(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
3670{
3671 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3672 NOREF(pvUser);
3673 NOREF(Port);
3674
3675 if (pData->u16VBEExtraAddress == 0xffff)
3676 {
3677 Log(("vbeIOPortReadVBEExtra: Requested number of 64k video banks\n"));
3678 *pu32 = pData->vram_size / _64K;
3679 return VINF_SUCCESS;
3680 }
3681
3682 if ( pData->u16VBEExtraAddress >= pData->cbVBEExtraData
3683 || pData->u16VBEExtraAddress + cb > pData->cbVBEExtraData)
3684 {
3685 *pu32 = 0;
3686 Log(("vbeIOPortReadVBEExtra: Requested address is out of VBE data!!! Address=%#x(%d) cbVBEExtraData=%#x(%d)\n",
3687 pData->u16VBEExtraAddress, pData->u16VBEExtraAddress, pData->cbVBEExtraData, pData->cbVBEExtraData));
3688 return VINF_SUCCESS;
3689 }
3690
3691 if (cb == 1)
3692 {
3693 *pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress] & 0xFF;
3694
3695 Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3696 return VINF_SUCCESS;
3697 }
3698
3699 if (cb == 2)
3700 {
3701 *pu32 = pData->pu8VBEExtraData[pData->u16VBEExtraAddress]
3702 | pData->pu8VBEExtraData[pData->u16VBEExtraAddress + 1] << 8;
3703
3704 Log(("vbeIOPortReadVBEExtra: cb=%#x %.*Vhxs\n", cb, cb, pu32));
3705 return VINF_SUCCESS;
3706 }
3707 Log(("vbeIOPortReadVBEExtra: Invalid cb=%d read from the VBE Extra port!!!\n", cb));
3708 return VERR_IOM_IOPORT_UNUSED;
3709}
3710# endif /* VBE_NEW_DYN_LIST */
3711
3712
3713/**
3714 * Parse the logo bitmap data at init time.
3715 *
3716 * @returns VBox status code.
3717 *
3718 * @param pData The VGA instance data.
3719 */
3720static int vbeParseBitmap(PVGASTATE pData)
3721{
3722 uint16_t i;
3723 PBMPINFO bmpInfo;
3724 POS2HDR pOs2Hdr;
3725 POS22HDR pOs22Hdr;
3726 PWINHDR pWinHdr;
3727
3728 /*
3729 * Get bitmap header data
3730 */
3731 bmpInfo = (PBMPINFO)(pData->pu8Logo + sizeof(LOGOHDR));
3732 pWinHdr = (PWINHDR)(pData->pu8Logo + sizeof(LOGOHDR) + sizeof(BMPINFO));
3733
3734 if (bmpInfo->Type == BMP_ID)
3735 {
3736 switch (pWinHdr->Size)
3737 {
3738 case BMP_HEADER_OS21:
3739 pOs2Hdr = (POS2HDR)pWinHdr;
3740 pData->cxLogo = pOs2Hdr->Width;
3741 pData->cyLogo = pOs2Hdr->Height;
3742 pData->cLogoPlanes = pOs2Hdr->Planes;
3743 pData->cLogoBits = pOs2Hdr->BitCount;
3744 pData->LogoCompression = BMP_COMPRESS_NONE;
3745 pData->cLogoUsedColors = 0;
3746 break;
3747
3748 case BMP_HEADER_OS22:
3749 pOs22Hdr = (POS22HDR)pWinHdr;
3750 pData->cxLogo = pOs22Hdr->Width;
3751 pData->cyLogo = pOs22Hdr->Height;
3752 pData->cLogoPlanes = pOs22Hdr->Planes;
3753 pData->cLogoBits = pOs22Hdr->BitCount;
3754 pData->LogoCompression = pOs22Hdr->Compression;
3755 pData->cLogoUsedColors = pOs22Hdr->ClrUsed;
3756 break;
3757
3758 case BMP_HEADER_WIN3:
3759 pData->cxLogo = pWinHdr->Width;
3760 pData->cyLogo = pWinHdr->Height;
3761 pData->cLogoPlanes = pWinHdr->Planes;
3762 pData->cLogoBits = pWinHdr->BitCount;
3763 pData->LogoCompression = pWinHdr->Compression;
3764 pData->cLogoUsedColors = pWinHdr->ClrUsed;
3765 break;
3766
3767 default:
3768 AssertMsgFailed(("Unsupported bitmap header.\n"));
3769 break;
3770 }
3771
3772 if (pData->cxLogo > LOGO_MAX_WIDTH || pData->cyLogo > LOGO_MAX_HEIGHT)
3773 {
3774 AssertMsgFailed(("Bitmap %ux%u is too big.\n", pData->cxLogo, pData->cyLogo));
3775 return VERR_INVALID_PARAMETER;
3776 }
3777
3778 if (pData->cLogoPlanes != 1)
3779 {
3780 AssertMsgFailed(("Bitmap planes %u != 1.\n", pData->cLogoPlanes));
3781 return VERR_INVALID_PARAMETER;
3782 }
3783
3784 if (pData->cLogoBits != 4 && pData->cLogoBits != 8 && pData->cLogoBits != 24)
3785 {
3786 AssertMsgFailed(("Unsupported %u depth.\n", pData->cLogoBits));
3787 return VERR_INVALID_PARAMETER;
3788 }
3789
3790 if (pData->cLogoUsedColors > 256)
3791 {
3792 AssertMsgFailed(("Unsupported %u colors.\n", pData->cLogoUsedColors));
3793 return VERR_INVALID_PARAMETER;
3794 }
3795
3796 if (pData->LogoCompression != BMP_COMPRESS_NONE)
3797 {
3798 AssertMsgFailed(("Unsupported %u compression.\n", pData->LogoCompression));
3799 return VERR_INVALID_PARAMETER;
3800 }
3801
3802 /*
3803 * Read bitmap palette
3804 */
3805 if (!pData->cLogoUsedColors)
3806 pData->cLogoPalEntries = 1 << (pData->cLogoPlanes * pData->cLogoBits);
3807 else
3808 pData->cLogoPalEntries = pData->cLogoUsedColors;
3809
3810 if (pData->cLogoPalEntries)
3811 {
3812 const uint8_t *pu8Pal = pData->pu8Logo + sizeof(LOGOHDR) + sizeof(BMPINFO) + pWinHdr->Size; /* ASSUMES Size location (safe) */
3813
3814 for (i = 0; i < pData->cLogoPalEntries; i++)
3815 {
3816 uint16_t j;
3817 uint32_t u32Pal = 0;
3818
3819 for (j = 0; j < 3; j++)
3820 {
3821 uint8_t b = *pu8Pal++;
3822 u32Pal <<= 8;
3823 u32Pal |= b;
3824 }
3825
3826 pu8Pal++; /* skip unused byte */
3827 pData->au32LogoPalette[i] = u32Pal;
3828 }
3829 }
3830
3831 /*
3832 * Bitmap data offset
3833 */
3834 pData->pu8LogoBitmap = pData->pu8Logo + sizeof(LOGOHDR) + bmpInfo->Offset;
3835 }
3836
3837 return VINF_SUCCESS;
3838}
3839
3840
3841/**
3842 * Show logo bitmap data.
3843 *
3844 * @returns VBox status code.
3845 *
3846 * @param cbDepth Logo depth.
3847 * @param xLogo Logo X position.
3848 * @param yLogo Logo Y position.
3849 * @param cxLogo Logo width.
3850 * @param cyLogo Logo height.
3851 * @param iStep Fade in/fade out step.
3852 * @param pu32Palette Palette data.
3853 * @param pu8Src Source buffer.
3854 * @param pu8Dst Destination buffer.
3855 */
3856static void vbeShowBitmap(uint16_t cBits, uint16_t xLogo, uint16_t yLogo, uint16_t cxLogo, uint16_t cyLogo, uint8_t iStep,
3857 const uint32_t *pu32Palette, const uint8_t *pu8Src, uint8_t *pu8Dst)
3858{
3859 uint16_t i;
3860 size_t cbPadBytes = 0;
3861 size_t cbLineDst = LOGO_MAX_WIDTH * 4;
3862 uint16_t cyLeft = cyLogo;
3863
3864 pu8Dst += xLogo * 4 + yLogo * cbLineDst;
3865
3866 switch (cBits)
3867 {
3868 case 1:
3869 pu8Dst += cyLogo * cbLineDst;
3870 cbPadBytes = 0;
3871 break;
3872
3873 case 4:
3874 if (((cxLogo % 8) == 0) || ((cxLogo % 8) > 6))
3875 cbPadBytes = 0;
3876 else if ((cxLogo % 8) <= 2)
3877 cbPadBytes = 3;
3878 else if ((cxLogo % 8) <= 4)
3879 cbPadBytes = 2;
3880 else
3881 cbPadBytes = 1;
3882 break;
3883
3884 case 8:
3885 cbPadBytes = ((cxLogo % 4) == 0) ? 0 : (4 - (cxLogo % 4));
3886 break;
3887
3888 case 24:
3889 cbPadBytes = cxLogo % 4;
3890 break;
3891 }
3892
3893 uint8_t j = 0, c = 0;
3894
3895 while (cyLeft-- > 0)
3896 {
3897 uint8_t *pu8TmpPtr = pu8Dst;
3898
3899 if (cBits != 1)
3900 j = 0;
3901
3902 for (i = 0; i < cxLogo; i++)
3903 {
3904 uint8_t pix;
3905
3906 switch (cBits)
3907 {
3908 case 1:
3909 {
3910 if (!j)
3911 c = *pu8Src++;
3912
3913 pix = (c & 1) ? 0xFF : 0;
3914 c >>= 1;
3915
3916 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3917 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3918 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3919 *pu8TmpPtr++;
3920
3921 j = (j + 1) % 8;
3922 break;
3923 }
3924
3925 case 4:
3926 {
3927 if (!j)
3928 c = *pu8Src++;
3929
3930 pix = (c >> 4) & 0xF;
3931 c <<= 4;
3932
3933 uint32_t u32Pal = pu32Palette[pix];
3934
3935 pix = (u32Pal >> 16) & 0xFF;
3936 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3937 pix = (u32Pal >> 8) & 0xFF;
3938 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3939 pix = u32Pal & 0xFF;
3940 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3941 *pu8TmpPtr++;
3942
3943 j = (j + 1) % 2;
3944 break;
3945 }
3946
3947 case 8:
3948 {
3949 uint32_t u32Pal = pu32Palette[*pu8Src++];
3950
3951 pix = (u32Pal >> 16) & 0xFF;
3952 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3953 pix = (u32Pal >> 8) & 0xFF;
3954 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3955 pix = u32Pal & 0xFF;
3956 *pu8TmpPtr++ = pix * iStep / LOGO_SHOW_STEPS;
3957 *pu8TmpPtr++;
3958 break;
3959 }
3960
3961 case 24:
3962 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3963 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3964 *pu8TmpPtr++ = *pu8Src++ * iStep / LOGO_SHOW_STEPS;
3965 *pu8TmpPtr++;
3966 break;
3967 }
3968 }
3969
3970 pu8Dst -= cbLineDst;
3971 pu8Src += cbPadBytes;
3972 }
3973}
3974
3975
3976
3977
3978/**
3979 * Port I/O Handler for BIOS Logo OUT operations.
3980 *
3981 * @returns VBox status code.
3982 *
3983 * @param pDevIns The device instance.
3984 * @param pvUser User argument - ignored.
3985 * @param Port Port number used for the IN operation.
3986 * @param u32 The value to output.
3987 * @param cb The value size in bytes.
3988 */
3989PDMBOTHCBDECL(int) vbeIOPortWriteCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
3990{
3991 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
3992 NOREF(pvUser);
3993 NOREF(Port);
3994
3995 Log(("vbeIOPortWriteCMDLogo: cb=%d u32=%#04x(%#04d) (byte)\n", cb, u32, u32));
3996
3997 if (cb == 2)
3998 {
3999 /* Get the logo command */
4000 switch (u32 & 0xFF00)
4001 {
4002 case LOGO_CMD_SET_OFFSET:
4003 pData->offLogoData = u32 & 0xFF;
4004 break;
4005
4006 case LOGO_CMD_SHOW_BMP:
4007 {
4008 uint8_t iStep = u32 & 0xFF;
4009 const uint8_t *pu8Src = pData->pu8LogoBitmap;
4010 uint8_t *pu8Dst;
4011 PLOGOHDR pLogoHdr = (PLOGOHDR)pData->pu8Logo;
4012 uint32_t offDirty = 0;
4013 uint16_t xLogo = (LOGO_MAX_WIDTH - pData->cxLogo) / 2;
4014 uint16_t yLogo = LOGO_MAX_HEIGHT - (LOGO_MAX_HEIGHT - pData->cyLogo) / 2;
4015
4016 /* Check VRAM size */
4017 if (pData->vram_size < LOGO_MAX_SIZE)
4018 break;
4019
4020 if (pData->vram_size >= LOGO_MAX_SIZE * 2)
4021 pu8Dst = pData->vram_ptrHC + LOGO_MAX_SIZE;
4022 else
4023 pu8Dst = pData->vram_ptrHC;
4024
4025 /* Clear screen - except on power on... */
4026 if (!pData->fLogoClearScreen)
4027 {
4028 uint32_t *pu32TmpPtr = (uint32_t *)pu8Dst;
4029
4030 /* Clear vram */
4031 for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4032 {
4033 for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4034 *pu32TmpPtr++ = 0;
4035 }
4036 pData->fLogoClearScreen = true;
4037 }
4038
4039 /* Show the bitmap. */
4040 vbeShowBitmap(pData->cLogoBits, xLogo, yLogo,
4041 pData->cxLogo, pData->cyLogo,
4042 iStep, &pData->au32LogoPalette[0],
4043 pu8Src, pu8Dst);
4044
4045 /* Show the 'Press F12...' text. */
4046 if (pLogoHdr->fu8ShowBootMenu == 2)
4047 vbeShowBitmap(1, LOGO_F12TEXT_X, LOGO_F12TEXT_Y,
4048 LOGO_F12TEXT_WIDTH, LOGO_F12TEXT_HEIGHT,
4049 iStep, &pData->au32LogoPalette[0],
4050 &g_abLogoF12BootText[0], pu8Dst);
4051
4052 /* Blit the offscreen buffer. */
4053 if (pData->vram_size >= LOGO_MAX_SIZE * 2)
4054 {
4055 uint32_t *pu32TmpDst = (uint32_t *)pData->vram_ptrHC;
4056 uint32_t *pu32TmpSrc = (uint32_t *)(pData->vram_ptrHC + LOGO_MAX_SIZE);
4057 for (int i = 0; i < LOGO_MAX_WIDTH; i++)
4058 {
4059 for (int j = 0; j < LOGO_MAX_HEIGHT; j++)
4060 *pu32TmpDst++ = *pu32TmpSrc++;
4061 }
4062 }
4063
4064 /* Set the dirty flags. */
4065 while (offDirty <= LOGO_MAX_SIZE)
4066 {
4067 vga_set_dirty(pData, offDirty);
4068 offDirty += PAGE_SIZE;
4069 }
4070 break;
4071 }
4072
4073 default:
4074 Log(("vbeIOPortWriteCMDLogo: invalid command %d\n", u32));
4075 pData->LogoCommand = LOGO_CMD_NOP;
4076 break;
4077 }
4078
4079 return VINF_SUCCESS;
4080 }
4081
4082 Log(("vbeIOPortWriteCMDLogo: Ignoring invalid cb=%d writes to the VBE Extra port!!!\n", cb));
4083 return VINF_SUCCESS;
4084}
4085
4086
4087/**
4088 * Port I/O Handler for BIOS Logo IN operations.
4089 *
4090 * @returns VBox status code.
4091 *
4092 * @param pDevIns The device instance.
4093 * @param pvUser User argument - ignored.
4094 * @param Port Port number used for the IN operation.
4095 * @param pu32 Where to store the result.
4096 * @param cb Number of bytes read.
4097 */
4098PDMBOTHCBDECL(int) vbeIOPortReadCMDLogo(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
4099{
4100 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4101 NOREF(pvUser);
4102 NOREF(Port);
4103
4104 PRTUINT64U p;
4105
4106 if (pData->offLogoData + cb > pData->cbLogo)
4107 {
4108 Log(("vbeIOPortReadCMDLogo: Requested address is out of Logo data!!! offLogoData=%#x(%d) cbLogo=%#x(%d)\n",
4109 pData->offLogoData, pData->offLogoData, pData->cbLogo, pData->cbLogo));
4110 return VINF_SUCCESS;
4111 }
4112 p = (PRTUINT64U)&pData->pu8Logo[pData->offLogoData];
4113
4114 switch (cb)
4115 {
4116 case 1: *pu32 = p->au8[0]; break;
4117 case 2: *pu32 = p->au16[0]; break;
4118 case 4: *pu32 = p->au32[0]; break;
4119 //case 8: *pu32 = p->au64[0]; break;
4120 default: AssertFailed(); break;
4121 }
4122 Log(("vbeIOPortReadCMDLogo: LogoOffset=%#x(%d) cb=%#x %.*Vhxs\n", pData->offLogoData, pData->offLogoData, cb, cb, pu32));
4123
4124 pData->LogoCommand = LOGO_CMD_NOP;
4125 pData->offLogoData += cb;
4126
4127 return VINF_SUCCESS;
4128}
4129
4130
4131
4132
4133/* -=-=-=-=-=- Ring 3: VGA BIOS I/Os -=-=-=-=-=- */
4134
4135/**
4136 * Port I/O Handler for VGA BIOS IN operations.
4137 *
4138 * @returns VBox status code.
4139 *
4140 * @param pDevIns The device instance.
4141 * @param pvUser User argument - ignored.
4142 * @param Port Port number used for the IN operation.
4143 * @param pu32 Where to store the result.
4144 * @param cb Number of bytes read.
4145 */
4146static DECLCALLBACK(int) vgaIOPortReadBIOS(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
4147{
4148 NOREF(pDevIns);
4149 NOREF(pvUser);
4150 NOREF(Port);
4151 NOREF(pu32);
4152 NOREF(cb);
4153 return VERR_IOM_IOPORT_UNUSED;
4154}
4155
4156/**
4157 * Port I/O Handler for VGA BIOS OUT operations.
4158 *
4159 * @returns VBox status code.
4160 *
4161 * @param pDevIns The device instance.
4162 * @param pvUser User argument - ignored.
4163 * @param Port Port number used for the IN operation.
4164 * @param u32 The value to output.
4165 * @param cb The value size in bytes.
4166 */
4167static DECLCALLBACK(int) vgaIOPortWriteBIOS(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
4168{
4169 static int lastWasNotNewline = 0; /* We are only called in a single-threaded way */
4170 /*
4171 * VGA BIOS char printing.
4172 */
4173 if ( cb == 1
4174 && Port == VBE_PRINTF_PORT)
4175 {
4176#if 0
4177 switch (u32)
4178 {
4179 case '\r': Log(("vgabios: <return>\n")); break;
4180 case '\n': Log(("vgabios: <newline>\n")); break;
4181 case '\t': Log(("vgabios: <tab>\n")); break;
4182 default:
4183 Log(("vgabios: %c\n", u32));
4184 }
4185#else
4186 if (lastWasNotNewline == 0)
4187 Log(("vgabios: "));
4188 if (u32 != '\r') /* return - is only sent in conjunction with '\n' */
4189 Log(("%c", u32));
4190 if (u32 == '\n')
4191 lastWasNotNewline = 0;
4192 else
4193 lastWasNotNewline = 1;
4194#endif
4195 return VINF_SUCCESS;
4196 }
4197
4198 /* not in use. */
4199 return VINF_SUCCESS;
4200}
4201
4202
4203/* -=-=-=-=-=- Ring 3: IBase -=-=-=-=-=- */
4204
4205/**
4206 * Queries an interface to the driver.
4207 *
4208 * @returns Pointer to interface.
4209 * @returns NULL if the interface was not supported by the driver.
4210 * @param pInterface Pointer to this interface structure.
4211 * @param enmInterface The requested interface identification.
4212 * @thread Any thread.
4213 */
4214static DECLCALLBACK(void *) vgaPortQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
4215{
4216 PVGASTATE pData = (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Base));
4217 switch (enmInterface)
4218 {
4219 case PDMINTERFACE_BASE:
4220 return &pData->Base;
4221 case PDMINTERFACE_DISPLAY_PORT:
4222 return &pData->Port;
4223 default:
4224 return NULL;
4225 }
4226}
4227
4228
4229/* -=-=-=-=-=- Ring 3: Dummy IDisplayConnector -=-=-=-=-=- */
4230
4231/**
4232 * Resize the display.
4233 * This is called when the resolution changes. This usually happens on
4234 * request from the guest os, but may also happen as the result of a reset.
4235 *
4236 * @param pInterface Pointer to this interface.
4237 * @param cx New display width.
4238 * @param cy New display height
4239 * @thread The emulation thread.
4240 */
4241static DECLCALLBACK(int) vgaDummyResize(PPDMIDISPLAYCONNECTOR pInterface, uint32_t bpp, void *pvVRAM, uint32_t cbLine, uint32_t cx, uint32_t cy)
4242{
4243 return VINF_SUCCESS;
4244}
4245
4246
4247/**
4248 * Update a rectangle of the display.
4249 * PDMIDISPLAYPORT::pfnUpdateDisplay is the caller.
4250 *
4251 * @param pInterface Pointer to this interface.
4252 * @param x The upper left corner x coordinate of the rectangle.
4253 * @param y The upper left corner y coordinate of the rectangle.
4254 * @param cx The width of the rectangle.
4255 * @param cy The height of the rectangle.
4256 * @thread The emulation thread.
4257 */
4258static DECLCALLBACK(void) vgaDummyUpdateRect(PPDMIDISPLAYCONNECTOR pInterface, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4259{
4260}
4261
4262
4263/**
4264 * Refresh the display.
4265 *
4266 * The interval between these calls is set by
4267 * PDMIDISPLAYPORT::pfnSetRefreshRate(). The driver should call
4268 * PDMIDISPLAYPORT::pfnUpdateDisplay() if it wishes to refresh the
4269 * display. PDMIDISPLAYPORT::pfnUpdateDisplay calls pfnUpdateRect with
4270 * the changed rectangles.
4271 *
4272 * @param pInterface Pointer to this interface.
4273 * @thread The emulation thread.
4274 */
4275static DECLCALLBACK(void) vgaDummyRefresh(PPDMIDISPLAYCONNECTOR pInterface)
4276{
4277}
4278
4279
4280/* -=-=-=-=-=- Ring 3: IDisplayPort -=-=-=-=-=- */
4281
4282/** Converts a display port interface pointer to a vga state pointer. */
4283#define IDISPLAYPORT_2_VGASTATE(pInterface) ( (PVGASTATE)((uintptr_t)pInterface - RT_OFFSETOF(VGASTATE, Port)) )
4284
4285
4286/**
4287 * Update the display with any changed regions.
4288 *
4289 * @param pInterface Pointer to this interface.
4290 * @see PDMIKEYBOARDPORT::pfnUpdateDisplay() for details.
4291 */
4292static DECLCALLBACK(int) vgaPortUpdateDisplay(PPDMIDISPLAYPORT pInterface)
4293{
4294 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4295 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4296
4297#ifdef DEBUG_sunlover
4298 LogFlow(("vgaPortUpdateDisplay\n"));
4299#endif /* DEBUG_sunlover */
4300
4301 /* This should be called only in non VBVA mode. */
4302
4303 int rc = vga_update_display(pData);
4304 if (rc != VINF_SUCCESS)
4305 return rc;
4306
4307 if (pData->fHaveDirtyBits && pData->GCPhysVRAM && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4308 {
4309 PPDMDEVINS pDevIns = pData->pDevInsHC;
4310 PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4311 pData->fHaveDirtyBits = false;
4312 }
4313
4314 return VINF_SUCCESS;
4315}
4316
4317
4318/**
4319 * Update the entire display.
4320 *
4321 * @param pInterface Pointer to this interface.
4322 * @see PDMIKEYBOARDPORT::pfnUpdateDisplayAll() for details.
4323 */
4324static DECLCALLBACK(int) vgaPortUpdateDisplayAll(PPDMIDISPLAYPORT pInterface)
4325{
4326 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4327 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4328
4329 /* This is called both in VBVA mode and normal modes. */
4330
4331#ifdef DEBUG_sunlover
4332 LogFlow(("vgaPortUpdateDisplayAll\n"));
4333#endif /* DEBUG_sunlover */
4334
4335 pData->graphic_mode = -1; /* force full update */
4336
4337 int rc = vga_update_display(pData);
4338
4339 /* The dirty bits array has been just cleared, reset handlers as well. */
4340 if (pData->GCPhysVRAM && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4341 {
4342 PPDMDEVINS pDevIns = pData->pDevInsHC;
4343 PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4344 }
4345
4346 return rc;
4347}
4348
4349
4350/**
4351 * Sets the refresh rate and restart the timer.
4352 *
4353 * @returns VBox status code.
4354 * @param pInterface Pointer to this interface.
4355 * @param cMilliesInterval Number of millies between two refreshes.
4356 * @see PDMIKEYBOARDPORT::pfnSetRefreshRate() for details.
4357 */
4358static DECLCALLBACK(int) vgaPortSetRefreshRate(PPDMIDISPLAYPORT pInterface, uint32_t cMilliesInterval)
4359{
4360 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4361
4362 pData->cMilliesRefreshInterval = cMilliesInterval;
4363 if (cMilliesInterval)
4364 return TMTimerSetMillies(pData->RefreshTimer, cMilliesInterval);
4365 return TMTimerStop(pData->RefreshTimer);
4366}
4367
4368
4369/** @copydoc PDMIDISPLAYPORT::pfnQueryColorDepth */
4370static DECLCALLBACK(int) vgaPortQueryColorDepth(PPDMIDISPLAYPORT pInterface, uint32_t *pcBits)
4371{
4372 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4373
4374 if (!pcBits)
4375 return VERR_INVALID_PARAMETER;
4376 *pcBits = vga_get_bpp(pData);
4377 return VINF_SUCCESS;
4378}
4379
4380/**
4381 * Create a 32-bbp snapshot of the display.
4382 *
4383 * @param pInterface Pointer to this interface.
4384 * @param pvData Pointer the buffer to copy the bits to.
4385 * @param cbData Size of the buffer.
4386 * @param pcx Where to store the width of the bitmap. (optional)
4387 * @param pcy Where to store the height of the bitmap. (optional)
4388 * @param pcbData Where to store the actual size of the bitmap. (optional)
4389 * @see PDMIKEYBOARDPORT::pfnSnapshot() for details.
4390 */
4391static DECLCALLBACK(int) vgaPortSnapshot(PPDMIDISPLAYPORT pInterface, void *pvData, size_t cbData, uint32_t *pcx, uint32_t *pcy, size_t *pcbData)
4392{
4393 /* @todo r=sunlover: replace the method with a direct VRAM rendering like in vgaPortUpdateDisplayRect. */
4394 PPDMIDISPLAYCONNECTOR pConnector;
4395 PDMIDISPLAYCONNECTOR Connector;
4396 int32_t graphic_mode;
4397 uint32_t fRenderVRAM;
4398 size_t cbRequired;
4399 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4400 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4401 LogFlow(("vgaPortSnapshot: pvData=%p cbData=%d pcx=%p pcy=%p pcbData=%p\n", pvData, cbData, pcx, pcy, pcbData));
4402
4403 /*
4404 * Validate input.
4405 */
4406 if (!pvData)
4407 return VERR_INVALID_PARAMETER;
4408
4409 /*
4410 * Do a regular refresh first to resolve any pending resize issues.
4411 *
4412 * 20060317 It used to be pfnUpdateDisplay, but by VBVA design
4413 * only pfnUpdateDisplayAll is allowed to be called in VBVA mode.
4414 * Also since the goal here is to have updated display for screenshot,
4415 * the UpdateDisplayAll is even more logical to call. (sunlover)
4416 */
4417 pInterface->pfnUpdateDisplayAll(pInterface);
4418
4419 /*
4420 * Validate the buffer size.
4421 */
4422 cbRequired = RT_ALIGN_Z(pData->last_scr_width, 4) * pData->last_scr_height * 4;
4423 if (cbRequired > cbData)
4424 {
4425 Log(("vgaPortSnapshot: %d bytes are required, a buffer of %d bytes is profiled.\n", cbRequired, cbData));
4426 return VERR_BUFFER_OVERFLOW;
4427 }
4428
4429 /*
4430 * Temporarily replace the display connector interface with a fake one.
4431 */
4432 Connector.pu8Data = (uint8_t*)pvData;
4433 Connector.cBits = 32;
4434 Connector.cx = pData->pDrv->cx;
4435 Connector.cy = pData->pDrv->cy;
4436 Connector.cbScanline = RT_ALIGN_32(Connector.cx, 4) * 4;
4437 Connector.pfnRefresh = vgaDummyRefresh;
4438 Connector.pfnResize = vgaDummyResize;
4439 Connector.pfnUpdateRect = vgaDummyUpdateRect;
4440
4441 /* save & replace state data. */
4442 pConnector = pData->pDrv;
4443 pData->pDrv = &Connector;
4444 graphic_mode = pData->graphic_mode;
4445 pData->graphic_mode = -1; /* force a full refresh. */
4446 fRenderVRAM = pData->fRenderVRAM;
4447 pData->fRenderVRAM = 1; /* force the guest VRAM rendering to the given buffer. */
4448
4449 /* make the snapshot. */
4450 int rc = vga_update_display(pData);
4451
4452 /* restore */
4453 pData->pDrv = pConnector;
4454 pData->graphic_mode = graphic_mode;
4455 pData->fRenderVRAM = fRenderVRAM;
4456
4457 if (rc != VINF_SUCCESS)
4458 return rc;
4459
4460 /*
4461 * Return the result.
4462 */
4463 if (pcx)
4464 *pcx = Connector.cx;
4465 if (pcy)
4466 *pcy = Connector.cy;
4467 if (pcbData)
4468 *pcbData = cbRequired;
4469 LogFlow(("vgaPortSnapshot: returns VINF_SUCCESS (cx=%d cy=%d cbData=%d)\n", Connector.cx, Connector.cy, cbRequired));
4470 return VINF_SUCCESS;
4471}
4472
4473
4474/**
4475 * Copy bitmap to the display.
4476 *
4477 * @param pInterface Pointer to this interface.
4478 * @param pvData Pointer to the bitmap bits.
4479 * @param x The upper left corner x coordinate of the destination rectangle.
4480 * @param y The upper left corner y coordinate of the destination rectangle.
4481 * @param cx The width of the source and destination rectangles.
4482 * @param cy The height of the source and destination rectangles.
4483 * @see PDMIDISPLAYPORT::pfnDisplayBlt() for details.
4484 */
4485static DECLCALLBACK(int) vgaPortDisplayBlt(PPDMIDISPLAYPORT pInterface, const void *pvData, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
4486{
4487 PVGASTATE pData = IDISPLAYPORT_2_VGASTATE(pInterface);
4488 int rc = VINF_SUCCESS;
4489 PDMDEV_ASSERT_EMT(VGASTATE2DEVINS(pData));
4490 LogFlow(("vgaPortDisplayBlt: pvData=%p x=%d y=%d cx=%d cy=%d\n", pvData, x, y, cx, cy));
4491
4492 /*
4493 * Validate input.
4494 */
4495 if ( pvData
4496 && x < pData->pDrv->cx
4497 && cx <= pData->pDrv->cx
4498 && cx + x <= pData->pDrv->cx
4499 && y < pData->pDrv->cy
4500 && cy <= pData->pDrv->cy
4501 && cy + y <= pData->pDrv->cy)
4502 {
4503 /*
4504 * Determin bytes per pixel in the destination buffer.
4505 */
4506 size_t cbPixelDst = 0;
4507 switch (pData->pDrv->cBits)
4508 {
4509 case 8:
4510 cbPixelDst = 1;
4511 break;
4512 case 15:
4513 case 16:
4514 cbPixelDst = 2;
4515 break;
4516 case 24:
4517 cbPixelDst = 3;
4518 break;
4519 case 32:
4520 cbPixelDst = 4;
4521 break;
4522 default:
4523 rc = VERR_INVALID_PARAMETER;
4524 break;
4525 }
4526 if (VBOX_SUCCESS(rc))
4527 {
4528 /*
4529 * The blitting loop.
4530 */
4531 size_t cbLineSrc = RT_ALIGN_Z(cx, 4) * 4;
4532 uint8_t *pu8Src = (uint8_t *)pvData;
4533 size_t cbLineDst = pData->pDrv->cbScanline;
4534 uint8_t *pu8Dst = pData->pDrv->pu8Data + y * cbLineDst + x * cbPixelDst;
4535 uint32_t cyLeft = cy;
4536 vga_draw_line_func *pfnVgaDrawLine = vga_draw_line_table[VGA_DRAW_LINE32 * 4 + get_depth_index(pData->pDrv->cBits)];
4537 Assert(pfnVgaDrawLine);
4538 while (cyLeft-- > 0)
4539 {
4540 pfnVgaDrawLine(pData, pu8Dst, pu8Src, cx);
4541 pu8Dst += cbLineDst;
4542 pu8Src += cbLineSrc;
4543 }
4544
4545 /*
4546 * Invalidate the area.
4547 */
4548 pData->pDrv->pfnUpdateRect(pData->pDrv, x, y, cx, cy);
4549 }
4550 }
4551 else
4552 rc = VERR_INVALID_PARAMETER;
4553
4554 LogFlow(("vgaPortDisplayBlt: returns %Vrc\n", rc));
4555 return rc;
4556}
4557
4558static DECLCALLBACK(void) vgaPortUpdateDisplayRect (PPDMIDISPLAYPORT pInterface, int32_t x, int32_t y, uint32_t w, uint32_t h)
4559{
4560 uint32_t v;
4561 vga_draw_line_func *vga_draw_line;
4562
4563 uint32_t cbPixelDst;
4564 uint32_t cbLineDst;
4565 uint8_t *pu8Dst;
4566
4567 uint32_t cbPixelSrc;
4568 uint32_t cbLineSrc;
4569 uint8_t *pu8Src;
4570
4571 uint32_t u32OffsetSrc, u32Dummy;
4572
4573 PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
4574
4575#ifdef DEBUG_sunlover
4576 LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d\n", x, y, w, h));
4577#endif /* DEBUG_sunlover */
4578
4579 Assert(pInterface);
4580 Assert(s->pDrv);
4581 Assert(s->pDrv->pu8Data);
4582
4583 /* Check if there is something to do at all. */
4584 if (!s->fRenderVRAM)
4585 {
4586 /* The framebuffer uses the guest VRAM directly. */
4587#ifdef DEBUG_sunlover
4588 LogFlow(("vgaPortUpdateDisplayRect: nothing to do fRender is false.\n"));
4589#endif /* DEBUG_sunlover */
4590 return;
4591 }
4592
4593 /* Correct negative x and y coordinates. */
4594 if (x < 0)
4595 {
4596 x += w; /* Compute xRight which is also the new width. */
4597 w = (x < 0) ? 0 : x;
4598 x = 0;
4599 }
4600
4601 if (y < 0)
4602 {
4603 y += h; /* Compute yBottom, which is also the new height. */
4604 h = (y < 0) ? 0 : y;
4605 y = 0;
4606 }
4607
4608 /* Also check if coords are greater than the display resolution. */
4609 if (x + w > s->pDrv->cx)
4610 {
4611#ifndef VBOX
4612 w = s->pDrv->cx > x? s->pDrv->cx - x: 0;
4613#else
4614 // x < 0 is not possible here
4615 w = s->pDrv->cx > (uint32_t)x? s->pDrv->cx - x: 0;
4616#endif
4617 }
4618
4619 if (y + h > s->pDrv->cy)
4620 {
4621#ifndef VBOX
4622 h = s->pDrv->cy > y? s->pDrv->cy - y: 0;
4623#else
4624 // y < 0 is not possible here
4625 h = s->pDrv->cy > (uint32_t)y? s->pDrv->cy - y: 0;
4626#endif
4627 }
4628
4629#ifdef DEBUG_sunlover
4630 LogFlow(("vgaPortUpdateDisplayRect: %d,%d %dx%d (corrected coords)\n", x, y, w, h));
4631#endif /* DEBUG_sunlover */
4632
4633 /* Check if there is something to do at all. */
4634 if (w == 0 || h == 0)
4635 {
4636 /* Empty rectangle. */
4637#ifdef DEBUG_sunlover
4638 LogFlow(("vgaPortUpdateDisplayRect: nothing to do: %dx%d\n", w, h));
4639#endif /* DEBUG_sunlover */
4640 return;
4641 }
4642
4643 /** @todo This method should be made universal and not only for VBVA.
4644 * VGA_DRAW_LINE* must be selected and src/dst address calculation
4645 * changed.
4646 */
4647
4648 /* Choose the rendering function. */
4649 switch(s->get_bpp(s))
4650 {
4651 default:
4652 case 0:
4653 /* A LFB mode is already disabled, but the callback is still called
4654 * by Display because VBVA buffer is being flushed.
4655 * Nothing to do, just return.
4656 */
4657 return;
4658 case 8:
4659 v = VGA_DRAW_LINE8;
4660 break;
4661 case 15:
4662 v = VGA_DRAW_LINE15;
4663 break;
4664 case 16:
4665 v = VGA_DRAW_LINE16;
4666 break;
4667 case 24:
4668 v = VGA_DRAW_LINE24;
4669 break;
4670 case 32:
4671 v = VGA_DRAW_LINE32;
4672 break;
4673 }
4674
4675 vga_draw_line = vga_draw_line_table[v * 4 + get_depth_index(s->pDrv->cBits)];
4676
4677 /* Compute source and destination addresses and pitches. */
4678 cbPixelDst = (s->pDrv->cBits + 7) / 8;
4679 cbLineDst = s->pDrv->cbScanline;
4680 pu8Dst = s->pDrv->pu8Data + y * cbLineDst + x * cbPixelDst;
4681
4682 cbPixelSrc = (s->get_bpp(s) + 7) / 8;
4683 s->get_offsets (s, &cbLineSrc, &u32OffsetSrc, &u32Dummy);
4684
4685 /* Assume that rendering is performed only on visible part of VRAM.
4686 * This is true because coordinates were verified.
4687 */
4688 pu8Src = s->vram_ptrHC;
4689 pu8Src += u32OffsetSrc + y * cbLineSrc + x * cbPixelSrc;
4690
4691 /* Render VRAM to framebuffer. */
4692
4693#ifdef DEBUG_sunlover
4694 LogFlow(("vgaPortUpdateDisplayRect: dst: %p, %d, %d. src: %p, %d, %d\n", pu8Dst, cbLineDst, cbPixelDst, pu8Src, cbLineSrc, cbPixelSrc));
4695#endif /* DEBUG_sunlover */
4696
4697 while (h-- > 0)
4698 {
4699 vga_draw_line (s, pu8Dst, pu8Src, w);
4700 pu8Dst += cbLineDst;
4701 pu8Src += cbLineSrc;
4702 }
4703
4704#ifdef DEBUG_sunlover
4705 LogFlow(("vgaPortUpdateDisplayRect: completed.\n"));
4706#endif /* DEBUG_sunlover */
4707}
4708
4709static DECLCALLBACK(void) vgaPortSetRenderVRAM(PPDMIDISPLAYPORT pInterface, bool fRender)
4710{
4711 PVGASTATE s = IDISPLAYPORT_2_VGASTATE(pInterface);
4712
4713 LogFlow(("vgaPortSetRenderVRAM: fRender = %d\n", fRender));
4714
4715 s->fRenderVRAM = fRender;
4716}
4717
4718
4719static DECLCALLBACK(void) vgaTimerRefresh(PPDMDEVINS pDevIns, PTMTIMER pTimer)
4720{
4721 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4722 if (pData->pDrv)
4723 pData->pDrv->pfnRefresh(pData->pDrv);
4724 if (pData->cMilliesRefreshInterval)
4725 TMTimerSetMillies(pTimer, pData->cMilliesRefreshInterval);
4726}
4727
4728
4729/* -=-=-=-=-=- Ring 3: PCI Device -=-=-=-=-=- */
4730
4731/**
4732 * Callback function for unmapping and/or mapping the VRAM MMIO2 region (called by the PCI bus).
4733 *
4734 * @return VBox status code.
4735 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4736 * @param iRegion The region number.
4737 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4738 * I/O port, else it's a physical address.
4739 * This address is *NOT* relative to pci_mem_base like earlier!
4740 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4741 */
4742static DECLCALLBACK(int) vgaR3IORegionMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4743{
4744 int rc;
4745 PPDMDEVINS pDevIns = pPciDev->pDevIns;
4746 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4747 LogFlow(("vgaR3IORegionMap: iRegion=%d GCPhysAddress=%VGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
4748 AssertReturn(iRegion == 0 && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);
4749
4750 if (GCPhysAddress != NIL_RTGCPHYS)
4751 {
4752 /*
4753 * Mapping the VRAM.
4754 */
4755 rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
4756 AssertRC(rc);
4757 if (RT_SUCCESS(rc))
4758 {
4759 rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
4760 PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,
4761 GCPhysAddress, GCPhysAddress + (pData->vram_size - 1),
4762 vgaR3LFBAccessHandler, pData,
4763 g_DeviceVga.szR0Mod, "vgaR0LFBAccessHandler", pDevIns->pvInstanceDataR0,
4764 g_DeviceVga.szGCMod, "vgaGCLFBAccessHandler", pDevIns->pvInstanceDataGC,
4765 "VGA LFB");
4766 AssertRC(rc);
4767 if (RT_SUCCESS(rc))
4768 pData->GCPhysVRAM = GCPhysAddress;
4769 }
4770 }
4771 else
4772 {
4773 /*
4774 * Unmapping of the VRAM in progress.
4775 * Deregister the access handler so PGM doesn't get upset.
4776 */
4777 Assert(pData->GCPhysVRAM);
4778 rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4779 AssertRC(rc);
4780 pData->GCPhysVRAM = 0;
4781 }
4782 return rc;
4783}
4784
4785
4786/* -=-=-=-=-=- Ring3: Misc Wrappers -=-=-=-=-=- */
4787
4788/**
4789 * Saves a state of the VGA device.
4790 *
4791 * @returns VBox status code.
4792 * @param pDevIns The device instance.
4793 * @param pSSMHandle The handle to save the state to.
4794 */
4795static DECLCALLBACK(int) vgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4796{
4797 vga_save(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE));
4798 return VINF_SUCCESS;
4799}
4800
4801
4802/**
4803 * Loads a saved VGA device state.
4804 *
4805 * @returns VBox status code.
4806 * @param pDevIns The device instance.
4807 * @param pSSMHandle The handle to the saved state.
4808 * @param u32Version The data unit version number.
4809 */
4810static DECLCALLBACK(int) vgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
4811{
4812 if (vga_load(pSSMHandle, PDMINS2DATA(pDevIns, PVGASTATE), u32Version))
4813 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4814 return VINF_SUCCESS;
4815}
4816
4817
4818/* -=-=-=-=-=- Ring 3: Device callbacks -=-=-=-=-=- */
4819
4820/**
4821 * Reset notification.
4822 *
4823 * @returns VBox status.
4824 * @param pDevIns The device instance data.
4825 */
4826static DECLCALLBACK(void) vgaR3Reset(PPDMDEVINS pDevIns)
4827{
4828 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4829 char *pchStart;
4830 char *pchEnd;
4831 LogFlow(("vgaReset\n"));
4832
4833 /* Clear the VRAM ourselves. */
4834 if (pData->vram_ptrHC && pData->vram_size)
4835 {
4836#ifdef LOG_ENABLED /** @todo separate function. */
4837 /* First dump the textmode contents to the log; handy for capturing Windows blue screens. */
4838 uint8_t graphic_mode;
4839 VGAState *s = pData;
4840
4841 if (!(s->ar_index & 0x20)) {
4842 graphic_mode = GMODE_BLANK;
4843 } else {
4844 graphic_mode = s->gr[6] & 1;
4845 }
4846 switch(graphic_mode)
4847 case GMODE_TEXT:
4848 {
4849 int cw, height, width, cheight, cx_min, cx_max, cy, cx;
4850 int x_incr;
4851 uint8_t *s1, *src, ch, cattr;
4852 int line_offset;
4853 uint16_t ch_attr;
4854
4855 line_offset = s->line_offset;
4856 s1 = s->CTXSUFF(vram_ptr) + (s->start_addr * 4);
4857
4858 /* total width & height */
4859 cheight = (s->cr[9] & 0x1f) + 1;
4860 cw = 8;
4861 if (!(s->sr[1] & 0x01))
4862 cw = 9;
4863 if (s->sr[1] & 0x08)
4864 cw = 16; /* NOTE: no 18 pixel wide */
4865 x_incr = cw * ((s->pDrv->cBits + 7) >> 3);
4866 width = (s->cr[0x01] + 1);
4867 if (s->cr[0x06] == 100) {
4868 /* ugly hack for CGA 160x100x16 - explain me the logic */
4869 height = 100;
4870 } else {
4871 height = s->cr[0x12] |
4872 ((s->cr[0x07] & 0x02) << 7) |
4873 ((s->cr[0x07] & 0x40) << 3);
4874 height = (height + 1) / cheight;
4875 }
4876 if ((height * width) > CH_ATTR_SIZE) {
4877 /* better than nothing: exit if transient size is too big */
4878 break;
4879 }
4880 RTLogPrintf("VGA textmode BEGIN (%dx%d):\n\n", height, width);
4881 for(cy = 0; cy < height; cy++) {
4882 src = s1;
4883 cx_min = width;
4884 cx_max = -1;
4885 for(cx = 0; cx < width; cx++) {
4886 ch_attr = *(uint16_t *)src;
4887 if (cx < cx_min)
4888 cx_min = cx;
4889 if (cx > cx_max)
4890 cx_max = cx;
4891# ifdef WORDS_BIGENDIAN
4892 ch = ch_attr >> 8;
4893 cattr = ch_attr & 0xff;
4894# else
4895 ch = ch_attr & 0xff;
4896 cattr = ch_attr >> 8;
4897# endif
4898 RTLogPrintf("%c", ch);
4899
4900 src += 4;
4901 }
4902 if (cx_max != -1)
4903 RTLogPrintf("\n");
4904
4905 s1 += line_offset;
4906 }
4907 RTLogPrintf("VGA textmode END:\n\n");
4908 }
4909
4910#endif /* LOG_ENABLED */
4911 memset(pData->vram_ptrHC, 0, pData->vram_size);
4912 }
4913
4914 /*
4915 * Zero most of it.
4916 *
4917 * Unlike vga_reset we're leaving out a few members which believe must
4918 * remain unchanged....
4919 */
4920 /* 1st part. */
4921 pchStart = (char *)&pData->latch;
4922 pchEnd = (char *)&pData->invalidated_y_table;
4923 memset(pchStart, 0, pchEnd - pchStart);
4924
4925 /* 2nd part. */
4926 pchStart = (char *)&pData->last_palette;
4927 pchEnd = (char *)&pData->u32Marker;
4928 memset(pchStart, 0, pchEnd - pchStart);
4929
4930
4931 /*
4932 * Restore and re-init some bits.
4933 */
4934 pData->get_bpp = vga_get_bpp;
4935 pData->get_offsets = vga_get_offsets;
4936 pData->get_resolution = vga_get_resolution;
4937 pData->graphic_mode = -1; /* Force full update. */
4938#ifdef CONFIG_BOCHS_VBE
4939 pData->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
4940 pData->vbe_regs[VBE_DISPI_INDEX_VBOX_VIDEO] = 0;
4941 pData->vbe_bank_mask = ((pData->vram_size >> 16) - 1);
4942#endif /* CONFIG_BOCHS_VBE */
4943
4944 /*
4945 * Reset the LBF mapping.
4946 */
4947 pData->fLFBUpdated = false;
4948 if ( ( pData->fGCEnabled
4949 || pData->fR0Enabled)
4950 && pData->GCPhysVRAM
4951 && pData->GCPhysVRAM != NIL_RTGCPHYS32)
4952 {
4953 int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pDevIns), pData->GCPhysVRAM);
4954 AssertRC(rc);
4955 }
4956
4957 /*
4958 * Reset the logo data.
4959 */
4960 pData->LogoCommand = LOGO_CMD_NOP;
4961 pData->offLogoData = 0;
4962
4963 /* notify port handler */
4964 if (pData->pDrv)
4965 pData->pDrv->pfnReset(pData->pDrv);
4966}
4967
4968
4969/**
4970 * Device relocation callback.
4971 *
4972 * @param pDevIns Pointer to the device instance.
4973 * @param offDelta The relocation delta relative to the old location.
4974 *
4975 * @see FNPDMDEVRELOCATE for details.
4976 */
4977static DECLCALLBACK(void) vgaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4978{
4979 if (offDelta)
4980 {
4981 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
4982 LogFlow(("vgaRelocate: offDelta = %08X\n", offDelta));
4983
4984 pData->GCPtrLFBHandler += offDelta;
4985 pData->vram_ptrGC += offDelta;
4986 }
4987}
4988
4989
4990/**
4991 * Attach command.
4992 *
4993 * This is called to let the device attach to a driver for a specified LUN
4994 * during runtime. This is not called during VM construction, the device
4995 * constructor have to attach to all the available drivers.
4996 *
4997 * This is like plugging in the monitor after turning on the PC.
4998 *
4999 * @returns VBox status code.
5000 * @param pDevIns The device instance.
5001 * @param iLUN The logical unit which is being detached.
5002 */
5003static DECLCALLBACK(int) vgaAttach(PPDMDEVINS pDevIns, unsigned iLUN)
5004{
5005 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5006 switch (iLUN)
5007 {
5008 /* LUN #0: Display port. */
5009 case 0:
5010 {
5011 int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &pData->Base, &pData->pDrvBase, "Display Port");
5012 if (VBOX_SUCCESS(rc))
5013 {
5014 pData->pDrv = (PDMIDISPLAYCONNECTOR*)pData->pDrvBase->pfnQueryInterface(pData->pDrvBase, PDMINTERFACE_DISPLAY_CONNECTOR);
5015 if (pData->pDrv)
5016 {
5017 /* pData->pDrv->pu8Data can be NULL when there is no framebuffer. */
5018 if ( pData->pDrv->pfnRefresh
5019 && pData->pDrv->pfnResize
5020 && pData->pDrv->pfnUpdateRect)
5021 rc = VINF_SUCCESS;
5022 else
5023 {
5024 Assert(pData->pDrv->pfnRefresh);
5025 Assert(pData->pDrv->pfnResize);
5026 Assert(pData->pDrv->pfnUpdateRect);
5027 pData->pDrv = NULL;
5028 pData->pDrvBase = NULL;
5029 rc = VERR_INTERNAL_ERROR;
5030 }
5031 }
5032 else
5033 {
5034 AssertMsgFailed(("LUN #0 doesn't have a display connector interface! rc=%Vrc\n", rc));
5035 pData->pDrvBase = NULL;
5036 rc = VERR_PDM_MISSING_INTERFACE;
5037 }
5038 }
5039 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5040 {
5041 Log(("%s/%d: warning: no driver attached to LUN #0!\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
5042 rc = VINF_SUCCESS;
5043 }
5044 else
5045 AssertMsgFailed(("Failed to attach LUN #0! rc=%Vrc\n", rc));
5046 return rc;
5047 }
5048
5049 default:
5050 AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
5051 return VERR_PDM_NO_SUCH_LUN;
5052 }
5053}
5054
5055
5056/**
5057 * Detach notification.
5058 *
5059 * This is called when a driver is detaching itself from a LUN of the device.
5060 * The device should adjust it's state to reflect this.
5061 *
5062 * This is like unplugging the monitor while the PC is still running.
5063 *
5064 * @param pDevIns The device instance.
5065 * @param iLUN The logical unit which is being detached.
5066 */
5067static DECLCALLBACK(void) vgaDetach(PPDMDEVINS pDevIns, unsigned iLUN)
5068{
5069 /*
5070 * Reset the interfaces and update the controller state.
5071 */
5072 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5073 switch (iLUN)
5074 {
5075 /* LUN #0: Display port. */
5076 case 0:
5077 pData->pDrv = NULL;
5078 pData->pDrvBase = NULL;
5079 break;
5080
5081 default:
5082 AssertMsgFailed(("Invalid LUN #%d\n", iLUN));
5083 break;
5084 }
5085}
5086
5087
5088
5089/**
5090 * Construct a VGA device instance for a VM.
5091 *
5092 * @returns VBox status.
5093 * @param pDevIns The device instance data.
5094 * If the registration structure is needed, pDevIns->pDevReg points to it.
5095 * @param iInstance Instance number. Use this to figure out which registers and such to use.
5096 * The device number is also found in pDevIns->iInstance, but since it's
5097 * likely to be freqently used PDM passes it as parameter.
5098 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
5099 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
5100 * iInstance it's expected to be used a bit in this function.
5101 */
5102static DECLCALLBACK(int) vgaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
5103{
5104 static bool fExpandDone = false;
5105 bool f;
5106 int rc;
5107 unsigned i;
5108 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5109 PVM pVM = PDMDevHlpGetVM(pDevIns);
5110#ifdef VBE_NEW_DYN_LIST
5111 uint32_t cCustomModes;
5112 uint32_t cyReduction;
5113 PVBEHEADER pVBEDataHdr;
5114 ModeInfoListItem *pCurMode;
5115 unsigned cb;
5116#endif
5117 Assert(iInstance == 0);
5118 Assert(pVM);
5119
5120 /*
5121 * Init static data.
5122 */
5123 if (!fExpandDone)
5124 {
5125 fExpandDone = true;
5126 vga_init_expand();
5127 }
5128
5129 /*
5130 * Validate configuration.
5131 */
5132 if (!CFGMR3AreValuesValid(pCfgHandle, "VRamSize\0"
5133 "GCEnabled\0"
5134 "R0Enabled\0"
5135 "FadeIn\0"
5136 "FadeOut\0"
5137 "LogoTime\0"
5138 "LogoFile\0"
5139 "ShowBootMenu\0"
5140 "CustomVideoModes\0"
5141 "HeightReduction\0"
5142 "CustomVideoMode1\0"
5143 "CustomVideoMode2\0"
5144 "CustomVideoMode3\0"
5145 "CustomVideoMode4\0"
5146 "CustomVideoMode5\0"
5147 "CustomVideoMode6\0"
5148 "CustomVideoMode7\0"
5149 "CustomVideoMode8\0"
5150 "CustomVideoMode9\0"
5151 "CustomVideoMode10\0"
5152 "CustomVideoMode11\0"
5153 "CustomVideoMode12\0"
5154 "CustomVideoMode13\0"
5155 "CustomVideoMode14\0"
5156 "CustomVideoMode15\0"
5157 "CustomVideoMode16\0"))
5158 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5159 N_("Invalid configuration for vga device"));
5160
5161 /*
5162 * Init state data.
5163 */
5164 rc = CFGMR3QueryU32(pCfgHandle, "VRamSize", &pData->vram_size);
5165 if (VBOX_FAILURE(rc) || !pData->vram_size)
5166 pData->vram_size = VGA_VRAM_DEFAULT;
5167 else if (pData->vram_size > VGA_VRAM_MAX)
5168 {
5169 AssertMsgFailed(("vram_size=%d max=%d\n", pData->vram_size, VGA_VRAM_MAX));
5170 pData->vram_size = VGA_VRAM_MAX;
5171 }
5172 else if (pData->vram_size < VGA_VRAM_MIN)
5173 {
5174 AssertMsgFailed(("vram_size=%d min=%d\n", pData->vram_size, VGA_VRAM_MIN));
5175 pData->vram_size = RT_ALIGN_32(pData->vram_size, _1M);
5176 }
5177 Log(("VGA: VRamSize=%#x\n", pData->vram_size));
5178
5179 pData->fGCEnabled = true;
5180 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &f);
5181 if (VBOX_SUCCESS(rc) && !f)
5182 pData->fGCEnabled = false;
5183 Log(("VGA: fGCEnabled=%d\n", pData->fGCEnabled));
5184
5185 pData->fR0Enabled = true;
5186 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &f);
5187 if (VBOX_SUCCESS(rc) && !f)
5188 pData->fR0Enabled = false;
5189 Log(("VGA: fR0Enabled=%d\n", pData->fR0Enabled));
5190
5191 pData->pDevInsHC = pDevIns;
5192
5193 vgaR3Reset(pDevIns);
5194
5195 /* The PCI devices configuration. */
5196 pData->Dev.config[0x00] = 0xee; /* PCI vendor, just a free bogus value */
5197 pData->Dev.config[0x01] = 0x80;
5198
5199 pData->Dev.config[0x02] = 0xef; /* Device ID */
5200 pData->Dev.config[0x03] = 0xbe;
5201
5202 pData->Dev.config[0x0a] = 0x00; /* VGA controller */
5203 pData->Dev.config[0x0b] = 0x03;
5204 pData->Dev.config[0x0e] = 0x00; /* header_type */
5205
5206 /* The LBF access handler - error handling is better here than in the map function. */
5207 rc = PDMR3GetSymbolGCLazy(pVM, pDevIns->pDevReg->szGCMod, "vgaGCLFBAccessHandler", &pData->GCPtrLFBHandler);
5208 if (VBOX_FAILURE(rc))
5209 {
5210 AssertReleaseMsgFailed(("PDMR3GetSymbolGC(, %s, \"vgaGCLFBAccessHandler\",) -> %Vrc\n", pDevIns->pDevReg->szGCMod, rc));
5211 return rc;
5212 }
5213
5214 /* the interfaces. */
5215 pData->Base.pfnQueryInterface = vgaPortQueryInterface;
5216
5217 pData->Port.pfnUpdateDisplay = vgaPortUpdateDisplay;
5218 pData->Port.pfnUpdateDisplayAll = vgaPortUpdateDisplayAll;
5219 pData->Port.pfnQueryColorDepth = vgaPortQueryColorDepth;
5220 pData->Port.pfnSetRefreshRate = vgaPortSetRefreshRate;
5221 pData->Port.pfnSnapshot = vgaPortSnapshot;
5222 pData->Port.pfnDisplayBlt = vgaPortDisplayBlt;
5223 pData->Port.pfnUpdateDisplayRect = vgaPortUpdateDisplayRect;
5224 pData->Port.pfnSetRenderVRAM = vgaPortSetRenderVRAM;
5225
5226
5227 /*
5228 * Allocate the VRAM and map the first 256KB of it into GC so we can speed up VGA support.
5229 */
5230 rc = PDMDevHlpMMIO2Register(pDevIns, 0 /* iRegion */, pData->vram_size, 0, (void **)&pData->vram_ptrHC, "VRam");
5231 AssertMsgRC(rc, ("PDMDevHlpMMIO2Register(%#x,) -> %Rrc\n", pData->vram_size, rc));
5232
5233 RTGCPTR pGCMapping = 0;
5234 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, 0 /* iRegion */, 0 /* off */, VGA_MAPPING_SIZE, "VGA VRam", &pGCMapping);
5235 AssertMsgRC(rc, ("MMR3HyperMapGCPhys(%#x,) -> %Rrc\n", pData->vram_size, rc));
5236#if GC_ARCH_BITS == 64
5237 Assert(!(pGCMapping >> 32ULL));
5238#endif
5239 pData->vram_ptrGC = pGCMapping;
5240
5241 /*
5242 * Register I/O ports, ROM and save state.
5243 */
5244 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3c0, 16, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3c0");
5245 if (VBOX_FAILURE(rc))
5246 return rc;
5247 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3b4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3b4");
5248 if (VBOX_FAILURE(rc))
5249 return rc;
5250 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3ba, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3ba");
5251 if (VBOX_FAILURE(rc))
5252 return rc;
5253 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3d4, 2, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3d4");
5254 if (VBOX_FAILURE(rc))
5255 return rc;
5256 rc = PDMDevHlpIOPortRegister(pDevIns, 0x3da, 1, NULL, vgaIOPortWrite, vgaIOPortRead, NULL, NULL, "VGA - 3da");
5257 if (VBOX_FAILURE(rc))
5258 return rc;
5259
5260#ifdef CONFIG_BOCHS_VBE
5261 rc = PDMDevHlpIOPortRegister(pDevIns, 0x1ce, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, NULL, NULL, "VGA/VBE - Index");
5262 if (VBOX_FAILURE(rc))
5263 return rc;
5264 rc = PDMDevHlpIOPortRegister(pDevIns, 0x1cf, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, NULL, NULL, "VGA/VBE - Data");
5265 if (VBOX_FAILURE(rc))
5266 return rc;
5267#if 0
5268 /* This now causes conflicts with Win2k & XP; it is not aware this range is taken
5269 and tries to map other devices there */
5270 /* Old Bochs. */
5271 rc = PDMDevHlpIOPortRegister(pDevIns, 0xff80, 1, NULL, vgaIOPortWriteVBEIndex, vgaIOPortReadVBEIndex, "VGA/VBE - Index Old");
5272 if (VBOX_FAILURE(rc))
5273 return rc;
5274 rc = PDMDevHlpIOPortRegister(pDevIns, 0xff81, 1, NULL, vgaIOPortWriteVBEData, vgaIOPortReadVBEData, "VGA/VBE - Data Old");
5275 if (VBOX_FAILURE(rc))
5276 return rc;
5277#endif
5278#endif /* CONFIG_BOCHS_VBE */
5279
5280 /* guest context extension */
5281 if (pData->fGCEnabled)
5282 {
5283 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
5284 if (VBOX_FAILURE(rc))
5285 return rc;
5286 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
5287 if (VBOX_FAILURE(rc))
5288 return rc;
5289 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
5290 if (VBOX_FAILURE(rc))
5291 return rc;
5292 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
5293 if (VBOX_FAILURE(rc))
5294 return rc;
5295 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
5296 if (VBOX_FAILURE(rc))
5297 return rc;
5298#ifdef CONFIG_BOCHS_VBE
5299 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
5300 if (VBOX_FAILURE(rc))
5301 return rc;
5302 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
5303 if (VBOX_FAILURE(rc))
5304 return rc;
5305
5306#if 0
5307 /* This now causes conflicts with Win2k & XP; they are not aware this range is taken
5308 and try to map other devices there */
5309 /* Old Bochs. */
5310 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
5311 if (VBOX_FAILURE(rc))
5312 return rc;
5313 rc = PDMDevHlpIOPortRegisterGC(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
5314 if (VBOX_FAILURE(rc))
5315 return rc;
5316#endif
5317
5318#endif /* CONFIG_BOCHS_VBE */
5319 }
5320
5321 /* R0 context extension */
5322 if (pData->fR0Enabled)
5323 {
5324 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3c0, 16, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3c0 (GC)");
5325 if (VBOX_FAILURE(rc))
5326 return rc;
5327 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3b4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3b4 (GC)");
5328 if (VBOX_FAILURE(rc))
5329 return rc;
5330 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3ba, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3ba (GC)");
5331 if (VBOX_FAILURE(rc))
5332 return rc;
5333 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3d4, 2, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3d4 (GC)");
5334 if (VBOX_FAILURE(rc))
5335 return rc;
5336 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x3da, 1, 0, "vgaIOPortWrite", "vgaIOPortRead", NULL, NULL, "VGA - 3da (GC)");
5337 if (VBOX_FAILURE(rc))
5338 return rc;
5339#ifdef CONFIG_BOCHS_VBE
5340 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1ce, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", NULL, NULL, "VGA/VBE - Index (GC)");
5341 if (VBOX_FAILURE(rc))
5342 return rc;
5343 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0x1cf, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", NULL, NULL, "VGA/VBE - Data (GC)");
5344 if (VBOX_FAILURE(rc))
5345 return rc;
5346
5347#if 0
5348 /* This now causes conflicts with Win2k & XP; they are not aware this range is taken
5349 and try to map other devices there */
5350 /* Old Bochs. */
5351 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff80, 1, 0, "vgaIOPortWriteVBEIndex", "vgaIOPortReadVBEIndex", "VGA/VBE - Index Old (GC)");
5352 if (VBOX_FAILURE(rc))
5353 return rc;
5354 rc = PDMDevHlpIOPortRegisterR0(pDevIns, 0xff81, 1, 0, "vgaIOPortWriteVBEData", "vgaIOPortReadVBEData", "VGA/VBE - Index Old (GC)");
5355 if (VBOX_FAILURE(rc))
5356 return rc;
5357#endif
5358
5359#endif /* CONFIG_BOCHS_VBE */
5360 }
5361
5362 /* vga mmio */
5363 rc = PDMDevHlpMMIORegister(pDevIns, 0x000a0000, 0x00020000, 0, vgaMMIOWrite, vgaMMIORead, vgaMMIOFill, "VGA - VGA Video Buffer");
5364 if (VBOX_FAILURE(rc))
5365 return rc;
5366 if (pData->fGCEnabled)
5367 {
5368 rc = PDMDevHlpMMIORegisterGC(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");
5369 if (VBOX_FAILURE(rc))
5370 return rc;
5371 }
5372 if (pData->fR0Enabled)
5373 {
5374 rc = PDMDevHlpMMIORegisterR0(pDevIns, 0x000a0000, 0x00020000, 0, "vgaMMIOWrite", "vgaMMIORead", "vgaMMIOFill");
5375 if (VBOX_FAILURE(rc))
5376 return rc;
5377 }
5378
5379 /* vga bios */
5380 rc = PDMDevHlpIOPortRegister(pDevIns, VBE_PRINTF_PORT, 1, NULL, vgaIOPortWriteBIOS, vgaIOPortReadBIOS, NULL, NULL, "VGA BIOS debug/panic");
5381 if (VBOX_FAILURE(rc))
5382 return rc;
5383 AssertReleaseMsg(g_cbVgaBiosBinary <= _64K && g_cbVgaBiosBinary >= 32*_1K, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
5384 AssertReleaseMsg(RT_ALIGN_Z(g_cbVgaBiosBinary, PAGE_SIZE) == g_cbVgaBiosBinary, ("g_cbVgaBiosBinary=%#x\n", g_cbVgaBiosBinary));
5385 rc = PDMDevHlpROMRegister(pDevIns, 0x000c0000, g_cbVgaBiosBinary, &g_abVgaBiosBinary[0],
5386 false /* fShadow */, "VGA BIOS");
5387 if (VBOX_FAILURE(rc))
5388 return rc;
5389
5390 /* save */
5391 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 1 /* version */, sizeof(*pData),
5392 NULL, vgaR3SaveExec, NULL,
5393 NULL, vgaR3LoadExec, NULL);
5394 if (VBOX_FAILURE(rc))
5395 return rc;
5396
5397 /* PCI */
5398 rc = PDMDevHlpPCIRegister(pDevIns, &pData->Dev);
5399 if (VBOX_FAILURE(rc))
5400 return rc;
5401 /*AssertMsg(pData->Dev.devfn == 16 || iInstance != 0, ("pData->Dev.devfn=%d\n", pData->Dev.devfn));*/
5402 if (pData->Dev.devfn != 16 && iInstance == 0)
5403 Log(("!!WARNING!!: pData->dev.devfn=%d (ignore if testcase or not started by Main)\n", pData->Dev.devfn));
5404
5405 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0 /* iRegion */, pData->vram_size, PCI_ADDRESS_SPACE_MEM_PREFETCH, vgaR3IORegionMap);
5406 if (VBOX_FAILURE(rc))
5407 return rc;
5408
5409 /*
5410 * Create the refresh timer.
5411 */
5412 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_REAL, vgaTimerRefresh, "VGA Refresh Timer", &pData->RefreshTimer);
5413 if (VBOX_FAILURE(rc))
5414 return rc;
5415
5416 /*
5417 * Attach to the display.
5418 */
5419 rc = vgaAttach(pDevIns, 0 /* display LUN # */);
5420 if (VBOX_FAILURE(rc))
5421 return rc;
5422
5423#ifdef VBE_NEW_DYN_LIST
5424 /*
5425 * Compute buffer size for the VBE BIOS Extra Data.
5426 */
5427 cb = sizeof(mode_info_list) + sizeof(ModeInfoListItem);
5428
5429 rc = CFGMR3QueryU32(pCfgHandle, "HeightReduction", &cyReduction);
5430 if (VBOX_SUCCESS(rc) && cyReduction)
5431 cb *= 2; /* Default mode list will be twice long */
5432 else
5433 cyReduction = 0;
5434
5435 rc = CFGMR3QueryU32(pCfgHandle, "CustomVideoModes", &cCustomModes);
5436 if (VBOX_SUCCESS(rc) && cCustomModes)
5437 cb += sizeof(ModeInfoListItem) * cCustomModes;
5438 else
5439 cCustomModes = 0;
5440
5441 /*
5442 * Allocate and initialize buffer for the VBE BIOS Extra Data.
5443 */
5444 pData->cbVBEExtraData = sizeof(VBEHEADER) + cb;
5445 pData->pu8VBEExtraData = (uint8_t *)PDMDevHlpMMHeapAllocZ(pDevIns, pData->cbVBEExtraData);
5446 if (!pData->pu8VBEExtraData)
5447 return VERR_NO_MEMORY;
5448
5449 pVBEDataHdr = (PVBEHEADER)pData->pu8VBEExtraData;
5450 pVBEDataHdr->u16Signature = VBEHEADER_MAGIC;
5451 pVBEDataHdr->cbData = cb;
5452
5453#ifndef VRAM_SIZE_FIX
5454 pCurMode = memcpy(pVBEDataHdr + 1, &mode_info_list, sizeof(mode_info_list));
5455 pCurMode = (ModeInfoListItem *)((uintptr_t)pCurMode + sizeof(mode_info_list));
5456#else /* VRAM_SIZE_FIX defined */
5457 pCurMode = (ModeInfoListItem *)(pVBEDataHdr + 1);
5458 for (i = 0; i < MODE_INFO_SIZE; i++)
5459 {
5460 uint32_t pixelWidth, reqSize;
5461 if (mode_info_list[i].info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
5462 pixelWidth = 2;
5463 else
5464 pixelWidth = (mode_info_list[i].info.BitsPerPixel +7) / 8;
5465 reqSize = mode_info_list[i].info.XResolution
5466 * mode_info_list[i].info.YResolution
5467 * pixelWidth;
5468 if (reqSize >= pData->vram_size)
5469 continue;
5470 *pCurMode = mode_info_list[i];
5471 pCurMode++;
5472 }
5473#endif /* VRAM_SIZE_FIX defined */
5474
5475 /*
5476 * Copy default modes with subtractred YResolution.
5477 */
5478 if (cyReduction)
5479 {
5480 ModeInfoListItem *pDefMode = mode_info_list;
5481 Log(("vgaR3Construct: cyReduction=%u\n", cyReduction));
5482#ifndef VRAM_SIZE_FIX
5483 for (i = 0; i < MODE_INFO_SIZE; i++, pCurMode++, pDefMode++)
5484 {
5485 *pCurMode = *pDefMode;
5486 pCurMode->mode += 0x30;
5487 pCurMode->info.YResolution -= cyReduction;
5488 }
5489#else /* VRAM_SIZE_FIX defined */
5490 for (i = 0; i < MODE_INFO_SIZE; i++, pDefMode++)
5491 {
5492 uint32_t pixelWidth, reqSize;
5493 if (pDefMode->info.MemoryModel == VBE_MEMORYMODEL_TEXT_MODE)
5494 pixelWidth = 2;
5495 else
5496 pixelWidth = (pDefMode->info.BitsPerPixel + 7) / 8;
5497 reqSize = pDefMode->info.XResolution * pDefMode->info.YResolution * pixelWidth;
5498 if (reqSize >= pData->vram_size)
5499 continue;
5500 *pCurMode = *pDefMode;
5501 pCurMode->mode += 0x30;
5502 pCurMode->info.YResolution -= cyReduction;
5503 pCurMode++;
5504 }
5505#endif /* VRAM_SIZE_FIX defined */
5506 }
5507
5508
5509 /*
5510 * Add custom modes.
5511 */
5512 if (cCustomModes)
5513 {
5514 uint16_t u16CurMode = 0x160;
5515 for (i = 1; i <= cCustomModes; i++)
5516 {
5517 char szExtraDataKey[sizeof("CustomVideoModeXX")];
5518 char *pszExtraData = NULL;
5519
5520 /* query and decode the custom mode string. */
5521 RTStrPrintf(szExtraDataKey, sizeof(szExtraDataKey), "CustomVideoMode%d", i);
5522 rc = CFGMR3QueryStringAlloc(pCfgHandle, szExtraDataKey, &pszExtraData);
5523 if (VBOX_SUCCESS(rc))
5524 {
5525 ModeInfoListItem *pDefMode = mode_info_list;
5526 unsigned int cx, cy, cBits, cParams, j;
5527 uint16_t u16DefMode;
5528
5529 cParams = sscanf(pszExtraData, "%ux%ux%u", &cx, &cy, &cBits);
5530 if ( cParams != 3
5531 || (cBits != 16 && cBits != 24 && cBits != 32))
5532 {
5533 AssertMsgFailed(("Configuration error: Invalid mode data '%s' for '%s'! cBits=%d\n", pszExtraData, szExtraDataKey, cBits));
5534 return VERR_VGA_INVALID_CUSTOM_MODE;
5535 }
5536#ifdef VRAM_SIZE_FIX
5537 if (cx * cy * cBits / 8 >= pData->vram_size)
5538 {
5539 AssertMsgFailed(("Configuration error: custom video mode %dx%dx%dbits is too large for the virtual video memory of %dMb. Please increase the video memory size.\n",
5540 cx, cy, cBits, pData->vram_size / _1M));
5541 return VERR_VGA_INVALID_CUSTOM_MODE;
5542 }
5543#endif /* VRAM_SIZE_FIX defined */
5544 MMR3HeapFree(pszExtraData);
5545
5546 /* Use defaults from max@bpp mode. */
5547 switch (cBits)
5548 {
5549 case 16:
5550 u16DefMode = VBE_VESA_MODE_1024X768X565;
5551 break;
5552
5553 case 24:
5554 u16DefMode = VBE_VESA_MODE_1024X768X888;
5555 break;
5556
5557 case 32:
5558 u16DefMode = VBE_OWN_MODE_1024X768X8888;
5559 break;
5560
5561 default: /* gcc, shut up! */
5562 AssertMsgFailed(("gone postal!\n"));
5563 continue;
5564 }
5565
5566 /* mode_info_list is not terminated */
5567 for (j = 0; j < MODE_INFO_SIZE && pDefMode->mode != u16DefMode; j++)
5568 pDefMode++;
5569 Assert(j < MODE_INFO_SIZE);
5570
5571 *pCurMode = *pDefMode;
5572 pCurMode->mode = u16CurMode++;
5573
5574 /* adjust defaults */
5575 pCurMode->info.XResolution = cx;
5576 pCurMode->info.YResolution = cy;
5577
5578 switch (cBits)
5579 {
5580 case 16:
5581 pCurMode->info.BytesPerScanLine = cx * 2;
5582 pCurMode->info.LinBytesPerScanLine = cx * 2;
5583 break;
5584
5585 case 24:
5586 pCurMode->info.BytesPerScanLine = cx * 3;
5587 pCurMode->info.LinBytesPerScanLine = cx * 3;
5588 break;
5589
5590 case 32:
5591 pCurMode->info.BytesPerScanLine = cx * 4;
5592 pCurMode->info.LinBytesPerScanLine = cx * 4;
5593 break;
5594 }
5595
5596 /* commit it */
5597 pCurMode++;
5598 }
5599 else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
5600 {
5601 AssertMsgFailed(("CFGMR3QueryStringAlloc(,'%s',) -> %Vrc\n", szExtraDataKey, rc));
5602 return rc;
5603 }
5604 } /* foreach custom mode key */
5605 }
5606
5607 /*
5608 * Add the "End of list" mode.
5609 */
5610 memset(pCurMode, 0, sizeof(*pCurMode));
5611 pCurMode->mode = VBE_VESA_MODE_END_OF_LIST;
5612
5613 /*
5614 * Register I/O Port for the VBE BIOS Extra Data.
5615 */
5616 rc = PDMDevHlpIOPortRegister(pDevIns, VBE_EXTRA_PORT, 1, NULL, vbeIOPortWriteVBEExtra, vbeIOPortReadVBEExtra, NULL, NULL, "VBE BIOS Extra Data");
5617 if (VBOX_FAILURE(rc))
5618 return rc;
5619#endif
5620
5621 /*
5622 * Register I/O Port for the BIOS Logo.
5623 */
5624 rc = PDMDevHlpIOPortRegister(pDevIns, LOGO_IO_PORT, 1, NULL, vbeIOPortWriteCMDLogo, vbeIOPortReadCMDLogo, NULL, NULL, "BIOS Logo");
5625 if (VBOX_FAILURE(rc))
5626 return rc;
5627
5628 /*
5629 * Construct the logo header.
5630 */
5631 LOGOHDR LogoHdr = { LOGO_HDR_MAGIC, 0, 0, 0, 0, 0, 0 };
5632
5633 rc = CFGMR3QueryU8(pCfgHandle, "FadeIn", &LogoHdr.fu8FadeIn);
5634 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5635 LogoHdr.fu8FadeIn = 1;
5636 else if (VBOX_FAILURE(rc))
5637 return PDMDEV_SET_ERROR(pDevIns, rc,
5638 N_("Configuration error: Querying \"FadeIn\" as integer failed"));
5639
5640 rc = CFGMR3QueryU8(pCfgHandle, "FadeOut", &LogoHdr.fu8FadeOut);
5641 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5642 LogoHdr.fu8FadeOut = 1;
5643 else if (VBOX_FAILURE(rc))
5644 return PDMDEV_SET_ERROR(pDevIns, rc,
5645 N_("Configuration error: Querying \"FadeOut\" as integer failed"));
5646
5647 rc = CFGMR3QueryU16(pCfgHandle, "LogoTime", &LogoHdr.u16LogoMillies);
5648 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5649 LogoHdr.u16LogoMillies = 0;
5650 else if (VBOX_FAILURE(rc))
5651 return PDMDEV_SET_ERROR(pDevIns, rc,
5652 N_("Configuration error: Querying \"LogoTime\" as integer failed"));
5653
5654 /* Delay the logo a little bit */
5655 if (LogoHdr.fu8FadeIn && LogoHdr.fu8FadeOut && !LogoHdr.u16LogoMillies)
5656 LogoHdr.u16LogoMillies = RT_MAX(LogoHdr.u16LogoMillies, LOGO_DELAY_TIME);
5657
5658 rc = CFGMR3QueryU8(pCfgHandle, "ShowBootMenu", &LogoHdr.fu8ShowBootMenu);
5659 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5660 LogoHdr.fu8ShowBootMenu = 0;
5661 else if (VBOX_FAILURE(rc))
5662 return PDMDEV_SET_ERROR(pDevIns, rc,
5663 N_("Configuration error: Querying \"ShowBootMenu\" as integer failed"));
5664
5665 /*
5666 * Get the Logo file name.
5667 */
5668 rc = CFGMR3QueryStringAlloc(pCfgHandle, "LogoFile", &pData->pszLogoFile);
5669 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
5670 pData->pszLogoFile = NULL;
5671 else if (VBOX_FAILURE(rc))
5672 return PDMDEV_SET_ERROR(pDevIns, rc,
5673 N_("Configuration error: Querying \"LogoFile\" as a string failed"));
5674 else if (!*pData->pszLogoFile)
5675 {
5676 MMR3HeapFree(pData->pszLogoFile);
5677 pData->pszLogoFile = NULL;
5678 }
5679
5680 /*
5681 * Determine the logo size, open any specified logo file in the process.
5682 */
5683 LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5684 RTFILE FileLogo = NIL_RTFILE;
5685 if (pData->pszLogoFile)
5686 {
5687 rc = RTFileOpen(&FileLogo, pData->pszLogoFile,
5688 RTFILE_O_READ | RTFILE_O_OPEN | RTFILE_O_DENY_WRITE);
5689 if (VBOX_SUCCESS(rc))
5690 {
5691 uint64_t cbFile;
5692 rc = RTFileGetSize(FileLogo, &cbFile);
5693 if (VBOX_SUCCESS(rc))
5694 {
5695 if (cbFile > 0 && cbFile < 32*_1M)
5696 LogoHdr.cbLogo = (uint32_t)cbFile;
5697 else
5698 rc = VERR_TOO_MUCH_DATA;
5699 }
5700 }
5701 if (VBOX_FAILURE(rc))
5702 {
5703 /*
5704 * Ignore failure and fall back to the default logo.
5705 */
5706 LogRel(("vgaR3Construct: Failed to open logo file '%s', rc=%Vrc!\n", pData->pszLogoFile, rc));
5707 if (FileLogo != NIL_RTFILE)
5708 RTFileClose(FileLogo);
5709 FileLogo = NIL_RTFILE;
5710 MMR3HeapFree(pData->pszLogoFile);
5711 pData->pszLogoFile = NULL;
5712 }
5713 }
5714
5715 /*
5716 * Disable graphic splash screen if it doesn't fit into VRAM.
5717 */
5718 if (pData->vram_size < LOGO_MAX_SIZE)
5719 LogoHdr.fu8FadeIn = LogoHdr.fu8FadeOut = LogoHdr.u16LogoMillies = 0;
5720
5721 /*
5722 * Allocate buffer for the logo data.
5723 * RT_MAX() is applied to let us fall back to default logo on read failure.
5724 */
5725 pData->cbLogo = sizeof(LogoHdr) + LogoHdr.cbLogo;
5726 pData->pu8Logo = (uint8_t *)PDMDevHlpMMHeapAlloc(pDevIns, RT_MAX(pData->cbLogo, g_cbVgaDefBiosLogo + sizeof(LogoHdr)));
5727 if (pData->pu8Logo)
5728 {
5729 /*
5730 * Write the logo header.
5731 */
5732 PLOGOHDR pLogoHdr = (PLOGOHDR)pData->pu8Logo;
5733 *pLogoHdr = LogoHdr;
5734
5735 /*
5736 * Write the logo bitmap.
5737 */
5738 if (pData->pszLogoFile)
5739 {
5740 rc = RTFileRead(FileLogo, pLogoHdr + 1, LogoHdr.cbLogo, NULL);
5741 if (VBOX_FAILURE(rc))
5742 {
5743 AssertMsgFailed(("RTFileRead(,,%d,NULL) -> %Vrc\n", LogoHdr.cbLogo, rc));
5744 pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5745 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5746 }
5747 }
5748 else
5749 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5750
5751 rc = vbeParseBitmap(pData);
5752 if (VBOX_FAILURE(rc))
5753 {
5754 AssertMsgFailed(("vbeParseBitmap() -> %Vrc\n", rc));
5755 pLogoHdr->cbLogo = LogoHdr.cbLogo = g_cbVgaDefBiosLogo;
5756 memcpy(pLogoHdr + 1, g_abVgaDefBiosLogo, LogoHdr.cbLogo);
5757 }
5758
5759 rc = vbeParseBitmap(pData);
5760 if (VBOX_FAILURE(rc))
5761 AssertReleaseMsgFailed(("Internal bitmap failed! vbeParseBitmap() -> %Vrc\n", rc));
5762
5763 rc = VINF_SUCCESS;
5764 }
5765 else
5766 rc = VERR_NO_MEMORY;
5767
5768 /*
5769 * Cleanup.
5770 */
5771 if (FileLogo != NIL_RTFILE)
5772 RTFileClose(FileLogo);
5773
5774 /*
5775 * Statistics.
5776 */
5777 STAM_REG(pVM, &pData->StatGCMemoryRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryRead() body.");
5778 STAM_REG(pVM, &pData->StatGCMemoryWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/Memory/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCMemoryWrite() body.");
5779 STAM_REG(pVM, &pData->StatGCIOPortRead, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Read", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortRead() body.");
5780 STAM_REG(pVM, &pData->StatGCIOPortWrite, STAMTYPE_PROFILE, "/Devices/VGA/GC/IOPort/Write", STAMUNIT_TICKS_PER_CALL, "Profiling of the VGAGCIOPortWrite() body.");
5781
5782 return rc;
5783}
5784
5785
5786/**
5787 * Destruct a device instance.
5788 *
5789 * Most VM resources are freed by the VM. This callback is provided so that any non-VM
5790 * resources can be freed correctly.
5791 *
5792 * @param pDevIns The device instance data.
5793 */
5794static DECLCALLBACK(int) vgaR3Destruct(PPDMDEVINS pDevIns)
5795{
5796#ifdef VBE_NEW_DYN_LIST
5797 PVGASTATE pData = PDMINS2DATA(pDevIns, PVGASTATE);
5798 LogFlow(("vgaR3Destruct:\n"));
5799
5800 /*
5801 * Free MM heap pointers.
5802 */
5803 if (pData->pu8VBEExtraData)
5804 {
5805 MMR3HeapFree(pData->pu8VBEExtraData);
5806 pData->pu8VBEExtraData = NULL;
5807 }
5808#endif
5809
5810 return VINF_SUCCESS;
5811}
5812
5813
5814/**
5815 * The device registration structure.
5816 */
5817const PDMDEVREG g_DeviceVga =
5818{
5819 /* u32Version */
5820 PDM_DEVREG_VERSION,
5821 /* szDeviceName */
5822 "vga",
5823 /* szGCMod */
5824 "VBoxDDGC.gc",
5825 /* szR0Mod */
5826 "VBoxDDR0.r0",
5827 /* pszDescription */
5828 "VGA Adaptor with VESA extensions.",
5829 /* fFlags */
5830 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
5831 /* fClass */
5832 PDM_DEVREG_CLASS_GRAPHICS,
5833 /* cMaxInstances */
5834 1,
5835 /* cbInstance */
5836 sizeof(VGASTATE),
5837 /* pfnConstruct */
5838 vgaR3Construct,
5839 /* pfnDestruct */
5840 vgaR3Destruct,
5841 /* pfnRelocate */
5842 vgaR3Relocate,
5843 /* pfnIOCtl */
5844 NULL,
5845 /* pfnPowerOn */
5846 NULL,
5847 /* pfnReset */
5848 vgaR3Reset,
5849 /* pfnSuspend */
5850 NULL,
5851 /* pfnResume */
5852 NULL,
5853 /* pfnAttach */
5854 vgaAttach,
5855 /* pfnDetach */
5856 vgaDetach,
5857 /* pfnQueryInterface */
5858 NULL,
5859 /* pfnInitComplete */
5860 NULL
5861};
5862
5863#endif /* !IN_RING3 */
5864#endif /* VBOX */
5865#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5866
5867/*
5868 * Local Variables:
5869 * nuke-trailing-whitespace-p:nil
5870 * End:
5871 */
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