VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.h

Last change on this file was 106061, checked in by vboxsync, 3 months ago

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1/* $Id: DevVGA.h 106061 2024-09-16 14:03:52Z vboxsync $ */
2/** @file
3 * DevVGA - VBox VGA/VESA device, internal header.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 * --------------------------------------------------------------------
27 *
28 * This code is based on:
29 *
30 * QEMU internal VGA defines.
31 *
32 * Copyright (c) 2003-2004 Fabrice Bellard
33 *
34 * Permission is hereby granted, free of charge, to any person obtaining a copy
35 * of this software and associated documentation files (the "Software"), to deal
36 * in the Software without restriction, including without limitation the rights
37 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38 * copies of the Software, and to permit persons to whom the Software is
39 * furnished to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included in
42 * all copies or substantial portions of the Software.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50 * THE SOFTWARE.
51 */
52
53#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_h
54#define VBOX_INCLUDED_SRC_Graphics_DevVGA_h
55#ifndef RT_WITHOUT_PRAGMA_ONCE
56# pragma once
57#endif
58
59#include <VBoxVideoVBE.h>
60#include <VBoxVideoVBEPrivate.h>
61
62#ifdef VBOX_WITH_HGSMI
63# include "HGSMI/HGSMIHost.h"
64#endif /* VBOX_WITH_HGSMI */
65#include "DevVGASavedState.h"
66
67#ifdef VBOX_WITH_VMSVGA
68# include "DevVGA-SVGA.h"
69#else
70# include <VBox/vmm/pdmifs.h>
71# include <VBox/vmm/stam.h>
72#endif
73
74#include <VBox/param.h> /* For VRAM ranges. */
75#ifdef VBOX_WITH_VMSVGA
76/* Make sure the param.h copy of the SVGA VRAM sizes matches the originals. */
77AssertCompile(VBOX_SVGA_VRAM_MIN_SIZE == SVGA_VRAM_MIN_SIZE);
78AssertCompile(VBOX_SVGA_VRAM_MIN_SIZE_3D == SVGA_VRAM_MIN_SIZE_3D);
79AssertCompile(VBOX_SVGA_VRAM_MAX_SIZE == SVGA_VRAM_MAX_SIZE);
80#endif
81
82#include <iprt/list.h>
83
84
85/** Use VBE bytewise I/O. Only needed for Windows Longhorn/Vista betas and backwards compatibility. */
86#define VBE_BYTEWISE_IO
87
88/** @name Macros dealing with partial ring-0/raw-mode VRAM mappings.
89 * @{ */
90/** The size of the VGA ring-0 and raw-mode mapping.
91 *
92 * This is supposed to be all the VGA memory accessible to the guest.
93 * The initial value was 256KB but NTAllInOne.iso appears to access more
94 * thus the limit was upped to 512KB.
95 *
96 * @todo Someone with some VGA knowhow should make a better guess at this value.
97 */
98#define VGA_MAPPING_SIZE _512K
99/** Enables partially mapping the VRAM into ring-0 rather than using the ring-3.
100 * The VGA_MAPPING_SIZE define sets the number of bytes that will be mapped. */
101#define VGA_WITH_PARTIAL_RING0_MAPPING
102
103/**
104 * Check buffer if an VRAM offset is within the right range or not.
105 */
106#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
107# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
108 do { \
109 if ((off) < VGA_MAPPING_SIZE) \
110 RT_UNTRUSTED_VALIDATED_FENCE(); \
111 else \
112 { \
113 AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
114 Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
115 return VINF_IOM_R3_MMIO_WRITE; \
116 } \
117 } while (0)
118#else
119# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
120 do { \
121 AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
122 RT_UNTRUSTED_VALIDATED_FENCE(); \
123 } while (0)
124#endif
125
126/**
127 * Check buffer if an VRAM offset is within the right range or not.
128 */
129#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
130# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
131 do { \
132 if ((off) < VGA_MAPPING_SIZE) \
133 RT_UNTRUSTED_VALIDATED_FENCE(); \
134 else \
135 { \
136 AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
137 Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
138 (rcVar) = VINF_IOM_R3_MMIO_READ; \
139 return 0; \
140 } \
141 } while (0)
142#else
143# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
144 do { \
145 AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
146 RT_UNTRUSTED_VALIDATED_FENCE(); \
147 NOREF(rcVar); \
148 } while (0)
149#endif
150/** @} */
151
152
153#define MSR_COLOR_EMULATION 0x01
154#define MSR_PAGE_SELECT 0x20
155
156#define ST01_V_RETRACE 0x08
157#define ST01_DISP_ENABLE 0x01
158
159/* bochs VBE support */
160#define CONFIG_BOCHS_VBE
161
162#ifdef CONFIG_BOCHS_VBE
163
164/* Cross reference with <VBoxVideoVBE.h> */
165#define VBE_DISPI_INDEX_NB_SAVED 0xb /* Old number of saved registers (vbe_regs array, see vga_load) */
166#define VBE_DISPI_INDEX_NB 0xd /* Total number of VBE registers */
167
168#define VGA_STATE_COMMON_BOCHS_VBE \
169 uint16_t vbe_index; \
170 uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
171 uint16_t alignment[2]; /* pad to 64 bits */ \
172 uint32_t vbe_start_addr; \
173 uint32_t vbe_line_offset; \
174 uint32_t vbe_bank_max;
175
176#else
177
178#define VGA_STATE_COMMON_BOCHS_VBE
179
180#endif /* !CONFIG_BOCHS_VBE */
181
182#define CH_ATTR_SIZE (160 * 100)
183#define VGA_MAX_HEIGHT VBE_DISPI_MAX_YRES
184
185typedef struct vga_retrace_s {
186 unsigned frame_cclks; /* Character clocks per frame. */
187 unsigned frame_ns; /* Frame duration in ns. */
188 unsigned cclk_ns; /* Character clock duration in ns. */
189 unsigned vb_start; /* Vertical blanking start (scanline). */
190 unsigned vb_end; /* Vertical blanking end (scanline). */
191 unsigned vb_end_ns; /* Vertical blanking end time (length) in ns. */
192 unsigned vs_start; /* Vertical sync start (scanline). */
193 unsigned vs_end; /* Vertical sync end (scanline). */
194 unsigned vs_start_ns; /* Vertical sync start time in ns. */
195 unsigned vs_end_ns; /* Vertical sync end time in ns. */
196 unsigned h_total; /* Horizontal total (cclks per scanline). */
197 unsigned h_total_ns; /* Scanline duration in ns. */
198 unsigned hb_start; /* Horizontal blanking start (cclk). */
199 unsigned hb_end; /* Horizontal blanking end (cclk). */
200 unsigned hb_end_ns; /* Horizontal blanking end time (length) in ns. */
201 unsigned v_freq_hz; /* Vertical refresh rate to emulate. */
202} vga_retrace_s;
203
204#ifndef VBOX
205#define VGA_STATE_COMMON \
206 unsigned long vram_offset; \
207 unsigned int vram_size; \
208 uint32_t latch; \
209 uint8_t sr_index; \
210 uint8_t sr[256]; \
211 uint8_t gr_index; \
212 uint8_t gr[256]; \
213 uint8_t ar_index; \
214 uint8_t ar[21]; \
215 int ar_flip_flop; \
216 uint8_t cr_index; \
217 uint8_t cr[256]; /* CRT registers */ \
218 uint8_t msr; /* Misc Output Register */ \
219 uint8_t fcr; /* Feature Control Register */ \
220 uint8_t st00; /* status 0 */ \
221 uint8_t st01; /* status 1 */ \
222 uint8_t dac_state; \
223 uint8_t dac_sub_index; \
224 uint8_t dac_read_index; \
225 uint8_t dac_write_index; \
226 uint8_t dac_cache[3]; /* used when writing */ \
227 uint8_t palette[768]; \
228 int32_t bank_offset; \
229 int (*get_bpp)(struct VGAState *s); \
230 void (*get_offsets)(struct VGAState *s, \
231 uint32_t *pline_offset, \
232 uint32_t *pstart_addr, \
233 uint32_t *pline_compare); \
234 void (*get_resolution)(struct VGAState *s, \
235 int *pwidth, \
236 int *pheight); \
237 VGA_STATE_COMMON_BOCHS_VBE \
238 /* display refresh support */ \
239 DisplayState *ds; \
240 uint32_t font_offsets[2]; \
241 int graphic_mode; \
242 uint8_t shift_control; \
243 uint8_t double_scan; \
244 uint32_t line_offset; \
245 uint32_t line_compare; \
246 uint32_t start_addr; \
247 uint32_t plane_updated; \
248 uint8_t last_cw, last_ch; \
249 uint32_t last_width, last_height; /* in chars or pixels */ \
250 uint32_t last_scr_width, last_scr_height; /* in pixels */ \
251 uint8_t cursor_start, cursor_end; \
252 uint32_t cursor_offset; \
253 unsigned int (*rgb_to_pixel)(unsigned int r, \
254 unsigned int g, unsigned b); \
255 /* hardware mouse cursor support */ \
256 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
257 void (*cursor_invalidate)(struct VGAState *s); \
258 void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \
259 /* tell for each page if it has been updated since the last time */ \
260 uint32_t last_palette[256]; \
261 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
262
263#else /* VBOX */
264
265/* bird: Since we've changed types, reordered members, done alignment
266 paddings and more, VGA_STATE_COMMON was added directly to the
267 struct to make it more readable and easier to handle. */
268
269struct VGAState;
270typedef int FNGETBPP(struct VGAState *s);
271typedef void FNGETOFFSETS(struct VGAState *s, uint32_t *pline_offset, uint32_t *pstart_addr, uint32_t *pline_compare);
272typedef void FNGETRESOLUTION(struct VGAState *s, int *pwidth, int *pheight);
273typedef unsigned int FNRGBTOPIXEL(unsigned int r, unsigned int g, unsigned b);
274typedef void FNCURSORINVALIDATE(struct VGAState *s);
275typedef void FNCURSORDRAWLINE(struct VGAState *s, uint8_t *d, int y);
276
277#endif /* VBOX */
278
279#ifdef VBOX_WITH_VDMA
280typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
281#endif
282
283#ifdef VBOX_WITH_VIDEOHWACCEL
284#define VBOX_VHWA_MAX_PENDING_COMMANDS 1000
285
286typedef struct _VBOX_VHWA_PENDINGCMD
287{
288 RTLISTNODE Node;
289 VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCommand;
290} VBOX_VHWA_PENDINGCMD;
291#endif
292
293
294/**
295 * The shared VGA state data.
296 */
297typedef struct VGAState
298{
299 uint32_t vram_size;
300 uint32_t latch;
301 uint8_t sr_index;
302 uint8_t sr[256];
303 uint8_t gr_index;
304 uint8_t gr[256];
305 uint8_t ar_index;
306 uint8_t ar[21];
307 int32_t ar_flip_flop;
308 uint8_t cr_index;
309 uint8_t cr[256]; /* CRT registers */
310 uint8_t msr; /* Misc Output Register */
311 uint8_t fcr; /* Feature Control Register */
312 uint8_t st00; /* status 0 */
313 uint8_t st01; /* status 1 */
314 uint8_t dac_state;
315 uint8_t dac_sub_index;
316 uint8_t dac_read_index;
317 uint8_t dac_write_index;
318 uint8_t dac_cache[3]; /* used when writing */
319 uint8_t palette[768];
320 int32_t bank_offset;
321 VGA_STATE_COMMON_BOCHS_VBE
322 /* display refresh support */
323 uint32_t font_offsets[2];
324 int32_t graphic_mode;
325 uint8_t shift_control;
326 uint8_t double_scan;
327 uint8_t padding1[2];
328 uint32_t line_offset;
329 uint32_t vga_addr_mask;
330 uint32_t padding1a;
331 uint32_t line_compare;
332 uint32_t start_addr;
333 uint32_t plane_updated;
334 uint8_t last_cw, last_ch;
335 uint8_t last_uline; \
336 bool last_blink; \
337 uint32_t last_width, last_height; /* in chars or pixels */
338 uint32_t last_scr_width, last_scr_height; /* in pixels */
339 uint32_t last_bpp;
340 uint8_t cursor_start, cursor_end;
341 bool last_cur_blink, last_chr_blink;
342 uint32_t cursor_offset;
343 /** hardware mouse cursor support */
344 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
345 /** tell for each page if it has been updated since the last time */
346 uint32_t last_palette[256];
347 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
348
349 /** end-of-common-state-marker */
350 uint32_t u32Marker;
351
352 /** Refresh timer handle - HC. */
353 TMTIMERHANDLE hRefreshTimer;
354
355#ifdef VBOX_WITH_VMSVGA
356 VMSVGASTATE svga;
357#endif
358
359 /** The number of monitors. */
360 uint32_t cMonitors;
361 /** Current refresh timer interval. */
362 uint32_t cMilliesRefreshInterval;
363 /** Bitmap tracking dirty pages. */
364 uint64_t bmDirtyBitmap[VGA_VRAM_MAX / GUEST_PAGE_SIZE / 64];
365 /** Bitmap tracking which VGA memory pages in the 0xa0000-0xbffff region has
366 * been remapped to allow direct access.
367 * @note It's quite possible that mapping in the 0xb0000-0xbffff isn't possible,
368 * but we're playing safe and cover the whole VGA MMIO region here. */
369 uint32_t bmPageRemappedVGA;
370
371 /** Flag indicating that there are dirty bits. This is used to optimize the handler resetting. */
372 bool fHasDirtyBits;
373 /** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
374 bool fRenderVRAM;
375 /** Whether 3D is enabled for the VM. */
376 bool f3DEnabled;
377 /** Set if state has been restored. */
378 bool fStateLoaded;
379 /** Flag whether to expose the legacy VGA interface to the guest. */
380 bool fLegacyVgaEnabled;
381#ifdef VBOX_WITH_VMSVGA
382 /* Whether the SVGA emulation is enabled or not. */
383 bool fVMSVGAEnabled;
384 bool fVMSVGA10;
385 bool fVMSVGAPciId;
386 bool fVMSVGAPciBarLayout;
387 /** Flag whether the SVGA3 interface is exposed to the guest. */
388 bool fVmSvga3;
389#else
390 bool afPadding4[5];
391#endif
392
393 struct {
394 uint32_t u32Padding1;
395 uint32_t iVRAM;
396#ifdef VBOX_WITH_VMSVGA
397 uint32_t iIO;
398 uint32_t iFIFO;
399#endif
400 } pciRegions;
401
402 /** The physical address the VRAM was assigned. */
403 RTGCPHYS GCPhysVRAM;
404 /** The critical section protect the instance data. */
405 PDMCRITSECT CritSect;
406
407 /* Keep track of ring 0 latched accesses to the VGA MMIO memory. */
408 uint64_t u64LastLatchedAccess;
409 uint32_t cLatchAccesses;
410 uint16_t uMaskLatchAccess;
411 uint16_t iMask;
412
413#ifdef VBE_BYTEWISE_IO
414 /** VBE read/write data/index flags */
415 uint8_t fReadVBEData;
416 uint8_t fWriteVBEData;
417 uint8_t fReadVBEIndex;
418 uint8_t fWriteVBEIndex;
419 /** VBE write data/index one byte buffer */
420 uint8_t cbWriteVBEData;
421 uint8_t cbWriteVBEIndex;
422 /** VBE Extra Data write address one byte buffer */
423 uint8_t cbWriteVBEExtraAddress;
424 uint8_t Padding5;
425#endif
426
427 /** Retrace emulation state */
428 bool fRealRetrace;
429 bool Padding6[HC_ARCH_BITS == 64 ? 7 : 3];
430 vga_retrace_s retrace_state;
431
432#ifdef VBOX_WITH_HGSMI
433 /** Base port in the assigned PCI I/O space. */
434 RTIOPORT IOPortBase;
435# ifdef VBOX_WITH_WDDM
436 uint8_t Padding10[2];
437 /** Specifies guest driver caps, i.e. whether it can handle IRQs from the
438 * adapter, the way it can handle async HGSMI command completion, etc. */
439 uint32_t fGuestCaps;
440 uint32_t fScanLineCfg;
441 uint32_t Padding11;
442# else
443 uint8_t Padding11[14];
444# endif
445
446 /** The critical section serializes the HGSMI IRQ setting/clearing. */
447 PDMCRITSECT CritSectIRQ;
448 /** VBVARaiseIRQ flags which were set when the guest was still processing previous IRQ. */
449 uint32_t fu32PendingGuestFlags;
450 uint32_t Padding12;
451#endif /* VBOX_WITH_HGSMI */
452
453 PDMLED Led3D;
454
455 struct {
456 volatile uint32_t cPending;
457 uint32_t Padding1;
458 union
459 {
460 RTLISTNODE PendingList;
461 /* make sure the structure sized cross different contexts correctly */
462 struct
463 {
464 R3PTRTYPE(void *) dummy1;
465 R3PTRTYPE(void *) dummy2;
466 } dummy;
467 };
468 } pendingVhwaCommands;
469
470 /** The MMIO handle of the legacy graphics buffer/regs at 0xa0000-0xbffff. */
471 PGMMMIO2HANDLE hMmioLegacy;
472
473 /** @name I/O ports for range 0x3c0-3cf.
474 * @{ */
475 IOMIOPORTHANDLE hIoPortAr;
476 IOMIOPORTHANDLE hIoPortMsrSt00;
477 IOMIOPORTHANDLE hIoPort3c3;
478 IOMIOPORTHANDLE hIoPortSr;
479 IOMIOPORTHANDLE hIoPortDac;
480 IOMIOPORTHANDLE hIoPortPos;
481 IOMIOPORTHANDLE hIoPortGr;
482 /** @} */
483
484 /** @name I/O ports for MDA 0x3b0-0x3bf (sparse)
485 * @{ */
486 IOMIOPORTHANDLE hIoPortMdaCrt;
487 IOMIOPORTHANDLE hIoPortMdaFcrSt;
488 /** @} */
489
490 /** @name I/O ports for CGA 0x3d0-0x3df (sparse)
491 * @{ */
492 IOMIOPORTHANDLE hIoPortCgaCrt;
493 IOMIOPORTHANDLE hIoPortCgaFcrSt;
494 /** @} */
495
496#ifdef VBOX_WITH_HGSMI
497 /** @name I/O ports for HGSMI 0x3b0-03b3 and 0x3d0-03d3 (ring-3 only)
498 * @{ */
499 IOMIOPORTHANDLE hIoPortHgsmiHost;
500 IOMIOPORTHANDLE hIoPortHgsmiGuest;
501 /** @} */
502#endif
503
504 /** @name I/O ports for Boch VBE 0x1ce-0x1cf
505 * @{ */
506 IOMIOPORTHANDLE hIoPortVbeIndex;
507 IOMIOPORTHANDLE hIoPortVbeData;
508 /** @} */
509
510 /** The BIOS printf I/O port. */
511 IOMIOPORTHANDLE hIoPortBios;
512 /** The VBE extra data I/O port. */
513 IOMIOPORTHANDLE hIoPortVbeExtra;
514 /** The logo command I/O port. */
515 IOMIOPORTHANDLE hIoPortCmdLogo;
516
517#ifdef VBOX_WITH_VMSVGA
518 /** VMSVGA: I/O port PCI region. */
519 IOMIOPORTHANDLE hIoPortVmSvga;
520 /** VMSVGA3: MMIO PCI region for the registers. */
521 IOMMMIOHANDLE hMmioSvga3;
522 /** VMSVGA: The MMIO2 handle of the FIFO PCI region. */
523 PGMMMIO2HANDLE hMmio2VmSvgaFifo;
524#endif
525 /** The MMIO2 handle of the VRAM. */
526 PGMMMIO2HANDLE hMmio2VRam;
527
528 STAMPROFILE StatRZMemoryRead;
529 STAMPROFILE StatR3MemoryRead;
530 STAMPROFILE StatRZMemoryWrite;
531 STAMPROFILE StatR3MemoryWrite;
532 STAMCOUNTER StatMapPage; /**< Counts IOMMmioMapMmio2Page calls. */
533 STAMCOUNTER StatMapReset; /**< Counts IOMMmioResetRegion calls. */
534 STAMCOUNTER StatUpdateDisp; /**< Counts vgaPortUpdateDisplay calls. */
535#ifdef VBOX_WITH_HGSMI
536 STAMCOUNTER StatHgsmiMdaCgaAccesses;
537#endif
538} VGAState;
539#ifdef VBOX
540/** VGA state. */
541typedef VGAState VGASTATE;
542/** Pointer to the VGA state. */
543typedef VGASTATE *PVGASTATE;
544AssertCompileMemberAlignment(VGASTATE, bank_offset, 8);
545AssertCompileMemberAlignment(VGASTATE, font_offsets, 8);
546AssertCompileMemberAlignment(VGASTATE, last_ch_attr, 8);
547AssertCompileMemberAlignment(VGASTATE, u32Marker, 8);
548AssertCompile(sizeof(uint64_t)/*bmPageMapBitmap*/ >= (_64K / GUEST_PAGE_SIZE / 8));
549#endif
550
551
552/**
553 * The VGA state data for ring-3 context.
554 */
555typedef struct VGASTATER3
556{
557 R3PTRTYPE(uint8_t *) pbVRam;
558 R3PTRTYPE(FNGETBPP *) get_bpp;
559 R3PTRTYPE(FNGETOFFSETS *) get_offsets;
560 R3PTRTYPE(FNGETRESOLUTION *) get_resolution;
561 R3PTRTYPE(FNRGBTOPIXEL *) rgb_to_pixel;
562 R3PTRTYPE(FNCURSORINVALIDATE *) cursor_invalidate;
563 R3PTRTYPE(FNCURSORDRAWLINE *) cursor_draw_line;
564
565 /** Pointer to the device instance.
566 * @note Only for getting our bearings in interface methods. */
567 PPDMDEVINSR3 pDevIns;
568#ifdef VBOX_WITH_HGSMI
569 R3PTRTYPE(PHGSMIINSTANCE) pHGSMI;
570#endif
571#ifdef VBOX_WITH_VDMA
572 R3PTRTYPE(PVBOXVDMAHOST) pVdma;
573#endif
574
575 /** LUN\#0: The display port base interface. */
576 PDMIBASE IBase;
577 /** LUN\#0: The display port interface. */
578 PDMIDISPLAYPORT IPort;
579#ifdef VBOX_WITH_HGSMI
580 /** LUN\#0: VBVA callbacks interface */
581 PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
582#endif
583 /** Status LUN: Leds interface. */
584 PDMILEDPORTS ILeds;
585
586 /** Pointer to base interface of the driver. */
587 R3PTRTYPE(PPDMIBASE) pDrvBase;
588 /** Pointer to display connector interface of the driver. */
589 R3PTRTYPE(PPDMIDISPLAYCONNECTOR) pDrv;
590
591 /** Status LUN: Partner of ILeds. */
592 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
593
594#ifdef VBOX_WITH_VMSVGA
595 /** The VMSVGA ring-3 state. */
596 VMSVGASTATER3 svga;
597#endif
598
599 /** The VGA BIOS ROM data. */
600 R3PTRTYPE(uint8_t *) pbVgaBios;
601 /** The size of the VGA BIOS ROM. */
602 uint64_t cbVgaBios;
603 /** The name of the VGA BIOS ROM file. */
604 R3PTRTYPE(char *) pszVgaBiosFile;
605
606 /** @name Logo data
607 * @{ */
608 /** Current logo data offset. */
609 uint32_t offLogoData;
610 /** The size of the BIOS logo data. */
611 uint32_t cbLogo;
612 /** Current logo command. */
613 uint16_t LogoCommand;
614 /** Bitmap width. */
615 uint16_t cxLogo;
616 /** Bitmap height. */
617 uint16_t cyLogo;
618 /** Bitmap planes. */
619 uint16_t cLogoPlanes;
620 /** Bitmap depth. */
621 uint16_t cLogoBits;
622 /** Bitmap compression. */
623 uint16_t LogoCompression;
624 /** Bitmap colors used. */
625 uint16_t cLogoUsedColors;
626 /** Palette size. */
627 uint16_t cLogoPalEntries;
628 /** Clear screen flag. */
629 uint8_t fLogoClearScreen;
630 bool fBootMenuInverse;
631 uint8_t Padding8[6];
632 /** Palette data. */
633 uint32_t au32LogoPalette[256];
634 /** The BIOS logo data. */
635 R3PTRTYPE(uint8_t *) pbLogo;
636 /** The name of the logo file. */
637 R3PTRTYPE(char *) pszLogoFile;
638 /** Bitmap image data. */
639 R3PTRTYPE(uint8_t *) pbLogoBitmap;
640 /** @} */
641
642 /** @name VBE extra data (modes)
643 * @{ */
644 /** The VBE BIOS extra data. */
645 R3PTRTYPE(uint8_t *) pbVBEExtraData;
646 /** The size of the VBE BIOS extra data. */
647 uint16_t cbVBEExtraData;
648 /** The VBE BIOS current memory address. */
649 uint16_t u16VBEExtraAddress;
650 uint16_t Padding7[2];
651 /** @} */
652
653} VGASTATER3;
654/** Pointer to the ring-3 VGA state. */
655typedef VGASTATER3 *PVGASTATER3;
656
657
658/**
659 * The VGA state data for ring-0 context.
660 */
661typedef struct VGASTATER0
662{
663 /** The R0 vram pointer. */
664 R0PTRTYPE(uint8_t *) pbVRam;
665#ifdef VBOX_WITH_VMSVGA
666 /** The VMSVGA ring-0 state. */
667 VMSVGASTATER0 svga;
668#endif
669} VGASTATER0;
670/** Pointer to the ring-0 VGA state. */
671typedef VGASTATER0 *PVGASTATER0;
672
673
674/**
675 * The VGA state data for raw-mode context.
676 */
677typedef struct VGASTATERC
678{
679 /** Pointer to the RC vram mapping. */
680 RCPTRTYPE(uint8_t *) pbVRam;
681} VGASTATERC;
682/** Pointer to the raw-mode VGA state. */
683typedef VGASTATERC *PVGASTATERC;
684
685
686/** The VGA state for the current context. */
687typedef CTX_SUFF(VGASTATE) VGASTATECC;
688/** Pointer to the VGA state for the current context. */
689typedef CTX_SUFF(PVGASTATE) PVGASTATECC;
690
691
692
693/** VBE Extra Data. */
694typedef VBEHeader VBEHEADER;
695/** Pointer to the VBE Extra Data. */
696typedef VBEHEADER *PVBEHEADER;
697
698#if !defined(VBOX) || defined(IN_RING3)
699static inline int c6_to_8(int v)
700{
701 int b;
702 v &= 0x3f;
703 b = v & 1;
704 return (v << 2) | (b << 1) | b;
705}
706#endif /* !VBOX || IN_RING3 */
707
708
709#ifdef VBOX_WITH_HGSMI
710int VBVAInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
711void VBVADestroy(PVGASTATECC pThisCC);
712int VBVAUpdateDisplay(PVGASTATE pThis, PVGASTATECC pThisCC);
713void VBVAReset(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
714void VBVAOnVBEChanged(PVGASTATE pThis, PVGASTATECC pThisCC);
715void VBVAOnResume(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
716
717bool VBVAIsPaused(PVGASTATECC pThisCC);
718#ifdef UNUSED_FUNCTION
719bool VBVAIsEnabled(PVGASTATECC pThisCC);
720#endif
721
722void VBVARaiseIrq(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t fFlags);
723
724int VBVAInfoScreen(PVGASTATE pThis, const VBVAINFOSCREEN RT_UNTRUSTED_VOLATILE_HOST *pScreen);
725#ifdef UNUSED_FUNCTION
726int VBVAGetInfoViewAndScreen(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32ViewIndex,
727 VBVAINFOVIEW *pView, VBVAINFOSCREEN *pScreen);
728#endif
729
730# ifdef VBOX_WITH_VIDEOHWACCEL
731DECLCALLBACK(int) vbvaR3VHWACommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface,
732 VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCmd);
733int vbvaVHWAConstruct(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
734
735void vbvaTimerCb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
736
737int vboxVBVASaveStatePrep(PPDMDEVINS pDevIns);
738int vboxVBVASaveStateDone(PPDMDEVINS pDevIns);
739# endif
740
741int vboxVBVASaveStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
742int vboxVBVALoadStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
743int vboxVBVALoadStateDone(PPDMDEVINS pDevIns);
744
745DECLCALLBACK(int) vbvaR3PortSendModeHint(PPDMIDISPLAYPORT pInterface, uint32_t cx, uint32_t cy, uint32_t cBPP,
746 uint32_t cDisplay, uint32_t dx, uint32_t dy, uint32_t fEnabled, uint32_t fNotifyGuest);
747
748# ifdef VBOX_WITH_VDMA
749typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
750int vboxVDMAConstruct(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t cPipeElements);
751void vboxVDMADestruct(PVBOXVDMAHOST pVdma);
752void vboxVDMAReset(PVBOXVDMAHOST pVdma);
753void vboxVDMAControl(PVBOXVDMAHOST pVdma, VBOXVDMA_CTL RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
754void vboxVDMACommand(PVBOXVDMAHOST pVdma, VBOXVDMACBUF_DR RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
755int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma);
756int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma);
757int vboxVDMASaveStateExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
758int vboxVDMASaveLoadExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM, uint32_t u32Version);
759int vboxVDMASaveLoadDone(struct VBOXVDMAHOST *pVdma);
760# endif /* VBOX_WITH_VDMA */
761
762#endif /* VBOX_WITH_HGSMI */
763
764# ifdef VBOX_WITH_VMSVGA
765int vgaR3UnregisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis);
766int vgaR3RegisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis, uint64_t cbFrameBuffer);
767int vgaR3UpdateDisplay(PVGASTATE pThis, unsigned xStart, unsigned yStart, unsigned width, unsigned height);
768# endif
769
770#ifndef VBOX
771void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
772 unsigned long vga_ram_offset, int vga_ram_size);
773uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
774void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
775void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
776
777void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
778 int poffset, int w,
779 unsigned int color0, unsigned int color1,
780 unsigned int color_xor);
781void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
782 int poffset, int w,
783 unsigned int color0, unsigned int color1,
784 unsigned int color_xor);
785void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
786 int poffset, int w,
787 unsigned int color0, unsigned int color1,
788 unsigned int color_xor);
789
790extern const uint8_t sr_mask[8];
791extern const uint8_t gr_mask[16];
792#endif /* !VBOX */
793
794#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_h */
795
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