DevVGA.h@ 86651

Last change on this file since 86651 was 86197, checked in by vboxsync, 4 years ago
Devices/Graphics: CFGM parameter to enable new capabilities.
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1	/* $Id: DevVGA.h 86197 2020-09-21 13:42:43Z vboxsync $ */
2	/** @file
3	* DevVGA - VBox VGA/VESA device, internal header.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU internal VGA defines.
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_h
44	#define VBOX_INCLUDED_SRC_Graphics_DevVGA_h
45	#ifndef RT_WITHOUT_PRAGMA_ONCE
46	# pragma once
47	#endif
48
49	#include <VBoxVideoVBE.h>
50	#include <VBoxVideoVBEPrivate.h>
51
52	#ifdef VBOX_WITH_HGSMI
53	# include "HGSMI/HGSMIHost.h"
54	#endif /* VBOX_WITH_HGSMI */
55	#include "DevVGASavedState.h"
56
57	#ifdef VBOX_WITH_VMSVGA
58	# include "DevVGA-SVGA.h"
59	#endif
60
61	#include <iprt/list.h>
62
63
64	/** Use VBE bytewise I/O. Only needed for Windows Longhorn/Vista betas and backwards compatibility. */
65	#define VBE_BYTEWISE_IO
66
67	#ifdef VBOX
68	/** The default amount of VRAM. */
69	# define VGA_VRAM_DEFAULT (_4M)
70	/** The maximum amount of VRAM. Limited by VBOX_MAX_ALLOC_PAGE_COUNT. */
71	# define VGA_VRAM_MAX (256 * _1M)
72	/** The minimum amount of VRAM. */
73	# define VGA_VRAM_MIN (_1M)
74	#endif
75
76
77	/** @name Macros dealing with partial ring-0/raw-mode VRAM mappings.
78	* @{ */
79	/** The size of the VGA ring-0 and raw-mode mapping.
80	*
81	* This is supposed to be all the VGA memory accessible to the guest.
82	* The initial value was 256KB but NTAllInOne.iso appears to access more
83	* thus the limit was upped to 512KB.
84	*
85	* @todo Someone with some VGA knowhow should make a better guess at this value.
86	*/
87	#define VGA_MAPPING_SIZE _512K
88	/** Enables partially mapping the VRAM into ring-0 rather than using the ring-3.
89	* The VGA_MAPPING_SIZE define sets the number of bytes that will be mapped. */
90	#define VGA_WITH_PARTIAL_RING0_MAPPING
91
92	/**
93	* Check buffer if an VRAM offset is within the right range or not.
94	*/
95	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
96	# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
97	do { \
98	if ((off) < VGA_MAPPING_SIZE) \
99	RT_UNTRUSTED_VALIDATED_FENCE(); \
100	else \
101	{ \
102	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
103	Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
104	return VINF_IOM_R3_MMIO_WRITE; \
105	} \
106	} while (0)
107	#else
108	# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
109	do { \
110	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
111	RT_UNTRUSTED_VALIDATED_FENCE(); \
112	} while (0)
113	#endif
114
115	/**
116	* Check buffer if an VRAM offset is within the right range or not.
117	*/
118	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
119	# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
120	do { \
121	if ((off) < VGA_MAPPING_SIZE) \
122	RT_UNTRUSTED_VALIDATED_FENCE(); \
123	else \
124	{ \
125	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
126	Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
127	(rcVar) = VINF_IOM_R3_MMIO_READ; \
128	return 0; \
129	} \
130	} while (0)
131	#else
132	# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
133	do { \
134	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
135	RT_UNTRUSTED_VALIDATED_FENCE(); \
136	NOREF(rcVar); \
137	} while (0)
138	#endif
139	/** @} */
140
141
142	#define MSR_COLOR_EMULATION 0x01
143	#define MSR_PAGE_SELECT 0x20
144
145	#define ST01_V_RETRACE 0x08
146	#define ST01_DISP_ENABLE 0x01
147
148	/* bochs VBE support */
149	#define CONFIG_BOCHS_VBE
150
151	#ifdef CONFIG_BOCHS_VBE
152
153	/* Cross reference with <VBoxVideoVBE.h> */
154	#define VBE_DISPI_INDEX_NB_SAVED 0xb /* Old number of saved registers (vbe_regs array, see vga_load) */
155	#define VBE_DISPI_INDEX_NB 0xd /* Total number of VBE registers */
156
157	#define VGA_STATE_COMMON_BOCHS_VBE \
158	uint16_t vbe_index; \
159	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
160	uint16_t alignment[2]; /* pad to 64 bits */ \
161	uint32_t vbe_start_addr; \
162	uint32_t vbe_line_offset; \
163	uint32_t vbe_bank_max;
164
165	#else
166
167	#define VGA_STATE_COMMON_BOCHS_VBE
168
169	#endif /* !CONFIG_BOCHS_VBE */
170
171	#define CH_ATTR_SIZE (160 * 100)
172	#define VGA_MAX_HEIGHT VBE_DISPI_MAX_YRES
173
174	typedef struct vga_retrace_s {
175	unsigned frame_cclks; /* Character clocks per frame. */
176	unsigned frame_ns; /* Frame duration in ns. */
177	unsigned cclk_ns; /* Character clock duration in ns. */
178	unsigned vb_start; /* Vertical blanking start (scanline). */
179	unsigned vb_end; /* Vertical blanking end (scanline). */
180	unsigned vb_end_ns; /* Vertical blanking end time (length) in ns. */
181	unsigned vs_start; /* Vertical sync start (scanline). */
182	unsigned vs_end; /* Vertical sync end (scanline). */
183	unsigned vs_start_ns; /* Vertical sync start time in ns. */
184	unsigned vs_end_ns; /* Vertical sync end time in ns. */
185	unsigned h_total; /* Horizontal total (cclks per scanline). */
186	unsigned h_total_ns; /* Scanline duration in ns. */
187	unsigned hb_start; /* Horizontal blanking start (cclk). */
188	unsigned hb_end; /* Horizontal blanking end (cclk). */
189	unsigned hb_end_ns; /* Horizontal blanking end time (length) in ns. */
190	unsigned v_freq_hz; /* Vertical refresh rate to emulate. */
191	} vga_retrace_s;
192
193	#ifndef VBOX
194	#define VGA_STATE_COMMON \
195	uint8_t *vram_ptr; \
196	unsigned long vram_offset; \
197	unsigned int vram_size; \
198	uint32_t latch; \
199	uint8_t sr_index; \
200	uint8_t sr[256]; \
201	uint8_t gr_index; \
202	uint8_t gr[256]; \
203	uint8_t ar_index; \
204	uint8_t ar[21]; \
205	int ar_flip_flop; \
206	uint8_t cr_index; \
207	uint8_t cr[256]; /* CRT registers */ \
208	uint8_t msr; /* Misc Output Register */ \
209	uint8_t fcr; /* Feature Control Register */ \
210	uint8_t st00; /* status 0 */ \
211	uint8_t st01; /* status 1 */ \
212	uint8_t dac_state; \
213	uint8_t dac_sub_index; \
214	uint8_t dac_read_index; \
215	uint8_t dac_write_index; \
216	uint8_t dac_cache[3]; /* used when writing */ \
217	uint8_t palette[768]; \
218	int32_t bank_offset; \
219	int (get_bpp)(struct VGAState s); \
220	void (get_offsets)(struct VGAState s, \
221	uint32_t *pline_offset, \
222	uint32_t *pstart_addr, \
223	uint32_t *pline_compare); \
224	void (get_resolution)(struct VGAState s, \
225	int *pwidth, \
226	int *pheight); \
227	VGA_STATE_COMMON_BOCHS_VBE \
228	/* display refresh support */ \
229	DisplayState *ds; \
230	uint32_t font_offsets[2]; \
231	int graphic_mode; \
232	uint8_t shift_control; \
233	uint8_t double_scan; \
234	uint32_t line_offset; \
235	uint32_t line_compare; \
236	uint32_t start_addr; \
237	uint32_t plane_updated; \
238	uint8_t last_cw, last_ch; \
239	uint32_t last_width, last_height; /* in chars or pixels */ \
240	uint32_t last_scr_width, last_scr_height; /* in pixels */ \
241	uint8_t cursor_start, cursor_end; \
242	uint32_t cursor_offset; \
243	unsigned int (*rgb_to_pixel)(unsigned int r, \
244	unsigned int g, unsigned b); \
245	/* hardware mouse cursor support */ \
246	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
247	void (cursor_invalidate)(struct VGAState s); \
248	void (cursor_draw_line)(struct VGAState s, uint8_t *d, int y); \
249	/* tell for each page if it has been updated since the last time */ \
250	uint32_t last_palette[256]; \
251	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
252
253	#else /* VBOX */
254
255	/* bird: Since we've changed types, reordered members, done alignment
256	paddings and more, VGA_STATE_COMMON was added directly to the
257	struct to make it more readable and easier to handle. */
258
259	struct VGAState;
260	typedef int FNGETBPP(struct VGAState *s);
261	typedef void FNGETOFFSETS(struct VGAState s, uint32_t pline_offset, uint32_t pstart_addr, uint32_t pline_compare);
262	typedef void FNGETRESOLUTION(struct VGAState s, int pwidth, int *pheight);
263	typedef unsigned int FNRGBTOPIXEL(unsigned int r, unsigned int g, unsigned b);
264	typedef void FNCURSORINVALIDATE(struct VGAState *s);
265	typedef void FNCURSORDRAWLINE(struct VGAState s, uint8_t d, int y);
266
267	#endif /* VBOX */
268
269	#ifdef VBOX_WITH_VDMA
270	typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
271	#endif
272
273	#ifdef VBOX_WITH_VIDEOHWACCEL
274	#define VBOX_VHWA_MAX_PENDING_COMMANDS 1000
275
276	typedef struct _VBOX_VHWA_PENDINGCMD
277	{
278	RTLISTNODE Node;
279	VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCommand;
280	} VBOX_VHWA_PENDINGCMD;
281	#endif
282
283
284	/**
285	* The shared VGA state data.
286	*/
287	typedef struct VGAState
288	{
289	uint32_t vram_size;
290	uint32_t latch;
291	uint8_t sr_index;
292	uint8_t sr[256];
293	uint8_t gr_index;
294	uint8_t gr[256];
295	uint8_t ar_index;
296	uint8_t ar[21];
297	int32_t ar_flip_flop;
298	uint8_t cr_index;
299	uint8_t cr[256]; /* CRT registers */
300	uint8_t msr; /* Misc Output Register */
301	uint8_t fcr; /* Feature Control Register */
302	uint8_t st00; /* status 0 */
303	uint8_t st01; /* status 1 */
304	uint8_t dac_state;
305	uint8_t dac_sub_index;
306	uint8_t dac_read_index;
307	uint8_t dac_write_index;
308	uint8_t dac_cache[3]; /* used when writing */
309	uint8_t palette[768];
310	int32_t bank_offset;
311	VGA_STATE_COMMON_BOCHS_VBE
312	/* display refresh support */
313	uint32_t font_offsets[2];
314	int32_t graphic_mode;
315	uint8_t shift_control;
316	uint8_t double_scan;
317	uint8_t padding1[2];
318	uint32_t line_offset;
319	uint32_t vga_addr_mask;
320	uint32_t padding1a;
321	uint32_t line_compare;
322	uint32_t start_addr;
323	uint32_t plane_updated;
324	uint8_t last_cw, last_ch, padding2[2];
325	uint32_t last_width, last_height; /* in chars or pixels */
326	uint32_t last_scr_width, last_scr_height; /* in pixels */
327	uint32_t last_bpp;
328	uint8_t cursor_start, cursor_end;
329	bool last_cur_blink, last_chr_blink;
330	uint32_t cursor_offset;
331	/** hardware mouse cursor support */
332	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
333	/** tell for each page if it has been updated since the last time */
334	uint32_t last_palette[256];
335	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
336
337	/** end-of-common-state-marker */
338	uint32_t u32Marker;
339
340	/** Refresh timer handle - HC. */
341	TMTIMERHANDLE hRefreshTimer;
342
343	#ifdef VBOX_WITH_VMSVGA
344	VMSVGASTATE svga;
345	#endif
346
347	/** The number of monitors. */
348	uint32_t cMonitors;
349	/** Current refresh timer interval. */
350	uint32_t cMilliesRefreshInterval;
351	/** Bitmap tracking dirty pages. */
352	uint32_t au32DirtyBitmap[VGA_VRAM_MAX / PAGE_SIZE / 32];
353
354	/** Flag indicating that there are dirty bits. This is used to optimize the handler resetting. */
355	bool fHasDirtyBits;
356	/** LFB was updated flag. */
357	bool fLFBUpdated;
358	/** Flag indicating that the VGA memory in the 0xa0000-0xbffff region has been remapped to allow direct access. */
359	bool fRemappedVGA;
360	/** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
361	bool fRenderVRAM;
362	/** Whether 3D is enabled for the VM. */
363	bool f3DEnabled;
364	/** Set if state has been restored. */
365	bool fStateLoaded;
366	#ifdef VBOX_WITH_VMSVGA
367	/* Whether the SVGA emulation is enabled or not. */
368	bool fVMSVGAEnabled;
369	bool fVMSVGA10;
370	bool fVMSVGAPciId;
371	bool fVMSVGAPciBarLayout;
372	bool Padding4[2];
373	#else
374	bool Padding4[4+2];
375	#endif
376
377	struct {
378	uint32_t u32Padding1;
379	uint32_t iVRAM;
380	#ifdef VBOX_WITH_VMSVGA
381	uint32_t iIO;
382	uint32_t iFIFO;
383	#endif
384	} pciRegions;
385
386	/** Physical access type for the linear frame buffer dirty page tracking. */
387	PGMPHYSHANDLERTYPE hLfbAccessHandlerType;
388
389	/** The physical address the VRAM was assigned. */
390	RTGCPHYS GCPhysVRAM;
391	/** The critical section protect the instance data. */
392	PDMCRITSECT CritSect;
393
394	/* Keep track of ring 0 latched accesses to the VGA MMIO memory. */
395	uint64_t u64LastLatchedAccess;
396	uint32_t cLatchAccesses;
397	uint16_t uMaskLatchAccess;
398	uint16_t iMask;
399
400	#ifdef VBE_BYTEWISE_IO
401	/** VBE read/write data/index flags */
402	uint8_t fReadVBEData;
403	uint8_t fWriteVBEData;
404	uint8_t fReadVBEIndex;
405	uint8_t fWriteVBEIndex;
406	/** VBE write data/index one byte buffer */
407	uint8_t cbWriteVBEData;
408	uint8_t cbWriteVBEIndex;
409	/** VBE Extra Data write address one byte buffer */
410	uint8_t cbWriteVBEExtraAddress;
411	uint8_t Padding5;
412	#endif
413
414	/** Retrace emulation state */
415	bool fRealRetrace;
416	bool Padding6[HC_ARCH_BITS == 64 ? 7 : 3];
417	vga_retrace_s retrace_state;
418
419	#ifdef VBOX_WITH_HGSMI
420	/** Base port in the assigned PCI I/O space. */
421	RTIOPORT IOPortBase;
422	# ifdef VBOX_WITH_WDDM
423	uint8_t Padding10[2];
424	/** Specifies guest driver caps, i.e. whether it can handle IRQs from the
425	* adapter, the way it can handle async HGSMI command completion, etc. */
426	uint32_t fGuestCaps;
427	uint32_t fScanLineCfg;
428	uint32_t Padding11;
429	# else
430	uint8_t Padding11[14];
431	# endif
432
433	/** The critical section serializes the HGSMI IRQ setting/clearing. */
434	PDMCRITSECT CritSectIRQ;
435	/** VBVARaiseIRQ flags which were set when the guest was still processing previous IRQ. */
436	uint32_t fu32PendingGuestFlags;
437	uint32_t Padding12;
438	#endif /* VBOX_WITH_HGSMI */
439
440	PDMLED Led3D;
441
442	struct {
443	volatile uint32_t cPending;
444	uint32_t Padding1;
445	union
446	{
447	RTLISTNODE PendingList;
448	/* make sure the structure sized cross different contexts correctly */
449	struct
450	{
451	R3PTRTYPE(void *) dummy1;
452	R3PTRTYPE(void *) dummy2;
453	} dummy;
454	};
455	} pendingVhwaCommands;
456
457	/** The MMIO handle of the legacy graphics buffer/regs at 0xa0000-0xbffff. */
458	PGMMMIO2HANDLE hMmioLegacy;
459
460	/** @name I/O ports for range 0x3c0-3cf.
461	* @{ */
462	IOMIOPORTHANDLE hIoPortAr;
463	IOMIOPORTHANDLE hIoPortMsrSt00;
464	IOMIOPORTHANDLE hIoPort3c3;
465	IOMIOPORTHANDLE hIoPortSr;
466	IOMIOPORTHANDLE hIoPortDac;
467	IOMIOPORTHANDLE hIoPortPos;
468	IOMIOPORTHANDLE hIoPortGr;
469	/** @} */
470
471	/** @name I/O ports for MDA 0x3b0-0x3bf (sparse)
472	* @{ */
473	IOMIOPORTHANDLE hIoPortMdaCrt;
474	IOMIOPORTHANDLE hIoPortMdaFcrSt;
475	/** @} */
476
477	/** @name I/O ports for CGA 0x3d0-0x3df (sparse)
478	* @{ */
479	IOMIOPORTHANDLE hIoPortCgaCrt;
480	IOMIOPORTHANDLE hIoPortCgaFcrSt;
481	/** @} */
482
483	#ifdef VBOX_WITH_HGSMI
484	/** @name I/O ports for HGSMI 0x3b0-03b3 and 0x3d0-03d3 (ring-3 only)
485	* @{ */
486	IOMIOPORTHANDLE hIoPortHgsmiHost;
487	IOMIOPORTHANDLE hIoPortHgsmiGuest;
488	/** @} */
489	#endif
490
491	/** @name I/O ports for Boch VBE 0x1ce-0x1cf
492	* @{ */
493	IOMIOPORTHANDLE hIoPortVbeIndex;
494	IOMIOPORTHANDLE hIoPortVbeData;
495	/** @} */
496
497	/** The BIOS printf I/O port. */
498	IOMIOPORTHANDLE hIoPortBios;
499	/** The VBE extra data I/O port. */
500	IOMIOPORTHANDLE hIoPortVbeExtra;
501	/** The logo command I/O port. */
502	IOMIOPORTHANDLE hIoPortCmdLogo;
503
504	#ifdef VBOX_WITH_VMSVGA
505	/** VMSVGA: I/O port PCI region. */
506	IOMIOPORTHANDLE hIoPortVmSvga;
507	/** VMSVGA: The MMIO2 handle of the FIFO PCI region. */
508	PGMMMIO2HANDLE hMmio2VmSvgaFifo;
509	#endif
510	/** The MMIO2 handle of the VRAM. */
511	PGMMMIO2HANDLE hMmio2VRam;
512
513	STAMPROFILE StatRZMemoryRead;
514	STAMPROFILE StatR3MemoryRead;
515	STAMPROFILE StatRZMemoryWrite;
516	STAMPROFILE StatR3MemoryWrite;
517	STAMCOUNTER StatMapPage; /*< Counts IOMMMIOMapMMIO2Page calls. /
518	STAMCOUNTER StatUpdateDisp; /*< Counts vgaPortUpdateDisplay calls. /
519	#ifdef VBOX_WITH_HGSMI
520	STAMCOUNTER StatHgsmiMdaCgaAccesses;
521	#endif
522	} VGAState;
523	#ifdef VBOX
524	/** VGA state. */
525	typedef VGAState VGASTATE;
526	/** Pointer to the VGA state. */
527	typedef VGASTATE *PVGASTATE;
528	AssertCompileMemberAlignment(VGASTATE, bank_offset, 8);
529	AssertCompileMemberAlignment(VGASTATE, font_offsets, 8);
530	AssertCompileMemberAlignment(VGASTATE, last_ch_attr, 8);
531	AssertCompileMemberAlignment(VGASTATE, u32Marker, 8);
532	#endif
533
534
535	/**
536	* The VGA state data for ring-3 context.
537	*/
538	typedef struct VGASTATER3
539	{
540	R3PTRTYPE(uint8_t *) pbVRam;
541	R3PTRTYPE(FNGETBPP *) get_bpp;
542	R3PTRTYPE(FNGETOFFSETS *) get_offsets;
543	R3PTRTYPE(FNGETRESOLUTION *) get_resolution;
544	R3PTRTYPE(FNRGBTOPIXEL *) rgb_to_pixel;
545	R3PTRTYPE(FNCURSORINVALIDATE *) cursor_invalidate;
546	R3PTRTYPE(FNCURSORDRAWLINE *) cursor_draw_line;
547
548	/** Pointer to the device instance.
549	* @note Only for getting our bearings in interface methods. */
550	PPDMDEVINSR3 pDevIns;
551	#ifdef VBOX_WITH_HGSMI
552	R3PTRTYPE(PHGSMIINSTANCE) pHGSMI;
553	#endif
554	#ifdef VBOX_WITH_VDMA
555	R3PTRTYPE(PVBOXVDMAHOST) pVdma;
556	#endif
557
558	/** LUN\#0: The display port base interface. */
559	PDMIBASE IBase;
560	/** LUN\#0: The display port interface. */
561	PDMIDISPLAYPORT IPort;
562	#ifdef VBOX_WITH_HGSMI
563	/** LUN\#0: VBVA callbacks interface */
564	PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
565	#endif
566	/** Status LUN: Leds interface. */
567	PDMILEDPORTS ILeds;
568
569	/** Pointer to base interface of the driver. */
570	R3PTRTYPE(PPDMIBASE) pDrvBase;
571	/** Pointer to display connector interface of the driver. */
572	R3PTRTYPE(PPDMIDISPLAYCONNECTOR) pDrv;
573
574	/** Status LUN: Partner of ILeds. */
575	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
576
577	#ifdef VBOX_WITH_VMSVGA
578	/** The VMSVGA ring-3 state. */
579	VMSVGASTATER3 svga;
580	#endif
581
582	/** The VGA BIOS ROM data. */
583	R3PTRTYPE(uint8_t *) pbVgaBios;
584	/** The size of the VGA BIOS ROM. */
585	uint64_t cbVgaBios;
586	/** The name of the VGA BIOS ROM file. */
587	R3PTRTYPE(char *) pszVgaBiosFile;
588
589	/** @name Logo data
590	* @{ */
591	/** Current logo data offset. */
592	uint32_t offLogoData;
593	/** The size of the BIOS logo data. */
594	uint32_t cbLogo;
595	/** Current logo command. */
596	uint16_t LogoCommand;
597	/** Bitmap width. */
598	uint16_t cxLogo;
599	/** Bitmap height. */
600	uint16_t cyLogo;
601	/** Bitmap planes. */
602	uint16_t cLogoPlanes;
603	/** Bitmap depth. */
604	uint16_t cLogoBits;
605	/** Bitmap compression. */
606	uint16_t LogoCompression;
607	/** Bitmap colors used. */
608	uint16_t cLogoUsedColors;
609	/** Palette size. */
610	uint16_t cLogoPalEntries;
611	/** Clear screen flag. */
612	uint8_t fLogoClearScreen;
613	bool fBootMenuInverse;
614	uint8_t Padding8[6];
615	/** Palette data. */
616	uint32_t au32LogoPalette[256];
617	/** The BIOS logo data. */
618	R3PTRTYPE(uint8_t *) pbLogo;
619	/** The name of the logo file. */
620	R3PTRTYPE(char *) pszLogoFile;
621	/** Bitmap image data. */
622	R3PTRTYPE(uint8_t *) pbLogoBitmap;
623	/** @} */
624
625	/** @name VBE extra data (modes)
626	* @{ */
627	/** The VBE BIOS extra data. */
628	R3PTRTYPE(uint8_t *) pbVBEExtraData;
629	/** The size of the VBE BIOS extra data. */
630	uint16_t cbVBEExtraData;
631	/** The VBE BIOS current memory address. */
632	uint16_t u16VBEExtraAddress;
633	uint16_t Padding7[2];
634	/** @} */
635
636	} VGASTATER3;
637	/** Pointer to the ring-3 VGA state. */
638	typedef VGASTATER3 *PVGASTATER3;
639
640
641	/**
642	* The VGA state data for ring-0 context.
643	*/
644	typedef struct VGASTATER0
645	{
646	/** The R0 vram pointer. */
647	R0PTRTYPE(uint8_t *) pbVRam;
648	#ifdef VBOX_WITH_VMSVGA
649	/** The VMSVGA ring-0 state. */
650	VMSVGASTATER0 svga;
651	#endif
652	} VGASTATER0;
653	/** Pointer to the ring-0 VGA state. */
654	typedef VGASTATER0 *PVGASTATER0;
655
656
657	/**
658	* The VGA state data for raw-mode context.
659	*/
660	typedef struct VGASTATERC
661	{
662	/** Pointer to the RC vram mapping. */
663	RCPTRTYPE(uint8_t *) pbVRam;
664	} VGASTATERC;
665	/** Pointer to the raw-mode VGA state. */
666	typedef VGASTATERC *PVGASTATERC;
667
668
669	/** The VGA state for the current context. */
670	typedef CTX_SUFF(VGASTATE) VGASTATECC;
671	/** Pointer to the VGA state for the current context. */
672	typedef CTX_SUFF(PVGASTATE) PVGASTATECC;
673
674
675
676	/** VBE Extra Data. */
677	typedef VBEHeader VBEHEADER;
678	/** Pointer to the VBE Extra Data. */
679	typedef VBEHEADER *PVBEHEADER;
680
681	#if !defined(VBOX) \|\| defined(IN_RING3)
682	static inline int c6_to_8(int v)
683	{
684	int b;
685	v &= 0x3f;
686	b = v & 1;
687	return (v << 2) \| (b << 1) \| b;
688	}
689	#endif /* !VBOX \|\| IN_RING3 */
690
691
692	#ifdef VBOX_WITH_HGSMI
693	int VBVAInit(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
694	void VBVADestroy(PVGASTATECC pThisCC);
695	int VBVAUpdateDisplay(PVGASTATE pThis, PVGASTATECC pThisCC);
696	void VBVAReset(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
697	void VBVAOnVBEChanged(PVGASTATE pThis, PVGASTATECC pThisCC);
698	void VBVAOnResume(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
699
700	bool VBVAIsPaused(PVGASTATECC pThisCC);
701	#ifdef UNUSED_FUNCTION
702	bool VBVAIsEnabled(PVGASTATECC pThisCC);
703	#endif
704
705	void VBVARaiseIrq(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t fFlags);
706
707	int VBVAInfoScreen(PVGASTATE pThis, const VBVAINFOSCREEN RT_UNTRUSTED_VOLATILE_HOST *pScreen);
708	#ifdef UNUSED_FUNCTION
709	int VBVAGetInfoViewAndScreen(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t u32ViewIndex,
710	VBVAINFOVIEW pView, VBVAINFOSCREEN pScreen);
711	#endif
712
713	/* @return host-guest flags that were set on reset
714	* this allows the caller to make further cleaning when needed,
715	* e.g. reset the IRQ */
716	uint32_t HGSMIReset(PHGSMIINSTANCE pIns);
717
718	# ifdef VBOX_WITH_VIDEOHWACCEL
719	DECLCALLBACK(int) vbvaR3VHWACommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface,
720	VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCmd);
721	int vbvaVHWAConstruct(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
722
723	void vbvaTimerCb(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
724
725	int vboxVBVASaveStatePrep(PPDMDEVINS pDevIns);
726	int vboxVBVASaveStateDone(PPDMDEVINS pDevIns);
727	# endif
728
729	int vboxVBVASaveStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
730	int vboxVBVALoadStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
731	int vboxVBVALoadStateDone(PPDMDEVINS pDevIns);
732
733	DECLCALLBACK(int) vbvaR3PortSendModeHint(PPDMIDISPLAYPORT pInterface, uint32_t cx, uint32_t cy, uint32_t cBPP,
734	uint32_t cDisplay, uint32_t dx, uint32_t dy, uint32_t fEnabled, uint32_t fNotifyGuest);
735
736	# ifdef VBOX_WITH_VDMA
737	typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
738	int vboxVDMAConstruct(PVGASTATE pThis, PVGASTATECC pThisCC, uint32_t cPipeElements);
739	void vboxVDMADestruct(PVBOXVDMAHOST pVdma);
740	void vboxVDMAReset(PVBOXVDMAHOST pVdma);
741	void vboxVDMAControl(PVBOXVDMAHOST pVdma, VBOXVDMA_CTL RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
742	void vboxVDMACommand(PVBOXVDMAHOST pVdma, VBOXVDMACBUF_DR RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
743	int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma);
744	int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma);
745	int vboxVDMASaveStateExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
746	int vboxVDMASaveLoadExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM, uint32_t u32Version);
747	int vboxVDMASaveLoadDone(struct VBOXVDMAHOST *pVdma);
748	# endif /* VBOX_WITH_VDMA */
749
750	#endif /* VBOX_WITH_HGSMI */
751
752	# ifdef VBOX_WITH_VMSVGA
753	int vgaR3UnregisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis);
754	int vgaR3RegisterVRAMHandler(PPDMDEVINS pDevIns, PVGASTATE pThis, uint64_t cbFrameBuffer);
755	int vgaR3UpdateDisplay(PVGASTATE pThis, unsigned xStart, unsigned yStart, unsigned width, unsigned height);
756	# endif
757
758	#ifndef VBOX
759	void vga_common_init(VGAState s, DisplayState ds, uint8_t *vga_ram_base,
760	unsigned long vga_ram_offset, int vga_ram_size);
761	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
762	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
763	void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
764
765	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
766	int poffset, int w,
767	unsigned int color0, unsigned int color1,
768	unsigned int color_xor);
769	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
770	int poffset, int w,
771	unsigned int color0, unsigned int color1,
772	unsigned int color_xor);
773	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
774	int poffset, int w,
775	unsigned int color0, unsigned int color1,
776	unsigned int color_xor);
777
778	extern const uint8_t sr_mask[8];
779	extern const uint8_t gr_mask[16];
780	#endif /* !VBOX */
781
782	#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_h */
783

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.h@ 86651

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