VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.h@ 82078

Last change on this file since 82078 was 82078, checked in by vboxsync, 5 years ago

DevVGA: Map part of the VRAM (512KB) into ring-0 for direct access there. bugref:9218
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File size: 27.1 KB
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1/* $Id: DevVGA.h 82078 2019-11-21 12:26:38Z vboxsync $ */
2/** @file
3 * DevVGA - VBox VGA/VESA device, internal header.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is based on:
19 *
20 * QEMU internal VGA defines.
21 *
22 * Copyright (c) 2003-2004 Fabrice Bellard
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_h
44#define VBOX_INCLUDED_SRC_Graphics_DevVGA_h
45#ifndef RT_WITHOUT_PRAGMA_ONCE
46# pragma once
47#endif
48
49#include <VBoxVideoVBE.h>
50#include <VBoxVideoVBEPrivate.h>
51
52#ifdef VBOX_WITH_HGSMI
53# include "HGSMI/HGSMIHost.h"
54#endif /* VBOX_WITH_HGSMI */
55#include "DevVGASavedState.h"
56
57#ifdef VBOX_WITH_VMSVGA
58# include "DevVGA-SVGA.h"
59#endif
60
61#include <iprt/list.h>
62
63
64/** Use VBE bytewise I/O. Only needed for Windows Longhorn/Vista betas and backwards compatibility. */
65#define VBE_BYTEWISE_IO
66
67#ifdef VBOX
68/** The default amount of VRAM. */
69# define VGA_VRAM_DEFAULT (_4M)
70/** The maximum amount of VRAM. Limited by VBOX_MAX_ALLOC_PAGE_COUNT. */
71# define VGA_VRAM_MAX (256 * _1M)
72/** The minimum amount of VRAM. */
73# define VGA_VRAM_MIN (_1M)
74#endif
75
76/** The size of the VGA ring-0 and raw-mode mapping.
77 *
78 * This is supposed to be all the VGA memory accessible to the guest.
79 * The initial value was 256KB but NTAllInOne.iso appears to access more
80 * thus the limit was upped to 512KB.
81 *
82 * @todo Someone with some VGA knowhow should make a better guess at this value.
83 */
84#define VGA_MAPPING_SIZE _512K
85/** Enables partially mapping the VRAM into ring-0 rather than using the ring-3.
86 * The VGA_MAPPING_SIZE define sets the number of bytes that will be mapped. */
87#define VGA_WITH_PARTIAL_RING0_MAPPING
88
89#define MSR_COLOR_EMULATION 0x01
90#define MSR_PAGE_SELECT 0x20
91
92#define ST01_V_RETRACE 0x08
93#define ST01_DISP_ENABLE 0x01
94
95/* bochs VBE support */
96#define CONFIG_BOCHS_VBE
97
98#ifdef CONFIG_BOCHS_VBE
99
100/* Cross reference with <VBoxVideoVBE.h> */
101#define VBE_DISPI_INDEX_NB_SAVED 0xb /* Old number of saved registers (vbe_regs array, see vga_load) */
102#define VBE_DISPI_INDEX_NB 0xd /* Total number of VBE registers */
103
104#define VGA_STATE_COMMON_BOCHS_VBE \
105 uint16_t vbe_index; \
106 uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
107 uint16_t alignment[2]; /* pad to 64 bits */ \
108 uint32_t vbe_start_addr; \
109 uint32_t vbe_line_offset; \
110 uint32_t vbe_bank_max;
111
112#else
113
114#define VGA_STATE_COMMON_BOCHS_VBE
115
116#endif /* !CONFIG_BOCHS_VBE */
117
118#define CH_ATTR_SIZE (160 * 100)
119#define VGA_MAX_HEIGHT VBE_DISPI_MAX_YRES
120
121typedef struct vga_retrace_s {
122 unsigned frame_cclks; /* Character clocks per frame. */
123 unsigned frame_ns; /* Frame duration in ns. */
124 unsigned cclk_ns; /* Character clock duration in ns. */
125 unsigned vb_start; /* Vertical blanking start (scanline). */
126 unsigned vb_end; /* Vertical blanking end (scanline). */
127 unsigned vb_end_ns; /* Vertical blanking end time (length) in ns. */
128 unsigned vs_start; /* Vertical sync start (scanline). */
129 unsigned vs_end; /* Vertical sync end (scanline). */
130 unsigned vs_start_ns; /* Vertical sync start time in ns. */
131 unsigned vs_end_ns; /* Vertical sync end time in ns. */
132 unsigned h_total; /* Horizontal total (cclks per scanline). */
133 unsigned h_total_ns; /* Scanline duration in ns. */
134 unsigned hb_start; /* Horizontal blanking start (cclk). */
135 unsigned hb_end; /* Horizontal blanking end (cclk). */
136 unsigned hb_end_ns; /* Horizontal blanking end time (length) in ns. */
137 unsigned v_freq_hz; /* Vertical refresh rate to emulate. */
138} vga_retrace_s;
139
140#ifndef VBOX
141#define VGA_STATE_COMMON \
142 uint8_t *vram_ptr; \
143 unsigned long vram_offset; \
144 unsigned int vram_size; \
145 uint32_t latch; \
146 uint8_t sr_index; \
147 uint8_t sr[256]; \
148 uint8_t gr_index; \
149 uint8_t gr[256]; \
150 uint8_t ar_index; \
151 uint8_t ar[21]; \
152 int ar_flip_flop; \
153 uint8_t cr_index; \
154 uint8_t cr[256]; /* CRT registers */ \
155 uint8_t msr; /* Misc Output Register */ \
156 uint8_t fcr; /* Feature Control Register */ \
157 uint8_t st00; /* status 0 */ \
158 uint8_t st01; /* status 1 */ \
159 uint8_t dac_state; \
160 uint8_t dac_sub_index; \
161 uint8_t dac_read_index; \
162 uint8_t dac_write_index; \
163 uint8_t dac_cache[3]; /* used when writing */ \
164 uint8_t palette[768]; \
165 int32_t bank_offset; \
166 int (*get_bpp)(struct VGAState *s); \
167 void (*get_offsets)(struct VGAState *s, \
168 uint32_t *pline_offset, \
169 uint32_t *pstart_addr, \
170 uint32_t *pline_compare); \
171 void (*get_resolution)(struct VGAState *s, \
172 int *pwidth, \
173 int *pheight); \
174 VGA_STATE_COMMON_BOCHS_VBE \
175 /* display refresh support */ \
176 DisplayState *ds; \
177 uint32_t font_offsets[2]; \
178 int graphic_mode; \
179 uint8_t shift_control; \
180 uint8_t double_scan; \
181 uint32_t line_offset; \
182 uint32_t line_compare; \
183 uint32_t start_addr; \
184 uint32_t plane_updated; \
185 uint8_t last_cw, last_ch; \
186 uint32_t last_width, last_height; /* in chars or pixels */ \
187 uint32_t last_scr_width, last_scr_height; /* in pixels */ \
188 uint8_t cursor_start, cursor_end; \
189 uint32_t cursor_offset; \
190 unsigned int (*rgb_to_pixel)(unsigned int r, \
191 unsigned int g, unsigned b); \
192 /* hardware mouse cursor support */ \
193 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
194 void (*cursor_invalidate)(struct VGAState *s); \
195 void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \
196 /* tell for each page if it has been updated since the last time */ \
197 uint32_t last_palette[256]; \
198 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
199
200#else /* VBOX */
201
202/* bird: Since we've changed types, reordered members, done alignment
203 paddings and more, VGA_STATE_COMMON was added directly to the
204 struct to make it more readable and easier to handle. */
205
206struct VGAState;
207typedef int FNGETBPP(struct VGAState *s);
208typedef void FNGETOFFSETS(struct VGAState *s, uint32_t *pline_offset, uint32_t *pstart_addr, uint32_t *pline_compare);
209typedef void FNGETRESOLUTION(struct VGAState *s, int *pwidth, int *pheight);
210typedef unsigned int FNRGBTOPIXEL(unsigned int r, unsigned int g, unsigned b);
211typedef void FNCURSORINVALIDATE(struct VGAState *s);
212typedef void FNCURSORDRAWLINE(struct VGAState *s, uint8_t *d, int y);
213
214#endif /* VBOX */
215
216#ifdef VBOX_WITH_VDMA
217typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
218#endif
219
220#ifdef VBOX_WITH_VIDEOHWACCEL
221#define VBOX_VHWA_MAX_PENDING_COMMANDS 1000
222
223typedef struct _VBOX_VHWA_PENDINGCMD
224{
225 RTLISTNODE Node;
226 VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCommand;
227} VBOX_VHWA_PENDINGCMD;
228#endif
229
230
231typedef struct VGAState
232{
233#ifndef VBOX
234 VGA_STATE_COMMON
235#else /* VBOX */
236 R3PTRTYPE(uint8_t *) vram_ptrR3;
237 R3PTRTYPE(FNGETBPP *) get_bpp;
238 R3PTRTYPE(FNGETOFFSETS *) get_offsets;
239 R3PTRTYPE(FNGETRESOLUTION *) get_resolution;
240 R3PTRTYPE(FNRGBTOPIXEL *) rgb_to_pixel;
241 R3PTRTYPE(FNCURSORINVALIDATE *) cursor_invalidate;
242 R3PTRTYPE(FNCURSORDRAWLINE *) cursor_draw_line;
243 RTR3PTR R3PtrCmnAlignment;
244 uint32_t vram_size;
245 uint32_t latch;
246 uint8_t sr_index;
247 uint8_t sr[256];
248 uint8_t gr_index;
249 uint8_t gr[256];
250 uint8_t ar_index;
251 uint8_t ar[21];
252 int32_t ar_flip_flop;
253 uint8_t cr_index;
254 uint8_t cr[256]; /* CRT registers */
255 uint8_t msr; /* Misc Output Register */
256 uint8_t fcr; /* Feature Control Register */
257 uint8_t st00; /* status 0 */
258 uint8_t st01; /* status 1 */
259 uint8_t dac_state;
260 uint8_t dac_sub_index;
261 uint8_t dac_read_index;
262 uint8_t dac_write_index;
263 uint8_t dac_cache[3]; /* used when writing */
264 uint8_t palette[768];
265 int32_t bank_offset;
266 VGA_STATE_COMMON_BOCHS_VBE
267 /* display refresh support */
268 uint32_t font_offsets[2];
269 int32_t graphic_mode;
270 uint8_t shift_control;
271 uint8_t double_scan;
272 uint8_t padding1[2];
273 uint32_t line_offset;
274 uint32_t vga_addr_mask;
275 uint32_t padding1a;
276 uint32_t line_compare;
277 uint32_t start_addr;
278 uint32_t plane_updated;
279 uint8_t last_cw, last_ch, padding2[2];
280 uint32_t last_width, last_height; /* in chars or pixels */
281 uint32_t last_scr_width, last_scr_height; /* in pixels */
282 uint32_t last_bpp;
283 uint8_t cursor_start, cursor_end;
284 bool last_cur_blink, last_chr_blink;
285 uint32_t cursor_offset;
286 /* hardware mouse cursor support */
287 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
288 /* tell for each page if it has been updated since the last time */
289 uint32_t last_palette[256];
290 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
291
292 /** end-of-common-state-marker */
293 uint32_t u32Marker;
294
295# ifdef VBOX_WITH_RAW_MODE_KEEP
296 /** Pointer to the device instance - RC Ptr. */
297 PPDMDEVINSRC pDevInsRC;
298 /** Pointer to the GC vram mapping. */
299 RCPTRTYPE(uint8_t *) vram_ptrRC;
300 uint32_t Padding1;
301# endif
302
303 /** Pointer to the device instance - R3 Ptr. */
304 PPDMDEVINSR3 pDevInsR3;
305# ifdef VBOX_WITH_HGSMI
306 R3PTRTYPE(PHGSMIINSTANCE) pHGSMI;
307# endif
308# ifdef VBOX_WITH_VDMA
309 R3PTRTYPE(PVBOXVDMAHOST) pVdma;
310# endif
311 /** LUN\#0: The display port base interface. */
312 PDMIBASE IBase;
313 /** LUN\#0: The display port interface. */
314 PDMIDISPLAYPORT IPort;
315# if defined(VBOX_WITH_HGSMI)
316 /** LUN\#0: VBVA callbacks interface */
317 PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
318# else
319 RTR3PTR Padding2;
320# endif
321 /** Status LUN: Leds interface. */
322 PDMILEDPORTS ILeds;
323
324 /** Pointer to base interface of the driver. */
325 R3PTRTYPE(PPDMIBASE) pDrvBase;
326 /** Pointer to display connector interface of the driver. */
327 R3PTRTYPE(PPDMIDISPLAYCONNECTOR) pDrv;
328
329 /** Status LUN: Partner of ILeds. */
330 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
331
332 /** Refresh timer handle - HC. */
333 TMTIMERHANDLE hRefreshTimer;
334
335 /** Pointer to the device instance - R0 Ptr. */
336 PPDMDEVINSR0 pDevInsR0;
337 /** The R0 vram pointer... */
338 R0PTRTYPE(uint8_t *) vram_ptrR0;
339
340# ifdef VBOX_WITH_VMSVGA
341 VMSVGAState svga;
342# endif
343
344 /** The number of monitors. */
345 uint32_t cMonitors;
346 /** Current refresh timer interval. */
347 uint32_t cMilliesRefreshInterval;
348 /** Bitmap tracking dirty pages. */
349 uint32_t au32DirtyBitmap[VGA_VRAM_MAX / PAGE_SIZE / 32];
350
351 /** Flag indicating that there are dirty bits. This is used to optimize the handler resetting. */
352 bool fHasDirtyBits;
353 /** LFB was updated flag. */
354 bool fLFBUpdated;
355 /** Flag indicating that the VGA memory in the 0xa0000-0xbffff region has been remapped to allow direct access. */
356 bool fRemappedVGA;
357 /** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
358 bool fRenderVRAM;
359 /** Whether 3D is enabled for the VM. */
360 bool f3DEnabled;
361# ifdef VBOX_WITH_VMSVGA
362 /* Whether the SVGA emulation is enabled or not. */
363 bool fVMSVGAEnabled;
364 bool fVMSVGAPciId;
365 bool fVMSVGAPciBarLayout;
366 bool Padding4[4];
367# else
368 bool Padding4[3+4];
369# endif
370
371 struct {
372 uint32_t u32Padding1;
373 uint32_t iVRAM;
374# ifdef VBOX_WITH_VMSVGA
375 uint32_t iIO;
376 uint32_t iFIFO;
377# endif
378 } pciRegions;
379
380 /** Physical access type for the linear frame buffer dirty page tracking. */
381 PGMPHYSHANDLERTYPE hLfbAccessHandlerType;
382
383 /** The physical address the VRAM was assigned. */
384 RTGCPHYS GCPhysVRAM;
385 /** The critical section protect the instance data. */
386 PDMCRITSECT CritSect;
387
388 STAMPROFILE StatRZMemoryRead;
389 STAMPROFILE StatR3MemoryRead;
390 STAMPROFILE StatRZMemoryWrite;
391 STAMPROFILE StatR3MemoryWrite;
392 STAMCOUNTER StatMapPage; /**< Counts IOMMMIOMapMMIO2Page calls. */
393 STAMCOUNTER StatUpdateDisp; /**< Counts vgaPortUpdateDisplay calls. */
394# ifdef VBOX_WITH_HGSMI
395 STAMCOUNTER StatHgsmiMdaCgaAccesses;
396# endif
397
398 /* Keep track of ring 0 latched accesses to the VGA MMIO memory. */
399 uint64_t u64LastLatchedAccess;
400 uint32_t cLatchAccesses;
401 uint16_t uMaskLatchAccess;
402 uint16_t iMask;
403
404# ifdef VBE_BYTEWISE_IO
405 /** VBE read/write data/index flags */
406 uint8_t fReadVBEData;
407 uint8_t fWriteVBEData;
408 uint8_t fReadVBEIndex;
409 uint8_t fWriteVBEIndex;
410 /** VBE write data/index one byte buffer */
411 uint8_t cbWriteVBEData;
412 uint8_t cbWriteVBEIndex;
413 /** VBE Extra Data write address one byte buffer */
414 uint8_t cbWriteVBEExtraAddress;
415 uint8_t Padding5;
416# endif
417
418 /** Retrace emulation state */
419 bool fRealRetrace;
420 bool Padding6[HC_ARCH_BITS == 64 ? 7 : 3];
421 vga_retrace_s retrace_state;
422
423 /** The VBE BIOS extra data. */
424 R3PTRTYPE(uint8_t *) pbVBEExtraData;
425 /** The size of the VBE BIOS extra data. */
426 uint16_t cbVBEExtraData;
427 /** The VBE BIOS current memory address. */
428 uint16_t u16VBEExtraAddress;
429 uint16_t Padding7[2];
430
431 /** The BIOS logo data. */
432 R3PTRTYPE(uint8_t *) pbLogo;
433 /** The name of the logo file. */
434 R3PTRTYPE(char *) pszLogoFile;
435 /** Bitmap image data. */
436 R3PTRTYPE(uint8_t *) pbLogoBitmap;
437 /** Current logo data offset. */
438 uint32_t offLogoData;
439 /** The size of the BIOS logo data. */
440 uint32_t cbLogo;
441 /** Current logo command. */
442 uint16_t LogoCommand;
443 /** Bitmap width. */
444 uint16_t cxLogo;
445 /** Bitmap height. */
446 uint16_t cyLogo;
447 /** Bitmap planes. */
448 uint16_t cLogoPlanes;
449 /** Bitmap depth. */
450 uint16_t cLogoBits;
451 /** Bitmap compression. */
452 uint16_t LogoCompression;
453 /** Bitmap colors used. */
454 uint16_t cLogoUsedColors;
455 /** Palette size. */
456 uint16_t cLogoPalEntries;
457 /** Clear screen flag. */
458 uint8_t fLogoClearScreen;
459 bool fBootMenuInverse;
460 uint8_t Padding8[6];
461 /** Palette data. */
462 uint32_t au32LogoPalette[256];
463
464 /** The VGA BIOS ROM data. */
465 R3PTRTYPE(uint8_t *) pbVgaBios;
466 /** The size of the VGA BIOS ROM. */
467 uint64_t cbVgaBios;
468 /** The name of the VGA BIOS ROM file. */
469 R3PTRTYPE(char *) pszVgaBiosFile;
470# if HC_ARCH_BITS == 32
471 uint32_t Padding9;
472# endif
473
474# ifdef VBOX_WITH_HGSMI
475 /** Base port in the assigned PCI I/O space. */
476 RTIOPORT IOPortBase;
477# ifdef VBOX_WITH_WDDM
478 uint8_t Padding10[2];
479 /** Specifies guest driver caps, i.e. whether it can handle IRQs from the
480 * adapter, the way it can handle async HGSMI command completion, etc. */
481 uint32_t fGuestCaps;
482 uint32_t fScanLineCfg;
483 uint32_t Padding11;
484# else
485 uint8_t Padding11[14];
486# endif
487
488 /** The critical section serializes the HGSMI IRQ setting/clearing. */
489 PDMCRITSECT CritSectIRQ;
490 /** VBVARaiseIRQ flags which were set when the guest was still processing previous IRQ. */
491 uint32_t fu32PendingGuestFlags;
492 uint32_t Padding12;
493# endif /* VBOX_WITH_HGSMI */
494
495 PDMLED Led3D;
496
497 struct {
498 volatile uint32_t cPending;
499 uint32_t Padding1;
500 union
501 {
502 RTLISTNODE PendingList;
503 /* make sure the structure sized cross different contexts correctly */
504 struct
505 {
506 R3PTRTYPE(void *) dummy1;
507 R3PTRTYPE(void *) dummy2;
508 } dummy;
509 };
510 } pendingVhwaCommands;
511
512 /** @name I/O ports for range 0x3c0-3cf.
513 * @{ */
514 IOMIOPORTHANDLE hIoPortAr;
515 IOMIOPORTHANDLE hIoPortMsrSt00;
516 IOMIOPORTHANDLE hIoPort3c3;
517 IOMIOPORTHANDLE hIoPortSr;
518 IOMIOPORTHANDLE hIoPortDac;
519 IOMIOPORTHANDLE hIoPortPos;
520 IOMIOPORTHANDLE hIoPortGr;
521 /** @} */
522
523 /** @name I/O ports for MDA 0x3b0-0x3bf (sparse)
524 * @{ */
525 IOMIOPORTHANDLE hIoPortMdaCrt;
526 IOMIOPORTHANDLE hIoPortMdaFcrSt;
527 /** @} */
528
529 /** @name I/O ports for CGA 0x3d0-0x3df (sparse)
530 * @{ */
531 IOMIOPORTHANDLE hIoPortCgaCrt;
532 IOMIOPORTHANDLE hIoPortCgaFcrSt;
533 /** @} */
534
535# ifdef VBOX_WITH_HGSMI
536 /** @name I/O ports for HGSMI 0x3b0-03b3 and 0x3d0-03d3 (ring-3 only)
537 * @{ */
538 IOMIOPORTHANDLE hIoPortHgsmiHost;
539 IOMIOPORTHANDLE hIoPortHgsmiGuest;
540 /** @} */
541# endif
542
543 /** @name I/O ports for Boch VBE 0x1ce-0x1cf
544 * @{ */
545 IOMIOPORTHANDLE hIoPortVbeIndex;
546 IOMIOPORTHANDLE hIoPortVbeData;
547 /** @} */
548
549 /** The BIOS printf I/O port. */
550 IOMIOPORTHANDLE hIoPortBios;
551 /** The VBE extra data I/O port. */
552 IOMIOPORTHANDLE hIoPortVbeExtra;
553 /** The logo command I/O port. */
554 IOMIOPORTHANDLE hIoPortCmdLogo;
555
556# ifdef VBOX_WITH_VMSVGA
557 /** VMSVGA: I/O port PCI region. */
558 IOMIOPORTHANDLE hIoPortVmSvga;
559 /** VMSVGA: The MMIO2 handle of the FIFO PCI region. */
560 PGMMMIO2HANDLE hMmio2VmSvgaFifo;
561# endif
562 /** The MMIO2 handle of the VRAM. */
563 PGMMMIO2HANDLE hMmio2VRam;
564#endif /* VBOX */
565} VGAState;
566#ifdef VBOX
567/** VGA state. */
568typedef VGAState VGASTATE;
569/** Pointer to the VGA state. */
570typedef VGASTATE *PVGASTATE;
571AssertCompileMemberAlignment(VGASTATE, bank_offset, 8);
572AssertCompileMemberAlignment(VGASTATE, font_offsets, 8);
573AssertCompileMemberAlignment(VGASTATE, last_ch_attr, 8);
574AssertCompileMemberAlignment(VGASTATE, u32Marker, 8);
575#endif
576
577/** VBE Extra Data. */
578typedef VBEHeader VBEHEADER;
579/** Pointer to the VBE Extra Data. */
580typedef VBEHEADER *PVBEHEADER;
581
582#if !defined(VBOX) || defined(IN_RING3)
583static inline int c6_to_8(int v)
584{
585 int b;
586 v &= 0x3f;
587 b = v & 1;
588 return (v << 2) | (b << 1) | b;
589}
590#endif /* !VBOX || IN_RING3 */
591
592
593#ifdef VBOX_WITH_HGSMI
594int VBVAInit (PVGASTATE pVGAState);
595void VBVADestroy (PVGASTATE pVGAState);
596int VBVAUpdateDisplay (PVGASTATE pVGAState);
597void VBVAReset (PVGASTATE pVGAState);
598void VBVAPause (PVGASTATE pVGAState, bool fPause);
599void VBVAOnVBEChanged(PVGASTATE pVGAState);
600void VBVAOnResume(PVGASTATE pThis);
601
602bool VBVAIsPaused(PVGASTATE pVGAState);
603bool VBVAIsEnabled(PVGASTATE pVGAState);
604
605void VBVARaiseIrq(PVGASTATE pVGAState, uint32_t fFlags);
606
607int VBVAInfoView(PVGASTATE pVGAState, const VBVAINFOVIEW RT_UNTRUSTED_VOLATILE_HOST *pView);
608int VBVAInfoScreen(PVGASTATE pVGAState, const VBVAINFOSCREEN RT_UNTRUSTED_VOLATILE_HOST *pScreen);
609int VBVAGetInfoViewAndScreen(PVGASTATE pVGAState, uint32_t u32ViewIndex, VBVAINFOVIEW *pView, VBVAINFOSCREEN *pScreen);
610
611/* @return host-guest flags that were set on reset
612 * this allows the caller to make further cleaning when needed,
613 * e.g. reset the IRQ */
614uint32_t HGSMIReset(PHGSMIINSTANCE pIns);
615
616# ifdef VBOX_WITH_VIDEOHWACCEL
617DECLCALLBACK(int) vbvaVHWACommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCmd);
618int vbvaVHWAConstruct(PVGASTATE pVGAState);
619int vbvaVHWAReset(PVGASTATE pVGAState);
620
621void vbvaTimerCb(PVGASTATE pVGAState);
622
623int vboxVBVASaveStatePrep(PPDMDEVINS pDevIns);
624int vboxVBVASaveStateDone(PPDMDEVINS pDevIns);
625# endif
626
627#define PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(_pcb) ( (PVGASTATE)((uint8_t *)(_pcb) - RT_OFFSETOF(VGASTATE, IVBVACallbacks)) )
628
629int vboxVBVASaveStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
630int vboxVBVALoadStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
631int vboxVBVALoadStateDone(PPDMDEVINS pDevIns);
632
633DECLCALLBACK(int) vgaUpdateDisplayAll(PVGASTATE pThis, bool fFailOnResize);
634DECLCALLBACK(int) vbvaPortSendModeHint(PPDMIDISPLAYPORT pInterface, uint32_t cx,
635 uint32_t cy, uint32_t cBPP,
636 uint32_t cDisplay, uint32_t dx,
637 uint32_t dy, uint32_t fEnabled,
638 uint32_t fNotifyGuest);
639
640# ifdef VBOX_WITH_VDMA
641typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
642int vboxVDMAConstruct(PVGASTATE pVGAState, uint32_t cPipeElements);
643void vboxVDMADestruct(PVBOXVDMAHOST pVdma);
644void vboxVDMAReset(PVBOXVDMAHOST pVdma);
645void vboxVDMAControl(PVBOXVDMAHOST pVdma, VBOXVDMA_CTL RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
646void vboxVDMACommand(PVBOXVDMAHOST pVdma, VBOXVDMACBUF_DR RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
647int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma);
648int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma);
649int vboxVDMASaveStateExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
650int vboxVDMASaveLoadExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM, uint32_t u32Version);
651int vboxVDMASaveLoadDone(struct VBOXVDMAHOST *pVdma);
652# endif /* VBOX_WITH_VDMA */
653
654#endif /* VBOX_WITH_HGSMI */
655
656# ifdef VBOX_WITH_VMSVGA
657int vgaR3RegisterVRAMHandler(PVGASTATE pVGAState, uint64_t cbFrameBuffer);
658int vgaR3UnregisterVRAMHandler(PVGASTATE pVGAState);
659int vgaR3UpdateDisplay(PVGASTATE pVGAState, unsigned xStart, unsigned yStart, unsigned width, unsigned height);
660# endif
661
662#ifndef VBOX
663void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
664 unsigned long vga_ram_offset, int vga_ram_size);
665uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
666void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
667void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
668
669void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
670 int poffset, int w,
671 unsigned int color0, unsigned int color1,
672 unsigned int color_xor);
673void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
674 int poffset, int w,
675 unsigned int color0, unsigned int color1,
676 unsigned int color_xor);
677void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
678 int poffset, int w,
679 unsigned int color0, unsigned int color1,
680 unsigned int color_xor);
681
682extern const uint8_t sr_mask[8];
683extern const uint8_t gr_mask[16];
684#endif /* !VBOX */
685
686#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_h */
687
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