DevVGA.h@ 82084

Last change on this file since 82084 was 82084, checked in by vboxsync, 5 years ago
DevVGA: Move VERIFY_VRAM_WRITE_OFF_RETURN and VERIFY_VRAM_READ_OFF_RETURN to the DevVGA.h header file so the macro we test for when defining them have a chance to be set. duh. bugref:9218
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1	/* $Id: DevVGA.h 82084 2019-11-21 16:26:41Z vboxsync $ */
2	/** @file
3	* DevVGA - VBox VGA/VESA device, internal header.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	* --------------------------------------------------------------------
17	*
18	* This code is based on:
19	*
20	* QEMU internal VGA defines.
21	*
22	* Copyright (c) 2003-2004 Fabrice Bellard
23	*
24	* Permission is hereby granted, free of charge, to any person obtaining a copy
25	* of this software and associated documentation files (the "Software"), to deal
26	* in the Software without restriction, including without limitation the rights
27	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28	* copies of the Software, and to permit persons to whom the Software is
29	* furnished to do so, subject to the following conditions:
30	*
31	* The above copyright notice and this permission notice shall be included in
32	* all copies or substantial portions of the Software.
33	*
34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40	* THE SOFTWARE.
41	*/
42
43	#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_h
44	#define VBOX_INCLUDED_SRC_Graphics_DevVGA_h
45	#ifndef RT_WITHOUT_PRAGMA_ONCE
46	# pragma once
47	#endif
48
49	#include <VBoxVideoVBE.h>
50	#include <VBoxVideoVBEPrivate.h>
51
52	#ifdef VBOX_WITH_HGSMI
53	# include "HGSMI/HGSMIHost.h"
54	#endif /* VBOX_WITH_HGSMI */
55	#include "DevVGASavedState.h"
56
57	#ifdef VBOX_WITH_VMSVGA
58	# include "DevVGA-SVGA.h"
59	#endif
60
61	#include <iprt/list.h>
62
63
64	/** Use VBE bytewise I/O. Only needed for Windows Longhorn/Vista betas and backwards compatibility. */
65	#define VBE_BYTEWISE_IO
66
67	#ifdef VBOX
68	/** The default amount of VRAM. */
69	# define VGA_VRAM_DEFAULT (_4M)
70	/** The maximum amount of VRAM. Limited by VBOX_MAX_ALLOC_PAGE_COUNT. */
71	# define VGA_VRAM_MAX (256 * _1M)
72	/** The minimum amount of VRAM. */
73	# define VGA_VRAM_MIN (_1M)
74	#endif
75
76
77	/** @name Macros dealing with partial ring-0/raw-mode VRAM mappings.
78	* @{ */
79	/** The size of the VGA ring-0 and raw-mode mapping.
80	*
81	* This is supposed to be all the VGA memory accessible to the guest.
82	* The initial value was 256KB but NTAllInOne.iso appears to access more
83	* thus the limit was upped to 512KB.
84	*
85	* @todo Someone with some VGA knowhow should make a better guess at this value.
86	*/
87	#define VGA_MAPPING_SIZE _512K
88	/** Enables partially mapping the VRAM into ring-0 rather than using the ring-3.
89	* The VGA_MAPPING_SIZE define sets the number of bytes that will be mapped. */
90	#define VGA_WITH_PARTIAL_RING0_MAPPING
91
92	/**
93	* Check buffer if an VRAM offset is within the right range or not.
94	*/
95	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
96	# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
97	do { \
98	if ((off) < VGA_MAPPING_SIZE) \
99	RT_UNTRUSTED_VALIDATED_FENCE(); \
100	else \
101	{ \
102	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
103	Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
104	return VINF_IOM_R3_MMIO_WRITE; \
105	} \
106	} while (0)
107	#else
108	# define VERIFY_VRAM_WRITE_OFF_RETURN(pThis, off) \
109	do { \
110	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), VINF_SUCCESS); \
111	RT_UNTRUSTED_VALIDATED_FENCE(); \
112	} while (0)
113	#endif
114
115	/**
116	* Check buffer if an VRAM offset is within the right range or not.
117	*/
118	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| (defined(IN_RING0) && defined(VGA_WITH_PARTIAL_RING0_MAPPING))
119	# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
120	do { \
121	if ((off) < VGA_MAPPING_SIZE) \
122	RT_UNTRUSTED_VALIDATED_FENCE(); \
123	else \
124	{ \
125	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
126	Log2(("%Rfn[%d]: %RX32 -> R3\n", __PRETTY_FUNCTION__, __LINE__, (off))); \
127	(rcVar) = VINF_IOM_R3_MMIO_READ; \
128	return 0; \
129	} \
130	} while (0)
131	#else
132	# define VERIFY_VRAM_READ_OFF_RETURN(pThis, off, rcVar) \
133	do { \
134	AssertMsgReturn((off) < (pThis)->vram_size, ("%RX32 !< %RX32\n", (uint32_t)(off), (pThis)->vram_size), 0xff); \
135	RT_UNTRUSTED_VALIDATED_FENCE(); \
136	NOREF(rcVar); \
137	} while (0)
138	#endif
139	/** @} */
140
141
142	#define MSR_COLOR_EMULATION 0x01
143	#define MSR_PAGE_SELECT 0x20
144
145	#define ST01_V_RETRACE 0x08
146	#define ST01_DISP_ENABLE 0x01
147
148	/* bochs VBE support */
149	#define CONFIG_BOCHS_VBE
150
151	#ifdef CONFIG_BOCHS_VBE
152
153	/* Cross reference with <VBoxVideoVBE.h> */
154	#define VBE_DISPI_INDEX_NB_SAVED 0xb /* Old number of saved registers (vbe_regs array, see vga_load) */
155	#define VBE_DISPI_INDEX_NB 0xd /* Total number of VBE registers */
156
157	#define VGA_STATE_COMMON_BOCHS_VBE \
158	uint16_t vbe_index; \
159	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
160	uint16_t alignment[2]; /* pad to 64 bits */ \
161	uint32_t vbe_start_addr; \
162	uint32_t vbe_line_offset; \
163	uint32_t vbe_bank_max;
164
165	#else
166
167	#define VGA_STATE_COMMON_BOCHS_VBE
168
169	#endif /* !CONFIG_BOCHS_VBE */
170
171	#define CH_ATTR_SIZE (160 * 100)
172	#define VGA_MAX_HEIGHT VBE_DISPI_MAX_YRES
173
174	typedef struct vga_retrace_s {
175	unsigned frame_cclks; /* Character clocks per frame. */
176	unsigned frame_ns; /* Frame duration in ns. */
177	unsigned cclk_ns; /* Character clock duration in ns. */
178	unsigned vb_start; /* Vertical blanking start (scanline). */
179	unsigned vb_end; /* Vertical blanking end (scanline). */
180	unsigned vb_end_ns; /* Vertical blanking end time (length) in ns. */
181	unsigned vs_start; /* Vertical sync start (scanline). */
182	unsigned vs_end; /* Vertical sync end (scanline). */
183	unsigned vs_start_ns; /* Vertical sync start time in ns. */
184	unsigned vs_end_ns; /* Vertical sync end time in ns. */
185	unsigned h_total; /* Horizontal total (cclks per scanline). */
186	unsigned h_total_ns; /* Scanline duration in ns. */
187	unsigned hb_start; /* Horizontal blanking start (cclk). */
188	unsigned hb_end; /* Horizontal blanking end (cclk). */
189	unsigned hb_end_ns; /* Horizontal blanking end time (length) in ns. */
190	unsigned v_freq_hz; /* Vertical refresh rate to emulate. */
191	} vga_retrace_s;
192
193	#ifndef VBOX
194	#define VGA_STATE_COMMON \
195	uint8_t *vram_ptr; \
196	unsigned long vram_offset; \
197	unsigned int vram_size; \
198	uint32_t latch; \
199	uint8_t sr_index; \
200	uint8_t sr[256]; \
201	uint8_t gr_index; \
202	uint8_t gr[256]; \
203	uint8_t ar_index; \
204	uint8_t ar[21]; \
205	int ar_flip_flop; \
206	uint8_t cr_index; \
207	uint8_t cr[256]; /* CRT registers */ \
208	uint8_t msr; /* Misc Output Register */ \
209	uint8_t fcr; /* Feature Control Register */ \
210	uint8_t st00; /* status 0 */ \
211	uint8_t st01; /* status 1 */ \
212	uint8_t dac_state; \
213	uint8_t dac_sub_index; \
214	uint8_t dac_read_index; \
215	uint8_t dac_write_index; \
216	uint8_t dac_cache[3]; /* used when writing */ \
217	uint8_t palette[768]; \
218	int32_t bank_offset; \
219	int (get_bpp)(struct VGAState s); \
220	void (get_offsets)(struct VGAState s, \
221	uint32_t *pline_offset, \
222	uint32_t *pstart_addr, \
223	uint32_t *pline_compare); \
224	void (get_resolution)(struct VGAState s, \
225	int *pwidth, \
226	int *pheight); \
227	VGA_STATE_COMMON_BOCHS_VBE \
228	/* display refresh support */ \
229	DisplayState *ds; \
230	uint32_t font_offsets[2]; \
231	int graphic_mode; \
232	uint8_t shift_control; \
233	uint8_t double_scan; \
234	uint32_t line_offset; \
235	uint32_t line_compare; \
236	uint32_t start_addr; \
237	uint32_t plane_updated; \
238	uint8_t last_cw, last_ch; \
239	uint32_t last_width, last_height; /* in chars or pixels */ \
240	uint32_t last_scr_width, last_scr_height; /* in pixels */ \
241	uint8_t cursor_start, cursor_end; \
242	uint32_t cursor_offset; \
243	unsigned int (*rgb_to_pixel)(unsigned int r, \
244	unsigned int g, unsigned b); \
245	/* hardware mouse cursor support */ \
246	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
247	void (cursor_invalidate)(struct VGAState s); \
248	void (cursor_draw_line)(struct VGAState s, uint8_t *d, int y); \
249	/* tell for each page if it has been updated since the last time */ \
250	uint32_t last_palette[256]; \
251	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
252
253	#else /* VBOX */
254
255	/* bird: Since we've changed types, reordered members, done alignment
256	paddings and more, VGA_STATE_COMMON was added directly to the
257	struct to make it more readable and easier to handle. */
258
259	struct VGAState;
260	typedef int FNGETBPP(struct VGAState *s);
261	typedef void FNGETOFFSETS(struct VGAState s, uint32_t pline_offset, uint32_t pstart_addr, uint32_t pline_compare);
262	typedef void FNGETRESOLUTION(struct VGAState s, int pwidth, int *pheight);
263	typedef unsigned int FNRGBTOPIXEL(unsigned int r, unsigned int g, unsigned b);
264	typedef void FNCURSORINVALIDATE(struct VGAState *s);
265	typedef void FNCURSORDRAWLINE(struct VGAState s, uint8_t d, int y);
266
267	#endif /* VBOX */
268
269	#ifdef VBOX_WITH_VDMA
270	typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
271	#endif
272
273	#ifdef VBOX_WITH_VIDEOHWACCEL
274	#define VBOX_VHWA_MAX_PENDING_COMMANDS 1000
275
276	typedef struct _VBOX_VHWA_PENDINGCMD
277	{
278	RTLISTNODE Node;
279	VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCommand;
280	} VBOX_VHWA_PENDINGCMD;
281	#endif
282
283
284	typedef struct VGAState
285	{
286	#ifndef VBOX
287	VGA_STATE_COMMON
288	#else /* VBOX */
289	R3PTRTYPE(uint8_t *) vram_ptrR3;
290	R3PTRTYPE(FNGETBPP *) get_bpp;
291	R3PTRTYPE(FNGETOFFSETS *) get_offsets;
292	R3PTRTYPE(FNGETRESOLUTION *) get_resolution;
293	R3PTRTYPE(FNRGBTOPIXEL *) rgb_to_pixel;
294	R3PTRTYPE(FNCURSORINVALIDATE *) cursor_invalidate;
295	R3PTRTYPE(FNCURSORDRAWLINE *) cursor_draw_line;
296	RTR3PTR R3PtrCmnAlignment;
297	uint32_t vram_size;
298	uint32_t latch;
299	uint8_t sr_index;
300	uint8_t sr[256];
301	uint8_t gr_index;
302	uint8_t gr[256];
303	uint8_t ar_index;
304	uint8_t ar[21];
305	int32_t ar_flip_flop;
306	uint8_t cr_index;
307	uint8_t cr[256]; /* CRT registers */
308	uint8_t msr; /* Misc Output Register */
309	uint8_t fcr; /* Feature Control Register */
310	uint8_t st00; /* status 0 */
311	uint8_t st01; /* status 1 */
312	uint8_t dac_state;
313	uint8_t dac_sub_index;
314	uint8_t dac_read_index;
315	uint8_t dac_write_index;
316	uint8_t dac_cache[3]; /* used when writing */
317	uint8_t palette[768];
318	int32_t bank_offset;
319	VGA_STATE_COMMON_BOCHS_VBE
320	/* display refresh support */
321	uint32_t font_offsets[2];
322	int32_t graphic_mode;
323	uint8_t shift_control;
324	uint8_t double_scan;
325	uint8_t padding1[2];
326	uint32_t line_offset;
327	uint32_t vga_addr_mask;
328	uint32_t padding1a;
329	uint32_t line_compare;
330	uint32_t start_addr;
331	uint32_t plane_updated;
332	uint8_t last_cw, last_ch, padding2[2];
333	uint32_t last_width, last_height; /* in chars or pixels */
334	uint32_t last_scr_width, last_scr_height; /* in pixels */
335	uint32_t last_bpp;
336	uint8_t cursor_start, cursor_end;
337	bool last_cur_blink, last_chr_blink;
338	uint32_t cursor_offset;
339	/* hardware mouse cursor support */
340	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
341	/* tell for each page if it has been updated since the last time */
342	uint32_t last_palette[256];
343	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
344
345	/** end-of-common-state-marker */
346	uint32_t u32Marker;
347
348	# ifdef VBOX_WITH_RAW_MODE_KEEP
349	/** Pointer to the device instance - RC Ptr. */
350	PPDMDEVINSRC pDevInsRC;
351	/** Pointer to the GC vram mapping. */
352	RCPTRTYPE(uint8_t *) vram_ptrRC;
353	uint32_t Padding1;
354	# endif
355
356	/** Pointer to the device instance - R3 Ptr. */
357	PPDMDEVINSR3 pDevInsR3;
358	# ifdef VBOX_WITH_HGSMI
359	R3PTRTYPE(PHGSMIINSTANCE) pHGSMI;
360	# endif
361	# ifdef VBOX_WITH_VDMA
362	R3PTRTYPE(PVBOXVDMAHOST) pVdma;
363	# endif
364	/** LUN\#0: The display port base interface. */
365	PDMIBASE IBase;
366	/** LUN\#0: The display port interface. */
367	PDMIDISPLAYPORT IPort;
368	# if defined(VBOX_WITH_HGSMI)
369	/** LUN\#0: VBVA callbacks interface */
370	PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
371	# else
372	RTR3PTR Padding2;
373	# endif
374	/** Status LUN: Leds interface. */
375	PDMILEDPORTS ILeds;
376
377	/** Pointer to base interface of the driver. */
378	R3PTRTYPE(PPDMIBASE) pDrvBase;
379	/** Pointer to display connector interface of the driver. */
380	R3PTRTYPE(PPDMIDISPLAYCONNECTOR) pDrv;
381
382	/** Status LUN: Partner of ILeds. */
383	R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
384
385	/** Refresh timer handle - HC. */
386	TMTIMERHANDLE hRefreshTimer;
387
388	/** Pointer to the device instance - R0 Ptr. */
389	PPDMDEVINSR0 pDevInsR0;
390	/** The R0 vram pointer... */
391	R0PTRTYPE(uint8_t *) vram_ptrR0;
392
393	# ifdef VBOX_WITH_VMSVGA
394	VMSVGAState svga;
395	# endif
396
397	/** The number of monitors. */
398	uint32_t cMonitors;
399	/** Current refresh timer interval. */
400	uint32_t cMilliesRefreshInterval;
401	/** Bitmap tracking dirty pages. */
402	uint32_t au32DirtyBitmap[VGA_VRAM_MAX / PAGE_SIZE / 32];
403
404	/** Flag indicating that there are dirty bits. This is used to optimize the handler resetting. */
405	bool fHasDirtyBits;
406	/** LFB was updated flag. */
407	bool fLFBUpdated;
408	/** Flag indicating that the VGA memory in the 0xa0000-0xbffff region has been remapped to allow direct access. */
409	bool fRemappedVGA;
410	/** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
411	bool fRenderVRAM;
412	/** Whether 3D is enabled for the VM. */
413	bool f3DEnabled;
414	# ifdef VBOX_WITH_VMSVGA
415	/* Whether the SVGA emulation is enabled or not. */
416	bool fVMSVGAEnabled;
417	bool fVMSVGAPciId;
418	bool fVMSVGAPciBarLayout;
419	bool Padding4[4];
420	# else
421	bool Padding4[3+4];
422	# endif
423
424	struct {
425	uint32_t u32Padding1;
426	uint32_t iVRAM;
427	# ifdef VBOX_WITH_VMSVGA
428	uint32_t iIO;
429	uint32_t iFIFO;
430	# endif
431	} pciRegions;
432
433	/** Physical access type for the linear frame buffer dirty page tracking. */
434	PGMPHYSHANDLERTYPE hLfbAccessHandlerType;
435
436	/** The physical address the VRAM was assigned. */
437	RTGCPHYS GCPhysVRAM;
438	/** The critical section protect the instance data. */
439	PDMCRITSECT CritSect;
440
441	STAMPROFILE StatRZMemoryRead;
442	STAMPROFILE StatR3MemoryRead;
443	STAMPROFILE StatRZMemoryWrite;
444	STAMPROFILE StatR3MemoryWrite;
445	STAMCOUNTER StatMapPage; /*< Counts IOMMMIOMapMMIO2Page calls. /
446	STAMCOUNTER StatUpdateDisp; /*< Counts vgaPortUpdateDisplay calls. /
447	# ifdef VBOX_WITH_HGSMI
448	STAMCOUNTER StatHgsmiMdaCgaAccesses;
449	# endif
450
451	/* Keep track of ring 0 latched accesses to the VGA MMIO memory. */
452	uint64_t u64LastLatchedAccess;
453	uint32_t cLatchAccesses;
454	uint16_t uMaskLatchAccess;
455	uint16_t iMask;
456
457	# ifdef VBE_BYTEWISE_IO
458	/** VBE read/write data/index flags */
459	uint8_t fReadVBEData;
460	uint8_t fWriteVBEData;
461	uint8_t fReadVBEIndex;
462	uint8_t fWriteVBEIndex;
463	/** VBE write data/index one byte buffer */
464	uint8_t cbWriteVBEData;
465	uint8_t cbWriteVBEIndex;
466	/** VBE Extra Data write address one byte buffer */
467	uint8_t cbWriteVBEExtraAddress;
468	uint8_t Padding5;
469	# endif
470
471	/** Retrace emulation state */
472	bool fRealRetrace;
473	bool Padding6[HC_ARCH_BITS == 64 ? 7 : 3];
474	vga_retrace_s retrace_state;
475
476	/** The VBE BIOS extra data. */
477	R3PTRTYPE(uint8_t *) pbVBEExtraData;
478	/** The size of the VBE BIOS extra data. */
479	uint16_t cbVBEExtraData;
480	/** The VBE BIOS current memory address. */
481	uint16_t u16VBEExtraAddress;
482	uint16_t Padding7[2];
483
484	/** The BIOS logo data. */
485	R3PTRTYPE(uint8_t *) pbLogo;
486	/** The name of the logo file. */
487	R3PTRTYPE(char *) pszLogoFile;
488	/** Bitmap image data. */
489	R3PTRTYPE(uint8_t *) pbLogoBitmap;
490	/** Current logo data offset. */
491	uint32_t offLogoData;
492	/** The size of the BIOS logo data. */
493	uint32_t cbLogo;
494	/** Current logo command. */
495	uint16_t LogoCommand;
496	/** Bitmap width. */
497	uint16_t cxLogo;
498	/** Bitmap height. */
499	uint16_t cyLogo;
500	/** Bitmap planes. */
501	uint16_t cLogoPlanes;
502	/** Bitmap depth. */
503	uint16_t cLogoBits;
504	/** Bitmap compression. */
505	uint16_t LogoCompression;
506	/** Bitmap colors used. */
507	uint16_t cLogoUsedColors;
508	/** Palette size. */
509	uint16_t cLogoPalEntries;
510	/** Clear screen flag. */
511	uint8_t fLogoClearScreen;
512	bool fBootMenuInverse;
513	uint8_t Padding8[6];
514	/** Palette data. */
515	uint32_t au32LogoPalette[256];
516
517	/** The VGA BIOS ROM data. */
518	R3PTRTYPE(uint8_t *) pbVgaBios;
519	/** The size of the VGA BIOS ROM. */
520	uint64_t cbVgaBios;
521	/** The name of the VGA BIOS ROM file. */
522	R3PTRTYPE(char *) pszVgaBiosFile;
523	# if HC_ARCH_BITS == 32
524	uint32_t Padding9;
525	# endif
526
527	# ifdef VBOX_WITH_HGSMI
528	/** Base port in the assigned PCI I/O space. */
529	RTIOPORT IOPortBase;
530	# ifdef VBOX_WITH_WDDM
531	uint8_t Padding10[2];
532	/** Specifies guest driver caps, i.e. whether it can handle IRQs from the
533	* adapter, the way it can handle async HGSMI command completion, etc. */
534	uint32_t fGuestCaps;
535	uint32_t fScanLineCfg;
536	uint32_t Padding11;
537	# else
538	uint8_t Padding11[14];
539	# endif
540
541	/** The critical section serializes the HGSMI IRQ setting/clearing. */
542	PDMCRITSECT CritSectIRQ;
543	/** VBVARaiseIRQ flags which were set when the guest was still processing previous IRQ. */
544	uint32_t fu32PendingGuestFlags;
545	uint32_t Padding12;
546	# endif /* VBOX_WITH_HGSMI */
547
548	PDMLED Led3D;
549
550	struct {
551	volatile uint32_t cPending;
552	uint32_t Padding1;
553	union
554	{
555	RTLISTNODE PendingList;
556	/* make sure the structure sized cross different contexts correctly */
557	struct
558	{
559	R3PTRTYPE(void *) dummy1;
560	R3PTRTYPE(void *) dummy2;
561	} dummy;
562	};
563	} pendingVhwaCommands;
564
565	/** @name I/O ports for range 0x3c0-3cf.
566	* @{ */
567	IOMIOPORTHANDLE hIoPortAr;
568	IOMIOPORTHANDLE hIoPortMsrSt00;
569	IOMIOPORTHANDLE hIoPort3c3;
570	IOMIOPORTHANDLE hIoPortSr;
571	IOMIOPORTHANDLE hIoPortDac;
572	IOMIOPORTHANDLE hIoPortPos;
573	IOMIOPORTHANDLE hIoPortGr;
574	/** @} */
575
576	/** @name I/O ports for MDA 0x3b0-0x3bf (sparse)
577	* @{ */
578	IOMIOPORTHANDLE hIoPortMdaCrt;
579	IOMIOPORTHANDLE hIoPortMdaFcrSt;
580	/** @} */
581
582	/** @name I/O ports for CGA 0x3d0-0x3df (sparse)
583	* @{ */
584	IOMIOPORTHANDLE hIoPortCgaCrt;
585	IOMIOPORTHANDLE hIoPortCgaFcrSt;
586	/** @} */
587
588	# ifdef VBOX_WITH_HGSMI
589	/** @name I/O ports for HGSMI 0x3b0-03b3 and 0x3d0-03d3 (ring-3 only)
590	* @{ */
591	IOMIOPORTHANDLE hIoPortHgsmiHost;
592	IOMIOPORTHANDLE hIoPortHgsmiGuest;
593	/** @} */
594	# endif
595
596	/** @name I/O ports for Boch VBE 0x1ce-0x1cf
597	* @{ */
598	IOMIOPORTHANDLE hIoPortVbeIndex;
599	IOMIOPORTHANDLE hIoPortVbeData;
600	/** @} */
601
602	/** The BIOS printf I/O port. */
603	IOMIOPORTHANDLE hIoPortBios;
604	/** The VBE extra data I/O port. */
605	IOMIOPORTHANDLE hIoPortVbeExtra;
606	/** The logo command I/O port. */
607	IOMIOPORTHANDLE hIoPortCmdLogo;
608
609	# ifdef VBOX_WITH_VMSVGA
610	/** VMSVGA: I/O port PCI region. */
611	IOMIOPORTHANDLE hIoPortVmSvga;
612	/** VMSVGA: The MMIO2 handle of the FIFO PCI region. */
613	PGMMMIO2HANDLE hMmio2VmSvgaFifo;
614	# endif
615	/** The MMIO2 handle of the VRAM. */
616	PGMMMIO2HANDLE hMmio2VRam;
617	#endif /* VBOX */
618	} VGAState;
619	#ifdef VBOX
620	/** VGA state. */
621	typedef VGAState VGASTATE;
622	/** Pointer to the VGA state. */
623	typedef VGASTATE *PVGASTATE;
624	AssertCompileMemberAlignment(VGASTATE, bank_offset, 8);
625	AssertCompileMemberAlignment(VGASTATE, font_offsets, 8);
626	AssertCompileMemberAlignment(VGASTATE, last_ch_attr, 8);
627	AssertCompileMemberAlignment(VGASTATE, u32Marker, 8);
628	#endif
629
630	/** VBE Extra Data. */
631	typedef VBEHeader VBEHEADER;
632	/** Pointer to the VBE Extra Data. */
633	typedef VBEHEADER *PVBEHEADER;
634
635	#if !defined(VBOX) \|\| defined(IN_RING3)
636	static inline int c6_to_8(int v)
637	{
638	int b;
639	v &= 0x3f;
640	b = v & 1;
641	return (v << 2) \| (b << 1) \| b;
642	}
643	#endif /* !VBOX \|\| IN_RING3 */
644
645
646	#ifdef VBOX_WITH_HGSMI
647	int VBVAInit (PVGASTATE pVGAState);
648	void VBVADestroy (PVGASTATE pVGAState);
649	int VBVAUpdateDisplay (PVGASTATE pVGAState);
650	void VBVAReset (PVGASTATE pVGAState);
651	void VBVAPause (PVGASTATE pVGAState, bool fPause);
652	void VBVAOnVBEChanged(PVGASTATE pVGAState);
653	void VBVAOnResume(PVGASTATE pThis);
654
655	bool VBVAIsPaused(PVGASTATE pVGAState);
656	bool VBVAIsEnabled(PVGASTATE pVGAState);
657
658	void VBVARaiseIrq(PVGASTATE pVGAState, uint32_t fFlags);
659
660	int VBVAInfoView(PVGASTATE pVGAState, const VBVAINFOVIEW RT_UNTRUSTED_VOLATILE_HOST *pView);
661	int VBVAInfoScreen(PVGASTATE pVGAState, const VBVAINFOSCREEN RT_UNTRUSTED_VOLATILE_HOST *pScreen);
662	int VBVAGetInfoViewAndScreen(PVGASTATE pVGAState, uint32_t u32ViewIndex, VBVAINFOVIEW pView, VBVAINFOSCREEN pScreen);
663
664	/* @return host-guest flags that were set on reset
665	* this allows the caller to make further cleaning when needed,
666	* e.g. reset the IRQ */
667	uint32_t HGSMIReset(PHGSMIINSTANCE pIns);
668
669	# ifdef VBOX_WITH_VIDEOHWACCEL
670	DECLCALLBACK(int) vbvaVHWACommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, VBOXVHWACMD RT_UNTRUSTED_VOLATILE_GUEST *pCmd);
671	int vbvaVHWAConstruct(PVGASTATE pVGAState);
672	int vbvaVHWAReset(PVGASTATE pVGAState);
673
674	void vbvaTimerCb(PVGASTATE pVGAState);
675
676	int vboxVBVASaveStatePrep(PPDMDEVINS pDevIns);
677	int vboxVBVASaveStateDone(PPDMDEVINS pDevIns);
678	# endif
679
680	#define PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(_pcb) ( (PVGASTATE)((uint8_t *)(_pcb) - RT_OFFSETOF(VGASTATE, IVBVACallbacks)) )
681
682	int vboxVBVASaveStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
683	int vboxVBVALoadStateExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
684	int vboxVBVALoadStateDone(PPDMDEVINS pDevIns);
685
686	DECLCALLBACK(int) vgaUpdateDisplayAll(PVGASTATE pThis, bool fFailOnResize);
687	DECLCALLBACK(int) vbvaPortSendModeHint(PPDMIDISPLAYPORT pInterface, uint32_t cx,
688	uint32_t cy, uint32_t cBPP,
689	uint32_t cDisplay, uint32_t dx,
690	uint32_t dy, uint32_t fEnabled,
691	uint32_t fNotifyGuest);
692
693	# ifdef VBOX_WITH_VDMA
694	typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
695	int vboxVDMAConstruct(PVGASTATE pVGAState, uint32_t cPipeElements);
696	void vboxVDMADestruct(PVBOXVDMAHOST pVdma);
697	void vboxVDMAReset(PVBOXVDMAHOST pVdma);
698	void vboxVDMAControl(PVBOXVDMAHOST pVdma, VBOXVDMA_CTL RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
699	void vboxVDMACommand(PVBOXVDMAHOST pVdma, VBOXVDMACBUF_DR RT_UNTRUSTED_VOLATILE_GUEST *pCmd, uint32_t cbCmd);
700	int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma);
701	int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma);
702	int vboxVDMASaveStateExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
703	int vboxVDMASaveLoadExecPerform(PCPDMDEVHLPR3 pHlp, struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM, uint32_t u32Version);
704	int vboxVDMASaveLoadDone(struct VBOXVDMAHOST *pVdma);
705	# endif /* VBOX_WITH_VDMA */
706
707	#endif /* VBOX_WITH_HGSMI */
708
709	# ifdef VBOX_WITH_VMSVGA
710	int vgaR3RegisterVRAMHandler(PVGASTATE pVGAState, uint64_t cbFrameBuffer);
711	int vgaR3UnregisterVRAMHandler(PVGASTATE pVGAState);
712	int vgaR3UpdateDisplay(PVGASTATE pVGAState, unsigned xStart, unsigned yStart, unsigned width, unsigned height);
713	# endif
714
715	#ifndef VBOX
716	void vga_common_init(VGAState s, DisplayState ds, uint8_t *vga_ram_base,
717	unsigned long vga_ram_offset, int vga_ram_size);
718	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
719	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
720	void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
721
722	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
723	int poffset, int w,
724	unsigned int color0, unsigned int color1,
725	unsigned int color_xor);
726	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
727	int poffset, int w,
728	unsigned int color0, unsigned int color1,
729	unsigned int color_xor);
730	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
731	int poffset, int w,
732	unsigned int color0, unsigned int color1,
733	unsigned int color_xor);
734
735	extern const uint8_t sr_mask[8];
736	extern const uint8_t gr_mask[16];
737	#endif /* !VBOX */
738
739	#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_h */
740

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA.h@ 82084

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