DevVGA_VDMA.cpp@ 69498

Last change on this file since 69498 was 69498, checked in by vboxsync, 7 years ago
backed out r118835 as it incorrectly updated the 'This file is based on' file headers.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 115.5 KB

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1	/* $Id: DevVGA_VDMA.cpp 69498 2017-10-28 15:07:25Z vboxsync $ */
2	/** @file
3	* Video DMA (VDMA) support.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_VGA
23	#include <VBox/VMMDev.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBoxVideo.h>
27	#include <iprt/semaphore.h>
28	#include <iprt/thread.h>
29	#include <iprt/mem.h>
30	#include <iprt/asm.h>
31	#include <iprt/list.h>
32	#include <iprt/param.h>
33
34	#include "DevVGA.h"
35	#include "HGSMI/SHGSMIHost.h"
36
37	#include <VBoxVideo3D.h>
38	#include <VBoxVideoHost3D.h>
39
40	#ifdef DEBUG_misha
41	# define VBOXVDBG_MEMCACHE_DISABLE
42	#endif
43
44	#ifndef VBOXVDBG_MEMCACHE_DISABLE
45	# include <iprt/memcache.h>
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef DEBUG_misha
53	# define WARN_BP() do { AssertFailed(); } while (0)
54	#else
55	# define WARN_BP() do { } while (0)
56	#endif
57	#define WARN(_msg) do { \
58	LogRel(_msg); \
59	WARN_BP(); \
60	} while (0)
61
62	#define VBOXVDMATHREAD_STATE_TERMINATED 0
63	#define VBOXVDMATHREAD_STATE_CREATING 1
64	#define VBOXVDMATHREAD_STATE_CREATED 3
65	#define VBOXVDMATHREAD_STATE_TERMINATING 4
66
67
68	/*********************************************************************************************************************************
69	* Structures and Typedefs *
70	*********************************************************************************************************************************/
71	struct VBOXVDMATHREAD;
72
73	typedef DECLCALLBACKPTR(void, PFNVBOXVDMATHREAD_CHANGED)(struct VBOXVDMATHREAD pThread, int rc, void pvThreadContext, void *pvChangeContext);
74
75	#ifdef VBOX_WITH_CRHGSMI
76	static DECLCALLBACK(int) vboxCmdVBVACmdCallout(struct VBOXVDMAHOST pVdma, struct VBOXCRCMDCTL pCmd, VBOXCRCMDCTL_CALLOUT_LISTENTRY *pEntry, PFNVBOXCRCMDCTL_CALLOUT_CB pfnCb);
77	#endif
78
79
80	typedef struct VBOXVDMATHREAD
81	{
82	RTTHREAD hWorkerThread;
83	RTSEMEVENT hEvent;
84	volatile uint32_t u32State;
85	PFNVBOXVDMATHREAD_CHANGED pfnChanged;
86	void *pvChanged;
87	} VBOXVDMATHREAD, *PVBOXVDMATHREAD;
88
89
90	/* state transformations:
91	*
92	* submitter \| processor
93	*
94	* LISTENING ---> PROCESSING
95	*
96	* */
97	#define VBVAEXHOSTCONTEXT_STATE_LISTENING 0
98	#define VBVAEXHOSTCONTEXT_STATE_PROCESSING 1
99
100	#define VBVAEXHOSTCONTEXT_ESTATE_DISABLED -1
101	#define VBVAEXHOSTCONTEXT_ESTATE_PAUSED 0
102	#define VBVAEXHOSTCONTEXT_ESTATE_ENABLED 1
103
104	typedef struct VBVAEXHOSTCONTEXT
105	{
106	VBVABUFFER *pVBVA;
107	volatile int32_t i32State;
108	volatile int32_t i32EnableState;
109	volatile uint32_t u32cCtls;
110	/* critical section for accessing ctl lists */
111	RTCRITSECT CltCritSect;
112	RTLISTANCHOR GuestCtlList;
113	RTLISTANCHOR HostCtlList;
114	#ifndef VBOXVDBG_MEMCACHE_DISABLE
115	RTMEMCACHE CtlCache;
116	#endif
117	} VBVAEXHOSTCONTEXT;
118
119	typedef enum
120	{
121	VBVAEXHOSTCTL_TYPE_UNDEFINED = 0,
122	VBVAEXHOSTCTL_TYPE_HH_INTERNAL_PAUSE,
123	VBVAEXHOSTCTL_TYPE_HH_INTERNAL_RESUME,
124	VBVAEXHOSTCTL_TYPE_HH_SAVESTATE,
125	VBVAEXHOSTCTL_TYPE_HH_LOADSTATE,
126	VBVAEXHOSTCTL_TYPE_HH_LOADSTATE_DONE,
127	VBVAEXHOSTCTL_TYPE_HH_BE_OPAQUE,
128	VBVAEXHOSTCTL_TYPE_HH_ON_HGCM_UNLOAD,
129	VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE,
130	VBVAEXHOSTCTL_TYPE_GHH_ENABLE,
131	VBVAEXHOSTCTL_TYPE_GHH_ENABLE_PAUSED,
132	VBVAEXHOSTCTL_TYPE_GHH_DISABLE,
133	VBVAEXHOSTCTL_TYPE_GHH_RESIZE
134	} VBVAEXHOSTCTL_TYPE;
135
136	struct VBVAEXHOSTCTL;
137
138	typedef DECLCALLBACKPTR(void, PFNVBVAEXHOSTCTL_COMPLETE)(VBVAEXHOSTCONTEXT pVbva, struct VBVAEXHOSTCTL pCtl, int rc, void *pvComplete);
139
140	typedef struct VBVAEXHOSTCTL
141	{
142	RTLISTNODE Node;
143	VBVAEXHOSTCTL_TYPE enmType;
144	union
145	{
146	struct
147	{
148	uint8_t * pu8Cmd;
149	uint32_t cbCmd;
150	} cmd;
151
152	struct
153	{
154	PSSMHANDLE pSSM;
155	uint32_t u32Version;
156	} state;
157	} u;
158	PFNVBVAEXHOSTCTL_COMPLETE pfnComplete;
159	void *pvComplete;
160	} VBVAEXHOSTCTL;
161
162	/* VBoxVBVAExHP**, i.e. processor functions, can NOT be called concurrently with each other,
163	* but can be called with other VBoxVBVAExS** (submitter) functions except Init/Start/Term aparently.
164	* Can only be called be the processor, i.e. the entity that acquired the processor state by direct or indirect call to the VBoxVBVAExHSCheckCommands
165	* see mor edetailed comments in headers for function definitions */
166	typedef enum
167	{
168	VBVAEXHOST_DATA_TYPE_NO_DATA = 0,
169	VBVAEXHOST_DATA_TYPE_CMD,
170	VBVAEXHOST_DATA_TYPE_HOSTCTL,
171	VBVAEXHOST_DATA_TYPE_GUESTCTL
172	} VBVAEXHOST_DATA_TYPE;
173
174
175	#ifdef VBOX_WITH_CRHGSMI
176	typedef struct VBOXVDMA_SOURCE
177	{
178	VBVAINFOSCREEN Screen;
179	VBOXCMDVBVA_SCREENMAP_DECL(uint32_t, aTargetMap);
180	} VBOXVDMA_SOURCE;
181	#endif
182
183	typedef struct VBOXVDMAHOST
184	{
185	PHGSMIINSTANCE pHgsmi;
186	PVGASTATE pVGAState;
187	#ifdef VBOX_WITH_CRHGSMI
188	VBVAEXHOSTCONTEXT CmdVbva;
189	VBOXVDMATHREAD Thread;
190	VBOXCRCMD_SVRINFO CrSrvInfo;
191	VBVAEXHOSTCTL* pCurRemainingHostCtl;
192	RTSEMEVENTMULTI HostCrCtlCompleteEvent;
193	int32_t volatile i32cHostCrCtlCompleted;
194	RTCRITSECT CalloutCritSect;
195	// VBOXVDMA_SOURCE aSources[VBOX_VIDEO_MAX_SCREENS];
196	#endif
197	#ifdef VBOX_VDMA_WITH_WATCHDOG
198	PTMTIMERR3 WatchDogTimer;
199	#endif
200	} VBOXVDMAHOST, *PVBOXVDMAHOST;
201
202
203	/*********************************************************************************************************************************
204	* Internal Functions *
205	*********************************************************************************************************************************/
206	#ifdef VBOX_WITH_CRHGSMI
207	static DECLCALLBACK(int) vdmaVBVANotifyDisable(PVGASTATE pVGAState);
208	static VBVAEXHOST_DATA_TYPE VBoxVBVAExHPDataGet(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t ppCmd, uint32_t pcbCmd);
209
210	static void VBoxVBVAExHPDataCompleteCmd(struct VBVAEXHOSTCONTEXT *pCmdVbva, uint32_t cbCmd);
211	static void VBoxVBVAExHPDataCompleteCtl(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl, int rc);
212
213	/* VBoxVBVAExHP**, i.e. processor functions, can NOT be called concurrently with each other,
214	* can be called concurrently with istelf as well as with other VBoxVBVAEx** functions except Init/Start/Term aparently */
215	static int VBoxVBVAExHSCheckCommands(struct VBVAEXHOSTCONTEXT *pCmdVbva);
216
217	static int VBoxVBVAExHSInit(struct VBVAEXHOSTCONTEXT *pCmdVbva);
218	static int VBoxVBVAExHSEnable(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVABUFFER pVBVA);
219	static int VBoxVBVAExHSDisable(struct VBVAEXHOSTCONTEXT *pCmdVbva);
220	static void VBoxVBVAExHSTerm(struct VBVAEXHOSTCONTEXT *pCmdVbva);
221	static int VBoxVBVAExHSSaveState(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM);
222	static int VBoxVBVAExHSLoadState(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM, uint32_t u32Version);
223
224	#endif /* VBOX_WITH_CRHGSMI */
225
226
227
228	#ifdef VBOX_WITH_CRHGSMI
229
230	static VBVAEXHOSTCTL* VBoxVBVAExHCtlAlloc(VBVAEXHOSTCONTEXT *pCmdVbva)
231	{
232	# ifndef VBOXVDBG_MEMCACHE_DISABLE
233	return (VBVAEXHOSTCTL*)RTMemCacheAlloc(pCmdVbva->CtlCache);
234	# else
235	return (VBVAEXHOSTCTL*)RTMemAlloc(sizeof (VBVAEXHOSTCTL));
236	# endif
237	}
238
239	static void VBoxVBVAExHCtlFree(VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl)
240	{
241	# ifndef VBOXVDBG_MEMCACHE_DISABLE
242	RTMemCacheFree(pCmdVbva->CtlCache, pCtl);
243	# else
244	RTMemFree(pCtl);
245	# endif
246	}
247
248	static VBVAEXHOSTCTL VBoxVBVAExHCtlCreate(VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL_TYPE enmType)
249	{
250	VBVAEXHOSTCTL* pCtl = VBoxVBVAExHCtlAlloc(pCmdVbva);
251	if (!pCtl)
252	{
253	WARN(("VBoxVBVAExHCtlAlloc failed\n"));
254	return NULL;
255	}
256
257	pCtl->enmType = enmType;
258	return pCtl;
259	}
260
261	static int vboxVBVAExHSProcessorAcquire(struct VBVAEXHOSTCONTEXT *pCmdVbva)
262	{
263	Assert(pCmdVbva->i32State >= VBVAEXHOSTCONTEXT_STATE_LISTENING);
264
265	if (ASMAtomicCmpXchgS32(&pCmdVbva->i32State, VBVAEXHOSTCONTEXT_STATE_PROCESSING, VBVAEXHOSTCONTEXT_STATE_LISTENING))
266	return VINF_SUCCESS;
267	return VERR_SEM_BUSY;
268	}
269
270	static VBVAEXHOSTCTL* vboxVBVAExHPCheckCtl(struct VBVAEXHOSTCONTEXT pCmdVbva, bool pfHostCtl, bool fHostOnlyMode)
271	{
272	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
273
274	if (!fHostOnlyMode && !ASMAtomicUoReadU32(&pCmdVbva->u32cCtls))
275	return NULL;
276
277	int rc = RTCritSectEnter(&pCmdVbva->CltCritSect);
278	if (RT_SUCCESS(rc))
279	{
280	VBVAEXHOSTCTL* pCtl = RTListGetFirst(&pCmdVbva->HostCtlList, VBVAEXHOSTCTL, Node);
281	if (pCtl)
282	*pfHostCtl = true;
283	else if (!fHostOnlyMode)
284	{
285	if (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) != VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
286	{
287	pCtl = RTListGetFirst(&pCmdVbva->GuestCtlList, VBVAEXHOSTCTL, Node);
288	/* pCtl can not be null here since pCmdVbva->u32cCtls is not null,
289	* and there are no HostCtl commands*/
290	Assert(pCtl);
291	*pfHostCtl = false;
292	}
293	}
294
295	if (pCtl)
296	{
297	RTListNodeRemove(&pCtl->Node);
298	ASMAtomicDecU32(&pCmdVbva->u32cCtls);
299	}
300
301	RTCritSectLeave(&pCmdVbva->CltCritSect);
302
303	return pCtl;
304	}
305	else
306	WARN(("RTCritSectEnter failed %d\n", rc));
307
308	return NULL;
309	}
310
311	static VBVAEXHOSTCTL* VBoxVBVAExHPCheckHostCtlOnDisable(struct VBVAEXHOSTCONTEXT *pCmdVbva)
312	{
313	bool fHostCtl = false;
314	VBVAEXHOSTCTL* pCtl = vboxVBVAExHPCheckCtl(pCmdVbva, &fHostCtl, true);
315	Assert(!pCtl \|\| fHostCtl);
316	return pCtl;
317	}
318
319	static int VBoxVBVAExHPPause(struct VBVAEXHOSTCONTEXT *pCmdVbva)
320	{
321	if (pCmdVbva->i32EnableState < VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
322	{
323	WARN(("Invalid state\n"));
324	return VERR_INVALID_STATE;
325	}
326
327	ASMAtomicWriteS32(&pCmdVbva->i32EnableState, VBVAEXHOSTCONTEXT_ESTATE_PAUSED);
328	return VINF_SUCCESS;
329	}
330
331	static int VBoxVBVAExHPResume(struct VBVAEXHOSTCONTEXT *pCmdVbva)
332	{
333	if (pCmdVbva->i32EnableState != VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
334	{
335	WARN(("Invalid state\n"));
336	return VERR_INVALID_STATE;
337	}
338
339	ASMAtomicWriteS32(&pCmdVbva->i32EnableState, VBVAEXHOSTCONTEXT_ESTATE_ENABLED);
340	return VINF_SUCCESS;
341	}
342
343	static bool vboxVBVAExHPCheckProcessCtlInternal(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl)
344	{
345	switch (pCtl->enmType)
346	{
347	case VBVAEXHOSTCTL_TYPE_HH_INTERNAL_PAUSE:
348	{
349	VBoxVBVAExHPPause(pCmdVbva);
350	VBoxVBVAExHPDataCompleteCtl(pCmdVbva, pCtl, VINF_SUCCESS);
351	return true;
352	}
353	case VBVAEXHOSTCTL_TYPE_HH_INTERNAL_RESUME:
354	{
355	VBoxVBVAExHPResume(pCmdVbva);
356	VBoxVBVAExHPDataCompleteCtl(pCmdVbva, pCtl, VINF_SUCCESS);
357	return true;
358	}
359	default:
360	return false;
361	}
362	}
363
364	static void vboxVBVAExHPProcessorRelease(struct VBVAEXHOSTCONTEXT *pCmdVbva)
365	{
366	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
367
368	ASMAtomicWriteS32(&pCmdVbva->i32State, VBVAEXHOSTCONTEXT_STATE_LISTENING);
369	}
370
371	static void vboxVBVAExHPHgEventSet(struct VBVAEXHOSTCONTEXT *pCmdVbva)
372	{
373	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
374	if (pCmdVbva->pVBVA)
375	ASMAtomicOrU32(&pCmdVbva->pVBVA->hostFlags.u32HostEvents, VBVA_F_STATE_PROCESSING);
376	}
377
378	static void vboxVBVAExHPHgEventClear(struct VBVAEXHOSTCONTEXT *pCmdVbva)
379	{
380	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
381	if (pCmdVbva->pVBVA)
382	ASMAtomicAndU32(&pCmdVbva->pVBVA->hostFlags.u32HostEvents, ~VBVA_F_STATE_PROCESSING);
383	}
384
385	static int vboxVBVAExHPCmdGet(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t ppCmd, uint32_t pcbCmd)
386	{
387	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
388	Assert(pCmdVbva->i32EnableState > VBVAEXHOSTCONTEXT_ESTATE_PAUSED);
389
390	VBVABUFFER *pVBVA = pCmdVbva->pVBVA;
391
392	uint32_t indexRecordFirst = pVBVA->indexRecordFirst;
393	uint32_t indexRecordFree = pVBVA->indexRecordFree;
394
395	Log(("first = %d, free = %d\n",
396	indexRecordFirst, indexRecordFree));
397
398	if (indexRecordFirst == indexRecordFree)
399	{
400	/* No records to process. Return without assigning output variables. */
401	return VINF_EOF;
402	}
403
404	uint32_t cbRecordCurrent = ASMAtomicReadU32(&pVBVA->aRecords[indexRecordFirst].cbRecord);
405
406	/* A new record need to be processed. */
407	if (cbRecordCurrent & VBVA_F_RECORD_PARTIAL)
408	{
409	/* the record is being recorded, try again */
410	return VINF_TRY_AGAIN;
411	}
412
413	uint32_t cbRecord = cbRecordCurrent & ~VBVA_F_RECORD_PARTIAL;
414
415	if (!cbRecord)
416	{
417	/* the record is being recorded, try again */
418	return VINF_TRY_AGAIN;
419	}
420
421	/* we should not get partial commands here actually */
422	Assert(cbRecord);
423
424	/* The size of largest contiguous chunk in the ring biffer. */
425	uint32_t u32BytesTillBoundary = pVBVA->cbData - pVBVA->off32Data;
426
427	/* The pointer to data in the ring buffer. */
428	uint8_t *pSrc = &pVBVA->au8Data[pVBVA->off32Data];
429
430	/* Fetch or point the data. */
431	if (u32BytesTillBoundary >= cbRecord)
432	{
433	/* The command does not cross buffer boundary. Return address in the buffer. */
434	*ppCmd = pSrc;
435	*pcbCmd = cbRecord;
436	return VINF_SUCCESS;
437	}
438
439	LogRel(("CmdVbva: cross-bound writes unsupported\n"));
440	return VERR_INVALID_STATE;
441	}
442
443	static void VBoxVBVAExHPDataCompleteCmd(struct VBVAEXHOSTCONTEXT *pCmdVbva, uint32_t cbCmd)
444	{
445	VBVABUFFER *pVBVA = pCmdVbva->pVBVA;
446	pVBVA->off32Data = (pVBVA->off32Data + cbCmd) % pVBVA->cbData;
447
448	pVBVA->indexRecordFirst = (pVBVA->indexRecordFirst + 1) % RT_ELEMENTS(pVBVA->aRecords);
449	}
450
451	static void VBoxVBVAExHPDataCompleteCtl(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl, int rc)
452	{
453	if (pCtl->pfnComplete)
454	pCtl->pfnComplete(pCmdVbva, pCtl, rc, pCtl->pvComplete);
455	else
456	VBoxVBVAExHCtlFree(pCmdVbva, pCtl);
457	}
458
459
460	static VBVAEXHOST_DATA_TYPE vboxVBVAExHPDataGet(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t ppCmd, uint32_t pcbCmd)
461	{
462	Assert(pCmdVbva->i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
463	VBVAEXHOSTCTL*pCtl;
464	bool fHostClt;
465
466	for (;;)
467	{
468	pCtl = vboxVBVAExHPCheckCtl(pCmdVbva, &fHostClt, false);
469	if (pCtl)
470	{
471	if (fHostClt)
472	{
473	if (!vboxVBVAExHPCheckProcessCtlInternal(pCmdVbva, pCtl))
474	{
475	ppCmd = (uint8_t)pCtl;
476	pcbCmd = sizeof (pCtl);
477	return VBVAEXHOST_DATA_TYPE_HOSTCTL;
478	}
479	continue;
480	}
481	else
482	{
483	ppCmd = (uint8_t)pCtl;
484	pcbCmd = sizeof (pCtl);
485	return VBVAEXHOST_DATA_TYPE_GUESTCTL;
486	}
487	}
488
489	if (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) <= VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
490	return VBVAEXHOST_DATA_TYPE_NO_DATA;
491
492	int rc = vboxVBVAExHPCmdGet(pCmdVbva, ppCmd, pcbCmd);
493	switch (rc)
494	{
495	case VINF_SUCCESS:
496	return VBVAEXHOST_DATA_TYPE_CMD;
497	case VINF_EOF:
498	return VBVAEXHOST_DATA_TYPE_NO_DATA;
499	case VINF_TRY_AGAIN:
500	RTThreadSleep(1);
501	continue;
502	default:
503	/* this is something really unexpected, i.e. most likely guest has written something incorrect to the VBVA buffer */
504	WARN(("Warning: vboxVBVAExHCmdGet returned unexpected status %d\n", rc));
505	return VBVAEXHOST_DATA_TYPE_NO_DATA;
506	}
507	}
508	/* not reached */
509	}
510
511	static VBVAEXHOST_DATA_TYPE VBoxVBVAExHPDataGet(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t ppCmd, uint32_t pcbCmd)
512	{
513	VBVAEXHOST_DATA_TYPE enmType = vboxVBVAExHPDataGet(pCmdVbva, ppCmd, pcbCmd);
514	if (enmType == VBVAEXHOST_DATA_TYPE_NO_DATA)
515	{
516	vboxVBVAExHPHgEventClear(pCmdVbva);
517	vboxVBVAExHPProcessorRelease(pCmdVbva);
518	/* we need to prevent racing between us clearing the flag and command check/submission thread, i.e.
519	* 1. we check the queue -> and it is empty
520	* 2. submitter adds command to the queue
521	* 3. submitter checks the "processing" -> and it is true , thus it does not submit a notification
522	* 4. we clear the "processing" state
523	* 5. ->here we need to re-check the queue state to ensure we do not leak the notification of the above command
524	* 6. if the queue appears to be not-empty set the "processing" state back to "true"
525	**/
526	int rc = vboxVBVAExHSProcessorAcquire(pCmdVbva);
527	if (RT_SUCCESS(rc))
528	{
529	/* we are the processor now */
530	enmType = vboxVBVAExHPDataGet(pCmdVbva, ppCmd, pcbCmd);
531	if (enmType == VBVAEXHOST_DATA_TYPE_NO_DATA)
532	{
533	vboxVBVAExHPProcessorRelease(pCmdVbva);
534	return VBVAEXHOST_DATA_TYPE_NO_DATA;
535	}
536
537	vboxVBVAExHPHgEventSet(pCmdVbva);
538	}
539	}
540
541	return enmType;
542	}
543
544	DECLINLINE(bool) vboxVBVAExHSHasCommands(struct VBVAEXHOSTCONTEXT *pCmdVbva)
545	{
546	VBVABUFFER *pVBVA = pCmdVbva->pVBVA;
547
548	if (pVBVA)
549	{
550	uint32_t indexRecordFirst = pVBVA->indexRecordFirst;
551	uint32_t indexRecordFree = pVBVA->indexRecordFree;
552
553	if (indexRecordFirst != indexRecordFree)
554	return true;
555	}
556
557	return !!ASMAtomicReadU32(&pCmdVbva->u32cCtls);
558	}
559
560	/** Checks whether the new commands are ready for processing
561	* @returns
562	* VINF_SUCCESS - there are commands are in a queue, and the given thread is now the processor (i.e. typically it would delegate processing to a worker thread)
563	* VINF_EOF - no commands in a queue
564	* VINF_ALREADY_INITIALIZED - another thread already processing the commands
565	* VERR_INVALID_STATE - the VBVA is paused or pausing */
566	static int VBoxVBVAExHSCheckCommands(struct VBVAEXHOSTCONTEXT *pCmdVbva)
567	{
568	int rc = vboxVBVAExHSProcessorAcquire(pCmdVbva);
569	if (RT_SUCCESS(rc))
570	{
571	/* we are the processor now */
572	if (vboxVBVAExHSHasCommands(pCmdVbva))
573	{
574	vboxVBVAExHPHgEventSet(pCmdVbva);
575	return VINF_SUCCESS;
576	}
577
578	vboxVBVAExHPProcessorRelease(pCmdVbva);
579	return VINF_EOF;
580	}
581	if (rc == VERR_SEM_BUSY)
582	return VINF_ALREADY_INITIALIZED;
583	return VERR_INVALID_STATE;
584	}
585
586	static int VBoxVBVAExHSInit(struct VBVAEXHOSTCONTEXT *pCmdVbva)
587	{
588	memset(pCmdVbva, 0, sizeof (*pCmdVbva));
589	int rc = RTCritSectInit(&pCmdVbva->CltCritSect);
590	if (RT_SUCCESS(rc))
591	{
592	# ifndef VBOXVDBG_MEMCACHE_DISABLE
593	rc = RTMemCacheCreate(&pCmdVbva->CtlCache, sizeof (VBVAEXHOSTCTL),
594	0, /* size_t cbAlignment */
595	UINT32_MAX, /* uint32_t cMaxObjects */
596	NULL, /* PFNMEMCACHECTOR pfnCtor*/
597	NULL, /* PFNMEMCACHEDTOR pfnDtor*/
598	NULL, /* void pvUser/
599	0 /* uint32_t fFlags*/
600	);
601	if (RT_SUCCESS(rc))
602	# endif
603	{
604	RTListInit(&pCmdVbva->GuestCtlList);
605	RTListInit(&pCmdVbva->HostCtlList);
606	pCmdVbva->i32State = VBVAEXHOSTCONTEXT_STATE_PROCESSING;
607	pCmdVbva->i32EnableState = VBVAEXHOSTCONTEXT_ESTATE_DISABLED;
608	return VINF_SUCCESS;
609	}
610	# ifndef VBOXVDBG_MEMCACHE_DISABLE
611	else
612	WARN(("RTMemCacheCreate failed %d\n", rc));
613	# endif
614	}
615	else
616	WARN(("RTCritSectInit failed %d\n", rc));
617
618	return rc;
619	}
620
621	DECLINLINE(bool) VBoxVBVAExHSIsEnabled(struct VBVAEXHOSTCONTEXT *pCmdVbva)
622	{
623	return (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) >= VBVAEXHOSTCONTEXT_ESTATE_PAUSED);
624	}
625
626	DECLINLINE(bool) VBoxVBVAExHSIsDisabled(struct VBVAEXHOSTCONTEXT *pCmdVbva)
627	{
628	return (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) == VBVAEXHOSTCONTEXT_ESTATE_DISABLED);
629	}
630
631	static int VBoxVBVAExHSEnable(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVABUFFER pVBVA)
632	{
633	if (VBoxVBVAExHSIsEnabled(pCmdVbva))
634	{
635	WARN(("VBVAEx is enabled already\n"));
636	return VERR_INVALID_STATE;
637	}
638
639	pCmdVbva->pVBVA = pVBVA;
640	pCmdVbva->pVBVA->hostFlags.u32HostEvents = 0;
641	ASMAtomicWriteS32(&pCmdVbva->i32EnableState, VBVAEXHOSTCONTEXT_ESTATE_ENABLED);
642	return VINF_SUCCESS;
643	}
644
645	static int VBoxVBVAExHSDisable(struct VBVAEXHOSTCONTEXT *pCmdVbva)
646	{
647	if (VBoxVBVAExHSIsDisabled(pCmdVbva))
648	return VINF_SUCCESS;
649
650	ASMAtomicWriteS32(&pCmdVbva->i32EnableState, VBVAEXHOSTCONTEXT_ESTATE_DISABLED);
651	return VINF_SUCCESS;
652	}
653
654	static void VBoxVBVAExHSTerm(struct VBVAEXHOSTCONTEXT *pCmdVbva)
655	{
656	/* ensure the processor is stopped */
657	Assert(pCmdVbva->i32State >= VBVAEXHOSTCONTEXT_STATE_LISTENING);
658
659	/* ensure no one tries to submit the command */
660	if (pCmdVbva->pVBVA)
661	pCmdVbva->pVBVA->hostFlags.u32HostEvents = 0;
662
663	Assert(RTListIsEmpty(&pCmdVbva->GuestCtlList));
664	Assert(RTListIsEmpty(&pCmdVbva->HostCtlList));
665
666	RTCritSectDelete(&pCmdVbva->CltCritSect);
667
668	# ifndef VBOXVDBG_MEMCACHE_DISABLE
669	RTMemCacheDestroy(pCmdVbva->CtlCache);
670	# endif
671
672	memset(pCmdVbva, 0, sizeof (*pCmdVbva));
673	}
674
675	static int vboxVBVAExHSSaveGuestCtl(struct VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl, uint8_t* pu8VramBase, PSSMHANDLE pSSM)
676	{
677	RT_NOREF(pCmdVbva);
678	int rc = SSMR3PutU32(pSSM, pCtl->enmType);
679	AssertRCReturn(rc, rc);
680	rc = SSMR3PutU32(pSSM, pCtl->u.cmd.cbCmd);
681	AssertRCReturn(rc, rc);
682	rc = SSMR3PutU32(pSSM, (uint32_t)(pCtl->u.cmd.pu8Cmd - pu8VramBase));
683	AssertRCReturn(rc, rc);
684
685	return VINF_SUCCESS;
686	}
687
688	static int vboxVBVAExHSSaveStateLocked(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM)
689	{
690	if (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) != VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
691	{
692	WARN(("vbva not paused\n"));
693	return VERR_INVALID_STATE;
694	}
695
696	int rc;
697	VBVAEXHOSTCTL* pCtl;
698	RTListForEach(&pCmdVbva->GuestCtlList, pCtl, VBVAEXHOSTCTL, Node)
699	{
700	rc = vboxVBVAExHSSaveGuestCtl(pCmdVbva, pCtl, pu8VramBase, pSSM);
701	AssertRCReturn(rc, rc);
702	}
703
704	rc = SSMR3PutU32(pSSM, 0);
705	AssertRCReturn(rc, rc);
706
707	return VINF_SUCCESS;
708	}
709
710
711	/** Saves state
712	* @returns - same as VBoxVBVAExHSCheckCommands, or failure on load state fail
713	*/
714	static int VBoxVBVAExHSSaveState(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM)
715	{
716	int rc = RTCritSectEnter(&pCmdVbva->CltCritSect);
717	if (RT_FAILURE(rc))
718	{
719	WARN(("RTCritSectEnter failed %d\n", rc));
720	return rc;
721	}
722
723	rc = vboxVBVAExHSSaveStateLocked(pCmdVbva, pu8VramBase, pSSM);
724	if (RT_FAILURE(rc))
725	WARN(("vboxVBVAExHSSaveStateLocked failed %d\n", rc));
726
727	RTCritSectLeave(&pCmdVbva->CltCritSect);
728
729	return rc;
730	}
731
732	static int vboxVBVAExHSLoadGuestCtl(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM, uint32_t u32Version)
733	{
734	RT_NOREF(u32Version);
735	uint32_t u32;
736	int rc = SSMR3GetU32(pSSM, &u32);
737	AssertLogRelRCReturn(rc, rc);
738
739	if (!u32)
740	return VINF_EOF;
741
742	VBVAEXHOSTCTL* pHCtl = VBoxVBVAExHCtlCreate(pCmdVbva, (VBVAEXHOSTCTL_TYPE)u32);
743	if (!pHCtl)
744	{
745	WARN(("VBoxVBVAExHCtlCreate failed\n"));
746	return VERR_NO_MEMORY;
747	}
748
749	rc = SSMR3GetU32(pSSM, &u32);
750	AssertLogRelRCReturn(rc, rc);
751	pHCtl->u.cmd.cbCmd = u32;
752
753	rc = SSMR3GetU32(pSSM, &u32);
754	AssertLogRelRCReturn(rc, rc);
755	pHCtl->u.cmd.pu8Cmd = pu8VramBase + u32;
756
757	RTListAppend(&pCmdVbva->GuestCtlList, &pHCtl->Node);
758	++pCmdVbva->u32cCtls;
759
760	return VINF_SUCCESS;
761	}
762
763
764	static int vboxVBVAExHSLoadStateLocked(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM, uint32_t u32Version)
765	{
766	if (ASMAtomicUoReadS32(&pCmdVbva->i32EnableState) != VBVAEXHOSTCONTEXT_ESTATE_PAUSED)
767	{
768	WARN(("vbva not stopped\n"));
769	return VERR_INVALID_STATE;
770	}
771
772	int rc;
773
774	do {
775	rc = vboxVBVAExHSLoadGuestCtl(pCmdVbva, pu8VramBase, pSSM, u32Version);
776	AssertLogRelRCReturn(rc, rc);
777	} while (VINF_EOF != rc);
778
779	return VINF_SUCCESS;
780	}
781
782	/** Loads state
783	* @returns - same as VBoxVBVAExHSCheckCommands, or failure on load state fail
784	*/
785	static int VBoxVBVAExHSLoadState(struct VBVAEXHOSTCONTEXT pCmdVbva, uint8_t pu8VramBase, PSSMHANDLE pSSM, uint32_t u32Version)
786	{
787	Assert(VGA_SAVEDSTATE_VERSION_3D <= u32Version);
788	int rc = RTCritSectEnter(&pCmdVbva->CltCritSect);
789	if (RT_FAILURE(rc))
790	{
791	WARN(("RTCritSectEnter failed %d\n", rc));
792	return rc;
793	}
794
795	rc = vboxVBVAExHSLoadStateLocked(pCmdVbva, pu8VramBase, pSSM, u32Version);
796	if (RT_FAILURE(rc))
797	WARN(("vboxVBVAExHSSaveStateLocked failed %d\n", rc));
798
799	RTCritSectLeave(&pCmdVbva->CltCritSect);
800
801	return rc;
802	}
803
804	typedef enum
805	{
806	VBVAEXHOSTCTL_SOURCE_GUEST = 0,
807	VBVAEXHOSTCTL_SOURCE_HOST
808	} VBVAEXHOSTCTL_SOURCE;
809
810
811	static int VBoxVBVAExHCtlSubmit(VBVAEXHOSTCONTEXT pCmdVbva, VBVAEXHOSTCTL pCtl, VBVAEXHOSTCTL_SOURCE enmSource, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void *pvComplete)
812	{
813	if (!VBoxVBVAExHSIsEnabled(pCmdVbva))
814	{
815	Log(("cmd vbva not enabled\n"));
816	return VERR_INVALID_STATE;
817	}
818
819	pCtl->pfnComplete = pfnComplete;
820	pCtl->pvComplete = pvComplete;
821
822	int rc = RTCritSectEnter(&pCmdVbva->CltCritSect);
823	if (RT_SUCCESS(rc))
824	{
825	if (!VBoxVBVAExHSIsEnabled(pCmdVbva))
826	{
827	Log(("cmd vbva not enabled\n"));
828	RTCritSectLeave(&pCmdVbva->CltCritSect);
829	return VERR_INVALID_STATE;
830	}
831
832	if (enmSource > VBVAEXHOSTCTL_SOURCE_GUEST)
833	{
834	RTListAppend(&pCmdVbva->HostCtlList, &pCtl->Node);
835	}
836	else
837	RTListAppend(&pCmdVbva->GuestCtlList, &pCtl->Node);
838
839	ASMAtomicIncU32(&pCmdVbva->u32cCtls);
840
841	RTCritSectLeave(&pCmdVbva->CltCritSect);
842
843	rc = VBoxVBVAExHSCheckCommands(pCmdVbva);
844	}
845	else
846	WARN(("RTCritSectEnter failed %d\n", rc));
847
848	return rc;
849	}
850
851	void VBoxVDMAThreadNotifyConstructSucceeded(PVBOXVDMATHREAD pThread, void *pvThreadContext)
852	{
853	Assert(pThread->u32State == VBOXVDMATHREAD_STATE_CREATING);
854	PFNVBOXVDMATHREAD_CHANGED pfnChanged = pThread->pfnChanged;
855	void *pvChanged = pThread->pvChanged;
856
857	pThread->pfnChanged = NULL;
858	pThread->pvChanged = NULL;
859
860	ASMAtomicWriteU32(&pThread->u32State, VBOXVDMATHREAD_STATE_CREATED);
861
862	if (pfnChanged)
863	pfnChanged(pThread, VINF_SUCCESS, pvThreadContext, pvChanged);
864	}
865
866	void VBoxVDMAThreadNotifyTerminatingSucceeded(PVBOXVDMATHREAD pThread, void *pvThreadContext)
867	{
868	Assert(pThread->u32State == VBOXVDMATHREAD_STATE_TERMINATING);
869	PFNVBOXVDMATHREAD_CHANGED pfnChanged = pThread->pfnChanged;
870	void *pvChanged = pThread->pvChanged;
871
872	pThread->pfnChanged = NULL;
873	pThread->pvChanged = NULL;
874
875	if (pfnChanged)
876	pfnChanged(pThread, VINF_SUCCESS, pvThreadContext, pvChanged);
877	}
878
879	DECLINLINE(bool) VBoxVDMAThreadIsTerminating(PVBOXVDMATHREAD pThread)
880	{
881	return ASMAtomicUoReadU32(&pThread->u32State) == VBOXVDMATHREAD_STATE_TERMINATING;
882	}
883
884	void VBoxVDMAThreadInit(PVBOXVDMATHREAD pThread)
885	{
886	memset(pThread, 0, sizeof (*pThread));
887	pThread->u32State = VBOXVDMATHREAD_STATE_TERMINATED;
888	}
889
890	int VBoxVDMAThreadCleanup(PVBOXVDMATHREAD pThread)
891	{
892	uint32_t u32State = ASMAtomicUoReadU32(&pThread->u32State);
893	switch (u32State)
894	{
895	case VBOXVDMATHREAD_STATE_TERMINATED:
896	return VINF_SUCCESS;
897	case VBOXVDMATHREAD_STATE_TERMINATING:
898	{
899	int rc = RTThreadWait(pThread->hWorkerThread, RT_INDEFINITE_WAIT, NULL);
900	if (!RT_SUCCESS(rc))
901	{
902	WARN(("RTThreadWait failed %d\n", rc));
903	return rc;
904	}
905
906	RTSemEventDestroy(pThread->hEvent);
907
908	ASMAtomicWriteU32(&pThread->u32State, VBOXVDMATHREAD_STATE_TERMINATED);
909	return VINF_SUCCESS;
910	}
911	default:
912	WARN(("invalid state"));
913	return VERR_INVALID_STATE;
914	}
915	}
916
917	int VBoxVDMAThreadCreate(PVBOXVDMATHREAD pThread, PFNRTTHREAD pfnThread, void pvThread, PFNVBOXVDMATHREAD_CHANGED pfnCreated, voidpvCreated)
918	{
919	int rc = VBoxVDMAThreadCleanup(pThread);
920	if (RT_FAILURE(rc))
921	{
922	WARN(("VBoxVDMAThreadCleanup failed %d\n", rc));
923	return rc;
924	}
925
926	rc = RTSemEventCreate(&pThread->hEvent);
927	if (RT_SUCCESS(rc))
928	{
929	pThread->u32State = VBOXVDMATHREAD_STATE_CREATING;
930	pThread->pfnChanged = pfnCreated;
931	pThread->pvChanged = pvCreated;
932	rc = RTThreadCreate(&pThread->hWorkerThread, pfnThread, pvThread, 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "VDMA");
933	if (RT_SUCCESS(rc))
934	return VINF_SUCCESS;
935	else
936	WARN(("RTThreadCreate failed %d\n", rc));
937
938	RTSemEventDestroy(pThread->hEvent);
939	}
940	else
941	WARN(("RTSemEventCreate failed %d\n", rc));
942
943	pThread->u32State = VBOXVDMATHREAD_STATE_TERMINATED;
944
945	return rc;
946	}
947
948	DECLINLINE(int) VBoxVDMAThreadEventNotify(PVBOXVDMATHREAD pThread)
949	{
950	int rc = RTSemEventSignal(pThread->hEvent);
951	AssertRC(rc);
952	return rc;
953	}
954
955	DECLINLINE(int) VBoxVDMAThreadEventWait(PVBOXVDMATHREAD pThread, RTMSINTERVAL cMillies)
956	{
957	int rc = RTSemEventWait(pThread->hEvent, cMillies);
958	AssertRC(rc);
959	return rc;
960	}
961
962	int VBoxVDMAThreadTerm(PVBOXVDMATHREAD pThread, PFNVBOXVDMATHREAD_CHANGED pfnTerminated, void*pvTerminated, bool fNotify)
963	{
964	int rc;
965	do
966	{
967	uint32_t u32State = ASMAtomicUoReadU32(&pThread->u32State);
968	switch (u32State)
969	{
970	case VBOXVDMATHREAD_STATE_CREATED:
971	pThread->pfnChanged = pfnTerminated;
972	pThread->pvChanged = pvTerminated;
973	ASMAtomicWriteU32(&pThread->u32State, VBOXVDMATHREAD_STATE_TERMINATING);
974	if (fNotify)
975	{
976	rc = VBoxVDMAThreadEventNotify(pThread);
977	AssertRC(rc);
978	}
979	return VINF_SUCCESS;
980	case VBOXVDMATHREAD_STATE_TERMINATING:
981	case VBOXVDMATHREAD_STATE_TERMINATED:
982	{
983	WARN(("thread is marked to termination or terminated\nn"));
984	return VERR_INVALID_STATE;
985	}
986	case VBOXVDMATHREAD_STATE_CREATING:
987	{
988	/* wait till the thread creation is completed */
989	WARN(("concurrent thread create/destron\n"));
990	RTThreadYield();
991	continue;
992	}
993	default:
994	WARN(("invalid state"));
995	return VERR_INVALID_STATE;
996	}
997	} while (1);
998
999	WARN(("should never be here\n"));
1000	return VERR_INTERNAL_ERROR;
1001	}
1002
1003	static int vdmaVBVACtlSubmitSync(PVBOXVDMAHOST pVdma, VBVAEXHOSTCTL* pCtl, VBVAEXHOSTCTL_SOURCE enmSource);
1004
1005	typedef DECLCALLBACK(void) FNVBOXVDMACRCTL_CALLBACK(PVGASTATE pVGAState, PVBOXVDMACMD_CHROMIUM_CTL pCmd, void* pvContext);
1006	typedef FNVBOXVDMACRCTL_CALLBACK *PFNVBOXVDMACRCTL_CALLBACK;
1007
1008	typedef struct VBOXVDMACMD_CHROMIUM_CTL_PRIVATE
1009	{
1010	uint32_t cRefs;
1011	int32_t rc;
1012	PFNVBOXVDMACRCTL_CALLBACK pfnCompletion;
1013	void *pvCompletion;
1014	VBOXVDMACMD_CHROMIUM_CTL Cmd;
1015	} VBOXVDMACMD_CHROMIUM_CTL_PRIVATE, *PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE;
1016
1017	# define VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(_p) ((PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE)(((uint8_t*)(_p)) - RT_OFFSETOF(VBOXVDMACMD_CHROMIUM_CTL_PRIVATE, Cmd)))
1018
1019	static PVBOXVDMACMD_CHROMIUM_CTL vboxVDMACrCtlCreate(VBOXVDMACMD_CHROMIUM_CTL_TYPE enmCmd, uint32_t cbCmd)
1020	{
1021	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pHdr = (PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE)RTMemAllocZ(cbCmd + RT_OFFSETOF(VBOXVDMACMD_CHROMIUM_CTL_PRIVATE, Cmd));
1022	Assert(pHdr);
1023	if (pHdr)
1024	{
1025	pHdr->cRefs = 1;
1026	pHdr->rc = VERR_NOT_IMPLEMENTED;
1027	pHdr->Cmd.enmType = enmCmd;
1028	pHdr->Cmd.cbCmd = cbCmd;
1029	return &pHdr->Cmd;
1030	}
1031
1032	return NULL;
1033	}
1034
1035	DECLINLINE(void) vboxVDMACrCtlRelease (PVBOXVDMACMD_CHROMIUM_CTL pCmd)
1036	{
1037	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pHdr = VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(pCmd);
1038	uint32_t cRefs = ASMAtomicDecU32(&pHdr->cRefs);
1039	if (!cRefs)
1040	RTMemFree(pHdr);
1041	}
1042
1043	#if 0 /* unused */
1044	DECLINLINE(void) vboxVDMACrCtlRetain(PVBOXVDMACMD_CHROMIUM_CTL pCmd)
1045	{
1046	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pHdr = VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(pCmd);
1047	ASMAtomicIncU32(&pHdr->cRefs);
1048	}
1049	#endif /* unused */
1050
1051	DECLINLINE(int) vboxVDMACrCtlGetRc (PVBOXVDMACMD_CHROMIUM_CTL pCmd)
1052	{
1053	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pHdr = VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(pCmd);
1054	return pHdr->rc;
1055	}
1056
1057	static DECLCALLBACK(void) vboxVDMACrCtlCbSetEvent(PVGASTATE pVGAState, PVBOXVDMACMD_CHROMIUM_CTL pCmd, void* pvContext)
1058	{
1059	RT_NOREF(pVGAState, pCmd);
1060	RTSemEventSignal((RTSEMEVENT)pvContext);
1061	}
1062
1063	# if 0 /** @todo vboxVDMACrCtlCbReleaseCmd is unused */
1064	static DECLCALLBACK(void) vboxVDMACrCtlCbReleaseCmd(PVGASTATE pVGAState, PVBOXVDMACMD_CHROMIUM_CTL pCmd, void* pvContext)
1065	{
1066	RT_NOREF(pVGAState, pvContext);
1067	vboxVDMACrCtlRelease(pCmd);
1068	}
1069	# endif
1070
1071	static int vboxVDMACrCtlPostAsync (PVGASTATE pVGAState, PVBOXVDMACMD_CHROMIUM_CTL pCmd, uint32_t cbCmd, PFNVBOXVDMACRCTL_CALLBACK pfnCompletion, void *pvCompletion)
1072	{
1073	if ( pVGAState->pDrv
1074	&& pVGAState->pDrv->pfnCrHgsmiControlProcess)
1075	{
1076	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pHdr = VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(pCmd);
1077	pHdr->pfnCompletion = pfnCompletion;
1078	pHdr->pvCompletion = pvCompletion;
1079	pVGAState->pDrv->pfnCrHgsmiControlProcess(pVGAState->pDrv, pCmd, cbCmd);
1080	return VINF_SUCCESS;
1081	}
1082	# ifdef DEBUG_misha
1083	Assert(0);
1084	# endif
1085	return VERR_NOT_SUPPORTED;
1086	}
1087
1088	static int vboxVDMACrCtlPost(PVGASTATE pVGAState, PVBOXVDMACMD_CHROMIUM_CTL pCmd, uint32_t cbCmd)
1089	{
1090	RTSEMEVENT hComplEvent;
1091	int rc = RTSemEventCreate(&hComplEvent);
1092	AssertRC(rc);
1093	if (RT_SUCCESS(rc))
1094	{
1095	rc = vboxVDMACrCtlPostAsync(pVGAState, pCmd, cbCmd, vboxVDMACrCtlCbSetEvent, (void*)hComplEvent);
1096	# ifdef DEBUG_misha
1097	AssertRC(rc);
1098	# endif
1099	if (RT_SUCCESS(rc))
1100	{
1101	rc = RTSemEventWaitNoResume(hComplEvent, RT_INDEFINITE_WAIT);
1102	AssertRC(rc);
1103	if (RT_SUCCESS(rc))
1104	{
1105	RTSemEventDestroy(hComplEvent);
1106	}
1107	}
1108	else
1109	{
1110	/* the command is completed */
1111	RTSemEventDestroy(hComplEvent);
1112	}
1113	}
1114	return rc;
1115	}
1116
1117	typedef struct VDMA_VBVA_CTL_CYNC_COMPLETION
1118	{
1119	int rc;
1120	RTSEMEVENT hEvent;
1121	} VDMA_VBVA_CTL_CYNC_COMPLETION;
1122
1123	static DECLCALLBACK(void) vboxVDMACrHgcmSubmitSyncCompletion(struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd, int rc, void *pvCompletion)
1124	{
1125	RT_NOREF(pCmd, cbCmd);
1126	VDMA_VBVA_CTL_CYNC_COMPLETION pData = (VDMA_VBVA_CTL_CYNC_COMPLETION)pvCompletion;
1127	pData->rc = rc;
1128	rc = RTSemEventSignal(pData->hEvent);
1129	if (!RT_SUCCESS(rc))
1130	WARN(("RTSemEventSignal failed %d\n", rc));
1131	}
1132
1133	static int vboxVDMACrHgcmSubmitSync(struct VBOXVDMAHOST pVdma, VBOXCRCMDCTL pCtl, uint32_t cbCtl)
1134	{
1135	VDMA_VBVA_CTL_CYNC_COMPLETION Data;
1136	Data.rc = VERR_NOT_IMPLEMENTED;
1137	int rc = RTSemEventCreate(&Data.hEvent);
1138	if (!RT_SUCCESS(rc))
1139	{
1140	WARN(("RTSemEventCreate failed %d\n", rc));
1141	return rc;
1142	}
1143
1144	pCtl->CalloutList.List.pNext = NULL;
1145
1146	PVGASTATE pVGAState = pVdma->pVGAState;
1147	rc = pVGAState->pDrv->pfnCrHgcmCtlSubmit(pVGAState->pDrv, pCtl, cbCtl, vboxVDMACrHgcmSubmitSyncCompletion, &Data);
1148	if (RT_SUCCESS(rc))
1149	{
1150	rc = RTSemEventWait(Data.hEvent, RT_INDEFINITE_WAIT);
1151	if (RT_SUCCESS(rc))
1152	{
1153	rc = Data.rc;
1154	if (!RT_SUCCESS(rc))
1155	{
1156	WARN(("pfnCrHgcmCtlSubmit command failed %d\n", rc));
1157	}
1158
1159	}
1160	else
1161	WARN(("RTSemEventWait failed %d\n", rc));
1162	}
1163	else
1164	WARN(("pfnCrHgcmCtlSubmit failed %d\n", rc));
1165
1166
1167	RTSemEventDestroy(Data.hEvent);
1168
1169	return rc;
1170	}
1171
1172	static int vdmaVBVACtlDisableSync(PVBOXVDMAHOST pVdma)
1173	{
1174	VBVAEXHOSTCTL HCtl;
1175	HCtl.enmType = VBVAEXHOSTCTL_TYPE_GHH_DISABLE;
1176	int rc = vdmaVBVACtlSubmitSync(pVdma, &HCtl, VBVAEXHOSTCTL_SOURCE_HOST);
1177	if (RT_FAILURE(rc))
1178	{
1179	Log(("vdmaVBVACtlSubmitSync failed %d\n", rc));
1180	return rc;
1181	}
1182
1183	vgaUpdateDisplayAll(pVdma->pVGAState, /* fFailOnResize = */ false);
1184
1185	return VINF_SUCCESS;
1186	}
1187
1188	static DECLCALLBACK(uint8_t) vboxVDMACrHgcmHandleEnableRemainingHostCommand(HVBOXCRCMDCTL_REMAINING_HOST_COMMAND hClient, uint32_t pcbCtl, int prevCmdRc)
1189	{
1190	struct VBOXVDMAHOST *pVdma = hClient;
1191	if (!pVdma->pCurRemainingHostCtl)
1192	{
1193	/* disable VBVA, all subsequent host commands will go HGCM way */
1194	VBoxVBVAExHSDisable(&pVdma->CmdVbva);
1195	}
1196	else
1197	{
1198	VBoxVBVAExHPDataCompleteCtl(&pVdma->CmdVbva, pVdma->pCurRemainingHostCtl, prevCmdRc);
1199	}
1200
1201	pVdma->pCurRemainingHostCtl = VBoxVBVAExHPCheckHostCtlOnDisable(&pVdma->CmdVbva);
1202	if (pVdma->pCurRemainingHostCtl)
1203	{
1204	*pcbCtl = pVdma->pCurRemainingHostCtl->u.cmd.cbCmd;
1205	return pVdma->pCurRemainingHostCtl->u.cmd.pu8Cmd;
1206	}
1207
1208	*pcbCtl = 0;
1209	return NULL;
1210	}
1211
1212	static DECLCALLBACK(void) vboxVDMACrHgcmNotifyTerminatingDoneCb(HVBOXCRCMDCTL_NOTIFY_TERMINATING hClient)
1213	{
1214	# ifdef VBOX_STRICT
1215	struct VBOXVDMAHOST *pVdma = hClient;
1216	Assert(pVdma->CmdVbva.i32State == VBVAEXHOSTCONTEXT_STATE_PROCESSING);
1217	Assert(pVdma->Thread.u32State == VBOXVDMATHREAD_STATE_TERMINATING);
1218	# else
1219	RT_NOREF(hClient);
1220	# endif
1221	}
1222
1223	static DECLCALLBACK(int) vboxVDMACrHgcmNotifyTerminatingCb(HVBOXCRCMDCTL_NOTIFY_TERMINATING hClient, VBOXCRCMDCTL_HGCMENABLE_DATA *pHgcmEnableData)
1224	{
1225	struct VBOXVDMAHOST *pVdma = hClient;
1226	VBVAEXHOSTCTL HCtl;
1227	HCtl.enmType = VBVAEXHOSTCTL_TYPE_HH_ON_HGCM_UNLOAD;
1228	int rc = vdmaVBVACtlSubmitSync(pVdma, &HCtl, VBVAEXHOSTCTL_SOURCE_HOST);
1229
1230	pHgcmEnableData->hRHCmd = pVdma;
1231	pHgcmEnableData->pfnRHCmd = vboxVDMACrHgcmHandleEnableRemainingHostCommand;
1232
1233	if (RT_FAILURE(rc))
1234	{
1235	if (rc == VERR_INVALID_STATE)
1236	rc = VINF_SUCCESS;
1237	else
1238	WARN(("vdmaVBVACtlSubmitSync failed %d\n", rc));
1239	}
1240
1241	return rc;
1242	}
1243
1244	static int vboxVDMACrHgcmHandleEnable(struct VBOXVDMAHOST *pVdma)
1245	{
1246	VBOXCRCMDCTL_ENABLE Enable;
1247	Enable.Hdr.enmType = VBOXCRCMDCTL_TYPE_ENABLE;
1248	Enable.Data.hRHCmd = pVdma;
1249	Enable.Data.pfnRHCmd = vboxVDMACrHgcmHandleEnableRemainingHostCommand;
1250
1251	int rc = vboxVDMACrHgcmSubmitSync(pVdma, &Enable.Hdr, sizeof (Enable));
1252	Assert(!pVdma->pCurRemainingHostCtl);
1253	if (RT_SUCCESS(rc))
1254	{
1255	Assert(!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva));
1256	return VINF_SUCCESS;
1257	}
1258
1259	Assert(VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva));
1260	WARN(("vboxVDMACrHgcmSubmitSync failed %d\n", rc));
1261
1262	return rc;
1263	}
1264
1265	static int vdmaVBVAEnableProcess(struct VBOXVDMAHOST *pVdma, uint32_t u32Offset)
1266	{
1267	if (VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
1268	{
1269	WARN(("vdma VBVA is already enabled\n"));
1270	return VERR_INVALID_STATE;
1271	}
1272
1273	VBVABUFFER pVBVA = (VBVABUFFER )HGSMIOffsetToPointerHost(pVdma->pHgsmi, u32Offset);
1274	if (!pVBVA)
1275	{
1276	WARN(("invalid offset %d\n", u32Offset));
1277	return VERR_INVALID_PARAMETER;
1278	}
1279
1280	if (!pVdma->CrSrvInfo.pfnEnable)
1281	{
1282	# ifdef DEBUG_misha
1283	WARN(("pfnEnable is NULL\n"));
1284	return VERR_NOT_SUPPORTED;
1285	# endif
1286	}
1287
1288	int rc = VBoxVBVAExHSEnable(&pVdma->CmdVbva, pVBVA);
1289	if (RT_SUCCESS(rc))
1290	{
1291	VBOXCRCMDCTL_DISABLE Disable;
1292	Disable.Hdr.enmType = VBOXCRCMDCTL_TYPE_DISABLE;
1293	Disable.Data.hNotifyTerm = pVdma;
1294	Disable.Data.pfnNotifyTerm = vboxVDMACrHgcmNotifyTerminatingCb;
1295	Disable.Data.pfnNotifyTermDone = vboxVDMACrHgcmNotifyTerminatingDoneCb;
1296	rc = vboxVDMACrHgcmSubmitSync(pVdma, &Disable.Hdr, sizeof (Disable));
1297	if (RT_SUCCESS(rc))
1298	{
1299	PVGASTATE pVGAState = pVdma->pVGAState;
1300	VBOXCRCMD_SVRENABLE_INFO Info;
1301	Info.hCltScr = pVGAState->pDrv;
1302	Info.pfnCltScrUpdateBegin = pVGAState->pDrv->pfnVBVAUpdateBegin;
1303	Info.pfnCltScrUpdateProcess = pVGAState->pDrv->pfnVBVAUpdateProcess;
1304	Info.pfnCltScrUpdateEnd = pVGAState->pDrv->pfnVBVAUpdateEnd;
1305	rc = pVdma->CrSrvInfo.pfnEnable(pVdma->CrSrvInfo.hSvr, &Info);
1306	if (RT_SUCCESS(rc))
1307	return VINF_SUCCESS;
1308	else
1309	WARN(("pfnEnable failed %d\n", rc));
1310
1311	vboxVDMACrHgcmHandleEnable(pVdma);
1312	}
1313	else
1314	WARN(("vboxVDMACrHgcmSubmitSync failed %d\n", rc));
1315
1316	VBoxVBVAExHSDisable(&pVdma->CmdVbva);
1317	}
1318	else
1319	WARN(("VBoxVBVAExHSEnable failed %d\n", rc));
1320
1321	return rc;
1322	}
1323
1324	static int vdmaVBVADisableProcess(struct VBOXVDMAHOST *pVdma, bool fDoHgcmEnable)
1325	{
1326	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
1327	{
1328	Log(("vdma VBVA is already disabled\n"));
1329	return VINF_SUCCESS;
1330	}
1331
1332	int rc = pVdma->CrSrvInfo.pfnDisable(pVdma->CrSrvInfo.hSvr);
1333	if (RT_SUCCESS(rc))
1334	{
1335	if (fDoHgcmEnable)
1336	{
1337	PVGASTATE pVGAState = pVdma->pVGAState;
1338
1339	/* disable is a bit tricky
1340	* we need to ensure the host ctl commands do not come out of order
1341	* and do not come over HGCM channel until after it is enabled */
1342	rc = vboxVDMACrHgcmHandleEnable(pVdma);
1343	if (RT_SUCCESS(rc))
1344	{
1345	vdmaVBVANotifyDisable(pVGAState);
1346	return VINF_SUCCESS;
1347	}
1348
1349	VBOXCRCMD_SVRENABLE_INFO Info;
1350	Info.hCltScr = pVGAState->pDrv;
1351	Info.pfnCltScrUpdateBegin = pVGAState->pDrv->pfnVBVAUpdateBegin;
1352	Info.pfnCltScrUpdateProcess = pVGAState->pDrv->pfnVBVAUpdateProcess;
1353	Info.pfnCltScrUpdateEnd = pVGAState->pDrv->pfnVBVAUpdateEnd;
1354	pVdma->CrSrvInfo.pfnEnable(pVdma->CrSrvInfo.hSvr, &Info);
1355	}
1356	}
1357	else
1358	WARN(("pfnDisable failed %d\n", rc));
1359
1360	return rc;
1361	}
1362
1363	static int vboxVDMACrHostCtlProcess(struct VBOXVDMAHOST pVdma, VBVAEXHOSTCTL pCmd, bool *pfContinue)
1364	{
1365	*pfContinue = true;
1366
1367	switch (pCmd->enmType)
1368	{
1369	case VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE:
1370	{
1371	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
1372	{
1373	WARN(("VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE for disabled vdma VBVA\n"));
1374	return VERR_INVALID_STATE;
1375	}
1376	return pVdma->CrSrvInfo.pfnHostCtl(pVdma->CrSrvInfo.hSvr, pCmd->u.cmd.pu8Cmd, pCmd->u.cmd.cbCmd);
1377	}
1378	case VBVAEXHOSTCTL_TYPE_GHH_DISABLE:
1379	{
1380	int rc = vdmaVBVADisableProcess(pVdma, true);
1381	if (RT_FAILURE(rc))
1382	{
1383	WARN(("vdmaVBVADisableProcess failed %d\n", rc));
1384	return rc;
1385	}
1386
1387	return VBoxVDMAThreadTerm(&pVdma->Thread, NULL, NULL, false);
1388	}
1389	case VBVAEXHOSTCTL_TYPE_HH_ON_HGCM_UNLOAD:
1390	{
1391	int rc = vdmaVBVADisableProcess(pVdma, false);
1392	if (RT_FAILURE(rc))
1393	{
1394	WARN(("vdmaVBVADisableProcess failed %d\n", rc));
1395	return rc;
1396	}
1397
1398	rc = VBoxVDMAThreadTerm(&pVdma->Thread, NULL, NULL, true);
1399	if (RT_FAILURE(rc))
1400	{
1401	WARN(("VBoxVDMAThreadTerm failed %d\n", rc));
1402	return rc;
1403	}
1404
1405	*pfContinue = false;
1406	return VINF_SUCCESS;
1407	}
1408	case VBVAEXHOSTCTL_TYPE_HH_SAVESTATE:
1409	{
1410	PVGASTATE pVGAState = pVdma->pVGAState;
1411	uint8_t * pu8VramBase = pVGAState->vram_ptrR3;
1412	int rc = VBoxVBVAExHSSaveState(&pVdma->CmdVbva, pu8VramBase, pCmd->u.state.pSSM);
1413	if (RT_FAILURE(rc))
1414	{
1415	WARN(("VBoxVBVAExHSSaveState failed %d\n", rc));
1416	return rc;
1417	}
1418	VGA_SAVED_STATE_PUT_MARKER(pCmd->u.state.pSSM, 4);
1419
1420	return pVdma->CrSrvInfo.pfnSaveState(pVdma->CrSrvInfo.hSvr, pCmd->u.state.pSSM);
1421	}
1422	case VBVAEXHOSTCTL_TYPE_HH_LOADSTATE:
1423	{
1424	PVGASTATE pVGAState = pVdma->pVGAState;
1425	uint8_t * pu8VramBase = pVGAState->vram_ptrR3;
1426
1427	int rc = VBoxVBVAExHSLoadState(&pVdma->CmdVbva, pu8VramBase, pCmd->u.state.pSSM, pCmd->u.state.u32Version);
1428	if (RT_FAILURE(rc))
1429	{
1430	WARN(("VBoxVBVAExHSSaveState failed %d\n", rc));
1431	return rc;
1432	}
1433
1434	VGA_SAVED_STATE_GET_MARKER_RETURN_ON_MISMATCH(pCmd->u.state.pSSM, pCmd->u.state.u32Version, 4);
1435	rc = pVdma->CrSrvInfo.pfnLoadState(pVdma->CrSrvInfo.hSvr, pCmd->u.state.pSSM, pCmd->u.state.u32Version);
1436	if (RT_FAILURE(rc))
1437	{
1438	WARN(("pfnLoadState failed %d\n", rc));
1439	return rc;
1440	}
1441
1442	return VINF_SUCCESS;
1443	}
1444	case VBVAEXHOSTCTL_TYPE_HH_LOADSTATE_DONE:
1445	{
1446	PVGASTATE pVGAState = pVdma->pVGAState;
1447
1448	for (uint32_t i = 0; i < pVGAState->cMonitors; ++i)
1449	{
1450	VBVAINFOSCREEN CurScreen;
1451	VBVAINFOVIEW CurView;
1452
1453	int rc = VBVAGetInfoViewAndScreen(pVGAState, i, &CurView, &CurScreen);
1454	if (RT_FAILURE(rc))
1455	{
1456	WARN(("VBVAGetInfoViewAndScreen failed %d\n", rc));
1457	return rc;
1458	}
1459
1460	rc = VBVAInfoScreen(pVGAState, &CurScreen);
1461	if (RT_FAILURE(rc))
1462	{
1463	WARN(("VBVAInfoScreen failed %d\n", rc));
1464	return rc;
1465	}
1466	}
1467
1468	return VINF_SUCCESS;
1469	}
1470	default:
1471	WARN(("unexpected host ctl type %d\n", pCmd->enmType));
1472	return VERR_INVALID_PARAMETER;
1473	}
1474	}
1475
1476	static int vboxVDMASetupScreenInfo(PVGASTATE pVGAState, VBVAINFOSCREEN *pScreen)
1477	{
1478	const uint32_t u32ViewIndex = pScreen->u32ViewIndex;
1479	const uint16_t u16Flags = pScreen->u16Flags;
1480
1481	if (u16Flags & VBVA_SCREEN_F_DISABLED)
1482	{
1483	if ( u32ViewIndex < pVGAState->cMonitors
1484	\|\| u32ViewIndex == UINT32_C(0xFFFFFFFF))
1485	{
1486	RT_ZERO(*pScreen);
1487	pScreen->u32ViewIndex = u32ViewIndex;
1488	pScreen->u16Flags = VBVA_SCREEN_F_ACTIVE \| VBVA_SCREEN_F_DISABLED;
1489	return VINF_SUCCESS;
1490	}
1491	}
1492	else
1493	{
1494	if (u16Flags & VBVA_SCREEN_F_BLANK2)
1495	{
1496	if ( u32ViewIndex >= pVGAState->cMonitors
1497	&& u32ViewIndex != UINT32_C(0xFFFFFFFF))
1498	{
1499	return VERR_INVALID_PARAMETER;
1500	}
1501
1502	/* Special case for blanking using current video mode.
1503	* Only 'u16Flags' and 'u32ViewIndex' field are relevant.
1504	*/
1505	RT_ZERO(*pScreen);
1506	pScreen->u32ViewIndex = u32ViewIndex;
1507	pScreen->u16Flags = u16Flags;
1508	return VINF_SUCCESS;
1509	}
1510
1511	if ( u32ViewIndex < pVGAState->cMonitors
1512	&& pScreen->u16BitsPerPixel <= 32
1513	&& pScreen->u32Width <= UINT16_MAX
1514	&& pScreen->u32Height <= UINT16_MAX
1515	&& pScreen->u32LineSize <= UINT16_MAX * 4)
1516	{
1517	const uint32_t u32BytesPerPixel = (pScreen->u16BitsPerPixel + 7) / 8;
1518	if (pScreen->u32Width <= pScreen->u32LineSize / (u32BytesPerPixel? u32BytesPerPixel: 1))
1519	{
1520	const uint64_t u64ScreenSize = (uint64_t)pScreen->u32LineSize * pScreen->u32Height;
1521	if ( pScreen->u32StartOffset <= pVGAState->vram_size
1522	&& u64ScreenSize <= pVGAState->vram_size
1523	&& pScreen->u32StartOffset <= pVGAState->vram_size - (uint32_t)u64ScreenSize)
1524	{
1525	return VINF_SUCCESS;
1526	}
1527	}
1528	}
1529	}
1530
1531	return VERR_INVALID_PARAMETER;
1532	}
1533
1534	static int vboxVDMACrGuestCtlResizeEntryProcess(struct VBOXVDMAHOST pVdma, VBOXCMDVBVA_RESIZE_ENTRY pEntry)
1535	{
1536	PVGASTATE pVGAState = pVdma->pVGAState;
1537	VBVAINFOSCREEN Screen = pEntry->Screen;
1538
1539	/* Verify and cleanup local copy of the input data. */
1540	int rc = vboxVDMASetupScreenInfo(pVGAState, &Screen);
1541	if (RT_FAILURE(rc))
1542	{
1543	WARN(("invalid screen data\n"));
1544	return rc;
1545	}
1546
1547	VBOXCMDVBVA_SCREENMAP_DECL(uint32_t, aTargetMap);
1548	memcpy(aTargetMap, pEntry->aTargetMap, sizeof(aTargetMap));
1549	ASMBitClearRange(aTargetMap, pVGAState->cMonitors, VBOX_VIDEO_MAX_SCREENS);
1550
1551	rc = pVdma->CrSrvInfo.pfnResize(pVdma->CrSrvInfo.hSvr, &Screen, aTargetMap);
1552	if (RT_FAILURE(rc))
1553	{
1554	WARN(("pfnResize failed %d\n", rc));
1555	return rc;
1556	}
1557
1558	/* A fake view which contains the current screen for the 2D VBVAInfoView. */
1559	VBVAINFOVIEW View;
1560	View.u32ViewOffset = 0;
1561	View.u32ViewSize = Screen.u32LineSize * Screen.u32Height + Screen.u32StartOffset;
1562	View.u32MaxScreenSize = Screen.u32LineSize * Screen.u32Height;
1563
1564	const bool fDisable = RT_BOOL(Screen.u16Flags & VBVA_SCREEN_F_DISABLED);
1565
1566	for (int i = ASMBitFirstSet(aTargetMap, pVGAState->cMonitors);
1567	i >= 0;
1568	i = ASMBitNextSet(aTargetMap, pVGAState->cMonitors, i))
1569	{
1570	Screen.u32ViewIndex = i;
1571
1572	VBVAINFOSCREEN CurScreen;
1573	VBVAINFOVIEW CurView;
1574
1575	rc = VBVAGetInfoViewAndScreen(pVGAState, i, &CurView, &CurScreen);
1576	AssertRC(rc);
1577
1578	if (!memcmp(&Screen, &CurScreen, sizeof (CurScreen)))
1579	continue;
1580
1581	/* The view does not change if _BLANK2 is set. */
1582	if ( (!fDisable \|\| !CurView.u32ViewSize)
1583	&& !RT_BOOL(Screen.u16Flags & VBVA_SCREEN_F_BLANK2))
1584	{
1585	View.u32ViewIndex = Screen.u32ViewIndex;
1586
1587	rc = VBVAInfoView(pVGAState, &View);
1588	if (RT_FAILURE(rc))
1589	{
1590	WARN(("VBVAInfoView failed %d\n", rc));
1591	break;
1592	}
1593	}
1594
1595	rc = VBVAInfoScreen(pVGAState, &Screen);
1596	if (RT_FAILURE(rc))
1597	{
1598	WARN(("VBVAInfoScreen failed %d\n", rc));
1599	break;
1600	}
1601	}
1602
1603	return rc;
1604	}
1605
1606	static int vboxVDMACrGuestCtlProcess(struct VBOXVDMAHOST pVdma, VBVAEXHOSTCTL pCmd)
1607	{
1608	VBVAEXHOSTCTL_TYPE enmType = pCmd->enmType;
1609	switch (enmType)
1610	{
1611	case VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE:
1612	{
1613	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
1614	{
1615	WARN(("VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE for disabled vdma VBVA\n"));
1616	return VERR_INVALID_STATE;
1617	}
1618	return pVdma->CrSrvInfo.pfnGuestCtl(pVdma->CrSrvInfo.hSvr, pCmd->u.cmd.pu8Cmd, pCmd->u.cmd.cbCmd);
1619	}
1620	case VBVAEXHOSTCTL_TYPE_GHH_RESIZE:
1621	{
1622	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
1623	{
1624	WARN(("VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE for disabled vdma VBVA\n"));
1625	return VERR_INVALID_STATE;
1626	}
1627
1628	uint32_t cbCmd = pCmd->u.cmd.cbCmd;
1629
1630	if (cbCmd % sizeof (VBOXCMDVBVA_RESIZE_ENTRY))
1631	{
1632	WARN(("invalid buffer size\n"));
1633	return VERR_INVALID_PARAMETER;
1634	}
1635
1636	uint32_t cElements = cbCmd / sizeof (VBOXCMDVBVA_RESIZE_ENTRY);
1637	if (!cElements)
1638	{
1639	WARN(("invalid buffer size\n"));
1640	return VERR_INVALID_PARAMETER;
1641	}
1642
1643	VBOXCMDVBVA_RESIZE pResize = (VBOXCMDVBVA_RESIZE)pCmd->u.cmd.pu8Cmd;
1644
1645	int rc = VINF_SUCCESS;
1646
1647	for (uint32_t i = 0; i < cElements; ++i)
1648	{
1649	VBOXCMDVBVA_RESIZE_ENTRY *pEntry = &pResize->aEntries[i];
1650	rc = vboxVDMACrGuestCtlResizeEntryProcess(pVdma, pEntry);
1651	if (RT_FAILURE(rc))
1652	{
1653	WARN(("vboxVDMACrGuestCtlResizeEntryProcess failed %d\n", rc));
1654	break;
1655	}
1656	}
1657	return rc;
1658	}
1659	case VBVAEXHOSTCTL_TYPE_GHH_ENABLE:
1660	case VBVAEXHOSTCTL_TYPE_GHH_ENABLE_PAUSED:
1661	{
1662	VBVAENABLE pEnable = (VBVAENABLE )pCmd->u.cmd.pu8Cmd;
1663	Assert(pCmd->u.cmd.cbCmd == sizeof (VBVAENABLE));
1664	uint32_t u32Offset = pEnable->u32Offset;
1665	int rc = vdmaVBVAEnableProcess(pVdma, u32Offset);
1666	if (!RT_SUCCESS(rc))
1667	{
1668	WARN(("vdmaVBVAEnableProcess failed %d\n", rc));
1669	return rc;
1670	}
1671
1672	if (enmType == VBVAEXHOSTCTL_TYPE_GHH_ENABLE_PAUSED)
1673	{
1674	rc = VBoxVBVAExHPPause(&pVdma->CmdVbva);
1675	if (!RT_SUCCESS(rc))
1676	{
1677	WARN(("VBoxVBVAExHPPause failed %d\n", rc));
1678	return rc;
1679	}
1680	}
1681
1682	return VINF_SUCCESS;
1683	}
1684	case VBVAEXHOSTCTL_TYPE_GHH_DISABLE:
1685	{
1686	int rc = vdmaVBVADisableProcess(pVdma, true);
1687	if (RT_FAILURE(rc))
1688	{
1689	WARN(("vdmaVBVADisableProcess failed %d\n", rc));
1690	return rc;
1691	}
1692
1693	/* do vgaUpdateDisplayAll right away */
1694	VMR3ReqCallNoWait(PDMDevHlpGetVM(pVdma->pVGAState->pDevInsR3), VMCPUID_ANY,
1695	(PFNRT)vgaUpdateDisplayAll, 2, pVdma->pVGAState, /* fFailOnResize = */ false);
1696
1697	return VBoxVDMAThreadTerm(&pVdma->Thread, NULL, NULL, false);
1698	}
1699	default:
1700	WARN(("unexpected ctl type %d\n", pCmd->enmType));
1701	return VERR_INVALID_PARAMETER;
1702	}
1703	}
1704
1705	/**
1706	* @param fIn - whether this is a page in or out op.
1707	* the direction is VRA#M - related, so fIn == true - transfer to VRAM); false - transfer from VRAM
1708	*/
1709	static int vboxVDMACrCmdVbvaProcessPagingEl(PPDMDEVINS pDevIns, VBOXCMDVBVAPAGEIDX iPage, uint8_t *pu8Vram, bool fIn)
1710	{
1711	RTGCPHYS phPage = (RTGCPHYS)iPage << PAGE_SHIFT;
1712	PGMPAGEMAPLOCK Lock;
1713	int rc;
1714
1715	if (fIn)
1716	{
1717	const void * pvPage;
1718	rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phPage, 0, &pvPage, &Lock);
1719	if (!RT_SUCCESS(rc))
1720	{
1721	WARN(("PDMDevHlpPhysGCPhys2CCPtrReadOnly failed %d", rc));
1722	return rc;
1723	}
1724
1725	memcpy(pu8Vram, pvPage, PAGE_SIZE);
1726
1727	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
1728	}
1729	else
1730	{
1731	void * pvPage;
1732	rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, phPage, 0, &pvPage, &Lock);
1733	if (!RT_SUCCESS(rc))
1734	{
1735	WARN(("PDMDevHlpPhysGCPhys2CCPtr failed %d", rc));
1736	return rc;
1737	}
1738
1739	memcpy(pvPage, pu8Vram, PAGE_SIZE);
1740
1741	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
1742	}
1743
1744	return VINF_SUCCESS;
1745	}
1746
1747	static int vboxVDMACrCmdVbvaProcessPagingEls(PPDMDEVINS pDevIns, const VBOXCMDVBVAPAGEIDX piPages, uint32_t cPages, uint8_t pu8Vram, bool fIn)
1748	{
1749	for (uint32_t i = 0; i < cPages; ++i, pu8Vram += PAGE_SIZE)
1750	{
1751	int rc = vboxVDMACrCmdVbvaProcessPagingEl(pDevIns, piPages[i], pu8Vram, fIn);
1752	if (!RT_SUCCESS(rc))
1753	{
1754	WARN(("vboxVDMACrCmdVbvaProcessPagingEl failed %d", rc));
1755	return rc;
1756	}
1757	}
1758
1759	return VINF_SUCCESS;
1760	}
1761
1762	static int8_t vboxVDMACrCmdVbvaPagingDataInit(PVGASTATE pVGAState, const VBOXCMDVBVA_HDR pHdr, const VBOXCMDVBVA_PAGING_TRANSFER_DATA pData, uint32_t cbCmd,
1763	const VBOXCMDVBVAPAGEIDX *ppPages, VBOXCMDVBVAPAGEIDX pcPages,
1764	uint8_t *ppu8Vram, bool pfIn)
1765	{
1766	if (cbCmd < sizeof (VBOXCMDVBVA_PAGING_TRANSFER))
1767	{
1768	WARN(("cmd too small"));
1769	return -1;
1770	}
1771
1772	VBOXCMDVBVAPAGEIDX cPages = cbCmd - RT_OFFSETOF(VBOXCMDVBVA_PAGING_TRANSFER, Data.aPageNumbers);
1773	if (cPages % sizeof (VBOXCMDVBVAPAGEIDX))
1774	{
1775	WARN(("invalid cmd size"));
1776	return -1;
1777	}
1778	cPages /= sizeof (VBOXCMDVBVAPAGEIDX);
1779
1780	VBOXCMDVBVAOFFSET offVRAM = pData->Alloc.u.offVRAM;
1781	if (offVRAM & PAGE_OFFSET_MASK)
1782	{
1783	WARN(("offVRAM address is not on page boundary\n"));
1784	return -1;
1785	}
1786	const VBOXCMDVBVAPAGEIDX *pPages = pData->aPageNumbers;
1787
1788	uint8_t * pu8VramBase = pVGAState->vram_ptrR3;
1789	if (offVRAM >= pVGAState->vram_size)
1790	{
1791	WARN(("invalid vram offset"));
1792	return -1;
1793	}
1794
1795	if (~(~(VBOXCMDVBVAPAGEIDX)0 >> PAGE_SHIFT) & cPages)
1796	{
1797	WARN(("invalid cPages %d", cPages));
1798	return -1;
1799	}
1800
1801	if (offVRAM + ((VBOXCMDVBVAOFFSET)cPages << PAGE_SHIFT) >= pVGAState->vram_size)
1802	{
1803	WARN(("invalid cPages %d, exceeding vram size", cPages));
1804	return -1;
1805	}
1806
1807	uint8_t *pu8Vram = pu8VramBase + offVRAM;
1808	bool fIn = !!(pHdr->u8Flags & VBOXCMDVBVA_OPF_PAGING_TRANSFER_IN);
1809
1810	*ppPages = pPages;
1811	*pcPages = cPages;
1812	*ppu8Vram = pu8Vram;
1813	*pfIn = fIn;
1814	return 0;
1815	}
1816
1817	static int8_t vboxVDMACrCmdVbvaPagingFill(PVGASTATE pVGAState, VBOXCMDVBVA_PAGING_FILL *pFill)
1818	{
1819	VBOXCMDVBVAOFFSET offVRAM = pFill->offVRAM;
1820	if (offVRAM & PAGE_OFFSET_MASK)
1821	{
1822	WARN(("offVRAM address is not on page boundary\n"));
1823	return -1;
1824	}
1825
1826	uint8_t * pu8VramBase = pVGAState->vram_ptrR3;
1827	if (offVRAM >= pVGAState->vram_size)
1828	{
1829	WARN(("invalid vram offset"));
1830	return -1;
1831	}
1832
1833	uint32_t cbFill = pFill->u32CbFill;
1834
1835	if (offVRAM + cbFill >= pVGAState->vram_size)
1836	{
1837	WARN(("invalid cPages"));
1838	return -1;
1839	}
1840
1841	uint32_t pu32Vram = (uint32_t)(pu8VramBase + offVRAM);
1842	uint32_t u32Color = pFill->u32Pattern;
1843
1844	Assert(!(cbFill % 4));
1845	for (uint32_t i = 0; i < cbFill / 4; ++i)
1846	{
1847	pu32Vram[i] = u32Color;
1848	}
1849
1850	return 0;
1851	}
1852
1853	static int8_t vboxVDMACrCmdVbvaProcessCmdData(struct VBOXVDMAHOST pVdma, const VBOXCMDVBVA_HDR pCmd, uint32_t cbCmd)
1854	{
1855	switch (pCmd->u8OpCode)
1856	{
1857	case VBOXCMDVBVA_OPTYPE_NOPCMD:
1858	return 0;
1859	case VBOXCMDVBVA_OPTYPE_PAGING_TRANSFER:
1860	{
1861	PVGASTATE pVGAState = pVdma->pVGAState;
1862	const VBOXCMDVBVAPAGEIDX *pPages;
1863	uint32_t cPages;
1864	uint8_t *pu8Vram;
1865	bool fIn;
1866	int8_t i8Result = vboxVDMACrCmdVbvaPagingDataInit(pVGAState, pCmd, &((VBOXCMDVBVA_PAGING_TRANSFER*)pCmd)->Data, cbCmd,
1867	&pPages, &cPages,
1868	&pu8Vram, &fIn);
1869	if (i8Result < 0)
1870	{
1871	WARN(("vboxVDMACrCmdVbvaPagingDataInit failed %d", i8Result));
1872	return i8Result;
1873	}
1874
1875	PPDMDEVINS pDevIns = pVGAState->pDevInsR3;
1876	int rc = vboxVDMACrCmdVbvaProcessPagingEls(pDevIns, pPages, cPages, pu8Vram, fIn);
1877	if (!RT_SUCCESS(rc))
1878	{
1879	WARN(("vboxVDMACrCmdVbvaProcessPagingEls failed %d", rc));
1880	return -1;
1881	}
1882
1883	return 0;
1884	}
1885	case VBOXCMDVBVA_OPTYPE_PAGING_FILL:
1886	{
1887	PVGASTATE pVGAState = pVdma->pVGAState;
1888	if (cbCmd != sizeof (VBOXCMDVBVA_PAGING_FILL))
1889	{
1890	WARN(("cmd too small"));
1891	return -1;
1892	}
1893
1894	return vboxVDMACrCmdVbvaPagingFill(pVGAState, (VBOXCMDVBVA_PAGING_FILL*)pCmd);
1895	}
1896	default:
1897	return pVdma->CrSrvInfo.pfnCmd(pVdma->CrSrvInfo.hSvr, pCmd, cbCmd);
1898	}
1899	}
1900
1901	# if 0
1902	typedef struct VBOXCMDVBVA_PAGING_TRANSFER
1903	{
1904	VBOXCMDVBVA_HDR Hdr;
1905	/* for now can only contain offVRAM.
1906	* paging transfer can NOT be initiated for allocations having host 3D object (hostID) associated */
1907	VBOXCMDVBVA_ALLOCINFO Alloc;
1908	uint32_t u32Reserved;
1909	VBOXCMDVBVA_SYSMEMEL aSysMem[1];
1910	} VBOXCMDVBVA_PAGING_TRANSFER;
1911	# endif
1912
1913	AssertCompile(sizeof (VBOXCMDVBVA_HDR) == 8);
1914	AssertCompile(sizeof (VBOXCMDVBVA_ALLOCINFO) == 4);
1915	AssertCompile(sizeof (VBOXCMDVBVAPAGEIDX) == 4);
1916	AssertCompile(!(PAGE_SIZE % sizeof (VBOXCMDVBVAPAGEIDX)));
1917
1918	# define VBOXCMDVBVA_NUM_SYSMEMEL_PER_PAGE (PAGE_SIZE / sizeof (VBOXCMDVBVA_SYSMEMEL))
1919
1920	static int8_t vboxVDMACrCmdVbvaProcess(struct VBOXVDMAHOST pVdma, const VBOXCMDVBVA_HDR pCmd, uint32_t cbCmd)
1921	{
1922	LogRelFlow(("VDMA: vboxVDMACrCmdVbvaProcess: ENTER, opCode(%i)\n", pCmd->u8OpCode));
1923	int8_t i8Result = 0;
1924
1925	switch (pCmd->u8OpCode)
1926	{
1927	case VBOXCMDVBVA_OPTYPE_SYSMEMCMD:
1928	{
1929	if (cbCmd < sizeof (VBOXCMDVBVA_SYSMEMCMD))
1930	{
1931	WARN(("invalid command size"));
1932	return -1;
1933	}
1934	VBOXCMDVBVA_SYSMEMCMD pSysmemCmd = (VBOXCMDVBVA_SYSMEMCMD)pCmd;
1935	const VBOXCMDVBVA_HDR *pRealCmdHdr;
1936	uint32_t cbRealCmd = pCmd->u8Flags;
1937	cbRealCmd \|= (uint32_t)pCmd->u.u8PrimaryID << 8;
1938	if (cbRealCmd < sizeof (VBOXCMDVBVA_HDR))
1939	{
1940	WARN(("invalid sysmem cmd size"));
1941	return -1;
1942	}
1943
1944	RTGCPHYS phCmd = (RTGCPHYS)pSysmemCmd->phCmd;
1945
1946	PGMPAGEMAPLOCK Lock;
1947	PVGASTATE pVGAState = pVdma->pVGAState;
1948	PPDMDEVINS pDevIns = pVGAState->pDevInsR3;
1949	const void * pvCmd;
1950	int rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phCmd, 0, &pvCmd, &Lock);
1951	if (!RT_SUCCESS(rc))
1952	{
1953	WARN(("PDMDevHlpPhysGCPhys2CCPtrReadOnly failed %d\n", rc));
1954	return -1;
1955	}
1956
1957	Assert((phCmd & PAGE_OFFSET_MASK) == (((uintptr_t)pvCmd) & PAGE_OFFSET_MASK));
1958
1959	uint32_t cbCmdPart = PAGE_SIZE - (((uintptr_t)pvCmd) & PAGE_OFFSET_MASK);
1960
1961	if (cbRealCmd <= cbCmdPart)
1962	{
1963	pRealCmdHdr = (const VBOXCMDVBVA_HDR *)pvCmd;
1964	i8Result = vboxVDMACrCmdVbvaProcessCmdData(pVdma, pRealCmdHdr, cbRealCmd);
1965	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
1966	return i8Result;
1967	}
1968
1969	VBOXCMDVBVA_HDR Hdr;
1970	const void *pvCurCmdTail;
1971	uint32_t cbCurCmdTail;
1972	if (cbCmdPart >= sizeof (*pRealCmdHdr))
1973	{
1974	pRealCmdHdr = (const VBOXCMDVBVA_HDR *)pvCmd;
1975	pvCurCmdTail = (const void*)(pRealCmdHdr + 1);
1976	cbCurCmdTail = cbCmdPart - sizeof (*pRealCmdHdr);
1977	}
1978	else
1979	{
1980	memcpy(&Hdr, pvCmd, cbCmdPart);
1981	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
1982	phCmd += cbCmdPart;
1983	Assert(!(phCmd & PAGE_OFFSET_MASK));
1984	rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phCmd, 0, &pvCmd, &Lock);
1985	if (!RT_SUCCESS(rc))
1986	{
1987	WARN(("PDMDevHlpPhysGCPhys2CCPtrReadOnly failed %d\n", rc));
1988	return -1;
1989	}
1990
1991	cbCmdPart = sizeof (*pRealCmdHdr) - cbCmdPart;
1992	memcpy(((uint8_t*)(&Hdr)) + cbCmdPart, pvCmd, cbCmdPart);
1993	pRealCmdHdr = &Hdr;
1994	pvCurCmdTail = (const void)(((uint8_t)pvCmd) + cbCmdPart);
1995	cbCurCmdTail = PAGE_SIZE - cbCmdPart;
1996	}
1997
1998	if (cbCurCmdTail > cbRealCmd - sizeof (*pRealCmdHdr))
1999	cbCurCmdTail = cbRealCmd - sizeof (*pRealCmdHdr);
2000
2001	switch (pRealCmdHdr->u8OpCode)
2002	{
2003	case VBOXCMDVBVA_OPTYPE_PAGING_TRANSFER:
2004	{
2005	const uint32_t *pPages;
2006	uint32_t cPages;
2007	uint8_t *pu8Vram;
2008	bool fIn;
2009	i8Result = vboxVDMACrCmdVbvaPagingDataInit(pVGAState, pRealCmdHdr, (const VBOXCMDVBVA_PAGING_TRANSFER_DATA*)pvCurCmdTail, cbRealCmd,
2010	&pPages, &cPages,
2011	&pu8Vram, &fIn);
2012	if (i8Result < 0)
2013	{
2014	WARN(("vboxVDMACrCmdVbvaPagingDataInit failed %d", i8Result));
2015	/* we need to break, not return, to ensure currently locked page is released */
2016	break;
2017	}
2018
2019	if (cbCurCmdTail & 3)
2020	{
2021	WARN(("command is not alligned properly %d", cbCurCmdTail));
2022	i8Result = -1;
2023	/* we need to break, not return, to ensure currently locked page is released */
2024	break;
2025	}
2026
2027	uint32_t cCurPages = cbCurCmdTail / sizeof (VBOXCMDVBVAPAGEIDX);
2028	Assert(cCurPages < cPages);
2029
2030	do
2031	{
2032	rc = vboxVDMACrCmdVbvaProcessPagingEls(pDevIns, pPages, cCurPages, pu8Vram, fIn);
2033	if (!RT_SUCCESS(rc))
2034	{
2035	WARN(("vboxVDMACrCmdVbvaProcessPagingEls failed %d", rc));
2036	i8Result = -1;
2037	/* we need to break, not return, to ensure currently locked page is released */
2038	break;
2039	}
2040
2041	Assert(cPages >= cCurPages);
2042	cPages -= cCurPages;
2043
2044	if (!cPages)
2045	break;
2046
2047	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
2048
2049	Assert(!(phCmd & PAGE_OFFSET_MASK));
2050
2051	phCmd += PAGE_SIZE;
2052	pu8Vram += (VBOXCMDVBVAOFFSET)cCurPages << PAGE_SHIFT;
2053
2054	rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phCmd, 0, &pvCmd, &Lock);
2055	if (!RT_SUCCESS(rc))
2056	{
2057	WARN(("PDMDevHlpPhysGCPhys2CCPtrReadOnly failed %d\n", rc));
2058	/* the page is not locked, return */
2059	return -1;
2060	}
2061
2062	cCurPages = PAGE_SIZE / sizeof (VBOXCMDVBVAPAGEIDX);
2063	if (cCurPages > cPages)
2064	cCurPages = cPages;
2065	} while (1);
2066	break;
2067	}
2068	default:
2069	WARN(("command can not be splitted"));
2070	i8Result = -1;
2071	break;
2072	}
2073
2074	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
2075	return i8Result;
2076	}
2077	case VBOXCMDVBVA_OPTYPE_COMPLEXCMD:
2078	{
2079	Assert(cbCmd >= sizeof (VBOXCMDVBVA_HDR));
2080	++pCmd;
2081	cbCmd -= sizeof (*pCmd);
2082	uint32_t cbCurCmd = 0;
2083	for ( ; cbCmd; cbCmd -= cbCurCmd, pCmd = (VBOXCMDVBVA_HDR)(((uint8_t)pCmd) + cbCurCmd))
2084	{
2085	if (cbCmd < sizeof (VBOXCMDVBVA_HDR))
2086	{
2087	WARN(("invalid command size"));
2088	return -1;
2089	}
2090
2091	cbCurCmd = pCmd->u2.complexCmdEl.u16CbCmdHost;
2092	if (cbCmd < cbCurCmd)
2093	{
2094	WARN(("invalid command size"));
2095	return -1;
2096	}
2097
2098	i8Result = vboxVDMACrCmdVbvaProcess(pVdma, pCmd, cbCurCmd);
2099	if (i8Result < 0)
2100	{
2101	WARN(("vboxVDMACrCmdVbvaProcess failed"));
2102	return i8Result;
2103	}
2104	}
2105	return 0;
2106	}
2107	default:
2108	i8Result = vboxVDMACrCmdVbvaProcessCmdData(pVdma, pCmd, cbCmd);
2109	LogRelFlow(("VDMA: vboxVDMACrCmdVbvaProcess: LEAVE, opCode(%i)\n", pCmd->u8OpCode));
2110	return i8Result;
2111	}
2112	}
2113
2114	static void vboxVDMACrCmdProcess(struct VBOXVDMAHOST pVdma, uint8_t pu8Cmd, uint32_t cbCmd)
2115	{
2116	if (*pu8Cmd == VBOXCMDVBVA_OPTYPE_NOP)
2117	return;
2118
2119	if (cbCmd < sizeof (VBOXCMDVBVA_HDR))
2120	{
2121	WARN(("invalid command size"));
2122	return;
2123	}
2124
2125	PVBOXCMDVBVA_HDR pCmd = (PVBOXCMDVBVA_HDR)pu8Cmd;
2126
2127	/* check if the command is cancelled */
2128	if (!ASMAtomicCmpXchgU8(&pCmd->u8State, VBOXCMDVBVA_STATE_IN_PROGRESS, VBOXCMDVBVA_STATE_SUBMITTED))
2129	{
2130	Assert(pCmd->u8State == VBOXCMDVBVA_STATE_CANCELLED);
2131	return;
2132	}
2133
2134	pCmd->u.i8Result = vboxVDMACrCmdVbvaProcess(pVdma, pCmd, cbCmd);
2135	}
2136
2137	static int vboxVDMACrCtlHgsmiSetup(struct VBOXVDMAHOST *pVdma)
2138	{
2139	PVBOXVDMACMD_CHROMIUM_CTL_CRHGSMI_SETUP pCmd = (PVBOXVDMACMD_CHROMIUM_CTL_CRHGSMI_SETUP)
2140	vboxVDMACrCtlCreate (VBOXVDMACMD_CHROMIUM_CTL_TYPE_CRHGSMI_SETUP, sizeof (*pCmd));
2141	int rc = VERR_NO_MEMORY;
2142	if (pCmd)
2143	{
2144	PVGASTATE pVGAState = pVdma->pVGAState;
2145	pCmd->pvVRamBase = pVGAState->vram_ptrR3;
2146	pCmd->cbVRam = pVGAState->vram_size;
2147	pCmd->pLed = &pVGAState->Led3D;
2148	pCmd->CrClientInfo.hClient = pVdma;
2149	pCmd->CrClientInfo.pfnCallout = vboxCmdVBVACmdCallout;
2150	rc = vboxVDMACrCtlPost(pVGAState, &pCmd->Hdr, sizeof (*pCmd));
2151	if (RT_SUCCESS(rc))
2152	{
2153	rc = vboxVDMACrCtlGetRc(&pCmd->Hdr);
2154	if (RT_SUCCESS(rc))
2155	pVdma->CrSrvInfo = pCmd->CrCmdServerInfo;
2156	else if (rc != VERR_NOT_SUPPORTED)
2157	WARN(("vboxVDMACrCtlGetRc returned %d\n", rc));
2158	}
2159	else
2160	WARN(("vboxVDMACrCtlPost failed %d\n", rc));
2161
2162	vboxVDMACrCtlRelease(&pCmd->Hdr);
2163	}
2164
2165	if (!RT_SUCCESS(rc))
2166	memset(&pVdma->CrSrvInfo, 0, sizeof (pVdma->CrSrvInfo));
2167
2168	return rc;
2169	}
2170
2171	static int vboxVDMACmdExecBpbTransfer(PVBOXVDMAHOST pVdma, const PVBOXVDMACMD_DMA_BPB_TRANSFER pTransfer, uint32_t cbBuffer);
2172
2173	/* check if this is external cmd to be passed to chromium backend */
2174	static int vboxVDMACmdCheckCrCmd(struct VBOXVDMAHOST *pVdma, PVBOXVDMACBUF_DR pCmdDr, uint32_t cbCmdDr)
2175	{
2176	PVBOXVDMACMD pDmaCmd = NULL;
2177	uint32_t cbDmaCmd = 0;
2178	uint8_t * pvRam = pVdma->pVGAState->vram_ptrR3;
2179	int rc = VINF_NOT_SUPPORTED;
2180
2181	cbDmaCmd = pCmdDr->cbBuf;
2182
2183	if (pCmdDr->fFlags & VBOXVDMACBUF_FLAG_BUF_FOLLOWS_DR)
2184	{
2185	if (cbCmdDr < sizeof (*pCmdDr) + VBOXVDMACMD_HEADER_SIZE())
2186	{
2187	AssertMsgFailed(("invalid buffer data!"));
2188	return VERR_INVALID_PARAMETER;
2189	}
2190
2191	if (cbDmaCmd < cbCmdDr - sizeof (*pCmdDr) - VBOXVDMACMD_HEADER_SIZE())
2192	{
2193	AssertMsgFailed(("invalid command buffer data!"));
2194	return VERR_INVALID_PARAMETER;
2195	}
2196
2197	pDmaCmd = VBOXVDMACBUF_DR_TAIL(pCmdDr, VBOXVDMACMD);
2198	}
2199	else if (pCmdDr->fFlags & VBOXVDMACBUF_FLAG_BUF_VRAM_OFFSET)
2200	{
2201	VBOXVIDEOOFFSET offBuf = pCmdDr->Location.offVramBuf;
2202	if (offBuf + cbDmaCmd > pVdma->pVGAState->vram_size)
2203	{
2204	AssertMsgFailed(("invalid command buffer data from offset!"));
2205	return VERR_INVALID_PARAMETER;
2206	}
2207	pDmaCmd = (VBOXVDMACMD*)(pvRam + offBuf);
2208	}
2209
2210	if (pDmaCmd)
2211	{
2212	Assert(cbDmaCmd >= VBOXVDMACMD_HEADER_SIZE());
2213	uint32_t cbBody = VBOXVDMACMD_BODY_SIZE(cbDmaCmd);
2214
2215	switch (pDmaCmd->enmType)
2216	{
2217	case VBOXVDMACMD_TYPE_CHROMIUM_CMD:
2218	{
2219	PVBOXVDMACMD_CHROMIUM_CMD pCrCmd = VBOXVDMACMD_BODY(pDmaCmd, VBOXVDMACMD_CHROMIUM_CMD);
2220	if (cbBody < sizeof (*pCrCmd))
2221	{
2222	AssertMsgFailed(("invalid chromium command buffer size!"));
2223	return VERR_INVALID_PARAMETER;
2224	}
2225	PVGASTATE pVGAState = pVdma->pVGAState;
2226	rc = VINF_SUCCESS;
2227	if (pVGAState->pDrv->pfnCrHgsmiCommandProcess)
2228	{
2229	VBoxSHGSMICommandMarkAsynchCompletion(pCmdDr);
2230	pVGAState->pDrv->pfnCrHgsmiCommandProcess(pVGAState->pDrv, pCrCmd, cbBody);
2231	break;
2232	}
2233	else
2234	{
2235	Assert(0);
2236	}
2237
2238	int tmpRc = VBoxSHGSMICommandComplete (pVdma->pHgsmi, pCmdDr);
2239	AssertRC(tmpRc);
2240	break;
2241	}
2242	case VBOXVDMACMD_TYPE_DMA_BPB_TRANSFER:
2243	{
2244	PVBOXVDMACMD_DMA_BPB_TRANSFER pTransfer = VBOXVDMACMD_BODY(pDmaCmd, VBOXVDMACMD_DMA_BPB_TRANSFER);
2245	if (cbBody < sizeof (*pTransfer))
2246	{
2247	AssertMsgFailed(("invalid bpb transfer buffer size!"));
2248	return VERR_INVALID_PARAMETER;
2249	}
2250
2251	rc = vboxVDMACmdExecBpbTransfer(pVdma, pTransfer, sizeof (*pTransfer));
2252	AssertRC(rc);
2253	if (RT_SUCCESS(rc))
2254	{
2255	pCmdDr->rc = VINF_SUCCESS;
2256	rc = VBoxSHGSMICommandComplete (pVdma->pHgsmi, pCmdDr);
2257	AssertRC(rc);
2258	rc = VINF_SUCCESS;
2259	}
2260	break;
2261	}
2262	default:
2263	break;
2264	}
2265	}
2266	return rc;
2267	}
2268
2269	int vboxVDMACrHgsmiCommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CMD pCmd, int rc)
2270	{
2271	PVGASTATE pVGAState = PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(pInterface);
2272	PHGSMIINSTANCE pIns = pVGAState->pHGSMI;
2273	VBOXVDMACMD *pDmaHdr = VBOXVDMACMD_FROM_BODY(pCmd);
2274	VBOXVDMACBUF_DR *pDr = VBOXVDMACBUF_DR_FROM_TAIL(pDmaHdr);
2275	AssertRC(rc);
2276	pDr->rc = rc;
2277
2278	Assert(pVGAState->fGuestCaps & VBVACAPS_COMPLETEGCMD_BY_IOREAD);
2279	rc = VBoxSHGSMICommandComplete(pIns, pDr);
2280	AssertRC(rc);
2281	return rc;
2282	}
2283
2284	int vboxVDMACrHgsmiControlCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CTL pCmd, int rc)
2285	{
2286	PVGASTATE pVGAState = PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(pInterface);
2287	PVBOXVDMACMD_CHROMIUM_CTL_PRIVATE pCmdPrivate = VBOXVDMACMD_CHROMIUM_CTL_PRIVATE_FROM_CTL(pCmd);
2288	pCmdPrivate->rc = rc;
2289	if (pCmdPrivate->pfnCompletion)
2290	{
2291	pCmdPrivate->pfnCompletion(pVGAState, pCmd, pCmdPrivate->pvCompletion);
2292	}
2293	return VINF_SUCCESS;
2294	}
2295
2296	static int vboxVDMACmdExecBltPerform(PVBOXVDMAHOST pVdma, uint8_t pvDstSurf, const uint8_t pvSrcSurf,
2297	const PVBOXVDMA_SURF_DESC pDstDesc, const PVBOXVDMA_SURF_DESC pSrcDesc,
2298	const VBOXVDMA_RECTL * pDstRectl, const VBOXVDMA_RECTL * pSrcRectl)
2299	{
2300	RT_NOREF(pVdma);
2301	/* we do not support color conversion */
2302	Assert(pDstDesc->format == pSrcDesc->format);
2303	/* we do not support stretching */
2304	Assert(pDstRectl->height == pSrcRectl->height);
2305	Assert(pDstRectl->width == pSrcRectl->width);
2306	if (pDstDesc->format != pSrcDesc->format)
2307	return VERR_INVALID_FUNCTION;
2308	if (pDstDesc->width == pDstRectl->width
2309	&& pSrcDesc->width == pSrcRectl->width
2310	&& pSrcDesc->width == pDstDesc->width)
2311	{
2312	Assert(!pDstRectl->left);
2313	Assert(!pSrcRectl->left);
2314	uint32_t cbOff = pDstDesc->pitch * pDstRectl->top;
2315	uint32_t cbSize = pDstDesc->pitch * pDstRectl->height;
2316	memcpy(pvDstSurf + cbOff, pvSrcSurf + cbOff, cbSize);
2317	}
2318	else
2319	{
2320	uint32_t offDstLineStart = pDstRectl->left * pDstDesc->bpp >> 3;
2321	uint32_t offDstLineEnd = ((pDstRectl->left * pDstDesc->bpp + 7) >> 3) + ((pDstDesc->bpp * pDstRectl->width + 7) >> 3);
2322	uint32_t cbDstLine = offDstLineEnd - offDstLineStart;
2323	uint32_t offDstStart = pDstDesc->pitch * pDstRectl->top + offDstLineStart;
2324	Assert(cbDstLine <= pDstDesc->pitch);
2325	uint32_t cbDstSkip = pDstDesc->pitch;
2326	uint8_t * pvDstStart = pvDstSurf + offDstStart;
2327
2328	uint32_t offSrcLineStart = pSrcRectl->left * pSrcDesc->bpp >> 3;
2329	# ifdef VBOX_STRICT
2330	uint32_t offSrcLineEnd = ((pSrcRectl->left * pSrcDesc->bpp + 7) >> 3) + ((pSrcDesc->bpp * pSrcRectl->width + 7) >> 3);
2331	uint32_t cbSrcLine = offSrcLineEnd - offSrcLineStart;
2332	# endif
2333	uint32_t offSrcStart = pSrcDesc->pitch * pSrcRectl->top + offSrcLineStart;
2334	Assert(cbSrcLine <= pSrcDesc->pitch);
2335	uint32_t cbSrcSkip = pSrcDesc->pitch;
2336	const uint8_t * pvSrcStart = pvSrcSurf + offSrcStart;
2337
2338	Assert(cbDstLine == cbSrcLine);
2339
2340	for (uint32_t i = 0; ; ++i)
2341	{
2342	memcpy (pvDstStart, pvSrcStart, cbDstLine);
2343	if (i == pDstRectl->height)
2344	break;
2345	pvDstStart += cbDstSkip;
2346	pvSrcStart += cbSrcSkip;
2347	}
2348	}
2349	return VINF_SUCCESS;
2350	}
2351
2352	static void vboxVDMARectlUnite(VBOXVDMA_RECTL * pRectl1, const VBOXVDMA_RECTL * pRectl2)
2353	{
2354	if (!pRectl1->width)
2355	pRectl1 = pRectl2;
2356	else
2357	{
2358	int16_t x21 = pRectl1->left + pRectl1->width;
2359	int16_t x22 = pRectl2->left + pRectl2->width;
2360	if (pRectl1->left > pRectl2->left)
2361	{
2362	pRectl1->left = pRectl2->left;
2363	pRectl1->width = x21 < x22 ? x22 - pRectl1->left : x21 - pRectl1->left;
2364	}
2365	else if (x21 < x22)
2366	pRectl1->width = x22 - pRectl1->left;
2367
2368	x21 = pRectl1->top + pRectl1->height;
2369	x22 = pRectl2->top + pRectl2->height;
2370	if (pRectl1->top > pRectl2->top)
2371	{
2372	pRectl1->top = pRectl2->top;
2373	pRectl1->height = x21 < x22 ? x22 - pRectl1->top : x21 - pRectl1->top;
2374	}
2375	else if (x21 < x22)
2376	pRectl1->height = x22 - pRectl1->top;
2377	}
2378	}
2379
2380	/*
2381	* @return on success the number of bytes the command contained, otherwise - VERR_xxx error code
2382	*/
2383	static int vboxVDMACmdExecBlt(PVBOXVDMAHOST pVdma, const PVBOXVDMACMD_DMA_PRESENT_BLT pBlt, uint32_t cbBuffer)
2384	{
2385	const uint32_t cbBlt = VBOXVDMACMD_BODY_FIELD_OFFSET(uint32_t, VBOXVDMACMD_DMA_PRESENT_BLT, aDstSubRects[pBlt->cDstSubRects]);
2386	Assert(cbBlt <= cbBuffer);
2387	if (cbBuffer < cbBlt)
2388	return VERR_INVALID_FUNCTION;
2389
2390	/* we do not support stretching for now */
2391	Assert(pBlt->srcRectl.width == pBlt->dstRectl.width);
2392	Assert(pBlt->srcRectl.height == pBlt->dstRectl.height);
2393	if (pBlt->srcRectl.width != pBlt->dstRectl.width)
2394	return VERR_INVALID_FUNCTION;
2395	if (pBlt->srcRectl.height != pBlt->dstRectl.height)
2396	return VERR_INVALID_FUNCTION;
2397	Assert(pBlt->cDstSubRects);
2398
2399	uint8_t * pvRam = pVdma->pVGAState->vram_ptrR3;
2400	VBOXVDMA_RECTL updateRectl = {0, 0, 0, 0};
2401
2402	if (pBlt->cDstSubRects)
2403	{
2404	VBOXVDMA_RECTL dstRectl, srcRectl;
2405	const VBOXVDMA_RECTL pDstRectl, pSrcRectl;
2406	for (uint32_t i = 0; i < pBlt->cDstSubRects; ++i)
2407	{
2408	pDstRectl = &pBlt->aDstSubRects[i];
2409	if (pBlt->dstRectl.left \|\| pBlt->dstRectl.top)
2410	{
2411	dstRectl.left = pDstRectl->left + pBlt->dstRectl.left;
2412	dstRectl.top = pDstRectl->top + pBlt->dstRectl.top;
2413	dstRectl.width = pDstRectl->width;
2414	dstRectl.height = pDstRectl->height;
2415	pDstRectl = &dstRectl;
2416	}
2417
2418	pSrcRectl = &pBlt->aDstSubRects[i];
2419	if (pBlt->srcRectl.left \|\| pBlt->srcRectl.top)
2420	{
2421	srcRectl.left = pSrcRectl->left + pBlt->srcRectl.left;
2422	srcRectl.top = pSrcRectl->top + pBlt->srcRectl.top;
2423	srcRectl.width = pSrcRectl->width;
2424	srcRectl.height = pSrcRectl->height;
2425	pSrcRectl = &srcRectl;
2426	}
2427
2428	int rc = vboxVDMACmdExecBltPerform(pVdma, pvRam + pBlt->offDst, pvRam + pBlt->offSrc,
2429	&pBlt->dstDesc, &pBlt->srcDesc,
2430	pDstRectl,
2431	pSrcRectl);
2432	AssertRC(rc);
2433	if (!RT_SUCCESS(rc))
2434	return rc;
2435
2436	vboxVDMARectlUnite(&updateRectl, pDstRectl);
2437	}
2438	}
2439	else
2440	{
2441	int rc = vboxVDMACmdExecBltPerform(pVdma, pvRam + pBlt->offDst, pvRam + pBlt->offSrc,
2442	&pBlt->dstDesc, &pBlt->srcDesc,
2443	&pBlt->dstRectl,
2444	&pBlt->srcRectl);
2445	AssertRC(rc);
2446	if (!RT_SUCCESS(rc))
2447	return rc;
2448
2449	vboxVDMARectlUnite(&updateRectl, &pBlt->dstRectl);
2450	}
2451
2452	return cbBlt;
2453	}
2454
2455	static int vboxVDMACmdExecBpbTransfer(PVBOXVDMAHOST pVdma, const PVBOXVDMACMD_DMA_BPB_TRANSFER pTransfer, uint32_t cbBuffer)
2456	{
2457	if (cbBuffer < sizeof (*pTransfer))
2458	return VERR_INVALID_PARAMETER;
2459
2460	PVGASTATE pVGAState = pVdma->pVGAState;
2461	uint8_t * pvRam = pVGAState->vram_ptrR3;
2462	PGMPAGEMAPLOCK SrcLock;
2463	PGMPAGEMAPLOCK DstLock;
2464	PPDMDEVINS pDevIns = pVdma->pVGAState->pDevInsR3;
2465	const void * pvSrc;
2466	void * pvDst;
2467	int rc = VINF_SUCCESS;
2468	uint32_t cbTransfer = pTransfer->cbTransferSize;
2469	uint32_t cbTransfered = 0;
2470	bool bSrcLocked = false;
2471	bool bDstLocked = false;
2472	do
2473	{
2474	uint32_t cbSubTransfer = cbTransfer;
2475	if (pTransfer->fFlags & VBOXVDMACMD_DMA_BPB_TRANSFER_F_SRC_VRAMOFFSET)
2476	{
2477	pvSrc = pvRam + pTransfer->Src.offVramBuf + cbTransfered;
2478	}
2479	else
2480	{
2481	RTGCPHYS phPage = pTransfer->Src.phBuf;
2482	phPage += cbTransfered;
2483	rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phPage, 0, &pvSrc, &SrcLock);
2484	AssertRC(rc);
2485	if (RT_SUCCESS(rc))
2486	{
2487	bSrcLocked = true;
2488	cbSubTransfer = RT_MIN(cbSubTransfer, 0x1000);
2489	}
2490	else
2491	{
2492	break;
2493	}
2494	}
2495
2496	if (pTransfer->fFlags & VBOXVDMACMD_DMA_BPB_TRANSFER_F_DST_VRAMOFFSET)
2497	{
2498	pvDst = pvRam + pTransfer->Dst.offVramBuf + cbTransfered;
2499	}
2500	else
2501	{
2502	RTGCPHYS phPage = pTransfer->Dst.phBuf;
2503	phPage += cbTransfered;
2504	rc = PDMDevHlpPhysGCPhys2CCPtr(pDevIns, phPage, 0, &pvDst, &DstLock);
2505	AssertRC(rc);
2506	if (RT_SUCCESS(rc))
2507	{
2508	bDstLocked = true;
2509	cbSubTransfer = RT_MIN(cbSubTransfer, 0x1000);
2510	}
2511	else
2512	{
2513	break;
2514	}
2515	}
2516
2517	if (RT_SUCCESS(rc))
2518	{
2519	memcpy(pvDst, pvSrc, cbSubTransfer);
2520	cbTransfer -= cbSubTransfer;
2521	cbTransfered += cbSubTransfer;
2522	}
2523	else
2524	{
2525	cbTransfer = 0; /* to break */
2526	}
2527
2528	if (bSrcLocked)
2529	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &SrcLock);
2530	if (bDstLocked)
2531	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &DstLock);
2532	} while (cbTransfer);
2533
2534	if (RT_SUCCESS(rc))
2535	return sizeof (*pTransfer);
2536	return rc;
2537	}
2538
2539	static int vboxVDMACmdExec(PVBOXVDMAHOST pVdma, const uint8_t *pvBuffer, uint32_t cbBuffer)
2540	{
2541	do
2542	{
2543	Assert(pvBuffer);
2544	Assert(cbBuffer >= VBOXVDMACMD_HEADER_SIZE());
2545
2546	if (!pvBuffer)
2547	return VERR_INVALID_PARAMETER;
2548	if (cbBuffer < VBOXVDMACMD_HEADER_SIZE())
2549	return VERR_INVALID_PARAMETER;
2550
2551	PVBOXVDMACMD pCmd = (PVBOXVDMACMD)pvBuffer;
2552	switch (pCmd->enmType)
2553	{
2554	case VBOXVDMACMD_TYPE_CHROMIUM_CMD:
2555	{
2556	# ifdef VBOXWDDM_TEST_UHGSMI
2557	static int count = 0;
2558	static uint64_t start, end;
2559	if (count==0)
2560	{
2561	start = RTTimeNanoTS();
2562	}
2563	++count;
2564	if (count==100000)
2565	{
2566	end = RTTimeNanoTS();
2567	float ems = (end-start)/1000000.f;
2568	LogRel(("100000 calls took %i ms, %i cps\n", (int)ems, (int)(100000.f*1000.f/ems) ));
2569	}
2570	# endif
2571	/** @todo post the buffer to chromium */
2572	return VINF_SUCCESS;
2573	}
2574	case VBOXVDMACMD_TYPE_DMA_PRESENT_BLT:
2575	{
2576	const PVBOXVDMACMD_DMA_PRESENT_BLT pBlt = VBOXVDMACMD_BODY(pCmd, VBOXVDMACMD_DMA_PRESENT_BLT);
2577	int cbBlt = vboxVDMACmdExecBlt(pVdma, pBlt, cbBuffer);
2578	Assert(cbBlt >= 0);
2579	Assert((uint32_t)cbBlt <= cbBuffer);
2580	if (cbBlt >= 0)
2581	{
2582	if ((uint32_t)cbBlt == cbBuffer)
2583	return VINF_SUCCESS;
2584	else
2585	{
2586	cbBuffer -= (uint32_t)cbBlt;
2587	pvBuffer -= cbBlt;
2588	}
2589	}
2590	else
2591	return cbBlt; /* error */
2592	break;
2593	}
2594	case VBOXVDMACMD_TYPE_DMA_BPB_TRANSFER:
2595	{
2596	const PVBOXVDMACMD_DMA_BPB_TRANSFER pTransfer = VBOXVDMACMD_BODY(pCmd, VBOXVDMACMD_DMA_BPB_TRANSFER);
2597	int cbTransfer = vboxVDMACmdExecBpbTransfer(pVdma, pTransfer, cbBuffer);
2598	Assert(cbTransfer >= 0);
2599	Assert((uint32_t)cbTransfer <= cbBuffer);
2600	if (cbTransfer >= 0)
2601	{
2602	if ((uint32_t)cbTransfer == cbBuffer)
2603	return VINF_SUCCESS;
2604	else
2605	{
2606	cbBuffer -= (uint32_t)cbTransfer;
2607	pvBuffer -= cbTransfer;
2608	}
2609	}
2610	else
2611	return cbTransfer; /* error */
2612	break;
2613	}
2614	case VBOXVDMACMD_TYPE_DMA_NOP:
2615	return VINF_SUCCESS;
2616	case VBOXVDMACMD_TYPE_CHILD_STATUS_IRQ:
2617	return VINF_SUCCESS;
2618	default:
2619	AssertBreakpoint();
2620	return VERR_INVALID_FUNCTION;
2621	}
2622	} while (1);
2623
2624	/* we should not be here */
2625	AssertBreakpoint();
2626	return VERR_INVALID_STATE;
2627	}
2628
2629	static DECLCALLBACK(int) vboxVDMAWorkerThread(RTTHREAD hThreadSelf, void *pvUser)
2630	{
2631	RT_NOREF(hThreadSelf);
2632	PVBOXVDMAHOST pVdma = (PVBOXVDMAHOST)pvUser;
2633	PVGASTATE pVGAState = pVdma->pVGAState;
2634	VBVAEXHOSTCONTEXT *pCmdVbva = &pVdma->CmdVbva;
2635	uint8_t *pCmd;
2636	uint32_t cbCmd;
2637	int rc;
2638
2639	VBoxVDMAThreadNotifyConstructSucceeded(&pVdma->Thread, pvUser);
2640
2641	while (!VBoxVDMAThreadIsTerminating(&pVdma->Thread))
2642	{
2643	VBVAEXHOST_DATA_TYPE enmType = VBoxVBVAExHPDataGet(pCmdVbva, &pCmd, &cbCmd);
2644	switch (enmType)
2645	{
2646	case VBVAEXHOST_DATA_TYPE_CMD:
2647	vboxVDMACrCmdProcess(pVdma, pCmd, cbCmd);
2648	VBoxVBVAExHPDataCompleteCmd(pCmdVbva, cbCmd);
2649	VBVARaiseIrq(pVGAState, 0);
2650	break;
2651	case VBVAEXHOST_DATA_TYPE_GUESTCTL:
2652	rc = vboxVDMACrGuestCtlProcess(pVdma, (VBVAEXHOSTCTL*)pCmd);
2653	VBoxVBVAExHPDataCompleteCtl(pCmdVbva, (VBVAEXHOSTCTL*)pCmd, rc);
2654	break;
2655	case VBVAEXHOST_DATA_TYPE_HOSTCTL:
2656	{
2657	bool fContinue = true;
2658	rc = vboxVDMACrHostCtlProcess(pVdma, (VBVAEXHOSTCTL*)pCmd, &fContinue);
2659	VBoxVBVAExHPDataCompleteCtl(pCmdVbva, (VBVAEXHOSTCTL*)pCmd, rc);
2660	if (fContinue)
2661	break;
2662	}
2663	RT_FALL_THRU();
2664	case VBVAEXHOST_DATA_TYPE_NO_DATA:
2665	rc = VBoxVDMAThreadEventWait(&pVdma->Thread, RT_INDEFINITE_WAIT);
2666	AssertRC(rc);
2667	break;
2668	default:
2669	WARN(("unexpected type %d\n", enmType));
2670	break;
2671	}
2672	}
2673
2674	VBoxVDMAThreadNotifyTerminatingSucceeded(&pVdma->Thread, pvUser);
2675
2676	return VINF_SUCCESS;
2677	}
2678
2679	static void vboxVDMACommandProcess(PVBOXVDMAHOST pVdma, PVBOXVDMACBUF_DR pCmd, uint32_t cbCmd)
2680	{
2681	RT_NOREF(cbCmd);
2682	PHGSMIINSTANCE pHgsmi = pVdma->pHgsmi;
2683	const uint8_t * pvBuf;
2684	PGMPAGEMAPLOCK Lock;
2685	int rc;
2686	bool bReleaseLocked = false;
2687
2688	do
2689	{
2690	PPDMDEVINS pDevIns = pVdma->pVGAState->pDevInsR3;
2691
2692	if (pCmd->fFlags & VBOXVDMACBUF_FLAG_BUF_FOLLOWS_DR)
2693	pvBuf = VBOXVDMACBUF_DR_TAIL(pCmd, const uint8_t);
2694	else if (pCmd->fFlags & VBOXVDMACBUF_FLAG_BUF_VRAM_OFFSET)
2695	{
2696	uint8_t * pvRam = pVdma->pVGAState->vram_ptrR3;
2697	pvBuf = pvRam + pCmd->Location.offVramBuf;
2698	}
2699	else
2700	{
2701	RTGCPHYS phPage = pCmd->Location.phBuf & ~0xfffULL;
2702	uint32_t offset = pCmd->Location.phBuf & 0xfff;
2703	Assert(offset + pCmd->cbBuf <= 0x1000);
2704	if (offset + pCmd->cbBuf > 0x1000)
2705	{
2706	/** @todo more advanced mechanism of command buffer proc is actually needed */
2707	rc = VERR_INVALID_PARAMETER;
2708	break;
2709	}
2710
2711	const void * pvPageBuf;
2712	rc = PDMDevHlpPhysGCPhys2CCPtrReadOnly(pDevIns, phPage, 0, &pvPageBuf, &Lock);
2713	AssertRC(rc);
2714	if (!RT_SUCCESS(rc))
2715	{
2716	/** @todo if (rc == VERR_PGM_PHYS_PAGE_RESERVED) -> fall back on using PGMPhysRead ?? */
2717	break;
2718	}
2719
2720	pvBuf = (const uint8_t *)pvPageBuf;
2721	pvBuf += offset;
2722
2723	bReleaseLocked = true;
2724	}
2725
2726	rc = vboxVDMACmdExec(pVdma, pvBuf, pCmd->cbBuf);
2727	AssertRC(rc);
2728
2729	if (bReleaseLocked)
2730	PDMDevHlpPhysReleasePageMappingLock(pDevIns, &Lock);
2731	} while (0);
2732
2733	pCmd->rc = rc;
2734
2735	rc = VBoxSHGSMICommandComplete (pHgsmi, pCmd);
2736	AssertRC(rc);
2737	}
2738
2739	# if 0 /** @todo vboxVDMAControlProcess is unused */
2740	static void vboxVDMAControlProcess(PVBOXVDMAHOST pVdma, PVBOXVDMA_CTL pCmd)
2741	{
2742	PHGSMIINSTANCE pHgsmi = pVdma->pHgsmi;
2743	pCmd->i32Result = VINF_SUCCESS;
2744	int rc = VBoxSHGSMICommandComplete (pHgsmi, pCmd);
2745	AssertRC(rc);
2746	}
2747	# endif
2748
2749	#endif /* VBOX_WITH_CRHGSMI */
2750	#ifdef VBOX_VDMA_WITH_WATCHDOG
2751
2752	static DECLCALLBACK(void) vboxVDMAWatchDogTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2753	{
2754	VBOXVDMAHOST pVdma = (VBOXVDMAHOST )pvUser;
2755	PVGASTATE pVGAState = pVdma->pVGAState;
2756	VBVARaiseIrq(pVGAState, HGSMIHOSTFLAGS_WATCHDOG);
2757	}
2758
2759	static int vboxVDMAWatchDogCtl(struct VBOXVDMAHOST *pVdma, uint32_t cMillis)
2760	{
2761	PPDMDEVINS pDevIns = pVdma->pVGAState->pDevInsR3;
2762	if (cMillis)
2763	TMTimerSetMillies(pVdma->WatchDogTimer, cMillis);
2764	else
2765	TMTimerStop(pVdma->WatchDogTimer);
2766	return VINF_SUCCESS;
2767	}
2768
2769	#endif /* VBOX_VDMA_WITH_WATCHDOG */
2770
2771	int vboxVDMAConstruct(PVGASTATE pVGAState, uint32_t cPipeElements)
2772	{
2773	RT_NOREF(cPipeElements);
2774	int rc;
2775	PVBOXVDMAHOST pVdma = (PVBOXVDMAHOST)RTMemAllocZ(sizeof(*pVdma));
2776	Assert(pVdma);
2777	if (pVdma)
2778	{
2779	pVdma->pHgsmi = pVGAState->pHGSMI;
2780	pVdma->pVGAState = pVGAState;
2781
2782	#ifdef VBOX_VDMA_WITH_WATCHDOG
2783	rc = PDMDevHlpTMTimerCreate(pVGAState->pDevInsR3, TMCLOCK_REAL, vboxVDMAWatchDogTimer,
2784	pVdma, TMTIMER_FLAGS_NO_CRIT_SECT,
2785	"VDMA WatchDog Timer", &pVdma->WatchDogTimer);
2786	AssertRC(rc);
2787	#endif
2788
2789	#ifdef VBOX_WITH_CRHGSMI
2790	VBoxVDMAThreadInit(&pVdma->Thread);
2791
2792	rc = RTSemEventMultiCreate(&pVdma->HostCrCtlCompleteEvent);
2793	if (RT_SUCCESS(rc))
2794	{
2795	rc = VBoxVBVAExHSInit(&pVdma->CmdVbva);
2796	if (RT_SUCCESS(rc))
2797	{
2798	rc = RTCritSectInit(&pVdma->CalloutCritSect);
2799	if (RT_SUCCESS(rc))
2800	{
2801	pVGAState->pVdma = pVdma;
2802	int rcIgnored = vboxVDMACrCtlHgsmiSetup(pVdma); NOREF(rcIgnored); /** @todo is this ignoring intentional? */
2803	return VINF_SUCCESS;
2804	}
2805	WARN(("RTCritSectInit failed %d\n", rc));
2806
2807	VBoxVBVAExHSTerm(&pVdma->CmdVbva);
2808	}
2809	else
2810	WARN(("VBoxVBVAExHSInit failed %d\n", rc));
2811
2812	RTSemEventMultiDestroy(pVdma->HostCrCtlCompleteEvent);
2813	}
2814	else
2815	WARN(("RTSemEventMultiCreate failed %d\n", rc));
2816
2817
2818	RTMemFree(pVdma);
2819	#else
2820	pVGAState->pVdma = pVdma;
2821	return VINF_SUCCESS;
2822	#endif
2823	}
2824	else
2825	rc = VERR_OUT_OF_RESOURCES;
2826
2827	return rc;
2828	}
2829
2830	int vboxVDMAReset(struct VBOXVDMAHOST *pVdma)
2831	{
2832	#ifdef VBOX_WITH_CRHGSMI
2833	vdmaVBVACtlDisableSync(pVdma);
2834	#else
2835	RT_NOREF(pVdma);
2836	#endif
2837	return VINF_SUCCESS;
2838	}
2839
2840	int vboxVDMADestruct(struct VBOXVDMAHOST *pVdma)
2841	{
2842	if (!pVdma)
2843	return VINF_SUCCESS;
2844	#ifdef VBOX_WITH_CRHGSMI
2845	vdmaVBVACtlDisableSync(pVdma);
2846	VBoxVDMAThreadCleanup(&pVdma->Thread);
2847	VBoxVBVAExHSTerm(&pVdma->CmdVbva);
2848	RTSemEventMultiDestroy(pVdma->HostCrCtlCompleteEvent);
2849	RTCritSectDelete(&pVdma->CalloutCritSect);
2850	#endif
2851	RTMemFree(pVdma);
2852	return VINF_SUCCESS;
2853	}
2854
2855	void vboxVDMAControl(struct VBOXVDMAHOST *pVdma, PVBOXVDMA_CTL pCmd, uint32_t cbCmd)
2856	{
2857	RT_NOREF(cbCmd);
2858	PHGSMIINSTANCE pIns = pVdma->pHgsmi;
2859
2860	switch (pCmd->enmCtl)
2861	{
2862	case VBOXVDMA_CTL_TYPE_ENABLE:
2863	pCmd->i32Result = VINF_SUCCESS;
2864	break;
2865	case VBOXVDMA_CTL_TYPE_DISABLE:
2866	pCmd->i32Result = VINF_SUCCESS;
2867	break;
2868	case VBOXVDMA_CTL_TYPE_FLUSH:
2869	pCmd->i32Result = VINF_SUCCESS;
2870	break;
2871	#ifdef VBOX_VDMA_WITH_WATCHDOG
2872	case VBOXVDMA_CTL_TYPE_WATCHDOG:
2873	pCmd->i32Result = vboxVDMAWatchDogCtl(pVdma, pCmd->u32Offset);
2874	break;
2875	#endif
2876	default:
2877	WARN(("cmd not supported"));
2878	pCmd->i32Result = VERR_NOT_SUPPORTED;
2879	}
2880
2881	int rc = VBoxSHGSMICommandComplete (pIns, pCmd);
2882	AssertRC(rc);
2883	}
2884
2885	void vboxVDMACommand(struct VBOXVDMAHOST *pVdma, PVBOXVDMACBUF_DR pCmd, uint32_t cbCmd)
2886	{
2887	int rc = VERR_NOT_IMPLEMENTED;
2888
2889	#ifdef VBOX_WITH_CRHGSMI
2890	/* chromium commands are processed by crhomium hgcm thread independently from our internal cmd processing pipeline
2891	* this is why we process them specially */
2892	rc = vboxVDMACmdCheckCrCmd(pVdma, pCmd, cbCmd);
2893	if (rc == VINF_SUCCESS)
2894	return;
2895
2896	if (RT_FAILURE(rc))
2897	{
2898	pCmd->rc = rc;
2899	rc = VBoxSHGSMICommandComplete (pVdma->pHgsmi, pCmd);
2900	AssertRC(rc);
2901	return;
2902	}
2903
2904	vboxVDMACommandProcess(pVdma, pCmd, cbCmd);
2905	#else
2906	RT_NOREF(cbCmd);
2907	pCmd->rc = rc;
2908	rc = VBoxSHGSMICommandComplete (pVdma->pHgsmi, pCmd);
2909	AssertRC(rc);
2910	#endif
2911	}
2912
2913	#ifdef VBOX_WITH_CRHGSMI
2914
2915	static DECLCALLBACK(void) vdmaVBVACtlSubmitSyncCompletion(VBVAEXHOSTCONTEXT pVbva, struct VBVAEXHOSTCTL pCtl, int rc, void *pvContext);
2916
2917	static int vdmaVBVACtlSubmit(PVBOXVDMAHOST pVdma, VBVAEXHOSTCTL* pCtl, VBVAEXHOSTCTL_SOURCE enmSource, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void *pvComplete)
2918	{
2919	int rc = VBoxVBVAExHCtlSubmit(&pVdma->CmdVbva, pCtl, enmSource, pfnComplete, pvComplete);
2920	if (RT_SUCCESS(rc))
2921	{
2922	if (rc == VINF_SUCCESS)
2923	return VBoxVDMAThreadEventNotify(&pVdma->Thread);
2924	else
2925	Assert(rc == VINF_ALREADY_INITIALIZED);
2926	}
2927	else
2928	Log(("VBoxVBVAExHCtlSubmit failed %d\n", rc));
2929
2930	return rc;
2931	}
2932
2933	static DECLCALLBACK(void) vboxCmdVBVACmdCtlGuestCompletion(VBVAEXHOSTCONTEXT pVbva, struct VBVAEXHOSTCTL pCtl, int rc, void *pvContext)
2934	{
2935	PVBOXVDMAHOST pVdma = (PVBOXVDMAHOST)pvContext;
2936	VBOXCMDVBVA_CTL pGCtl = (VBOXCMDVBVA_CTL)(pCtl->u.cmd.pu8Cmd - sizeof (VBOXCMDVBVA_CTL));
2937	AssertRC(rc);
2938	pGCtl->i32Result = rc;
2939
2940	Assert(pVdma->pVGAState->fGuestCaps & VBVACAPS_COMPLETEGCMD_BY_IOREAD);
2941	rc = VBoxSHGSMICommandComplete(pVdma->pHgsmi, pGCtl);
2942	AssertRC(rc);
2943
2944	VBoxVBVAExHCtlFree(pVbva, pCtl);
2945	}
2946
2947	static int vdmaVBVACtlGenericSubmit(PVBOXVDMAHOST pVdma, VBVAEXHOSTCTL_SOURCE enmSource, VBVAEXHOSTCTL_TYPE enmType, uint8_t* pu8Cmd, uint32_t cbCmd, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void *pvComplete)
2948	{
2949	VBVAEXHOSTCTL* pHCtl = VBoxVBVAExHCtlCreate(&pVdma->CmdVbva, enmType);
2950	if (!pHCtl)
2951	{
2952	WARN(("VBoxVBVAExHCtlCreate failed\n"));
2953	return VERR_NO_MEMORY;
2954	}
2955
2956	pHCtl->u.cmd.pu8Cmd = pu8Cmd;
2957	pHCtl->u.cmd.cbCmd = cbCmd;
2958	int rc = vdmaVBVACtlSubmit(pVdma, pHCtl, enmSource, pfnComplete, pvComplete);
2959	if (RT_FAILURE(rc))
2960	{
2961	VBoxVBVAExHCtlFree(&pVdma->CmdVbva, pHCtl);
2962	Log(("vdmaVBVACtlSubmit failed rc %d\n", rc));
2963	return rc;;
2964	}
2965	return VINF_SUCCESS;
2966	}
2967
2968	static int vdmaVBVACtlGenericGuestSubmit(PVBOXVDMAHOST pVdma, VBVAEXHOSTCTL_TYPE enmType, VBOXCMDVBVA_CTL *pCtl, uint32_t cbCtl)
2969	{
2970	Assert(cbCtl >= sizeof (VBOXCMDVBVA_CTL));
2971	VBoxSHGSMICommandMarkAsynchCompletion(pCtl);
2972	int rc = vdmaVBVACtlGenericSubmit(pVdma, VBVAEXHOSTCTL_SOURCE_GUEST, enmType, (uint8_t*)(pCtl+1), cbCtl - sizeof (VBOXCMDVBVA_CTL), vboxCmdVBVACmdCtlGuestCompletion, pVdma);
2973	if (RT_SUCCESS(rc))
2974	return VINF_SUCCESS;
2975
2976	WARN(("vdmaVBVACtlGenericSubmit failed %d\n", rc));
2977	pCtl->i32Result = rc;
2978	rc = VBoxSHGSMICommandComplete(pVdma->pHgsmi, pCtl);
2979	AssertRC(rc);
2980	return VINF_SUCCESS;
2981	}
2982
2983	static DECLCALLBACK(void) vboxCmdVBVACmdCtlHostCompletion(VBVAEXHOSTCONTEXT pVbva, struct VBVAEXHOSTCTL pCtl, int rc, void *pvCompletion)
2984	{
2985	VBOXCRCMDCTL* pVboxCtl = (VBOXCRCMDCTL*)pCtl->u.cmd.pu8Cmd;
2986	if (pVboxCtl->u.pfnInternal)
2987	((PFNCRCTLCOMPLETION)pVboxCtl->u.pfnInternal)(pVboxCtl, pCtl->u.cmd.cbCmd, rc, pvCompletion);
2988	VBoxVBVAExHCtlFree(pVbva, pCtl);
2989	}
2990
2991	static int vdmaVBVACtlOpaqueHostSubmit(PVBOXVDMAHOST pVdma, struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd,
2992	PFNCRCTLCOMPLETION pfnCompletion,
2993	void *pvCompletion)
2994	{
2995	pCmd->u.pfnInternal = (void(*)())pfnCompletion;
2996	int rc = vdmaVBVACtlGenericSubmit(pVdma, VBVAEXHOSTCTL_SOURCE_HOST, VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE, (uint8_t*)pCmd, cbCmd, vboxCmdVBVACmdCtlHostCompletion, pvCompletion);
2997	if (RT_FAILURE(rc))
2998	{
2999	if (rc == VERR_INVALID_STATE)
3000	{
3001	pCmd->u.pfnInternal = NULL;
3002	PVGASTATE pVGAState = pVdma->pVGAState;
3003	rc = pVGAState->pDrv->pfnCrHgcmCtlSubmit(pVGAState->pDrv, pCmd, cbCmd, pfnCompletion, pvCompletion);
3004	if (!RT_SUCCESS(rc))
3005	WARN(("pfnCrHgsmiControlProcess failed %d\n", rc));
3006
3007	return rc;
3008	}
3009	WARN(("vdmaVBVACtlGenericSubmit failed %d\n", rc));
3010	return rc;
3011	}
3012
3013	return VINF_SUCCESS;
3014	}
3015
3016	static DECLCALLBACK(int) vdmaVBVANotifyEnable(PVGASTATE pVGAState)
3017	{
3018	for (uint32_t i = 0; i < pVGAState->cMonitors; i++)
3019	{
3020	int rc = pVGAState->pDrv->pfnVBVAEnable (pVGAState->pDrv, i, NULL, true);
3021	if (!RT_SUCCESS(rc))
3022	{
3023	WARN(("pfnVBVAEnable failed %d\n", rc));
3024	for (uint32_t j = 0; j < i; j++)
3025	{
3026	pVGAState->pDrv->pfnVBVADisable (pVGAState->pDrv, j);
3027	}
3028
3029	return rc;
3030	}
3031	}
3032	return VINF_SUCCESS;
3033	}
3034
3035	static DECLCALLBACK(int) vdmaVBVANotifyDisable(PVGASTATE pVGAState)
3036	{
3037	for (uint32_t i = 0; i < pVGAState->cMonitors; i++)
3038	{
3039	pVGAState->pDrv->pfnVBVADisable (pVGAState->pDrv, i);
3040	}
3041	return VINF_SUCCESS;
3042	}
3043
3044	static DECLCALLBACK(void) vdmaVBVACtlThreadCreatedEnable(struct VBOXVDMATHREAD *pThread, int rc,
3045	void pvThreadContext, void pvContext)
3046	{
3047	RT_NOREF(pThread);
3048	PVBOXVDMAHOST pVdma = (PVBOXVDMAHOST)pvThreadContext;
3049	VBVAEXHOSTCTL* pHCtl = (VBVAEXHOSTCTL*)pvContext;
3050
3051	if (RT_SUCCESS(rc))
3052	{
3053	rc = vboxVDMACrGuestCtlProcess(pVdma, pHCtl);
3054	/* rc == VINF_SUCCESS would mean the actual state change has occcured */
3055	if (rc == VINF_SUCCESS)
3056	{
3057	/* we need to inform Main about VBVA enable/disable
3058	* main expects notifications to be done from the main thread
3059	* submit it there */
3060	PVGASTATE pVGAState = pVdma->pVGAState;
3061
3062	if (VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
3063	vdmaVBVANotifyEnable(pVGAState);
3064	else
3065	vdmaVBVANotifyDisable(pVGAState);
3066	}
3067	else if (RT_FAILURE(rc))
3068	WARN(("vboxVDMACrGuestCtlProcess failed %d\n", rc));
3069	}
3070	else
3071	WARN(("vdmaVBVACtlThreadCreatedEnable is passed %d\n", rc));
3072
3073	VBoxVBVAExHPDataCompleteCtl(&pVdma->CmdVbva, pHCtl, rc);
3074	}
3075
3076	static int vdmaVBVACtlEnableSubmitInternal(PVBOXVDMAHOST pVdma, VBVAENABLE pEnable, bool fPaused, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void pvComplete)
3077	{
3078	int rc;
3079	VBVAEXHOSTCTL* pHCtl = VBoxVBVAExHCtlCreate(&pVdma->CmdVbva, fPaused ? VBVAEXHOSTCTL_TYPE_GHH_ENABLE_PAUSED : VBVAEXHOSTCTL_TYPE_GHH_ENABLE);
3080	if (pHCtl)
3081	{
3082	pHCtl->u.cmd.pu8Cmd = (uint8_t*)pEnable;
3083	pHCtl->u.cmd.cbCmd = sizeof (*pEnable);
3084	pHCtl->pfnComplete = pfnComplete;
3085	pHCtl->pvComplete = pvComplete;
3086
3087	rc = VBoxVDMAThreadCreate(&pVdma->Thread, vboxVDMAWorkerThread, pVdma, vdmaVBVACtlThreadCreatedEnable, pHCtl);
3088	if (RT_SUCCESS(rc))
3089	return VINF_SUCCESS;
3090	else
3091	WARN(("VBoxVDMAThreadCreate failed %d\n", rc));
3092
3093	VBoxVBVAExHCtlFree(&pVdma->CmdVbva, pHCtl);
3094	}
3095	else
3096	{
3097	WARN(("VBoxVBVAExHCtlCreate failed\n"));
3098	rc = VERR_NO_MEMORY;
3099	}
3100
3101	return rc;
3102	}
3103
3104	static int vdmaVBVACtlEnableSubmitSync(PVBOXVDMAHOST pVdma, uint32_t offVram, bool fPaused)
3105	{
3106	VBVAENABLE Enable = {0};
3107	Enable.u32Flags = VBVA_F_ENABLE;
3108	Enable.u32Offset = offVram;
3109
3110	VDMA_VBVA_CTL_CYNC_COMPLETION Data;
3111	Data.rc = VERR_NOT_IMPLEMENTED;
3112	int rc = RTSemEventCreate(&Data.hEvent);
3113	if (!RT_SUCCESS(rc))
3114	{
3115	WARN(("RTSemEventCreate failed %d\n", rc));
3116	return rc;
3117	}
3118
3119	rc = vdmaVBVACtlEnableSubmitInternal(pVdma, &Enable, fPaused, vdmaVBVACtlSubmitSyncCompletion, &Data);
3120	if (RT_SUCCESS(rc))
3121	{
3122	rc = RTSemEventWait(Data.hEvent, RT_INDEFINITE_WAIT);
3123	if (RT_SUCCESS(rc))
3124	{
3125	rc = Data.rc;
3126	if (!RT_SUCCESS(rc))
3127	WARN(("vdmaVBVACtlSubmitSyncCompletion returned %d\n", rc));
3128	}
3129	else
3130	WARN(("RTSemEventWait failed %d\n", rc));
3131	}
3132	else
3133	WARN(("vdmaVBVACtlSubmit failed %d\n", rc));
3134
3135	RTSemEventDestroy(Data.hEvent);
3136
3137	return rc;
3138	}
3139
3140	static int vdmaVBVACtlDisableSubmitInternal(PVBOXVDMAHOST pVdma, VBVAENABLE pEnable, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void pvComplete)
3141	{
3142	int rc;
3143	VBVAEXHOSTCTL* pHCtl;
3144	if (VBoxVBVAExHSIsDisabled(&pVdma->CmdVbva))
3145	{
3146	WARN(("VBoxVBVAExHSIsDisabled: disabled"));
3147	return VINF_SUCCESS;
3148	}
3149
3150	pHCtl = VBoxVBVAExHCtlCreate(&pVdma->CmdVbva, VBVAEXHOSTCTL_TYPE_GHH_DISABLE);
3151	if (!pHCtl)
3152	{
3153	WARN(("VBoxVBVAExHCtlCreate failed\n"));
3154	return VERR_NO_MEMORY;
3155	}
3156
3157	pHCtl->u.cmd.pu8Cmd = (uint8_t*)pEnable;
3158	pHCtl->u.cmd.cbCmd = sizeof (*pEnable);
3159	rc = vdmaVBVACtlSubmit(pVdma, pHCtl, VBVAEXHOSTCTL_SOURCE_GUEST, pfnComplete, pvComplete);
3160	if (RT_SUCCESS(rc))
3161	return VINF_SUCCESS;
3162
3163	WARN(("vdmaVBVACtlSubmit failed rc %d\n", rc));
3164	VBoxVBVAExHCtlFree(&pVdma->CmdVbva, pHCtl);
3165	return rc;
3166	}
3167
3168	static int vdmaVBVACtlEnableDisableSubmitInternal(PVBOXVDMAHOST pVdma, VBVAENABLE pEnable, PFNVBVAEXHOSTCTL_COMPLETE pfnComplete, void pvComplete)
3169	{
3170	bool fEnable = ((pEnable->u32Flags & (VBVA_F_ENABLE \| VBVA_F_DISABLE)) == VBVA_F_ENABLE);
3171	if (fEnable)
3172	return vdmaVBVACtlEnableSubmitInternal(pVdma, pEnable, false, pfnComplete, pvComplete);
3173	return vdmaVBVACtlDisableSubmitInternal(pVdma, pEnable, pfnComplete, pvComplete);
3174	}
3175
3176	static int vdmaVBVACtlEnableDisableSubmit(PVBOXVDMAHOST pVdma, VBOXCMDVBVA_CTL_ENABLE *pEnable)
3177	{
3178	VBoxSHGSMICommandMarkAsynchCompletion(&pEnable->Hdr);
3179	int rc = vdmaVBVACtlEnableDisableSubmitInternal(pVdma, &pEnable->Enable, vboxCmdVBVACmdCtlGuestCompletion, pVdma);
3180	if (RT_SUCCESS(rc))
3181	return VINF_SUCCESS;
3182
3183	WARN(("vdmaVBVACtlEnableDisableSubmitInternal failed %d\n", rc));
3184	pEnable->Hdr.i32Result = rc;
3185	rc = VBoxSHGSMICommandComplete(pVdma->pHgsmi, &pEnable->Hdr);
3186	AssertRC(rc);
3187	return VINF_SUCCESS;
3188	}
3189
3190	static DECLCALLBACK(void) vdmaVBVACtlSubmitSyncCompletion(VBVAEXHOSTCONTEXT pVbva, struct VBVAEXHOSTCTL pCtl,
3191	int rc, void *pvContext)
3192	{
3193	RT_NOREF(pVbva, pCtl);
3194	VDMA_VBVA_CTL_CYNC_COMPLETION pData = (VDMA_VBVA_CTL_CYNC_COMPLETION)pvContext;
3195	pData->rc = rc;
3196	rc = RTSemEventSignal(pData->hEvent);
3197	if (!RT_SUCCESS(rc))
3198	WARN(("RTSemEventSignal failed %d\n", rc));
3199	}
3200
3201	static int vdmaVBVACtlSubmitSync(PVBOXVDMAHOST pVdma, VBVAEXHOSTCTL* pCtl, VBVAEXHOSTCTL_SOURCE enmSource)
3202	{
3203	VDMA_VBVA_CTL_CYNC_COMPLETION Data;
3204	Data.rc = VERR_NOT_IMPLEMENTED;
3205	int rc = RTSemEventCreate(&Data.hEvent);
3206	if (!RT_SUCCESS(rc))
3207	{
3208	WARN(("RTSemEventCreate failed %d\n", rc));
3209	return rc;
3210	}
3211
3212	rc = vdmaVBVACtlSubmit(pVdma, pCtl, enmSource, vdmaVBVACtlSubmitSyncCompletion, &Data);
3213	if (RT_SUCCESS(rc))
3214	{
3215	rc = RTSemEventWait(Data.hEvent, RT_INDEFINITE_WAIT);
3216	if (RT_SUCCESS(rc))
3217	{
3218	rc = Data.rc;
3219	if (!RT_SUCCESS(rc))
3220	WARN(("vdmaVBVACtlSubmitSyncCompletion returned %d\n", rc));
3221	}
3222	else
3223	WARN(("RTSemEventWait failed %d\n", rc));
3224	}
3225	else
3226	Log(("vdmaVBVACtlSubmit failed %d\n", rc));
3227
3228	RTSemEventDestroy(Data.hEvent);
3229
3230	return rc;
3231	}
3232
3233	static int vdmaVBVAPause(PVBOXVDMAHOST pVdma)
3234	{
3235	VBVAEXHOSTCTL Ctl;
3236	Ctl.enmType = VBVAEXHOSTCTL_TYPE_HH_INTERNAL_PAUSE;
3237	return vdmaVBVACtlSubmitSync(pVdma, &Ctl, VBVAEXHOSTCTL_SOURCE_HOST);
3238	}
3239
3240	static int vdmaVBVAResume(PVBOXVDMAHOST pVdma)
3241	{
3242	VBVAEXHOSTCTL Ctl;
3243	Ctl.enmType = VBVAEXHOSTCTL_TYPE_HH_INTERNAL_RESUME;
3244	return vdmaVBVACtlSubmitSync(pVdma, &Ctl, VBVAEXHOSTCTL_SOURCE_HOST);
3245	}
3246
3247	static int vboxVDMACmdSubmitPerform(struct VBOXVDMAHOST *pVdma)
3248	{
3249	int rc = VBoxVBVAExHSCheckCommands(&pVdma->CmdVbva);
3250	switch (rc)
3251	{
3252	case VINF_SUCCESS:
3253	return VBoxVDMAThreadEventNotify(&pVdma->Thread);
3254	case VINF_ALREADY_INITIALIZED:
3255	case VINF_EOF:
3256	case VERR_INVALID_STATE:
3257	return VINF_SUCCESS;
3258	default:
3259	Assert(!RT_FAILURE(rc));
3260	return RT_FAILURE(rc) ? rc : VERR_INTERNAL_ERROR;
3261	}
3262	}
3263
3264
3265	int vboxCmdVBVACmdHostCtl(PPDMIDISPLAYVBVACALLBACKS pInterface,
3266	struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd,
3267	PFNCRCTLCOMPLETION pfnCompletion,
3268	void *pvCompletion)
3269	{
3270	PVGASTATE pVGAState = PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(pInterface);
3271	struct VBOXVDMAHOST *pVdma = pVGAState->pVdma;
3272	if (pVdma == NULL)
3273	return VERR_INVALID_STATE;
3274	pCmd->CalloutList.List.pNext = NULL;
3275	return vdmaVBVACtlOpaqueHostSubmit(pVdma, pCmd, cbCmd, pfnCompletion, pvCompletion);
3276	}
3277
3278	typedef struct VBOXCMDVBVA_CMDHOSTCTL_SYNC
3279	{
3280	struct VBOXVDMAHOST *pVdma;
3281	uint32_t fProcessing;
3282	int rc;
3283	} VBOXCMDVBVA_CMDHOSTCTL_SYNC;
3284
3285	static DECLCALLBACK(void) vboxCmdVBVACmdHostCtlSyncCb(struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd, int rc, void *pvCompletion)
3286	{
3287	RT_NOREF(pCmd, cbCmd);
3288	VBOXCMDVBVA_CMDHOSTCTL_SYNC pData = (VBOXCMDVBVA_CMDHOSTCTL_SYNC)pvCompletion;
3289
3290	pData->rc = rc;
3291
3292	struct VBOXVDMAHOST *pVdma = pData->pVdma;
3293
3294	ASMAtomicIncS32(&pVdma->i32cHostCrCtlCompleted);
3295
3296	pData->fProcessing = 0;
3297
3298	RTSemEventMultiSignal(pVdma->HostCrCtlCompleteEvent);
3299	}
3300
3301	static DECLCALLBACK(int) vboxCmdVBVACmdCallout(struct VBOXVDMAHOST pVdma, struct VBOXCRCMDCTL pCmd, VBOXCRCMDCTL_CALLOUT_LISTENTRY *pEntry, PFNVBOXCRCMDCTL_CALLOUT_CB pfnCb)
3302	{
3303	pEntry->pfnCb = pfnCb;
3304	int rc = RTCritSectEnter(&pVdma->CalloutCritSect);
3305	if (RT_SUCCESS(rc))
3306	{
3307	RTListAppend(&pCmd->CalloutList.List, &pEntry->Node);
3308	RTCritSectLeave(&pVdma->CalloutCritSect);
3309
3310	RTSemEventMultiSignal(pVdma->HostCrCtlCompleteEvent);
3311	}
3312	else
3313	WARN(("RTCritSectEnter failed %d\n", rc));
3314
3315	return rc;
3316	}
3317
3318
3319	static int vboxCmdVBVACmdCalloutProcess(struct VBOXVDMAHOST pVdma, struct VBOXCRCMDCTL pCmd)
3320	{
3321	int rc = VINF_SUCCESS;
3322	for (;;)
3323	{
3324	rc = RTCritSectEnter(&pVdma->CalloutCritSect);
3325	if (RT_SUCCESS(rc))
3326	{
3327	VBOXCRCMDCTL_CALLOUT_LISTENTRY* pEntry = RTListGetFirst(&pCmd->CalloutList.List, VBOXCRCMDCTL_CALLOUT_LISTENTRY, Node);
3328	if (pEntry)
3329	RTListNodeRemove(&pEntry->Node);
3330	RTCritSectLeave(&pVdma->CalloutCritSect);
3331
3332	if (!pEntry)
3333	break;
3334
3335	pEntry->pfnCb(pEntry);
3336	}
3337	else
3338	{
3339	WARN(("RTCritSectEnter failed %d\n", rc));
3340	break;
3341	}
3342	}
3343
3344	return rc;
3345	}
3346
3347	DECLCALLBACK(int) vboxCmdVBVACmdHostCtlSync(PPDMIDISPLAYVBVACALLBACKS pInterface,
3348	struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd)
3349	{
3350	PVGASTATE pVGAState = PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(pInterface);
3351	struct VBOXVDMAHOST *pVdma = pVGAState->pVdma;
3352	if (pVdma == NULL)
3353	return VERR_INVALID_STATE;
3354	VBOXCMDVBVA_CMDHOSTCTL_SYNC Data;
3355	Data.pVdma = pVdma;
3356	Data.fProcessing = 1;
3357	Data.rc = VERR_INTERNAL_ERROR;
3358	RTListInit(&pCmd->CalloutList.List);
3359	int rc = vdmaVBVACtlOpaqueHostSubmit(pVdma, pCmd, cbCmd, vboxCmdVBVACmdHostCtlSyncCb, &Data);
3360	if (!RT_SUCCESS(rc))
3361	{
3362	WARN(("vdmaVBVACtlOpaqueHostSubmit failed %d", rc));
3363	return rc;
3364	}
3365
3366	while (Data.fProcessing)
3367	{
3368	/* Poll infrequently to make sure no completed message has been missed. */
3369	RTSemEventMultiWait(pVdma->HostCrCtlCompleteEvent, 500);
3370
3371	vboxCmdVBVACmdCalloutProcess(pVdma, pCmd);
3372
3373	if (Data.fProcessing)
3374	RTThreadYield();
3375	}
3376
3377	/* extra check callouts */
3378	vboxCmdVBVACmdCalloutProcess(pVdma, pCmd);
3379
3380	/* 'Our' message has been processed, so should reset the semaphore.
3381	* There is still possible that another message has been processed
3382	* and the semaphore has been signalled again.
3383	* Reset only if there are no other messages completed.
3384	*/
3385	int32_t c = ASMAtomicDecS32(&pVdma->i32cHostCrCtlCompleted);
3386	Assert(c >= 0);
3387	if (!c)
3388	RTSemEventMultiReset(pVdma->HostCrCtlCompleteEvent);
3389
3390	rc = Data.rc;
3391	if (!RT_SUCCESS(rc))
3392	WARN(("host call failed %d", rc));
3393
3394	return rc;
3395	}
3396
3397	int vboxCmdVBVACmdCtl(PVGASTATE pVGAState, VBOXCMDVBVA_CTL *pCtl, uint32_t cbCtl)
3398	{
3399	struct VBOXVDMAHOST *pVdma = pVGAState->pVdma;
3400	int rc = VINF_SUCCESS;
3401	switch (pCtl->u32Type)
3402	{
3403	case VBOXCMDVBVACTL_TYPE_3DCTL:
3404	return vdmaVBVACtlGenericGuestSubmit(pVdma, VBVAEXHOSTCTL_TYPE_GHH_BE_OPAQUE, pCtl, cbCtl);
3405	case VBOXCMDVBVACTL_TYPE_RESIZE:
3406	return vdmaVBVACtlGenericGuestSubmit(pVdma, VBVAEXHOSTCTL_TYPE_GHH_RESIZE, pCtl, cbCtl);
3407	case VBOXCMDVBVACTL_TYPE_ENABLE:
3408	if (cbCtl != sizeof (VBOXCMDVBVA_CTL_ENABLE))
3409	{
3410	WARN(("incorrect enable size\n"));
3411	rc = VERR_INVALID_PARAMETER;
3412	break;
3413	}
3414	return vdmaVBVACtlEnableDisableSubmit(pVdma, (VBOXCMDVBVA_CTL_ENABLE*)pCtl);
3415	default:
3416	WARN(("unsupported type\n"));
3417	rc = VERR_INVALID_PARAMETER;
3418	break;
3419	}
3420
3421	pCtl->i32Result = rc;
3422	rc = VBoxSHGSMICommandComplete(pVdma->pHgsmi, pCtl);
3423	AssertRC(rc);
3424	return VINF_SUCCESS;
3425	}
3426
3427	int vboxCmdVBVACmdSubmit(PVGASTATE pVGAState)
3428	{
3429	if (!VBoxVBVAExHSIsEnabled(&pVGAState->pVdma->CmdVbva))
3430	{
3431	WARN(("vdma VBVA is disabled\n"));
3432	return VERR_INVALID_STATE;
3433	}
3434
3435	return vboxVDMACmdSubmitPerform(pVGAState->pVdma);
3436	}
3437
3438	int vboxCmdVBVACmdFlush(PVGASTATE pVGAState)
3439	{
3440	WARN(("flush\n"));
3441	if (!VBoxVBVAExHSIsEnabled(&pVGAState->pVdma->CmdVbva))
3442	{
3443	WARN(("vdma VBVA is disabled\n"));
3444	return VERR_INVALID_STATE;
3445	}
3446	return vboxVDMACmdSubmitPerform(pVGAState->pVdma);
3447	}
3448
3449	void vboxCmdVBVACmdTimer(PVGASTATE pVGAState)
3450	{
3451	if (!VBoxVBVAExHSIsEnabled(&pVGAState->pVdma->CmdVbva))
3452	return;
3453	vboxVDMACmdSubmitPerform(pVGAState->pVdma);
3454	}
3455
3456	bool vboxCmdVBVAIsEnabled(PVGASTATE pVGAState)
3457	{
3458	return VBoxVBVAExHSIsEnabled(&pVGAState->pVdma->CmdVbva);
3459	}
3460
3461	#endif /* VBOX_WITH_CRHGSMI */
3462
3463	int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma)
3464	{
3465	#ifdef VBOX_WITH_CRHGSMI
3466	int rc = vdmaVBVAPause(pVdma);
3467	if (RT_SUCCESS(rc))
3468	return VINF_SUCCESS;
3469
3470	if (rc != VERR_INVALID_STATE)
3471	{
3472	WARN(("vdmaVBVAPause failed %d\n", rc));
3473	return rc;
3474	}
3475
3476	# ifdef DEBUG_misha
3477	WARN(("debug prep"));
3478	# endif
3479
3480	PVGASTATE pVGAState = pVdma->pVGAState;
3481	PVBOXVDMACMD_CHROMIUM_CTL pCmd = (PVBOXVDMACMD_CHROMIUM_CTL)vboxVDMACrCtlCreate(
3482	VBOXVDMACMD_CHROMIUM_CTL_TYPE_SAVESTATE_BEGIN, sizeof (*pCmd));
3483	Assert(pCmd);
3484	if (pCmd)
3485	{
3486	rc = vboxVDMACrCtlPost(pVGAState, pCmd, sizeof (*pCmd));
3487	AssertRC(rc);
3488	if (RT_SUCCESS(rc))
3489	{
3490	rc = vboxVDMACrCtlGetRc(pCmd);
3491	}
3492	vboxVDMACrCtlRelease(pCmd);
3493	return rc;
3494	}
3495	return VERR_NO_MEMORY;
3496	#else
3497	RT_NOREF(pVdma);
3498	return VINF_SUCCESS;
3499	#endif
3500	}
3501
3502	int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma)
3503	{
3504	#ifdef VBOX_WITH_CRHGSMI
3505	int rc = vdmaVBVAResume(pVdma);
3506	if (RT_SUCCESS(rc))
3507	return VINF_SUCCESS;
3508
3509	if (rc != VERR_INVALID_STATE)
3510	{
3511	WARN(("vdmaVBVAResume failed %d\n", rc));
3512	return rc;
3513	}
3514
3515	# ifdef DEBUG_misha
3516	WARN(("debug done"));
3517	# endif
3518
3519	PVGASTATE pVGAState = pVdma->pVGAState;
3520	PVBOXVDMACMD_CHROMIUM_CTL pCmd = (PVBOXVDMACMD_CHROMIUM_CTL)vboxVDMACrCtlCreate(
3521	VBOXVDMACMD_CHROMIUM_CTL_TYPE_SAVESTATE_END, sizeof (*pCmd));
3522	Assert(pCmd);
3523	if (pCmd)
3524	{
3525	rc = vboxVDMACrCtlPost(pVGAState, pCmd, sizeof (*pCmd));
3526	AssertRC(rc);
3527	if (RT_SUCCESS(rc))
3528	{
3529	rc = vboxVDMACrCtlGetRc(pCmd);
3530	}
3531	vboxVDMACrCtlRelease(pCmd);
3532	return rc;
3533	}
3534	return VERR_NO_MEMORY;
3535	#else
3536	RT_NOREF(pVdma);
3537	return VINF_SUCCESS;
3538	#endif
3539	}
3540
3541	int vboxVDMASaveStateExecPerform(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM)
3542	{
3543	int rc;
3544	#ifndef VBOX_WITH_CRHGSMI
3545	RT_NOREF(pVdma, pSSM);
3546
3547	#else
3548	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
3549	#endif
3550	{
3551	rc = SSMR3PutU32(pSSM, UINT32_MAX);
3552	AssertRCReturn(rc, rc);
3553	return VINF_SUCCESS;
3554	}
3555
3556	#ifdef VBOX_WITH_CRHGSMI
3557	PVGASTATE pVGAState = pVdma->pVGAState;
3558	uint8_t * pu8VramBase = pVGAState->vram_ptrR3;
3559
3560	rc = SSMR3PutU32(pSSM, (uint32_t)(((uint8_t*)pVdma->CmdVbva.pVBVA) - pu8VramBase));
3561	AssertRCReturn(rc, rc);
3562
3563	VBVAEXHOSTCTL HCtl;
3564	HCtl.enmType = VBVAEXHOSTCTL_TYPE_HH_SAVESTATE;
3565	HCtl.u.state.pSSM = pSSM;
3566	HCtl.u.state.u32Version = 0;
3567	return vdmaVBVACtlSubmitSync(pVdma, &HCtl, VBVAEXHOSTCTL_SOURCE_HOST);
3568	#endif
3569	}
3570
3571	int vboxVDMASaveLoadExecPerform(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM, uint32_t u32Version)
3572	{
3573	uint32_t u32;
3574	int rc = SSMR3GetU32(pSSM, &u32);
3575	AssertLogRelRCReturn(rc, rc);
3576
3577	if (u32 != UINT32_MAX)
3578	{
3579	#ifdef VBOX_WITH_CRHGSMI
3580	rc = vdmaVBVACtlEnableSubmitSync(pVdma, u32, true);
3581	AssertLogRelRCReturn(rc, rc);
3582
3583	Assert(pVdma->CmdVbva.i32State == VBVAEXHOSTCONTEXT_ESTATE_PAUSED);
3584
3585	VBVAEXHOSTCTL HCtl;
3586	HCtl.enmType = VBVAEXHOSTCTL_TYPE_HH_LOADSTATE;
3587	HCtl.u.state.pSSM = pSSM;
3588	HCtl.u.state.u32Version = u32Version;
3589	rc = vdmaVBVACtlSubmitSync(pVdma, &HCtl, VBVAEXHOSTCTL_SOURCE_HOST);
3590	AssertLogRelRCReturn(rc, rc);
3591
3592	rc = vdmaVBVAResume(pVdma);
3593	AssertLogRelRCReturn(rc, rc);
3594
3595	return VINF_SUCCESS;
3596	#else
3597	RT_NOREF(pVdma, u32Version);
3598	WARN(("Unsupported VBVACtl info!\n"));
3599	return VERR_VERSION_MISMATCH;
3600	#endif
3601	}
3602
3603	return VINF_SUCCESS;
3604	}
3605
3606	int vboxVDMASaveLoadDone(struct VBOXVDMAHOST *pVdma)
3607	{
3608	#ifdef VBOX_WITH_CRHGSMI
3609	if (!VBoxVBVAExHSIsEnabled(&pVdma->CmdVbva))
3610	return VINF_SUCCESS;
3611
3612	/** @todo r=bird: BTW. would be great if you put in a couple of comments here and there explaining what
3613	* the purpose of this code is. */
3614	VBVAEXHOSTCTL* pHCtl = VBoxVBVAExHCtlCreate(&pVdma->CmdVbva, VBVAEXHOSTCTL_TYPE_HH_LOADSTATE_DONE);
3615	if (!pHCtl)
3616	{
3617	WARN(("VBoxVBVAExHCtlCreate failed\n"));
3618	return VERR_NO_MEMORY;
3619	}
3620
3621	/* sanity */
3622	pHCtl->u.cmd.pu8Cmd = NULL;
3623	pHCtl->u.cmd.cbCmd = 0;
3624
3625	/* NULL completion will just free the ctl up */
3626	int rc = vdmaVBVACtlSubmit(pVdma, pHCtl, VBVAEXHOSTCTL_SOURCE_HOST, NULL, NULL);
3627	if (RT_FAILURE(rc))
3628	{
3629	Log(("vdmaVBVACtlSubmit failed rc %d\n", rc));
3630	VBoxVBVAExHCtlFree(&pVdma->CmdVbva, pHCtl);
3631	return rc;
3632	}
3633	#else
3634	RT_NOREF(pVdma);
3635	#endif
3636	return VINF_SUCCESS;
3637	}
3638

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source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA_VDMA.cpp@ 69498

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