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source: vbox/trunk/src/VBox/Devices/Graphics/shaderlib/wine/include/cvconst.h@ 53206

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Devices/vmsvga: header fixes
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1/*
2 * File cvconst.h - MS debug information
3 *
4 * Copyright (C) 2004, Eric Pouech
5 * Copyright (C) 2012, André Hentschel
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22/*
23 * Oracle LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
24 * other than GPL or LGPL is available it will apply instead, Oracle elects to use only
25 * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
26 * a choice of LGPL license versions is made available with the language indicating
27 * that LGPLv2 or any later version may be used, or where a choice of which version
28 * of the LGPL is applied is otherwise unspecified.
29 */
30
31/* information in this file is highly derived from MSDN DIA information pages */
32
33/* symbols & types enumeration */
34enum SymTagEnum
35{
36 SymTagNull,
37 SymTagExe,
38 SymTagCompiland,
39 SymTagCompilandDetails,
40 SymTagCompilandEnv,
41 SymTagFunction,
42 SymTagBlock,
43 SymTagData,
44 SymTagAnnotation,
45 SymTagLabel,
46 SymTagPublicSymbol,
47 SymTagUDT,
48 SymTagEnum,
49 SymTagFunctionType,
50 SymTagPointerType,
51 SymTagArrayType,
52 SymTagBaseType,
53 SymTagTypedef,
54 SymTagBaseClass,
55 SymTagFriend,
56 SymTagFunctionArgType,
57 SymTagFuncDebugStart,
58 SymTagFuncDebugEnd,
59 SymTagUsingNamespace,
60 SymTagVTableShape,
61 SymTagVTable,
62 SymTagCustom,
63 SymTagThunk,
64 SymTagCustomType,
65 SymTagManagedType,
66 SymTagDimension,
67 SymTagMax
68};
69
70enum BasicType
71{
72 btNoType = 0,
73 btVoid = 1,
74 btChar = 2,
75 btWChar = 3,
76 btInt = 6,
77 btUInt = 7,
78 btFloat = 8,
79 btBCD = 9,
80 btBool = 10,
81 btLong = 13,
82 btULong = 14,
83 btCurrency = 25,
84 btDate = 26,
85 btVariant = 27,
86 btComplex = 28,
87 btBit = 29,
88 btBSTR = 30,
89 btHresult = 31,
90};
91
92/* kind of UDT */
93enum UdtKind
94{
95 UdtStruct,
96 UdtClass,
97 UdtUnion
98};
99
100/* where a SymTagData is */
101enum LocationType
102{
103 LocIsNull,
104 LocIsStatic,
105 LocIsTLS,
106 LocIsRegRel,
107 LocIsThisRel,
108 LocIsEnregistered,
109 LocIsBitField,
110 LocIsSlot,
111 LocIsIlRel,
112 LocInMetaData,
113 LocIsConstant
114};
115
116/* kind of SymTagData */
117enum DataKind
118{
119 DataIsUnknown,
120 DataIsLocal,
121 DataIsStaticLocal,
122 DataIsParam,
123 DataIsObjectPtr,
124 DataIsFileStatic,
125 DataIsGlobal,
126 DataIsMember,
127 DataIsStaticMember,
128 DataIsConstant
129};
130
131/* values for registers (on different CPUs) */
132enum CV_HREG_e
133{
134 /* those values are common to all supported CPUs (and CPU independent) */
135 CV_ALLREG_ERR = 30000,
136 CV_ALLREG_TEB = 30001,
137 CV_ALLREG_TIMER = 30002,
138 CV_ALLREG_EFAD1 = 30003,
139 CV_ALLREG_EFAD2 = 30004,
140 CV_ALLREG_EFAD3 = 30005,
141 CV_ALLREG_VFRAME = 30006,
142 CV_ALLREG_HANDLE = 30007,
143 CV_ALLREG_PARAMS = 30008,
144 CV_ALLREG_LOCALS = 30009,
145 CV_ALLREG_TID = 30010,
146 CV_ALLREG_ENV = 30011,
147 CV_ALLREG_CMDLN = 30012,
148
149 /* Intel x86 CPU */
150 CV_REG_NONE = 0,
151 CV_REG_AL = 1,
152 CV_REG_CL = 2,
153 CV_REG_DL = 3,
154 CV_REG_BL = 4,
155 CV_REG_AH = 5,
156 CV_REG_CH = 6,
157 CV_REG_DH = 7,
158 CV_REG_BH = 8,
159 CV_REG_AX = 9,
160 CV_REG_CX = 10,
161 CV_REG_DX = 11,
162 CV_REG_BX = 12,
163 CV_REG_SP = 13,
164 CV_REG_BP = 14,
165 CV_REG_SI = 15,
166 CV_REG_DI = 16,
167 CV_REG_EAX = 17,
168 CV_REG_ECX = 18,
169 CV_REG_EDX = 19,
170 CV_REG_EBX = 20,
171 CV_REG_ESP = 21,
172 CV_REG_EBP = 22,
173 CV_REG_ESI = 23,
174 CV_REG_EDI = 24,
175 CV_REG_ES = 25,
176 CV_REG_CS = 26,
177 CV_REG_SS = 27,
178 CV_REG_DS = 28,
179 CV_REG_FS = 29,
180 CV_REG_GS = 30,
181 CV_REG_IP = 31,
182 CV_REG_FLAGS = 32,
183 CV_REG_EIP = 33,
184 CV_REG_EFLAGS = 34,
185
186 /* <pcode> */
187 CV_REG_TEMP = 40,
188 CV_REG_TEMPH = 41,
189 CV_REG_QUOTE = 42,
190 CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */
191 CV_REG_CR0 = 80, /* this includes CR1 to CR4 */
192 CV_REG_DR0 = 90, /* this includes DR1 to DR7 */
193 /* </pcode> */
194
195 CV_REG_GDTR = 110,
196 CV_REG_GDTL = 111,
197 CV_REG_IDTR = 112,
198 CV_REG_IDTL = 113,
199 CV_REG_LDTR = 114,
200 CV_REG_TR = 115,
201
202 CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */
203 CV_REG_ST0 = 128, /* this includes ST1 to ST7 */
204 CV_REG_CTRL = 136,
205 CV_REG_STAT = 137,
206 CV_REG_TAG = 138,
207 CV_REG_FPIP = 139,
208 CV_REG_FPCS = 140,
209 CV_REG_FPDO = 141,
210 CV_REG_FPDS = 142,
211 CV_REG_ISEM = 143,
212 CV_REG_FPEIP = 144,
213 CV_REG_FPEDO = 145,
214 CV_REG_MM0 = 146, /* this includes MM1 to MM7 */
215 CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */
216 CV_REG_XMM00 = 162,
217 CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */
218 CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */
219 CV_REG_MXCSR = 211,
220 CV_REG_EDXEAX = 212,
221 CV_REG_EMM0L = 220,
222 CV_REG_EMM0H = 228,
223 CV_REG_MM00 = 236,
224 CV_REG_MM01 = 237,
225 CV_REG_MM10 = 238,
226 CV_REG_MM11 = 239,
227 CV_REG_MM20 = 240,
228 CV_REG_MM21 = 241,
229 CV_REG_MM30 = 242,
230 CV_REG_MM31 = 243,
231 CV_REG_MM40 = 244,
232 CV_REG_MM41 = 245,
233 CV_REG_MM50 = 246,
234 CV_REG_MM51 = 247,
235 CV_REG_MM60 = 248,
236 CV_REG_MM61 = 249,
237 CV_REG_MM70 = 250,
238 CV_REG_MM71 = 251,
239
240 CV_REG_YMM0 = 252, /* this includes YMM1 to YMM7 */
241 CV_REG_YMM0H = 260, /* this includes YMM1H to YMM7H */
242 CV_REG_YMM0I0 = 268, /* this includes YMM0I1 to YMM0I3 */
243 CV_REG_YMM1I0 = 272, /* this includes YMM1I1 to YMM1I3 */
244 CV_REG_YMM2I0 = 276, /* this includes YMM2I1 to YMM2I3 */
245 CV_REG_YMM3I0 = 280, /* this includes YMM3I1 to YMM3I3 */
246 CV_REG_YMM4I0 = 284, /* this includes YMM4I1 to YMM4I3 */
247 CV_REG_YMM5I0 = 288, /* this includes YMM5I1 to YMM5I3 */
248 CV_REG_YMM6I0 = 292, /* this includes YMM6I1 to YMM6I3 */
249 CV_REG_YMM7I0 = 296, /* this includes YMM7I1 to YMM7I3 */
250 CV_REG_YMM0F0 = 300, /* this includes YMM0F1 to YMM0F7 */
251 CV_REG_YMM1F0 = 308, /* this includes YMM1F1 to YMM1F7 */
252 CV_REG_YMM2F0 = 316, /* this includes YMM2F1 to YMM2F7 */
253 CV_REG_YMM3F0 = 324, /* this includes YMM3F1 to YMM3F7 */
254 CV_REG_YMM4F0 = 332, /* this includes YMM4F1 to YMM4F7 */
255 CV_REG_YMM5F0 = 340, /* this includes YMM5F1 to YMM5F7 */
256 CV_REG_YMM6F0 = 348, /* this includes YMM6F1 to YMM6F7 */
257 CV_REG_YMM7F0 = 356, /* this includes YMM7F1 to YMM7F7 */
258 CV_REG_YMM0D0 = 364, /* this includes YMM0D1 to YMM0D3 */
259 CV_REG_YMM1D0 = 368, /* this includes YMM1D1 to YMM1D3 */
260 CV_REG_YMM2D0 = 372, /* this includes YMM2D1 to YMM2D3 */
261 CV_REG_YMM3D0 = 376, /* this includes YMM3D1 to YMM3D3 */
262 CV_REG_YMM4D0 = 380, /* this includes YMM4D1 to YMM4D3 */
263 CV_REG_YMM5D0 = 384, /* this includes YMM5D1 to YMM5D3 */
264 CV_REG_YMM6D0 = 388, /* this includes YMM6D1 to YMM6D3 */
265 CV_REG_YMM7D0 = 392, /* this includes YMM7D1 to YMM7D3 */
266
267 /* Motorola 68K CPU */
268 CV_R68_D0 = 0, /* this includes D1 to D7 too */
269 CV_R68_A0 = 8, /* this includes A1 to A7 too */
270 CV_R68_CCR = 16,
271 CV_R68_SR = 17,
272 CV_R68_USP = 18,
273 CV_R68_MSP = 19,
274 CV_R68_SFC = 20,
275 CV_R68_DFC = 21,
276 CV_R68_CACR = 22,
277 CV_R68_VBR = 23,
278 CV_R68_CAAR = 24,
279 CV_R68_ISP = 25,
280 CV_R68_PC = 26,
281 CV_R68_FPCR = 28,
282 CV_R68_FPSR = 29,
283 CV_R68_FPIAR = 30,
284 CV_R68_FP0 = 32, /* this includes FP1 to FP7 */
285 CV_R68_MMUSR030 = 41,
286 CV_R68_MMUSR = 42,
287 CV_R68_URP = 43,
288 CV_R68_DTT0 = 44,
289 CV_R68_DTT1 = 45,
290 CV_R68_ITT0 = 46,
291 CV_R68_ITT1 = 47,
292 CV_R68_PSR = 51,
293 CV_R68_PCSR = 52,
294 CV_R68_VAL = 53,
295 CV_R68_CRP = 54,
296 CV_R68_SRP = 55,
297 CV_R68_DRP = 56,
298 CV_R68_TC = 57,
299 CV_R68_AC = 58,
300 CV_R68_SCC = 59,
301 CV_R68_CAL = 60,
302 CV_R68_TT0 = 61,
303 CV_R68_TT1 = 62,
304 CV_R68_BAD0 = 64, /* this includes BAD1 to BAD7 */
305 CV_R68_BAC0 = 72, /* this includes BAC1 to BAC7 */
306
307 /* MIPS 4000 CPU */
308 CV_M4_NOREG = CV_REG_NONE,
309 CV_M4_IntZERO = 10,
310 CV_M4_IntAT = 11,
311 CV_M4_IntV0 = 12,
312 CV_M4_IntV1 = 13,
313 CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */
314 CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */
315 CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */
316 CV_M4_IntT8 = 34,
317 CV_M4_IntT9 = 35,
318 CV_M4_IntKT0 = 36,
319 CV_M4_IntKT1 = 37,
320 CV_M4_IntGP = 38,
321 CV_M4_IntSP = 39,
322 CV_M4_IntS8 = 40,
323 CV_M4_IntRA = 41,
324 CV_M4_IntLO = 42,
325 CV_M4_IntHI = 43,
326 CV_M4_Fir = 50,
327 CV_M4_Psr = 51,
328 CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */
329 CV_M4_FltFsr = 92,
330
331 /* Alpha AXP CPU */
332 CV_ALPHA_NOREG = CV_REG_NONE,
333 CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */
334 CV_ALPHA_IntV0 = 42,
335 CV_ALPHA_IntT0 = 43, /* this includes T1 to T7 */
336 CV_ALPHA_IntS0 = 51, /* this includes S1 to S5 */
337 CV_ALPHA_IntFP = 57,
338 CV_ALPHA_IntA0 = 58, /* this includes A1 to A5 */
339 CV_ALPHA_IntT8 = 64,
340 CV_ALPHA_IntT9 = 65,
341 CV_ALPHA_IntT10 = 66,
342 CV_ALPHA_IntT11 = 67,
343 CV_ALPHA_IntRA = 68,
344 CV_ALPHA_IntT12 = 69,
345 CV_ALPHA_IntAT = 70,
346 CV_ALPHA_IntGP = 71,
347 CV_ALPHA_IntSP = 72,
348 CV_ALPHA_IntZERO = 73,
349 CV_ALPHA_Fpcr = 74,
350 CV_ALPHA_Fir = 75,
351 CV_ALPHA_Psr = 76,
352 CV_ALPHA_FltFsr = 77,
353 CV_ALPHA_SoftFpcr = 78,
354
355 /* Motorola & IBM PowerPC CPU */
356 CV_PPC_GPR0 = 1, /* this includes GPR1 to GPR31 */
357 CV_PPC_CR = 33,
358 CV_PPC_CR0 = 34, /* this includes CR1 to CR7 */
359 CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */
360
361 CV_PPC_FPSCR = 74,
362 CV_PPC_MSR = 75,
363 CV_PPC_SR0 = 76, /* this includes SR1 to SR15 */
364 CV_PPC_PC = 99,
365 CV_PPC_MQ = 100,
366 CV_PPC_XER = 101,
367 CV_PPC_RTCU = 104,
368 CV_PPC_RTCL = 105,
369 CV_PPC_LR = 108,
370 CV_PPC_CTR = 109,
371 CV_PPC_COMPARE = 110,
372 CV_PPC_COUNT = 111,
373 CV_PPC_DSISR = 118,
374 CV_PPC_DAR = 119,
375 CV_PPC_DEC = 122,
376 CV_PPC_SDR1 = 125,
377 CV_PPC_SRR0 = 126,
378 CV_PPC_SRR1 = 127,
379 CV_PPC_SPRG0 = 372, /* this includes SPRG1 to SPRG3 */
380 CV_PPC_ASR = 280,
381 CV_PPC_EAR = 382,
382 CV_PPC_PVR = 287,
383 CV_PPC_BAT0U = 628,
384 CV_PPC_BAT0L = 629,
385 CV_PPC_BAT1U = 630,
386 CV_PPC_BAT1L = 631,
387 CV_PPC_BAT2U = 632,
388 CV_PPC_BAT2L = 633,
389 CV_PPC_BAT3U = 634,
390 CV_PPC_BAT3L = 635,
391 CV_PPC_DBAT0U = 636,
392 CV_PPC_DBAT0L = 637,
393 CV_PPC_DBAT1U = 638,
394 CV_PPC_DBAT1L = 639,
395 CV_PPC_DBAT2U = 640,
396 CV_PPC_DBAT2L = 641,
397 CV_PPC_DBAT3U = 642,
398 CV_PPC_DBAT3L = 643,
399 CV_PPC_PMR0 = 1044, /* this includes PMR1 to PMR15 */
400 CV_PPC_DMISS = 1076,
401 CV_PPC_DCMP = 1077,
402 CV_PPC_HASH1 = 1078,
403 CV_PPC_HASH2 = 1079,
404 CV_PPC_IMISS = 1080,
405 CV_PPC_ICMP = 1081,
406 CV_PPC_RPA = 1082,
407 CV_PPC_HID0 = 1108, /* this includes HID1 to HID15 */
408
409 /* Java */
410 CV_JAVA_PC = 1,
411
412 /* Hitachi SH3 CPU */
413 CV_SH3_NOREG = CV_REG_NONE,
414 CV_SH3_IntR0 = 10, /* this include R1 to R13 */
415 CV_SH3_IntFp = 24,
416 CV_SH3_IntSp = 25,
417 CV_SH3_Gbr = 38,
418 CV_SH3_Pr = 39,
419 CV_SH3_Mach = 40,
420 CV_SH3_Macl = 41,
421 CV_SH3_Pc = 50,
422 CV_SH3_Sr = 51,
423 CV_SH3_BarA = 60,
424 CV_SH3_BasrA = 61,
425 CV_SH3_BamrA = 62,
426 CV_SH3_BbrA = 63,
427 CV_SH3_BarB = 64,
428 CV_SH3_BasrB = 65,
429 CV_SH3_BamrB = 66,
430 CV_SH3_BbrB = 67,
431 CV_SH3_BdrB = 68,
432 CV_SH3_BdmrB = 69,
433 CV_SH3_Brcr = 70,
434 CV_SH_Fpscr = 75,
435 CV_SH_Fpul = 76,
436 CV_SH_FpR0 = 80, /* this includes FpR1 to FpR15 */
437 CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */
438
439 /* ARM CPU */
440 CV_ARM_NOREG = CV_REG_NONE,
441 CV_ARM_R0 = 10, /* this includes R1 to R12 */
442 CV_ARM_SP = 23,
443 CV_ARM_LR = 24,
444 CV_ARM_PC = 25,
445 CV_ARM_CPSR = 26,
446 CV_ARM_ACC0 = 27,
447 CV_ARM_FPSCR = 40,
448 CV_ARM_FPEXC = 41,
449 CV_ARM_FS0 = 50, /* this includes FS1 to FS31 */
450 CV_ARM_FPEXTRA0 = 90, /* this includes FPEXTRA1 to FPEXTRA7 */
451 CV_ARM_WR0 = 128, /* this includes WR1 to WR15 */
452 CV_ARM_WCID = 144,
453 CV_ARM_WCON = 145,
454 CV_ARM_WCSSF = 146,
455 CV_ARM_WCASF = 147,
456 CV_ARM_WC4 = 148,
457 CV_ARM_WC5 = 149,
458 CV_ARM_WC6 = 150,
459 CV_ARM_WC7 = 151,
460 CV_ARM_WCGR0 = 152, /* this includes WCGR1 to WCGR3 */
461 CV_ARM_WC12 = 156,
462 CV_ARM_WC13 = 157,
463 CV_ARM_WC14 = 158,
464 CV_ARM_WC15 = 159,
465 CV_ARM_FS32 = 200, /* this includes FS33 to FS63 */
466 CV_ARM_ND0 = 300, /* this includes ND1 to ND31 */
467 CV_ARM_NQ0 = 400, /* this includes NQ1 to NQ15 */
468
469 /* Intel IA64 CPU */
470 CV_IA64_NOREG = CV_REG_NONE,
471 CV_IA64_Br0 = 512, /* this includes Br1 to Br7 */
472 CV_IA64_P0 = 704, /* this includes P1 to P63 */
473 CV_IA64_Preds = 768,
474 CV_IA64_IntH0 = 832, /* this includes H1 to H15 */
475 CV_IA64_Ip = 1016,
476 CV_IA64_Umask = 1017,
477 CV_IA64_Cfm = 1018,
478 CV_IA64_Psr = 1019,
479 CV_IA64_Nats = 1020,
480 CV_IA64_Nats2 = 1021,
481 CV_IA64_Nats3 = 1022,
482 CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */
483 CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */
484 /* some IA64 registers missing */
485
486 /* TriCore CPU */
487 CV_TRI_NOREG = CV_REG_NONE,
488 CV_TRI_D0 = 10, /* includes D1 to D15 */
489 CV_TRI_A0 = 26, /* includes A1 to A15 */
490 CV_TRI_E0 = 42,
491 CV_TRI_E2 = 43,
492 CV_TRI_E4 = 44,
493 CV_TRI_E6 = 45,
494 CV_TRI_E8 = 46,
495 CV_TRI_E10 = 47,
496 CV_TRI_E12 = 48,
497 CV_TRI_E14 = 49,
498 CV_TRI_EA0 = 50,
499 CV_TRI_EA2 = 51,
500 CV_TRI_EA4 = 52,
501 CV_TRI_EA6 = 53,
502 CV_TRI_EA8 = 54,
503 CV_TRI_EA10 = 55,
504 CV_TRI_EA12 = 56,
505 CV_TRI_EA14 = 57,
506 CV_TRI_PSW = 58,
507 CV_TRI_PCXI = 59,
508 CV_TRI_PC = 60,
509 CV_TRI_FCX = 61,
510 CV_TRI_LCX = 62,
511 CV_TRI_ISP = 63,
512 CV_TRI_ICR = 64,
513 CV_TRI_BIV = 65,
514 CV_TRI_BTV = 66,
515 CV_TRI_SYSCON = 67,
516 CV_TRI_DPRx_0 = 68, /* includes DPRx_1 to DPRx_3 */
517 CV_TRI_CPRx_0 = 68, /* includes CPRx_1 to CPRx_3 */
518 CV_TRI_DPMx_0 = 68, /* includes DPMx_1 to DPMx_3 */
519 CV_TRI_CPMx_0 = 68, /* includes CPMx_1 to CPMx_3 */
520 CV_TRI_DBGSSR = 72,
521 CV_TRI_EXEVT = 73,
522 CV_TRI_SWEVT = 74,
523 CV_TRI_CREVT = 75,
524 CV_TRI_TRnEVT = 76,
525 CV_TRI_MMUCON = 77,
526 CV_TRI_ASI = 78,
527 CV_TRI_TVA = 79,
528 CV_TRI_TPA = 80,
529 CV_TRI_TPX = 81,
530 CV_TRI_TFA = 82,
531
532 /* AM33 (and the likes) CPU */
533 CV_AM33_NOREG = CV_REG_NONE,
534 CV_AM33_E0 = 10, /* this includes E1 to E7 */
535 CV_AM33_A0 = 20, /* this includes A1 to A3 */
536 CV_AM33_D0 = 30, /* this includes D1 to D3 */
537 CV_AM33_FS0 = 40, /* this includes FS1 to FS31 */
538 CV_AM33_SP = 80,
539 CV_AM33_PC = 81,
540 CV_AM33_MDR = 82,
541 CV_AM33_MDRQ = 83,
542 CV_AM33_MCRH = 84,
543 CV_AM33_MCRL = 85,
544 CV_AM33_MCVF = 86,
545 CV_AM33_EPSW = 87,
546 CV_AM33_FPCR = 88,
547 CV_AM33_LIR = 89,
548 CV_AM33_LAR = 90,
549
550 /* Mitsubishi M32R CPU */
551 CV_M32R_NOREG = CV_REG_NONE,
552 CV_M32R_R0 = 10, /* this includes R1 to R11 */
553 CV_M32R_R12 = 22,
554 CV_M32R_R13 = 23,
555 CV_M32R_R14 = 24,
556 CV_M32R_R15 = 25,
557 CV_M32R_PSW = 26,
558 CV_M32R_CBR = 27,
559 CV_M32R_SPI = 28,
560 CV_M32R_SPU = 29,
561 CV_M32R_SPO = 30,
562 CV_M32R_BPC = 31,
563 CV_M32R_ACHI = 32,
564 CV_M32R_ACLO = 33,
565 CV_M32R_PC = 34,
566
567 /* AMD/Intel x86_64 CPU */
568 CV_AMD64_NONE = CV_REG_NONE,
569 CV_AMD64_AL = CV_REG_AL,
570 CV_AMD64_CL = CV_REG_CL,
571 CV_AMD64_DL = CV_REG_DL,
572 CV_AMD64_BL = CV_REG_BL,
573 CV_AMD64_AH = CV_REG_AH,
574 CV_AMD64_CH = CV_REG_CH,
575 CV_AMD64_DH = CV_REG_DH,
576 CV_AMD64_BH = CV_REG_BH,
577 CV_AMD64_AX = CV_REG_AX,
578 CV_AMD64_CX = CV_REG_CX,
579 CV_AMD64_DX = CV_REG_DX,
580 CV_AMD64_BX = CV_REG_BX,
581 CV_AMD64_SP = CV_REG_SP,
582 CV_AMD64_BP = CV_REG_BP,
583 CV_AMD64_SI = CV_REG_SI,
584 CV_AMD64_DI = CV_REG_DI,
585 CV_AMD64_EAX = CV_REG_EAX,
586 CV_AMD64_ECX = CV_REG_ECX,
587 CV_AMD64_EDX = CV_REG_EDX,
588 CV_AMD64_EBX = CV_REG_EBX,
589 CV_AMD64_ESP = CV_REG_ESP,
590 CV_AMD64_EBP = CV_REG_EBP,
591 CV_AMD64_ESI = CV_REG_ESI,
592 CV_AMD64_EDI = CV_REG_EDI,
593 CV_AMD64_ES = CV_REG_ES,
594 CV_AMD64_CS = CV_REG_CS,
595 CV_AMD64_SS = CV_REG_SS,
596 CV_AMD64_DS = CV_REG_DS,
597 CV_AMD64_FS = CV_REG_FS,
598 CV_AMD64_GS = CV_REG_GS,
599 CV_AMD64_FLAGS = CV_REG_FLAGS,
600 CV_AMD64_RIP = CV_REG_EIP,
601 CV_AMD64_EFLAGS = CV_REG_EFLAGS,
602
603 /* <pcode> */
604 CV_AMD64_TEMP = CV_REG_TEMP,
605 CV_AMD64_TEMPH = CV_REG_TEMPH,
606 CV_AMD64_QUOTE = CV_REG_QUOTE,
607 CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
608 CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */
609 CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */
610 /* </pcode> */
611
612 CV_AMD64_GDTR = CV_REG_GDTR,
613 CV_AMD64_GDTL = CV_REG_GDTL,
614 CV_AMD64_IDTR = CV_REG_IDTR,
615 CV_AMD64_IDTL = CV_REG_IDTL,
616 CV_AMD64_LDTR = CV_REG_LDTR,
617 CV_AMD64_TR = CV_REG_TR,
618
619 CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */
620 CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */
621 CV_AMD64_CTRL = CV_REG_CTRL,
622 CV_AMD64_STAT = CV_REG_STAT,
623 CV_AMD64_TAG = CV_REG_TAG,
624 CV_AMD64_FPIP = CV_REG_FPIP,
625 CV_AMD64_FPCS = CV_REG_FPCS,
626 CV_AMD64_FPDO = CV_REG_FPDO,
627 CV_AMD64_FPDS = CV_REG_FPDS,
628 CV_AMD64_ISEM = CV_REG_ISEM,
629 CV_AMD64_FPEIP = CV_REG_FPEIP,
630 CV_AMD64_FPEDO = CV_REG_FPEDO,
631 CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */
632 CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */
633 CV_AMD64_XMM00 = CV_REG_XMM00,
634 CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */
635 CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */
636 CV_AMD64_MXCSR = CV_REG_MXCSR,
637 CV_AMD64_EDXEAX = CV_REG_EDXEAX,
638 CV_AMD64_EMM0L = CV_REG_EMM0L,
639 CV_AMD64_EMM0H = CV_REG_EMM0H,
640 CV_AMD64_MM00 = CV_REG_MM00,
641 CV_AMD64_MM01 = CV_REG_MM01,
642 CV_AMD64_MM10 = CV_REG_MM10,
643 CV_AMD64_MM11 = CV_REG_MM11,
644 CV_AMD64_MM20 = CV_REG_MM20,
645 CV_AMD64_MM21 = CV_REG_MM21,
646 CV_AMD64_MM30 = CV_REG_MM30,
647 CV_AMD64_MM31 = CV_REG_MM31,
648 CV_AMD64_MM40 = CV_REG_MM40,
649 CV_AMD64_MM41 = CV_REG_MM41,
650 CV_AMD64_MM50 = CV_REG_MM50,
651 CV_AMD64_MM51 = CV_REG_MM51,
652 CV_AMD64_MM60 = CV_REG_MM60,
653 CV_AMD64_MM61 = CV_REG_MM61,
654 CV_AMD64_MM70 = CV_REG_MM70,
655 CV_AMD64_MM71 = CV_REG_MM71,
656
657 CV_AMD64_XMM8 = 252, /* this includes XMM9 to XMM15 */
658
659 CV_AMD64_RAX = 328,
660 CV_AMD64_RBX = 329,
661 CV_AMD64_RCX = 330,
662 CV_AMD64_RDX = 331,
663 CV_AMD64_RSI = 332,
664 CV_AMD64_RDI = 333,
665 CV_AMD64_RBP = 334,
666 CV_AMD64_RSP = 335,
667
668 CV_AMD64_R8 = 336,
669 CV_AMD64_R9 = 337,
670 CV_AMD64_R10 = 338,
671 CV_AMD64_R11 = 339,
672 CV_AMD64_R12 = 340,
673 CV_AMD64_R13 = 341,
674 CV_AMD64_R14 = 342,
675 CV_AMD64_R15 = 343,
676
677 /* Wine extension */
678 CV_ARM64_NOREG = CV_REG_NONE,
679 CV_ARM64_X0 = 10, /* this includes X0 to X30 */
680 CV_ARM64_SP = 41,
681 CV_ARM64_PC = 42,
682 CV_ARM64_PSTATE = 43,
683};
684
685typedef enum
686{
687 THUNK_ORDINAL_NOTYPE,
688 THUNK_ORDINAL_ADJUSTOR,
689 THUNK_ORDINAL_VCALL,
690 THUNK_ORDINAL_PCODE,
691 THUNK_ORDINAL_LOAD
692} THUNK_ORDINAL;
693
694typedef enum CV_call_e
695{
696 CV_CALL_NEAR_C,
697 CV_CALL_FAR_C,
698 CV_CALL_NEAR_PASCAL,
699 CV_CALL_FAR_PASCAL,
700 CV_CALL_NEAR_FAST,
701 CV_CALL_FAR_FAST,
702 CV_CALL_SKIPPED,
703 CV_CALL_NEAR_STD,
704 CV_CALL_FAR_STD,
705 CV_CALL_NEAR_SYS,
706 CV_CALL_FAR_SYS,
707 CV_CALL_THISCALL,
708 CV_CALL_MIPSCALL,
709 CV_CALL_GENERIC,
710 CV_CALL_ALPHACALL,
711 CV_CALL_PPCCALL,
712 CV_CALL_SHCALL,
713 CV_CALL_ARMCALL,
714 CV_CALL_AM33CALL,
715 CV_CALL_TRICALL,
716 CV_CALL_SH5CALL,
717 CV_CALL_M32RCALL,
718 CV_CALL_RESERVED,
719} CV_call_e;
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