VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/vmsvga/svga3d_reg.h@ 82254

Last change on this file since 82254 was 76565, checked in by vboxsync, 6 years ago

Devices: Use VBOX_INCLUDED_SRC_ as header guard prefix with scm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 66.6 KB
Line 
1/**********************************************************
2 * Copyright 1998-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26/*
27 * svga3d_reg.h --
28 *
29 * SVGA 3D hardware definitions
30 */
31
32#ifndef _SVGA3D_REG_H_
33#define _SVGA3D_REG_H_
34#ifndef RT_WITHOUT_PRAGMA_ONCE
35# pragma once
36#endif
37
38#include "svga_reg.h"
39
40
41/*
42 * 3D Hardware Version
43 *
44 * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
45 * register. Is set by the host and read by the guest. This lets
46 * us make new guest drivers which are backwards-compatible with old
47 * SVGA hardware revisions. It does not let us support old guest
48 * drivers. Good enough for now.
49 *
50 */
51
52#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
53#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
54#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
55
56typedef enum {
57 SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
58 SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
59 SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
60 SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
61 SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
62 SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
63 SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
64 SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1
65} SVGA3dHardwareVersion;
66
67/*
68 * Generic Types
69 */
70
71typedef uint32_t SVGA3dBool; /* 32-bit Bool definition */
72#define SVGA3D_NUM_CLIPPLANES 6
73#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8
74#define SVGA3D_MAX_CONTEXT_IDS 256
75#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
76
77/*
78 * Surface formats.
79 *
80 * If you modify this list, be sure to keep GLUtil.c in sync. It
81 * includes the internal format definition of each surface in
82 * GLUtil_ConvertSurfaceFormat, and it contains a table of
83 * human-readable names in GLUtil_GetFormatName.
84 */
85
86typedef enum SVGA3dSurfaceFormat {
87 SVGA3D_FORMAT_INVALID = 0,
88
89 SVGA3D_X8R8G8B8 = 1,
90 SVGA3D_A8R8G8B8 = 2,
91
92 SVGA3D_R5G6B5 = 3,
93 SVGA3D_X1R5G5B5 = 4,
94 SVGA3D_A1R5G5B5 = 5,
95 SVGA3D_A4R4G4B4 = 6,
96
97 SVGA3D_Z_D32 = 7,
98 SVGA3D_Z_D16 = 8,
99 SVGA3D_Z_D24S8 = 9,
100 SVGA3D_Z_D15S1 = 10,
101
102 SVGA3D_LUMINANCE8 = 11,
103 SVGA3D_LUMINANCE4_ALPHA4 = 12,
104 SVGA3D_LUMINANCE16 = 13,
105 SVGA3D_LUMINANCE8_ALPHA8 = 14,
106
107 SVGA3D_DXT1 = 15,
108 SVGA3D_DXT2 = 16,
109 SVGA3D_DXT3 = 17,
110 SVGA3D_DXT4 = 18,
111 SVGA3D_DXT5 = 19,
112
113 SVGA3D_BUMPU8V8 = 20,
114 SVGA3D_BUMPL6V5U5 = 21,
115 SVGA3D_BUMPX8L8V8U8 = 22,
116 SVGA3D_BUMPL8V8U8 = 23,
117
118 SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
119 SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
120
121 SVGA3D_A2R10G10B10 = 26,
122
123 /* signed formats */
124 SVGA3D_V8U8 = 27,
125 SVGA3D_Q8W8V8U8 = 28,
126 SVGA3D_CxV8U8 = 29,
127
128 /* mixed formats */
129 SVGA3D_X8L8V8U8 = 30,
130 SVGA3D_A2W10V10U10 = 31,
131
132 SVGA3D_ALPHA8 = 32,
133
134 /* Single- and dual-component floating point formats */
135 SVGA3D_R_S10E5 = 33,
136 SVGA3D_R_S23E8 = 34,
137 SVGA3D_RG_S10E5 = 35,
138 SVGA3D_RG_S23E8 = 36,
139
140 /*
141 * Any surface can be used as a buffer object, but SVGA3D_BUFFER is
142 * the most efficient format to use when creating new surfaces
143 * expressly for index or vertex data.
144 */
145
146 SVGA3D_BUFFER = 37,
147
148 SVGA3D_Z_D24X8 = 38,
149
150 SVGA3D_V16U16 = 39,
151
152 SVGA3D_G16R16 = 40,
153 SVGA3D_A16B16G16R16 = 41,
154
155 /* Packed Video formats */
156 SVGA3D_UYVY = 42,
157 SVGA3D_YUY2 = 43,
158
159 /* Planar video formats */
160 SVGA3D_NV12 = 44,
161
162 /* Video format with alpha */
163 SVGA3D_AYUV = 45,
164
165 SVGA3D_R8G8B8A8_UNORM = 68, /// @todo use headers from newer Mesa
166
167 SVGA3D_BC4_UNORM = 108,
168 SVGA3D_BC5_UNORM = 111,
169
170 /* Advanced D3D9 depth formats. */
171 SVGA3D_Z_DF16 = 118,
172 SVGA3D_Z_DF24 = 119,
173 SVGA3D_Z_D24S8_INT = 120,
174
175 SVGA3D_R8G8B8A8_SNORM = 127, /// @todo use headers from newer Mesa
176 SVGA3D_R16G16_UNORM = 129, /// @todo use headers from newer Mesa
177
178 SVGA3D_FORMAT_MAX
179} SVGA3dSurfaceFormat;
180
181typedef uint32_t SVGA3dColor; /* a, r, g, b */
182
183/*
184 * These match the D3DFORMAT_OP definitions used by Direct3D. We need
185 * them so that we can query the host for what the supported surface
186 * operations are (when we're using the D3D backend, in particular),
187 * and so we can send those operations to the guest.
188 */
189typedef enum {
190 SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
191 SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
192 SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
193 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
194 SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
195 SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
196 SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
197
198/*
199 * This format can be used as a render target if the current display mode
200 * is the same depth if the alpha channel is ignored. e.g. if the device
201 * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
202 * format op list entry for A8R8G8B8 should have this cap.
203 */
204 SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
205
206/*
207 * This format contains DirectDraw support (including Flip). This flag
208 * should not to be set on alpha formats.
209 */
210 SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
211
212/*
213 * The rasterizer can support some level of Direct3D support in this format
214 * and implies that the driver can create a Context in this mode (for some
215 * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
216 * flag must also be set.
217 */
218 SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
219
220/*
221 * This is set for a private format when the driver has put the bpp in
222 * the structure.
223 */
224 SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
225
226/*
227 * Indicates that this format can be converted to any RGB format for which
228 * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified
229 */
230 SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
231
232/*
233 * Indicates that this format can be used to create offscreen plain surfaces.
234 */
235 SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
236
237/*
238 * Indicated that this format can be read as an SRGB texture (meaning that the
239 * sampler will linearize the looked up data)
240 */
241 SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
242
243/*
244 * Indicates that this format can be used in the bumpmap instructions
245 */
246 SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
247
248/*
249 * Indicates that this format can be sampled by the displacement map sampler
250 */
251 SVGA3DFORMAT_OP_DMAP = 0x00020000,
252
253/*
254 * Indicates that this format cannot be used with texture filtering
255 */
256 SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
257
258/*
259 * Indicates that format conversions are supported to this RGB format if
260 * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
261 */
262 SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
263
264/*
265 * Indicated that this format can be written as an SRGB target (meaning that the
266 * pixel pipe will DE-linearize data on output to format)
267 */
268 SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
269
270/*
271 * Indicates that this format cannot be used with alpha blending
272 */
273 SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
274
275/*
276 * Indicates that the device can auto-generated sublevels for resources
277 * of this format
278 */
279 SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
280
281/*
282 * Indicates that this format can be used by vertex texture sampler
283 */
284 SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
285
286/*
287 * Indicates that this format supports neither texture coordinate wrap
288 * modes, nor mipmapping
289 */
290 SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
291} SVGA3dFormatOp;
292
293/*
294 * This structure is a conversion of SVGA3DFORMAT_OP_*.
295 * Entries must be located at the same position.
296 */
297typedef union {
298 uint32_t value;
299 struct {
300 uint32_t texture : 1;
301 uint32_t volumeTexture : 1;
302 uint32_t cubeTexture : 1;
303 uint32_t offscreenRenderTarget : 1;
304 uint32_t sameFormatRenderTarget : 1;
305 uint32_t unknown1 : 1;
306 uint32_t zStencil : 1;
307 uint32_t zStencilArbitraryDepth : 1;
308 uint32_t sameFormatUpToAlpha : 1;
309 uint32_t unknown2 : 1;
310 uint32_t displayMode : 1;
311 uint32_t acceleration3d : 1;
312 uint32_t pixelSize : 1;
313 uint32_t convertToARGB : 1;
314 uint32_t offscreenPlain : 1;
315 uint32_t sRGBRead : 1;
316 uint32_t bumpMap : 1;
317 uint32_t dmap : 1;
318 uint32_t noFilter : 1;
319 uint32_t memberOfGroupARGB : 1;
320 uint32_t sRGBWrite : 1;
321 uint32_t noAlphaBlend : 1;
322 uint32_t autoGenMipMap : 1;
323 uint32_t vertexTexture : 1;
324 uint32_t noTexCoordWrapNorMip : 1;
325 } s;
326} SVGA3dSurfaceFormatCaps;
327
328/*
329 * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
330 * must fit in a uint32_t.
331 */
332
333typedef enum {
334 SVGA3D_RS_INVALID = 0,
335 SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
336 SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
337 SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
338 SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
339 SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
340 SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
341 SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
342 SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
343 SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
344 SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
345 SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
346 SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
347 SVGA3D_RS_STENCILREF = 13, /* uint32_t */
348 SVGA3D_RS_STENCILMASK = 14, /* uint32_t */
349 SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32_t */
350 SVGA3D_RS_FOGSTART = 16, /* float */
351 SVGA3D_RS_FOGEND = 17, /* float */
352 SVGA3D_RS_FOGDENSITY = 18, /* float */
353 SVGA3D_RS_POINTSIZE = 19, /* float */
354 SVGA3D_RS_POINTSIZEMIN = 20, /* float */
355 SVGA3D_RS_POINTSIZEMAX = 21, /* float */
356 SVGA3D_RS_POINTSCALE_A = 22, /* float */
357 SVGA3D_RS_POINTSCALE_B = 23, /* float */
358 SVGA3D_RS_POINTSCALE_C = 24, /* float */
359 SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
360 SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
361 SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
362 SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
363 SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
364 SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
365 SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
366 SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
367 SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
368 SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
369 SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
370 SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
371 SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
372 SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
373 SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
374 SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
375 SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
376 SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
377 SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
378 SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
379 SVGA3D_RS_ZBIAS = 45, /* float */
380 SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
381 SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
382 SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
383 SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
384 SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
385 SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
386 SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
387 SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
388 SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
389 SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
390 SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
391 SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
392 SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
393 SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
394 SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
395 SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
396 SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
397 SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
398 SVGA3D_RS_DEPTHBIAS = 64, /* float */
399
400
401 /*
402 * Output Gamma Level
403 *
404 * Output gamma effects the gamma curve of colors that are output from the
405 * rendering pipeline. A value of 1.0 specifies a linear color space. If the
406 * value is <= 0.0, gamma correction is ignored and linear color space is
407 * used.
408 */
409
410 SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
411 SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
412 SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
413 SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
414 SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
415 SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
416 SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
417 SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
418 SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
419 SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
420 SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
421 SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
422 SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
423 SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
424 SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
425 SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
426 SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
427 SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
428 SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
429 SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
430 SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
431 SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32_t */
432 SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
433 SVGA3D_RS_TWEENFACTOR = 88, /* float */
434 SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
435 SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
436 SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
437 SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
438 SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
439 SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
440 SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
441 SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
442 SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
443 SVGA3D_RS_LINEAA = 98, /* SVGA3dBool */
444 SVGA3D_RS_LINEWIDTH = 99, /* float */
445 SVGA3D_RS_MAX
446} SVGA3dRenderStateName;
447
448typedef enum {
449 SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
450 SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
451 SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
452 SVGA3D_TRANSPARENCYANTIALIAS_MAX
453} SVGA3dTransparencyAntialiasType;
454
455typedef enum {
456 SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
457 SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
458 SVGA3D_VERTEXMATERIAL_SPECULAR = 2 /* Use the value in the specular component */
459} SVGA3dVertexMaterial;
460
461typedef enum {
462 SVGA3D_FILLMODE_INVALID = 0,
463 SVGA3D_FILLMODE_POINT = 1,
464 SVGA3D_FILLMODE_LINE = 2,
465 SVGA3D_FILLMODE_FILL = 3,
466 SVGA3D_FILLMODE_MAX
467} SVGA3dFillModeType;
468
469
470typedef
471union {
472 struct {
473 uint16_t mode; /* SVGA3dFillModeType */
474 uint16_t face; /* SVGA3dFace */
475 } s;
476 uint32_t uintValue;
477} SVGA3dFillMode;
478
479typedef enum {
480 SVGA3D_SHADEMODE_INVALID = 0,
481 SVGA3D_SHADEMODE_FLAT = 1,
482 SVGA3D_SHADEMODE_SMOOTH = 2,
483 SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
484 SVGA3D_SHADEMODE_MAX
485} SVGA3dShadeMode;
486
487typedef
488union {
489 struct {
490 uint16_t repeat;
491 uint16_t pattern;
492 } s;
493 uint32_t uintValue;
494} SVGA3dLinePattern;
495
496typedef enum {
497 SVGA3D_BLENDOP_INVALID = 0,
498 SVGA3D_BLENDOP_ZERO = 1,
499 SVGA3D_BLENDOP_ONE = 2,
500 SVGA3D_BLENDOP_SRCCOLOR = 3,
501 SVGA3D_BLENDOP_INVSRCCOLOR = 4,
502 SVGA3D_BLENDOP_SRCALPHA = 5,
503 SVGA3D_BLENDOP_INVSRCALPHA = 6,
504 SVGA3D_BLENDOP_DESTALPHA = 7,
505 SVGA3D_BLENDOP_INVDESTALPHA = 8,
506 SVGA3D_BLENDOP_DESTCOLOR = 9,
507 SVGA3D_BLENDOP_INVDESTCOLOR = 10,
508 SVGA3D_BLENDOP_SRCALPHASAT = 11,
509 SVGA3D_BLENDOP_BLENDFACTOR = 12,
510 SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
511 SVGA3D_BLENDOP_MAX
512} SVGA3dBlendOp;
513
514typedef enum {
515 SVGA3D_BLENDEQ_INVALID = 0,
516 SVGA3D_BLENDEQ_ADD = 1,
517 SVGA3D_BLENDEQ_SUBTRACT = 2,
518 SVGA3D_BLENDEQ_REVSUBTRACT = 3,
519 SVGA3D_BLENDEQ_MINIMUM = 4,
520 SVGA3D_BLENDEQ_MAXIMUM = 5,
521 SVGA3D_BLENDEQ_MAX
522} SVGA3dBlendEquation;
523
524typedef enum {
525 SVGA3D_FRONTWINDING_INVALID = 0,
526 SVGA3D_FRONTWINDING_CW = 1,
527 SVGA3D_FRONTWINDING_CCW = 2,
528 SVGA3D_FRONTWINDING_MAX
529} SVGA3dFrontWinding;
530
531typedef enum {
532 SVGA3D_FACE_INVALID = 0,
533 SVGA3D_FACE_NONE = 1,
534 SVGA3D_FACE_FRONT = 2,
535 SVGA3D_FACE_BACK = 3,
536 SVGA3D_FACE_FRONT_BACK = 4,
537 SVGA3D_FACE_MAX
538} SVGA3dFace;
539
540/*
541 * The order and the values should not be changed
542 */
543
544typedef enum {
545 SVGA3D_CMP_INVALID = 0,
546 SVGA3D_CMP_NEVER = 1,
547 SVGA3D_CMP_LESS = 2,
548 SVGA3D_CMP_EQUAL = 3,
549 SVGA3D_CMP_LESSEQUAL = 4,
550 SVGA3D_CMP_GREATER = 5,
551 SVGA3D_CMP_NOTEQUAL = 6,
552 SVGA3D_CMP_GREATEREQUAL = 7,
553 SVGA3D_CMP_ALWAYS = 8,
554 SVGA3D_CMP_MAX
555} SVGA3dCmpFunc;
556
557/*
558 * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
559 * the fog factor to be specified in the alpha component of the specular
560 * (a.k.a. secondary) vertex color.
561 */
562typedef enum {
563 SVGA3D_FOGFUNC_INVALID = 0,
564 SVGA3D_FOGFUNC_EXP = 1,
565 SVGA3D_FOGFUNC_EXP2 = 2,
566 SVGA3D_FOGFUNC_LINEAR = 3,
567 SVGA3D_FOGFUNC_PER_VERTEX = 4
568} SVGA3dFogFunction;
569
570/*
571 * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
572 * or per-pixel basis.
573 */
574typedef enum {
575 SVGA3D_FOGTYPE_INVALID = 0,
576 SVGA3D_FOGTYPE_VERTEX = 1,
577 SVGA3D_FOGTYPE_PIXEL = 2,
578 SVGA3D_FOGTYPE_MAX = 3
579} SVGA3dFogType;
580
581/*
582 * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
583 * computed using the eye Z value of each pixel (or vertex), whereas range-
584 * based fog is computed using the actual distance (range) to the eye.
585 */
586typedef enum {
587 SVGA3D_FOGBASE_INVALID = 0,
588 SVGA3D_FOGBASE_DEPTHBASED = 1,
589 SVGA3D_FOGBASE_RANGEBASED = 2,
590 SVGA3D_FOGBASE_MAX = 3
591} SVGA3dFogBase;
592
593typedef enum {
594 SVGA3D_STENCILOP_INVALID = 0,
595 SVGA3D_STENCILOP_KEEP = 1,
596 SVGA3D_STENCILOP_ZERO = 2,
597 SVGA3D_STENCILOP_REPLACE = 3,
598 SVGA3D_STENCILOP_INCRSAT = 4,
599 SVGA3D_STENCILOP_DECRSAT = 5,
600 SVGA3D_STENCILOP_INVERT = 6,
601 SVGA3D_STENCILOP_INCR = 7,
602 SVGA3D_STENCILOP_DECR = 8,
603 SVGA3D_STENCILOP_MAX
604} SVGA3dStencilOp;
605
606typedef enum {
607 SVGA3D_CLIPPLANE_0 = (1 << 0),
608 SVGA3D_CLIPPLANE_1 = (1 << 1),
609 SVGA3D_CLIPPLANE_2 = (1 << 2),
610 SVGA3D_CLIPPLANE_3 = (1 << 3),
611 SVGA3D_CLIPPLANE_4 = (1 << 4),
612 SVGA3D_CLIPPLANE_5 = (1 << 5),
613 SVGA3D_CLIPPLANE_MAX = SVGA3D_CLIPPLANE_5
614} SVGA3dClipPlanes;
615
616typedef enum {
617 SVGA3D_CLEAR_COLOR = 0x1,
618 SVGA3D_CLEAR_DEPTH = 0x2,
619 SVGA3D_CLEAR_STENCIL = 0x4
620} SVGA3dClearFlag;
621
622typedef enum {
623 SVGA3D_RT_DEPTH = 0,
624 SVGA3D_RT_STENCIL = 1,
625 SVGA3D_RT_COLOR0 = 2,
626 SVGA3D_RT_COLOR1 = 3,
627 SVGA3D_RT_COLOR2 = 4,
628 SVGA3D_RT_COLOR3 = 5,
629 SVGA3D_RT_COLOR4 = 6,
630 SVGA3D_RT_COLOR5 = 7,
631 SVGA3D_RT_COLOR6 = 8,
632 SVGA3D_RT_COLOR7 = 9,
633 SVGA3D_RT_MAX,
634 SVGA3D_RT_INVALID = ((uint32_t)-1)
635} SVGA3dRenderTargetType;
636
637#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
638
639typedef
640union {
641 struct {
642 uint32_t red : 1;
643 uint32_t green : 1;
644 uint32_t blue : 1;
645 uint32_t alpha : 1;
646 } s;
647 uint32_t uintValue;
648} SVGA3dColorMask;
649
650typedef enum {
651 SVGA3D_VBLEND_DISABLE = 0,
652 SVGA3D_VBLEND_1WEIGHT = 1,
653 SVGA3D_VBLEND_2WEIGHT = 2,
654 SVGA3D_VBLEND_3WEIGHT = 3
655} SVGA3dVertexBlendFlags;
656
657typedef enum {
658 SVGA3D_WRAPCOORD_0 = 1 << 0,
659 SVGA3D_WRAPCOORD_1 = 1 << 1,
660 SVGA3D_WRAPCOORD_2 = 1 << 2,
661 SVGA3D_WRAPCOORD_3 = 1 << 3,
662 SVGA3D_WRAPCOORD_ALL = 0xF
663} SVGA3dWrapFlags;
664
665/*
666 * SVGA_3D_CMD_TEXTURESTATE Types. All value types
667 * must fit in a uint32_t.
668 */
669
670typedef enum {
671 SVGA3D_TS_INVALID = 0,
672 SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
673 SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
674 SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
675 SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
676 SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
677 SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
678 SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
679 SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
680 SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
681 SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
682 SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
683 SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
684 SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
685 SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32_t */
686 SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
687 SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
688 SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
689 SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
690 SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
691 SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
692 SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32_t */
693 SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
694 SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32_t */
695 SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
696
697
698 /*
699 * Sampler Gamma Level
700 *
701 * Sampler gamma effects the color of samples taken from the sampler. A
702 * value of 1.0 will produce linear samples. If the value is <= 0.0 the
703 * gamma value is ignored and a linear space is used.
704 */
705
706 SVGA3D_TS_GAMMA = 25, /* float */
707 SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
708 SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
709 SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
710 SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
711 SVGA3D_TS_MAX
712} SVGA3dTextureStateName;
713
714typedef enum {
715 SVGA3D_TC_INVALID = 0,
716 SVGA3D_TC_DISABLE = 1,
717 SVGA3D_TC_SELECTARG1 = 2,
718 SVGA3D_TC_SELECTARG2 = 3,
719 SVGA3D_TC_MODULATE = 4,
720 SVGA3D_TC_ADD = 5,
721 SVGA3D_TC_ADDSIGNED = 6,
722 SVGA3D_TC_SUBTRACT = 7,
723 SVGA3D_TC_BLENDTEXTUREALPHA = 8,
724 SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
725 SVGA3D_TC_BLENDCURRENTALPHA = 10,
726 SVGA3D_TC_BLENDFACTORALPHA = 11,
727 SVGA3D_TC_MODULATE2X = 12,
728 SVGA3D_TC_MODULATE4X = 13,
729 SVGA3D_TC_DSDT = 14,
730 SVGA3D_TC_DOTPRODUCT3 = 15,
731 SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
732 SVGA3D_TC_ADDSIGNED2X = 17,
733 SVGA3D_TC_ADDSMOOTH = 18,
734 SVGA3D_TC_PREMODULATE = 19,
735 SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
736 SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
737 SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
738 SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
739 SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
740 SVGA3D_TC_MULTIPLYADD = 25,
741 SVGA3D_TC_LERP = 26,
742 SVGA3D_TC_MAX
743} SVGA3dTextureCombiner;
744
745#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
746
747typedef enum {
748 SVGA3D_TEX_ADDRESS_INVALID = 0,
749 SVGA3D_TEX_ADDRESS_WRAP = 1,
750 SVGA3D_TEX_ADDRESS_MIRROR = 2,
751 SVGA3D_TEX_ADDRESS_CLAMP = 3,
752 SVGA3D_TEX_ADDRESS_BORDER = 4,
753 SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
754 SVGA3D_TEX_ADDRESS_EDGE = 6,
755 SVGA3D_TEX_ADDRESS_MAX
756} SVGA3dTextureAddress;
757
758/*
759 * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
760 * disabled, and the rasterizer should use the magnification filter instead.
761 */
762typedef enum {
763 SVGA3D_TEX_FILTER_NONE = 0,
764 SVGA3D_TEX_FILTER_NEAREST = 1,
765 SVGA3D_TEX_FILTER_LINEAR = 2,
766 SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
767 SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented
768 SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented
769 SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented
770 SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented
771 SVGA3D_TEX_FILTER_MAX
772} SVGA3dTextureFilter;
773
774typedef enum {
775 SVGA3D_TEX_TRANSFORM_OFF = 0,
776 SVGA3D_TEX_TRANSFORM_S = (1 << 0),
777 SVGA3D_TEX_TRANSFORM_T = (1 << 1),
778 SVGA3D_TEX_TRANSFORM_R = (1 << 2),
779 SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
780 SVGA3D_TEX_PROJECTED = (1 << 15)
781} SVGA3dTexTransformFlags;
782
783typedef enum {
784 SVGA3D_TEXCOORD_GEN_OFF = 0,
785 SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
786 SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
787 SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
788 SVGA3D_TEXCOORD_GEN_SPHERE = 4,
789 SVGA3D_TEXCOORD_GEN_MAX
790} SVGA3dTextureCoordGen;
791
792/*
793 * Texture argument constants for texture combiner
794 */
795typedef enum {
796 SVGA3D_TA_INVALID = 0,
797 SVGA3D_TA_CONSTANT = 1,
798 SVGA3D_TA_PREVIOUS = 2,
799 SVGA3D_TA_DIFFUSE = 3,
800 SVGA3D_TA_TEXTURE = 4,
801 SVGA3D_TA_SPECULAR = 5,
802 SVGA3D_TA_MAX
803} SVGA3dTextureArgData;
804
805#define SVGA3D_TM_MASK_LEN 4
806
807/* Modifiers for texture argument constants defined above. */
808typedef enum {
809 SVGA3D_TM_NONE = 0,
810 SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
811 SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN)
812} SVGA3dTextureArgModifier;
813
814#define SVGA3D_INVALID_ID ((uint32_t)-1)
815#define SVGA3D_MAX_CLIP_PLANES 6
816
817/*
818 * This is the limit to the number of fixed-function texture
819 * transforms and texture coordinates we can support. It does *not*
820 * correspond to the number of texture image units (samplers) we
821 * support!
822 */
823#define SVGA3D_MAX_TEXTURE_COORDS 8
824
825/*
826 * Vertex declarations
827 *
828 * Notes:
829 *
830 * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
831 * draw with any POSITIONT vertex arrays, the programmable vertex
832 * pipeline will be implicitly disabled. Drawing will take place as if
833 * no vertex shader was bound.
834 */
835
836typedef enum {
837 SVGA3D_DECLUSAGE_POSITION = 0,
838 SVGA3D_DECLUSAGE_BLENDWEIGHT, // 1
839 SVGA3D_DECLUSAGE_BLENDINDICES, // 2
840 SVGA3D_DECLUSAGE_NORMAL, // 3
841 SVGA3D_DECLUSAGE_PSIZE, // 4
842 SVGA3D_DECLUSAGE_TEXCOORD, // 5
843 SVGA3D_DECLUSAGE_TANGENT, // 6
844 SVGA3D_DECLUSAGE_BINORMAL, // 7
845 SVGA3D_DECLUSAGE_TESSFACTOR, // 8
846 SVGA3D_DECLUSAGE_POSITIONT, // 9
847 SVGA3D_DECLUSAGE_COLOR, // 10
848 SVGA3D_DECLUSAGE_FOG, // 11
849 SVGA3D_DECLUSAGE_DEPTH, // 12
850 SVGA3D_DECLUSAGE_SAMPLE, // 13
851 SVGA3D_DECLUSAGE_MAX
852} SVGA3dDeclUsage;
853
854typedef enum {
855 SVGA3D_DECLMETHOD_DEFAULT = 0,
856 SVGA3D_DECLMETHOD_PARTIALU,
857 SVGA3D_DECLMETHOD_PARTIALV,
858 SVGA3D_DECLMETHOD_CROSSUV, // Normal
859 SVGA3D_DECLMETHOD_UV,
860 SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map
861 SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED // Lookup a pre-sampled displacement map
862} SVGA3dDeclMethod;
863
864typedef enum {
865 SVGA3D_DECLTYPE_FLOAT1 = 0,
866 SVGA3D_DECLTYPE_FLOAT2 = 1,
867 SVGA3D_DECLTYPE_FLOAT3 = 2,
868 SVGA3D_DECLTYPE_FLOAT4 = 3,
869 SVGA3D_DECLTYPE_D3DCOLOR = 4,
870 SVGA3D_DECLTYPE_UBYTE4 = 5,
871 SVGA3D_DECLTYPE_SHORT2 = 6,
872 SVGA3D_DECLTYPE_SHORT4 = 7,
873 SVGA3D_DECLTYPE_UBYTE4N = 8,
874 SVGA3D_DECLTYPE_SHORT2N = 9,
875 SVGA3D_DECLTYPE_SHORT4N = 10,
876 SVGA3D_DECLTYPE_USHORT2N = 11,
877 SVGA3D_DECLTYPE_USHORT4N = 12,
878 SVGA3D_DECLTYPE_UDEC3 = 13,
879 SVGA3D_DECLTYPE_DEC3N = 14,
880 SVGA3D_DECLTYPE_FLOAT16_2 = 15,
881 SVGA3D_DECLTYPE_FLOAT16_4 = 16,
882 SVGA3D_DECLTYPE_MAX
883} SVGA3dDeclType;
884
885/*
886 * This structure is used for the divisor for geometry instancing;
887 * it's a direct translation of the Direct3D equivalent.
888 */
889typedef union {
890 struct {
891 /*
892 * For index data, this number represents the number of instances to draw.
893 * For instance data, this number represents the number of
894 * instances/vertex in this stream
895 */
896 uint32_t count : 30;
897
898 /*
899 * This is 1 if this is supposed to be the data that is repeated for
900 * every instance.
901 */
902 uint32_t indexedData : 1;
903
904 /*
905 * This is 1 if this is supposed to be the per-instance data.
906 */
907 uint32_t instanceData : 1;
908 } s;
909
910 uint32_t value;
911} SVGA3dVertexDivisor;
912
913typedef enum {
914 SVGA3D_PRIMITIVE_INVALID = 0,
915 SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
916 SVGA3D_PRIMITIVE_POINTLIST = 2,
917 SVGA3D_PRIMITIVE_LINELIST = 3,
918 SVGA3D_PRIMITIVE_LINESTRIP = 4,
919 SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
920 SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
921 SVGA3D_PRIMITIVE_MAX
922} SVGA3dPrimitiveType;
923
924typedef enum {
925 SVGA3D_COORDINATE_INVALID = 0,
926 SVGA3D_COORDINATE_LEFTHANDED = 1,
927 SVGA3D_COORDINATE_RIGHTHANDED = 2,
928 SVGA3D_COORDINATE_MAX
929} SVGA3dCoordinateType;
930
931typedef enum {
932 SVGA3D_TRANSFORM_INVALID = 0,
933 SVGA3D_TRANSFORM_WORLD = 1,
934 SVGA3D_TRANSFORM_VIEW = 2,
935 SVGA3D_TRANSFORM_PROJECTION = 3,
936 SVGA3D_TRANSFORM_TEXTURE0 = 4,
937 SVGA3D_TRANSFORM_TEXTURE1 = 5,
938 SVGA3D_TRANSFORM_TEXTURE2 = 6,
939 SVGA3D_TRANSFORM_TEXTURE3 = 7,
940 SVGA3D_TRANSFORM_TEXTURE4 = 8,
941 SVGA3D_TRANSFORM_TEXTURE5 = 9,
942 SVGA3D_TRANSFORM_TEXTURE6 = 10,
943 SVGA3D_TRANSFORM_TEXTURE7 = 11,
944 SVGA3D_TRANSFORM_WORLD1 = 12,
945 SVGA3D_TRANSFORM_WORLD2 = 13,
946 SVGA3D_TRANSFORM_WORLD3 = 14,
947 SVGA3D_TRANSFORM_MAX
948} SVGA3dTransformType;
949
950typedef enum {
951 SVGA3D_LIGHTTYPE_INVALID = 0,
952 SVGA3D_LIGHTTYPE_POINT = 1,
953 SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
954 SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
955 SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
956 SVGA3D_LIGHTTYPE_MAX
957} SVGA3dLightType;
958
959typedef enum {
960 SVGA3D_CUBEFACE_POSX = 0,
961 SVGA3D_CUBEFACE_NEGX = 1,
962 SVGA3D_CUBEFACE_POSY = 2,
963 SVGA3D_CUBEFACE_NEGY = 3,
964 SVGA3D_CUBEFACE_POSZ = 4,
965 SVGA3D_CUBEFACE_NEGZ = 5
966} SVGA3dCubeFace;
967
968typedef enum {
969 SVGA3D_SHADERTYPE_VS = 1,
970 SVGA3D_SHADERTYPE_PS = 2,
971 SVGA3D_SHADERTYPE_MAX
972} SVGA3dShaderType;
973
974typedef enum {
975 SVGA3D_CONST_TYPE_FLOAT = 0,
976 SVGA3D_CONST_TYPE_INT = 1,
977 SVGA3D_CONST_TYPE_BOOL = 2
978} SVGA3dShaderConstType;
979
980#define SVGA3D_MAX_SURFACE_FACES 6
981
982typedef enum {
983 SVGA3D_STRETCH_BLT_POINT = 0,
984 SVGA3D_STRETCH_BLT_LINEAR = 1,
985 SVGA3D_STRETCH_BLT_MAX
986} SVGA3dStretchBltMode;
987
988typedef enum {
989 SVGA3D_QUERYTYPE_OCCLUSION = 0,
990 SVGA3D_QUERYTYPE_MAX
991} SVGA3dQueryType;
992
993typedef enum {
994 SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */
995 SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */
996 SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */
997 SVGA3D_QUERYSTATE_NEW = 3 /* Never submitted (For guest use only) */
998} SVGA3dQueryState;
999
1000typedef enum {
1001 SVGA3D_WRITE_HOST_VRAM = 1,
1002 SVGA3D_READ_HOST_VRAM = 2
1003} SVGA3dTransferType;
1004
1005/*
1006 * The maximum number of vertex arrays we're guaranteed to support in
1007 * SVGA_3D_CMD_DRAWPRIMITIVES.
1008 */
1009#define SVGA3D_MAX_VERTEX_ARRAYS 32
1010
1011/*
1012 * The maximum number of primitive ranges we're guaranteed to support
1013 * in SVGA_3D_CMD_DRAWPRIMITIVES.
1014 */
1015#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
1016
1017/*
1018 * Identifiers for commands in the command FIFO.
1019 *
1020 * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
1021 * the SVGA3D protocol and remain reserved; they should not be used in the
1022 * future.
1023 *
1024 * IDs between 1040 and 1999 (inclusive) are available for use by the
1025 * current SVGA3D protocol.
1026 *
1027 * FIFO clients other than SVGA3D should stay below 1000, or at 2000
1028 * and up.
1029 */
1030
1031#define SVGA_3D_CMD_LEGACY_BASE 1000
1032#define SVGA_3D_CMD_BASE 1040
1033
1034#define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 // Deprecated
1035#define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1
1036#define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2
1037#define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3
1038#define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4
1039#define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5
1040#define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6
1041#define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7
1042#define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8
1043#define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9
1044#define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10
1045#define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11
1046#define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12
1047#define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13
1048#define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14
1049#define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15
1050#define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16
1051#define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17
1052#define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 // Deprecated
1053#define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19
1054#define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20
1055#define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21
1056#define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22
1057#define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23
1058#define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24
1059#define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25
1060#define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26
1061#define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27
1062#define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 // Deprecated
1063#define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29
1064#define SVGA_3D_CMD_SURFACE_DEFINE_V2 SVGA_3D_CMD_BASE + 30
1065#define SVGA_3D_CMD_GENERATE_MIPMAPS SVGA_3D_CMD_BASE + 31
1066#define SVGA_3D_CMD_ACTIVATE_SURFACE SVGA_3D_CMD_BASE + 40
1067#define SVGA_3D_CMD_DEACTIVATE_SURFACE SVGA_3D_CMD_BASE + 41
1068#define SVGA_3D_CMD_MAX SVGA_3D_CMD_BASE + 42
1069
1070#define SVGA_3D_CMD_FUTURE_MAX 2000
1071
1072/*
1073 * Common substructures used in multiple FIFO commands:
1074 */
1075
1076typedef struct {
1077 union {
1078 struct {
1079 uint16_t function; // SVGA3dFogFunction
1080 uint8_t type; // SVGA3dFogType
1081 uint8_t base; // SVGA3dFogBase
1082 } s;
1083 uint32_t uintValue;
1084 };
1085} SVGA3dFogMode;
1086
1087/*
1088 * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1089 * is a surface ID as well as face/mipmap indices.
1090 */
1091
1092typedef
1093struct SVGA3dSurfaceImageId {
1094 uint32_t sid;
1095 uint32_t face;
1096 uint32_t mipmap;
1097} SVGA3dSurfaceImageId;
1098
1099typedef
1100struct SVGA3dGuestImage {
1101 SVGAGuestPtr ptr;
1102
1103 /*
1104 * A note on interpretation of pitch: This value of pitch is the
1105 * number of bytes between vertically adjacent image
1106 * blocks. Normally this is the number of bytes between the first
1107 * pixel of two adjacent scanlines. With compressed textures,
1108 * however, this may represent the number of bytes between
1109 * compression blocks rather than between rows of pixels.
1110 *
1111 * XXX: Compressed textures currently must be tightly packed in guest memory.
1112 *
1113 * If the image is 1-dimensional, pitch is ignored.
1114 *
1115 * If 'pitch' is zero, the SVGA3D device calculates a pitch value
1116 * assuming each row of blocks is tightly packed.
1117 */
1118 uint32_t pitch;
1119} SVGA3dGuestImage;
1120
1121
1122/*
1123 * FIFO command format definitions:
1124 */
1125
1126/*
1127 * The data size header following cmdNum for every 3d command
1128 */
1129typedef
1130struct {
1131 /* uint32_t id; duplicate*/
1132 uint32_t size;
1133} SVGA3dCmdHeader;
1134
1135/*
1136 * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with
1137 * optional mipmaps and cube faces.
1138 */
1139
1140typedef
1141struct {
1142 uint32_t width;
1143 uint32_t height;
1144 uint32_t depth;
1145} SVGA3dSize;
1146
1147typedef enum {
1148 SVGA3D_SURFACE_CUBEMAP = (1 << 0),
1149 SVGA3D_SURFACE_HINT_STATIC = (1 << 1),
1150 SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2),
1151 SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3),
1152 SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4),
1153 SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5),
1154 SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6),
1155 SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7),
1156 SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8),
1157 SVGA3D_SURFACE_MASKABLE_ANTIALIAS = (1 << 9),
1158 SVGA3D_SURFACE_AUTOGENMIPMAPS = (1 << 10)
1159} SVGA3dSurfaceFlags;
1160
1161typedef
1162struct {
1163 uint32_t numMipLevels;
1164} SVGA3dSurfaceFace;
1165
1166typedef
1167struct {
1168 uint32_t sid;
1169 SVGA3dSurfaceFlags surfaceFlags;
1170 SVGA3dSurfaceFormat format;
1171 /*
1172 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1173 * structures must have the same value of numMipLevels field.
1174 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1175 * numMipLevels set to 0.
1176 */
1177 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1178 /*
1179 * Followed by an SVGA3dSize structure for each mip level in each face.
1180 *
1181 * A note on surface sizes: Sizes are always specified in pixels,
1182 * even if the true surface size is not a multiple of the minimum
1183 * block size of the surface's format. For example, a 3x3x1 DXT1
1184 * compressed texture would actually be stored as a 4x4x1 image in
1185 * memory.
1186 */
1187} SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
1188
1189typedef
1190struct {
1191 uint32_t sid;
1192 SVGA3dSurfaceFlags surfaceFlags;
1193 SVGA3dSurfaceFormat format;
1194 /*
1195 * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
1196 * structures must have the same value of numMipLevels field.
1197 * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
1198 * numMipLevels set to 0.
1199 */
1200 SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
1201 uint32_t multisampleCount;
1202 SVGA3dTextureFilter autogenFilter;
1203 /*
1204 * Followed by an SVGA3dSize structure for each mip level in each face.
1205 *
1206 * A note on surface sizes: Sizes are always specified in pixels,
1207 * even if the true surface size is not a multiple of the minimum
1208 * block size of the surface's format. For example, a 3x3x1 DXT1
1209 * compressed texture would actually be stored as a 4x4x1 image in
1210 * memory.
1211 */
1212} SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
1213
1214typedef
1215struct {
1216 uint32_t sid;
1217} SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
1218
1219typedef
1220struct {
1221 uint32_t cid;
1222} SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
1223
1224typedef
1225struct {
1226 uint32_t cid;
1227} SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
1228
1229typedef
1230struct {
1231 uint32_t cid;
1232 SVGA3dClearFlag clearFlag;
1233 uint32_t color;
1234 float depth;
1235 uint32_t stencil;
1236 /* Followed by variable number of SVGA3dRect structures */
1237} SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
1238
1239typedef
1240struct SVGA3dCopyRect {
1241 uint32_t x;
1242 uint32_t y;
1243 uint32_t w;
1244 uint32_t h;
1245 uint32_t srcx;
1246 uint32_t srcy;
1247} SVGA3dCopyRect;
1248
1249typedef
1250struct SVGA3dCopyBox {
1251 uint32_t x;
1252 uint32_t y;
1253 uint32_t z;
1254 uint32_t w;
1255 uint32_t h;
1256 uint32_t d;
1257 uint32_t srcx;
1258 uint32_t srcy;
1259 uint32_t srcz;
1260} SVGA3dCopyBox;
1261
1262typedef
1263struct {
1264 uint32_t x;
1265 uint32_t y;
1266 uint32_t w;
1267 uint32_t h;
1268} SVGA3dRect;
1269
1270typedef
1271struct {
1272 uint32_t x;
1273 uint32_t y;
1274 uint32_t z;
1275 uint32_t w;
1276 uint32_t h;
1277 uint32_t d;
1278} SVGA3dBox;
1279
1280typedef
1281struct {
1282 uint32_t x;
1283 uint32_t y;
1284 uint32_t z;
1285} SVGA3dPoint;
1286
1287typedef
1288struct {
1289 SVGA3dLightType type;
1290 SVGA3dBool inWorldSpace;
1291 float diffuse[4];
1292 float specular[4];
1293 float ambient[4];
1294 float position[4];
1295 float direction[4];
1296 float range;
1297 float falloff;
1298 float attenuation0;
1299 float attenuation1;
1300 float attenuation2;
1301 float theta;
1302 float phi;
1303} SVGA3dLightData;
1304
1305typedef
1306struct {
1307 uint32_t sid;
1308 /* Followed by variable number of SVGA3dCopyRect structures */
1309} SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
1310
1311typedef
1312struct {
1313 SVGA3dRenderStateName state;
1314 union {
1315 uint32_t uintValue;
1316 float floatValue;
1317 };
1318} SVGA3dRenderState;
1319
1320typedef
1321struct {
1322 uint32_t cid;
1323 /* Followed by variable number of SVGA3dRenderState structures */
1324} SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
1325
1326typedef
1327struct {
1328 uint32_t cid;
1329 SVGA3dRenderTargetType type;
1330 SVGA3dSurfaceImageId target;
1331} SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
1332
1333typedef
1334struct {
1335 SVGA3dSurfaceImageId src;
1336 SVGA3dSurfaceImageId dest;
1337 /* Followed by variable number of SVGA3dCopyBox structures */
1338} SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
1339
1340typedef
1341struct {
1342 SVGA3dSurfaceImageId src;
1343 SVGA3dSurfaceImageId dest;
1344 SVGA3dBox boxSrc;
1345 SVGA3dBox boxDest;
1346 SVGA3dStretchBltMode mode;
1347} SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
1348
1349typedef
1350struct {
1351 /*
1352 * If the discard flag is present in a surface DMA operation, the host may
1353 * discard the contents of the current mipmap level and face of the target
1354 * surface before applying the surface DMA contents.
1355 */
1356 uint32_t discard : 1;
1357
1358 /*
1359 * If the unsynchronized flag is present, the host may perform this upload
1360 * without syncing to pending reads on this surface.
1361 */
1362 uint32_t unsynchronized : 1;
1363
1364 /*
1365 * Guests *MUST* set the reserved bits to 0 before submitting the command
1366 * suffix as future flags may occupy these bits.
1367 */
1368 uint32_t reserved : 30;
1369} SVGA3dSurfaceDMAFlags;
1370
1371typedef
1372struct {
1373 SVGA3dGuestImage guest;
1374 SVGA3dSurfaceImageId host;
1375 SVGA3dTransferType transfer;
1376 /*
1377 * Followed by variable number of SVGA3dCopyBox structures. For consistency
1378 * in all clipping logic and coordinate translation, we define the
1379 * "source" in each copyBox as the guest image and the
1380 * "destination" as the host image, regardless of transfer
1381 * direction.
1382 *
1383 * For efficiency, the SVGA3D device is free to copy more data than
1384 * specified. For example, it may round copy boxes outwards such
1385 * that they lie on particular alignment boundaries.
1386 */
1387} SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
1388
1389/*
1390 * SVGA3dCmdSurfaceDMASuffix --
1391 *
1392 * This is a command suffix that will appear after a SurfaceDMA command in
1393 * the FIFO. It contains some extra information that hosts may use to
1394 * optimize performance or protect the guest. This suffix exists to preserve
1395 * backwards compatibility while also allowing for new functionality to be
1396 * implemented.
1397 */
1398
1399typedef
1400struct {
1401 uint32_t suffixSize;
1402
1403 /*
1404 * The maximum offset is used to determine the maximum offset from the
1405 * guestPtr base address that will be accessed or written to during this
1406 * surfaceDMA. If the suffix is supported, the host will respect this
1407 * boundary while performing surface DMAs.
1408 *
1409 * Defaults to MAX_uint32_t
1410 */
1411 uint32_t maximumOffset;
1412
1413 /*
1414 * A set of flags that describes optimizations that the host may perform
1415 * while performing this surface DMA operation. The guest should never rely
1416 * on behaviour that is different when these flags are set for correctness.
1417 *
1418 * Defaults to 0
1419 */
1420 SVGA3dSurfaceDMAFlags flags;
1421} SVGA3dCmdSurfaceDMASuffix;
1422
1423/*
1424 * SVGA_3D_CMD_DRAW_PRIMITIVES --
1425 *
1426 * This command is the SVGA3D device's generic drawing entry point.
1427 * It can draw multiple ranges of primitives, optionally using an
1428 * index buffer, using an arbitrary collection of vertex buffers.
1429 *
1430 * Each SVGA3dVertexDecl defines a distinct vertex array to bind
1431 * during this draw call. The declarations specify which surface
1432 * the vertex data lives in, what that vertex data is used for,
1433 * and how to interpret it.
1434 *
1435 * Each SVGA3dPrimitiveRange defines a collection of primitives
1436 * to render using the same vertex arrays. An index buffer is
1437 * optional.
1438 */
1439
1440typedef
1441struct {
1442 /*
1443 * A range hint is an optional specification for the range of indices
1444 * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
1445 * that the entire array will be used.
1446 *
1447 * These are only hints. The SVGA3D device may use them for
1448 * performance optimization if possible, but it's also allowed to
1449 * ignore these values.
1450 */
1451 uint32_t first;
1452 uint32_t last;
1453} SVGA3dArrayRangeHint;
1454
1455typedef
1456struct {
1457 /*
1458 * Define the origin and shape of a vertex or index array. Both
1459 * 'offset' and 'stride' are in bytes. The provided surface will be
1460 * reinterpreted as a flat array of bytes in the same format used
1461 * by surface DMA operations. To avoid unnecessary conversions, the
1462 * surface should be created with the SVGA3D_BUFFER format.
1463 *
1464 * Index 0 in the array starts 'offset' bytes into the surface.
1465 * Index 1 begins at byte 'offset + stride', etc. Array indices may
1466 * not be negative.
1467 */
1468 uint32_t surfaceId;
1469 uint32_t offset;
1470 uint32_t stride;
1471} SVGA3dArray;
1472
1473typedef
1474struct {
1475 /*
1476 * Describe a vertex array's data type, and define how it is to be
1477 * used by the fixed function pipeline or the vertex shader. It
1478 * isn't useful to have two VertexDecls with the same
1479 * VertexArrayIdentity in one draw call.
1480 */
1481 SVGA3dDeclType type;
1482 SVGA3dDeclMethod method;
1483 SVGA3dDeclUsage usage;
1484 uint32_t usageIndex;
1485} SVGA3dVertexArrayIdentity;
1486
1487typedef
1488struct {
1489 SVGA3dVertexArrayIdentity identity;
1490 SVGA3dArray array;
1491 SVGA3dArrayRangeHint rangeHint;
1492} SVGA3dVertexDecl;
1493
1494typedef
1495struct {
1496 /*
1497 * Define a group of primitives to render, from sequential indices.
1498 *
1499 * The value of 'primitiveType' and 'primitiveCount' imply the
1500 * total number of vertices that will be rendered.
1501 */
1502 SVGA3dPrimitiveType primType;
1503 uint32_t primitiveCount;
1504
1505 /*
1506 * Optional index buffer. If indexArray.surfaceId is
1507 * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
1508 * without an index buffer is identical to rendering with an index
1509 * buffer containing the sequence [0, 1, 2, 3, ...].
1510 *
1511 * If an index buffer is in use, indexWidth specifies the width in
1512 * bytes of each index value. It must be less than or equal to
1513 * indexArray.stride.
1514 *
1515 * (Currently, the SVGA3D device requires index buffers to be tightly
1516 * packed. In other words, indexWidth == indexArray.stride)
1517 */
1518 SVGA3dArray indexArray;
1519 uint32_t indexWidth;
1520
1521 /*
1522 * Optional index bias. This number is added to all indices from
1523 * indexArray before they are used as vertex array indices. This
1524 * can be used in multiple ways:
1525 *
1526 * - When not using an indexArray, this bias can be used to
1527 * specify where in the vertex arrays to begin rendering.
1528 *
1529 * - A positive number here is equivalent to increasing the
1530 * offset in each vertex array.
1531 *
1532 * - A negative number can be used to render using a small
1533 * vertex array and an index buffer that contains large
1534 * values. This may be used by some applications that
1535 * crop a vertex buffer without modifying their index
1536 * buffer.
1537 *
1538 * Note that rendering with a negative bias value may be slower and
1539 * use more memory than rendering with a positive or zero bias.
1540 */
1541 int32_t indexBias;
1542} SVGA3dPrimitiveRange;
1543
1544typedef
1545struct {
1546 uint32_t cid;
1547 uint32_t numVertexDecls;
1548 uint32_t numRanges;
1549
1550 /*
1551 * There are two variable size arrays after the
1552 * SVGA3dCmdDrawPrimitives structure. In order,
1553 * they are:
1554 *
1555 * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
1556 * SVGA3D_MAX_VERTEX_ARRAYS;
1557 * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
1558 * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
1559 * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
1560 * the frequency divisor for the corresponding vertex decl).
1561 */
1562} SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
1563
1564typedef
1565struct {
1566 uint32_t stage;
1567 SVGA3dTextureStateName name;
1568 union {
1569 uint32_t value;
1570 float floatValue;
1571 };
1572} SVGA3dTextureState;
1573
1574typedef
1575struct {
1576 uint32_t cid;
1577 /* Followed by variable number of SVGA3dTextureState structures */
1578} SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
1579
1580typedef
1581struct {
1582 uint32_t cid;
1583 SVGA3dTransformType type;
1584 float matrix[16];
1585} SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
1586
1587typedef
1588struct {
1589 float min;
1590 float max;
1591} SVGA3dZRange;
1592
1593typedef
1594struct {
1595 uint32_t cid;
1596 SVGA3dZRange zRange;
1597} SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
1598
1599typedef
1600struct {
1601 float diffuse[4];
1602 float ambient[4];
1603 float specular[4];
1604 float emissive[4];
1605 float shininess;
1606} SVGA3dMaterial;
1607
1608typedef
1609struct {
1610 uint32_t cid;
1611 SVGA3dFace face;
1612 SVGA3dMaterial material;
1613} SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
1614
1615typedef
1616struct {
1617 uint32_t cid;
1618 uint32_t index;
1619 SVGA3dLightData data;
1620} SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
1621
1622typedef
1623struct {
1624 uint32_t cid;
1625 uint32_t index;
1626 uint32_t enabled;
1627} SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
1628
1629typedef
1630struct {
1631 uint32_t cid;
1632 SVGA3dRect rect;
1633} SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
1634
1635typedef
1636struct {
1637 uint32_t cid;
1638 SVGA3dRect rect;
1639} SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
1640
1641typedef
1642struct {
1643 uint32_t cid;
1644 uint32_t index;
1645 float plane[4];
1646} SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
1647
1648typedef
1649struct {
1650 uint32_t cid;
1651 uint32_t shid;
1652 SVGA3dShaderType type;
1653 /* Followed by variable number of DWORDs for shader bycode */
1654} SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
1655
1656typedef
1657struct {
1658 uint32_t cid;
1659 uint32_t shid;
1660 SVGA3dShaderType type;
1661} SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
1662
1663typedef
1664struct {
1665 uint32_t cid;
1666 uint32_t reg; /* register number */
1667 SVGA3dShaderType type;
1668 SVGA3dShaderConstType ctype;
1669 uint32_t values[4];
1670} SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
1671
1672typedef
1673struct {
1674 uint32_t cid;
1675 SVGA3dShaderType type;
1676 uint32_t shid;
1677} SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
1678
1679typedef
1680struct {
1681 uint32_t cid;
1682 SVGA3dQueryType type;
1683} SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
1684
1685typedef
1686struct {
1687 uint32_t cid;
1688 SVGA3dQueryType type;
1689 SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1690} SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
1691
1692typedef
1693struct {
1694 uint32_t cid; /* Same parameters passed to END_QUERY */
1695 SVGA3dQueryType type;
1696 SVGAGuestPtr guestResult;
1697} SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
1698
1699typedef
1700struct {
1701 uint32_t totalSize; /* Set by guest before query is ended. */
1702 SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1703 union { /* Set by host on exit from PENDING state */
1704 uint32_t result32;
1705 };
1706} SVGA3dQueryResult;
1707
1708/*
1709 * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1710 *
1711 * This is a blit from an SVGA3D surface to a Screen Object. Just
1712 * like GMR-to-screen blits, this blit may be directed at a
1713 * specific screen or to the virtual coordinate space.
1714 *
1715 * The blit copies from a rectangular region of an SVGA3D surface
1716 * image to a rectangular region of a screen or screens.
1717 *
1718 * This command takes an optional variable-length list of clipping
1719 * rectangles after the body of the command. If no rectangles are
1720 * specified, there is no clipping region. The entire destRect is
1721 * drawn to. If one or more rectangles are included, they describe
1722 * a clipping region. The clip rectangle coordinates are measured
1723 * relative to the top-left corner of destRect.
1724 *
1725 * This clipping region serves multiple purposes:
1726 *
1727 * - It can be used to perform an irregularly shaped blit more
1728 * efficiently than by issuing many separate blit commands.
1729 *
1730 * - It is equivalent to allowing blits with non-integer
1731 * source coordinates. You could blit just one half-pixel
1732 * of a source, for example, by specifying a larger
1733 * destination rectangle than you need, then removing
1734 * part of it using a clip rectangle.
1735 *
1736 * Availability:
1737 * SVGA_FIFO_CAP_SCREEN_OBJECT
1738 *
1739 * Limitations:
1740 *
1741 * - Currently, no backend supports blits from a mipmap or face
1742 * other than the first one.
1743 */
1744
1745typedef
1746struct {
1747 SVGA3dSurfaceImageId srcImage;
1748 SVGASignedRect srcRect;
1749 uint32_t destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */
1750 SVGASignedRect destRect; /* Supports scaling if src/rest different size */
1751 /* Clipping: zero or more SVGASignedRects follow */
1752} SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
1753
1754typedef
1755struct {
1756 uint32_t sid;
1757 SVGA3dTextureFilter filter;
1758} SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
1759
1760
1761/*
1762 * Capability query index.
1763 *
1764 * Notes:
1765 *
1766 * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
1767 * fixed-function texture units available. Each of these units
1768 * work in both FFP and Shader modes, and they support texture
1769 * transforms and texture coordinates. The host may have additional
1770 * texture image units that are only usable with shaders.
1771 *
1772 * 2. The BUFFER_FORMAT capabilities are deprecated, and they always
1773 * return TRUE. Even on physical hardware that does not support
1774 * these formats natively, the SVGA3D device will provide an emulation
1775 * which should be invisible to the guest OS.
1776 *
1777 * In general, the SVGA3D device should support any operation on
1778 * any surface format, it just may perform some of these
1779 * operations in software depending on the capabilities of the
1780 * available physical hardware.
1781 *
1782 * XXX: In the future, we will add capabilities that describe in
1783 * detail what formats are supported in hardware for what kinds
1784 * of operations.
1785 */
1786
1787typedef enum {
1788 SVGA3D_DEVCAP_3D = 0,
1789 SVGA3D_DEVCAP_MAX_LIGHTS = 1,
1790 SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */
1791 SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3,
1792 SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4,
1793 SVGA3D_DEVCAP_VERTEX_SHADER = 5,
1794 SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6,
1795 SVGA3D_DEVCAP_FRAGMENT_SHADER = 7,
1796 SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8,
1797 SVGA3D_DEVCAP_S23E8_TEXTURES = 9,
1798 SVGA3D_DEVCAP_S10E5_TEXTURES = 10,
1799 SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11,
1800 SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */
1801 SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */
1802 SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */
1803 SVGA3D_DEVCAP_QUERY_TYPES = 15,
1804 SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16,
1805 SVGA3D_DEVCAP_MAX_POINT_SIZE = 17,
1806 SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18,
1807 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19,
1808 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20,
1809 SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21,
1810 SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22,
1811 SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23,
1812 SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24,
1813 SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25,
1814 SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26,
1815 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27,
1816 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28,
1817 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29,
1818 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30,
1819 SVGA3D_DEVCAP_TEXTURE_OPS = 31,
1820 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32,
1821 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33,
1822 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34,
1823 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35,
1824 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36,
1825 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37,
1826 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38,
1827 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39,
1828 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40,
1829 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41,
1830 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42,
1831 SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43,
1832 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44,
1833 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45,
1834 SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46,
1835 SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47,
1836 SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48,
1837 SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49,
1838 SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50,
1839 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51,
1840 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52,
1841 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53,
1842 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54,
1843 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55,
1844 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56,
1845 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57,
1846 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58,
1847 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59,
1848 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60,
1849 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61,
1850 SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63,
1851
1852 /*
1853 * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
1854 * render targets. This does no include the depth or stencil targets.
1855 */
1856 SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64,
1857
1858 SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65,
1859 SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66,
1860 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67,
1861 SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68,
1862 SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69,
1863 SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = 70,
1864 SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = 71,
1865 SVGA3D_DEVCAP_ALPHATOCOVERAGE = 72,
1866 SVGA3D_DEVCAP_SUPERSAMPLE = 73,
1867 SVGA3D_DEVCAP_AUTOGENMIPMAPS = 74,
1868 SVGA3D_DEVCAP_SURFACEFMT_NV12 = 75,
1869 SVGA3D_DEVCAP_SURFACEFMT_AYUV = 76,
1870
1871 /*
1872 * This is the maximum number of SVGA context IDs that the guest
1873 * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
1874 */
1875 SVGA3D_DEVCAP_MAX_CONTEXT_IDS = 77,
1876
1877 /*
1878 * This is the maximum number of SVGA surface IDs that the guest
1879 * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
1880 */
1881 SVGA3D_DEVCAP_MAX_SURFACE_IDS = 78,
1882
1883 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = 79,
1884 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = 80,
1885 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = 81,
1886
1887 SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = 82,
1888 SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = 83,
1889
1890 /*
1891 * Don't add new caps into the previous section; the values in this
1892 * enumeration must not change. You can put new values right before
1893 * SVGA3D_DEVCAP_MAX.
1894 */
1895 SVGA3D_DEVCAP_MAX /* This must be the last index. */
1896} SVGA3dDevCapIndex;
1897
1898typedef union {
1899 bool b;
1900 uint32_t u;
1901 int32_t i;
1902 float f;
1903} SVGA3dDevCapResult;
1904
1905#endif /* !_SVGA3D_REG_H_ */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette