VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 19167

Last change on this file since 19167 was 18841, checked in by vboxsync, 16 years ago

DevE1000: corrected comment, the EMT involvment in PhysWrite happens only once in a while.
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  • Property svn:keywords set to Author Date Id Revision
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1/* $Id: DevE1000.cpp 18841 2009-04-07 22:44:38Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo VLAN checksum offloading support
14 * @todo Flexible Filter / Wakeup (optional?)
15 */
16
17/*
18 * Copyright (C) 2007 Sun Microsystems, Inc.
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 *
28 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
29 * Clara, CA 95054 USA or visit http://www.sun.com if you need
30 * additional information or have any questions.
31 */
32
33
34#define LOG_GROUP LOG_GROUP_DEV_E1000
35
36//#define E1kLogRel(a) LogRel(a)
37#define E1kLogRel(a)
38
39/* Options */
40#define E1K_ITR_ENABLED
41//#define E1K_GLOBAL_MUTEX
42//#define E1K_USE_TX_TIMERS
43//#define E1K_NO_TAD
44//#define E1K_REL_DEBUG
45//#define E1K_INT_STATS
46//#define E1K_REL_STATS
47
48#include <iprt/crc32.h>
49#include <iprt/ctype.h>
50#include <iprt/semaphore.h>
51#include <iprt/string.h>
52#include <VBox/pdmdev.h>
53#include <VBox/tm.h>
54#include <VBox/vm.h>
55#include "../Builtins.h"
56
57#include "DevEEPROM.h"
58#include "DevE1000Phy.h"
59
60/* Little helpers ************************************************************/
61#undef htons
62#undef ntohs
63#undef htonl
64#undef ntohl
65#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
66#define ntohs(x) htons(x)
67#define htonl(x) ASMByteSwapU32(x)
68#define ntohl(x) htonl(x)
69
70#ifndef DEBUG
71# ifdef E1K_REL_STATS
72# undef STAM_COUNTER_INC
73# undef STAM_PROFILE_ADV_START
74# undef STAM_PROFILE_ADV_STOP
75# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
76# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
77# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
78# endif
79# ifdef E1K_REL_DEBUG
80# define DEBUG
81# define E1kLog(a) LogRel(a)
82# define E1kLog2(a) LogRel(a)
83# define E1kLog3(a) LogRel(a)
84//# define E1kLog3(a)
85# else
86# define E1kLog(a)
87# define E1kLog2(a)
88# define E1kLog3(a)
89# endif
90#else
91# define E1kLog(a) Log(a)
92# define E1kLog2(a) Log2(a)
93# define E1kLog3(a) Log3(a)
94//# define E1kLog(a)
95//# define E1kLog2(a)
96//# define E1kLog3(a)
97#endif
98
99//#undef DEBUG
100
101#define INSTANCE(pState) pState->szInstance
102#define IFACE_TO_STATE(pIface, ifaceName) ((E1KSTATE *)((char*)pIface - RT_OFFSETOF(E1KSTATE, ifaceName)))
103#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
104
105#define E1K_INC_CNT32(cnt) \
106do { \
107 if (cnt < UINT32_MAX) \
108 cnt++; \
109} while (0)
110
111#define E1K_ADD_CNT64(cntLo, cntHi, val) \
112do { \
113 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
114 uint64_t tmp = u64Cnt; \
115 u64Cnt += val; \
116 if (tmp > u64Cnt ) \
117 u64Cnt = UINT64_MAX; \
118 cntLo = (uint32_t)u64Cnt; \
119 cntHi = (uint32_t)(u64Cnt >> 32); \
120} while (0)
121
122#ifdef E1K_INT_STATS
123# define E1K_INC_ISTAT_CNT(cnt) ++cnt
124#else /* E1K_INT_STATS */
125# define E1K_INC_ISTAT_CNT(cnt)
126#endif /* E1K_INT_STATS */
127
128
129/*****************************************************************************/
130
131typedef uint32_t E1KCHIP;
132#define E1K_CHIP_82540EM 0
133#define E1K_CHIP_82543GC 1
134#define E1K_CHIP_82545EM 2
135
136struct E1kChips
137{
138 uint16_t uPCIVendorId;
139 uint16_t uPCIDeviceId;
140 uint16_t uPCISubsystemVendorId;
141 uint16_t uPCISubsystemId;
142 const char *pcszName;
143} g_Chips[] =
144{
145 /* Vendor Device SSVendor SubSys Name */
146 { 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
147 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
148 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
149};
150
151
152/* The size of register area mapped to I/O space */
153#define E1K_IOPORT_SIZE 0x8
154/* The size of memory-mapped register area */
155#define E1K_MM_SIZE 0x20000
156
157#define E1K_MAX_TX_PKT_SIZE 16288
158#define E1K_MAX_RX_PKT_SIZE 16384
159
160/*****************************************************************************/
161
162#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
163#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
164#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
165#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
166#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
167
168#define CTRL_SLU 0x00000040
169#define CTRL_MDIO 0x00100000
170#define CTRL_MDC 0x00200000
171#define CTRL_MDIO_DIR 0x01000000
172#define CTRL_MDC_DIR 0x02000000
173#define CTRL_RESET 0x04000000
174#define CTRL_VME 0x40000000
175
176#define STATUS_LU 0x00000002
177
178#define EECD_EE_WIRES 0x0F
179#define EECD_EE_REQ 0x40
180#define EECD_EE_GNT 0x80
181
182#define MDIC_DATA_MASK 0x0000FFFF
183#define MDIC_DATA_SHIFT 0
184#define MDIC_REG_MASK 0x001F0000
185#define MDIC_REG_SHIFT 16
186#define MDIC_PHY_MASK 0x03E00000
187#define MDIC_PHY_SHIFT 21
188#define MDIC_OP_WRITE 0x04000000
189#define MDIC_OP_READ 0x08000000
190#define MDIC_READY 0x10000000
191#define MDIC_INT_EN 0x20000000
192#define MDIC_ERROR 0x40000000
193
194#define TCTL_EN 0x00000002
195#define TCTL_PSP 0x00000008
196
197#define RCTL_EN 0x00000002
198#define RCTL_UPE 0x00000008
199#define RCTL_MPE 0x00000010
200#define RCTL_LPE 0x00000020
201#define RCTL_LBM_MASK 0x000000C0
202#define RCTL_LBM_SHIFT 6
203#define RCTL_RDMTS_MASK 0x00000300
204#define RCTL_RDMTS_SHIFT 8
205#define RCTL_LBM_TCVR 3
206#define RCTL_MO_MASK 0x00003000
207#define RCTL_MO_SHIFT 12
208#define RCTL_BAM 0x00008000
209#define RCTL_BSIZE_MASK 0x00030000
210#define RCTL_BSIZE_SHIFT 16
211#define RCTL_VFE 0x00040000
212#define RCTL_BSEX 0x02000000
213#define RCTL_SECRC 0x04000000
214
215#define ICR_TXDW 0x00000001
216#define ICR_TXQE 0x00000002
217#define ICR_LSC 0x00000004
218#define ICR_RXDMT0 0x00000010
219#define ICR_RXT0 0x00000080
220#define ICR_TXD_LOW 0x00008000
221#define RDTR_FPD 0x80000000
222
223#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
224typedef struct
225{
226 unsigned rxa : 7;
227 unsigned rxa_r : 9;
228 unsigned txa : 16;
229} PBAST;
230AssertCompileSize(PBAST, 4);
231
232#define TXDCTL_WTHRESH_MASK 0x003F0000
233#define TXDCTL_WTHRESH_SHIFT 16
234#define TXDCTL_LWTHRESH_MASK 0xFE000000
235#define TXDCTL_LWTHRESH_SHIFT 25
236
237#define RXCSUM_PCSS_MASK 0x000000FF
238#define RXCSUM_PCSS_SHIFT 0
239
240/* Register access macros ****************************************************/
241#define CTRL pState->auRegs[CTRL_IDX]
242#define STATUS pState->auRegs[STATUS_IDX]
243#define EECD pState->auRegs[EECD_IDX]
244#define EERD pState->auRegs[EERD_IDX]
245#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
246#define FLA pState->auRegs[FLA_IDX]
247#define MDIC pState->auRegs[MDIC_IDX]
248#define FCAL pState->auRegs[FCAL_IDX]
249#define FCAH pState->auRegs[FCAH_IDX]
250#define FCT pState->auRegs[FCT_IDX]
251#define VET pState->auRegs[VET_IDX]
252#define ICR pState->auRegs[ICR_IDX]
253#define ITR pState->auRegs[ITR_IDX]
254#define ICS pState->auRegs[ICS_IDX]
255#define IMS pState->auRegs[IMS_IDX]
256#define IMC pState->auRegs[IMC_IDX]
257#define RCTL pState->auRegs[RCTL_IDX]
258#define FCTTV pState->auRegs[FCTTV_IDX]
259#define TXCW pState->auRegs[TXCW_IDX]
260#define RXCW pState->auRegs[RXCW_IDX]
261#define TCTL pState->auRegs[TCTL_IDX]
262#define TIPG pState->auRegs[TIPG_IDX]
263#define AIFS pState->auRegs[AIFS_IDX]
264#define LEDCTL pState->auRegs[LEDCTL_IDX]
265#define PBA pState->auRegs[PBA_IDX]
266#define FCRTL pState->auRegs[FCRTL_IDX]
267#define FCRTH pState->auRegs[FCRTH_IDX]
268#define RDFH pState->auRegs[RDFH_IDX]
269#define RDFT pState->auRegs[RDFT_IDX]
270#define RDFHS pState->auRegs[RDFHS_IDX]
271#define RDFTS pState->auRegs[RDFTS_IDX]
272#define RDFPC pState->auRegs[RDFPC_IDX]
273#define RDBAL pState->auRegs[RDBAL_IDX]
274#define RDBAH pState->auRegs[RDBAH_IDX]
275#define RDLEN pState->auRegs[RDLEN_IDX]
276#define RDH pState->auRegs[RDH_IDX]
277#define RDT pState->auRegs[RDT_IDX]
278#define RDTR pState->auRegs[RDTR_IDX]
279#define RXDCTL pState->auRegs[RXDCTL_IDX]
280#define RADV pState->auRegs[RADV_IDX]
281#define RSRPD pState->auRegs[RSRPD_IDX]
282#define TXDMAC pState->auRegs[TXDMAC_IDX]
283#define TDFH pState->auRegs[TDFH_IDX]
284#define TDFT pState->auRegs[TDFT_IDX]
285#define TDFHS pState->auRegs[TDFHS_IDX]
286#define TDFTS pState->auRegs[TDFTS_IDX]
287#define TDFPC pState->auRegs[TDFPC_IDX]
288#define TDBAL pState->auRegs[TDBAL_IDX]
289#define TDBAH pState->auRegs[TDBAH_IDX]
290#define TDLEN pState->auRegs[TDLEN_IDX]
291#define TDH pState->auRegs[TDH_IDX]
292#define TDT pState->auRegs[TDT_IDX]
293#define TIDV pState->auRegs[TIDV_IDX]
294#define TXDCTL pState->auRegs[TXDCTL_IDX]
295#define TADV pState->auRegs[TADV_IDX]
296#define TSPMT pState->auRegs[TSPMT_IDX]
297#define CRCERRS pState->auRegs[CRCERRS_IDX]
298#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
299#define SYMERRS pState->auRegs[SYMERRS_IDX]
300#define RXERRC pState->auRegs[RXERRC_IDX]
301#define MPC pState->auRegs[MPC_IDX]
302#define SCC pState->auRegs[SCC_IDX]
303#define ECOL pState->auRegs[ECOL_IDX]
304#define MCC pState->auRegs[MCC_IDX]
305#define LATECOL pState->auRegs[LATECOL_IDX]
306#define COLC pState->auRegs[COLC_IDX]
307#define DC pState->auRegs[DC_IDX]
308#define TNCRS pState->auRegs[TNCRS_IDX]
309#define SEC pState->auRegs[SEC_IDX]
310#define CEXTERR pState->auRegs[CEXTERR_IDX]
311#define RLEC pState->auRegs[RLEC_IDX]
312#define XONRXC pState->auRegs[XONRXC_IDX]
313#define XONTXC pState->auRegs[XONTXC_IDX]
314#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
315#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
316#define FCRUC pState->auRegs[FCRUC_IDX]
317#define PRC64 pState->auRegs[PRC64_IDX]
318#define PRC127 pState->auRegs[PRC127_IDX]
319#define PRC255 pState->auRegs[PRC255_IDX]
320#define PRC511 pState->auRegs[PRC511_IDX]
321#define PRC1023 pState->auRegs[PRC1023_IDX]
322#define PRC1522 pState->auRegs[PRC1522_IDX]
323#define GPRC pState->auRegs[GPRC_IDX]
324#define BPRC pState->auRegs[BPRC_IDX]
325#define MPRC pState->auRegs[MPRC_IDX]
326#define GPTC pState->auRegs[GPTC_IDX]
327#define GORCL pState->auRegs[GORCL_IDX]
328#define GORCH pState->auRegs[GORCH_IDX]
329#define GOTCL pState->auRegs[GOTCL_IDX]
330#define GOTCH pState->auRegs[GOTCH_IDX]
331#define RNBC pState->auRegs[RNBC_IDX]
332#define RUC pState->auRegs[RUC_IDX]
333#define RFC pState->auRegs[RFC_IDX]
334#define ROC pState->auRegs[ROC_IDX]
335#define RJC pState->auRegs[RJC_IDX]
336#define MGTPRC pState->auRegs[MGTPRC_IDX]
337#define MGTPDC pState->auRegs[MGTPDC_IDX]
338#define MGTPTC pState->auRegs[MGTPTC_IDX]
339#define TORL pState->auRegs[TORL_IDX]
340#define TORH pState->auRegs[TORH_IDX]
341#define TOTL pState->auRegs[TOTL_IDX]
342#define TOTH pState->auRegs[TOTH_IDX]
343#define TPR pState->auRegs[TPR_IDX]
344#define TPT pState->auRegs[TPT_IDX]
345#define PTC64 pState->auRegs[PTC64_IDX]
346#define PTC127 pState->auRegs[PTC127_IDX]
347#define PTC255 pState->auRegs[PTC255_IDX]
348#define PTC511 pState->auRegs[PTC511_IDX]
349#define PTC1023 pState->auRegs[PTC1023_IDX]
350#define PTC1522 pState->auRegs[PTC1522_IDX]
351#define MPTC pState->auRegs[MPTC_IDX]
352#define BPTC pState->auRegs[BPTC_IDX]
353#define TSCTC pState->auRegs[TSCTC_IDX]
354#define TSCTFC pState->auRegs[TSCTFC_IDX]
355#define RXCSUM pState->auRegs[RXCSUM_IDX]
356#define WUC pState->auRegs[WUC_IDX]
357#define WUFC pState->auRegs[WUFC_IDX]
358#define WUS pState->auRegs[WUS_IDX]
359#define MANC pState->auRegs[MANC_IDX]
360#define IPAV pState->auRegs[IPAV_IDX]
361#define WUPL pState->auRegs[WUPL_IDX]
362
363/**
364 * Indices of memory-mapped registers in register table
365 */
366typedef enum
367{
368 CTRL_IDX,
369 STATUS_IDX,
370 EECD_IDX,
371 EERD_IDX,
372 CTRL_EXT_IDX,
373 FLA_IDX,
374 MDIC_IDX,
375 FCAL_IDX,
376 FCAH_IDX,
377 FCT_IDX,
378 VET_IDX,
379 ICR_IDX,
380 ITR_IDX,
381 ICS_IDX,
382 IMS_IDX,
383 IMC_IDX,
384 RCTL_IDX,
385 FCTTV_IDX,
386 TXCW_IDX,
387 RXCW_IDX,
388 TCTL_IDX,
389 TIPG_IDX,
390 AIFS_IDX,
391 LEDCTL_IDX,
392 PBA_IDX,
393 FCRTL_IDX,
394 FCRTH_IDX,
395 RDFH_IDX,
396 RDFT_IDX,
397 RDFHS_IDX,
398 RDFTS_IDX,
399 RDFPC_IDX,
400 RDBAL_IDX,
401 RDBAH_IDX,
402 RDLEN_IDX,
403 RDH_IDX,
404 RDT_IDX,
405 RDTR_IDX,
406 RXDCTL_IDX,
407 RADV_IDX,
408 RSRPD_IDX,
409 TXDMAC_IDX,
410 TDFH_IDX,
411 TDFT_IDX,
412 TDFHS_IDX,
413 TDFTS_IDX,
414 TDFPC_IDX,
415 TDBAL_IDX,
416 TDBAH_IDX,
417 TDLEN_IDX,
418 TDH_IDX,
419 TDT_IDX,
420 TIDV_IDX,
421 TXDCTL_IDX,
422 TADV_IDX,
423 TSPMT_IDX,
424 CRCERRS_IDX,
425 ALGNERRC_IDX,
426 SYMERRS_IDX,
427 RXERRC_IDX,
428 MPC_IDX,
429 SCC_IDX,
430 ECOL_IDX,
431 MCC_IDX,
432 LATECOL_IDX,
433 COLC_IDX,
434 DC_IDX,
435 TNCRS_IDX,
436 SEC_IDX,
437 CEXTERR_IDX,
438 RLEC_IDX,
439 XONRXC_IDX,
440 XONTXC_IDX,
441 XOFFRXC_IDX,
442 XOFFTXC_IDX,
443 FCRUC_IDX,
444 PRC64_IDX,
445 PRC127_IDX,
446 PRC255_IDX,
447 PRC511_IDX,
448 PRC1023_IDX,
449 PRC1522_IDX,
450 GPRC_IDX,
451 BPRC_IDX,
452 MPRC_IDX,
453 GPTC_IDX,
454 GORCL_IDX,
455 GORCH_IDX,
456 GOTCL_IDX,
457 GOTCH_IDX,
458 RNBC_IDX,
459 RUC_IDX,
460 RFC_IDX,
461 ROC_IDX,
462 RJC_IDX,
463 MGTPRC_IDX,
464 MGTPDC_IDX,
465 MGTPTC_IDX,
466 TORL_IDX,
467 TORH_IDX,
468 TOTL_IDX,
469 TOTH_IDX,
470 TPR_IDX,
471 TPT_IDX,
472 PTC64_IDX,
473 PTC127_IDX,
474 PTC255_IDX,
475 PTC511_IDX,
476 PTC1023_IDX,
477 PTC1522_IDX,
478 MPTC_IDX,
479 BPTC_IDX,
480 TSCTC_IDX,
481 TSCTFC_IDX,
482 RXCSUM_IDX,
483 WUC_IDX,
484 WUFC_IDX,
485 WUS_IDX,
486 MANC_IDX,
487 IPAV_IDX,
488 WUPL_IDX,
489 MTA_IDX,
490 RA_IDX,
491 VFTA_IDX,
492 IP4AT_IDX,
493 IP6AT_IDX,
494 WUPM_IDX,
495 FFLT_IDX,
496 FFMT_IDX,
497 FFVT_IDX,
498 PBM_IDX,
499 RA_82542_IDX,
500 MTA_82542_IDX,
501 VFTA_82542_IDX,
502 E1K_NUM_OF_REGS
503} E1kRegIndex;
504
505#define E1K_NUM_OF_32BIT_REGS MTA_IDX
506
507
508/**
509 * Define E1000-specific EEPROM layout.
510 */
511class E1kEEPROM
512{
513 public:
514 EEPROM93C46 eeprom;
515
516#ifdef IN_RING3
517 /**
518 * Initialize EEPROM content.
519 *
520 * @param macAddr MAC address of E1000.
521 */
522 void init(RTMAC &macAddr)
523 {
524 eeprom.init();
525 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
526 eeprom.m_au16Data[0x04] = 0xFFFF;
527 /*
528 * bit 3 - full support for power management
529 * bit 10 - full duplex
530 */
531 eeprom.m_au16Data[0x0A] = 0x4408;
532 eeprom.m_au16Data[0x0B] = 0x001E;
533 eeprom.m_au16Data[0x0C] = 0x8086;
534 eeprom.m_au16Data[0x0D] = 0x100E;
535 eeprom.m_au16Data[0x0E] = 0x8086;
536 eeprom.m_au16Data[0x0F] = 0x3040;
537 eeprom.m_au16Data[0x21] = 0x7061;
538 eeprom.m_au16Data[0x22] = 0x280C;
539 eeprom.m_au16Data[0x23] = 0x00C8;
540 eeprom.m_au16Data[0x24] = 0x00C8;
541 eeprom.m_au16Data[0x2F] = 0x0602;
542 updateChecksum();
543 };
544
545 /**
546 * Compute the checksum as required by E1000 and store it
547 * in the last word.
548 */
549 void updateChecksum()
550 {
551 uint16_t u16Checksum = 0;
552
553 for (int i = 0; i < eeprom.SIZE-1; i++)
554 u16Checksum += eeprom.m_au16Data[i];
555 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
556 };
557
558 /**
559 * First 6 bytes of EEPROM contain MAC address.
560 *
561 * @returns MAC address of E1000.
562 */
563 void getMac(PRTMAC pMac)
564 {
565 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
566 };
567
568 uint32_t read()
569 {
570 return eeprom.read();
571 }
572
573 void write(uint32_t u32Wires)
574 {
575 eeprom.write(u32Wires);
576 }
577#endif /* IN_RING3 */
578};
579
580struct E1kRxDStatus
581{
582 /* Descriptor Status field */
583 unsigned fDD : 1;
584 unsigned fEOP : 1;
585 unsigned fIXSM : 1;
586 unsigned fVP : 1;
587 unsigned : 1;
588 unsigned fTCPCS : 1;
589 unsigned fIPCS : 1;
590 unsigned fPIF : 1;
591 /* Descriptor Errors field */
592 unsigned fCE : 1;
593 unsigned : 4;
594 unsigned fTCPE : 1;
595 unsigned fIPE : 1;
596 unsigned fRXE : 1;
597 /* Descriptor Special field */
598 unsigned u12VLAN : 12;
599 unsigned fCFI : 1;
600 unsigned u3PRI : 3;
601};
602typedef struct E1kRxDStatus E1KRXDST;
603
604struct E1kRxDesc_st
605{
606 uint64_t u64BufAddr; /**< Address of data buffer */
607 uint16_t u16Length; /**< Length of data in buffer */
608 uint16_t u16Checksum; /**< Packet checksum */
609 E1KRXDST status;
610};
611typedef struct E1kRxDesc_st E1KRXDESC;
612AssertCompileSize(E1KRXDESC, 16);
613
614#define E1K_DTYP_LEGACY -1
615#define E1K_DTYP_CONTEXT 0
616#define E1K_DTYP_DATA 1
617
618struct E1kTDLegacy
619{
620 uint64_t u64BufAddr; /**< Address of data buffer */
621 struct TDLCmd_st
622 {
623 unsigned u16Length : 16;
624 unsigned u8CSO : 8;
625 /* CMD field : 8 */
626 unsigned fEOP : 1;
627 unsigned fIFCS : 1;
628 unsigned fIC : 1;
629 unsigned fRS : 1;
630 unsigned fRSV : 1;
631 unsigned fDEXT : 1;
632 unsigned fVLE : 1;
633 unsigned fIDE : 1;
634 } cmd;
635 struct TDLDw3_st
636 {
637 /* STA field */
638 unsigned fDD : 1;
639 unsigned fEC : 1;
640 unsigned fLC : 1;
641 unsigned fTURSV : 1;
642 /* RSV field */
643 unsigned u4RSV : 4;
644 /* CSS field */
645 unsigned u8CSS : 8;
646 /* Special field*/
647 unsigned u12VLAN : 12;
648 unsigned fCFI : 1;
649 unsigned u3PRI : 3;
650 } dw3;
651};
652
653struct E1kTDContext
654{
655 struct CheckSum_st
656 {
657 unsigned u8CSS : 8;
658 unsigned u8CSO : 8;
659 unsigned u16CSE : 16;
660 } ip;
661 struct CheckSum_st tu;
662 struct TDCDw2_st
663 {
664 unsigned u20PAYLEN : 20;
665 unsigned u4DTYP : 4;
666 /* CMD field : 8 */
667 unsigned fTCP : 1;
668 unsigned fIP : 1;
669 unsigned fTSE : 1;
670 unsigned fRS : 1;
671 unsigned fRSV1 : 1;
672 unsigned fDEXT : 1;
673 unsigned fRSV2 : 1;
674 unsigned fIDE : 1;
675 } dw2;
676 struct TDCDw3_st
677 {
678 unsigned fDD : 1;
679 unsigned u7RSV : 7;
680 unsigned u8HDRLEN : 8;
681 unsigned u16MSS : 16;
682 } dw3;
683};
684typedef struct E1kTDContext E1KTXCTX;
685
686struct E1kTDData
687{
688 uint64_t u64BufAddr; /**< Address of data buffer */
689 struct TDDCmd_st
690 {
691 unsigned u20DTALEN : 20;
692 unsigned u4DTYP : 4;
693 /* DCMD field : 8 */
694 unsigned fEOP : 1;
695 unsigned fIFCS : 1;
696 unsigned fTSE : 1;
697 unsigned fRS : 1;
698 unsigned fRSV : 1;
699 unsigned fDEXT : 1;
700 unsigned fVLE : 1;
701 unsigned fIDE : 1;
702 } cmd;
703 struct TDDDw3_st
704 {
705 /* STA field */
706 unsigned fDD : 1;
707 unsigned fEC : 1;
708 unsigned fLC : 1;
709 unsigned fTURSV : 1;
710 /* RSV field */
711 unsigned u4RSV : 4;
712 /* POPTS field */
713 unsigned fIXSM : 1;
714 unsigned fTXSM : 1;
715 unsigned u6RSV : 6;
716 /* Special field*/
717 unsigned u12VLAN : 12;
718 unsigned fCFI : 1;
719 unsigned u3PRI : 3;
720 } dw3;
721};
722typedef struct E1kTDData E1KTXDAT;
723
724union E1kTxDesc
725{
726 struct E1kTDLegacy legacy;
727 struct E1kTDContext context;
728 struct E1kTDData data;
729};
730typedef union E1kTxDesc E1KTXDESC;
731AssertCompileSize(E1KTXDESC, 16);
732
733#define RA_CTL_AS 0x0003
734#define RA_CTL_AV 0x8000
735
736union E1kRecAddr
737{
738 uint32_t au32[32];
739 struct RAArray
740 {
741 uint8_t addr[6];
742 uint16_t ctl;
743 } array[16];
744};
745typedef struct E1kRecAddr::RAArray E1KRAELEM;
746typedef union E1kRecAddr E1KRA;
747AssertCompileSize(E1KRA, 8*16);
748
749#define E1K_IP_RF 0x8000 /* reserved fragment flag */
750#define E1K_IP_DF 0x4000 /* dont fragment flag */
751#define E1K_IP_MF 0x2000 /* more fragments flag */
752#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
753
754/** @todo use+extend RTNETIPV4 */
755struct E1kIpHeader
756{
757 /* type of service / version / header length */
758 uint16_t tos_ver_hl;
759 /* total length */
760 uint16_t total_len;
761 /* identification */
762 uint16_t ident;
763 /* fragment offset field */
764 uint16_t offset;
765 /* time to live / protocol*/
766 uint16_t ttl_proto;
767 /* checksum */
768 uint16_t chksum;
769 /* source IP address */
770 uint32_t src;
771 /* destination IP address */
772 uint32_t dest;
773};
774AssertCompileSize(struct E1kIpHeader, 20);
775
776#define E1K_TCP_FIN 0x01U
777#define E1K_TCP_SYN 0x02U
778#define E1K_TCP_RST 0x04U
779#define E1K_TCP_PSH 0x08U
780#define E1K_TCP_ACK 0x10U
781#define E1K_TCP_URG 0x20U
782#define E1K_TCP_ECE 0x40U
783#define E1K_TCP_CWR 0x80U
784
785#define E1K_TCP_FLAGS 0x3fU
786
787/** @todo use+extend RTNETTCP */
788struct E1kTcpHeader
789{
790 uint16_t src;
791 uint16_t dest;
792 uint32_t seqno;
793 uint32_t ackno;
794 uint16_t hdrlen_flags;
795 uint16_t wnd;
796 uint16_t chksum;
797 uint16_t urgp;
798};
799AssertCompileSize(struct E1kTcpHeader, 20);
800
801
802#define E1K_SAVEDSTATE_VERSION 1
803
804/**
805 * Device state structure. Holds the current state of device.
806 */
807struct E1kState_st
808{
809 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
810 PDMIBASE IBase;
811 PDMINETWORKPORT INetworkPort;
812 PDMINETWORKCONFIG INetworkConfig;
813 PDMILEDPORTS ILeds; /**< LED interface */
814 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
815 R3PTRTYPE(PPDMINETWORKCONNECTOR) pDrv; /**< Connector of attached network driver. */
816 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
817
818 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
819 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
820 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
821 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
822 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
823 PTMTIMERR3 pTIDTimerR3; /**< Tranmsit Interrupt Delay Timer - R3. */
824 PTMTIMERR3 pTADTimerR3; /**< Tranmsit Absolute Delay Timer - R3. */
825 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
826
827 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
828 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
829 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
830 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
831 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
832 PTMTIMERR0 pTIDTimerR0; /**< Tranmsit Interrupt Delay Timer - R0. */
833 PTMTIMERR0 pTADTimerR0; /**< Tranmsit Absolute Delay Timer - R0. */
834 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
835
836 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
837 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
838 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
839 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
840 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
841 PTMTIMERRC pTIDTimerRC; /**< Tranmsit Interrupt Delay Timer - RC. */
842 PTMTIMERRC pTADTimerRC; /**< Tranmsit Absolute Delay Timer - RC. */
843 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
844
845 PTMTIMERR3 pLUTimer; /**< Link Up(/Restore) Timer. */
846 PPDMTHREAD pTxThread; /**< Transmit thread. */
847 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
848#ifndef E1K_GLOBAL_MUTEX
849 PDMCRITSECT csRx; /**< RX Critical section. */
850// PDMCRITSECT csTx; /**< TX Critical section. */
851#endif
852 /** Transmit thread blocker. */
853 RTSEMEVENT hTxSem;
854 /** Base address of memory-mapped registers. */
855 RTGCPHYS addrMMReg;
856 /** MAC address obtained from the configuration. */
857 RTMAC macAddress;
858 /** Base port of I/O space region. */
859 RTIOPORT addrIOPort;
860 /** EMT: */
861 PCIDEVICE pciDevice;
862 /** EMT: Last time the interrupt was acknowledged. */
863 uint64_t u64AckedAt;
864 /** All: Used for eliminating spurious interrupts. */
865 bool fIntRaised;
866 /** EMT: */
867 bool fCableConnected;
868 /** EMT: */
869 bool fR0Enabled;
870 /** EMT: */
871 bool fGCEnabled;
872
873 /* All: Device register storage. */
874 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
875 /** TX/RX: Status LED. */
876 PDMLED led;
877 /** TX/RX: Number of packet being sent/received to show in debug log. */
878 uint32_t u32PktNo;
879
880 /** EMT: Offset of the register to be read via IO. */
881 uint32_t uSelectedReg;
882 /** EMT: Multicast Table Array. */
883 uint32_t auMTA[128];
884 /** EMT: Receive Address registers. */
885 E1KRA aRecAddr;
886 /** EMT: VLAN filter table array. */
887 uint32_t auVFTA[128];
888 /** EMT: Receive buffer size. */
889 uint16_t u16RxBSize;
890 /** EMT: Locked state -- no state alteration possible. */
891 bool fLocked;
892 /** EMT: */
893 bool fDelayInts;
894 /** All: */
895 bool fIntMaskUsed;
896
897 /** N/A: */
898 bool volatile fMaybeOutOfSpace;
899 /** EMT: Gets signalled when more RX descriptors become available. */
900 RTSEMEVENT hEventMoreRxDescAvail;
901
902 /** TX: Context used for TCP segmentation packets. */
903 E1KTXCTX contextTSE;
904 /** TX: Context used for ordinary packets. */
905 E1KTXCTX contextNormal;
906 /** TX: Transmit packet buffer. */
907 uint8_t aTxPacket[E1K_MAX_TX_PKT_SIZE];
908 /** TX: Number of bytes assembled in TX packet buffer. */
909 uint16_t u16TxPktLen;
910 /** TX: IP checksum has to be inserted if true. */
911 bool fIPcsum;
912 /** TX: TCP/UDP checksum has to be inserted if true. */
913 bool fTCPcsum;
914 /** TX: Number of payload bytes remaining in TSE context. */
915 uint32_t u32PayRemain;
916 /** TX: Number of header bytes remaining in TSE context. */
917 uint16_t u16HdrRemain;
918 /** TX: Flags from template header. */
919 uint16_t u16SavedFlags;
920 /** TX: Partial checksum from template header. */
921 uint32_t u32SavedCsum;
922 /** ?: Emulated controller type. */
923 E1KCHIP eChip;
924 uint32_t alignmentFix;
925
926 /** EMT: EEPROM emulation */
927 E1kEEPROM eeprom;
928 /** EMT: Physical interface emulation. */
929 PHY phy;
930
931 STAMCOUNTER StatReceiveBytes;
932 STAMCOUNTER StatTransmitBytes;
933#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
934 STAMPROFILEADV StatMMIOReadGC;
935 STAMPROFILEADV StatMMIOReadHC;
936 STAMPROFILEADV StatMMIOWriteGC;
937 STAMPROFILEADV StatMMIOWriteHC;
938 STAMPROFILEADV StatEEPROMRead;
939 STAMPROFILEADV StatEEPROMWrite;
940 STAMPROFILEADV StatIOReadGC;
941 STAMPROFILEADV StatIOReadHC;
942 STAMPROFILEADV StatIOWriteGC;
943 STAMPROFILEADV StatIOWriteHC;
944 STAMPROFILEADV StatLateIntTimer;
945 STAMCOUNTER StatLateInts;
946 STAMCOUNTER StatIntsRaised;
947 STAMCOUNTER StatIntsPrevented;
948 STAMPROFILEADV StatReceive;
949 STAMPROFILEADV StatReceiveFilter;
950 STAMPROFILEADV StatReceiveStore;
951 STAMPROFILEADV StatTransmit;
952 STAMPROFILEADV StatTransmitSend;
953 STAMPROFILE StatRxOverflow;
954 STAMCOUNTER StatRxOverflowWakeup;
955 STAMCOUNTER StatTxDescLegacy;
956 STAMCOUNTER StatTxDescData;
957 STAMCOUNTER StatTxDescTSEData;
958 STAMCOUNTER StatPHYAccesses;
959
960#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
961
962#ifdef E1K_INT_STATS
963 /* Internal stats */
964 uint32_t uStatInt;
965 uint32_t uStatIntTry;
966 int32_t uStatIntLower;
967 uint32_t uStatIntDly;
968 int32_t iStatIntLost;
969 int32_t iStatIntLostOne;
970 uint32_t uStatDisDly;
971 uint32_t uStatIntSkip;
972 uint32_t uStatIntLate;
973 uint32_t uStatIntMasked;
974 uint32_t uStatIntEarly;
975 uint32_t uStatIntRx;
976 uint32_t uStatIntTx;
977 uint32_t uStatIntICS;
978 uint32_t uStatIntRDTR;
979 uint32_t uStatIntRXDMT0;
980 uint32_t uStatIntTXQE;
981 uint32_t uStatTxNoRS;
982 uint32_t uStatTxIDE;
983 uint32_t uStatTAD;
984 uint32_t uStatTID;
985 uint32_t uStatRAD;
986 uint32_t uStatRID;
987 uint32_t uStatRxFrm;
988 uint32_t uStatTxFrm;
989 uint32_t uStatDescCtx;
990 uint32_t uStatDescDat;
991 uint32_t uStatDescLeg;
992#endif /* E1K_INT_STATS */
993};
994typedef struct E1kState_st E1KSTATE;
995
996#ifndef VBOX_DEVICE_STRUCT_TESTCASE
997
998/* Forward declarations ******************************************************/
999__BEGIN_DECLS
1000PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1001PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1002PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
1003PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
1004__END_DECLS
1005
1006static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1007static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1008static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1009static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1010static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1011#if 0 /* unused */
1012static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1013#endif
1014static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1015static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1016static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1017static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1018static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1019static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1020static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1021static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1022static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1023static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1024static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1025static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1026static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1027static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1028static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1029static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1030static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1031static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1032static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1033static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1034
1035/**
1036 * Register map table.
1037 *
1038 * Override fn_read and fn_write to get register-specific behavior.
1039 */
1040const static struct E1kRegMap_st
1041{
1042 /** Register offset in the register space. */
1043 uint32_t offset;
1044 /** Size in bytes. Registers of size > 4 are in fact tables. */
1045 uint32_t size;
1046 /** Readable bits. */
1047 uint32_t readable;
1048 /** Writable bits. */
1049 uint32_t writable;
1050 /** Read callback. */
1051 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1052 /** Write callback. */
1053 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1054 /** Abbreviated name. */
1055 const char *abbrev;
1056 /** Full name. */
1057 const char *name;
1058} s_e1kRegMap[E1K_NUM_OF_REGS] =
1059{
1060 /* offset size read mask write mask read callback write callback abbrev full name */
1061 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1062 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1063 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1064 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1065 { 0x00014, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "EERD" , "EEPROM Read" },
1066 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1067 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1068 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1069 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1070 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1071 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1072 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1073 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1074 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1075 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1076 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1077 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1078 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1079 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1080 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1081 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1082 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1083 { 0x00410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TIPG" , "Transmit IPG" },
1084 { 0x00458, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "AIFS" , "Adaptive IFS Throttle - AIT" },
1085 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1086 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1087 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1088 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1089 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1090 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1091 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1092 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1093 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1094 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1095 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1096 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1097 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1098 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1099 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1100 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1101 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1102 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1103 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1104 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1105 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1106 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1107 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1108 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1109 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1110 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1111 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1112 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1113 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1114 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1115 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1116 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1117 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSPMT" , "TCP Segmentation Pad and Threshold" },
1118 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1119 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1120 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1121 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1122 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1123 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1124 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1125 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1126 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1127 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1128 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1129 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1130 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1131 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1132 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1133 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1134 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1135 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1136 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1137 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1138 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1139 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1140 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1141 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1142 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1143 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1144 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1145 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1146 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1147 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1148 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1149 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1150 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1151 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1152 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1153 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1154 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1155 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1156 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1157 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1158 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1159 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1160 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1161 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1162 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1163 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1164 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1165 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1166 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1167 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1168 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1169 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1170 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1171 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1172 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1173 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1174 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1175 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1176 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1177 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1178 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1179 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1180 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1181 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1182 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1183 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1184 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1185 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1186 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1187 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1188 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1189 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1190 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1191 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1192 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1193 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1194 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1195 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1196};
1197
1198#ifdef DEBUG
1199/**
1200 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1201 *
1202 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1203 *
1204 * @returns The buffer.
1205 *
1206 * @param u32 The word to convert into string.
1207 * @param mask Selects which bytes to convert.
1208 * @param buf Where to put the result.
1209 */
1210static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1211{
1212 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1213 {
1214 if (mask & 0xF)
1215 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1216 else
1217 *ptr = '.';
1218 }
1219 buf[8] = 0;
1220 return buf;
1221}
1222
1223/**
1224 * Returns timer name for debug purposes.
1225 *
1226 * @returns The timer name.
1227 *
1228 * @param pState The device state structure.
1229 * @param pTimer The timer to get the name for.
1230 */
1231DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1232{
1233 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1234 return "TID";
1235 if (pTimer == pState->CTX_SUFF(pTADTimer))
1236 return "TAD";
1237 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1238 return "RID";
1239 if (pTimer == pState->CTX_SUFF(pRADTimer))
1240 return "RAD";
1241 if (pTimer == pState->CTX_SUFF(pIntTimer))
1242 return "Int";
1243 return "unknown";
1244}
1245#endif /* DEBUG */
1246
1247/**
1248 * Arm a timer.
1249 *
1250 * @param pState Pointer to the device state structure.
1251 * @param pTimer Pointer to the timer.
1252 * @param uExpireIn Expiration interval in microseconds.
1253 */
1254DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1255{
1256 if (pState->fLocked)
1257 return;
1258
1259 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1260 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1261 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1262 TMTimerGet(pTimer));
1263}
1264
1265/**
1266 * Cancel a timer.
1267 *
1268 * @param pState Pointer to the device state structure.
1269 * @param pTimer Pointer to the timer.
1270 */
1271DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1272{
1273 E1kLog2(("%s Stopping %s timer...\n",
1274 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1275 int rc = TMTimerStop(pTimer);
1276 if (RT_FAILURE(rc))
1277 {
1278 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1279 INSTANCE(pState), rc));
1280 }
1281}
1282
1283#ifdef E1K_GLOBAL_MUTEX
1284DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1285{
1286 return VINF_SUCCESS;
1287}
1288
1289DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1290{
1291}
1292
1293#define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1294#define e1kCsRxLeave(ps)
1295
1296#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1297#define e1kCsTxLeave(ps)
1298
1299
1300DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1301{
1302 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1303 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1304 {
1305 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1306 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1307 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1308 "%s Failed to enter critical section, rc=%Rrc\n",
1309 INSTANCE(pState), rc);
1310 }
1311 else
1312 {
1313 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1314 }
1315 return rc;
1316}
1317
1318DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1319{
1320 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1321 PDMCritSectLeave(&pState->cs);
1322}
1323
1324#else /* !E1K_GLOBAL_MUTEX */
1325#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1326#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1327
1328#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1329#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1330
1331#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1332#define e1kCsTxLeave(ps)
1333//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1334//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1335
1336#if 0
1337DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1338{
1339 int rc = PDMCritSectEnter(pCs, iBusyRc);
1340 if (RT_FAILURE(rc))
1341 {
1342 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1343 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1344 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1345 "%s Failed to enter critical section, rc=%Rrc\n",
1346 INSTANCE(pState), rc);
1347 }
1348 else
1349 {
1350 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1351 }
1352 return RT_SUCCESS(rc);
1353}
1354
1355DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1356{
1357 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1358 PDMCritSectLeave(&pState->cs);
1359}
1360#endif
1361DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1362{
1363 return VINF_SUCCESS;
1364}
1365
1366DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1367{
1368}
1369#endif /* !E1K_GLOBAL_MUTEX */
1370
1371#ifdef IN_RING3
1372/**
1373 * Wakeup the RX thread.
1374 */
1375static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1376{
1377 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1378 if ( pState->fMaybeOutOfSpace
1379 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1380 {
1381 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1382 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1383 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1384 }
1385}
1386
1387/**
1388 * Compute Internet checksum.
1389 *
1390 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1391 *
1392 * @param pState The device state structure.
1393 * @param cpPacket The packet.
1394 * @param cb The size of the packet.
1395 * @param cszText A string denoting direction of packet transfer.
1396 *
1397 * @return The 1's complement of the 1's complement sum.
1398 *
1399 * @thread E1000_TX
1400 */
1401static DECLCALLBACK(uint16_t) e1kCSum16(const void *pvBuf, size_t cb)
1402{
1403 uint32_t csum = 0;
1404 uint16_t *pu16 = (uint16_t *)pvBuf;
1405
1406 while (cb > 1)
1407 {
1408 csum += *pu16++;
1409 cb -= 2;
1410 }
1411 if (cb)
1412 csum += *(uint8_t*)pu16;
1413 while (csum >> 16)
1414 csum = (csum >> 16) + (csum & 0xFFFF);
1415 return ~csum;
1416}
1417
1418/**
1419 * Dump a packet to debug log.
1420 *
1421 * @param pState The device state structure.
1422 * @param cpPacket The packet.
1423 * @param cb The size of the packet.
1424 * @param cszText A string denoting direction of packet transfer.
1425 * @thread E1000_TX
1426 */
1427DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1428{
1429#ifdef DEBUG
1430 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1431 {
1432 E1kLog(("%s --- %s packet #%d: ---\n",
1433 INSTANCE(pState), cszText, ++pState->u32PktNo));
1434 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1435 e1kCsLeave(pState);
1436 }
1437#else
1438 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1439 {
1440 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1441 e1kCsLeave(pState);
1442 }
1443#endif
1444}
1445
1446/**
1447 * Determine the type of transmit descriptor.
1448 *
1449 * @returns Descriptor type. See E1K_DTYPE_XXX defines.
1450 *
1451 * @param pDesc Pointer to descriptor union.
1452 * @thread E1000_TX
1453 */
1454DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1455{
1456 if (pDesc->legacy.cmd.fDEXT)
1457 return pDesc->context.dw2.u4DTYP;
1458 return E1K_DTYP_LEGACY;
1459}
1460
1461/**
1462 * Dump receive descriptor to debug log.
1463 *
1464 * @param pState The device state structure.
1465 * @param pDesc Pointer to the descriptor.
1466 * @thread E1000_RX
1467 */
1468static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1469{
1470 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1471 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1472 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1473 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1474 pDesc->status.fPIF ? "PIF" : "pif",
1475 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1476 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1477 pDesc->status.fVP ? "VP" : "vp",
1478 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1479 pDesc->status.fEOP ? "EOP" : "eop",
1480 pDesc->status.fDD ? "DD" : "dd",
1481 pDesc->status.fRXE ? "RXE" : "rxe",
1482 pDesc->status.fIPE ? "IPE" : "ipe",
1483 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1484 pDesc->status.fCE ? "CE" : "ce",
1485 pDesc->status.fCFI ? "CFI" :"cfi",
1486 pDesc->status.u12VLAN,
1487 pDesc->status.u3PRI));
1488}
1489
1490/**
1491 * Dump transmit descriptor to debug log.
1492 *
1493 * @param pState The device state structure.
1494 * @param pDesc Pointer to descriptor union.
1495 * @param cszDir A string denoting direction of descriptor transfer
1496 * @thread E1000_TX
1497 */
1498static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1499{
1500 switch (e1kGetDescType(pDesc))
1501 {
1502 case E1K_DTYP_CONTEXT:
1503 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1504 INSTANCE(pState), cszDir, cszDir));
1505 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1506 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1507 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1508 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1509 pDesc->context.dw2.fIDE ? " IDE":"",
1510 pDesc->context.dw2.fRS ? " RS" :"",
1511 pDesc->context.dw2.fTSE ? " TSE":"",
1512 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1513 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1514 pDesc->context.dw2.u20PAYLEN,
1515 pDesc->context.dw3.u8HDRLEN,
1516 pDesc->context.dw3.u16MSS,
1517 pDesc->context.dw3.fDD?"DD":""));
1518 break;
1519 case E1K_DTYP_DATA:
1520 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1521 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1522 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1523 pDesc->data.u64BufAddr,
1524 pDesc->data.cmd.u20DTALEN));
1525 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1526 pDesc->data.cmd.fIDE ? " IDE" :"",
1527 pDesc->data.cmd.fVLE ? " VLE" :"",
1528 pDesc->data.cmd.fRS ? " RS" :"",
1529 pDesc->data.cmd.fTSE ? " TSE" :"",
1530 pDesc->data.cmd.fIFCS? " IFCS":"",
1531 pDesc->data.cmd.fEOP ? " EOP" :"",
1532 pDesc->data.dw3.fDD ? " DD" :"",
1533 pDesc->data.dw3.fEC ? " EC" :"",
1534 pDesc->data.dw3.fLC ? " LC" :"",
1535 pDesc->data.dw3.fTXSM? " TXSM":"",
1536 pDesc->data.dw3.fIXSM? " IXSM":"",
1537 pDesc->data.dw3.fCFI ? " CFI" :"",
1538 pDesc->data.dw3.u12VLAN,
1539 pDesc->data.dw3.u3PRI));
1540 break;
1541 case E1K_DTYP_LEGACY:
1542 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1543 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1544 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1545 pDesc->data.u64BufAddr,
1546 pDesc->legacy.cmd.u16Length));
1547 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1548 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1549 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1550 pDesc->legacy.cmd.fRS ? " RS" :"",
1551 pDesc->legacy.cmd.fIC ? " IC" :"",
1552 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1553 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1554 pDesc->legacy.dw3.fDD ? " DD" :"",
1555 pDesc->legacy.dw3.fEC ? " EC" :"",
1556 pDesc->legacy.dw3.fLC ? " LC" :"",
1557 pDesc->legacy.cmd.u8CSO,
1558 pDesc->legacy.dw3.u8CSS,
1559 pDesc->legacy.dw3.fCFI ? " CFI" :"",
1560 pDesc->legacy.dw3.u12VLAN,
1561 pDesc->legacy.dw3.u3PRI));
1562 break;
1563 default:
1564 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1565 INSTANCE(pState), cszDir, cszDir));
1566 break;
1567 }
1568}
1569#endif /* IN_RING3 */
1570
1571/**
1572 * Hardware reset. Revert all registers to initial values.
1573 *
1574 * @param pState The device state structure.
1575 */
1576PDMBOTHCBDECL(void) e1kHardReset(E1KSTATE *pState)
1577{
1578 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1579 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1580 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1581 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1582 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1583 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1584}
1585
1586/**
1587 * Raise interrupt if not masked.
1588 *
1589 * @param pState The device state structure.
1590 */
1591PDMBOTHCBDECL(int) e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1592{
1593 int rc = e1kCsEnter(pState, rcBusy);
1594 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1595 return rc;
1596
1597 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1598 ICR |= u32IntCause;
1599 if (ICR & IMS)
1600 {
1601#if 0
1602 if (pState->fDelayInts)
1603 {
1604 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1605 pState->iStatIntLostOne = 1;
1606 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1607 INSTANCE(pState), ICR));
1608#define E1K_LOST_IRQ_THRSLD 20
1609//#define E1K_LOST_IRQ_THRSLD 200000000
1610 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1611 {
1612 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1613 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1614 pState->fIntMaskUsed = false;
1615 pState->uStatDisDly++;
1616 }
1617 }
1618 else
1619#endif
1620 if (pState->fIntRaised)
1621 {
1622 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1623 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1624 INSTANCE(pState), ICR & IMS));
1625 }
1626 else
1627 {
1628#ifdef E1K_ITR_ENABLED
1629 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1630 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1631 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1632 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1633 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1634 {
1635 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1636 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1637 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1638 }
1639 else
1640#endif
1641 {
1642
1643 /* Since we are delivering the interrupt now
1644 * there is no need to do it later -- stop the timer.
1645 */
1646 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1647 E1K_INC_ISTAT_CNT(pState->uStatInt);
1648 STAM_COUNTER_INC(&pState->StatIntsRaised);
1649 /* Got at least one unmasked interrupt cause */
1650 pState->fIntRaised = true;
1651 /* Raise(1) INTA(0) */
1652 //PDMDevHlpPCISetIrqNoWait(pState->CTXSUFF(pInst), 0, 1);
1653 //e1kMutexRelease(pState);
1654 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1655 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1656 //e1kMutexAcquire(pState, RT_SRC_POS);
1657 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1658 INSTANCE(pState), ICR & IMS));
1659 }
1660 }
1661 }
1662 else
1663 {
1664 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1665 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1666 INSTANCE(pState), ICR, IMS));
1667 }
1668 e1kCsLeave(pState);
1669 return VINF_SUCCESS;
1670}
1671
1672#ifdef IN_RING3
1673/**
1674 * Compute the physical address of the descriptor.
1675 *
1676 * @returns the physical address of the descriptor.
1677 *
1678 * @param baseHigh High-order 32 bits of descriptor table address.
1679 * @param baseLow Low-order 32 bits of descriptor table address.
1680 * @param idxDesc The descriptor index in the table.
1681 */
1682DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1683{
1684 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1685 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1686}
1687
1688/**
1689 * Advance the head pointer of the receive descriptor queue.
1690 *
1691 * @remarks RDH always points to the next available RX descriptor.
1692 *
1693 * @param pState The device state structure.
1694 */
1695DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1696{
1697 //e1kCsEnter(pState, RT_SRC_POS);
1698 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1699 RDH = 0;
1700 /*
1701 * Compute current recieve queue length and fire RXDMT0 interrupt
1702 * if we are low on recieve buffers
1703 */
1704 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1705 /*
1706 * The minimum threshold is controlled by RDMTS bits of RCTL:
1707 * 00 = 1/2 of RDLEN
1708 * 01 = 1/4 of RDLEN
1709 * 10 = 1/8 of RDLEN
1710 * 11 = reserved
1711 */
1712 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1713 if (uRQueueLen <= uMinRQThreshold)
1714 {
1715 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1716 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1717 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1718 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1719 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1720 }
1721 //e1kCsLeave(pState);
1722}
1723
1724/**
1725 * Store a fragment of received packet that fits into the next available RX
1726 * buffer.
1727 *
1728 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1729 *
1730 * @param pState The device state structure.
1731 * @param pDesc The next available RX descriptor.
1732 * @param pvBuf The fragment.
1733 * @param cb The size of the fragment.
1734 */
1735static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1736{
1737 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1738 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1739 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1740 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1741 /* Write back the descriptor */
1742 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1743 e1kPrintRDesc(pState, pDesc);
1744 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1745 /* Advance head */
1746 e1kAdvanceRDH(pState);
1747 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1748 if (pDesc->status.fEOP)
1749 {
1750 /* Complete packet has been stored -- it is time to let the guest know. */
1751#ifdef E1K_USE_RX_TIMERS
1752 if (RDTR)
1753 {
1754 /* Arm the timer to fire in RDTR usec (discard .024) */
1755 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1756 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1757 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1758 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1759 }
1760 else
1761 {
1762#endif
1763 /* 0 delay means immediate interrupt */
1764 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1765 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1766#ifdef E1K_USE_RX_TIMERS
1767 }
1768#endif
1769 }
1770 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1771}
1772
1773/**
1774 * Returns true if it is a broadcast packet.
1775 *
1776 * @returns true if destination address indicates broadcast.
1777 * @param pvBuf The ethernet packet.
1778 */
1779DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1780{
1781 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1782 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1783}
1784
1785/**
1786 * Returns true if it is a multicast packet.
1787 *
1788 * @remarks returns true for broadcast packets as well.
1789 * @returns true if destination address indicates multicast.
1790 * @param pvBuf The ethernet packet.
1791 */
1792DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1793{
1794 return (*(char*)pvBuf) & 1;
1795}
1796
1797/**
1798 * Pad and store received packet.
1799 *
1800 * @remarks Make sure that the packet appears to upper layer as one coming
1801 * from real Ethernet: pad it and insert FCS.
1802 *
1803 * @returns VBox status code.
1804 * @param pState The device state structure.
1805 * @param pvBuf The available data.
1806 * @param cb Number of bytes available in the buffer.
1807 * @param status Bit fields containing status info.
1808 */
1809static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
1810{
1811 E1KRXDESC desc;
1812 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
1813 uint8_t *ptr = rxPacket;
1814
1815#ifndef E1K_GLOBAL_MUTEX
1816 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1817 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1818 return rc;
1819#endif
1820
1821#ifdef E1K_LEDS_WITH_MUTEX
1822 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1823 {
1824#endif /* E1K_LEDS_WITH_MUTEX */
1825 pState->led.Asserted.s.fReading = 1;
1826 pState->led.Actual.s.fReading = 1;
1827#ifdef E1K_LEDS_WITH_MUTEX
1828 e1kCsLeave(pState);
1829 }
1830#endif /* E1K_LEDS_WITH_MUTEX */
1831
1832 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
1833 memcpy(rxPacket, pvBuf, cb);
1834 /* Pad short packets */
1835 if (cb < 60)
1836 cb = 60;
1837 if (!(RCTL & RCTL_SECRC))
1838 {
1839 /* Add FCS if CRC stripping is not enabled */
1840 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
1841 cb += sizeof(uint32_t);
1842 }
1843 /* Compute checksum of complete packet */
1844 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
1845
1846 /* Update stats */
1847 E1K_INC_CNT32(GPRC);
1848 if (e1kIsBroadcast(pvBuf))
1849 E1K_INC_CNT32(BPRC);
1850 else if (e1kIsMulticast(pvBuf))
1851 E1K_INC_CNT32(MPRC);
1852 /* Update octet receive counter */
1853 E1K_ADD_CNT64(GORCL, GORCH, cb);
1854 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
1855 if (cb == 64)
1856 E1K_INC_CNT32(PRC64);
1857 else if (cb < 128)
1858 E1K_INC_CNT32(PRC127);
1859 else if (cb < 256)
1860 E1K_INC_CNT32(PRC255);
1861 else if (cb < 512)
1862 E1K_INC_CNT32(PRC511);
1863 else if (cb < 1024)
1864 E1K_INC_CNT32(PRC1023);
1865 else
1866 E1K_INC_CNT32(PRC1522);
1867
1868 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
1869
1870 if (RDH == RDT)
1871 {
1872 E1kLog(("%s Out of recieve buffers, dropping the packet",
1873 INSTANCE(pState)));
1874 }
1875 /* Store the packet to receive buffers */
1876 while (RDH != RDT)
1877 {
1878 /* Load the desciptor pointed by head */
1879 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
1880 &desc, sizeof(desc));
1881 if (desc.u64BufAddr)
1882 {
1883 /* Update descriptor */
1884 desc.status = status;
1885 desc.u16Checksum = checksum;
1886 desc.status.fDD = true;
1887 //desc.fIXSM = true;
1888 desc.status.fIPCS = true;
1889 desc.status.fTCPCS = true;
1890 //desc.status.fIPE = false;
1891 //desc.status.fTCPE = false;
1892 /*
1893 * We need to leave Rx critical section here or we risk deadlocking
1894 * with EMT in e1kRegWriteRDT when the write is to an unallocated
1895 * page or has an access handler associated with it.
1896 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
1897 * modifies RDT only.
1898 */
1899 if(cb > pState->u16RxBSize)
1900 {
1901 desc.status.fEOP = false;
1902 e1kCsRxLeave(pState);
1903 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
1904 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1905 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1906 return rc;
1907 ptr += pState->u16RxBSize;
1908 cb -= pState->u16RxBSize;
1909 }
1910 else
1911 {
1912 desc.status.fEOP = true;
1913 e1kCsRxLeave(pState);
1914 e1kStoreRxFragment(pState, &desc, ptr, cb);
1915#ifdef E1K_LEDS_WITH_MUTEX
1916 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1917 {
1918#endif /* E1K_LEDS_WITH_MUTEX */
1919 pState->led.Actual.s.fReading = 0;
1920#ifdef E1K_LEDS_WITH_MUTEX
1921 e1kCsLeave(pState);
1922 }
1923#endif /* E1K_LEDS_WITH_MUTEX */
1924 return VINF_SUCCESS;
1925 }
1926 /* Note: RDH is advanced by e1kStoreRxFragment! */
1927 }
1928 else
1929 {
1930 desc.status.fDD = true;
1931 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
1932 e1kDescAddr(RDBAH, RDBAL, RDH),
1933 &desc, sizeof(desc));
1934 e1kAdvanceRDH(pState);
1935 }
1936 }
1937#ifdef E1K_LEDS_WITH_MUTEX
1938 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1939 {
1940#endif /* E1K_LEDS_WITH_MUTEX */
1941 pState->led.Actual.s.fReading = 0;
1942#ifdef E1K_LEDS_WITH_MUTEX
1943 e1kCsLeave(pState);
1944 }
1945#endif /* E1K_LEDS_WITH_MUTEX */
1946
1947 e1kCsRxLeave(pState);
1948
1949 return VINF_SUCCESS;
1950}
1951
1952#endif /* IN_RING3 */
1953
1954#if 0 /* unused */
1955/**
1956 * Read handler for Device Status register.
1957 *
1958 * Get the link status from PHY.
1959 *
1960 * @returns VBox status code.
1961 *
1962 * @param pState The device state structure.
1963 * @param offset Register offset in memory-mapped frame.
1964 * @param index Register index in register array.
1965 * @param mask Used to implement partial reads (8 and 16-bit).
1966 */
1967static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
1968{
1969 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
1970 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
1971 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
1972 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
1973 {
1974 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
1975 if (Phy::readMDIO(&pState->phy))
1976 *pu32Value = CTRL | CTRL_MDIO;
1977 else
1978 *pu32Value = CTRL & ~CTRL_MDIO;
1979 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
1980 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
1981 }
1982 else
1983 {
1984 /* MDIO pin is used for output, ignore it */
1985 *pu32Value = CTRL;
1986 }
1987 return VINF_SUCCESS;
1988}
1989#endif /* unused */
1990
1991/**
1992 * Write handler for Device Control register.
1993 *
1994 * Handles reset.
1995 *
1996 * @param pState The device state structure.
1997 * @param offset Register offset in memory-mapped frame.
1998 * @param index Register index in register array.
1999 * @param value The value to store.
2000 * @param mask Used to implement partial writes (8 and 16-bit).
2001 * @thread EMT
2002 */
2003static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2004{
2005 int rc = VINF_SUCCESS;
2006
2007 if (value & CTRL_RESET)
2008 { /* RST */
2009 e1kHardReset(pState);
2010 }
2011 else
2012 {
2013 if (value & CTRL_SLU)
2014 {
2015 /* The driver indicates that we should bring up the link */
2016 STATUS |= STATUS_LU;
2017 }
2018 if (value & CTRL_VME)
2019 {
2020 E1kLog(("%s VLAN Mode is not supported yet!\n", INSTANCE(pState)));
2021 }
2022 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2023 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2024 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2025 if (value & CTRL_MDC)
2026 {
2027 if (value & CTRL_MDIO_DIR)
2028 {
2029 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2030 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2031 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2032 }
2033 else
2034 {
2035 if (Phy::readMDIO(&pState->phy))
2036 value |= CTRL_MDIO;
2037 else
2038 value &= ~CTRL_MDIO;
2039 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2040 INSTANCE(pState), !!(value & CTRL_MDIO)));
2041 }
2042 }
2043 rc = e1kRegWriteDefault(pState, offset, index, value);
2044 }
2045
2046 return rc;
2047}
2048
2049/**
2050 * Write handler for EEPROM/Flash Control/Data register.
2051 *
2052 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2053 *
2054 * @param pState The device state structure.
2055 * @param offset Register offset in memory-mapped frame.
2056 * @param index Register index in register array.
2057 * @param value The value to store.
2058 * @param mask Used to implement partial writes (8 and 16-bit).
2059 * @thread EMT
2060 */
2061static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2062{
2063#ifdef IN_RING3
2064 /* So far we are conserned with lower byte only */
2065 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2066 {
2067 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2068 /* Note: 82543GC does not need to request EEPROM access */
2069 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2070 pState->eeprom.write(value & EECD_EE_WIRES);
2071 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2072 }
2073 if (value & EECD_EE_REQ)
2074 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2075 else
2076 EECD &= ~EECD_EE_GNT;
2077 //e1kRegWriteDefault(pState, offset, index, value );
2078
2079 return VINF_SUCCESS;
2080#else /* !IN_RING3 */
2081 return VINF_IOM_HC_MMIO_WRITE;
2082#endif /* !IN_RING3 */
2083}
2084
2085/**
2086 * Read handler for EEPROM/Flash Control/Data register.
2087 *
2088 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2089 *
2090 * @returns VBox status code.
2091 *
2092 * @param pState The device state structure.
2093 * @param offset Register offset in memory-mapped frame.
2094 * @param index Register index in register array.
2095 * @param mask Used to implement partial reads (8 and 16-bit).
2096 * @thread EMT
2097 */
2098static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2099{
2100#ifdef IN_RING3
2101 uint32_t value;
2102 int rc = e1kRegReadDefault(pState, offset, index, &value);
2103 if (RT_SUCCESS(rc))
2104 {
2105 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2106 {
2107 /* Note: 82543GC does not need to request EEPROM access */
2108 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2109 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2110 value |= pState->eeprom.read();
2111 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2112 }
2113 *pu32Value = value;
2114 }
2115
2116 return rc;
2117#else /* !IN_RING3 */
2118 return VINF_IOM_HC_MMIO_READ;
2119#endif /* !IN_RING3 */
2120}
2121
2122/**
2123 * Write handler for MDI Control register.
2124 *
2125 * Handles PHY read/write requests; forwards requests to internal PHY device.
2126 *
2127 * @param pState The device state structure.
2128 * @param offset Register offset in memory-mapped frame.
2129 * @param index Register index in register array.
2130 * @param value The value to store.
2131 * @param mask Used to implement partial writes (8 and 16-bit).
2132 * @thread EMT
2133 */
2134static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2135{
2136 if (value & MDIC_INT_EN)
2137 {
2138 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2139 INSTANCE(pState)));
2140 }
2141 else if (value & MDIC_READY)
2142 {
2143 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2144 INSTANCE(pState)));
2145 }
2146 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2147 {
2148 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2149 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2150 }
2151 else
2152 {
2153 /* Store the value */
2154 e1kRegWriteDefault(pState, offset, index, value);
2155 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2156 /* Forward op to PHY */
2157 if (value & MDIC_OP_READ)
2158 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2159 else
2160 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2161 /* Let software know that we are done */
2162 MDIC |= MDIC_READY;
2163 }
2164
2165 return VINF_SUCCESS;
2166}
2167
2168/**
2169 * Write handler for Interrupt Cause Read register.
2170 *
2171 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2172 *
2173 * @param pState The device state structure.
2174 * @param offset Register offset in memory-mapped frame.
2175 * @param index Register index in register array.
2176 * @param value The value to store.
2177 * @param mask Used to implement partial writes (8 and 16-bit).
2178 * @thread EMT
2179 */
2180static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2181{
2182 ICR &= ~value;
2183
2184 return VINF_SUCCESS;
2185}
2186
2187/**
2188 * Read handler for Interrupt Cause Read register.
2189 *
2190 * Reading this register acknowledges all interrupts.
2191 *
2192 * @returns VBox status code.
2193 *
2194 * @param pState The device state structure.
2195 * @param offset Register offset in memory-mapped frame.
2196 * @param index Register index in register array.
2197 * @param mask Not used.
2198 * @thread EMT
2199 */
2200static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2201{
2202 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2203 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2204 return rc;
2205
2206 uint32_t value = 0;
2207 rc = e1kRegReadDefault(pState, offset, index, &value);
2208 if (RT_SUCCESS(rc))
2209 {
2210 if (value)
2211 {
2212 if (IMS)
2213 {
2214 /*
2215 * Interrupts were enabled -- we are supposedly at the very
2216 * beginning of interrupt handler
2217 */
2218 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2219 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2220 /* Clear all pending interrupts */
2221 ICR = 0;
2222 pState->fIntRaised = false;
2223 /* Lower(0) INTA(0) */
2224 //PDMDevHlpPCISetIrqNoWait(pState->CTX_SUFF(pDevIns), 0, 0);
2225 //e1kMutexRelease(pState);
2226 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2227 //e1kMutexAcquire(pState, RT_SRC_POS);
2228
2229 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2230 if (pState->fIntMaskUsed)
2231 pState->fDelayInts = true;
2232 }
2233 else
2234 {
2235 /*
2236 * Interrupts are disabled -- in windows guests ICR read is done
2237 * just before re-enabling interrupts
2238 */
2239 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2240 }
2241 }
2242 *pu32Value = value;
2243 }
2244 e1kCsLeave(pState);
2245
2246 return rc;
2247}
2248
2249/**
2250 * Write handler for Interrupt Cause Set register.
2251 *
2252 * Bits corresponding to 1s in 'value' will be set in ICR register.
2253 *
2254 * @param pState The device state structure.
2255 * @param offset Register offset in memory-mapped frame.
2256 * @param index Register index in register array.
2257 * @param value The value to store.
2258 * @param mask Used to implement partial writes (8 and 16-bit).
2259 * @thread EMT
2260 */
2261static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2262{
2263 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2264 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2265}
2266
2267/**
2268 * Write handler for Interrupt Mask Set register.
2269 *
2270 * Will trigger pending interrupts.
2271 *
2272 * @param pState The device state structure.
2273 * @param offset Register offset in memory-mapped frame.
2274 * @param index Register index in register array.
2275 * @param value The value to store.
2276 * @param mask Used to implement partial writes (8 and 16-bit).
2277 * @thread EMT
2278 */
2279static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2280{
2281 IMS |= value;
2282 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2283 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2284 /* Mask changes, we need to raise pending interrupts. */
2285 if ((ICR & IMS) && !pState->fLocked)
2286 {
2287 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2288 INSTANCE(pState), ICR));
2289 //TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2290 // TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2291 e1kRaiseInterrupt(pState, VERR_SEM_BUSY);
2292 }
2293
2294 return VINF_SUCCESS;
2295}
2296
2297/**
2298 * Write handler for Interrupt Mask Clear register.
2299 *
2300 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2301 *
2302 * @param pState The device state structure.
2303 * @param offset Register offset in memory-mapped frame.
2304 * @param index Register index in register array.
2305 * @param value The value to store.
2306 * @param mask Used to implement partial writes (8 and 16-bit).
2307 * @thread EMT
2308 */
2309static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2310{
2311 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2312 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2313 return rc;
2314 if (pState->fIntRaised)
2315 {
2316 /*
2317 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2318 * Windows to freeze since it may receive an interrupt while still in the very beginning
2319 * of interrupt handler.
2320 */
2321 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2322 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2323 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2324 /* Lower(0) INTA(0) */
2325 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2326 pState->fIntRaised = false;
2327 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2328 }
2329 IMS &= ~value;
2330 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2331 e1kCsLeave(pState);
2332
2333 return VINF_SUCCESS;
2334}
2335
2336/**
2337 * Write handler for Receive Control register.
2338 *
2339 * @param pState The device state structure.
2340 * @param offset Register offset in memory-mapped frame.
2341 * @param index Register index in register array.
2342 * @param value The value to store.
2343 * @param mask Used to implement partial writes (8 and 16-bit).
2344 * @thread EMT
2345 */
2346static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2347{
2348 e1kRegWriteDefault(pState, offset, index, value);
2349 pState->u16RxBSize = 2048 >> GET_BITS(RCTL, BSIZE);
2350 if (RCTL & RCTL_BSEX)
2351 pState->u16RxBSize *= 16;
2352 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d\n",
2353 INSTANCE(pState), pState->u16RxBSize));
2354
2355 return VINF_SUCCESS;
2356}
2357
2358/**
2359 * Write handler for Packet Buffer Allocation register.
2360 *
2361 * TXA = 64 - RXA.
2362 *
2363 * @param pState The device state structure.
2364 * @param offset Register offset in memory-mapped frame.
2365 * @param index Register index in register array.
2366 * @param value The value to store.
2367 * @param mask Used to implement partial writes (8 and 16-bit).
2368 * @thread EMT
2369 */
2370static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2371{
2372 e1kRegWriteDefault(pState, offset, index, value);
2373 PBA_st->txa = 64 - PBA_st->rxa;
2374
2375 return VINF_SUCCESS;
2376}
2377
2378/**
2379 * Write handler for Receive Descriptor Tail register.
2380 *
2381 * @remarks Write into RDT forces switch to HC and signal to
2382 * e1kWaitReceiveAvail().
2383 *
2384 * @returns VBox status code.
2385 *
2386 * @param pState The device state structure.
2387 * @param offset Register offset in memory-mapped frame.
2388 * @param index Register index in register array.
2389 * @param value The value to store.
2390 * @param mask Used to implement partial writes (8 and 16-bit).
2391 * @thread EMT
2392 */
2393static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2394{
2395#ifndef IN_RING3
2396 /* XXX */
2397// return VINF_IOM_HC_MMIO_WRITE;
2398#endif
2399 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2400 if (RT_LIKELY(rc == VINF_SUCCESS))
2401 {
2402 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2403 rc = e1kRegWriteDefault(pState, offset, index, value);
2404 e1kCsRxLeave(pState);
2405 if (RT_SUCCESS(rc))
2406 {
2407#ifdef IN_RING3
2408 /* Signal that we have more receive descriptors avalable. */
2409 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2410#else
2411 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2412 if (pItem)
2413 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2414#endif
2415 }
2416 }
2417 return rc;
2418}
2419
2420/**
2421 * Write handler for Receive Delay Timer register.
2422 *
2423 * @param pState The device state structure.
2424 * @param offset Register offset in memory-mapped frame.
2425 * @param index Register index in register array.
2426 * @param value The value to store.
2427 * @param mask Used to implement partial writes (8 and 16-bit).
2428 * @thread EMT
2429 */
2430static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2431{
2432 e1kRegWriteDefault(pState, offset, index, value);
2433 if (value & RDTR_FPD)
2434 {
2435 /* Flush requested, cancel both timers and raise interrupt */
2436#ifdef E1K_USE_RX_TIMERS
2437 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2438 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2439#endif
2440 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2441 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2442 }
2443
2444 return VINF_SUCCESS;
2445}
2446
2447DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2448{
2449 /**
2450 * Make sure TDT won't change during computation. EMT may modify TDT at
2451 * any moment.
2452 */
2453 uint32_t tdt = TDT;
2454 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2455}
2456
2457#ifdef IN_RING3
2458#ifdef E1K_USE_TX_TIMERS
2459/**
2460 * Transmit Interrupt Delay Timer handler.
2461 *
2462 * @remarks We only get here when the timer expires.
2463 *
2464 * @param pDevIns Pointer to device instance structure.
2465 * @param pTimer Pointer to the timer.
2466 * @thread EMT
2467 */
2468static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2469{
2470 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2471
2472 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2473 {
2474 E1K_INC_ISTAT_CNT(pState->uStatTID);
2475 /* Cancel absolute delay timer as we have already got attention */
2476#ifndef E1K_NO_TAD
2477 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2478#endif /* E1K_NO_TAD */
2479 e1kRaiseInterrupt(pState, ICR_TXDW);
2480 e1kMutexRelease(pState);
2481 }
2482}
2483
2484/**
2485 * Transmit Absolute Delay Timer handler.
2486 *
2487 * @remarks We only get here when the timer expires.
2488 *
2489 * @param pDevIns Pointer to device instance structure.
2490 * @param pTimer Pointer to the timer.
2491 * @thread EMT
2492 */
2493static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2494{
2495 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2496
2497 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2498 {
2499 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2500 /* Cancel interrupt delay timer as we have already got attention */
2501 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2502 e1kRaiseInterrupt(pState, ICR_TXDW);
2503 e1kMutexRelease(pState);
2504 }
2505}
2506#endif /* E1K_USE_TX_TIMERS */
2507
2508#ifdef E1K_USE_RX_TIMERS
2509/**
2510 * Receive Interrupt Delay Timer handler.
2511 *
2512 * @remarks We only get here when the timer expires.
2513 *
2514 * @param pDevIns Pointer to device instance structure.
2515 * @param pTimer Pointer to the timer.
2516 * @thread EMT
2517 */
2518static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2519{
2520 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2521
2522 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2523 {
2524 E1K_INC_ISTAT_CNT(pState->uStatRID);
2525 /* Cancel absolute delay timer as we have already got attention */
2526 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2527 e1kRaiseInterrupt(pState, ICR_RXT0);
2528 e1kMutexRelease(pState);
2529 }
2530}
2531
2532/**
2533 * Receive Absolute Delay Timer handler.
2534 *
2535 * @remarks We only get here when the timer expires.
2536 *
2537 * @param pDevIns Pointer to device instance structure.
2538 * @param pTimer Pointer to the timer.
2539 * @thread EMT
2540 */
2541static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2542{
2543 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2544
2545 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2546 {
2547 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2548 /* Cancel interrupt delay timer as we have already got attention */
2549 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2550 e1kRaiseInterrupt(pState, ICR_RXT0);
2551 e1kMutexRelease(pState);
2552 }
2553}
2554#endif /* E1K_USE_RX_TIMERS */
2555
2556/**
2557 * Late Interrupt Timer handler.
2558 *
2559 * @param pDevIns Pointer to device instance structure.
2560 * @param pTimer Pointer to the timer.
2561 * @thread EMT
2562 */
2563static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2564{
2565 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2566
2567 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2568 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2569 {
2570 STAM_COUNTER_INC(&pState->StatLateInts);
2571 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2572#if 0
2573 if (pState->iStatIntLost > -100)
2574 pState->iStatIntLost--;
2575#endif
2576 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2577 e1kMutexRelease(pState);
2578 }
2579 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2580}
2581
2582/**
2583 * Link Up Timer handler.
2584 *
2585 * @param pDevIns Pointer to device instance structure.
2586 * @param pTimer Pointer to the timer.
2587 * @thread EMT
2588 */
2589static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
2590{
2591 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
2592
2593 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2594 {
2595 STATUS |= STATUS_LU;
2596 Phy::setLinkStatus(&pState->phy, true);
2597 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2598 e1kMutexRelease(pState);
2599 }
2600}
2601
2602
2603
2604
2605/**
2606 * Load transmit descriptor from guest memory.
2607 *
2608 * @param pState The device state structure.
2609 * @param pDesc Pointer to descriptor union.
2610 * @param addr Physical address in guest context.
2611 * @thread E1000_TX
2612 */
2613DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2614{
2615 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2616}
2617
2618/**
2619 * Write back transmit descriptor to guest memory.
2620 *
2621 * @param pState The device state structure.
2622 * @param pDesc Pointer to descriptor union.
2623 * @param addr Physical address in guest context.
2624 * @thread E1000_TX
2625 */
2626DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2627{
2628 /* Only the last half of the descriptor has to be written back. */
2629 e1kPrintTDesc(pState, pDesc, "^^^");
2630 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2631}
2632
2633/**
2634 * Transmit complete frame.
2635 *
2636 * @remarks Since we do not have real Ethernet medium between us and NAT (or
2637 * another connector) there is no need for padding and FCS.
2638 *
2639 * @param pState The device state structure.
2640 * @param pFrame Pointer to the frame buffer.
2641 * @param u16FrameLen Length of the frame.
2642 * @thread E1000_TX
2643 */
2644static void e1kTransmitFrame(E1KSTATE* pState, uint8_t *pFrame, uint16_t u16FrameLen)
2645{
2646/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
2647 "%.*Rhxd\n"
2648 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
2649 INSTANCE(pState), u16FrameLen, pFrame, INSTANCE(pState)));*/
2650#ifdef E1K_LEDS_WITH_MUTEX
2651 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2652 {
2653#endif /* E1K_LEDS_WITH_MUTEX */
2654 pState->led.Asserted.s.fWriting = 1;
2655 pState->led.Actual.s.fWriting = 1;
2656#ifdef E1K_LEDS_WITH_MUTEX
2657 e1kCsLeave(pState);
2658 }
2659#endif /* E1K_LEDS_WITH_MUTEX */
2660 /* Update the stats */
2661 E1K_INC_CNT32(TPT);
2662 E1K_ADD_CNT64(TOTL, TOTH, u16FrameLen);
2663 E1K_INC_CNT32(GPTC);
2664 if (e1kIsBroadcast(pFrame))
2665 E1K_INC_CNT32(BPTC);
2666 else if (e1kIsMulticast(pFrame))
2667 E1K_INC_CNT32(MPTC);
2668 /* Update octet transmit counter */
2669 E1K_ADD_CNT64(GOTCL, GOTCH, u16FrameLen);
2670 if (pState->pDrv)
2671 {
2672 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, u16FrameLen);
2673 }
2674 if (u16FrameLen == 64)
2675 E1K_INC_CNT32(PTC64);
2676 else if (u16FrameLen < 128)
2677 E1K_INC_CNT32(PTC127);
2678 else if (u16FrameLen < 256)
2679 E1K_INC_CNT32(PTC255);
2680 else if (u16FrameLen < 512)
2681 E1K_INC_CNT32(PTC511);
2682 else if (u16FrameLen < 1024)
2683 E1K_INC_CNT32(PTC1023);
2684 else
2685 E1K_INC_CNT32(PTC1522);
2686
2687 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
2688
2689 e1kPacketDump(pState, pFrame, u16FrameLen, "--> Outgoing");
2690
2691
2692 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
2693 {
2694 E1KRXDST status;
2695 status.fPIF = true;
2696 /* Loopback mode */
2697 e1kHandleRxPacket(pState, pFrame, u16FrameLen, status);
2698 }
2699 else if (pState->pDrv)
2700 {
2701 /* Release critical section to avoid deadlock in CanReceive */
2702 //e1kCsLeave(pState);
2703 e1kMutexRelease(pState);
2704 STAM_PROFILE_ADV_START(&pState->StatTransmitSend, a);
2705 int rc = pState->pDrv->pfnSend(pState->pDrv, pFrame, u16FrameLen);
2706 STAM_PROFILE_ADV_STOP(&pState->StatTransmitSend, a);
2707 if (rc != VINF_SUCCESS)
2708 {
2709 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
2710 }
2711 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
2712 //e1kCsEnter(pState, RT_SRC_POS);
2713 }
2714#ifdef E1K_LEDS_WITH_MUTEX
2715 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2716 {
2717#endif /* E1K_LEDS_WITH_MUTEX */
2718 pState->led.Actual.s.fWriting = 0;
2719#ifdef E1K_LEDS_WITH_MUTEX
2720 e1kCsLeave(pState);
2721 }
2722#endif /* E1K_LEDS_WITH_MUTEX */
2723}
2724
2725/**
2726 * Compute and write checksum at the specified offset.
2727 *
2728 * @param pState The device state structure.
2729 * @param pPkt Pointer to the packet.
2730 * @param u16PktLen Total length of the packet.
2731 * @param cso Offset in packet to write checksum at.
2732 * @param css Offset in packet to start computing
2733 * checksum from.
2734 * @param cse Offset in packet to stop computing
2735 * checksum at.
2736 * @thread E1000_TX
2737 */
2738static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
2739{
2740 if (cso > u16PktLen)
2741 {
2742 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
2743 INSTANCE(pState), cso, u16PktLen));
2744 return;
2745 }
2746
2747 if (cse == 0)
2748 cse = u16PktLen - 1;
2749 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
2750 e1kCSum16(pPkt + css, cse - css + 1), cso,
2751 *(uint16_t*)(pPkt + cso)));
2752 *(uint16_t*)(pPkt + cso) = e1kCSum16(pPkt + css, cse - css + 1);
2753}
2754
2755/**
2756 * Add a part of descriptor's buffer to transmit frame.
2757 *
2758 * @remarks data.u64BufAddr is used uncoditionally for both data
2759 * and legacy descriptors since it is identical to
2760 * legacy.u64BufAddr.
2761 *
2762 * @param pState The device state structure.
2763 * @param pDesc Pointer to the descriptor to transmit.
2764 * @param u16Len Length of buffer to the end of segment.
2765 * @param fSend Force packet sending.
2766 * @thread E1000_TX
2767 */
2768static void e1kAddSegment(E1KSTATE* pState, E1KTXDESC* pDesc, uint16_t u16Len, bool fSend)
2769{
2770 /* TCP header being transmitted */
2771 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
2772 (pState->aTxPacket + pState->contextTSE.tu.u8CSS);
2773 /* IP header being transmitted */
2774 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
2775 (pState->aTxPacket + pState->contextTSE.ip.u8CSS);
2776
2777 E1kLog3(("%s e1kAddSegment: Length=%x, remaining payload=%x, header=%x, send=%s\n",
2778 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain,
2779 fSend ? "true" : "false"));
2780 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
2781
2782 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr,
2783 pState->aTxPacket + pState->u16TxPktLen, u16Len);
2784 E1kLog3(("%s Dump of the segment:\n"
2785 "%.*Rhxd\n"
2786 "%s --- End of dump ---\n",
2787 INSTANCE(pState), u16Len, pState->aTxPacket + pState->u16TxPktLen, INSTANCE(pState)));
2788 pState->u16TxPktLen += u16Len;
2789 E1kLog3(("%s e1kAddSegment: pState->u16TxPktLen=%x\n",
2790 INSTANCE(pState), pState->u16TxPktLen));
2791 if (pState->u16HdrRemain > 0)
2792 {
2793 /* The header was not complete, check if it is now */
2794 if (u16Len >= pState->u16HdrRemain)
2795 {
2796 /* The rest is payload */
2797 u16Len -= pState->u16HdrRemain;
2798 pState->u16HdrRemain = 0;
2799 /* Save partial checksum and flags */
2800 pState->u32SavedCsum = pTcpHdr->chksum;
2801 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
2802 /* Clear FIN and PSH flags now and set them only in the last segment */
2803 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
2804 }
2805 else
2806 {
2807 /* Still not */
2808 pState->u16HdrRemain -= u16Len;
2809 E1kLog3(("%s e1kAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
2810 INSTANCE(pState), pState->u16HdrRemain));
2811 return;
2812 }
2813 }
2814
2815 pState->u32PayRemain -= u16Len;
2816
2817 if (fSend)
2818 {
2819 /* Leave ethernet header intact */
2820 /* IP Total Length = payload + headers - ethernet header */
2821 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
2822 E1kLog3(("%s e1kAddSegment: End of packet, pIpHdr->total_len=%x\n",
2823 INSTANCE(pState), ntohs(pIpHdr->total_len)));
2824 /* Update IP Checksum */
2825 pIpHdr->chksum = 0;
2826 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2827 pState->contextTSE.ip.u8CSO,
2828 pState->contextTSE.ip.u8CSS,
2829 pState->contextTSE.ip.u16CSE);
2830
2831 /* Update TCP flags */
2832 /* Restore original FIN and PSH flags for the last segment */
2833 if (pState->u32PayRemain == 0)
2834 {
2835 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
2836 E1K_INC_CNT32(TSCTC);
2837 }
2838 /* Add TCP length to partial pseudo header sum */
2839 uint32_t csum = pState->u32SavedCsum
2840 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
2841 while (csum >> 16)
2842 csum = (csum >> 16) + (csum & 0xFFFF);
2843 pTcpHdr->chksum = csum;
2844 /* Compute final checksum */
2845 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2846 pState->contextTSE.tu.u8CSO,
2847 pState->contextTSE.tu.u8CSS,
2848 pState->contextTSE.tu.u16CSE);
2849 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
2850 /* Update Sequence Number */
2851 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
2852 - pState->contextTSE.dw3.u8HDRLEN);
2853 /* Increment IP identification */
2854 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
2855 }
2856}
2857
2858/**
2859 * Add descriptor's buffer to transmit frame.
2860 *
2861 * @remarks data.u64BufAddr is used uncoditionally for both data
2862 * and legacy descriptors since it is identical to
2863 * legacy.u64BufAddr.
2864 *
2865 * @param pState The device state structure.
2866 * @param pDesc Pointer to the descriptor to transmit.
2867 * @param u16PartLen Length of descriptor's buffer.
2868 * @thread E1000_TX
2869 */
2870static bool e1kAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t u32PartLen)
2871{
2872 if (e1kGetDescType(pDesc) == E1K_DTYP_DATA && pDesc->data.cmd.fTSE)
2873 {
2874 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
2875 Assert(u16MaxPktLen != 0);
2876 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
2877
2878 do {
2879 /* Calculate how many bytes have left in this TCP segment */
2880 uint32_t uLen = u16MaxPktLen - pState->u16TxPktLen;
2881 if (uLen > u32PartLen)
2882 {
2883 /* This descriptor fits completely into current segment */
2884 uLen = u32PartLen;
2885 e1kAddSegment(pState, pDesc, uLen, pDesc->data.cmd.fEOP);
2886 }
2887 else
2888 {
2889 e1kAddSegment(pState, pDesc, uLen, true);
2890 /*
2891 * Rewind the packet tail pointer to the beginning of payload,
2892 * so we continue writing right beyond the header.
2893 */
2894 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
2895 }
2896 pDesc->data.u64BufAddr += uLen;
2897 u32PartLen -= uLen;
2898 } while (u32PartLen > 0);
2899 if (pDesc->data.cmd.fEOP)
2900 {
2901 /* End of packet, next segment will contain header. */
2902 pState->u16TxPktLen = 0;
2903 }
2904 return false;
2905 }
2906 else
2907 {
2908 if (u32PartLen + pState->u16TxPktLen > E1K_MAX_TX_PKT_SIZE)
2909 {
2910 E1kLog(("%s Transmit packet is too large: %d > %d(max)\n",
2911 INSTANCE(pState), u32PartLen + pState->u16TxPktLen, E1K_MAX_TX_PKT_SIZE));
2912 return false;
2913 }
2914 else
2915 {
2916 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr, pState->aTxPacket + pState->u16TxPktLen, u32PartLen);
2917 pState->u16TxPktLen += u32PartLen;
2918 }
2919 }
2920
2921 return true;
2922}
2923
2924
2925/**
2926 * Write the descriptor back to guest memory and notify the guest.
2927 *
2928 * @param pState The device state structure.
2929 * @param pDesc Pointer to the descriptor have been transmited.
2930 * @param addr Physical address of the descriptor in guest memory.
2931 * @thread E1000_TX
2932 */
2933static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2934{
2935 /*
2936 * We fake descriptor write-back bursting. Descriptors are written back as they are
2937 * processed.
2938 */
2939 /* Let's pretend we process descriptors. Write back with DD set. */
2940 if (pDesc->legacy.cmd.fRS || (GET_BITS(TXDCTL, WTHRESH) > 0))
2941 {
2942 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
2943 e1kWriteBackDesc(pState, pDesc, addr);
2944 if (pDesc->legacy.cmd.fEOP)
2945 {
2946#ifdef E1K_USE_TX_TIMERS
2947 if (pDesc->legacy.cmd.fIDE)
2948 {
2949 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
2950 //if (pState->fIntRaised)
2951 //{
2952 // /* Interrupt is already pending, no need for timers */
2953 // ICR |= ICR_TXDW;
2954 //}
2955 //else {
2956 /* Arm the timer to fire in TIVD usec (discard .024) */
2957 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
2958#ifndef E1K_NO_TAD
2959 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2960 E1kLog2(("%s Checking if TAD timer is running\n",
2961 INSTANCE(pState)));
2962 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
2963 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
2964#endif /* E1K_NO_TAD */
2965 }
2966 else
2967 {
2968 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
2969 INSTANCE(pState)));
2970#ifndef E1K_NO_TAD
2971 /* Cancel both timers if armed and fire immediately. */
2972 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2973#endif /* E1K_NO_TAD */
2974#endif /* E1K_USE_TX_TIMERS */
2975 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
2976 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
2977#ifdef E1K_USE_TX_TIMERS
2978 }
2979#endif /* E1K_USE_TX_TIMERS */
2980 }
2981 }
2982 else
2983 {
2984 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
2985 }
2986}
2987
2988/**
2989 * Process Transmit Descriptor.
2990 *
2991 * E1000 supports three types of transmit descriptors:
2992 * - legacy data descriptors of older format (context-less).
2993 * - data the same as legacy but providing new offloading capabilities.
2994 * - context sets up the context for following data descriptors.
2995 *
2996 * @param pState The device state structure.
2997 * @param pDesc Pointer to descriptor union.
2998 * @param addr Physical address of descriptor in guest memory.
2999 * @thread E1000_TX
3000 */
3001static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3002{
3003 e1kPrintTDesc(pState, pDesc, "vvv");
3004
3005#ifdef E1K_USE_TX_TIMERS
3006 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3007#endif /* E1K_USE_TX_TIMERS */
3008
3009 switch (e1kGetDescType(pDesc))
3010 {
3011 case E1K_DTYP_CONTEXT:
3012 if (pDesc->context.dw2.fTSE)
3013 {
3014 pState->contextTSE = pDesc->context;
3015 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3016 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3017 }
3018 else
3019 pState->contextNormal = pDesc->context;
3020 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3021 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3022 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3023 pDesc->context.ip.u8CSS,
3024 pDesc->context.ip.u8CSO,
3025 pDesc->context.ip.u16CSE,
3026 pDesc->context.tu.u8CSS,
3027 pDesc->context.tu.u8CSO,
3028 pDesc->context.tu.u16CSE));
3029 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3030 e1kDescReport(pState, pDesc, addr);
3031 break;
3032 case E1K_DTYP_DATA:
3033 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3034 {
3035 E1kLog2(("% Empty descriptor, skipped.\n", INSTANCE(pState)));
3036 break;
3037 }
3038 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3039 &pState->StatTxDescTSEData:
3040 &pState->StatTxDescData);
3041 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3042 /* IXSM and TXSM options are valid in the first fragment only */
3043 if (pState->u16TxPktLen == 0)
3044 {
3045 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3046 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3047 E1kLog2(("%s Saving checksum flags:%s%s\n", INSTANCE(pState),
3048 pState->fIPcsum ? " IP" : "",
3049 pState->fTCPcsum ? " TCP/UDP" : ""));
3050 }
3051 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3052 if (e1kAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN) && pDesc->data.cmd.fEOP)
3053 {
3054 if (!pDesc->data.cmd.fTSE)
3055 {
3056 /*
3057 * We only insert checksums here if this packet was not segmented,
3058 * otherwise it has already been taken care of by e1kAddSegment().
3059 */
3060 if (pState->fIPcsum)
3061 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3062 pState->contextNormal.ip.u8CSO,
3063 pState->contextNormal.ip.u8CSS,
3064 pState->contextNormal.ip.u16CSE);
3065 if (pState->fTCPcsum)
3066 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3067 pState->contextNormal.tu.u8CSO,
3068 pState->contextNormal.tu.u8CSS,
3069 pState->contextNormal.tu.u16CSE);
3070 }
3071 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3072 /* Reset transmit packet storage. */
3073 pState->u16TxPktLen = 0;
3074 }
3075 e1kDescReport(pState, pDesc, addr);
3076 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3077 break;
3078 case E1K_DTYP_LEGACY:
3079 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3080 {
3081 E1kLog(("%s Empty descriptor, skipped.\n", INSTANCE(pState)));
3082 break;
3083 }
3084 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3085 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3086 if (e1kAddToFrame(pState, pDesc, pDesc->legacy.cmd.u16Length))
3087 {
3088 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3089 /** @todo Offload processing goes here. */
3090 if (pDesc->legacy.cmd.fEOP)
3091 {
3092 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3093 /* Reset transmit packet storage. */
3094 pState->u16TxPktLen = 0;
3095 }
3096 }
3097 e1kDescReport(pState, pDesc, addr);
3098 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3099 break;
3100 default:
3101 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3102 INSTANCE(pState), e1kGetDescType(pDesc)));
3103 break;
3104 }
3105}
3106
3107/**
3108 * Wake up callback for transmission thread.
3109 *
3110 * @returns VBox status code. Returning failure will naturally terminate the thread.
3111 * @param pDevIns The pcnet device instance.
3112 * @param pThread The thread.
3113 */
3114static DECLCALLBACK(int) e1kTxThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3115{
3116 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3117 int rc = RTSemEventSignal(pState->hTxSem);
3118 AssertRC(rc);
3119 return VINF_SUCCESS;
3120}
3121
3122/**
3123 * I/O thread for packet transmission.
3124 *
3125 * @returns VBox status code. Returning failure will naturally terminate the thread.
3126 * @param pDevIns Pointer to device instance structure.
3127 * @param pThread The thread.
3128 * @thread E1000_TX
3129 */
3130static DECLCALLBACK(int) e1kTxThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3131{
3132 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3133
3134 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3135 {
3136 int rc = RTSemEventWait(pState->hTxSem, RT_INDEFINITE_WAIT);
3137 AssertRCReturn(rc, rc);
3138 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3139 break;
3140
3141 if (pThread->enmState == PDMTHREADSTATE_RUNNING)
3142 {
3143 E1KTXDESC desc;
3144 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3145 AssertRCReturn(rc, rc);
3146 /* Do not process descriptors in locked state */
3147 while (TDH != TDT && !pState->fLocked)
3148 {
3149 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3150 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3151 //if (!e1kCsEnter(pState, RT_SRC_POS))
3152 // return VERR_PERMISSION_DENIED;
3153 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3154 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3155 if (++TDH * sizeof(desc) >= TDLEN)
3156 TDH = 0;
3157 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3158 {
3159 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3160 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3161 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3162 }
3163 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3164 //e1kCsLeave(pState);
3165 }
3166 /// @todo: uncomment: pState->uStatIntTXQE++;
3167 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3168 e1kMutexRelease(pState);
3169 }
3170 }
3171 return VINF_SUCCESS;
3172}
3173
3174/**
3175 * Callback for consuming from transmit queue. It gets called in R3 whenever
3176 * we enqueue something in R0/GC.
3177 *
3178 * @returns true
3179 * @param pDevIns Pointer to device instance structure.
3180 * @param pItem Pointer to the element being dequeued (not used).
3181 * @thread ???
3182 */
3183static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3184{
3185 NOREF(pItem);
3186 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3187 E1kLog2(("%s e1kTxQueueConsumer: Waking up TX thread...\n", INSTANCE(pState)));
3188 int rc = RTSemEventSignal(pState->hTxSem);
3189 AssertRC(rc);
3190 return true;
3191}
3192
3193/**
3194 * Handler for the wakeup signaller queue.
3195 */
3196static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3197{
3198 e1kWakeupReceive(pDevIns);
3199 return true;
3200}
3201
3202#endif /* IN_RING3 */
3203
3204/**
3205 * Write handler for Transmit Descriptor Tail register.
3206 *
3207 * @param pState The device state structure.
3208 * @param offset Register offset in memory-mapped frame.
3209 * @param index Register index in register array.
3210 * @param value The value to store.
3211 * @param mask Used to implement partial writes (8 and 16-bit).
3212 * @thread EMT
3213 */
3214static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3215{
3216#ifndef IN_RING3
3217// return VINF_IOM_HC_MMIO_WRITE;
3218#endif
3219 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
3220 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3221 return rc;
3222 rc = e1kRegWriteDefault(pState, offset, index, value);
3223 /* All descriptors starting with head and not including tail belong to us. */
3224 /* Process them. */
3225 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3226 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
3227 /* Ignore TDT writes when the link is down. */
3228 if (TDH != TDT && (STATUS & STATUS_LU))
3229 {
3230 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
3231 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
3232 INSTANCE(pState), e1kGetTxLen(pState)));
3233#ifdef IN_RING3
3234 rc = RTSemEventSignal(pState->hTxSem);
3235 AssertRC(rc);
3236#else
3237 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
3238 if (RT_UNLIKELY(pItem))
3239 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
3240#endif /* !IN_RING3 */
3241
3242 }
3243 e1kCsTxLeave(pState);
3244
3245 return rc;
3246}
3247
3248/**
3249 * Write handler for Multicast Table Array registers.
3250 *
3251 * @param pState The device state structure.
3252 * @param offset Register offset in memory-mapped frame.
3253 * @param index Register index in register array.
3254 * @param value The value to store.
3255 * @thread EMT
3256 */
3257static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3258{
3259 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3260 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
3261
3262 return VINF_SUCCESS;
3263}
3264
3265/**
3266 * Read handler for Multicast Table Array registers.
3267 *
3268 * @returns VBox status code.
3269 *
3270 * @param pState The device state structure.
3271 * @param offset Register offset in memory-mapped frame.
3272 * @param index Register index in register array.
3273 * @thread EMT
3274 */
3275static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3276{
3277 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3278 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
3279
3280 return VINF_SUCCESS;
3281}
3282
3283/**
3284 * Write handler for Receive Address registers.
3285 *
3286 * @param pState The device state structure.
3287 * @param offset Register offset in memory-mapped frame.
3288 * @param index Register index in register array.
3289 * @param value The value to store.
3290 * @thread EMT
3291 */
3292static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3293{
3294 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3295 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
3296
3297 return VINF_SUCCESS;
3298}
3299
3300/**
3301 * Read handler for Receive Address registers.
3302 *
3303 * @returns VBox status code.
3304 *
3305 * @param pState The device state structure.
3306 * @param offset Register offset in memory-mapped frame.
3307 * @param index Register index in register array.
3308 * @thread EMT
3309 */
3310static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3311{
3312 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3313 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
3314
3315 return VINF_SUCCESS;
3316}
3317
3318/**
3319 * Write handler for VLAN Filter Table Array registers.
3320 *
3321 * @param pState The device state structure.
3322 * @param offset Register offset in memory-mapped frame.
3323 * @param index Register index in register array.
3324 * @param value The value to store.
3325 * @thread EMT
3326 */
3327static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3328{
3329 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
3330 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
3331
3332 return VINF_SUCCESS;
3333}
3334
3335/**
3336 * Read handler for VLAN Filter Table Array registers.
3337 *
3338 * @returns VBox status code.
3339 *
3340 * @param pState The device state structure.
3341 * @param offset Register offset in memory-mapped frame.
3342 * @param index Register index in register array.
3343 * @thread EMT
3344 */
3345static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3346{
3347 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
3348 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
3349
3350 return VINF_SUCCESS;
3351}
3352
3353/**
3354 * Read handler for unimplemented registers.
3355 *
3356 * Merely reports reads from unimplemented registers.
3357 *
3358 * @returns VBox status code.
3359 *
3360 * @param pState The device state structure.
3361 * @param offset Register offset in memory-mapped frame.
3362 * @param index Register index in register array.
3363 * @thread EMT
3364 */
3365
3366static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3367{
3368 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
3369 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3370 *pu32Value = 0;
3371
3372 return VINF_SUCCESS;
3373}
3374
3375/**
3376 * Default register read handler with automatic clear operation.
3377 *
3378 * Retrieves the value of register from register array in device state structure.
3379 * Then resets all bits.
3380 *
3381 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3382 * done in the caller.
3383 *
3384 * @returns VBox status code.
3385 *
3386 * @param pState The device state structure.
3387 * @param offset Register offset in memory-mapped frame.
3388 * @param index Register index in register array.
3389 * @thread EMT
3390 */
3391
3392static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3393{
3394 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3395 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
3396 pState->auRegs[index] = 0;
3397
3398 return rc;
3399}
3400
3401/**
3402 * Default register read handler.
3403 *
3404 * Retrieves the value of register from register array in device state structure.
3405 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
3406 *
3407 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3408 * done in the caller.
3409 *
3410 * @returns VBox status code.
3411 *
3412 * @param pState The device state structure.
3413 * @param offset Register offset in memory-mapped frame.
3414 * @param index Register index in register array.
3415 * @thread EMT
3416 */
3417
3418static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3419{
3420 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3421 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
3422
3423 return VINF_SUCCESS;
3424}
3425
3426/**
3427 * Write handler for unimplemented registers.
3428 *
3429 * Merely reports writes to unimplemented registers.
3430 *
3431 * @param pState The device state structure.
3432 * @param offset Register offset in memory-mapped frame.
3433 * @param index Register index in register array.
3434 * @param value The value to store.
3435 * @thread EMT
3436 */
3437
3438static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3439{
3440 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
3441 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3442
3443 return VINF_SUCCESS;
3444}
3445
3446/**
3447 * Default register write handler.
3448 *
3449 * Stores the value to the register array in device state structure. Only bits
3450 * corresponding to 1s both in 'writable' and 'mask' will be stored.
3451 *
3452 * @returns VBox status code.
3453 *
3454 * @param pState The device state structure.
3455 * @param offset Register offset in memory-mapped frame.
3456 * @param index Register index in register array.
3457 * @param value The value to store.
3458 * @param mask Used to implement partial writes (8 and 16-bit).
3459 * @thread EMT
3460 */
3461
3462static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3463{
3464 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3465 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
3466 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
3467
3468 return VINF_SUCCESS;
3469}
3470
3471/**
3472 * Search register table for matching register.
3473 *
3474 * @returns Index in the register table or -1 if not found.
3475 *
3476 * @param pState The device state structure.
3477 * @param uOffset Register offset in memory-mapped region.
3478 * @thread EMT
3479 */
3480static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
3481{
3482 int index;
3483
3484 for (index = 0; index < E1K_NUM_OF_REGS; index++)
3485 {
3486 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
3487 {
3488 return index;
3489 }
3490 }
3491
3492 return -1;
3493}
3494
3495/**
3496 * Handle register read operation.
3497 *
3498 * Looks up and calls appropriate handler.
3499 *
3500 * @returns VBox status code.
3501 *
3502 * @param pState The device state structure.
3503 * @param uOffset Register offset in memory-mapped frame.
3504 * @param pv Where to store the result.
3505 * @param cb Number of bytes to read.
3506 * @thread EMT
3507 */
3508static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
3509{
3510 uint32_t u32 = 0;
3511 uint32_t mask = 0;
3512 uint32_t shift;
3513 int rc = VINF_SUCCESS;
3514 int index = e1kRegLookup(pState, uOffset);
3515 const char *szInst = INSTANCE(pState);
3516#ifdef DEBUG
3517 char buf[9];
3518#endif
3519
3520 /*
3521 * From the spec:
3522 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3523 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3524 */
3525
3526 /*
3527 * To be able to write bytes and short word we convert them
3528 * to properly shifted 32-bit words and masks. The idea is
3529 * to keep register-specific handlers simple. Most accesses
3530 * will be 32-bit anyway.
3531 */
3532 switch (cb)
3533 {
3534 case 1: mask = 0x000000FF; break;
3535 case 2: mask = 0x0000FFFF; break;
3536 case 4: mask = 0xFFFFFFFF; break;
3537 default:
3538 return PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3539 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
3540 szInst, uOffset, cb);
3541 }
3542 if (index != -1)
3543 {
3544 if (s_e1kRegMap[index].readable)
3545 {
3546 /* Make the mask correspond to the bits we are about to read. */
3547 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
3548 mask <<= shift;
3549 if (!mask)
3550 return PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3551 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
3552 szInst, uOffset, cb);
3553 /*
3554 * Read it. Pass the mask so the handler knows what has to be read.
3555 * Mask out irrelevant bits.
3556 */
3557#ifdef E1K_GLOBAL_MUTEX
3558 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
3559#else
3560 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3561#endif
3562 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3563 return rc;
3564 //pState->fDelayInts = false;
3565 //pState->iStatIntLost += pState->iStatIntLostOne;
3566 //pState->iStatIntLostOne = 0;
3567 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32) & mask;
3568 //e1kCsLeave(pState);
3569 e1kMutexRelease(pState);
3570 E1kLog2(("%s At %08X read %s from %s (%s)\n",
3571 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3572 /* Shift back the result. */
3573 u32 >>= shift;
3574 }
3575 else
3576 {
3577 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
3578 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3579 }
3580 }
3581 else
3582 {
3583 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
3584 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
3585 }
3586
3587 memcpy(pv, &u32, cb);
3588 return rc;
3589}
3590
3591/**
3592 * Handle register write operation.
3593 *
3594 * Looks up and calls appropriate handler.
3595 *
3596 * @returns VBox status code.
3597 *
3598 * @param pState The device state structure.
3599 * @param uOffset Register offset in memory-mapped frame.
3600 * @param pv Where to fetch the value.
3601 * @param cb Number of bytes to write.
3602 * @thread EMT
3603 */
3604static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void *pv, unsigned cb)
3605{
3606 int rc = VINF_SUCCESS;
3607 int index = e1kRegLookup(pState, uOffset);
3608 uint32_t u32;
3609
3610 /*
3611 * From the spec:
3612 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3613 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3614 */
3615
3616 if (cb != 4)
3617 {
3618 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
3619 INSTANCE(pState), uOffset, cb));
3620 return VINF_SUCCESS;
3621 }
3622 if (uOffset & 3)
3623 {
3624 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
3625 INSTANCE(pState), uOffset, cb));
3626 return VINF_SUCCESS;
3627 }
3628 u32 = *(uint32_t*)pv;
3629 if (index != -1)
3630 {
3631 if (s_e1kRegMap[index].writable)
3632 {
3633 /*
3634 * Write it. Pass the mask so the handler knows what has to be written.
3635 * Mask out irrelevant bits.
3636 */
3637 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
3638 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3639#ifdef E1K_GLOBAL_MUTEX
3640 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
3641#else
3642 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3643#endif
3644 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3645 return rc;
3646 //pState->fDelayInts = false;
3647 //pState->iStatIntLost += pState->iStatIntLostOne;
3648 //pState->iStatIntLostOne = 0;
3649 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
3650 //e1kCsLeave(pState);
3651 e1kMutexRelease(pState);
3652 }
3653 else
3654 {
3655 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
3656 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3657 }
3658 }
3659 else
3660 {
3661 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
3662 INSTANCE(pState), uOffset, u32));
3663 }
3664 return rc;
3665}
3666
3667/**
3668 * I/O handler for memory-mapped read operations.
3669 *
3670 * @returns VBox status code.
3671 *
3672 * @param pDevIns The device instance.
3673 * @param pvUser User argument.
3674 * @param GCPhysAddr Physical address (in GC) where the read starts.
3675 * @param pv Where to store the result.
3676 * @param cb Number of bytes read.
3677 * @thread EMT
3678 */
3679PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
3680 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3681{
3682 NOREF(pvUser);
3683 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3684 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3685 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIORead), a);
3686
3687 Assert(uOffset < E1K_MM_SIZE);
3688
3689 int rc = e1kRegRead(pState, uOffset, pv, cb);
3690 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIORead), a);
3691 return rc;
3692}
3693
3694/**
3695 * Memory mapped I/O Handler for write operations.
3696 *
3697 * @returns VBox status code.
3698 *
3699 * @param pDevIns The device instance.
3700 * @param pvUser User argument.
3701 * @param GCPhysAddr Physical address (in GC) where the read starts.
3702 * @param pv Where to fetch the value.
3703 * @param cb Number of bytes to write.
3704 * @thread EMT
3705 */
3706PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
3707 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3708{
3709 NOREF(pvUser);
3710 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3711 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3712 int rc;
3713 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIOWrite), a);
3714
3715 Assert(uOffset < E1K_MM_SIZE);
3716 if (cb != 4)
3717 {
3718 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
3719 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
3720 }
3721 else
3722 rc = e1kRegWrite(pState, uOffset, pv, cb);
3723
3724 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIOWrite), a);
3725 return rc;
3726}
3727
3728/**
3729 * Port I/O Handler for IN operations.
3730 *
3731 * @returns VBox status code.
3732 *
3733 * @param pDevIns The device instance.
3734 * @param pvUser Pointer to the device state structure.
3735 * @param port Port number used for the IN operation.
3736 * @param pu32 Where to store the result.
3737 * @param cb Number of bytes read.
3738 * @thread EMT
3739 */
3740PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
3741 RTIOPORT port, uint32_t *pu32, unsigned cb)
3742{
3743 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3744 int rc = VINF_SUCCESS;
3745 const char *szInst = INSTANCE(pState);
3746 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
3747
3748 port -= pState->addrIOPort;
3749 if (cb != 4)
3750 {
3751 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
3752 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3753 }
3754 else
3755 switch (port)
3756 {
3757 case 0x00: /* IOADDR */
3758 *pu32 = pState->uSelectedReg;
3759 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3760 break;
3761 case 0x04: /* IODATA */
3762 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
3763 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3764 break;
3765 default:
3766 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
3767 //*pRC = VERR_IOM_IOPORT_UNUSED;
3768 }
3769
3770 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
3771 return rc;
3772}
3773
3774
3775/**
3776 * Port I/O Handler for OUT operations.
3777 *
3778 * @returns VBox status code.
3779 *
3780 * @param pDevIns The device instance.
3781 * @param pvUser User argument.
3782 * @param Port Port number used for the IN operation.
3783 * @param u32 The value to output.
3784 * @param cb The value size in bytes.
3785 * @thread EMT
3786 */
3787PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
3788 RTIOPORT port, uint32_t u32, unsigned cb)
3789{
3790 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3791 int rc = VINF_SUCCESS;
3792 const char *szInst = INSTANCE(pState);
3793 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
3794
3795 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
3796 if (cb != 4)
3797 {
3798 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
3799 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3800 }
3801 else
3802 {
3803 port -= pState->addrIOPort;
3804 switch (port)
3805 {
3806 case 0x00: /* IOADDR */
3807 pState->uSelectedReg = u32;
3808 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
3809 break;
3810 case 0x04: /* IODATA */
3811 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
3812 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
3813 break;
3814 default:
3815 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
3816 /** @todo Do we need to return an error here?
3817 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
3818 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
3819 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
3820 }
3821 }
3822
3823 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
3824 return rc;
3825}
3826
3827#ifdef IN_RING3
3828/**
3829 * Dump complete device state to log.
3830 *
3831 * @param pState Pointer to device state.
3832 */
3833static void e1kDumpState(E1KSTATE *pState)
3834{
3835 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
3836 {
3837 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
3838 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
3839 }
3840#ifdef E1K_INT_STATS
3841 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
3842 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
3843 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
3844 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
3845 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
3846 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
3847 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
3848 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
3849 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
3850 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
3851 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
3852 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
3853 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
3854 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
3855 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
3856 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
3857 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
3858 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
3859 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
3860 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
3861 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
3862 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
3863 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
3864 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
3865 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
3866 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
3867 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
3868#endif /* E1K_INT_STATS */
3869}
3870
3871/**
3872 * Map PCI I/O region.
3873 *
3874 * @return VBox status code.
3875 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
3876 * @param iRegion The region number.
3877 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
3878 * I/O port, else it's a physical address.
3879 * This address is *NOT* relative to pci_mem_base like earlier!
3880 * @param cb Region size.
3881 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3882 * @thread EMT
3883 */
3884static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
3885 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3886{
3887 int rc;
3888 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
3889
3890 switch (enmType)
3891 {
3892 case PCI_ADDRESS_SPACE_IO:
3893 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
3894 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3895 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
3896 if (RT_FAILURE(rc))
3897 break;
3898 if (pState->fR0Enabled)
3899 {
3900 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3901 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
3902 if (RT_FAILURE(rc))
3903 break;
3904 }
3905 if (pState->fGCEnabled)
3906 {
3907 rc = PDMDevHlpIOPortRegisterGC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3908 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
3909 }
3910 break;
3911 case PCI_ADDRESS_SPACE_MEM:
3912 pState->addrMMReg = GCPhysAddress;
3913 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
3914 e1kMMIOWrite, e1kMMIORead, NULL, "E1000");
3915 if (pState->fR0Enabled)
3916 {
3917 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, 0,
3918 "e1kMMIOWrite", "e1kMMIORead", NULL);
3919 if (RT_FAILURE(rc))
3920 break;
3921 }
3922 if (pState->fGCEnabled)
3923 {
3924 rc = PDMDevHlpMMIORegisterGC(pPciDev->pDevIns, GCPhysAddress, cb, 0,
3925 "e1kMMIOWrite", "e1kMMIORead", NULL);
3926 }
3927 break;
3928 default:
3929 /* We should never get here */
3930 AssertMsgFailed(("Invalid PCI address space param in map callback"));
3931 rc = VERR_INTERNAL_ERROR;
3932 break;
3933 }
3934 return rc;
3935}
3936
3937/**
3938 * Check if the device can receive data now.
3939 * This must be called before the pfnRecieve() method is called.
3940 *
3941 * @returns Number of bytes the device can receive.
3942 * @param pInterface Pointer to the interface structure containing the called function pointer.
3943 * @thread EMT
3944 */
3945static int e1kCanReceive(E1KSTATE *pState)
3946{
3947 size_t cb;
3948
3949 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
3950 return VERR_NET_NO_BUFFER_SPACE;
3951 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
3952 return VERR_NET_NO_BUFFER_SPACE;
3953
3954 if (RDH < RDT)
3955 cb = (RDT - RDH) * pState->u16RxBSize;
3956 else if (RDH > RDT)
3957 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
3958 else
3959 {
3960 cb = 0;
3961 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
3962 }
3963
3964 e1kCsRxLeave(pState);
3965 e1kMutexRelease(pState);
3966 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
3967}
3968
3969static DECLCALLBACK(int) e1kWaitReceiveAvail(PPDMINETWORKPORT pInterface, unsigned cMillies)
3970{
3971 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkPort);
3972 int rc = e1kCanReceive(pState);
3973
3974 if (RT_SUCCESS(rc))
3975 return VINF_SUCCESS;
3976 if (RT_UNLIKELY(cMillies == 0))
3977 return VERR_NET_NO_BUFFER_SPACE;
3978
3979 rc = VERR_INTERRUPTED;
3980 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
3981 STAM_PROFILE_START(&pState->StatRxOverflow, a);
3982 while (RT_LIKELY(PDMDevHlpVMState(pState->CTX_SUFF(pDevIns)) == VMSTATE_RUNNING))
3983 {
3984 int rc2 = e1kCanReceive(pState);
3985 if (RT_SUCCESS(rc2))
3986 {
3987 rc = VINF_SUCCESS;
3988 break;
3989 }
3990 E1kLogRel(("E1000 e1kWaitReceiveAvail: waiting cMillies=%u...\n",
3991 cMillies));
3992 E1kLog(("%s e1kWaitReceiveAvail: waiting cMillies=%u...\n",
3993 INSTANCE(pState), cMillies));
3994 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
3995 }
3996 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
3997 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
3998
3999 return rc;
4000}
4001
4002
4003/**
4004 * Matches the packet addresses against Receive Address table. Looks for
4005 * exact matches only.
4006 *
4007 * @returns true if address matches.
4008 * @param pState Pointer to the state structure.
4009 * @param pvBuf The ethernet packet.
4010 * @param cb Number of bytes available in the packet.
4011 * @thread EMT
4012 */
4013static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4014{
4015 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4016 {
4017 E1KRAELEM* ra = pState->aRecAddr.array + i;
4018
4019 /* Valid address? */
4020 if (ra->ctl & RA_CTL_AV)
4021 {
4022 Assert((ra->ctl & RA_CTL_AS) < 2);
4023 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4024 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4025 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4026 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4027 /*
4028 * Address Select:
4029 * 00b = Destination address
4030 * 01b = Source address
4031 * 10b = Reserved
4032 * 11b = Reserved
4033 * Since ethernet header is (DA, SA, len) we can use address
4034 * select as index.
4035 */
4036 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4037 ra->addr, sizeof(ra->addr)) == 0)
4038 return true;
4039 }
4040 }
4041
4042 return false;
4043}
4044
4045/**
4046 * Returns the value of a bit in a bit vector.
4047 *
4048 * @returns true if bit is set.
4049 * @param pBitVector The ethernet packet.
4050 * @param u16Bit Bit number.
4051 * @thread EMT
4052 */
4053DECLINLINE(bool) e1kGetBit(uint32_t* pBitVector, uint16_t u16Bit)
4054{
4055 return !!(pBitVector[u16Bit] & (1 << (u16Bit & 0x1F)));
4056}
4057
4058/**
4059 * Matches the packet addresses against Multicast Table Array.
4060 *
4061 * @remarks This is imperfect match since it matches not exact address but
4062 * a subset of addresses.
4063 *
4064 * @returns true if address matches.
4065 * @param pState Pointer to the state structure.
4066 * @param pvBuf The ethernet packet.
4067 * @param cb Number of bytes available in the packet.
4068 * @thread EMT
4069 */
4070static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4071{
4072 /* Get bits 32..47 of destination address */
4073 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4074
4075 unsigned offset = GET_BITS(RCTL, MO);
4076 /*
4077 * offset means:
4078 * 00b = bits 36..47
4079 * 01b = bits 35..46
4080 * 10b = bits 34..45
4081 * 11b = bits 32..43
4082 */
4083 if (offset < 3)
4084 u16Bit = u16Bit >> (4 - offset);
4085 return e1kGetBit(pState->auMTA, u16Bit & 0xFFF);
4086}
4087
4088/**
4089 * Determines if the packet is to be delivered to upper layer. The following
4090 * filters supported:
4091 * - Exact Unicast/Multicast
4092 * - Promiscuous Unicast/Multicast
4093 * - Multicast
4094 * - VLAN
4095 *
4096 * @returns true if packet is intended for this node.
4097 * @param pState Pointer to the state structure.
4098 * @param pvBuf The ethernet packet.
4099 * @param cb Number of bytes available in the packet.
4100 * @param pStatus Bit field to store status bits.
4101 * @thread EMT
4102 */
4103static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4104{
4105 Assert(cb > 14);
4106 /* Assume that we fail to pass exact filter. */
4107 pStatus->fPIF = false;
4108 pStatus->fVP = false;
4109 /* Discard oversized packets */
4110 if (cb > E1K_MAX_RX_PKT_SIZE)
4111 {
4112 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4113 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4114 E1K_INC_CNT32(ROC);
4115 return false;
4116 }
4117 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4118 {
4119 /* When long packet reception is disabled packets over 1522 are discarded */
4120 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4121 INSTANCE(pState), cb));
4122 E1K_INC_CNT32(ROC);
4123 return false;
4124 }
4125
4126 /* Broadcast filtering */
4127 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4128 return true;
4129 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4130 if (e1kIsMulticast(pvBuf))
4131 {
4132 /* Is multicast promiscuous enabled? */
4133 if (RCTL & RCTL_MPE)
4134 return true;
4135 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4136 /* Try perfect matches first */
4137 if (e1kPerfectMatch(pState, pvBuf))
4138 {
4139 pStatus->fPIF = true;
4140 return true;
4141 }
4142 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4143 if (e1kImperfectMatch(pState, pvBuf))
4144 return true;
4145 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
4146 }
4147 else {
4148 /* Is unicast promiscuous enabled? */
4149 if (RCTL & RCTL_UPE)
4150 return true;
4151 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
4152 if (e1kPerfectMatch(pState, pvBuf))
4153 {
4154 pStatus->fPIF = true;
4155 return true;
4156 }
4157 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4158 }
4159 /* Is VLAN filtering enabled? */
4160 if (RCTL & RCTL_VFE)
4161 {
4162 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4163 /* Compare TPID with VLAN Ether Type */
4164 if (u16Ptr[6] == VET)
4165 {
4166 pStatus->fVP = true;
4167 /* It is 802.1q packet indeed, let's filter by VID */
4168 if (e1kGetBit(pState->auVFTA, RT_BE2H_U16(u16Ptr[7]) & 0xFFF))
4169 return true;
4170 E1kLog2(("%s Packet filter: no VLAN match\n", INSTANCE(pState)));
4171 }
4172 }
4173 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
4174 return false;
4175}
4176
4177/**
4178 * Receive data from the network.
4179 *
4180 * @returns VBox status code.
4181 * @param pInterface Pointer to the interface structure containing the called function pointer.
4182 * @param pvBuf The available data.
4183 * @param cb Number of bytes available in the buffer.
4184 * @thread ???
4185 */
4186static DECLCALLBACK(int) e1kReceive(PPDMINETWORKPORT pInterface, const void *pvBuf, size_t cb)
4187{
4188 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkPort);
4189 int rc = VINF_SUCCESS;
4190
4191 /* Discard incoming packets in locked state */
4192 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
4193 {
4194 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
4195 return VINF_SUCCESS;
4196 }
4197
4198 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
4199 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4200 if (RT_LIKELY(rc == VINF_SUCCESS))
4201 {
4202 //if (!e1kCsEnter(pState, RT_SRC_POS))
4203 // return VERR_PERMISSION_DENIED;
4204
4205 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
4206
4207 /* Update stats */
4208 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
4209 {
4210 E1K_INC_CNT32(TPR);
4211 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
4212 e1kCsLeave(pState);
4213 }
4214 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
4215 E1KRXDST status;
4216 memset(&status, 0, sizeof(status));
4217 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
4218 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
4219 if (fPassed)
4220 {
4221 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
4222 }
4223 //e1kCsLeave(pState);
4224 e1kMutexRelease(pState);
4225 }
4226 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
4227
4228 return rc;
4229}
4230
4231/**
4232 * Gets the pointer to the status LED of a unit.
4233 *
4234 * @returns VBox status code.
4235 * @param pInterface Pointer to the interface structure.
4236 * @param iLUN The unit which status LED we desire.
4237 * @param ppLed Where to store the LED pointer.
4238 * @thread EMT
4239 */
4240static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4241{
4242 E1KSTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
4243 int rc = VERR_PDM_LUN_NOT_FOUND;
4244
4245 if (iLUN == 0)
4246 {
4247 *ppLed = &pState->led;
4248 rc = VINF_SUCCESS;
4249 }
4250 return rc;
4251}
4252
4253/**
4254 * Gets the current Media Access Control (MAC) address.
4255 *
4256 * @returns VBox status code.
4257 * @param pInterface Pointer to the interface structure containing the called function pointer.
4258 * @param pMac Where to store the MAC address.
4259 * @thread EMT
4260 */
4261static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4262{
4263 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4264 pState->eeprom.getMac(pMac);
4265 return VINF_SUCCESS;
4266}
4267
4268
4269/**
4270 * Gets the new link state.
4271 *
4272 * @returns The current link state.
4273 * @param pInterface Pointer to the interface structure containing the called function pointer.
4274 * @thread EMT
4275 */
4276static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
4277{
4278 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4279 if (STATUS & STATUS_LU)
4280 return PDMNETWORKLINKSTATE_UP;
4281 return PDMNETWORKLINKSTATE_DOWN;
4282}
4283
4284
4285/**
4286 * Sets the new link state.
4287 *
4288 * @returns VBox status code.
4289 * @param pInterface Pointer to the interface structure containing the called function pointer.
4290 * @param enmState The new link state
4291 * @thread EMT
4292 */
4293static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4294{
4295 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4296 bool fOldUp = !!(STATUS & STATUS_LU);
4297 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
4298
4299 if (fNewUp != fOldUp)
4300 {
4301 if (fNewUp)
4302 {
4303 E1kLog(("%s Link is up\n", INSTANCE(pState)));
4304 STATUS |= STATUS_LU;
4305 Phy::setLinkStatus(&pState->phy, true);
4306 }
4307 else
4308 {
4309 E1kLog(("%s Link is down\n", INSTANCE(pState)));
4310 STATUS &= ~STATUS_LU;
4311 Phy::setLinkStatus(&pState->phy, false);
4312 }
4313 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4314 if (pState->pDrv)
4315 pState->pDrv->pfnNotifyLinkChanged(pState->pDrv, enmState);
4316 }
4317 return VINF_SUCCESS;
4318}
4319
4320/**
4321 * Provides interfaces to the driver.
4322 *
4323 * @returns Pointer to interface. NULL if the interface is not supported.
4324 * @param pInterface Pointer to this interface structure.
4325 * @param enmInterface The requested interface identification.
4326 * @thread EMT
4327 */
4328static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, PDMINTERFACE enmInterface)
4329{
4330 E1KSTATE *pState = IFACE_TO_STATE(pInterface, IBase);
4331 Assert(&pState->IBase == pInterface);
4332 switch (enmInterface)
4333 {
4334 case PDMINTERFACE_BASE:
4335 return &pState->IBase;
4336 case PDMINTERFACE_NETWORK_PORT:
4337 return &pState->INetworkPort;
4338 case PDMINTERFACE_NETWORK_CONFIG:
4339 return &pState->INetworkConfig;
4340 case PDMINTERFACE_LED_PORTS:
4341 return &pState->ILeds;
4342 default:
4343 return NULL;
4344 }
4345}
4346
4347/**
4348 * Prepares for state saving.
4349 *
4350 * @returns VBox status code.
4351 * @param pDevIns The device instance.
4352 * @param pSSMHandle The handle to save the state to.
4353 */
4354static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4355{
4356 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4357
4358 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4359 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4360 return rc;
4361 e1kCsLeave(pState);
4362 return VINF_SUCCESS;
4363#if 0
4364 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4365 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4366 return rc;
4367 /* 1) Prevent all threads from modifying the state and memory */
4368 //pState->fLocked = true;
4369 /* 2) Cancel all timers */
4370#ifdef E1K_USE_TX_TIMERS
4371 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
4372#ifndef E1K_NO_TAD
4373 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
4374#endif /* E1K_NO_TAD */
4375#endif /* E1K_USE_TX_TIMERS */
4376#ifdef E1K_USE_RX_TIMERS
4377 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
4378 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
4379#endif /* E1K_USE_RX_TIMERS */
4380 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
4381 /* 3) Did I forget anything? */
4382 E1kLog(("%s Locked\n", INSTANCE(pState)));
4383 e1kMutexRelease(pState);
4384 return VINF_SUCCESS;
4385#endif
4386}
4387
4388
4389/**
4390 * Saves the state of device.
4391 *
4392 * @returns VBox status code.
4393 * @param pDevIns The device instance.
4394 * @param pSSMHandle The handle to save the state to.
4395 */
4396static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4397{
4398 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4399
4400 e1kDumpState(pState);
4401 SSMR3PutMem(pSSMHandle, pState->auRegs, sizeof(pState->auRegs));
4402 SSMR3PutBool(pSSMHandle, pState->fIntRaised);
4403 Phy::saveState(pSSMHandle, &pState->phy);
4404 SSMR3PutU32(pSSMHandle, pState->uSelectedReg);
4405 SSMR3PutMem(pSSMHandle, pState->auMTA, sizeof(pState->auMTA));
4406 SSMR3PutMem(pSSMHandle, &pState->aRecAddr, sizeof(pState->aRecAddr));
4407 SSMR3PutMem(pSSMHandle, pState->auVFTA, sizeof(pState->auVFTA));
4408 SSMR3PutU64(pSSMHandle, pState->u64AckedAt);
4409 SSMR3PutU16(pSSMHandle, pState->u16RxBSize);
4410 //SSMR3PutBool(pSSMHandle, pState->fDelayInts);
4411 //SSMR3PutBool(pSSMHandle, pState->fIntMaskUsed);
4412 SSMR3PutU16(pSSMHandle, pState->u16TxPktLen);
4413 SSMR3PutMem(pSSMHandle, pState->aTxPacket, pState->u16TxPktLen);
4414 SSMR3PutBool(pSSMHandle, pState->fIPcsum);
4415 SSMR3PutBool(pSSMHandle, pState->fTCPcsum);
4416 SSMR3PutMem(pSSMHandle, &pState->contextTSE, sizeof(pState->contextTSE));
4417 SSMR3PutMem(pSSMHandle, &pState->contextNormal, sizeof(pState->contextNormal));
4418 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
4419 return VINF_SUCCESS;
4420}
4421
4422#if 0
4423/**
4424 * Cleanup after saving.
4425 *
4426 * @returns VBox status code.
4427 * @param pDevIns The device instance.
4428 * @param pSSMHandle The handle to save the state to.
4429 */
4430static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4431{
4432 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4433
4434 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4435 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4436 return rc;
4437 /* If VM is being powered off unlocking will result in assertions in PGM */
4438 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
4439 pState->fLocked = false;
4440 else
4441 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
4442 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
4443 e1kMutexRelease(pState);
4444 return VINF_SUCCESS;
4445}
4446#endif
4447
4448/**
4449 * Sync with .
4450 *
4451 * @returns VBox status code.
4452 * @param pDevIns The device instance.
4453 * @param pSSMHandle The handle to the saved state.
4454 */
4455static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4456{
4457 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4458
4459 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4460 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4461 return rc;
4462 e1kCsLeave(pState);
4463 return VINF_SUCCESS;
4464}
4465
4466/**
4467 * Restore previously saved state of device.
4468 *
4469 * @returns VBox status code.
4470 * @param pDevIns The device instance.
4471 * @param pSSMHandle The handle to the saved state.
4472 * @param u32Version The data unit version number.
4473 */
4474static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
4475{
4476 if (u32Version != E1K_SAVEDSTATE_VERSION)
4477 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4478
4479 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4480 SSMR3GetMem(pSSMHandle, &pState->auRegs, sizeof(pState->auRegs));
4481 SSMR3GetBool(pSSMHandle, &pState->fIntRaised);
4482 /** @todo: PHY should be made a separate device with its own versioning */
4483 Phy::loadState(pSSMHandle, &pState->phy);
4484 SSMR3GetU32(pSSMHandle, &pState->uSelectedReg);
4485 SSMR3GetMem(pSSMHandle, &pState->auMTA, sizeof(pState->auMTA));
4486 SSMR3GetMem(pSSMHandle, &pState->aRecAddr, sizeof(pState->aRecAddr));
4487 SSMR3GetMem(pSSMHandle, &pState->auVFTA, sizeof(pState->auVFTA));
4488 SSMR3GetU64(pSSMHandle, &pState->u64AckedAt);
4489 SSMR3GetU16(pSSMHandle, &pState->u16RxBSize);
4490 //SSMR3GetBool(pSSMHandle, pState->fDelayInts);
4491 //SSMR3GetBool(pSSMHandle, pState->fIntMaskUsed);
4492 SSMR3GetU16(pSSMHandle, &pState->u16TxPktLen);
4493 SSMR3GetMem(pSSMHandle, &pState->aTxPacket, pState->u16TxPktLen);
4494 SSMR3GetBool(pSSMHandle, &pState->fIPcsum);
4495 SSMR3GetBool(pSSMHandle, &pState->fTCPcsum);
4496 SSMR3GetMem(pSSMHandle, &pState->contextTSE, sizeof(pState->contextTSE));
4497 SSMR3GetMem(pSSMHandle, &pState->contextNormal, sizeof(pState->contextNormal));
4498 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
4499 e1kDumpState(pState);
4500 return VINF_SUCCESS;
4501}
4502
4503/**
4504 * Link status adjustments after loading.
4505 *
4506 * @returns VBox status code.
4507 * @param pDevIns The device instance.
4508 * @param pSSMHandle The handle to the saved state.
4509 */
4510#if 0
4511static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
4512{
4513 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4514
4515 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4516 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4517 return rc;
4518 /*
4519 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
4520 * passed to us. We go through all this stuff if the link was up only.
4521 */
4522 if (STATUS & STATUS_LU)
4523 {
4524 E1kLog(("%s Link is down temporarely\n", INSTANCE(pState)));
4525 STATUS &= ~STATUS_LU;
4526 Phy::setLinkStatus(&pState->phy, false);
4527 e1kRaiseInterrupt(pState, ICR_LSC);
4528 /* Restore the link back in half a second. */
4529 e1kArmTimer(pState, pState->pLUTimer, 500000);
4530 }
4531 e1kMutexRelease(pState);
4532 return VINF_SUCCESS;
4533}
4534#endif
4535
4536/**
4537 * Sets 8-bit register in PCI configuration space.
4538 * @param refPciDev The PCI device.
4539 * @param uOffset The register offset.
4540 * @param u16Value The value to store in the register.
4541 * @thread EMT
4542 */
4543DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
4544{
4545 Assert(uOffset < sizeof(refPciDev.config));
4546 refPciDev.config[uOffset] = u8Value;
4547}
4548
4549/**
4550 * Sets 16-bit register in PCI configuration space.
4551 * @param refPciDev The PCI device.
4552 * @param uOffset The register offset.
4553 * @param u16Value The value to store in the register.
4554 * @thread EMT
4555 */
4556DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
4557{
4558 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
4559 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
4560}
4561
4562/**
4563 * Sets 32-bit register in PCI configuration space.
4564 * @param refPciDev The PCI device.
4565 * @param uOffset The register offset.
4566 * @param u32Value The value to store in the register.
4567 * @thread EMT
4568 */
4569DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
4570{
4571 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
4572 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
4573}
4574
4575/**
4576 * Set PCI configuration space registers.
4577 *
4578 * @param pci Reference to PCI device structure.
4579 * @thread EMT
4580 */
4581static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
4582{
4583 Assert(eChip < RT_ELEMENTS(g_Chips));
4584 /* Configure PCI Device, assume 32-bit mode ******************************/
4585 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
4586 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
4587 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
4588 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
4589
4590 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
4591 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
4592 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS, 0x0230);
4593 /* Stepping A2 */
4594 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
4595 /* Ethernet adapter */
4596 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
4597 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
4598 /* normal single function Ethernet controller */
4599 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
4600 /* Memory Register Base Address */
4601 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
4602 /* Memory Flash Base Address */
4603 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
4604 /* IO Register Base Address */
4605 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
4606 /* Expansion ROM Base Address */
4607 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
4608 /* Capabilities Pointer */
4609 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
4610 /* Interrupt Pin: INTA# */
4611 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
4612 /* Max_Lat/Min_Gnt: very high priority and time slice */
4613 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
4614 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
4615
4616 /* PCI Power Management Registers ****************************************/
4617 /* Capability ID: PCI Power Management Registers */
4618 e1kPCICfgSetU8( pci, 0xDC, 0x01);
4619 /* Next Item Pointer: PCI-X */
4620 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
4621 /* Power Management Capabilities: PM disabled, DSI */
4622 e1kPCICfgSetU16(pci, 0xDC + 2, 0x0022);
4623 /* Power Management Control / Status Register: PM disabled */
4624 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
4625 /* PMCSR_BSE Bridge Support Extensions: Not supported */
4626 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
4627 /* Data Register: PM disabled, always 0 */
4628 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
4629
4630 /* PCI-X Configuration Registers *****************************************/
4631 /* Capability ID: PCI-X Configuration Registers */
4632 e1kPCICfgSetU8( pci, 0xE4, 0x07);
4633 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
4634 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
4635 /* PCI-X Command: Enable Relaxed Ordering */
4636 e1kPCICfgSetU16(pci, 0xE4 + 2, 0x0002);
4637 /* PCI-X Status: 32-bit, 66MHz*/
4638 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
4639}
4640
4641/**
4642 * Construct a device instance for a VM.
4643 *
4644 * @returns VBox status.
4645 * @param pDevIns The device instance data.
4646 * If the registration structure is needed, pDevIns->pDevReg points to it.
4647 * @param iInstance Instance number. Use this to figure out which registers and such to use.
4648 * The device number is also found in pDevIns->iInstance, but since it's
4649 * likely to be freqently used PDM passes it as parameter.
4650 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
4651 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
4652 * iInstance it's expected to be used a bit in this function.
4653 * @thread EMT
4654 */
4655static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4656{
4657 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4658 int rc;
4659
4660 /* Init handles and log related stuff. */
4661 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
4662 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
4663 pState->hTxSem = NIL_RTSEMEVENT;
4664 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
4665
4666 /*
4667 * Validate configuration.
4668 */
4669 if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0"))
4670 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4671 N_("Invalid configuraton for E1000 device"));
4672
4673 /** @todo: LineSpeed unused! */
4674
4675 /* Get config params */
4676 rc = CFGMR3QueryBytes(pCfgHandle, "MAC", pState->macAddress.au8,
4677 sizeof(pState->macAddress.au8));
4678 if (RT_FAILURE(rc))
4679 return PDMDEV_SET_ERROR(pDevIns, rc,
4680 N_("Configuration error: Failed to get MAC address"));
4681 rc = CFGMR3QueryBool(pCfgHandle, "CableConnected", &pState->fCableConnected);
4682 if (RT_FAILURE(rc))
4683 return PDMDEV_SET_ERROR(pDevIns, rc,
4684 N_("Configuration error: Failed to get the value of 'CableConnected'"));
4685 rc = CFGMR3QueryU32(pCfgHandle, "AdapterType", (uint32_t*)&pState->eChip);
4686 if (RT_FAILURE(rc))
4687 return PDMDEV_SET_ERROR(pDevIns, rc,
4688 N_("Configuration error: Failed to get the value of 'AdapterType'"));
4689 Assert(pState->eChip <= E1K_CHIP_82545EM);
4690
4691 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
4692
4693 /* Initialize state structure */
4694 pState->fR0Enabled = true;
4695 pState->fGCEnabled = true;
4696 pState->pDevInsR3 = pDevIns;
4697 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4698 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4699 pState->u16TxPktLen = 0;
4700 pState->fIPcsum = false;
4701 pState->fTCPcsum = false;
4702 pState->fIntMaskUsed = false;
4703 pState->fDelayInts = false;
4704 pState->fLocked = false;
4705 pState->u64AckedAt = 0;
4706 pState->led.u32Magic = PDMLED_MAGIC;
4707 pState->u32PktNo = 1;
4708
4709#ifdef E1K_INT_STATS
4710 pState->uStatInt = 0;
4711 pState->uStatIntTry = 0;
4712 pState->uStatIntLower = 0;
4713 pState->uStatIntDly = 0;
4714 pState->uStatDisDly = 0;
4715 pState->iStatIntLost = 0;
4716 pState->iStatIntLostOne = 0;
4717 pState->uStatIntLate = 0;
4718 pState->uStatIntMasked = 0;
4719 pState->uStatIntEarly = 0;
4720 pState->uStatIntRx = 0;
4721 pState->uStatIntTx = 0;
4722 pState->uStatIntICS = 0;
4723 pState->uStatIntRDTR = 0;
4724 pState->uStatIntRXDMT0 = 0;
4725 pState->uStatIntTXQE = 0;
4726 pState->uStatTxNoRS = 0;
4727 pState->uStatTxIDE = 0;
4728 pState->uStatTAD = 0;
4729 pState->uStatTID = 0;
4730 pState->uStatRAD = 0;
4731 pState->uStatRID = 0;
4732 pState->uStatRxFrm = 0;
4733 pState->uStatTxFrm = 0;
4734 pState->uStatDescCtx = 0;
4735 pState->uStatDescDat = 0;
4736 pState->uStatDescLeg = 0;
4737#endif /* E1K_INT_STATS */
4738
4739 /* Interfaces */
4740 pState->IBase.pfnQueryInterface = e1kQueryInterface;
4741 pState->INetworkPort.pfnWaitReceiveAvail = e1kWaitReceiveAvail;
4742 pState->INetworkPort.pfnReceive = e1kReceive;
4743 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
4744 pState->INetworkConfig.pfnGetMac = e1kGetMac;
4745 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
4746 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
4747
4748 /* Initialize the EEPROM */
4749 pState->eeprom.init(pState->macAddress);
4750
4751 /* Initialize internal PHY */
4752 Phy::init(&pState->phy, iInstance,
4753 pState->eChip == E1K_CHIP_82543GC?
4754 PHY_EPID_M881000 : PHY_EPID_M881011);
4755 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
4756
4757 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance,
4758 E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE),
4759 e1kSavePrep, e1kSaveExec, NULL,
4760 e1kLoadPrep, e1kLoadExec, NULL);
4761 if (RT_FAILURE(rc))
4762 return rc;
4763
4764 /* Initialize critical section */
4765 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, pState->szInstance);
4766 if (RT_FAILURE(rc))
4767 return rc;
4768#ifndef E1K_GLOBAL_MUTEX
4769 char szTmp[sizeof(pState->szInstance) + 2];
4770 RTStrPrintf(szTmp, sizeof(szTmp), "%sRX", pState->szInstance);
4771 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, szTmp);
4772 if (RT_FAILURE(rc))
4773 return rc;
4774#endif
4775
4776 /* Set PCI config registers */
4777 e1kConfigurePCI(pState->pciDevice, pState->eChip);
4778 /* Register PCI device */
4779 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
4780 if (RT_FAILURE(rc))
4781 return rc;
4782
4783 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
4784 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
4785 PCI_ADDRESS_SPACE_MEM, e1kMap);
4786 if (RT_FAILURE(rc))
4787 return rc;
4788 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
4789 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
4790 PCI_ADDRESS_SPACE_IO, e1kMap);
4791 if (RT_FAILURE(rc))
4792 return rc;
4793
4794 /* Create transmit queue */
4795 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4796 e1kTxQueueConsumer, true, &pState->pTxQueueR3);
4797 if (RT_FAILURE(rc))
4798 return rc;
4799 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
4800 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
4801
4802 /* Create the RX notifier signaller. */
4803 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4804 e1kCanRxQueueConsumer, true, &pState->pCanRxQueueR3);
4805 if (RT_FAILURE(rc))
4806 return rc;
4807 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
4808 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
4809
4810#ifdef E1K_USE_TX_TIMERS
4811 /* Create Transmit Interrupt Delay Timer */
4812 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer,
4813 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
4814 if (RT_FAILURE(rc))
4815 return rc;
4816 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
4817 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
4818
4819# ifndef E1K_NO_TAD
4820 /* Create Transmit Absolute Delay Timer */
4821 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer,
4822 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
4823 if (RT_FAILURE(rc))
4824 return rc;
4825 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
4826 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
4827# endif /* E1K_NO_TAD */
4828#endif /* E1K_USE_TX_TIMERS */
4829
4830#ifdef E1K_USE_RX_TIMERS
4831 /* Create Receive Interrupt Delay Timer */
4832 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer,
4833 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
4834 if (RT_FAILURE(rc))
4835 return rc;
4836 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
4837 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
4838
4839 /* Create Receive Absolute Delay Timer */
4840 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer,
4841 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
4842 if (RT_FAILURE(rc))
4843 return rc;
4844 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
4845 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
4846#endif /* E1K_USE_RX_TIMERS */
4847
4848 /* Create Late Interrupt Timer */
4849 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer,
4850 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
4851 if (RT_FAILURE(rc))
4852 return rc;
4853 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
4854 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
4855
4856 /* Create Link Up Timer */
4857 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer,
4858 "E1000 Link Up Timer", &pState->pLUTimer);
4859 if (RT_FAILURE(rc))
4860 return rc;
4861
4862 /* Status driver */
4863 PPDMIBASE pBase;
4864 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
4865 if (RT_FAILURE(rc))
4866 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
4867 pState->pLedsConnector = (PPDMILEDCONNECTORS)pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
4868
4869 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
4870 if (RT_SUCCESS(rc))
4871 {
4872 if (rc == VINF_NAT_DNS)
4873 {
4874 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
4875 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4876 }
4877 pState->pDrv = (PPDMINETWORKCONNECTOR)
4878 pState->pDrvBase->pfnQueryInterface(pState->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
4879 if (!pState->pDrv)
4880 {
4881 AssertMsgFailed(("%s Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
4882 return VERR_PDM_MISSING_INTERFACE_BELOW;
4883 }
4884 }
4885 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4886 {
4887 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
4888 }
4889 else
4890 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
4891
4892 rc = RTSemEventCreate(&pState->hTxSem);
4893 if (RT_FAILURE(rc))
4894 return rc;
4895 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
4896 if (RT_FAILURE(rc))
4897 return rc;
4898
4899 e1kHardReset(pState);
4900
4901 rc = PDMDevHlpPDMThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");
4902 if (RT_FAILURE(rc))
4903 return rc;
4904
4905#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
4906 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/E1k%d/MMIO/ReadGC", iInstance);
4907 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/E1k%d/MMIO/ReadHC", iInstance);
4908 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/E1k%d/MMIO/WriteGC", iInstance);
4909 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/E1k%d/MMIO/WriteHC", iInstance);
4910 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
4911 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
4912 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/E1k%d/IO/ReadGC", iInstance);
4913 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/E1k%d/IO/ReadHC", iInstance);
4914 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/E1k%d/IO/WriteGC", iInstance);
4915 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/E1k%d/IO/WriteHC", iInstance);
4916 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
4917 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
4918 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
4919 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
4920 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
4921 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
4922 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
4923 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
4924 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
4925#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
4926 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
4927#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
4928 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/E1k%d/Transmit/Total", iInstance);
4929#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
4930 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
4931#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
4932 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in HC", "/Devices/E1k%d/Transmit/Send", iInstance);
4933
4934 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
4935 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
4936 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
4937 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
4938#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
4939
4940 return VINF_SUCCESS;
4941}
4942
4943/**
4944 * Destruct a device instance.
4945 *
4946 * We need to free non-VM resources only.
4947 *
4948 * @returns VBox status.
4949 * @param pDevIns The device instance data.
4950 * @thread EMT
4951 */
4952static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
4953{
4954 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4955
4956 e1kDumpState(pState);
4957 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
4958 if (PDMCritSectIsInitialized(&pState->cs))
4959 {
4960 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
4961 {
4962 RTSemEventSignal(pState->hEventMoreRxDescAvail);
4963 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
4964 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
4965 }
4966 if (pState->hTxSem != NIL_RTSEMEVENT)
4967 {
4968 RTSemEventDestroy(pState->hTxSem);
4969 pState->hTxSem = NIL_RTSEMEVENT;
4970 }
4971#ifndef E1K_GLOBAL_MUTEX
4972 PDMR3CritSectDelete(&pState->csRx);
4973 //PDMR3CritSectDelete(&pState->csTx);
4974#endif
4975 PDMR3CritSectDelete(&pState->cs);
4976 }
4977 return VINF_SUCCESS;
4978}
4979
4980/**
4981 * Device relocation callback.
4982 *
4983 * When this callback is called the device instance data, and if the
4984 * device have a GC component, is being relocated, or/and the selectors
4985 * have been changed. The device must use the chance to perform the
4986 * necessary pointer relocations and data updates.
4987 *
4988 * Before the GC code is executed the first time, this function will be
4989 * called with a 0 delta so GC pointer calculations can be one in one place.
4990 *
4991 * @param pDevIns Pointer to the device instance.
4992 * @param offDelta The relocation delta relative to the old location.
4993 *
4994 * @remark A relocation CANNOT fail.
4995 */
4996static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4997{
4998 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4999 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5000 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5001 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5002#ifdef E1K_USE_RX_TIMERS
5003 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5004 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5005#endif /* E1K_USE_RX_TIMERS */
5006#ifdef E1K_USE_TX_TIMERS
5007 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5008# ifndef E1K_NO_TAD
5009 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5010# endif /* E1K_NO_TAD */
5011#endif /* E1K_USE_TX_TIMERS */
5012 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5013}
5014
5015/**
5016 * @copydoc FNPDMDEVSUSPEND
5017 */
5018static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
5019{
5020 /* Poke thread waiting for buffer space. */
5021 e1kWakeupReceive(pDevIns);
5022}
5023
5024/**
5025 * @copydoc FNPDMDEVPOWEROFF
5026 */
5027static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
5028{
5029 /* Poke thread waiting for buffer space. */
5030 e1kWakeupReceive(pDevIns);
5031}
5032
5033/**
5034 * The device registration structure.
5035 */
5036const PDMDEVREG g_DeviceE1000 =
5037{
5038 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
5039 PDM_DEVREG_VERSION,
5040 /* Device name. */
5041 "e1000",
5042 /* Name of guest context module (no path).
5043 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5044 "VBoxDDGC.gc",
5045 /* Name of ring-0 module (no path).
5046 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5047 "VBoxDDR0.r0",
5048 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
5049 * remain unchanged from registration till VM destruction. */
5050 "Intel PRO/1000 MT Desktop Ethernet.\n",
5051
5052 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
5053 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5054 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
5055 PDM_DEVREG_CLASS_NETWORK,
5056 /* Maximum number of instances (per VM). */
5057 8,
5058 /* Size of the instance data. */
5059 sizeof(E1KSTATE),
5060
5061 /* Construct instance - required. */
5062 e1kConstruct,
5063 /* Destruct instance - optional. */
5064 e1kDestruct,
5065 /* Relocation command - optional. */
5066 e1kRelocate,
5067 /* I/O Control interface - optional. */
5068 NULL,
5069 /* Power on notification - optional. */
5070 NULL,
5071 /* Reset notification - optional. */
5072 NULL,
5073 /* Suspend notification - optional. */
5074 e1kSuspend,
5075 /* Resume notification - optional. */
5076 NULL,
5077 /* Attach command - optional. */
5078 NULL,
5079 /* Detach notification - optional. */
5080 NULL,
5081 /* Query a LUN base interface - optional. */
5082 NULL,
5083 /* Init complete notification - optional. */
5084 NULL,
5085 /* Power off notification - optional. */
5086 e1kPowerOff,
5087 /* pfnSoftReset */
5088 NULL,
5089 /* u32VersionEnd */
5090 PDM_DEVREG_VERSION
5091};
5092
5093#endif /* IN_RING3 */
5094#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5095
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