VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 27031

Last change on this file since 27031 was 27002, checked in by vboxsync, 15 years ago

e1000: A workaround for Windows lockups on link status interrupt.
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1/* $Id: DevE1000.cpp 27002 2010-03-03 18:34:42Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo VLAN checksum offloading support
14 * @todo Flexible Filter / Wakeup (optional?)
15 */
16
17/*
18 * Copyright (C) 2007 Sun Microsystems, Inc.
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 *
28 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
29 * Clara, CA 95054 USA or visit http://www.sun.com if you need
30 * additional information or have any questions.
31 */
32
33
34#define LOG_GROUP LOG_GROUP_DEV_E1000
35
36//#define E1kLogRel(a) LogRel(a)
37#define E1kLogRel(a)
38
39/* Options */
40#define E1K_INIT_RA0
41#define E1K_LSC_ON_SLU
42#define E1K_ITR_ENABLED
43//#define E1K_GLOBAL_MUTEX
44//#define E1K_USE_TX_TIMERS
45//#define E1K_NO_TAD
46//#define E1K_REL_DEBUG
47//#define E1K_INT_STATS
48//#define E1K_REL_STATS
49
50#include <iprt/crc32.h>
51#include <iprt/ctype.h>
52#include <iprt/net.h>
53#include <iprt/semaphore.h>
54#include <iprt/string.h>
55#include <iprt/uuid.h>
56#include <VBox/pdmdev.h>
57#include <VBox/pdmnetifs.h>
58#include <VBox/tm.h>
59#include <VBox/vm.h>
60#include "../Builtins.h"
61
62#include "DevEEPROM.h"
63#include "DevE1000Phy.h"
64
65/* Little helpers ************************************************************/
66#undef htons
67#undef ntohs
68#undef htonl
69#undef ntohl
70#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
71#define ntohs(x) htons(x)
72#define htonl(x) ASMByteSwapU32(x)
73#define ntohl(x) htonl(x)
74
75#ifndef DEBUG
76# ifdef E1K_REL_STATS
77# undef STAM_COUNTER_INC
78# undef STAM_PROFILE_ADV_START
79# undef STAM_PROFILE_ADV_STOP
80# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
81# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
82# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
83# endif
84# ifdef E1K_REL_DEBUG
85# define DEBUG
86# define E1kLog(a) LogRel(a)
87# define E1kLog2(a) LogRel(a)
88# define E1kLog3(a) LogRel(a)
89//# define E1kLog3(a) do {} while (0)
90# else
91# define E1kLog(a) do {} while (0)
92# define E1kLog2(a) do {} while (0)
93# define E1kLog3(a) do {} while (0)
94# endif
95#else
96# define E1kLog(a) Log(a)
97# define E1kLog2(a) Log2(a)
98# define E1kLog3(a) Log3(a)
99//# define E1kLog(a) do {} while (0)
100//# define E1kLog2(a) do {} while (0)
101//# define E1kLog3(a) do {} while (0)
102#endif
103
104//#undef DEBUG
105
106#define INSTANCE(pState) pState->szInstance
107#define IFACE_TO_STATE(pIface, ifaceName) ((E1KSTATE *)((char*)pIface - RT_OFFSETOF(E1KSTATE, ifaceName)))
108#define STATE_TO_DEVINS(pState) (((E1KSTATE *)pState)->CTX_SUFF(pDevIns))
109#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
110
111#define E1K_INC_CNT32(cnt) \
112do { \
113 if (cnt < UINT32_MAX) \
114 cnt++; \
115} while (0)
116
117#define E1K_ADD_CNT64(cntLo, cntHi, val) \
118do { \
119 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
120 uint64_t tmp = u64Cnt; \
121 u64Cnt += val; \
122 if (tmp > u64Cnt ) \
123 u64Cnt = UINT64_MAX; \
124 cntLo = (uint32_t)u64Cnt; \
125 cntHi = (uint32_t)(u64Cnt >> 32); \
126} while (0)
127
128#ifdef E1K_INT_STATS
129# define E1K_INC_ISTAT_CNT(cnt) ++cnt
130#else /* E1K_INT_STATS */
131# define E1K_INC_ISTAT_CNT(cnt)
132#endif /* E1K_INT_STATS */
133
134
135/*****************************************************************************/
136
137typedef uint32_t E1KCHIP;
138#define E1K_CHIP_82540EM 0
139#define E1K_CHIP_82543GC 1
140#define E1K_CHIP_82545EM 2
141
142struct E1kChips
143{
144 uint16_t uPCIVendorId;
145 uint16_t uPCIDeviceId;
146 uint16_t uPCISubsystemVendorId;
147 uint16_t uPCISubsystemId;
148 const char *pcszName;
149} g_Chips[] =
150{
151 /* Vendor Device SSVendor SubSys Name */
152 { 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
153 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
154 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
155};
156
157
158/* The size of register area mapped to I/O space */
159#define E1K_IOPORT_SIZE 0x8
160/* The size of memory-mapped register area */
161#define E1K_MM_SIZE 0x20000
162
163#define E1K_MAX_TX_PKT_SIZE 16288
164#define E1K_MAX_RX_PKT_SIZE 16384
165
166/*****************************************************************************/
167
168#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
169#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
170#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
171#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
172#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
173
174#define CTRL_SLU 0x00000040
175#define CTRL_MDIO 0x00100000
176#define CTRL_MDC 0x00200000
177#define CTRL_MDIO_DIR 0x01000000
178#define CTRL_MDC_DIR 0x02000000
179#define CTRL_RESET 0x04000000
180#define CTRL_VME 0x40000000
181
182#define STATUS_LU 0x00000002
183
184#define EECD_EE_WIRES 0x0F
185#define EECD_EE_REQ 0x40
186#define EECD_EE_GNT 0x80
187
188#define EERD_START 0x00000001
189#define EERD_DONE 0x00000010
190#define EERD_DATA_MASK 0xFFFF0000
191#define EERD_DATA_SHIFT 16
192#define EERD_ADDR_MASK 0x0000FF00
193#define EERD_ADDR_SHIFT 8
194
195#define MDIC_DATA_MASK 0x0000FFFF
196#define MDIC_DATA_SHIFT 0
197#define MDIC_REG_MASK 0x001F0000
198#define MDIC_REG_SHIFT 16
199#define MDIC_PHY_MASK 0x03E00000
200#define MDIC_PHY_SHIFT 21
201#define MDIC_OP_WRITE 0x04000000
202#define MDIC_OP_READ 0x08000000
203#define MDIC_READY 0x10000000
204#define MDIC_INT_EN 0x20000000
205#define MDIC_ERROR 0x40000000
206
207#define TCTL_EN 0x00000002
208#define TCTL_PSP 0x00000008
209
210#define RCTL_EN 0x00000002
211#define RCTL_UPE 0x00000008
212#define RCTL_MPE 0x00000010
213#define RCTL_LPE 0x00000020
214#define RCTL_LBM_MASK 0x000000C0
215#define RCTL_LBM_SHIFT 6
216#define RCTL_RDMTS_MASK 0x00000300
217#define RCTL_RDMTS_SHIFT 8
218#define RCTL_LBM_TCVR 3
219#define RCTL_MO_MASK 0x00003000
220#define RCTL_MO_SHIFT 12
221#define RCTL_BAM 0x00008000
222#define RCTL_BSIZE_MASK 0x00030000
223#define RCTL_BSIZE_SHIFT 16
224#define RCTL_VFE 0x00040000
225#define RCTL_BSEX 0x02000000
226#define RCTL_SECRC 0x04000000
227
228#define ICR_TXDW 0x00000001
229#define ICR_TXQE 0x00000002
230#define ICR_LSC 0x00000004
231#define ICR_RXDMT0 0x00000010
232#define ICR_RXT0 0x00000080
233#define ICR_TXD_LOW 0x00008000
234#define RDTR_FPD 0x80000000
235
236#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
237typedef struct
238{
239 unsigned rxa : 7;
240 unsigned rxa_r : 9;
241 unsigned txa : 16;
242} PBAST;
243AssertCompileSize(PBAST, 4);
244
245#define TXDCTL_WTHRESH_MASK 0x003F0000
246#define TXDCTL_WTHRESH_SHIFT 16
247#define TXDCTL_LWTHRESH_MASK 0xFE000000
248#define TXDCTL_LWTHRESH_SHIFT 25
249
250#define RXCSUM_PCSS_MASK 0x000000FF
251#define RXCSUM_PCSS_SHIFT 0
252
253/* Register access macros ****************************************************/
254#define CTRL pState->auRegs[CTRL_IDX]
255#define STATUS pState->auRegs[STATUS_IDX]
256#define EECD pState->auRegs[EECD_IDX]
257#define EERD pState->auRegs[EERD_IDX]
258#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
259#define FLA pState->auRegs[FLA_IDX]
260#define MDIC pState->auRegs[MDIC_IDX]
261#define FCAL pState->auRegs[FCAL_IDX]
262#define FCAH pState->auRegs[FCAH_IDX]
263#define FCT pState->auRegs[FCT_IDX]
264#define VET pState->auRegs[VET_IDX]
265#define ICR pState->auRegs[ICR_IDX]
266#define ITR pState->auRegs[ITR_IDX]
267#define ICS pState->auRegs[ICS_IDX]
268#define IMS pState->auRegs[IMS_IDX]
269#define IMC pState->auRegs[IMC_IDX]
270#define RCTL pState->auRegs[RCTL_IDX]
271#define FCTTV pState->auRegs[FCTTV_IDX]
272#define TXCW pState->auRegs[TXCW_IDX]
273#define RXCW pState->auRegs[RXCW_IDX]
274#define TCTL pState->auRegs[TCTL_IDX]
275#define TIPG pState->auRegs[TIPG_IDX]
276#define AIFS pState->auRegs[AIFS_IDX]
277#define LEDCTL pState->auRegs[LEDCTL_IDX]
278#define PBA pState->auRegs[PBA_IDX]
279#define FCRTL pState->auRegs[FCRTL_IDX]
280#define FCRTH pState->auRegs[FCRTH_IDX]
281#define RDFH pState->auRegs[RDFH_IDX]
282#define RDFT pState->auRegs[RDFT_IDX]
283#define RDFHS pState->auRegs[RDFHS_IDX]
284#define RDFTS pState->auRegs[RDFTS_IDX]
285#define RDFPC pState->auRegs[RDFPC_IDX]
286#define RDBAL pState->auRegs[RDBAL_IDX]
287#define RDBAH pState->auRegs[RDBAH_IDX]
288#define RDLEN pState->auRegs[RDLEN_IDX]
289#define RDH pState->auRegs[RDH_IDX]
290#define RDT pState->auRegs[RDT_IDX]
291#define RDTR pState->auRegs[RDTR_IDX]
292#define RXDCTL pState->auRegs[RXDCTL_IDX]
293#define RADV pState->auRegs[RADV_IDX]
294#define RSRPD pState->auRegs[RSRPD_IDX]
295#define TXDMAC pState->auRegs[TXDMAC_IDX]
296#define TDFH pState->auRegs[TDFH_IDX]
297#define TDFT pState->auRegs[TDFT_IDX]
298#define TDFHS pState->auRegs[TDFHS_IDX]
299#define TDFTS pState->auRegs[TDFTS_IDX]
300#define TDFPC pState->auRegs[TDFPC_IDX]
301#define TDBAL pState->auRegs[TDBAL_IDX]
302#define TDBAH pState->auRegs[TDBAH_IDX]
303#define TDLEN pState->auRegs[TDLEN_IDX]
304#define TDH pState->auRegs[TDH_IDX]
305#define TDT pState->auRegs[TDT_IDX]
306#define TIDV pState->auRegs[TIDV_IDX]
307#define TXDCTL pState->auRegs[TXDCTL_IDX]
308#define TADV pState->auRegs[TADV_IDX]
309#define TSPMT pState->auRegs[TSPMT_IDX]
310#define CRCERRS pState->auRegs[CRCERRS_IDX]
311#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
312#define SYMERRS pState->auRegs[SYMERRS_IDX]
313#define RXERRC pState->auRegs[RXERRC_IDX]
314#define MPC pState->auRegs[MPC_IDX]
315#define SCC pState->auRegs[SCC_IDX]
316#define ECOL pState->auRegs[ECOL_IDX]
317#define MCC pState->auRegs[MCC_IDX]
318#define LATECOL pState->auRegs[LATECOL_IDX]
319#define COLC pState->auRegs[COLC_IDX]
320#define DC pState->auRegs[DC_IDX]
321#define TNCRS pState->auRegs[TNCRS_IDX]
322#define SEC pState->auRegs[SEC_IDX]
323#define CEXTERR pState->auRegs[CEXTERR_IDX]
324#define RLEC pState->auRegs[RLEC_IDX]
325#define XONRXC pState->auRegs[XONRXC_IDX]
326#define XONTXC pState->auRegs[XONTXC_IDX]
327#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
328#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
329#define FCRUC pState->auRegs[FCRUC_IDX]
330#define PRC64 pState->auRegs[PRC64_IDX]
331#define PRC127 pState->auRegs[PRC127_IDX]
332#define PRC255 pState->auRegs[PRC255_IDX]
333#define PRC511 pState->auRegs[PRC511_IDX]
334#define PRC1023 pState->auRegs[PRC1023_IDX]
335#define PRC1522 pState->auRegs[PRC1522_IDX]
336#define GPRC pState->auRegs[GPRC_IDX]
337#define BPRC pState->auRegs[BPRC_IDX]
338#define MPRC pState->auRegs[MPRC_IDX]
339#define GPTC pState->auRegs[GPTC_IDX]
340#define GORCL pState->auRegs[GORCL_IDX]
341#define GORCH pState->auRegs[GORCH_IDX]
342#define GOTCL pState->auRegs[GOTCL_IDX]
343#define GOTCH pState->auRegs[GOTCH_IDX]
344#define RNBC pState->auRegs[RNBC_IDX]
345#define RUC pState->auRegs[RUC_IDX]
346#define RFC pState->auRegs[RFC_IDX]
347#define ROC pState->auRegs[ROC_IDX]
348#define RJC pState->auRegs[RJC_IDX]
349#define MGTPRC pState->auRegs[MGTPRC_IDX]
350#define MGTPDC pState->auRegs[MGTPDC_IDX]
351#define MGTPTC pState->auRegs[MGTPTC_IDX]
352#define TORL pState->auRegs[TORL_IDX]
353#define TORH pState->auRegs[TORH_IDX]
354#define TOTL pState->auRegs[TOTL_IDX]
355#define TOTH pState->auRegs[TOTH_IDX]
356#define TPR pState->auRegs[TPR_IDX]
357#define TPT pState->auRegs[TPT_IDX]
358#define PTC64 pState->auRegs[PTC64_IDX]
359#define PTC127 pState->auRegs[PTC127_IDX]
360#define PTC255 pState->auRegs[PTC255_IDX]
361#define PTC511 pState->auRegs[PTC511_IDX]
362#define PTC1023 pState->auRegs[PTC1023_IDX]
363#define PTC1522 pState->auRegs[PTC1522_IDX]
364#define MPTC pState->auRegs[MPTC_IDX]
365#define BPTC pState->auRegs[BPTC_IDX]
366#define TSCTC pState->auRegs[TSCTC_IDX]
367#define TSCTFC pState->auRegs[TSCTFC_IDX]
368#define RXCSUM pState->auRegs[RXCSUM_IDX]
369#define WUC pState->auRegs[WUC_IDX]
370#define WUFC pState->auRegs[WUFC_IDX]
371#define WUS pState->auRegs[WUS_IDX]
372#define MANC pState->auRegs[MANC_IDX]
373#define IPAV pState->auRegs[IPAV_IDX]
374#define WUPL pState->auRegs[WUPL_IDX]
375
376/**
377 * Indices of memory-mapped registers in register table
378 */
379typedef enum
380{
381 CTRL_IDX,
382 STATUS_IDX,
383 EECD_IDX,
384 EERD_IDX,
385 CTRL_EXT_IDX,
386 FLA_IDX,
387 MDIC_IDX,
388 FCAL_IDX,
389 FCAH_IDX,
390 FCT_IDX,
391 VET_IDX,
392 ICR_IDX,
393 ITR_IDX,
394 ICS_IDX,
395 IMS_IDX,
396 IMC_IDX,
397 RCTL_IDX,
398 FCTTV_IDX,
399 TXCW_IDX,
400 RXCW_IDX,
401 TCTL_IDX,
402 TIPG_IDX,
403 AIFS_IDX,
404 LEDCTL_IDX,
405 PBA_IDX,
406 FCRTL_IDX,
407 FCRTH_IDX,
408 RDFH_IDX,
409 RDFT_IDX,
410 RDFHS_IDX,
411 RDFTS_IDX,
412 RDFPC_IDX,
413 RDBAL_IDX,
414 RDBAH_IDX,
415 RDLEN_IDX,
416 RDH_IDX,
417 RDT_IDX,
418 RDTR_IDX,
419 RXDCTL_IDX,
420 RADV_IDX,
421 RSRPD_IDX,
422 TXDMAC_IDX,
423 TDFH_IDX,
424 TDFT_IDX,
425 TDFHS_IDX,
426 TDFTS_IDX,
427 TDFPC_IDX,
428 TDBAL_IDX,
429 TDBAH_IDX,
430 TDLEN_IDX,
431 TDH_IDX,
432 TDT_IDX,
433 TIDV_IDX,
434 TXDCTL_IDX,
435 TADV_IDX,
436 TSPMT_IDX,
437 CRCERRS_IDX,
438 ALGNERRC_IDX,
439 SYMERRS_IDX,
440 RXERRC_IDX,
441 MPC_IDX,
442 SCC_IDX,
443 ECOL_IDX,
444 MCC_IDX,
445 LATECOL_IDX,
446 COLC_IDX,
447 DC_IDX,
448 TNCRS_IDX,
449 SEC_IDX,
450 CEXTERR_IDX,
451 RLEC_IDX,
452 XONRXC_IDX,
453 XONTXC_IDX,
454 XOFFRXC_IDX,
455 XOFFTXC_IDX,
456 FCRUC_IDX,
457 PRC64_IDX,
458 PRC127_IDX,
459 PRC255_IDX,
460 PRC511_IDX,
461 PRC1023_IDX,
462 PRC1522_IDX,
463 GPRC_IDX,
464 BPRC_IDX,
465 MPRC_IDX,
466 GPTC_IDX,
467 GORCL_IDX,
468 GORCH_IDX,
469 GOTCL_IDX,
470 GOTCH_IDX,
471 RNBC_IDX,
472 RUC_IDX,
473 RFC_IDX,
474 ROC_IDX,
475 RJC_IDX,
476 MGTPRC_IDX,
477 MGTPDC_IDX,
478 MGTPTC_IDX,
479 TORL_IDX,
480 TORH_IDX,
481 TOTL_IDX,
482 TOTH_IDX,
483 TPR_IDX,
484 TPT_IDX,
485 PTC64_IDX,
486 PTC127_IDX,
487 PTC255_IDX,
488 PTC511_IDX,
489 PTC1023_IDX,
490 PTC1522_IDX,
491 MPTC_IDX,
492 BPTC_IDX,
493 TSCTC_IDX,
494 TSCTFC_IDX,
495 RXCSUM_IDX,
496 WUC_IDX,
497 WUFC_IDX,
498 WUS_IDX,
499 MANC_IDX,
500 IPAV_IDX,
501 WUPL_IDX,
502 MTA_IDX,
503 RA_IDX,
504 VFTA_IDX,
505 IP4AT_IDX,
506 IP6AT_IDX,
507 WUPM_IDX,
508 FFLT_IDX,
509 FFMT_IDX,
510 FFVT_IDX,
511 PBM_IDX,
512 RA_82542_IDX,
513 MTA_82542_IDX,
514 VFTA_82542_IDX,
515 E1K_NUM_OF_REGS
516} E1kRegIndex;
517
518#define E1K_NUM_OF_32BIT_REGS MTA_IDX
519
520
521/**
522 * Define E1000-specific EEPROM layout.
523 */
524class E1kEEPROM
525{
526 public:
527 EEPROM93C46 eeprom;
528
529#ifdef IN_RING3
530 /**
531 * Initialize EEPROM content.
532 *
533 * @param macAddr MAC address of E1000.
534 */
535 void init(RTMAC &macAddr)
536 {
537 eeprom.init();
538 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
539 eeprom.m_au16Data[0x04] = 0xFFFF;
540 /*
541 * bit 3 - full support for power management
542 * bit 10 - full duplex
543 */
544 eeprom.m_au16Data[0x0A] = 0x4408;
545 eeprom.m_au16Data[0x0B] = 0x001E;
546 eeprom.m_au16Data[0x0C] = 0x8086;
547 eeprom.m_au16Data[0x0D] = 0x100E;
548 eeprom.m_au16Data[0x0E] = 0x8086;
549 eeprom.m_au16Data[0x0F] = 0x3040;
550 eeprom.m_au16Data[0x21] = 0x7061;
551 eeprom.m_au16Data[0x22] = 0x280C;
552 eeprom.m_au16Data[0x23] = 0x00C8;
553 eeprom.m_au16Data[0x24] = 0x00C8;
554 eeprom.m_au16Data[0x2F] = 0x0602;
555 updateChecksum();
556 };
557
558 /**
559 * Compute the checksum as required by E1000 and store it
560 * in the last word.
561 */
562 void updateChecksum()
563 {
564 uint16_t u16Checksum = 0;
565
566 for (int i = 0; i < eeprom.SIZE-1; i++)
567 u16Checksum += eeprom.m_au16Data[i];
568 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
569 };
570
571 /**
572 * First 6 bytes of EEPROM contain MAC address.
573 *
574 * @returns MAC address of E1000.
575 */
576 void getMac(PRTMAC pMac)
577 {
578 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
579 };
580
581 uint32_t read()
582 {
583 return eeprom.read();
584 }
585
586 void write(uint32_t u32Wires)
587 {
588 eeprom.write(u32Wires);
589 }
590
591 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
592 {
593 return eeprom.readWord(u32Addr, pu16Value);
594 }
595
596 int load(PSSMHANDLE pSSM)
597 {
598 return eeprom.load(pSSM);
599 }
600
601 void save(PSSMHANDLE pSSM)
602 {
603 eeprom.save(pSSM);
604 }
605#endif /* IN_RING3 */
606};
607
608struct E1kRxDStatus
609{
610 /* Descriptor Status field */
611 unsigned fDD : 1;
612 unsigned fEOP : 1;
613 unsigned fIXSM : 1;
614 unsigned fVP : 1;
615 unsigned : 1;
616 unsigned fTCPCS : 1;
617 unsigned fIPCS : 1;
618 unsigned fPIF : 1;
619 /* Descriptor Errors field */
620 unsigned fCE : 1;
621 unsigned : 4;
622 unsigned fTCPE : 1;
623 unsigned fIPE : 1;
624 unsigned fRXE : 1;
625 /* Descriptor Special field */
626 unsigned u12VLAN : 12;
627 unsigned fCFI : 1;
628 unsigned u3PRI : 3;
629};
630typedef struct E1kRxDStatus E1KRXDST;
631
632struct E1kRxDesc_st
633{
634 uint64_t u64BufAddr; /**< Address of data buffer */
635 uint16_t u16Length; /**< Length of data in buffer */
636 uint16_t u16Checksum; /**< Packet checksum */
637 E1KRXDST status;
638};
639typedef struct E1kRxDesc_st E1KRXDESC;
640AssertCompileSize(E1KRXDESC, 16);
641
642#define E1K_DTYP_LEGACY -1
643#define E1K_DTYP_CONTEXT 0
644#define E1K_DTYP_DATA 1
645
646struct E1kTDLegacy
647{
648 uint64_t u64BufAddr; /**< Address of data buffer */
649 struct TDLCmd_st
650 {
651 unsigned u16Length : 16;
652 unsigned u8CSO : 8;
653 /* CMD field : 8 */
654 unsigned fEOP : 1;
655 unsigned fIFCS : 1;
656 unsigned fIC : 1;
657 unsigned fRS : 1;
658 unsigned fRSV : 1;
659 unsigned fDEXT : 1;
660 unsigned fVLE : 1;
661 unsigned fIDE : 1;
662 } cmd;
663 struct TDLDw3_st
664 {
665 /* STA field */
666 unsigned fDD : 1;
667 unsigned fEC : 1;
668 unsigned fLC : 1;
669 unsigned fTURSV : 1;
670 /* RSV field */
671 unsigned u4RSV : 4;
672 /* CSS field */
673 unsigned u8CSS : 8;
674 /* Special field*/
675 unsigned u12VLAN : 12;
676 unsigned fCFI : 1;
677 unsigned u3PRI : 3;
678 } dw3;
679};
680
681struct E1kTDContext
682{
683 struct CheckSum_st
684 {
685 unsigned u8CSS : 8;
686 unsigned u8CSO : 8;
687 unsigned u16CSE : 16;
688 } ip;
689 struct CheckSum_st tu;
690 struct TDCDw2_st
691 {
692 unsigned u20PAYLEN : 20;
693 unsigned u4DTYP : 4;
694 /* CMD field : 8 */
695 unsigned fTCP : 1;
696 unsigned fIP : 1;
697 unsigned fTSE : 1;
698 unsigned fRS : 1;
699 unsigned fRSV1 : 1;
700 unsigned fDEXT : 1;
701 unsigned fRSV2 : 1;
702 unsigned fIDE : 1;
703 } dw2;
704 struct TDCDw3_st
705 {
706 unsigned fDD : 1;
707 unsigned u7RSV : 7;
708 unsigned u8HDRLEN : 8;
709 unsigned u16MSS : 16;
710 } dw3;
711};
712typedef struct E1kTDContext E1KTXCTX;
713
714struct E1kTDData
715{
716 uint64_t u64BufAddr; /**< Address of data buffer */
717 struct TDDCmd_st
718 {
719 unsigned u20DTALEN : 20;
720 unsigned u4DTYP : 4;
721 /* DCMD field : 8 */
722 unsigned fEOP : 1;
723 unsigned fIFCS : 1;
724 unsigned fTSE : 1;
725 unsigned fRS : 1;
726 unsigned fRSV : 1;
727 unsigned fDEXT : 1;
728 unsigned fVLE : 1;
729 unsigned fIDE : 1;
730 } cmd;
731 struct TDDDw3_st
732 {
733 /* STA field */
734 unsigned fDD : 1;
735 unsigned fEC : 1;
736 unsigned fLC : 1;
737 unsigned fTURSV : 1;
738 /* RSV field */
739 unsigned u4RSV : 4;
740 /* POPTS field */
741 unsigned fIXSM : 1;
742 unsigned fTXSM : 1;
743 unsigned u6RSV : 6;
744 /* Special field*/
745 unsigned u12VLAN : 12;
746 unsigned fCFI : 1;
747 unsigned u3PRI : 3;
748 } dw3;
749};
750typedef struct E1kTDData E1KTXDAT;
751
752union E1kTxDesc
753{
754 struct E1kTDLegacy legacy;
755 struct E1kTDContext context;
756 struct E1kTDData data;
757};
758typedef union E1kTxDesc E1KTXDESC;
759AssertCompileSize(E1KTXDESC, 16);
760
761#define RA_CTL_AS 0x0003
762#define RA_CTL_AV 0x8000
763
764union E1kRecAddr
765{
766 uint32_t au32[32];
767 struct RAArray
768 {
769 uint8_t addr[6];
770 uint16_t ctl;
771 } array[16];
772};
773typedef struct E1kRecAddr::RAArray E1KRAELEM;
774typedef union E1kRecAddr E1KRA;
775AssertCompileSize(E1KRA, 8*16);
776
777#define E1K_IP_RF 0x8000 /* reserved fragment flag */
778#define E1K_IP_DF 0x4000 /* dont fragment flag */
779#define E1K_IP_MF 0x2000 /* more fragments flag */
780#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
781
782/** @todo use+extend RTNETIPV4 */
783struct E1kIpHeader
784{
785 /* type of service / version / header length */
786 uint16_t tos_ver_hl;
787 /* total length */
788 uint16_t total_len;
789 /* identification */
790 uint16_t ident;
791 /* fragment offset field */
792 uint16_t offset;
793 /* time to live / protocol*/
794 uint16_t ttl_proto;
795 /* checksum */
796 uint16_t chksum;
797 /* source IP address */
798 uint32_t src;
799 /* destination IP address */
800 uint32_t dest;
801};
802AssertCompileSize(struct E1kIpHeader, 20);
803
804#define E1K_TCP_FIN 0x01U
805#define E1K_TCP_SYN 0x02U
806#define E1K_TCP_RST 0x04U
807#define E1K_TCP_PSH 0x08U
808#define E1K_TCP_ACK 0x10U
809#define E1K_TCP_URG 0x20U
810#define E1K_TCP_ECE 0x40U
811#define E1K_TCP_CWR 0x80U
812
813#define E1K_TCP_FLAGS 0x3fU
814
815/** @todo use+extend RTNETTCP */
816struct E1kTcpHeader
817{
818 uint16_t src;
819 uint16_t dest;
820 uint32_t seqno;
821 uint32_t ackno;
822 uint16_t hdrlen_flags;
823 uint16_t wnd;
824 uint16_t chksum;
825 uint16_t urgp;
826};
827AssertCompileSize(struct E1kTcpHeader, 20);
828
829
830/** The current Saved state version. */
831#define E1K_SAVEDSTATE_VERSION 2
832/** Saved state version for VirtualBox 3.0 and earlier.
833 * This did not include the configuration part nor the E1kEEPROM. */
834#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
835
836/**
837 * Device state structure. Holds the current state of device.
838 *
839 * @implements PDMINETWORKDOWN
840 * @implements PDMINETWORKCONFIG
841 * @implements PDMILEDPORTS
842 */
843struct E1kState_st
844{
845 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
846 PDMIBASE IBase;
847 PDMINETWORKDOWN INetworkDown;
848 PDMINETWORKCONFIG INetworkConfig;
849 PDMILEDPORTS ILeds; /**< LED interface */
850 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
851 R3PTRTYPE(PPDMINETWORKUP) pDrv; /**< Connector of attached network driver. */
852 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
853#if HC_ARCH_BITS == 32
854 uint32_t u32Padding;
855#endif
856
857 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
858 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
859 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
860 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
861 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
862 PTMTIMERR3 pTIDTimerR3; /**< Tranmsit Interrupt Delay Timer - R3. */
863 PTMTIMERR3 pTADTimerR3; /**< Tranmsit Absolute Delay Timer - R3. */
864 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
865 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
866
867 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
868 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
869 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
870 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
871 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
872 PTMTIMERR0 pTIDTimerR0; /**< Tranmsit Interrupt Delay Timer - R0. */
873 PTMTIMERR0 pTADTimerR0; /**< Tranmsit Absolute Delay Timer - R0. */
874 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
875 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
876
877 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
878 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
879 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
880 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
881 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
882 PTMTIMERRC pTIDTimerRC; /**< Tranmsit Interrupt Delay Timer - RC. */
883 PTMTIMERRC pTADTimerRC; /**< Tranmsit Absolute Delay Timer - RC. */
884 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
885 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
886
887#if HC_ARCH_BITS != 32
888 uint32_t u32Padding2;
889#endif
890
891 PPDMTHREAD pTxThread; /**< Transmit thread. */
892 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
893#ifndef E1K_GLOBAL_MUTEX
894 PDMCRITSECT csRx; /**< RX Critical section. */
895// PDMCRITSECT csTx; /**< TX Critical section. */
896#endif
897 /** Transmit thread blocker. */
898 RTSEMEVENT hTxSem;
899 /** Base address of memory-mapped registers. */
900 RTGCPHYS addrMMReg;
901 /** MAC address obtained from the configuration. */
902 RTMAC macConfigured;
903 /** Base port of I/O space region. */
904 RTIOPORT addrIOPort;
905 /** EMT: */
906 PCIDEVICE pciDevice;
907 /** EMT: Last time the interrupt was acknowledged. */
908 uint64_t u64AckedAt;
909 /** All: Used for eliminating spurious interrupts. */
910 bool fIntRaised;
911 /** EMT: false if the cable is disconnected by the GUI. */
912 bool fCableConnected;
913 /** EMT: */
914 bool fR0Enabled;
915 /** EMT: */
916 bool fGCEnabled;
917
918 /* All: Device register storage. */
919 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
920 /** TX/RX: Status LED. */
921 PDMLED led;
922 /** TX/RX: Number of packet being sent/received to show in debug log. */
923 uint32_t u32PktNo;
924
925 /** EMT: Offset of the register to be read via IO. */
926 uint32_t uSelectedReg;
927 /** EMT: Multicast Table Array. */
928 uint32_t auMTA[128];
929 /** EMT: Receive Address registers. */
930 E1KRA aRecAddr;
931 /** EMT: VLAN filter table array. */
932 uint32_t auVFTA[128];
933 /** EMT: Receive buffer size. */
934 uint16_t u16RxBSize;
935 /** EMT: Locked state -- no state alteration possible. */
936 bool fLocked;
937 /** EMT: */
938 bool fDelayInts;
939 /** All: */
940 bool fIntMaskUsed;
941
942 /** N/A: */
943 bool volatile fMaybeOutOfSpace;
944 /** EMT: Gets signalled when more RX descriptors become available. */
945 RTSEMEVENT hEventMoreRxDescAvail;
946
947 /** TX: Context used for TCP segmentation packets. */
948 E1KTXCTX contextTSE;
949 /** TX: Context used for ordinary packets. */
950 E1KTXCTX contextNormal;
951 /** TX: Transmit packet buffer. */
952 uint8_t aTxPacket[E1K_MAX_TX_PKT_SIZE];
953 /** TX: Number of bytes assembled in TX packet buffer. */
954 uint16_t u16TxPktLen;
955 /** TX: IP checksum has to be inserted if true. */
956 bool fIPcsum;
957 /** TX: TCP/UDP checksum has to be inserted if true. */
958 bool fTCPcsum;
959 /** TX: Number of payload bytes remaining in TSE context. */
960 uint32_t u32PayRemain;
961 /** TX: Number of header bytes remaining in TSE context. */
962 uint16_t u16HdrRemain;
963 /** TX: Flags from template header. */
964 uint16_t u16SavedFlags;
965 /** TX: Partial checksum from template header. */
966 uint32_t u32SavedCsum;
967 /** ?: Emulated controller type. */
968 E1KCHIP eChip;
969 uint32_t alignmentFix;
970
971 /** EMT: EEPROM emulation */
972 E1kEEPROM eeprom;
973 /** EMT: Physical interface emulation. */
974 PHY phy;
975
976 /** Alignment padding. */
977 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
978
979 STAMCOUNTER StatReceiveBytes;
980 STAMCOUNTER StatTransmitBytes;
981#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
982 STAMPROFILEADV StatMMIOReadGC;
983 STAMPROFILEADV StatMMIOReadHC;
984 STAMPROFILEADV StatMMIOWriteGC;
985 STAMPROFILEADV StatMMIOWriteHC;
986 STAMPROFILEADV StatEEPROMRead;
987 STAMPROFILEADV StatEEPROMWrite;
988 STAMPROFILEADV StatIOReadGC;
989 STAMPROFILEADV StatIOReadHC;
990 STAMPROFILEADV StatIOWriteGC;
991 STAMPROFILEADV StatIOWriteHC;
992 STAMPROFILEADV StatLateIntTimer;
993 STAMCOUNTER StatLateInts;
994 STAMCOUNTER StatIntsRaised;
995 STAMCOUNTER StatIntsPrevented;
996 STAMPROFILEADV StatReceive;
997 STAMPROFILEADV StatReceiveFilter;
998 STAMPROFILEADV StatReceiveStore;
999 STAMPROFILEADV StatTransmit;
1000 STAMPROFILEADV StatTransmitSend;
1001 STAMPROFILE StatRxOverflow;
1002 STAMCOUNTER StatRxOverflowWakeup;
1003 STAMCOUNTER StatTxDescLegacy;
1004 STAMCOUNTER StatTxDescData;
1005 STAMCOUNTER StatTxDescTSEData;
1006 STAMCOUNTER StatPHYAccesses;
1007
1008#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
1009
1010#ifdef E1K_INT_STATS
1011 /* Internal stats */
1012 uint32_t uStatInt;
1013 uint32_t uStatIntTry;
1014 int32_t uStatIntLower;
1015 uint32_t uStatIntDly;
1016 int32_t iStatIntLost;
1017 int32_t iStatIntLostOne;
1018 uint32_t uStatDisDly;
1019 uint32_t uStatIntSkip;
1020 uint32_t uStatIntLate;
1021 uint32_t uStatIntMasked;
1022 uint32_t uStatIntEarly;
1023 uint32_t uStatIntRx;
1024 uint32_t uStatIntTx;
1025 uint32_t uStatIntICS;
1026 uint32_t uStatIntRDTR;
1027 uint32_t uStatIntRXDMT0;
1028 uint32_t uStatIntTXQE;
1029 uint32_t uStatTxNoRS;
1030 uint32_t uStatTxIDE;
1031 uint32_t uStatTAD;
1032 uint32_t uStatTID;
1033 uint32_t uStatRAD;
1034 uint32_t uStatRID;
1035 uint32_t uStatRxFrm;
1036 uint32_t uStatTxFrm;
1037 uint32_t uStatDescCtx;
1038 uint32_t uStatDescDat;
1039 uint32_t uStatDescLeg;
1040#endif /* E1K_INT_STATS */
1041};
1042typedef struct E1kState_st E1KSTATE;
1043
1044#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1045
1046/* Forward declarations ******************************************************/
1047RT_C_DECLS_BEGIN
1048PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1049PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1050PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
1051PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
1052RT_C_DECLS_END
1053
1054static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1055static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1056static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1057static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1058static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1059#if 0 /* unused */
1060static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1061#endif
1062static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1063static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1064static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1065static int e1kRegWriteEERD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1066static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1067static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1068static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1069static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1070static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1071static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1072static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1073static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1074static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1075static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1076static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1077static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1078static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1079static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1080static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1081static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1082static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1083
1084/**
1085 * Register map table.
1086 *
1087 * Override fn_read and fn_write to get register-specific behavior.
1088 */
1089const static struct E1kRegMap_st
1090{
1091 /** Register offset in the register space. */
1092 uint32_t offset;
1093 /** Size in bytes. Registers of size > 4 are in fact tables. */
1094 uint32_t size;
1095 /** Readable bits. */
1096 uint32_t readable;
1097 /** Writable bits. */
1098 uint32_t writable;
1099 /** Read callback. */
1100 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1101 /** Write callback. */
1102 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1103 /** Abbreviated name. */
1104 const char *abbrev;
1105 /** Full name. */
1106 const char *name;
1107} s_e1kRegMap[E1K_NUM_OF_REGS] =
1108{
1109 /* offset size read mask write mask read callback write callback abbrev full name */
1110 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1111 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1112 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1113 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1114 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1115 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1116 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1117 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1118 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1119 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1120 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1121 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1122 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1123 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1124 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1125 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1126 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1127 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1128 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1129 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1130 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1131 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1132 { 0x00410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TIPG" , "Transmit IPG" },
1133 { 0x00458, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "AIFS" , "Adaptive IFS Throttle - AIT" },
1134 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1135 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1136 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1137 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1138 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1139 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1140 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1141 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1142 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1143 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1144 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1145 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1146 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1147 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1148 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1149 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1150 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1151 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1152 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1153 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1154 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1155 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1156 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1157 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1158 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1159 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1160 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1161 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1162 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1163 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1164 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1165 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1166 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSPMT" , "TCP Segmentation Pad and Threshold" },
1167 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1168 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1169 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1170 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1171 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1172 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1173 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1174 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1175 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1176 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1177 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1178 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1179 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1180 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1181 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1182 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1183 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1184 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1185 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1186 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1187 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1188 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1189 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1190 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1191 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1192 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1193 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1194 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1195 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1196 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1197 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1198 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1199 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1200 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1201 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1202 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1203 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1204 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1205 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1206 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1207 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1208 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1209 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1210 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1211 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1212 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1213 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1214 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1215 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1216 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1217 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1218 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1219 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1220 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1221 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1222 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1223 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1224 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1225 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1226 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1227 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1228 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1229 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1230 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1231 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1232 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1233 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1234 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1235 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1236 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1237 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1238 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1239 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1240 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1241 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1242 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1243 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1244 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1245};
1246
1247#ifdef DEBUG
1248/**
1249 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1250 *
1251 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1252 *
1253 * @returns The buffer.
1254 *
1255 * @param u32 The word to convert into string.
1256 * @param mask Selects which bytes to convert.
1257 * @param buf Where to put the result.
1258 */
1259static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1260{
1261 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1262 {
1263 if (mask & 0xF)
1264 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1265 else
1266 *ptr = '.';
1267 }
1268 buf[8] = 0;
1269 return buf;
1270}
1271
1272/**
1273 * Returns timer name for debug purposes.
1274 *
1275 * @returns The timer name.
1276 *
1277 * @param pState The device state structure.
1278 * @param pTimer The timer to get the name for.
1279 */
1280DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1281{
1282 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1283 return "TID";
1284 if (pTimer == pState->CTX_SUFF(pTADTimer))
1285 return "TAD";
1286 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1287 return "RID";
1288 if (pTimer == pState->CTX_SUFF(pRADTimer))
1289 return "RAD";
1290 if (pTimer == pState->CTX_SUFF(pIntTimer))
1291 return "Int";
1292 return "unknown";
1293}
1294#endif /* DEBUG */
1295
1296/**
1297 * Arm a timer.
1298 *
1299 * @param pState Pointer to the device state structure.
1300 * @param pTimer Pointer to the timer.
1301 * @param uExpireIn Expiration interval in microseconds.
1302 */
1303DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1304{
1305 if (pState->fLocked)
1306 return;
1307
1308 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1309 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1310 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1311 TMTimerGet(pTimer));
1312}
1313
1314/**
1315 * Cancel a timer.
1316 *
1317 * @param pState Pointer to the device state structure.
1318 * @param pTimer Pointer to the timer.
1319 */
1320DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1321{
1322 E1kLog2(("%s Stopping %s timer...\n",
1323 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1324 int rc = TMTimerStop(pTimer);
1325 if (RT_FAILURE(rc))
1326 {
1327 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1328 INSTANCE(pState), rc));
1329 }
1330}
1331
1332#ifdef E1K_GLOBAL_MUTEX
1333DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1334{
1335 return VINF_SUCCESS;
1336}
1337
1338DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1339{
1340}
1341
1342#define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1343#define e1kCsRxLeave(ps)
1344
1345#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1346#define e1kCsTxLeave(ps)
1347
1348
1349DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1350{
1351 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1352 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1353 {
1354 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1355 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1356 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1357 "%s Failed to enter critical section, rc=%Rrc\n",
1358 INSTANCE(pState), rc);
1359 }
1360 else
1361 {
1362 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1363 }
1364 return rc;
1365}
1366
1367DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1368{
1369 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1370 PDMCritSectLeave(&pState->cs);
1371}
1372
1373#else /* !E1K_GLOBAL_MUTEX */
1374#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1375#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1376
1377#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1378#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1379
1380#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1381#define e1kCsTxLeave(ps)
1382//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1383//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1384
1385#if 0
1386DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1387{
1388 int rc = PDMCritSectEnter(pCs, iBusyRc);
1389 if (RT_FAILURE(rc))
1390 {
1391 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1392 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1393 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1394 "%s Failed to enter critical section, rc=%Rrc\n",
1395 INSTANCE(pState), rc);
1396 }
1397 else
1398 {
1399 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1400 }
1401 return RT_SUCCESS(rc);
1402}
1403
1404DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1405{
1406 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1407 PDMCritSectLeave(&pState->cs);
1408}
1409#endif
1410DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1411{
1412 return VINF_SUCCESS;
1413}
1414
1415DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1416{
1417}
1418#endif /* !E1K_GLOBAL_MUTEX */
1419
1420#ifdef IN_RING3
1421/**
1422 * Wakeup the RX thread.
1423 */
1424static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1425{
1426 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1427 if ( pState->fMaybeOutOfSpace
1428 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1429 {
1430 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1431 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1432 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1433 }
1434}
1435
1436/**
1437 * Compute Internet checksum.
1438 *
1439 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1440 *
1441 * @param pState The device state structure.
1442 * @param cpPacket The packet.
1443 * @param cb The size of the packet.
1444 * @param cszText A string denoting direction of packet transfer.
1445 *
1446 * @return The 1's complement of the 1's complement sum.
1447 *
1448 * @thread E1000_TX
1449 */
1450static DECLCALLBACK(uint16_t) e1kCSum16(const void *pvBuf, size_t cb)
1451{
1452 uint32_t csum = 0;
1453 uint16_t *pu16 = (uint16_t *)pvBuf;
1454
1455 while (cb > 1)
1456 {
1457 csum += *pu16++;
1458 cb -= 2;
1459 }
1460 if (cb)
1461 csum += *(uint8_t*)pu16;
1462 while (csum >> 16)
1463 csum = (csum >> 16) + (csum & 0xFFFF);
1464 return ~csum;
1465}
1466
1467/**
1468 * Dump a packet to debug log.
1469 *
1470 * @param pState The device state structure.
1471 * @param cpPacket The packet.
1472 * @param cb The size of the packet.
1473 * @param cszText A string denoting direction of packet transfer.
1474 * @thread E1000_TX
1475 */
1476DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1477{
1478#ifdef DEBUG
1479 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1480 {
1481 E1kLog(("%s --- %s packet #%d: ---\n",
1482 INSTANCE(pState), cszText, ++pState->u32PktNo));
1483 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1484 e1kCsLeave(pState);
1485 }
1486#else
1487 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1488 {
1489 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1490 e1kCsLeave(pState);
1491 }
1492#endif
1493}
1494
1495/**
1496 * Determine the type of transmit descriptor.
1497 *
1498 * @returns Descriptor type. See E1K_DTYPE_XXX defines.
1499 *
1500 * @param pDesc Pointer to descriptor union.
1501 * @thread E1000_TX
1502 */
1503DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1504{
1505 if (pDesc->legacy.cmd.fDEXT)
1506 return pDesc->context.dw2.u4DTYP;
1507 return E1K_DTYP_LEGACY;
1508}
1509
1510/**
1511 * Dump receive descriptor to debug log.
1512 *
1513 * @param pState The device state structure.
1514 * @param pDesc Pointer to the descriptor.
1515 * @thread E1000_RX
1516 */
1517static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1518{
1519 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1520 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1521 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1522 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1523 pDesc->status.fPIF ? "PIF" : "pif",
1524 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1525 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1526 pDesc->status.fVP ? "VP" : "vp",
1527 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1528 pDesc->status.fEOP ? "EOP" : "eop",
1529 pDesc->status.fDD ? "DD" : "dd",
1530 pDesc->status.fRXE ? "RXE" : "rxe",
1531 pDesc->status.fIPE ? "IPE" : "ipe",
1532 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1533 pDesc->status.fCE ? "CE" : "ce",
1534 pDesc->status.fCFI ? "CFI" :"cfi",
1535 pDesc->status.u12VLAN,
1536 pDesc->status.u3PRI));
1537}
1538
1539/**
1540 * Dump transmit descriptor to debug log.
1541 *
1542 * @param pState The device state structure.
1543 * @param pDesc Pointer to descriptor union.
1544 * @param cszDir A string denoting direction of descriptor transfer
1545 * @thread E1000_TX
1546 */
1547static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1548{
1549 switch (e1kGetDescType(pDesc))
1550 {
1551 case E1K_DTYP_CONTEXT:
1552 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1553 INSTANCE(pState), cszDir, cszDir));
1554 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1555 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1556 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1557 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1558 pDesc->context.dw2.fIDE ? " IDE":"",
1559 pDesc->context.dw2.fRS ? " RS" :"",
1560 pDesc->context.dw2.fTSE ? " TSE":"",
1561 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1562 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1563 pDesc->context.dw2.u20PAYLEN,
1564 pDesc->context.dw3.u8HDRLEN,
1565 pDesc->context.dw3.u16MSS,
1566 pDesc->context.dw3.fDD?"DD":""));
1567 break;
1568 case E1K_DTYP_DATA:
1569 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1570 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1571 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1572 pDesc->data.u64BufAddr,
1573 pDesc->data.cmd.u20DTALEN));
1574 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1575 pDesc->data.cmd.fIDE ? " IDE" :"",
1576 pDesc->data.cmd.fVLE ? " VLE" :"",
1577 pDesc->data.cmd.fRS ? " RS" :"",
1578 pDesc->data.cmd.fTSE ? " TSE" :"",
1579 pDesc->data.cmd.fIFCS? " IFCS":"",
1580 pDesc->data.cmd.fEOP ? " EOP" :"",
1581 pDesc->data.dw3.fDD ? " DD" :"",
1582 pDesc->data.dw3.fEC ? " EC" :"",
1583 pDesc->data.dw3.fLC ? " LC" :"",
1584 pDesc->data.dw3.fTXSM? " TXSM":"",
1585 pDesc->data.dw3.fIXSM? " IXSM":"",
1586 pDesc->data.dw3.fCFI ? " CFI" :"",
1587 pDesc->data.dw3.u12VLAN,
1588 pDesc->data.dw3.u3PRI));
1589 break;
1590 case E1K_DTYP_LEGACY:
1591 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1592 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1593 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1594 pDesc->data.u64BufAddr,
1595 pDesc->legacy.cmd.u16Length));
1596 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1597 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1598 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1599 pDesc->legacy.cmd.fRS ? " RS" :"",
1600 pDesc->legacy.cmd.fIC ? " IC" :"",
1601 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1602 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1603 pDesc->legacy.dw3.fDD ? " DD" :"",
1604 pDesc->legacy.dw3.fEC ? " EC" :"",
1605 pDesc->legacy.dw3.fLC ? " LC" :"",
1606 pDesc->legacy.cmd.u8CSO,
1607 pDesc->legacy.dw3.u8CSS,
1608 pDesc->legacy.dw3.fCFI ? " CFI" :"",
1609 pDesc->legacy.dw3.u12VLAN,
1610 pDesc->legacy.dw3.u3PRI));
1611 break;
1612 default:
1613 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1614 INSTANCE(pState), cszDir, cszDir));
1615 break;
1616 }
1617}
1618#endif /* IN_RING3 */
1619
1620/**
1621 * Hardware reset. Revert all registers to initial values.
1622 *
1623 * @param pState The device state structure.
1624 */
1625PDMBOTHCBDECL(void) e1kHardReset(E1KSTATE *pState)
1626{
1627 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1628 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1629 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1630#ifdef E1K_INIT_RA0
1631 memcpy(pState->aRecAddr.au32, pState->macConfigured.au8,
1632 sizeof(pState->macConfigured.au8));
1633 pState->aRecAddr.array[0].ctl |= RA_CTL_AV;
1634#endif /* E1K_INIT_RA0 */
1635 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1636 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1637 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1638 Assert(GET_BITS(RCTL, BSIZE) == 0);
1639 pState->u16RxBSize = 2048;
1640}
1641
1642/**
1643 * Raise interrupt if not masked.
1644 *
1645 * @param pState The device state structure.
1646 */
1647PDMBOTHCBDECL(int) e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1648{
1649 int rc = e1kCsEnter(pState, rcBusy);
1650 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1651 return rc;
1652
1653 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1654 ICR |= u32IntCause;
1655 if (ICR & IMS)
1656 {
1657#if 0
1658 if (pState->fDelayInts)
1659 {
1660 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1661 pState->iStatIntLostOne = 1;
1662 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1663 INSTANCE(pState), ICR));
1664#define E1K_LOST_IRQ_THRSLD 20
1665//#define E1K_LOST_IRQ_THRSLD 200000000
1666 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1667 {
1668 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1669 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1670 pState->fIntMaskUsed = false;
1671 pState->uStatDisDly++;
1672 }
1673 }
1674 else
1675#endif
1676 if (pState->fIntRaised)
1677 {
1678 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1679 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1680 INSTANCE(pState), ICR & IMS));
1681 }
1682 else
1683 {
1684#ifdef E1K_ITR_ENABLED
1685 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1686 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1687 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1688 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1689 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1690 {
1691 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1692 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1693 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1694 }
1695 else
1696#endif
1697 {
1698
1699 /* Since we are delivering the interrupt now
1700 * there is no need to do it later -- stop the timer.
1701 */
1702 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1703 E1K_INC_ISTAT_CNT(pState->uStatInt);
1704 STAM_COUNTER_INC(&pState->StatIntsRaised);
1705 /* Got at least one unmasked interrupt cause */
1706 pState->fIntRaised = true;
1707 /* Raise(1) INTA(0) */
1708 //PDMDevHlpPCISetIrqNoWait(pState->CTXSUFF(pInst), 0, 1);
1709 //e1kMutexRelease(pState);
1710 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1711 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1712 //e1kMutexAcquire(pState, RT_SRC_POS);
1713 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1714 INSTANCE(pState), ICR & IMS));
1715 }
1716 }
1717 }
1718 else
1719 {
1720 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1721 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1722 INSTANCE(pState), ICR, IMS));
1723 }
1724 e1kCsLeave(pState);
1725 return VINF_SUCCESS;
1726}
1727
1728#ifdef IN_RING3
1729/**
1730 * Compute the physical address of the descriptor.
1731 *
1732 * @returns the physical address of the descriptor.
1733 *
1734 * @param baseHigh High-order 32 bits of descriptor table address.
1735 * @param baseLow Low-order 32 bits of descriptor table address.
1736 * @param idxDesc The descriptor index in the table.
1737 */
1738DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1739{
1740 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1741 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1742}
1743
1744/**
1745 * Advance the head pointer of the receive descriptor queue.
1746 *
1747 * @remarks RDH always points to the next available RX descriptor.
1748 *
1749 * @param pState The device state structure.
1750 */
1751DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1752{
1753 //e1kCsEnter(pState, RT_SRC_POS);
1754 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1755 RDH = 0;
1756 /*
1757 * Compute current recieve queue length and fire RXDMT0 interrupt
1758 * if we are low on recieve buffers
1759 */
1760 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1761 /*
1762 * The minimum threshold is controlled by RDMTS bits of RCTL:
1763 * 00 = 1/2 of RDLEN
1764 * 01 = 1/4 of RDLEN
1765 * 10 = 1/8 of RDLEN
1766 * 11 = reserved
1767 */
1768 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1769 if (uRQueueLen <= uMinRQThreshold)
1770 {
1771 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1772 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1773 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1774 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1775 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1776 }
1777 //e1kCsLeave(pState);
1778}
1779
1780/**
1781 * Store a fragment of received packet that fits into the next available RX
1782 * buffer.
1783 *
1784 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1785 *
1786 * @param pState The device state structure.
1787 * @param pDesc The next available RX descriptor.
1788 * @param pvBuf The fragment.
1789 * @param cb The size of the fragment.
1790 */
1791static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1792{
1793 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1794 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1795 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1796 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1797 /* Write back the descriptor */
1798 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1799 e1kPrintRDesc(pState, pDesc);
1800 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1801 /* Advance head */
1802 e1kAdvanceRDH(pState);
1803 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1804 if (pDesc->status.fEOP)
1805 {
1806 /* Complete packet has been stored -- it is time to let the guest know. */
1807#ifdef E1K_USE_RX_TIMERS
1808 if (RDTR)
1809 {
1810 /* Arm the timer to fire in RDTR usec (discard .024) */
1811 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1812 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1813 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1814 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1815 }
1816 else
1817 {
1818#endif
1819 /* 0 delay means immediate interrupt */
1820 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1821 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1822#ifdef E1K_USE_RX_TIMERS
1823 }
1824#endif
1825 }
1826 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1827}
1828
1829/**
1830 * Returns true if it is a broadcast packet.
1831 *
1832 * @returns true if destination address indicates broadcast.
1833 * @param pvBuf The ethernet packet.
1834 */
1835DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1836{
1837 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1838 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1839}
1840
1841/**
1842 * Returns true if it is a multicast packet.
1843 *
1844 * @remarks returns true for broadcast packets as well.
1845 * @returns true if destination address indicates multicast.
1846 * @param pvBuf The ethernet packet.
1847 */
1848DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1849{
1850 return (*(char*)pvBuf) & 1;
1851}
1852
1853/**
1854 * Set IXSM, IPCS and TCPCS flags according to the packet type.
1855 *
1856 * @remarks We emulate checksum offloading for major packets types only.
1857 *
1858 * @returns VBox status code.
1859 * @param pState The device state structure.
1860 * @param pFrame The available data.
1861 * @param cb Number of bytes available in the buffer.
1862 * @param status Bit fields containing status info.
1863 */
1864static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
1865{
1866 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
1867 PRTNETIPV4 pIpHdr4;
1868
1869 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", INSTANCE(pState), uEtherType));
1870
1871 //pStatus->fIPE = false;
1872 //pStatus->fTCPE = false;
1873 switch (uEtherType)
1874 {
1875 case 0x800: /* IPv4 */
1876 pStatus->fIXSM = false;
1877 pStatus->fIPCS = true;
1878 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
1879 /* TCP/UDP checksum offloading works with TCP and UDP only */
1880 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
1881 break;
1882 case 0x86DD: /* IPv6 */
1883 pStatus->fIXSM = false;
1884 pStatus->fIPCS = false;
1885 pStatus->fTCPCS = true;
1886 break;
1887 default: /* ARP, VLAN, etc. */
1888 pStatus->fIXSM = true;
1889 break;
1890 }
1891
1892 return VINF_SUCCESS;
1893}
1894
1895/**
1896 * Pad and store received packet.
1897 *
1898 * @remarks Make sure that the packet appears to upper layer as one coming
1899 * from real Ethernet: pad it and insert FCS.
1900 *
1901 * @returns VBox status code.
1902 * @param pState The device state structure.
1903 * @param pvBuf The available data.
1904 * @param cb Number of bytes available in the buffer.
1905 * @param status Bit fields containing status info.
1906 */
1907static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
1908{
1909 E1KRXDESC desc;
1910 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
1911 uint8_t *ptr = rxPacket;
1912
1913#ifndef E1K_GLOBAL_MUTEX
1914 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1915 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1916 return rc;
1917#endif
1918
1919#ifdef E1K_LEDS_WITH_MUTEX
1920 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1921 {
1922#endif /* E1K_LEDS_WITH_MUTEX */
1923 pState->led.Asserted.s.fReading = 1;
1924 pState->led.Actual.s.fReading = 1;
1925#ifdef E1K_LEDS_WITH_MUTEX
1926 e1kCsLeave(pState);
1927 }
1928#endif /* E1K_LEDS_WITH_MUTEX */
1929
1930 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
1931 memcpy(rxPacket, pvBuf, cb);
1932 /* Pad short packets */
1933 if (cb < 60)
1934 {
1935 memset(rxPacket + cb, 0, 60 - cb);
1936 cb = 60;
1937 }
1938 if (!(RCTL & RCTL_SECRC))
1939 {
1940 /* Add FCS if CRC stripping is not enabled */
1941 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
1942 cb += sizeof(uint32_t);
1943 }
1944 /* Compute checksum of complete packet */
1945 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
1946 e1kRxChecksumOffload(pState, rxPacket, cb, &status);
1947
1948 /* Update stats */
1949 E1K_INC_CNT32(GPRC);
1950 if (e1kIsBroadcast(pvBuf))
1951 E1K_INC_CNT32(BPRC);
1952 else if (e1kIsMulticast(pvBuf))
1953 E1K_INC_CNT32(MPRC);
1954 /* Update octet receive counter */
1955 E1K_ADD_CNT64(GORCL, GORCH, cb);
1956 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
1957 if (cb == 64)
1958 E1K_INC_CNT32(PRC64);
1959 else if (cb < 128)
1960 E1K_INC_CNT32(PRC127);
1961 else if (cb < 256)
1962 E1K_INC_CNT32(PRC255);
1963 else if (cb < 512)
1964 E1K_INC_CNT32(PRC511);
1965 else if (cb < 1024)
1966 E1K_INC_CNT32(PRC1023);
1967 else
1968 E1K_INC_CNT32(PRC1522);
1969
1970 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
1971
1972 if (RDH == RDT)
1973 {
1974 E1kLog(("%s Out of recieve buffers, dropping the packet",
1975 INSTANCE(pState)));
1976 }
1977 /* Store the packet to receive buffers */
1978 while (RDH != RDT)
1979 {
1980 /* Load the desciptor pointed by head */
1981 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
1982 &desc, sizeof(desc));
1983 if (desc.u64BufAddr)
1984 {
1985 /* Update descriptor */
1986 desc.status = status;
1987 desc.u16Checksum = checksum;
1988 desc.status.fDD = true;
1989
1990 /*
1991 * We need to leave Rx critical section here or we risk deadlocking
1992 * with EMT in e1kRegWriteRDT when the write is to an unallocated
1993 * page or has an access handler associated with it.
1994 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
1995 * modifies RDT only.
1996 */
1997 if(cb > pState->u16RxBSize)
1998 {
1999 desc.status.fEOP = false;
2000 e1kCsRxLeave(pState);
2001 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
2002 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2003 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2004 return rc;
2005 ptr += pState->u16RxBSize;
2006 cb -= pState->u16RxBSize;
2007 }
2008 else
2009 {
2010 desc.status.fEOP = true;
2011 e1kCsRxLeave(pState);
2012 e1kStoreRxFragment(pState, &desc, ptr, cb);
2013#ifdef E1K_LEDS_WITH_MUTEX
2014 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2015 {
2016#endif /* E1K_LEDS_WITH_MUTEX */
2017 pState->led.Actual.s.fReading = 0;
2018#ifdef E1K_LEDS_WITH_MUTEX
2019 e1kCsLeave(pState);
2020 }
2021#endif /* E1K_LEDS_WITH_MUTEX */
2022 return VINF_SUCCESS;
2023 }
2024 /* Note: RDH is advanced by e1kStoreRxFragment! */
2025 }
2026 else
2027 {
2028 desc.status.fDD = true;
2029 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
2030 e1kDescAddr(RDBAH, RDBAL, RDH),
2031 &desc, sizeof(desc));
2032 e1kAdvanceRDH(pState);
2033 }
2034 }
2035#ifdef E1K_LEDS_WITH_MUTEX
2036 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2037 {
2038#endif /* E1K_LEDS_WITH_MUTEX */
2039 pState->led.Actual.s.fReading = 0;
2040#ifdef E1K_LEDS_WITH_MUTEX
2041 e1kCsLeave(pState);
2042 }
2043#endif /* E1K_LEDS_WITH_MUTEX */
2044
2045 e1kCsRxLeave(pState);
2046
2047 return VINF_SUCCESS;
2048}
2049
2050#endif /* IN_RING3 */
2051
2052#if 0 /* unused */
2053/**
2054 * Read handler for Device Status register.
2055 *
2056 * Get the link status from PHY.
2057 *
2058 * @returns VBox status code.
2059 *
2060 * @param pState The device state structure.
2061 * @param offset Register offset in memory-mapped frame.
2062 * @param index Register index in register array.
2063 * @param mask Used to implement partial reads (8 and 16-bit).
2064 */
2065static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2066{
2067 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2068 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2069 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2070 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2071 {
2072 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2073 if (Phy::readMDIO(&pState->phy))
2074 *pu32Value = CTRL | CTRL_MDIO;
2075 else
2076 *pu32Value = CTRL & ~CTRL_MDIO;
2077 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2078 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
2079 }
2080 else
2081 {
2082 /* MDIO pin is used for output, ignore it */
2083 *pu32Value = CTRL;
2084 }
2085 return VINF_SUCCESS;
2086}
2087#endif /* unused */
2088
2089/**
2090 * Write handler for Device Control register.
2091 *
2092 * Handles reset.
2093 *
2094 * @param pState The device state structure.
2095 * @param offset Register offset in memory-mapped frame.
2096 * @param index Register index in register array.
2097 * @param value The value to store.
2098 * @param mask Used to implement partial writes (8 and 16-bit).
2099 * @thread EMT
2100 */
2101static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2102{
2103 int rc = VINF_SUCCESS;
2104
2105 if (value & CTRL_RESET)
2106 { /* RST */
2107 e1kHardReset(pState);
2108 }
2109 else
2110 {
2111 if ( (value & CTRL_SLU)
2112 && pState->fCableConnected
2113 && !(STATUS & STATUS_LU))
2114 {
2115 /* The driver indicates that we should bring up the link */
2116 /* Do so in 5 seconds. */
2117 e1kArmTimer(pState, pState->CTX_SUFF(pLUTimer), 5000000);
2118 }
2119 if (value & CTRL_VME)
2120 {
2121 E1kLog(("%s VLAN Mode is not supported yet!\n", INSTANCE(pState)));
2122 }
2123 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2124 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2125 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2126 if (value & CTRL_MDC)
2127 {
2128 if (value & CTRL_MDIO_DIR)
2129 {
2130 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2131 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2132 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2133 }
2134 else
2135 {
2136 if (Phy::readMDIO(&pState->phy))
2137 value |= CTRL_MDIO;
2138 else
2139 value &= ~CTRL_MDIO;
2140 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2141 INSTANCE(pState), !!(value & CTRL_MDIO)));
2142 }
2143 }
2144 rc = e1kRegWriteDefault(pState, offset, index, value);
2145 }
2146
2147 return rc;
2148}
2149
2150/**
2151 * Write handler for EEPROM/Flash Control/Data register.
2152 *
2153 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2154 *
2155 * @param pState The device state structure.
2156 * @param offset Register offset in memory-mapped frame.
2157 * @param index Register index in register array.
2158 * @param value The value to store.
2159 * @param mask Used to implement partial writes (8 and 16-bit).
2160 * @thread EMT
2161 */
2162static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2163{
2164#ifdef IN_RING3
2165 /* So far we are conserned with lower byte only */
2166 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2167 {
2168 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2169 /* Note: 82543GC does not need to request EEPROM access */
2170 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2171 pState->eeprom.write(value & EECD_EE_WIRES);
2172 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2173 }
2174 if (value & EECD_EE_REQ)
2175 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2176 else
2177 EECD &= ~EECD_EE_GNT;
2178 //e1kRegWriteDefault(pState, offset, index, value );
2179
2180 return VINF_SUCCESS;
2181#else /* !IN_RING3 */
2182 return VINF_IOM_HC_MMIO_WRITE;
2183#endif /* !IN_RING3 */
2184}
2185
2186/**
2187 * Read handler for EEPROM/Flash Control/Data register.
2188 *
2189 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2190 *
2191 * @returns VBox status code.
2192 *
2193 * @param pState The device state structure.
2194 * @param offset Register offset in memory-mapped frame.
2195 * @param index Register index in register array.
2196 * @param mask Used to implement partial reads (8 and 16-bit).
2197 * @thread EMT
2198 */
2199static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2200{
2201#ifdef IN_RING3
2202 uint32_t value;
2203 int rc = e1kRegReadDefault(pState, offset, index, &value);
2204 if (RT_SUCCESS(rc))
2205 {
2206 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2207 {
2208 /* Note: 82543GC does not need to request EEPROM access */
2209 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2210 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2211 value |= pState->eeprom.read();
2212 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2213 }
2214 *pu32Value = value;
2215 }
2216
2217 return rc;
2218#else /* !IN_RING3 */
2219 return VINF_IOM_HC_MMIO_READ;
2220#endif /* !IN_RING3 */
2221}
2222
2223/**
2224 * Write handler for EEPROM Read register.
2225 *
2226 * Handles EEPROM word access requests, reads EEPROM and stores the result
2227 * into DATA field.
2228 *
2229 * @param pState The device state structure.
2230 * @param offset Register offset in memory-mapped frame.
2231 * @param index Register index in register array.
2232 * @param value The value to store.
2233 * @param mask Used to implement partial writes (8 and 16-bit).
2234 * @thread EMT
2235 */
2236static int e1kRegWriteEERD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2237{
2238#ifdef IN_RING3
2239 /* Make use of 'writable' and 'readable' masks. */
2240 e1kRegWriteDefault(pState, offset, index, value);
2241 /* DONE and DATA are set only if read was triggered by START. */
2242 if (value & EERD_START)
2243 {
2244 uint16_t tmp;
2245 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2246 if (pState->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2247 SET_BITS(EERD, DATA, tmp);
2248 EERD |= EERD_DONE;
2249 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2250 }
2251
2252 return VINF_SUCCESS;
2253#else /* !IN_RING3 */
2254 return VINF_IOM_HC_MMIO_WRITE;
2255#endif /* !IN_RING3 */
2256}
2257
2258
2259/**
2260 * Write handler for MDI Control register.
2261 *
2262 * Handles PHY read/write requests; forwards requests to internal PHY device.
2263 *
2264 * @param pState The device state structure.
2265 * @param offset Register offset in memory-mapped frame.
2266 * @param index Register index in register array.
2267 * @param value The value to store.
2268 * @param mask Used to implement partial writes (8 and 16-bit).
2269 * @thread EMT
2270 */
2271static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2272{
2273 if (value & MDIC_INT_EN)
2274 {
2275 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2276 INSTANCE(pState)));
2277 }
2278 else if (value & MDIC_READY)
2279 {
2280 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2281 INSTANCE(pState)));
2282 }
2283 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2284 {
2285 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2286 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2287 }
2288 else
2289 {
2290 /* Store the value */
2291 e1kRegWriteDefault(pState, offset, index, value);
2292 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2293 /* Forward op to PHY */
2294 if (value & MDIC_OP_READ)
2295 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2296 else
2297 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2298 /* Let software know that we are done */
2299 MDIC |= MDIC_READY;
2300 }
2301
2302 return VINF_SUCCESS;
2303}
2304
2305/**
2306 * Write handler for Interrupt Cause Read register.
2307 *
2308 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2309 *
2310 * @param pState The device state structure.
2311 * @param offset Register offset in memory-mapped frame.
2312 * @param index Register index in register array.
2313 * @param value The value to store.
2314 * @param mask Used to implement partial writes (8 and 16-bit).
2315 * @thread EMT
2316 */
2317static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2318{
2319 ICR &= ~value;
2320
2321 return VINF_SUCCESS;
2322}
2323
2324/**
2325 * Read handler for Interrupt Cause Read register.
2326 *
2327 * Reading this register acknowledges all interrupts.
2328 *
2329 * @returns VBox status code.
2330 *
2331 * @param pState The device state structure.
2332 * @param offset Register offset in memory-mapped frame.
2333 * @param index Register index in register array.
2334 * @param mask Not used.
2335 * @thread EMT
2336 */
2337static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2338{
2339 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2340 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2341 return rc;
2342
2343 uint32_t value = 0;
2344 rc = e1kRegReadDefault(pState, offset, index, &value);
2345 if (RT_SUCCESS(rc))
2346 {
2347 if (value)
2348 {
2349 /*
2350 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2351 * with disabled interrupts.
2352 */
2353 //if (IMS)
2354 if (1)
2355 {
2356 /*
2357 * Interrupts were enabled -- we are supposedly at the very
2358 * beginning of interrupt handler
2359 */
2360 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2361 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2362 /* Clear all pending interrupts */
2363 ICR = 0;
2364 pState->fIntRaised = false;
2365 /* Lower(0) INTA(0) */
2366 //PDMDevHlpPCISetIrqNoWait(pState->CTX_SUFF(pDevIns), 0, 0);
2367 //e1kMutexRelease(pState);
2368 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2369 //e1kMutexAcquire(pState, RT_SRC_POS);
2370
2371 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2372 if (pState->fIntMaskUsed)
2373 pState->fDelayInts = true;
2374 }
2375 else
2376 {
2377 /*
2378 * Interrupts are disabled -- in windows guests ICR read is done
2379 * just before re-enabling interrupts
2380 */
2381 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2382 }
2383 }
2384 *pu32Value = value;
2385 }
2386 e1kCsLeave(pState);
2387
2388 return rc;
2389}
2390
2391/**
2392 * Write handler for Interrupt Cause Set register.
2393 *
2394 * Bits corresponding to 1s in 'value' will be set in ICR register.
2395 *
2396 * @param pState The device state structure.
2397 * @param offset Register offset in memory-mapped frame.
2398 * @param index Register index in register array.
2399 * @param value The value to store.
2400 * @param mask Used to implement partial writes (8 and 16-bit).
2401 * @thread EMT
2402 */
2403static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2404{
2405 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2406 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2407}
2408
2409/**
2410 * Write handler for Interrupt Mask Set register.
2411 *
2412 * Will trigger pending interrupts.
2413 *
2414 * @param pState The device state structure.
2415 * @param offset Register offset in memory-mapped frame.
2416 * @param index Register index in register array.
2417 * @param value The value to store.
2418 * @param mask Used to implement partial writes (8 and 16-bit).
2419 * @thread EMT
2420 */
2421static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2422{
2423 IMS |= value;
2424 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2425 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2426 /* Mask changes, we need to raise pending interrupts. */
2427 if ((ICR & IMS) && !pState->fLocked)
2428 {
2429 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2430 INSTANCE(pState), ICR));
2431 //TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2432 // TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2433 e1kRaiseInterrupt(pState, VERR_SEM_BUSY);
2434 }
2435
2436 return VINF_SUCCESS;
2437}
2438
2439/**
2440 * Write handler for Interrupt Mask Clear register.
2441 *
2442 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2443 *
2444 * @param pState The device state structure.
2445 * @param offset Register offset in memory-mapped frame.
2446 * @param index Register index in register array.
2447 * @param value The value to store.
2448 * @param mask Used to implement partial writes (8 and 16-bit).
2449 * @thread EMT
2450 */
2451static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2452{
2453 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2454 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2455 return rc;
2456 if (pState->fIntRaised)
2457 {
2458 /*
2459 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2460 * Windows to freeze since it may receive an interrupt while still in the very beginning
2461 * of interrupt handler.
2462 */
2463 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2464 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2465 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2466 /* Lower(0) INTA(0) */
2467 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2468 pState->fIntRaised = false;
2469 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2470 }
2471 IMS &= ~value;
2472 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2473 e1kCsLeave(pState);
2474
2475 return VINF_SUCCESS;
2476}
2477
2478/**
2479 * Write handler for Receive Control register.
2480 *
2481 * @param pState The device state structure.
2482 * @param offset Register offset in memory-mapped frame.
2483 * @param index Register index in register array.
2484 * @param value The value to store.
2485 * @param mask Used to implement partial writes (8 and 16-bit).
2486 * @thread EMT
2487 */
2488static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2489{
2490 e1kRegWriteDefault(pState, offset, index, value);
2491 pState->u16RxBSize = 2048 >> GET_BITS(RCTL, BSIZE);
2492 if (RCTL & RCTL_BSEX)
2493 pState->u16RxBSize *= 16;
2494 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d\n",
2495 INSTANCE(pState), pState->u16RxBSize));
2496
2497 return VINF_SUCCESS;
2498}
2499
2500/**
2501 * Write handler for Packet Buffer Allocation register.
2502 *
2503 * TXA = 64 - RXA.
2504 *
2505 * @param pState The device state structure.
2506 * @param offset Register offset in memory-mapped frame.
2507 * @param index Register index in register array.
2508 * @param value The value to store.
2509 * @param mask Used to implement partial writes (8 and 16-bit).
2510 * @thread EMT
2511 */
2512static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2513{
2514 e1kRegWriteDefault(pState, offset, index, value);
2515 PBA_st->txa = 64 - PBA_st->rxa;
2516
2517 return VINF_SUCCESS;
2518}
2519
2520/**
2521 * Write handler for Receive Descriptor Tail register.
2522 *
2523 * @remarks Write into RDT forces switch to HC and signal to
2524 * e1kWaitReceiveAvail().
2525 *
2526 * @returns VBox status code.
2527 *
2528 * @param pState The device state structure.
2529 * @param offset Register offset in memory-mapped frame.
2530 * @param index Register index in register array.
2531 * @param value The value to store.
2532 * @param mask Used to implement partial writes (8 and 16-bit).
2533 * @thread EMT
2534 */
2535static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2536{
2537#ifndef IN_RING3
2538 /* XXX */
2539// return VINF_IOM_HC_MMIO_WRITE;
2540#endif
2541 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2542 if (RT_LIKELY(rc == VINF_SUCCESS))
2543 {
2544 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2545 rc = e1kRegWriteDefault(pState, offset, index, value);
2546 e1kCsRxLeave(pState);
2547 if (RT_SUCCESS(rc))
2548 {
2549#ifdef IN_RING3
2550 /* Signal that we have more receive descriptors avalable. */
2551 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2552#else
2553 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2554 if (pItem)
2555 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2556#endif
2557 }
2558 }
2559 return rc;
2560}
2561
2562/**
2563 * Write handler for Receive Delay Timer register.
2564 *
2565 * @param pState The device state structure.
2566 * @param offset Register offset in memory-mapped frame.
2567 * @param index Register index in register array.
2568 * @param value The value to store.
2569 * @param mask Used to implement partial writes (8 and 16-bit).
2570 * @thread EMT
2571 */
2572static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2573{
2574 e1kRegWriteDefault(pState, offset, index, value);
2575 if (value & RDTR_FPD)
2576 {
2577 /* Flush requested, cancel both timers and raise interrupt */
2578#ifdef E1K_USE_RX_TIMERS
2579 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2580 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2581#endif
2582 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2583 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2584 }
2585
2586 return VINF_SUCCESS;
2587}
2588
2589DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2590{
2591 /**
2592 * Make sure TDT won't change during computation. EMT may modify TDT at
2593 * any moment.
2594 */
2595 uint32_t tdt = TDT;
2596 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2597}
2598
2599#ifdef IN_RING3
2600#ifdef E1K_USE_TX_TIMERS
2601/**
2602 * Transmit Interrupt Delay Timer handler.
2603 *
2604 * @remarks We only get here when the timer expires.
2605 *
2606 * @param pDevIns Pointer to device instance structure.
2607 * @param pTimer Pointer to the timer.
2608 * @param pvUser NULL.
2609 * @thread EMT
2610 */
2611static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2612{
2613 E1KSTATE *pState = (E1KSTATE *)pvUser;
2614
2615 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2616 {
2617 E1K_INC_ISTAT_CNT(pState->uStatTID);
2618 /* Cancel absolute delay timer as we have already got attention */
2619#ifndef E1K_NO_TAD
2620 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2621#endif /* E1K_NO_TAD */
2622 e1kRaiseInterrupt(pState, ICR_TXDW);
2623 e1kMutexRelease(pState);
2624 }
2625}
2626
2627/**
2628 * Transmit Absolute Delay Timer handler.
2629 *
2630 * @remarks We only get here when the timer expires.
2631 *
2632 * @param pDevIns Pointer to device instance structure.
2633 * @param pTimer Pointer to the timer.
2634 * @param pvUser NULL.
2635 * @thread EMT
2636 */
2637static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2638{
2639 E1KSTATE *pState = (E1KSTATE *)pvUser;
2640
2641 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2642 {
2643 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2644 /* Cancel interrupt delay timer as we have already got attention */
2645 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2646 e1kRaiseInterrupt(pState, ICR_TXDW);
2647 e1kMutexRelease(pState);
2648 }
2649}
2650#endif /* E1K_USE_TX_TIMERS */
2651
2652#ifdef E1K_USE_RX_TIMERS
2653/**
2654 * Receive Interrupt Delay Timer handler.
2655 *
2656 * @remarks We only get here when the timer expires.
2657 *
2658 * @param pDevIns Pointer to device instance structure.
2659 * @param pTimer Pointer to the timer.
2660 * @param pvUser NULL.
2661 * @thread EMT
2662 */
2663static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2664{
2665 E1KSTATE *pState = (E1KSTATE *)pvUser;
2666
2667 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2668 {
2669 E1K_INC_ISTAT_CNT(pState->uStatRID);
2670 /* Cancel absolute delay timer as we have already got attention */
2671 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2672 e1kRaiseInterrupt(pState, ICR_RXT0);
2673 e1kMutexRelease(pState);
2674 }
2675}
2676
2677/**
2678 * Receive Absolute Delay Timer handler.
2679 *
2680 * @remarks We only get here when the timer expires.
2681 *
2682 * @param pDevIns Pointer to device instance structure.
2683 * @param pTimer Pointer to the timer.
2684 * @param pvUser NULL.
2685 * @thread EMT
2686 */
2687static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2688{
2689 E1KSTATE *pState = (E1KSTATE *)pvUser;
2690
2691 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2692 {
2693 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2694 /* Cancel interrupt delay timer as we have already got attention */
2695 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2696 e1kRaiseInterrupt(pState, ICR_RXT0);
2697 e1kMutexRelease(pState);
2698 }
2699}
2700#endif /* E1K_USE_RX_TIMERS */
2701
2702/**
2703 * Late Interrupt Timer handler.
2704 *
2705 * @param pDevIns Pointer to device instance structure.
2706 * @param pTimer Pointer to the timer.
2707 * @param pvUser NULL.
2708 * @thread EMT
2709 */
2710static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2711{
2712 E1KSTATE *pState = (E1KSTATE *)pvUser;
2713
2714 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2715 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2716 {
2717 STAM_COUNTER_INC(&pState->StatLateInts);
2718 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2719#if 0
2720 if (pState->iStatIntLost > -100)
2721 pState->iStatIntLost--;
2722#endif
2723 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2724 e1kMutexRelease(pState);
2725 }
2726 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2727}
2728
2729/**
2730 * Link Up Timer handler.
2731 *
2732 * @param pDevIns Pointer to device instance structure.
2733 * @param pTimer Pointer to the timer.
2734 * @param pvUser NULL.
2735 * @thread EMT
2736 */
2737static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2738{
2739 E1KSTATE *pState = (E1KSTATE *)pvUser;
2740
2741 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2742 {
2743 STATUS |= STATUS_LU;
2744 Phy::setLinkStatus(&pState->phy, true);
2745 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2746 e1kMutexRelease(pState);
2747 }
2748}
2749
2750
2751
2752
2753/**
2754 * Load transmit descriptor from guest memory.
2755 *
2756 * @param pState The device state structure.
2757 * @param pDesc Pointer to descriptor union.
2758 * @param addr Physical address in guest context.
2759 * @thread E1000_TX
2760 */
2761DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2762{
2763 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2764}
2765
2766/**
2767 * Write back transmit descriptor to guest memory.
2768 *
2769 * @param pState The device state structure.
2770 * @param pDesc Pointer to descriptor union.
2771 * @param addr Physical address in guest context.
2772 * @thread E1000_TX
2773 */
2774DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2775{
2776 /* Only the last half of the descriptor has to be written back. */
2777 e1kPrintTDesc(pState, pDesc, "^^^");
2778 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2779}
2780
2781/**
2782 * Transmit complete frame.
2783 *
2784 * @remarks Since we do not have real Ethernet medium between us and NAT (or
2785 * another connector) there is no need for padding and FCS.
2786 *
2787 * @param pState The device state structure.
2788 * @param pFrame Pointer to the frame buffer.
2789 * @param u16FrameLen Length of the frame.
2790 * @thread E1000_TX
2791 */
2792static void e1kTransmitFrame(E1KSTATE* pState, uint8_t *pFrame, uint16_t u16FrameLen)
2793{
2794/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
2795 "%.*Rhxd\n"
2796 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
2797 INSTANCE(pState), u16FrameLen, pFrame, INSTANCE(pState)));*/
2798#ifdef E1K_LEDS_WITH_MUTEX
2799 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2800 {
2801#endif /* E1K_LEDS_WITH_MUTEX */
2802 pState->led.Asserted.s.fWriting = 1;
2803 pState->led.Actual.s.fWriting = 1;
2804#ifdef E1K_LEDS_WITH_MUTEX
2805 e1kCsLeave(pState);
2806 }
2807#endif /* E1K_LEDS_WITH_MUTEX */
2808 /* Update the stats */
2809 E1K_INC_CNT32(TPT);
2810 E1K_ADD_CNT64(TOTL, TOTH, u16FrameLen);
2811 E1K_INC_CNT32(GPTC);
2812 if (e1kIsBroadcast(pFrame))
2813 E1K_INC_CNT32(BPTC);
2814 else if (e1kIsMulticast(pFrame))
2815 E1K_INC_CNT32(MPTC);
2816 /* Update octet transmit counter */
2817 E1K_ADD_CNT64(GOTCL, GOTCH, u16FrameLen);
2818 if (pState->pDrv)
2819 {
2820 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, u16FrameLen);
2821 }
2822 if (u16FrameLen == 64)
2823 E1K_INC_CNT32(PTC64);
2824 else if (u16FrameLen < 128)
2825 E1K_INC_CNT32(PTC127);
2826 else if (u16FrameLen < 256)
2827 E1K_INC_CNT32(PTC255);
2828 else if (u16FrameLen < 512)
2829 E1K_INC_CNT32(PTC511);
2830 else if (u16FrameLen < 1024)
2831 E1K_INC_CNT32(PTC1023);
2832 else
2833 E1K_INC_CNT32(PTC1522);
2834
2835 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
2836
2837 e1kPacketDump(pState, pFrame, u16FrameLen, "--> Outgoing");
2838
2839
2840 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
2841 {
2842 E1KRXDST status;
2843 status.fPIF = true;
2844 /* Loopback mode */
2845 e1kHandleRxPacket(pState, pFrame, u16FrameLen, status);
2846 }
2847 else if (pState->pDrv)
2848 {
2849 /* Release critical section to avoid deadlock in CanReceive */
2850 //e1kCsLeave(pState);
2851 e1kMutexRelease(pState);
2852 STAM_PROFILE_ADV_START(&pState->StatTransmitSend, a);
2853 int rc = pState->pDrv->pfnSendDeprecated(pState->pDrv, pFrame, u16FrameLen);
2854 STAM_PROFILE_ADV_STOP(&pState->StatTransmitSend, a);
2855 if (rc != VINF_SUCCESS)
2856 {
2857 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
2858 }
2859 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
2860 //e1kCsEnter(pState, RT_SRC_POS);
2861 }
2862#ifdef E1K_LEDS_WITH_MUTEX
2863 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2864 {
2865#endif /* E1K_LEDS_WITH_MUTEX */
2866 pState->led.Actual.s.fWriting = 0;
2867#ifdef E1K_LEDS_WITH_MUTEX
2868 e1kCsLeave(pState);
2869 }
2870#endif /* E1K_LEDS_WITH_MUTEX */
2871}
2872
2873/**
2874 * Compute and write checksum at the specified offset.
2875 *
2876 * @param pState The device state structure.
2877 * @param pPkt Pointer to the packet.
2878 * @param u16PktLen Total length of the packet.
2879 * @param cso Offset in packet to write checksum at.
2880 * @param css Offset in packet to start computing
2881 * checksum from.
2882 * @param cse Offset in packet to stop computing
2883 * checksum at.
2884 * @thread E1000_TX
2885 */
2886static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
2887{
2888 if (cso > u16PktLen)
2889 {
2890 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
2891 INSTANCE(pState), cso, u16PktLen));
2892 return;
2893 }
2894
2895 if (cse == 0)
2896 cse = u16PktLen - 1;
2897 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
2898 e1kCSum16(pPkt + css, cse - css + 1), cso,
2899 *(uint16_t*)(pPkt + cso)));
2900 *(uint16_t*)(pPkt + cso) = e1kCSum16(pPkt + css, cse - css + 1);
2901}
2902
2903/**
2904 * Add a part of descriptor's buffer to transmit frame.
2905 *
2906 * @remarks data.u64BufAddr is used uncoditionally for both data
2907 * and legacy descriptors since it is identical to
2908 * legacy.u64BufAddr.
2909 *
2910 * @param pState The device state structure.
2911 * @param pDesc Pointer to the descriptor to transmit.
2912 * @param u16Len Length of buffer to the end of segment.
2913 * @param fSend Force packet sending.
2914 * @thread E1000_TX
2915 */
2916static void e1kAddSegment(E1KSTATE* pState, E1KTXDESC* pDesc, uint16_t u16Len, bool fSend)
2917{
2918 /* TCP header being transmitted */
2919 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
2920 (pState->aTxPacket + pState->contextTSE.tu.u8CSS);
2921 /* IP header being transmitted */
2922 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
2923 (pState->aTxPacket + pState->contextTSE.ip.u8CSS);
2924
2925 E1kLog3(("%s e1kAddSegment: Length=%x, remaining payload=%x, header=%x, send=%s\n",
2926 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain,
2927 fSend ? "true" : "false"));
2928 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
2929
2930 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr,
2931 pState->aTxPacket + pState->u16TxPktLen, u16Len);
2932 E1kLog3(("%s Dump of the segment:\n"
2933 "%.*Rhxd\n"
2934 "%s --- End of dump ---\n",
2935 INSTANCE(pState), u16Len, pState->aTxPacket + pState->u16TxPktLen, INSTANCE(pState)));
2936 pState->u16TxPktLen += u16Len;
2937 E1kLog3(("%s e1kAddSegment: pState->u16TxPktLen=%x\n",
2938 INSTANCE(pState), pState->u16TxPktLen));
2939 if (pState->u16HdrRemain > 0)
2940 {
2941 /* The header was not complete, check if it is now */
2942 if (u16Len >= pState->u16HdrRemain)
2943 {
2944 /* The rest is payload */
2945 u16Len -= pState->u16HdrRemain;
2946 pState->u16HdrRemain = 0;
2947 /* Save partial checksum and flags */
2948 pState->u32SavedCsum = pTcpHdr->chksum;
2949 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
2950 /* Clear FIN and PSH flags now and set them only in the last segment */
2951 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
2952 }
2953 else
2954 {
2955 /* Still not */
2956 pState->u16HdrRemain -= u16Len;
2957 E1kLog3(("%s e1kAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
2958 INSTANCE(pState), pState->u16HdrRemain));
2959 return;
2960 }
2961 }
2962
2963 pState->u32PayRemain -= u16Len;
2964
2965 if (fSend)
2966 {
2967 /* Leave ethernet header intact */
2968 /* IP Total Length = payload + headers - ethernet header */
2969 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
2970 E1kLog3(("%s e1kAddSegment: End of packet, pIpHdr->total_len=%x\n",
2971 INSTANCE(pState), ntohs(pIpHdr->total_len)));
2972 /* Update IP Checksum */
2973 pIpHdr->chksum = 0;
2974 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2975 pState->contextTSE.ip.u8CSO,
2976 pState->contextTSE.ip.u8CSS,
2977 pState->contextTSE.ip.u16CSE);
2978
2979 /* Update TCP flags */
2980 /* Restore original FIN and PSH flags for the last segment */
2981 if (pState->u32PayRemain == 0)
2982 {
2983 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
2984 E1K_INC_CNT32(TSCTC);
2985 }
2986 /* Add TCP length to partial pseudo header sum */
2987 uint32_t csum = pState->u32SavedCsum
2988 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
2989 while (csum >> 16)
2990 csum = (csum >> 16) + (csum & 0xFFFF);
2991 pTcpHdr->chksum = csum;
2992 /* Compute final checksum */
2993 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2994 pState->contextTSE.tu.u8CSO,
2995 pState->contextTSE.tu.u8CSS,
2996 pState->contextTSE.tu.u16CSE);
2997 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
2998 /* Update Sequence Number */
2999 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
3000 - pState->contextTSE.dw3.u8HDRLEN);
3001 /* Increment IP identification */
3002 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
3003 }
3004}
3005
3006/**
3007 * Add descriptor's buffer to transmit frame.
3008 *
3009 * @remarks data.u64BufAddr is used uncoditionally for both data
3010 * and legacy descriptors since it is identical to
3011 * legacy.u64BufAddr.
3012 *
3013 * @param pState The device state structure.
3014 * @param pDesc Pointer to the descriptor to transmit.
3015 * @param u16PartLen Length of descriptor's buffer.
3016 * @thread E1000_TX
3017 */
3018static bool e1kAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t u32PartLen)
3019{
3020 if (e1kGetDescType(pDesc) == E1K_DTYP_DATA && pDesc->data.cmd.fTSE)
3021 {
3022 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
3023 Assert(u16MaxPktLen != 0);
3024 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
3025
3026 do {
3027 /* Calculate how many bytes have left in this TCP segment */
3028 uint32_t uLen = u16MaxPktLen - pState->u16TxPktLen;
3029 if (uLen > u32PartLen)
3030 {
3031 /* This descriptor fits completely into current segment */
3032 uLen = u32PartLen;
3033 e1kAddSegment(pState, pDesc, uLen, pDesc->data.cmd.fEOP);
3034 }
3035 else
3036 {
3037 e1kAddSegment(pState, pDesc, uLen, true);
3038 /*
3039 * Rewind the packet tail pointer to the beginning of payload,
3040 * so we continue writing right beyond the header.
3041 */
3042 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
3043 }
3044 pDesc->data.u64BufAddr += uLen;
3045 u32PartLen -= uLen;
3046 } while (u32PartLen > 0);
3047 if (pDesc->data.cmd.fEOP)
3048 {
3049 /* End of packet, next segment will contain header. */
3050 pState->u16TxPktLen = 0;
3051 }
3052 return false;
3053 }
3054 else
3055 {
3056 if (u32PartLen + pState->u16TxPktLen > E1K_MAX_TX_PKT_SIZE)
3057 {
3058 E1kLog(("%s Transmit packet is too large: %d > %d(max)\n",
3059 INSTANCE(pState), u32PartLen + pState->u16TxPktLen, E1K_MAX_TX_PKT_SIZE));
3060 return false;
3061 }
3062 else
3063 {
3064 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr, pState->aTxPacket + pState->u16TxPktLen, u32PartLen);
3065 pState->u16TxPktLen += u32PartLen;
3066 }
3067 }
3068
3069 return true;
3070}
3071
3072
3073/**
3074 * Write the descriptor back to guest memory and notify the guest.
3075 *
3076 * @param pState The device state structure.
3077 * @param pDesc Pointer to the descriptor have been transmited.
3078 * @param addr Physical address of the descriptor in guest memory.
3079 * @thread E1000_TX
3080 */
3081static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3082{
3083 /*
3084 * We fake descriptor write-back bursting. Descriptors are written back as they are
3085 * processed.
3086 */
3087 /* Let's pretend we process descriptors. Write back with DD set. */
3088 if (pDesc->legacy.cmd.fRS || (GET_BITS(TXDCTL, WTHRESH) > 0))
3089 {
3090 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
3091 e1kWriteBackDesc(pState, pDesc, addr);
3092 if (pDesc->legacy.cmd.fEOP)
3093 {
3094#ifdef E1K_USE_TX_TIMERS
3095 if (pDesc->legacy.cmd.fIDE)
3096 {
3097 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
3098 //if (pState->fIntRaised)
3099 //{
3100 // /* Interrupt is already pending, no need for timers */
3101 // ICR |= ICR_TXDW;
3102 //}
3103 //else {
3104 /* Arm the timer to fire in TIVD usec (discard .024) */
3105 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
3106#ifndef E1K_NO_TAD
3107 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
3108 E1kLog2(("%s Checking if TAD timer is running\n",
3109 INSTANCE(pState)));
3110 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
3111 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
3112#endif /* E1K_NO_TAD */
3113 }
3114 else
3115 {
3116 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
3117 INSTANCE(pState)));
3118#ifndef E1K_NO_TAD
3119 /* Cancel both timers if armed and fire immediately. */
3120 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
3121#endif /* E1K_NO_TAD */
3122#endif /* E1K_USE_TX_TIMERS */
3123 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
3124 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
3125#ifdef E1K_USE_TX_TIMERS
3126 }
3127#endif /* E1K_USE_TX_TIMERS */
3128 }
3129 }
3130 else
3131 {
3132 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
3133 }
3134}
3135
3136/**
3137 * Process Transmit Descriptor.
3138 *
3139 * E1000 supports three types of transmit descriptors:
3140 * - legacy data descriptors of older format (context-less).
3141 * - data the same as legacy but providing new offloading capabilities.
3142 * - context sets up the context for following data descriptors.
3143 *
3144 * @param pState The device state structure.
3145 * @param pDesc Pointer to descriptor union.
3146 * @param addr Physical address of descriptor in guest memory.
3147 * @thread E1000_TX
3148 */
3149static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3150{
3151 e1kPrintTDesc(pState, pDesc, "vvv");
3152
3153#ifdef E1K_USE_TX_TIMERS
3154 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3155#endif /* E1K_USE_TX_TIMERS */
3156
3157 switch (e1kGetDescType(pDesc))
3158 {
3159 case E1K_DTYP_CONTEXT:
3160 if (pDesc->context.dw2.fTSE)
3161 {
3162 pState->contextTSE = pDesc->context;
3163 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3164 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3165 }
3166 else
3167 pState->contextNormal = pDesc->context;
3168 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3169 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3170 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3171 pDesc->context.ip.u8CSS,
3172 pDesc->context.ip.u8CSO,
3173 pDesc->context.ip.u16CSE,
3174 pDesc->context.tu.u8CSS,
3175 pDesc->context.tu.u8CSO,
3176 pDesc->context.tu.u16CSE));
3177 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3178 e1kDescReport(pState, pDesc, addr);
3179 break;
3180 case E1K_DTYP_DATA:
3181 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3182 {
3183 E1kLog2(("% Empty descriptor, skipped.\n", INSTANCE(pState)));
3184 break;
3185 }
3186 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3187 &pState->StatTxDescTSEData:
3188 &pState->StatTxDescData);
3189 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3190 /* IXSM and TXSM options are valid in the first fragment only */
3191 if (pState->u16TxPktLen == 0)
3192 {
3193 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3194 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3195 E1kLog2(("%s Saving checksum flags:%s%s\n", INSTANCE(pState),
3196 pState->fIPcsum ? " IP" : "",
3197 pState->fTCPcsum ? " TCP/UDP" : ""));
3198 }
3199 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3200 if (e1kAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN) && pDesc->data.cmd.fEOP)
3201 {
3202 if (!pDesc->data.cmd.fTSE)
3203 {
3204 /*
3205 * We only insert checksums here if this packet was not segmented,
3206 * otherwise it has already been taken care of by e1kAddSegment().
3207 */
3208 if (pState->fIPcsum)
3209 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3210 pState->contextNormal.ip.u8CSO,
3211 pState->contextNormal.ip.u8CSS,
3212 pState->contextNormal.ip.u16CSE);
3213 if (pState->fTCPcsum)
3214 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3215 pState->contextNormal.tu.u8CSO,
3216 pState->contextNormal.tu.u8CSS,
3217 pState->contextNormal.tu.u16CSE);
3218 }
3219 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3220 /* Reset transmit packet storage. */
3221 pState->u16TxPktLen = 0;
3222 }
3223 e1kDescReport(pState, pDesc, addr);
3224 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3225 break;
3226 case E1K_DTYP_LEGACY:
3227 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3228 {
3229 E1kLog(("%s Empty descriptor, skipped.\n", INSTANCE(pState)));
3230 break;
3231 }
3232 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3233 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3234 if (e1kAddToFrame(pState, pDesc, pDesc->legacy.cmd.u16Length))
3235 {
3236 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3237 /** @todo Offload processing goes here. */
3238 if (pDesc->legacy.cmd.fEOP)
3239 {
3240 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3241 /* Reset transmit packet storage. */
3242 pState->u16TxPktLen = 0;
3243 }
3244 }
3245 e1kDescReport(pState, pDesc, addr);
3246 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3247 break;
3248 default:
3249 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3250 INSTANCE(pState), e1kGetDescType(pDesc)));
3251 break;
3252 }
3253}
3254
3255/**
3256 * Wake up callback for transmission thread.
3257 *
3258 * @returns VBox status code. Returning failure will naturally terminate the thread.
3259 * @param pDevIns The pcnet device instance.
3260 * @param pThread The thread.
3261 */
3262static DECLCALLBACK(int) e1kTxThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3263{
3264 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3265 int rc = RTSemEventSignal(pState->hTxSem);
3266 AssertRC(rc);
3267 return VINF_SUCCESS;
3268}
3269
3270/**
3271 * I/O thread for packet transmission.
3272 *
3273 * @returns VBox status code. Returning failure will naturally terminate the thread.
3274 * @param pDevIns Pointer to device instance structure.
3275 * @param pThread The thread.
3276 * @thread E1000_TX
3277 */
3278static DECLCALLBACK(int) e1kTxThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3279{
3280 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3281
3282 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3283 {
3284 int rc = RTSemEventWait(pState->hTxSem, RT_INDEFINITE_WAIT);
3285 AssertRCReturn(rc, rc);
3286 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3287 break;
3288
3289 if (pThread->enmState == PDMTHREADSTATE_RUNNING)
3290 {
3291 E1KTXDESC desc;
3292 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3293 AssertRCReturn(rc, rc);
3294 /* Do not process descriptors in locked state */
3295 while (TDH != TDT && !pState->fLocked)
3296 {
3297 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3298 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3299 //if (!e1kCsEnter(pState, RT_SRC_POS))
3300 // return VERR_PERMISSION_DENIED;
3301 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3302 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3303 if (++TDH * sizeof(desc) >= TDLEN)
3304 TDH = 0;
3305 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3306 {
3307 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3308 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3309 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3310 }
3311 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3312 //e1kCsLeave(pState);
3313 }
3314 /// @todo: uncomment: pState->uStatIntTXQE++;
3315 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3316 e1kMutexRelease(pState);
3317 }
3318 }
3319 return VINF_SUCCESS;
3320}
3321
3322/**
3323 * Callback for consuming from transmit queue. It gets called in R3 whenever
3324 * we enqueue something in R0/GC.
3325 *
3326 * @returns true
3327 * @param pDevIns Pointer to device instance structure.
3328 * @param pItem Pointer to the element being dequeued (not used).
3329 * @thread ???
3330 */
3331static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3332{
3333 NOREF(pItem);
3334 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3335 E1kLog2(("%s e1kTxQueueConsumer: Waking up TX thread...\n", INSTANCE(pState)));
3336 int rc = RTSemEventSignal(pState->hTxSem);
3337 AssertRC(rc);
3338 return true;
3339}
3340
3341/**
3342 * Handler for the wakeup signaller queue.
3343 */
3344static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3345{
3346 e1kWakeupReceive(pDevIns);
3347 return true;
3348}
3349
3350#endif /* IN_RING3 */
3351
3352/**
3353 * Write handler for Transmit Descriptor Tail register.
3354 *
3355 * @param pState The device state structure.
3356 * @param offset Register offset in memory-mapped frame.
3357 * @param index Register index in register array.
3358 * @param value The value to store.
3359 * @param mask Used to implement partial writes (8 and 16-bit).
3360 * @thread EMT
3361 */
3362static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3363{
3364#ifndef IN_RING3
3365// return VINF_IOM_HC_MMIO_WRITE;
3366#endif
3367 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
3368 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3369 return rc;
3370 rc = e1kRegWriteDefault(pState, offset, index, value);
3371 /* All descriptors starting with head and not including tail belong to us. */
3372 /* Process them. */
3373 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3374 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
3375 /* Ignore TDT writes when the link is down. */
3376 if (TDH != TDT && (STATUS & STATUS_LU))
3377 {
3378 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
3379 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
3380 INSTANCE(pState), e1kGetTxLen(pState)));
3381#ifdef IN_RING3
3382 rc = RTSemEventSignal(pState->hTxSem);
3383 AssertRC(rc);
3384#else
3385 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
3386 if (RT_UNLIKELY(pItem))
3387 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
3388#endif /* !IN_RING3 */
3389
3390 }
3391 e1kCsTxLeave(pState);
3392
3393 return rc;
3394}
3395
3396/**
3397 * Write handler for Multicast Table Array registers.
3398 *
3399 * @param pState The device state structure.
3400 * @param offset Register offset in memory-mapped frame.
3401 * @param index Register index in register array.
3402 * @param value The value to store.
3403 * @thread EMT
3404 */
3405static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3406{
3407 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3408 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
3409
3410 return VINF_SUCCESS;
3411}
3412
3413/**
3414 * Read handler for Multicast Table Array registers.
3415 *
3416 * @returns VBox status code.
3417 *
3418 * @param pState The device state structure.
3419 * @param offset Register offset in memory-mapped frame.
3420 * @param index Register index in register array.
3421 * @thread EMT
3422 */
3423static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3424{
3425 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3426 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
3427
3428 return VINF_SUCCESS;
3429}
3430
3431/**
3432 * Write handler for Receive Address registers.
3433 *
3434 * @param pState The device state structure.
3435 * @param offset Register offset in memory-mapped frame.
3436 * @param index Register index in register array.
3437 * @param value The value to store.
3438 * @thread EMT
3439 */
3440static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3441{
3442 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3443 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
3444
3445 return VINF_SUCCESS;
3446}
3447
3448/**
3449 * Read handler for Receive Address registers.
3450 *
3451 * @returns VBox status code.
3452 *
3453 * @param pState The device state structure.
3454 * @param offset Register offset in memory-mapped frame.
3455 * @param index Register index in register array.
3456 * @thread EMT
3457 */
3458static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3459{
3460 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3461 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
3462
3463 return VINF_SUCCESS;
3464}
3465
3466/**
3467 * Write handler for VLAN Filter Table Array registers.
3468 *
3469 * @param pState The device state structure.
3470 * @param offset Register offset in memory-mapped frame.
3471 * @param index Register index in register array.
3472 * @param value The value to store.
3473 * @thread EMT
3474 */
3475static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3476{
3477 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
3478 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
3479
3480 return VINF_SUCCESS;
3481}
3482
3483/**
3484 * Read handler for VLAN Filter Table Array registers.
3485 *
3486 * @returns VBox status code.
3487 *
3488 * @param pState The device state structure.
3489 * @param offset Register offset in memory-mapped frame.
3490 * @param index Register index in register array.
3491 * @thread EMT
3492 */
3493static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3494{
3495 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
3496 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
3497
3498 return VINF_SUCCESS;
3499}
3500
3501/**
3502 * Read handler for unimplemented registers.
3503 *
3504 * Merely reports reads from unimplemented registers.
3505 *
3506 * @returns VBox status code.
3507 *
3508 * @param pState The device state structure.
3509 * @param offset Register offset in memory-mapped frame.
3510 * @param index Register index in register array.
3511 * @thread EMT
3512 */
3513
3514static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3515{
3516 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
3517 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3518 *pu32Value = 0;
3519
3520 return VINF_SUCCESS;
3521}
3522
3523/**
3524 * Default register read handler with automatic clear operation.
3525 *
3526 * Retrieves the value of register from register array in device state structure.
3527 * Then resets all bits.
3528 *
3529 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3530 * done in the caller.
3531 *
3532 * @returns VBox status code.
3533 *
3534 * @param pState The device state structure.
3535 * @param offset Register offset in memory-mapped frame.
3536 * @param index Register index in register array.
3537 * @thread EMT
3538 */
3539
3540static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3541{
3542 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3543 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
3544 pState->auRegs[index] = 0;
3545
3546 return rc;
3547}
3548
3549/**
3550 * Default register read handler.
3551 *
3552 * Retrieves the value of register from register array in device state structure.
3553 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
3554 *
3555 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3556 * done in the caller.
3557 *
3558 * @returns VBox status code.
3559 *
3560 * @param pState The device state structure.
3561 * @param offset Register offset in memory-mapped frame.
3562 * @param index Register index in register array.
3563 * @thread EMT
3564 */
3565
3566static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3567{
3568 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3569 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
3570
3571 return VINF_SUCCESS;
3572}
3573
3574/**
3575 * Write handler for unimplemented registers.
3576 *
3577 * Merely reports writes to unimplemented registers.
3578 *
3579 * @param pState The device state structure.
3580 * @param offset Register offset in memory-mapped frame.
3581 * @param index Register index in register array.
3582 * @param value The value to store.
3583 * @thread EMT
3584 */
3585
3586static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3587{
3588 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
3589 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3590
3591 return VINF_SUCCESS;
3592}
3593
3594/**
3595 * Default register write handler.
3596 *
3597 * Stores the value to the register array in device state structure. Only bits
3598 * corresponding to 1s both in 'writable' and 'mask' will be stored.
3599 *
3600 * @returns VBox status code.
3601 *
3602 * @param pState The device state structure.
3603 * @param offset Register offset in memory-mapped frame.
3604 * @param index Register index in register array.
3605 * @param value The value to store.
3606 * @param mask Used to implement partial writes (8 and 16-bit).
3607 * @thread EMT
3608 */
3609
3610static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3611{
3612 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3613 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
3614 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
3615
3616 return VINF_SUCCESS;
3617}
3618
3619/**
3620 * Search register table for matching register.
3621 *
3622 * @returns Index in the register table or -1 if not found.
3623 *
3624 * @param pState The device state structure.
3625 * @param uOffset Register offset in memory-mapped region.
3626 * @thread EMT
3627 */
3628static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
3629{
3630 int index;
3631
3632 for (index = 0; index < E1K_NUM_OF_REGS; index++)
3633 {
3634 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
3635 {
3636 return index;
3637 }
3638 }
3639
3640 return -1;
3641}
3642
3643/**
3644 * Handle register read operation.
3645 *
3646 * Looks up and calls appropriate handler.
3647 *
3648 * @returns VBox status code.
3649 *
3650 * @param pState The device state structure.
3651 * @param uOffset Register offset in memory-mapped frame.
3652 * @param pv Where to store the result.
3653 * @param cb Number of bytes to read.
3654 * @thread EMT
3655 */
3656static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
3657{
3658 uint32_t u32 = 0;
3659 uint32_t mask = 0;
3660 uint32_t shift;
3661 int rc = VINF_SUCCESS;
3662 int index = e1kRegLookup(pState, uOffset);
3663 const char *szInst = INSTANCE(pState);
3664#ifdef DEBUG
3665 char buf[9];
3666#endif
3667
3668 /*
3669 * From the spec:
3670 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3671 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3672 */
3673
3674 /*
3675 * To be able to write bytes and short word we convert them
3676 * to properly shifted 32-bit words and masks. The idea is
3677 * to keep register-specific handlers simple. Most accesses
3678 * will be 32-bit anyway.
3679 */
3680 switch (cb)
3681 {
3682 case 1: mask = 0x000000FF; break;
3683 case 2: mask = 0x0000FFFF; break;
3684 case 4: mask = 0xFFFFFFFF; break;
3685 default:
3686 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3687 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
3688 szInst, uOffset, cb);
3689 }
3690 if (index != -1)
3691 {
3692 if (s_e1kRegMap[index].readable)
3693 {
3694 /* Make the mask correspond to the bits we are about to read. */
3695 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
3696 mask <<= shift;
3697 if (!mask)
3698 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3699 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
3700 szInst, uOffset, cb);
3701 /*
3702 * Read it. Pass the mask so the handler knows what has to be read.
3703 * Mask out irrelevant bits.
3704 */
3705#ifdef E1K_GLOBAL_MUTEX
3706 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
3707#else
3708 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3709#endif
3710 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3711 return rc;
3712 //pState->fDelayInts = false;
3713 //pState->iStatIntLost += pState->iStatIntLostOne;
3714 //pState->iStatIntLostOne = 0;
3715 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32) & mask;
3716 //e1kCsLeave(pState);
3717 e1kMutexRelease(pState);
3718 E1kLog2(("%s At %08X read %s from %s (%s)\n",
3719 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3720 /* Shift back the result. */
3721 u32 >>= shift;
3722 }
3723 else
3724 {
3725 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
3726 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3727 }
3728 }
3729 else
3730 {
3731 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
3732 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
3733 }
3734
3735 memcpy(pv, &u32, cb);
3736 return rc;
3737}
3738
3739/**
3740 * Handle register write operation.
3741 *
3742 * Looks up and calls appropriate handler.
3743 *
3744 * @returns VBox status code.
3745 *
3746 * @param pState The device state structure.
3747 * @param uOffset Register offset in memory-mapped frame.
3748 * @param pv Where to fetch the value.
3749 * @param cb Number of bytes to write.
3750 * @thread EMT
3751 */
3752static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void *pv, unsigned cb)
3753{
3754 int rc = VINF_SUCCESS;
3755 int index = e1kRegLookup(pState, uOffset);
3756 uint32_t u32;
3757
3758 /*
3759 * From the spec:
3760 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3761 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3762 */
3763
3764 if (cb != 4)
3765 {
3766 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
3767 INSTANCE(pState), uOffset, cb));
3768 return VINF_SUCCESS;
3769 }
3770 if (uOffset & 3)
3771 {
3772 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
3773 INSTANCE(pState), uOffset, cb));
3774 return VINF_SUCCESS;
3775 }
3776 u32 = *(uint32_t*)pv;
3777 if (index != -1)
3778 {
3779 if (s_e1kRegMap[index].writable)
3780 {
3781 /*
3782 * Write it. Pass the mask so the handler knows what has to be written.
3783 * Mask out irrelevant bits.
3784 */
3785 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
3786 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3787#ifdef E1K_GLOBAL_MUTEX
3788 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
3789#else
3790 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3791#endif
3792 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3793 return rc;
3794 //pState->fDelayInts = false;
3795 //pState->iStatIntLost += pState->iStatIntLostOne;
3796 //pState->iStatIntLostOne = 0;
3797 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
3798 //e1kCsLeave(pState);
3799 e1kMutexRelease(pState);
3800 }
3801 else
3802 {
3803 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
3804 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3805 }
3806 }
3807 else
3808 {
3809 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
3810 INSTANCE(pState), uOffset, u32));
3811 }
3812 return rc;
3813}
3814
3815/**
3816 * I/O handler for memory-mapped read operations.
3817 *
3818 * @returns VBox status code.
3819 *
3820 * @param pDevIns The device instance.
3821 * @param pvUser User argument.
3822 * @param GCPhysAddr Physical address (in GC) where the read starts.
3823 * @param pv Where to store the result.
3824 * @param cb Number of bytes read.
3825 * @thread EMT
3826 */
3827PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
3828 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3829{
3830 NOREF(pvUser);
3831 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3832 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3833 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIORead), a);
3834
3835 Assert(uOffset < E1K_MM_SIZE);
3836
3837 int rc = e1kRegRead(pState, uOffset, pv, cb);
3838 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIORead), a);
3839 return rc;
3840}
3841
3842/**
3843 * Memory mapped I/O Handler for write operations.
3844 *
3845 * @returns VBox status code.
3846 *
3847 * @param pDevIns The device instance.
3848 * @param pvUser User argument.
3849 * @param GCPhysAddr Physical address (in GC) where the read starts.
3850 * @param pv Where to fetch the value.
3851 * @param cb Number of bytes to write.
3852 * @thread EMT
3853 */
3854PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
3855 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3856{
3857 NOREF(pvUser);
3858 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3859 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3860 int rc;
3861 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIOWrite), a);
3862
3863 Assert(uOffset < E1K_MM_SIZE);
3864 if (cb != 4)
3865 {
3866 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
3867 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
3868 }
3869 else
3870 rc = e1kRegWrite(pState, uOffset, pv, cb);
3871
3872 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIOWrite), a);
3873 return rc;
3874}
3875
3876/**
3877 * Port I/O Handler for IN operations.
3878 *
3879 * @returns VBox status code.
3880 *
3881 * @param pDevIns The device instance.
3882 * @param pvUser Pointer to the device state structure.
3883 * @param port Port number used for the IN operation.
3884 * @param pu32 Where to store the result.
3885 * @param cb Number of bytes read.
3886 * @thread EMT
3887 */
3888PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
3889 RTIOPORT port, uint32_t *pu32, unsigned cb)
3890{
3891 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3892 int rc = VINF_SUCCESS;
3893 const char *szInst = INSTANCE(pState);
3894 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
3895
3896 port -= pState->addrIOPort;
3897 if (cb != 4)
3898 {
3899 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
3900 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3901 }
3902 else
3903 switch (port)
3904 {
3905 case 0x00: /* IOADDR */
3906 *pu32 = pState->uSelectedReg;
3907 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3908 break;
3909 case 0x04: /* IODATA */
3910 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
3911 /* @todo wrong return code triggers assertions in the debug build; fix please */
3912 if (rc == VINF_IOM_HC_MMIO_READ)
3913 rc = VINF_IOM_HC_IOPORT_READ;
3914
3915 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3916 break;
3917 default:
3918 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
3919 //*pRC = VERR_IOM_IOPORT_UNUSED;
3920 }
3921
3922 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
3923 return rc;
3924}
3925
3926
3927/**
3928 * Port I/O Handler for OUT operations.
3929 *
3930 * @returns VBox status code.
3931 *
3932 * @param pDevIns The device instance.
3933 * @param pvUser User argument.
3934 * @param Port Port number used for the IN operation.
3935 * @param u32 The value to output.
3936 * @param cb The value size in bytes.
3937 * @thread EMT
3938 */
3939PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
3940 RTIOPORT port, uint32_t u32, unsigned cb)
3941{
3942 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3943 int rc = VINF_SUCCESS;
3944 const char *szInst = INSTANCE(pState);
3945 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
3946
3947 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
3948 if (cb != 4)
3949 {
3950 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
3951 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3952 }
3953 else
3954 {
3955 port -= pState->addrIOPort;
3956 switch (port)
3957 {
3958 case 0x00: /* IOADDR */
3959 pState->uSelectedReg = u32;
3960 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
3961 break;
3962 case 0x04: /* IODATA */
3963 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
3964 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
3965 /* @todo wrong return code triggers assertions in the debug build; fix please */
3966 if (rc == VINF_IOM_HC_MMIO_WRITE)
3967 rc = VINF_IOM_HC_IOPORT_WRITE;
3968 break;
3969 default:
3970 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
3971 /** @todo Do we need to return an error here?
3972 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
3973 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
3974 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
3975 }
3976 }
3977
3978 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
3979 return rc;
3980}
3981
3982#ifdef IN_RING3
3983/**
3984 * Dump complete device state to log.
3985 *
3986 * @param pState Pointer to device state.
3987 */
3988static void e1kDumpState(E1KSTATE *pState)
3989{
3990 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
3991 {
3992 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
3993 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
3994 }
3995#ifdef E1K_INT_STATS
3996 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
3997 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
3998 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
3999 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
4000 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
4001 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
4002 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
4003 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
4004 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
4005 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
4006 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
4007 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
4008 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
4009 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
4010 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
4011 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
4012 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
4013 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
4014 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
4015 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
4016 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
4017 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
4018 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
4019 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
4020 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
4021 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
4022 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
4023#endif /* E1K_INT_STATS */
4024}
4025
4026/**
4027 * Map PCI I/O region.
4028 *
4029 * @return VBox status code.
4030 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4031 * @param iRegion The region number.
4032 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4033 * I/O port, else it's a physical address.
4034 * This address is *NOT* relative to pci_mem_base like earlier!
4035 * @param cb Region size.
4036 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4037 * @thread EMT
4038 */
4039static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
4040 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4041{
4042 int rc;
4043 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
4044
4045 switch (enmType)
4046 {
4047 case PCI_ADDRESS_SPACE_IO:
4048 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
4049 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4050 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
4051 if (RT_FAILURE(rc))
4052 break;
4053 if (pState->fR0Enabled)
4054 {
4055 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4056 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4057 if (RT_FAILURE(rc))
4058 break;
4059 }
4060 if (pState->fGCEnabled)
4061 {
4062 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4063 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4064 }
4065 break;
4066 case PCI_ADDRESS_SPACE_MEM:
4067 pState->addrMMReg = GCPhysAddress;
4068 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4069 e1kMMIOWrite, e1kMMIORead, NULL, "E1000");
4070 if (pState->fR0Enabled)
4071 {
4072 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4073 "e1kMMIOWrite", "e1kMMIORead", NULL);
4074 if (RT_FAILURE(rc))
4075 break;
4076 }
4077 if (pState->fGCEnabled)
4078 {
4079 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4080 "e1kMMIOWrite", "e1kMMIORead", NULL);
4081 }
4082 break;
4083 default:
4084 /* We should never get here */
4085 AssertMsgFailed(("Invalid PCI address space param in map callback"));
4086 rc = VERR_INTERNAL_ERROR;
4087 break;
4088 }
4089 return rc;
4090}
4091
4092/**
4093 * Check if the device can receive data now.
4094 * This must be called before the pfnRecieve() method is called.
4095 *
4096 * @returns Number of bytes the device can receive.
4097 * @param pInterface Pointer to the interface structure containing the called function pointer.
4098 * @thread EMT
4099 */
4100static int e1kCanReceive(E1KSTATE *pState)
4101{
4102 size_t cb;
4103
4104 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
4105 return VERR_NET_NO_BUFFER_SPACE;
4106 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
4107 return VERR_NET_NO_BUFFER_SPACE;
4108
4109 if (RDH < RDT)
4110 cb = (RDT - RDH) * pState->u16RxBSize;
4111 else if (RDH > RDT)
4112 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
4113 else
4114 {
4115 cb = 0;
4116 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
4117 }
4118
4119 e1kCsRxLeave(pState);
4120 e1kMutexRelease(pState);
4121 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
4122}
4123
4124static DECLCALLBACK(int) e1kWaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4125{
4126 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkDown);
4127 int rc = e1kCanReceive(pState);
4128
4129 if (RT_SUCCESS(rc))
4130 return VINF_SUCCESS;
4131 if (RT_UNLIKELY(cMillies == 0))
4132 return VERR_NET_NO_BUFFER_SPACE;
4133
4134 rc = VERR_INTERRUPTED;
4135 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
4136 STAM_PROFILE_START(&pState->StatRxOverflow, a);
4137 VMSTATE enmVMState;
4138 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pState->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
4139 || enmVMState == VMSTATE_RUNNING_LS))
4140 {
4141 int rc2 = e1kCanReceive(pState);
4142 if (RT_SUCCESS(rc2))
4143 {
4144 rc = VINF_SUCCESS;
4145 break;
4146 }
4147 E1kLogRel(("E1000 e1kWaitReceiveAvail: waiting cMillies=%u...\n",
4148 cMillies));
4149 E1kLog(("%s e1kWaitReceiveAvail: waiting cMillies=%u...\n",
4150 INSTANCE(pState), cMillies));
4151 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
4152 }
4153 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
4154 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
4155
4156 return rc;
4157}
4158
4159
4160/**
4161 * Matches the packet addresses against Receive Address table. Looks for
4162 * exact matches only.
4163 *
4164 * @returns true if address matches.
4165 * @param pState Pointer to the state structure.
4166 * @param pvBuf The ethernet packet.
4167 * @param cb Number of bytes available in the packet.
4168 * @thread EMT
4169 */
4170static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4171{
4172 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4173 {
4174 E1KRAELEM* ra = pState->aRecAddr.array + i;
4175
4176 /* Valid address? */
4177 if (ra->ctl & RA_CTL_AV)
4178 {
4179 Assert((ra->ctl & RA_CTL_AS) < 2);
4180 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4181 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4182 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4183 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4184 /*
4185 * Address Select:
4186 * 00b = Destination address
4187 * 01b = Source address
4188 * 10b = Reserved
4189 * 11b = Reserved
4190 * Since ethernet header is (DA, SA, len) we can use address
4191 * select as index.
4192 */
4193 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4194 ra->addr, sizeof(ra->addr)) == 0)
4195 return true;
4196 }
4197 }
4198
4199 return false;
4200}
4201
4202/**
4203 * Matches the packet addresses against Multicast Table Array.
4204 *
4205 * @remarks This is imperfect match since it matches not exact address but
4206 * a subset of addresses.
4207 *
4208 * @returns true if address matches.
4209 * @param pState Pointer to the state structure.
4210 * @param pvBuf The ethernet packet.
4211 * @param cb Number of bytes available in the packet.
4212 * @thread EMT
4213 */
4214static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4215{
4216 /* Get bits 32..47 of destination address */
4217 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4218
4219 unsigned offset = GET_BITS(RCTL, MO);
4220 /*
4221 * offset means:
4222 * 00b = bits 36..47
4223 * 01b = bits 35..46
4224 * 10b = bits 34..45
4225 * 11b = bits 32..43
4226 */
4227 if (offset < 3)
4228 u16Bit = u16Bit >> (4 - offset);
4229 return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
4230}
4231
4232/**
4233 * Determines if the packet is to be delivered to upper layer. The following
4234 * filters supported:
4235 * - Exact Unicast/Multicast
4236 * - Promiscuous Unicast/Multicast
4237 * - Multicast
4238 * - VLAN
4239 *
4240 * @returns true if packet is intended for this node.
4241 * @param pState Pointer to the state structure.
4242 * @param pvBuf The ethernet packet.
4243 * @param cb Number of bytes available in the packet.
4244 * @param pStatus Bit field to store status bits.
4245 * @thread EMT
4246 */
4247static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4248{
4249 Assert(cb > 14);
4250 /* Assume that we fail to pass exact filter. */
4251 pStatus->fPIF = false;
4252 pStatus->fVP = false;
4253 /* Discard oversized packets */
4254 if (cb > E1K_MAX_RX_PKT_SIZE)
4255 {
4256 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4257 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4258 E1K_INC_CNT32(ROC);
4259 return false;
4260 }
4261 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4262 {
4263 /* When long packet reception is disabled packets over 1522 are discarded */
4264 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4265 INSTANCE(pState), cb));
4266 E1K_INC_CNT32(ROC);
4267 return false;
4268 }
4269
4270 /* Broadcast filtering */
4271 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4272 return true;
4273 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4274 if (e1kIsMulticast(pvBuf))
4275 {
4276 /* Is multicast promiscuous enabled? */
4277 if (RCTL & RCTL_MPE)
4278 return true;
4279 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4280 /* Try perfect matches first */
4281 if (e1kPerfectMatch(pState, pvBuf))
4282 {
4283 pStatus->fPIF = true;
4284 return true;
4285 }
4286 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4287 if (e1kImperfectMatch(pState, pvBuf))
4288 return true;
4289 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
4290 }
4291 else {
4292 /* Is unicast promiscuous enabled? */
4293 if (RCTL & RCTL_UPE)
4294 return true;
4295 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
4296 if (e1kPerfectMatch(pState, pvBuf))
4297 {
4298 pStatus->fPIF = true;
4299 return true;
4300 }
4301 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4302 }
4303 /* Is VLAN filtering enabled? */
4304 if (RCTL & RCTL_VFE)
4305 {
4306 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4307 /* Compare TPID with VLAN Ether Type */
4308 if (u16Ptr[6] == VET)
4309 {
4310 pStatus->fVP = true;
4311 /* It is 802.1q packet indeed, let's filter by VID */
4312 if (ASMBitTest(pState->auVFTA, RT_BE2H_U16(u16Ptr[7]) & 0xFFF))
4313 return true;
4314 E1kLog2(("%s Packet filter: no VLAN match\n", INSTANCE(pState)));
4315 }
4316 }
4317 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
4318 return false;
4319}
4320
4321/**
4322 * Receive data from the network.
4323 *
4324 * @returns VBox status code.
4325 * @param pInterface Pointer to the interface structure containing the called function pointer.
4326 * @param pvBuf The available data.
4327 * @param cb Number of bytes available in the buffer.
4328 * @thread ???
4329 */
4330static DECLCALLBACK(int) e1kReceive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
4331{
4332 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkDown);
4333 int rc = VINF_SUCCESS;
4334
4335 /*
4336 * Drop packets if the VM is not running yet/anymore.
4337 */
4338 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pState));
4339 if ( enmVMState != VMSTATE_RUNNING
4340 && enmVMState != VMSTATE_RUNNING_LS)
4341 {
4342 E1kLog(("%s Dropping incoming packet as VM is not running.\n", INSTANCE(pState)));
4343 return VINF_SUCCESS;
4344 }
4345
4346 /* Discard incoming packets in locked state */
4347 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
4348 {
4349 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
4350 return VINF_SUCCESS;
4351 }
4352
4353 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
4354 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4355 if (RT_LIKELY(rc == VINF_SUCCESS))
4356 {
4357 //if (!e1kCsEnter(pState, RT_SRC_POS))
4358 // return VERR_PERMISSION_DENIED;
4359
4360 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
4361
4362 /* Update stats */
4363 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
4364 {
4365 E1K_INC_CNT32(TPR);
4366 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
4367 e1kCsLeave(pState);
4368 }
4369 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
4370 E1KRXDST status;
4371 memset(&status, 0, sizeof(status));
4372 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
4373 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
4374 if (fPassed)
4375 {
4376 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
4377 }
4378 //e1kCsLeave(pState);
4379 e1kMutexRelease(pState);
4380 }
4381 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
4382
4383 return rc;
4384}
4385
4386/**
4387 * Gets the pointer to the status LED of a unit.
4388 *
4389 * @returns VBox status code.
4390 * @param pInterface Pointer to the interface structure.
4391 * @param iLUN The unit which status LED we desire.
4392 * @param ppLed Where to store the LED pointer.
4393 * @thread EMT
4394 */
4395static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4396{
4397 E1KSTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
4398 int rc = VERR_PDM_LUN_NOT_FOUND;
4399
4400 if (iLUN == 0)
4401 {
4402 *ppLed = &pState->led;
4403 rc = VINF_SUCCESS;
4404 }
4405 return rc;
4406}
4407
4408/**
4409 * Gets the current Media Access Control (MAC) address.
4410 *
4411 * @returns VBox status code.
4412 * @param pInterface Pointer to the interface structure containing the called function pointer.
4413 * @param pMac Where to store the MAC address.
4414 * @thread EMT
4415 */
4416static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4417{
4418 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4419 pState->eeprom.getMac(pMac);
4420 return VINF_SUCCESS;
4421}
4422
4423
4424/**
4425 * Gets the new link state.
4426 *
4427 * @returns The current link state.
4428 * @param pInterface Pointer to the interface structure containing the called function pointer.
4429 * @thread EMT
4430 */
4431static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
4432{
4433 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4434 if (STATUS & STATUS_LU)
4435 return PDMNETWORKLINKSTATE_UP;
4436 return PDMNETWORKLINKSTATE_DOWN;
4437}
4438
4439
4440/**
4441 * Sets the new link state.
4442 *
4443 * @returns VBox status code.
4444 * @param pInterface Pointer to the interface structure containing the called function pointer.
4445 * @param enmState The new link state
4446 * @thread EMT
4447 */
4448static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4449{
4450 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4451 bool fOldUp = !!(STATUS & STATUS_LU);
4452 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
4453
4454 if (fNewUp != fOldUp)
4455 {
4456 if (fNewUp)
4457 {
4458 E1kLog(("%s Link will be up in approximately 5 secs\n", INSTANCE(pState)));
4459 pState->fCableConnected = true;
4460 STATUS &= ~STATUS_LU;
4461 Phy::setLinkStatus(&pState->phy, false);
4462 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4463 /* Restore the link back in 5 second. */
4464 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
4465 }
4466 else
4467 {
4468 E1kLog(("%s Link is down\n", INSTANCE(pState)));
4469 pState->fCableConnected = false;
4470 STATUS &= ~STATUS_LU;
4471 Phy::setLinkStatus(&pState->phy, false);
4472 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4473 }
4474 if (pState->pDrv)
4475 pState->pDrv->pfnNotifyLinkChanged(pState->pDrv, enmState);
4476 }
4477 return VINF_SUCCESS;
4478}
4479
4480/**
4481 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4482 */
4483static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
4484{
4485 E1KSTATE *pThis = IFACE_TO_STATE(pInterface, IBase);
4486 Assert(&pThis->IBase == pInterface);
4487
4488 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4489 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
4490 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
4491 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
4492 return NULL;
4493}
4494
4495/**
4496 * Saves the configuration.
4497 *
4498 * @param pState The E1K state.
4499 * @param pSSM The handle to the saved state.
4500 */
4501static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
4502{
4503 SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
4504 SSMR3PutU32(pSSM, pState->eChip);
4505}
4506
4507/**
4508 * Live save - save basic configuration.
4509 *
4510 * @returns VBox status code.
4511 * @param pDevIns The device instance.
4512 * @param pSSM The handle to the saved state.
4513 * @param uPass
4514 */
4515static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4516{
4517 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4518 e1kSaveConfig(pState, pSSM);
4519 return VINF_SSM_DONT_CALL_AGAIN;
4520}
4521
4522/**
4523 * Prepares for state saving.
4524 *
4525 * @returns VBox status code.
4526 * @param pDevIns The device instance.
4527 * @param pSSM The handle to the saved state.
4528 */
4529static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4530{
4531 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4532
4533 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4534 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4535 return rc;
4536 e1kCsLeave(pState);
4537 return VINF_SUCCESS;
4538#if 0
4539 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4540 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4541 return rc;
4542 /* 1) Prevent all threads from modifying the state and memory */
4543 //pState->fLocked = true;
4544 /* 2) Cancel all timers */
4545#ifdef E1K_USE_TX_TIMERS
4546 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
4547#ifndef E1K_NO_TAD
4548 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
4549#endif /* E1K_NO_TAD */
4550#endif /* E1K_USE_TX_TIMERS */
4551#ifdef E1K_USE_RX_TIMERS
4552 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
4553 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
4554#endif /* E1K_USE_RX_TIMERS */
4555 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
4556 /* 3) Did I forget anything? */
4557 E1kLog(("%s Locked\n", INSTANCE(pState)));
4558 e1kMutexRelease(pState);
4559 return VINF_SUCCESS;
4560#endif
4561}
4562
4563
4564/**
4565 * Saves the state of device.
4566 *
4567 * @returns VBox status code.
4568 * @param pDevIns The device instance.
4569 * @param pSSM The handle to the saved state.
4570 */
4571static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4572{
4573 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4574
4575 e1kSaveConfig(pState, pSSM);
4576 pState->eeprom.save(pSSM);
4577 e1kDumpState(pState);
4578 SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
4579 SSMR3PutBool(pSSM, pState->fIntRaised);
4580 Phy::saveState(pSSM, &pState->phy);
4581 SSMR3PutU32(pSSM, pState->uSelectedReg);
4582 SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
4583 SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
4584 SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
4585 SSMR3PutU64(pSSM, pState->u64AckedAt);
4586 SSMR3PutU16(pSSM, pState->u16RxBSize);
4587 //SSMR3PutBool(pSSM, pState->fDelayInts);
4588 //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
4589 SSMR3PutU16(pSSM, pState->u16TxPktLen);
4590 SSMR3PutMem(pSSM, pState->aTxPacket, pState->u16TxPktLen);
4591 SSMR3PutBool(pSSM, pState->fIPcsum);
4592 SSMR3PutBool(pSSM, pState->fTCPcsum);
4593 SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
4594 SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
4595 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
4596 return VINF_SUCCESS;
4597}
4598
4599#if 0
4600/**
4601 * Cleanup after saving.
4602 *
4603 * @returns VBox status code.
4604 * @param pDevIns The device instance.
4605 * @param pSSM The handle to the saved state.
4606 */
4607static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4608{
4609 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4610
4611 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4612 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4613 return rc;
4614 /* If VM is being powered off unlocking will result in assertions in PGM */
4615 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
4616 pState->fLocked = false;
4617 else
4618 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
4619 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
4620 e1kMutexRelease(pState);
4621 return VINF_SUCCESS;
4622}
4623#endif
4624
4625/**
4626 * Sync with .
4627 *
4628 * @returns VBox status code.
4629 * @param pDevIns The device instance.
4630 * @param pSSM The handle to the saved state.
4631 */
4632static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4633{
4634 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4635
4636 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4637 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4638 return rc;
4639 e1kCsLeave(pState);
4640 return VINF_SUCCESS;
4641}
4642
4643/**
4644 * Restore previously saved state of device.
4645 *
4646 * @returns VBox status code.
4647 * @param pDevIns The device instance.
4648 * @param pSSM The handle to the saved state.
4649 * @param uVersion The data unit version number.
4650 * @param uPass The data pass.
4651 */
4652static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4653{
4654 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4655 int rc;
4656
4657 if ( uVersion != E1K_SAVEDSTATE_VERSION
4658 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
4659 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4660
4661 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
4662 || uPass != SSM_PASS_FINAL)
4663 {
4664 /* config checks */
4665 RTMAC macConfigured;
4666 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
4667 AssertRCReturn(rc, rc);
4668 if ( memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
4669 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4670 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", INSTANCE(pState), &pState->macConfigured, &macConfigured));
4671
4672 E1KCHIP eChip;
4673 rc = SSMR3GetU32(pSSM, &eChip);
4674 AssertRCReturn(rc, rc);
4675 if (eChip != pState->eChip)
4676 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pState->eChip, eChip);
4677 }
4678
4679 if (uPass == SSM_PASS_FINAL)
4680 {
4681 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
4682 {
4683 rc = pState->eeprom.load(pSSM);
4684 AssertRCReturn(rc, rc);
4685 }
4686 /* the state */
4687 SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
4688 SSMR3GetBool(pSSM, &pState->fIntRaised);
4689 /** @todo: PHY could be made a separate device with its own versioning */
4690 Phy::loadState(pSSM, &pState->phy);
4691 SSMR3GetU32(pSSM, &pState->uSelectedReg);
4692 SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
4693 SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
4694 SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
4695 SSMR3GetU64(pSSM, &pState->u64AckedAt);
4696 SSMR3GetU16(pSSM, &pState->u16RxBSize);
4697 //SSMR3GetBool(pSSM, pState->fDelayInts);
4698 //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
4699 SSMR3GetU16(pSSM, &pState->u16TxPktLen);
4700 SSMR3GetMem(pSSM, &pState->aTxPacket[0], pState->u16TxPktLen);
4701 SSMR3GetBool(pSSM, &pState->fIPcsum);
4702 SSMR3GetBool(pSSM, &pState->fTCPcsum);
4703 SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
4704 rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
4705 AssertRCReturn(rc, rc);
4706 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
4707 e1kDumpState(pState);
4708 }
4709 return VINF_SUCCESS;
4710}
4711
4712/**
4713 * Link status adjustments after loading.
4714 *
4715 * @returns VBox status code.
4716 * @param pDevIns The device instance.
4717 * @param pSSM The handle to the saved state.
4718 */
4719static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4720{
4721 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4722
4723 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4724 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4725 return rc;
4726 /*
4727 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
4728 * passed to us. We go through all this stuff if the link was up and we
4729 * wasn't teleported.
4730 */
4731 if ( (STATUS & STATUS_LU)
4732 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
4733 {
4734 E1kLog(("%s Link is down temporarily\n", INSTANCE(pState)));
4735 STATUS &= ~STATUS_LU;
4736 Phy::setLinkStatus(&pState->phy, false);
4737 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4738 /* Restore the link back in five seconds. */
4739 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
4740 }
4741 e1kMutexRelease(pState);
4742 return VINF_SUCCESS;
4743}
4744
4745/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
4746
4747#ifdef VBOX_DYNAMIC_NET_ATTACH
4748
4749/**
4750 * Detach notification.
4751 *
4752 * One port on the network card has been disconnected from the network.
4753 *
4754 * @param pDevIns The device instance.
4755 * @param iLUN The logical unit which is being detached.
4756 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4757 */
4758static DECLCALLBACK(void) e1kDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4759{
4760 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4761 Log(("%s e1kDetach:\n", INSTANCE(pState)));
4762
4763 AssertLogRelReturnVoid(iLUN == 0);
4764
4765 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
4766
4767 /** @todo: r=pritesh still need to check if i missed
4768 * to clean something in this function
4769 */
4770
4771 /*
4772 * Zero some important members.
4773 */
4774 pState->pDrvBase = NULL;
4775 pState->pDrv = NULL;
4776
4777 PDMCritSectLeave(&pState->cs);
4778}
4779
4780
4781/**
4782 * Attach the Network attachment.
4783 *
4784 * One port on the network card has been connected to a network.
4785 *
4786 * @returns VBox status code.
4787 * @param pDevIns The device instance.
4788 * @param iLUN The logical unit which is being attached.
4789 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4790 *
4791 * @remarks This code path is not used during construction.
4792 */
4793static DECLCALLBACK(int) e1kAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4794{
4795 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4796 LogFlow(("%s e1kAttach:\n", INSTANCE(pState)));
4797
4798 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
4799
4800 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
4801
4802 /*
4803 * Attach the driver.
4804 */
4805 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
4806 if (RT_SUCCESS(rc))
4807 {
4808 if (rc == VINF_NAT_DNS)
4809 {
4810#ifdef RT_OS_LINUX
4811 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
4812 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4813#else
4814 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
4815 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
4816#endif
4817 }
4818 pState->pDrv = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
4819 AssertMsgStmt(pState->pDrv, ("Failed to obtain the PDMINETWORKUP interface!\n"),
4820 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
4821 }
4822 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4823 Log(("%s No attached driver!\n", INSTANCE(pState)));
4824
4825
4826 /*
4827 * Temporary set the link down if it was up so that the guest
4828 * will know that we have change the configuration of the
4829 * network card
4830 */
4831 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
4832 {
4833 STATUS &= ~STATUS_LU;
4834 Phy::setLinkStatus(&pState->phy, false);
4835 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4836 /* Restore the link back in 5 second. */
4837 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
4838 }
4839
4840 PDMCritSectLeave(&pState->cs);
4841 return rc;
4842
4843}
4844
4845#endif /* VBOX_DYNAMIC_NET_ATTACH */
4846
4847/**
4848 * @copydoc FNPDMDEVPOWEROFF
4849 */
4850static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
4851{
4852 /* Poke thread waiting for buffer space. */
4853 e1kWakeupReceive(pDevIns);
4854}
4855
4856/**
4857 * @copydoc FNPDMDEVSUSPEND
4858 */
4859static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
4860{
4861 /* Poke thread waiting for buffer space. */
4862 e1kWakeupReceive(pDevIns);
4863}
4864
4865/**
4866 * Device relocation callback.
4867 *
4868 * When this callback is called the device instance data, and if the
4869 * device have a GC component, is being relocated, or/and the selectors
4870 * have been changed. The device must use the chance to perform the
4871 * necessary pointer relocations and data updates.
4872 *
4873 * Before the GC code is executed the first time, this function will be
4874 * called with a 0 delta so GC pointer calculations can be one in one place.
4875 *
4876 * @param pDevIns Pointer to the device instance.
4877 * @param offDelta The relocation delta relative to the old location.
4878 *
4879 * @remark A relocation CANNOT fail.
4880 */
4881static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4882{
4883 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4884 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4885 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
4886 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
4887#ifdef E1K_USE_RX_TIMERS
4888 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
4889 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
4890#endif /* E1K_USE_RX_TIMERS */
4891#ifdef E1K_USE_TX_TIMERS
4892 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
4893# ifndef E1K_NO_TAD
4894 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
4895# endif /* E1K_NO_TAD */
4896#endif /* E1K_USE_TX_TIMERS */
4897 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
4898 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
4899}
4900
4901/**
4902 * Destruct a device instance.
4903 *
4904 * We need to free non-VM resources only.
4905 *
4906 * @returns VBox status.
4907 * @param pDevIns The device instance data.
4908 * @thread EMT
4909 */
4910static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
4911{
4912 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4913 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4914
4915 e1kDumpState(pState);
4916 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
4917 if (PDMCritSectIsInitialized(&pState->cs))
4918 {
4919 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
4920 {
4921 RTSemEventSignal(pState->hEventMoreRxDescAvail);
4922 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
4923 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
4924 }
4925 if (pState->hTxSem != NIL_RTSEMEVENT)
4926 {
4927 RTSemEventDestroy(pState->hTxSem);
4928 pState->hTxSem = NIL_RTSEMEVENT;
4929 }
4930#ifndef E1K_GLOBAL_MUTEX
4931 PDMR3CritSectDelete(&pState->csRx);
4932 //PDMR3CritSectDelete(&pState->csTx);
4933#endif
4934 PDMR3CritSectDelete(&pState->cs);
4935 }
4936 return VINF_SUCCESS;
4937}
4938
4939/**
4940 * Sets 8-bit register in PCI configuration space.
4941 * @param refPciDev The PCI device.
4942 * @param uOffset The register offset.
4943 * @param u16Value The value to store in the register.
4944 * @thread EMT
4945 */
4946DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
4947{
4948 Assert(uOffset < sizeof(refPciDev.config));
4949 refPciDev.config[uOffset] = u8Value;
4950}
4951
4952/**
4953 * Sets 16-bit register in PCI configuration space.
4954 * @param refPciDev The PCI device.
4955 * @param uOffset The register offset.
4956 * @param u16Value The value to store in the register.
4957 * @thread EMT
4958 */
4959DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
4960{
4961 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
4962 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
4963}
4964
4965/**
4966 * Sets 32-bit register in PCI configuration space.
4967 * @param refPciDev The PCI device.
4968 * @param uOffset The register offset.
4969 * @param u32Value The value to store in the register.
4970 * @thread EMT
4971 */
4972DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
4973{
4974 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
4975 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
4976}
4977
4978/**
4979 * Set PCI configuration space registers.
4980 *
4981 * @param pci Reference to PCI device structure.
4982 * @thread EMT
4983 */
4984static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
4985{
4986 Assert(eChip < RT_ELEMENTS(g_Chips));
4987 /* Configure PCI Device, assume 32-bit mode ******************************/
4988 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
4989 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
4990 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
4991 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
4992
4993 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
4994 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
4995 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS, 0x0230);
4996 /* Stepping A2 */
4997 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
4998 /* Ethernet adapter */
4999 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
5000 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
5001 /* normal single function Ethernet controller */
5002 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
5003 /* Memory Register Base Address */
5004 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
5005 /* Memory Flash Base Address */
5006 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
5007 /* IO Register Base Address */
5008 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
5009 /* Expansion ROM Base Address */
5010 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
5011 /* Capabilities Pointer */
5012 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
5013 /* Interrupt Pin: INTA# */
5014 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
5015 /* Max_Lat/Min_Gnt: very high priority and time slice */
5016 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
5017 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
5018
5019 /* PCI Power Management Registers ****************************************/
5020 /* Capability ID: PCI Power Management Registers */
5021 e1kPCICfgSetU8( pci, 0xDC, 0x01);
5022 /* Next Item Pointer: PCI-X */
5023 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
5024 /* Power Management Capabilities: PM disabled, DSI */
5025 e1kPCICfgSetU16(pci, 0xDC + 2, 0x0022);
5026 /* Power Management Control / Status Register: PM disabled */
5027 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
5028 /* PMCSR_BSE Bridge Support Extensions: Not supported */
5029 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
5030 /* Data Register: PM disabled, always 0 */
5031 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
5032
5033 /* PCI-X Configuration Registers *****************************************/
5034 /* Capability ID: PCI-X Configuration Registers */
5035 e1kPCICfgSetU8( pci, 0xE4, 0x07);
5036 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
5037 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
5038 /* PCI-X Command: Enable Relaxed Ordering */
5039 e1kPCICfgSetU16(pci, 0xE4 + 2, 0x0002);
5040 /* PCI-X Status: 32-bit, 66MHz*/
5041 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
5042}
5043
5044/**
5045 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5046 */
5047static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5048{
5049 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5050 int rc;
5051 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5052
5053 /* Init handles and log related stuff. */
5054 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
5055 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
5056 pState->hTxSem = NIL_RTSEMEVENT;
5057 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5058
5059 /*
5060 * Validate configuration.
5061 */
5062 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0"))
5063 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5064 N_("Invalid configuration for E1000 device"));
5065
5066 /** @todo: LineSpeed unused! */
5067
5068 /* Get config params */
5069 rc = CFGMR3QueryBytes(pCfg, "MAC", pState->macConfigured.au8,
5070 sizeof(pState->macConfigured.au8));
5071 if (RT_FAILURE(rc))
5072 return PDMDEV_SET_ERROR(pDevIns, rc,
5073 N_("Configuration error: Failed to get MAC address"));
5074 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pState->fCableConnected);
5075 if (RT_FAILURE(rc))
5076 return PDMDEV_SET_ERROR(pDevIns, rc,
5077 N_("Configuration error: Failed to get the value of 'CableConnected'"));
5078 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pState->eChip);
5079 if (RT_FAILURE(rc))
5080 return PDMDEV_SET_ERROR(pDevIns, rc,
5081 N_("Configuration error: Failed to get the value of 'AdapterType'"));
5082 Assert(pState->eChip <= E1K_CHIP_82545EM);
5083
5084 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
5085
5086 /* Initialize state structure */
5087 pState->fR0Enabled = true;
5088 pState->fGCEnabled = true;
5089 pState->pDevInsR3 = pDevIns;
5090 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5091 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5092 pState->u16TxPktLen = 0;
5093 pState->fIPcsum = false;
5094 pState->fTCPcsum = false;
5095 pState->fIntMaskUsed = false;
5096 pState->fDelayInts = false;
5097 pState->fLocked = false;
5098 pState->u64AckedAt = 0;
5099 pState->led.u32Magic = PDMLED_MAGIC;
5100 pState->u32PktNo = 1;
5101
5102#ifdef E1K_INT_STATS
5103 pState->uStatInt = 0;
5104 pState->uStatIntTry = 0;
5105 pState->uStatIntLower = 0;
5106 pState->uStatIntDly = 0;
5107 pState->uStatDisDly = 0;
5108 pState->iStatIntLost = 0;
5109 pState->iStatIntLostOne = 0;
5110 pState->uStatIntLate = 0;
5111 pState->uStatIntMasked = 0;
5112 pState->uStatIntEarly = 0;
5113 pState->uStatIntRx = 0;
5114 pState->uStatIntTx = 0;
5115 pState->uStatIntICS = 0;
5116 pState->uStatIntRDTR = 0;
5117 pState->uStatIntRXDMT0 = 0;
5118 pState->uStatIntTXQE = 0;
5119 pState->uStatTxNoRS = 0;
5120 pState->uStatTxIDE = 0;
5121 pState->uStatTAD = 0;
5122 pState->uStatTID = 0;
5123 pState->uStatRAD = 0;
5124 pState->uStatRID = 0;
5125 pState->uStatRxFrm = 0;
5126 pState->uStatTxFrm = 0;
5127 pState->uStatDescCtx = 0;
5128 pState->uStatDescDat = 0;
5129 pState->uStatDescLeg = 0;
5130#endif /* E1K_INT_STATS */
5131
5132 /* Interfaces */
5133 pState->IBase.pfnQueryInterface = e1kQueryInterface;
5134 pState->INetworkDown.pfnWaitReceiveAvail = e1kWaitReceiveAvail;
5135 pState->INetworkDown.pfnReceive = e1kReceive;
5136 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
5137 pState->INetworkConfig.pfnGetMac = e1kGetMac;
5138 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
5139 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
5140
5141 /* Initialize the EEPROM */
5142 pState->eeprom.init(pState->macConfigured);
5143
5144 /* Initialize internal PHY */
5145 Phy::init(&pState->phy, iInstance,
5146 pState->eChip == E1K_CHIP_82543GC?
5147 PHY_EPID_M881000 : PHY_EPID_M881011);
5148 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
5149
5150 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
5151 NULL, e1kLiveExec, NULL,
5152 e1kSavePrep, e1kSaveExec, NULL,
5153 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
5154 if (RT_FAILURE(rc))
5155 return rc;
5156
5157 /* Initialize critical section */
5158 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
5159 if (RT_FAILURE(rc))
5160 return rc;
5161#ifndef E1K_GLOBAL_MUTEX
5162 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, RT_SRC_POS, "%sRX", pState->szInstance);
5163 if (RT_FAILURE(rc))
5164 return rc;
5165#endif
5166
5167 /* Set PCI config registers */
5168 e1kConfigurePCI(pState->pciDevice, pState->eChip);
5169 /* Register PCI device */
5170 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
5171 if (RT_FAILURE(rc))
5172 return rc;
5173
5174 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
5175 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
5176 PCI_ADDRESS_SPACE_MEM, e1kMap);
5177 if (RT_FAILURE(rc))
5178 return rc;
5179 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
5180 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
5181 PCI_ADDRESS_SPACE_IO, e1kMap);
5182 if (RT_FAILURE(rc))
5183 return rc;
5184
5185 /* Create transmit queue */
5186 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5187 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3);
5188 if (RT_FAILURE(rc))
5189 return rc;
5190 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
5191 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5192
5193 /* Create the RX notifier signaller. */
5194 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5195 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3);
5196 if (RT_FAILURE(rc))
5197 return rc;
5198 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
5199 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5200
5201#ifdef E1K_USE_TX_TIMERS
5202 /* Create Transmit Interrupt Delay Timer */
5203 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pState,
5204 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5205 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
5206 if (RT_FAILURE(rc))
5207 return rc;
5208 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
5209 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5210
5211# ifndef E1K_NO_TAD
5212 /* Create Transmit Absolute Delay Timer */
5213 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pState,
5214 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5215 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
5216 if (RT_FAILURE(rc))
5217 return rc;
5218 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
5219 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5220# endif /* E1K_NO_TAD */
5221#endif /* E1K_USE_TX_TIMERS */
5222
5223#ifdef E1K_USE_RX_TIMERS
5224 /* Create Receive Interrupt Delay Timer */
5225 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pState,
5226 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5227 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
5228 if (RT_FAILURE(rc))
5229 return rc;
5230 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
5231 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5232
5233 /* Create Receive Absolute Delay Timer */
5234 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pState,
5235 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5236 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
5237 if (RT_FAILURE(rc))
5238 return rc;
5239 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
5240 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5241#endif /* E1K_USE_RX_TIMERS */
5242
5243 /* Create Late Interrupt Timer */
5244 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pState,
5245 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5246 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
5247 if (RT_FAILURE(rc))
5248 return rc;
5249 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
5250 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5251
5252 /* Create Link Up Timer */
5253 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pState,
5254 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5255 "E1000 Link Up Timer", &pState->pLUTimerR3);
5256 if (RT_FAILURE(rc))
5257 return rc;
5258 pState->pLUTimerR0 = TMTimerR0Ptr(pState->pLUTimerR3);
5259 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5260
5261 /* Status driver */
5262 PPDMIBASE pBase;
5263 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
5264 if (RT_FAILURE(rc))
5265 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
5266 pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5267
5268 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5269 if (RT_SUCCESS(rc))
5270 {
5271 if (rc == VINF_NAT_DNS)
5272 {
5273 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5274 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5275 }
5276 pState->pDrv = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5277 AssertMsgReturn(pState->pDrv, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5278 VERR_PDM_MISSING_INTERFACE_BELOW);
5279 }
5280 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5281 {
5282 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
5283 }
5284 else
5285 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
5286
5287 rc = RTSemEventCreate(&pState->hTxSem);
5288 if (RT_FAILURE(rc))
5289 return rc;
5290 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
5291 if (RT_FAILURE(rc))
5292 return rc;
5293
5294 e1kHardReset(pState);
5295
5296 rc = PDMDevHlpThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");
5297 if (RT_FAILURE(rc))
5298 return rc;
5299
5300#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5301 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/E1k%d/MMIO/ReadGC", iInstance);
5302 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/E1k%d/MMIO/ReadHC", iInstance);
5303 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/E1k%d/MMIO/WriteGC", iInstance);
5304 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/E1k%d/MMIO/WriteHC", iInstance);
5305 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
5306 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
5307 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/E1k%d/IO/ReadGC", iInstance);
5308 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/E1k%d/IO/ReadHC", iInstance);
5309 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/E1k%d/IO/WriteGC", iInstance);
5310 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/E1k%d/IO/WriteHC", iInstance);
5311 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
5312 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
5313 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
5314 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
5315 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
5316 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
5317 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
5318 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
5319 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
5320#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5321 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
5322#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5323 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/E1k%d/Transmit/Total", iInstance);
5324#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5325 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
5326#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5327 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in HC", "/Devices/E1k%d/Transmit/Send", iInstance);
5328
5329 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
5330 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
5331 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
5332 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
5333#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5334
5335 return VINF_SUCCESS;
5336}
5337
5338/**
5339 * The device registration structure.
5340 */
5341const PDMDEVREG g_DeviceE1000 =
5342{
5343 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
5344 PDM_DEVREG_VERSION,
5345 /* Device name. */
5346 "e1000",
5347 /* Name of guest context module (no path).
5348 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5349 "VBoxDDGC.gc",
5350 /* Name of ring-0 module (no path).
5351 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5352 "VBoxDDR0.r0",
5353 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
5354 * remain unchanged from registration till VM destruction. */
5355 "Intel PRO/1000 MT Desktop Ethernet.\n",
5356
5357 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
5358 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5359 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
5360 PDM_DEVREG_CLASS_NETWORK,
5361 /* Maximum number of instances (per VM). */
5362 8,
5363 /* Size of the instance data. */
5364 sizeof(E1KSTATE),
5365
5366 /* Construct instance - required. */
5367 e1kConstruct,
5368 /* Destruct instance - optional. */
5369 e1kDestruct,
5370 /* Relocation command - optional. */
5371 e1kRelocate,
5372 /* I/O Control interface - optional. */
5373 NULL,
5374 /* Power on notification - optional. */
5375 NULL,
5376 /* Reset notification - optional. */
5377 NULL,
5378 /* Suspend notification - optional. */
5379 e1kSuspend,
5380 /* Resume notification - optional. */
5381 NULL,
5382#ifdef VBOX_DYNAMIC_NET_ATTACH
5383 /* Attach command - optional. */
5384 e1kAttach,
5385 /* Detach notification - optional. */
5386 e1kDetach,
5387#else /* !VBOX_DYNAMIC_NET_ATTACH */
5388 /* Attach command - optional. */
5389 NULL,
5390 /* Detach notification - optional. */
5391 NULL,
5392#endif /* !VBOX_DYNAMIC_NET_ATTACH */
5393 /* Query a LUN base interface - optional. */
5394 NULL,
5395 /* Init complete notification - optional. */
5396 NULL,
5397 /* Power off notification - optional. */
5398 e1kPowerOff,
5399 /* pfnSoftReset */
5400 NULL,
5401 /* u32VersionEnd */
5402 PDM_DEVREG_VERSION
5403};
5404
5405#endif /* IN_RING3 */
5406#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5407
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