VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 39344

Last change on this file since 39344 was 39344, checked in by vboxsync, 13 years ago

e1000: move part of eth header instead of packet body (#4806)
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1/* $Id: DevE1000.cpp 39344 2011-11-17 11:21:13Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2011 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28#define LOG_GROUP LOG_GROUP_DEV_E1000
29
30//#define E1kLogRel(a) LogRel(a)
31#define E1kLogRel(a)
32
33/* Options */
34#define E1K_INIT_RA0
35#define E1K_LSC_ON_SLU
36#define E1K_ITR_ENABLED
37//#define E1K_GLOBAL_MUTEX
38//#define E1K_USE_TX_TIMERS
39//#define E1K_NO_TAD
40//#define E1K_REL_DEBUG
41//#define E1K_INT_STATS
42//#define E1K_REL_STATS
43//#define E1K_USE_SUPLIB_SEMEVENT
44//#define E1K_WITH_MSI
45
46#include <iprt/crc.h>
47#include <iprt/ctype.h>
48#include <iprt/net.h>
49#include <iprt/semaphore.h>
50#include <iprt/string.h>
51#include <iprt/uuid.h>
52#include <VBox/vmm/pdmdev.h>
53#include <VBox/vmm/pdmnetifs.h>
54#include <VBox/vmm/pdmnetinline.h>
55#include <VBox/param.h>
56#include "VBoxDD.h"
57
58#include "DevEEPROM.h"
59#include "DevE1000Phy.h"
60
61/* Little helpers ************************************************************/
62#undef htons
63#undef ntohs
64#undef htonl
65#undef ntohl
66#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
67#define ntohs(x) htons(x)
68#define htonl(x) ASMByteSwapU32(x)
69#define ntohl(x) htonl(x)
70
71#ifndef DEBUG
72# ifdef E1K_REL_STATS
73# undef STAM_COUNTER_INC
74# undef STAM_PROFILE_ADV_START
75# undef STAM_PROFILE_ADV_STOP
76# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
77# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
78# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
79# endif
80# ifdef E1K_REL_DEBUG
81# define DEBUG
82# define E1kLog(a) LogRel(a)
83# define E1kLog2(a) LogRel(a)
84# define E1kLog3(a) LogRel(a)
85//# define E1kLog3(a) do {} while (0)
86# else
87# define E1kLog(a) do {} while (0)
88# define E1kLog2(a) do {} while (0)
89# define E1kLog3(a) do {} while (0)
90# endif
91#else
92# define E1kLog(a) Log(a)
93# define E1kLog2(a) Log2(a)
94# define E1kLog3(a) Log3(a)
95//# define E1kLog(a) do {} while (0)
96//# define E1kLog2(a) do {} while (0)
97//# define E1kLog3(a) do {} while (0)
98#endif
99
100//#undef DEBUG
101
102#define INSTANCE(pState) pState->szInstance
103#define STATE_TO_DEVINS(pState) (((E1KSTATE *)pState)->CTX_SUFF(pDevIns))
104#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
105
106#define E1K_INC_CNT32(cnt) \
107do { \
108 if (cnt < UINT32_MAX) \
109 cnt++; \
110} while (0)
111
112#define E1K_ADD_CNT64(cntLo, cntHi, val) \
113do { \
114 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
115 uint64_t tmp = u64Cnt; \
116 u64Cnt += val; \
117 if (tmp > u64Cnt ) \
118 u64Cnt = UINT64_MAX; \
119 cntLo = (uint32_t)u64Cnt; \
120 cntHi = (uint32_t)(u64Cnt >> 32); \
121} while (0)
122
123#ifdef E1K_INT_STATS
124# define E1K_INC_ISTAT_CNT(cnt) ++cnt
125#else /* E1K_INT_STATS */
126# define E1K_INC_ISTAT_CNT(cnt)
127#endif /* E1K_INT_STATS */
128
129
130/*****************************************************************************/
131
132typedef uint32_t E1KCHIP;
133#define E1K_CHIP_82540EM 0
134#define E1K_CHIP_82543GC 1
135#define E1K_CHIP_82545EM 2
136
137struct E1kChips
138{
139 uint16_t uPCIVendorId;
140 uint16_t uPCIDeviceId;
141 uint16_t uPCISubsystemVendorId;
142 uint16_t uPCISubsystemId;
143 const char *pcszName;
144} g_Chips[] =
145{
146 /* Vendor Device SSVendor SubSys Name */
147 { 0x8086,
148 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
149#ifdef E1K_WITH_MSI
150 0x105E,
151#else
152 0x100E,
153#endif
154 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
155 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
156 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
157};
158
159
160/* The size of register area mapped to I/O space */
161#define E1K_IOPORT_SIZE 0x8
162/* The size of memory-mapped register area */
163#define E1K_MM_SIZE 0x20000
164
165#define E1K_MAX_TX_PKT_SIZE 16288
166#define E1K_MAX_RX_PKT_SIZE 16384
167
168/*****************************************************************************/
169
170/** Gets the specfieid bits from the register. */
171#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
172#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
173#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
174#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
175#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
176
177#define CTRL_SLU 0x00000040
178#define CTRL_MDIO 0x00100000
179#define CTRL_MDC 0x00200000
180#define CTRL_MDIO_DIR 0x01000000
181#define CTRL_MDC_DIR 0x02000000
182#define CTRL_RESET 0x04000000
183#define CTRL_VME 0x40000000
184
185#define STATUS_LU 0x00000002
186
187#define EECD_EE_WIRES 0x0F
188#define EECD_EE_REQ 0x40
189#define EECD_EE_GNT 0x80
190
191#define EERD_START 0x00000001
192#define EERD_DONE 0x00000010
193#define EERD_DATA_MASK 0xFFFF0000
194#define EERD_DATA_SHIFT 16
195#define EERD_ADDR_MASK 0x0000FF00
196#define EERD_ADDR_SHIFT 8
197
198#define MDIC_DATA_MASK 0x0000FFFF
199#define MDIC_DATA_SHIFT 0
200#define MDIC_REG_MASK 0x001F0000
201#define MDIC_REG_SHIFT 16
202#define MDIC_PHY_MASK 0x03E00000
203#define MDIC_PHY_SHIFT 21
204#define MDIC_OP_WRITE 0x04000000
205#define MDIC_OP_READ 0x08000000
206#define MDIC_READY 0x10000000
207#define MDIC_INT_EN 0x20000000
208#define MDIC_ERROR 0x40000000
209
210#define TCTL_EN 0x00000002
211#define TCTL_PSP 0x00000008
212
213#define RCTL_EN 0x00000002
214#define RCTL_UPE 0x00000008
215#define RCTL_MPE 0x00000010
216#define RCTL_LPE 0x00000020
217#define RCTL_LBM_MASK 0x000000C0
218#define RCTL_LBM_SHIFT 6
219#define RCTL_RDMTS_MASK 0x00000300
220#define RCTL_RDMTS_SHIFT 8
221#define RCTL_LBM_TCVR 3 /**< PHY or external SerDes loopback. */
222#define RCTL_MO_MASK 0x00003000
223#define RCTL_MO_SHIFT 12
224#define RCTL_BAM 0x00008000
225#define RCTL_BSIZE_MASK 0x00030000
226#define RCTL_BSIZE_SHIFT 16
227#define RCTL_VFE 0x00040000
228#define RCTL_CFIEN 0x00080000
229#define RCTL_CFI 0x00100000
230#define RCTL_BSEX 0x02000000
231#define RCTL_SECRC 0x04000000
232
233#define ICR_TXDW 0x00000001
234#define ICR_TXQE 0x00000002
235#define ICR_LSC 0x00000004
236#define ICR_RXDMT0 0x00000010
237#define ICR_RXT0 0x00000080
238#define ICR_TXD_LOW 0x00008000
239#define RDTR_FPD 0x80000000
240
241#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
242typedef struct
243{
244 unsigned rxa : 7;
245 unsigned rxa_r : 9;
246 unsigned txa : 16;
247} PBAST;
248AssertCompileSize(PBAST, 4);
249
250#define TXDCTL_WTHRESH_MASK 0x003F0000
251#define TXDCTL_WTHRESH_SHIFT 16
252#define TXDCTL_LWTHRESH_MASK 0xFE000000
253#define TXDCTL_LWTHRESH_SHIFT 25
254
255#define RXCSUM_PCSS_MASK 0x000000FF
256#define RXCSUM_PCSS_SHIFT 0
257
258/* Register access macros ****************************************************/
259#define CTRL pState->auRegs[CTRL_IDX]
260#define STATUS pState->auRegs[STATUS_IDX]
261#define EECD pState->auRegs[EECD_IDX]
262#define EERD pState->auRegs[EERD_IDX]
263#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
264#define FLA pState->auRegs[FLA_IDX]
265#define MDIC pState->auRegs[MDIC_IDX]
266#define FCAL pState->auRegs[FCAL_IDX]
267#define FCAH pState->auRegs[FCAH_IDX]
268#define FCT pState->auRegs[FCT_IDX]
269#define VET pState->auRegs[VET_IDX]
270#define ICR pState->auRegs[ICR_IDX]
271#define ITR pState->auRegs[ITR_IDX]
272#define ICS pState->auRegs[ICS_IDX]
273#define IMS pState->auRegs[IMS_IDX]
274#define IMC pState->auRegs[IMC_IDX]
275#define RCTL pState->auRegs[RCTL_IDX]
276#define FCTTV pState->auRegs[FCTTV_IDX]
277#define TXCW pState->auRegs[TXCW_IDX]
278#define RXCW pState->auRegs[RXCW_IDX]
279#define TCTL pState->auRegs[TCTL_IDX]
280#define TIPG pState->auRegs[TIPG_IDX]
281#define AIFS pState->auRegs[AIFS_IDX]
282#define LEDCTL pState->auRegs[LEDCTL_IDX]
283#define PBA pState->auRegs[PBA_IDX]
284#define FCRTL pState->auRegs[FCRTL_IDX]
285#define FCRTH pState->auRegs[FCRTH_IDX]
286#define RDFH pState->auRegs[RDFH_IDX]
287#define RDFT pState->auRegs[RDFT_IDX]
288#define RDFHS pState->auRegs[RDFHS_IDX]
289#define RDFTS pState->auRegs[RDFTS_IDX]
290#define RDFPC pState->auRegs[RDFPC_IDX]
291#define RDBAL pState->auRegs[RDBAL_IDX]
292#define RDBAH pState->auRegs[RDBAH_IDX]
293#define RDLEN pState->auRegs[RDLEN_IDX]
294#define RDH pState->auRegs[RDH_IDX]
295#define RDT pState->auRegs[RDT_IDX]
296#define RDTR pState->auRegs[RDTR_IDX]
297#define RXDCTL pState->auRegs[RXDCTL_IDX]
298#define RADV pState->auRegs[RADV_IDX]
299#define RSRPD pState->auRegs[RSRPD_IDX]
300#define TXDMAC pState->auRegs[TXDMAC_IDX]
301#define TDFH pState->auRegs[TDFH_IDX]
302#define TDFT pState->auRegs[TDFT_IDX]
303#define TDFHS pState->auRegs[TDFHS_IDX]
304#define TDFTS pState->auRegs[TDFTS_IDX]
305#define TDFPC pState->auRegs[TDFPC_IDX]
306#define TDBAL pState->auRegs[TDBAL_IDX]
307#define TDBAH pState->auRegs[TDBAH_IDX]
308#define TDLEN pState->auRegs[TDLEN_IDX]
309#define TDH pState->auRegs[TDH_IDX]
310#define TDT pState->auRegs[TDT_IDX]
311#define TIDV pState->auRegs[TIDV_IDX]
312#define TXDCTL pState->auRegs[TXDCTL_IDX]
313#define TADV pState->auRegs[TADV_IDX]
314#define TSPMT pState->auRegs[TSPMT_IDX]
315#define CRCERRS pState->auRegs[CRCERRS_IDX]
316#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
317#define SYMERRS pState->auRegs[SYMERRS_IDX]
318#define RXERRC pState->auRegs[RXERRC_IDX]
319#define MPC pState->auRegs[MPC_IDX]
320#define SCC pState->auRegs[SCC_IDX]
321#define ECOL pState->auRegs[ECOL_IDX]
322#define MCC pState->auRegs[MCC_IDX]
323#define LATECOL pState->auRegs[LATECOL_IDX]
324#define COLC pState->auRegs[COLC_IDX]
325#define DC pState->auRegs[DC_IDX]
326#define TNCRS pState->auRegs[TNCRS_IDX]
327#define SEC pState->auRegs[SEC_IDX]
328#define CEXTERR pState->auRegs[CEXTERR_IDX]
329#define RLEC pState->auRegs[RLEC_IDX]
330#define XONRXC pState->auRegs[XONRXC_IDX]
331#define XONTXC pState->auRegs[XONTXC_IDX]
332#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
333#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
334#define FCRUC pState->auRegs[FCRUC_IDX]
335#define PRC64 pState->auRegs[PRC64_IDX]
336#define PRC127 pState->auRegs[PRC127_IDX]
337#define PRC255 pState->auRegs[PRC255_IDX]
338#define PRC511 pState->auRegs[PRC511_IDX]
339#define PRC1023 pState->auRegs[PRC1023_IDX]
340#define PRC1522 pState->auRegs[PRC1522_IDX]
341#define GPRC pState->auRegs[GPRC_IDX]
342#define BPRC pState->auRegs[BPRC_IDX]
343#define MPRC pState->auRegs[MPRC_IDX]
344#define GPTC pState->auRegs[GPTC_IDX]
345#define GORCL pState->auRegs[GORCL_IDX]
346#define GORCH pState->auRegs[GORCH_IDX]
347#define GOTCL pState->auRegs[GOTCL_IDX]
348#define GOTCH pState->auRegs[GOTCH_IDX]
349#define RNBC pState->auRegs[RNBC_IDX]
350#define RUC pState->auRegs[RUC_IDX]
351#define RFC pState->auRegs[RFC_IDX]
352#define ROC pState->auRegs[ROC_IDX]
353#define RJC pState->auRegs[RJC_IDX]
354#define MGTPRC pState->auRegs[MGTPRC_IDX]
355#define MGTPDC pState->auRegs[MGTPDC_IDX]
356#define MGTPTC pState->auRegs[MGTPTC_IDX]
357#define TORL pState->auRegs[TORL_IDX]
358#define TORH pState->auRegs[TORH_IDX]
359#define TOTL pState->auRegs[TOTL_IDX]
360#define TOTH pState->auRegs[TOTH_IDX]
361#define TPR pState->auRegs[TPR_IDX]
362#define TPT pState->auRegs[TPT_IDX]
363#define PTC64 pState->auRegs[PTC64_IDX]
364#define PTC127 pState->auRegs[PTC127_IDX]
365#define PTC255 pState->auRegs[PTC255_IDX]
366#define PTC511 pState->auRegs[PTC511_IDX]
367#define PTC1023 pState->auRegs[PTC1023_IDX]
368#define PTC1522 pState->auRegs[PTC1522_IDX]
369#define MPTC pState->auRegs[MPTC_IDX]
370#define BPTC pState->auRegs[BPTC_IDX]
371#define TSCTC pState->auRegs[TSCTC_IDX]
372#define TSCTFC pState->auRegs[TSCTFC_IDX]
373#define RXCSUM pState->auRegs[RXCSUM_IDX]
374#define WUC pState->auRegs[WUC_IDX]
375#define WUFC pState->auRegs[WUFC_IDX]
376#define WUS pState->auRegs[WUS_IDX]
377#define MANC pState->auRegs[MANC_IDX]
378#define IPAV pState->auRegs[IPAV_IDX]
379#define WUPL pState->auRegs[WUPL_IDX]
380
381/**
382 * Indices of memory-mapped registers in register table
383 */
384typedef enum
385{
386 CTRL_IDX,
387 STATUS_IDX,
388 EECD_IDX,
389 EERD_IDX,
390 CTRL_EXT_IDX,
391 FLA_IDX,
392 MDIC_IDX,
393 FCAL_IDX,
394 FCAH_IDX,
395 FCT_IDX,
396 VET_IDX,
397 ICR_IDX,
398 ITR_IDX,
399 ICS_IDX,
400 IMS_IDX,
401 IMC_IDX,
402 RCTL_IDX,
403 FCTTV_IDX,
404 TXCW_IDX,
405 RXCW_IDX,
406 TCTL_IDX,
407 TIPG_IDX,
408 AIFS_IDX,
409 LEDCTL_IDX,
410 PBA_IDX,
411 FCRTL_IDX,
412 FCRTH_IDX,
413 RDFH_IDX,
414 RDFT_IDX,
415 RDFHS_IDX,
416 RDFTS_IDX,
417 RDFPC_IDX,
418 RDBAL_IDX,
419 RDBAH_IDX,
420 RDLEN_IDX,
421 RDH_IDX,
422 RDT_IDX,
423 RDTR_IDX,
424 RXDCTL_IDX,
425 RADV_IDX,
426 RSRPD_IDX,
427 TXDMAC_IDX,
428 TDFH_IDX,
429 TDFT_IDX,
430 TDFHS_IDX,
431 TDFTS_IDX,
432 TDFPC_IDX,
433 TDBAL_IDX,
434 TDBAH_IDX,
435 TDLEN_IDX,
436 TDH_IDX,
437 TDT_IDX,
438 TIDV_IDX,
439 TXDCTL_IDX,
440 TADV_IDX,
441 TSPMT_IDX,
442 CRCERRS_IDX,
443 ALGNERRC_IDX,
444 SYMERRS_IDX,
445 RXERRC_IDX,
446 MPC_IDX,
447 SCC_IDX,
448 ECOL_IDX,
449 MCC_IDX,
450 LATECOL_IDX,
451 COLC_IDX,
452 DC_IDX,
453 TNCRS_IDX,
454 SEC_IDX,
455 CEXTERR_IDX,
456 RLEC_IDX,
457 XONRXC_IDX,
458 XONTXC_IDX,
459 XOFFRXC_IDX,
460 XOFFTXC_IDX,
461 FCRUC_IDX,
462 PRC64_IDX,
463 PRC127_IDX,
464 PRC255_IDX,
465 PRC511_IDX,
466 PRC1023_IDX,
467 PRC1522_IDX,
468 GPRC_IDX,
469 BPRC_IDX,
470 MPRC_IDX,
471 GPTC_IDX,
472 GORCL_IDX,
473 GORCH_IDX,
474 GOTCL_IDX,
475 GOTCH_IDX,
476 RNBC_IDX,
477 RUC_IDX,
478 RFC_IDX,
479 ROC_IDX,
480 RJC_IDX,
481 MGTPRC_IDX,
482 MGTPDC_IDX,
483 MGTPTC_IDX,
484 TORL_IDX,
485 TORH_IDX,
486 TOTL_IDX,
487 TOTH_IDX,
488 TPR_IDX,
489 TPT_IDX,
490 PTC64_IDX,
491 PTC127_IDX,
492 PTC255_IDX,
493 PTC511_IDX,
494 PTC1023_IDX,
495 PTC1522_IDX,
496 MPTC_IDX,
497 BPTC_IDX,
498 TSCTC_IDX,
499 TSCTFC_IDX,
500 RXCSUM_IDX,
501 WUC_IDX,
502 WUFC_IDX,
503 WUS_IDX,
504 MANC_IDX,
505 IPAV_IDX,
506 WUPL_IDX,
507 MTA_IDX,
508 RA_IDX,
509 VFTA_IDX,
510 IP4AT_IDX,
511 IP6AT_IDX,
512 WUPM_IDX,
513 FFLT_IDX,
514 FFMT_IDX,
515 FFVT_IDX,
516 PBM_IDX,
517 RA_82542_IDX,
518 MTA_82542_IDX,
519 VFTA_82542_IDX,
520 E1K_NUM_OF_REGS
521} E1kRegIndex;
522
523#define E1K_NUM_OF_32BIT_REGS MTA_IDX
524
525
526/**
527 * Define E1000-specific EEPROM layout.
528 */
529class E1kEEPROM
530{
531 public:
532 EEPROM93C46 eeprom;
533
534#ifdef IN_RING3
535 /**
536 * Initialize EEPROM content.
537 *
538 * @param macAddr MAC address of E1000.
539 */
540 void init(RTMAC &macAddr)
541 {
542 eeprom.init();
543 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
544 eeprom.m_au16Data[0x04] = 0xFFFF;
545 /*
546 * bit 3 - full support for power management
547 * bit 10 - full duplex
548 */
549 eeprom.m_au16Data[0x0A] = 0x4408;
550 eeprom.m_au16Data[0x0B] = 0x001E;
551 eeprom.m_au16Data[0x0C] = 0x8086;
552 eeprom.m_au16Data[0x0D] = 0x100E;
553 eeprom.m_au16Data[0x0E] = 0x8086;
554 eeprom.m_au16Data[0x0F] = 0x3040;
555 eeprom.m_au16Data[0x21] = 0x7061;
556 eeprom.m_au16Data[0x22] = 0x280C;
557 eeprom.m_au16Data[0x23] = 0x00C8;
558 eeprom.m_au16Data[0x24] = 0x00C8;
559 eeprom.m_au16Data[0x2F] = 0x0602;
560 updateChecksum();
561 };
562
563 /**
564 * Compute the checksum as required by E1000 and store it
565 * in the last word.
566 */
567 void updateChecksum()
568 {
569 uint16_t u16Checksum = 0;
570
571 for (int i = 0; i < eeprom.SIZE-1; i++)
572 u16Checksum += eeprom.m_au16Data[i];
573 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
574 };
575
576 /**
577 * First 6 bytes of EEPROM contain MAC address.
578 *
579 * @returns MAC address of E1000.
580 */
581 void getMac(PRTMAC pMac)
582 {
583 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
584 };
585
586 uint32_t read()
587 {
588 return eeprom.read();
589 }
590
591 void write(uint32_t u32Wires)
592 {
593 eeprom.write(u32Wires);
594 }
595
596 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
597 {
598 return eeprom.readWord(u32Addr, pu16Value);
599 }
600
601 int load(PSSMHANDLE pSSM)
602 {
603 return eeprom.load(pSSM);
604 }
605
606 void save(PSSMHANDLE pSSM)
607 {
608 eeprom.save(pSSM);
609 }
610#endif /* IN_RING3 */
611};
612
613
614#define E1K_SPEC_VLAN(s) (s & 0xFFF)
615#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
616#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
617
618struct E1kRxDStatus
619{
620 /** @name Descriptor Status field (3.2.3.1)
621 * @{ */
622 unsigned fDD : 1; /**< Descriptor Done. */
623 unsigned fEOP : 1; /**< End of packet. */
624 unsigned fIXSM : 1; /**< Ignore checksum indication. */
625 unsigned fVP : 1; /**< VLAN, matches VET. */
626 unsigned : 1;
627 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
628 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
629 unsigned fPIF : 1; /**< Passed in-exact filter */
630 /** @} */
631 /** @name Descriptor Errors field (3.2.3.2)
632 * (Only valid when fEOP and fDD are set.)
633 * @{ */
634 unsigned fCE : 1; /**< CRC or alignment error. */
635 unsigned : 4; /**< Reserved, varies with different models... */
636 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
637 unsigned fIPE : 1; /**< IP Checksum error. */
638 unsigned fRXE : 1; /**< RX Data error. */
639 /** @} */
640 /** @name Descriptor Special field (3.2.3.3)
641 * @{ */
642 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
643 /** @} */
644};
645typedef struct E1kRxDStatus E1KRXDST;
646
647struct E1kRxDesc_st
648{
649 uint64_t u64BufAddr; /**< Address of data buffer */
650 uint16_t u16Length; /**< Length of data in buffer */
651 uint16_t u16Checksum; /**< Packet checksum */
652 E1KRXDST status;
653};
654typedef struct E1kRxDesc_st E1KRXDESC;
655AssertCompileSize(E1KRXDESC, 16);
656
657#define E1K_DTYP_LEGACY -1
658#define E1K_DTYP_CONTEXT 0
659#define E1K_DTYP_DATA 1
660
661struct E1kTDLegacy
662{
663 uint64_t u64BufAddr; /**< Address of data buffer */
664 struct TDLCmd_st
665 {
666 unsigned u16Length : 16;
667 unsigned u8CSO : 8;
668 /* CMD field : 8 */
669 unsigned fEOP : 1;
670 unsigned fIFCS : 1;
671 unsigned fIC : 1;
672 unsigned fRS : 1;
673 unsigned fRSV : 1;
674 unsigned fDEXT : 1;
675 unsigned fVLE : 1;
676 unsigned fIDE : 1;
677 } cmd;
678 struct TDLDw3_st
679 {
680 /* STA field */
681 unsigned fDD : 1;
682 unsigned fEC : 1;
683 unsigned fLC : 1;
684 unsigned fTURSV : 1;
685 /* RSV field */
686 unsigned u4RSV : 4;
687 /* CSS field */
688 unsigned u8CSS : 8;
689 /* Special field*/
690 unsigned u16Special: 16;
691 } dw3;
692};
693
694/**
695 * TCP/IP Context Transmit Descriptor, section 3.3.6.
696 */
697struct E1kTDContext
698{
699 struct CheckSum_st
700 {
701 /** TSE: Header start. !TSE: Checksum start. */
702 unsigned u8CSS : 8;
703 /** Checksum offset - where to store it. */
704 unsigned u8CSO : 8;
705 /** Checksum ending (inclusive) offset, 0 = end of packet. */
706 unsigned u16CSE : 16;
707 } ip;
708 struct CheckSum_st tu;
709 struct TDCDw2_st
710 {
711 /** TSE: The total number of payload bytes for this context. Sans header. */
712 unsigned u20PAYLEN : 20;
713 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
714 unsigned u4DTYP : 4;
715 /** TUCMD field, 8 bits
716 * @{ */
717 /** TSE: TCP (set) or UDP (clear). */
718 unsigned fTCP : 1;
719 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
720 * the IP header. Does not affect the checksumming.
721 * @remarks 82544GC/EI interprets a cleared field differently. */
722 unsigned fIP : 1;
723 /** TSE: TCP segmentation enable. When clear the context describes */
724 unsigned fTSE : 1;
725 /** Report status (only applies to dw3.fDD for here). */
726 unsigned fRS : 1;
727 /** Reserved, MBZ. */
728 unsigned fRSV1 : 1;
729 /** Descriptor extension, must be set for this descriptor type. */
730 unsigned fDEXT : 1;
731 /** Reserved, MBZ. */
732 unsigned fRSV2 : 1;
733 /** Interrupt delay enable. */
734 unsigned fIDE : 1;
735 /** @} */
736 } dw2;
737 struct TDCDw3_st
738 {
739 /** Descriptor Done. */
740 unsigned fDD : 1;
741 /** Reserved, MBZ. */
742 unsigned u7RSV : 7;
743 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
744 unsigned u8HDRLEN : 8;
745 /** TSO: Maximum segment size. */
746 unsigned u16MSS : 16;
747 } dw3;
748};
749typedef struct E1kTDContext E1KTXCTX;
750
751/**
752 * TCP/IP Data Transmit Descriptor, section 3.3.7.
753 */
754struct E1kTDData
755{
756 uint64_t u64BufAddr; /**< Address of data buffer */
757 struct TDDCmd_st
758 {
759 /** The total length of data pointed to by this descriptor. */
760 unsigned u20DTALEN : 20;
761 /** The descriptor type - E1K_DTYP_DATA (1). */
762 unsigned u4DTYP : 4;
763 /** @name DCMD field, 8 bits (3.3.7.1).
764 * @{ */
765 /** End of packet. Note TSCTFC update. */
766 unsigned fEOP : 1;
767 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
768 unsigned fIFCS : 1;
769 /** Use the TSE context when set and the normal when clear. */
770 unsigned fTSE : 1;
771 /** Report status (dw3.STA). */
772 unsigned fRS : 1;
773 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
774 unsigned fRSV : 1;
775 /** Descriptor extension, must be set for this descriptor type. */
776 unsigned fDEXT : 1;
777 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
778 * Insert dw3.SPECIAL after ethernet header. */
779 unsigned fVLE : 1;
780 /** Interrupt delay enable. */
781 unsigned fIDE : 1;
782 /** @} */
783 } cmd;
784 struct TDDDw3_st
785 {
786 /** @name STA field (3.3.7.2)
787 * @{ */
788 unsigned fDD : 1; /**< Descriptor done. */
789 unsigned fEC : 1; /**< Excess collision. */
790 unsigned fLC : 1; /**< Late collision. */
791 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
792 unsigned fTURSV : 1;
793 /** @} */
794 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
795 /** @name POPTS (Packet Option) field (3.3.7.3)
796 * @{ */
797 unsigned fIXSM : 1; /**< Insert IP checksum. */
798 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
799 unsigned u6RSV : 6; /**< Reserved, MBZ. */
800 /** @} */
801 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
802 * Requires fEOP, fVLE and CTRL.VME to be set.
803 * @{ */
804 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
805 /** @} */
806 } dw3;
807};
808typedef struct E1kTDData E1KTXDAT;
809
810union E1kTxDesc
811{
812 struct E1kTDLegacy legacy;
813 struct E1kTDContext context;
814 struct E1kTDData data;
815};
816typedef union E1kTxDesc E1KTXDESC;
817AssertCompileSize(E1KTXDESC, 16);
818
819#define RA_CTL_AS 0x0003
820#define RA_CTL_AV 0x8000
821
822union E1kRecAddr
823{
824 uint32_t au32[32];
825 struct RAArray
826 {
827 uint8_t addr[6];
828 uint16_t ctl;
829 } array[16];
830};
831typedef struct E1kRecAddr::RAArray E1KRAELEM;
832typedef union E1kRecAddr E1KRA;
833AssertCompileSize(E1KRA, 8*16);
834
835#define E1K_IP_RF 0x8000 /* reserved fragment flag */
836#define E1K_IP_DF 0x4000 /* dont fragment flag */
837#define E1K_IP_MF 0x2000 /* more fragments flag */
838#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
839
840/** @todo use+extend RTNETIPV4 */
841struct E1kIpHeader
842{
843 /* type of service / version / header length */
844 uint16_t tos_ver_hl;
845 /* total length */
846 uint16_t total_len;
847 /* identification */
848 uint16_t ident;
849 /* fragment offset field */
850 uint16_t offset;
851 /* time to live / protocol*/
852 uint16_t ttl_proto;
853 /* checksum */
854 uint16_t chksum;
855 /* source IP address */
856 uint32_t src;
857 /* destination IP address */
858 uint32_t dest;
859};
860AssertCompileSize(struct E1kIpHeader, 20);
861
862#define E1K_TCP_FIN 0x01U
863#define E1K_TCP_SYN 0x02U
864#define E1K_TCP_RST 0x04U
865#define E1K_TCP_PSH 0x08U
866#define E1K_TCP_ACK 0x10U
867#define E1K_TCP_URG 0x20U
868#define E1K_TCP_ECE 0x40U
869#define E1K_TCP_CWR 0x80U
870
871#define E1K_TCP_FLAGS 0x3fU
872
873/** @todo use+extend RTNETTCP */
874struct E1kTcpHeader
875{
876 uint16_t src;
877 uint16_t dest;
878 uint32_t seqno;
879 uint32_t ackno;
880 uint16_t hdrlen_flags;
881 uint16_t wnd;
882 uint16_t chksum;
883 uint16_t urgp;
884};
885AssertCompileSize(struct E1kTcpHeader, 20);
886
887
888/** The current Saved state version. */
889#define E1K_SAVEDSTATE_VERSION 3
890/** Saved state version for VirtualBox 4.1 and earlier.
891 * These did not include VLAN tag fields. */
892#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
893/** Saved state version for VirtualBox 3.0 and earlier.
894 * This did not include the configuration part nor the E1kEEPROM. */
895#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
896
897/**
898 * Device state structure. Holds the current state of device.
899 *
900 * @implements PDMINETWORKDOWN
901 * @implements PDMINETWORKCONFIG
902 * @implements PDMILEDPORTS
903 */
904struct E1kState_st
905{
906 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
907 PDMIBASE IBase;
908 PDMINETWORKDOWN INetworkDown;
909 PDMINETWORKCONFIG INetworkConfig;
910 PDMILEDPORTS ILeds; /**< LED interface */
911 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
912 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
913
914 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
915 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
916 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
917 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
918 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
919 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
920 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
921 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
922 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
923 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
924 /** The scatter / gather buffer used for the current outgoing packet - R3. */
925 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
926
927 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
928 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
929 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
930 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
931 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
932 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
933 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
934 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
935 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
936 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
937 /** The scatter / gather buffer used for the current outgoing packet - R0. */
938 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
939
940 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
941 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
942 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
943 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
944 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
945 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
946 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
947 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
948 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
949 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
950 /** The scatter / gather buffer used for the current outgoing packet - RC. */
951 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
952 RTRCPTR RCPtrAlignment;
953
954#if HC_ARCH_BITS == 32
955 uint32_t Alignment1;
956#endif
957 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
958#ifndef E1K_GLOBAL_MUTEX
959 PDMCRITSECT csRx; /**< RX Critical section. */
960// PDMCRITSECT csTx; /**< TX Critical section. */
961#endif
962 /** Base address of memory-mapped registers. */
963 RTGCPHYS addrMMReg;
964 /** MAC address obtained from the configuration. */
965 RTMAC macConfigured;
966 /** Base port of I/O space region. */
967 RTIOPORT addrIOPort;
968 /** EMT: */
969 PCIDEVICE pciDevice;
970 /** EMT: Last time the interrupt was acknowledged. */
971 uint64_t u64AckedAt;
972 /** All: Used for eliminating spurious interrupts. */
973 bool fIntRaised;
974 /** EMT: false if the cable is disconnected by the GUI. */
975 bool fCableConnected;
976 /** EMT: */
977 bool fR0Enabled;
978 /** EMT: */
979 bool fGCEnabled;
980
981 /** All: Device register storage. */
982 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
983 /** TX/RX: Status LED. */
984 PDMLED led;
985 /** TX/RX: Number of packet being sent/received to show in debug log. */
986 uint32_t u32PktNo;
987
988 /** EMT: Offset of the register to be read via IO. */
989 uint32_t uSelectedReg;
990 /** EMT: Multicast Table Array. */
991 uint32_t auMTA[128];
992 /** EMT: Receive Address registers. */
993 E1KRA aRecAddr;
994 /** EMT: VLAN filter table array. */
995 uint32_t auVFTA[128];
996 /** EMT: Receive buffer size. */
997 uint16_t u16RxBSize;
998 /** EMT: Locked state -- no state alteration possible. */
999 bool fLocked;
1000 /** EMT: */
1001 bool fDelayInts;
1002 /** All: */
1003 bool fIntMaskUsed;
1004
1005 /** N/A: */
1006 bool volatile fMaybeOutOfSpace;
1007 /** EMT: Gets signalled when more RX descriptors become available. */
1008 RTSEMEVENT hEventMoreRxDescAvail;
1009
1010 /** TX: Context used for TCP segmentation packets. */
1011 E1KTXCTX contextTSE;
1012 /** TX: Context used for ordinary packets. */
1013 E1KTXCTX contextNormal;
1014 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1015 * applicable to the current TSE mode. */
1016 PDMNETWORKGSO GsoCtx;
1017 /** Scratch space for holding the loopback / fallback scatter / gather
1018 * descriptor. */
1019 union
1020 {
1021 PDMSCATTERGATHER Sg;
1022 uint8_t padding[8 * sizeof(RTUINTPTR)];
1023 } uTxFallback;
1024 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1025 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1026 /** TX: Number of bytes assembled in TX packet buffer. */
1027 uint16_t u16TxPktLen;
1028 /** TX: IP checksum has to be inserted if true. */
1029 bool fIPcsum;
1030 /** TX: TCP/UDP checksum has to be inserted if true. */
1031 bool fTCPcsum;
1032 /** TX: VLAN tag has to be inserted if true. */
1033 bool fVTag;
1034 /** TX: TCI part of VLAN tag to be inserted. */
1035 uint16_t u16VTagTCI;
1036 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1037 uint32_t u32PayRemain;
1038 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1039 uint16_t u16HdrRemain;
1040 /** TX TSE fallback: Flags from template header. */
1041 uint16_t u16SavedFlags;
1042 /** TX TSE fallback: Partial checksum from template header. */
1043 uint32_t u32SavedCsum;
1044 /** ?: Emulated controller type. */
1045 E1KCHIP eChip;
1046
1047 /** EMT: EEPROM emulation */
1048 E1kEEPROM eeprom;
1049 /** EMT: Physical interface emulation. */
1050 PHY phy;
1051
1052#if 0
1053 /** Alignment padding. */
1054 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1055#endif
1056
1057 STAMCOUNTER StatReceiveBytes;
1058 STAMCOUNTER StatTransmitBytes;
1059#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
1060 STAMPROFILEADV StatMMIOReadRZ;
1061 STAMPROFILEADV StatMMIOReadR3;
1062 STAMPROFILEADV StatMMIOWriteRZ;
1063 STAMPROFILEADV StatMMIOWriteR3;
1064 STAMPROFILEADV StatEEPROMRead;
1065 STAMPROFILEADV StatEEPROMWrite;
1066 STAMPROFILEADV StatIOReadRZ;
1067 STAMPROFILEADV StatIOReadR3;
1068 STAMPROFILEADV StatIOWriteRZ;
1069 STAMPROFILEADV StatIOWriteR3;
1070 STAMPROFILEADV StatLateIntTimer;
1071 STAMCOUNTER StatLateInts;
1072 STAMCOUNTER StatIntsRaised;
1073 STAMCOUNTER StatIntsPrevented;
1074 STAMPROFILEADV StatReceive;
1075 STAMPROFILEADV StatReceiveFilter;
1076 STAMPROFILEADV StatReceiveStore;
1077 STAMPROFILEADV StatTransmitRZ;
1078 STAMPROFILEADV StatTransmitR3;
1079 STAMPROFILE StatTransmitSendRZ;
1080 STAMPROFILE StatTransmitSendR3;
1081 STAMPROFILE StatRxOverflow;
1082 STAMCOUNTER StatRxOverflowWakeup;
1083 STAMCOUNTER StatTxDescCtxNormal;
1084 STAMCOUNTER StatTxDescCtxTSE;
1085 STAMCOUNTER StatTxDescLegacy;
1086 STAMCOUNTER StatTxDescData;
1087 STAMCOUNTER StatTxDescTSEData;
1088 STAMCOUNTER StatTxPathFallback;
1089 STAMCOUNTER StatTxPathGSO;
1090 STAMCOUNTER StatTxPathRegular;
1091 STAMCOUNTER StatPHYAccesses;
1092
1093#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
1094
1095#ifdef E1K_INT_STATS
1096 /* Internal stats */
1097 uint32_t uStatInt;
1098 uint32_t uStatIntTry;
1099 int32_t uStatIntLower;
1100 uint32_t uStatIntDly;
1101 int32_t iStatIntLost;
1102 int32_t iStatIntLostOne;
1103 uint32_t uStatDisDly;
1104 uint32_t uStatIntSkip;
1105 uint32_t uStatIntLate;
1106 uint32_t uStatIntMasked;
1107 uint32_t uStatIntEarly;
1108 uint32_t uStatIntRx;
1109 uint32_t uStatIntTx;
1110 uint32_t uStatIntICS;
1111 uint32_t uStatIntRDTR;
1112 uint32_t uStatIntRXDMT0;
1113 uint32_t uStatIntTXQE;
1114 uint32_t uStatTxNoRS;
1115 uint32_t uStatTxIDE;
1116 uint32_t uStatTAD;
1117 uint32_t uStatTID;
1118 uint32_t uStatRAD;
1119 uint32_t uStatRID;
1120 uint32_t uStatRxFrm;
1121 uint32_t uStatTxFrm;
1122 uint32_t uStatDescCtx;
1123 uint32_t uStatDescDat;
1124 uint32_t uStatDescLeg;
1125#endif /* E1K_INT_STATS */
1126};
1127typedef struct E1kState_st E1KSTATE;
1128
1129#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1130
1131/* Forward declarations ******************************************************/
1132static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread);
1133
1134static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1135static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1136static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1137static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1138static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1139#if 0 /* unused */
1140static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1141#endif
1142static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1143static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1144static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1145static int e1kRegWriteEERD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1146static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1147static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1148static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1149static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1150static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1151static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1152static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1153static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1154static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1155static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1156static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1157static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1158static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1159static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1160static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1161static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1162static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1163
1164/**
1165 * Register map table.
1166 *
1167 * Override fn_read and fn_write to get register-specific behavior.
1168 */
1169const static struct E1kRegMap_st
1170{
1171 /** Register offset in the register space. */
1172 uint32_t offset;
1173 /** Size in bytes. Registers of size > 4 are in fact tables. */
1174 uint32_t size;
1175 /** Readable bits. */
1176 uint32_t readable;
1177 /** Writable bits. */
1178 uint32_t writable;
1179 /** Read callback. */
1180 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1181 /** Write callback. */
1182 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1183 /** Abbreviated name. */
1184 const char *abbrev;
1185 /** Full name. */
1186 const char *name;
1187} s_e1kRegMap[E1K_NUM_OF_REGS] =
1188{
1189 /* offset size read mask write mask read callback write callback abbrev full name */
1190 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1191 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1192 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1193 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1194 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1195 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1196 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1197 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1198 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1199 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1200 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1201 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1202 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1203 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1204 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1205 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1206 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1207 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1208 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1209 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1210 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1211 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1212 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1213 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1214 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1215 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1216 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1217 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1218 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1219 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1220 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1221 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1222 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1223 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1224 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1225 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1226 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1227 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1228 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1229 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1230 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1231 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1232 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1233 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1234 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1235 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1236 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1237 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1238 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1239 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1240 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1241 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1242 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1243 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1244 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1245 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1246 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1247 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1248 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1249 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1250 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1251 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1252 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1253 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1254 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1255 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1256 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1257 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1258 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1259 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1260 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1261 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1262 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1263 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1264 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1265 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1266 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1267 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1268 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1269 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1270 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1271 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1272 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1273 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1274 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1275 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1276 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1277 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1278 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1279 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1280 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1281 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1282 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1283 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1284 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1285 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1286 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1287 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1288 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1289 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1290 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1291 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1292 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1293 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1294 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1295 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1296 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1297 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1298 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1299 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1300 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1301 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1302 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1303 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1304 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1305 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1306 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1307 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1308 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1309 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1310 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1311 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1312 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1313 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1314 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1315 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1316 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1317 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1318 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1319 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1320 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1321 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1322 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1323 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1324 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1325};
1326
1327#ifdef DEBUG
1328
1329/**
1330 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1331 *
1332 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1333 *
1334 * @returns The buffer.
1335 *
1336 * @param u32 The word to convert into string.
1337 * @param mask Selects which bytes to convert.
1338 * @param buf Where to put the result.
1339 */
1340static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1341{
1342 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1343 {
1344 if (mask & 0xF)
1345 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1346 else
1347 *ptr = '.';
1348 }
1349 buf[8] = 0;
1350 return buf;
1351}
1352
1353/**
1354 * Returns timer name for debug purposes.
1355 *
1356 * @returns The timer name.
1357 *
1358 * @param pState The device state structure.
1359 * @param pTimer The timer to get the name for.
1360 */
1361DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1362{
1363 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1364 return "TID";
1365 if (pTimer == pState->CTX_SUFF(pTADTimer))
1366 return "TAD";
1367 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1368 return "RID";
1369 if (pTimer == pState->CTX_SUFF(pRADTimer))
1370 return "RAD";
1371 if (pTimer == pState->CTX_SUFF(pIntTimer))
1372 return "Int";
1373 return "unknown";
1374}
1375
1376#endif /* DEBUG */
1377
1378/**
1379 * Arm a timer.
1380 *
1381 * @param pState Pointer to the device state structure.
1382 * @param pTimer Pointer to the timer.
1383 * @param uExpireIn Expiration interval in microseconds.
1384 */
1385DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1386{
1387 if (pState->fLocked)
1388 return;
1389
1390 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1391 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1392 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1393 TMTimerGet(pTimer));
1394}
1395
1396/**
1397 * Cancel a timer.
1398 *
1399 * @param pState Pointer to the device state structure.
1400 * @param pTimer Pointer to the timer.
1401 */
1402DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1403{
1404 E1kLog2(("%s Stopping %s timer...\n",
1405 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1406 int rc = TMTimerStop(pTimer);
1407 if (RT_FAILURE(rc))
1408 {
1409 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1410 INSTANCE(pState), rc));
1411 }
1412}
1413
1414#ifdef E1K_GLOBAL_MUTEX
1415
1416DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1417{
1418 return VINF_SUCCESS;
1419}
1420
1421DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1422{
1423}
1424
1425# define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1426# define e1kCsRxLeave(ps) do { } while (0)
1427
1428# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1429# define e1kCsTxLeave(ps) do { } while (0)
1430
1431
1432DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1433{
1434 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1435 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1436 {
1437 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1438 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1439 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1440 "%s Failed to enter critical section, rc=%Rrc\n",
1441 INSTANCE(pState), rc);
1442 }
1443 else
1444 {
1445 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1446 }
1447 return rc;
1448}
1449
1450DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1451{
1452 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1453 PDMCritSectLeave(&pState->cs);
1454}
1455
1456#else /* !E1K_GLOBAL_MUTEX */
1457# define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1458# define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1459
1460# define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1461# define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1462
1463# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1464# define e1kCsTxLeave(ps) do { } while (0)
1465//# define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1466//# define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1467
1468# if 0
1469DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1470{
1471 int rc = PDMCritSectEnter(pCs, iBusyRc);
1472 if (RT_FAILURE(rc))
1473 {
1474 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1475 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1476 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1477 "%s Failed to enter critical section, rc=%Rrc\n",
1478 INSTANCE(pState), rc);
1479 }
1480 else
1481 {
1482 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1483 }
1484 return RT_SUCCESS(rc);
1485}
1486
1487DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1488{
1489 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1490 PDMCritSectLeave(&pState->cs);
1491}
1492# endif
1493DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1494{
1495 return VINF_SUCCESS;
1496}
1497
1498DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1499{
1500}
1501
1502#endif /* !E1K_GLOBAL_MUTEX */
1503#ifdef IN_RING3
1504
1505/**
1506 * Wakeup the RX thread.
1507 */
1508static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1509{
1510 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1511 if ( pState->fMaybeOutOfSpace
1512 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1513 {
1514 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1515 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1516 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1517 }
1518}
1519
1520/**
1521 * Hardware reset. Revert all registers to initial values.
1522 *
1523 * @param pState The device state structure.
1524 */
1525static void e1kHardReset(E1KSTATE *pState)
1526{
1527 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1528 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1529 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1530#ifdef E1K_INIT_RA0
1531 memcpy(pState->aRecAddr.au32, pState->macConfigured.au8,
1532 sizeof(pState->macConfigured.au8));
1533 pState->aRecAddr.array[0].ctl |= RA_CTL_AV;
1534#endif /* E1K_INIT_RA0 */
1535 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1536 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1537 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1538 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1539 Assert(GET_BITS(RCTL, BSIZE) == 0);
1540 pState->u16RxBSize = 2048;
1541
1542 /* Reset promiscuous mode */
1543 if (pState->pDrvR3)
1544 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, false);
1545}
1546
1547#endif /* IN_RING3 */
1548
1549/**
1550 * Compute Internet checksum.
1551 *
1552 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1553 *
1554 * @param pState The device state structure.
1555 * @param cpPacket The packet.
1556 * @param cb The size of the packet.
1557 * @param cszText A string denoting direction of packet transfer.
1558 *
1559 * @return The 1's complement of the 1's complement sum.
1560 *
1561 * @thread E1000_TX
1562 */
1563static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1564{
1565 uint32_t csum = 0;
1566 uint16_t *pu16 = (uint16_t *)pvBuf;
1567
1568 while (cb > 1)
1569 {
1570 csum += *pu16++;
1571 cb -= 2;
1572 }
1573 if (cb)
1574 csum += *(uint8_t*)pu16;
1575 while (csum >> 16)
1576 csum = (csum >> 16) + (csum & 0xFFFF);
1577 return ~csum;
1578}
1579
1580/**
1581 * Dump a packet to debug log.
1582 *
1583 * @param pState The device state structure.
1584 * @param cpPacket The packet.
1585 * @param cb The size of the packet.
1586 * @param cszText A string denoting direction of packet transfer.
1587 * @thread E1000_TX
1588 */
1589DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1590{
1591#ifdef DEBUG
1592 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
1593 {
1594 E1kLog(("%s --- %s packet #%d: ---\n",
1595 INSTANCE(pState), cszText, ++pState->u32PktNo));
1596 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1597 e1kCsLeave(pState);
1598 }
1599#else
1600 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
1601 {
1602 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1603 e1kCsLeave(pState);
1604 }
1605#endif
1606}
1607
1608/**
1609 * Determine the type of transmit descriptor.
1610 *
1611 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1612 *
1613 * @param pDesc Pointer to descriptor union.
1614 * @thread E1000_TX
1615 */
1616DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1617{
1618 if (pDesc->legacy.cmd.fDEXT)
1619 return pDesc->context.dw2.u4DTYP;
1620 return E1K_DTYP_LEGACY;
1621}
1622
1623/**
1624 * Dump receive descriptor to debug log.
1625 *
1626 * @param pState The device state structure.
1627 * @param pDesc Pointer to the descriptor.
1628 * @thread E1000_RX
1629 */
1630static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1631{
1632 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1633 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1634 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1635 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1636 pDesc->status.fPIF ? "PIF" : "pif",
1637 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1638 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1639 pDesc->status.fVP ? "VP" : "vp",
1640 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1641 pDesc->status.fEOP ? "EOP" : "eop",
1642 pDesc->status.fDD ? "DD" : "dd",
1643 pDesc->status.fRXE ? "RXE" : "rxe",
1644 pDesc->status.fIPE ? "IPE" : "ipe",
1645 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1646 pDesc->status.fCE ? "CE" : "ce",
1647 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1648 E1K_SPEC_VLAN(pDesc->status.u16Special),
1649 E1K_SPEC_PRI(pDesc->status.u16Special)));
1650}
1651
1652/**
1653 * Dump transmit descriptor to debug log.
1654 *
1655 * @param pState The device state structure.
1656 * @param pDesc Pointer to descriptor union.
1657 * @param cszDir A string denoting direction of descriptor transfer
1658 * @thread E1000_TX
1659 */
1660static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1661{
1662 switch (e1kGetDescType(pDesc))
1663 {
1664 case E1K_DTYP_CONTEXT:
1665 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1666 INSTANCE(pState), cszDir, cszDir));
1667 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1668 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1669 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1670 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1671 pDesc->context.dw2.fIDE ? " IDE":"",
1672 pDesc->context.dw2.fRS ? " RS" :"",
1673 pDesc->context.dw2.fTSE ? " TSE":"",
1674 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1675 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1676 pDesc->context.dw2.u20PAYLEN,
1677 pDesc->context.dw3.u8HDRLEN,
1678 pDesc->context.dw3.u16MSS,
1679 pDesc->context.dw3.fDD?"DD":""));
1680 break;
1681 case E1K_DTYP_DATA:
1682 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1683 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1684 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1685 pDesc->data.u64BufAddr,
1686 pDesc->data.cmd.u20DTALEN));
1687 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1688 pDesc->data.cmd.fIDE ? " IDE" :"",
1689 pDesc->data.cmd.fVLE ? " VLE" :"",
1690 pDesc->data.cmd.fRS ? " RS" :"",
1691 pDesc->data.cmd.fTSE ? " TSE" :"",
1692 pDesc->data.cmd.fIFCS? " IFCS":"",
1693 pDesc->data.cmd.fEOP ? " EOP" :"",
1694 pDesc->data.dw3.fDD ? " DD" :"",
1695 pDesc->data.dw3.fEC ? " EC" :"",
1696 pDesc->data.dw3.fLC ? " LC" :"",
1697 pDesc->data.dw3.fTXSM? " TXSM":"",
1698 pDesc->data.dw3.fIXSM? " IXSM":"",
1699 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
1700 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
1701 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
1702 break;
1703 case E1K_DTYP_LEGACY:
1704 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1705 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1706 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1707 pDesc->data.u64BufAddr,
1708 pDesc->legacy.cmd.u16Length));
1709 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1710 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1711 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1712 pDesc->legacy.cmd.fRS ? " RS" :"",
1713 pDesc->legacy.cmd.fIC ? " IC" :"",
1714 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1715 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1716 pDesc->legacy.dw3.fDD ? " DD" :"",
1717 pDesc->legacy.dw3.fEC ? " EC" :"",
1718 pDesc->legacy.dw3.fLC ? " LC" :"",
1719 pDesc->legacy.cmd.u8CSO,
1720 pDesc->legacy.dw3.u8CSS,
1721 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
1722 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
1723 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
1724 break;
1725 default:
1726 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1727 INSTANCE(pState), cszDir, cszDir));
1728 break;
1729 }
1730}
1731
1732/**
1733 * Raise interrupt if not masked.
1734 *
1735 * @param pState The device state structure.
1736 */
1737static int e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1738{
1739 int rc = e1kCsEnter(pState, rcBusy);
1740 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1741 return rc;
1742
1743 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1744 ICR |= u32IntCause;
1745 if (ICR & IMS)
1746 {
1747#if 0
1748 if (pState->fDelayInts)
1749 {
1750 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1751 pState->iStatIntLostOne = 1;
1752 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1753 INSTANCE(pState), ICR));
1754#define E1K_LOST_IRQ_THRSLD 20
1755//#define E1K_LOST_IRQ_THRSLD 200000000
1756 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1757 {
1758 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1759 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1760 pState->fIntMaskUsed = false;
1761 pState->uStatDisDly++;
1762 }
1763 }
1764 else
1765#endif
1766 if (pState->fIntRaised)
1767 {
1768 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1769 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1770 INSTANCE(pState), ICR & IMS));
1771 }
1772 else
1773 {
1774#ifdef E1K_ITR_ENABLED
1775 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1776 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1777 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1778 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1779 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1780 {
1781 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1782 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1783 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1784 }
1785 else
1786#endif
1787 {
1788
1789 /* Since we are delivering the interrupt now
1790 * there is no need to do it later -- stop the timer.
1791 */
1792 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1793 E1K_INC_ISTAT_CNT(pState->uStatInt);
1794 STAM_COUNTER_INC(&pState->StatIntsRaised);
1795 /* Got at least one unmasked interrupt cause */
1796 pState->fIntRaised = true;
1797 /* Raise(1) INTA(0) */
1798 //e1kMutexRelease(pState);
1799 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1800 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1801 //e1kMutexAcquire(pState, RT_SRC_POS);
1802 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1803 INSTANCE(pState), ICR & IMS));
1804 }
1805 }
1806 }
1807 else
1808 {
1809 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1810 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1811 INSTANCE(pState), ICR, IMS));
1812 }
1813 e1kCsLeave(pState);
1814 return VINF_SUCCESS;
1815}
1816
1817/**
1818 * Compute the physical address of the descriptor.
1819 *
1820 * @returns the physical address of the descriptor.
1821 *
1822 * @param baseHigh High-order 32 bits of descriptor table address.
1823 * @param baseLow Low-order 32 bits of descriptor table address.
1824 * @param idxDesc The descriptor index in the table.
1825 */
1826DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1827{
1828 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1829 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1830}
1831
1832/**
1833 * Advance the head pointer of the receive descriptor queue.
1834 *
1835 * @remarks RDH always points to the next available RX descriptor.
1836 *
1837 * @param pState The device state structure.
1838 */
1839DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1840{
1841 //e1kCsEnter(pState, RT_SRC_POS);
1842 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1843 RDH = 0;
1844 /*
1845 * Compute current receive queue length and fire RXDMT0 interrupt
1846 * if we are low on receive buffers
1847 */
1848 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1849 /*
1850 * The minimum threshold is controlled by RDMTS bits of RCTL:
1851 * 00 = 1/2 of RDLEN
1852 * 01 = 1/4 of RDLEN
1853 * 10 = 1/8 of RDLEN
1854 * 11 = reserved
1855 */
1856 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1857 if (uRQueueLen <= uMinRQThreshold)
1858 {
1859 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1860 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1861 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1862 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1863 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1864 }
1865 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
1866 INSTANCE(pState), RDH, RDT, uRQueueLen));
1867 //e1kCsLeave(pState);
1868}
1869
1870/**
1871 * Store a fragment of received packet that fits into the next available RX
1872 * buffer.
1873 *
1874 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1875 *
1876 * @param pState The device state structure.
1877 * @param pDesc The next available RX descriptor.
1878 * @param pvBuf The fragment.
1879 * @param cb The size of the fragment.
1880 */
1881static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1882{
1883 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1884 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1885 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1886 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1887 /* Write back the descriptor */
1888 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1889 e1kPrintRDesc(pState, pDesc);
1890 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1891 /* Advance head */
1892 e1kAdvanceRDH(pState);
1893 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1894 if (pDesc->status.fEOP)
1895 {
1896 /* Complete packet has been stored -- it is time to let the guest know. */
1897#ifdef E1K_USE_RX_TIMERS
1898 if (RDTR)
1899 {
1900 /* Arm the timer to fire in RDTR usec (discard .024) */
1901 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1902 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1903 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1904 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1905 }
1906 else
1907 {
1908#endif
1909 /* 0 delay means immediate interrupt */
1910 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1911 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1912#ifdef E1K_USE_RX_TIMERS
1913 }
1914#endif
1915 }
1916 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1917}
1918
1919/**
1920 * Returns true if it is a broadcast packet.
1921 *
1922 * @returns true if destination address indicates broadcast.
1923 * @param pvBuf The ethernet packet.
1924 */
1925DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1926{
1927 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1928 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1929}
1930
1931/**
1932 * Returns true if it is a multicast packet.
1933 *
1934 * @remarks returns true for broadcast packets as well.
1935 * @returns true if destination address indicates multicast.
1936 * @param pvBuf The ethernet packet.
1937 */
1938DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1939{
1940 return (*(char*)pvBuf) & 1;
1941}
1942
1943/**
1944 * Set IXSM, IPCS and TCPCS flags according to the packet type.
1945 *
1946 * @remarks We emulate checksum offloading for major packets types only.
1947 *
1948 * @returns VBox status code.
1949 * @param pState The device state structure.
1950 * @param pFrame The available data.
1951 * @param cb Number of bytes available in the buffer.
1952 * @param status Bit fields containing status info.
1953 */
1954static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
1955{
1956 /** @todo
1957 * It is not safe to bypass checksum verification for packets coming
1958 * from real wire. We currently unable to tell where packets are
1959 * coming from so we tell the driver to ignore our checksum flags
1960 * and do verification in software.
1961 */
1962#if 0
1963 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
1964
1965 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", INSTANCE(pState), uEtherType));
1966
1967 switch (uEtherType)
1968 {
1969 case 0x800: /* IPv4 */
1970 {
1971 pStatus->fIXSM = false;
1972 pStatus->fIPCS = true;
1973 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
1974 /* TCP/UDP checksum offloading works with TCP and UDP only */
1975 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
1976 break;
1977 }
1978 case 0x86DD: /* IPv6 */
1979 pStatus->fIXSM = false;
1980 pStatus->fIPCS = false;
1981 pStatus->fTCPCS = true;
1982 break;
1983 default: /* ARP, VLAN, etc. */
1984 pStatus->fIXSM = true;
1985 break;
1986 }
1987#else
1988 pStatus->fIXSM = true;
1989#endif
1990 return VINF_SUCCESS;
1991}
1992
1993/**
1994 * Pad and store received packet.
1995 *
1996 * @remarks Make sure that the packet appears to upper layer as one coming
1997 * from real Ethernet: pad it and insert FCS.
1998 *
1999 * @returns VBox status code.
2000 * @param pState The device state structure.
2001 * @param pvBuf The available data.
2002 * @param cb Number of bytes available in the buffer.
2003 * @param status Bit fields containing status info.
2004 */
2005static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
2006{
2007#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2008 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2009 uint8_t *ptr = rxPacket;
2010
2011#ifndef E1K_GLOBAL_MUTEX
2012 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2013 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2014 return rc;
2015#endif
2016
2017 if (cb > 70) /* unqualified guess */
2018 pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
2019
2020 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2021 Assert(cb > 16);
2022 if (status.fVP && cb > 16)
2023 {
2024 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2025 /* VLAN packet -- strip VLAN tag */
2026 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2027 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2028 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2029 }
2030 else
2031 memcpy(rxPacket, pvBuf, cb);
2032 /* Pad short packets */
2033 if (cb < 60)
2034 {
2035 memset(rxPacket + cb, 0, 60 - cb);
2036 cb = 60;
2037 }
2038 if (!(RCTL & RCTL_SECRC))
2039 {
2040 /* Add FCS if CRC stripping is not enabled */
2041 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2042 cb += sizeof(uint32_t);
2043 }
2044 /* Compute checksum of complete packet */
2045 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2046 e1kRxChecksumOffload(pState, rxPacket, cb, &status);
2047
2048 /* Update stats */
2049 E1K_INC_CNT32(GPRC);
2050 if (e1kIsBroadcast(pvBuf))
2051 E1K_INC_CNT32(BPRC);
2052 else if (e1kIsMulticast(pvBuf))
2053 E1K_INC_CNT32(MPRC);
2054 /* Update octet receive counter */
2055 E1K_ADD_CNT64(GORCL, GORCH, cb);
2056 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
2057 if (cb == 64)
2058 E1K_INC_CNT32(PRC64);
2059 else if (cb < 128)
2060 E1K_INC_CNT32(PRC127);
2061 else if (cb < 256)
2062 E1K_INC_CNT32(PRC255);
2063 else if (cb < 512)
2064 E1K_INC_CNT32(PRC511);
2065 else if (cb < 1024)
2066 E1K_INC_CNT32(PRC1023);
2067 else
2068 E1K_INC_CNT32(PRC1522);
2069
2070 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
2071
2072 if (RDH == RDT)
2073 {
2074 E1kLog(("%s Out of receive buffers, dropping the packet",
2075 INSTANCE(pState)));
2076 }
2077 /* Store the packet to receive buffers */
2078 while (RDH != RDT)
2079 {
2080 /* Load the descriptor pointed by head */
2081 E1KRXDESC desc;
2082 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2083 &desc, sizeof(desc));
2084 if (desc.u64BufAddr)
2085 {
2086 /* Update descriptor */
2087 desc.status = status;
2088 desc.u16Checksum = checksum;
2089 desc.status.fDD = true;
2090
2091 /*
2092 * We need to leave Rx critical section here or we risk deadlocking
2093 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2094 * page or has an access handler associated with it.
2095 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
2096 * modifies RDT only.
2097 */
2098 if (cb > pState->u16RxBSize)
2099 {
2100 desc.status.fEOP = false;
2101 e1kCsRxLeave(pState);
2102 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
2103 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2104 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2105 return rc;
2106 ptr += pState->u16RxBSize;
2107 cb -= pState->u16RxBSize;
2108 }
2109 else
2110 {
2111 desc.status.fEOP = true;
2112 e1kCsRxLeave(pState);
2113 e1kStoreRxFragment(pState, &desc, ptr, cb);
2114 pState->led.Actual.s.fReading = 0;
2115 return VINF_SUCCESS;
2116 }
2117 /* Note: RDH is advanced by e1kStoreRxFragment! */
2118 }
2119 else
2120 {
2121 desc.status.fDD = true;
2122 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
2123 e1kDescAddr(RDBAH, RDBAL, RDH),
2124 &desc, sizeof(desc));
2125 e1kAdvanceRDH(pState);
2126 }
2127 }
2128
2129 if (cb > 0)
2130 E1kLog(("%s Out of receive buffers, dropping %u bytes", INSTANCE(pState), cb));
2131
2132 pState->led.Actual.s.fReading = 0;
2133
2134 e1kCsRxLeave(pState);
2135
2136 return VINF_SUCCESS;
2137#else
2138 return VERR_INTERNAL_ERROR_2;
2139#endif
2140}
2141
2142
2143#if 0 /* unused */
2144/**
2145 * Read handler for Device Status register.
2146 *
2147 * Get the link status from PHY.
2148 *
2149 * @returns VBox status code.
2150 *
2151 * @param pState The device state structure.
2152 * @param offset Register offset in memory-mapped frame.
2153 * @param index Register index in register array.
2154 * @param mask Used to implement partial reads (8 and 16-bit).
2155 */
2156static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2157{
2158 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2159 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2160 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2161 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2162 {
2163 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2164 if (Phy::readMDIO(&pState->phy))
2165 *pu32Value = CTRL | CTRL_MDIO;
2166 else
2167 *pu32Value = CTRL & ~CTRL_MDIO;
2168 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2169 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
2170 }
2171 else
2172 {
2173 /* MDIO pin is used for output, ignore it */
2174 *pu32Value = CTRL;
2175 }
2176 return VINF_SUCCESS;
2177}
2178#endif /* unused */
2179
2180/**
2181 * Write handler for Device Control register.
2182 *
2183 * Handles reset.
2184 *
2185 * @param pState The device state structure.
2186 * @param offset Register offset in memory-mapped frame.
2187 * @param index Register index in register array.
2188 * @param value The value to store.
2189 * @param mask Used to implement partial writes (8 and 16-bit).
2190 * @thread EMT
2191 */
2192static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2193{
2194 int rc = VINF_SUCCESS;
2195
2196 if (value & CTRL_RESET)
2197 { /* RST */
2198#ifndef IN_RING3
2199 return VINF_IOM_HC_IOPORT_WRITE;
2200#else
2201 e1kHardReset(pState);
2202#endif
2203 }
2204 else
2205 {
2206 if ( (value & CTRL_SLU)
2207 && pState->fCableConnected
2208 && !(STATUS & STATUS_LU))
2209 {
2210 /* The driver indicates that we should bring up the link */
2211 /* Do so in 5 seconds. */
2212 e1kArmTimer(pState, pState->CTX_SUFF(pLUTimer), 5000000);
2213 /*
2214 * Change the status (but not PHY status) anyway as Windows expects
2215 * it for 82543GC.
2216 */
2217 STATUS |= STATUS_LU;
2218 }
2219 if (value & CTRL_VME)
2220 {
2221 E1kLog(("%s VLAN Mode Enabled\n", INSTANCE(pState)));
2222 }
2223 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2224 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2225 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2226 if (value & CTRL_MDC)
2227 {
2228 if (value & CTRL_MDIO_DIR)
2229 {
2230 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2231 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2232 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2233 }
2234 else
2235 {
2236 if (Phy::readMDIO(&pState->phy))
2237 value |= CTRL_MDIO;
2238 else
2239 value &= ~CTRL_MDIO;
2240 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2241 INSTANCE(pState), !!(value & CTRL_MDIO)));
2242 }
2243 }
2244 rc = e1kRegWriteDefault(pState, offset, index, value);
2245 }
2246
2247 return rc;
2248}
2249
2250/**
2251 * Write handler for EEPROM/Flash Control/Data register.
2252 *
2253 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2254 *
2255 * @param pState The device state structure.
2256 * @param offset Register offset in memory-mapped frame.
2257 * @param index Register index in register array.
2258 * @param value The value to store.
2259 * @param mask Used to implement partial writes (8 and 16-bit).
2260 * @thread EMT
2261 */
2262static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2263{
2264#ifdef IN_RING3
2265 /* So far we are concerned with lower byte only */
2266 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2267 {
2268 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2269 /* Note: 82543GC does not need to request EEPROM access */
2270 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2271 pState->eeprom.write(value & EECD_EE_WIRES);
2272 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2273 }
2274 if (value & EECD_EE_REQ)
2275 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2276 else
2277 EECD &= ~EECD_EE_GNT;
2278 //e1kRegWriteDefault(pState, offset, index, value );
2279
2280 return VINF_SUCCESS;
2281#else /* !IN_RING3 */
2282 return VINF_IOM_HC_MMIO_WRITE;
2283#endif /* !IN_RING3 */
2284}
2285
2286/**
2287 * Read handler for EEPROM/Flash Control/Data register.
2288 *
2289 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2290 *
2291 * @returns VBox status code.
2292 *
2293 * @param pState The device state structure.
2294 * @param offset Register offset in memory-mapped frame.
2295 * @param index Register index in register array.
2296 * @param mask Used to implement partial reads (8 and 16-bit).
2297 * @thread EMT
2298 */
2299static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2300{
2301#ifdef IN_RING3
2302 uint32_t value;
2303 int rc = e1kRegReadDefault(pState, offset, index, &value);
2304 if (RT_SUCCESS(rc))
2305 {
2306 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2307 {
2308 /* Note: 82543GC does not need to request EEPROM access */
2309 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2310 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2311 value |= pState->eeprom.read();
2312 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2313 }
2314 *pu32Value = value;
2315 }
2316
2317 return rc;
2318#else /* !IN_RING3 */
2319 return VINF_IOM_HC_MMIO_READ;
2320#endif /* !IN_RING3 */
2321}
2322
2323/**
2324 * Write handler for EEPROM Read register.
2325 *
2326 * Handles EEPROM word access requests, reads EEPROM and stores the result
2327 * into DATA field.
2328 *
2329 * @param pState The device state structure.
2330 * @param offset Register offset in memory-mapped frame.
2331 * @param index Register index in register array.
2332 * @param value The value to store.
2333 * @param mask Used to implement partial writes (8 and 16-bit).
2334 * @thread EMT
2335 */
2336static int e1kRegWriteEERD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2337{
2338#ifdef IN_RING3
2339 /* Make use of 'writable' and 'readable' masks. */
2340 e1kRegWriteDefault(pState, offset, index, value);
2341 /* DONE and DATA are set only if read was triggered by START. */
2342 if (value & EERD_START)
2343 {
2344 uint16_t tmp;
2345 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2346 if (pState->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2347 SET_BITS(EERD, DATA, tmp);
2348 EERD |= EERD_DONE;
2349 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2350 }
2351
2352 return VINF_SUCCESS;
2353#else /* !IN_RING3 */
2354 return VINF_IOM_HC_MMIO_WRITE;
2355#endif /* !IN_RING3 */
2356}
2357
2358
2359/**
2360 * Write handler for MDI Control register.
2361 *
2362 * Handles PHY read/write requests; forwards requests to internal PHY device.
2363 *
2364 * @param pState The device state structure.
2365 * @param offset Register offset in memory-mapped frame.
2366 * @param index Register index in register array.
2367 * @param value The value to store.
2368 * @param mask Used to implement partial writes (8 and 16-bit).
2369 * @thread EMT
2370 */
2371static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2372{
2373 if (value & MDIC_INT_EN)
2374 {
2375 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2376 INSTANCE(pState)));
2377 }
2378 else if (value & MDIC_READY)
2379 {
2380 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2381 INSTANCE(pState)));
2382 }
2383 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2384 {
2385 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2386 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2387 }
2388 else
2389 {
2390 /* Store the value */
2391 e1kRegWriteDefault(pState, offset, index, value);
2392 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2393 /* Forward op to PHY */
2394 if (value & MDIC_OP_READ)
2395 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2396 else
2397 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2398 /* Let software know that we are done */
2399 MDIC |= MDIC_READY;
2400 }
2401
2402 return VINF_SUCCESS;
2403}
2404
2405/**
2406 * Write handler for Interrupt Cause Read register.
2407 *
2408 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2409 *
2410 * @param pState The device state structure.
2411 * @param offset Register offset in memory-mapped frame.
2412 * @param index Register index in register array.
2413 * @param value The value to store.
2414 * @param mask Used to implement partial writes (8 and 16-bit).
2415 * @thread EMT
2416 */
2417static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2418{
2419 ICR &= ~value;
2420
2421 return VINF_SUCCESS;
2422}
2423
2424/**
2425 * Read handler for Interrupt Cause Read register.
2426 *
2427 * Reading this register acknowledges all interrupts.
2428 *
2429 * @returns VBox status code.
2430 *
2431 * @param pState The device state structure.
2432 * @param offset Register offset in memory-mapped frame.
2433 * @param index Register index in register array.
2434 * @param mask Not used.
2435 * @thread EMT
2436 */
2437static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2438{
2439 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2440 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2441 return rc;
2442
2443 uint32_t value = 0;
2444 rc = e1kRegReadDefault(pState, offset, index, &value);
2445 if (RT_SUCCESS(rc))
2446 {
2447 if (value)
2448 {
2449 /*
2450 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2451 * with disabled interrupts.
2452 */
2453 //if (IMS)
2454 if (1)
2455 {
2456 /*
2457 * Interrupts were enabled -- we are supposedly at the very
2458 * beginning of interrupt handler
2459 */
2460 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2461 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2462 /* Clear all pending interrupts */
2463 ICR = 0;
2464 pState->fIntRaised = false;
2465 /* Lower(0) INTA(0) */
2466 //e1kMutexRelease(pState);
2467 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2468 //e1kMutexAcquire(pState, RT_SRC_POS);
2469
2470 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2471 if (pState->fIntMaskUsed)
2472 pState->fDelayInts = true;
2473 }
2474 else
2475 {
2476 /*
2477 * Interrupts are disabled -- in windows guests ICR read is done
2478 * just before re-enabling interrupts
2479 */
2480 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2481 }
2482 }
2483 *pu32Value = value;
2484 }
2485 e1kCsLeave(pState);
2486
2487 return rc;
2488}
2489
2490/**
2491 * Write handler for Interrupt Cause Set register.
2492 *
2493 * Bits corresponding to 1s in 'value' will be set in ICR register.
2494 *
2495 * @param pState The device state structure.
2496 * @param offset Register offset in memory-mapped frame.
2497 * @param index Register index in register array.
2498 * @param value The value to store.
2499 * @param mask Used to implement partial writes (8 and 16-bit).
2500 * @thread EMT
2501 */
2502static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2503{
2504 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2505 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2506}
2507
2508/**
2509 * Write handler for Interrupt Mask Set register.
2510 *
2511 * Will trigger pending interrupts.
2512 *
2513 * @param pState The device state structure.
2514 * @param offset Register offset in memory-mapped frame.
2515 * @param index Register index in register array.
2516 * @param value The value to store.
2517 * @param mask Used to implement partial writes (8 and 16-bit).
2518 * @thread EMT
2519 */
2520static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2521{
2522 IMS |= value;
2523 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2524 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2525 /* Mask changes, we need to raise pending interrupts. */
2526 if ((ICR & IMS) && !pState->fLocked)
2527 {
2528 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2529 INSTANCE(pState), ICR));
2530 /* Raising an interrupt immediately causes win7 to hang upon NIC reconfiguration (#5023) */
2531 TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2532 TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2533 }
2534
2535 return VINF_SUCCESS;
2536}
2537
2538/**
2539 * Write handler for Interrupt Mask Clear register.
2540 *
2541 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2542 *
2543 * @param pState The device state structure.
2544 * @param offset Register offset in memory-mapped frame.
2545 * @param index Register index in register array.
2546 * @param value The value to store.
2547 * @param mask Used to implement partial writes (8 and 16-bit).
2548 * @thread EMT
2549 */
2550static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2551{
2552 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2553 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2554 return rc;
2555 if (pState->fIntRaised)
2556 {
2557 /*
2558 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2559 * Windows to freeze since it may receive an interrupt while still in the very beginning
2560 * of interrupt handler.
2561 */
2562 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2563 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2564 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2565 /* Lower(0) INTA(0) */
2566 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2567 pState->fIntRaised = false;
2568 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2569 }
2570 IMS &= ~value;
2571 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2572 e1kCsLeave(pState);
2573
2574 return VINF_SUCCESS;
2575}
2576
2577/**
2578 * Write handler for Receive Control register.
2579 *
2580 * @param pState The device state structure.
2581 * @param offset Register offset in memory-mapped frame.
2582 * @param index Register index in register array.
2583 * @param value The value to store.
2584 * @param mask Used to implement partial writes (8 and 16-bit).
2585 * @thread EMT
2586 */
2587static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2588{
2589 /* Update promiscuous mode */
2590 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
2591 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
2592 {
2593 /* Promiscuity has changed, pass the knowledge on. */
2594#ifndef IN_RING3
2595 return VINF_IOM_HC_IOPORT_WRITE;
2596#else
2597 if (pState->pDrvR3)
2598 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3, fBecomePromiscous);
2599#endif
2600 }
2601
2602 /* Adjust receive buffer size */
2603 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
2604 if (value & RCTL_BSEX)
2605 cbRxBuf *= 16;
2606 if (cbRxBuf != pState->u16RxBSize)
2607 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
2608 INSTANCE(pState), cbRxBuf, pState->u16RxBSize));
2609 pState->u16RxBSize = cbRxBuf;
2610
2611 /* Update the register */
2612 e1kRegWriteDefault(pState, offset, index, value);
2613
2614 return VINF_SUCCESS;
2615}
2616
2617/**
2618 * Write handler for Packet Buffer Allocation register.
2619 *
2620 * TXA = 64 - RXA.
2621 *
2622 * @param pState The device state structure.
2623 * @param offset Register offset in memory-mapped frame.
2624 * @param index Register index in register array.
2625 * @param value The value to store.
2626 * @param mask Used to implement partial writes (8 and 16-bit).
2627 * @thread EMT
2628 */
2629static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2630{
2631 e1kRegWriteDefault(pState, offset, index, value);
2632 PBA_st->txa = 64 - PBA_st->rxa;
2633
2634 return VINF_SUCCESS;
2635}
2636
2637/**
2638 * Write handler for Receive Descriptor Tail register.
2639 *
2640 * @remarks Write into RDT forces switch to HC and signal to
2641 * e1kNetworkDown_WaitReceiveAvail().
2642 *
2643 * @returns VBox status code.
2644 *
2645 * @param pState The device state structure.
2646 * @param offset Register offset in memory-mapped frame.
2647 * @param index Register index in register array.
2648 * @param value The value to store.
2649 * @param mask Used to implement partial writes (8 and 16-bit).
2650 * @thread EMT
2651 */
2652static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2653{
2654#ifndef IN_RING3
2655 /* XXX */
2656// return VINF_IOM_HC_MMIO_WRITE;
2657#endif
2658 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2659 if (RT_LIKELY(rc == VINF_SUCCESS))
2660 {
2661 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2662 rc = e1kRegWriteDefault(pState, offset, index, value);
2663 e1kCsRxLeave(pState);
2664 if (RT_SUCCESS(rc))
2665 {
2666/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
2667 * without requiring any context switches. We should also check the
2668 * wait condition before bothering to queue the item as we're currently
2669 * queuing thousands of items per second here in a normal transmit
2670 * scenario. Expect performance changes when fixing this! */
2671#ifdef IN_RING3
2672 /* Signal that we have more receive descriptors available. */
2673 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2674#else
2675 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2676 if (pItem)
2677 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2678#endif
2679 }
2680 }
2681 return rc;
2682}
2683
2684/**
2685 * Write handler for Receive Delay Timer register.
2686 *
2687 * @param pState The device state structure.
2688 * @param offset Register offset in memory-mapped frame.
2689 * @param index Register index in register array.
2690 * @param value The value to store.
2691 * @param mask Used to implement partial writes (8 and 16-bit).
2692 * @thread EMT
2693 */
2694static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2695{
2696 e1kRegWriteDefault(pState, offset, index, value);
2697 if (value & RDTR_FPD)
2698 {
2699 /* Flush requested, cancel both timers and raise interrupt */
2700#ifdef E1K_USE_RX_TIMERS
2701 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2702 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2703#endif
2704 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2705 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2706 }
2707
2708 return VINF_SUCCESS;
2709}
2710
2711DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2712{
2713 /**
2714 * Make sure TDT won't change during computation. EMT may modify TDT at
2715 * any moment.
2716 */
2717 uint32_t tdt = TDT;
2718 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2719}
2720
2721#ifdef IN_RING3
2722#ifdef E1K_USE_TX_TIMERS
2723
2724/**
2725 * Transmit Interrupt Delay Timer handler.
2726 *
2727 * @remarks We only get here when the timer expires.
2728 *
2729 * @param pDevIns Pointer to device instance structure.
2730 * @param pTimer Pointer to the timer.
2731 * @param pvUser NULL.
2732 * @thread EMT
2733 */
2734static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2735{
2736 E1KSTATE *pState = (E1KSTATE *)pvUser;
2737
2738 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2739 {
2740 E1K_INC_ISTAT_CNT(pState->uStatTID);
2741 /* Cancel absolute delay timer as we have already got attention */
2742#ifndef E1K_NO_TAD
2743 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2744#endif /* E1K_NO_TAD */
2745 e1kRaiseInterrupt(pState, ICR_TXDW);
2746 e1kMutexRelease(pState);
2747 }
2748}
2749
2750/**
2751 * Transmit Absolute Delay Timer handler.
2752 *
2753 * @remarks We only get here when the timer expires.
2754 *
2755 * @param pDevIns Pointer to device instance structure.
2756 * @param pTimer Pointer to the timer.
2757 * @param pvUser NULL.
2758 * @thread EMT
2759 */
2760static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2761{
2762 E1KSTATE *pState = (E1KSTATE *)pvUser;
2763
2764 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2765 {
2766 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2767 /* Cancel interrupt delay timer as we have already got attention */
2768 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2769 e1kRaiseInterrupt(pState, ICR_TXDW);
2770 e1kMutexRelease(pState);
2771 }
2772}
2773
2774#endif /* E1K_USE_TX_TIMERS */
2775#ifdef E1K_USE_RX_TIMERS
2776
2777/**
2778 * Receive Interrupt Delay Timer handler.
2779 *
2780 * @remarks We only get here when the timer expires.
2781 *
2782 * @param pDevIns Pointer to device instance structure.
2783 * @param pTimer Pointer to the timer.
2784 * @param pvUser NULL.
2785 * @thread EMT
2786 */
2787static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2788{
2789 E1KSTATE *pState = (E1KSTATE *)pvUser;
2790
2791 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2792 {
2793 E1K_INC_ISTAT_CNT(pState->uStatRID);
2794 /* Cancel absolute delay timer as we have already got attention */
2795 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2796 e1kRaiseInterrupt(pState, ICR_RXT0);
2797 e1kMutexRelease(pState);
2798 }
2799}
2800
2801/**
2802 * Receive Absolute Delay Timer handler.
2803 *
2804 * @remarks We only get here when the timer expires.
2805 *
2806 * @param pDevIns Pointer to device instance structure.
2807 * @param pTimer Pointer to the timer.
2808 * @param pvUser NULL.
2809 * @thread EMT
2810 */
2811static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2812{
2813 E1KSTATE *pState = (E1KSTATE *)pvUser;
2814
2815 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2816 {
2817 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2818 /* Cancel interrupt delay timer as we have already got attention */
2819 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2820 e1kRaiseInterrupt(pState, ICR_RXT0);
2821 e1kMutexRelease(pState);
2822 }
2823}
2824
2825#endif /* E1K_USE_RX_TIMERS */
2826
2827/**
2828 * Late Interrupt Timer handler.
2829 *
2830 * @param pDevIns Pointer to device instance structure.
2831 * @param pTimer Pointer to the timer.
2832 * @param pvUser NULL.
2833 * @thread EMT
2834 */
2835static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2836{
2837 E1KSTATE *pState = (E1KSTATE *)pvUser;
2838
2839 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2840 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2841 {
2842 STAM_COUNTER_INC(&pState->StatLateInts);
2843 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2844#if 0
2845 if (pState->iStatIntLost > -100)
2846 pState->iStatIntLost--;
2847#endif
2848 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2849 e1kMutexRelease(pState);
2850 }
2851 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2852}
2853
2854/**
2855 * Link Up Timer handler.
2856 *
2857 * @param pDevIns Pointer to device instance structure.
2858 * @param pTimer Pointer to the timer.
2859 * @param pvUser NULL.
2860 * @thread EMT
2861 */
2862static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2863{
2864 E1KSTATE *pState = (E1KSTATE *)pvUser;
2865
2866 /*
2867 * This can happen if we set the link status to down when the Link up timer was
2868 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
2869 * and connect+disconnect the cable very quick.
2870 */
2871 if (!pState->fCableConnected)
2872 return;
2873
2874 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2875 {
2876 STATUS |= STATUS_LU;
2877 Phy::setLinkStatus(&pState->phy, true);
2878 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2879 e1kMutexRelease(pState);
2880 }
2881}
2882
2883#endif /* IN_RING3 */
2884
2885/**
2886 * Sets up the GSO context according to the TSE new context descriptor.
2887 *
2888 * @param pGso The GSO context to setup.
2889 * @param pCtx The context descriptor.
2890 */
2891DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
2892{
2893 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
2894
2895 /*
2896 * See if the context descriptor describes something that could be TCP or
2897 * UDP over IPv[46].
2898 */
2899 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
2900 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
2901 {
2902 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
2903 return;
2904 }
2905 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
2906 {
2907 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
2908 return;
2909 }
2910 if (RT_UNLIKELY( pCtx->dw2.fTCP
2911 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
2912 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
2913 {
2914 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
2915 return;
2916 }
2917
2918 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
2919 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
2920 {
2921 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
2922 return;
2923 }
2924
2925 /* IPv4 checksum offset. */
2926 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
2927 {
2928 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
2929 return;
2930 }
2931
2932 /* TCP/UDP checksum offsets. */
2933 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
2934 != ( pCtx->dw2.fTCP
2935 ? RT_UOFFSETOF(RTNETTCP, th_sum)
2936 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
2937 {
2938 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
2939 return;
2940 }
2941
2942 /*
2943 * Because of internal networking using a 16-bit size field for GSO context
2944 * plus frame, we have to make sure we don't exceed this.
2945 */
2946 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
2947 {
2948 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
2949 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
2950 return;
2951 }
2952
2953 /*
2954 * We're good for now - we'll do more checks when seeing the data.
2955 * So, figure the type of offloading and setup the context.
2956 */
2957 if (pCtx->dw2.fIP)
2958 {
2959 if (pCtx->dw2.fTCP)
2960 {
2961 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
2962 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
2963 }
2964 else
2965 {
2966 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
2967 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
2968 }
2969 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
2970 * this yet it seems)... */
2971 }
2972 else
2973 {
2974 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /* @todo IPv6 UFO */
2975 if (pCtx->dw2.fTCP)
2976 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
2977 else
2978 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
2979 }
2980 pGso->offHdr1 = pCtx->ip.u8CSS;
2981 pGso->offHdr2 = pCtx->tu.u8CSS;
2982 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
2983 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
2984 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
2985 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
2986 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
2987}
2988
2989/**
2990 * Checks if we can use GSO processing for the current TSE frame.
2991 *
2992 * @param pGso The GSO context.
2993 * @param pData The first data descriptor of the frame.
2994 * @param pCtx The TSO context descriptor.
2995 */
2996DECLINLINE(bool) e1kCanDoGso(PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
2997{
2998 if (!pData->cmd.fTSE)
2999 {
3000 E1kLog2(("e1kCanDoGso: !TSE\n"));
3001 return false;
3002 }
3003 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3004 {
3005 E1kLog(("e1kCanDoGso: VLE\n"));
3006 return false;
3007 }
3008
3009 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3010 {
3011 case PDMNETWORKGSOTYPE_IPV4_TCP:
3012 case PDMNETWORKGSOTYPE_IPV4_UDP:
3013 if (!pData->dw3.fIXSM)
3014 {
3015 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3016 return false;
3017 }
3018 if (!pData->dw3.fTXSM)
3019 {
3020 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3021 return false;
3022 }
3023 /** @todo what more check should we perform here? Ethernet frame type? */
3024 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3025 return true;
3026
3027 case PDMNETWORKGSOTYPE_IPV6_TCP:
3028 case PDMNETWORKGSOTYPE_IPV6_UDP:
3029 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3030 {
3031 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3032 return false;
3033 }
3034 if (!pData->dw3.fTXSM)
3035 {
3036 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3037 return false;
3038 }
3039 /** @todo what more check should we perform here? Ethernet frame type? */
3040 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3041 return true;
3042
3043 default:
3044 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3045 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3046 return false;
3047 }
3048}
3049
3050/**
3051 * Frees the current xmit buffer.
3052 *
3053 * @param pState The device state structure.
3054 */
3055static void e1kXmitFreeBuf(E1KSTATE *pState)
3056{
3057 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
3058 if (pSg)
3059 {
3060 pState->CTX_SUFF(pTxSg) = NULL;
3061
3062 if (pSg->pvAllocator != pState)
3063 {
3064 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3065 if (pDrv)
3066 pDrv->pfnFreeBuf(pDrv, pSg);
3067 }
3068 else
3069 {
3070 /* loopback */
3071 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3072 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3073 pSg->fFlags = 0;
3074 pSg->pvAllocator = NULL;
3075 }
3076 }
3077}
3078
3079/**
3080 * Allocates a xmit buffer.
3081 *
3082 * Presently this will always return a buffer. Later on we'll have a
3083 * out-of-buffer mechanism in place where the driver calls us back when buffers
3084 * becomes available.
3085 *
3086 * @returns See PDMINETWORKUP::pfnAllocBuf.
3087 * @param pState The device state structure.
3088 * @param cbMin The minimum frame size.
3089 * @param fExactSize Whether cbMin is exact or if we have to max it
3090 * out to the max MTU size.
3091 * @param fGso Whether this is a GSO frame or not.
3092 */
3093DECLINLINE(int) e1kXmitAllocBuf(E1KSTATE *pState, size_t cbMin, bool fExactSize, bool fGso)
3094{
3095 /* Adjust cbMin if necessary. */
3096 if (!fExactSize)
3097 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3098
3099 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3100 if (RT_UNLIKELY(pState->CTX_SUFF(pTxSg)))
3101 e1kXmitFreeBuf(pState);
3102 Assert(pState->CTX_SUFF(pTxSg) == NULL);
3103
3104 /*
3105 * Allocate the buffer.
3106 */
3107 PPDMSCATTERGATHER pSg;
3108 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3109 {
3110 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3111 if (RT_UNLIKELY(!pDrv))
3112 return VERR_NET_DOWN;
3113 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pState->GsoCtx : NULL, &pSg);
3114 if (RT_FAILURE(rc))
3115 return rc;
3116 }
3117 else
3118 {
3119 /* Create a loopback using the fallback buffer and preallocated SG. */
3120 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3121 pSg = &pState->uTxFallback.Sg;
3122 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3123 pSg->cbUsed = 0;
3124 pSg->cbAvailable = 0;
3125 pSg->pvAllocator = pState;
3126 pSg->pvUser = NULL; /* No GSO here. */
3127 pSg->cSegs = 1;
3128 pSg->aSegs[0].pvSeg = pState->aTxPacketFallback;
3129 pSg->aSegs[0].cbSeg = sizeof(pState->aTxPacketFallback);
3130 }
3131
3132 pState->CTX_SUFF(pTxSg) = pSg;
3133 return VINF_SUCCESS;
3134}
3135
3136/**
3137 * Checks if it's a GSO buffer or not.
3138 *
3139 * @returns true / false.
3140 * @param pTxSg The scatter / gather buffer.
3141 */
3142DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3143{
3144#if 0
3145 if (!pTxSg)
3146 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3147 if (pTxSg && pTxSg->pvUser)
3148 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3149#endif
3150 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3151}
3152
3153/**
3154 * Load transmit descriptor from guest memory.
3155 *
3156 * @param pState The device state structure.
3157 * @param pDesc Pointer to descriptor union.
3158 * @param addr Physical address in guest context.
3159 * @thread E1000_TX
3160 */
3161DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3162{
3163 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3164}
3165
3166/**
3167 * Write back transmit descriptor to guest memory.
3168 *
3169 * @param pState The device state structure.
3170 * @param pDesc Pointer to descriptor union.
3171 * @param addr Physical address in guest context.
3172 * @thread E1000_TX
3173 */
3174DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3175{
3176 /* Only the last half of the descriptor has to be written back. */
3177 e1kPrintTDesc(pState, pDesc, "^^^");
3178 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3179}
3180
3181/**
3182 * Transmit complete frame.
3183 *
3184 * @remarks We skip the FCS since we're not responsible for sending anything to
3185 * a real ethernet wire.
3186 *
3187 * @param pState The device state structure.
3188 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3189 * @thread E1000_TX
3190 */
3191static void e1kTransmitFrame(E1KSTATE* pState, bool fOnWorkerThread)
3192{
3193 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
3194 uint32_t const cbFrame = pSg ? ((uint32_t)pSg->cbUsed + (pState->fVTag ? 4 : 0)) : 0;
3195 Assert(!pSg || pSg->cSegs == 1);
3196
3197/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
3198 "%.*Rhxd\n"
3199 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
3200 INSTANCE(pState), cbFrame, pSg->aSegs[0].pvSeg, INSTANCE(pState)));*/
3201
3202 if (cbFrame > 70) /* unqualified guess */
3203 pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
3204
3205 /* Add VLAN tag */
3206 if (cbFrame > 16 && pState->fVTag)
3207 {
3208 /*
3209 * We should have 'adjusted' pvSeg earlier to make room for four
3210 * additional bytes at the beginning of buffer. Now we move it back.
3211 */
3212 uint32_t *pSrc = (uint32_t*)pSg->aSegs[0].pvSeg;
3213 uint32_t *pDst = pSrc - 1;
3214 pSg->aSegs[0].pvSeg = pDst;
3215 *pDst++ = *pSrc++; /* Copy destination address */
3216 *pDst++ = *pSrc++; /* Copy destination and source addresses */
3217 *pDst++ = *pSrc++; /* Copy source address */
3218 *pDst++ = RT_BE2H_U16(VET) | (RT_BE2H_U16(pState->u16VTagTCI) << 16);
3219 E1kLog3(("%s Inserted VLAN tag %08x\n",
3220 INSTANCE(pState), RT_BE2H_U16(VET) | (RT_BE2H_U16(pState->u16VTagTCI) << 16)));
3221 }
3222 /* Update the stats */
3223 E1K_INC_CNT32(TPT);
3224 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3225 E1K_INC_CNT32(GPTC);
3226 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3227 E1K_INC_CNT32(BPTC);
3228 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3229 E1K_INC_CNT32(MPTC);
3230 /* Update octet transmit counter */
3231 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3232 if (pState->CTX_SUFF(pDrv))
3233 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, cbFrame);
3234 if (cbFrame == 64)
3235 E1K_INC_CNT32(PTC64);
3236 else if (cbFrame < 128)
3237 E1K_INC_CNT32(PTC127);
3238 else if (cbFrame < 256)
3239 E1K_INC_CNT32(PTC255);
3240 else if (cbFrame < 512)
3241 E1K_INC_CNT32(PTC511);
3242 else if (cbFrame < 1024)
3243 E1K_INC_CNT32(PTC1023);
3244 else
3245 E1K_INC_CNT32(PTC1522);
3246
3247 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
3248
3249 /*
3250 * Dump and send the packet.
3251 */
3252 int rc = VERR_NET_DOWN;
3253 if (pSg && pSg->pvAllocator != pState)
3254 {
3255 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3256
3257 pState->CTX_SUFF(pTxSg) = NULL;
3258 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3259 if (pDrv)
3260 {
3261 /* Release critical section to avoid deadlock in CanReceive */
3262 //e1kCsLeave(pState);
3263 e1kMutexRelease(pState);
3264 STAM_PROFILE_START(&pState->CTX_SUFF_Z(StatTransmitSend), a);
3265 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3266 STAM_PROFILE_STOP(&pState->CTX_SUFF_Z(StatTransmitSend), a);
3267 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3268 //e1kCsEnter(pState, RT_SRC_POS);
3269 }
3270 }
3271 else if (pSg)
3272 {
3273 Assert(pSg->aSegs[0].pvSeg == pState->aTxPacketFallback);
3274 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3275
3276 /** @todo do we actually need to check that we're in loopback mode here? */
3277 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3278 {
3279 E1KRXDST status;
3280 RT_ZERO(status);
3281 status.fPIF = true;
3282 e1kHandleRxPacket(pState, pSg->aSegs[0].pvSeg, cbFrame, status);
3283 rc = VINF_SUCCESS;
3284 }
3285 e1kXmitFreeBuf(pState);
3286 }
3287 else
3288 rc = VERR_NET_DOWN;
3289 if (RT_FAILURE(rc))
3290 {
3291 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3292 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3293 }
3294
3295 pState->led.Actual.s.fWriting = 0;
3296}
3297
3298/**
3299 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3300 *
3301 * @param pState The device state structure.
3302 * @param pPkt Pointer to the packet.
3303 * @param u16PktLen Total length of the packet.
3304 * @param cso Offset in packet to write checksum at.
3305 * @param css Offset in packet to start computing
3306 * checksum from.
3307 * @param cse Offset in packet to stop computing
3308 * checksum at.
3309 * @thread E1000_TX
3310 */
3311static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3312{
3313 if (cso > u16PktLen)
3314 {
3315 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
3316 INSTANCE(pState), cso, u16PktLen));
3317 return;
3318 }
3319
3320 if (cse == 0)
3321 cse = u16PktLen - 1;
3322 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
3323 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
3324 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
3325 *(uint16_t*)(pPkt + cso) = u16ChkSum;
3326}
3327
3328/**
3329 * Add a part of descriptor's buffer to transmit frame.
3330 *
3331 * @remarks data.u64BufAddr is used unconditionally for both data
3332 * and legacy descriptors since it is identical to
3333 * legacy.u64BufAddr.
3334 *
3335 * @param pState The device state structure.
3336 * @param pDesc Pointer to the descriptor to transmit.
3337 * @param u16Len Length of buffer to the end of segment.
3338 * @param fSend Force packet sending.
3339 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3340 * @thread E1000_TX
3341 */
3342static void e1kFallbackAddSegment(E1KSTATE* pState, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
3343{
3344 /* TCP header being transmitted */
3345 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
3346 (pState->aTxPacketFallback + pState->contextTSE.tu.u8CSS);
3347 /* IP header being transmitted */
3348 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
3349 (pState->aTxPacketFallback + pState->contextTSE.ip.u8CSS);
3350
3351 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
3352 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain, fSend));
3353 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
3354
3355 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), PhysAddr,
3356 pState->aTxPacketFallback + pState->u16TxPktLen, u16Len);
3357 E1kLog3(("%s Dump of the segment:\n"
3358 "%.*Rhxd\n"
3359 "%s --- End of dump ---\n",
3360 INSTANCE(pState), u16Len, pState->aTxPacketFallback + pState->u16TxPktLen, INSTANCE(pState)));
3361 pState->u16TxPktLen += u16Len;
3362 E1kLog3(("%s e1kFallbackAddSegment: pState->u16TxPktLen=%x\n",
3363 INSTANCE(pState), pState->u16TxPktLen));
3364 if (pState->u16HdrRemain > 0)
3365 {
3366 /* The header was not complete, check if it is now */
3367 if (u16Len >= pState->u16HdrRemain)
3368 {
3369 /* The rest is payload */
3370 u16Len -= pState->u16HdrRemain;
3371 pState->u16HdrRemain = 0;
3372 /* Save partial checksum and flags */
3373 pState->u32SavedCsum = pTcpHdr->chksum;
3374 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
3375 /* Clear FIN and PSH flags now and set them only in the last segment */
3376 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
3377 }
3378 else
3379 {
3380 /* Still not */
3381 pState->u16HdrRemain -= u16Len;
3382 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
3383 INSTANCE(pState), pState->u16HdrRemain));
3384 return;
3385 }
3386 }
3387
3388 pState->u32PayRemain -= u16Len;
3389
3390 if (fSend)
3391 {
3392 /* Leave ethernet header intact */
3393 /* IP Total Length = payload + headers - ethernet header */
3394 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
3395 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
3396 INSTANCE(pState), ntohs(pIpHdr->total_len)));
3397 /* Update IP Checksum */
3398 pIpHdr->chksum = 0;
3399 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3400 pState->contextTSE.ip.u8CSO,
3401 pState->contextTSE.ip.u8CSS,
3402 pState->contextTSE.ip.u16CSE);
3403
3404 /* Update TCP flags */
3405 /* Restore original FIN and PSH flags for the last segment */
3406 if (pState->u32PayRemain == 0)
3407 {
3408 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
3409 E1K_INC_CNT32(TSCTC);
3410 }
3411 /* Add TCP length to partial pseudo header sum */
3412 uint32_t csum = pState->u32SavedCsum
3413 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
3414 while (csum >> 16)
3415 csum = (csum >> 16) + (csum & 0xFFFF);
3416 pTcpHdr->chksum = csum;
3417 /* Compute final checksum */
3418 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3419 pState->contextTSE.tu.u8CSO,
3420 pState->contextTSE.tu.u8CSS,
3421 pState->contextTSE.tu.u16CSE);
3422
3423 /*
3424 * Transmit it. If we've use the SG already, allocate a new one before
3425 * we copy of the data.
3426 */
3427 if (!pState->CTX_SUFF(pTxSg))
3428 e1kXmitAllocBuf(pState, pState->u16TxPktLen, true /*fExactSize*/, false /*fGso*/);
3429 if (pState->CTX_SUFF(pTxSg))
3430 {
3431 Assert(pState->u16TxPktLen <= pState->CTX_SUFF(pTxSg)->cbAvailable);
3432 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3433 if (pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pState->aTxPacketFallback)
3434 memcpy(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->aTxPacketFallback, pState->u16TxPktLen);
3435 pState->CTX_SUFF(pTxSg)->cbUsed = pState->u16TxPktLen;
3436 pState->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pState->u16TxPktLen;
3437 }
3438 e1kTransmitFrame(pState, fOnWorkerThread);
3439
3440 /* Update Sequence Number */
3441 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
3442 - pState->contextTSE.dw3.u8HDRLEN);
3443 /* Increment IP identification */
3444 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
3445 }
3446}
3447
3448/**
3449 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
3450 * frame.
3451 *
3452 * We construct the frame in the fallback buffer first and the copy it to the SG
3453 * buffer before passing it down to the network driver code.
3454 *
3455 * @returns true if the frame should be transmitted, false if not.
3456 *
3457 * @param pState The device state structure.
3458 * @param pDesc Pointer to the descriptor to transmit.
3459 * @param cbFragment Length of descriptor's buffer.
3460 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3461 * @thread E1000_TX
3462 */
3463static bool e1kFallbackAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
3464{
3465 PPDMSCATTERGATHER pTxSg = pState->CTX_SUFF(pTxSg);
3466 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
3467 Assert(pDesc->data.cmd.fTSE);
3468 Assert(!e1kXmitIsGsoBuf(pTxSg));
3469
3470 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
3471 Assert(u16MaxPktLen != 0);
3472 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
3473
3474 /*
3475 * Carve out segments.
3476 */
3477 do
3478 {
3479 /* Calculate how many bytes we have left in this TCP segment */
3480 uint32_t cb = u16MaxPktLen - pState->u16TxPktLen;
3481 if (cb > cbFragment)
3482 {
3483 /* This descriptor fits completely into current segment */
3484 cb = cbFragment;
3485 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
3486 }
3487 else
3488 {
3489 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
3490 /*
3491 * Rewind the packet tail pointer to the beginning of payload,
3492 * so we continue writing right beyond the header.
3493 */
3494 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
3495 }
3496
3497 pDesc->data.u64BufAddr += cb;
3498 cbFragment -= cb;
3499 } while (cbFragment > 0);
3500
3501 if (pDesc->data.cmd.fEOP)
3502 {
3503 /* End of packet, next segment will contain header. */
3504 if (pState->u32PayRemain != 0)
3505 E1K_INC_CNT32(TSCTFC);
3506 pState->u16TxPktLen = 0;
3507 e1kXmitFreeBuf(pState);
3508 }
3509
3510 return false;
3511}
3512
3513
3514/**
3515 * Add descriptor's buffer to transmit frame.
3516 *
3517 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
3518 * TSE frames we cannot handle as GSO.
3519 *
3520 * @returns true on success, false on failure.
3521 *
3522 * @param pThis The device state structure.
3523 * @param PhysAddr The physical address of the descriptor buffer.
3524 * @param cbFragment Length of descriptor's buffer.
3525 * @thread E1000_TX
3526 */
3527static bool e1kAddToFrame(E1KSTATE *pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
3528{
3529 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
3530 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
3531 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
3532
3533 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
3534 {
3535 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", INSTANCE(pThis), cbNewPkt, E1K_MAX_TX_PKT_SIZE));
3536 return false;
3537 }
3538 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
3539 {
3540 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", INSTANCE(pThis), cbNewPkt, pTxSg->cbAvailable));
3541 return false;
3542 }
3543
3544 if (RT_LIKELY(pTxSg))
3545 {
3546 Assert(pTxSg->cSegs == 1);
3547 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
3548
3549 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
3550 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
3551
3552 pTxSg->cbUsed = cbNewPkt;
3553 }
3554 pThis->u16TxPktLen = cbNewPkt;
3555
3556 return true;
3557}
3558
3559
3560/**
3561 * Write the descriptor back to guest memory and notify the guest.
3562 *
3563 * @param pState The device state structure.
3564 * @param pDesc Pointer to the descriptor have been transmitted.
3565 * @param addr Physical address of the descriptor in guest memory.
3566 * @thread E1000_TX
3567 */
3568static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3569{
3570 /*
3571 * We fake descriptor write-back bursting. Descriptors are written back as they are
3572 * processed.
3573 */
3574 /* Let's pretend we process descriptors. Write back with DD set. */
3575 /*
3576 * Prior to r71586 we tried to accomodate the case when write-back bursts
3577 * are enabled without actually implementing bursting by writing back all
3578 * descriptors, even the ones that do not have RS set. This caused kernel
3579 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
3580 * associated with written back descriptor if it happened to be a context
3581 * descriptor since context descriptors do not have skb associated to them.
3582 * Starting from r71586 we write back only the descriptors with RS set,
3583 * which is a little bit different from what the real hardware does in
3584 * case there is a chain of data descritors where some of them have RS set
3585 * and others do not. It is very uncommon scenario imho.
3586 */
3587 if (pDesc->legacy.cmd.fRS)
3588 {
3589 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
3590 e1kWriteBackDesc(pState, pDesc, addr);
3591 if (pDesc->legacy.cmd.fEOP)
3592 {
3593#ifdef E1K_USE_TX_TIMERS
3594 if (pDesc->legacy.cmd.fIDE)
3595 {
3596 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
3597 //if (pState->fIntRaised)
3598 //{
3599 // /* Interrupt is already pending, no need for timers */
3600 // ICR |= ICR_TXDW;
3601 //}
3602 //else {
3603 /* Arm the timer to fire in TIVD usec (discard .024) */
3604 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
3605# ifndef E1K_NO_TAD
3606 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
3607 E1kLog2(("%s Checking if TAD timer is running\n",
3608 INSTANCE(pState)));
3609 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
3610 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
3611# endif /* E1K_NO_TAD */
3612 }
3613 else
3614 {
3615 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
3616 INSTANCE(pState)));
3617# ifndef E1K_NO_TAD
3618 /* Cancel both timers if armed and fire immediately. */
3619 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
3620# endif /* E1K_NO_TAD */
3621#endif /* E1K_USE_TX_TIMERS */
3622 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
3623 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
3624#ifdef E1K_USE_TX_TIMERS
3625 }
3626#endif /* E1K_USE_TX_TIMERS */
3627 }
3628 }
3629 else
3630 {
3631 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
3632 }
3633}
3634
3635/**
3636 * Process Transmit Descriptor.
3637 *
3638 * E1000 supports three types of transmit descriptors:
3639 * - legacy data descriptors of older format (context-less).
3640 * - data the same as legacy but providing new offloading capabilities.
3641 * - context sets up the context for following data descriptors.
3642 *
3643 * @param pState The device state structure.
3644 * @param pDesc Pointer to descriptor union.
3645 * @param addr Physical address of descriptor in guest memory.
3646 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3647 * @thread E1000_TX
3648 */
3649static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
3650{
3651 uint32_t cbVTag = 0;
3652
3653 e1kPrintTDesc(pState, pDesc, "vvv");
3654
3655#ifdef E1K_USE_TX_TIMERS
3656 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3657#endif /* E1K_USE_TX_TIMERS */
3658
3659 switch (e1kGetDescType(pDesc))
3660 {
3661 case E1K_DTYP_CONTEXT:
3662 if (pDesc->context.dw2.fTSE)
3663 {
3664 pState->contextTSE = pDesc->context;
3665 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3666 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3667 e1kSetupGsoCtx(&pState->GsoCtx, &pDesc->context);
3668 STAM_COUNTER_INC(&pState->StatTxDescCtxTSE);
3669 }
3670 else
3671 {
3672 pState->contextNormal = pDesc->context;
3673 STAM_COUNTER_INC(&pState->StatTxDescCtxNormal);
3674 }
3675 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3676 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3677 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3678 pDesc->context.ip.u8CSS,
3679 pDesc->context.ip.u8CSO,
3680 pDesc->context.ip.u16CSE,
3681 pDesc->context.tu.u8CSS,
3682 pDesc->context.tu.u8CSO,
3683 pDesc->context.tu.u16CSE));
3684 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3685 e1kDescReport(pState, pDesc, addr);
3686 break;
3687
3688 case E1K_DTYP_DATA:
3689 {
3690 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3691 {
3692 E1kLog2(("% Empty data descriptor, skipped.\n", INSTANCE(pState)));
3693 /** @todo Same as legacy when !TSE. See below. */
3694 break;
3695 }
3696 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3697 &pState->StatTxDescTSEData:
3698 &pState->StatTxDescData);
3699 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
3700 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3701
3702 /*
3703 * The last descriptor of non-TSE packet must contain VLE flag.
3704 * TSE packets have VLE flag in the first descriptor. The later
3705 * case is taken care of a bit later when cbVTag gets assigned.
3706 *
3707 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
3708 */
3709 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
3710 {
3711 pState->fVTag = pDesc->data.cmd.fVLE;
3712 pState->u16VTagTCI = pDesc->data.dw3.u16Special;
3713 }
3714 /*
3715 * First fragment: Allocate new buffer and save the IXSM and TXSM
3716 * packet options as these are only valid in the first fragment.
3717 */
3718 if (pState->u16TxPktLen == 0)
3719 {
3720 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3721 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3722 E1kLog2(("%s Saving checksum flags:%s%s; \n", INSTANCE(pState),
3723 pState->fIPcsum ? " IP" : "",
3724 pState->fTCPcsum ? " TCP/UDP" : ""));
3725 if (pDesc->data.cmd.fTSE)
3726 {
3727 /* 2) pDesc->data.cmd.fTSE && pState->u16TxPktLen == 0 */
3728 pState->fVTag = pDesc->data.cmd.fVLE;
3729 pState->u16VTagTCI = pDesc->data.dw3.u16Special;
3730 cbVTag = pState->fVTag ? 4 : 0;
3731 }
3732 else if (pDesc->data.cmd.fEOP)
3733 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
3734 else
3735 cbVTag = 4;
3736 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", INSTANCE(pState), cbVTag));
3737 if (e1kCanDoGso(&pState->GsoCtx, &pDesc->data, &pState->contextTSE))
3738 e1kXmitAllocBuf(pState, pState->contextTSE.dw2.u20PAYLEN + pState->contextTSE.dw3.u8HDRLEN + cbVTag,
3739 true /*fExactSize*/, true /*fGso*/);
3740 else
3741 e1kXmitAllocBuf(pState, pState->contextTSE.dw3.u16MSS + pState->contextTSE.dw3.u8HDRLEN + cbVTag,
3742 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
3743 /** @todo Is there any way to indicating errors other than collisions? Like
3744 * VERR_NET_DOWN. */
3745 /*
3746 * If allocate a bigger buffer we need to move pvSeg
3747 * accordingly, leaving room in front.
3748 *
3749 * Note that e1kTransmitFrame not necessarily moves it back. In
3750 * case of multi-descriptor packet with TSE we won't know if
3751 * VLAN tag has to be inserted until the last descriptor is
3752 * fetched. If it has not we simply leave pvSeg as it is (+4)
3753 * and send the packet without inserting VLAN tag.
3754 */
3755 if (cbVTag)
3756 {
3757 Assert(cbVTag == 4);
3758 pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg =
3759 (uint8_t*)(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg) + cbVTag;
3760 }
3761 }
3762
3763 /*
3764 * Add the descriptor data to the frame. If the frame is complete,
3765 * transmit it and reset the u16TxPktLen field.
3766 */
3767 if (e1kXmitIsGsoBuf(pState->CTX_SUFF(pTxSg)))
3768 {
3769 STAM_COUNTER_INC(&pState->StatTxPathGSO);
3770 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3771 if (pDesc->data.cmd.fEOP)
3772 {
3773 if ( fRc
3774 && pState->CTX_SUFF(pTxSg)
3775 && pState->CTX_SUFF(pTxSg)->cbUsed == (size_t)pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN)
3776 {
3777 e1kTransmitFrame(pState, fOnWorkerThread);
3778 E1K_INC_CNT32(TSCTC);
3779 }
3780 else
3781 {
3782 if (fRc)
3783 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , INSTANCE(pState),
3784 pState->CTX_SUFF(pTxSg), pState->CTX_SUFF(pTxSg) ? pState->CTX_SUFF(pTxSg)->cbUsed : 0,
3785 pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN));
3786 e1kXmitFreeBuf(pState);
3787 E1K_INC_CNT32(TSCTFC);
3788 }
3789 pState->u16TxPktLen = 0;
3790 }
3791 }
3792 else if (!pDesc->data.cmd.fTSE)
3793 {
3794 STAM_COUNTER_INC(&pState->StatTxPathRegular);
3795 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3796 if (pDesc->data.cmd.fEOP)
3797 {
3798 if (fRc && pState->CTX_SUFF(pTxSg))
3799 {
3800 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3801 if (pState->fIPcsum)
3802 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3803 pState->contextNormal.ip.u8CSO,
3804 pState->contextNormal.ip.u8CSS,
3805 pState->contextNormal.ip.u16CSE);
3806 if (pState->fTCPcsum)
3807 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3808 pState->contextNormal.tu.u8CSO,
3809 pState->contextNormal.tu.u8CSS,
3810 pState->contextNormal.tu.u16CSE);
3811 e1kTransmitFrame(pState, fOnWorkerThread);
3812 }
3813 else
3814 e1kXmitFreeBuf(pState);
3815 pState->u16TxPktLen = 0;
3816 }
3817 }
3818 else
3819 {
3820 STAM_COUNTER_INC(&pState->StatTxPathFallback);
3821 e1kFallbackAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
3822 }
3823
3824 e1kDescReport(pState, pDesc, addr);
3825 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3826 break;
3827 }
3828
3829 case E1K_DTYP_LEGACY:
3830 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3831 {
3832 E1kLog(("%s Empty legacy descriptor, skipped.\n", INSTANCE(pState)));
3833 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
3834 break;
3835 }
3836 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3837 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatTransmit), a);
3838
3839 /* First fragment: allocate new buffer. */
3840 if (pState->u16TxPktLen == 0)
3841 {
3842 if (pDesc->legacy.cmd.fEOP)
3843 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
3844 else
3845 cbVTag = 4;
3846 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", INSTANCE(pState), cbVTag));
3847 /** @todo reset status bits? */
3848 e1kXmitAllocBuf(pState, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
3849 /** @todo Is there any way to indicating errors other than collisions? Like
3850 * VERR_NET_DOWN. */
3851 /*
3852 * If allocate a bigger buffer we need to move pvSeg
3853 * accordingly, leaving room in front. Also see the comment
3854 * in data descriptor processing.
3855 */
3856 if (cbVTag)
3857 {
3858 Assert(cbVTag == 4);
3859 pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg =
3860 (uint8_t*)(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg) + cbVTag;
3861 }
3862 }
3863
3864 /* Add fragment to frame. */
3865 if (e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
3866 {
3867 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3868
3869 /* Last fragment: Transmit and reset the packet storage counter. */
3870 if (pDesc->legacy.cmd.fEOP)
3871 {
3872 pState->fVTag = pDesc->legacy.cmd.fVLE;
3873 pState->u16VTagTCI = pDesc->legacy.dw3.u16Special;
3874 /** @todo Offload processing goes here. */
3875 e1kTransmitFrame(pState, fOnWorkerThread);
3876 pState->u16TxPktLen = 0;
3877 }
3878 }
3879 /* Last fragment + failure: free the buffer and reset the storage counter. */
3880 else if (pDesc->legacy.cmd.fEOP)
3881 {
3882 e1kXmitFreeBuf(pState);
3883 pState->u16TxPktLen = 0;
3884 }
3885
3886 e1kDescReport(pState, pDesc, addr);
3887 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3888 break;
3889
3890 default:
3891 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3892 INSTANCE(pState), e1kGetDescType(pDesc)));
3893 break;
3894 }
3895}
3896
3897
3898/**
3899 * Transmit pending descriptors.
3900 *
3901 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
3902 *
3903 * @param pState The E1000 state.
3904 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
3905 */
3906static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread)
3907{
3908 int rc;
3909
3910 /*
3911 * Grab the xmit lock of the driver as well as the E1K device state.
3912 */
3913 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3914 if (pDrv)
3915 {
3916 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
3917 if (RT_FAILURE(rc))
3918 return rc;
3919 }
3920 rc = e1kMutexAcquire(pState, VERR_TRY_AGAIN, RT_SRC_POS);
3921 if (RT_SUCCESS(rc))
3922 {
3923 /*
3924 * Process all pending descriptors.
3925 * Note! Do not process descriptors in locked state
3926 */
3927 while (TDH != TDT && !pState->fLocked)
3928 {
3929 E1KTXDESC desc;
3930 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3931 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3932
3933 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3934 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc), fOnWorkerThread);
3935 if (++TDH * sizeof(desc) >= TDLEN)
3936 TDH = 0;
3937
3938 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3939 {
3940 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3941 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3942 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3943 }
3944
3945 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatTransmit), a);
3946 }
3947
3948 /// @todo: uncomment: pState->uStatIntTXQE++;
3949 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3950
3951 /*
3952 * Release the locks.
3953 */
3954 e1kMutexRelease(pState);
3955 }
3956 if (pDrv)
3957 pDrv->pfnEndXmit(pDrv);
3958 return rc;
3959}
3960
3961#ifdef IN_RING3
3962
3963/**
3964 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
3965 */
3966static DECLCALLBACK(void) e1kNetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
3967{
3968 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
3969 e1kXmitPending(pState, true /*fOnWorkerThread*/);
3970}
3971
3972/**
3973 * Callback for consuming from transmit queue. It gets called in R3 whenever
3974 * we enqueue something in R0/GC.
3975 *
3976 * @returns true
3977 * @param pDevIns Pointer to device instance structure.
3978 * @param pItem Pointer to the element being dequeued (not used).
3979 * @thread ???
3980 */
3981static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3982{
3983 NOREF(pItem);
3984 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3985 E1kLog2(("%s e1kTxQueueConsumer:\n", INSTANCE(pState)));
3986
3987 int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
3988 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3989
3990 return true;
3991}
3992
3993/**
3994 * Handler for the wakeup signaller queue.
3995 */
3996static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3997{
3998 e1kWakeupReceive(pDevIns);
3999 return true;
4000}
4001
4002#endif /* IN_RING3 */
4003
4004/**
4005 * Write handler for Transmit Descriptor Tail register.
4006 *
4007 * @param pState The device state structure.
4008 * @param offset Register offset in memory-mapped frame.
4009 * @param index Register index in register array.
4010 * @param value The value to store.
4011 * @param mask Used to implement partial writes (8 and 16-bit).
4012 * @thread EMT
4013 */
4014static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4015{
4016 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
4017 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4018 return rc;
4019 rc = e1kRegWriteDefault(pState, offset, index, value);
4020
4021 /* All descriptors starting with head and not including tail belong to us. */
4022 /* Process them. */
4023 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
4024 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
4025
4026 /* Ignore TDT writes when the link is down. */
4027 if (TDH != TDT && (STATUS & STATUS_LU))
4028 {
4029 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
4030 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
4031 INSTANCE(pState), e1kGetTxLen(pState)));
4032 e1kCsTxLeave(pState);
4033
4034 /* Transmit pending packets if possible, defer it if we cannot do it
4035 in the current context. */
4036# ifndef IN_RING3
4037 if (!pState->CTX_SUFF(pDrv))
4038 {
4039 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
4040 if (RT_UNLIKELY(pItem))
4041 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
4042 }
4043 else
4044# endif
4045 {
4046 rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
4047 if (rc == VERR_TRY_AGAIN)
4048 rc = VINF_SUCCESS;
4049 AssertRC(rc);
4050 }
4051 }
4052 else
4053 e1kCsTxLeave(pState);
4054
4055 return rc;
4056}
4057
4058/**
4059 * Write handler for Multicast Table Array registers.
4060 *
4061 * @param pState The device state structure.
4062 * @param offset Register offset in memory-mapped frame.
4063 * @param index Register index in register array.
4064 * @param value The value to store.
4065 * @thread EMT
4066 */
4067static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4068{
4069 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
4070 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
4071
4072 return VINF_SUCCESS;
4073}
4074
4075/**
4076 * Read handler for Multicast Table Array registers.
4077 *
4078 * @returns VBox status code.
4079 *
4080 * @param pState The device state structure.
4081 * @param offset Register offset in memory-mapped frame.
4082 * @param index Register index in register array.
4083 * @thread EMT
4084 */
4085static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4086{
4087 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
4088 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
4089
4090 return VINF_SUCCESS;
4091}
4092
4093/**
4094 * Write handler for Receive Address registers.
4095 *
4096 * @param pState The device state structure.
4097 * @param offset Register offset in memory-mapped frame.
4098 * @param index Register index in register array.
4099 * @param value The value to store.
4100 * @thread EMT
4101 */
4102static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4103{
4104 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
4105 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
4106
4107 return VINF_SUCCESS;
4108}
4109
4110/**
4111 * Read handler for Receive Address registers.
4112 *
4113 * @returns VBox status code.
4114 *
4115 * @param pState The device state structure.
4116 * @param offset Register offset in memory-mapped frame.
4117 * @param index Register index in register array.
4118 * @thread EMT
4119 */
4120static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4121{
4122 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
4123 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
4124
4125 return VINF_SUCCESS;
4126}
4127
4128/**
4129 * Write handler for VLAN Filter Table Array registers.
4130 *
4131 * @param pState The device state structure.
4132 * @param offset Register offset in memory-mapped frame.
4133 * @param index Register index in register array.
4134 * @param value The value to store.
4135 * @thread EMT
4136 */
4137static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4138{
4139 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
4140 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
4141
4142 return VINF_SUCCESS;
4143}
4144
4145/**
4146 * Read handler for VLAN Filter Table Array registers.
4147 *
4148 * @returns VBox status code.
4149 *
4150 * @param pState The device state structure.
4151 * @param offset Register offset in memory-mapped frame.
4152 * @param index Register index in register array.
4153 * @thread EMT
4154 */
4155static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4156{
4157 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
4158 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
4159
4160 return VINF_SUCCESS;
4161}
4162
4163/**
4164 * Read handler for unimplemented registers.
4165 *
4166 * Merely reports reads from unimplemented registers.
4167 *
4168 * @returns VBox status code.
4169 *
4170 * @param pState The device state structure.
4171 * @param offset Register offset in memory-mapped frame.
4172 * @param index Register index in register array.
4173 * @thread EMT
4174 */
4175
4176static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4177{
4178 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
4179 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4180 *pu32Value = 0;
4181
4182 return VINF_SUCCESS;
4183}
4184
4185/**
4186 * Default register read handler with automatic clear operation.
4187 *
4188 * Retrieves the value of register from register array in device state structure.
4189 * Then resets all bits.
4190 *
4191 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4192 * done in the caller.
4193 *
4194 * @returns VBox status code.
4195 *
4196 * @param pState The device state structure.
4197 * @param offset Register offset in memory-mapped frame.
4198 * @param index Register index in register array.
4199 * @thread EMT
4200 */
4201
4202static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4203{
4204 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4205 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
4206 pState->auRegs[index] = 0;
4207
4208 return rc;
4209}
4210
4211/**
4212 * Default register read handler.
4213 *
4214 * Retrieves the value of register from register array in device state structure.
4215 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
4216 *
4217 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4218 * done in the caller.
4219 *
4220 * @returns VBox status code.
4221 *
4222 * @param pState The device state structure.
4223 * @param offset Register offset in memory-mapped frame.
4224 * @param index Register index in register array.
4225 * @thread EMT
4226 */
4227
4228static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4229{
4230 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4231 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
4232
4233 return VINF_SUCCESS;
4234}
4235
4236/**
4237 * Write handler for unimplemented registers.
4238 *
4239 * Merely reports writes to unimplemented registers.
4240 *
4241 * @param pState The device state structure.
4242 * @param offset Register offset in memory-mapped frame.
4243 * @param index Register index in register array.
4244 * @param value The value to store.
4245 * @thread EMT
4246 */
4247
4248 static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4249{
4250 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
4251 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4252
4253 return VINF_SUCCESS;
4254}
4255
4256/**
4257 * Default register write handler.
4258 *
4259 * Stores the value to the register array in device state structure. Only bits
4260 * corresponding to 1s both in 'writable' and 'mask' will be stored.
4261 *
4262 * @returns VBox status code.
4263 *
4264 * @param pState The device state structure.
4265 * @param offset Register offset in memory-mapped frame.
4266 * @param index Register index in register array.
4267 * @param value The value to store.
4268 * @param mask Used to implement partial writes (8 and 16-bit).
4269 * @thread EMT
4270 */
4271
4272static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4273{
4274 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4275 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
4276 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
4277
4278 return VINF_SUCCESS;
4279}
4280
4281/**
4282 * Search register table for matching register.
4283 *
4284 * @returns Index in the register table or -1 if not found.
4285 *
4286 * @param pState The device state structure.
4287 * @param uOffset Register offset in memory-mapped region.
4288 * @thread EMT
4289 */
4290static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
4291{
4292 int index;
4293
4294 for (index = 0; index < E1K_NUM_OF_REGS; index++)
4295 {
4296 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
4297 {
4298 return index;
4299 }
4300 }
4301
4302 return -1;
4303}
4304
4305/**
4306 * Handle register read operation.
4307 *
4308 * Looks up and calls appropriate handler.
4309 *
4310 * @returns VBox status code.
4311 *
4312 * @param pState The device state structure.
4313 * @param uOffset Register offset in memory-mapped frame.
4314 * @param pv Where to store the result.
4315 * @param cb Number of bytes to read.
4316 * @thread EMT
4317 */
4318static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
4319{
4320 uint32_t u32 = 0;
4321 uint32_t mask = 0;
4322 uint32_t shift;
4323 int rc = VINF_SUCCESS;
4324 int index = e1kRegLookup(pState, uOffset);
4325 const char *szInst = INSTANCE(pState);
4326#ifdef DEBUG
4327 char buf[9];
4328#endif
4329
4330 /*
4331 * From the spec:
4332 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4333 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4334 */
4335
4336 /*
4337 * To be able to write bytes and short word we convert them
4338 * to properly shifted 32-bit words and masks. The idea is
4339 * to keep register-specific handlers simple. Most accesses
4340 * will be 32-bit anyway.
4341 */
4342 switch (cb)
4343 {
4344 case 1: mask = 0x000000FF; break;
4345 case 2: mask = 0x0000FFFF; break;
4346 case 4: mask = 0xFFFFFFFF; break;
4347 default:
4348 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4349 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
4350 szInst, uOffset, cb);
4351 }
4352 if (index != -1)
4353 {
4354 if (s_e1kRegMap[index].readable)
4355 {
4356 /* Make the mask correspond to the bits we are about to read. */
4357 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
4358 mask <<= shift;
4359 if (!mask)
4360 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4361 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
4362 szInst, uOffset, cb);
4363 /*
4364 * Read it. Pass the mask so the handler knows what has to be read.
4365 * Mask out irrelevant bits.
4366 */
4367#ifdef E1K_GLOBAL_MUTEX
4368 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
4369#else
4370 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4371#endif
4372 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4373 return rc;
4374 //pState->fDelayInts = false;
4375 //pState->iStatIntLost += pState->iStatIntLostOne;
4376 //pState->iStatIntLostOne = 0;
4377 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32);
4378 u32 &= mask;
4379 //e1kCsLeave(pState);
4380 e1kMutexRelease(pState);
4381 E1kLog2(("%s At %08X read %s from %s (%s)\n",
4382 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4383 /* Shift back the result. */
4384 u32 >>= shift;
4385 }
4386 else
4387 {
4388 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
4389 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4390 }
4391 }
4392 else
4393 {
4394 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
4395 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
4396 }
4397
4398 memcpy(pv, &u32, cb);
4399 return rc;
4400}
4401
4402/**
4403 * Handle register write operation.
4404 *
4405 * Looks up and calls appropriate handler.
4406 *
4407 * @returns VBox status code.
4408 *
4409 * @param pState The device state structure.
4410 * @param uOffset Register offset in memory-mapped frame.
4411 * @param pv Where to fetch the value.
4412 * @param cb Number of bytes to write.
4413 * @thread EMT
4414 */
4415static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void const *pv, unsigned cb)
4416{
4417 int rc = VINF_SUCCESS;
4418 int index = e1kRegLookup(pState, uOffset);
4419 uint32_t u32;
4420
4421 /*
4422 * From the spec:
4423 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4424 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4425 */
4426
4427 if (cb != 4)
4428 {
4429 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
4430 INSTANCE(pState), uOffset, cb));
4431 return VINF_SUCCESS;
4432 }
4433 if (uOffset & 3)
4434 {
4435 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
4436 INSTANCE(pState), uOffset, cb));
4437 return VINF_SUCCESS;
4438 }
4439 u32 = *(uint32_t*)pv;
4440 if (index != -1)
4441 {
4442 if (s_e1kRegMap[index].writable)
4443 {
4444 /*
4445 * Write it. Pass the mask so the handler knows what has to be written.
4446 * Mask out irrelevant bits.
4447 */
4448 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
4449 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4450#ifdef E1K_GLOBAL_MUTEX
4451 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
4452#else
4453 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4454#endif
4455 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4456 return rc;
4457 //pState->fDelayInts = false;
4458 //pState->iStatIntLost += pState->iStatIntLostOne;
4459 //pState->iStatIntLostOne = 0;
4460 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
4461 //e1kCsLeave(pState);
4462 e1kMutexRelease(pState);
4463 }
4464 else
4465 {
4466 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
4467 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4468 }
4469 }
4470 else
4471 {
4472 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
4473 INSTANCE(pState), uOffset, u32));
4474 }
4475 return rc;
4476}
4477
4478/**
4479 * I/O handler for memory-mapped read operations.
4480 *
4481 * @returns VBox status code.
4482 *
4483 * @param pDevIns The device instance.
4484 * @param pvUser User argument.
4485 * @param GCPhysAddr Physical address (in GC) where the read starts.
4486 * @param pv Where to store the result.
4487 * @param cb Number of bytes read.
4488 * @thread EMT
4489 */
4490PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
4491 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4492{
4493 NOREF(pvUser);
4494 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4495 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4496 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIORead), a);
4497
4498 Assert(uOffset < E1K_MM_SIZE);
4499
4500 int rc = e1kRegRead(pState, uOffset, pv, cb);
4501 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIORead), a);
4502 return rc;
4503}
4504
4505/**
4506 * Memory mapped I/O Handler for write operations.
4507 *
4508 * @returns VBox status code.
4509 *
4510 * @param pDevIns The device instance.
4511 * @param pvUser User argument.
4512 * @param GCPhysAddr Physical address (in GC) where the read starts.
4513 * @param pv Where to fetch the value.
4514 * @param cb Number of bytes to write.
4515 * @thread EMT
4516 */
4517PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
4518 RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4519{
4520 NOREF(pvUser);
4521 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4522 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4523 int rc;
4524 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
4525
4526 Assert(uOffset < E1K_MM_SIZE);
4527 if (cb != 4)
4528 {
4529 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
4530 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
4531 }
4532 else
4533 rc = e1kRegWrite(pState, uOffset, pv, cb);
4534
4535 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatMMIOWrite), a);
4536 return rc;
4537}
4538
4539/**
4540 * Port I/O Handler for IN operations.
4541 *
4542 * @returns VBox status code.
4543 *
4544 * @param pDevIns The device instance.
4545 * @param pvUser Pointer to the device state structure.
4546 * @param port Port number used for the IN operation.
4547 * @param pu32 Where to store the result.
4548 * @param cb Number of bytes read.
4549 * @thread EMT
4550 */
4551PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
4552 RTIOPORT port, uint32_t *pu32, unsigned cb)
4553{
4554 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4555 int rc = VINF_SUCCESS;
4556 const char *szInst = INSTANCE(pState);
4557 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIORead), a);
4558
4559 port -= pState->addrIOPort;
4560 if (cb != 4)
4561 {
4562 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
4563 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4564 }
4565 else
4566 switch (port)
4567 {
4568 case 0x00: /* IOADDR */
4569 *pu32 = pState->uSelectedReg;
4570 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4571 break;
4572 case 0x04: /* IODATA */
4573 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
4574 /** @todo wrong return code triggers assertions in the debug build; fix please */
4575 if (rc == VINF_IOM_HC_MMIO_READ)
4576 rc = VINF_IOM_HC_IOPORT_READ;
4577
4578 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4579 break;
4580 default:
4581 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
4582 //*pRC = VERR_IOM_IOPORT_UNUSED;
4583 }
4584
4585 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIORead), a);
4586 return rc;
4587}
4588
4589
4590/**
4591 * Port I/O Handler for OUT operations.
4592 *
4593 * @returns VBox status code.
4594 *
4595 * @param pDevIns The device instance.
4596 * @param pvUser User argument.
4597 * @param Port Port number used for the IN operation.
4598 * @param u32 The value to output.
4599 * @param cb The value size in bytes.
4600 * @thread EMT
4601 */
4602PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
4603 RTIOPORT port, uint32_t u32, unsigned cb)
4604{
4605 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4606 int rc = VINF_SUCCESS;
4607 const char *szInst = INSTANCE(pState);
4608 STAM_PROFILE_ADV_START(&pState->CTX_SUFF_Z(StatIOWrite), a);
4609
4610 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
4611 if (cb != 4)
4612 {
4613 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
4614 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4615 }
4616 else
4617 {
4618 port -= pState->addrIOPort;
4619 switch (port)
4620 {
4621 case 0x00: /* IOADDR */
4622 pState->uSelectedReg = u32;
4623 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
4624 break;
4625 case 0x04: /* IODATA */
4626 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
4627 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
4628 /** @todo wrong return code triggers assertions in the debug build; fix please */
4629 if (rc == VINF_IOM_HC_MMIO_WRITE)
4630 rc = VINF_IOM_HC_IOPORT_WRITE;
4631 break;
4632 default:
4633 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
4634 /** @todo Do we need to return an error here?
4635 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
4636 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
4637 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
4638 }
4639 }
4640
4641 STAM_PROFILE_ADV_STOP(&pState->CTX_SUFF_Z(StatIOWrite), a);
4642 return rc;
4643}
4644
4645#ifdef IN_RING3
4646/**
4647 * Dump complete device state to log.
4648 *
4649 * @param pState Pointer to device state.
4650 */
4651static void e1kDumpState(E1KSTATE *pState)
4652{
4653 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
4654 {
4655 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
4656 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
4657 }
4658#ifdef E1K_INT_STATS
4659 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
4660 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
4661 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
4662 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
4663 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
4664 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
4665 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
4666 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
4667 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
4668 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
4669 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
4670 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
4671 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
4672 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
4673 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
4674 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
4675 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
4676 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
4677 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
4678 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
4679 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
4680 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
4681 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
4682 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
4683 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
4684 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
4685 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
4686#endif /* E1K_INT_STATS */
4687}
4688
4689/**
4690 * Map PCI I/O region.
4691 *
4692 * @return VBox status code.
4693 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4694 * @param iRegion The region number.
4695 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4696 * I/O port, else it's a physical address.
4697 * This address is *NOT* relative to pci_mem_base like earlier!
4698 * @param cb Region size.
4699 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4700 * @thread EMT
4701 */
4702static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
4703 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4704{
4705 int rc;
4706 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
4707
4708 switch (enmType)
4709 {
4710 case PCI_ADDRESS_SPACE_IO:
4711 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
4712 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4713 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
4714 if (RT_FAILURE(rc))
4715 break;
4716 if (pState->fR0Enabled)
4717 {
4718 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4719 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4720 if (RT_FAILURE(rc))
4721 break;
4722 }
4723 if (pState->fGCEnabled)
4724 {
4725 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4726 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4727 }
4728 break;
4729 case PCI_ADDRESS_SPACE_MEM:
4730 pState->addrMMReg = GCPhysAddress;
4731 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4732 IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4733 e1kMMIOWrite, e1kMMIORead, "E1000");
4734 if (pState->fR0Enabled)
4735 {
4736 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4737 "e1kMMIOWrite", "e1kMMIORead");
4738 if (RT_FAILURE(rc))
4739 break;
4740 }
4741 if (pState->fGCEnabled)
4742 {
4743 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4744 "e1kMMIOWrite", "e1kMMIORead");
4745 }
4746 break;
4747 default:
4748 /* We should never get here */
4749 AssertMsgFailed(("Invalid PCI address space param in map callback"));
4750 rc = VERR_INTERNAL_ERROR;
4751 break;
4752 }
4753 return rc;
4754}
4755
4756/**
4757 * Check if the device can receive data now.
4758 * This must be called before the pfnRecieve() method is called.
4759 *
4760 * @returns Number of bytes the device can receive.
4761 * @param pInterface Pointer to the interface structure containing the called function pointer.
4762 * @thread EMT
4763 */
4764static int e1kCanReceive(E1KSTATE *pState)
4765{
4766 size_t cb;
4767
4768 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
4769 return VERR_NET_NO_BUFFER_SPACE;
4770 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
4771 return VERR_NET_NO_BUFFER_SPACE;
4772
4773 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
4774 {
4775 E1KRXDESC desc;
4776 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
4777 &desc, sizeof(desc));
4778 if (desc.status.fDD)
4779 cb = 0;
4780 else
4781 cb = pState->u16RxBSize;
4782 }
4783 else if (RDH < RDT)
4784 cb = (RDT - RDH) * pState->u16RxBSize;
4785 else if (RDH > RDT)
4786 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
4787 else
4788 {
4789 cb = 0;
4790 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
4791 }
4792 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
4793 INSTANCE(pState), RDH, RDT, RDLEN, pState->u16RxBSize, cb));
4794
4795 e1kCsRxLeave(pState);
4796 e1kMutexRelease(pState);
4797 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
4798}
4799
4800/**
4801 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
4802 */
4803static DECLCALLBACK(int) e1kNetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4804{
4805 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
4806 int rc = e1kCanReceive(pState);
4807
4808 if (RT_SUCCESS(rc))
4809 return VINF_SUCCESS;
4810 if (RT_UNLIKELY(cMillies == 0))
4811 return VERR_NET_NO_BUFFER_SPACE;
4812
4813 rc = VERR_INTERRUPTED;
4814 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
4815 STAM_PROFILE_START(&pState->StatRxOverflow, a);
4816 VMSTATE enmVMState;
4817 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pState->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
4818 || enmVMState == VMSTATE_RUNNING_LS))
4819 {
4820 int rc2 = e1kCanReceive(pState);
4821 if (RT_SUCCESS(rc2))
4822 {
4823 rc = VINF_SUCCESS;
4824 break;
4825 }
4826 E1kLogRel(("E1000 e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4827 cMillies));
4828 E1kLog(("%s e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4829 INSTANCE(pState), cMillies));
4830 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
4831 }
4832 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
4833 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
4834
4835 return rc;
4836}
4837
4838
4839/**
4840 * Matches the packet addresses against Receive Address table. Looks for
4841 * exact matches only.
4842 *
4843 * @returns true if address matches.
4844 * @param pState Pointer to the state structure.
4845 * @param pvBuf The ethernet packet.
4846 * @param cb Number of bytes available in the packet.
4847 * @thread EMT
4848 */
4849static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4850{
4851 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4852 {
4853 E1KRAELEM* ra = pState->aRecAddr.array + i;
4854
4855 /* Valid address? */
4856 if (ra->ctl & RA_CTL_AV)
4857 {
4858 Assert((ra->ctl & RA_CTL_AS) < 2);
4859 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4860 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4861 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4862 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4863 /*
4864 * Address Select:
4865 * 00b = Destination address
4866 * 01b = Source address
4867 * 10b = Reserved
4868 * 11b = Reserved
4869 * Since ethernet header is (DA, SA, len) we can use address
4870 * select as index.
4871 */
4872 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4873 ra->addr, sizeof(ra->addr)) == 0)
4874 return true;
4875 }
4876 }
4877
4878 return false;
4879}
4880
4881/**
4882 * Matches the packet addresses against Multicast Table Array.
4883 *
4884 * @remarks This is imperfect match since it matches not exact address but
4885 * a subset of addresses.
4886 *
4887 * @returns true if address matches.
4888 * @param pState Pointer to the state structure.
4889 * @param pvBuf The ethernet packet.
4890 * @param cb Number of bytes available in the packet.
4891 * @thread EMT
4892 */
4893static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4894{
4895 /* Get bits 32..47 of destination address */
4896 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4897
4898 unsigned offset = GET_BITS(RCTL, MO);
4899 /*
4900 * offset means:
4901 * 00b = bits 36..47
4902 * 01b = bits 35..46
4903 * 10b = bits 34..45
4904 * 11b = bits 32..43
4905 */
4906 if (offset < 3)
4907 u16Bit = u16Bit >> (4 - offset);
4908 return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
4909}
4910
4911/**
4912 * Determines if the packet is to be delivered to upper layer. The following
4913 * filters supported:
4914 * - Exact Unicast/Multicast
4915 * - Promiscuous Unicast/Multicast
4916 * - Multicast
4917 * - VLAN
4918 *
4919 * @returns true if packet is intended for this node.
4920 * @param pState Pointer to the state structure.
4921 * @param pvBuf The ethernet packet.
4922 * @param cb Number of bytes available in the packet.
4923 * @param pStatus Bit field to store status bits.
4924 * @thread EMT
4925 */
4926static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4927{
4928 Assert(cb > 14);
4929 /* Assume that we fail to pass exact filter. */
4930 pStatus->fPIF = false;
4931 pStatus->fVP = false;
4932 /* Discard oversized packets */
4933 if (cb > E1K_MAX_RX_PKT_SIZE)
4934 {
4935 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4936 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4937 E1K_INC_CNT32(ROC);
4938 return false;
4939 }
4940 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4941 {
4942 /* When long packet reception is disabled packets over 1522 are discarded */
4943 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4944 INSTANCE(pState), cb));
4945 E1K_INC_CNT32(ROC);
4946 return false;
4947 }
4948
4949 /* Is VLAN filtering enabled? */
4950 if (RCTL & RCTL_VFE)
4951 {
4952 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4953 /* Compare TPID with VLAN Ether Type */
4954 if (RT_BE2H_U16(u16Ptr[6]) == VET)
4955 {
4956 pStatus->fVP = true;
4957 /* It is 802.1q packet indeed, let's filter by VID */
4958 if (RCTL & RCTL_CFIEN)
4959 {
4960 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", INSTANCE(pState),
4961 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
4962 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
4963 !!(RCTL & RCTL_CFI)));
4964 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
4965 {
4966 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
4967 INSTANCE(pState), E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
4968 return false;
4969 }
4970 }
4971 else
4972 E1kLog3(("%s VLAN filter: VLAN=%d\n", INSTANCE(pState),
4973 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
4974 if (!ASMBitTest(pState->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
4975 {
4976 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
4977 INSTANCE(pState), E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
4978 return false;
4979 }
4980 }
4981 }
4982 /* Broadcast filtering */
4983 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4984 return true;
4985 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4986 if (e1kIsMulticast(pvBuf))
4987 {
4988 /* Is multicast promiscuous enabled? */
4989 if (RCTL & RCTL_MPE)
4990 return true;
4991 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4992 /* Try perfect matches first */
4993 if (e1kPerfectMatch(pState, pvBuf))
4994 {
4995 pStatus->fPIF = true;
4996 return true;
4997 }
4998 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4999 if (e1kImperfectMatch(pState, pvBuf))
5000 return true;
5001 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
5002 }
5003 else {
5004 /* Is unicast promiscuous enabled? */
5005 if (RCTL & RCTL_UPE)
5006 return true;
5007 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
5008 if (e1kPerfectMatch(pState, pvBuf))
5009 {
5010 pStatus->fPIF = true;
5011 return true;
5012 }
5013 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
5014 }
5015 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
5016 return false;
5017}
5018
5019/**
5020 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
5021 */
5022static DECLCALLBACK(int) e1kNetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
5023{
5024 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
5025 int rc = VINF_SUCCESS;
5026
5027 /*
5028 * Drop packets if the VM is not running yet/anymore.
5029 */
5030 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pState));
5031 if ( enmVMState != VMSTATE_RUNNING
5032 && enmVMState != VMSTATE_RUNNING_LS)
5033 {
5034 E1kLog(("%s Dropping incoming packet as VM is not running.\n", INSTANCE(pState)));
5035 return VINF_SUCCESS;
5036 }
5037
5038 /* Discard incoming packets in locked state */
5039 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
5040 {
5041 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
5042 return VINF_SUCCESS;
5043 }
5044
5045 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
5046 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5047 if (RT_LIKELY(rc == VINF_SUCCESS))
5048 {
5049 //if (!e1kCsEnter(pState, RT_SRC_POS))
5050 // return VERR_PERMISSION_DENIED;
5051
5052 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
5053
5054 /* Update stats */
5055 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
5056 {
5057 E1K_INC_CNT32(TPR);
5058 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
5059 e1kCsLeave(pState);
5060 }
5061 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
5062 E1KRXDST status;
5063 RT_ZERO(status);
5064 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
5065 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
5066 if (fPassed)
5067 {
5068 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
5069 }
5070 //e1kCsLeave(pState);
5071 e1kMutexRelease(pState);
5072 }
5073 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
5074
5075 return rc;
5076}
5077
5078/**
5079 * Gets the pointer to the status LED of a unit.
5080 *
5081 * @returns VBox status code.
5082 * @param pInterface Pointer to the interface structure.
5083 * @param iLUN The unit which status LED we desire.
5084 * @param ppLed Where to store the LED pointer.
5085 * @thread EMT
5086 */
5087static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5088{
5089 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
5090 int rc = VERR_PDM_LUN_NOT_FOUND;
5091
5092 if (iLUN == 0)
5093 {
5094 *ppLed = &pState->led;
5095 rc = VINF_SUCCESS;
5096 }
5097 return rc;
5098}
5099
5100/**
5101 * Gets the current Media Access Control (MAC) address.
5102 *
5103 * @returns VBox status code.
5104 * @param pInterface Pointer to the interface structure containing the called function pointer.
5105 * @param pMac Where to store the MAC address.
5106 * @thread EMT
5107 */
5108static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
5109{
5110 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
5111 pState->eeprom.getMac(pMac);
5112 return VINF_SUCCESS;
5113}
5114
5115
5116/**
5117 * Gets the new link state.
5118 *
5119 * @returns The current link state.
5120 * @param pInterface Pointer to the interface structure containing the called function pointer.
5121 * @thread EMT
5122 */
5123static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
5124{
5125 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
5126 if (STATUS & STATUS_LU)
5127 return PDMNETWORKLINKSTATE_UP;
5128 return PDMNETWORKLINKSTATE_DOWN;
5129}
5130
5131
5132/**
5133 * Sets the new link state.
5134 *
5135 * @returns VBox status code.
5136 * @param pInterface Pointer to the interface structure containing the called function pointer.
5137 * @param enmState The new link state
5138 * @thread EMT
5139 */
5140static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
5141{
5142 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
5143 bool fOldUp = !!(STATUS & STATUS_LU);
5144 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
5145
5146 if ( fNewUp != fOldUp
5147 || (!fNewUp && pState->fCableConnected)) /* old state was connected but STATUS not
5148 * yet written by guest */
5149 {
5150 if (fNewUp)
5151 {
5152 E1kLog(("%s Link will be up in approximately 5 secs\n", INSTANCE(pState)));
5153 pState->fCableConnected = true;
5154 STATUS &= ~STATUS_LU;
5155 Phy::setLinkStatus(&pState->phy, false);
5156 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5157 /* Restore the link back in 5 second. */
5158 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5159 }
5160 else
5161 {
5162 E1kLog(("%s Link is down\n", INSTANCE(pState)));
5163 pState->fCableConnected = false;
5164 STATUS &= ~STATUS_LU;
5165 Phy::setLinkStatus(&pState->phy, false);
5166 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5167 }
5168 if (pState->pDrvR3)
5169 pState->pDrvR3->pfnNotifyLinkChanged(pState->pDrvR3, enmState);
5170 }
5171 return VINF_SUCCESS;
5172}
5173
5174/**
5175 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5176 */
5177static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5178{
5179 E1KSTATE *pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
5180 Assert(&pThis->IBase == pInterface);
5181
5182 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5183 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
5184 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
5185 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
5186 return NULL;
5187}
5188
5189/**
5190 * Saves the configuration.
5191 *
5192 * @param pState The E1K state.
5193 * @param pSSM The handle to the saved state.
5194 */
5195static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
5196{
5197 SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
5198 SSMR3PutU32(pSSM, pState->eChip);
5199}
5200
5201/**
5202 * Live save - save basic configuration.
5203 *
5204 * @returns VBox status code.
5205 * @param pDevIns The device instance.
5206 * @param pSSM The handle to the saved state.
5207 * @param uPass
5208 */
5209static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5210{
5211 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5212 e1kSaveConfig(pState, pSSM);
5213 return VINF_SSM_DONT_CALL_AGAIN;
5214}
5215
5216/**
5217 * Prepares for state saving.
5218 *
5219 * @returns VBox status code.
5220 * @param pDevIns The device instance.
5221 * @param pSSM The handle to the saved state.
5222 */
5223static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5224{
5225 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5226
5227 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5228 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5229 return rc;
5230 e1kCsLeave(pState);
5231 return VINF_SUCCESS;
5232#if 0
5233 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5234 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5235 return rc;
5236 /* 1) Prevent all threads from modifying the state and memory */
5237 //pState->fLocked = true;
5238 /* 2) Cancel all timers */
5239#ifdef E1K_USE_TX_TIMERS
5240 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
5241#ifndef E1K_NO_TAD
5242 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
5243#endif /* E1K_NO_TAD */
5244#endif /* E1K_USE_TX_TIMERS */
5245#ifdef E1K_USE_RX_TIMERS
5246 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
5247 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
5248#endif /* E1K_USE_RX_TIMERS */
5249 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
5250 /* 3) Did I forget anything? */
5251 E1kLog(("%s Locked\n", INSTANCE(pState)));
5252 e1kMutexRelease(pState);
5253 return VINF_SUCCESS;
5254#endif
5255}
5256
5257
5258/**
5259 * Saves the state of device.
5260 *
5261 * @returns VBox status code.
5262 * @param pDevIns The device instance.
5263 * @param pSSM The handle to the saved state.
5264 */
5265static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5266{
5267 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5268
5269 e1kSaveConfig(pState, pSSM);
5270 pState->eeprom.save(pSSM);
5271 e1kDumpState(pState);
5272 SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
5273 SSMR3PutBool(pSSM, pState->fIntRaised);
5274 Phy::saveState(pSSM, &pState->phy);
5275 SSMR3PutU32(pSSM, pState->uSelectedReg);
5276 SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
5277 SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5278 SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
5279 SSMR3PutU64(pSSM, pState->u64AckedAt);
5280 SSMR3PutU16(pSSM, pState->u16RxBSize);
5281 //SSMR3PutBool(pSSM, pState->fDelayInts);
5282 //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
5283 SSMR3PutU16(pSSM, pState->u16TxPktLen);
5284/** @todo State wrt to the TSE buffer is incomplete, so little point in
5285 * saving this actually. */
5286 SSMR3PutMem(pSSM, pState->aTxPacketFallback, pState->u16TxPktLen);
5287 SSMR3PutBool(pSSM, pState->fIPcsum);
5288 SSMR3PutBool(pSSM, pState->fTCPcsum);
5289 SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5290 SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5291 SSMR3PutBool(pSSM, pState->fVTag);
5292 SSMR3PutU16(pSSM, pState->u16VTagTCI);
5293/**@todo GSO requires some more state here. */
5294 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
5295 return VINF_SUCCESS;
5296}
5297
5298#if 0
5299/**
5300 * Cleanup after saving.
5301 *
5302 * @returns VBox status code.
5303 * @param pDevIns The device instance.
5304 * @param pSSM The handle to the saved state.
5305 */
5306static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5307{
5308 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5309
5310 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5311 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5312 return rc;
5313 /* If VM is being powered off unlocking will result in assertions in PGM */
5314 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
5315 pState->fLocked = false;
5316 else
5317 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
5318 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
5319 e1kMutexRelease(pState);
5320 return VINF_SUCCESS;
5321}
5322#endif
5323
5324/**
5325 * Sync with .
5326 *
5327 * @returns VBox status code.
5328 * @param pDevIns The device instance.
5329 * @param pSSM The handle to the saved state.
5330 */
5331static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5332{
5333 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5334
5335 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5336 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5337 return rc;
5338 e1kCsLeave(pState);
5339 return VINF_SUCCESS;
5340}
5341
5342/**
5343 * Restore previously saved state of device.
5344 *
5345 * @returns VBox status code.
5346 * @param pDevIns The device instance.
5347 * @param pSSM The handle to the saved state.
5348 * @param uVersion The data unit version number.
5349 * @param uPass The data pass.
5350 */
5351static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5352{
5353 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5354 int rc;
5355
5356 if ( uVersion != E1K_SAVEDSTATE_VERSION
5357 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
5358 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
5359 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5360
5361 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
5362 || uPass != SSM_PASS_FINAL)
5363 {
5364 /* config checks */
5365 RTMAC macConfigured;
5366 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
5367 AssertRCReturn(rc, rc);
5368 if ( memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
5369 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
5370 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", INSTANCE(pState), &pState->macConfigured, &macConfigured));
5371
5372 E1KCHIP eChip;
5373 rc = SSMR3GetU32(pSSM, &eChip);
5374 AssertRCReturn(rc, rc);
5375 if (eChip != pState->eChip)
5376 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pState->eChip, eChip);
5377 }
5378
5379 if (uPass == SSM_PASS_FINAL)
5380 {
5381 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
5382 {
5383 rc = pState->eeprom.load(pSSM);
5384 AssertRCReturn(rc, rc);
5385 }
5386 /* the state */
5387 SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
5388 SSMR3GetBool(pSSM, &pState->fIntRaised);
5389 /** @todo: PHY could be made a separate device with its own versioning */
5390 Phy::loadState(pSSM, &pState->phy);
5391 SSMR3GetU32(pSSM, &pState->uSelectedReg);
5392 SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
5393 SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5394 SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
5395 SSMR3GetU64(pSSM, &pState->u64AckedAt);
5396 SSMR3GetU16(pSSM, &pState->u16RxBSize);
5397 //SSMR3GetBool(pSSM, pState->fDelayInts);
5398 //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
5399 SSMR3GetU16(pSSM, &pState->u16TxPktLen);
5400 SSMR3GetMem(pSSM, &pState->aTxPacketFallback[0], pState->u16TxPktLen);
5401 SSMR3GetBool(pSSM, &pState->fIPcsum);
5402 SSMR3GetBool(pSSM, &pState->fTCPcsum);
5403 SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5404 rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5405 AssertRCReturn(rc, rc);
5406 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
5407 {
5408 SSMR3GetBool(pSSM, &pState->fVTag);
5409 rc = SSMR3GetU16(pSSM, &pState->u16VTagTCI);
5410 AssertRCReturn(rc, rc);
5411 }
5412 else
5413 {
5414 pState->fVTag = false;
5415 pState->u16VTagTCI = 0;
5416 }
5417 /* derived state */
5418 e1kSetupGsoCtx(&pState->GsoCtx, &pState->contextTSE);
5419
5420 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
5421 e1kDumpState(pState);
5422 }
5423 return VINF_SUCCESS;
5424}
5425
5426/**
5427 * Link status adjustments after loading.
5428 *
5429 * @returns VBox status code.
5430 * @param pDevIns The device instance.
5431 * @param pSSM The handle to the saved state.
5432 */
5433static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5434{
5435 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5436
5437 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5438 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5439 return rc;
5440
5441 /* Update promiscuous mode */
5442 if (pState->pDrvR3)
5443 pState->pDrvR3->pfnSetPromiscuousMode(pState->pDrvR3,
5444 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
5445
5446 /*
5447 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
5448 * passed to us. We go through all this stuff if the link was up and we
5449 * wasn't teleported.
5450 */
5451 if ( (STATUS & STATUS_LU)
5452 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
5453 {
5454 E1kLog(("%s Link is down temporarily\n", INSTANCE(pState)));
5455 STATUS &= ~STATUS_LU;
5456 Phy::setLinkStatus(&pState->phy, false);
5457 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5458 /* Restore the link back in five seconds. */
5459 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5460 }
5461 e1kMutexRelease(pState);
5462 return VINF_SUCCESS;
5463}
5464
5465
5466/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
5467
5468/**
5469 * Detach notification.
5470 *
5471 * One port on the network card has been disconnected from the network.
5472 *
5473 * @param pDevIns The device instance.
5474 * @param iLUN The logical unit which is being detached.
5475 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5476 */
5477static DECLCALLBACK(void) e1kDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5478{
5479 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5480 Log(("%s e1kDetach:\n", INSTANCE(pState)));
5481
5482 AssertLogRelReturnVoid(iLUN == 0);
5483
5484 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5485
5486 /** @todo: r=pritesh still need to check if i missed
5487 * to clean something in this function
5488 */
5489
5490 /*
5491 * Zero some important members.
5492 */
5493 pState->pDrvBase = NULL;
5494 pState->pDrvR3 = NULL;
5495 pState->pDrvR0 = NIL_RTR0PTR;
5496 pState->pDrvRC = NIL_RTRCPTR;
5497
5498 PDMCritSectLeave(&pState->cs);
5499}
5500
5501/**
5502 * Attach the Network attachment.
5503 *
5504 * One port on the network card has been connected to a network.
5505 *
5506 * @returns VBox status code.
5507 * @param pDevIns The device instance.
5508 * @param iLUN The logical unit which is being attached.
5509 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5510 *
5511 * @remarks This code path is not used during construction.
5512 */
5513static DECLCALLBACK(int) e1kAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5514{
5515 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5516 LogFlow(("%s e1kAttach:\n", INSTANCE(pState)));
5517
5518 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
5519
5520 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5521
5522 /*
5523 * Attach the driver.
5524 */
5525 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5526 if (RT_SUCCESS(rc))
5527 {
5528 if (rc == VINF_NAT_DNS)
5529 {
5530#ifdef RT_OS_LINUX
5531 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5532 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5533#else
5534 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5535 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5536#endif
5537 }
5538 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5539 AssertMsgStmt(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5540 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
5541 if (RT_SUCCESS(rc))
5542 {
5543 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0);
5544 pState->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5545
5546 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC);
5547 pState->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5548 }
5549 }
5550 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5551 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5552 {
5553 /* This should never happen because this function is not called
5554 * if there is no driver to attach! */
5555 Log(("%s No attached driver!\n", INSTANCE(pState)));
5556 }
5557
5558 /*
5559 * Temporary set the link down if it was up so that the guest
5560 * will know that we have change the configuration of the
5561 * network card
5562 */
5563 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
5564 {
5565 STATUS &= ~STATUS_LU;
5566 Phy::setLinkStatus(&pState->phy, false);
5567 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5568 /* Restore the link back in 5 second. */
5569 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5570 }
5571
5572 PDMCritSectLeave(&pState->cs);
5573 return rc;
5574
5575}
5576
5577/**
5578 * @copydoc FNPDMDEVPOWEROFF
5579 */
5580static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
5581{
5582 /* Poke thread waiting for buffer space. */
5583 e1kWakeupReceive(pDevIns);
5584}
5585
5586/**
5587 * @copydoc FNPDMDEVRESET
5588 */
5589static DECLCALLBACK(void) e1kReset(PPDMDEVINS pDevIns)
5590{
5591 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5592 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
5593 e1kCancelTimer(pState, pState->CTX_SUFF(pLUTimer));
5594 e1kXmitFreeBuf(pState);
5595 pState->u16TxPktLen = 0;
5596 pState->fIPcsum = false;
5597 pState->fTCPcsum = false;
5598 pState->fIntMaskUsed = false;
5599 pState->fDelayInts = false;
5600 pState->fLocked = false;
5601 pState->u64AckedAt = 0;
5602 e1kHardReset(pState);
5603}
5604
5605/**
5606 * @copydoc FNPDMDEVSUSPEND
5607 */
5608static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
5609{
5610 /* Poke thread waiting for buffer space. */
5611 e1kWakeupReceive(pDevIns);
5612}
5613
5614/**
5615 * Device relocation callback.
5616 *
5617 * When this callback is called the device instance data, and if the
5618 * device have a GC component, is being relocated, or/and the selectors
5619 * have been changed. The device must use the chance to perform the
5620 * necessary pointer relocations and data updates.
5621 *
5622 * Before the GC code is executed the first time, this function will be
5623 * called with a 0 delta so GC pointer calculations can be one in one place.
5624 *
5625 * @param pDevIns Pointer to the device instance.
5626 * @param offDelta The relocation delta relative to the old location.
5627 *
5628 * @remark A relocation CANNOT fail.
5629 */
5630static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5631{
5632 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5633 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5634 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5635 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5636#ifdef E1K_USE_RX_TIMERS
5637 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5638 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5639#endif /* E1K_USE_RX_TIMERS */
5640#ifdef E1K_USE_TX_TIMERS
5641 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5642# ifndef E1K_NO_TAD
5643 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5644# endif /* E1K_NO_TAD */
5645#endif /* E1K_USE_TX_TIMERS */
5646 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5647 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5648}
5649
5650/**
5651 * Destruct a device instance.
5652 *
5653 * We need to free non-VM resources only.
5654 *
5655 * @returns VBox status.
5656 * @param pDevIns The device instance data.
5657 * @thread EMT
5658 */
5659static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
5660{
5661 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5662 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5663
5664 e1kDumpState(pState);
5665 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
5666 if (PDMCritSectIsInitialized(&pState->cs))
5667 {
5668 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
5669 {
5670 RTSemEventSignal(pState->hEventMoreRxDescAvail);
5671 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
5672 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5673 }
5674#ifndef E1K_GLOBAL_MUTEX
5675 PDMR3CritSectDelete(&pState->csRx);
5676 //PDMR3CritSectDelete(&pState->csTx);
5677#endif
5678 PDMR3CritSectDelete(&pState->cs);
5679 }
5680 return VINF_SUCCESS;
5681}
5682
5683/**
5684 * Status info callback.
5685 *
5686 * @param pDevIns The device instance.
5687 * @param pHlp The output helpers.
5688 * @param pszArgs The arguments.
5689 */
5690static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5691{
5692 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5693 unsigned i;
5694 // bool fRcvRing = false;
5695 // bool fXmtRing = false;
5696
5697 /*
5698 * Parse args.
5699 if (pszArgs)
5700 {
5701 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
5702 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
5703 }
5704 */
5705
5706 /*
5707 * Show info.
5708 */
5709 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RX32 mac-cfg=%RTmac %s%s%s\n",
5710 pDevIns->iInstance, pState->addrIOPort, pState->addrMMReg,
5711 &pState->macConfigured, g_Chips[pState->eChip].pcszName,
5712 pState->fGCEnabled ? " GC" : "", pState->fR0Enabled ? " R0" : "");
5713
5714 e1kCsEnter(pState, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
5715
5716 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
5717 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", s_e1kRegMap[i].abbrev, pState->auRegs[i]);
5718
5719 for (i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
5720 {
5721 E1KRAELEM* ra = pState->aRecAddr.array + i;
5722 if (ra->ctl & RA_CTL_AV)
5723 {
5724 const char *pcszTmp;
5725 switch (ra->ctl & RA_CTL_AS)
5726 {
5727 case 0: pcszTmp = "DST"; break;
5728 case 1: pcszTmp = "SRC"; break;
5729 default: pcszTmp = "reserved";
5730 }
5731 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
5732 }
5733 }
5734
5735
5736#ifdef E1K_INT_STATS
5737 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pState->uStatIntTry);
5738 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pState->uStatInt);
5739 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pState->uStatIntLower);
5740 pHlp->pfnPrintf(pHlp, "Interrupts delayed: %d\n", pState->uStatIntDly);
5741 pHlp->pfnPrintf(pHlp, "Disabled delayed: %d\n", pState->uStatDisDly);
5742 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pState->uStatIntSkip);
5743 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pState->uStatIntMasked);
5744 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pState->uStatIntEarly);
5745 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pState->uStatIntLate);
5746 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pState->iStatIntLost);
5747 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pState->uStatIntRx);
5748 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pState->uStatIntTx);
5749 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pState->uStatIntICS);
5750 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pState->uStatIntRDTR);
5751 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pState->uStatIntRXDMT0);
5752 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pState->uStatIntTXQE);
5753 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pState->uStatTxIDE);
5754 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pState->uStatTxNoRS);
5755 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pState->uStatTAD);
5756 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pState->uStatTID);
5757 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pState->uStatRAD);
5758 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pState->uStatRID);
5759 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pState->uStatDescCtx);
5760 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pState->uStatDescDat);
5761 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pState->uStatDescLeg);
5762 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pState->uStatRxFrm);
5763 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pState->uStatTxFrm);
5764#endif /* E1K_INT_STATS */
5765
5766 e1kCsLeave(pState);
5767}
5768
5769/**
5770 * Sets 8-bit register in PCI configuration space.
5771 * @param refPciDev The PCI device.
5772 * @param uOffset The register offset.
5773 * @param u16Value The value to store in the register.
5774 * @thread EMT
5775 */
5776DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
5777{
5778 Assert(uOffset < sizeof(refPciDev.config));
5779 refPciDev.config[uOffset] = u8Value;
5780}
5781
5782/**
5783 * Sets 16-bit register in PCI configuration space.
5784 * @param refPciDev The PCI device.
5785 * @param uOffset The register offset.
5786 * @param u16Value The value to store in the register.
5787 * @thread EMT
5788 */
5789DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
5790{
5791 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
5792 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
5793}
5794
5795/**
5796 * Sets 32-bit register in PCI configuration space.
5797 * @param refPciDev The PCI device.
5798 * @param uOffset The register offset.
5799 * @param u32Value The value to store in the register.
5800 * @thread EMT
5801 */
5802DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
5803{
5804 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
5805 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
5806}
5807
5808/**
5809 * Set PCI configuration space registers.
5810 *
5811 * @param pci Reference to PCI device structure.
5812 * @thread EMT
5813 */
5814static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
5815{
5816 Assert(eChip < RT_ELEMENTS(g_Chips));
5817 /* Configure PCI Device, assume 32-bit mode ******************************/
5818 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
5819 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
5820 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
5821 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
5822
5823 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
5824 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
5825 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS,
5826 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
5827 /* Stepping A2 */
5828 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
5829 /* Ethernet adapter */
5830 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
5831 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
5832 /* normal single function Ethernet controller */
5833 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
5834 /* Memory Register Base Address */
5835 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
5836 /* Memory Flash Base Address */
5837 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
5838 /* IO Register Base Address */
5839 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
5840 /* Expansion ROM Base Address */
5841 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
5842 /* Capabilities Pointer */
5843 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
5844 /* Interrupt Pin: INTA# */
5845 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
5846 /* Max_Lat/Min_Gnt: very high priority and time slice */
5847 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
5848 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
5849
5850 /* PCI Power Management Registers ****************************************/
5851 /* Capability ID: PCI Power Management Registers */
5852 e1kPCICfgSetU8( pci, 0xDC, VBOX_PCI_CAP_ID_PM);
5853 /* Next Item Pointer: PCI-X */
5854 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
5855 /* Power Management Capabilities: PM disabled, DSI */
5856 e1kPCICfgSetU16(pci, 0xDC + 2,
5857 0x0002 | VBOX_PCI_PM_CAP_DSI);
5858 /* Power Management Control / Status Register: PM disabled */
5859 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
5860 /* PMCSR_BSE Bridge Support Extensions: Not supported */
5861 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
5862 /* Data Register: PM disabled, always 0 */
5863 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
5864
5865 /* PCI-X Configuration Registers *****************************************/
5866 /* Capability ID: PCI-X Configuration Registers */
5867 e1kPCICfgSetU8( pci, 0xE4, VBOX_PCI_CAP_ID_PCIX);
5868#ifdef E1K_WITH_MSI
5869 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x80);
5870#else
5871 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
5872 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
5873#endif
5874 /* PCI-X Command: Enable Relaxed Ordering */
5875 e1kPCICfgSetU16(pci, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
5876 /* PCI-X Status: 32-bit, 66MHz*/
5877 /// @todo: is this value really correct? fff8 doesn't look like actual PCI address
5878 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
5879}
5880
5881/**
5882 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5883 */
5884static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5885{
5886 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5887 int rc;
5888 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5889
5890 /* Init handles and log related stuff. */
5891 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
5892 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
5893 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5894
5895 /*
5896 * Validate configuration.
5897 */
5898 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"))
5899 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5900 N_("Invalid configuration for E1000 device"));
5901
5902 /** @todo: LineSpeed unused! */
5903
5904 pState->fR0Enabled = true;
5905 pState->fGCEnabled = true;
5906
5907 /* Get config params */
5908 rc = CFGMR3QueryBytes(pCfg, "MAC", pState->macConfigured.au8,
5909 sizeof(pState->macConfigured.au8));
5910 if (RT_FAILURE(rc))
5911 return PDMDEV_SET_ERROR(pDevIns, rc,
5912 N_("Configuration error: Failed to get MAC address"));
5913 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pState->fCableConnected);
5914 if (RT_FAILURE(rc))
5915 return PDMDEV_SET_ERROR(pDevIns, rc,
5916 N_("Configuration error: Failed to get the value of 'CableConnected'"));
5917 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pState->eChip);
5918 if (RT_FAILURE(rc))
5919 return PDMDEV_SET_ERROR(pDevIns, rc,
5920 N_("Configuration error: Failed to get the value of 'AdapterType'"));
5921 Assert(pState->eChip <= E1K_CHIP_82545EM);
5922 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pState->fGCEnabled, true);
5923 if (RT_FAILURE(rc))
5924 return PDMDEV_SET_ERROR(pDevIns, rc,
5925 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
5926
5927 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pState->fR0Enabled, true);
5928 if (RT_FAILURE(rc))
5929 return PDMDEV_SET_ERROR(pDevIns, rc,
5930 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
5931
5932 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
5933
5934 /* Initialize state structure */
5935 pState->pDevInsR3 = pDevIns;
5936 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5937 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5938 pState->u16TxPktLen = 0;
5939 pState->fIPcsum = false;
5940 pState->fTCPcsum = false;
5941 pState->fIntMaskUsed = false;
5942 pState->fDelayInts = false;
5943 pState->fLocked = false;
5944 pState->u64AckedAt = 0;
5945 pState->led.u32Magic = PDMLED_MAGIC;
5946 pState->u32PktNo = 1;
5947
5948#ifdef E1K_INT_STATS
5949 pState->uStatInt = 0;
5950 pState->uStatIntTry = 0;
5951 pState->uStatIntLower = 0;
5952 pState->uStatIntDly = 0;
5953 pState->uStatDisDly = 0;
5954 pState->iStatIntLost = 0;
5955 pState->iStatIntLostOne = 0;
5956 pState->uStatIntLate = 0;
5957 pState->uStatIntMasked = 0;
5958 pState->uStatIntEarly = 0;
5959 pState->uStatIntRx = 0;
5960 pState->uStatIntTx = 0;
5961 pState->uStatIntICS = 0;
5962 pState->uStatIntRDTR = 0;
5963 pState->uStatIntRXDMT0 = 0;
5964 pState->uStatIntTXQE = 0;
5965 pState->uStatTxNoRS = 0;
5966 pState->uStatTxIDE = 0;
5967 pState->uStatTAD = 0;
5968 pState->uStatTID = 0;
5969 pState->uStatRAD = 0;
5970 pState->uStatRID = 0;
5971 pState->uStatRxFrm = 0;
5972 pState->uStatTxFrm = 0;
5973 pState->uStatDescCtx = 0;
5974 pState->uStatDescDat = 0;
5975 pState->uStatDescLeg = 0;
5976#endif /* E1K_INT_STATS */
5977
5978 /* Interfaces */
5979 pState->IBase.pfnQueryInterface = e1kQueryInterface;
5980
5981 pState->INetworkDown.pfnWaitReceiveAvail = e1kNetworkDown_WaitReceiveAvail;
5982 pState->INetworkDown.pfnReceive = e1kNetworkDown_Receive;
5983 pState->INetworkDown.pfnXmitPending = e1kNetworkDown_XmitPending;
5984
5985 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
5986
5987 pState->INetworkConfig.pfnGetMac = e1kGetMac;
5988 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
5989 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
5990
5991 /* Initialize the EEPROM */
5992 pState->eeprom.init(pState->macConfigured);
5993
5994 /* Initialize internal PHY */
5995 Phy::init(&pState->phy, iInstance,
5996 pState->eChip == E1K_CHIP_82543GC?
5997 PHY_EPID_M881000 : PHY_EPID_M881011);
5998 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
5999
6000 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
6001 NULL, e1kLiveExec, NULL,
6002 e1kSavePrep, e1kSaveExec, NULL,
6003 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
6004 if (RT_FAILURE(rc))
6005 return rc;
6006
6007 /* Initialize critical section */
6008 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
6009 if (RT_FAILURE(rc))
6010 return rc;
6011#ifndef E1K_GLOBAL_MUTEX
6012 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, RT_SRC_POS, "%sRX", pState->szInstance);
6013 if (RT_FAILURE(rc))
6014 return rc;
6015#endif
6016
6017 /* Set PCI config registers */
6018 e1kConfigurePCI(pState->pciDevice, pState->eChip);
6019 /* Register PCI device */
6020 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
6021 if (RT_FAILURE(rc))
6022 return rc;
6023
6024#ifdef E1K_WITH_MSI
6025 PDMMSIREG aMsiReg;
6026 aMsiReg.cVectors = 1;
6027 aMsiReg.iCapOffset = 0x80;
6028 aMsiReg.iNextOffset = 0x0;
6029 aMsiReg.iMsiFlags = 0;
6030 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &aMsiReg);
6031 AssertRC(rc);
6032 if (RT_FAILURE (rc))
6033 return rc;
6034#endif
6035
6036
6037 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
6038 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
6039 PCI_ADDRESS_SPACE_MEM, e1kMap);
6040 if (RT_FAILURE(rc))
6041 return rc;
6042 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
6043 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
6044 PCI_ADDRESS_SPACE_IO, e1kMap);
6045 if (RT_FAILURE(rc))
6046 return rc;
6047
6048 /* Create transmit queue */
6049 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
6050 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3);
6051 if (RT_FAILURE(rc))
6052 return rc;
6053 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
6054 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
6055
6056 /* Create the RX notifier signaller. */
6057 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
6058 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3);
6059 if (RT_FAILURE(rc))
6060 return rc;
6061 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
6062 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
6063
6064#ifdef E1K_USE_TX_TIMERS
6065 /* Create Transmit Interrupt Delay Timer */
6066 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pState,
6067 TMTIMER_FLAGS_NO_CRIT_SECT,
6068 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
6069 if (RT_FAILURE(rc))
6070 return rc;
6071 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
6072 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
6073
6074# ifndef E1K_NO_TAD
6075 /* Create Transmit Absolute Delay Timer */
6076 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pState,
6077 TMTIMER_FLAGS_NO_CRIT_SECT,
6078 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
6079 if (RT_FAILURE(rc))
6080 return rc;
6081 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
6082 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
6083# endif /* E1K_NO_TAD */
6084#endif /* E1K_USE_TX_TIMERS */
6085
6086#ifdef E1K_USE_RX_TIMERS
6087 /* Create Receive Interrupt Delay Timer */
6088 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pState,
6089 TMTIMER_FLAGS_NO_CRIT_SECT,
6090 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
6091 if (RT_FAILURE(rc))
6092 return rc;
6093 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
6094 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
6095
6096 /* Create Receive Absolute Delay Timer */
6097 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pState,
6098 TMTIMER_FLAGS_NO_CRIT_SECT,
6099 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
6100 if (RT_FAILURE(rc))
6101 return rc;
6102 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
6103 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
6104#endif /* E1K_USE_RX_TIMERS */
6105
6106 /* Create Late Interrupt Timer */
6107 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pState,
6108 TMTIMER_FLAGS_NO_CRIT_SECT,
6109 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
6110 if (RT_FAILURE(rc))
6111 return rc;
6112 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
6113 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
6114
6115 /* Create Link Up Timer */
6116 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pState,
6117 TMTIMER_FLAGS_NO_CRIT_SECT,
6118 "E1000 Link Up Timer", &pState->pLUTimerR3);
6119 if (RT_FAILURE(rc))
6120 return rc;
6121 pState->pLUTimerR0 = TMTimerR0Ptr(pState->pLUTimerR3);
6122 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
6123
6124 /* Register the info item */
6125 char szTmp[20];
6126 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
6127 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
6128
6129 /* Status driver */
6130 PPDMIBASE pBase;
6131 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
6132 if (RT_FAILURE(rc))
6133 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
6134 pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
6135
6136 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
6137 if (RT_SUCCESS(rc))
6138 {
6139 if (rc == VINF_NAT_DNS)
6140 {
6141 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
6142 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
6143 }
6144 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
6145 AssertMsgReturn(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
6146 VERR_PDM_MISSING_INTERFACE_BELOW);
6147
6148 pState->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0), PDMINETWORKUP);
6149 pState->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC), PDMINETWORKUP);
6150 }
6151 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
6152 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
6153 {
6154 /* No error! */
6155 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
6156 }
6157 else
6158 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
6159
6160 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
6161 if (RT_FAILURE(rc))
6162 return rc;
6163
6164 e1kHardReset(pState);
6165
6166#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
6167 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
6168 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
6169 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
6170 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
6171 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
6172 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
6173 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
6174 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
6175 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
6176 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
6177 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
6178 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
6179 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
6180 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
6181 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
6182 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
6183 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
6184 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
6185 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
6186#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
6187 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
6188#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
6189 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
6190 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
6191#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
6192 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
6193#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
6194 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
6195 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
6196
6197 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
6198 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
6199 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
6200 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
6201 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
6202 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
6203 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
6204 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
6205 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
6206#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
6207
6208 return VINF_SUCCESS;
6209}
6210
6211/**
6212 * The device registration structure.
6213 */
6214const PDMDEVREG g_DeviceE1000 =
6215{
6216 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
6217 PDM_DEVREG_VERSION,
6218 /* Device name. */
6219 "e1000",
6220 /* Name of guest context module (no path).
6221 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
6222 "VBoxDDGC.gc",
6223 /* Name of ring-0 module (no path).
6224 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
6225 "VBoxDDR0.r0",
6226 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
6227 * remain unchanged from registration till VM destruction. */
6228 "Intel PRO/1000 MT Desktop Ethernet.\n",
6229
6230 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
6231 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6232 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
6233 PDM_DEVREG_CLASS_NETWORK,
6234 /* Maximum number of instances (per VM). */
6235 ~0,
6236 /* Size of the instance data. */
6237 sizeof(E1KSTATE),
6238
6239 /* Construct instance - required. */
6240 e1kConstruct,
6241 /* Destruct instance - optional. */
6242 e1kDestruct,
6243 /* Relocation command - optional. */
6244 e1kRelocate,
6245 /* I/O Control interface - optional. */
6246 NULL,
6247 /* Power on notification - optional. */
6248 NULL,
6249 /* Reset notification - optional. */
6250 e1kReset,
6251 /* Suspend notification - optional. */
6252 e1kSuspend,
6253 /* Resume notification - optional. */
6254 NULL,
6255 /* Attach command - optional. */
6256 e1kAttach,
6257 /* Detach notification - optional. */
6258 e1kDetach,
6259 /* Query a LUN base interface - optional. */
6260 NULL,
6261 /* Init complete notification - optional. */
6262 NULL,
6263 /* Power off notification - optional. */
6264 e1kPowerOff,
6265 /* pfnSoftReset */
6266 NULL,
6267 /* u32VersionEnd */
6268 PDM_DEVREG_VERSION
6269};
6270
6271#endif /* IN_RING3 */
6272#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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