VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 61541

Last change on this file since 61541 was 60775, checked in by vboxsync, 9 years ago

remove LOG_ENABLED from DevE1000 (accidently introduced in r106573)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 317.4 KB
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1/* $Id: DevE1000.cpp 60775 2016-05-02 06:54:26Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2015 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/* Options *******************************************************************/
51/** @def E1K_INIT_RA0
52 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
53 * table to MAC address obtained from CFGM. Most guests read MAC address from
54 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
55 * being already set (see @bugref{4657}).
56 */
57#define E1K_INIT_RA0
58/** @def E1K_LSC_ON_SLU
59 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
60 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
61 * that requires it is Mac OS X (see @bugref{4657}).
62 */
63#define E1K_LSC_ON_SLU
64/** @def E1K_ITR_ENABLED
65 * E1K_ITR_ENABLED reduces the number of interrupts generated by E1000 if a
66 * guest driver requested it by writing non-zero value to the Interrupt
67 * Throttling Register (see section 13.4.18 in "8254x Family of Gigabit
68 * Ethernet Controllers Software Developer’s Manual").
69 */
70//#define E1K_ITR_ENABLED
71/** @def E1K_TX_DELAY
72 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
73 * preventing packets to be sent immediately. It allows to send several
74 * packets in a batch reducing the number of acknowledgments. Note that it
75 * effectively disables R0 TX path, forcing sending in R3.
76 */
77//#define E1K_TX_DELAY 150
78/** @def E1K_USE_TX_TIMERS
79 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
80 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
81 * register. Enabling it showed no positive effects on existing guests so it
82 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
83 * Ethernet Controllers Software Developer’s Manual" for more detailed
84 * explanation.
85 */
86//#define E1K_USE_TX_TIMERS
87/** @def E1K_NO_TAD
88 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
89 * Transmit Absolute Delay time. This timer sets the maximum time interval
90 * during which TX interrupts can be postponed (delayed). It has no effect
91 * if E1K_USE_TX_TIMERS is not defined.
92 */
93//#define E1K_NO_TAD
94/** @def E1K_REL_DEBUG
95 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
96 */
97//#define E1K_REL_DEBUG
98/** @def E1K_INT_STATS
99 * E1K_INT_STATS enables collection of internal statistics used for
100 * debugging of delayed interrupts, etc.
101 */
102//#define E1K_INT_STATS
103/** @def E1K_WITH_MSI
104 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
105 */
106//#define E1K_WITH_MSI
107/** @def E1K_WITH_TX_CS
108 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
109 */
110#define E1K_WITH_TX_CS
111/** @def E1K_WITH_TXD_CACHE
112 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
113 * single physical memory read (or two if it wraps around the end of TX
114 * descriptor ring). It is required for proper functioning of bandwidth
115 * resource control as it allows to compute exact sizes of packets prior
116 * to allocating their buffers (see @bugref{5582}).
117 */
118#define E1K_WITH_TXD_CACHE
119/** @def E1K_WITH_RXD_CACHE
120 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
121 * single physical memory read (or two if it wraps around the end of RX
122 * descriptor ring). Intel's packet driver for DOS needs this option in
123 * order to work properly (see @bugref{6217}).
124 */
125#define E1K_WITH_RXD_CACHE
126/* End of Options ************************************************************/
127
128#ifdef E1K_WITH_TXD_CACHE
129/**
130 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
131 * in the state structure. It limits the amount of descriptors loaded in one
132 * batch read. For example, Linux guest may use up to 20 descriptors per
133 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
134 */
135# define E1K_TXD_CACHE_SIZE 64u
136#endif /* E1K_WITH_TXD_CACHE */
137
138#ifdef E1K_WITH_RXD_CACHE
139/**
140 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
141 * in the state structure. It limits the amount of descriptors loaded in one
142 * batch read. For example, XP guest adds 15 RX descriptors at a time.
143 */
144# define E1K_RXD_CACHE_SIZE 16u
145#endif /* E1K_WITH_RXD_CACHE */
146
147
148/* Little helpers ************************************************************/
149#undef htons
150#undef ntohs
151#undef htonl
152#undef ntohl
153#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
154#define ntohs(x) htons(x)
155#define htonl(x) ASMByteSwapU32(x)
156#define ntohl(x) htonl(x)
157
158#ifndef DEBUG
159# ifdef E1K_REL_DEBUG
160# define DEBUG
161# define E1kLog(a) LogRel(a)
162# define E1kLog2(a) LogRel(a)
163# define E1kLog3(a) LogRel(a)
164# define E1kLogX(x, a) LogRel(a)
165//# define E1kLog3(a) do {} while (0)
166# else
167# define E1kLog(a) do {} while (0)
168# define E1kLog2(a) do {} while (0)
169# define E1kLog3(a) do {} while (0)
170# define E1kLogX(x, a) do {} while (0)
171# endif
172#else
173# define E1kLog(a) Log(a)
174# define E1kLog2(a) Log2(a)
175# define E1kLog3(a) Log3(a)
176# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
177//# define E1kLog(a) do {} while (0)
178//# define E1kLog2(a) do {} while (0)
179//# define E1kLog3(a) do {} while (0)
180#endif
181
182#if 0
183# define E1kLogRel(a) LogRel(a)
184#else
185# define E1kLogRel(a) do { } while (0)
186#endif
187
188//#undef DEBUG
189
190#define STATE_TO_DEVINS(pThis) (((PE1KSTATE )pThis)->CTX_SUFF(pDevIns))
191#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
192
193#define E1K_INC_CNT32(cnt) \
194do { \
195 if (cnt < UINT32_MAX) \
196 cnt++; \
197} while (0)
198
199#define E1K_ADD_CNT64(cntLo, cntHi, val) \
200do { \
201 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
202 uint64_t tmp = u64Cnt; \
203 u64Cnt += val; \
204 if (tmp > u64Cnt ) \
205 u64Cnt = UINT64_MAX; \
206 cntLo = (uint32_t)u64Cnt; \
207 cntHi = (uint32_t)(u64Cnt >> 32); \
208} while (0)
209
210#ifdef E1K_INT_STATS
211# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
212#else /* E1K_INT_STATS */
213# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
214#endif /* E1K_INT_STATS */
215
216
217/*****************************************************************************/
218
219typedef uint32_t E1KCHIP;
220#define E1K_CHIP_82540EM 0
221#define E1K_CHIP_82543GC 1
222#define E1K_CHIP_82545EM 2
223
224/** Different E1000 chips. */
225static const struct E1kChips
226{
227 uint16_t uPCIVendorId;
228 uint16_t uPCIDeviceId;
229 uint16_t uPCISubsystemVendorId;
230 uint16_t uPCISubsystemId;
231 const char *pcszName;
232} g_Chips[] =
233{
234 /* Vendor Device SSVendor SubSys Name */
235 { 0x8086,
236 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
237#ifdef E1K_WITH_MSI
238 0x105E,
239#else
240 0x100E,
241#endif
242 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
243 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
244 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
245};
246
247
248/* The size of register area mapped to I/O space */
249#define E1K_IOPORT_SIZE 0x8
250/* The size of memory-mapped register area */
251#define E1K_MM_SIZE 0x20000
252
253#define E1K_MAX_TX_PKT_SIZE 16288
254#define E1K_MAX_RX_PKT_SIZE 16384
255
256/*****************************************************************************/
257
258/** Gets the specfieid bits from the register. */
259#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
260#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
261#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
262#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
263#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
264
265#define CTRL_SLU UINT32_C(0x00000040)
266#define CTRL_MDIO UINT32_C(0x00100000)
267#define CTRL_MDC UINT32_C(0x00200000)
268#define CTRL_MDIO_DIR UINT32_C(0x01000000)
269#define CTRL_MDC_DIR UINT32_C(0x02000000)
270#define CTRL_RESET UINT32_C(0x04000000)
271#define CTRL_VME UINT32_C(0x40000000)
272
273#define STATUS_LU UINT32_C(0x00000002)
274#define STATUS_TXOFF UINT32_C(0x00000010)
275
276#define EECD_EE_WIRES UINT32_C(0x0F)
277#define EECD_EE_REQ UINT32_C(0x40)
278#define EECD_EE_GNT UINT32_C(0x80)
279
280#define EERD_START UINT32_C(0x00000001)
281#define EERD_DONE UINT32_C(0x00000010)
282#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
283#define EERD_DATA_SHIFT 16
284#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
285#define EERD_ADDR_SHIFT 8
286
287#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
288#define MDIC_DATA_SHIFT 0
289#define MDIC_REG_MASK UINT32_C(0x001F0000)
290#define MDIC_REG_SHIFT 16
291#define MDIC_PHY_MASK UINT32_C(0x03E00000)
292#define MDIC_PHY_SHIFT 21
293#define MDIC_OP_WRITE UINT32_C(0x04000000)
294#define MDIC_OP_READ UINT32_C(0x08000000)
295#define MDIC_READY UINT32_C(0x10000000)
296#define MDIC_INT_EN UINT32_C(0x20000000)
297#define MDIC_ERROR UINT32_C(0x40000000)
298
299#define TCTL_EN UINT32_C(0x00000002)
300#define TCTL_PSP UINT32_C(0x00000008)
301
302#define RCTL_EN UINT32_C(0x00000002)
303#define RCTL_UPE UINT32_C(0x00000008)
304#define RCTL_MPE UINT32_C(0x00000010)
305#define RCTL_LPE UINT32_C(0x00000020)
306#define RCTL_LBM_MASK UINT32_C(0x000000C0)
307#define RCTL_LBM_SHIFT 6
308#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
309#define RCTL_RDMTS_SHIFT 8
310#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
311#define RCTL_MO_MASK UINT32_C(0x00003000)
312#define RCTL_MO_SHIFT 12
313#define RCTL_BAM UINT32_C(0x00008000)
314#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
315#define RCTL_BSIZE_SHIFT 16
316#define RCTL_VFE UINT32_C(0x00040000)
317#define RCTL_CFIEN UINT32_C(0x00080000)
318#define RCTL_CFI UINT32_C(0x00100000)
319#define RCTL_BSEX UINT32_C(0x02000000)
320#define RCTL_SECRC UINT32_C(0x04000000)
321
322#define ICR_TXDW UINT32_C(0x00000001)
323#define ICR_TXQE UINT32_C(0x00000002)
324#define ICR_LSC UINT32_C(0x00000004)
325#define ICR_RXDMT0 UINT32_C(0x00000010)
326#define ICR_RXT0 UINT32_C(0x00000080)
327#define ICR_TXD_LOW UINT32_C(0x00008000)
328#define RDTR_FPD UINT32_C(0x80000000)
329
330#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
331typedef struct
332{
333 unsigned rxa : 7;
334 unsigned rxa_r : 9;
335 unsigned txa : 16;
336} PBAST;
337AssertCompileSize(PBAST, 4);
338
339#define TXDCTL_WTHRESH_MASK 0x003F0000
340#define TXDCTL_WTHRESH_SHIFT 16
341#define TXDCTL_LWTHRESH_MASK 0xFE000000
342#define TXDCTL_LWTHRESH_SHIFT 25
343
344#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
345#define RXCSUM_PCSS_SHIFT 0
346
347/** @name Register access macros
348 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
349 * @{ */
350#define CTRL pThis->auRegs[CTRL_IDX]
351#define STATUS pThis->auRegs[STATUS_IDX]
352#define EECD pThis->auRegs[EECD_IDX]
353#define EERD pThis->auRegs[EERD_IDX]
354#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
355#define FLA pThis->auRegs[FLA_IDX]
356#define MDIC pThis->auRegs[MDIC_IDX]
357#define FCAL pThis->auRegs[FCAL_IDX]
358#define FCAH pThis->auRegs[FCAH_IDX]
359#define FCT pThis->auRegs[FCT_IDX]
360#define VET pThis->auRegs[VET_IDX]
361#define ICR pThis->auRegs[ICR_IDX]
362#define ITR pThis->auRegs[ITR_IDX]
363#define ICS pThis->auRegs[ICS_IDX]
364#define IMS pThis->auRegs[IMS_IDX]
365#define IMC pThis->auRegs[IMC_IDX]
366#define RCTL pThis->auRegs[RCTL_IDX]
367#define FCTTV pThis->auRegs[FCTTV_IDX]
368#define TXCW pThis->auRegs[TXCW_IDX]
369#define RXCW pThis->auRegs[RXCW_IDX]
370#define TCTL pThis->auRegs[TCTL_IDX]
371#define TIPG pThis->auRegs[TIPG_IDX]
372#define AIFS pThis->auRegs[AIFS_IDX]
373#define LEDCTL pThis->auRegs[LEDCTL_IDX]
374#define PBA pThis->auRegs[PBA_IDX]
375#define FCRTL pThis->auRegs[FCRTL_IDX]
376#define FCRTH pThis->auRegs[FCRTH_IDX]
377#define RDFH pThis->auRegs[RDFH_IDX]
378#define RDFT pThis->auRegs[RDFT_IDX]
379#define RDFHS pThis->auRegs[RDFHS_IDX]
380#define RDFTS pThis->auRegs[RDFTS_IDX]
381#define RDFPC pThis->auRegs[RDFPC_IDX]
382#define RDBAL pThis->auRegs[RDBAL_IDX]
383#define RDBAH pThis->auRegs[RDBAH_IDX]
384#define RDLEN pThis->auRegs[RDLEN_IDX]
385#define RDH pThis->auRegs[RDH_IDX]
386#define RDT pThis->auRegs[RDT_IDX]
387#define RDTR pThis->auRegs[RDTR_IDX]
388#define RXDCTL pThis->auRegs[RXDCTL_IDX]
389#define RADV pThis->auRegs[RADV_IDX]
390#define RSRPD pThis->auRegs[RSRPD_IDX]
391#define TXDMAC pThis->auRegs[TXDMAC_IDX]
392#define TDFH pThis->auRegs[TDFH_IDX]
393#define TDFT pThis->auRegs[TDFT_IDX]
394#define TDFHS pThis->auRegs[TDFHS_IDX]
395#define TDFTS pThis->auRegs[TDFTS_IDX]
396#define TDFPC pThis->auRegs[TDFPC_IDX]
397#define TDBAL pThis->auRegs[TDBAL_IDX]
398#define TDBAH pThis->auRegs[TDBAH_IDX]
399#define TDLEN pThis->auRegs[TDLEN_IDX]
400#define TDH pThis->auRegs[TDH_IDX]
401#define TDT pThis->auRegs[TDT_IDX]
402#define TIDV pThis->auRegs[TIDV_IDX]
403#define TXDCTL pThis->auRegs[TXDCTL_IDX]
404#define TADV pThis->auRegs[TADV_IDX]
405#define TSPMT pThis->auRegs[TSPMT_IDX]
406#define CRCERRS pThis->auRegs[CRCERRS_IDX]
407#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
408#define SYMERRS pThis->auRegs[SYMERRS_IDX]
409#define RXERRC pThis->auRegs[RXERRC_IDX]
410#define MPC pThis->auRegs[MPC_IDX]
411#define SCC pThis->auRegs[SCC_IDX]
412#define ECOL pThis->auRegs[ECOL_IDX]
413#define MCC pThis->auRegs[MCC_IDX]
414#define LATECOL pThis->auRegs[LATECOL_IDX]
415#define COLC pThis->auRegs[COLC_IDX]
416#define DC pThis->auRegs[DC_IDX]
417#define TNCRS pThis->auRegs[TNCRS_IDX]
418/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
419#define CEXTERR pThis->auRegs[CEXTERR_IDX]
420#define RLEC pThis->auRegs[RLEC_IDX]
421#define XONRXC pThis->auRegs[XONRXC_IDX]
422#define XONTXC pThis->auRegs[XONTXC_IDX]
423#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
424#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
425#define FCRUC pThis->auRegs[FCRUC_IDX]
426#define PRC64 pThis->auRegs[PRC64_IDX]
427#define PRC127 pThis->auRegs[PRC127_IDX]
428#define PRC255 pThis->auRegs[PRC255_IDX]
429#define PRC511 pThis->auRegs[PRC511_IDX]
430#define PRC1023 pThis->auRegs[PRC1023_IDX]
431#define PRC1522 pThis->auRegs[PRC1522_IDX]
432#define GPRC pThis->auRegs[GPRC_IDX]
433#define BPRC pThis->auRegs[BPRC_IDX]
434#define MPRC pThis->auRegs[MPRC_IDX]
435#define GPTC pThis->auRegs[GPTC_IDX]
436#define GORCL pThis->auRegs[GORCL_IDX]
437#define GORCH pThis->auRegs[GORCH_IDX]
438#define GOTCL pThis->auRegs[GOTCL_IDX]
439#define GOTCH pThis->auRegs[GOTCH_IDX]
440#define RNBC pThis->auRegs[RNBC_IDX]
441#define RUC pThis->auRegs[RUC_IDX]
442#define RFC pThis->auRegs[RFC_IDX]
443#define ROC pThis->auRegs[ROC_IDX]
444#define RJC pThis->auRegs[RJC_IDX]
445#define MGTPRC pThis->auRegs[MGTPRC_IDX]
446#define MGTPDC pThis->auRegs[MGTPDC_IDX]
447#define MGTPTC pThis->auRegs[MGTPTC_IDX]
448#define TORL pThis->auRegs[TORL_IDX]
449#define TORH pThis->auRegs[TORH_IDX]
450#define TOTL pThis->auRegs[TOTL_IDX]
451#define TOTH pThis->auRegs[TOTH_IDX]
452#define TPR pThis->auRegs[TPR_IDX]
453#define TPT pThis->auRegs[TPT_IDX]
454#define PTC64 pThis->auRegs[PTC64_IDX]
455#define PTC127 pThis->auRegs[PTC127_IDX]
456#define PTC255 pThis->auRegs[PTC255_IDX]
457#define PTC511 pThis->auRegs[PTC511_IDX]
458#define PTC1023 pThis->auRegs[PTC1023_IDX]
459#define PTC1522 pThis->auRegs[PTC1522_IDX]
460#define MPTC pThis->auRegs[MPTC_IDX]
461#define BPTC pThis->auRegs[BPTC_IDX]
462#define TSCTC pThis->auRegs[TSCTC_IDX]
463#define TSCTFC pThis->auRegs[TSCTFC_IDX]
464#define RXCSUM pThis->auRegs[RXCSUM_IDX]
465#define WUC pThis->auRegs[WUC_IDX]
466#define WUFC pThis->auRegs[WUFC_IDX]
467#define WUS pThis->auRegs[WUS_IDX]
468#define MANC pThis->auRegs[MANC_IDX]
469#define IPAV pThis->auRegs[IPAV_IDX]
470#define WUPL pThis->auRegs[WUPL_IDX]
471/** @} */
472
473/**
474 * Indices of memory-mapped registers in register table.
475 */
476typedef enum
477{
478 CTRL_IDX,
479 STATUS_IDX,
480 EECD_IDX,
481 EERD_IDX,
482 CTRL_EXT_IDX,
483 FLA_IDX,
484 MDIC_IDX,
485 FCAL_IDX,
486 FCAH_IDX,
487 FCT_IDX,
488 VET_IDX,
489 ICR_IDX,
490 ITR_IDX,
491 ICS_IDX,
492 IMS_IDX,
493 IMC_IDX,
494 RCTL_IDX,
495 FCTTV_IDX,
496 TXCW_IDX,
497 RXCW_IDX,
498 TCTL_IDX,
499 TIPG_IDX,
500 AIFS_IDX,
501 LEDCTL_IDX,
502 PBA_IDX,
503 FCRTL_IDX,
504 FCRTH_IDX,
505 RDFH_IDX,
506 RDFT_IDX,
507 RDFHS_IDX,
508 RDFTS_IDX,
509 RDFPC_IDX,
510 RDBAL_IDX,
511 RDBAH_IDX,
512 RDLEN_IDX,
513 RDH_IDX,
514 RDT_IDX,
515 RDTR_IDX,
516 RXDCTL_IDX,
517 RADV_IDX,
518 RSRPD_IDX,
519 TXDMAC_IDX,
520 TDFH_IDX,
521 TDFT_IDX,
522 TDFHS_IDX,
523 TDFTS_IDX,
524 TDFPC_IDX,
525 TDBAL_IDX,
526 TDBAH_IDX,
527 TDLEN_IDX,
528 TDH_IDX,
529 TDT_IDX,
530 TIDV_IDX,
531 TXDCTL_IDX,
532 TADV_IDX,
533 TSPMT_IDX,
534 CRCERRS_IDX,
535 ALGNERRC_IDX,
536 SYMERRS_IDX,
537 RXERRC_IDX,
538 MPC_IDX,
539 SCC_IDX,
540 ECOL_IDX,
541 MCC_IDX,
542 LATECOL_IDX,
543 COLC_IDX,
544 DC_IDX,
545 TNCRS_IDX,
546 SEC_IDX,
547 CEXTERR_IDX,
548 RLEC_IDX,
549 XONRXC_IDX,
550 XONTXC_IDX,
551 XOFFRXC_IDX,
552 XOFFTXC_IDX,
553 FCRUC_IDX,
554 PRC64_IDX,
555 PRC127_IDX,
556 PRC255_IDX,
557 PRC511_IDX,
558 PRC1023_IDX,
559 PRC1522_IDX,
560 GPRC_IDX,
561 BPRC_IDX,
562 MPRC_IDX,
563 GPTC_IDX,
564 GORCL_IDX,
565 GORCH_IDX,
566 GOTCL_IDX,
567 GOTCH_IDX,
568 RNBC_IDX,
569 RUC_IDX,
570 RFC_IDX,
571 ROC_IDX,
572 RJC_IDX,
573 MGTPRC_IDX,
574 MGTPDC_IDX,
575 MGTPTC_IDX,
576 TORL_IDX,
577 TORH_IDX,
578 TOTL_IDX,
579 TOTH_IDX,
580 TPR_IDX,
581 TPT_IDX,
582 PTC64_IDX,
583 PTC127_IDX,
584 PTC255_IDX,
585 PTC511_IDX,
586 PTC1023_IDX,
587 PTC1522_IDX,
588 MPTC_IDX,
589 BPTC_IDX,
590 TSCTC_IDX,
591 TSCTFC_IDX,
592 RXCSUM_IDX,
593 WUC_IDX,
594 WUFC_IDX,
595 WUS_IDX,
596 MANC_IDX,
597 IPAV_IDX,
598 WUPL_IDX,
599 MTA_IDX,
600 RA_IDX,
601 VFTA_IDX,
602 IP4AT_IDX,
603 IP6AT_IDX,
604 WUPM_IDX,
605 FFLT_IDX,
606 FFMT_IDX,
607 FFVT_IDX,
608 PBM_IDX,
609 RA_82542_IDX,
610 MTA_82542_IDX,
611 VFTA_82542_IDX,
612 E1K_NUM_OF_REGS
613} E1kRegIndex;
614
615#define E1K_NUM_OF_32BIT_REGS MTA_IDX
616/** The number of registers with strictly increasing offset. */
617#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
618
619
620/**
621 * Define E1000-specific EEPROM layout.
622 */
623struct E1kEEPROM
624{
625 public:
626 EEPROM93C46 eeprom;
627
628#ifdef IN_RING3
629 /**
630 * Initialize EEPROM content.
631 *
632 * @param macAddr MAC address of E1000.
633 */
634 void init(RTMAC &macAddr)
635 {
636 eeprom.init();
637 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
638 eeprom.m_au16Data[0x04] = 0xFFFF;
639 /*
640 * bit 3 - full support for power management
641 * bit 10 - full duplex
642 */
643 eeprom.m_au16Data[0x0A] = 0x4408;
644 eeprom.m_au16Data[0x0B] = 0x001E;
645 eeprom.m_au16Data[0x0C] = 0x8086;
646 eeprom.m_au16Data[0x0D] = 0x100E;
647 eeprom.m_au16Data[0x0E] = 0x8086;
648 eeprom.m_au16Data[0x0F] = 0x3040;
649 eeprom.m_au16Data[0x21] = 0x7061;
650 eeprom.m_au16Data[0x22] = 0x280C;
651 eeprom.m_au16Data[0x23] = 0x00C8;
652 eeprom.m_au16Data[0x24] = 0x00C8;
653 eeprom.m_au16Data[0x2F] = 0x0602;
654 updateChecksum();
655 };
656
657 /**
658 * Compute the checksum as required by E1000 and store it
659 * in the last word.
660 */
661 void updateChecksum()
662 {
663 uint16_t u16Checksum = 0;
664
665 for (int i = 0; i < eeprom.SIZE-1; i++)
666 u16Checksum += eeprom.m_au16Data[i];
667 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
668 };
669
670 /**
671 * First 6 bytes of EEPROM contain MAC address.
672 *
673 * @returns MAC address of E1000.
674 */
675 void getMac(PRTMAC pMac)
676 {
677 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
678 };
679
680 uint32_t read()
681 {
682 return eeprom.read();
683 }
684
685 void write(uint32_t u32Wires)
686 {
687 eeprom.write(u32Wires);
688 }
689
690 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
691 {
692 return eeprom.readWord(u32Addr, pu16Value);
693 }
694
695 int load(PSSMHANDLE pSSM)
696 {
697 return eeprom.load(pSSM);
698 }
699
700 void save(PSSMHANDLE pSSM)
701 {
702 eeprom.save(pSSM);
703 }
704#endif /* IN_RING3 */
705};
706
707
708#define E1K_SPEC_VLAN(s) (s & 0xFFF)
709#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
710#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
711
712struct E1kRxDStatus
713{
714 /** @name Descriptor Status field (3.2.3.1)
715 * @{ */
716 unsigned fDD : 1; /**< Descriptor Done. */
717 unsigned fEOP : 1; /**< End of packet. */
718 unsigned fIXSM : 1; /**< Ignore checksum indication. */
719 unsigned fVP : 1; /**< VLAN, matches VET. */
720 unsigned : 1;
721 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
722 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
723 unsigned fPIF : 1; /**< Passed in-exact filter */
724 /** @} */
725 /** @name Descriptor Errors field (3.2.3.2)
726 * (Only valid when fEOP and fDD are set.)
727 * @{ */
728 unsigned fCE : 1; /**< CRC or alignment error. */
729 unsigned : 4; /**< Reserved, varies with different models... */
730 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
731 unsigned fIPE : 1; /**< IP Checksum error. */
732 unsigned fRXE : 1; /**< RX Data error. */
733 /** @} */
734 /** @name Descriptor Special field (3.2.3.3)
735 * @{ */
736 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
737 /** @} */
738};
739typedef struct E1kRxDStatus E1KRXDST;
740
741struct E1kRxDesc_st
742{
743 uint64_t u64BufAddr; /**< Address of data buffer */
744 uint16_t u16Length; /**< Length of data in buffer */
745 uint16_t u16Checksum; /**< Packet checksum */
746 E1KRXDST status;
747};
748typedef struct E1kRxDesc_st E1KRXDESC;
749AssertCompileSize(E1KRXDESC, 16);
750
751#define E1K_DTYP_LEGACY -1
752#define E1K_DTYP_CONTEXT 0
753#define E1K_DTYP_DATA 1
754
755struct E1kTDLegacy
756{
757 uint64_t u64BufAddr; /**< Address of data buffer */
758 struct TDLCmd_st
759 {
760 unsigned u16Length : 16;
761 unsigned u8CSO : 8;
762 /* CMD field : 8 */
763 unsigned fEOP : 1;
764 unsigned fIFCS : 1;
765 unsigned fIC : 1;
766 unsigned fRS : 1;
767 unsigned fRPS : 1;
768 unsigned fDEXT : 1;
769 unsigned fVLE : 1;
770 unsigned fIDE : 1;
771 } cmd;
772 struct TDLDw3_st
773 {
774 /* STA field */
775 unsigned fDD : 1;
776 unsigned fEC : 1;
777 unsigned fLC : 1;
778 unsigned fTURSV : 1;
779 /* RSV field */
780 unsigned u4RSV : 4;
781 /* CSS field */
782 unsigned u8CSS : 8;
783 /* Special field*/
784 unsigned u16Special: 16;
785 } dw3;
786};
787
788/**
789 * TCP/IP Context Transmit Descriptor, section 3.3.6.
790 */
791struct E1kTDContext
792{
793 struct CheckSum_st
794 {
795 /** TSE: Header start. !TSE: Checksum start. */
796 unsigned u8CSS : 8;
797 /** Checksum offset - where to store it. */
798 unsigned u8CSO : 8;
799 /** Checksum ending (inclusive) offset, 0 = end of packet. */
800 unsigned u16CSE : 16;
801 } ip;
802 struct CheckSum_st tu;
803 struct TDCDw2_st
804 {
805 /** TSE: The total number of payload bytes for this context. Sans header. */
806 unsigned u20PAYLEN : 20;
807 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
808 unsigned u4DTYP : 4;
809 /** TUCMD field, 8 bits
810 * @{ */
811 /** TSE: TCP (set) or UDP (clear). */
812 unsigned fTCP : 1;
813 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
814 * the IP header. Does not affect the checksumming.
815 * @remarks 82544GC/EI interprets a cleared field differently. */
816 unsigned fIP : 1;
817 /** TSE: TCP segmentation enable. When clear the context describes */
818 unsigned fTSE : 1;
819 /** Report status (only applies to dw3.fDD for here). */
820 unsigned fRS : 1;
821 /** Reserved, MBZ. */
822 unsigned fRSV1 : 1;
823 /** Descriptor extension, must be set for this descriptor type. */
824 unsigned fDEXT : 1;
825 /** Reserved, MBZ. */
826 unsigned fRSV2 : 1;
827 /** Interrupt delay enable. */
828 unsigned fIDE : 1;
829 /** @} */
830 } dw2;
831 struct TDCDw3_st
832 {
833 /** Descriptor Done. */
834 unsigned fDD : 1;
835 /** Reserved, MBZ. */
836 unsigned u7RSV : 7;
837 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
838 unsigned u8HDRLEN : 8;
839 /** TSO: Maximum segment size. */
840 unsigned u16MSS : 16;
841 } dw3;
842};
843typedef struct E1kTDContext E1KTXCTX;
844
845/**
846 * TCP/IP Data Transmit Descriptor, section 3.3.7.
847 */
848struct E1kTDData
849{
850 uint64_t u64BufAddr; /**< Address of data buffer */
851 struct TDDCmd_st
852 {
853 /** The total length of data pointed to by this descriptor. */
854 unsigned u20DTALEN : 20;
855 /** The descriptor type - E1K_DTYP_DATA (1). */
856 unsigned u4DTYP : 4;
857 /** @name DCMD field, 8 bits (3.3.7.1).
858 * @{ */
859 /** End of packet. Note TSCTFC update. */
860 unsigned fEOP : 1;
861 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
862 unsigned fIFCS : 1;
863 /** Use the TSE context when set and the normal when clear. */
864 unsigned fTSE : 1;
865 /** Report status (dw3.STA). */
866 unsigned fRS : 1;
867 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
868 unsigned fRPS : 1;
869 /** Descriptor extension, must be set for this descriptor type. */
870 unsigned fDEXT : 1;
871 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
872 * Insert dw3.SPECIAL after ethernet header. */
873 unsigned fVLE : 1;
874 /** Interrupt delay enable. */
875 unsigned fIDE : 1;
876 /** @} */
877 } cmd;
878 struct TDDDw3_st
879 {
880 /** @name STA field (3.3.7.2)
881 * @{ */
882 unsigned fDD : 1; /**< Descriptor done. */
883 unsigned fEC : 1; /**< Excess collision. */
884 unsigned fLC : 1; /**< Late collision. */
885 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
886 unsigned fTURSV : 1;
887 /** @} */
888 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
889 /** @name POPTS (Packet Option) field (3.3.7.3)
890 * @{ */
891 unsigned fIXSM : 1; /**< Insert IP checksum. */
892 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
893 unsigned u6RSV : 6; /**< Reserved, MBZ. */
894 /** @} */
895 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
896 * Requires fEOP, fVLE and CTRL.VME to be set.
897 * @{ */
898 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
899 /** @} */
900 } dw3;
901};
902typedef struct E1kTDData E1KTXDAT;
903
904union E1kTxDesc
905{
906 struct E1kTDLegacy legacy;
907 struct E1kTDContext context;
908 struct E1kTDData data;
909};
910typedef union E1kTxDesc E1KTXDESC;
911AssertCompileSize(E1KTXDESC, 16);
912
913#define RA_CTL_AS 0x0003
914#define RA_CTL_AV 0x8000
915
916union E1kRecAddr
917{
918 uint32_t au32[32];
919 struct RAArray
920 {
921 uint8_t addr[6];
922 uint16_t ctl;
923 } array[16];
924};
925typedef struct E1kRecAddr::RAArray E1KRAELEM;
926typedef union E1kRecAddr E1KRA;
927AssertCompileSize(E1KRA, 8*16);
928
929#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
930#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
931#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
932#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
933
934/** @todo use+extend RTNETIPV4 */
935struct E1kIpHeader
936{
937 /* type of service / version / header length */
938 uint16_t tos_ver_hl;
939 /* total length */
940 uint16_t total_len;
941 /* identification */
942 uint16_t ident;
943 /* fragment offset field */
944 uint16_t offset;
945 /* time to live / protocol*/
946 uint16_t ttl_proto;
947 /* checksum */
948 uint16_t chksum;
949 /* source IP address */
950 uint32_t src;
951 /* destination IP address */
952 uint32_t dest;
953};
954AssertCompileSize(struct E1kIpHeader, 20);
955
956#define E1K_TCP_FIN UINT16_C(0x01)
957#define E1K_TCP_SYN UINT16_C(0x02)
958#define E1K_TCP_RST UINT16_C(0x04)
959#define E1K_TCP_PSH UINT16_C(0x08)
960#define E1K_TCP_ACK UINT16_C(0x10)
961#define E1K_TCP_URG UINT16_C(0x20)
962#define E1K_TCP_ECE UINT16_C(0x40)
963#define E1K_TCP_CWR UINT16_C(0x80)
964#define E1K_TCP_FLAGS UINT16_C(0x3f)
965
966/** @todo use+extend RTNETTCP */
967struct E1kTcpHeader
968{
969 uint16_t src;
970 uint16_t dest;
971 uint32_t seqno;
972 uint32_t ackno;
973 uint16_t hdrlen_flags;
974 uint16_t wnd;
975 uint16_t chksum;
976 uint16_t urgp;
977};
978AssertCompileSize(struct E1kTcpHeader, 20);
979
980
981#ifdef E1K_WITH_TXD_CACHE
982/** The current Saved state version. */
983# define E1K_SAVEDSTATE_VERSION 4
984/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
985# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
986#else /* !E1K_WITH_TXD_CACHE */
987/** The current Saved state version. */
988# define E1K_SAVEDSTATE_VERSION 3
989#endif /* !E1K_WITH_TXD_CACHE */
990/** Saved state version for VirtualBox 4.1 and earlier.
991 * These did not include VLAN tag fields. */
992#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
993/** Saved state version for VirtualBox 3.0 and earlier.
994 * This did not include the configuration part nor the E1kEEPROM. */
995#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
996
997/**
998 * Device state structure.
999 *
1000 * Holds the current state of device.
1001 *
1002 * @implements PDMINETWORKDOWN
1003 * @implements PDMINETWORKCONFIG
1004 * @implements PDMILEDPORTS
1005 */
1006struct E1kState_st
1007{
1008 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1009 PDMIBASE IBase;
1010 PDMINETWORKDOWN INetworkDown;
1011 PDMINETWORKCONFIG INetworkConfig;
1012 PDMILEDPORTS ILeds; /**< LED interface */
1013 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
1014 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1015
1016 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
1017 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
1018 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
1019 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
1020 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
1021 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
1022 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
1023 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
1024 PTMTIMERR3 pTXDTimerR3; /**< Transmit Delay Timer - R3. */
1025 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
1026 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
1027 /** The scatter / gather buffer used for the current outgoing packet - R3. */
1028 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1029
1030 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
1031 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
1032 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
1033 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
1034 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
1035 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
1036 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
1037 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
1038 PTMTIMERR0 pTXDTimerR0; /**< Transmit Delay Timer - R0. */
1039 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
1040 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
1041 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1042 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1043
1044 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
1045 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
1046 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
1047 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
1048 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
1049 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
1050 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
1051 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
1052 PTMTIMERRC pTXDTimerRC; /**< Transmit Delay Timer - RC. */
1053 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
1054 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
1055 /** The scatter / gather buffer used for the current outgoing packet - RC. */
1056 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1057 RTRCPTR RCPtrAlignment;
1058
1059#if HC_ARCH_BITS != 32
1060 uint32_t Alignment1;
1061#endif
1062 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
1063 PDMCRITSECT csRx; /**< RX Critical section. */
1064#ifdef E1K_WITH_TX_CS
1065 PDMCRITSECT csTx; /**< TX Critical section. */
1066#endif /* E1K_WITH_TX_CS */
1067 /** Base address of memory-mapped registers. */
1068 RTGCPHYS addrMMReg;
1069 /** MAC address obtained from the configuration. */
1070 RTMAC macConfigured;
1071 /** Base port of I/O space region. */
1072 RTIOPORT IOPortBase;
1073 /** EMT: */
1074 PCIDEVICE pciDevice;
1075 /** EMT: Last time the interrupt was acknowledged. */
1076 uint64_t u64AckedAt;
1077 /** All: Used for eliminating spurious interrupts. */
1078 bool fIntRaised;
1079 /** EMT: false if the cable is disconnected by the GUI. */
1080 bool fCableConnected;
1081 /** EMT: */
1082 bool fR0Enabled;
1083 /** EMT: */
1084 bool fRCEnabled;
1085 /** EMT: Compute Ethernet CRC for RX packets. */
1086 bool fEthernetCRC;
1087
1088 bool Alignment2[3];
1089 /** Link up delay (in milliseconds). */
1090 uint32_t cMsLinkUpDelay;
1091
1092 /** All: Device register storage. */
1093 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1094 /** TX/RX: Status LED. */
1095 PDMLED led;
1096 /** TX/RX: Number of packet being sent/received to show in debug log. */
1097 uint32_t u32PktNo;
1098
1099 /** EMT: Offset of the register to be read via IO. */
1100 uint32_t uSelectedReg;
1101 /** EMT: Multicast Table Array. */
1102 uint32_t auMTA[128];
1103 /** EMT: Receive Address registers. */
1104 E1KRA aRecAddr;
1105 /** EMT: VLAN filter table array. */
1106 uint32_t auVFTA[128];
1107 /** EMT: Receive buffer size. */
1108 uint16_t u16RxBSize;
1109 /** EMT: Locked state -- no state alteration possible. */
1110 bool fLocked;
1111 /** EMT: */
1112 bool fDelayInts;
1113 /** All: */
1114 bool fIntMaskUsed;
1115
1116 /** N/A: */
1117 bool volatile fMaybeOutOfSpace;
1118 /** EMT: Gets signalled when more RX descriptors become available. */
1119 RTSEMEVENT hEventMoreRxDescAvail;
1120#ifdef E1K_WITH_RXD_CACHE
1121 /** RX: Fetched RX descriptors. */
1122 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1123 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1124 /** RX: Actual number of fetched RX descriptors. */
1125 uint32_t nRxDFetched;
1126 /** RX: Index in cache of RX descriptor being processed. */
1127 uint32_t iRxDCurrent;
1128#endif /* E1K_WITH_RXD_CACHE */
1129
1130 /** TX: Context used for TCP segmentation packets. */
1131 E1KTXCTX contextTSE;
1132 /** TX: Context used for ordinary packets. */
1133 E1KTXCTX contextNormal;
1134#ifdef E1K_WITH_TXD_CACHE
1135 /** TX: Fetched TX descriptors. */
1136 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1137 /** TX: Actual number of fetched TX descriptors. */
1138 uint8_t nTxDFetched;
1139 /** TX: Index in cache of TX descriptor being processed. */
1140 uint8_t iTxDCurrent;
1141 /** TX: Will this frame be sent as GSO. */
1142 bool fGSO;
1143 /** Alignment padding. */
1144 bool fReserved;
1145 /** TX: Number of bytes in next packet. */
1146 uint32_t cbTxAlloc;
1147
1148#endif /* E1K_WITH_TXD_CACHE */
1149 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1150 * applicable to the current TSE mode. */
1151 PDMNETWORKGSO GsoCtx;
1152 /** Scratch space for holding the loopback / fallback scatter / gather
1153 * descriptor. */
1154 union
1155 {
1156 PDMSCATTERGATHER Sg;
1157 uint8_t padding[8 * sizeof(RTUINTPTR)];
1158 } uTxFallback;
1159 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1160 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1161 /** TX: Number of bytes assembled in TX packet buffer. */
1162 uint16_t u16TxPktLen;
1163 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1164 bool fGSOEnabled;
1165 /** TX: IP checksum has to be inserted if true. */
1166 bool fIPcsum;
1167 /** TX: TCP/UDP checksum has to be inserted if true. */
1168 bool fTCPcsum;
1169 /** TX: VLAN tag has to be inserted if true. */
1170 bool fVTag;
1171 /** TX: TCI part of VLAN tag to be inserted. */
1172 uint16_t u16VTagTCI;
1173 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1174 uint32_t u32PayRemain;
1175 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1176 uint16_t u16HdrRemain;
1177 /** TX TSE fallback: Flags from template header. */
1178 uint16_t u16SavedFlags;
1179 /** TX TSE fallback: Partial checksum from template header. */
1180 uint32_t u32SavedCsum;
1181 /** ?: Emulated controller type. */
1182 E1KCHIP eChip;
1183
1184 /** EMT: EEPROM emulation */
1185 E1kEEPROM eeprom;
1186 /** EMT: Physical interface emulation. */
1187 PHY phy;
1188
1189#if 0
1190 /** Alignment padding. */
1191 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1192#endif
1193
1194 STAMCOUNTER StatReceiveBytes;
1195 STAMCOUNTER StatTransmitBytes;
1196#if defined(VBOX_WITH_STATISTICS)
1197 STAMPROFILEADV StatMMIOReadRZ;
1198 STAMPROFILEADV StatMMIOReadR3;
1199 STAMPROFILEADV StatMMIOWriteRZ;
1200 STAMPROFILEADV StatMMIOWriteR3;
1201 STAMPROFILEADV StatEEPROMRead;
1202 STAMPROFILEADV StatEEPROMWrite;
1203 STAMPROFILEADV StatIOReadRZ;
1204 STAMPROFILEADV StatIOReadR3;
1205 STAMPROFILEADV StatIOWriteRZ;
1206 STAMPROFILEADV StatIOWriteR3;
1207 STAMPROFILEADV StatLateIntTimer;
1208 STAMCOUNTER StatLateInts;
1209 STAMCOUNTER StatIntsRaised;
1210 STAMCOUNTER StatIntsPrevented;
1211 STAMPROFILEADV StatReceive;
1212 STAMPROFILEADV StatReceiveCRC;
1213 STAMPROFILEADV StatReceiveFilter;
1214 STAMPROFILEADV StatReceiveStore;
1215 STAMPROFILEADV StatTransmitRZ;
1216 STAMPROFILEADV StatTransmitR3;
1217 STAMPROFILE StatTransmitSendRZ;
1218 STAMPROFILE StatTransmitSendR3;
1219 STAMPROFILE StatRxOverflow;
1220 STAMCOUNTER StatRxOverflowWakeup;
1221 STAMCOUNTER StatTxDescCtxNormal;
1222 STAMCOUNTER StatTxDescCtxTSE;
1223 STAMCOUNTER StatTxDescLegacy;
1224 STAMCOUNTER StatTxDescData;
1225 STAMCOUNTER StatTxDescTSEData;
1226 STAMCOUNTER StatTxPathFallback;
1227 STAMCOUNTER StatTxPathGSO;
1228 STAMCOUNTER StatTxPathRegular;
1229 STAMCOUNTER StatPHYAccesses;
1230 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1231 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1232#endif /* VBOX_WITH_STATISTICS */
1233
1234#ifdef E1K_INT_STATS
1235 /* Internal stats */
1236 uint64_t u64ArmedAt;
1237 uint64_t uStatMaxTxDelay;
1238 uint32_t uStatInt;
1239 uint32_t uStatIntTry;
1240 uint32_t uStatIntLower;
1241 uint32_t uStatIntDly;
1242 int32_t iStatIntLost;
1243 int32_t iStatIntLostOne;
1244 uint32_t uStatDisDly;
1245 uint32_t uStatIntSkip;
1246 uint32_t uStatIntLate;
1247 uint32_t uStatIntMasked;
1248 uint32_t uStatIntEarly;
1249 uint32_t uStatIntRx;
1250 uint32_t uStatIntTx;
1251 uint32_t uStatIntICS;
1252 uint32_t uStatIntRDTR;
1253 uint32_t uStatIntRXDMT0;
1254 uint32_t uStatIntTXQE;
1255 uint32_t uStatTxNoRS;
1256 uint32_t uStatTxIDE;
1257 uint32_t uStatTxDelayed;
1258 uint32_t uStatTxDelayExp;
1259 uint32_t uStatTAD;
1260 uint32_t uStatTID;
1261 uint32_t uStatRAD;
1262 uint32_t uStatRID;
1263 uint32_t uStatRxFrm;
1264 uint32_t uStatTxFrm;
1265 uint32_t uStatDescCtx;
1266 uint32_t uStatDescDat;
1267 uint32_t uStatDescLeg;
1268 uint32_t uStatTx1514;
1269 uint32_t uStatTx2962;
1270 uint32_t uStatTx4410;
1271 uint32_t uStatTx5858;
1272 uint32_t uStatTx7306;
1273 uint32_t uStatTx8754;
1274 uint32_t uStatTx16384;
1275 uint32_t uStatTx32768;
1276 uint32_t uStatTxLarge;
1277 uint32_t uStatAlign;
1278#endif /* E1K_INT_STATS */
1279};
1280typedef struct E1kState_st E1KSTATE;
1281/** Pointer to the E1000 device state. */
1282typedef E1KSTATE *PE1KSTATE;
1283
1284#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1285
1286/* Forward declarations ******************************************************/
1287static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread);
1288
1289static int e1kRegReadUnimplemented (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1290static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1291static int e1kRegReadAutoClear (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1292static int e1kRegReadDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1293static int e1kRegWriteDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1294#if 0 /* unused */
1295static int e1kRegReadCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1296#endif
1297static int e1kRegWriteCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1298static int e1kRegReadEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1299static int e1kRegWriteEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1300static int e1kRegWriteEERD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1301static int e1kRegWriteMDIC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1302static int e1kRegReadICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1303static int e1kRegWriteICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1304static int e1kRegWriteICS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1305static int e1kRegWriteIMS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1306static int e1kRegWriteIMC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1307static int e1kRegWriteRCTL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1308static int e1kRegWritePBA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1309static int e1kRegWriteRDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1310static int e1kRegWriteRDTR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1311static int e1kRegWriteTDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1312static int e1kRegReadMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1313static int e1kRegWriteMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1314static int e1kRegReadRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1315static int e1kRegWriteRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1316static int e1kRegReadVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1317static int e1kRegWriteVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1318
1319/**
1320 * Register map table.
1321 *
1322 * Override pfnRead and pfnWrite to get register-specific behavior.
1323 */
1324static const struct E1kRegMap_st
1325{
1326 /** Register offset in the register space. */
1327 uint32_t offset;
1328 /** Size in bytes. Registers of size > 4 are in fact tables. */
1329 uint32_t size;
1330 /** Readable bits. */
1331 uint32_t readable;
1332 /** Writable bits. */
1333 uint32_t writable;
1334 /** Read callback. */
1335 int (*pfnRead)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1336 /** Write callback. */
1337 int (*pfnWrite)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1338 /** Abbreviated name. */
1339 const char *abbrev;
1340 /** Full name. */
1341 const char *name;
1342} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1343{
1344 /* offset size read mask write mask read callback write callback abbrev full name */
1345 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1346 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1347 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1348 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1349 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1350 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1351 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1352 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1353 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1354 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1355 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1356 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1357 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1358 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1359 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1360 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1361 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1362 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1363 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1364 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1365 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1366 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1367 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1368 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1369 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1370 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1371 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1372 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1373 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1374 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1375 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1376 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1377 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1378 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1379 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1380 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1381 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1382 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1383 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1384 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1385 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1386 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1387 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1388 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1389 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1390 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1391 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1392 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1393 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1394 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1395 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1396 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1397 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1398 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1399 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1400 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1401 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1402 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1403 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1404 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1405 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1406 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1407 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1408 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1409 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1410 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1411 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1412 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1413 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1414 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1415 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1416 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1417 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1418 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1419 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1420 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1421 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1422 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1423 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1424 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1425 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1426 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1427 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1428 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1429 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1430 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1431 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1432 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1433 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1434 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1435 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1436 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1437 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1438 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1439 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1440 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1441 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1442 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1443 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1444 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1445 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1446 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1447 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1448 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1449 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1450 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1451 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1452 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1453 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1454 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1455 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1456 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1457 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1458 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1459 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1460 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1461 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1462 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1463 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1464 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1465 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1466 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1467 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1468 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1469 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1470 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1471 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1472 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1473 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1474 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1475 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1476 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1477 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1478 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1479 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1480};
1481
1482#ifdef LOG_ENABLED
1483
1484/**
1485 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1486 *
1487 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1488 *
1489 * @returns The buffer.
1490 *
1491 * @param u32 The word to convert into string.
1492 * @param mask Selects which bytes to convert.
1493 * @param buf Where to put the result.
1494 */
1495static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1496{
1497 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1498 {
1499 if (mask & 0xF)
1500 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1501 else
1502 *ptr = '.';
1503 }
1504 buf[8] = 0;
1505 return buf;
1506}
1507
1508/**
1509 * Returns timer name for debug purposes.
1510 *
1511 * @returns The timer name.
1512 *
1513 * @param pThis The device state structure.
1514 * @param pTimer The timer to get the name for.
1515 */
1516DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, PTMTIMER pTimer)
1517{
1518 if (pTimer == pThis->CTX_SUFF(pTIDTimer))
1519 return "TID";
1520 if (pTimer == pThis->CTX_SUFF(pTADTimer))
1521 return "TAD";
1522 if (pTimer == pThis->CTX_SUFF(pRIDTimer))
1523 return "RID";
1524 if (pTimer == pThis->CTX_SUFF(pRADTimer))
1525 return "RAD";
1526 if (pTimer == pThis->CTX_SUFF(pIntTimer))
1527 return "Int";
1528 if (pTimer == pThis->CTX_SUFF(pTXDTimer))
1529 return "TXD";
1530 if (pTimer == pThis->CTX_SUFF(pLUTimer))
1531 return "LinkUp";
1532 return "unknown";
1533}
1534
1535#endif /* DEBUG */
1536
1537/**
1538 * Arm a timer.
1539 *
1540 * @param pThis Pointer to the device state structure.
1541 * @param pTimer Pointer to the timer.
1542 * @param uExpireIn Expiration interval in microseconds.
1543 */
1544DECLINLINE(void) e1kArmTimer(PE1KSTATE pThis, PTMTIMER pTimer, uint32_t uExpireIn)
1545{
1546 if (pThis->fLocked)
1547 return;
1548
1549 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1550 pThis->szPrf, e1kGetTimerName(pThis, pTimer), uExpireIn));
1551 TMTimerSetMicro(pTimer, uExpireIn);
1552}
1553
1554/**
1555 * Cancel a timer.
1556 *
1557 * @param pThis Pointer to the device state structure.
1558 * @param pTimer Pointer to the timer.
1559 */
1560DECLINLINE(void) e1kCancelTimer(PE1KSTATE pThis, PTMTIMER pTimer)
1561{
1562 E1kLog2(("%s Stopping %s timer...\n",
1563 pThis->szPrf, e1kGetTimerName(pThis, pTimer)));
1564 int rc = TMTimerStop(pTimer);
1565 if (RT_FAILURE(rc))
1566 {
1567 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1568 pThis->szPrf, rc));
1569 }
1570}
1571
1572#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1573#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1574
1575#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1576#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1577#define e1kCsRxIsOwner(ps) PDMCritSectIsOwner(&ps->csRx)
1578
1579#ifndef E1K_WITH_TX_CS
1580# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1581# define e1kCsTxLeave(ps) do { } while (0)
1582#else /* E1K_WITH_TX_CS */
1583# define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1584# define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1585#endif /* E1K_WITH_TX_CS */
1586
1587#ifdef IN_RING3
1588
1589/**
1590 * Wakeup the RX thread.
1591 */
1592static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1593{
1594 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
1595 if ( pThis->fMaybeOutOfSpace
1596 && pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1597 {
1598 STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1599 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1600 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
1601 }
1602}
1603
1604/**
1605 * Hardware reset. Revert all registers to initial values.
1606 *
1607 * @param pThis The device state structure.
1608 */
1609static void e1kHardReset(PE1KSTATE pThis)
1610{
1611 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1612 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1613 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1614#ifdef E1K_INIT_RA0
1615 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1616 sizeof(pThis->macConfigured.au8));
1617 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1618#endif /* E1K_INIT_RA0 */
1619 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1620 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1621 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1622 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1623 Assert(GET_BITS(RCTL, BSIZE) == 0);
1624 pThis->u16RxBSize = 2048;
1625
1626 /* Reset promiscuous mode */
1627 if (pThis->pDrvR3)
1628 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, false);
1629
1630#ifdef E1K_WITH_TXD_CACHE
1631 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1632 if (RT_LIKELY(rc == VINF_SUCCESS))
1633 {
1634 pThis->nTxDFetched = 0;
1635 pThis->iTxDCurrent = 0;
1636 pThis->fGSO = false;
1637 pThis->cbTxAlloc = 0;
1638 e1kCsTxLeave(pThis);
1639 }
1640#endif /* E1K_WITH_TXD_CACHE */
1641#ifdef E1K_WITH_RXD_CACHE
1642 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1643 {
1644 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1645 e1kCsRxLeave(pThis);
1646 }
1647#endif /* E1K_WITH_RXD_CACHE */
1648}
1649
1650#endif /* IN_RING3 */
1651
1652/**
1653 * Compute Internet checksum.
1654 *
1655 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1656 *
1657 * @param pThis The device state structure.
1658 * @param cpPacket The packet.
1659 * @param cb The size of the packet.
1660 * @param cszText A string denoting direction of packet transfer.
1661 *
1662 * @return The 1's complement of the 1's complement sum.
1663 *
1664 * @thread E1000_TX
1665 */
1666static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1667{
1668 uint32_t csum = 0;
1669 uint16_t *pu16 = (uint16_t *)pvBuf;
1670
1671 while (cb > 1)
1672 {
1673 csum += *pu16++;
1674 cb -= 2;
1675 }
1676 if (cb)
1677 csum += *(uint8_t*)pu16;
1678 while (csum >> 16)
1679 csum = (csum >> 16) + (csum & 0xFFFF);
1680 return ~csum;
1681}
1682
1683/**
1684 * Dump a packet to debug log.
1685 *
1686 * @param pThis The device state structure.
1687 * @param cpPacket The packet.
1688 * @param cb The size of the packet.
1689 * @param cszText A string denoting direction of packet transfer.
1690 * @thread E1000_TX
1691 */
1692DECLINLINE(void) e1kPacketDump(PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *cszText)
1693{
1694#ifdef DEBUG
1695 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1696 {
1697 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1698 pThis->szPrf, cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1699 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1700 {
1701 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1702 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1703 if (*(cpPacket+14+6) == 0x6)
1704 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1705 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1706 }
1707 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1708 {
1709 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1710 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1711 if (*(cpPacket+14+6) == 0x6)
1712 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1713 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1714 }
1715 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1716 e1kCsLeave(pThis);
1717 }
1718#else
1719 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1720 {
1721 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1722 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1723 cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1724 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1725 else
1726 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1727 cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1728 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1729 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1730 e1kCsLeave(pThis);
1731 }
1732#endif
1733}
1734
1735/**
1736 * Determine the type of transmit descriptor.
1737 *
1738 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1739 *
1740 * @param pDesc Pointer to descriptor union.
1741 * @thread E1000_TX
1742 */
1743DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1744{
1745 if (pDesc->legacy.cmd.fDEXT)
1746 return pDesc->context.dw2.u4DTYP;
1747 return E1K_DTYP_LEGACY;
1748}
1749
1750/**
1751 * Dump receive descriptor to debug log.
1752 *
1753 * @param pThis The device state structure.
1754 * @param pDesc Pointer to the descriptor.
1755 * @thread E1000_RX
1756 */
1757static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC* pDesc)
1758{
1759 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1760 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1761 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1762 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1763 pDesc->status.fPIF ? "PIF" : "pif",
1764 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1765 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1766 pDesc->status.fVP ? "VP" : "vp",
1767 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1768 pDesc->status.fEOP ? "EOP" : "eop",
1769 pDesc->status.fDD ? "DD" : "dd",
1770 pDesc->status.fRXE ? "RXE" : "rxe",
1771 pDesc->status.fIPE ? "IPE" : "ipe",
1772 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1773 pDesc->status.fCE ? "CE" : "ce",
1774 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1775 E1K_SPEC_VLAN(pDesc->status.u16Special),
1776 E1K_SPEC_PRI(pDesc->status.u16Special)));
1777}
1778
1779/**
1780 * Dump transmit descriptor to debug log.
1781 *
1782 * @param pThis The device state structure.
1783 * @param pDesc Pointer to descriptor union.
1784 * @param cszDir A string denoting direction of descriptor transfer
1785 * @thread E1000_TX
1786 */
1787static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, const char* cszDir,
1788 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1789{
1790 /*
1791 * Unfortunately we cannot use our format handler here, we want R0 logging
1792 * as well.
1793 */
1794 switch (e1kGetDescType(pDesc))
1795 {
1796 case E1K_DTYP_CONTEXT:
1797 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
1798 pThis->szPrf, cszDir, cszDir));
1799 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1800 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1801 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1802 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1803 pDesc->context.dw2.fIDE ? " IDE":"",
1804 pDesc->context.dw2.fRS ? " RS" :"",
1805 pDesc->context.dw2.fTSE ? " TSE":"",
1806 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1807 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1808 pDesc->context.dw2.u20PAYLEN,
1809 pDesc->context.dw3.u8HDRLEN,
1810 pDesc->context.dw3.u16MSS,
1811 pDesc->context.dw3.fDD?"DD":""));
1812 break;
1813 case E1K_DTYP_DATA:
1814 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1815 pThis->szPrf, cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1816 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1817 pDesc->data.u64BufAddr,
1818 pDesc->data.cmd.u20DTALEN));
1819 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1820 pDesc->data.cmd.fIDE ? " IDE" :"",
1821 pDesc->data.cmd.fVLE ? " VLE" :"",
1822 pDesc->data.cmd.fRPS ? " RPS" :"",
1823 pDesc->data.cmd.fRS ? " RS" :"",
1824 pDesc->data.cmd.fTSE ? " TSE" :"",
1825 pDesc->data.cmd.fIFCS? " IFCS":"",
1826 pDesc->data.cmd.fEOP ? " EOP" :"",
1827 pDesc->data.dw3.fDD ? " DD" :"",
1828 pDesc->data.dw3.fEC ? " EC" :"",
1829 pDesc->data.dw3.fLC ? " LC" :"",
1830 pDesc->data.dw3.fTXSM? " TXSM":"",
1831 pDesc->data.dw3.fIXSM? " IXSM":"",
1832 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
1833 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
1834 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
1835 break;
1836 case E1K_DTYP_LEGACY:
1837 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1838 pThis->szPrf, cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1839 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1840 pDesc->data.u64BufAddr,
1841 pDesc->legacy.cmd.u16Length));
1842 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1843 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1844 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1845 pDesc->legacy.cmd.fRPS ? " RPS" :"",
1846 pDesc->legacy.cmd.fRS ? " RS" :"",
1847 pDesc->legacy.cmd.fIC ? " IC" :"",
1848 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1849 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1850 pDesc->legacy.dw3.fDD ? " DD" :"",
1851 pDesc->legacy.dw3.fEC ? " EC" :"",
1852 pDesc->legacy.dw3.fLC ? " LC" :"",
1853 pDesc->legacy.cmd.u8CSO,
1854 pDesc->legacy.dw3.u8CSS,
1855 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
1856 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
1857 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
1858 break;
1859 default:
1860 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1861 pThis->szPrf, cszDir, cszDir));
1862 break;
1863 }
1864}
1865
1866/**
1867 * Raise interrupt if not masked.
1868 *
1869 * @param pThis The device state structure.
1870 */
1871static int e1kRaiseInterrupt(PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
1872{
1873 int rc = e1kCsEnter(pThis, rcBusy);
1874 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1875 return rc;
1876
1877 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
1878 ICR |= u32IntCause;
1879 if (ICR & IMS)
1880 {
1881#if 0
1882 if (pThis->fDelayInts)
1883 {
1884 E1K_INC_ISTAT_CNT(pThis->uStatIntDly);
1885 pThis->iStatIntLostOne = 1;
1886 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1887 pThis->szPrf, ICR));
1888#define E1K_LOST_IRQ_THRSLD 20
1889//#define E1K_LOST_IRQ_THRSLD 200000000
1890 if (pThis->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1891 {
1892 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1893 pThis->szPrf, pThis->uStatIntDly, pThis->uStatIntLate));
1894 pThis->fIntMaskUsed = false;
1895 pThis->uStatDisDly++;
1896 }
1897 }
1898 else
1899#endif
1900 if (pThis->fIntRaised)
1901 {
1902 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
1903 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1904 pThis->szPrf, ICR & IMS));
1905 }
1906 else
1907 {
1908#ifdef E1K_ITR_ENABLED
1909 uint64_t tstamp = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
1910 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1911 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pThis->u64AckedAt = %d, ITR * 256 = %d\n",
1912 pThis->szPrf, (uint32_t)(tstamp - pThis->u64AckedAt), ITR * 256));
1913 //if (!!ITR && pThis->fIntMaskUsed && tstamp - pThis->u64AckedAt < ITR * 256)
1914 if (!!ITR && tstamp - pThis->u64AckedAt < ITR * 256 && !(ICR & ICR_RXT0))
1915 {
1916 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
1917 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1918 pThis->szPrf, (uint32_t)(tstamp - pThis->u64AckedAt), ITR * 256));
1919 }
1920 else
1921#endif
1922 {
1923
1924 /* Since we are delivering the interrupt now
1925 * there is no need to do it later -- stop the timer.
1926 */
1927 TMTimerStop(pThis->CTX_SUFF(pIntTimer));
1928 E1K_INC_ISTAT_CNT(pThis->uStatInt);
1929 STAM_COUNTER_INC(&pThis->StatIntsRaised);
1930 /* Got at least one unmasked interrupt cause */
1931 pThis->fIntRaised = true;
1932 /* Raise(1) INTA(0) */
1933 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1934 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
1935 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1936 pThis->szPrf, ICR & IMS));
1937 }
1938 }
1939 }
1940 else
1941 {
1942 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
1943 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1944 pThis->szPrf, ICR, IMS));
1945 }
1946 e1kCsLeave(pThis);
1947 return VINF_SUCCESS;
1948}
1949
1950/**
1951 * Compute the physical address of the descriptor.
1952 *
1953 * @returns the physical address of the descriptor.
1954 *
1955 * @param baseHigh High-order 32 bits of descriptor table address.
1956 * @param baseLow Low-order 32 bits of descriptor table address.
1957 * @param idxDesc The descriptor index in the table.
1958 */
1959DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1960{
1961 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1962 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1963}
1964
1965/**
1966 * Advance the head pointer of the receive descriptor queue.
1967 *
1968 * @remarks RDH always points to the next available RX descriptor.
1969 *
1970 * @param pThis The device state structure.
1971 */
1972DECLINLINE(void) e1kAdvanceRDH(PE1KSTATE pThis)
1973{
1974 Assert(e1kCsRxIsOwner(pThis));
1975 //e1kCsEnter(pThis, RT_SRC_POS);
1976 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1977 RDH = 0;
1978 /*
1979 * Compute current receive queue length and fire RXDMT0 interrupt
1980 * if we are low on receive buffers
1981 */
1982 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1983 /*
1984 * The minimum threshold is controlled by RDMTS bits of RCTL:
1985 * 00 = 1/2 of RDLEN
1986 * 01 = 1/4 of RDLEN
1987 * 10 = 1/8 of RDLEN
1988 * 11 = reserved
1989 */
1990 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1991 if (uRQueueLen <= uMinRQThreshold)
1992 {
1993 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1994 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1995 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
1996 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
1997 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXDMT0);
1998 }
1999 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2000 pThis->szPrf, RDH, RDT, uRQueueLen));
2001 //e1kCsLeave(pThis);
2002}
2003
2004#ifdef E1K_WITH_RXD_CACHE
2005/**
2006 * Return the number of RX descriptor that belong to the hardware.
2007 *
2008 * @returns the number of available descriptors in RX ring.
2009 * @param pThis The device state structure.
2010 * @thread ???
2011 */
2012DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
2013{
2014 /**
2015 * Make sure RDT won't change during computation. EMT may modify RDT at
2016 * any moment.
2017 */
2018 uint32_t rdt = RDT;
2019 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
2020}
2021
2022DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
2023{
2024 return pThis->nRxDFetched > pThis->iRxDCurrent ?
2025 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
2026}
2027
2028DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
2029{
2030 return pThis->iRxDCurrent >= pThis->nRxDFetched;
2031}
2032
2033/**
2034 * Load receive descriptors from guest memory. The caller needs to be in Rx
2035 * critical section.
2036 *
2037 * We need two physical reads in case the tail wrapped around the end of RX
2038 * descriptor ring.
2039 *
2040 * @returns the actual number of descriptors fetched.
2041 * @param pThis The device state structure.
2042 * @param pDesc Pointer to descriptor union.
2043 * @param addr Physical address in guest context.
2044 * @thread EMT, RX
2045 */
2046DECLINLINE(unsigned) e1kRxDPrefetch(PE1KSTATE pThis)
2047{
2048 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
2049 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
2050 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
2051 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
2052 Assert(nDescsTotal != 0);
2053 if (nDescsTotal == 0)
2054 return 0;
2055 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
2056 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2057 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2058 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2059 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2060 nFirstNotLoaded, nDescsInSingleRead));
2061 if (nDescsToFetch == 0)
2062 return 0;
2063 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2064 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2065 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2066 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2067 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2068 // unsigned i, j;
2069 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2070 // {
2071 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2072 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2073 // }
2074 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2075 pThis->szPrf, nDescsInSingleRead,
2076 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
2077 nFirstNotLoaded, RDLEN, RDH, RDT));
2078 if (nDescsToFetch > nDescsInSingleRead)
2079 {
2080 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2081 ((uint64_t)RDBAH << 32) + RDBAL,
2082 pFirstEmptyDesc + nDescsInSingleRead,
2083 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2084 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2085 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2086 // {
2087 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2088 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2089 // }
2090 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2091 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2092 RDBAH, RDBAL));
2093 }
2094 pThis->nRxDFetched += nDescsToFetch;
2095 return nDescsToFetch;
2096}
2097
2098/**
2099 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2100 * RX ring if the cache is empty.
2101 *
2102 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2103 * go out of sync with RDH which will cause trouble when EMT checks if the
2104 * cache is empty to do pre-fetch @bugref(6217).
2105 *
2106 * @param pThis The device state structure.
2107 * @thread RX
2108 */
2109DECLINLINE(E1KRXDESC*) e1kRxDGet(PE1KSTATE pThis)
2110{
2111 Assert(e1kCsRxIsOwner(pThis));
2112 /* Check the cache first. */
2113 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2114 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2115 /* Cache is empty, reset it and check if we can fetch more. */
2116 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2117 if (e1kRxDPrefetch(pThis))
2118 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2119 /* Out of Rx descriptors. */
2120 return NULL;
2121}
2122
2123/**
2124 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2125 * pointer. The descriptor gets written back to the RXD ring.
2126 *
2127 * @param pThis The device state structure.
2128 * @param pDesc The descriptor being "returned" to the RX ring.
2129 * @thread RX
2130 */
2131DECLINLINE(void) e1kRxDPut(PE1KSTATE pThis, E1KRXDESC* pDesc)
2132{
2133 Assert(e1kCsRxIsOwner(pThis));
2134 pThis->iRxDCurrent++;
2135 // Assert(pDesc >= pThis->aRxDescriptors);
2136 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2137 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2138 // uint32_t rdh = RDH;
2139 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2140 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2141 e1kDescAddr(RDBAH, RDBAL, RDH),
2142 pDesc, sizeof(E1KRXDESC));
2143 e1kAdvanceRDH(pThis);
2144 e1kPrintRDesc(pThis, pDesc);
2145}
2146
2147/**
2148 * Store a fragment of received packet at the specifed address.
2149 *
2150 * @param pThis The device state structure.
2151 * @param pDesc The next available RX descriptor.
2152 * @param pvBuf The fragment.
2153 * @param cb The size of the fragment.
2154 */
2155static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2156{
2157 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2158 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2159 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2160 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2161 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2162 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2163}
2164
2165#else /* !E1K_WITH_RXD_CACHE */
2166
2167/**
2168 * Store a fragment of received packet that fits into the next available RX
2169 * buffer.
2170 *
2171 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2172 *
2173 * @param pThis The device state structure.
2174 * @param pDesc The next available RX descriptor.
2175 * @param pvBuf The fragment.
2176 * @param cb The size of the fragment.
2177 */
2178static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2179{
2180 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2181 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2182 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2183 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2184 /* Write back the descriptor */
2185 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2186 e1kPrintRDesc(pThis, pDesc);
2187 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2188 /* Advance head */
2189 e1kAdvanceRDH(pThis);
2190 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2191 if (pDesc->status.fEOP)
2192 {
2193 /* Complete packet has been stored -- it is time to let the guest know. */
2194#ifdef E1K_USE_RX_TIMERS
2195 if (RDTR)
2196 {
2197 /* Arm the timer to fire in RDTR usec (discard .024) */
2198 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2199 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2200 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2201 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2202 }
2203 else
2204 {
2205#endif
2206 /* 0 delay means immediate interrupt */
2207 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2208 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2209#ifdef E1K_USE_RX_TIMERS
2210 }
2211#endif
2212 }
2213 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2214}
2215#endif /* !E1K_WITH_RXD_CACHE */
2216
2217/**
2218 * Returns true if it is a broadcast packet.
2219 *
2220 * @returns true if destination address indicates broadcast.
2221 * @param pvBuf The ethernet packet.
2222 */
2223DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2224{
2225 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2226 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2227}
2228
2229/**
2230 * Returns true if it is a multicast packet.
2231 *
2232 * @remarks returns true for broadcast packets as well.
2233 * @returns true if destination address indicates multicast.
2234 * @param pvBuf The ethernet packet.
2235 */
2236DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2237{
2238 return (*(char*)pvBuf) & 1;
2239}
2240
2241/**
2242 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2243 *
2244 * @remarks We emulate checksum offloading for major packets types only.
2245 *
2246 * @returns VBox status code.
2247 * @param pThis The device state structure.
2248 * @param pFrame The available data.
2249 * @param cb Number of bytes available in the buffer.
2250 * @param status Bit fields containing status info.
2251 */
2252static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2253{
2254 /** @todo
2255 * It is not safe to bypass checksum verification for packets coming
2256 * from real wire. We currently unable to tell where packets are
2257 * coming from so we tell the driver to ignore our checksum flags
2258 * and do verification in software.
2259 */
2260#if 0
2261 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2262
2263 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2264
2265 switch (uEtherType)
2266 {
2267 case 0x800: /* IPv4 */
2268 {
2269 pStatus->fIXSM = false;
2270 pStatus->fIPCS = true;
2271 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2272 /* TCP/UDP checksum offloading works with TCP and UDP only */
2273 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2274 break;
2275 }
2276 case 0x86DD: /* IPv6 */
2277 pStatus->fIXSM = false;
2278 pStatus->fIPCS = false;
2279 pStatus->fTCPCS = true;
2280 break;
2281 default: /* ARP, VLAN, etc. */
2282 pStatus->fIXSM = true;
2283 break;
2284 }
2285#else
2286 pStatus->fIXSM = true;
2287#endif
2288 return VINF_SUCCESS;
2289}
2290
2291/**
2292 * Pad and store received packet.
2293 *
2294 * @remarks Make sure that the packet appears to upper layer as one coming
2295 * from real Ethernet: pad it and insert FCS.
2296 *
2297 * @returns VBox status code.
2298 * @param pThis The device state structure.
2299 * @param pvBuf The available data.
2300 * @param cb Number of bytes available in the buffer.
2301 * @param status Bit fields containing status info.
2302 */
2303static int e1kHandleRxPacket(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2304{
2305#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2306 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2307 uint8_t *ptr = rxPacket;
2308
2309 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2310 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2311 return rc;
2312
2313 if (cb > 70) /* unqualified guess */
2314 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2315
2316 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2317 Assert(cb > 16);
2318 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2319 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2320 if (status.fVP)
2321 {
2322 /* VLAN packet -- strip VLAN tag in VLAN mode */
2323 if ((CTRL & CTRL_VME) && cb > 16)
2324 {
2325 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2326 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2327 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2328 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2329 cb -= 4;
2330 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2331 pThis->szPrf, status.u16Special, cb));
2332 }
2333 else
2334 status.fVP = false; /* Set VP only if we stripped the tag */
2335 }
2336 else
2337 memcpy(rxPacket, pvBuf, cb);
2338 /* Pad short packets */
2339 if (cb < 60)
2340 {
2341 memset(rxPacket + cb, 0, 60 - cb);
2342 cb = 60;
2343 }
2344 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2345 {
2346 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2347 /*
2348 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2349 * is ignored by most of drivers we may as well save us the trouble
2350 * of calculating it (see EthernetCRC CFGM parameter).
2351 */
2352 if (pThis->fEthernetCRC)
2353 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2354 cb += sizeof(uint32_t);
2355 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2356 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2357 }
2358 /* Compute checksum of complete packet */
2359 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2360 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2361
2362 /* Update stats */
2363 E1K_INC_CNT32(GPRC);
2364 if (e1kIsBroadcast(pvBuf))
2365 E1K_INC_CNT32(BPRC);
2366 else if (e1kIsMulticast(pvBuf))
2367 E1K_INC_CNT32(MPRC);
2368 /* Update octet receive counter */
2369 E1K_ADD_CNT64(GORCL, GORCH, cb);
2370 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2371 if (cb == 64)
2372 E1K_INC_CNT32(PRC64);
2373 else if (cb < 128)
2374 E1K_INC_CNT32(PRC127);
2375 else if (cb < 256)
2376 E1K_INC_CNT32(PRC255);
2377 else if (cb < 512)
2378 E1K_INC_CNT32(PRC511);
2379 else if (cb < 1024)
2380 E1K_INC_CNT32(PRC1023);
2381 else
2382 E1K_INC_CNT32(PRC1522);
2383
2384 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2385
2386#ifdef E1K_WITH_RXD_CACHE
2387 while (cb > 0)
2388 {
2389 E1KRXDESC *pDesc = e1kRxDGet(pThis);
2390
2391 if (pDesc == NULL)
2392 {
2393 E1kLog(("%s Out of receive buffers, dropping the packet "
2394 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2395 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2396 break;
2397 }
2398#else /* !E1K_WITH_RXD_CACHE */
2399 if (RDH == RDT)
2400 {
2401 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2402 pThis->szPrf));
2403 }
2404 /* Store the packet to receive buffers */
2405 while (RDH != RDT)
2406 {
2407 /* Load the descriptor pointed by head */
2408 E1KRXDESC desc, *pDesc = &desc;
2409 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2410 &desc, sizeof(desc));
2411#endif /* !E1K_WITH_RXD_CACHE */
2412 if (pDesc->u64BufAddr)
2413 {
2414 /* Update descriptor */
2415 pDesc->status = status;
2416 pDesc->u16Checksum = checksum;
2417 pDesc->status.fDD = true;
2418
2419 /*
2420 * We need to leave Rx critical section here or we risk deadlocking
2421 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2422 * page or has an access handler associated with it.
2423 * Note that it is safe to leave the critical section here since
2424 * e1kRegWriteRDT() never modifies RDH. It never touches already
2425 * fetched RxD cache entries either.
2426 */
2427 if (cb > pThis->u16RxBSize)
2428 {
2429 pDesc->status.fEOP = false;
2430 e1kCsRxLeave(pThis);
2431 e1kStoreRxFragment(pThis, pDesc, ptr, pThis->u16RxBSize);
2432 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2433 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2434 return rc;
2435 ptr += pThis->u16RxBSize;
2436 cb -= pThis->u16RxBSize;
2437 }
2438 else
2439 {
2440 pDesc->status.fEOP = true;
2441 e1kCsRxLeave(pThis);
2442 e1kStoreRxFragment(pThis, pDesc, ptr, cb);
2443#ifdef E1K_WITH_RXD_CACHE
2444 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2445 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2446 return rc;
2447 cb = 0;
2448#else /* !E1K_WITH_RXD_CACHE */
2449 pThis->led.Actual.s.fReading = 0;
2450 return VINF_SUCCESS;
2451#endif /* !E1K_WITH_RXD_CACHE */
2452 }
2453 /*
2454 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2455 * is not defined.
2456 */
2457 }
2458#ifdef E1K_WITH_RXD_CACHE
2459 /* Write back the descriptor. */
2460 pDesc->status.fDD = true;
2461 e1kRxDPut(pThis, pDesc);
2462#else /* !E1K_WITH_RXD_CACHE */
2463 else
2464 {
2465 /* Write back the descriptor. */
2466 pDesc->status.fDD = true;
2467 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2468 e1kDescAddr(RDBAH, RDBAL, RDH),
2469 pDesc, sizeof(E1KRXDESC));
2470 e1kAdvanceRDH(pThis);
2471 }
2472#endif /* !E1K_WITH_RXD_CACHE */
2473 }
2474
2475 if (cb > 0)
2476 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2477
2478 pThis->led.Actual.s.fReading = 0;
2479
2480 e1kCsRxLeave(pThis);
2481#ifdef E1K_WITH_RXD_CACHE
2482 /* Complete packet has been stored -- it is time to let the guest know. */
2483# ifdef E1K_USE_RX_TIMERS
2484 if (RDTR)
2485 {
2486 /* Arm the timer to fire in RDTR usec (discard .024) */
2487 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2488 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2489 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2490 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2491 }
2492 else
2493 {
2494# endif /* E1K_USE_RX_TIMERS */
2495 /* 0 delay means immediate interrupt */
2496 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2497 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2498# ifdef E1K_USE_RX_TIMERS
2499 }
2500# endif /* E1K_USE_RX_TIMERS */
2501#endif /* E1K_WITH_RXD_CACHE */
2502
2503 return VINF_SUCCESS;
2504#else
2505 return VERR_INTERNAL_ERROR_2;
2506#endif
2507}
2508
2509
2510/**
2511 * Bring the link up after the configured delay, 5 seconds by default.
2512 *
2513 * @param pThis The device state structure.
2514 * @thread any
2515 */
2516DECLINLINE(void) e1kBringLinkUpDelayed(PE1KSTATE pThis)
2517{
2518 E1kLog(("%s Will bring up the link in %d seconds...\n",
2519 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2520 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
2521}
2522
2523#ifdef IN_RING3
2524/**
2525 * Bring up the link immediately.
2526 *
2527 * @param pThis The device state structure.
2528 */
2529DECLINLINE(void) e1kR3LinkUp(PE1KSTATE pThis)
2530{
2531 E1kLog(("%s Link is up\n", pThis->szPrf));
2532 STATUS |= STATUS_LU;
2533 Phy::setLinkStatus(&pThis->phy, true);
2534 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2535 if (pThis->pDrvR3)
2536 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_UP);
2537}
2538
2539/**
2540 * Bring down the link immediately.
2541 *
2542 * @param pThis The device state structure.
2543 */
2544DECLINLINE(void) e1kR3LinkDown(PE1KSTATE pThis)
2545{
2546 E1kLog(("%s Link is down\n", pThis->szPrf));
2547 STATUS &= ~STATUS_LU;
2548 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2549 if (pThis->pDrvR3)
2550 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2551}
2552
2553/**
2554 * Bring down the link temporarily.
2555 *
2556 * @param pThis The device state structure.
2557 */
2558DECLINLINE(void) e1kR3LinkDownTemp(PE1KSTATE pThis)
2559{
2560 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2561 STATUS &= ~STATUS_LU;
2562 Phy::setLinkStatus(&pThis->phy, false);
2563 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2564 /*
2565 * Notifying the associated driver that the link went down (even temporarily)
2566 * seems to be the right thing, but it was not done before. This may cause
2567 * a regression if the driver does not expect the link to go down as a result
2568 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2569 * of code notified the driver that the link was up! See @bugref{7057}.
2570 */
2571 if (pThis->pDrvR3)
2572 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2573 e1kBringLinkUpDelayed(pThis);
2574}
2575#endif /* IN_RING3 */
2576
2577#if 0 /* unused */
2578/**
2579 * Read handler for Device Status register.
2580 *
2581 * Get the link status from PHY.
2582 *
2583 * @returns VBox status code.
2584 *
2585 * @param pThis The device state structure.
2586 * @param offset Register offset in memory-mapped frame.
2587 * @param index Register index in register array.
2588 * @param mask Used to implement partial reads (8 and 16-bit).
2589 */
2590static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2591{
2592 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2593 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2594 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2595 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2596 {
2597 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2598 if (Phy::readMDIO(&pThis->phy))
2599 *pu32Value = CTRL | CTRL_MDIO;
2600 else
2601 *pu32Value = CTRL & ~CTRL_MDIO;
2602 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2603 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2604 }
2605 else
2606 {
2607 /* MDIO pin is used for output, ignore it */
2608 *pu32Value = CTRL;
2609 }
2610 return VINF_SUCCESS;
2611}
2612#endif /* unused */
2613
2614/**
2615 * Write handler for Device Control register.
2616 *
2617 * Handles reset.
2618 *
2619 * @param pThis The device state structure.
2620 * @param offset Register offset in memory-mapped frame.
2621 * @param index Register index in register array.
2622 * @param value The value to store.
2623 * @param mask Used to implement partial writes (8 and 16-bit).
2624 * @thread EMT
2625 */
2626static int e1kRegWriteCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2627{
2628 int rc = VINF_SUCCESS;
2629
2630 if (value & CTRL_RESET)
2631 { /* RST */
2632#ifndef IN_RING3
2633 return VINF_IOM_R3_MMIO_WRITE;
2634#else
2635 e1kHardReset(pThis);
2636#endif
2637 }
2638 else
2639 {
2640 if ( (value & CTRL_SLU)
2641 && pThis->fCableConnected
2642 && !(STATUS & STATUS_LU))
2643 {
2644 /* The driver indicates that we should bring up the link */
2645 /* Do so in 5 seconds (by default). */
2646 e1kBringLinkUpDelayed(pThis);
2647 /*
2648 * Change the status (but not PHY status) anyway as Windows expects
2649 * it for 82543GC.
2650 */
2651 STATUS |= STATUS_LU;
2652 }
2653 if (value & CTRL_VME)
2654 {
2655 E1kLog(("%s VLAN Mode Enabled\n", pThis->szPrf));
2656 }
2657 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2658 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2659 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2660 if (value & CTRL_MDC)
2661 {
2662 if (value & CTRL_MDIO_DIR)
2663 {
2664 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2665 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2666 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO));
2667 }
2668 else
2669 {
2670 if (Phy::readMDIO(&pThis->phy))
2671 value |= CTRL_MDIO;
2672 else
2673 value &= ~CTRL_MDIO;
2674 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2675 pThis->szPrf, !!(value & CTRL_MDIO)));
2676 }
2677 }
2678 rc = e1kRegWriteDefault(pThis, offset, index, value);
2679 }
2680
2681 return rc;
2682}
2683
2684/**
2685 * Write handler for EEPROM/Flash Control/Data register.
2686 *
2687 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2688 *
2689 * @param pThis The device state structure.
2690 * @param offset Register offset in memory-mapped frame.
2691 * @param index Register index in register array.
2692 * @param value The value to store.
2693 * @param mask Used to implement partial writes (8 and 16-bit).
2694 * @thread EMT
2695 */
2696static int e1kRegWriteEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2697{
2698#ifdef IN_RING3
2699 /* So far we are concerned with lower byte only */
2700 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2701 {
2702 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2703 /* Note: 82543GC does not need to request EEPROM access */
2704 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2705 pThis->eeprom.write(value & EECD_EE_WIRES);
2706 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2707 }
2708 if (value & EECD_EE_REQ)
2709 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2710 else
2711 EECD &= ~EECD_EE_GNT;
2712 //e1kRegWriteDefault(pThis, offset, index, value );
2713
2714 return VINF_SUCCESS;
2715#else /* !IN_RING3 */
2716 return VINF_IOM_R3_MMIO_WRITE;
2717#endif /* !IN_RING3 */
2718}
2719
2720/**
2721 * Read handler for EEPROM/Flash Control/Data register.
2722 *
2723 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2724 *
2725 * @returns VBox status code.
2726 *
2727 * @param pThis The device state structure.
2728 * @param offset Register offset in memory-mapped frame.
2729 * @param index Register index in register array.
2730 * @param mask Used to implement partial reads (8 and 16-bit).
2731 * @thread EMT
2732 */
2733static int e1kRegReadEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2734{
2735#ifdef IN_RING3
2736 uint32_t value;
2737 int rc = e1kRegReadDefault(pThis, offset, index, &value);
2738 if (RT_SUCCESS(rc))
2739 {
2740 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2741 {
2742 /* Note: 82543GC does not need to request EEPROM access */
2743 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2744 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2745 value |= pThis->eeprom.read();
2746 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2747 }
2748 *pu32Value = value;
2749 }
2750
2751 return rc;
2752#else /* !IN_RING3 */
2753 return VINF_IOM_R3_MMIO_READ;
2754#endif /* !IN_RING3 */
2755}
2756
2757/**
2758 * Write handler for EEPROM Read register.
2759 *
2760 * Handles EEPROM word access requests, reads EEPROM and stores the result
2761 * into DATA field.
2762 *
2763 * @param pThis The device state structure.
2764 * @param offset Register offset in memory-mapped frame.
2765 * @param index Register index in register array.
2766 * @param value The value to store.
2767 * @param mask Used to implement partial writes (8 and 16-bit).
2768 * @thread EMT
2769 */
2770static int e1kRegWriteEERD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2771{
2772#ifdef IN_RING3
2773 /* Make use of 'writable' and 'readable' masks. */
2774 e1kRegWriteDefault(pThis, offset, index, value);
2775 /* DONE and DATA are set only if read was triggered by START. */
2776 if (value & EERD_START)
2777 {
2778 uint16_t tmp;
2779 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2780 if (pThis->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2781 SET_BITS(EERD, DATA, tmp);
2782 EERD |= EERD_DONE;
2783 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2784 }
2785
2786 return VINF_SUCCESS;
2787#else /* !IN_RING3 */
2788 return VINF_IOM_R3_MMIO_WRITE;
2789#endif /* !IN_RING3 */
2790}
2791
2792
2793/**
2794 * Write handler for MDI Control register.
2795 *
2796 * Handles PHY read/write requests; forwards requests to internal PHY device.
2797 *
2798 * @param pThis The device state structure.
2799 * @param offset Register offset in memory-mapped frame.
2800 * @param index Register index in register array.
2801 * @param value The value to store.
2802 * @param mask Used to implement partial writes (8 and 16-bit).
2803 * @thread EMT
2804 */
2805static int e1kRegWriteMDIC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2806{
2807 if (value & MDIC_INT_EN)
2808 {
2809 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2810 pThis->szPrf));
2811 }
2812 else if (value & MDIC_READY)
2813 {
2814 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2815 pThis->szPrf));
2816 }
2817 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2818 {
2819 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
2820 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
2821 /*
2822 * Some drivers scan the MDIO bus for a PHY. We can work with these
2823 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
2824 * at the requested address, see @bugref{7346}.
2825 */
2826 MDIC = MDIC_READY | MDIC_ERROR;
2827 }
2828 else
2829 {
2830 /* Store the value */
2831 e1kRegWriteDefault(pThis, offset, index, value);
2832 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
2833 /* Forward op to PHY */
2834 if (value & MDIC_OP_READ)
2835 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG)));
2836 else
2837 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2838 /* Let software know that we are done */
2839 MDIC |= MDIC_READY;
2840 }
2841
2842 return VINF_SUCCESS;
2843}
2844
2845/**
2846 * Write handler for Interrupt Cause Read register.
2847 *
2848 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2849 *
2850 * @param pThis The device state structure.
2851 * @param offset Register offset in memory-mapped frame.
2852 * @param index Register index in register array.
2853 * @param value The value to store.
2854 * @param mask Used to implement partial writes (8 and 16-bit).
2855 * @thread EMT
2856 */
2857static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2858{
2859 ICR &= ~value;
2860
2861 return VINF_SUCCESS;
2862}
2863
2864/**
2865 * Read handler for Interrupt Cause Read register.
2866 *
2867 * Reading this register acknowledges all interrupts.
2868 *
2869 * @returns VBox status code.
2870 *
2871 * @param pThis The device state structure.
2872 * @param offset Register offset in memory-mapped frame.
2873 * @param index Register index in register array.
2874 * @param mask Not used.
2875 * @thread EMT
2876 */
2877static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2878{
2879 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
2880 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2881 return rc;
2882
2883 uint32_t value = 0;
2884 rc = e1kRegReadDefault(pThis, offset, index, &value);
2885 if (RT_SUCCESS(rc))
2886 {
2887 if (value)
2888 {
2889 /*
2890 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2891 * with disabled interrupts.
2892 */
2893 //if (IMS)
2894 if (1)
2895 {
2896 /*
2897 * Interrupts were enabled -- we are supposedly at the very
2898 * beginning of interrupt handler
2899 */
2900 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2901 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
2902 /* Clear all pending interrupts */
2903 ICR = 0;
2904 pThis->fIntRaised = false;
2905 /* Lower(0) INTA(0) */
2906 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
2907
2908 pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
2909 if (pThis->fIntMaskUsed)
2910 pThis->fDelayInts = true;
2911 }
2912 else
2913 {
2914 /*
2915 * Interrupts are disabled -- in windows guests ICR read is done
2916 * just before re-enabling interrupts
2917 */
2918 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
2919 }
2920 }
2921 *pu32Value = value;
2922 }
2923 e1kCsLeave(pThis);
2924
2925 return rc;
2926}
2927
2928/**
2929 * Write handler for Interrupt Cause Set register.
2930 *
2931 * Bits corresponding to 1s in 'value' will be set in ICR register.
2932 *
2933 * @param pThis The device state structure.
2934 * @param offset Register offset in memory-mapped frame.
2935 * @param index Register index in register array.
2936 * @param value The value to store.
2937 * @param mask Used to implement partial writes (8 and 16-bit).
2938 * @thread EMT
2939 */
2940static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2941{
2942 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
2943 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
2944}
2945
2946/**
2947 * Write handler for Interrupt Mask Set register.
2948 *
2949 * Will trigger pending interrupts.
2950 *
2951 * @param pThis The device state structure.
2952 * @param offset Register offset in memory-mapped frame.
2953 * @param index Register index in register array.
2954 * @param value The value to store.
2955 * @param mask Used to implement partial writes (8 and 16-bit).
2956 * @thread EMT
2957 */
2958static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2959{
2960 IMS |= value;
2961 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2962 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
2963 /* Mask changes, we need to raise pending interrupts. */
2964 if ((ICR & IMS) && !pThis->fLocked)
2965 {
2966 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2967 pThis->szPrf, ICR));
2968 /* Raising an interrupt immediately causes win7 to hang upon NIC reconfiguration, see @bugref{5023}. */
2969 TMTimerSet(pThis->CTX_SUFF(pIntTimer), TMTimerFromNano(pThis->CTX_SUFF(pIntTimer), ITR * 256) +
2970 TMTimerGet(pThis->CTX_SUFF(pIntTimer)));
2971 }
2972
2973 return VINF_SUCCESS;
2974}
2975
2976/**
2977 * Write handler for Interrupt Mask Clear register.
2978 *
2979 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2980 *
2981 * @param pThis The device state structure.
2982 * @param offset Register offset in memory-mapped frame.
2983 * @param index Register index in register array.
2984 * @param value The value to store.
2985 * @param mask Used to implement partial writes (8 and 16-bit).
2986 * @thread EMT
2987 */
2988static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2989{
2990 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
2991 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2992 return rc;
2993 if (pThis->fIntRaised)
2994 {
2995 /*
2996 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2997 * Windows to freeze since it may receive an interrupt while still in the very beginning
2998 * of interrupt handler.
2999 */
3000 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3001 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3002 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3003 /* Lower(0) INTA(0) */
3004 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
3005 pThis->fIntRaised = false;
3006 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3007 }
3008 IMS &= ~value;
3009 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3010 e1kCsLeave(pThis);
3011
3012 return VINF_SUCCESS;
3013}
3014
3015/**
3016 * Write handler for Receive Control register.
3017 *
3018 * @param pThis The device state structure.
3019 * @param offset Register offset in memory-mapped frame.
3020 * @param index Register index in register array.
3021 * @param value The value to store.
3022 * @param mask Used to implement partial writes (8 and 16-bit).
3023 * @thread EMT
3024 */
3025static int e1kRegWriteRCTL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3026{
3027 /* Update promiscuous mode */
3028 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3029 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3030 {
3031 /* Promiscuity has changed, pass the knowledge on. */
3032#ifndef IN_RING3
3033 return VINF_IOM_R3_MMIO_WRITE;
3034#else
3035 if (pThis->pDrvR3)
3036 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, fBecomePromiscous);
3037#endif
3038 }
3039
3040 /* Adjust receive buffer size */
3041 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3042 if (value & RCTL_BSEX)
3043 cbRxBuf *= 16;
3044 if (cbRxBuf != pThis->u16RxBSize)
3045 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3046 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3047 pThis->u16RxBSize = cbRxBuf;
3048
3049 /* Update the register */
3050 e1kRegWriteDefault(pThis, offset, index, value);
3051
3052 return VINF_SUCCESS;
3053}
3054
3055/**
3056 * Write handler for Packet Buffer Allocation register.
3057 *
3058 * TXA = 64 - RXA.
3059 *
3060 * @param pThis The device state structure.
3061 * @param offset Register offset in memory-mapped frame.
3062 * @param index Register index in register array.
3063 * @param value The value to store.
3064 * @param mask Used to implement partial writes (8 and 16-bit).
3065 * @thread EMT
3066 */
3067static int e1kRegWritePBA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3068{
3069 e1kRegWriteDefault(pThis, offset, index, value);
3070 PBA_st->txa = 64 - PBA_st->rxa;
3071
3072 return VINF_SUCCESS;
3073}
3074
3075/**
3076 * Write handler for Receive Descriptor Tail register.
3077 *
3078 * @remarks Write into RDT forces switch to HC and signal to
3079 * e1kR3NetworkDown_WaitReceiveAvail().
3080 *
3081 * @returns VBox status code.
3082 *
3083 * @param pThis The device state structure.
3084 * @param offset Register offset in memory-mapped frame.
3085 * @param index Register index in register array.
3086 * @param value The value to store.
3087 * @param mask Used to implement partial writes (8 and 16-bit).
3088 * @thread EMT
3089 */
3090static int e1kRegWriteRDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3091{
3092#ifndef IN_RING3
3093 /* XXX */
3094// return VINF_IOM_R3_MMIO_WRITE;
3095#endif
3096 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3097 if (RT_LIKELY(rc == VINF_SUCCESS))
3098 {
3099 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3100 /*
3101 * Some drivers advance RDT too far, so that it equals RDH. This
3102 * somehow manages to work with real hardware but not with this
3103 * emulated device. We can work with these drivers if we just
3104 * write 1 less when we see a driver writing RDT equal to RDH,
3105 * see @bugref{7346}.
3106 */
3107 if (value == RDH)
3108 {
3109 if (RDH == 0)
3110 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3111 else
3112 value = RDH - 1;
3113 }
3114 rc = e1kRegWriteDefault(pThis, offset, index, value);
3115#ifdef E1K_WITH_RXD_CACHE
3116 /*
3117 * We need to fetch descriptors now as RDT may go whole circle
3118 * before we attempt to store a received packet. For example,
3119 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3120 * size being only 8 descriptors! Note that we fetch descriptors
3121 * only when the cache is empty to reduce the number of memory reads
3122 * in case of frequent RDT writes. Don't fetch anything when the
3123 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3124 * messed up state.
3125 * Note that despite the cache may seem empty, meaning that there are
3126 * no more available descriptors in it, it may still be used by RX
3127 * thread which has not yet written the last descriptor back but has
3128 * temporarily released the RX lock in order to write the packet body
3129 * to descriptor's buffer. At this point we still going to do prefetch
3130 * but it won't actually fetch anything if there are no unused slots in
3131 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3132 * reset the cache here even if it appears empty. It will be reset at
3133 * a later point in e1kRxDGet().
3134 */
3135 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3136 e1kRxDPrefetch(pThis);
3137#endif /* E1K_WITH_RXD_CACHE */
3138 e1kCsRxLeave(pThis);
3139 if (RT_SUCCESS(rc))
3140 {
3141/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
3142 * without requiring any context switches. We should also check the
3143 * wait condition before bothering to queue the item as we're currently
3144 * queuing thousands of items per second here in a normal transmit
3145 * scenario. Expect performance changes when fixing this! */
3146#ifdef IN_RING3
3147 /* Signal that we have more receive descriptors available. */
3148 e1kWakeupReceive(pThis->CTX_SUFF(pDevIns));
3149#else
3150 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
3151 if (pItem)
3152 PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
3153#endif
3154 }
3155 }
3156 return rc;
3157}
3158
3159/**
3160 * Write handler for Receive Delay Timer register.
3161 *
3162 * @param pThis The device state structure.
3163 * @param offset Register offset in memory-mapped frame.
3164 * @param index Register index in register array.
3165 * @param value The value to store.
3166 * @param mask Used to implement partial writes (8 and 16-bit).
3167 * @thread EMT
3168 */
3169static int e1kRegWriteRDTR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3170{
3171 e1kRegWriteDefault(pThis, offset, index, value);
3172 if (value & RDTR_FPD)
3173 {
3174 /* Flush requested, cancel both timers and raise interrupt */
3175#ifdef E1K_USE_RX_TIMERS
3176 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3177 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3178#endif
3179 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3180 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3181 }
3182
3183 return VINF_SUCCESS;
3184}
3185
3186DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3187{
3188 /**
3189 * Make sure TDT won't change during computation. EMT may modify TDT at
3190 * any moment.
3191 */
3192 uint32_t tdt = TDT;
3193 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3194}
3195
3196#ifdef IN_RING3
3197#ifdef E1K_TX_DELAY
3198
3199/**
3200 * Transmit Delay Timer handler.
3201 *
3202 * @remarks We only get here when the timer expires.
3203 *
3204 * @param pDevIns Pointer to device instance structure.
3205 * @param pTimer Pointer to the timer.
3206 * @param pvUser NULL.
3207 * @thread EMT
3208 */
3209static DECLCALLBACK(void) e1kTxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3210{
3211 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3212 Assert(PDMCritSectIsOwner(&pThis->csTx));
3213
3214 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3215#ifdef E1K_INT_STATS
3216 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3217 if (u64Elapsed > pThis->uStatMaxTxDelay)
3218 pThis->uStatMaxTxDelay = u64Elapsed;
3219#endif
3220 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
3221 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3222}
3223#endif /* E1K_TX_DELAY */
3224
3225#ifdef E1K_USE_TX_TIMERS
3226
3227/**
3228 * Transmit Interrupt Delay Timer handler.
3229 *
3230 * @remarks We only get here when the timer expires.
3231 *
3232 * @param pDevIns Pointer to device instance structure.
3233 * @param pTimer Pointer to the timer.
3234 * @param pvUser NULL.
3235 * @thread EMT
3236 */
3237static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3238{
3239 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3240
3241 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3242 /* Cancel absolute delay timer as we have already got attention */
3243#ifndef E1K_NO_TAD
3244 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
3245#endif /* E1K_NO_TAD */
3246 e1kRaiseInterrupt(pThis, ICR_TXDW);
3247}
3248
3249/**
3250 * Transmit Absolute Delay Timer handler.
3251 *
3252 * @remarks We only get here when the timer expires.
3253 *
3254 * @param pDevIns Pointer to device instance structure.
3255 * @param pTimer Pointer to the timer.
3256 * @param pvUser NULL.
3257 * @thread EMT
3258 */
3259static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3260{
3261 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3262
3263 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3264 /* Cancel interrupt delay timer as we have already got attention */
3265 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
3266 e1kRaiseInterrupt(pThis, ICR_TXDW);
3267}
3268
3269#endif /* E1K_USE_TX_TIMERS */
3270#ifdef E1K_USE_RX_TIMERS
3271
3272/**
3273 * Receive Interrupt Delay Timer handler.
3274 *
3275 * @remarks We only get here when the timer expires.
3276 *
3277 * @param pDevIns Pointer to device instance structure.
3278 * @param pTimer Pointer to the timer.
3279 * @param pvUser NULL.
3280 * @thread EMT
3281 */
3282static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3283{
3284 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3285
3286 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3287 /* Cancel absolute delay timer as we have already got attention */
3288 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3289 e1kRaiseInterrupt(pThis, ICR_RXT0);
3290}
3291
3292/**
3293 * Receive Absolute Delay Timer handler.
3294 *
3295 * @remarks We only get here when the timer expires.
3296 *
3297 * @param pDevIns Pointer to device instance structure.
3298 * @param pTimer Pointer to the timer.
3299 * @param pvUser NULL.
3300 * @thread EMT
3301 */
3302static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3303{
3304 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3305
3306 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3307 /* Cancel interrupt delay timer as we have already got attention */
3308 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3309 e1kRaiseInterrupt(pThis, ICR_RXT0);
3310}
3311
3312#endif /* E1K_USE_RX_TIMERS */
3313
3314/**
3315 * Late Interrupt Timer handler.
3316 *
3317 * @param pDevIns Pointer to device instance structure.
3318 * @param pTimer Pointer to the timer.
3319 * @param pvUser NULL.
3320 * @thread EMT
3321 */
3322static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3323{
3324 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3325
3326 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3327 STAM_COUNTER_INC(&pThis->StatLateInts);
3328 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3329#if 0
3330 if (pThis->iStatIntLost > -100)
3331 pThis->iStatIntLost--;
3332#endif
3333 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, 0);
3334 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3335}
3336
3337/**
3338 * Link Up Timer handler.
3339 *
3340 * @param pDevIns Pointer to device instance structure.
3341 * @param pTimer Pointer to the timer.
3342 * @param pvUser NULL.
3343 * @thread EMT
3344 */
3345static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3346{
3347 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3348
3349 /*
3350 * This can happen if we set the link status to down when the Link up timer was
3351 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3352 * and connect+disconnect the cable very quick.
3353 */
3354 if (!pThis->fCableConnected)
3355 return;
3356
3357 e1kR3LinkUp(pThis);
3358}
3359
3360#endif /* IN_RING3 */
3361
3362/**
3363 * Sets up the GSO context according to the TSE new context descriptor.
3364 *
3365 * @param pGso The GSO context to setup.
3366 * @param pCtx The context descriptor.
3367 */
3368DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3369{
3370 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3371
3372 /*
3373 * See if the context descriptor describes something that could be TCP or
3374 * UDP over IPv[46].
3375 */
3376 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3377 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3378 {
3379 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3380 return;
3381 }
3382 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3383 {
3384 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3385 return;
3386 }
3387 if (RT_UNLIKELY( pCtx->dw2.fTCP
3388 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3389 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3390 {
3391 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3392 return;
3393 }
3394
3395 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3396 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3397 {
3398 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3399 return;
3400 }
3401
3402 /* IPv4 checksum offset. */
3403 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3404 {
3405 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3406 return;
3407 }
3408
3409 /* TCP/UDP checksum offsets. */
3410 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3411 != ( pCtx->dw2.fTCP
3412 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3413 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3414 {
3415 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3416 return;
3417 }
3418
3419 /*
3420 * Because of internal networking using a 16-bit size field for GSO context
3421 * plus frame, we have to make sure we don't exceed this.
3422 */
3423 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3424 {
3425 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3426 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3427 return;
3428 }
3429
3430 /*
3431 * We're good for now - we'll do more checks when seeing the data.
3432 * So, figure the type of offloading and setup the context.
3433 */
3434 if (pCtx->dw2.fIP)
3435 {
3436 if (pCtx->dw2.fTCP)
3437 {
3438 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3439 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3440 }
3441 else
3442 {
3443 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3444 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3445 }
3446 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3447 * this yet it seems)... */
3448 }
3449 else
3450 {
3451 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /* @todo IPv6 UFO */
3452 if (pCtx->dw2.fTCP)
3453 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3454 else
3455 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3456 }
3457 pGso->offHdr1 = pCtx->ip.u8CSS;
3458 pGso->offHdr2 = pCtx->tu.u8CSS;
3459 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3460 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3461 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3462 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3463 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3464}
3465
3466/**
3467 * Checks if we can use GSO processing for the current TSE frame.
3468 *
3469 * @param pThis The device state structure.
3470 * @param pGso The GSO context.
3471 * @param pData The first data descriptor of the frame.
3472 * @param pCtx The TSO context descriptor.
3473 */
3474DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3475{
3476 if (!pData->cmd.fTSE)
3477 {
3478 E1kLog2(("e1kCanDoGso: !TSE\n"));
3479 return false;
3480 }
3481 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3482 {
3483 E1kLog(("e1kCanDoGso: VLE\n"));
3484 return false;
3485 }
3486 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3487 {
3488 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3489 return false;
3490 }
3491
3492 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3493 {
3494 case PDMNETWORKGSOTYPE_IPV4_TCP:
3495 case PDMNETWORKGSOTYPE_IPV4_UDP:
3496 if (!pData->dw3.fIXSM)
3497 {
3498 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3499 return false;
3500 }
3501 if (!pData->dw3.fTXSM)
3502 {
3503 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3504 return false;
3505 }
3506 /** @todo what more check should we perform here? Ethernet frame type? */
3507 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3508 return true;
3509
3510 case PDMNETWORKGSOTYPE_IPV6_TCP:
3511 case PDMNETWORKGSOTYPE_IPV6_UDP:
3512 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3513 {
3514 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3515 return false;
3516 }
3517 if (!pData->dw3.fTXSM)
3518 {
3519 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3520 return false;
3521 }
3522 /** @todo what more check should we perform here? Ethernet frame type? */
3523 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3524 return true;
3525
3526 default:
3527 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3528 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3529 return false;
3530 }
3531}
3532
3533/**
3534 * Frees the current xmit buffer.
3535 *
3536 * @param pThis The device state structure.
3537 */
3538static void e1kXmitFreeBuf(PE1KSTATE pThis)
3539{
3540 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3541 if (pSg)
3542 {
3543 pThis->CTX_SUFF(pTxSg) = NULL;
3544
3545 if (pSg->pvAllocator != pThis)
3546 {
3547 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3548 if (pDrv)
3549 pDrv->pfnFreeBuf(pDrv, pSg);
3550 }
3551 else
3552 {
3553 /* loopback */
3554 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3555 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3556 pSg->fFlags = 0;
3557 pSg->pvAllocator = NULL;
3558 }
3559 }
3560}
3561
3562#ifndef E1K_WITH_TXD_CACHE
3563/**
3564 * Allocates an xmit buffer.
3565 *
3566 * @returns See PDMINETWORKUP::pfnAllocBuf.
3567 * @param pThis The device state structure.
3568 * @param cbMin The minimum frame size.
3569 * @param fExactSize Whether cbMin is exact or if we have to max it
3570 * out to the max MTU size.
3571 * @param fGso Whether this is a GSO frame or not.
3572 */
3573DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, size_t cbMin, bool fExactSize, bool fGso)
3574{
3575 /* Adjust cbMin if necessary. */
3576 if (!fExactSize)
3577 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3578
3579 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3580 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3581 e1kXmitFreeBuf(pThis);
3582 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3583
3584 /*
3585 * Allocate the buffer.
3586 */
3587 PPDMSCATTERGATHER pSg;
3588 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3589 {
3590 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3591 if (RT_UNLIKELY(!pDrv))
3592 return VERR_NET_DOWN;
3593 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3594 if (RT_FAILURE(rc))
3595 {
3596 /* Suspend TX as we are out of buffers atm */
3597 STATUS |= STATUS_TXOFF;
3598 return rc;
3599 }
3600 }
3601 else
3602 {
3603 /* Create a loopback using the fallback buffer and preallocated SG. */
3604 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3605 pSg = &pThis->uTxFallback.Sg;
3606 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3607 pSg->cbUsed = 0;
3608 pSg->cbAvailable = 0;
3609 pSg->pvAllocator = pThis;
3610 pSg->pvUser = NULL; /* No GSO here. */
3611 pSg->cSegs = 1;
3612 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3613 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3614 }
3615
3616 pThis->CTX_SUFF(pTxSg) = pSg;
3617 return VINF_SUCCESS;
3618}
3619#else /* E1K_WITH_TXD_CACHE */
3620/**
3621 * Allocates an xmit buffer.
3622 *
3623 * @returns See PDMINETWORKUP::pfnAllocBuf.
3624 * @param pThis The device state structure.
3625 * @param cbMin The minimum frame size.
3626 * @param fExactSize Whether cbMin is exact or if we have to max it
3627 * out to the max MTU size.
3628 * @param fGso Whether this is a GSO frame or not.
3629 */
3630DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, bool fGso)
3631{
3632 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3633 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3634 e1kXmitFreeBuf(pThis);
3635 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3636
3637 /*
3638 * Allocate the buffer.
3639 */
3640 PPDMSCATTERGATHER pSg;
3641 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3642 {
3643 if (pThis->cbTxAlloc == 0)
3644 {
3645 /* Zero packet, no need for the buffer */
3646 return VINF_SUCCESS;
3647 }
3648
3649 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3650 if (RT_UNLIKELY(!pDrv))
3651 return VERR_NET_DOWN;
3652 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3653 if (RT_FAILURE(rc))
3654 {
3655 /* Suspend TX as we are out of buffers atm */
3656 STATUS |= STATUS_TXOFF;
3657 return rc;
3658 }
3659 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3660 pThis->szPrf, pThis->cbTxAlloc,
3661 pThis->fVTag ? "VLAN " : "",
3662 pThis->fGSO ? "GSO " : ""));
3663 pThis->cbTxAlloc = 0;
3664 }
3665 else
3666 {
3667 /* Create a loopback using the fallback buffer and preallocated SG. */
3668 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3669 pSg = &pThis->uTxFallback.Sg;
3670 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3671 pSg->cbUsed = 0;
3672 pSg->cbAvailable = 0;
3673 pSg->pvAllocator = pThis;
3674 pSg->pvUser = NULL; /* No GSO here. */
3675 pSg->cSegs = 1;
3676 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3677 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3678 }
3679
3680 pThis->CTX_SUFF(pTxSg) = pSg;
3681 return VINF_SUCCESS;
3682}
3683#endif /* E1K_WITH_TXD_CACHE */
3684
3685/**
3686 * Checks if it's a GSO buffer or not.
3687 *
3688 * @returns true / false.
3689 * @param pTxSg The scatter / gather buffer.
3690 */
3691DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3692{
3693#if 0
3694 if (!pTxSg)
3695 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3696 if (pTxSg && pTxSg->pvUser)
3697 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3698#endif
3699 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3700}
3701
3702#ifndef E1K_WITH_TXD_CACHE
3703/**
3704 * Load transmit descriptor from guest memory.
3705 *
3706 * @param pThis The device state structure.
3707 * @param pDesc Pointer to descriptor union.
3708 * @param addr Physical address in guest context.
3709 * @thread E1000_TX
3710 */
3711DECLINLINE(void) e1kLoadDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
3712{
3713 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3714}
3715#else /* E1K_WITH_TXD_CACHE */
3716/**
3717 * Load transmit descriptors from guest memory.
3718 *
3719 * We need two physical reads in case the tail wrapped around the end of TX
3720 * descriptor ring.
3721 *
3722 * @returns the actual number of descriptors fetched.
3723 * @param pThis The device state structure.
3724 * @param pDesc Pointer to descriptor union.
3725 * @param addr Physical address in guest context.
3726 * @thread E1000_TX
3727 */
3728DECLINLINE(unsigned) e1kTxDLoadMore(PE1KSTATE pThis)
3729{
3730 Assert(pThis->iTxDCurrent == 0);
3731 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3732 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3733 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3734 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3735 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3736 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3737 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u "
3738 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3739 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3740 nFirstNotLoaded, nDescsInSingleRead));
3741 if (nDescsToFetch == 0)
3742 return 0;
3743 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3744 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3745 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3746 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3747 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3748 pThis->szPrf, nDescsInSingleRead,
3749 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3750 nFirstNotLoaded, TDLEN, TDH, TDT));
3751 if (nDescsToFetch > nDescsInSingleRead)
3752 {
3753 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3754 ((uint64_t)TDBAH << 32) + TDBAL,
3755 pFirstEmptyDesc + nDescsInSingleRead,
3756 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3757 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3758 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3759 TDBAH, TDBAL));
3760 }
3761 pThis->nTxDFetched += nDescsToFetch;
3762 return nDescsToFetch;
3763}
3764
3765/**
3766 * Load transmit descriptors from guest memory only if there are no loaded
3767 * descriptors.
3768 *
3769 * @returns true if there are descriptors in cache.
3770 * @param pThis The device state structure.
3771 * @param pDesc Pointer to descriptor union.
3772 * @param addr Physical address in guest context.
3773 * @thread E1000_TX
3774 */
3775DECLINLINE(bool) e1kTxDLazyLoad(PE1KSTATE pThis)
3776{
3777 if (pThis->nTxDFetched == 0)
3778 return e1kTxDLoadMore(pThis) != 0;
3779 return true;
3780}
3781#endif /* E1K_WITH_TXD_CACHE */
3782
3783/**
3784 * Write back transmit descriptor to guest memory.
3785 *
3786 * @param pThis The device state structure.
3787 * @param pDesc Pointer to descriptor union.
3788 * @param addr Physical address in guest context.
3789 * @thread E1000_TX
3790 */
3791DECLINLINE(void) e1kWriteBackDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
3792{
3793 /* Only the last half of the descriptor has to be written back. */
3794 e1kPrintTDesc(pThis, pDesc, "^^^");
3795 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3796}
3797
3798/**
3799 * Transmit complete frame.
3800 *
3801 * @remarks We skip the FCS since we're not responsible for sending anything to
3802 * a real ethernet wire.
3803 *
3804 * @param pThis The device state structure.
3805 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3806 * @thread E1000_TX
3807 */
3808static void e1kTransmitFrame(PE1KSTATE pThis, bool fOnWorkerThread)
3809{
3810 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3811 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
3812 Assert(!pSg || pSg->cSegs == 1);
3813
3814 if (cbFrame > 70) /* unqualified guess */
3815 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
3816
3817#ifdef E1K_INT_STATS
3818 if (cbFrame <= 1514)
3819 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
3820 else if (cbFrame <= 2962)
3821 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
3822 else if (cbFrame <= 4410)
3823 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
3824 else if (cbFrame <= 5858)
3825 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
3826 else if (cbFrame <= 7306)
3827 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
3828 else if (cbFrame <= 8754)
3829 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
3830 else if (cbFrame <= 16384)
3831 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
3832 else if (cbFrame <= 32768)
3833 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
3834 else
3835 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
3836#endif /* E1K_INT_STATS */
3837
3838 /* Add VLAN tag */
3839 if (cbFrame > 12 && pThis->fVTag)
3840 {
3841 E1kLog3(("%s Inserting VLAN tag %08x\n",
3842 pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
3843 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
3844 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
3845 pSg->cbUsed += 4;
3846 cbFrame += 4;
3847 Assert(pSg->cbUsed == cbFrame);
3848 Assert(pSg->cbUsed <= pSg->cbAvailable);
3849 }
3850/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
3851 "%.*Rhxd\n"
3852 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
3853 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
3854
3855 /* Update the stats */
3856 E1K_INC_CNT32(TPT);
3857 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3858 E1K_INC_CNT32(GPTC);
3859 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3860 E1K_INC_CNT32(BPTC);
3861 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3862 E1K_INC_CNT32(MPTC);
3863 /* Update octet transmit counter */
3864 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3865 if (pThis->CTX_SUFF(pDrv))
3866 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
3867 if (cbFrame == 64)
3868 E1K_INC_CNT32(PTC64);
3869 else if (cbFrame < 128)
3870 E1K_INC_CNT32(PTC127);
3871 else if (cbFrame < 256)
3872 E1K_INC_CNT32(PTC255);
3873 else if (cbFrame < 512)
3874 E1K_INC_CNT32(PTC511);
3875 else if (cbFrame < 1024)
3876 E1K_INC_CNT32(PTC1023);
3877 else
3878 E1K_INC_CNT32(PTC1522);
3879
3880 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
3881
3882 /*
3883 * Dump and send the packet.
3884 */
3885 int rc = VERR_NET_DOWN;
3886 if (pSg && pSg->pvAllocator != pThis)
3887 {
3888 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3889
3890 pThis->CTX_SUFF(pTxSg) = NULL;
3891 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3892 if (pDrv)
3893 {
3894 /* Release critical section to avoid deadlock in CanReceive */
3895 //e1kCsLeave(pThis);
3896 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3897 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3898 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3899 //e1kCsEnter(pThis, RT_SRC_POS);
3900 }
3901 }
3902 else if (pSg)
3903 {
3904 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
3905 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3906
3907 /** @todo do we actually need to check that we're in loopback mode here? */
3908 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3909 {
3910 E1KRXDST status;
3911 RT_ZERO(status);
3912 status.fPIF = true;
3913 e1kHandleRxPacket(pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
3914 rc = VINF_SUCCESS;
3915 }
3916 e1kXmitFreeBuf(pThis);
3917 }
3918 else
3919 rc = VERR_NET_DOWN;
3920 if (RT_FAILURE(rc))
3921 {
3922 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3923 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3924 }
3925
3926 pThis->led.Actual.s.fWriting = 0;
3927}
3928
3929/**
3930 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3931 *
3932 * @param pThis The device state structure.
3933 * @param pPkt Pointer to the packet.
3934 * @param u16PktLen Total length of the packet.
3935 * @param cso Offset in packet to write checksum at.
3936 * @param css Offset in packet to start computing
3937 * checksum from.
3938 * @param cse Offset in packet to stop computing
3939 * checksum at.
3940 * @thread E1000_TX
3941 */
3942static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3943{
3944 if (css >= u16PktLen)
3945 {
3946 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
3947 pThis->szPrf, cso, u16PktLen));
3948 return;
3949 }
3950
3951 if (cso >= u16PktLen - 1)
3952 {
3953 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
3954 pThis->szPrf, cso, u16PktLen));
3955 return;
3956 }
3957
3958 if (cse == 0)
3959 cse = u16PktLen - 1;
3960 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
3961 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
3962 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
3963 *(uint16_t*)(pPkt + cso) = u16ChkSum;
3964}
3965
3966/**
3967 * Add a part of descriptor's buffer to transmit frame.
3968 *
3969 * @remarks data.u64BufAddr is used unconditionally for both data
3970 * and legacy descriptors since it is identical to
3971 * legacy.u64BufAddr.
3972 *
3973 * @param pThis The device state structure.
3974 * @param pDesc Pointer to the descriptor to transmit.
3975 * @param u16Len Length of buffer to the end of segment.
3976 * @param fSend Force packet sending.
3977 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3978 * @thread E1000_TX
3979 */
3980#ifndef E1K_WITH_TXD_CACHE
3981static void e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
3982{
3983 /* TCP header being transmitted */
3984 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
3985 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
3986 /* IP header being transmitted */
3987 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
3988 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
3989
3990 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
3991 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
3992 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
3993
3994 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
3995 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
3996 E1kLog3(("%s Dump of the segment:\n"
3997 "%.*Rhxd\n"
3998 "%s --- End of dump ---\n",
3999 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4000 pThis->u16TxPktLen += u16Len;
4001 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4002 pThis->szPrf, pThis->u16TxPktLen));
4003 if (pThis->u16HdrRemain > 0)
4004 {
4005 /* The header was not complete, check if it is now */
4006 if (u16Len >= pThis->u16HdrRemain)
4007 {
4008 /* The rest is payload */
4009 u16Len -= pThis->u16HdrRemain;
4010 pThis->u16HdrRemain = 0;
4011 /* Save partial checksum and flags */
4012 pThis->u32SavedCsum = pTcpHdr->chksum;
4013 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4014 /* Clear FIN and PSH flags now and set them only in the last segment */
4015 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4016 }
4017 else
4018 {
4019 /* Still not */
4020 pThis->u16HdrRemain -= u16Len;
4021 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4022 pThis->szPrf, pThis->u16HdrRemain));
4023 return;
4024 }
4025 }
4026
4027 pThis->u32PayRemain -= u16Len;
4028
4029 if (fSend)
4030 {
4031 /* Leave ethernet header intact */
4032 /* IP Total Length = payload + headers - ethernet header */
4033 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4034 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4035 pThis->szPrf, ntohs(pIpHdr->total_len)));
4036 /* Update IP Checksum */
4037 pIpHdr->chksum = 0;
4038 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4039 pThis->contextTSE.ip.u8CSO,
4040 pThis->contextTSE.ip.u8CSS,
4041 pThis->contextTSE.ip.u16CSE);
4042
4043 /* Update TCP flags */
4044 /* Restore original FIN and PSH flags for the last segment */
4045 if (pThis->u32PayRemain == 0)
4046 {
4047 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4048 E1K_INC_CNT32(TSCTC);
4049 }
4050 /* Add TCP length to partial pseudo header sum */
4051 uint32_t csum = pThis->u32SavedCsum
4052 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4053 while (csum >> 16)
4054 csum = (csum >> 16) + (csum & 0xFFFF);
4055 pTcpHdr->chksum = csum;
4056 /* Compute final checksum */
4057 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4058 pThis->contextTSE.tu.u8CSO,
4059 pThis->contextTSE.tu.u8CSS,
4060 pThis->contextTSE.tu.u16CSE);
4061
4062 /*
4063 * Transmit it. If we've use the SG already, allocate a new one before
4064 * we copy of the data.
4065 */
4066 if (!pThis->CTX_SUFF(pTxSg))
4067 e1kXmitAllocBuf(pThis, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4068 if (pThis->CTX_SUFF(pTxSg))
4069 {
4070 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4071 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4072 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4073 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4074 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4075 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4076 }
4077 e1kTransmitFrame(pThis, fOnWorkerThread);
4078
4079 /* Update Sequence Number */
4080 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4081 - pThis->contextTSE.dw3.u8HDRLEN);
4082 /* Increment IP identification */
4083 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4084 }
4085}
4086#else /* E1K_WITH_TXD_CACHE */
4087static int e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4088{
4089 int rc = VINF_SUCCESS;
4090 /* TCP header being transmitted */
4091 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4092 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4093 /* IP header being transmitted */
4094 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4095 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4096
4097 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4098 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4099 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4100
4101 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4102 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4103 E1kLog3(("%s Dump of the segment:\n"
4104 "%.*Rhxd\n"
4105 "%s --- End of dump ---\n",
4106 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4107 pThis->u16TxPktLen += u16Len;
4108 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4109 pThis->szPrf, pThis->u16TxPktLen));
4110 if (pThis->u16HdrRemain > 0)
4111 {
4112 /* The header was not complete, check if it is now */
4113 if (u16Len >= pThis->u16HdrRemain)
4114 {
4115 /* The rest is payload */
4116 u16Len -= pThis->u16HdrRemain;
4117 pThis->u16HdrRemain = 0;
4118 /* Save partial checksum and flags */
4119 pThis->u32SavedCsum = pTcpHdr->chksum;
4120 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4121 /* Clear FIN and PSH flags now and set them only in the last segment */
4122 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4123 }
4124 else
4125 {
4126 /* Still not */
4127 pThis->u16HdrRemain -= u16Len;
4128 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4129 pThis->szPrf, pThis->u16HdrRemain));
4130 return rc;
4131 }
4132 }
4133
4134 pThis->u32PayRemain -= u16Len;
4135
4136 if (fSend)
4137 {
4138 /* Leave ethernet header intact */
4139 /* IP Total Length = payload + headers - ethernet header */
4140 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4141 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4142 pThis->szPrf, ntohs(pIpHdr->total_len)));
4143 /* Update IP Checksum */
4144 pIpHdr->chksum = 0;
4145 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4146 pThis->contextTSE.ip.u8CSO,
4147 pThis->contextTSE.ip.u8CSS,
4148 pThis->contextTSE.ip.u16CSE);
4149
4150 /* Update TCP flags */
4151 /* Restore original FIN and PSH flags for the last segment */
4152 if (pThis->u32PayRemain == 0)
4153 {
4154 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4155 E1K_INC_CNT32(TSCTC);
4156 }
4157 /* Add TCP length to partial pseudo header sum */
4158 uint32_t csum = pThis->u32SavedCsum
4159 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4160 while (csum >> 16)
4161 csum = (csum >> 16) + (csum & 0xFFFF);
4162 pTcpHdr->chksum = csum;
4163 /* Compute final checksum */
4164 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4165 pThis->contextTSE.tu.u8CSO,
4166 pThis->contextTSE.tu.u8CSS,
4167 pThis->contextTSE.tu.u16CSE);
4168
4169 /*
4170 * Transmit it.
4171 */
4172 if (pThis->CTX_SUFF(pTxSg))
4173 {
4174 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4175 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4176 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4177 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4178 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4179 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4180 }
4181 e1kTransmitFrame(pThis, fOnWorkerThread);
4182
4183 /* Update Sequence Number */
4184 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4185 - pThis->contextTSE.dw3.u8HDRLEN);
4186 /* Increment IP identification */
4187 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4188
4189 /* Allocate new buffer for the next segment. */
4190 if (pThis->u32PayRemain)
4191 {
4192 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4193 pThis->contextTSE.dw3.u16MSS)
4194 + pThis->contextTSE.dw3.u8HDRLEN
4195 + (pThis->fVTag ? 4 : 0);
4196 rc = e1kXmitAllocBuf(pThis, false /* fGSO */);
4197 }
4198 }
4199
4200 return rc;
4201}
4202#endif /* E1K_WITH_TXD_CACHE */
4203
4204#ifndef E1K_WITH_TXD_CACHE
4205/**
4206 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4207 * frame.
4208 *
4209 * We construct the frame in the fallback buffer first and the copy it to the SG
4210 * buffer before passing it down to the network driver code.
4211 *
4212 * @returns true if the frame should be transmitted, false if not.
4213 *
4214 * @param pThis The device state structure.
4215 * @param pDesc Pointer to the descriptor to transmit.
4216 * @param cbFragment Length of descriptor's buffer.
4217 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4218 * @thread E1000_TX
4219 */
4220static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4221{
4222 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4223 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4224 Assert(pDesc->data.cmd.fTSE);
4225 Assert(!e1kXmitIsGsoBuf(pTxSg));
4226
4227 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4228 Assert(u16MaxPktLen != 0);
4229 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4230
4231 /*
4232 * Carve out segments.
4233 */
4234 do
4235 {
4236 /* Calculate how many bytes we have left in this TCP segment */
4237 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4238 if (cb > cbFragment)
4239 {
4240 /* This descriptor fits completely into current segment */
4241 cb = cbFragment;
4242 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4243 }
4244 else
4245 {
4246 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4247 /*
4248 * Rewind the packet tail pointer to the beginning of payload,
4249 * so we continue writing right beyond the header.
4250 */
4251 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4252 }
4253
4254 pDesc->data.u64BufAddr += cb;
4255 cbFragment -= cb;
4256 } while (cbFragment > 0);
4257
4258 if (pDesc->data.cmd.fEOP)
4259 {
4260 /* End of packet, next segment will contain header. */
4261 if (pThis->u32PayRemain != 0)
4262 E1K_INC_CNT32(TSCTFC);
4263 pThis->u16TxPktLen = 0;
4264 e1kXmitFreeBuf(pThis);
4265 }
4266
4267 return false;
4268}
4269#else /* E1K_WITH_TXD_CACHE */
4270/**
4271 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4272 * frame.
4273 *
4274 * We construct the frame in the fallback buffer first and the copy it to the SG
4275 * buffer before passing it down to the network driver code.
4276 *
4277 * @returns error code
4278 *
4279 * @param pThis The device state structure.
4280 * @param pDesc Pointer to the descriptor to transmit.
4281 * @param cbFragment Length of descriptor's buffer.
4282 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4283 * @thread E1000_TX
4284 */
4285static int e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, bool fOnWorkerThread)
4286{
4287 int rc = VINF_SUCCESS;
4288 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4289 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4290 Assert(pDesc->data.cmd.fTSE);
4291 Assert(!e1kXmitIsGsoBuf(pTxSg));
4292
4293 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4294 Assert(u16MaxPktLen != 0);
4295 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4296
4297 /*
4298 * Carve out segments.
4299 */
4300 do
4301 {
4302 /* Calculate how many bytes we have left in this TCP segment */
4303 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4304 if (cb > pDesc->data.cmd.u20DTALEN)
4305 {
4306 /* This descriptor fits completely into current segment */
4307 cb = pDesc->data.cmd.u20DTALEN;
4308 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4309 }
4310 else
4311 {
4312 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4313 /*
4314 * Rewind the packet tail pointer to the beginning of payload,
4315 * so we continue writing right beyond the header.
4316 */
4317 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4318 }
4319
4320 pDesc->data.u64BufAddr += cb;
4321 pDesc->data.cmd.u20DTALEN -= cb;
4322 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4323
4324 if (pDesc->data.cmd.fEOP)
4325 {
4326 /* End of packet, next segment will contain header. */
4327 if (pThis->u32PayRemain != 0)
4328 E1K_INC_CNT32(TSCTFC);
4329 pThis->u16TxPktLen = 0;
4330 e1kXmitFreeBuf(pThis);
4331 }
4332
4333 return false;
4334}
4335#endif /* E1K_WITH_TXD_CACHE */
4336
4337
4338/**
4339 * Add descriptor's buffer to transmit frame.
4340 *
4341 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4342 * TSE frames we cannot handle as GSO.
4343 *
4344 * @returns true on success, false on failure.
4345 *
4346 * @param pThis The device state structure.
4347 * @param PhysAddr The physical address of the descriptor buffer.
4348 * @param cbFragment Length of descriptor's buffer.
4349 * @thread E1000_TX
4350 */
4351static bool e1kAddToFrame(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
4352{
4353 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4354 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4355 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4356
4357 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4358 {
4359 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4360 return false;
4361 }
4362 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
4363 {
4364 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4365 return false;
4366 }
4367
4368 if (RT_LIKELY(pTxSg))
4369 {
4370 Assert(pTxSg->cSegs == 1);
4371 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
4372
4373 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4374 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4375
4376 pTxSg->cbUsed = cbNewPkt;
4377 }
4378 pThis->u16TxPktLen = cbNewPkt;
4379
4380 return true;
4381}
4382
4383
4384/**
4385 * Write the descriptor back to guest memory and notify the guest.
4386 *
4387 * @param pThis The device state structure.
4388 * @param pDesc Pointer to the descriptor have been transmitted.
4389 * @param addr Physical address of the descriptor in guest memory.
4390 * @thread E1000_TX
4391 */
4392static void e1kDescReport(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
4393{
4394 /*
4395 * We fake descriptor write-back bursting. Descriptors are written back as they are
4396 * processed.
4397 */
4398 /* Let's pretend we process descriptors. Write back with DD set. */
4399 /*
4400 * Prior to r71586 we tried to accomodate the case when write-back bursts
4401 * are enabled without actually implementing bursting by writing back all
4402 * descriptors, even the ones that do not have RS set. This caused kernel
4403 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4404 * associated with written back descriptor if it happened to be a context
4405 * descriptor since context descriptors do not have skb associated to them.
4406 * Starting from r71586 we write back only the descriptors with RS set,
4407 * which is a little bit different from what the real hardware does in
4408 * case there is a chain of data descritors where some of them have RS set
4409 * and others do not. It is very uncommon scenario imho.
4410 * We need to check RPS as well since some legacy drivers use it instead of
4411 * RS even with newer cards.
4412 */
4413 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4414 {
4415 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4416 e1kWriteBackDesc(pThis, pDesc, addr);
4417 if (pDesc->legacy.cmd.fEOP)
4418 {
4419#ifdef E1K_USE_TX_TIMERS
4420 if (pDesc->legacy.cmd.fIDE)
4421 {
4422 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4423 //if (pThis->fIntRaised)
4424 //{
4425 // /* Interrupt is already pending, no need for timers */
4426 // ICR |= ICR_TXDW;
4427 //}
4428 //else {
4429 /* Arm the timer to fire in TIVD usec (discard .024) */
4430 e1kArmTimer(pThis, pThis->CTX_SUFF(pTIDTimer), TIDV);
4431# ifndef E1K_NO_TAD
4432 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4433 E1kLog2(("%s Checking if TAD timer is running\n",
4434 pThis->szPrf));
4435 if (TADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pTADTimer)))
4436 e1kArmTimer(pThis, pThis->CTX_SUFF(pTADTimer), TADV);
4437# endif /* E1K_NO_TAD */
4438 }
4439 else
4440 {
4441 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4442 pThis->szPrf));
4443# ifndef E1K_NO_TAD
4444 /* Cancel both timers if armed and fire immediately. */
4445 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
4446# endif /* E1K_NO_TAD */
4447#endif /* E1K_USE_TX_TIMERS */
4448 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4449 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXDW);
4450#ifdef E1K_USE_TX_TIMERS
4451 }
4452#endif /* E1K_USE_TX_TIMERS */
4453 }
4454 }
4455 else
4456 {
4457 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4458 }
4459}
4460
4461#ifndef E1K_WITH_TXD_CACHE
4462
4463/**
4464 * Process Transmit Descriptor.
4465 *
4466 * E1000 supports three types of transmit descriptors:
4467 * - legacy data descriptors of older format (context-less).
4468 * - data the same as legacy but providing new offloading capabilities.
4469 * - context sets up the context for following data descriptors.
4470 *
4471 * @param pThis The device state structure.
4472 * @param pDesc Pointer to descriptor union.
4473 * @param addr Physical address of descriptor in guest memory.
4474 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4475 * @thread E1000_TX
4476 */
4477static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
4478{
4479 int rc = VINF_SUCCESS;
4480 uint32_t cbVTag = 0;
4481
4482 e1kPrintTDesc(pThis, pDesc, "vvv");
4483
4484#ifdef E1K_USE_TX_TIMERS
4485 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4486#endif /* E1K_USE_TX_TIMERS */
4487
4488 switch (e1kGetDescType(pDesc))
4489 {
4490 case E1K_DTYP_CONTEXT:
4491 if (pDesc->context.dw2.fTSE)
4492 {
4493 pThis->contextTSE = pDesc->context;
4494 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4495 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4496 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4497 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4498 }
4499 else
4500 {
4501 pThis->contextNormal = pDesc->context;
4502 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4503 }
4504 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4505 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4506 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4507 pDesc->context.ip.u8CSS,
4508 pDesc->context.ip.u8CSO,
4509 pDesc->context.ip.u16CSE,
4510 pDesc->context.tu.u8CSS,
4511 pDesc->context.tu.u8CSO,
4512 pDesc->context.tu.u16CSE));
4513 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4514 e1kDescReport(pThis, pDesc, addr);
4515 break;
4516
4517 case E1K_DTYP_DATA:
4518 {
4519 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4520 {
4521 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4522 /** @todo Same as legacy when !TSE. See below. */
4523 break;
4524 }
4525 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4526 &pThis->StatTxDescTSEData:
4527 &pThis->StatTxDescData);
4528 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4529 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4530
4531 /*
4532 * The last descriptor of non-TSE packet must contain VLE flag.
4533 * TSE packets have VLE flag in the first descriptor. The later
4534 * case is taken care of a bit later when cbVTag gets assigned.
4535 *
4536 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4537 */
4538 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4539 {
4540 pThis->fVTag = pDesc->data.cmd.fVLE;
4541 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4542 }
4543 /*
4544 * First fragment: Allocate new buffer and save the IXSM and TXSM
4545 * packet options as these are only valid in the first fragment.
4546 */
4547 if (pThis->u16TxPktLen == 0)
4548 {
4549 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4550 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4551 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4552 pThis->fIPcsum ? " IP" : "",
4553 pThis->fTCPcsum ? " TCP/UDP" : ""));
4554 if (pDesc->data.cmd.fTSE)
4555 {
4556 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4557 pThis->fVTag = pDesc->data.cmd.fVLE;
4558 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4559 cbVTag = pThis->fVTag ? 4 : 0;
4560 }
4561 else if (pDesc->data.cmd.fEOP)
4562 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4563 else
4564 cbVTag = 4;
4565 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4566 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4567 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4568 true /*fExactSize*/, true /*fGso*/);
4569 else if (pDesc->data.cmd.fTSE)
4570 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4571 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4572 else
4573 rc = e1kXmitAllocBuf(pThis, pDesc->data.cmd.u20DTALEN + cbVTag,
4574 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4575
4576 /**
4577 * @todo: Perhaps it is not that simple for GSO packets! We may
4578 * need to unwind some changes.
4579 */
4580 if (RT_FAILURE(rc))
4581 {
4582 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4583 break;
4584 }
4585 /** @todo Is there any way to indicating errors other than collisions? Like
4586 * VERR_NET_DOWN. */
4587 }
4588
4589 /*
4590 * Add the descriptor data to the frame. If the frame is complete,
4591 * transmit it and reset the u16TxPktLen field.
4592 */
4593 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4594 {
4595 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4596 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4597 if (pDesc->data.cmd.fEOP)
4598 {
4599 if ( fRc
4600 && pThis->CTX_SUFF(pTxSg)
4601 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4602 {
4603 e1kTransmitFrame(pThis, fOnWorkerThread);
4604 E1K_INC_CNT32(TSCTC);
4605 }
4606 else
4607 {
4608 if (fRc)
4609 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4610 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4611 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4612 e1kXmitFreeBuf(pThis);
4613 E1K_INC_CNT32(TSCTFC);
4614 }
4615 pThis->u16TxPktLen = 0;
4616 }
4617 }
4618 else if (!pDesc->data.cmd.fTSE)
4619 {
4620 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4621 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4622 if (pDesc->data.cmd.fEOP)
4623 {
4624 if (fRc && pThis->CTX_SUFF(pTxSg))
4625 {
4626 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4627 if (pThis->fIPcsum)
4628 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4629 pThis->contextNormal.ip.u8CSO,
4630 pThis->contextNormal.ip.u8CSS,
4631 pThis->contextNormal.ip.u16CSE);
4632 if (pThis->fTCPcsum)
4633 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4634 pThis->contextNormal.tu.u8CSO,
4635 pThis->contextNormal.tu.u8CSS,
4636 pThis->contextNormal.tu.u16CSE);
4637 e1kTransmitFrame(pThis, fOnWorkerThread);
4638 }
4639 else
4640 e1kXmitFreeBuf(pThis);
4641 pThis->u16TxPktLen = 0;
4642 }
4643 }
4644 else
4645 {
4646 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4647 e1kFallbackAddToFrame(pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4648 }
4649
4650 e1kDescReport(pThis, pDesc, addr);
4651 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4652 break;
4653 }
4654
4655 case E1K_DTYP_LEGACY:
4656 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4657 {
4658 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4659 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4660 break;
4661 }
4662 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4663 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4664
4665 /* First fragment: allocate new buffer. */
4666 if (pThis->u16TxPktLen == 0)
4667 {
4668 if (pDesc->legacy.cmd.fEOP)
4669 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4670 else
4671 cbVTag = 4;
4672 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4673 /** @todo reset status bits? */
4674 rc = e1kXmitAllocBuf(pThis, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4675 if (RT_FAILURE(rc))
4676 {
4677 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4678 break;
4679 }
4680
4681 /** @todo Is there any way to indicating errors other than collisions? Like
4682 * VERR_NET_DOWN. */
4683 }
4684
4685 /* Add fragment to frame. */
4686 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4687 {
4688 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4689
4690 /* Last fragment: Transmit and reset the packet storage counter. */
4691 if (pDesc->legacy.cmd.fEOP)
4692 {
4693 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4694 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4695 /** @todo Offload processing goes here. */
4696 e1kTransmitFrame(pThis, fOnWorkerThread);
4697 pThis->u16TxPktLen = 0;
4698 }
4699 }
4700 /* Last fragment + failure: free the buffer and reset the storage counter. */
4701 else if (pDesc->legacy.cmd.fEOP)
4702 {
4703 e1kXmitFreeBuf(pThis);
4704 pThis->u16TxPktLen = 0;
4705 }
4706
4707 e1kDescReport(pThis, pDesc, addr);
4708 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4709 break;
4710
4711 default:
4712 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4713 pThis->szPrf, e1kGetDescType(pDesc)));
4714 break;
4715 }
4716
4717 return rc;
4718}
4719
4720#else /* E1K_WITH_TXD_CACHE */
4721
4722/**
4723 * Process Transmit Descriptor.
4724 *
4725 * E1000 supports three types of transmit descriptors:
4726 * - legacy data descriptors of older format (context-less).
4727 * - data the same as legacy but providing new offloading capabilities.
4728 * - context sets up the context for following data descriptors.
4729 *
4730 * @param pThis The device state structure.
4731 * @param pDesc Pointer to descriptor union.
4732 * @param addr Physical address of descriptor in guest memory.
4733 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4734 * @param cbPacketSize Size of the packet as previously computed.
4735 * @thread E1000_TX
4736 */
4737static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr,
4738 bool fOnWorkerThread)
4739{
4740 int rc = VINF_SUCCESS;
4741 uint32_t cbVTag = 0;
4742
4743 e1kPrintTDesc(pThis, pDesc, "vvv");
4744
4745#ifdef E1K_USE_TX_TIMERS
4746 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4747#endif /* E1K_USE_TX_TIMERS */
4748
4749 switch (e1kGetDescType(pDesc))
4750 {
4751 case E1K_DTYP_CONTEXT:
4752 /* The caller have already updated the context */
4753 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4754 e1kDescReport(pThis, pDesc, addr);
4755 break;
4756
4757 case E1K_DTYP_DATA:
4758 {
4759 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4760 &pThis->StatTxDescTSEData:
4761 &pThis->StatTxDescData);
4762 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4763 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4764 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4765 {
4766 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4767 }
4768 else
4769 {
4770 /*
4771 * Add the descriptor data to the frame. If the frame is complete,
4772 * transmit it and reset the u16TxPktLen field.
4773 */
4774 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4775 {
4776 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4777 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4778 if (pDesc->data.cmd.fEOP)
4779 {
4780 if ( fRc
4781 && pThis->CTX_SUFF(pTxSg)
4782 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4783 {
4784 e1kTransmitFrame(pThis, fOnWorkerThread);
4785 E1K_INC_CNT32(TSCTC);
4786 }
4787 else
4788 {
4789 if (fRc)
4790 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4791 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4792 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4793 e1kXmitFreeBuf(pThis);
4794 E1K_INC_CNT32(TSCTFC);
4795 }
4796 pThis->u16TxPktLen = 0;
4797 }
4798 }
4799 else if (!pDesc->data.cmd.fTSE)
4800 {
4801 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4802 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4803 if (pDesc->data.cmd.fEOP)
4804 {
4805 if (fRc && pThis->CTX_SUFF(pTxSg))
4806 {
4807 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4808 if (pThis->fIPcsum)
4809 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4810 pThis->contextNormal.ip.u8CSO,
4811 pThis->contextNormal.ip.u8CSS,
4812 pThis->contextNormal.ip.u16CSE);
4813 if (pThis->fTCPcsum)
4814 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4815 pThis->contextNormal.tu.u8CSO,
4816 pThis->contextNormal.tu.u8CSS,
4817 pThis->contextNormal.tu.u16CSE);
4818 e1kTransmitFrame(pThis, fOnWorkerThread);
4819 }
4820 else
4821 e1kXmitFreeBuf(pThis);
4822 pThis->u16TxPktLen = 0;
4823 }
4824 }
4825 else
4826 {
4827 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4828 rc = e1kFallbackAddToFrame(pThis, pDesc, fOnWorkerThread);
4829 }
4830 }
4831 e1kDescReport(pThis, pDesc, addr);
4832 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4833 break;
4834 }
4835
4836 case E1K_DTYP_LEGACY:
4837 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4838 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4839 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4840 {
4841 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4842 }
4843 else
4844 {
4845 /* Add fragment to frame. */
4846 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4847 {
4848 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4849
4850 /* Last fragment: Transmit and reset the packet storage counter. */
4851 if (pDesc->legacy.cmd.fEOP)
4852 {
4853 if (pDesc->legacy.cmd.fIC)
4854 {
4855 e1kInsertChecksum(pThis,
4856 (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
4857 pThis->u16TxPktLen,
4858 pDesc->legacy.cmd.u8CSO,
4859 pDesc->legacy.dw3.u8CSS,
4860 0);
4861 }
4862 e1kTransmitFrame(pThis, fOnWorkerThread);
4863 pThis->u16TxPktLen = 0;
4864 }
4865 }
4866 /* Last fragment + failure: free the buffer and reset the storage counter. */
4867 else if (pDesc->legacy.cmd.fEOP)
4868 {
4869 e1kXmitFreeBuf(pThis);
4870 pThis->u16TxPktLen = 0;
4871 }
4872 }
4873 e1kDescReport(pThis, pDesc, addr);
4874 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4875 break;
4876
4877 default:
4878 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4879 pThis->szPrf, e1kGetDescType(pDesc)));
4880 break;
4881 }
4882
4883 return rc;
4884}
4885
4886DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC* pDesc)
4887{
4888 if (pDesc->context.dw2.fTSE)
4889 {
4890 pThis->contextTSE = pDesc->context;
4891 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4892 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4893 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4894 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4895 }
4896 else
4897 {
4898 pThis->contextNormal = pDesc->context;
4899 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4900 }
4901 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4902 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4903 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4904 pDesc->context.ip.u8CSS,
4905 pDesc->context.ip.u8CSO,
4906 pDesc->context.ip.u16CSE,
4907 pDesc->context.tu.u8CSS,
4908 pDesc->context.tu.u8CSO,
4909 pDesc->context.tu.u16CSE));
4910}
4911
4912static bool e1kLocateTxPacket(PE1KSTATE pThis)
4913{
4914 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
4915 pThis->szPrf, pThis->cbTxAlloc));
4916 /* Check if we have located the packet already. */
4917 if (pThis->cbTxAlloc)
4918 {
4919 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
4920 pThis->szPrf, pThis->cbTxAlloc));
4921 return true;
4922 }
4923
4924 bool fTSE = false;
4925 uint32_t cbPacket = 0;
4926
4927 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
4928 {
4929 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
4930 switch (e1kGetDescType(pDesc))
4931 {
4932 case E1K_DTYP_CONTEXT:
4933 e1kUpdateTxContext(pThis, pDesc);
4934 continue;
4935 case E1K_DTYP_LEGACY:
4936 /* Skip empty descriptors. */
4937 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
4938 break;
4939 cbPacket += pDesc->legacy.cmd.u16Length;
4940 pThis->fGSO = false;
4941 break;
4942 case E1K_DTYP_DATA:
4943 /* Skip empty descriptors. */
4944 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
4945 break;
4946 if (cbPacket == 0)
4947 {
4948 /*
4949 * The first fragment: save IXSM and TXSM options
4950 * as these are only valid in the first fragment.
4951 */
4952 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4953 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4954 fTSE = pDesc->data.cmd.fTSE;
4955 /*
4956 * TSE descriptors have VLE bit properly set in
4957 * the first fragment.
4958 */
4959 if (fTSE)
4960 {
4961 pThis->fVTag = pDesc->data.cmd.fVLE;
4962 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4963 }
4964 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
4965 }
4966 cbPacket += pDesc->data.cmd.u20DTALEN;
4967 break;
4968 default:
4969 AssertMsgFailed(("Impossible descriptor type!"));
4970 }
4971 if (pDesc->legacy.cmd.fEOP)
4972 {
4973 /*
4974 * Non-TSE descriptors have VLE bit properly set in
4975 * the last fragment.
4976 */
4977 if (!fTSE)
4978 {
4979 pThis->fVTag = pDesc->data.cmd.fVLE;
4980 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4981 }
4982 /*
4983 * Compute the required buffer size. If we cannot do GSO but still
4984 * have to do segmentation we allocate the first segment only.
4985 */
4986 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
4987 cbPacket :
4988 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
4989 if (pThis->fVTag)
4990 pThis->cbTxAlloc += 4;
4991 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
4992 pThis->szPrf, pThis->cbTxAlloc));
4993 return true;
4994 }
4995 }
4996
4997 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
4998 {
4999 /* All descriptors were empty, we need to process them as a dummy packet */
5000 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5001 pThis->szPrf, pThis->cbTxAlloc));
5002 return true;
5003 }
5004 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d\n",
5005 pThis->szPrf, pThis->cbTxAlloc));
5006 return false;
5007}
5008
5009static int e1kXmitPacket(PE1KSTATE pThis, bool fOnWorkerThread)
5010{
5011 int rc = VINF_SUCCESS;
5012
5013 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5014 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5015
5016 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5017 {
5018 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5019 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5020 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5021 rc = e1kXmitDesc(pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5022 if (RT_FAILURE(rc))
5023 break;
5024 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5025 TDH = 0;
5026 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5027 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5028 {
5029 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5030 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5031 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5032 }
5033 ++pThis->iTxDCurrent;
5034 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5035 break;
5036 }
5037
5038 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5039 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5040 return rc;
5041}
5042
5043#endif /* E1K_WITH_TXD_CACHE */
5044#ifndef E1K_WITH_TXD_CACHE
5045
5046/**
5047 * Transmit pending descriptors.
5048 *
5049 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5050 *
5051 * @param pThis The E1000 state.
5052 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5053 */
5054static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5055{
5056 int rc = VINF_SUCCESS;
5057
5058 /* Check if transmitter is enabled. */
5059 if (!(TCTL & TCTL_EN))
5060 return VINF_SUCCESS;
5061 /*
5062 * Grab the xmit lock of the driver as well as the E1K device state.
5063 */
5064 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5065 if (RT_LIKELY(rc == VINF_SUCCESS))
5066 {
5067 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5068 if (pDrv)
5069 {
5070 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5071 if (RT_FAILURE(rc))
5072 {
5073 e1kCsTxLeave(pThis);
5074 return rc;
5075 }
5076 }
5077 /*
5078 * Process all pending descriptors.
5079 * Note! Do not process descriptors in locked state
5080 */
5081 while (TDH != TDT && !pThis->fLocked)
5082 {
5083 E1KTXDESC desc;
5084 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5085 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5086
5087 e1kLoadDesc(pThis, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5088 rc = e1kXmitDesc(pThis, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5089 /* If we failed to transmit descriptor we will try it again later */
5090 if (RT_FAILURE(rc))
5091 break;
5092 if (++TDH * sizeof(desc) >= TDLEN)
5093 TDH = 0;
5094
5095 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5096 {
5097 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5098 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5099 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5100 }
5101
5102 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5103 }
5104
5105 /// @todo: uncomment: pThis->uStatIntTXQE++;
5106 /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5107 /*
5108 * Release the lock.
5109 */
5110 if (pDrv)
5111 pDrv->pfnEndXmit(pDrv);
5112 e1kCsTxLeave(pThis);
5113 }
5114
5115 return rc;
5116}
5117
5118#else /* E1K_WITH_TXD_CACHE */
5119
5120static void e1kDumpTxDCache(PE1KSTATE pThis)
5121{
5122 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5123 uint32_t tdh = TDH;
5124 LogRel(("-- Transmit Descriptors (%d total) --\n", cDescs));
5125 for (i = 0; i < cDescs; ++i)
5126 {
5127 E1KTXDESC desc;
5128 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
5129 &desc, sizeof(desc));
5130 if (i == tdh)
5131 LogRel((">>> "));
5132 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5133 }
5134 LogRel(("-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5135 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5136 if (tdh > pThis->iTxDCurrent)
5137 tdh -= pThis->iTxDCurrent;
5138 else
5139 tdh = cDescs + tdh - pThis->iTxDCurrent;
5140 for (i = 0; i < pThis->nTxDFetched; ++i)
5141 {
5142 if (i == pThis->iTxDCurrent)
5143 LogRel((">>> "));
5144 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5145 }
5146}
5147
5148/**
5149 * Transmit pending descriptors.
5150 *
5151 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5152 *
5153 * @param pThis The E1000 state.
5154 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5155 */
5156static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5157{
5158 int rc = VINF_SUCCESS;
5159
5160 /* Check if transmitter is enabled. */
5161 if (!(TCTL & TCTL_EN))
5162 return VINF_SUCCESS;
5163 /*
5164 * Grab the xmit lock of the driver as well as the E1K device state.
5165 */
5166 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5167 if (pDrv)
5168 {
5169 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5170 if (RT_FAILURE(rc))
5171 return rc;
5172 }
5173
5174 /*
5175 * Process all pending descriptors.
5176 * Note! Do not process descriptors in locked state
5177 */
5178 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5179 if (RT_LIKELY(rc == VINF_SUCCESS))
5180 {
5181 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5182 /*
5183 * fIncomplete is set whenever we try to fetch additional descriptors
5184 * for an incomplete packet. If fail to locate a complete packet on
5185 * the next iteration we need to reset the cache or we risk to get
5186 * stuck in this loop forever.
5187 */
5188 bool fIncomplete = false;
5189 while (!pThis->fLocked && e1kTxDLazyLoad(pThis))
5190 {
5191 while (e1kLocateTxPacket(pThis))
5192 {
5193 fIncomplete = false;
5194 /* Found a complete packet, allocate it. */
5195 rc = e1kXmitAllocBuf(pThis, pThis->fGSO);
5196 /* If we're out of bandwidth we'll come back later. */
5197 if (RT_FAILURE(rc))
5198 goto out;
5199 /* Copy the packet to allocated buffer and send it. */
5200 rc = e1kXmitPacket(pThis, fOnWorkerThread);
5201 /* If we're out of bandwidth we'll come back later. */
5202 if (RT_FAILURE(rc))
5203 goto out;
5204 }
5205 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5206 if (RT_UNLIKELY(fIncomplete))
5207 {
5208 static bool fTxDCacheDumped = false;
5209 /*
5210 * The descriptor cache is full, but we were unable to find
5211 * a complete packet in it. Drop the cache and hope that
5212 * the guest driver can recover from network card error.
5213 */
5214 LogRel(("%s No complete packets in%s TxD cache! "
5215 "Fetched=%d, current=%d, TX len=%d.\n",
5216 pThis->szPrf,
5217 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5218 pThis->nTxDFetched, pThis->iTxDCurrent,
5219 e1kGetTxLen(pThis)));
5220 if (!fTxDCacheDumped)
5221 {
5222 fTxDCacheDumped = true;
5223 e1kDumpTxDCache(pThis);
5224 }
5225 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5226 /*
5227 * Returning an error at this point means Guru in R0
5228 * (see @bugref{6428}).
5229 */
5230# ifdef IN_RING3
5231 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5232# else /* !IN_RING3 */
5233 rc = VINF_IOM_R3_MMIO_WRITE;
5234# endif /* !IN_RING3 */
5235 goto out;
5236 }
5237 if (u8Remain > 0)
5238 {
5239 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5240 "%d more are available\n",
5241 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5242 e1kGetTxLen(pThis) - u8Remain));
5243
5244 /*
5245 * A packet was partially fetched. Move incomplete packet to
5246 * the beginning of cache buffer, then load more descriptors.
5247 */
5248 memmove(pThis->aTxDescriptors,
5249 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5250 u8Remain * sizeof(E1KTXDESC));
5251 pThis->iTxDCurrent = 0;
5252 pThis->nTxDFetched = u8Remain;
5253 e1kTxDLoadMore(pThis);
5254 fIncomplete = true;
5255 }
5256 else
5257 pThis->nTxDFetched = 0;
5258 pThis->iTxDCurrent = 0;
5259 }
5260 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5261 {
5262 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5263 pThis->szPrf));
5264 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5265 }
5266out:
5267 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5268
5269 /// @todo: uncomment: pThis->uStatIntTXQE++;
5270 /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5271
5272 e1kCsTxLeave(pThis);
5273 }
5274
5275
5276 /*
5277 * Release the lock.
5278 */
5279 if (pDrv)
5280 pDrv->pfnEndXmit(pDrv);
5281 return rc;
5282}
5283
5284#endif /* E1K_WITH_TXD_CACHE */
5285#ifdef IN_RING3
5286
5287/**
5288 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5289 */
5290static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5291{
5292 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
5293 /* Resume suspended transmission */
5294 STATUS &= ~STATUS_TXOFF;
5295 e1kXmitPending(pThis, true /*fOnWorkerThread*/);
5296}
5297
5298/**
5299 * Callback for consuming from transmit queue. It gets called in R3 whenever
5300 * we enqueue something in R0/GC.
5301 *
5302 * @returns true
5303 * @param pDevIns Pointer to device instance structure.
5304 * @param pItem Pointer to the element being dequeued (not used).
5305 * @thread ???
5306 */
5307static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5308{
5309 NOREF(pItem);
5310 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5311 E1kLog2(("%s e1kTxQueueConsumer:\n", pThis->szPrf));
5312
5313 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5314 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
5315
5316 return true;
5317}
5318
5319/**
5320 * Handler for the wakeup signaller queue.
5321 */
5322static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5323{
5324 e1kWakeupReceive(pDevIns);
5325 return true;
5326}
5327
5328#endif /* IN_RING3 */
5329
5330/**
5331 * Write handler for Transmit Descriptor Tail register.
5332 *
5333 * @param pThis The device state structure.
5334 * @param offset Register offset in memory-mapped frame.
5335 * @param index Register index in register array.
5336 * @param value The value to store.
5337 * @param mask Used to implement partial writes (8 and 16-bit).
5338 * @thread EMT
5339 */
5340static int e1kRegWriteTDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5341{
5342 int rc = e1kRegWriteDefault(pThis, offset, index, value);
5343
5344 /* All descriptors starting with head and not including tail belong to us. */
5345 /* Process them. */
5346 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5347 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5348
5349 /* Ignore TDT writes when the link is down. */
5350 if (TDH != TDT && (STATUS & STATUS_LU))
5351 {
5352 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5353 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5354 pThis->szPrf, e1kGetTxLen(pThis)));
5355
5356 /* Transmit pending packets if possible, defer it if we cannot do it
5357 in the current context. */
5358#ifdef E1K_TX_DELAY
5359 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5360 if (RT_LIKELY(rc == VINF_SUCCESS))
5361 {
5362 if (!TMTimerIsActive(pThis->CTX_SUFF(pTXDTimer)))
5363 {
5364#ifdef E1K_INT_STATS
5365 pThis->u64ArmedAt = RTTimeNanoTS();
5366#endif
5367 e1kArmTimer(pThis, pThis->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
5368 }
5369 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5370 e1kCsTxLeave(pThis);
5371 return rc;
5372 }
5373 /* We failed to enter the TX critical section -- transmit as usual. */
5374#endif /* E1K_TX_DELAY */
5375#ifndef IN_RING3
5376 if (!pThis->CTX_SUFF(pDrv))
5377 {
5378 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
5379 if (RT_UNLIKELY(pItem))
5380 PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
5381 }
5382 else
5383#endif
5384 {
5385 rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5386 if (rc == VERR_TRY_AGAIN)
5387 rc = VINF_SUCCESS;
5388 else if (rc == VERR_SEM_BUSY)
5389 rc = VINF_IOM_R3_MMIO_WRITE;
5390 AssertRC(rc);
5391 }
5392 }
5393
5394 return rc;
5395}
5396
5397/**
5398 * Write handler for Multicast Table Array registers.
5399 *
5400 * @param pThis The device state structure.
5401 * @param offset Register offset in memory-mapped frame.
5402 * @param index Register index in register array.
5403 * @param value The value to store.
5404 * @thread EMT
5405 */
5406static int e1kRegWriteMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5407{
5408 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5409 pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])] = value;
5410
5411 return VINF_SUCCESS;
5412}
5413
5414/**
5415 * Read handler for Multicast Table Array registers.
5416 *
5417 * @returns VBox status code.
5418 *
5419 * @param pThis The device state structure.
5420 * @param offset Register offset in memory-mapped frame.
5421 * @param index Register index in register array.
5422 * @thread EMT
5423 */
5424static int e1kRegReadMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5425{
5426 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5427 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5428
5429 return VINF_SUCCESS;
5430}
5431
5432/**
5433 * Write handler for Receive Address registers.
5434 *
5435 * @param pThis The device state structure.
5436 * @param offset Register offset in memory-mapped frame.
5437 * @param index Register index in register array.
5438 * @param value The value to store.
5439 * @thread EMT
5440 */
5441static int e1kRegWriteRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5442{
5443 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5444 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5445
5446 return VINF_SUCCESS;
5447}
5448
5449/**
5450 * Read handler for Receive Address registers.
5451 *
5452 * @returns VBox status code.
5453 *
5454 * @param pThis The device state structure.
5455 * @param offset Register offset in memory-mapped frame.
5456 * @param index Register index in register array.
5457 * @thread EMT
5458 */
5459static int e1kRegReadRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5460{
5461 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5462 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5463
5464 return VINF_SUCCESS;
5465}
5466
5467/**
5468 * Write handler for VLAN Filter Table Array registers.
5469 *
5470 * @param pThis The device state structure.
5471 * @param offset Register offset in memory-mapped frame.
5472 * @param index Register index in register array.
5473 * @param value The value to store.
5474 * @thread EMT
5475 */
5476static int e1kRegWriteVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5477{
5478 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5479 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5480
5481 return VINF_SUCCESS;
5482}
5483
5484/**
5485 * Read handler for VLAN Filter Table Array registers.
5486 *
5487 * @returns VBox status code.
5488 *
5489 * @param pThis The device state structure.
5490 * @param offset Register offset in memory-mapped frame.
5491 * @param index Register index in register array.
5492 * @thread EMT
5493 */
5494static int e1kRegReadVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5495{
5496 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5497 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5498
5499 return VINF_SUCCESS;
5500}
5501
5502/**
5503 * Read handler for unimplemented registers.
5504 *
5505 * Merely reports reads from unimplemented registers.
5506 *
5507 * @returns VBox status code.
5508 *
5509 * @param pThis The device state structure.
5510 * @param offset Register offset in memory-mapped frame.
5511 * @param index Register index in register array.
5512 * @thread EMT
5513 */
5514static int e1kRegReadUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5515{
5516 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5517 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5518 *pu32Value = 0;
5519
5520 return VINF_SUCCESS;
5521}
5522
5523/**
5524 * Default register read handler with automatic clear operation.
5525 *
5526 * Retrieves the value of register from register array in device state structure.
5527 * Then resets all bits.
5528 *
5529 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5530 * done in the caller.
5531 *
5532 * @returns VBox status code.
5533 *
5534 * @param pThis The device state structure.
5535 * @param offset Register offset in memory-mapped frame.
5536 * @param index Register index in register array.
5537 * @thread EMT
5538 */
5539static int e1kRegReadAutoClear(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5540{
5541 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5542 int rc = e1kRegReadDefault(pThis, offset, index, pu32Value);
5543 pThis->auRegs[index] = 0;
5544
5545 return rc;
5546}
5547
5548/**
5549 * Default register read handler.
5550 *
5551 * Retrieves the value of register from register array in device state structure.
5552 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5553 *
5554 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5555 * done in the caller.
5556 *
5557 * @returns VBox status code.
5558 *
5559 * @param pThis The device state structure.
5560 * @param offset Register offset in memory-mapped frame.
5561 * @param index Register index in register array.
5562 * @thread EMT
5563 */
5564static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5565{
5566 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5567 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5568
5569 return VINF_SUCCESS;
5570}
5571
5572/**
5573 * Write handler for unimplemented registers.
5574 *
5575 * Merely reports writes to unimplemented registers.
5576 *
5577 * @param pThis The device state structure.
5578 * @param offset Register offset in memory-mapped frame.
5579 * @param index Register index in register array.
5580 * @param value The value to store.
5581 * @thread EMT
5582 */
5583
5584 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5585{
5586 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5587 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5588
5589 return VINF_SUCCESS;
5590}
5591
5592/**
5593 * Default register write handler.
5594 *
5595 * Stores the value to the register array in device state structure. Only bits
5596 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5597 *
5598 * @returns VBox status code.
5599 *
5600 * @param pThis The device state structure.
5601 * @param offset Register offset in memory-mapped frame.
5602 * @param index Register index in register array.
5603 * @param value The value to store.
5604 * @param mask Used to implement partial writes (8 and 16-bit).
5605 * @thread EMT
5606 */
5607
5608static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5609{
5610 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5611 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5612 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5613
5614 return VINF_SUCCESS;
5615}
5616
5617/**
5618 * Search register table for matching register.
5619 *
5620 * @returns Index in the register table or -1 if not found.
5621 *
5622 * @param pThis The device state structure.
5623 * @param offReg Register offset in memory-mapped region.
5624 * @thread EMT
5625 */
5626static int e1kRegLookup(PE1KSTATE pThis, uint32_t offReg)
5627{
5628#if 0
5629 int index;
5630
5631 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5632 {
5633 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5634 {
5635 return index;
5636 }
5637 }
5638#else
5639 int iStart = 0;
5640 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5641 for (;;)
5642 {
5643 int i = (iEnd - iStart) / 2 + iStart;
5644 uint32_t offCur = g_aE1kRegMap[i].offset;
5645 if (offReg < offCur)
5646 {
5647 if (i == iStart)
5648 break;
5649 iEnd = i;
5650 }
5651 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5652 {
5653 i++;
5654 if (i == iEnd)
5655 break;
5656 iStart = i;
5657 }
5658 else
5659 return i;
5660 Assert(iEnd > iStart);
5661 }
5662
5663 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5664 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5665 return i;
5666
5667# ifdef VBOX_STRICT
5668 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5669 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5670# endif
5671
5672#endif
5673
5674 return -1;
5675}
5676
5677/**
5678 * Handle unaligned register read operation.
5679 *
5680 * Looks up and calls appropriate handler.
5681 *
5682 * @returns VBox status code.
5683 *
5684 * @param pThis The device state structure.
5685 * @param offReg Register offset in memory-mapped frame.
5686 * @param pv Where to store the result.
5687 * @param cb Number of bytes to read.
5688 * @thread EMT
5689 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5690 * accesses we have to take care of that ourselves.
5691 */
5692static int e1kRegReadUnaligned(PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5693{
5694 uint32_t u32 = 0;
5695 uint32_t shift;
5696 int rc = VINF_SUCCESS;
5697 int index = e1kRegLookup(pThis, offReg);
5698#ifdef LOG_ENABLED
5699 char buf[9];
5700#endif
5701
5702 /*
5703 * From the spec:
5704 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
5705 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
5706 */
5707
5708 /*
5709 * To be able to read bytes and short word we convert them to properly
5710 * shifted 32-bit words and masks. The idea is to keep register-specific
5711 * handlers simple. Most accesses will be 32-bit anyway.
5712 */
5713 uint32_t mask;
5714 switch (cb)
5715 {
5716 case 4: mask = 0xFFFFFFFF; break;
5717 case 2: mask = 0x0000FFFF; break;
5718 case 1: mask = 0x000000FF; break;
5719 default:
5720 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5721 "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
5722 }
5723 if (index != -1)
5724 {
5725 if (g_aE1kRegMap[index].readable)
5726 {
5727 /* Make the mask correspond to the bits we are about to read. */
5728 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
5729 mask <<= shift;
5730 if (!mask)
5731 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
5732 /*
5733 * Read it. Pass the mask so the handler knows what has to be read.
5734 * Mask out irrelevant bits.
5735 */
5736 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5737 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5738 return rc;
5739 //pThis->fDelayInts = false;
5740 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5741 //pThis->iStatIntLostOne = 0;
5742 rc = g_aE1kRegMap[index].pfnRead(pThis, offReg & 0xFFFFFFFC, index, &u32);
5743 u32 &= mask;
5744 //e1kCsLeave(pThis);
5745 E1kLog2(("%s At %08X read %s from %s (%s)\n",
5746 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5747 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
5748 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5749 /* Shift back the result. */
5750 u32 >>= shift;
5751 }
5752 else
5753 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
5754 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5755 if (IOM_SUCCESS(rc))
5756 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
5757 }
5758 else
5759 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
5760 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
5761
5762 memcpy(pv, &u32, cb);
5763 return rc;
5764}
5765
5766/**
5767 * Handle 4 byte aligned and sized read operation.
5768 *
5769 * Looks up and calls appropriate handler.
5770 *
5771 * @returns VBox status code.
5772 *
5773 * @param pThis The device state structure.
5774 * @param offReg Register offset in memory-mapped frame.
5775 * @param pu32 Where to store the result.
5776 * @thread EMT
5777 */
5778static int e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
5779{
5780 Assert(!(offReg & 3));
5781
5782 /*
5783 * Lookup the register and check that it's readable.
5784 */
5785 int rc = VINF_SUCCESS;
5786 int idxReg = e1kRegLookup(pThis, offReg);
5787 if (RT_LIKELY(idxReg != -1))
5788 {
5789 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
5790 {
5791 /*
5792 * Read it. Pass the mask so the handler knows what has to be read.
5793 * Mask out irrelevant bits.
5794 */
5795 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5796 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5797 // return rc;
5798 //pThis->fDelayInts = false;
5799 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5800 //pThis->iStatIntLostOne = 0;
5801 rc = g_aE1kRegMap[idxReg].pfnRead(pThis, offReg & 0xFFFFFFFC, idxReg, pu32);
5802 //e1kCsLeave(pThis);
5803 Log6(("%s At %08X read %08X from %s (%s)\n",
5804 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5805 if (IOM_SUCCESS(rc))
5806 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
5807 }
5808 else
5809 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
5810 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5811 }
5812 else
5813 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
5814 return rc;
5815}
5816
5817/**
5818 * Handle 4 byte sized and aligned register write operation.
5819 *
5820 * Looks up and calls appropriate handler.
5821 *
5822 * @returns VBox status code.
5823 *
5824 * @param pThis The device state structure.
5825 * @param offReg Register offset in memory-mapped frame.
5826 * @param u32Value The value to write.
5827 * @thread EMT
5828 */
5829static int e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
5830{
5831 int rc = VINF_SUCCESS;
5832 int index = e1kRegLookup(pThis, offReg);
5833 if (RT_LIKELY(index != -1))
5834 {
5835 if (RT_LIKELY(g_aE1kRegMap[index].writable))
5836 {
5837 /*
5838 * Write it. Pass the mask so the handler knows what has to be written.
5839 * Mask out irrelevant bits.
5840 */
5841 Log6(("%s At %08X write %08X to %s (%s)\n",
5842 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5843 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5844 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5845 // return rc;
5846 //pThis->fDelayInts = false;
5847 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5848 //pThis->iStatIntLostOne = 0;
5849 rc = g_aE1kRegMap[index].pfnWrite(pThis, offReg, index, u32Value);
5850 //e1kCsLeave(pThis);
5851 }
5852 else
5853 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
5854 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5855 if (IOM_SUCCESS(rc))
5856 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
5857 }
5858 else
5859 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
5860 pThis->szPrf, offReg, u32Value));
5861 return rc;
5862}
5863
5864
5865/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
5866
5867/**
5868 * @callback_method_impl{FNIOMMMIOREAD}
5869 */
5870PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
5871{
5872 NOREF(pvUser);
5873 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5874 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5875
5876 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5877 Assert(offReg < E1K_MM_SIZE);
5878 Assert(cb == 4);
5879 Assert(!(GCPhysAddr & 3));
5880
5881 int rc = e1kRegReadAlignedU32(pThis, offReg, (uint32_t *)pv);
5882
5883 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5884 return rc;
5885}
5886
5887/**
5888 * @callback_method_impl{FNIOMMMIOWRITE}
5889 */
5890PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
5891{
5892 NOREF(pvUser);
5893 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5894 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5895
5896 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5897 Assert(offReg < E1K_MM_SIZE);
5898 Assert(cb == 4);
5899 Assert(!(GCPhysAddr & 3));
5900
5901 int rc = e1kRegWriteAlignedU32(pThis, offReg, *(uint32_t const *)pv);
5902
5903 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5904 return rc;
5905}
5906
5907/**
5908 * @callback_method_impl{FNIOMIOPORTIN}
5909 */
5910PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
5911{
5912 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5913 int rc;
5914 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
5915
5916 uPort -= pThis->IOPortBase;
5917 if (RT_LIKELY(cb == 4))
5918 switch (uPort)
5919 {
5920 case 0x00: /* IOADDR */
5921 *pu32 = pThis->uSelectedReg;
5922 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
5923 rc = VINF_SUCCESS;
5924 break;
5925
5926 case 0x04: /* IODATA */
5927 if (!(pThis->uSelectedReg & 3))
5928 rc = e1kRegReadAlignedU32(pThis, pThis->uSelectedReg, pu32);
5929 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
5930 rc = e1kRegReadUnaligned(pThis, pThis->uSelectedReg, pu32, cb);
5931 if (rc == VINF_IOM_R3_MMIO_READ)
5932 rc = VINF_IOM_R3_IOPORT_READ;
5933 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
5934 break;
5935
5936 default:
5937 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, uPort));
5938 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
5939 rc = VINF_SUCCESS;
5940 }
5941 else
5942 {
5943 E1kLog(("%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x", pThis->szPrf, uPort, cb));
5944 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb);
5945 }
5946 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
5947 return rc;
5948}
5949
5950
5951/**
5952 * @callback_method_impl{FNIOMIOPORTOUT}
5953 */
5954PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
5955{
5956 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5957 int rc;
5958 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
5959
5960 E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
5961 if (RT_LIKELY(cb == 4))
5962 {
5963 uPort -= pThis->IOPortBase;
5964 switch (uPort)
5965 {
5966 case 0x00: /* IOADDR */
5967 pThis->uSelectedReg = u32;
5968 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
5969 rc = VINF_SUCCESS;
5970 break;
5971
5972 case 0x04: /* IODATA */
5973 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
5974 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
5975 {
5976 rc = e1kRegWriteAlignedU32(pThis, pThis->uSelectedReg, u32);
5977 if (rc == VINF_IOM_R3_MMIO_WRITE)
5978 rc = VINF_IOM_R3_IOPORT_WRITE;
5979 }
5980 else
5981 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5982 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
5983 break;
5984
5985 default:
5986 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, uPort));
5987 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", uPort);
5988 }
5989 }
5990 else
5991 {
5992 E1kLog(("%s e1kIOPortOut: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb));
5993 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: uPort=%RTiop cb=%#x\n", pThis->szPrf, uPort, cb);
5994 }
5995
5996 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
5997 return rc;
5998}
5999
6000#ifdef IN_RING3
6001
6002/**
6003 * Dump complete device state to log.
6004 *
6005 * @param pThis Pointer to device state.
6006 */
6007static void e1kDumpState(PE1KSTATE pThis)
6008{
6009 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6010 {
6011 E1kLog2(("%s %8.8s = %08x\n", pThis->szPrf,
6012 g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6013 }
6014# ifdef E1K_INT_STATS
6015 LogRel(("%s Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6016 LogRel(("%s Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6017 LogRel(("%s Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6018 LogRel(("%s Interrupts delayed: %d\n", pThis->szPrf, pThis->uStatIntDly));
6019 LogRel(("%s Disabled delayed: %d\n", pThis->szPrf, pThis->uStatDisDly));
6020 LogRel(("%s Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6021 LogRel(("%s Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6022 LogRel(("%s Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6023 LogRel(("%s Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6024 LogRel(("%s Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6025 LogRel(("%s Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6026 LogRel(("%s Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6027 LogRel(("%s Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6028 LogRel(("%s Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6029 LogRel(("%s Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6030 LogRel(("%s Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6031 LogRel(("%s TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6032 LogRel(("%s TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6033 LogRel(("%s TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6034 LogRel(("%s TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6035 LogRel(("%s TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6036 LogRel(("%s TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6037 LogRel(("%s RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6038 LogRel(("%s RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6039 LogRel(("%s TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6040 LogRel(("%s TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6041 LogRel(("%s TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6042 LogRel(("%s Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6043 LogRel(("%s Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6044 LogRel(("%s TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6045 LogRel(("%s TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6046 LogRel(("%s TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6047 LogRel(("%s TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6048 LogRel(("%s TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6049 LogRel(("%s TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6050 LogRel(("%s TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6051 LogRel(("%s TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6052 LogRel(("%s Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6053 LogRel(("%s Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6054# endif /* E1K_INT_STATS */
6055}
6056
6057/**
6058 * @callback_method_impl{FNPCIIOREGIONMAP}
6059 */
6060static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
6061{
6062 PE1KSTATE pThis = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
6063 int rc;
6064
6065 switch (enmType)
6066 {
6067 case PCI_ADDRESS_SPACE_IO:
6068 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
6069 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
6070 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
6071 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6072 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
6073 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6074 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6075 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
6076 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6077 break;
6078
6079 case PCI_ADDRESS_SPACE_MEM:
6080 /*
6081 * From the spec:
6082 * For registers that should be accessed as 32-bit double words,
6083 * partial writes (less than a 32-bit double word) is ignored.
6084 * Partial reads return all 32 bits of data regardless of the
6085 * byte enables.
6086 */
6087 pThis->addrMMReg = GCPhysAddress; Assert(!(GCPhysAddress & 7));
6088 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
6089 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
6090 e1kMMIOWrite, e1kMMIORead, "E1000");
6091 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6092 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
6093 "e1kMMIOWrite", "e1kMMIORead");
6094 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6095 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
6096 "e1kMMIOWrite", "e1kMMIORead");
6097 break;
6098
6099 default:
6100 /* We should never get here */
6101 AssertMsgFailed(("Invalid PCI address space param in map callback"));
6102 rc = VERR_INTERNAL_ERROR;
6103 break;
6104 }
6105 return rc;
6106}
6107
6108
6109/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6110
6111/**
6112 * Check if the device can receive data now.
6113 * This must be called before the pfnRecieve() method is called.
6114 *
6115 * @returns Number of bytes the device can receive.
6116 * @param pInterface Pointer to the interface structure containing the called function pointer.
6117 * @thread EMT
6118 */
6119static int e1kCanReceive(PE1KSTATE pThis)
6120{
6121#ifndef E1K_WITH_RXD_CACHE
6122 size_t cb;
6123
6124 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6125 return VERR_NET_NO_BUFFER_SPACE;
6126
6127 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6128 {
6129 E1KRXDESC desc;
6130 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6131 &desc, sizeof(desc));
6132 if (desc.status.fDD)
6133 cb = 0;
6134 else
6135 cb = pThis->u16RxBSize;
6136 }
6137 else if (RDH < RDT)
6138 cb = (RDT - RDH) * pThis->u16RxBSize;
6139 else if (RDH > RDT)
6140 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6141 else
6142 {
6143 cb = 0;
6144 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6145 }
6146 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6147 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6148
6149 e1kCsRxLeave(pThis);
6150 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6151#else /* E1K_WITH_RXD_CACHE */
6152 int rc = VINF_SUCCESS;
6153
6154 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6155 return VERR_NET_NO_BUFFER_SPACE;
6156
6157 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6158 {
6159 E1KRXDESC desc;
6160 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6161 &desc, sizeof(desc));
6162 if (desc.status.fDD)
6163 rc = VERR_NET_NO_BUFFER_SPACE;
6164 }
6165 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6166 {
6167 /* Cache is empty, so is the RX ring. */
6168 rc = VERR_NET_NO_BUFFER_SPACE;
6169 }
6170 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6171 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6172 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6173
6174 e1kCsRxLeave(pThis);
6175 return rc;
6176#endif /* E1K_WITH_RXD_CACHE */
6177}
6178
6179/**
6180 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6181 */
6182static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6183{
6184 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6185 int rc = e1kCanReceive(pThis);
6186
6187 if (RT_SUCCESS(rc))
6188 return VINF_SUCCESS;
6189 if (RT_UNLIKELY(cMillies == 0))
6190 return VERR_NET_NO_BUFFER_SPACE;
6191
6192 rc = VERR_INTERRUPTED;
6193 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6194 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6195 VMSTATE enmVMState;
6196 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
6197 || enmVMState == VMSTATE_RUNNING_LS))
6198 {
6199 int rc2 = e1kCanReceive(pThis);
6200 if (RT_SUCCESS(rc2))
6201 {
6202 rc = VINF_SUCCESS;
6203 break;
6204 }
6205 E1kLogRel(("E1000 e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6206 E1kLog(("%s e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6207 RTSemEventWait(pThis->hEventMoreRxDescAvail, cMillies);
6208 }
6209 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6210 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6211
6212 return rc;
6213}
6214
6215
6216/**
6217 * Matches the packet addresses against Receive Address table. Looks for
6218 * exact matches only.
6219 *
6220 * @returns true if address matches.
6221 * @param pThis Pointer to the state structure.
6222 * @param pvBuf The ethernet packet.
6223 * @param cb Number of bytes available in the packet.
6224 * @thread EMT
6225 */
6226static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6227{
6228 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6229 {
6230 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6231
6232 /* Valid address? */
6233 if (ra->ctl & RA_CTL_AV)
6234 {
6235 Assert((ra->ctl & RA_CTL_AS) < 2);
6236 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6237 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6238 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6239 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6240 /*
6241 * Address Select:
6242 * 00b = Destination address
6243 * 01b = Source address
6244 * 10b = Reserved
6245 * 11b = Reserved
6246 * Since ethernet header is (DA, SA, len) we can use address
6247 * select as index.
6248 */
6249 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6250 ra->addr, sizeof(ra->addr)) == 0)
6251 return true;
6252 }
6253 }
6254
6255 return false;
6256}
6257
6258/**
6259 * Matches the packet addresses against Multicast Table Array.
6260 *
6261 * @remarks This is imperfect match since it matches not exact address but
6262 * a subset of addresses.
6263 *
6264 * @returns true if address matches.
6265 * @param pThis Pointer to the state structure.
6266 * @param pvBuf The ethernet packet.
6267 * @param cb Number of bytes available in the packet.
6268 * @thread EMT
6269 */
6270static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6271{
6272 /* Get bits 32..47 of destination address */
6273 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6274
6275 unsigned offset = GET_BITS(RCTL, MO);
6276 /*
6277 * offset means:
6278 * 00b = bits 36..47
6279 * 01b = bits 35..46
6280 * 10b = bits 34..45
6281 * 11b = bits 32..43
6282 */
6283 if (offset < 3)
6284 u16Bit = u16Bit >> (4 - offset);
6285 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6286}
6287
6288/**
6289 * Determines if the packet is to be delivered to upper layer.
6290 *
6291 * The following filters supported:
6292 * - Exact Unicast/Multicast
6293 * - Promiscuous Unicast/Multicast
6294 * - Multicast
6295 * - VLAN
6296 *
6297 * @returns true if packet is intended for this node.
6298 * @param pThis Pointer to the state structure.
6299 * @param pvBuf The ethernet packet.
6300 * @param cb Number of bytes available in the packet.
6301 * @param pStatus Bit field to store status bits.
6302 * @thread EMT
6303 */
6304static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6305{
6306 Assert(cb > 14);
6307 /* Assume that we fail to pass exact filter. */
6308 pStatus->fPIF = false;
6309 pStatus->fVP = false;
6310 /* Discard oversized packets */
6311 if (cb > E1K_MAX_RX_PKT_SIZE)
6312 {
6313 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6314 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6315 E1K_INC_CNT32(ROC);
6316 return false;
6317 }
6318 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6319 {
6320 /* When long packet reception is disabled packets over 1522 are discarded */
6321 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6322 pThis->szPrf, cb));
6323 E1K_INC_CNT32(ROC);
6324 return false;
6325 }
6326
6327 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6328 /* Compare TPID with VLAN Ether Type */
6329 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6330 {
6331 pStatus->fVP = true;
6332 /* Is VLAN filtering enabled? */
6333 if (RCTL & RCTL_VFE)
6334 {
6335 /* It is 802.1q packet indeed, let's filter by VID */
6336 if (RCTL & RCTL_CFIEN)
6337 {
6338 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6339 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6340 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6341 !!(RCTL & RCTL_CFI)));
6342 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6343 {
6344 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6345 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6346 return false;
6347 }
6348 }
6349 else
6350 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6351 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6352 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6353 {
6354 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6355 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6356 return false;
6357 }
6358 }
6359 }
6360 /* Broadcast filtering */
6361 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6362 return true;
6363 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6364 if (e1kIsMulticast(pvBuf))
6365 {
6366 /* Is multicast promiscuous enabled? */
6367 if (RCTL & RCTL_MPE)
6368 return true;
6369 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6370 /* Try perfect matches first */
6371 if (e1kPerfectMatch(pThis, pvBuf))
6372 {
6373 pStatus->fPIF = true;
6374 return true;
6375 }
6376 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6377 if (e1kImperfectMatch(pThis, pvBuf))
6378 return true;
6379 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6380 }
6381 else {
6382 /* Is unicast promiscuous enabled? */
6383 if (RCTL & RCTL_UPE)
6384 return true;
6385 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6386 if (e1kPerfectMatch(pThis, pvBuf))
6387 {
6388 pStatus->fPIF = true;
6389 return true;
6390 }
6391 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6392 }
6393 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6394 return false;
6395}
6396
6397/**
6398 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6399 */
6400static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6401{
6402 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6403 int rc = VINF_SUCCESS;
6404
6405 /*
6406 * Drop packets if the VM is not running yet/anymore.
6407 */
6408 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pThis));
6409 if ( enmVMState != VMSTATE_RUNNING
6410 && enmVMState != VMSTATE_RUNNING_LS)
6411 {
6412 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6413 return VINF_SUCCESS;
6414 }
6415
6416 /* Discard incoming packets in locked state */
6417 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6418 {
6419 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6420 return VINF_SUCCESS;
6421 }
6422
6423 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6424
6425 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6426 // return VERR_PERMISSION_DENIED;
6427
6428 e1kPacketDump(pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6429
6430 /* Update stats */
6431 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6432 {
6433 E1K_INC_CNT32(TPR);
6434 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6435 e1kCsLeave(pThis);
6436 }
6437 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6438 E1KRXDST status;
6439 RT_ZERO(status);
6440 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6441 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6442 if (fPassed)
6443 {
6444 rc = e1kHandleRxPacket(pThis, pvBuf, cb, status);
6445 }
6446 //e1kCsLeave(pThis);
6447 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6448
6449 return rc;
6450}
6451
6452
6453/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6454
6455/**
6456 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6457 */
6458static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6459{
6460 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
6461 int rc = VERR_PDM_LUN_NOT_FOUND;
6462
6463 if (iLUN == 0)
6464 {
6465 *ppLed = &pThis->led;
6466 rc = VINF_SUCCESS;
6467 }
6468 return rc;
6469}
6470
6471
6472/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6473
6474/**
6475 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6476 */
6477static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6478{
6479 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6480 pThis->eeprom.getMac(pMac);
6481 return VINF_SUCCESS;
6482}
6483
6484/**
6485 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6486 */
6487static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6488{
6489 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6490 if (STATUS & STATUS_LU)
6491 return PDMNETWORKLINKSTATE_UP;
6492 return PDMNETWORKLINKSTATE_DOWN;
6493}
6494
6495/**
6496 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6497 */
6498static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6499{
6500 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6501
6502 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6503 switch (enmState)
6504 {
6505 case PDMNETWORKLINKSTATE_UP:
6506 pThis->fCableConnected = true;
6507 /* If link was down, bring it up after a while. */
6508 if (!(STATUS & STATUS_LU))
6509 e1kBringLinkUpDelayed(pThis);
6510 break;
6511 case PDMNETWORKLINKSTATE_DOWN:
6512 pThis->fCableConnected = false;
6513 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6514 * We might have to set the link state before the driver initializes us. */
6515 Phy::setLinkStatus(&pThis->phy, false);
6516 /* If link was up, bring it down. */
6517 if (STATUS & STATUS_LU)
6518 e1kR3LinkDown(pThis);
6519 break;
6520 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6521 /*
6522 * There is not much sense in bringing down the link if it has not come up yet.
6523 * If it is up though, we bring it down temporarely, then bring it up again.
6524 */
6525 if (STATUS & STATUS_LU)
6526 e1kR3LinkDownTemp(pThis);
6527 break;
6528 default:
6529 ;
6530 }
6531 return VINF_SUCCESS;
6532}
6533
6534
6535/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6536
6537/**
6538 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6539 */
6540static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6541{
6542 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
6543 Assert(&pThis->IBase == pInterface);
6544
6545 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
6546 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
6547 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
6548 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
6549 return NULL;
6550}
6551
6552
6553/* -=-=-=-=- Saved State -=-=-=-=- */
6554
6555/**
6556 * Saves the configuration.
6557 *
6558 * @param pThis The E1K state.
6559 * @param pSSM The handle to the saved state.
6560 */
6561static void e1kSaveConfig(PE1KSTATE pThis, PSSMHANDLE pSSM)
6562{
6563 SSMR3PutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6564 SSMR3PutU32(pSSM, pThis->eChip);
6565}
6566
6567/**
6568 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6569 */
6570static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6571{
6572 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6573 e1kSaveConfig(pThis, pSSM);
6574 return VINF_SSM_DONT_CALL_AGAIN;
6575}
6576
6577/**
6578 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6579 */
6580static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6581{
6582 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6583
6584 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6585 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6586 return rc;
6587 e1kCsLeave(pThis);
6588 return VINF_SUCCESS;
6589#if 0
6590 /* 1) Prevent all threads from modifying the state and memory */
6591 //pThis->fLocked = true;
6592 /* 2) Cancel all timers */
6593#ifdef E1K_TX_DELAY
6594 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6595#endif /* E1K_TX_DELAY */
6596#ifdef E1K_USE_TX_TIMERS
6597 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6598#ifndef E1K_NO_TAD
6599 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6600#endif /* E1K_NO_TAD */
6601#endif /* E1K_USE_TX_TIMERS */
6602#ifdef E1K_USE_RX_TIMERS
6603 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6604 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6605#endif /* E1K_USE_RX_TIMERS */
6606 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6607 /* 3) Did I forget anything? */
6608 E1kLog(("%s Locked\n", pThis->szPrf));
6609 return VINF_SUCCESS;
6610#endif
6611}
6612
6613/**
6614 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6615 */
6616static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6617{
6618 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6619
6620 e1kSaveConfig(pThis, pSSM);
6621 pThis->eeprom.save(pSSM);
6622 e1kDumpState(pThis);
6623 SSMR3PutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6624 SSMR3PutBool(pSSM, pThis->fIntRaised);
6625 Phy::saveState(pSSM, &pThis->phy);
6626 SSMR3PutU32(pSSM, pThis->uSelectedReg);
6627 SSMR3PutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6628 SSMR3PutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6629 SSMR3PutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6630 SSMR3PutU64(pSSM, pThis->u64AckedAt);
6631 SSMR3PutU16(pSSM, pThis->u16RxBSize);
6632 //SSMR3PutBool(pSSM, pThis->fDelayInts);
6633 //SSMR3PutBool(pSSM, pThis->fIntMaskUsed);
6634 SSMR3PutU16(pSSM, pThis->u16TxPktLen);
6635/** @todo State wrt to the TSE buffer is incomplete, so little point in
6636 * saving this actually. */
6637 SSMR3PutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6638 SSMR3PutBool(pSSM, pThis->fIPcsum);
6639 SSMR3PutBool(pSSM, pThis->fTCPcsum);
6640 SSMR3PutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6641 SSMR3PutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6642 SSMR3PutBool(pSSM, pThis->fVTag);
6643 SSMR3PutU16(pSSM, pThis->u16VTagTCI);
6644#ifdef E1K_WITH_TXD_CACHE
6645#if 0
6646 SSMR3PutU8(pSSM, pThis->nTxDFetched);
6647 SSMR3PutMem(pSSM, pThis->aTxDescriptors,
6648 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6649#else
6650 /*
6651 * There is no point in storing TX descriptor cache entries as we can simply
6652 * fetch them again. Moreover, normally the cache is always empty when we
6653 * save the state. Store zero entries for compatibility.
6654 */
6655 SSMR3PutU8(pSSM, 0);
6656#endif
6657#endif /* E1K_WITH_TXD_CACHE */
6658/**@todo GSO requires some more state here. */
6659 E1kLog(("%s State has been saved\n", pThis->szPrf));
6660 return VINF_SUCCESS;
6661}
6662
6663#if 0
6664/**
6665 * @callback_method_impl{FNSSMDEVSAVEDONE}
6666 */
6667static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6668{
6669 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6670
6671 /* If VM is being powered off unlocking will result in assertions in PGM */
6672 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6673 pThis->fLocked = false;
6674 else
6675 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6676 E1kLog(("%s Unlocked\n", pThis->szPrf));
6677 return VINF_SUCCESS;
6678}
6679#endif
6680
6681/**
6682 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6683 */
6684static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6685{
6686 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6687
6688 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6689 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6690 return rc;
6691 e1kCsLeave(pThis);
6692 return VINF_SUCCESS;
6693}
6694
6695/**
6696 * @callback_method_impl{FNSSMDEVLOADEXEC}
6697 */
6698static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6699{
6700 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6701 int rc;
6702
6703 if ( uVersion != E1K_SAVEDSTATE_VERSION
6704#ifdef E1K_WITH_TXD_CACHE
6705 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6706#endif /* E1K_WITH_TXD_CACHE */
6707 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6708 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6709 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6710
6711 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6712 || uPass != SSM_PASS_FINAL)
6713 {
6714 /* config checks */
6715 RTMAC macConfigured;
6716 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
6717 AssertRCReturn(rc, rc);
6718 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6719 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6720 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6721
6722 E1KCHIP eChip;
6723 rc = SSMR3GetU32(pSSM, &eChip);
6724 AssertRCReturn(rc, rc);
6725 if (eChip != pThis->eChip)
6726 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6727 }
6728
6729 if (uPass == SSM_PASS_FINAL)
6730 {
6731 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6732 {
6733 rc = pThis->eeprom.load(pSSM);
6734 AssertRCReturn(rc, rc);
6735 }
6736 /* the state */
6737 SSMR3GetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
6738 SSMR3GetBool(pSSM, &pThis->fIntRaised);
6739 /** @todo: PHY could be made a separate device with its own versioning */
6740 Phy::loadState(pSSM, &pThis->phy);
6741 SSMR3GetU32(pSSM, &pThis->uSelectedReg);
6742 SSMR3GetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
6743 SSMR3GetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6744 SSMR3GetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
6745 SSMR3GetU64(pSSM, &pThis->u64AckedAt);
6746 SSMR3GetU16(pSSM, &pThis->u16RxBSize);
6747 //SSMR3GetBool(pSSM, pThis->fDelayInts);
6748 //SSMR3GetBool(pSSM, pThis->fIntMaskUsed);
6749 SSMR3GetU16(pSSM, &pThis->u16TxPktLen);
6750 SSMR3GetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
6751 SSMR3GetBool(pSSM, &pThis->fIPcsum);
6752 SSMR3GetBool(pSSM, &pThis->fTCPcsum);
6753 SSMR3GetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6754 rc = SSMR3GetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6755 AssertRCReturn(rc, rc);
6756 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
6757 {
6758 SSMR3GetBool(pSSM, &pThis->fVTag);
6759 rc = SSMR3GetU16(pSSM, &pThis->u16VTagTCI);
6760 AssertRCReturn(rc, rc);
6761 }
6762 else
6763 {
6764 pThis->fVTag = false;
6765 pThis->u16VTagTCI = 0;
6766 }
6767#ifdef E1K_WITH_TXD_CACHE
6768 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
6769 {
6770 rc = SSMR3GetU8(pSSM, &pThis->nTxDFetched);
6771 AssertRCReturn(rc, rc);
6772 if (pThis->nTxDFetched)
6773 SSMR3GetMem(pSSM, pThis->aTxDescriptors,
6774 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6775 }
6776 else
6777 pThis->nTxDFetched = 0;
6778 /*
6779 * @todo: Perhaps we should not store TXD cache as the entries can be
6780 * simply fetched again from guest's memory. Or can't they?
6781 */
6782#endif /* E1K_WITH_TXD_CACHE */
6783#ifdef E1K_WITH_RXD_CACHE
6784 /*
6785 * There is no point in storing the RX descriptor cache in the saved
6786 * state, we just need to make sure it is empty.
6787 */
6788 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
6789#endif /* E1K_WITH_RXD_CACHE */
6790 /* derived state */
6791 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
6792
6793 E1kLog(("%s State has been restored\n", pThis->szPrf));
6794 e1kDumpState(pThis);
6795 }
6796 return VINF_SUCCESS;
6797}
6798
6799/**
6800 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
6801 */
6802static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6803{
6804 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6805
6806 /* Update promiscuous mode */
6807 if (pThis->pDrvR3)
6808 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3,
6809 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
6810
6811 /*
6812 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
6813 * passed to us. We go through all this stuff if the link was up and we
6814 * wasn't teleported.
6815 */
6816 if ( (STATUS & STATUS_LU)
6817 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
6818 && pThis->cMsLinkUpDelay)
6819 {
6820 e1kR3LinkDownTemp(pThis);
6821 }
6822 return VINF_SUCCESS;
6823}
6824
6825
6826
6827/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
6828
6829/**
6830 * @callback_method_impl{FNRTSTRFORMATTYPE}
6831 */
6832static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
6833 void *pvArgOutput,
6834 const char *pszType,
6835 void const *pvValue,
6836 int cchWidth,
6837 int cchPrecision,
6838 unsigned fFlags,
6839 void *pvUser)
6840{
6841 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
6842 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
6843 if (!pDesc)
6844 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
6845
6846 size_t cbPrintf = 0;
6847 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
6848 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
6849 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
6850 pDesc->status.fPIF ? "PIF" : "pif",
6851 pDesc->status.fIPCS ? "IPCS" : "ipcs",
6852 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
6853 pDesc->status.fVP ? "VP" : "vp",
6854 pDesc->status.fIXSM ? "IXSM" : "ixsm",
6855 pDesc->status.fEOP ? "EOP" : "eop",
6856 pDesc->status.fDD ? "DD" : "dd",
6857 pDesc->status.fRXE ? "RXE" : "rxe",
6858 pDesc->status.fIPE ? "IPE" : "ipe",
6859 pDesc->status.fTCPE ? "TCPE" : "tcpe",
6860 pDesc->status.fCE ? "CE" : "ce",
6861 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
6862 E1K_SPEC_VLAN(pDesc->status.u16Special),
6863 E1K_SPEC_PRI(pDesc->status.u16Special));
6864 return cbPrintf;
6865}
6866
6867/**
6868 * @callback_method_impl{FNRTSTRFORMATTYPE}
6869 */
6870static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
6871 void *pvArgOutput,
6872 const char *pszType,
6873 void const *pvValue,
6874 int cchWidth,
6875 int cchPrecision,
6876 unsigned fFlags,
6877 void *pvUser)
6878{
6879 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
6880 E1KTXDESC* pDesc = (E1KTXDESC*)pvValue;
6881 if (!pDesc)
6882 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
6883
6884 size_t cbPrintf = 0;
6885 switch (e1kGetDescType(pDesc))
6886 {
6887 case E1K_DTYP_CONTEXT:
6888 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
6889 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
6890 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
6891 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
6892 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
6893 pDesc->context.dw2.fIDE ? " IDE":"",
6894 pDesc->context.dw2.fRS ? " RS" :"",
6895 pDesc->context.dw2.fTSE ? " TSE":"",
6896 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
6897 pDesc->context.dw2.fTCP ? "TCP":"UDP",
6898 pDesc->context.dw2.u20PAYLEN,
6899 pDesc->context.dw3.u8HDRLEN,
6900 pDesc->context.dw3.u16MSS,
6901 pDesc->context.dw3.fDD?"DD":"");
6902 break;
6903 case E1K_DTYP_DATA:
6904 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
6905 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
6906 pDesc->data.u64BufAddr,
6907 pDesc->data.cmd.u20DTALEN,
6908 pDesc->data.cmd.fIDE ? " IDE" :"",
6909 pDesc->data.cmd.fVLE ? " VLE" :"",
6910 pDesc->data.cmd.fRPS ? " RPS" :"",
6911 pDesc->data.cmd.fRS ? " RS" :"",
6912 pDesc->data.cmd.fTSE ? " TSE" :"",
6913 pDesc->data.cmd.fIFCS? " IFCS":"",
6914 pDesc->data.cmd.fEOP ? " EOP" :"",
6915 pDesc->data.dw3.fDD ? " DD" :"",
6916 pDesc->data.dw3.fEC ? " EC" :"",
6917 pDesc->data.dw3.fLC ? " LC" :"",
6918 pDesc->data.dw3.fTXSM? " TXSM":"",
6919 pDesc->data.dw3.fIXSM? " IXSM":"",
6920 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
6921 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
6922 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
6923 break;
6924 case E1K_DTYP_LEGACY:
6925 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
6926 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
6927 pDesc->data.u64BufAddr,
6928 pDesc->legacy.cmd.u16Length,
6929 pDesc->legacy.cmd.fIDE ? " IDE" :"",
6930 pDesc->legacy.cmd.fVLE ? " VLE" :"",
6931 pDesc->legacy.cmd.fRPS ? " RPS" :"",
6932 pDesc->legacy.cmd.fRS ? " RS" :"",
6933 pDesc->legacy.cmd.fIC ? " IC" :"",
6934 pDesc->legacy.cmd.fIFCS? " IFCS":"",
6935 pDesc->legacy.cmd.fEOP ? " EOP" :"",
6936 pDesc->legacy.dw3.fDD ? " DD" :"",
6937 pDesc->legacy.dw3.fEC ? " EC" :"",
6938 pDesc->legacy.dw3.fLC ? " LC" :"",
6939 pDesc->legacy.cmd.u8CSO,
6940 pDesc->legacy.dw3.u8CSS,
6941 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
6942 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
6943 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
6944 break;
6945 default:
6946 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
6947 break;
6948 }
6949
6950 return cbPrintf;
6951}
6952
6953/** Initializes debug helpers (logging format types). */
6954static int e1kInitDebugHelpers(void)
6955{
6956 int rc = VINF_SUCCESS;
6957 static bool s_fHelpersRegistered = false;
6958 if (!s_fHelpersRegistered)
6959 {
6960 s_fHelpersRegistered = true;
6961 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
6962 AssertRCReturn(rc, rc);
6963 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
6964 AssertRCReturn(rc, rc);
6965 }
6966 return rc;
6967}
6968
6969/**
6970 * Status info callback.
6971 *
6972 * @param pDevIns The device instance.
6973 * @param pHlp The output helpers.
6974 * @param pszArgs The arguments.
6975 */
6976static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6977{
6978 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6979 unsigned i;
6980 // bool fRcvRing = false;
6981 // bool fXmtRing = false;
6982
6983 /*
6984 * Parse args.
6985 if (pszArgs)
6986 {
6987 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
6988 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
6989 }
6990 */
6991
6992 /*
6993 * Show info.
6994 */
6995 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
6996 pDevIns->iInstance, pThis->IOPortBase, pThis->addrMMReg,
6997 &pThis->macConfigured, g_Chips[pThis->eChip].pcszName,
6998 pThis->fRCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
6999
7000 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7001
7002 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7003 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7004
7005 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7006 {
7007 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7008 if (ra->ctl & RA_CTL_AV)
7009 {
7010 const char *pcszTmp;
7011 switch (ra->ctl & RA_CTL_AS)
7012 {
7013 case 0: pcszTmp = "DST"; break;
7014 case 1: pcszTmp = "SRC"; break;
7015 default: pcszTmp = "reserved";
7016 }
7017 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7018 }
7019 }
7020 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7021 uint32_t rdh = RDH;
7022 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7023 for (i = 0; i < cDescs; ++i)
7024 {
7025 E1KRXDESC desc;
7026 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7027 &desc, sizeof(desc));
7028 if (i == rdh)
7029 pHlp->pfnPrintf(pHlp, ">>> ");
7030 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7031 }
7032#ifdef E1K_WITH_RXD_CACHE
7033 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7034 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7035 if (rdh > pThis->iRxDCurrent)
7036 rdh -= pThis->iRxDCurrent;
7037 else
7038 rdh = cDescs + rdh - pThis->iRxDCurrent;
7039 for (i = 0; i < pThis->nRxDFetched; ++i)
7040 {
7041 if (i == pThis->iRxDCurrent)
7042 pHlp->pfnPrintf(pHlp, ">>> ");
7043 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7044 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7045 &pThis->aRxDescriptors[i]);
7046 }
7047#endif /* E1K_WITH_RXD_CACHE */
7048
7049 cDescs = TDLEN / sizeof(E1KTXDESC);
7050 uint32_t tdh = TDH;
7051 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7052 for (i = 0; i < cDescs; ++i)
7053 {
7054 E1KTXDESC desc;
7055 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7056 &desc, sizeof(desc));
7057 if (i == tdh)
7058 pHlp->pfnPrintf(pHlp, ">>> ");
7059 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7060 }
7061#ifdef E1K_WITH_TXD_CACHE
7062 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7063 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7064 if (tdh > pThis->iTxDCurrent)
7065 tdh -= pThis->iTxDCurrent;
7066 else
7067 tdh = cDescs + tdh - pThis->iTxDCurrent;
7068 for (i = 0; i < pThis->nTxDFetched; ++i)
7069 {
7070 if (i == pThis->iTxDCurrent)
7071 pHlp->pfnPrintf(pHlp, ">>> ");
7072 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7073 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7074 &pThis->aTxDescriptors[i]);
7075 }
7076#endif /* E1K_WITH_TXD_CACHE */
7077
7078
7079#ifdef E1K_INT_STATS
7080 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7081 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7082 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7083 pHlp->pfnPrintf(pHlp, "Interrupts delayed: %d\n", pThis->uStatIntDly);
7084 pHlp->pfnPrintf(pHlp, "Disabled delayed: %d\n", pThis->uStatDisDly);
7085 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7086 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7087 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7088 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7089 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7090 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7091 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7092 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7093 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7094 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7095 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7096 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7097 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7098 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7099 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7100 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7101 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7102 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7103 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7104 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7105 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7106 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7107 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7108 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7109 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7110 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7111 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7112 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7113 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7114 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7115 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7116 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7117 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7118#endif /* E1K_INT_STATS */
7119
7120 e1kCsLeave(pThis);
7121}
7122
7123
7124
7125/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7126
7127/**
7128 * Detach notification.
7129 *
7130 * One port on the network card has been disconnected from the network.
7131 *
7132 * @param pDevIns The device instance.
7133 * @param iLUN The logical unit which is being detached.
7134 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7135 */
7136static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7137{
7138 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7139 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7140
7141 AssertLogRelReturnVoid(iLUN == 0);
7142
7143 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7144
7145 /** @todo: r=pritesh still need to check if i missed
7146 * to clean something in this function
7147 */
7148
7149 /*
7150 * Zero some important members.
7151 */
7152 pThis->pDrvBase = NULL;
7153 pThis->pDrvR3 = NULL;
7154 pThis->pDrvR0 = NIL_RTR0PTR;
7155 pThis->pDrvRC = NIL_RTRCPTR;
7156
7157 PDMCritSectLeave(&pThis->cs);
7158}
7159
7160/**
7161 * Attach the Network attachment.
7162 *
7163 * One port on the network card has been connected to a network.
7164 *
7165 * @returns VBox status code.
7166 * @param pDevIns The device instance.
7167 * @param iLUN The logical unit which is being attached.
7168 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7169 *
7170 * @remarks This code path is not used during construction.
7171 */
7172static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7173{
7174 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7175 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7176
7177 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7178
7179 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7180
7181 /*
7182 * Attach the driver.
7183 */
7184 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7185 if (RT_SUCCESS(rc))
7186 {
7187 if (rc == VINF_NAT_DNS)
7188 {
7189#ifdef RT_OS_LINUX
7190 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7191 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7192#else
7193 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7194 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7195#endif
7196 }
7197 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7198 AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7199 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7200 if (RT_SUCCESS(rc))
7201 {
7202 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0);
7203 pThis->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7204
7205 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC);
7206 pThis->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7207 }
7208 }
7209 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7210 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7211 {
7212 /* This should never happen because this function is not called
7213 * if there is no driver to attach! */
7214 Log(("%s No attached driver!\n", pThis->szPrf));
7215 }
7216
7217 /*
7218 * Temporary set the link down if it was up so that the guest
7219 * will know that we have change the configuration of the
7220 * network card
7221 */
7222 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7223 e1kR3LinkDownTemp(pThis);
7224
7225 PDMCritSectLeave(&pThis->cs);
7226 return rc;
7227
7228}
7229
7230/**
7231 * @copydoc FNPDMDEVPOWEROFF
7232 */
7233static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7234{
7235 /* Poke thread waiting for buffer space. */
7236 e1kWakeupReceive(pDevIns);
7237}
7238
7239/**
7240 * @copydoc FNPDMDEVRESET
7241 */
7242static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7243{
7244 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7245#ifdef E1K_TX_DELAY
7246 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7247#endif /* E1K_TX_DELAY */
7248 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7249 e1kCancelTimer(pThis, pThis->CTX_SUFF(pLUTimer));
7250 e1kXmitFreeBuf(pThis);
7251 pThis->u16TxPktLen = 0;
7252 pThis->fIPcsum = false;
7253 pThis->fTCPcsum = false;
7254 pThis->fIntMaskUsed = false;
7255 pThis->fDelayInts = false;
7256 pThis->fLocked = false;
7257 pThis->u64AckedAt = 0;
7258 e1kHardReset(pThis);
7259}
7260
7261/**
7262 * @copydoc FNPDMDEVSUSPEND
7263 */
7264static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7265{
7266 /* Poke thread waiting for buffer space. */
7267 e1kWakeupReceive(pDevIns);
7268}
7269
7270/**
7271 * Device relocation callback.
7272 *
7273 * When this callback is called the device instance data, and if the
7274 * device have a GC component, is being relocated, or/and the selectors
7275 * have been changed. The device must use the chance to perform the
7276 * necessary pointer relocations and data updates.
7277 *
7278 * Before the GC code is executed the first time, this function will be
7279 * called with a 0 delta so GC pointer calculations can be one in one place.
7280 *
7281 * @param pDevIns Pointer to the device instance.
7282 * @param offDelta The relocation delta relative to the old location.
7283 *
7284 * @remark A relocation CANNOT fail.
7285 */
7286static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7287{
7288 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7289 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7290 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7291 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7292#ifdef E1K_USE_RX_TIMERS
7293 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7294 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7295#endif /* E1K_USE_RX_TIMERS */
7296#ifdef E1K_USE_TX_TIMERS
7297 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7298# ifndef E1K_NO_TAD
7299 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7300# endif /* E1K_NO_TAD */
7301#endif /* E1K_USE_TX_TIMERS */
7302#ifdef E1K_TX_DELAY
7303 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7304#endif /* E1K_TX_DELAY */
7305 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7306 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7307}
7308
7309/**
7310 * Destruct a device instance.
7311 *
7312 * We need to free non-VM resources only.
7313 *
7314 * @returns VBox status code.
7315 * @param pDevIns The device instance data.
7316 * @thread EMT
7317 */
7318static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7319{
7320 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7321 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7322
7323 e1kDumpState(pThis);
7324 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7325 if (PDMCritSectIsInitialized(&pThis->cs))
7326 {
7327 if (pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
7328 {
7329 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
7330 RTSemEventDestroy(pThis->hEventMoreRxDescAvail);
7331 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7332 }
7333#ifdef E1K_WITH_TX_CS
7334 PDMR3CritSectDelete(&pThis->csTx);
7335#endif /* E1K_WITH_TX_CS */
7336 PDMR3CritSectDelete(&pThis->csRx);
7337 PDMR3CritSectDelete(&pThis->cs);
7338 }
7339 return VINF_SUCCESS;
7340}
7341
7342
7343/**
7344 * Set PCI configuration space registers.
7345 *
7346 * @param pci Reference to PCI device structure.
7347 * @thread EMT
7348 */
7349static DECLCALLBACK(void) e1kConfigurePciDev(PPCIDEVICE pPciDev, E1KCHIP eChip)
7350{
7351 Assert(eChip < RT_ELEMENTS(g_Chips));
7352 /* Configure PCI Device, assume 32-bit mode ******************************/
7353 PCIDevSetVendorId(pPciDev, g_Chips[eChip].uPCIVendorId);
7354 PCIDevSetDeviceId(pPciDev, g_Chips[eChip].uPCIDeviceId);
7355 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
7356 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
7357
7358 PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7359 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7360 PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
7361 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7362 /* Stepping A2 */
7363 PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7364 /* Ethernet adapter */
7365 PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7366 PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7367 /* normal single function Ethernet controller */
7368 PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7369 /* Memory Register Base Address */
7370 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7371 /* Memory Flash Base Address */
7372 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7373 /* IO Register Base Address */
7374 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7375 /* Expansion ROM Base Address */
7376 PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7377 /* Capabilities Pointer */
7378 PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7379 /* Interrupt Pin: INTA# */
7380 PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7381 /* Max_Lat/Min_Gnt: very high priority and time slice */
7382 PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7383 PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7384
7385 /* PCI Power Management Registers ****************************************/
7386 /* Capability ID: PCI Power Management Registers */
7387 PCIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7388 /* Next Item Pointer: PCI-X */
7389 PCIDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7390 /* Power Management Capabilities: PM disabled, DSI */
7391 PCIDevSetWord( pPciDev, 0xDC + 2,
7392 0x0002 | VBOX_PCI_PM_CAP_DSI);
7393 /* Power Management Control / Status Register: PM disabled */
7394 PCIDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7395 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7396 PCIDevSetByte( pPciDev, 0xDC + 6, 0x00);
7397 /* Data Register: PM disabled, always 0 */
7398 PCIDevSetByte( pPciDev, 0xDC + 7, 0x00);
7399
7400 /* PCI-X Configuration Registers *****************************************/
7401 /* Capability ID: PCI-X Configuration Registers */
7402 PCIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7403#ifdef E1K_WITH_MSI
7404 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7405#else
7406 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7407 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7408#endif
7409 /* PCI-X Command: Enable Relaxed Ordering */
7410 PCIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7411 /* PCI-X Status: 32-bit, 66MHz*/
7412 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7413 PCIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7414}
7415
7416/**
7417 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7418 */
7419static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7420{
7421 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7422 int rc;
7423 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7424
7425 /*
7426 * Initialize the instance data (state).
7427 * Note! Caller has initialized it to ZERO already.
7428 */
7429 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7430 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7431 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7432 pThis->pDevInsR3 = pDevIns;
7433 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7434 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7435 pThis->u16TxPktLen = 0;
7436 pThis->fIPcsum = false;
7437 pThis->fTCPcsum = false;
7438 pThis->fIntMaskUsed = false;
7439 pThis->fDelayInts = false;
7440 pThis->fLocked = false;
7441 pThis->u64AckedAt = 0;
7442 pThis->led.u32Magic = PDMLED_MAGIC;
7443 pThis->u32PktNo = 1;
7444
7445 /* Interfaces */
7446 pThis->IBase.pfnQueryInterface = e1kR3QueryInterface;
7447
7448 pThis->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7449 pThis->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7450 pThis->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7451
7452 pThis->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7453
7454 pThis->INetworkConfig.pfnGetMac = e1kR3GetMac;
7455 pThis->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7456 pThis->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7457
7458 /*
7459 * Internal validations.
7460 */
7461 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7462 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7463 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7464 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7465 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7466 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7467 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7468 VERR_INTERNAL_ERROR_4);
7469
7470 /*
7471 * Validate configuration.
7472 */
7473 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0"
7474 "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"
7475 "EthernetCRC\0" "GSOEnabled\0" "LinkUpDelay\0"))
7476 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7477 N_("Invalid configuration for E1000 device"));
7478
7479 /** @todo: LineSpeed unused! */
7480
7481 pThis->fR0Enabled = true;
7482 pThis->fRCEnabled = true;
7483 pThis->fEthernetCRC = true;
7484 pThis->fGSOEnabled = true;
7485
7486 /* Get config params */
7487 rc = CFGMR3QueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7488 if (RT_FAILURE(rc))
7489 return PDMDEV_SET_ERROR(pDevIns, rc,
7490 N_("Configuration error: Failed to get MAC address"));
7491 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7492 if (RT_FAILURE(rc))
7493 return PDMDEV_SET_ERROR(pDevIns, rc,
7494 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7495 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7496 if (RT_FAILURE(rc))
7497 return PDMDEV_SET_ERROR(pDevIns, rc,
7498 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7499 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7500 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fRCEnabled, true);
7501 if (RT_FAILURE(rc))
7502 return PDMDEV_SET_ERROR(pDevIns, rc,
7503 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
7504
7505 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
7506 if (RT_FAILURE(rc))
7507 return PDMDEV_SET_ERROR(pDevIns, rc,
7508 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
7509
7510 rc = CFGMR3QueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7511 if (RT_FAILURE(rc))
7512 return PDMDEV_SET_ERROR(pDevIns, rc,
7513 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7514
7515 rc = CFGMR3QueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7516 if (RT_FAILURE(rc))
7517 return PDMDEV_SET_ERROR(pDevIns, rc,
7518 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7519
7520 rc = CFGMR3QueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 5000); /* ms */
7521 if (RT_FAILURE(rc))
7522 return PDMDEV_SET_ERROR(pDevIns, rc,
7523 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7524 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7525 if (pThis->cMsLinkUpDelay > 5000)
7526 LogRel(("%s WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7527 else if (pThis->cMsLinkUpDelay == 0)
7528 LogRel(("%s WARNING! Link up delay is disabled!\n", pThis->szPrf));
7529
7530 E1kLog(("%s Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s R0=%s GC=%s\n", pThis->szPrf,
7531 g_Chips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7532 pThis->fEthernetCRC ? "on" : "off",
7533 pThis->fGSOEnabled ? "enabled" : "disabled",
7534 pThis->fR0Enabled ? "enabled" : "disabled",
7535 pThis->fRCEnabled ? "enabled" : "disabled"));
7536
7537 /* Initialize the EEPROM. */
7538 pThis->eeprom.init(pThis->macConfigured);
7539
7540 /* Initialize internal PHY. */
7541 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7542 Phy::setLinkStatus(&pThis->phy, pThis->fCableConnected);
7543
7544 /* Initialize critical sections. We do our own locking. */
7545 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7546 AssertRCReturn(rc, rc);
7547
7548 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7549 if (RT_FAILURE(rc))
7550 return rc;
7551 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7552 if (RT_FAILURE(rc))
7553 return rc;
7554#ifdef E1K_WITH_TX_CS
7555 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7556 if (RT_FAILURE(rc))
7557 return rc;
7558#endif /* E1K_WITH_TX_CS */
7559
7560 /* Saved state registration. */
7561 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7562 NULL, e1kLiveExec, NULL,
7563 e1kSavePrep, e1kSaveExec, NULL,
7564 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7565 if (RT_FAILURE(rc))
7566 return rc;
7567
7568 /* Set PCI config registers and register ourselves with the PCI bus. */
7569 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip);
7570 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice);
7571 if (RT_FAILURE(rc))
7572 return rc;
7573
7574#ifdef E1K_WITH_MSI
7575 PDMMSIREG MsiReg;
7576 RT_ZERO(MsiReg);
7577 MsiReg.cMsiVectors = 1;
7578 MsiReg.iMsiCapOffset = 0x80;
7579 MsiReg.iMsiNextOffset = 0x0;
7580 MsiReg.fMsi64bit = false;
7581 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7582 AssertRCReturn(rc, rc);
7583#endif
7584
7585
7586 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
7587 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, e1kMap);
7588 if (RT_FAILURE(rc))
7589 return rc;
7590 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
7591 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE, PCI_ADDRESS_SPACE_IO, e1kMap);
7592 if (RT_FAILURE(rc))
7593 return rc;
7594
7595 /* Create transmit queue */
7596 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7597 e1kTxQueueConsumer, true, "E1000-Xmit", &pThis->pTxQueueR3);
7598 if (RT_FAILURE(rc))
7599 return rc;
7600 pThis->pTxQueueR0 = PDMQueueR0Ptr(pThis->pTxQueueR3);
7601 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7602
7603 /* Create the RX notifier signaller. */
7604 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7605 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pThis->pCanRxQueueR3);
7606 if (RT_FAILURE(rc))
7607 return rc;
7608 pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
7609 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7610
7611#ifdef E1K_TX_DELAY
7612 /* Create Transmit Delay Timer */
7613 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxDelayTimer, pThis,
7614 TMTIMER_FLAGS_NO_CRIT_SECT,
7615 "E1000 Transmit Delay Timer", &pThis->pTXDTimerR3);
7616 if (RT_FAILURE(rc))
7617 return rc;
7618 pThis->pTXDTimerR0 = TMTimerR0Ptr(pThis->pTXDTimerR3);
7619 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7620 TMR3TimerSetCritSect(pThis->pTXDTimerR3, &pThis->csTx);
7621#endif /* E1K_TX_DELAY */
7622
7623#ifdef E1K_USE_TX_TIMERS
7624 /* Create Transmit Interrupt Delay Timer */
7625 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pThis,
7626 TMTIMER_FLAGS_NO_CRIT_SECT,
7627 "E1000 Transmit Interrupt Delay Timer", &pThis->pTIDTimerR3);
7628 if (RT_FAILURE(rc))
7629 return rc;
7630 pThis->pTIDTimerR0 = TMTimerR0Ptr(pThis->pTIDTimerR3);
7631 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7632
7633# ifndef E1K_NO_TAD
7634 /* Create Transmit Absolute Delay Timer */
7635 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pThis,
7636 TMTIMER_FLAGS_NO_CRIT_SECT,
7637 "E1000 Transmit Absolute Delay Timer", &pThis->pTADTimerR3);
7638 if (RT_FAILURE(rc))
7639 return rc;
7640 pThis->pTADTimerR0 = TMTimerR0Ptr(pThis->pTADTimerR3);
7641 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7642# endif /* E1K_NO_TAD */
7643#endif /* E1K_USE_TX_TIMERS */
7644
7645#ifdef E1K_USE_RX_TIMERS
7646 /* Create Receive Interrupt Delay Timer */
7647 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pThis,
7648 TMTIMER_FLAGS_NO_CRIT_SECT,
7649 "E1000 Receive Interrupt Delay Timer", &pThis->pRIDTimerR3);
7650 if (RT_FAILURE(rc))
7651 return rc;
7652 pThis->pRIDTimerR0 = TMTimerR0Ptr(pThis->pRIDTimerR3);
7653 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7654
7655 /* Create Receive Absolute Delay Timer */
7656 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pThis,
7657 TMTIMER_FLAGS_NO_CRIT_SECT,
7658 "E1000 Receive Absolute Delay Timer", &pThis->pRADTimerR3);
7659 if (RT_FAILURE(rc))
7660 return rc;
7661 pThis->pRADTimerR0 = TMTimerR0Ptr(pThis->pRADTimerR3);
7662 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7663#endif /* E1K_USE_RX_TIMERS */
7664
7665 /* Create Late Interrupt Timer */
7666 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pThis,
7667 TMTIMER_FLAGS_NO_CRIT_SECT,
7668 "E1000 Late Interrupt Timer", &pThis->pIntTimerR3);
7669 if (RT_FAILURE(rc))
7670 return rc;
7671 pThis->pIntTimerR0 = TMTimerR0Ptr(pThis->pIntTimerR3);
7672 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7673
7674 /* Create Link Up Timer */
7675 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pThis,
7676 TMTIMER_FLAGS_NO_CRIT_SECT,
7677 "E1000 Link Up Timer", &pThis->pLUTimerR3);
7678 if (RT_FAILURE(rc))
7679 return rc;
7680 pThis->pLUTimerR0 = TMTimerR0Ptr(pThis->pLUTimerR3);
7681 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7682
7683 /* Register the info item */
7684 char szTmp[20];
7685 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7686 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7687
7688 /* Status driver */
7689 PPDMIBASE pBase;
7690 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
7691 if (RT_FAILURE(rc))
7692 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7693 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7694
7695 /* Network driver */
7696 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7697 if (RT_SUCCESS(rc))
7698 {
7699 if (rc == VINF_NAT_DNS)
7700 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7701 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7702 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7703 AssertMsgReturn(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7704
7705 pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7706 pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7707 }
7708 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7709 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7710 {
7711 /* No error! */
7712 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7713 }
7714 else
7715 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7716
7717 rc = RTSemEventCreate(&pThis->hEventMoreRxDescAvail);
7718 if (RT_FAILURE(rc))
7719 return rc;
7720
7721 rc = e1kInitDebugHelpers();
7722 if (RT_FAILURE(rc))
7723 return rc;
7724
7725 e1kHardReset(pThis);
7726
7727 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Public/Net/E1k%u/BytesReceived", iInstance);
7728 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Public/Net/E1k%u/BytesTransmitted", iInstance);
7729
7730 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
7731 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
7732
7733#if defined(VBOX_WITH_STATISTICS)
7734 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
7735 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
7736 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
7737 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
7738 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
7739 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
7740 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
7741 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
7742 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
7743 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
7744 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
7745 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
7746 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
7747 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
7748 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
7749 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming", "/Devices/E1k%d/Receive/CRC", iInstance);
7750 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
7751 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
7752 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
7753 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
7754 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
7755 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
7756 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
7757 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
7758
7759 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
7760 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
7761 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
7762 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
7763 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
7764 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
7765 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
7766 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
7767 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
7768 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
7769 {
7770 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7771 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Reads", iInstance, g_aE1kRegMap[iReg].abbrev);
7772 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7773 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Writes", iInstance, g_aE1kRegMap[iReg].abbrev);
7774 }
7775#endif /* VBOX_WITH_STATISTICS */
7776
7777#ifdef E1K_INT_STATS
7778 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "u64ArmedAt", "/Devices/E1k%d/u64ArmedAt", iInstance);
7779 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatMaxTxDelay", "/Devices/E1k%d/uStatMaxTxDelay", iInstance);
7780 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatInt, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatInt", "/Devices/E1k%d/uStatInt", iInstance);
7781 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTry", "/Devices/E1k%d/uStatIntTry", iInstance);
7782 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLower", "/Devices/E1k%d/uStatIntLower", iInstance);
7783 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntDly", "/Devices/E1k%d/uStatIntDly", iInstance);
7784 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLost", "/Devices/E1k%d/iStatIntLost", iInstance);
7785 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLostOne", "/Devices/E1k%d/iStatIntLostOne", iInstance);
7786 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDisDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDisDly", "/Devices/E1k%d/uStatDisDly", iInstance);
7787 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntSkip", "/Devices/E1k%d/uStatIntSkip", iInstance);
7788 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLate", "/Devices/E1k%d/uStatIntLate", iInstance);
7789 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntMasked", "/Devices/E1k%d/uStatIntMasked", iInstance);
7790 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntEarly", "/Devices/E1k%d/uStatIntEarly", iInstance);
7791 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRx", "/Devices/E1k%d/uStatIntRx", iInstance);
7792 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTx", "/Devices/E1k%d/uStatIntTx", iInstance);
7793 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntICS", "/Devices/E1k%d/uStatIntICS", iInstance);
7794 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRDTR", "/Devices/E1k%d/uStatIntRDTR", iInstance);
7795 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRXDMT0", "/Devices/E1k%d/uStatIntRXDMT0", iInstance);
7796 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTXQE", "/Devices/E1k%d/uStatIntTXQE", iInstance);
7797 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxNoRS", "/Devices/E1k%d/uStatTxNoRS", iInstance);
7798 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxIDE", "/Devices/E1k%d/uStatTxIDE", iInstance);
7799 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayed", "/Devices/E1k%d/uStatTxDelayed", iInstance);
7800 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayExp", "/Devices/E1k%d/uStatTxDelayExp", iInstance);
7801 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTAD", "/Devices/E1k%d/uStatTAD", iInstance);
7802 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTID", "/Devices/E1k%d/uStatTID", iInstance);
7803 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRAD", "/Devices/E1k%d/uStatRAD", iInstance);
7804 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRID", "/Devices/E1k%d/uStatRID", iInstance);
7805 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRxFrm", "/Devices/E1k%d/uStatRxFrm", iInstance);
7806 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxFrm", "/Devices/E1k%d/uStatTxFrm", iInstance);
7807 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescCtx", "/Devices/E1k%d/uStatDescCtx", iInstance);
7808 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescDat", "/Devices/E1k%d/uStatDescDat", iInstance);
7809 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescLeg", "/Devices/E1k%d/uStatDescLeg", iInstance);
7810 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx1514", "/Devices/E1k%d/uStatTx1514", iInstance);
7811 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx2962", "/Devices/E1k%d/uStatTx2962", iInstance);
7812 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx4410", "/Devices/E1k%d/uStatTx4410", iInstance);
7813 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx5858", "/Devices/E1k%d/uStatTx5858", iInstance);
7814 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx7306", "/Devices/E1k%d/uStatTx7306", iInstance);
7815 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx8754", "/Devices/E1k%d/uStatTx8754", iInstance);
7816 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx16384", "/Devices/E1k%d/uStatTx16384", iInstance);
7817 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx32768", "/Devices/E1k%d/uStatTx32768", iInstance);
7818 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxLarge", "/Devices/E1k%d/uStatTxLarge", iInstance);
7819#endif /* E1K_INT_STATS */
7820
7821 return VINF_SUCCESS;
7822}
7823
7824/**
7825 * The device registration structure.
7826 */
7827const PDMDEVREG g_DeviceE1000 =
7828{
7829 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
7830 PDM_DEVREG_VERSION,
7831 /* Device name. */
7832 "e1000",
7833 /* Name of guest context module (no path).
7834 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7835 "VBoxDDRC.rc",
7836 /* Name of ring-0 module (no path).
7837 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7838 "VBoxDDR0.r0",
7839 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
7840 * remain unchanged from registration till VM destruction. */
7841 "Intel PRO/1000 MT Desktop Ethernet.\n",
7842
7843 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
7844 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
7845 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
7846 PDM_DEVREG_CLASS_NETWORK,
7847 /* Maximum number of instances (per VM). */
7848 ~0U,
7849 /* Size of the instance data. */
7850 sizeof(E1KSTATE),
7851
7852 /* pfnConstruct */
7853 e1kR3Construct,
7854 /* pfnDestruct */
7855 e1kR3Destruct,
7856 /* pfnRelocate */
7857 e1kR3Relocate,
7858 /* pfnMemSetup */
7859 NULL,
7860 /* pfnPowerOn */
7861 NULL,
7862 /* pfnReset */
7863 e1kR3Reset,
7864 /* pfnSuspend */
7865 e1kR3Suspend,
7866 /* pfnResume */
7867 NULL,
7868 /* pfnAttach */
7869 e1kR3Attach,
7870 /* pfnDeatch */
7871 e1kR3Detach,
7872 /* pfnQueryInterface */
7873 NULL,
7874 /* pfnInitComplete */
7875 NULL,
7876 /* pfnPowerOff */
7877 e1kR3PowerOff,
7878 /* pfnSoftReset */
7879 NULL,
7880
7881 /* u32VersionEnd */
7882 PDM_DEVREG_VERSION
7883};
7884
7885#endif /* IN_RING3 */
7886#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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