VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 92723

Last change on this file since 92723 was 91485, checked in by vboxsync, 3 years ago

Dev/e1000: bugref:10114 Increased link up delay to 5 seconds
  • Property svn:eol-style set to native
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File size: 334.6 KB
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1/* $Id: DevE1000.cpp 91485 2021-09-30 07:57:39Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2020 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280#ifndef VBOX_DEVICE_STRUCT_TESTCASE
281/** Gets the specfieid bits from the register. */
282#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
284#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
285#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
287
288#define CTRL_SLU UINT32_C(0x00000040)
289#define CTRL_MDIO UINT32_C(0x00100000)
290#define CTRL_MDC UINT32_C(0x00200000)
291#define CTRL_MDIO_DIR UINT32_C(0x01000000)
292#define CTRL_MDC_DIR UINT32_C(0x02000000)
293#define CTRL_RESET UINT32_C(0x04000000)
294#define CTRL_VME UINT32_C(0x40000000)
295
296#define STATUS_LU UINT32_C(0x00000002)
297#define STATUS_TXOFF UINT32_C(0x00000010)
298
299#define EECD_EE_WIRES UINT32_C(0x0F)
300#define EECD_EE_REQ UINT32_C(0x40)
301#define EECD_EE_GNT UINT32_C(0x80)
302
303#define EERD_START UINT32_C(0x00000001)
304#define EERD_DONE UINT32_C(0x00000010)
305#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
306#define EERD_DATA_SHIFT 16
307#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
308#define EERD_ADDR_SHIFT 8
309
310#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
311#define MDIC_DATA_SHIFT 0
312#define MDIC_REG_MASK UINT32_C(0x001F0000)
313#define MDIC_REG_SHIFT 16
314#define MDIC_PHY_MASK UINT32_C(0x03E00000)
315#define MDIC_PHY_SHIFT 21
316#define MDIC_OP_WRITE UINT32_C(0x04000000)
317#define MDIC_OP_READ UINT32_C(0x08000000)
318#define MDIC_READY UINT32_C(0x10000000)
319#define MDIC_INT_EN UINT32_C(0x20000000)
320#define MDIC_ERROR UINT32_C(0x40000000)
321
322#define TCTL_EN UINT32_C(0x00000002)
323#define TCTL_PSP UINT32_C(0x00000008)
324
325#define RCTL_EN UINT32_C(0x00000002)
326#define RCTL_UPE UINT32_C(0x00000008)
327#define RCTL_MPE UINT32_C(0x00000010)
328#define RCTL_LPE UINT32_C(0x00000020)
329#define RCTL_LBM_MASK UINT32_C(0x000000C0)
330#define RCTL_LBM_SHIFT 6
331#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
332#define RCTL_RDMTS_SHIFT 8
333#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
334#define RCTL_MO_MASK UINT32_C(0x00003000)
335#define RCTL_MO_SHIFT 12
336#define RCTL_BAM UINT32_C(0x00008000)
337#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
338#define RCTL_BSIZE_SHIFT 16
339#define RCTL_VFE UINT32_C(0x00040000)
340#define RCTL_CFIEN UINT32_C(0x00080000)
341#define RCTL_CFI UINT32_C(0x00100000)
342#define RCTL_BSEX UINT32_C(0x02000000)
343#define RCTL_SECRC UINT32_C(0x04000000)
344
345#define ICR_TXDW UINT32_C(0x00000001)
346#define ICR_TXQE UINT32_C(0x00000002)
347#define ICR_LSC UINT32_C(0x00000004)
348#define ICR_RXDMT0 UINT32_C(0x00000010)
349#define ICR_RXT0 UINT32_C(0x00000080)
350#define ICR_TXD_LOW UINT32_C(0x00008000)
351#define RDTR_FPD UINT32_C(0x80000000)
352
353#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
354typedef struct
355{
356 unsigned rxa : 7;
357 unsigned rxa_r : 9;
358 unsigned txa : 16;
359} PBAST;
360AssertCompileSize(PBAST, 4);
361
362#define TXDCTL_WTHRESH_MASK 0x003F0000
363#define TXDCTL_WTHRESH_SHIFT 16
364#define TXDCTL_LWTHRESH_MASK 0xFE000000
365#define TXDCTL_LWTHRESH_SHIFT 25
366
367#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
368#define RXCSUM_PCSS_SHIFT 0
369
370/** @name Register access macros
371 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
372 * @{ */
373#define CTRL pThis->auRegs[CTRL_IDX]
374#define STATUS pThis->auRegs[STATUS_IDX]
375#define EECD pThis->auRegs[EECD_IDX]
376#define EERD pThis->auRegs[EERD_IDX]
377#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
378#define FLA pThis->auRegs[FLA_IDX]
379#define MDIC pThis->auRegs[MDIC_IDX]
380#define FCAL pThis->auRegs[FCAL_IDX]
381#define FCAH pThis->auRegs[FCAH_IDX]
382#define FCT pThis->auRegs[FCT_IDX]
383#define VET pThis->auRegs[VET_IDX]
384#define ICR pThis->auRegs[ICR_IDX]
385#define ITR pThis->auRegs[ITR_IDX]
386#define ICS pThis->auRegs[ICS_IDX]
387#define IMS pThis->auRegs[IMS_IDX]
388#define IMC pThis->auRegs[IMC_IDX]
389#define RCTL pThis->auRegs[RCTL_IDX]
390#define FCTTV pThis->auRegs[FCTTV_IDX]
391#define TXCW pThis->auRegs[TXCW_IDX]
392#define RXCW pThis->auRegs[RXCW_IDX]
393#define TCTL pThis->auRegs[TCTL_IDX]
394#define TIPG pThis->auRegs[TIPG_IDX]
395#define AIFS pThis->auRegs[AIFS_IDX]
396#define LEDCTL pThis->auRegs[LEDCTL_IDX]
397#define PBA pThis->auRegs[PBA_IDX]
398#define FCRTL pThis->auRegs[FCRTL_IDX]
399#define FCRTH pThis->auRegs[FCRTH_IDX]
400#define RDFH pThis->auRegs[RDFH_IDX]
401#define RDFT pThis->auRegs[RDFT_IDX]
402#define RDFHS pThis->auRegs[RDFHS_IDX]
403#define RDFTS pThis->auRegs[RDFTS_IDX]
404#define RDFPC pThis->auRegs[RDFPC_IDX]
405#define RDBAL pThis->auRegs[RDBAL_IDX]
406#define RDBAH pThis->auRegs[RDBAH_IDX]
407#define RDLEN pThis->auRegs[RDLEN_IDX]
408#define RDH pThis->auRegs[RDH_IDX]
409#define RDT pThis->auRegs[RDT_IDX]
410#define RDTR pThis->auRegs[RDTR_IDX]
411#define RXDCTL pThis->auRegs[RXDCTL_IDX]
412#define RADV pThis->auRegs[RADV_IDX]
413#define RSRPD pThis->auRegs[RSRPD_IDX]
414#define TXDMAC pThis->auRegs[TXDMAC_IDX]
415#define TDFH pThis->auRegs[TDFH_IDX]
416#define TDFT pThis->auRegs[TDFT_IDX]
417#define TDFHS pThis->auRegs[TDFHS_IDX]
418#define TDFTS pThis->auRegs[TDFTS_IDX]
419#define TDFPC pThis->auRegs[TDFPC_IDX]
420#define TDBAL pThis->auRegs[TDBAL_IDX]
421#define TDBAH pThis->auRegs[TDBAH_IDX]
422#define TDLEN pThis->auRegs[TDLEN_IDX]
423#define TDH pThis->auRegs[TDH_IDX]
424#define TDT pThis->auRegs[TDT_IDX]
425#define TIDV pThis->auRegs[TIDV_IDX]
426#define TXDCTL pThis->auRegs[TXDCTL_IDX]
427#define TADV pThis->auRegs[TADV_IDX]
428#define TSPMT pThis->auRegs[TSPMT_IDX]
429#define CRCERRS pThis->auRegs[CRCERRS_IDX]
430#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
431#define SYMERRS pThis->auRegs[SYMERRS_IDX]
432#define RXERRC pThis->auRegs[RXERRC_IDX]
433#define MPC pThis->auRegs[MPC_IDX]
434#define SCC pThis->auRegs[SCC_IDX]
435#define ECOL pThis->auRegs[ECOL_IDX]
436#define MCC pThis->auRegs[MCC_IDX]
437#define LATECOL pThis->auRegs[LATECOL_IDX]
438#define COLC pThis->auRegs[COLC_IDX]
439#define DC pThis->auRegs[DC_IDX]
440#define TNCRS pThis->auRegs[TNCRS_IDX]
441/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
442#define CEXTERR pThis->auRegs[CEXTERR_IDX]
443#define RLEC pThis->auRegs[RLEC_IDX]
444#define XONRXC pThis->auRegs[XONRXC_IDX]
445#define XONTXC pThis->auRegs[XONTXC_IDX]
446#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
447#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
448#define FCRUC pThis->auRegs[FCRUC_IDX]
449#define PRC64 pThis->auRegs[PRC64_IDX]
450#define PRC127 pThis->auRegs[PRC127_IDX]
451#define PRC255 pThis->auRegs[PRC255_IDX]
452#define PRC511 pThis->auRegs[PRC511_IDX]
453#define PRC1023 pThis->auRegs[PRC1023_IDX]
454#define PRC1522 pThis->auRegs[PRC1522_IDX]
455#define GPRC pThis->auRegs[GPRC_IDX]
456#define BPRC pThis->auRegs[BPRC_IDX]
457#define MPRC pThis->auRegs[MPRC_IDX]
458#define GPTC pThis->auRegs[GPTC_IDX]
459#define GORCL pThis->auRegs[GORCL_IDX]
460#define GORCH pThis->auRegs[GORCH_IDX]
461#define GOTCL pThis->auRegs[GOTCL_IDX]
462#define GOTCH pThis->auRegs[GOTCH_IDX]
463#define RNBC pThis->auRegs[RNBC_IDX]
464#define RUC pThis->auRegs[RUC_IDX]
465#define RFC pThis->auRegs[RFC_IDX]
466#define ROC pThis->auRegs[ROC_IDX]
467#define RJC pThis->auRegs[RJC_IDX]
468#define MGTPRC pThis->auRegs[MGTPRC_IDX]
469#define MGTPDC pThis->auRegs[MGTPDC_IDX]
470#define MGTPTC pThis->auRegs[MGTPTC_IDX]
471#define TORL pThis->auRegs[TORL_IDX]
472#define TORH pThis->auRegs[TORH_IDX]
473#define TOTL pThis->auRegs[TOTL_IDX]
474#define TOTH pThis->auRegs[TOTH_IDX]
475#define TPR pThis->auRegs[TPR_IDX]
476#define TPT pThis->auRegs[TPT_IDX]
477#define PTC64 pThis->auRegs[PTC64_IDX]
478#define PTC127 pThis->auRegs[PTC127_IDX]
479#define PTC255 pThis->auRegs[PTC255_IDX]
480#define PTC511 pThis->auRegs[PTC511_IDX]
481#define PTC1023 pThis->auRegs[PTC1023_IDX]
482#define PTC1522 pThis->auRegs[PTC1522_IDX]
483#define MPTC pThis->auRegs[MPTC_IDX]
484#define BPTC pThis->auRegs[BPTC_IDX]
485#define TSCTC pThis->auRegs[TSCTC_IDX]
486#define TSCTFC pThis->auRegs[TSCTFC_IDX]
487#define RXCSUM pThis->auRegs[RXCSUM_IDX]
488#define WUC pThis->auRegs[WUC_IDX]
489#define WUFC pThis->auRegs[WUFC_IDX]
490#define WUS pThis->auRegs[WUS_IDX]
491#define MANC pThis->auRegs[MANC_IDX]
492#define IPAV pThis->auRegs[IPAV_IDX]
493#define WUPL pThis->auRegs[WUPL_IDX]
494/** @} */
495#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
496
497/**
498 * Indices of memory-mapped registers in register table.
499 */
500typedef enum
501{
502 CTRL_IDX,
503 STATUS_IDX,
504 EECD_IDX,
505 EERD_IDX,
506 CTRL_EXT_IDX,
507 FLA_IDX,
508 MDIC_IDX,
509 FCAL_IDX,
510 FCAH_IDX,
511 FCT_IDX,
512 VET_IDX,
513 ICR_IDX,
514 ITR_IDX,
515 ICS_IDX,
516 IMS_IDX,
517 IMC_IDX,
518 RCTL_IDX,
519 FCTTV_IDX,
520 TXCW_IDX,
521 RXCW_IDX,
522 TCTL_IDX,
523 TIPG_IDX,
524 AIFS_IDX,
525 LEDCTL_IDX,
526 PBA_IDX,
527 FCRTL_IDX,
528 FCRTH_IDX,
529 RDFH_IDX,
530 RDFT_IDX,
531 RDFHS_IDX,
532 RDFTS_IDX,
533 RDFPC_IDX,
534 RDBAL_IDX,
535 RDBAH_IDX,
536 RDLEN_IDX,
537 RDH_IDX,
538 RDT_IDX,
539 RDTR_IDX,
540 RXDCTL_IDX,
541 RADV_IDX,
542 RSRPD_IDX,
543 TXDMAC_IDX,
544 TDFH_IDX,
545 TDFT_IDX,
546 TDFHS_IDX,
547 TDFTS_IDX,
548 TDFPC_IDX,
549 TDBAL_IDX,
550 TDBAH_IDX,
551 TDLEN_IDX,
552 TDH_IDX,
553 TDT_IDX,
554 TIDV_IDX,
555 TXDCTL_IDX,
556 TADV_IDX,
557 TSPMT_IDX,
558 CRCERRS_IDX,
559 ALGNERRC_IDX,
560 SYMERRS_IDX,
561 RXERRC_IDX,
562 MPC_IDX,
563 SCC_IDX,
564 ECOL_IDX,
565 MCC_IDX,
566 LATECOL_IDX,
567 COLC_IDX,
568 DC_IDX,
569 TNCRS_IDX,
570 SEC_IDX,
571 CEXTERR_IDX,
572 RLEC_IDX,
573 XONRXC_IDX,
574 XONTXC_IDX,
575 XOFFRXC_IDX,
576 XOFFTXC_IDX,
577 FCRUC_IDX,
578 PRC64_IDX,
579 PRC127_IDX,
580 PRC255_IDX,
581 PRC511_IDX,
582 PRC1023_IDX,
583 PRC1522_IDX,
584 GPRC_IDX,
585 BPRC_IDX,
586 MPRC_IDX,
587 GPTC_IDX,
588 GORCL_IDX,
589 GORCH_IDX,
590 GOTCL_IDX,
591 GOTCH_IDX,
592 RNBC_IDX,
593 RUC_IDX,
594 RFC_IDX,
595 ROC_IDX,
596 RJC_IDX,
597 MGTPRC_IDX,
598 MGTPDC_IDX,
599 MGTPTC_IDX,
600 TORL_IDX,
601 TORH_IDX,
602 TOTL_IDX,
603 TOTH_IDX,
604 TPR_IDX,
605 TPT_IDX,
606 PTC64_IDX,
607 PTC127_IDX,
608 PTC255_IDX,
609 PTC511_IDX,
610 PTC1023_IDX,
611 PTC1522_IDX,
612 MPTC_IDX,
613 BPTC_IDX,
614 TSCTC_IDX,
615 TSCTFC_IDX,
616 RXCSUM_IDX,
617 WUC_IDX,
618 WUFC_IDX,
619 WUS_IDX,
620 MANC_IDX,
621 IPAV_IDX,
622 WUPL_IDX,
623 MTA_IDX,
624 RA_IDX,
625 VFTA_IDX,
626 IP4AT_IDX,
627 IP6AT_IDX,
628 WUPM_IDX,
629 FFLT_IDX,
630 FFMT_IDX,
631 FFVT_IDX,
632 PBM_IDX,
633 RA_82542_IDX,
634 MTA_82542_IDX,
635 VFTA_82542_IDX,
636 E1K_NUM_OF_REGS
637} E1kRegIndex;
638
639#define E1K_NUM_OF_32BIT_REGS MTA_IDX
640/** The number of registers with strictly increasing offset. */
641#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
642
643
644/**
645 * Define E1000-specific EEPROM layout.
646 */
647struct E1kEEPROM
648{
649 public:
650 EEPROM93C46 eeprom;
651
652#ifdef IN_RING3
653 /**
654 * Initialize EEPROM content.
655 *
656 * @param macAddr MAC address of E1000.
657 */
658 void init(RTMAC &macAddr)
659 {
660 eeprom.init();
661 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
662 eeprom.m_au16Data[0x04] = 0xFFFF;
663 /*
664 * bit 3 - full support for power management
665 * bit 10 - full duplex
666 */
667 eeprom.m_au16Data[0x0A] = 0x4408;
668 eeprom.m_au16Data[0x0B] = 0x001E;
669 eeprom.m_au16Data[0x0C] = 0x8086;
670 eeprom.m_au16Data[0x0D] = 0x100E;
671 eeprom.m_au16Data[0x0E] = 0x8086;
672 eeprom.m_au16Data[0x0F] = 0x3040;
673 eeprom.m_au16Data[0x21] = 0x7061;
674 eeprom.m_au16Data[0x22] = 0x280C;
675 eeprom.m_au16Data[0x23] = 0x00C8;
676 eeprom.m_au16Data[0x24] = 0x00C8;
677 eeprom.m_au16Data[0x2F] = 0x0602;
678 updateChecksum();
679 };
680
681 /**
682 * Compute the checksum as required by E1000 and store it
683 * in the last word.
684 */
685 void updateChecksum()
686 {
687 uint16_t u16Checksum = 0;
688
689 for (int i = 0; i < eeprom.SIZE-1; i++)
690 u16Checksum += eeprom.m_au16Data[i];
691 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
692 };
693
694 /**
695 * First 6 bytes of EEPROM contain MAC address.
696 *
697 * @returns MAC address of E1000.
698 */
699 void getMac(PRTMAC pMac)
700 {
701 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
702 };
703
704 uint32_t read()
705 {
706 return eeprom.read();
707 }
708
709 void write(uint32_t u32Wires)
710 {
711 eeprom.write(u32Wires);
712 }
713
714 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
715 {
716 return eeprom.readWord(u32Addr, pu16Value);
717 }
718
719 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
720 {
721 return eeprom.load(pHlp, pSSM);
722 }
723
724 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
725 {
726 eeprom.save(pHlp, pSSM);
727 }
728#endif /* IN_RING3 */
729};
730
731
732#define E1K_SPEC_VLAN(s) (s & 0xFFF)
733#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
734#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
735
736struct E1kRxDStatus
737{
738 /** @name Descriptor Status field (3.2.3.1)
739 * @{ */
740 unsigned fDD : 1; /**< Descriptor Done. */
741 unsigned fEOP : 1; /**< End of packet. */
742 unsigned fIXSM : 1; /**< Ignore checksum indication. */
743 unsigned fVP : 1; /**< VLAN, matches VET. */
744 unsigned : 1;
745 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
746 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
747 unsigned fPIF : 1; /**< Passed in-exact filter */
748 /** @} */
749 /** @name Descriptor Errors field (3.2.3.2)
750 * (Only valid when fEOP and fDD are set.)
751 * @{ */
752 unsigned fCE : 1; /**< CRC or alignment error. */
753 unsigned : 4; /**< Reserved, varies with different models... */
754 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
755 unsigned fIPE : 1; /**< IP Checksum error. */
756 unsigned fRXE : 1; /**< RX Data error. */
757 /** @} */
758 /** @name Descriptor Special field (3.2.3.3)
759 * @{ */
760 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
761 /** @} */
762};
763typedef struct E1kRxDStatus E1KRXDST;
764
765struct E1kRxDesc_st
766{
767 uint64_t u64BufAddr; /**< Address of data buffer */
768 uint16_t u16Length; /**< Length of data in buffer */
769 uint16_t u16Checksum; /**< Packet checksum */
770 E1KRXDST status;
771};
772typedef struct E1kRxDesc_st E1KRXDESC;
773AssertCompileSize(E1KRXDESC, 16);
774
775#define E1K_DTYP_LEGACY -1
776#define E1K_DTYP_CONTEXT 0
777#define E1K_DTYP_DATA 1
778
779struct E1kTDLegacy
780{
781 uint64_t u64BufAddr; /**< Address of data buffer */
782 struct TDLCmd_st
783 {
784 unsigned u16Length : 16;
785 unsigned u8CSO : 8;
786 /* CMD field : 8 */
787 unsigned fEOP : 1;
788 unsigned fIFCS : 1;
789 unsigned fIC : 1;
790 unsigned fRS : 1;
791 unsigned fRPS : 1;
792 unsigned fDEXT : 1;
793 unsigned fVLE : 1;
794 unsigned fIDE : 1;
795 } cmd;
796 struct TDLDw3_st
797 {
798 /* STA field */
799 unsigned fDD : 1;
800 unsigned fEC : 1;
801 unsigned fLC : 1;
802 unsigned fTURSV : 1;
803 /* RSV field */
804 unsigned u4RSV : 4;
805 /* CSS field */
806 unsigned u8CSS : 8;
807 /* Special field*/
808 unsigned u16Special: 16;
809 } dw3;
810};
811
812/**
813 * TCP/IP Context Transmit Descriptor, section 3.3.6.
814 */
815struct E1kTDContext
816{
817 struct CheckSum_st
818 {
819 /** TSE: Header start. !TSE: Checksum start. */
820 unsigned u8CSS : 8;
821 /** Checksum offset - where to store it. */
822 unsigned u8CSO : 8;
823 /** Checksum ending (inclusive) offset, 0 = end of packet. */
824 unsigned u16CSE : 16;
825 } ip;
826 struct CheckSum_st tu;
827 struct TDCDw2_st
828 {
829 /** TSE: The total number of payload bytes for this context. Sans header. */
830 unsigned u20PAYLEN : 20;
831 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
832 unsigned u4DTYP : 4;
833 /** TUCMD field, 8 bits
834 * @{ */
835 /** TSE: TCP (set) or UDP (clear). */
836 unsigned fTCP : 1;
837 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
838 * the IP header. Does not affect the checksumming.
839 * @remarks 82544GC/EI interprets a cleared field differently. */
840 unsigned fIP : 1;
841 /** TSE: TCP segmentation enable. When clear the context describes */
842 unsigned fTSE : 1;
843 /** Report status (only applies to dw3.fDD for here). */
844 unsigned fRS : 1;
845 /** Reserved, MBZ. */
846 unsigned fRSV1 : 1;
847 /** Descriptor extension, must be set for this descriptor type. */
848 unsigned fDEXT : 1;
849 /** Reserved, MBZ. */
850 unsigned fRSV2 : 1;
851 /** Interrupt delay enable. */
852 unsigned fIDE : 1;
853 /** @} */
854 } dw2;
855 struct TDCDw3_st
856 {
857 /** Descriptor Done. */
858 unsigned fDD : 1;
859 /** Reserved, MBZ. */
860 unsigned u7RSV : 7;
861 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
862 unsigned u8HDRLEN : 8;
863 /** TSO: Maximum segment size. */
864 unsigned u16MSS : 16;
865 } dw3;
866};
867typedef struct E1kTDContext E1KTXCTX;
868
869/**
870 * TCP/IP Data Transmit Descriptor, section 3.3.7.
871 */
872struct E1kTDData
873{
874 uint64_t u64BufAddr; /**< Address of data buffer */
875 struct TDDCmd_st
876 {
877 /** The total length of data pointed to by this descriptor. */
878 unsigned u20DTALEN : 20;
879 /** The descriptor type - E1K_DTYP_DATA (1). */
880 unsigned u4DTYP : 4;
881 /** @name DCMD field, 8 bits (3.3.7.1).
882 * @{ */
883 /** End of packet. Note TSCTFC update. */
884 unsigned fEOP : 1;
885 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
886 unsigned fIFCS : 1;
887 /** Use the TSE context when set and the normal when clear. */
888 unsigned fTSE : 1;
889 /** Report status (dw3.STA). */
890 unsigned fRS : 1;
891 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
892 unsigned fRPS : 1;
893 /** Descriptor extension, must be set for this descriptor type. */
894 unsigned fDEXT : 1;
895 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
896 * Insert dw3.SPECIAL after ethernet header. */
897 unsigned fVLE : 1;
898 /** Interrupt delay enable. */
899 unsigned fIDE : 1;
900 /** @} */
901 } cmd;
902 struct TDDDw3_st
903 {
904 /** @name STA field (3.3.7.2)
905 * @{ */
906 unsigned fDD : 1; /**< Descriptor done. */
907 unsigned fEC : 1; /**< Excess collision. */
908 unsigned fLC : 1; /**< Late collision. */
909 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
910 unsigned fTURSV : 1;
911 /** @} */
912 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
913 /** @name POPTS (Packet Option) field (3.3.7.3)
914 * @{ */
915 unsigned fIXSM : 1; /**< Insert IP checksum. */
916 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
917 unsigned u6RSV : 6; /**< Reserved, MBZ. */
918 /** @} */
919 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
920 * Requires fEOP, fVLE and CTRL.VME to be set.
921 * @{ */
922 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
923 /** @} */
924 } dw3;
925};
926typedef struct E1kTDData E1KTXDAT;
927
928union E1kTxDesc
929{
930 struct E1kTDLegacy legacy;
931 struct E1kTDContext context;
932 struct E1kTDData data;
933};
934typedef union E1kTxDesc E1KTXDESC;
935AssertCompileSize(E1KTXDESC, 16);
936
937#define RA_CTL_AS 0x0003
938#define RA_CTL_AV 0x8000
939
940union E1kRecAddr
941{
942 uint32_t au32[32];
943 struct RAArray
944 {
945 uint8_t addr[6];
946 uint16_t ctl;
947 } array[16];
948};
949typedef struct E1kRecAddr::RAArray E1KRAELEM;
950typedef union E1kRecAddr E1KRA;
951AssertCompileSize(E1KRA, 8*16);
952
953#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
954#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
955#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
956#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
957
958/** @todo use+extend RTNETIPV4 */
959struct E1kIpHeader
960{
961 /* type of service / version / header length */
962 uint16_t tos_ver_hl;
963 /* total length */
964 uint16_t total_len;
965 /* identification */
966 uint16_t ident;
967 /* fragment offset field */
968 uint16_t offset;
969 /* time to live / protocol*/
970 uint16_t ttl_proto;
971 /* checksum */
972 uint16_t chksum;
973 /* source IP address */
974 uint32_t src;
975 /* destination IP address */
976 uint32_t dest;
977};
978AssertCompileSize(struct E1kIpHeader, 20);
979
980#define E1K_TCP_FIN UINT16_C(0x01)
981#define E1K_TCP_SYN UINT16_C(0x02)
982#define E1K_TCP_RST UINT16_C(0x04)
983#define E1K_TCP_PSH UINT16_C(0x08)
984#define E1K_TCP_ACK UINT16_C(0x10)
985#define E1K_TCP_URG UINT16_C(0x20)
986#define E1K_TCP_ECE UINT16_C(0x40)
987#define E1K_TCP_CWR UINT16_C(0x80)
988#define E1K_TCP_FLAGS UINT16_C(0x3f)
989
990/** @todo use+extend RTNETTCP */
991struct E1kTcpHeader
992{
993 uint16_t src;
994 uint16_t dest;
995 uint32_t seqno;
996 uint32_t ackno;
997 uint16_t hdrlen_flags;
998 uint16_t wnd;
999 uint16_t chksum;
1000 uint16_t urgp;
1001};
1002AssertCompileSize(struct E1kTcpHeader, 20);
1003
1004
1005#ifdef E1K_WITH_TXD_CACHE
1006/** The current Saved state version. */
1007# define E1K_SAVEDSTATE_VERSION 4
1008/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1009# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1010#else /* !E1K_WITH_TXD_CACHE */
1011/** The current Saved state version. */
1012# define E1K_SAVEDSTATE_VERSION 3
1013#endif /* !E1K_WITH_TXD_CACHE */
1014/** Saved state version for VirtualBox 4.1 and earlier.
1015 * These did not include VLAN tag fields. */
1016#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1017/** Saved state version for VirtualBox 3.0 and earlier.
1018 * This did not include the configuration part nor the E1kEEPROM. */
1019#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1020
1021/**
1022 * E1000 shared device state.
1023 *
1024 * This is shared between ring-0 and ring-3.
1025 */
1026typedef struct E1KSTATE
1027{
1028 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1029
1030 /** Handle to PCI region \#0, the MMIO region. */
1031 IOMIOPORTHANDLE hMmioRegion;
1032 /** Handle to PCI region \#2, the I/O ports. */
1033 IOMIOPORTHANDLE hIoPorts;
1034
1035 /** Receive Interrupt Delay Timer. */
1036 TMTIMERHANDLE hRIDTimer;
1037 /** Receive Absolute Delay Timer. */
1038 TMTIMERHANDLE hRADTimer;
1039 /** Transmit Interrupt Delay Timer. */
1040 TMTIMERHANDLE hTIDTimer;
1041 /** Transmit Absolute Delay Timer. */
1042 TMTIMERHANDLE hTADTimer;
1043 /** Transmit Delay Timer. */
1044 TMTIMERHANDLE hTXDTimer;
1045 /** Late Interrupt Timer. */
1046 TMTIMERHANDLE hIntTimer;
1047 /** Link Up(/Restore) Timer. */
1048 TMTIMERHANDLE hLUTimer;
1049
1050 /** Transmit task. */
1051 PDMTASKHANDLE hTxTask;
1052
1053 /** Critical section - what is it protecting? */
1054 PDMCRITSECT cs;
1055 /** RX Critical section. */
1056 PDMCRITSECT csRx;
1057#ifdef E1K_WITH_TX_CS
1058 /** TX Critical section. */
1059 PDMCRITSECT csTx;
1060#endif /* E1K_WITH_TX_CS */
1061 /** MAC address obtained from the configuration. */
1062 RTMAC macConfigured;
1063 uint16_t u16Padding0;
1064 /** EMT: Last time the interrupt was acknowledged. */
1065 uint64_t u64AckedAt;
1066 /** All: Used for eliminating spurious interrupts. */
1067 bool fIntRaised;
1068 /** EMT: false if the cable is disconnected by the GUI. */
1069 bool fCableConnected;
1070 /** EMT: Compute Ethernet CRC for RX packets. */
1071 bool fEthernetCRC;
1072 /** All: throttle interrupts. */
1073 bool fItrEnabled;
1074 /** All: throttle RX interrupts. */
1075 bool fItrRxEnabled;
1076 /** All: Delay TX interrupts using TIDV/TADV. */
1077 bool fTidEnabled;
1078 bool afPadding[2];
1079 /** Link up delay (in milliseconds). */
1080 uint32_t cMsLinkUpDelay;
1081
1082 /** All: Device register storage. */
1083 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1084 /** TX/RX: Status LED. */
1085 PDMLED led;
1086 /** TX/RX: Number of packet being sent/received to show in debug log. */
1087 uint32_t u32PktNo;
1088
1089 /** EMT: Offset of the register to be read via IO. */
1090 uint32_t uSelectedReg;
1091 /** EMT: Multicast Table Array. */
1092 uint32_t auMTA[128];
1093 /** EMT: Receive Address registers. */
1094 E1KRA aRecAddr;
1095 /** EMT: VLAN filter table array. */
1096 uint32_t auVFTA[128];
1097 /** EMT: Receive buffer size. */
1098 uint16_t u16RxBSize;
1099 /** EMT: Locked state -- no state alteration possible. */
1100 bool fLocked;
1101 /** EMT: */
1102 bool fDelayInts;
1103 /** All: */
1104 bool fIntMaskUsed;
1105
1106 /** N/A: */
1107 bool volatile fMaybeOutOfSpace;
1108 /** EMT: Gets signalled when more RX descriptors become available. */
1109 SUPSEMEVENT hEventMoreRxDescAvail;
1110#ifdef E1K_WITH_RXD_CACHE
1111 /** RX: Fetched RX descriptors. */
1112 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1113 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1114 /** RX: Actual number of fetched RX descriptors. */
1115 uint32_t nRxDFetched;
1116 /** RX: Index in cache of RX descriptor being processed. */
1117 uint32_t iRxDCurrent;
1118#endif /* E1K_WITH_RXD_CACHE */
1119
1120 /** TX: Context used for TCP segmentation packets. */
1121 E1KTXCTX contextTSE;
1122 /** TX: Context used for ordinary packets. */
1123 E1KTXCTX contextNormal;
1124#ifdef E1K_WITH_TXD_CACHE
1125 /** TX: Fetched TX descriptors. */
1126 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1127 /** TX: Validity of TX descriptors. Set by e1kLocateTxPacket, used by e1kXmitPacket. */
1128 bool afTxDValid[E1K_TXD_CACHE_SIZE];
1129 /** TX: Actual number of fetched TX descriptors. */
1130 uint8_t nTxDFetched;
1131 /** TX: Index in cache of TX descriptor being processed. */
1132 uint8_t iTxDCurrent;
1133 /** TX: Will this frame be sent as GSO. */
1134 bool fGSO;
1135 /** Alignment padding. */
1136 bool fReserved;
1137 /** TX: Number of bytes in next packet. */
1138 uint32_t cbTxAlloc;
1139
1140#endif /* E1K_WITH_TXD_CACHE */
1141 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1142 * applicable to the current TSE mode. */
1143 PDMNETWORKGSO GsoCtx;
1144 /** Scratch space for holding the loopback / fallback scatter / gather
1145 * descriptor. */
1146 union
1147 {
1148 PDMSCATTERGATHER Sg;
1149 uint8_t padding[8 * sizeof(RTUINTPTR)];
1150 } uTxFallback;
1151 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1152 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1153 /** TX: Number of bytes assembled in TX packet buffer. */
1154 uint16_t u16TxPktLen;
1155 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1156 bool fGSOEnabled;
1157 /** TX: IP checksum has to be inserted if true. */
1158 bool fIPcsum;
1159 /** TX: TCP/UDP checksum has to be inserted if true. */
1160 bool fTCPcsum;
1161 /** TX: VLAN tag has to be inserted if true. */
1162 bool fVTag;
1163 /** TX: TCI part of VLAN tag to be inserted. */
1164 uint16_t u16VTagTCI;
1165 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1166 uint32_t u32PayRemain;
1167 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1168 uint16_t u16HdrRemain;
1169 /** TX TSE fallback: Flags from template header. */
1170 uint16_t u16SavedFlags;
1171 /** TX TSE fallback: Partial checksum from template header. */
1172 uint32_t u32SavedCsum;
1173 /** ?: Emulated controller type. */
1174 E1KCHIP eChip;
1175
1176 /** EMT: Physical interface emulation. */
1177 PHY phy;
1178
1179#if 0
1180 /** Alignment padding. */
1181 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1182#endif
1183
1184 STAMCOUNTER StatReceiveBytes;
1185 STAMCOUNTER StatTransmitBytes;
1186#if defined(VBOX_WITH_STATISTICS)
1187 STAMPROFILEADV StatMMIOReadRZ;
1188 STAMPROFILEADV StatMMIOReadR3;
1189 STAMPROFILEADV StatMMIOWriteRZ;
1190 STAMPROFILEADV StatMMIOWriteR3;
1191 STAMPROFILEADV StatEEPROMRead;
1192 STAMPROFILEADV StatEEPROMWrite;
1193 STAMPROFILEADV StatIOReadRZ;
1194 STAMPROFILEADV StatIOReadR3;
1195 STAMPROFILEADV StatIOWriteRZ;
1196 STAMPROFILEADV StatIOWriteR3;
1197 STAMPROFILEADV StatLateIntTimer;
1198 STAMCOUNTER StatLateInts;
1199 STAMCOUNTER StatIntsRaised;
1200 STAMCOUNTER StatIntsPrevented;
1201 STAMPROFILEADV StatReceive;
1202 STAMPROFILEADV StatReceiveCRC;
1203 STAMPROFILEADV StatReceiveFilter;
1204 STAMPROFILEADV StatReceiveStore;
1205 STAMPROFILEADV StatTransmitRZ;
1206 STAMPROFILEADV StatTransmitR3;
1207 STAMPROFILE StatTransmitSendRZ;
1208 STAMPROFILE StatTransmitSendR3;
1209 STAMPROFILE StatRxOverflow;
1210 STAMCOUNTER StatRxOverflowWakeupRZ;
1211 STAMCOUNTER StatRxOverflowWakeupR3;
1212 STAMCOUNTER StatTxDescCtxNormal;
1213 STAMCOUNTER StatTxDescCtxTSE;
1214 STAMCOUNTER StatTxDescLegacy;
1215 STAMCOUNTER StatTxDescData;
1216 STAMCOUNTER StatTxDescTSEData;
1217 STAMCOUNTER StatTxPathFallback;
1218 STAMCOUNTER StatTxPathGSO;
1219 STAMCOUNTER StatTxPathRegular;
1220 STAMCOUNTER StatPHYAccesses;
1221 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1222 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1223#endif /* VBOX_WITH_STATISTICS */
1224
1225#ifdef E1K_INT_STATS
1226 /* Internal stats */
1227 uint64_t u64ArmedAt;
1228 uint64_t uStatMaxTxDelay;
1229 uint32_t uStatInt;
1230 uint32_t uStatIntTry;
1231 uint32_t uStatIntLower;
1232 uint32_t uStatNoIntICR;
1233 int32_t iStatIntLost;
1234 int32_t iStatIntLostOne;
1235 uint32_t uStatIntIMS;
1236 uint32_t uStatIntSkip;
1237 uint32_t uStatIntLate;
1238 uint32_t uStatIntMasked;
1239 uint32_t uStatIntEarly;
1240 uint32_t uStatIntRx;
1241 uint32_t uStatIntTx;
1242 uint32_t uStatIntICS;
1243 uint32_t uStatIntRDTR;
1244 uint32_t uStatIntRXDMT0;
1245 uint32_t uStatIntTXQE;
1246 uint32_t uStatTxNoRS;
1247 uint32_t uStatTxIDE;
1248 uint32_t uStatTxDelayed;
1249 uint32_t uStatTxDelayExp;
1250 uint32_t uStatTAD;
1251 uint32_t uStatTID;
1252 uint32_t uStatRAD;
1253 uint32_t uStatRID;
1254 uint32_t uStatRxFrm;
1255 uint32_t uStatTxFrm;
1256 uint32_t uStatDescCtx;
1257 uint32_t uStatDescDat;
1258 uint32_t uStatDescLeg;
1259 uint32_t uStatTx1514;
1260 uint32_t uStatTx2962;
1261 uint32_t uStatTx4410;
1262 uint32_t uStatTx5858;
1263 uint32_t uStatTx7306;
1264 uint32_t uStatTx8754;
1265 uint32_t uStatTx16384;
1266 uint32_t uStatTx32768;
1267 uint32_t uStatTxLarge;
1268 uint32_t uStatAlign;
1269#endif /* E1K_INT_STATS */
1270} E1KSTATE;
1271/** Pointer to the E1000 device state. */
1272typedef E1KSTATE *PE1KSTATE;
1273
1274/**
1275 * E1000 ring-3 device state
1276 *
1277 * @implements PDMINETWORKDOWN
1278 * @implements PDMINETWORKCONFIG
1279 * @implements PDMILEDPORTS
1280 */
1281typedef struct E1KSTATER3
1282{
1283 PDMIBASE IBase;
1284 PDMINETWORKDOWN INetworkDown;
1285 PDMINETWORKCONFIG INetworkConfig;
1286 /** LED interface */
1287 PDMILEDPORTS ILeds;
1288 /** Attached network driver. */
1289 R3PTRTYPE(PPDMIBASE) pDrvBase;
1290 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1291
1292 /** Pointer to the shared state. */
1293 R3PTRTYPE(PE1KSTATE) pShared;
1294
1295 /** Device instance. */
1296 PPDMDEVINSR3 pDevInsR3;
1297 /** Attached network driver. */
1298 PPDMINETWORKUPR3 pDrvR3;
1299 /** The scatter / gather buffer used for the current outgoing packet. */
1300 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1301
1302 /** EMT: EEPROM emulation */
1303 E1kEEPROM eeprom;
1304} E1KSTATER3;
1305/** Pointer to the E1000 ring-3 device state. */
1306typedef E1KSTATER3 *PE1KSTATER3;
1307
1308
1309/**
1310 * E1000 ring-0 device state
1311 */
1312typedef struct E1KSTATER0
1313{
1314 /** Device instance. */
1315 PPDMDEVINSR0 pDevInsR0;
1316 /** Attached network driver. */
1317 PPDMINETWORKUPR0 pDrvR0;
1318 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1319 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1320} E1KSTATER0;
1321/** Pointer to the E1000 ring-0 device state. */
1322typedef E1KSTATER0 *PE1KSTATER0;
1323
1324
1325/**
1326 * E1000 raw-mode device state
1327 */
1328typedef struct E1KSTATERC
1329{
1330 /** Device instance. */
1331 PPDMDEVINSRC pDevInsRC;
1332 /** Attached network driver. */
1333 PPDMINETWORKUPRC pDrvRC;
1334 /** The scatter / gather buffer used for the current outgoing packet. */
1335 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1336} E1KSTATERC;
1337/** Pointer to the E1000 raw-mode device state. */
1338typedef E1KSTATERC *PE1KSTATERC;
1339
1340
1341/** @def PE1KSTATECC
1342 * Pointer to the instance data for the current context. */
1343#ifdef IN_RING3
1344typedef E1KSTATER3 E1KSTATECC;
1345typedef PE1KSTATER3 PE1KSTATECC;
1346#elif defined(IN_RING0)
1347typedef E1KSTATER0 E1KSTATECC;
1348typedef PE1KSTATER0 PE1KSTATECC;
1349#elif defined(IN_RC)
1350typedef E1KSTATERC E1KSTATECC;
1351typedef PE1KSTATERC PE1KSTATECC;
1352#else
1353# error "Not IN_RING3, IN_RING0 or IN_RC"
1354#endif
1355
1356
1357#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1358
1359/* Forward declarations ******************************************************/
1360static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1361
1362/**
1363 * E1000 register read handler.
1364 */
1365typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1366/**
1367 * E1000 register write handler.
1368 */
1369typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1370
1371static FNE1KREGREAD e1kRegReadUnimplemented;
1372static FNE1KREGWRITE e1kRegWriteUnimplemented;
1373static FNE1KREGREAD e1kRegReadAutoClear;
1374static FNE1KREGREAD e1kRegReadDefault;
1375static FNE1KREGWRITE e1kRegWriteDefault;
1376#if 0 /* unused */
1377static FNE1KREGREAD e1kRegReadCTRL;
1378#endif
1379static FNE1KREGWRITE e1kRegWriteCTRL;
1380static FNE1KREGREAD e1kRegReadEECD;
1381static FNE1KREGWRITE e1kRegWriteEECD;
1382static FNE1KREGWRITE e1kRegWriteEERD;
1383static FNE1KREGWRITE e1kRegWriteMDIC;
1384static FNE1KREGREAD e1kRegReadICR;
1385static FNE1KREGWRITE e1kRegWriteICR;
1386static FNE1KREGREAD e1kRegReadICS;
1387static FNE1KREGWRITE e1kRegWriteICS;
1388static FNE1KREGWRITE e1kRegWriteIMS;
1389static FNE1KREGWRITE e1kRegWriteIMC;
1390static FNE1KREGWRITE e1kRegWriteRCTL;
1391static FNE1KREGWRITE e1kRegWritePBA;
1392static FNE1KREGWRITE e1kRegWriteRDT;
1393static FNE1KREGWRITE e1kRegWriteRDTR;
1394static FNE1KREGWRITE e1kRegWriteTDT;
1395static FNE1KREGREAD e1kRegReadMTA;
1396static FNE1KREGWRITE e1kRegWriteMTA;
1397static FNE1KREGREAD e1kRegReadRA;
1398static FNE1KREGWRITE e1kRegWriteRA;
1399static FNE1KREGREAD e1kRegReadVFTA;
1400static FNE1KREGWRITE e1kRegWriteVFTA;
1401
1402/**
1403 * Register map table.
1404 *
1405 * Override pfnRead and pfnWrite to get register-specific behavior.
1406 */
1407static const struct E1kRegMap_st
1408{
1409 /** Register offset in the register space. */
1410 uint32_t offset;
1411 /** Size in bytes. Registers of size > 4 are in fact tables. */
1412 uint32_t size;
1413 /** Readable bits. */
1414 uint32_t readable;
1415 /** Writable bits. */
1416 uint32_t writable;
1417 /** Read callback. */
1418 FNE1KREGREAD *pfnRead;
1419 /** Write callback. */
1420 FNE1KREGWRITE *pfnWrite;
1421 /** Abbreviated name. */
1422 const char *abbrev;
1423 /** Full name. */
1424 const char *name;
1425} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1426{
1427 /* offset size read mask write mask read callback write callback abbrev full name */
1428 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1429 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1430 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1431 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1432 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1433 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1434 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1435 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1436 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1437 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1438 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1439 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1440 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1441 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1442 { 0x000c8, 0x00004, 0x0001F6DF, 0xFFFFFFFF, e1kRegReadICS , e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1443 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1444 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1445 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1446 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1447 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1448 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1449 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1450 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1451 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1452 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1453 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1454 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1455 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1456 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1457 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1458 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1459 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1460 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1461 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1462 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1463 { 0x02808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1464 { 0x02810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1465 { 0x02818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1466 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1467 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1468 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1469 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1470 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1471 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1472 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1473 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1474 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1475 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1476 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1477 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1478 { 0x03808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1479 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1480 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1481 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1482 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1483 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1484 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1485 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1486 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1487 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1488 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1489 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1490 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1491 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1492 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1493 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1494 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1495 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1496 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1497 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1498 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1499 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1500 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1501 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1502 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1503 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1504 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1505 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1506 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1507 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1508 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1509 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1510 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1511 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1512 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1513 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1514 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1515 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1516 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1517 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1518 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1519 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1520 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1521 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1522 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1523 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1524 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1525 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1526 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1527 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1528 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1529 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1530 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1531 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1532 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1533 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1534 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1535 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1536 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1537 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1538 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1539 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1540 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1541 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1542 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1543 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1544 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1545 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1546 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1547 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1548 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1549 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1550 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1551 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1552 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1553 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1554 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1555 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1556 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1557 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1558 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1559 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1560 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1561 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1562 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1563};
1564
1565#ifdef LOG_ENABLED
1566
1567/**
1568 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1569 *
1570 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1571 *
1572 * @returns The buffer.
1573 *
1574 * @param u32 The word to convert into string.
1575 * @param mask Selects which bytes to convert.
1576 * @param buf Where to put the result.
1577 */
1578static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1579{
1580 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1581 {
1582 if (mask & 0xF)
1583 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1584 else
1585 *ptr = '.';
1586 }
1587 buf[8] = 0;
1588 return buf;
1589}
1590
1591/**
1592 * Returns timer name for debug purposes.
1593 *
1594 * @returns The timer name.
1595 *
1596 * @param pThis The device state structure.
1597 * @param hTimer The timer to name.
1598 */
1599DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1600{
1601 if (hTimer == pThis->hTIDTimer)
1602 return "TID";
1603 if (hTimer == pThis->hTADTimer)
1604 return "TAD";
1605 if (hTimer == pThis->hRIDTimer)
1606 return "RID";
1607 if (hTimer == pThis->hRADTimer)
1608 return "RAD";
1609 if (hTimer == pThis->hIntTimer)
1610 return "Int";
1611 if (hTimer == pThis->hTXDTimer)
1612 return "TXD";
1613 if (hTimer == pThis->hLUTimer)
1614 return "LinkUp";
1615 return "unknown";
1616}
1617
1618#endif /* LOG_ENABLED */
1619
1620/**
1621 * Arm a timer.
1622 *
1623 * @param pDevIns The device instance.
1624 * @param pThis Pointer to the device state structure.
1625 * @param hTimer The timer to arm.
1626 * @param uExpireIn Expiration interval in microseconds.
1627 */
1628DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1629{
1630 if (pThis->fLocked)
1631 return;
1632
1633 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1634 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1635 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1636 AssertRC(rc);
1637}
1638
1639#ifdef IN_RING3
1640/**
1641 * Cancel a timer.
1642 *
1643 * @param pDevIns The device instance.
1644 * @param pThis Pointer to the device state structure.
1645 * @param pTimer Pointer to the timer.
1646 */
1647DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1648{
1649 E1kLog2(("%s Stopping %s timer...\n",
1650 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1651 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1652 if (RT_FAILURE(rc))
1653 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1654 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1655 RT_NOREF_PV(pThis);
1656}
1657#endif /* IN_RING3 */
1658
1659
1660#define e1kCsEnter(ps, rcBusy) PDMDevHlpCritSectEnter(pDevIns, &(ps)->cs, (rcBusy))
1661#define e1kCsEnterReturn(ps, rcBusy) do { \
1662 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &(ps)->cs, (rcBusy)); \
1663 if (rcLock == VINF_SUCCESS) { /* likely */ } \
1664 else return rcLock; \
1665 } while (0)
1666#define e1kR3CsEnterAsserted(ps) do { \
1667 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &(ps)->cs, VERR_SEM_BUSY); \
1668 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &(ps)->cs, rcLock); \
1669 } while (0)
1670#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &(ps)->cs)
1671
1672
1673#define e1kCsRxEnter(ps, rcBusy) PDMDevHlpCritSectEnter(pDevIns, &(ps)->csRx, (rcBusy))
1674#define e1kCsRxEnterReturn(ps) do { \
1675 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &(ps)->csRx, VERR_SEM_BUSY); \
1676 AssertRCReturn(rcLock, rcLock); \
1677 } while (0)
1678#define e1kR3CsRxEnterAsserted(ps) do { \
1679 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &(ps)->csRx, VERR_SEM_BUSY); \
1680 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &(ps)->csRx, rcLock); \
1681 } while (0)
1682#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &(ps)->csRx)
1683#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &(ps)->csRx)
1684
1685
1686#ifndef E1K_WITH_TX_CS
1687# define e1kCsTxEnter(ps, rcBusy) VINF_SUCCESS
1688# define e1kR3CsTxEnterAsserted(ps) do { } while (0)
1689# define e1kCsTxLeave(ps) do { } while (0)
1690#else /* E1K_WITH_TX_CS */
1691# define e1kCsTxEnter(ps, rcBusy) PDMDevHlpCritSectEnter(pDevIns, &(ps)->csTx, (rcBusy))
1692# define e1kR3CsTxEnterAsserted(ps) do { \
1693 int const rcLock = PDMDevHlpCritSectEnter(pDevIns, &(ps)->csTx, VERR_SEM_BUSY); \
1694 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &(ps)->csTx, rcLock); \
1695 } while (0)
1696# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &(ps)->csTx)
1697# define e1kCsTxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &(ps)->csTx)
1698#endif /* E1K_WITH_TX_CS */
1699
1700
1701#ifdef E1K_WITH_TXD_CACHE
1702/*
1703 * Transmit Descriptor Register Context
1704 */
1705struct E1kTxDContext
1706{
1707 uint32_t tdlen;
1708 uint32_t tdh;
1709 uint32_t tdt;
1710};
1711typedef struct E1kTxDContext E1KTXDC, *PE1KTXDC;
1712
1713DECLINLINE(bool) e1kUpdateTxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pContext)
1714{
1715 Assert(e1kCsTxIsOwner(pThis));
1716 if (!e1kCsTxIsOwner(pThis))
1717 {
1718 memset(pContext, 0, sizeof(E1KTXDC));
1719 return false;
1720 }
1721 pContext->tdlen = TDLEN;
1722 pContext->tdh = TDH;
1723 pContext->tdt = TDT;
1724 uint32_t cTxRingSize = pContext->tdlen / sizeof(E1KTXDESC);
1725#ifdef DEBUG
1726 if (pContext->tdh >= cTxRingSize)
1727 {
1728 Log(("%s e1kUpdateTxDContext: will return false because TDH too big (%u >= %u)\n",
1729 pThis->szPrf, pContext->tdh, cTxRingSize));
1730 return VINF_SUCCESS;
1731 }
1732 if (pContext->tdt >= cTxRingSize)
1733 {
1734 Log(("%s e1kUpdateTxDContext: will return false because TDT too big (%u >= %u)\n",
1735 pThis->szPrf, pContext->tdt, cTxRingSize));
1736 return VINF_SUCCESS;
1737 }
1738#endif /* DEBUG */
1739 return pContext->tdh < cTxRingSize && pContext->tdt < cTxRingSize;
1740}
1741#endif /* E1K_WITH_TXD_CACHE */
1742#ifdef E1K_WITH_RXD_CACHE
1743/*
1744 * Receive Descriptor Register Context
1745 */
1746struct E1kRxDContext
1747{
1748 uint32_t rdlen;
1749 uint32_t rdh;
1750 uint32_t rdt;
1751};
1752typedef struct E1kRxDContext E1KRXDC, *PE1KRXDC;
1753
1754DECLINLINE(bool) e1kUpdateRxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pContext, const char *pcszCallee)
1755{
1756 Assert(e1kCsRxIsOwner(pThis));
1757 if (!e1kCsRxIsOwner(pThis))
1758 return false;
1759 pContext->rdlen = RDLEN;
1760 pContext->rdh = RDH;
1761 pContext->rdt = RDT;
1762 uint32_t cRxRingSize = pContext->rdlen / sizeof(E1KRXDESC);
1763 /*
1764 * Note that the checks for RDT are a bit different. Some guests, OS/2 for
1765 * example, intend to use all descriptors in RX ring, so they point RDT
1766 * right beyond the last descriptor in the ring. While this is not
1767 * acceptable for other registers, it works out fine for RDT.
1768 */
1769#ifdef DEBUG
1770 if (pContext->rdh >= cRxRingSize)
1771 {
1772 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDH too big (%u >= %u)\n",
1773 pThis->szPrf, pcszCallee, pContext->rdh, cRxRingSize));
1774 return VINF_SUCCESS;
1775 }
1776 if (pContext->rdt > cRxRingSize)
1777 {
1778 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDT too big (%u > %u)\n",
1779 pThis->szPrf, pcszCallee, pContext->rdt, cRxRingSize));
1780 return VINF_SUCCESS;
1781 }
1782#else /* !DEBUG */
1783 RT_NOREF(pcszCallee);
1784#endif /* !DEBUG */
1785 return pContext->rdh < cRxRingSize && pContext->rdt <= cRxRingSize; // && (RCTL & RCTL_EN);
1786}
1787#endif /* E1K_WITH_RXD_CACHE */
1788
1789/**
1790 * Wakeup the RX thread.
1791 */
1792static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1793{
1794 if ( pThis->fMaybeOutOfSpace
1795 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1796 {
1797 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1798 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1799 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1800 AssertRC(rc);
1801 }
1802}
1803
1804#ifdef IN_RING3
1805
1806/**
1807 * Hardware reset. Revert all registers to initial values.
1808 *
1809 * @param pDevIns The device instance.
1810 * @param pThis The device state structure.
1811 * @param pThisCC The current context instance data.
1812 */
1813static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1814{
1815 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1816 /* No interrupts should survive device reset, see @bugref(9556). */
1817 if (pThis->fIntRaised)
1818 {
1819 /* Lower(0) INTA(0) */
1820 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1821 pThis->fIntRaised = false;
1822 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1823 }
1824 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1825 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1826# ifdef E1K_INIT_RA0
1827 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1828 sizeof(pThis->macConfigured.au8));
1829 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1830# endif /* E1K_INIT_RA0 */
1831 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1832 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1833 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1834 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1835 Assert(GET_BITS(RCTL, BSIZE) == 0);
1836 pThis->u16RxBSize = 2048;
1837
1838 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1839 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1840 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1841
1842 /* Reset promiscuous mode */
1843 if (pThisCC->pDrvR3)
1844 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1845
1846# ifdef E1K_WITH_TXD_CACHE
1847 e1kR3CsTxEnterAsserted(pThis);
1848 pThis->nTxDFetched = 0;
1849 pThis->iTxDCurrent = 0;
1850 pThis->fGSO = false;
1851 pThis->cbTxAlloc = 0;
1852 e1kCsTxLeave(pThis);
1853# endif /* E1K_WITH_TXD_CACHE */
1854# ifdef E1K_WITH_RXD_CACHE
1855 e1kR3CsRxEnterAsserted(pThis);
1856 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1857 e1kCsRxLeave(pThis);
1858# endif /* E1K_WITH_RXD_CACHE */
1859# ifdef E1K_LSC_ON_RESET
1860 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1861 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1862 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1863# endif /* E1K_LSC_ON_RESET */
1864}
1865
1866#endif /* IN_RING3 */
1867
1868/**
1869 * Compute Internet checksum.
1870 *
1871 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1872 *
1873 * @param pThis The device state structure.
1874 * @param cpPacket The packet.
1875 * @param cb The size of the packet.
1876 * @param pszText A string denoting direction of packet transfer.
1877 *
1878 * @return The 1's complement of the 1's complement sum.
1879 *
1880 * @thread E1000_TX
1881 */
1882static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1883{
1884 uint32_t csum = 0;
1885 uint16_t *pu16 = (uint16_t *)pvBuf;
1886
1887 while (cb > 1)
1888 {
1889 csum += *pu16++;
1890 cb -= 2;
1891 }
1892 if (cb)
1893 csum += *(uint8_t*)pu16;
1894 while (csum >> 16)
1895 csum = (csum >> 16) + (csum & 0xFFFF);
1896 Assert(csum < 65536);
1897 return (uint16_t)~csum;
1898}
1899
1900/**
1901 * Dump a packet to debug log.
1902 *
1903 * @param pDevIns The device instance.
1904 * @param pThis The device state structure.
1905 * @param cpPacket The packet.
1906 * @param cb The size of the packet.
1907 * @param pszText A string denoting direction of packet transfer.
1908 * @thread E1000_TX
1909 */
1910DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1911{
1912#ifdef DEBUG
1913 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1914 {
1915 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1916 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1917 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1918 {
1919 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1920 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1921 if (*(cpPacket+14+6) == 0x6)
1922 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1923 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1924 }
1925 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1926 {
1927 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1928 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1929 if (*(cpPacket+14+6) == 0x6)
1930 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1931 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1932 }
1933 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1934 e1kCsLeave(pThis);
1935 }
1936#else
1937 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1938 {
1939 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1940 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1941 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1942 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1943 else
1944 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1945 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1946 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1947 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1948 e1kCsLeave(pThis);
1949 }
1950 RT_NOREF2(cb, pszText);
1951#endif
1952}
1953
1954/**
1955 * Determine the type of transmit descriptor.
1956 *
1957 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1958 *
1959 * @param pDesc Pointer to descriptor union.
1960 * @thread E1000_TX
1961 */
1962DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1963{
1964 if (pDesc->legacy.cmd.fDEXT)
1965 return pDesc->context.dw2.u4DTYP;
1966 return E1K_DTYP_LEGACY;
1967}
1968
1969
1970#ifdef E1K_WITH_RXD_CACHE
1971/**
1972 * Return the number of RX descriptor that belong to the hardware.
1973 *
1974 * @returns the number of available descriptors in RX ring.
1975 * @param pRxdc The receive descriptor register context.
1976 * @thread ???
1977 */
1978DECLINLINE(uint32_t) e1kGetRxLen(PE1KRXDC pRxdc)
1979{
1980 /**
1981 * Make sure RDT won't change during computation. EMT may modify RDT at
1982 * any moment.
1983 */
1984 uint32_t rdt = pRxdc->rdt;
1985 return (pRxdc->rdh > rdt ? pRxdc->rdlen/sizeof(E1KRXDESC) : 0) + rdt - pRxdc->rdh;
1986}
1987
1988DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1989{
1990 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1991 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1992}
1993
1994DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1995{
1996 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1997}
1998
1999/**
2000 * Load receive descriptors from guest memory. The caller needs to be in Rx
2001 * critical section.
2002 *
2003 * We need two physical reads in case the tail wrapped around the end of RX
2004 * descriptor ring.
2005 *
2006 * @returns the actual number of descriptors fetched.
2007 * @param pDevIns The device instance.
2008 * @param pThis The device state structure.
2009 * @thread EMT, RX
2010 */
2011DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2012{
2013 E1kLog3(("%s e1kRxDPrefetch: RDH=%x RDT=%x RDLEN=%x "
2014 "iRxDCurrent=%x nRxDFetched=%x\n",
2015 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pRxdc->rdlen, pThis->iRxDCurrent, pThis->nRxDFetched));
2016 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
2017 unsigned nDescsAvailable = e1kGetRxLen(pRxdc) - e1kRxDInCache(pThis);
2018 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
2019 unsigned nDescsTotal = pRxdc->rdlen / sizeof(E1KRXDESC);
2020 Assert(nDescsTotal != 0);
2021 if (nDescsTotal == 0)
2022 return 0;
2023 unsigned nFirstNotLoaded = (pRxdc->rdh + e1kRxDInCache(pThis)) % nDescsTotal;
2024 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2025 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2026 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2027 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2028 nFirstNotLoaded, nDescsInSingleRead));
2029 if (nDescsToFetch == 0)
2030 return 0;
2031 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2032 PDMDevHlpPCIPhysRead(pDevIns,
2033 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2034 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2035 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2036 // unsigned i, j;
2037 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2038 // {
2039 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2040 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2041 // }
2042 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2043 pThis->szPrf, nDescsInSingleRead,
2044 RDBAH, RDBAL + pRxdc->rdh * sizeof(E1KRXDESC),
2045 nFirstNotLoaded, pRxdc->rdlen, pRxdc->rdh, pRxdc->rdt));
2046 if (nDescsToFetch > nDescsInSingleRead)
2047 {
2048 PDMDevHlpPCIPhysRead(pDevIns,
2049 ((uint64_t)RDBAH << 32) + RDBAL,
2050 pFirstEmptyDesc + nDescsInSingleRead,
2051 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2052 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2053 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2054 // {
2055 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2056 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2057 // }
2058 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2059 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2060 RDBAH, RDBAL));
2061 }
2062 pThis->nRxDFetched += nDescsToFetch;
2063 return nDescsToFetch;
2064}
2065
2066# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2067/**
2068 * Dump receive descriptor to debug log.
2069 *
2070 * @param pThis The device state structure.
2071 * @param pDesc Pointer to the descriptor.
2072 * @thread E1000_RX
2073 */
2074static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
2075{
2076 RT_NOREF2(pThis, pDesc);
2077 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
2078 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
2079 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
2080 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
2081 pDesc->status.fPIF ? "PIF" : "pif",
2082 pDesc->status.fIPCS ? "IPCS" : "ipcs",
2083 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
2084 pDesc->status.fVP ? "VP" : "vp",
2085 pDesc->status.fIXSM ? "IXSM" : "ixsm",
2086 pDesc->status.fEOP ? "EOP" : "eop",
2087 pDesc->status.fDD ? "DD" : "dd",
2088 pDesc->status.fRXE ? "RXE" : "rxe",
2089 pDesc->status.fIPE ? "IPE" : "ipe",
2090 pDesc->status.fTCPE ? "TCPE" : "tcpe",
2091 pDesc->status.fCE ? "CE" : "ce",
2092 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
2093 E1K_SPEC_VLAN(pDesc->status.u16Special),
2094 E1K_SPEC_PRI(pDesc->status.u16Special)));
2095}
2096# endif /* IN_RING3 */
2097#endif /* E1K_WITH_RXD_CACHE */
2098
2099/**
2100 * Dump transmit descriptor to debug log.
2101 *
2102 * @param pThis The device state structure.
2103 * @param pDesc Pointer to descriptor union.
2104 * @param pszDir A string denoting direction of descriptor transfer
2105 * @thread E1000_TX
2106 */
2107static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
2108 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
2109{
2110 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
2111
2112 /*
2113 * Unfortunately we cannot use our format handler here, we want R0 logging
2114 * as well.
2115 */
2116 switch (e1kGetDescType(pDesc))
2117 {
2118 case E1K_DTYP_CONTEXT:
2119 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2120 pThis->szPrf, pszDir, pszDir));
2121 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2122 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2123 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2124 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2125 pDesc->context.dw2.fIDE ? " IDE":"",
2126 pDesc->context.dw2.fRS ? " RS" :"",
2127 pDesc->context.dw2.fTSE ? " TSE":"",
2128 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2129 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2130 pDesc->context.dw2.u20PAYLEN,
2131 pDesc->context.dw3.u8HDRLEN,
2132 pDesc->context.dw3.u16MSS,
2133 pDesc->context.dw3.fDD?"DD":""));
2134 break;
2135 case E1K_DTYP_DATA:
2136 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2137 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2138 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2139 pDesc->data.u64BufAddr,
2140 pDesc->data.cmd.u20DTALEN));
2141 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2142 pDesc->data.cmd.fIDE ? " IDE" :"",
2143 pDesc->data.cmd.fVLE ? " VLE" :"",
2144 pDesc->data.cmd.fRPS ? " RPS" :"",
2145 pDesc->data.cmd.fRS ? " RS" :"",
2146 pDesc->data.cmd.fTSE ? " TSE" :"",
2147 pDesc->data.cmd.fIFCS? " IFCS":"",
2148 pDesc->data.cmd.fEOP ? " EOP" :"",
2149 pDesc->data.dw3.fDD ? " DD" :"",
2150 pDesc->data.dw3.fEC ? " EC" :"",
2151 pDesc->data.dw3.fLC ? " LC" :"",
2152 pDesc->data.dw3.fTXSM? " TXSM":"",
2153 pDesc->data.dw3.fIXSM? " IXSM":"",
2154 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2155 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2156 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2157 break;
2158 case E1K_DTYP_LEGACY:
2159 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2160 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2161 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2162 pDesc->data.u64BufAddr,
2163 pDesc->legacy.cmd.u16Length));
2164 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2165 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2166 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2167 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2168 pDesc->legacy.cmd.fRS ? " RS" :"",
2169 pDesc->legacy.cmd.fIC ? " IC" :"",
2170 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2171 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2172 pDesc->legacy.dw3.fDD ? " DD" :"",
2173 pDesc->legacy.dw3.fEC ? " EC" :"",
2174 pDesc->legacy.dw3.fLC ? " LC" :"",
2175 pDesc->legacy.cmd.u8CSO,
2176 pDesc->legacy.dw3.u8CSS,
2177 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2178 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2179 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2180 break;
2181 default:
2182 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2183 pThis->szPrf, pszDir, pszDir));
2184 break;
2185 }
2186}
2187
2188/**
2189 * Raise an interrupt later.
2190 *
2191 * @param pThis The device state structure.
2192 */
2193DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2194{
2195 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2196 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2197}
2198
2199/**
2200 * Raise interrupt if not masked.
2201 *
2202 * @param pThis The device state structure.
2203 */
2204static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause)
2205{
2206 /* Do NOT use e1kCsEnterReturn here as most callers doesn't check the
2207 status code. They'll pass a negative rcBusy. */
2208 int rc = e1kCsEnter(pThis, rcBusy);
2209 if (RT_LIKELY(rc == VINF_SUCCESS))
2210 { /* likely */ }
2211 else
2212 {
2213 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, &pThis->cs, rc);
2214 return rc;
2215 }
2216
2217 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2218 ICR |= u32IntCause;
2219 if (ICR & IMS)
2220 {
2221 if (pThis->fIntRaised)
2222 {
2223 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2224 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2225 pThis->szPrf, ICR & IMS));
2226 }
2227 else
2228 {
2229 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2230 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2231 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2232 {
2233 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2234 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2235 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2236 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2237 }
2238 else
2239 {
2240
2241 /* Since we are delivering the interrupt now
2242 * there is no need to do it later -- stop the timer.
2243 */
2244 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2245 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2246 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2247 /* Got at least one unmasked interrupt cause */
2248 pThis->fIntRaised = true;
2249 /* Raise(1) INTA(0) */
2250 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2251 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2252 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2253 pThis->szPrf, ICR & IMS));
2254 }
2255 }
2256 }
2257 else
2258 {
2259 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2260 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2261 pThis->szPrf, ICR, IMS));
2262 }
2263 e1kCsLeave(pThis);
2264 return VINF_SUCCESS;
2265}
2266
2267/**
2268 * Compute the physical address of the descriptor.
2269 *
2270 * @returns the physical address of the descriptor.
2271 *
2272 * @param baseHigh High-order 32 bits of descriptor table address.
2273 * @param baseLow Low-order 32 bits of descriptor table address.
2274 * @param idxDesc The descriptor index in the table.
2275 */
2276DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2277{
2278 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2279 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2280}
2281
2282#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2283/**
2284 * Advance the head pointer of the receive descriptor queue.
2285 *
2286 * @remarks RDH always points to the next available RX descriptor.
2287 *
2288 * @param pDevIns The device instance.
2289 * @param pThis The device state structure.
2290 */
2291DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2292{
2293 Assert(e1kCsRxIsOwner(pThis));
2294 //e1kR3CsEnterAsserted(pThis);
2295 if (++pRxdc->rdh * sizeof(E1KRXDESC) >= pRxdc->rdlen)
2296 pRxdc->rdh = 0;
2297 RDH = pRxdc->rdh; /* Sync the actual register and RXDC */
2298#ifdef E1K_WITH_RXD_CACHE
2299 /*
2300 * We need to fetch descriptors now as the guest may advance RDT all the way
2301 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2302 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2303 * check if the receiver is enabled. It must be, otherwise we won't get here
2304 * in the first place.
2305 *
2306 * Note that we should have moved both RDH and iRxDCurrent by now.
2307 */
2308 if (e1kRxDIsCacheEmpty(pThis))
2309 {
2310 /* Cache is empty, reset it and check if we can fetch more. */
2311 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2312 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2313 "iRxDCurrent=%x nRxDFetched=%x\n",
2314 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pThis->iRxDCurrent, pThis->nRxDFetched));
2315 e1kRxDPrefetch(pDevIns, pThis, pRxdc);
2316 }
2317#endif /* E1K_WITH_RXD_CACHE */
2318 /*
2319 * Compute current receive queue length and fire RXDMT0 interrupt
2320 * if we are low on receive buffers
2321 */
2322 uint32_t uRQueueLen = pRxdc->rdh>pRxdc->rdt ? pRxdc->rdlen/sizeof(E1KRXDESC)-pRxdc->rdh+pRxdc->rdt : pRxdc->rdt-pRxdc->rdh;
2323 /*
2324 * The minimum threshold is controlled by RDMTS bits of RCTL:
2325 * 00 = 1/2 of RDLEN
2326 * 01 = 1/4 of RDLEN
2327 * 10 = 1/8 of RDLEN
2328 * 11 = reserved
2329 */
2330 uint32_t uMinRQThreshold = pRxdc->rdlen / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2331 if (uRQueueLen <= uMinRQThreshold)
2332 {
2333 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2334 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2335 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2336 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2337 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2338 }
2339 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2340 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen));
2341 //e1kCsLeave(pThis);
2342}
2343#endif /* IN_RING3 */
2344
2345#ifdef E1K_WITH_RXD_CACHE
2346
2347# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2348
2349/**
2350 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2351 * RX ring if the cache is empty.
2352 *
2353 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2354 * go out of sync with RDH which will cause trouble when EMT checks if the
2355 * cache is empty to do pre-fetch @bugref(6217).
2356 *
2357 * @param pDevIns The device instance.
2358 * @param pThis The device state structure.
2359 * @thread RX
2360 */
2361DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2362{
2363 Assert(e1kCsRxIsOwner(pThis));
2364 /* Check the cache first. */
2365 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2366 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2367 /* Cache is empty, reset it and check if we can fetch more. */
2368 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2369 if (e1kRxDPrefetch(pDevIns, pThis, pRxdc))
2370 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2371 /* Out of Rx descriptors. */
2372 return NULL;
2373}
2374
2375
2376/**
2377 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2378 * pointer. The descriptor gets written back to the RXD ring.
2379 *
2380 * @param pDevIns The device instance.
2381 * @param pThis The device state structure.
2382 * @param pDesc The descriptor being "returned" to the RX ring.
2383 * @thread RX
2384 */
2385DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc, PE1KRXDC pRxdc)
2386{
2387 Assert(e1kCsRxIsOwner(pThis));
2388 pThis->iRxDCurrent++;
2389 // Assert(pDesc >= pThis->aRxDescriptors);
2390 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2391 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2392 // uint32_t rdh = RDH;
2393 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2394 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, pRxdc->rdh), pDesc, sizeof(E1KRXDESC));
2395 /*
2396 * We need to print the descriptor before advancing RDH as it may fetch new
2397 * descriptors into the cache.
2398 */
2399 e1kPrintRDesc(pThis, pDesc);
2400 e1kAdvanceRDH(pDevIns, pThis, pRxdc);
2401}
2402
2403/**
2404 * Store a fragment of received packet at the specifed address.
2405 *
2406 * @param pDevIns The device instance.
2407 * @param pThis The device state structure.
2408 * @param pDesc The next available RX descriptor.
2409 * @param pvBuf The fragment.
2410 * @param cb The size of the fragment.
2411 */
2412static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2413{
2414 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2415 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2416 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2417 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2418 pDesc->u16Length = (uint16_t)cb;
2419 Assert(pDesc->u16Length == cb);
2420 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2421 RT_NOREF(pThis);
2422}
2423
2424# endif /* IN_RING3 */
2425
2426#else /* !E1K_WITH_RXD_CACHE */
2427
2428/**
2429 * Store a fragment of received packet that fits into the next available RX
2430 * buffer.
2431 *
2432 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2433 *
2434 * @param pDevIns The device instance.
2435 * @param pThis The device state structure.
2436 * @param pDesc The next available RX descriptor.
2437 * @param pvBuf The fragment.
2438 * @param cb The size of the fragment.
2439 */
2440static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2441{
2442 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2443 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2444 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2445 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2446 /* Write back the descriptor */
2447 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2448 e1kPrintRDesc(pThis, pDesc);
2449 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2450 /* Advance head */
2451 e1kAdvanceRDH(pDevIns, pThis);
2452 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2453 if (pDesc->status.fEOP)
2454 {
2455 /* Complete packet has been stored -- it is time to let the guest know. */
2456#ifdef E1K_USE_RX_TIMERS
2457 if (RDTR)
2458 {
2459 /* Arm the timer to fire in RDTR usec (discard .024) */
2460 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2461 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2462 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2463 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2464 }
2465 else
2466 {
2467#endif
2468 /* 0 delay means immediate interrupt */
2469 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2470 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2471#ifdef E1K_USE_RX_TIMERS
2472 }
2473#endif
2474 }
2475 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2476}
2477
2478#endif /* !E1K_WITH_RXD_CACHE */
2479
2480/**
2481 * Returns true if it is a broadcast packet.
2482 *
2483 * @returns true if destination address indicates broadcast.
2484 * @param pvBuf The ethernet packet.
2485 */
2486DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2487{
2488 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2489 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2490}
2491
2492/**
2493 * Returns true if it is a multicast packet.
2494 *
2495 * @remarks returns true for broadcast packets as well.
2496 * @returns true if destination address indicates multicast.
2497 * @param pvBuf The ethernet packet.
2498 */
2499DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2500{
2501 return (*(char*)pvBuf) & 1;
2502}
2503
2504#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2505/**
2506 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2507 *
2508 * @remarks We emulate checksum offloading for major packets types only.
2509 *
2510 * @returns VBox status code.
2511 * @param pThis The device state structure.
2512 * @param pFrame The available data.
2513 * @param cb Number of bytes available in the buffer.
2514 * @param status Bit fields containing status info.
2515 */
2516static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2517{
2518 /** @todo
2519 * It is not safe to bypass checksum verification for packets coming
2520 * from real wire. We currently unable to tell where packets are
2521 * coming from so we tell the driver to ignore our checksum flags
2522 * and do verification in software.
2523 */
2524# if 0
2525 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2526
2527 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2528
2529 switch (uEtherType)
2530 {
2531 case 0x800: /* IPv4 */
2532 {
2533 pStatus->fIXSM = false;
2534 pStatus->fIPCS = true;
2535 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2536 /* TCP/UDP checksum offloading works with TCP and UDP only */
2537 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2538 break;
2539 }
2540 case 0x86DD: /* IPv6 */
2541 pStatus->fIXSM = false;
2542 pStatus->fIPCS = false;
2543 pStatus->fTCPCS = true;
2544 break;
2545 default: /* ARP, VLAN, etc. */
2546 pStatus->fIXSM = true;
2547 break;
2548 }
2549# else
2550 pStatus->fIXSM = true;
2551 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2552# endif
2553 return VINF_SUCCESS;
2554}
2555#endif /* IN_RING3 */
2556
2557/**
2558 * Pad and store received packet.
2559 *
2560 * @remarks Make sure that the packet appears to upper layer as one coming
2561 * from real Ethernet: pad it and insert FCS.
2562 *
2563 * @returns VBox status code.
2564 * @param pDevIns The device instance.
2565 * @param pThis The device state structure.
2566 * @param pvBuf The available data.
2567 * @param cb Number of bytes available in the buffer.
2568 * @param status Bit fields containing status info.
2569 */
2570static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2571{
2572#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2573 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2574 uint8_t *ptr = rxPacket;
2575# ifdef E1K_WITH_RXD_CACHE
2576 E1KRXDC rxdc;
2577# endif /* E1K_WITH_RXD_CACHE */
2578
2579 e1kCsRxEnterReturn(pThis);
2580# ifdef E1K_WITH_RXD_CACHE
2581 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2582 {
2583 e1kCsRxLeave(pThis);
2584 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2585 return VINF_SUCCESS;
2586 }
2587# endif /* E1K_WITH_RXD_CACHE */
2588
2589 if (cb > 70) /* unqualified guess */
2590 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2591
2592 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2593 Assert(cb > 16);
2594 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2595 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2596 if (status.fVP)
2597 {
2598 /* VLAN packet -- strip VLAN tag in VLAN mode */
2599 if ((CTRL & CTRL_VME) && cb > 16)
2600 {
2601 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2602 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2603 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2604 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2605 cb -= 4;
2606 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2607 pThis->szPrf, status.u16Special, cb));
2608 }
2609 else
2610 {
2611 status.fVP = false; /* Set VP only if we stripped the tag */
2612 memcpy(rxPacket, pvBuf, cb);
2613 }
2614 }
2615 else
2616 memcpy(rxPacket, pvBuf, cb);
2617 /* Pad short packets */
2618 if (cb < 60)
2619 {
2620 memset(rxPacket + cb, 0, 60 - cb);
2621 cb = 60;
2622 }
2623 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2624 {
2625 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2626 /*
2627 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2628 * is ignored by most of drivers we may as well save us the trouble
2629 * of calculating it (see EthernetCRC CFGM parameter).
2630 */
2631 if (pThis->fEthernetCRC)
2632 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2633 cb += sizeof(uint32_t);
2634 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2635 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2636 }
2637 /* Compute checksum of complete packet */
2638 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2639 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2640 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2641
2642 /* Update stats */
2643 E1K_INC_CNT32(GPRC);
2644 if (e1kIsBroadcast(pvBuf))
2645 E1K_INC_CNT32(BPRC);
2646 else if (e1kIsMulticast(pvBuf))
2647 E1K_INC_CNT32(MPRC);
2648 /* Update octet receive counter */
2649 E1K_ADD_CNT64(GORCL, GORCH, cb);
2650 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2651 if (cb == 64)
2652 E1K_INC_CNT32(PRC64);
2653 else if (cb < 128)
2654 E1K_INC_CNT32(PRC127);
2655 else if (cb < 256)
2656 E1K_INC_CNT32(PRC255);
2657 else if (cb < 512)
2658 E1K_INC_CNT32(PRC511);
2659 else if (cb < 1024)
2660 E1K_INC_CNT32(PRC1023);
2661 else
2662 E1K_INC_CNT32(PRC1522);
2663
2664 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2665
2666# ifdef E1K_WITH_RXD_CACHE
2667 while (cb > 0)
2668 {
2669 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis, &rxdc);
2670
2671 if (pDesc == NULL)
2672 {
2673 E1kLog(("%s Out of receive buffers, dropping the packet "
2674 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2675 pThis->szPrf, cb, e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt));
2676 break;
2677 }
2678# else /* !E1K_WITH_RXD_CACHE */
2679 if (RDH == RDT)
2680 {
2681 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2682 pThis->szPrf));
2683 }
2684 /* Store the packet to receive buffers */
2685 while (RDH != RDT)
2686 {
2687 /* Load the descriptor pointed by head */
2688 E1KRXDESC desc, *pDesc = &desc;
2689 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2690# endif /* !E1K_WITH_RXD_CACHE */
2691 if (pDesc->u64BufAddr)
2692 {
2693 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2694
2695 /* Update descriptor */
2696 pDesc->status = status;
2697 pDesc->u16Checksum = checksum;
2698 pDesc->status.fDD = true;
2699
2700 /*
2701 * We need to leave Rx critical section here or we risk deadlocking
2702 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2703 * page or has an access handler associated with it.
2704 * Note that it is safe to leave the critical section here since
2705 * e1kRegWriteRDT() never modifies RDH. It never touches already
2706 * fetched RxD cache entries either.
2707 */
2708 if (cb > u16RxBufferSize)
2709 {
2710 pDesc->status.fEOP = false;
2711 e1kCsRxLeave(pThis);
2712 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2713 e1kCsRxEnterReturn(pThis);
2714# ifdef E1K_WITH_RXD_CACHE
2715 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2716 {
2717 e1kCsRxLeave(pThis);
2718 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2719 return VINF_SUCCESS;
2720 }
2721# endif /* E1K_WITH_RXD_CACHE */
2722 ptr += u16RxBufferSize;
2723 cb -= u16RxBufferSize;
2724 }
2725 else
2726 {
2727 pDesc->status.fEOP = true;
2728 e1kCsRxLeave(pThis);
2729 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2730# ifdef E1K_WITH_RXD_CACHE
2731 e1kCsRxEnterReturn(pThis);
2732 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2733 {
2734 e1kCsRxLeave(pThis);
2735 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2736 return VINF_SUCCESS;
2737 }
2738 cb = 0;
2739# else /* !E1K_WITH_RXD_CACHE */
2740 pThis->led.Actual.s.fReading = 0;
2741 return VINF_SUCCESS;
2742# endif /* !E1K_WITH_RXD_CACHE */
2743 }
2744 /*
2745 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2746 * is not defined.
2747 */
2748 }
2749# ifdef E1K_WITH_RXD_CACHE
2750 /* Write back the descriptor. */
2751 pDesc->status.fDD = true;
2752 e1kRxDPut(pDevIns, pThis, pDesc, &rxdc);
2753# else /* !E1K_WITH_RXD_CACHE */
2754 else
2755 {
2756 /* Write back the descriptor. */
2757 pDesc->status.fDD = true;
2758 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2759 e1kAdvanceRDH(pDevIns, pThis);
2760 }
2761# endif /* !E1K_WITH_RXD_CACHE */
2762 }
2763
2764 if (cb > 0)
2765 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2766
2767 pThis->led.Actual.s.fReading = 0;
2768
2769 e1kCsRxLeave(pThis);
2770# ifdef E1K_WITH_RXD_CACHE
2771 /* Complete packet has been stored -- it is time to let the guest know. */
2772# ifdef E1K_USE_RX_TIMERS
2773 if (RDTR)
2774 {
2775 /* Arm the timer to fire in RDTR usec (discard .024) */
2776 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2777 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2778 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2779 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2780 }
2781 else
2782 {
2783# endif /* E1K_USE_RX_TIMERS */
2784 /* 0 delay means immediate interrupt */
2785 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2786 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2787# ifdef E1K_USE_RX_TIMERS
2788 }
2789# endif /* E1K_USE_RX_TIMERS */
2790# endif /* E1K_WITH_RXD_CACHE */
2791
2792 return VINF_SUCCESS;
2793#else /* !IN_RING3 */
2794 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2795 return VERR_INTERNAL_ERROR_2;
2796#endif /* !IN_RING3 */
2797}
2798
2799
2800#ifdef IN_RING3
2801/**
2802 * Bring the link up after the configured delay, 5 seconds by default.
2803 *
2804 * @param pDevIns The device instance.
2805 * @param pThis The device state structure.
2806 * @thread any
2807 */
2808DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2809{
2810 E1kLog(("%s Will bring up the link in %d seconds...\n",
2811 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2812 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2813}
2814
2815/**
2816 * Bring up the link immediately.
2817 *
2818 * @param pDevIns The device instance.
2819 * @param pThis The device state structure.
2820 * @param pThisCC The current context instance data.
2821 */
2822DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2823{
2824 E1kLog(("%s Link is up\n", pThis->szPrf));
2825 STATUS |= STATUS_LU;
2826 Phy::setLinkStatus(&pThis->phy, true);
2827 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2828 if (pThisCC->pDrvR3)
2829 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2830 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2831 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2832}
2833
2834/**
2835 * Bring down the link immediately.
2836 *
2837 * @param pDevIns The device instance.
2838 * @param pThis The device state structure.
2839 * @param pThisCC The current context instance data.
2840 */
2841DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2842{
2843 E1kLog(("%s Link is down\n", pThis->szPrf));
2844 STATUS &= ~STATUS_LU;
2845#ifdef E1K_LSC_ON_RESET
2846 Phy::setLinkStatus(&pThis->phy, false);
2847#endif /* E1K_LSC_ON_RESET */
2848 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2849 if (pThisCC->pDrvR3)
2850 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2851}
2852
2853/**
2854 * Bring down the link temporarily.
2855 *
2856 * @param pDevIns The device instance.
2857 * @param pThis The device state structure.
2858 * @param pThisCC The current context instance data.
2859 */
2860DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2861{
2862 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2863 STATUS &= ~STATUS_LU;
2864 Phy::setLinkStatus(&pThis->phy, false);
2865 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2866 /*
2867 * Notifying the associated driver that the link went down (even temporarily)
2868 * seems to be the right thing, but it was not done before. This may cause
2869 * a regression if the driver does not expect the link to go down as a result
2870 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2871 * of code notified the driver that the link was up! See @bugref{7057}.
2872 */
2873 if (pThisCC->pDrvR3)
2874 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2875 e1kBringLinkUpDelayed(pDevIns, pThis);
2876}
2877#endif /* IN_RING3 */
2878
2879#if 0 /* unused */
2880/**
2881 * Read handler for Device Status register.
2882 *
2883 * Get the link status from PHY.
2884 *
2885 * @returns VBox status code.
2886 *
2887 * @param pThis The device state structure.
2888 * @param offset Register offset in memory-mapped frame.
2889 * @param index Register index in register array.
2890 * @param mask Used to implement partial reads (8 and 16-bit).
2891 */
2892static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2893{
2894 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2895 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2896 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2897 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2898 {
2899 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2900 if (Phy::readMDIO(&pThis->phy))
2901 *pu32Value = CTRL | CTRL_MDIO;
2902 else
2903 *pu32Value = CTRL & ~CTRL_MDIO;
2904 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2905 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2906 }
2907 else
2908 {
2909 /* MDIO pin is used for output, ignore it */
2910 *pu32Value = CTRL;
2911 }
2912 return VINF_SUCCESS;
2913}
2914#endif /* unused */
2915
2916/**
2917 * A helper function to detect the link state to the other side of "the wire".
2918 *
2919 * When deciding to bring up the link we need to take into account both if the
2920 * cable is connected and if our device is actually connected to the outside
2921 * world. If no driver is attached we won't be able to allocate TX buffers,
2922 * which will prevent us from TX descriptor processing, which will result in
2923 * "TX unit hang" in the guest.
2924 *
2925 * @returns true if the device is connected to something.
2926 *
2927 * @param pDevIns The device instance.
2928 */
2929DECLINLINE(bool) e1kIsConnected(PPDMDEVINS pDevIns)
2930{
2931 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2932 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2933 return pThis->fCableConnected && pThisCC->CTX_SUFF(pDrv);
2934}
2935
2936/**
2937 * A callback used by PHY to indicate that the link needs to be updated due to
2938 * reset of PHY.
2939 *
2940 * @param pDevIns The device instance.
2941 * @thread any
2942 */
2943void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2944{
2945 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2946
2947 /* Make sure we have cable connected and MAC can talk to PHY */
2948 if (e1kIsConnected(pDevIns) && (CTRL & CTRL_SLU))
2949 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2950}
2951
2952/**
2953 * Write handler for Device Control register.
2954 *
2955 * Handles reset.
2956 *
2957 * @param pThis The device state structure.
2958 * @param offset Register offset in memory-mapped frame.
2959 * @param index Register index in register array.
2960 * @param value The value to store.
2961 * @param mask Used to implement partial writes (8 and 16-bit).
2962 * @thread EMT
2963 */
2964static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2965{
2966 int rc = VINF_SUCCESS;
2967
2968 if (value & CTRL_RESET)
2969 { /* RST */
2970#ifndef IN_RING3
2971 return VINF_IOM_R3_MMIO_WRITE;
2972#else
2973 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2974#endif
2975 }
2976 else
2977 {
2978#ifdef E1K_LSC_ON_SLU
2979 /*
2980 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2981 * the link is down and the cable is connected, and if they are we
2982 * bring the link up, see @bugref{8624}.
2983 */
2984 if ( (value & CTRL_SLU)
2985 && !(CTRL & CTRL_SLU)
2986 && pThis->fCableConnected
2987 && !(STATUS & STATUS_LU))
2988 {
2989 /* It should take about 2 seconds for the link to come up */
2990 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2991 }
2992#else /* !E1K_LSC_ON_SLU */
2993 if ( (value & CTRL_SLU)
2994 && !(CTRL & CTRL_SLU)
2995 && e1kIsConnected(pDevIns)
2996 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2997 {
2998 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2999 STATUS |= STATUS_LU;
3000 }
3001#endif /* !E1K_LSC_ON_SLU */
3002 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
3003 {
3004 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
3005 }
3006 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
3007 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
3008 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
3009 if (value & CTRL_MDC)
3010 {
3011 if (value & CTRL_MDIO_DIR)
3012 {
3013 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
3014 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
3015 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
3016 }
3017 else
3018 {
3019 if (Phy::readMDIO(&pThis->phy))
3020 value |= CTRL_MDIO;
3021 else
3022 value &= ~CTRL_MDIO;
3023 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
3024 }
3025 }
3026 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3027 }
3028
3029 return rc;
3030}
3031
3032/**
3033 * Write handler for EEPROM/Flash Control/Data register.
3034 *
3035 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
3036 *
3037 * @param pThis The device state structure.
3038 * @param offset Register offset in memory-mapped frame.
3039 * @param index Register index in register array.
3040 * @param value The value to store.
3041 * @param mask Used to implement partial writes (8 and 16-bit).
3042 * @thread EMT
3043 */
3044static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3045{
3046 RT_NOREF(pDevIns, offset, index);
3047#ifdef IN_RING3
3048 /* So far we are concerned with lower byte only */
3049 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3050 {
3051 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
3052 /* Note: 82543GC does not need to request EEPROM access */
3053 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
3054 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3055 pThisCC->eeprom.write(value & EECD_EE_WIRES);
3056 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
3057 }
3058 if (value & EECD_EE_REQ)
3059 EECD |= EECD_EE_REQ|EECD_EE_GNT;
3060 else
3061 EECD &= ~EECD_EE_GNT;
3062 //e1kRegWriteDefault(pThis, offset, index, value );
3063
3064 return VINF_SUCCESS;
3065#else /* !IN_RING3 */
3066 RT_NOREF(pThis, value);
3067 return VINF_IOM_R3_MMIO_WRITE;
3068#endif /* !IN_RING3 */
3069}
3070
3071/**
3072 * Read handler for EEPROM/Flash Control/Data register.
3073 *
3074 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
3075 *
3076 * @returns VBox status code.
3077 *
3078 * @param pThis The device state structure.
3079 * @param offset Register offset in memory-mapped frame.
3080 * @param index Register index in register array.
3081 * @param mask Used to implement partial reads (8 and 16-bit).
3082 * @thread EMT
3083 */
3084static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3085{
3086#ifdef IN_RING3
3087 uint32_t value = 0; /* Get rid of false positive in parfait. */
3088 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3089 if (RT_SUCCESS(rc))
3090 {
3091 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3092 {
3093 /* Note: 82543GC does not need to request EEPROM access */
3094 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
3095 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3096 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3097 value |= pThisCC->eeprom.read();
3098 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3099 }
3100 *pu32Value = value;
3101 }
3102
3103 return rc;
3104#else /* !IN_RING3 */
3105 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
3106 return VINF_IOM_R3_MMIO_READ;
3107#endif /* !IN_RING3 */
3108}
3109
3110/**
3111 * Write handler for EEPROM Read register.
3112 *
3113 * Handles EEPROM word access requests, reads EEPROM and stores the result
3114 * into DATA field.
3115 *
3116 * @param pThis The device state structure.
3117 * @param offset Register offset in memory-mapped frame.
3118 * @param index Register index in register array.
3119 * @param value The value to store.
3120 * @param mask Used to implement partial writes (8 and 16-bit).
3121 * @thread EMT
3122 */
3123static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3124{
3125#ifdef IN_RING3
3126 /* Make use of 'writable' and 'readable' masks. */
3127 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3128 /* DONE and DATA are set only if read was triggered by START. */
3129 if (value & EERD_START)
3130 {
3131 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3132 uint16_t tmp;
3133 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3134 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
3135 SET_BITS(EERD, DATA, tmp);
3136 EERD |= EERD_DONE;
3137 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3138 }
3139
3140 return VINF_SUCCESS;
3141#else /* !IN_RING3 */
3142 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
3143 return VINF_IOM_R3_MMIO_WRITE;
3144#endif /* !IN_RING3 */
3145}
3146
3147
3148/**
3149 * Write handler for MDI Control register.
3150 *
3151 * Handles PHY read/write requests; forwards requests to internal PHY device.
3152 *
3153 * @param pThis The device state structure.
3154 * @param offset Register offset in memory-mapped frame.
3155 * @param index Register index in register array.
3156 * @param value The value to store.
3157 * @param mask Used to implement partial writes (8 and 16-bit).
3158 * @thread EMT
3159 */
3160static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3161{
3162 if (value & MDIC_INT_EN)
3163 {
3164 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
3165 pThis->szPrf));
3166 }
3167 else if (value & MDIC_READY)
3168 {
3169 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3170 pThis->szPrf));
3171 }
3172 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3173 {
3174 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3175 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3176 /*
3177 * Some drivers scan the MDIO bus for a PHY. We can work with these
3178 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3179 * at the requested address, see @bugref{7346}.
3180 */
3181 MDIC = MDIC_READY | MDIC_ERROR;
3182 }
3183 else
3184 {
3185 /* Store the value */
3186 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3187 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3188 /* Forward op to PHY */
3189 if (value & MDIC_OP_READ)
3190 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3191 else
3192 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3193 /* Let software know that we are done */
3194 MDIC |= MDIC_READY;
3195 }
3196
3197 return VINF_SUCCESS;
3198}
3199
3200/**
3201 * Write handler for Interrupt Cause Read register.
3202 *
3203 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3204 *
3205 * @param pThis The device state structure.
3206 * @param offset Register offset in memory-mapped frame.
3207 * @param index Register index in register array.
3208 * @param value The value to store.
3209 * @param mask Used to implement partial writes (8 and 16-bit).
3210 * @thread EMT
3211 */
3212static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3213{
3214 ICR &= ~value;
3215
3216 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3217 return VINF_SUCCESS;
3218}
3219
3220/**
3221 * Read handler for Interrupt Cause Read register.
3222 *
3223 * Reading this register acknowledges all interrupts.
3224 *
3225 * @returns VBox status code.
3226 *
3227 * @param pThis The device state structure.
3228 * @param offset Register offset in memory-mapped frame.
3229 * @param index Register index in register array.
3230 * @param mask Not used.
3231 * @thread EMT
3232 */
3233static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3234{
3235 e1kCsEnterReturn(pThis, VINF_IOM_R3_MMIO_READ);
3236
3237 uint32_t value = 0;
3238 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3239 if (RT_SUCCESS(rc))
3240 {
3241 if (value)
3242 {
3243 if (!pThis->fIntRaised)
3244 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3245 /*
3246 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3247 * with disabled interrupts.
3248 */
3249 //if (IMS)
3250 if (1)
3251 {
3252 /*
3253 * Interrupts were enabled -- we are supposedly at the very
3254 * beginning of interrupt handler
3255 */
3256 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3257 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3258 /* Clear all pending interrupts */
3259 ICR = 0;
3260 pThis->fIntRaised = false;
3261 /* Lower(0) INTA(0) */
3262 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3263
3264 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3265 if (pThis->fIntMaskUsed)
3266 pThis->fDelayInts = true;
3267 }
3268 else
3269 {
3270 /*
3271 * Interrupts are disabled -- in windows guests ICR read is done
3272 * just before re-enabling interrupts
3273 */
3274 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3275 }
3276 }
3277 *pu32Value = value;
3278 }
3279 e1kCsLeave(pThis);
3280
3281 return rc;
3282}
3283
3284/**
3285 * Read handler for Interrupt Cause Set register.
3286 *
3287 * VxWorks driver uses this undocumented feature of real H/W to read ICR without acknowledging interrupts.
3288 *
3289 * @returns VBox status code.
3290 *
3291 * @param pThis The device state structure.
3292 * @param offset Register offset in memory-mapped frame.
3293 * @param index Register index in register array.
3294 * @param pu32Value Where to store the value of the register.
3295 * @thread EMT
3296 */
3297static int e1kRegReadICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3298{
3299 RT_NOREF_PV(index);
3300 return e1kRegReadDefault(pDevIns, pThis, offset, ICR_IDX, pu32Value);
3301}
3302
3303/**
3304 * Write handler for Interrupt Cause Set register.
3305 *
3306 * Bits corresponding to 1s in 'value' will be set in ICR register.
3307 *
3308 * @param pThis The device state structure.
3309 * @param offset Register offset in memory-mapped frame.
3310 * @param index Register index in register array.
3311 * @param value The value to store.
3312 * @param mask Used to implement partial writes (8 and 16-bit).
3313 * @thread EMT
3314 */
3315static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3316{
3317 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3318 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3319 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3320}
3321
3322/**
3323 * Write handler for Interrupt Mask Set register.
3324 *
3325 * Will trigger pending interrupts.
3326 *
3327 * @param pThis The device state structure.
3328 * @param offset Register offset in memory-mapped frame.
3329 * @param index Register index in register array.
3330 * @param value The value to store.
3331 * @param mask Used to implement partial writes (8 and 16-bit).
3332 * @thread EMT
3333 */
3334static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3335{
3336 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3337
3338 IMS |= value;
3339 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3340 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3341 /*
3342 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3343 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3344 */
3345 if ((ICR & IMS) && !pThis->fLocked)
3346 {
3347 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3348 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3349 }
3350
3351 return VINF_SUCCESS;
3352}
3353
3354/**
3355 * Write handler for Interrupt Mask Clear register.
3356 *
3357 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3358 *
3359 * @param pThis The device state structure.
3360 * @param offset Register offset in memory-mapped frame.
3361 * @param index Register index in register array.
3362 * @param value The value to store.
3363 * @param mask Used to implement partial writes (8 and 16-bit).
3364 * @thread EMT
3365 */
3366static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3367{
3368 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3369
3370 e1kCsEnterReturn(pThis, VINF_IOM_R3_MMIO_WRITE);
3371 if (pThis->fIntRaised)
3372 {
3373 /*
3374 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3375 * Windows to freeze since it may receive an interrupt while still in the very beginning
3376 * of interrupt handler.
3377 */
3378 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3379 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3380 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3381 /* Lower(0) INTA(0) */
3382 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3383 pThis->fIntRaised = false;
3384 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3385 }
3386 IMS &= ~value;
3387 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3388 e1kCsLeave(pThis);
3389
3390 return VINF_SUCCESS;
3391}
3392
3393/**
3394 * Write handler for Receive Control register.
3395 *
3396 * @param pThis The device state structure.
3397 * @param offset Register offset in memory-mapped frame.
3398 * @param index Register index in register array.
3399 * @param value The value to store.
3400 * @param mask Used to implement partial writes (8 and 16-bit).
3401 * @thread EMT
3402 */
3403static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3404{
3405 /* Update promiscuous mode */
3406 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3407 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3408 {
3409 /* Promiscuity has changed, pass the knowledge on. */
3410#ifndef IN_RING3
3411 return VINF_IOM_R3_MMIO_WRITE;
3412#else
3413 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3414 if (pThisCC->pDrvR3)
3415 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3416#endif
3417 }
3418
3419 /* Adjust receive buffer size */
3420 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3421 if (value & RCTL_BSEX)
3422 cbRxBuf *= 16;
3423 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3424 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3425 if (cbRxBuf != pThis->u16RxBSize)
3426 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3427 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3428 Assert(cbRxBuf < 65536);
3429 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3430
3431 /* Update the register */
3432 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3433}
3434
3435/**
3436 * Write handler for Packet Buffer Allocation register.
3437 *
3438 * TXA = 64 - RXA.
3439 *
3440 * @param pThis The device state structure.
3441 * @param offset Register offset in memory-mapped frame.
3442 * @param index Register index in register array.
3443 * @param value The value to store.
3444 * @param mask Used to implement partial writes (8 and 16-bit).
3445 * @thread EMT
3446 */
3447static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3448{
3449 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3450 PBA_st->txa = 64 - PBA_st->rxa;
3451
3452 return VINF_SUCCESS;
3453}
3454
3455/**
3456 * Write handler for Receive Descriptor Tail register.
3457 *
3458 * @remarks Write into RDT forces switch to HC and signal to
3459 * e1kR3NetworkDown_WaitReceiveAvail().
3460 *
3461 * @returns VBox status code.
3462 *
3463 * @param pThis The device state structure.
3464 * @param offset Register offset in memory-mapped frame.
3465 * @param index Register index in register array.
3466 * @param value The value to store.
3467 * @param mask Used to implement partial writes (8 and 16-bit).
3468 * @thread EMT
3469 */
3470static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3471{
3472#ifndef IN_RING3
3473 /* XXX */
3474// return VINF_IOM_R3_MMIO_WRITE;
3475#endif
3476 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3477 if (RT_LIKELY(rc == VINF_SUCCESS))
3478 {
3479 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3480#ifndef E1K_WITH_RXD_CACHE
3481 /*
3482 * Some drivers advance RDT too far, so that it equals RDH. This
3483 * somehow manages to work with real hardware but not with this
3484 * emulated device. We can work with these drivers if we just
3485 * write 1 less when we see a driver writing RDT equal to RDH,
3486 * see @bugref{7346}.
3487 */
3488 if (value == RDH)
3489 {
3490 if (RDH == 0)
3491 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3492 else
3493 value = RDH - 1;
3494 }
3495#endif /* !E1K_WITH_RXD_CACHE */
3496 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3497#ifdef E1K_WITH_RXD_CACHE
3498 E1KRXDC rxdc;
3499 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kRegWriteRDT")))
3500 {
3501 e1kCsRxLeave(pThis);
3502 E1kLog(("%s e1kRegWriteRDT: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
3503 return VINF_SUCCESS;
3504 }
3505 /*
3506 * We need to fetch descriptors now as RDT may go whole circle
3507 * before we attempt to store a received packet. For example,
3508 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3509 * size being only 8 descriptors! Note that we fetch descriptors
3510 * only when the cache is empty to reduce the number of memory reads
3511 * in case of frequent RDT writes. Don't fetch anything when the
3512 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3513 * messed up state.
3514 * Note that despite the cache may seem empty, meaning that there are
3515 * no more available descriptors in it, it may still be used by RX
3516 * thread which has not yet written the last descriptor back but has
3517 * temporarily released the RX lock in order to write the packet body
3518 * to descriptor's buffer. At this point we still going to do prefetch
3519 * but it won't actually fetch anything if there are no unused slots in
3520 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3521 * reset the cache here even if it appears empty. It will be reset at
3522 * a later point in e1kRxDGet().
3523 */
3524 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3525 e1kRxDPrefetch(pDevIns, pThis, &rxdc);
3526#endif /* E1K_WITH_RXD_CACHE */
3527 e1kCsRxLeave(pThis);
3528 if (RT_SUCCESS(rc))
3529 {
3530 /* Signal that we have more receive descriptors available. */
3531 e1kWakeupReceive(pDevIns, pThis);
3532 }
3533 }
3534 return rc;
3535}
3536
3537/**
3538 * Write handler for Receive Delay Timer register.
3539 *
3540 * @param pThis The device state structure.
3541 * @param offset Register offset in memory-mapped frame.
3542 * @param index Register index in register array.
3543 * @param value The value to store.
3544 * @param mask Used to implement partial writes (8 and 16-bit).
3545 * @thread EMT
3546 */
3547static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3548{
3549 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3550 if (value & RDTR_FPD)
3551 {
3552 /* Flush requested, cancel both timers and raise interrupt */
3553#ifdef E1K_USE_RX_TIMERS
3554 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3555 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3556#endif
3557 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3558 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3559 }
3560
3561 return VINF_SUCCESS;
3562}
3563
3564DECLINLINE(uint32_t) e1kGetTxLen(PE1KTXDC pTxdc)
3565{
3566 /**
3567 * Make sure TDT won't change during computation. EMT may modify TDT at
3568 * any moment.
3569 */
3570 uint32_t tdt = pTxdc->tdt;
3571 return (pTxdc->tdh > tdt ? pTxdc->tdlen/sizeof(E1KTXDESC) : 0) + tdt - pTxdc->tdh;
3572}
3573
3574#ifdef IN_RING3
3575
3576# ifdef E1K_TX_DELAY
3577/**
3578 * @callback_method_impl{FNTMTIMERDEV, Transmit Delay Timer handler.}
3579 */
3580static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3581{
3582 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3583 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->csTx));
3584 RT_NOREF(hTimer);
3585
3586 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3587# ifdef E1K_INT_STATS
3588 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3589 if (u64Elapsed > pThis->uStatMaxTxDelay)
3590 pThis->uStatMaxTxDelay = u64Elapsed;
3591# endif
3592 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3593 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3594}
3595# endif /* E1K_TX_DELAY */
3596
3597//# ifdef E1K_USE_TX_TIMERS
3598
3599/**
3600 * @callback_method_impl{FNTMTIMERDEV, Transmit Interrupt Delay Timer handler.}
3601 */
3602static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3603{
3604 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3605 Assert(hTimer == pThis->hTIDTimer); RT_NOREF(hTimer);
3606
3607 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3608 /* Cancel absolute delay timer as we have already got attention */
3609# ifndef E1K_NO_TAD
3610 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3611# endif
3612 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3613}
3614
3615/**
3616 * @callback_method_impl{FNTMTIMERDEV, Transmit Absolute Delay Timer handler.}
3617 */
3618static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3619{
3620 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3621 Assert(hTimer == pThis->hTADTimer); RT_NOREF(hTimer);
3622
3623 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3624 /* Cancel interrupt delay timer as we have already got attention */
3625 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3626 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3627}
3628
3629//# endif /* E1K_USE_TX_TIMERS */
3630# ifdef E1K_USE_RX_TIMERS
3631
3632/**
3633 * @callback_method_impl{FNTMTIMERDEV, Receive Interrupt Delay Timer handler.}
3634 */
3635static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3636{
3637 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3638 Assert(hTimer == pThis->hRIDTimer); RT_NOREF(hTimer);
3639
3640 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3641 /* Cancel absolute delay timer as we have already got attention */
3642 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3643 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3644}
3645
3646/**
3647 * @callback_method_impl{FNTMTIMERDEV, Receive Absolute Delay Timer handler.}
3648 */
3649static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3650{
3651 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3652 Assert(hTimer == pThis->hRADTimer); RT_NOREF(hTimer);
3653
3654 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3655 /* Cancel interrupt delay timer as we have already got attention */
3656 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3657 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3658}
3659
3660# endif /* E1K_USE_RX_TIMERS */
3661
3662/**
3663 * @callback_method_impl{FNTMTIMERDEV, Late Interrupt Timer handler.}
3664 */
3665static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3666{
3667 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3668 Assert(hTimer == pThis->hIntTimer); RT_NOREF(hTimer);
3669 RT_NOREF(hTimer);
3670
3671 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3672 STAM_COUNTER_INC(&pThis->StatLateInts);
3673 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3674# if 0
3675 if (pThis->iStatIntLost > -100)
3676 pThis->iStatIntLost--;
3677# endif
3678 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3679 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3680}
3681
3682/**
3683 * @callback_method_impl{FNTMTIMERDEV, Link Up Timer handler.}
3684 */
3685static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3686{
3687 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3688 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3689 Assert(hTimer == pThis->hLUTimer); RT_NOREF(hTimer);
3690
3691 /*
3692 * This can happen if we set the link status to down when the Link up timer was
3693 * already armed (shortly after e1kR3LoadDone() or when the cable was disconnected
3694 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3695 * on reset even if the cable is unplugged (see @bugref{8942}).
3696 */
3697 if (e1kIsConnected(pDevIns))
3698 {
3699 /* 82543GC does not have an internal PHY */
3700 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3701 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3702 }
3703# ifdef E1K_LSC_ON_RESET
3704 else if (pThis->eChip == E1K_CHIP_82543GC)
3705 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3706# endif /* E1K_LSC_ON_RESET */
3707}
3708
3709#endif /* IN_RING3 */
3710
3711/**
3712 * Sets up the GSO context according to the TSE new context descriptor.
3713 *
3714 * @param pGso The GSO context to setup.
3715 * @param pCtx The context descriptor.
3716 */
3717DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3718{
3719 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3720
3721 /*
3722 * See if the context descriptor describes something that could be TCP or
3723 * UDP over IPv[46].
3724 */
3725 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3726 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3727 {
3728 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3729 return;
3730 }
3731 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3732 {
3733 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3734 return;
3735 }
3736 if (RT_UNLIKELY( pCtx->dw2.fTCP
3737 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3738 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3739 {
3740 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3741 return;
3742 }
3743
3744 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3745 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3746 {
3747 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3748 return;
3749 }
3750
3751 /* IPv4 checksum offset. */
3752 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3753 {
3754 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3755 return;
3756 }
3757
3758 /* TCP/UDP checksum offsets. */
3759 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3760 != ( pCtx->dw2.fTCP
3761 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3762 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3763 {
3764 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3765 return;
3766 }
3767
3768 /*
3769 * Because of internal networking using a 16-bit size field for GSO context
3770 * plus frame, we have to make sure we don't exceed this.
3771 */
3772 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3773 {
3774 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3775 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3776 return;
3777 }
3778
3779 /*
3780 * We're good for now - we'll do more checks when seeing the data.
3781 * So, figure the type of offloading and setup the context.
3782 */
3783 if (pCtx->dw2.fIP)
3784 {
3785 if (pCtx->dw2.fTCP)
3786 {
3787 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3788 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3789 }
3790 else
3791 {
3792 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3793 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3794 }
3795 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3796 * this yet it seems)... */
3797 }
3798 else
3799 {
3800 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3801 if (pCtx->dw2.fTCP)
3802 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3803 else
3804 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3805 }
3806 pGso->offHdr1 = pCtx->ip.u8CSS;
3807 pGso->offHdr2 = pCtx->tu.u8CSS;
3808 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3809 pGso->cbMaxSeg = pCtx->dw3.u16MSS + (pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP ? pGso->offHdr2 : 0);
3810 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3811 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3812 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3813}
3814
3815/**
3816 * Checks if we can use GSO processing for the current TSE frame.
3817 *
3818 * @param pThis The device state structure.
3819 * @param pGso The GSO context.
3820 * @param pData The first data descriptor of the frame.
3821 * @param pCtx The TSO context descriptor.
3822 */
3823DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3824{
3825 if (!pData->cmd.fTSE)
3826 {
3827 E1kLog2(("e1kCanDoGso: !TSE\n"));
3828 return false;
3829 }
3830 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3831 {
3832 E1kLog(("e1kCanDoGso: VLE\n"));
3833 return false;
3834 }
3835 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3836 {
3837 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3838 return false;
3839 }
3840
3841 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3842 {
3843 case PDMNETWORKGSOTYPE_IPV4_TCP:
3844 case PDMNETWORKGSOTYPE_IPV4_UDP:
3845 if (!pData->dw3.fIXSM)
3846 {
3847 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3848 return false;
3849 }
3850 if (!pData->dw3.fTXSM)
3851 {
3852 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3853 return false;
3854 }
3855 /** @todo what more check should we perform here? Ethernet frame type? */
3856 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3857 return true;
3858
3859 case PDMNETWORKGSOTYPE_IPV6_TCP:
3860 case PDMNETWORKGSOTYPE_IPV6_UDP:
3861 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3862 {
3863 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3864 return false;
3865 }
3866 if (!pData->dw3.fTXSM)
3867 {
3868 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3869 return false;
3870 }
3871 /** @todo what more check should we perform here? Ethernet frame type? */
3872 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3873 return true;
3874
3875 default:
3876 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3877 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3878 return false;
3879 }
3880}
3881
3882/**
3883 * Frees the current xmit buffer.
3884 *
3885 * @param pThis The device state structure.
3886 */
3887static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3888{
3889 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3890 if (pSg)
3891 {
3892 pThisCC->CTX_SUFF(pTxSg) = NULL;
3893
3894 if (pSg->pvAllocator != pThis)
3895 {
3896 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3897 if (pDrv)
3898 pDrv->pfnFreeBuf(pDrv, pSg);
3899 }
3900 else
3901 {
3902 /* loopback */
3903 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3904 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3905 pSg->fFlags = 0;
3906 pSg->pvAllocator = NULL;
3907 }
3908 }
3909}
3910
3911#ifndef E1K_WITH_TXD_CACHE
3912/**
3913 * Allocates an xmit buffer.
3914 *
3915 * @returns See PDMINETWORKUP::pfnAllocBuf.
3916 * @param pThis The device state structure.
3917 * @param cbMin The minimum frame size.
3918 * @param fExactSize Whether cbMin is exact or if we have to max it
3919 * out to the max MTU size.
3920 * @param fGso Whether this is a GSO frame or not.
3921 */
3922DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3923{
3924 /* Adjust cbMin if necessary. */
3925 if (!fExactSize)
3926 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3927
3928 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3929 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3930 e1kXmitFreeBuf(pThis, pThisCC);
3931 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3932
3933 /*
3934 * Allocate the buffer.
3935 */
3936 PPDMSCATTERGATHER pSg;
3937 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3938 {
3939 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3940 if (RT_UNLIKELY(!pDrv))
3941 return VERR_NET_DOWN;
3942 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3943 if (RT_FAILURE(rc))
3944 {
3945 /* Suspend TX as we are out of buffers atm */
3946 STATUS |= STATUS_TXOFF;
3947 return rc;
3948 }
3949 }
3950 else
3951 {
3952 /* Create a loopback using the fallback buffer and preallocated SG. */
3953 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3954 pSg = &pThis->uTxFallback.Sg;
3955 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3956 pSg->cbUsed = 0;
3957 pSg->cbAvailable = 0;
3958 pSg->pvAllocator = pThis;
3959 pSg->pvUser = NULL; /* No GSO here. */
3960 pSg->cSegs = 1;
3961 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3962 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3963 }
3964
3965 pThisCC->CTX_SUFF(pTxSg) = pSg;
3966 return VINF_SUCCESS;
3967}
3968#else /* E1K_WITH_TXD_CACHE */
3969/**
3970 * Allocates an xmit buffer.
3971 *
3972 * @returns See PDMINETWORKUP::pfnAllocBuf.
3973 * @param pThis The device state structure.
3974 * @param cbMin The minimum frame size.
3975 * @param fExactSize Whether cbMin is exact or if we have to max it
3976 * out to the max MTU size.
3977 * @param fGso Whether this is a GSO frame or not.
3978 */
3979DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3980{
3981 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3982 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3983 e1kXmitFreeBuf(pThis, pThisCC);
3984 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3985
3986 /*
3987 * Allocate the buffer.
3988 */
3989 PPDMSCATTERGATHER pSg;
3990 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3991 {
3992 if (pThis->cbTxAlloc == 0)
3993 {
3994 /* Zero packet, no need for the buffer */
3995 return VINF_SUCCESS;
3996 }
3997 if (fGso && pThis->GsoCtx.u8Type == PDMNETWORKGSOTYPE_INVALID)
3998 {
3999 E1kLog3(("Invalid GSO context, won't allocate this packet, cb=%u %s%s\n",
4000 pThis->cbTxAlloc, pThis->fVTag ? "VLAN " : "", pThis->fGSO ? "GSO " : ""));
4001 /* No valid GSO context is available, ignore this packet. */
4002 pThis->cbTxAlloc = 0;
4003 return VINF_SUCCESS;
4004 }
4005
4006 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4007 if (RT_UNLIKELY(!pDrv))
4008 return VERR_NET_DOWN;
4009 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
4010 if (RT_FAILURE(rc))
4011 {
4012 /* Suspend TX as we are out of buffers atm */
4013 STATUS |= STATUS_TXOFF;
4014 return rc;
4015 }
4016 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
4017 pThis->szPrf, pThis->cbTxAlloc,
4018 pThis->fVTag ? "VLAN " : "",
4019 pThis->fGSO ? "GSO " : ""));
4020 }
4021 else
4022 {
4023 /* Create a loopback using the fallback buffer and preallocated SG. */
4024 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
4025 pSg = &pThis->uTxFallback.Sg;
4026 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
4027 pSg->cbUsed = 0;
4028 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
4029 pSg->pvAllocator = pThis;
4030 pSg->pvUser = NULL; /* No GSO here. */
4031 pSg->cSegs = 1;
4032 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
4033 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
4034 }
4035 pThis->cbTxAlloc = 0;
4036
4037 pThisCC->CTX_SUFF(pTxSg) = pSg;
4038 return VINF_SUCCESS;
4039}
4040#endif /* E1K_WITH_TXD_CACHE */
4041
4042/**
4043 * Checks if it's a GSO buffer or not.
4044 *
4045 * @returns true / false.
4046 * @param pTxSg The scatter / gather buffer.
4047 */
4048DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
4049{
4050#if 0
4051 if (!pTxSg)
4052 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
4053 if (pTxSg && pTxSg->pvUser)
4054 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
4055#endif
4056 return pTxSg && pTxSg->pvUser /* GSO indicator */;
4057}
4058
4059#ifndef E1K_WITH_TXD_CACHE
4060/**
4061 * Load transmit descriptor from guest memory.
4062 *
4063 * @param pDevIns The device instance.
4064 * @param pDesc Pointer to descriptor union.
4065 * @param addr Physical address in guest context.
4066 * @thread E1000_TX
4067 */
4068DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
4069{
4070 PDMDevHlpPCIPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4071}
4072#else /* E1K_WITH_TXD_CACHE */
4073/**
4074 * Load transmit descriptors from guest memory.
4075 *
4076 * We need two physical reads in case the tail wrapped around the end of TX
4077 * descriptor ring.
4078 *
4079 * @returns the actual number of descriptors fetched.
4080 * @param pDevIns The device instance.
4081 * @param pThis The device state structure.
4082 * @thread E1000_TX
4083 */
4084DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4085{
4086 Assert(pThis->iTxDCurrent == 0);
4087 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
4088 unsigned nDescsAvailable = e1kGetTxLen(pTxdc) - pThis->nTxDFetched;
4089 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
4090 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
4091 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
4092 unsigned nDescsTotal = pTxdc->tdlen / sizeof(E1KTXDESC);
4093 Assert(nDescsTotal != 0);
4094 if (nDescsTotal == 0)
4095 return 0;
4096 unsigned nFirstNotLoaded = (pTxdc->tdh + pThis->nTxDFetched) % nDescsTotal;
4097 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
4098 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
4099 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
4100 nFirstNotLoaded, nDescsInSingleRead));
4101 if (nDescsToFetch == 0)
4102 return 0;
4103 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
4104 PDMDevHlpPCIPhysRead(pDevIns,
4105 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
4106 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
4107 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
4108 pThis->szPrf, nDescsInSingleRead,
4109 TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC),
4110 nFirstNotLoaded, pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
4111 if (nDescsToFetch > nDescsInSingleRead)
4112 {
4113 PDMDevHlpPCIPhysRead(pDevIns,
4114 ((uint64_t)TDBAH << 32) + TDBAL,
4115 pFirstEmptyDesc + nDescsInSingleRead,
4116 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
4117 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
4118 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
4119 TDBAH, TDBAL));
4120 }
4121 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
4122 return nDescsToFetch;
4123}
4124
4125/**
4126 * Load transmit descriptors from guest memory only if there are no loaded
4127 * descriptors.
4128 *
4129 * @returns true if there are descriptors in cache.
4130 * @param pDevIns The device instance.
4131 * @param pThis The device state structure.
4132 * @thread E1000_TX
4133 */
4134DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4135{
4136 if (pThis->nTxDFetched == 0)
4137 return e1kTxDLoadMore(pDevIns, pThis, pTxdc) != 0;
4138 return true;
4139}
4140#endif /* E1K_WITH_TXD_CACHE */
4141
4142/**
4143 * Write back transmit descriptor to guest memory.
4144 *
4145 * @param pDevIns The device instance.
4146 * @param pThis The device state structure.
4147 * @param pDesc Pointer to descriptor union.
4148 * @param addr Physical address in guest context.
4149 * @thread E1000_TX
4150 */
4151DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4152{
4153 /* Only the last half of the descriptor has to be written back. */
4154 e1kPrintTDesc(pThis, pDesc, "^^^");
4155 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4156}
4157
4158/**
4159 * Transmit complete frame.
4160 *
4161 * @remarks We skip the FCS since we're not responsible for sending anything to
4162 * a real ethernet wire.
4163 *
4164 * @param pDevIns The device instance.
4165 * @param pThis The device state structure.
4166 * @param pThisCC The current context instance data.
4167 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4168 * @thread E1000_TX
4169 */
4170static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4171{
4172 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4173 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4174 Assert(!pSg || pSg->cSegs == 1);
4175
4176 if (cbFrame > 70) /* unqualified guess */
4177 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4178
4179#ifdef E1K_INT_STATS
4180 if (cbFrame <= 1514)
4181 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4182 else if (cbFrame <= 2962)
4183 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4184 else if (cbFrame <= 4410)
4185 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4186 else if (cbFrame <= 5858)
4187 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4188 else if (cbFrame <= 7306)
4189 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4190 else if (cbFrame <= 8754)
4191 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4192 else if (cbFrame <= 16384)
4193 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4194 else if (cbFrame <= 32768)
4195 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4196 else
4197 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4198#endif /* E1K_INT_STATS */
4199
4200 /* Add VLAN tag */
4201 if (cbFrame > 12 && pThis->fVTag)
4202 {
4203 E1kLog3(("%s Inserting VLAN tag %08x\n",
4204 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4205 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4206 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4207 pSg->cbUsed += 4;
4208 cbFrame += 4;
4209 Assert(pSg->cbUsed == cbFrame);
4210 Assert(pSg->cbUsed <= pSg->cbAvailable);
4211 }
4212/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4213 "%.*Rhxd\n"
4214 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4215 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4216
4217 /* Update the stats */
4218 E1K_INC_CNT32(TPT);
4219 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4220 E1K_INC_CNT32(GPTC);
4221 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4222 E1K_INC_CNT32(BPTC);
4223 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4224 E1K_INC_CNT32(MPTC);
4225 /* Update octet transmit counter */
4226 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4227 if (pThisCC->CTX_SUFF(pDrv))
4228 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4229 if (cbFrame == 64)
4230 E1K_INC_CNT32(PTC64);
4231 else if (cbFrame < 128)
4232 E1K_INC_CNT32(PTC127);
4233 else if (cbFrame < 256)
4234 E1K_INC_CNT32(PTC255);
4235 else if (cbFrame < 512)
4236 E1K_INC_CNT32(PTC511);
4237 else if (cbFrame < 1024)
4238 E1K_INC_CNT32(PTC1023);
4239 else
4240 E1K_INC_CNT32(PTC1522);
4241
4242 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4243
4244 /*
4245 * Dump and send the packet.
4246 */
4247 int rc = VERR_NET_DOWN;
4248 if (pSg && pSg->pvAllocator != pThis)
4249 {
4250 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4251
4252 pThisCC->CTX_SUFF(pTxSg) = NULL;
4253 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4254 if (pDrv)
4255 {
4256 /* Release critical section to avoid deadlock in CanReceive */
4257 //e1kCsLeave(pThis);
4258 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4259 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4260 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4261 //e1kR3CsEnterAsserted(pThis);
4262 }
4263 }
4264 else if (pSg)
4265 {
4266 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4267 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4268
4269 /** @todo do we actually need to check that we're in loopback mode here? */
4270 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4271 {
4272 E1KRXDST status;
4273 RT_ZERO(status);
4274 status.fPIF = true;
4275 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4276 rc = VINF_SUCCESS;
4277 }
4278 e1kXmitFreeBuf(pThis, pThisCC);
4279 }
4280 else
4281 rc = VERR_NET_DOWN;
4282 if (RT_FAILURE(rc))
4283 {
4284 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4285 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4286 }
4287
4288 pThis->led.Actual.s.fWriting = 0;
4289}
4290
4291/**
4292 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4293 *
4294 * @param pThis The device state structure.
4295 * @param pPkt Pointer to the packet.
4296 * @param u16PktLen Total length of the packet.
4297 * @param cso Offset in packet to write checksum at.
4298 * @param css Offset in packet to start computing
4299 * checksum from.
4300 * @param cse Offset in packet to stop computing
4301 * checksum at.
4302 * @param fUdp Replace 0 checksum with all 1s.
4303 * @thread E1000_TX
4304 */
4305static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse, bool fUdp = false)
4306{
4307 RT_NOREF1(pThis);
4308
4309 if (css >= u16PktLen)
4310 {
4311 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4312 pThis->szPrf, cso, u16PktLen));
4313 return;
4314 }
4315
4316 if (cso >= u16PktLen - 1)
4317 {
4318 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4319 pThis->szPrf, cso, u16PktLen));
4320 return;
4321 }
4322
4323 if (cse == 0 || cse >= u16PktLen)
4324 cse = u16PktLen - 1;
4325 else if (cse < css)
4326 {
4327 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4328 pThis->szPrf, css, cse));
4329 return;
4330 }
4331
4332 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4333 if (fUdp && u16ChkSum == 0)
4334 u16ChkSum = ~u16ChkSum; /* 0 means no checksum computed in case of UDP (see @bugref{9883}) */
4335 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4336 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4337 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4338}
4339
4340/**
4341 * Add a part of descriptor's buffer to transmit frame.
4342 *
4343 * @remarks data.u64BufAddr is used unconditionally for both data
4344 * and legacy descriptors since it is identical to
4345 * legacy.u64BufAddr.
4346 *
4347 * @param pDevIns The device instance.
4348 * @param pThis The device state structure.
4349 * @param pDesc Pointer to the descriptor to transmit.
4350 * @param u16Len Length of buffer to the end of segment.
4351 * @param fSend Force packet sending.
4352 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4353 * @thread E1000_TX
4354 */
4355#ifndef E1K_WITH_TXD_CACHE
4356static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4357{
4358 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4359 /* TCP header being transmitted */
4360 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4361 /* IP header being transmitted */
4362 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4363
4364 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4365 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4366 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4367
4368 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4369 E1kLog3(("%s Dump of the segment:\n"
4370 "%.*Rhxd\n"
4371 "%s --- End of dump ---\n",
4372 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4373 pThis->u16TxPktLen += u16Len;
4374 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4375 pThis->szPrf, pThis->u16TxPktLen));
4376 if (pThis->u16HdrRemain > 0)
4377 {
4378 /* The header was not complete, check if it is now */
4379 if (u16Len >= pThis->u16HdrRemain)
4380 {
4381 /* The rest is payload */
4382 u16Len -= pThis->u16HdrRemain;
4383 pThis->u16HdrRemain = 0;
4384 /* Save partial checksum and flags */
4385 pThis->u32SavedCsum = pTcpHdr->chksum;
4386 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4387 /* Clear FIN and PSH flags now and set them only in the last segment */
4388 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4389 }
4390 else
4391 {
4392 /* Still not */
4393 pThis->u16HdrRemain -= u16Len;
4394 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4395 pThis->szPrf, pThis->u16HdrRemain));
4396 return;
4397 }
4398 }
4399
4400 pThis->u32PayRemain -= u16Len;
4401
4402 if (fSend)
4403 {
4404 /* Leave ethernet header intact */
4405 /* IP Total Length = payload + headers - ethernet header */
4406 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4407 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4408 pThis->szPrf, ntohs(pIpHdr->total_len)));
4409 /* Update IP Checksum */
4410 pIpHdr->chksum = 0;
4411 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4412 pThis->contextTSE.ip.u8CSO,
4413 pThis->contextTSE.ip.u8CSS,
4414 pThis->contextTSE.ip.u16CSE);
4415
4416 /* Update TCP flags */
4417 /* Restore original FIN and PSH flags for the last segment */
4418 if (pThis->u32PayRemain == 0)
4419 {
4420 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4421 E1K_INC_CNT32(TSCTC);
4422 }
4423 /* Add TCP length to partial pseudo header sum */
4424 uint32_t csum = pThis->u32SavedCsum
4425 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4426 while (csum >> 16)
4427 csum = (csum >> 16) + (csum & 0xFFFF);
4428 pTcpHdr->chksum = csum;
4429 /* Compute final checksum */
4430 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4431 pThis->contextTSE.tu.u8CSO,
4432 pThis->contextTSE.tu.u8CSS,
4433 pThis->contextTSE.tu.u16CSE);
4434
4435 /*
4436 * Transmit it. If we've use the SG already, allocate a new one before
4437 * we copy of the data.
4438 */
4439 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4440 if (!pTxSg)
4441 {
4442 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4443 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4444 }
4445 if (pTxSg)
4446 {
4447 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4448 Assert(pTxSg->cSegs == 1);
4449 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4450 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4451 pTxSg->cbUsed = pThis->u16TxPktLen;
4452 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4453 }
4454 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4455
4456 /* Update Sequence Number */
4457 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4458 - pThis->contextTSE.dw3.u8HDRLEN);
4459 /* Increment IP identification */
4460 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4461 }
4462}
4463#else /* E1K_WITH_TXD_CACHE */
4464static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4465{
4466 int rc = VINF_SUCCESS;
4467 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4468 /* TCP header being transmitted */
4469 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4470 /* IP header being transmitted */
4471 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4472
4473 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4474 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4475 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4476
4477 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4478 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4479 else
4480 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4481 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4482 E1kLog3(("%s Dump of the segment:\n"
4483 "%.*Rhxd\n"
4484 "%s --- End of dump ---\n",
4485 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4486 pThis->u16TxPktLen += u16Len;
4487 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4488 pThis->szPrf, pThis->u16TxPktLen));
4489 if (pThis->u16HdrRemain > 0)
4490 {
4491 /* The header was not complete, check if it is now */
4492 if (u16Len >= pThis->u16HdrRemain)
4493 {
4494 /* The rest is payload */
4495 u16Len -= pThis->u16HdrRemain;
4496 pThis->u16HdrRemain = 0;
4497 /* Save partial checksum and flags */
4498 pThis->u32SavedCsum = pTcpHdr->chksum;
4499 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4500 /* Clear FIN and PSH flags now and set them only in the last segment */
4501 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4502 }
4503 else
4504 {
4505 /* Still not */
4506 pThis->u16HdrRemain -= u16Len;
4507 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4508 pThis->szPrf, pThis->u16HdrRemain));
4509 return rc;
4510 }
4511 }
4512
4513 if (u16Len > pThis->u32PayRemain)
4514 pThis->u32PayRemain = 0;
4515 else
4516 pThis->u32PayRemain -= u16Len;
4517
4518 if (fSend)
4519 {
4520 /* Leave ethernet header intact */
4521 /* IP Total Length = payload + headers - ethernet header */
4522 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4523 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4524 pThis->szPrf, ntohs(pIpHdr->total_len)));
4525 /* Update IP Checksum */
4526 pIpHdr->chksum = 0;
4527 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4528 pThis->contextTSE.ip.u8CSO,
4529 pThis->contextTSE.ip.u8CSS,
4530 pThis->contextTSE.ip.u16CSE);
4531
4532 /* Update TCP flags */
4533 /* Restore original FIN and PSH flags for the last segment */
4534 if (pThis->u32PayRemain == 0)
4535 {
4536 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4537 E1K_INC_CNT32(TSCTC);
4538 }
4539 /* Add TCP length to partial pseudo header sum */
4540 uint32_t csum = pThis->u32SavedCsum
4541 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4542 while (csum >> 16)
4543 csum = (csum >> 16) + (csum & 0xFFFF);
4544 Assert(csum < 65536);
4545 pTcpHdr->chksum = (uint16_t)csum;
4546 /* Compute final checksum */
4547 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4548 pThis->contextTSE.tu.u8CSO,
4549 pThis->contextTSE.tu.u8CSS,
4550 pThis->contextTSE.tu.u16CSE);
4551
4552 /*
4553 * Transmit it.
4554 */
4555 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4556 if (pTxSg)
4557 {
4558 /* Make sure the packet fits into the allocated buffer */
4559 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4560#ifdef DEBUG
4561 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4562 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4563 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4564#endif /* DEBUG */
4565 Assert(pTxSg->cSegs == 1);
4566 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4567 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4568 pTxSg->cbUsed = cbCopy;
4569 pTxSg->aSegs[0].cbSeg = cbCopy;
4570 }
4571 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4572
4573 /* Update Sequence Number */
4574 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4575 - pThis->contextTSE.dw3.u8HDRLEN);
4576 /* Increment IP identification */
4577 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4578
4579 /* Allocate new buffer for the next segment. */
4580 if (pThis->u32PayRemain)
4581 {
4582 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4583 pThis->contextTSE.dw3.u16MSS)
4584 + pThis->contextTSE.dw3.u8HDRLEN;
4585 /* Do not add VLAN tags to empty packets. */
4586 if (pThis->fVTag && pThis->cbTxAlloc > 0)
4587 pThis->cbTxAlloc += 4;
4588 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4589 }
4590 }
4591
4592 return rc;
4593}
4594#endif /* E1K_WITH_TXD_CACHE */
4595
4596#ifndef E1K_WITH_TXD_CACHE
4597/**
4598 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4599 * frame.
4600 *
4601 * We construct the frame in the fallback buffer first and the copy it to the SG
4602 * buffer before passing it down to the network driver code.
4603 *
4604 * @returns true if the frame should be transmitted, false if not.
4605 *
4606 * @param pThis The device state structure.
4607 * @param pDesc Pointer to the descriptor to transmit.
4608 * @param cbFragment Length of descriptor's buffer.
4609 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4610 * @thread E1000_TX
4611 */
4612static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4613{
4614 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4615 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4616 Assert(pDesc->data.cmd.fTSE);
4617 Assert(!e1kXmitIsGsoBuf(pTxSg));
4618
4619 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4620 Assert(u16MaxPktLen != 0);
4621 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4622
4623 /*
4624 * Carve out segments.
4625 */
4626 do
4627 {
4628 /* Calculate how many bytes we have left in this TCP segment */
4629 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4630 if (cb > cbFragment)
4631 {
4632 /* This descriptor fits completely into current segment */
4633 cb = cbFragment;
4634 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4635 }
4636 else
4637 {
4638 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4639 /*
4640 * Rewind the packet tail pointer to the beginning of payload,
4641 * so we continue writing right beyond the header.
4642 */
4643 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4644 }
4645
4646 pDesc->data.u64BufAddr += cb;
4647 cbFragment -= cb;
4648 } while (cbFragment > 0);
4649
4650 if (pDesc->data.cmd.fEOP)
4651 {
4652 /* End of packet, next segment will contain header. */
4653 if (pThis->u32PayRemain != 0)
4654 E1K_INC_CNT32(TSCTFC);
4655 pThis->u16TxPktLen = 0;
4656 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4657 }
4658
4659 return false;
4660}
4661#else /* E1K_WITH_TXD_CACHE */
4662/**
4663 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4664 * frame.
4665 *
4666 * We construct the frame in the fallback buffer first and the copy it to the SG
4667 * buffer before passing it down to the network driver code.
4668 *
4669 * @returns error code
4670 *
4671 * @param pDevIns The device instance.
4672 * @param pThis The device state structure.
4673 * @param pDesc Pointer to the descriptor to transmit.
4674 * @param cbFragment Length of descriptor's buffer.
4675 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4676 * @thread E1000_TX
4677 */
4678static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4679{
4680#ifdef VBOX_STRICT
4681 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4682 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4683 Assert(pDesc->data.cmd.fTSE);
4684 Assert(!e1kXmitIsGsoBuf(pTxSg));
4685#endif
4686
4687 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4688 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4689 if (u16MaxPktLen == 0)
4690 return VINF_SUCCESS;
4691
4692 /*
4693 * Carve out segments.
4694 */
4695 int rc = VINF_SUCCESS;
4696 do
4697 {
4698 /* Calculate how many bytes we have left in this TCP segment */
4699 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4700 if (cb > pDesc->data.cmd.u20DTALEN)
4701 {
4702 /* This descriptor fits completely into current segment */
4703 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4704 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4705 }
4706 else
4707 {
4708 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4709 /*
4710 * Rewind the packet tail pointer to the beginning of payload,
4711 * so we continue writing right beyond the header.
4712 */
4713 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4714 }
4715
4716 pDesc->data.u64BufAddr += cb;
4717 pDesc->data.cmd.u20DTALEN -= cb;
4718 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4719
4720 if (pDesc->data.cmd.fEOP)
4721 {
4722 /* End of packet, next segment will contain header. */
4723 if (pThis->u32PayRemain != 0)
4724 E1K_INC_CNT32(TSCTFC);
4725 pThis->u16TxPktLen = 0;
4726 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4727 }
4728
4729 return VINF_SUCCESS; /// @todo consider rc;
4730}
4731#endif /* E1K_WITH_TXD_CACHE */
4732
4733
4734/**
4735 * Add descriptor's buffer to transmit frame.
4736 *
4737 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4738 * TSE frames we cannot handle as GSO.
4739 *
4740 * @returns true on success, false on failure.
4741 *
4742 * @param pDevIns The device instance.
4743 * @param pThisCC The current context instance data.
4744 * @param pThis The device state structure.
4745 * @param PhysAddr The physical address of the descriptor buffer.
4746 * @param cbFragment Length of descriptor's buffer.
4747 * @thread E1000_TX
4748 */
4749static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4750{
4751 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4752 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4753 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4754
4755 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4756 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4757 fGso ? "true" : "false"));
4758 PCPDMNETWORKGSO pGso = (PCPDMNETWORKGSO)pTxSg->pvUser;
4759 if (pGso)
4760 {
4761 if (RT_UNLIKELY(pGso->cbMaxSeg == 0))
4762 {
4763 E1kLog(("%s zero-sized fragments are not allowed\n", pThis->szPrf));
4764 return false;
4765 }
4766 if (RT_UNLIKELY(pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP))
4767 {
4768 E1kLog(("%s UDP fragmentation is no longer supported\n", pThis->szPrf));
4769 return false;
4770 }
4771 }
4772 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4773 {
4774 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4775 return false;
4776 }
4777 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4778 {
4779 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4780 return false;
4781 }
4782
4783 if (RT_LIKELY(pTxSg))
4784 {
4785 Assert(pTxSg->cSegs == 1);
4786 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4787 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4788 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4789
4790 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4791
4792 pTxSg->cbUsed = cbNewPkt;
4793 }
4794 pThis->u16TxPktLen = cbNewPkt;
4795
4796 return true;
4797}
4798
4799
4800/**
4801 * Write the descriptor back to guest memory and notify the guest.
4802 *
4803 * @param pThis The device state structure.
4804 * @param pDesc Pointer to the descriptor have been transmitted.
4805 * @param addr Physical address of the descriptor in guest memory.
4806 * @thread E1000_TX
4807 */
4808static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4809{
4810 /*
4811 * We fake descriptor write-back bursting. Descriptors are written back as they are
4812 * processed.
4813 */
4814 /* Let's pretend we process descriptors. Write back with DD set. */
4815 /*
4816 * Prior to r71586 we tried to accomodate the case when write-back bursts
4817 * are enabled without actually implementing bursting by writing back all
4818 * descriptors, even the ones that do not have RS set. This caused kernel
4819 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4820 * associated with written back descriptor if it happened to be a context
4821 * descriptor since context descriptors do not have skb associated to them.
4822 * Starting from r71586 we write back only the descriptors with RS set,
4823 * which is a little bit different from what the real hardware does in
4824 * case there is a chain of data descritors where some of them have RS set
4825 * and others do not. It is very uncommon scenario imho.
4826 * We need to check RPS as well since some legacy drivers use it instead of
4827 * RS even with newer cards.
4828 */
4829 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4830 {
4831 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4832 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4833 if (pDesc->legacy.cmd.fEOP)
4834 {
4835//#ifdef E1K_USE_TX_TIMERS
4836 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4837 {
4838 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4839 //if (pThis->fIntRaised)
4840 //{
4841 // /* Interrupt is already pending, no need for timers */
4842 // ICR |= ICR_TXDW;
4843 //}
4844 //else {
4845 /* Arm the timer to fire in TIVD usec (discard .024) */
4846 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4847# ifndef E1K_NO_TAD
4848 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4849 E1kLog2(("%s Checking if TAD timer is running\n",
4850 pThis->szPrf));
4851 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4852 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4853# endif /* E1K_NO_TAD */
4854 }
4855 else
4856 {
4857 if (pThis->fTidEnabled)
4858 {
4859 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4860 pThis->szPrf));
4861 /* Cancel both timers if armed and fire immediately. */
4862# ifndef E1K_NO_TAD
4863 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4864# endif
4865 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4866 }
4867//#endif /* E1K_USE_TX_TIMERS */
4868 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4869 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4870//#ifdef E1K_USE_TX_TIMERS
4871 }
4872//#endif /* E1K_USE_TX_TIMERS */
4873 }
4874 }
4875 else
4876 {
4877 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4878 }
4879}
4880
4881#ifndef E1K_WITH_TXD_CACHE
4882
4883/**
4884 * Process Transmit Descriptor.
4885 *
4886 * E1000 supports three types of transmit descriptors:
4887 * - legacy data descriptors of older format (context-less).
4888 * - data the same as legacy but providing new offloading capabilities.
4889 * - context sets up the context for following data descriptors.
4890 *
4891 * @param pDevIns The device instance.
4892 * @param pThis The device state structure.
4893 * @param pThisCC The current context instance data.
4894 * @param pDesc Pointer to descriptor union.
4895 * @param addr Physical address of descriptor in guest memory.
4896 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4897 * @thread E1000_TX
4898 */
4899static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4900 RTGCPHYS addr, bool fOnWorkerThread)
4901{
4902 int rc = VINF_SUCCESS;
4903 uint32_t cbVTag = 0;
4904
4905 e1kPrintTDesc(pThis, pDesc, "vvv");
4906
4907//#ifdef E1K_USE_TX_TIMERS
4908 if (pThis->fTidEnabled)
4909 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4910//#endif /* E1K_USE_TX_TIMERS */
4911
4912 switch (e1kGetDescType(pDesc))
4913 {
4914 case E1K_DTYP_CONTEXT:
4915 if (pDesc->context.dw2.fTSE)
4916 {
4917 pThis->contextTSE = pDesc->context;
4918 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4919 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4920 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4921 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4922 }
4923 else
4924 {
4925 pThis->contextNormal = pDesc->context;
4926 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4927 }
4928 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4929 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4930 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4931 pDesc->context.ip.u8CSS,
4932 pDesc->context.ip.u8CSO,
4933 pDesc->context.ip.u16CSE,
4934 pDesc->context.tu.u8CSS,
4935 pDesc->context.tu.u8CSO,
4936 pDesc->context.tu.u16CSE));
4937 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4938 e1kDescReport(pThis, pDesc, addr);
4939 break;
4940
4941 case E1K_DTYP_DATA:
4942 {
4943 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4944 {
4945 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4946 /** @todo Same as legacy when !TSE. See below. */
4947 break;
4948 }
4949 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4950 &pThis->StatTxDescTSEData:
4951 &pThis->StatTxDescData);
4952 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4953 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4954
4955 /*
4956 * The last descriptor of non-TSE packet must contain VLE flag.
4957 * TSE packets have VLE flag in the first descriptor. The later
4958 * case is taken care of a bit later when cbVTag gets assigned.
4959 *
4960 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4961 */
4962 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4963 {
4964 pThis->fVTag = pDesc->data.cmd.fVLE;
4965 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4966 }
4967 /*
4968 * First fragment: Allocate new buffer and save the IXSM and TXSM
4969 * packet options as these are only valid in the first fragment.
4970 */
4971 if (pThis->u16TxPktLen == 0)
4972 {
4973 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4974 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4975 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4976 pThis->fIPcsum ? " IP" : "",
4977 pThis->fTCPcsum ? " TCP/UDP" : ""));
4978 if (pDesc->data.cmd.fTSE)
4979 {
4980 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4981 pThis->fVTag = pDesc->data.cmd.fVLE;
4982 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4983 cbVTag = pThis->fVTag ? 4 : 0;
4984 }
4985 else if (pDesc->data.cmd.fEOP)
4986 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4987 else
4988 cbVTag = 4;
4989 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4990 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4991 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4992 true /*fExactSize*/, true /*fGso*/);
4993 else if (pDesc->data.cmd.fTSE)
4994 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4995 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4996 else
4997 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4998 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4999
5000 /**
5001 * @todo: Perhaps it is not that simple for GSO packets! We may
5002 * need to unwind some changes.
5003 */
5004 if (RT_FAILURE(rc))
5005 {
5006 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5007 break;
5008 }
5009 /** @todo Is there any way to indicating errors other than collisions? Like
5010 * VERR_NET_DOWN. */
5011 }
5012
5013 /*
5014 * Add the descriptor data to the frame. If the frame is complete,
5015 * transmit it and reset the u16TxPktLen field.
5016 */
5017 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5018 {
5019 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5020 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5021 if (pDesc->data.cmd.fEOP)
5022 {
5023 if ( fRc
5024 && pThisCC->CTX_SUFF(pTxSg)
5025 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5026 {
5027 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5028 E1K_INC_CNT32(TSCTC);
5029 }
5030 else
5031 {
5032 if (fRc)
5033 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5034 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5035 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5036 e1kXmitFreeBuf(pThis);
5037 E1K_INC_CNT32(TSCTFC);
5038 }
5039 pThis->u16TxPktLen = 0;
5040 }
5041 }
5042 else if (!pDesc->data.cmd.fTSE)
5043 {
5044 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5045 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5046 if (pDesc->data.cmd.fEOP)
5047 {
5048 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5049 {
5050 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5051 if (pThis->fIPcsum)
5052 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5053 pThis->contextNormal.ip.u8CSO,
5054 pThis->contextNormal.ip.u8CSS,
5055 pThis->contextNormal.ip.u16CSE);
5056 if (pThis->fTCPcsum)
5057 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5058 pThis->contextNormal.tu.u8CSO,
5059 pThis->contextNormal.tu.u8CSS,
5060 pThis->contextNormal.tu.u16CSE,
5061 !pThis->contextNormal.dw2.fTCP);
5062 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5063 }
5064 else
5065 e1kXmitFreeBuf(pThis);
5066 pThis->u16TxPktLen = 0;
5067 }
5068 }
5069 else
5070 {
5071 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5072 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
5073 }
5074
5075 e1kDescReport(pThis, pDesc, addr);
5076 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5077 break;
5078 }
5079
5080 case E1K_DTYP_LEGACY:
5081 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5082 {
5083 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5084 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
5085 break;
5086 }
5087 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5088 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5089
5090 /* First fragment: allocate new buffer. */
5091 if (pThis->u16TxPktLen == 0)
5092 {
5093 if (pDesc->legacy.cmd.fEOP)
5094 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
5095 else
5096 cbVTag = 4;
5097 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
5098 /** @todo reset status bits? */
5099 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
5100 if (RT_FAILURE(rc))
5101 {
5102 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5103 break;
5104 }
5105
5106 /** @todo Is there any way to indicating errors other than collisions? Like
5107 * VERR_NET_DOWN. */
5108 }
5109
5110 /* Add fragment to frame. */
5111 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5112 {
5113 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5114
5115 /* Last fragment: Transmit and reset the packet storage counter. */
5116 if (pDesc->legacy.cmd.fEOP)
5117 {
5118 pThis->fVTag = pDesc->legacy.cmd.fVLE;
5119 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
5120 /** @todo Offload processing goes here. */
5121 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5122 pThis->u16TxPktLen = 0;
5123 }
5124 }
5125 /* Last fragment + failure: free the buffer and reset the storage counter. */
5126 else if (pDesc->legacy.cmd.fEOP)
5127 {
5128 e1kXmitFreeBuf(pThis);
5129 pThis->u16TxPktLen = 0;
5130 }
5131
5132 e1kDescReport(pThis, pDesc, addr);
5133 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5134 break;
5135
5136 default:
5137 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5138 pThis->szPrf, e1kGetDescType(pDesc)));
5139 break;
5140 }
5141
5142 return rc;
5143}
5144
5145#else /* E1K_WITH_TXD_CACHE */
5146
5147/**
5148 * Process Transmit Descriptor.
5149 *
5150 * E1000 supports three types of transmit descriptors:
5151 * - legacy data descriptors of older format (context-less).
5152 * - data the same as legacy but providing new offloading capabilities.
5153 * - context sets up the context for following data descriptors.
5154 *
5155 * @param pDevIns The device instance.
5156 * @param pThis The device state structure.
5157 * @param pThisCC The current context instance data.
5158 * @param pDesc Pointer to descriptor union.
5159 * @param addr Physical address of descriptor in guest memory.
5160 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
5161 * @param cbPacketSize Size of the packet as previously computed.
5162 * @thread E1000_TX
5163 */
5164static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
5165 RTGCPHYS addr, bool fOnWorkerThread)
5166{
5167 int rc = VINF_SUCCESS;
5168
5169 e1kPrintTDesc(pThis, pDesc, "vvv");
5170
5171//#ifdef E1K_USE_TX_TIMERS
5172 if (pThis->fTidEnabled)
5173 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5174//#endif /* E1K_USE_TX_TIMERS */
5175
5176 switch (e1kGetDescType(pDesc))
5177 {
5178 case E1K_DTYP_CONTEXT:
5179 /* The caller have already updated the context */
5180 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5181 e1kDescReport(pDevIns, pThis, pDesc, addr);
5182 break;
5183
5184 case E1K_DTYP_DATA:
5185 {
5186 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5187 &pThis->StatTxDescTSEData:
5188 &pThis->StatTxDescData);
5189 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5190 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5191 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5192 {
5193 E1kLog2(("%s Empty data descriptor, skipped.\n", pThis->szPrf));
5194 if (pDesc->data.cmd.fEOP)
5195 {
5196 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5197 pThis->u16TxPktLen = 0;
5198 }
5199 }
5200 else
5201 {
5202 /*
5203 * Add the descriptor data to the frame. If the frame is complete,
5204 * transmit it and reset the u16TxPktLen field.
5205 */
5206 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5207 {
5208 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5209 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5210 if (pDesc->data.cmd.fEOP)
5211 {
5212 if ( fRc
5213 && pThisCC->CTX_SUFF(pTxSg)
5214 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5215 {
5216 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5217 E1K_INC_CNT32(TSCTC);
5218 }
5219 else
5220 {
5221 if (fRc)
5222 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5223 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5224 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5225 e1kXmitFreeBuf(pThis, pThisCC);
5226 E1K_INC_CNT32(TSCTFC);
5227 }
5228 pThis->u16TxPktLen = 0;
5229 }
5230 }
5231 else if (!pDesc->data.cmd.fTSE)
5232 {
5233 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5234 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5235 if (pDesc->data.cmd.fEOP)
5236 {
5237 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5238 {
5239 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5240 if (pThis->fIPcsum)
5241 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5242 pThis->contextNormal.ip.u8CSO,
5243 pThis->contextNormal.ip.u8CSS,
5244 pThis->contextNormal.ip.u16CSE);
5245 if (pThis->fTCPcsum)
5246 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5247 pThis->contextNormal.tu.u8CSO,
5248 pThis->contextNormal.tu.u8CSS,
5249 pThis->contextNormal.tu.u16CSE,
5250 !pThis->contextNormal.dw2.fTCP);
5251 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5252 }
5253 else
5254 e1kXmitFreeBuf(pThis, pThisCC);
5255 pThis->u16TxPktLen = 0;
5256 }
5257 }
5258 else
5259 {
5260 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5261 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5262 }
5263 }
5264 e1kDescReport(pDevIns, pThis, pDesc, addr);
5265 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5266 break;
5267 }
5268
5269 case E1K_DTYP_LEGACY:
5270 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5271 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5272 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5273 {
5274 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5275 }
5276 else
5277 {
5278 /* Add fragment to frame. */
5279 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5280 {
5281 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5282
5283 /* Last fragment: Transmit and reset the packet storage counter. */
5284 if (pDesc->legacy.cmd.fEOP)
5285 {
5286 if (pDesc->legacy.cmd.fIC)
5287 {
5288 e1kInsertChecksum(pThis,
5289 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5290 pThis->u16TxPktLen,
5291 pDesc->legacy.cmd.u8CSO,
5292 pDesc->legacy.dw3.u8CSS,
5293 0);
5294 }
5295 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5296 pThis->u16TxPktLen = 0;
5297 }
5298 }
5299 /* Last fragment + failure: free the buffer and reset the storage counter. */
5300 else if (pDesc->legacy.cmd.fEOP)
5301 {
5302 e1kXmitFreeBuf(pThis, pThisCC);
5303 pThis->u16TxPktLen = 0;
5304 }
5305 }
5306 e1kDescReport(pDevIns, pThis, pDesc, addr);
5307 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5308 break;
5309
5310 default:
5311 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5312 pThis->szPrf, e1kGetDescType(pDesc)));
5313 break;
5314 }
5315
5316 return rc;
5317}
5318
5319DECLINLINE(bool) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5320{
5321 if (pDesc->context.dw2.fTSE)
5322 {
5323 pThis->contextTSE = pDesc->context;
5324 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5325 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5326 {
5327 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5328 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5329 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5330 }
5331 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5332 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5333 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5334 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5335 }
5336 else
5337 {
5338 pThis->contextNormal = pDesc->context;
5339 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5340 }
5341 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5342 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5343 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5344 pDesc->context.ip.u8CSS,
5345 pDesc->context.ip.u8CSO,
5346 pDesc->context.ip.u16CSE,
5347 pDesc->context.tu.u8CSS,
5348 pDesc->context.tu.u8CSO,
5349 pDesc->context.tu.u16CSE));
5350 return true; /* Consider returning false for invalid descriptors */
5351}
5352
5353static bool e1kLocateTxPacket(PE1KSTATE pThis)
5354{
5355 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5356 pThis->szPrf, pThis->cbTxAlloc));
5357 /* Check if we have located the packet already. */
5358 if (pThis->cbTxAlloc)
5359 {
5360 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5361 pThis->szPrf, pThis->cbTxAlloc));
5362 return true;
5363 }
5364
5365 bool fTSE = false;
5366 uint32_t cbPacket = 0;
5367
5368 /* Since we process one packet at a time we will only mark current packet's descriptors as valid */
5369 memset(pThis->afTxDValid, 0, sizeof(pThis->afTxDValid));
5370 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5371 {
5372 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5373 /* Assume the descriptor valid until proven otherwise. */
5374 pThis->afTxDValid[i] = true;
5375 switch (e1kGetDescType(pDesc))
5376 {
5377 case E1K_DTYP_CONTEXT:
5378 if (cbPacket == 0)
5379 pThis->afTxDValid[i] = e1kUpdateTxContext(pThis, pDesc);
5380 else
5381 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5382 pThis->szPrf, cbPacket));
5383 continue;
5384 case E1K_DTYP_LEGACY:
5385 /* Skip invalid descriptors. */
5386 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5387 {
5388 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5389 pThis->szPrf, cbPacket));
5390 pThis->afTxDValid[i] = false; /* Make sure it is skipped by processing */
5391 continue;
5392 }
5393 /* Skip empty descriptors. */
5394 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5395 break;
5396 cbPacket += pDesc->legacy.cmd.u16Length;
5397 pThis->fGSO = false;
5398 break;
5399 case E1K_DTYP_DATA:
5400 /* Skip invalid descriptors. */
5401 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5402 {
5403 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5404 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5405 pThis->afTxDValid[i] = false; /* Make sure it is skipped by processing */
5406 continue;
5407 }
5408 /* Skip empty descriptors. */
5409 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5410 break;
5411 if (cbPacket == 0)
5412 {
5413 /*
5414 * The first fragment: save IXSM and TXSM options
5415 * as these are only valid in the first fragment.
5416 */
5417 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5418 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5419 fTSE = pDesc->data.cmd.fTSE;
5420 /*
5421 * TSE descriptors have VLE bit properly set in
5422 * the first fragment.
5423 */
5424 if (fTSE)
5425 {
5426 pThis->fVTag = pDesc->data.cmd.fVLE;
5427 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5428 }
5429 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5430 }
5431 cbPacket += pDesc->data.cmd.u20DTALEN;
5432 break;
5433 default:
5434 AssertMsgFailed(("Impossible descriptor type!"));
5435 continue;
5436 }
5437 if (pDesc->legacy.cmd.fEOP)
5438 {
5439 /*
5440 * Non-TSE descriptors have VLE bit properly set in
5441 * the last fragment.
5442 */
5443 if (!fTSE)
5444 {
5445 pThis->fVTag = pDesc->data.cmd.fVLE;
5446 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5447 }
5448 /*
5449 * Compute the required buffer size. If we cannot do GSO but still
5450 * have to do segmentation we allocate the first segment only.
5451 */
5452 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5453 cbPacket :
5454 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5455 /* Do not add VLAN tags to empty packets. */
5456 if (pThis->fVTag && pThis->cbTxAlloc > 0)
5457 pThis->cbTxAlloc += 4;
5458 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5459 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5460 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5461 return true;
5462 }
5463 }
5464
5465 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5466 {
5467 /* All descriptors were empty, we need to process them as a dummy packet */
5468 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5469 pThis->szPrf, pThis->cbTxAlloc));
5470 return true;
5471 }
5472 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5473 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5474 return false;
5475}
5476
5477static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread, PE1KTXDC pTxdc)
5478{
5479 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5480 int rc = VINF_SUCCESS;
5481
5482 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5483 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5484
5485 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5486 {
5487 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5488 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5489 pThis->szPrf, TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC), pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
5490 if (!pThis->afTxDValid[pThis->iTxDCurrent])
5491 {
5492 e1kPrintTDesc(pThis, pDesc, "vvv");
5493 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
5494 e1kDescReport(pDevIns, pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh));
5495 rc = VINF_SUCCESS;
5496 }
5497 else
5498 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh), fOnWorkerThread);
5499 if (RT_FAILURE(rc))
5500 break;
5501 if (++pTxdc->tdh * sizeof(E1KTXDESC) >= pTxdc->tdlen)
5502 pTxdc->tdh = 0;
5503 TDH = pTxdc->tdh; /* Sync the actual register and TXDC */
5504 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5505 if (uLowThreshold != 0 && e1kGetTxLen(pTxdc) <= uLowThreshold)
5506 {
5507 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5508 pThis->szPrf, e1kGetTxLen(pTxdc), GET_BITS(TXDCTL, LWTHRESH)*8));
5509 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5510 }
5511 ++pThis->iTxDCurrent;
5512 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5513 break;
5514 }
5515
5516 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5517 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5518 return rc;
5519}
5520
5521#endif /* E1K_WITH_TXD_CACHE */
5522#ifndef E1K_WITH_TXD_CACHE
5523
5524/**
5525 * Transmit pending descriptors.
5526 *
5527 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5528 *
5529 * @param pDevIns The device instance.
5530 * @param pThis The E1000 state.
5531 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5532 */
5533static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5534{
5535 int rc = VINF_SUCCESS;
5536 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5537
5538 /* Check if transmitter is enabled. */
5539 if (!(TCTL & TCTL_EN))
5540 return VINF_SUCCESS;
5541 /*
5542 * Grab the xmit lock of the driver as well as the E1K device state.
5543 */
5544 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5545 if (RT_LIKELY(rc == VINF_SUCCESS))
5546 {
5547 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5548 if (pDrv)
5549 {
5550 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5551 if (RT_FAILURE(rc))
5552 {
5553 e1kCsTxLeave(pThis);
5554 return rc;
5555 }
5556 }
5557 /*
5558 * Process all pending descriptors.
5559 * Note! Do not process descriptors in locked state
5560 */
5561 while (TDH != TDT && !pThis->fLocked)
5562 {
5563 E1KTXDESC desc;
5564 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5565 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5566
5567 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5568 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5569 /* If we failed to transmit descriptor we will try it again later */
5570 if (RT_FAILURE(rc))
5571 break;
5572 if (++TDH * sizeof(desc) >= TDLEN)
5573 TDH = 0;
5574
5575 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5576 {
5577 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5578 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5579 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5580 }
5581
5582 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5583 }
5584
5585 /// @todo uncomment: pThis->uStatIntTXQE++;
5586 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5587 /*
5588 * Release the lock.
5589 */
5590 if (pDrv)
5591 pDrv->pfnEndXmit(pDrv);
5592 e1kCsTxLeave(pThis);
5593 }
5594
5595 return rc;
5596}
5597
5598#else /* E1K_WITH_TXD_CACHE */
5599
5600static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
5601{
5602 unsigned i, cDescs = pTxdc->tdlen / sizeof(E1KTXDESC);
5603 uint32_t tdh = pTxdc->tdh;
5604 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5605 for (i = 0; i < cDescs; ++i)
5606 {
5607 E1KTXDESC desc;
5608 PDMDevHlpPCIPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5609 if (i == tdh)
5610 LogRel(("E1000: >>> "));
5611 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5612 }
5613 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5614 pThis->iTxDCurrent, pTxdc->tdh, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5615 if (tdh > pThis->iTxDCurrent)
5616 tdh -= pThis->iTxDCurrent;
5617 else
5618 tdh = cDescs + tdh - pThis->iTxDCurrent;
5619 for (i = 0; i < pThis->nTxDFetched; ++i)
5620 {
5621 if (i == pThis->iTxDCurrent)
5622 LogRel(("E1000: >>> "));
5623 if (cDescs)
5624 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5625 else
5626 LogRel(("E1000: <lost>: %R[e1ktxd]\n", &pThis->aTxDescriptors[i]));
5627 }
5628}
5629
5630/**
5631 * Transmit pending descriptors.
5632 *
5633 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5634 *
5635 * @param pDevIns The device instance.
5636 * @param pThis The E1000 state.
5637 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5638 */
5639static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5640{
5641 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5642 int rc = VINF_SUCCESS;
5643
5644 /* Check if transmitter is enabled. */
5645 if (!(TCTL & TCTL_EN))
5646 return VINF_SUCCESS;
5647 /*
5648 * Grab the xmit lock of the driver as well as the E1K device state.
5649 */
5650 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5651 if (pDrv)
5652 {
5653 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5654 if (RT_FAILURE(rc))
5655 return rc;
5656 }
5657
5658 /*
5659 * Process all pending descriptors.
5660 * Note! Do not process descriptors in locked state
5661 */
5662 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5663 if (RT_LIKELY(rc == VINF_SUCCESS && (TCTL & TCTL_EN)))
5664 {
5665 E1KTXDC txdc;
5666 bool fTxContextValid = e1kUpdateTxDContext(pDevIns, pThis, &txdc);
5667 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5668 /*
5669 * fIncomplete is set whenever we try to fetch additional descriptors
5670 * for an incomplete packet. If fail to locate a complete packet on
5671 * the next iteration we need to reset the cache or we risk to get
5672 * stuck in this loop forever.
5673 */
5674 bool fIncomplete = false;
5675 while (fTxContextValid && !pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis, &txdc))
5676 {
5677 while (e1kLocateTxPacket(pThis))
5678 {
5679 fIncomplete = false;
5680 /* Found a complete packet, allocate it. */
5681 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5682 /* If we're out of bandwidth we'll come back later. */
5683 if (RT_FAILURE(rc))
5684 goto out;
5685 /* Copy the packet to allocated buffer and send it. */
5686 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread, &txdc);
5687 /* If we're out of bandwidth we'll come back later. */
5688 if (RT_FAILURE(rc))
5689 goto out;
5690 }
5691 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5692 if (RT_UNLIKELY(fIncomplete))
5693 {
5694 static bool fTxDCacheDumped = false;
5695 /*
5696 * The descriptor cache is full, but we were unable to find
5697 * a complete packet in it. Drop the cache and hope that
5698 * the guest driver can recover from network card error.
5699 */
5700 LogRel(("%s: No complete packets in%s TxD cache! "
5701 "Fetched=%d, current=%d, TX len=%d.\n",
5702 pThis->szPrf,
5703 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5704 pThis->nTxDFetched, pThis->iTxDCurrent,
5705 e1kGetTxLen(&txdc)));
5706 if (!fTxDCacheDumped)
5707 {
5708 fTxDCacheDumped = true;
5709 e1kDumpTxDCache(pDevIns, pThis, &txdc);
5710 }
5711 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5712 /*
5713 * Returning an error at this point means Guru in R0
5714 * (see @bugref{6428}).
5715 */
5716# ifdef IN_RING3
5717 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5718# else /* !IN_RING3 */
5719 rc = VINF_IOM_R3_MMIO_WRITE;
5720# endif /* !IN_RING3 */
5721 goto out;
5722 }
5723 if (u8Remain > 0)
5724 {
5725 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5726 "%d more are available\n",
5727 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5728 e1kGetTxLen(&txdc) - u8Remain));
5729
5730 /*
5731 * A packet was partially fetched. Move incomplete packet to
5732 * the beginning of cache buffer, then load more descriptors.
5733 */
5734 memmove(pThis->aTxDescriptors,
5735 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5736 u8Remain * sizeof(E1KTXDESC));
5737 pThis->iTxDCurrent = 0;
5738 pThis->nTxDFetched = u8Remain;
5739 e1kTxDLoadMore(pDevIns, pThis, &txdc);
5740 fIncomplete = true;
5741 }
5742 else
5743 pThis->nTxDFetched = 0;
5744 pThis->iTxDCurrent = 0;
5745 }
5746 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5747 {
5748 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5749 pThis->szPrf));
5750 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5751 }
5752out:
5753 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5754
5755 /// @todo uncomment: pThis->uStatIntTXQE++;
5756 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5757
5758 e1kCsTxLeave(pThis);
5759 }
5760
5761
5762 /*
5763 * Release the lock.
5764 */
5765 if (pDrv)
5766 pDrv->pfnEndXmit(pDrv);
5767 return rc;
5768}
5769
5770#endif /* E1K_WITH_TXD_CACHE */
5771#ifdef IN_RING3
5772
5773/**
5774 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5775 */
5776static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5777{
5778 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5779 PE1KSTATE pThis = pThisCC->pShared;
5780 /* Resume suspended transmission */
5781 STATUS &= ~STATUS_TXOFF;
5782 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5783}
5784
5785/**
5786 * @callback_method_impl{FNPDMTASKDEV,
5787 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5788 * @note Not executed on EMT.
5789 */
5790static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5791{
5792 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5793 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5794
5795 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5796 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5797
5798 RT_NOREF(rc, pvUser);
5799}
5800
5801#endif /* IN_RING3 */
5802
5803/**
5804 * Write handler for Transmit Descriptor Tail register.
5805 *
5806 * @param pThis The device state structure.
5807 * @param offset Register offset in memory-mapped frame.
5808 * @param index Register index in register array.
5809 * @param value The value to store.
5810 * @param mask Used to implement partial writes (8 and 16-bit).
5811 * @thread EMT
5812 */
5813static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5814{
5815 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5816
5817 /* All descriptors starting with head and not including tail belong to us. */
5818 /* Process them. */
5819 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5820 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5821
5822 /* Compose a temporary TX context, breaking TX CS rule, for debugging purposes. */
5823 /* If we decide to transmit, the TX critical section will be entered later in e1kXmitPending(). */
5824 E1KTXDC txdc;
5825 txdc.tdlen = TDLEN;
5826 txdc.tdh = TDH;
5827 txdc.tdt = TDT;
5828 /* Ignore TDT writes when the link is down. */
5829 if (txdc.tdh != txdc.tdt && (STATUS & STATUS_LU))
5830 {
5831 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", txdc.tdh, txdc.tdt, e1kGetTxLen(&txdc)));
5832 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5833 pThis->szPrf, e1kGetTxLen(&txdc)));
5834
5835 /* Transmit pending packets if possible, defer it if we cannot do it
5836 in the current context. */
5837#ifdef E1K_TX_DELAY
5838 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5839 if (RT_LIKELY(rc == VINF_SUCCESS))
5840 {
5841 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5842 {
5843# ifdef E1K_INT_STATS
5844 pThis->u64ArmedAt = RTTimeNanoTS();
5845# endif
5846 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5847 }
5848 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5849 e1kCsTxLeave(pThis);
5850 return rc;
5851 }
5852 /* We failed to enter the TX critical section -- transmit as usual. */
5853#endif /* E1K_TX_DELAY */
5854#ifndef IN_RING3
5855 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5856 if (!pThisCC->CTX_SUFF(pDrv))
5857 {
5858 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5859 rc = VINF_SUCCESS;
5860 }
5861 else
5862#endif
5863 {
5864 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5865 if (rc == VERR_TRY_AGAIN)
5866 rc = VINF_SUCCESS;
5867#ifndef IN_RING3
5868 else if (rc == VERR_SEM_BUSY)
5869 rc = VINF_IOM_R3_MMIO_WRITE;
5870#endif
5871 AssertRC(rc);
5872 }
5873 }
5874
5875 return rc;
5876}
5877
5878/**
5879 * Write handler for Multicast Table Array registers.
5880 *
5881 * @param pThis The device state structure.
5882 * @param offset Register offset in memory-mapped frame.
5883 * @param index Register index in register array.
5884 * @param value The value to store.
5885 * @thread EMT
5886 */
5887static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5888{
5889 RT_NOREF_PV(pDevIns);
5890 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5891 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5892
5893 return VINF_SUCCESS;
5894}
5895
5896/**
5897 * Read handler for Multicast Table Array registers.
5898 *
5899 * @returns VBox status code.
5900 *
5901 * @param pThis The device state structure.
5902 * @param offset Register offset in memory-mapped frame.
5903 * @param index Register index in register array.
5904 * @thread EMT
5905 */
5906static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5907{
5908 RT_NOREF_PV(pDevIns);
5909 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5910 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5911
5912 return VINF_SUCCESS;
5913}
5914
5915/**
5916 * Write handler for Receive Address registers.
5917 *
5918 * @param pThis The device state structure.
5919 * @param offset Register offset in memory-mapped frame.
5920 * @param index Register index in register array.
5921 * @param value The value to store.
5922 * @thread EMT
5923 */
5924static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5925{
5926 RT_NOREF_PV(pDevIns);
5927 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5928 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5929
5930 return VINF_SUCCESS;
5931}
5932
5933/**
5934 * Read handler for Receive Address registers.
5935 *
5936 * @returns VBox status code.
5937 *
5938 * @param pThis The device state structure.
5939 * @param offset Register offset in memory-mapped frame.
5940 * @param index Register index in register array.
5941 * @thread EMT
5942 */
5943static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5944{
5945 RT_NOREF_PV(pDevIns);
5946 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5947 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5948
5949 return VINF_SUCCESS;
5950}
5951
5952/**
5953 * Write handler for VLAN Filter Table Array registers.
5954 *
5955 * @param pThis The device state structure.
5956 * @param offset Register offset in memory-mapped frame.
5957 * @param index Register index in register array.
5958 * @param value The value to store.
5959 * @thread EMT
5960 */
5961static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5962{
5963 RT_NOREF_PV(pDevIns);
5964 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5965 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5966
5967 return VINF_SUCCESS;
5968}
5969
5970/**
5971 * Read handler for VLAN Filter Table Array registers.
5972 *
5973 * @returns VBox status code.
5974 *
5975 * @param pThis The device state structure.
5976 * @param offset Register offset in memory-mapped frame.
5977 * @param index Register index in register array.
5978 * @thread EMT
5979 */
5980static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5981{
5982 RT_NOREF_PV(pDevIns);
5983 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5984 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5985
5986 return VINF_SUCCESS;
5987}
5988
5989/**
5990 * Read handler for unimplemented registers.
5991 *
5992 * Merely reports reads from unimplemented registers.
5993 *
5994 * @returns VBox status code.
5995 *
5996 * @param pThis The device state structure.
5997 * @param offset Register offset in memory-mapped frame.
5998 * @param index Register index in register array.
5999 * @thread EMT
6000 */
6001static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6002{
6003 RT_NOREF(pDevIns, pThis, offset, index);
6004 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
6005 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6006 *pu32Value = 0;
6007
6008 return VINF_SUCCESS;
6009}
6010
6011/**
6012 * Default register read handler with automatic clear operation.
6013 *
6014 * Retrieves the value of register from register array in device state structure.
6015 * Then resets all bits.
6016 *
6017 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
6018 * done in the caller.
6019 *
6020 * @returns VBox status code.
6021 *
6022 * @param pThis The device state structure.
6023 * @param offset Register offset in memory-mapped frame.
6024 * @param index Register index in register array.
6025 * @thread EMT
6026 */
6027static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6028{
6029 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6030 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
6031 pThis->auRegs[index] = 0;
6032
6033 return rc;
6034}
6035
6036/**
6037 * Default register read handler.
6038 *
6039 * Retrieves the value of register from register array in device state structure.
6040 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
6041 *
6042 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
6043 * done in the caller.
6044 *
6045 * @returns VBox status code.
6046 *
6047 * @param pThis The device state structure.
6048 * @param offset Register offset in memory-mapped frame.
6049 * @param index Register index in register array.
6050 * @thread EMT
6051 */
6052static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6053{
6054 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
6055
6056 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6057 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
6058
6059 return VINF_SUCCESS;
6060}
6061
6062/**
6063 * Write handler for unimplemented registers.
6064 *
6065 * Merely reports writes to unimplemented registers.
6066 *
6067 * @param pThis The device state structure.
6068 * @param offset Register offset in memory-mapped frame.
6069 * @param index Register index in register array.
6070 * @param value The value to store.
6071 * @thread EMT
6072 */
6073
6074 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6075{
6076 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
6077
6078 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
6079 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6080
6081 return VINF_SUCCESS;
6082}
6083
6084/**
6085 * Default register write handler.
6086 *
6087 * Stores the value to the register array in device state structure. Only bits
6088 * corresponding to 1s both in 'writable' and 'mask' will be stored.
6089 *
6090 * @returns VBox status code.
6091 *
6092 * @param pThis The device state structure.
6093 * @param offset Register offset in memory-mapped frame.
6094 * @param index Register index in register array.
6095 * @param value The value to store.
6096 * @param mask Used to implement partial writes (8 and 16-bit).
6097 * @thread EMT
6098 */
6099
6100static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6101{
6102 RT_NOREF(pDevIns, offset);
6103
6104 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6105 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
6106 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
6107
6108 return VINF_SUCCESS;
6109}
6110
6111/**
6112 * Search register table for matching register.
6113 *
6114 * @returns Index in the register table or -1 if not found.
6115 *
6116 * @param offReg Register offset in memory-mapped region.
6117 * @thread EMT
6118 */
6119static int e1kRegLookup(uint32_t offReg)
6120{
6121
6122#if 0
6123 int index;
6124
6125 for (index = 0; index < E1K_NUM_OF_REGS; index++)
6126 {
6127 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
6128 {
6129 return index;
6130 }
6131 }
6132#else
6133 int iStart = 0;
6134 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
6135 for (;;)
6136 {
6137 int i = (iEnd - iStart) / 2 + iStart;
6138 uint32_t offCur = g_aE1kRegMap[i].offset;
6139 if (offReg < offCur)
6140 {
6141 if (i == iStart)
6142 break;
6143 iEnd = i;
6144 }
6145 else if (offReg >= offCur + g_aE1kRegMap[i].size)
6146 {
6147 i++;
6148 if (i == iEnd)
6149 break;
6150 iStart = i;
6151 }
6152 else
6153 return i;
6154 Assert(iEnd > iStart);
6155 }
6156
6157 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6158 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
6159 return (int)i;
6160
6161# ifdef VBOX_STRICT
6162 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6163 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
6164# endif
6165
6166#endif
6167
6168 return -1;
6169}
6170
6171/**
6172 * Handle unaligned register read operation.
6173 *
6174 * Looks up and calls appropriate handler.
6175 *
6176 * @returns VBox status code.
6177 *
6178 * @param pDevIns The device instance.
6179 * @param pThis The device state structure.
6180 * @param offReg Register offset in memory-mapped frame.
6181 * @param pv Where to store the result.
6182 * @param cb Number of bytes to read.
6183 * @thread EMT
6184 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
6185 * accesses we have to take care of that ourselves.
6186 */
6187static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
6188{
6189 uint32_t u32 = 0;
6190 uint32_t shift;
6191 int rc = VINF_SUCCESS;
6192 int index = e1kRegLookup(offReg);
6193#ifdef LOG_ENABLED
6194 char buf[9];
6195#endif
6196
6197 /*
6198 * From the spec:
6199 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6200 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6201 */
6202
6203 /*
6204 * To be able to read bytes and short word we convert them to properly
6205 * shifted 32-bit words and masks. The idea is to keep register-specific
6206 * handlers simple. Most accesses will be 32-bit anyway.
6207 */
6208 uint32_t mask;
6209 switch (cb)
6210 {
6211 case 4: mask = 0xFFFFFFFF; break;
6212 case 2: mask = 0x0000FFFF; break;
6213 case 1: mask = 0x000000FF; break;
6214 default:
6215 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6216 }
6217 if (index >= 0)
6218 {
6219 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6220 if (g_aE1kRegMap[index].readable)
6221 {
6222 /* Make the mask correspond to the bits we are about to read. */
6223 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6224 mask <<= shift;
6225 if (!mask)
6226 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6227 /*
6228 * Read it. Pass the mask so the handler knows what has to be read.
6229 * Mask out irrelevant bits.
6230 */
6231 //e1kCsEnterReturn(pThis, VERR_SEM_BUSY);
6232 //pThis->fDelayInts = false;
6233 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6234 //pThis->iStatIntLostOne = 0;
6235 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6236 u32 &= mask;
6237 //e1kCsLeave(pThis);
6238 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6239 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6240 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6241 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6242 /* Shift back the result. */
6243 u32 >>= shift;
6244 }
6245 else
6246 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6247 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6248 if (IOM_SUCCESS(rc))
6249 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6250 }
6251 else
6252 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6253 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6254
6255 memcpy(pv, &u32, cb);
6256 return rc;
6257}
6258
6259/**
6260 * Handle 4 byte aligned and sized read operation.
6261 *
6262 * Looks up and calls appropriate handler.
6263 *
6264 * @returns VBox status code.
6265 *
6266 * @param pDevIns The device instance.
6267 * @param pThis The device state structure.
6268 * @param offReg Register offset in memory-mapped frame.
6269 * @param pu32 Where to store the result.
6270 * @thread EMT
6271 */
6272static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6273{
6274 Assert(!(offReg & 3));
6275
6276 /*
6277 * Lookup the register and check that it's readable.
6278 */
6279 VBOXSTRICTRC rc = VINF_SUCCESS;
6280 int idxReg = e1kRegLookup(offReg);
6281 if (RT_LIKELY(idxReg >= 0))
6282 {
6283 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6284 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6285 {
6286 /*
6287 * Read it. Pass the mask so the handler knows what has to be read.
6288 * Mask out irrelevant bits.
6289 */
6290 //e1kCsEnterReturn(pThis, VERR_SEM_BUSY);
6291 //pThis->fDelayInts = false;
6292 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6293 //pThis->iStatIntLostOne = 0;
6294 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6295 //e1kCsLeave(pThis);
6296 Log6(("%s At %08X read %08X from %s (%s)\n",
6297 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6298 if (IOM_SUCCESS(rc))
6299 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6300 }
6301 else
6302 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6303 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6304 }
6305 else
6306 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6307 return rc;
6308}
6309
6310/**
6311 * Handle 4 byte sized and aligned register write operation.
6312 *
6313 * Looks up and calls appropriate handler.
6314 *
6315 * @returns VBox status code.
6316 *
6317 * @param pDevIns The device instance.
6318 * @param pThis The device state structure.
6319 * @param offReg Register offset in memory-mapped frame.
6320 * @param u32Value The value to write.
6321 * @thread EMT
6322 */
6323static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6324{
6325 VBOXSTRICTRC rc = VINF_SUCCESS;
6326 int index = e1kRegLookup(offReg);
6327 if (RT_LIKELY(index >= 0))
6328 {
6329 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6330 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6331 {
6332 /*
6333 * Write it. Pass the mask so the handler knows what has to be written.
6334 * Mask out irrelevant bits.
6335 */
6336 Log6(("%s At %08X write %08X to %s (%s)\n",
6337 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6338 //e1kCsEnterReturn(pThis, VERR_SEM_BUSY);
6339 //pThis->fDelayInts = false;
6340 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6341 //pThis->iStatIntLostOne = 0;
6342 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6343 //e1kCsLeave(pThis);
6344 }
6345 else
6346 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6347 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6348 if (IOM_SUCCESS(rc))
6349 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6350 }
6351 else
6352 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6353 pThis->szPrf, offReg, u32Value));
6354 return rc;
6355}
6356
6357
6358/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6359
6360/**
6361 * @callback_method_impl{FNIOMMMIONEWREAD}
6362 */
6363static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6364{
6365 RT_NOREF2(pvUser, cb);
6366 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6367 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6368
6369 Assert(off < E1K_MM_SIZE);
6370 Assert(cb == 4);
6371 Assert(!(off & 3));
6372
6373 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6374
6375 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6376 return rcStrict;
6377}
6378
6379/**
6380 * @callback_method_impl{FNIOMMMIONEWWRITE}
6381 */
6382static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6383{
6384 RT_NOREF2(pvUser, cb);
6385 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6386 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6387
6388 Assert(off < E1K_MM_SIZE);
6389 Assert(cb == 4);
6390 Assert(!(off & 3));
6391
6392 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6393
6394 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6395 return rcStrict;
6396}
6397
6398/**
6399 * @callback_method_impl{FNIOMIOPORTNEWIN}
6400 */
6401static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6402{
6403 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6404 VBOXSTRICTRC rc;
6405 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6406 RT_NOREF_PV(pvUser);
6407
6408 if (RT_LIKELY(cb == 4))
6409 switch (offPort)
6410 {
6411 case 0x00: /* IOADDR */
6412 *pu32 = pThis->uSelectedReg;
6413 Log9(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6414 rc = VINF_SUCCESS;
6415 break;
6416
6417 case 0x04: /* IODATA */
6418 if (!(pThis->uSelectedReg & 3))
6419 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6420 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6421 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6422 if (rc == VINF_IOM_R3_MMIO_READ)
6423 rc = VINF_IOM_R3_IOPORT_READ;
6424 Log9(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6425 break;
6426
6427 default:
6428 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6429 /** @todo r=bird: Check what real hardware returns here. */
6430 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6431 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6432 break;
6433 }
6434 else
6435 {
6436 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6437 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6438 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6439 }
6440 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6441 return rc;
6442}
6443
6444
6445/**
6446 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6447 */
6448static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6449{
6450 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6451 VBOXSTRICTRC rc;
6452 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6453 RT_NOREF_PV(pvUser);
6454
6455 Log9(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6456 if (RT_LIKELY(cb == 4))
6457 {
6458 switch (offPort)
6459 {
6460 case 0x00: /* IOADDR */
6461 pThis->uSelectedReg = u32;
6462 Log9(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6463 rc = VINF_SUCCESS;
6464 break;
6465
6466 case 0x04: /* IODATA */
6467 Log9(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6468 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6469 {
6470 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6471 if (rc == VINF_IOM_R3_MMIO_WRITE)
6472 rc = VINF_IOM_R3_IOPORT_WRITE;
6473 }
6474 else
6475 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6476 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6477 break;
6478
6479 default:
6480 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6481 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6482 }
6483 }
6484 else
6485 {
6486 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6487 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6488 }
6489
6490 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6491 return rc;
6492}
6493
6494#ifdef IN_RING3
6495
6496/**
6497 * Dump complete device state to log.
6498 *
6499 * @param pThis Pointer to device state.
6500 */
6501static void e1kDumpState(PE1KSTATE pThis)
6502{
6503 RT_NOREF(pThis);
6504 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6505 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6506# ifdef E1K_INT_STATS
6507 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6508 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6509 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6510 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6511 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6512 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6513 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6514 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6515 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6516 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6517 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6518 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6519 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6520 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6521 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6522 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6523 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6524 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6525 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6526 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6527 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6528 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6529 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6530 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6531 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6532 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6533 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6534 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6535 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6536 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6537 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6538 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6539 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6540 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6541 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6542 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6543 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6544 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6545 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6546# endif /* E1K_INT_STATS */
6547}
6548
6549
6550/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6551
6552/**
6553 * Check if the device can receive data now.
6554 * This must be called before the pfnRecieve() method is called.
6555 *
6556 * @returns VBox status code.
6557 * @retval VERR_NET_NO_BUFFER_SPACE if we cannot receive.
6558 * @param pDevIns The device instance.
6559 * @param pThis The instance data.
6560 * @thread EMT
6561 */
6562static int e1kR3CanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6563{
6564# ifndef E1K_WITH_RXD_CACHE
6565 size_t cb;
6566
6567 e1kCsRxEnterReturn(pThis);
6568
6569 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6570 {
6571 E1KRXDESC desc;
6572 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6573 if (desc.status.fDD)
6574 cb = 0;
6575 else
6576 cb = pThis->u16RxBSize;
6577 }
6578 else if (RDH < RDT)
6579 cb = (RDT - RDH) * pThis->u16RxBSize;
6580 else if (RDH > RDT)
6581 cb = (RDLEN / sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6582 else
6583 {
6584 cb = 0;
6585 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6586 }
6587 E1kLog2(("%s e1kR3CanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6588 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6589
6590 e1kCsRxLeave(pThis);
6591 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6592# else /* E1K_WITH_RXD_CACHE */
6593
6594 e1kCsRxEnterReturn(pThis);
6595
6596 E1KRXDC rxdc;
6597 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kR3CanReceive")))
6598 {
6599 e1kCsRxLeave(pThis);
6600 E1kLog(("%s e1kR3CanReceive: failed to update Rx context, returning VERR_NET_NO_BUFFER_SPACE\n", pThis->szPrf));
6601 return VERR_NET_NO_BUFFER_SPACE;
6602 }
6603
6604 int rc = VINF_SUCCESS;
6605 if (RT_UNLIKELY(rxdc.rdlen == sizeof(E1KRXDESC)))
6606 {
6607 E1KRXDESC desc;
6608 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, rxdc.rdh), &desc, sizeof(desc));
6609 if (desc.status.fDD)
6610 rc = VERR_NET_NO_BUFFER_SPACE;
6611 }
6612 else if (e1kRxDIsCacheEmpty(pThis) && rxdc.rdh == rxdc.rdt)
6613 {
6614 /* Cache is empty, so is the RX ring. */
6615 rc = VERR_NET_NO_BUFFER_SPACE;
6616 }
6617 E1kLog2(("%s e1kR3CanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6618 e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt, rxdc.rdlen, pThis->u16RxBSize, rc));
6619
6620 e1kCsRxLeave(pThis);
6621 return rc;
6622# endif /* E1K_WITH_RXD_CACHE */
6623}
6624
6625/**
6626 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6627 */
6628static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6629{
6630 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6631 PE1KSTATE pThis = pThisCC->pShared;
6632 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6633
6634 int rc = e1kR3CanReceive(pDevIns, pThis);
6635 if (RT_SUCCESS(rc))
6636 return VINF_SUCCESS;
6637
6638 if (RT_UNLIKELY(cMillies == 0))
6639 return VERR_NET_NO_BUFFER_SPACE;
6640
6641 rc = VERR_INTERRUPTED;
6642 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6643 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6644 VMSTATE enmVMState;
6645 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6646 || enmVMState == VMSTATE_RUNNING_LS))
6647 {
6648 int rc2 = e1kR3CanReceive(pDevIns, pThis);
6649 if (RT_SUCCESS(rc2))
6650 {
6651 rc = VINF_SUCCESS;
6652 break;
6653 }
6654 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6655 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6656 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6657 }
6658 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6659 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6660
6661 return rc;
6662}
6663
6664
6665/**
6666 * Matches the packet addresses against Receive Address table. Looks for
6667 * exact matches only.
6668 *
6669 * @returns true if address matches.
6670 * @param pThis Pointer to the state structure.
6671 * @param pvBuf The ethernet packet.
6672 * @param cb Number of bytes available in the packet.
6673 * @thread EMT
6674 */
6675static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6676{
6677 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6678 {
6679 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6680
6681 /* Valid address? */
6682 if (ra->ctl & RA_CTL_AV)
6683 {
6684 Assert((ra->ctl & RA_CTL_AS) < 2);
6685 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6686 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6687 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6688 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6689 /*
6690 * Address Select:
6691 * 00b = Destination address
6692 * 01b = Source address
6693 * 10b = Reserved
6694 * 11b = Reserved
6695 * Since ethernet header is (DA, SA, len) we can use address
6696 * select as index.
6697 */
6698 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6699 ra->addr, sizeof(ra->addr)) == 0)
6700 return true;
6701 }
6702 }
6703
6704 return false;
6705}
6706
6707/**
6708 * Matches the packet addresses against Multicast Table Array.
6709 *
6710 * @remarks This is imperfect match since it matches not exact address but
6711 * a subset of addresses.
6712 *
6713 * @returns true if address matches.
6714 * @param pThis Pointer to the state structure.
6715 * @param pvBuf The ethernet packet.
6716 * @param cb Number of bytes available in the packet.
6717 * @thread EMT
6718 */
6719static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6720{
6721 /* Get bits 32..47 of destination address */
6722 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6723
6724 unsigned offset = GET_BITS(RCTL, MO);
6725 /*
6726 * offset means:
6727 * 00b = bits 36..47
6728 * 01b = bits 35..46
6729 * 10b = bits 34..45
6730 * 11b = bits 32..43
6731 */
6732 if (offset < 3)
6733 u16Bit = u16Bit >> (4 - offset);
6734 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6735}
6736
6737/**
6738 * Determines if the packet is to be delivered to upper layer.
6739 *
6740 * The following filters supported:
6741 * - Exact Unicast/Multicast
6742 * - Promiscuous Unicast/Multicast
6743 * - Multicast
6744 * - VLAN
6745 *
6746 * @returns true if packet is intended for this node.
6747 * @param pThis Pointer to the state structure.
6748 * @param pvBuf The ethernet packet.
6749 * @param cb Number of bytes available in the packet.
6750 * @param pStatus Bit field to store status bits.
6751 * @thread EMT
6752 */
6753static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6754{
6755 Assert(cb > 14);
6756 /* Assume that we fail to pass exact filter. */
6757 pStatus->fPIF = false;
6758 pStatus->fVP = false;
6759 /* Discard oversized packets */
6760 if (cb > E1K_MAX_RX_PKT_SIZE)
6761 {
6762 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6763 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6764 E1K_INC_CNT32(ROC);
6765 return false;
6766 }
6767 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6768 {
6769 /* When long packet reception is disabled packets over 1522 are discarded */
6770 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6771 pThis->szPrf, cb));
6772 E1K_INC_CNT32(ROC);
6773 return false;
6774 }
6775
6776 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6777 /* Compare TPID with VLAN Ether Type */
6778 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6779 {
6780 pStatus->fVP = true;
6781 /* Is VLAN filtering enabled? */
6782 if (RCTL & RCTL_VFE)
6783 {
6784 /* It is 802.1q packet indeed, let's filter by VID */
6785 if (RCTL & RCTL_CFIEN)
6786 {
6787 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6788 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6789 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6790 !!(RCTL & RCTL_CFI)));
6791 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6792 {
6793 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6794 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6795 return false;
6796 }
6797 }
6798 else
6799 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6800 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6801 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6802 {
6803 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6804 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6805 return false;
6806 }
6807 }
6808 }
6809 /* Broadcast filtering */
6810 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6811 return true;
6812 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6813 if (e1kIsMulticast(pvBuf))
6814 {
6815 /* Is multicast promiscuous enabled? */
6816 if (RCTL & RCTL_MPE)
6817 return true;
6818 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6819 /* Try perfect matches first */
6820 if (e1kPerfectMatch(pThis, pvBuf))
6821 {
6822 pStatus->fPIF = true;
6823 return true;
6824 }
6825 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6826 if (e1kImperfectMatch(pThis, pvBuf))
6827 return true;
6828 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6829 }
6830 else {
6831 /* Is unicast promiscuous enabled? */
6832 if (RCTL & RCTL_UPE)
6833 return true;
6834 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6835 if (e1kPerfectMatch(pThis, pvBuf))
6836 {
6837 pStatus->fPIF = true;
6838 return true;
6839 }
6840 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6841 }
6842 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6843 return false;
6844}
6845
6846/**
6847 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6848 */
6849static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6850{
6851 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6852 PE1KSTATE pThis = pThisCC->pShared;
6853 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6854 int rc = VINF_SUCCESS;
6855
6856 /*
6857 * Drop packets if the VM is not running yet/anymore.
6858 */
6859 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6860 if ( enmVMState != VMSTATE_RUNNING
6861 && enmVMState != VMSTATE_RUNNING_LS)
6862 {
6863 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6864 return VINF_SUCCESS;
6865 }
6866
6867 /* Discard incoming packets in locked state */
6868 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6869 {
6870 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6871 return VINF_SUCCESS;
6872 }
6873
6874 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6875
6876 //e1kR3CsEnterAsserted(pThis);
6877
6878 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6879
6880 /* Update stats */
6881 e1kR3CsEnterAsserted(pThis);
6882 E1K_INC_CNT32(TPR);
6883 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6884 e1kCsLeave(pThis);
6885
6886 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6887 E1KRXDST status;
6888 RT_ZERO(status);
6889 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6890 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6891 if (fPassed)
6892 {
6893 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6894 }
6895 //e1kCsLeave(pThis);
6896 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6897
6898 return rc;
6899}
6900
6901
6902/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6903
6904/**
6905 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6906 */
6907static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6908{
6909 if (iLUN == 0)
6910 {
6911 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6912 *ppLed = &pThisCC->pShared->led;
6913 return VINF_SUCCESS;
6914 }
6915 return VERR_PDM_LUN_NOT_FOUND;
6916}
6917
6918
6919/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6920
6921/**
6922 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6923 */
6924static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6925{
6926 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6927 pThisCC->eeprom.getMac(pMac);
6928 return VINF_SUCCESS;
6929}
6930
6931/**
6932 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6933 */
6934static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6935{
6936 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6937 PE1KSTATE pThis = pThisCC->pShared;
6938 if (STATUS & STATUS_LU)
6939 return PDMNETWORKLINKSTATE_UP;
6940 return PDMNETWORKLINKSTATE_DOWN;
6941}
6942
6943/**
6944 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6945 */
6946static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6947{
6948 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6949 PE1KSTATE pThis = pThisCC->pShared;
6950 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6951
6952 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6953 switch (enmState)
6954 {
6955 case PDMNETWORKLINKSTATE_UP:
6956 pThis->fCableConnected = true;
6957 /* If link was down, bring it up after a while. */
6958 if (!(STATUS & STATUS_LU))
6959 e1kBringLinkUpDelayed(pDevIns, pThis);
6960 break;
6961 case PDMNETWORKLINKSTATE_DOWN:
6962 pThis->fCableConnected = false;
6963 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6964 * We might have to set the link state before the driver initializes us. */
6965 Phy::setLinkStatus(&pThis->phy, false);
6966 /* If link was up, bring it down. */
6967 if (STATUS & STATUS_LU)
6968 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6969 break;
6970 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6971 /*
6972 * There is not much sense in bringing down the link if it has not come up yet.
6973 * If it is up though, we bring it down temporarely, then bring it up again.
6974 */
6975 if (STATUS & STATUS_LU)
6976 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6977 break;
6978 default:
6979 ;
6980 }
6981 return VINF_SUCCESS;
6982}
6983
6984
6985/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6986
6987/**
6988 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6989 */
6990static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6991{
6992 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6993 Assert(&pThisCC->IBase == pInterface);
6994
6995 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6996 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6997 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6998 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6999 return NULL;
7000}
7001
7002
7003/* -=-=-=-=- Saved State -=-=-=-=- */
7004
7005/**
7006 * Saves the configuration.
7007 *
7008 * @param pThis The E1K state.
7009 * @param pSSM The handle to the saved state.
7010 */
7011static void e1kR3SaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
7012{
7013 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
7014 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
7015}
7016
7017/**
7018 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
7019 */
7020static DECLCALLBACK(int) e1kR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
7021{
7022 RT_NOREF(uPass);
7023 e1kR3SaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
7024 return VINF_SSM_DONT_CALL_AGAIN;
7025}
7026
7027/**
7028 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
7029 */
7030static DECLCALLBACK(int) e1kR3SavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7031{
7032 RT_NOREF(pSSM);
7033 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7034
7035 e1kCsEnterReturn(pThis, VERR_SEM_BUSY);
7036 e1kCsLeave(pThis);
7037 return VINF_SUCCESS;
7038#if 0
7039 /* 1) Prevent all threads from modifying the state and memory */
7040 //pThis->fLocked = true;
7041 /* 2) Cancel all timers */
7042#ifdef E1K_TX_DELAY
7043 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7044#endif /* E1K_TX_DELAY */
7045//#ifdef E1K_USE_TX_TIMERS
7046 if (pThis->fTidEnabled)
7047 {
7048 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
7049#ifndef E1K_NO_TAD
7050 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
7051#endif /* E1K_NO_TAD */
7052 }
7053//#endif /* E1K_USE_TX_TIMERS */
7054#ifdef E1K_USE_RX_TIMERS
7055 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
7056 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
7057#endif /* E1K_USE_RX_TIMERS */
7058 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7059 /* 3) Did I forget anything? */
7060 E1kLog(("%s Locked\n", pThis->szPrf));
7061 return VINF_SUCCESS;
7062#endif
7063}
7064
7065/**
7066 * @callback_method_impl{FNSSMDEVSAVEEXEC}
7067 */
7068static DECLCALLBACK(int) e1kR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7069{
7070 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7071 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7072 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7073
7074 e1kR3SaveConfig(pHlp, pThis, pSSM);
7075 pThisCC->eeprom.save(pHlp, pSSM);
7076 e1kDumpState(pThis);
7077 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
7078 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
7079 Phy::saveState(pHlp, pSSM, &pThis->phy);
7080 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
7081 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
7082 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7083 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
7084 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
7085 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
7086 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
7087 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
7088 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
7089/** @todo State wrt to the TSE buffer is incomplete, so little point in
7090 * saving this actually. */
7091 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
7092 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
7093 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
7094 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7095 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7096 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
7097 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
7098#ifdef E1K_WITH_TXD_CACHE
7099# if 0
7100 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
7101 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
7102 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7103# else
7104 /*
7105 * There is no point in storing TX descriptor cache entries as we can simply
7106 * fetch them again. Moreover, normally the cache is always empty when we
7107 * save the state. Store zero entries for compatibility.
7108 */
7109 pHlp->pfnSSMPutU8(pSSM, 0);
7110# endif
7111#endif /* E1K_WITH_TXD_CACHE */
7112/** @todo GSO requires some more state here. */
7113 E1kLog(("%s State has been saved\n", pThis->szPrf));
7114 return VINF_SUCCESS;
7115}
7116
7117#if 0
7118/**
7119 * @callback_method_impl{FNSSMDEVSAVEDONE}
7120 */
7121static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7122{
7123 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7124
7125 /* If VM is being powered off unlocking will result in assertions in PGM */
7126 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
7127 pThis->fLocked = false;
7128 else
7129 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
7130 E1kLog(("%s Unlocked\n", pThis->szPrf));
7131 return VINF_SUCCESS;
7132}
7133#endif
7134
7135/**
7136 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
7137 */
7138static DECLCALLBACK(int) e1kR3LoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7139{
7140 RT_NOREF(pSSM);
7141 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7142
7143 e1kCsEnterReturn(pThis, VERR_SEM_BUSY);
7144 e1kCsLeave(pThis);
7145 return VINF_SUCCESS;
7146}
7147
7148/**
7149 * @callback_method_impl{FNSSMDEVLOADEXEC}
7150 */
7151static DECLCALLBACK(int) e1kR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7152{
7153 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7154 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7155 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7156 int rc;
7157
7158 if ( uVersion != E1K_SAVEDSTATE_VERSION
7159#ifdef E1K_WITH_TXD_CACHE
7160 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
7161#endif /* E1K_WITH_TXD_CACHE */
7162 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
7163 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
7164 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7165
7166 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
7167 || uPass != SSM_PASS_FINAL)
7168 {
7169 /* config checks */
7170 RTMAC macConfigured;
7171 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
7172 AssertRCReturn(rc, rc);
7173 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
7174 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
7175 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
7176
7177 E1KCHIP eChip;
7178 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
7179 AssertRCReturn(rc, rc);
7180 if (eChip != pThis->eChip)
7181 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
7182 }
7183
7184 if (uPass == SSM_PASS_FINAL)
7185 {
7186 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
7187 {
7188 rc = pThisCC->eeprom.load(pHlp, pSSM);
7189 AssertRCReturn(rc, rc);
7190 }
7191 /* the state */
7192 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7193 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7194 /** @todo PHY could be made a separate device with its own versioning */
7195 Phy::loadState(pHlp, pSSM, &pThis->phy);
7196 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7197 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7198 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7199 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7200 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7201 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7202 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7203 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7204 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7205 AssertRCReturn(rc, rc);
7206 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7207 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7208 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7209 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7210 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7211 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7212 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7213 AssertRCReturn(rc, rc);
7214 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7215 {
7216 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7217 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7218 AssertRCReturn(rc, rc);
7219 }
7220 else
7221 {
7222 pThis->fVTag = false;
7223 pThis->u16VTagTCI = 0;
7224 }
7225#ifdef E1K_WITH_TXD_CACHE
7226 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7227 {
7228 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7229 AssertRCReturn(rc, rc);
7230 if (pThis->nTxDFetched)
7231 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7232 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7233 }
7234 else
7235 pThis->nTxDFetched = 0;
7236 /**
7237 * @todo Perhaps we should not store TXD cache as the entries can be
7238 * simply fetched again from guest's memory. Or can't they?
7239 */
7240#endif /* E1K_WITH_TXD_CACHE */
7241#ifdef E1K_WITH_RXD_CACHE
7242 /*
7243 * There is no point in storing the RX descriptor cache in the saved
7244 * state, we just need to make sure it is empty.
7245 */
7246 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7247#endif /* E1K_WITH_RXD_CACHE */
7248 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7249 AssertRCReturn(rc, rc);
7250
7251 /* derived state */
7252 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7253
7254 E1kLog(("%s State has been restored\n", pThis->szPrf));
7255 e1kDumpState(pThis);
7256 }
7257 return VINF_SUCCESS;
7258}
7259
7260/**
7261 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7262 */
7263static DECLCALLBACK(int) e1kR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7264{
7265 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7266 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7267 RT_NOREF(pSSM);
7268
7269 /* Update promiscuous mode */
7270 if (pThisCC->pDrvR3)
7271 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7272
7273 /*
7274 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7275 * passed to us. We go through all this stuff if the link was up and we
7276 * wasn't teleported.
7277 */
7278 if ( (STATUS & STATUS_LU)
7279 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7280 && pThis->cMsLinkUpDelay)
7281 {
7282 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7283 }
7284 return VINF_SUCCESS;
7285}
7286
7287
7288
7289/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7290
7291/**
7292 * @callback_method_impl{FNRTSTRFORMATTYPE}
7293 */
7294static DECLCALLBACK(size_t) e1kR3FmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7295 void *pvArgOutput,
7296 const char *pszType,
7297 void const *pvValue,
7298 int cchWidth,
7299 int cchPrecision,
7300 unsigned fFlags,
7301 void *pvUser)
7302{
7303 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7304 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7305 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7306 if (!pDesc)
7307 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7308
7309 size_t cbPrintf = 0;
7310 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7311 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7312 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7313 pDesc->status.fPIF ? "PIF" : "pif",
7314 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7315 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7316 pDesc->status.fVP ? "VP" : "vp",
7317 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7318 pDesc->status.fEOP ? "EOP" : "eop",
7319 pDesc->status.fDD ? "DD" : "dd",
7320 pDesc->status.fRXE ? "RXE" : "rxe",
7321 pDesc->status.fIPE ? "IPE" : "ipe",
7322 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7323 pDesc->status.fCE ? "CE" : "ce",
7324 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7325 E1K_SPEC_VLAN(pDesc->status.u16Special),
7326 E1K_SPEC_PRI(pDesc->status.u16Special));
7327 return cbPrintf;
7328}
7329
7330/**
7331 * @callback_method_impl{FNRTSTRFORMATTYPE}
7332 */
7333static DECLCALLBACK(size_t) e1kR3FmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7334 void *pvArgOutput,
7335 const char *pszType,
7336 void const *pvValue,
7337 int cchWidth,
7338 int cchPrecision,
7339 unsigned fFlags,
7340 void *pvUser)
7341{
7342 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7343 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7344 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7345 if (!pDesc)
7346 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7347
7348 size_t cbPrintf = 0;
7349 switch (e1kGetDescType(pDesc))
7350 {
7351 case E1K_DTYP_CONTEXT:
7352 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7353 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7354 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7355 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7356 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7357 pDesc->context.dw2.fIDE ? " IDE":"",
7358 pDesc->context.dw2.fRS ? " RS" :"",
7359 pDesc->context.dw2.fTSE ? " TSE":"",
7360 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7361 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7362 pDesc->context.dw2.u20PAYLEN,
7363 pDesc->context.dw3.u8HDRLEN,
7364 pDesc->context.dw3.u16MSS,
7365 pDesc->context.dw3.fDD?"DD":"");
7366 break;
7367 case E1K_DTYP_DATA:
7368 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7369 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7370 pDesc->data.u64BufAddr,
7371 pDesc->data.cmd.u20DTALEN,
7372 pDesc->data.cmd.fIDE ? " IDE" :"",
7373 pDesc->data.cmd.fVLE ? " VLE" :"",
7374 pDesc->data.cmd.fRPS ? " RPS" :"",
7375 pDesc->data.cmd.fRS ? " RS" :"",
7376 pDesc->data.cmd.fTSE ? " TSE" :"",
7377 pDesc->data.cmd.fIFCS? " IFCS":"",
7378 pDesc->data.cmd.fEOP ? " EOP" :"",
7379 pDesc->data.dw3.fDD ? " DD" :"",
7380 pDesc->data.dw3.fEC ? " EC" :"",
7381 pDesc->data.dw3.fLC ? " LC" :"",
7382 pDesc->data.dw3.fTXSM? " TXSM":"",
7383 pDesc->data.dw3.fIXSM? " IXSM":"",
7384 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7385 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7386 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7387 break;
7388 case E1K_DTYP_LEGACY:
7389 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7390 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7391 pDesc->data.u64BufAddr,
7392 pDesc->legacy.cmd.u16Length,
7393 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7394 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7395 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7396 pDesc->legacy.cmd.fRS ? " RS" :"",
7397 pDesc->legacy.cmd.fIC ? " IC" :"",
7398 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7399 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7400 pDesc->legacy.dw3.fDD ? " DD" :"",
7401 pDesc->legacy.dw3.fEC ? " EC" :"",
7402 pDesc->legacy.dw3.fLC ? " LC" :"",
7403 pDesc->legacy.cmd.u8CSO,
7404 pDesc->legacy.dw3.u8CSS,
7405 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7406 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7407 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7408 break;
7409 default:
7410 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7411 break;
7412 }
7413
7414 return cbPrintf;
7415}
7416
7417/** Initializes debug helpers (logging format types). */
7418static int e1kR3InitDebugHelpers(void)
7419{
7420 int rc = VINF_SUCCESS;
7421 static bool s_fHelpersRegistered = false;
7422 if (!s_fHelpersRegistered)
7423 {
7424 s_fHelpersRegistered = true;
7425 rc = RTStrFormatTypeRegister("e1krxd", e1kR3FmtRxDesc, NULL);
7426 AssertRCReturn(rc, rc);
7427 rc = RTStrFormatTypeRegister("e1ktxd", e1kR3FmtTxDesc, NULL);
7428 AssertRCReturn(rc, rc);
7429 }
7430 return rc;
7431}
7432
7433/**
7434 * Status info callback.
7435 *
7436 * @param pDevIns The device instance.
7437 * @param pHlp The output helpers.
7438 * @param pszArgs The arguments.
7439 */
7440static DECLCALLBACK(void) e1kR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7441{
7442 RT_NOREF(pszArgs);
7443 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7444 unsigned i;
7445 // bool fRcvRing = false;
7446 // bool fXmtRing = false;
7447
7448 /*
7449 * Parse args.
7450 if (pszArgs)
7451 {
7452 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7453 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7454 }
7455 */
7456
7457 /*
7458 * Show info.
7459 */
7460 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7461 pDevIns->iInstance,
7462 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7463 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7464 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7465 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7466
7467 e1kR3CsEnterAsserted(pThis); /* Not sure why but PCNet does it */
7468
7469 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7470 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7471
7472 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7473 {
7474 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7475 if (ra->ctl & RA_CTL_AV)
7476 {
7477 const char *pcszTmp;
7478 switch (ra->ctl & RA_CTL_AS)
7479 {
7480 case 0: pcszTmp = "DST"; break;
7481 case 1: pcszTmp = "SRC"; break;
7482 default: pcszTmp = "reserved";
7483 }
7484 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7485 }
7486 }
7487 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7488 uint32_t rdh = RDH;
7489 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7490 for (i = 0; i < cDescs; ++i)
7491 {
7492 E1KRXDESC desc;
7493 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7494 &desc, sizeof(desc));
7495 if (i == rdh)
7496 pHlp->pfnPrintf(pHlp, ">>> ");
7497 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7498 }
7499#ifdef E1K_WITH_RXD_CACHE
7500 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7501 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7502 if (rdh > pThis->iRxDCurrent)
7503 rdh -= pThis->iRxDCurrent;
7504 else
7505 rdh = cDescs + rdh - pThis->iRxDCurrent;
7506 for (i = 0; i < pThis->nRxDFetched; ++i)
7507 {
7508 if (i == pThis->iRxDCurrent)
7509 pHlp->pfnPrintf(pHlp, ">>> ");
7510 if (cDescs)
7511 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7512 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7513 &pThis->aRxDescriptors[i]);
7514 else
7515 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1krxd]\n",
7516 &pThis->aRxDescriptors[i]);
7517 }
7518#endif /* E1K_WITH_RXD_CACHE */
7519
7520 cDescs = TDLEN / sizeof(E1KTXDESC);
7521 uint32_t tdh = TDH;
7522 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7523 for (i = 0; i < cDescs; ++i)
7524 {
7525 E1KTXDESC desc;
7526 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7527 &desc, sizeof(desc));
7528 if (i == tdh)
7529 pHlp->pfnPrintf(pHlp, ">>> ");
7530 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7531 }
7532#ifdef E1K_WITH_TXD_CACHE
7533 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7534 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7535 if (tdh > pThis->iTxDCurrent)
7536 tdh -= pThis->iTxDCurrent;
7537 else
7538 tdh = cDescs + tdh - pThis->iTxDCurrent;
7539 for (i = 0; i < pThis->nTxDFetched; ++i)
7540 {
7541 if (i == pThis->iTxDCurrent)
7542 pHlp->pfnPrintf(pHlp, ">>> ");
7543 if (cDescs)
7544 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7545 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7546 &pThis->aTxDescriptors[i]);
7547 else
7548 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1ktxd]\n",
7549 &pThis->aTxDescriptors[i]);
7550 }
7551#endif /* E1K_WITH_TXD_CACHE */
7552
7553
7554#ifdef E1K_INT_STATS
7555 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7556 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7557 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7558 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7559 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7560 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7561 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7562 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7563 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7564 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7565 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7566 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7567 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7568 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7569 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7570 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7571 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7572 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7573 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7574 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7575 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7576 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7577 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7578 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7579 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7580 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7581 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7582 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7583 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7584 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7585 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7586 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7587 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7588 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7589 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7590 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7591 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7592 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7593#endif /* E1K_INT_STATS */
7594
7595 e1kCsLeave(pThis);
7596}
7597
7598
7599
7600/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7601
7602/**
7603 * Detach notification.
7604 *
7605 * One port on the network card has been disconnected from the network.
7606 *
7607 * @param pDevIns The device instance.
7608 * @param iLUN The logical unit which is being detached.
7609 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7610 */
7611static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7612{
7613 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7614 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7615 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7616 RT_NOREF(fFlags);
7617
7618 AssertLogRelReturnVoid(iLUN == 0);
7619
7620 e1kR3CsEnterAsserted(pThis);
7621
7622 /*
7623 * Zero some important members.
7624 */
7625 pThisCC->pDrvBase = NULL;
7626 pThisCC->pDrvR3 = NULL;
7627#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7628 pThisR0->pDrvR0 = NIL_RTR0PTR;
7629 pThisRC->pDrvRC = NIL_RTRCPTR;
7630#endif
7631
7632 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7633}
7634
7635/**
7636 * Attach the Network attachment.
7637 *
7638 * One port on the network card has been connected to a network.
7639 *
7640 * @returns VBox status code.
7641 * @param pDevIns The device instance.
7642 * @param iLUN The logical unit which is being attached.
7643 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7644 *
7645 * @remarks This code path is not used during construction.
7646 */
7647static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7648{
7649 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7650 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7651 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7652 RT_NOREF(fFlags);
7653
7654 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7655
7656 e1kR3CsEnterAsserted(pThis);
7657
7658 /*
7659 * Attach the driver.
7660 */
7661 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7662 if (RT_SUCCESS(rc))
7663 {
7664 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7665 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7666 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7667 if (RT_SUCCESS(rc))
7668 {
7669#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7670 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7671 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7672#endif
7673 }
7674 }
7675 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7676 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7677 {
7678 /* This should never happen because this function is not called
7679 * if there is no driver to attach! */
7680 Log(("%s No attached driver!\n", pThis->szPrf));
7681 }
7682
7683 /*
7684 * Temporary set the link down if it was up so that the guest will know
7685 * that we have change the configuration of the network card
7686 */
7687 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7688 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7689
7690 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7691 return rc;
7692}
7693
7694/**
7695 * @copydoc FNPDMDEVPOWEROFF
7696 */
7697static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7698{
7699 /* Poke thread waiting for buffer space. */
7700 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7701}
7702
7703/**
7704 * @copydoc FNPDMDEVRESET
7705 */
7706static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7707{
7708 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7709 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7710#ifdef E1K_TX_DELAY
7711 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7712#endif /* E1K_TX_DELAY */
7713 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7714 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7715 e1kXmitFreeBuf(pThis, pThisCC);
7716 pThis->u16TxPktLen = 0;
7717 pThis->fIPcsum = false;
7718 pThis->fTCPcsum = false;
7719 pThis->fIntMaskUsed = false;
7720 pThis->fDelayInts = false;
7721 pThis->fLocked = false;
7722 pThis->u64AckedAt = 0;
7723 e1kR3HardReset(pDevIns, pThis, pThisCC);
7724}
7725
7726/**
7727 * @copydoc FNPDMDEVSUSPEND
7728 */
7729static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7730{
7731 /* Poke thread waiting for buffer space. */
7732 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7733}
7734
7735/**
7736 * Device relocation callback.
7737 *
7738 * When this callback is called the device instance data, and if the
7739 * device have a GC component, is being relocated, or/and the selectors
7740 * have been changed. The device must use the chance to perform the
7741 * necessary pointer relocations and data updates.
7742 *
7743 * Before the GC code is executed the first time, this function will be
7744 * called with a 0 delta so GC pointer calculations can be one in one place.
7745 *
7746 * @param pDevIns Pointer to the device instance.
7747 * @param offDelta The relocation delta relative to the old location.
7748 *
7749 * @remark A relocation CANNOT fail.
7750 */
7751static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7752{
7753 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7754 if (pThisRC)
7755 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7756 RT_NOREF(offDelta);
7757}
7758
7759/**
7760 * Destruct a device instance.
7761 *
7762 * We need to free non-VM resources only.
7763 *
7764 * @returns VBox status code.
7765 * @param pDevIns The device instance data.
7766 * @thread EMT
7767 */
7768static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7769{
7770 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7771 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7772
7773 e1kDumpState(pThis);
7774 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7775 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7776 {
7777 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7778 {
7779 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7780 RTThreadYield();
7781 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7782 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7783 }
7784#ifdef E1K_WITH_TX_CS
7785 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7786#endif /* E1K_WITH_TX_CS */
7787 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7788 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7789 }
7790 return VINF_SUCCESS;
7791}
7792
7793
7794/**
7795 * Set PCI configuration space registers.
7796 *
7797 * @param pci Reference to PCI device structure.
7798 * @thread EMT
7799 */
7800static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7801{
7802 Assert(eChip < RT_ELEMENTS(g_aChips));
7803 /* Configure PCI Device, assume 32-bit mode ******************************/
7804 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7805 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7806 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7807 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7808
7809 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7810 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7811 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7812 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7813 /* Stepping A2 */
7814 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7815 /* Ethernet adapter */
7816 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7817 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7818 /* normal single function Ethernet controller */
7819 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7820 /* Memory Register Base Address */
7821 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7822 /* Memory Flash Base Address */
7823 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7824 /* IO Register Base Address */
7825 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7826 /* Expansion ROM Base Address */
7827 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7828 /* Capabilities Pointer */
7829 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7830 /* Interrupt Pin: INTA# */
7831 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7832 /* Max_Lat/Min_Gnt: very high priority and time slice */
7833 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7834 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7835
7836 /* PCI Power Management Registers ****************************************/
7837 /* Capability ID: PCI Power Management Registers */
7838 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7839 /* Next Item Pointer: PCI-X */
7840 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7841 /* Power Management Capabilities: PM disabled, DSI */
7842 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7843 0x0002 | VBOX_PCI_PM_CAP_DSI);
7844 /* Power Management Control / Status Register: PM disabled */
7845 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7846 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7847 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7848 /* Data Register: PM disabled, always 0 */
7849 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7850
7851 /* PCI-X Configuration Registers *****************************************/
7852 /* Capability ID: PCI-X Configuration Registers */
7853 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7854#ifdef E1K_WITH_MSI
7855 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7856#else
7857 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7858 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7859#endif
7860 /* PCI-X Command: Enable Relaxed Ordering */
7861 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7862 /* PCI-X Status: 32-bit, 66MHz*/
7863 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7864 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7865}
7866
7867/**
7868 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7869 */
7870static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7871{
7872 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7873 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7874 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7875 int rc;
7876
7877 /*
7878 * Initialize the instance data (state).
7879 * Note! Caller has initialized it to ZERO already.
7880 */
7881 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7882 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7883 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7884 pThis->u16TxPktLen = 0;
7885 pThis->fIPcsum = false;
7886 pThis->fTCPcsum = false;
7887 pThis->fIntMaskUsed = false;
7888 pThis->fDelayInts = false;
7889 pThis->fLocked = false;
7890 pThis->u64AckedAt = 0;
7891 pThis->led.u32Magic = PDMLED_MAGIC;
7892 pThis->u32PktNo = 1;
7893
7894 pThisCC->pDevInsR3 = pDevIns;
7895 pThisCC->pShared = pThis;
7896
7897 /* Interfaces */
7898 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7899
7900 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7901 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7902 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7903
7904 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7905
7906 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7907 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7908 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7909
7910 /*
7911 * Internal validations.
7912 */
7913 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7914 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7915 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7916 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7917 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7918 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7919 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7920 VERR_INTERNAL_ERROR_4);
7921
7922 /*
7923 * Validate configuration.
7924 */
7925 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7926 "MAC|"
7927 "CableConnected|"
7928 "AdapterType|"
7929 "LineSpeed|"
7930 "ItrEnabled|"
7931 "ItrRxEnabled|"
7932 "EthernetCRC|"
7933 "GSOEnabled|"
7934 "LinkUpDelay|"
7935 "StatNo",
7936 "");
7937
7938 /** @todo LineSpeed unused! */
7939
7940 /*
7941 * Get config params
7942 */
7943 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7944 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7945 if (RT_FAILURE(rc))
7946 return PDMDEV_SET_ERROR(pDevIns, rc,
7947 N_("Configuration error: Failed to get MAC address"));
7948 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7949 if (RT_FAILURE(rc))
7950 return PDMDEV_SET_ERROR(pDevIns, rc,
7951 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7952 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7953 if (RT_FAILURE(rc))
7954 return PDMDEV_SET_ERROR(pDevIns, rc,
7955 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7956 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7957
7958 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7959 if (RT_FAILURE(rc))
7960 return PDMDEV_SET_ERROR(pDevIns, rc,
7961 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7962
7963 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7964 if (RT_FAILURE(rc))
7965 return PDMDEV_SET_ERROR(pDevIns, rc,
7966 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7967
7968 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7969 if (RT_FAILURE(rc))
7970 return PDMDEV_SET_ERROR(pDevIns, rc,
7971 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7972
7973 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7974 if (RT_FAILURE(rc))
7975 return PDMDEV_SET_ERROR(pDevIns, rc,
7976 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7977
7978 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7979 if (RT_FAILURE(rc))
7980 return PDMDEV_SET_ERROR(pDevIns, rc,
7981 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7982
7983 /*
7984 * Increased the link up delay from 3 to 5 seconds to make sure a guest notices the link loss
7985 * and updates its network configuration when the link is restored. See @bugref{10114}.
7986 */
7987 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 5000); /* ms */
7988 if (RT_FAILURE(rc))
7989 return PDMDEV_SET_ERROR(pDevIns, rc,
7990 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7991 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7992 if (pThis->cMsLinkUpDelay > 5000)
7993 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7994 else if (pThis->cMsLinkUpDelay == 0)
7995 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7996
7997 uint32_t uStatNo = (uint32_t)iInstance;
7998 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7999 if (RT_FAILURE(rc))
8000 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
8001
8002 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
8003 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
8004 pThis->fEthernetCRC ? "on" : "off",
8005 pThis->fGSOEnabled ? "enabled" : "disabled",
8006 pThis->fItrEnabled ? "enabled" : "disabled",
8007 pThis->fItrRxEnabled ? "enabled" : "disabled",
8008 pThis->fTidEnabled ? "enabled" : "disabled",
8009 pDevIns->fR0Enabled ? "enabled" : "disabled",
8010 pDevIns->fRCEnabled ? "enabled" : "disabled"));
8011
8012 /*
8013 * Initialize sub-components and register everything with the VMM.
8014 */
8015
8016 /* Initialize the EEPROM. */
8017 pThisCC->eeprom.init(pThis->macConfigured);
8018
8019 /* Initialize internal PHY. */
8020 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
8021
8022 /* Initialize critical sections. We do our own locking. */
8023 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8024 AssertRCReturn(rc, rc);
8025
8026 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
8027 AssertRCReturn(rc, rc);
8028 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
8029 AssertRCReturn(rc, rc);
8030#ifdef E1K_WITH_TX_CS
8031 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
8032 AssertRCReturn(rc, rc);
8033#endif
8034
8035 /* Saved state registration. */
8036 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
8037 NULL, e1kR3LiveExec, NULL,
8038 e1kR3SavePrep, e1kR3SaveExec, NULL,
8039 e1kR3LoadPrep, e1kR3LoadExec, e1kR3LoadDone);
8040 AssertRCReturn(rc, rc);
8041
8042 /* Set PCI config registers and register ourselves with the PCI bus. */
8043 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
8044 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
8045 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
8046 AssertRCReturn(rc, rc);
8047
8048#ifdef E1K_WITH_MSI
8049 PDMMSIREG MsiReg;
8050 RT_ZERO(MsiReg);
8051 MsiReg.cMsiVectors = 1;
8052 MsiReg.iMsiCapOffset = 0x80;
8053 MsiReg.iMsiNextOffset = 0x0;
8054 MsiReg.fMsi64bit = false;
8055 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
8056 AssertRCReturn(rc, rc);
8057#endif
8058
8059 /*
8060 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
8061 * From the spec (regarding flags):
8062 * For registers that should be accessed as 32-bit double words,
8063 * partial writes (less than a 32-bit double word) is ignored.
8064 * Partial reads return all 32 bits of data regardless of the
8065 * byte enables.
8066 */
8067 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
8068 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
8069 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
8070 AssertRCReturn(rc, rc);
8071 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
8072 AssertRCReturn(rc, rc);
8073
8074 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
8075 static IOMIOPORTDESC const s_aExtDescs[] =
8076 {
8077 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8078 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8079 { NULL, NULL, NULL, NULL }
8080 };
8081 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
8082 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
8083 AssertRCReturn(rc, rc);
8084 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
8085 AssertRCReturn(rc, rc);
8086
8087 /* Create transmit queue */
8088 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
8089 AssertRCReturn(rc, rc);
8090
8091#ifdef E1K_TX_DELAY
8092 /* Create Transmit Delay Timer */
8093 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis,
8094 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Delay", &pThis->hTXDTimer);
8095 AssertRCReturn(rc, rc);
8096 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
8097 AssertRCReturn(rc, rc);
8098#endif /* E1K_TX_DELAY */
8099
8100//#ifdef E1K_USE_TX_TIMERS
8101 if (pThis->fTidEnabled)
8102 {
8103 /* Create Transmit Interrupt Delay Timer */
8104 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis,
8105 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit IRQ Delay", &pThis->hTIDTimer);
8106 AssertRCReturn(rc, rc);
8107
8108# ifndef E1K_NO_TAD
8109 /* Create Transmit Absolute Delay Timer */
8110 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis,
8111 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Abs Delay", &pThis->hTADTimer);
8112 AssertRCReturn(rc, rc);
8113# endif /* E1K_NO_TAD */
8114 }
8115//#endif /* E1K_USE_TX_TIMERS */
8116
8117#ifdef E1K_USE_RX_TIMERS
8118 /* Create Receive Interrupt Delay Timer */
8119 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis,
8120 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv IRQ Delay", &pThis->hRIDTimer);
8121 AssertRCReturn(rc, rc);
8122
8123 /* Create Receive Absolute Delay Timer */
8124 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis,
8125 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv Abs Delay", &pThis->hRADTimer);
8126 AssertRCReturn(rc, rc);
8127#endif /* E1K_USE_RX_TIMERS */
8128
8129 /* Create Late Interrupt Timer */
8130 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis,
8131 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Late IRQ", &pThis->hIntTimer);
8132 AssertRCReturn(rc, rc);
8133
8134 /* Create Link Up Timer */
8135 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis,
8136 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Link Up", &pThis->hLUTimer);
8137 AssertRCReturn(rc, rc);
8138
8139 /* Register the info item */
8140 char szTmp[20];
8141 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
8142 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kR3Info);
8143
8144 /* Status driver */
8145 PPDMIBASE pBase;
8146 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
8147 if (RT_FAILURE(rc))
8148 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
8149 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8150
8151 /* Network driver */
8152 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
8153 if (RT_SUCCESS(rc))
8154 {
8155 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
8156 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
8157
8158#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
8159 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
8160 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
8161#endif
8162 }
8163 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
8164 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
8165 {
8166 /* No error! */
8167 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
8168 }
8169 else
8170 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
8171
8172 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
8173 AssertRCReturn(rc, rc);
8174
8175 rc = e1kR3InitDebugHelpers();
8176 AssertRCReturn(rc, rc);
8177
8178 e1kR3HardReset(pDevIns, pThis, pThisCC);
8179
8180 /*
8181 * Register statistics.
8182 * The /Public/ bits are official and used by session info in the GUI.
8183 */
8184 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8185 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
8186 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8187 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
8188 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8189 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
8190
8191 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
8192 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
8193
8194#if defined(VBOX_WITH_STATISTICS)
8195 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
8196 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
8197 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
8198 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
8199 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8200 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8201 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8202 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8203 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8204 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8205 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8206 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8207 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8208 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8209 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8210 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8211 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8212 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8213 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8214 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8215 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8216 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8217 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8218 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8219 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8220
8221 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8222 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8223 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8224 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8225 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8226 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8227 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8228 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8229 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8230 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8231 {
8232 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8233 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8234 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8235 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8236 }
8237#endif /* VBOX_WITH_STATISTICS */
8238
8239#ifdef E1K_INT_STATS
8240 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8241 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8242 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8243 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8244 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8245 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8246 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8247 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8248 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8249 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8250 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8251 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8252 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8253 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8254 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8255 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8256 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8257 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8258 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8259 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8260 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8261 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8262 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8263 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8264 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8265 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8266 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8267 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8268 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8269 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8270 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8271 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8272 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8273 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8274 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8275 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8276 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8277 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8278 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8279 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8280 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8281#endif /* E1K_INT_STATS */
8282
8283 return VINF_SUCCESS;
8284}
8285
8286#else /* !IN_RING3 */
8287
8288/**
8289 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8290 */
8291static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8292{
8293 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8294 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8295 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8296
8297 /* Initialize context specific state data: */
8298 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8299 /** @todo @bugref{9218} ring-0 driver stuff */
8300 pThisCC->CTX_SUFF(pDrv) = NULL;
8301 pThisCC->CTX_SUFF(pTxSg) = NULL;
8302
8303 /* Configure critical sections the same way: */
8304 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8305 AssertRCReturn(rc, rc);
8306
8307 /* Set up MMIO and I/O port callbacks for this context: */
8308 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8309 AssertRCReturn(rc, rc);
8310
8311 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8312 AssertRCReturn(rc, rc);
8313
8314 return VINF_SUCCESS;
8315}
8316
8317#endif /* !IN_RING3 */
8318
8319/**
8320 * The device registration structure.
8321 */
8322const PDMDEVREG g_DeviceE1000 =
8323{
8324 /* .u32version = */ PDM_DEVREG_VERSION,
8325 /* .uReserved0 = */ 0,
8326 /* .szName = */ "e1000",
8327 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8328 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8329 /* .cMaxInstances = */ ~0U,
8330 /* .uSharedVersion = */ 42,
8331 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8332 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8333 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8334 /* .cMaxPciDevices = */ 1,
8335 /* .cMaxMsixVectors = */ 0,
8336 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8337#if defined(IN_RING3)
8338 /* .pszRCMod = */ "VBoxDDRC.rc",
8339 /* .pszR0Mod = */ "VBoxDDR0.r0",
8340 /* .pfnConstruct = */ e1kR3Construct,
8341 /* .pfnDestruct = */ e1kR3Destruct,
8342 /* .pfnRelocate = */ e1kR3Relocate,
8343 /* .pfnMemSetup = */ NULL,
8344 /* .pfnPowerOn = */ NULL,
8345 /* .pfnReset = */ e1kR3Reset,
8346 /* .pfnSuspend = */ e1kR3Suspend,
8347 /* .pfnResume = */ NULL,
8348 /* .pfnAttach = */ e1kR3Attach,
8349 /* .pfnDeatch = */ e1kR3Detach,
8350 /* .pfnQueryInterface = */ NULL,
8351 /* .pfnInitComplete = */ NULL,
8352 /* .pfnPowerOff = */ e1kR3PowerOff,
8353 /* .pfnSoftReset = */ NULL,
8354 /* .pfnReserved0 = */ NULL,
8355 /* .pfnReserved1 = */ NULL,
8356 /* .pfnReserved2 = */ NULL,
8357 /* .pfnReserved3 = */ NULL,
8358 /* .pfnReserved4 = */ NULL,
8359 /* .pfnReserved5 = */ NULL,
8360 /* .pfnReserved6 = */ NULL,
8361 /* .pfnReserved7 = */ NULL,
8362#elif defined(IN_RING0)
8363 /* .pfnEarlyConstruct = */ NULL,
8364 /* .pfnConstruct = */ e1kRZConstruct,
8365 /* .pfnDestruct = */ NULL,
8366 /* .pfnFinalDestruct = */ NULL,
8367 /* .pfnRequest = */ NULL,
8368 /* .pfnReserved0 = */ NULL,
8369 /* .pfnReserved1 = */ NULL,
8370 /* .pfnReserved2 = */ NULL,
8371 /* .pfnReserved3 = */ NULL,
8372 /* .pfnReserved4 = */ NULL,
8373 /* .pfnReserved5 = */ NULL,
8374 /* .pfnReserved6 = */ NULL,
8375 /* .pfnReserved7 = */ NULL,
8376#elif defined(IN_RC)
8377 /* .pfnConstruct = */ e1kRZConstruct,
8378 /* .pfnReserved0 = */ NULL,
8379 /* .pfnReserved1 = */ NULL,
8380 /* .pfnReserved2 = */ NULL,
8381 /* .pfnReserved3 = */ NULL,
8382 /* .pfnReserved4 = */ NULL,
8383 /* .pfnReserved5 = */ NULL,
8384 /* .pfnReserved6 = */ NULL,
8385 /* .pfnReserved7 = */ NULL,
8386#else
8387# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8388#endif
8389 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8390};
8391
8392#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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