VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 24074

Last change on this file since 24074 was 24039, checked in by vboxsync, 15 years ago

DevE1000.cpp: Enable the new saved state version (2) that includes config and the EEPROM.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 204.1 KB
Line 
1/* $Id: DevE1000.cpp 24039 2009-10-23 14:18:09Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo VLAN checksum offloading support
14 * @todo Flexible Filter / Wakeup (optional?)
15 */
16
17/*
18 * Copyright (C) 2007 Sun Microsystems, Inc.
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 *
28 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
29 * Clara, CA 95054 USA or visit http://www.sun.com if you need
30 * additional information or have any questions.
31 */
32
33
34#define LOG_GROUP LOG_GROUP_DEV_E1000
35
36//#define E1kLogRel(a) LogRel(a)
37#define E1kLogRel(a)
38
39/* Options */
40#define E1K_ITR_ENABLED
41//#define E1K_GLOBAL_MUTEX
42//#define E1K_USE_TX_TIMERS
43//#define E1K_NO_TAD
44//#define E1K_REL_DEBUG
45//#define E1K_INT_STATS
46//#define E1K_REL_STATS
47
48#include <iprt/crc32.h>
49#include <iprt/ctype.h>
50#include <iprt/net.h>
51#include <iprt/semaphore.h>
52#include <iprt/string.h>
53#include <VBox/pdmdev.h>
54#include <VBox/tm.h>
55#include <VBox/vm.h>
56#include "../Builtins.h"
57
58#include "DevEEPROM.h"
59#include "DevE1000Phy.h"
60
61/* Little helpers ************************************************************/
62#undef htons
63#undef ntohs
64#undef htonl
65#undef ntohl
66#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
67#define ntohs(x) htons(x)
68#define htonl(x) ASMByteSwapU32(x)
69#define ntohl(x) htonl(x)
70
71#ifndef DEBUG
72# ifdef E1K_REL_STATS
73# undef STAM_COUNTER_INC
74# undef STAM_PROFILE_ADV_START
75# undef STAM_PROFILE_ADV_STOP
76# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
77# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
78# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
79# endif
80# ifdef E1K_REL_DEBUG
81# define DEBUG
82# define E1kLog(a) LogRel(a)
83# define E1kLog2(a) LogRel(a)
84# define E1kLog3(a) LogRel(a)
85//# define E1kLog3(a) do {} while (0)
86# else
87# define E1kLog(a) do {} while (0)
88# define E1kLog2(a) do {} while (0)
89# define E1kLog3(a) do {} while (0)
90# endif
91#else
92# define E1kLog(a) Log(a)
93# define E1kLog2(a) Log2(a)
94# define E1kLog3(a) Log3(a)
95//# define E1kLog(a) do {} while (0)
96//# define E1kLog2(a) do {} while (0)
97//# define E1kLog3(a) do {} while (0)
98#endif
99
100//#undef DEBUG
101
102#define INSTANCE(pState) pState->szInstance
103#define IFACE_TO_STATE(pIface, ifaceName) ((E1KSTATE *)((char*)pIface - RT_OFFSETOF(E1KSTATE, ifaceName)))
104#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
105
106#define E1K_INC_CNT32(cnt) \
107do { \
108 if (cnt < UINT32_MAX) \
109 cnt++; \
110} while (0)
111
112#define E1K_ADD_CNT64(cntLo, cntHi, val) \
113do { \
114 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
115 uint64_t tmp = u64Cnt; \
116 u64Cnt += val; \
117 if (tmp > u64Cnt ) \
118 u64Cnt = UINT64_MAX; \
119 cntLo = (uint32_t)u64Cnt; \
120 cntHi = (uint32_t)(u64Cnt >> 32); \
121} while (0)
122
123#ifdef E1K_INT_STATS
124# define E1K_INC_ISTAT_CNT(cnt) ++cnt
125#else /* E1K_INT_STATS */
126# define E1K_INC_ISTAT_CNT(cnt)
127#endif /* E1K_INT_STATS */
128
129
130/*****************************************************************************/
131
132typedef uint32_t E1KCHIP;
133#define E1K_CHIP_82540EM 0
134#define E1K_CHIP_82543GC 1
135#define E1K_CHIP_82545EM 2
136
137struct E1kChips
138{
139 uint16_t uPCIVendorId;
140 uint16_t uPCIDeviceId;
141 uint16_t uPCISubsystemVendorId;
142 uint16_t uPCISubsystemId;
143 const char *pcszName;
144} g_Chips[] =
145{
146 /* Vendor Device SSVendor SubSys Name */
147 { 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
148 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
149 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
150};
151
152
153/* The size of register area mapped to I/O space */
154#define E1K_IOPORT_SIZE 0x8
155/* The size of memory-mapped register area */
156#define E1K_MM_SIZE 0x20000
157
158#define E1K_MAX_TX_PKT_SIZE 16288
159#define E1K_MAX_RX_PKT_SIZE 16384
160
161/*****************************************************************************/
162
163#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
164#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
165#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
166#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
167#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
168
169#define CTRL_SLU 0x00000040
170#define CTRL_MDIO 0x00100000
171#define CTRL_MDC 0x00200000
172#define CTRL_MDIO_DIR 0x01000000
173#define CTRL_MDC_DIR 0x02000000
174#define CTRL_RESET 0x04000000
175#define CTRL_VME 0x40000000
176
177#define STATUS_LU 0x00000002
178
179#define EECD_EE_WIRES 0x0F
180#define EECD_EE_REQ 0x40
181#define EECD_EE_GNT 0x80
182
183#define MDIC_DATA_MASK 0x0000FFFF
184#define MDIC_DATA_SHIFT 0
185#define MDIC_REG_MASK 0x001F0000
186#define MDIC_REG_SHIFT 16
187#define MDIC_PHY_MASK 0x03E00000
188#define MDIC_PHY_SHIFT 21
189#define MDIC_OP_WRITE 0x04000000
190#define MDIC_OP_READ 0x08000000
191#define MDIC_READY 0x10000000
192#define MDIC_INT_EN 0x20000000
193#define MDIC_ERROR 0x40000000
194
195#define TCTL_EN 0x00000002
196#define TCTL_PSP 0x00000008
197
198#define RCTL_EN 0x00000002
199#define RCTL_UPE 0x00000008
200#define RCTL_MPE 0x00000010
201#define RCTL_LPE 0x00000020
202#define RCTL_LBM_MASK 0x000000C0
203#define RCTL_LBM_SHIFT 6
204#define RCTL_RDMTS_MASK 0x00000300
205#define RCTL_RDMTS_SHIFT 8
206#define RCTL_LBM_TCVR 3
207#define RCTL_MO_MASK 0x00003000
208#define RCTL_MO_SHIFT 12
209#define RCTL_BAM 0x00008000
210#define RCTL_BSIZE_MASK 0x00030000
211#define RCTL_BSIZE_SHIFT 16
212#define RCTL_VFE 0x00040000
213#define RCTL_BSEX 0x02000000
214#define RCTL_SECRC 0x04000000
215
216#define ICR_TXDW 0x00000001
217#define ICR_TXQE 0x00000002
218#define ICR_LSC 0x00000004
219#define ICR_RXDMT0 0x00000010
220#define ICR_RXT0 0x00000080
221#define ICR_TXD_LOW 0x00008000
222#define RDTR_FPD 0x80000000
223
224#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
225typedef struct
226{
227 unsigned rxa : 7;
228 unsigned rxa_r : 9;
229 unsigned txa : 16;
230} PBAST;
231AssertCompileSize(PBAST, 4);
232
233#define TXDCTL_WTHRESH_MASK 0x003F0000
234#define TXDCTL_WTHRESH_SHIFT 16
235#define TXDCTL_LWTHRESH_MASK 0xFE000000
236#define TXDCTL_LWTHRESH_SHIFT 25
237
238#define RXCSUM_PCSS_MASK 0x000000FF
239#define RXCSUM_PCSS_SHIFT 0
240
241/* Register access macros ****************************************************/
242#define CTRL pState->auRegs[CTRL_IDX]
243#define STATUS pState->auRegs[STATUS_IDX]
244#define EECD pState->auRegs[EECD_IDX]
245#define EERD pState->auRegs[EERD_IDX]
246#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
247#define FLA pState->auRegs[FLA_IDX]
248#define MDIC pState->auRegs[MDIC_IDX]
249#define FCAL pState->auRegs[FCAL_IDX]
250#define FCAH pState->auRegs[FCAH_IDX]
251#define FCT pState->auRegs[FCT_IDX]
252#define VET pState->auRegs[VET_IDX]
253#define ICR pState->auRegs[ICR_IDX]
254#define ITR pState->auRegs[ITR_IDX]
255#define ICS pState->auRegs[ICS_IDX]
256#define IMS pState->auRegs[IMS_IDX]
257#define IMC pState->auRegs[IMC_IDX]
258#define RCTL pState->auRegs[RCTL_IDX]
259#define FCTTV pState->auRegs[FCTTV_IDX]
260#define TXCW pState->auRegs[TXCW_IDX]
261#define RXCW pState->auRegs[RXCW_IDX]
262#define TCTL pState->auRegs[TCTL_IDX]
263#define TIPG pState->auRegs[TIPG_IDX]
264#define AIFS pState->auRegs[AIFS_IDX]
265#define LEDCTL pState->auRegs[LEDCTL_IDX]
266#define PBA pState->auRegs[PBA_IDX]
267#define FCRTL pState->auRegs[FCRTL_IDX]
268#define FCRTH pState->auRegs[FCRTH_IDX]
269#define RDFH pState->auRegs[RDFH_IDX]
270#define RDFT pState->auRegs[RDFT_IDX]
271#define RDFHS pState->auRegs[RDFHS_IDX]
272#define RDFTS pState->auRegs[RDFTS_IDX]
273#define RDFPC pState->auRegs[RDFPC_IDX]
274#define RDBAL pState->auRegs[RDBAL_IDX]
275#define RDBAH pState->auRegs[RDBAH_IDX]
276#define RDLEN pState->auRegs[RDLEN_IDX]
277#define RDH pState->auRegs[RDH_IDX]
278#define RDT pState->auRegs[RDT_IDX]
279#define RDTR pState->auRegs[RDTR_IDX]
280#define RXDCTL pState->auRegs[RXDCTL_IDX]
281#define RADV pState->auRegs[RADV_IDX]
282#define RSRPD pState->auRegs[RSRPD_IDX]
283#define TXDMAC pState->auRegs[TXDMAC_IDX]
284#define TDFH pState->auRegs[TDFH_IDX]
285#define TDFT pState->auRegs[TDFT_IDX]
286#define TDFHS pState->auRegs[TDFHS_IDX]
287#define TDFTS pState->auRegs[TDFTS_IDX]
288#define TDFPC pState->auRegs[TDFPC_IDX]
289#define TDBAL pState->auRegs[TDBAL_IDX]
290#define TDBAH pState->auRegs[TDBAH_IDX]
291#define TDLEN pState->auRegs[TDLEN_IDX]
292#define TDH pState->auRegs[TDH_IDX]
293#define TDT pState->auRegs[TDT_IDX]
294#define TIDV pState->auRegs[TIDV_IDX]
295#define TXDCTL pState->auRegs[TXDCTL_IDX]
296#define TADV pState->auRegs[TADV_IDX]
297#define TSPMT pState->auRegs[TSPMT_IDX]
298#define CRCERRS pState->auRegs[CRCERRS_IDX]
299#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
300#define SYMERRS pState->auRegs[SYMERRS_IDX]
301#define RXERRC pState->auRegs[RXERRC_IDX]
302#define MPC pState->auRegs[MPC_IDX]
303#define SCC pState->auRegs[SCC_IDX]
304#define ECOL pState->auRegs[ECOL_IDX]
305#define MCC pState->auRegs[MCC_IDX]
306#define LATECOL pState->auRegs[LATECOL_IDX]
307#define COLC pState->auRegs[COLC_IDX]
308#define DC pState->auRegs[DC_IDX]
309#define TNCRS pState->auRegs[TNCRS_IDX]
310#define SEC pState->auRegs[SEC_IDX]
311#define CEXTERR pState->auRegs[CEXTERR_IDX]
312#define RLEC pState->auRegs[RLEC_IDX]
313#define XONRXC pState->auRegs[XONRXC_IDX]
314#define XONTXC pState->auRegs[XONTXC_IDX]
315#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
316#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
317#define FCRUC pState->auRegs[FCRUC_IDX]
318#define PRC64 pState->auRegs[PRC64_IDX]
319#define PRC127 pState->auRegs[PRC127_IDX]
320#define PRC255 pState->auRegs[PRC255_IDX]
321#define PRC511 pState->auRegs[PRC511_IDX]
322#define PRC1023 pState->auRegs[PRC1023_IDX]
323#define PRC1522 pState->auRegs[PRC1522_IDX]
324#define GPRC pState->auRegs[GPRC_IDX]
325#define BPRC pState->auRegs[BPRC_IDX]
326#define MPRC pState->auRegs[MPRC_IDX]
327#define GPTC pState->auRegs[GPTC_IDX]
328#define GORCL pState->auRegs[GORCL_IDX]
329#define GORCH pState->auRegs[GORCH_IDX]
330#define GOTCL pState->auRegs[GOTCL_IDX]
331#define GOTCH pState->auRegs[GOTCH_IDX]
332#define RNBC pState->auRegs[RNBC_IDX]
333#define RUC pState->auRegs[RUC_IDX]
334#define RFC pState->auRegs[RFC_IDX]
335#define ROC pState->auRegs[ROC_IDX]
336#define RJC pState->auRegs[RJC_IDX]
337#define MGTPRC pState->auRegs[MGTPRC_IDX]
338#define MGTPDC pState->auRegs[MGTPDC_IDX]
339#define MGTPTC pState->auRegs[MGTPTC_IDX]
340#define TORL pState->auRegs[TORL_IDX]
341#define TORH pState->auRegs[TORH_IDX]
342#define TOTL pState->auRegs[TOTL_IDX]
343#define TOTH pState->auRegs[TOTH_IDX]
344#define TPR pState->auRegs[TPR_IDX]
345#define TPT pState->auRegs[TPT_IDX]
346#define PTC64 pState->auRegs[PTC64_IDX]
347#define PTC127 pState->auRegs[PTC127_IDX]
348#define PTC255 pState->auRegs[PTC255_IDX]
349#define PTC511 pState->auRegs[PTC511_IDX]
350#define PTC1023 pState->auRegs[PTC1023_IDX]
351#define PTC1522 pState->auRegs[PTC1522_IDX]
352#define MPTC pState->auRegs[MPTC_IDX]
353#define BPTC pState->auRegs[BPTC_IDX]
354#define TSCTC pState->auRegs[TSCTC_IDX]
355#define TSCTFC pState->auRegs[TSCTFC_IDX]
356#define RXCSUM pState->auRegs[RXCSUM_IDX]
357#define WUC pState->auRegs[WUC_IDX]
358#define WUFC pState->auRegs[WUFC_IDX]
359#define WUS pState->auRegs[WUS_IDX]
360#define MANC pState->auRegs[MANC_IDX]
361#define IPAV pState->auRegs[IPAV_IDX]
362#define WUPL pState->auRegs[WUPL_IDX]
363
364/**
365 * Indices of memory-mapped registers in register table
366 */
367typedef enum
368{
369 CTRL_IDX,
370 STATUS_IDX,
371 EECD_IDX,
372 EERD_IDX,
373 CTRL_EXT_IDX,
374 FLA_IDX,
375 MDIC_IDX,
376 FCAL_IDX,
377 FCAH_IDX,
378 FCT_IDX,
379 VET_IDX,
380 ICR_IDX,
381 ITR_IDX,
382 ICS_IDX,
383 IMS_IDX,
384 IMC_IDX,
385 RCTL_IDX,
386 FCTTV_IDX,
387 TXCW_IDX,
388 RXCW_IDX,
389 TCTL_IDX,
390 TIPG_IDX,
391 AIFS_IDX,
392 LEDCTL_IDX,
393 PBA_IDX,
394 FCRTL_IDX,
395 FCRTH_IDX,
396 RDFH_IDX,
397 RDFT_IDX,
398 RDFHS_IDX,
399 RDFTS_IDX,
400 RDFPC_IDX,
401 RDBAL_IDX,
402 RDBAH_IDX,
403 RDLEN_IDX,
404 RDH_IDX,
405 RDT_IDX,
406 RDTR_IDX,
407 RXDCTL_IDX,
408 RADV_IDX,
409 RSRPD_IDX,
410 TXDMAC_IDX,
411 TDFH_IDX,
412 TDFT_IDX,
413 TDFHS_IDX,
414 TDFTS_IDX,
415 TDFPC_IDX,
416 TDBAL_IDX,
417 TDBAH_IDX,
418 TDLEN_IDX,
419 TDH_IDX,
420 TDT_IDX,
421 TIDV_IDX,
422 TXDCTL_IDX,
423 TADV_IDX,
424 TSPMT_IDX,
425 CRCERRS_IDX,
426 ALGNERRC_IDX,
427 SYMERRS_IDX,
428 RXERRC_IDX,
429 MPC_IDX,
430 SCC_IDX,
431 ECOL_IDX,
432 MCC_IDX,
433 LATECOL_IDX,
434 COLC_IDX,
435 DC_IDX,
436 TNCRS_IDX,
437 SEC_IDX,
438 CEXTERR_IDX,
439 RLEC_IDX,
440 XONRXC_IDX,
441 XONTXC_IDX,
442 XOFFRXC_IDX,
443 XOFFTXC_IDX,
444 FCRUC_IDX,
445 PRC64_IDX,
446 PRC127_IDX,
447 PRC255_IDX,
448 PRC511_IDX,
449 PRC1023_IDX,
450 PRC1522_IDX,
451 GPRC_IDX,
452 BPRC_IDX,
453 MPRC_IDX,
454 GPTC_IDX,
455 GORCL_IDX,
456 GORCH_IDX,
457 GOTCL_IDX,
458 GOTCH_IDX,
459 RNBC_IDX,
460 RUC_IDX,
461 RFC_IDX,
462 ROC_IDX,
463 RJC_IDX,
464 MGTPRC_IDX,
465 MGTPDC_IDX,
466 MGTPTC_IDX,
467 TORL_IDX,
468 TORH_IDX,
469 TOTL_IDX,
470 TOTH_IDX,
471 TPR_IDX,
472 TPT_IDX,
473 PTC64_IDX,
474 PTC127_IDX,
475 PTC255_IDX,
476 PTC511_IDX,
477 PTC1023_IDX,
478 PTC1522_IDX,
479 MPTC_IDX,
480 BPTC_IDX,
481 TSCTC_IDX,
482 TSCTFC_IDX,
483 RXCSUM_IDX,
484 WUC_IDX,
485 WUFC_IDX,
486 WUS_IDX,
487 MANC_IDX,
488 IPAV_IDX,
489 WUPL_IDX,
490 MTA_IDX,
491 RA_IDX,
492 VFTA_IDX,
493 IP4AT_IDX,
494 IP6AT_IDX,
495 WUPM_IDX,
496 FFLT_IDX,
497 FFMT_IDX,
498 FFVT_IDX,
499 PBM_IDX,
500 RA_82542_IDX,
501 MTA_82542_IDX,
502 VFTA_82542_IDX,
503 E1K_NUM_OF_REGS
504} E1kRegIndex;
505
506#define E1K_NUM_OF_32BIT_REGS MTA_IDX
507
508
509/**
510 * Define E1000-specific EEPROM layout.
511 */
512class E1kEEPROM
513{
514 public:
515 EEPROM93C46 eeprom;
516
517#ifdef IN_RING3
518 /**
519 * Initialize EEPROM content.
520 *
521 * @param macAddr MAC address of E1000.
522 */
523 void init(RTMAC &macAddr)
524 {
525 eeprom.init();
526 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
527 eeprom.m_au16Data[0x04] = 0xFFFF;
528 /*
529 * bit 3 - full support for power management
530 * bit 10 - full duplex
531 */
532 eeprom.m_au16Data[0x0A] = 0x4408;
533 eeprom.m_au16Data[0x0B] = 0x001E;
534 eeprom.m_au16Data[0x0C] = 0x8086;
535 eeprom.m_au16Data[0x0D] = 0x100E;
536 eeprom.m_au16Data[0x0E] = 0x8086;
537 eeprom.m_au16Data[0x0F] = 0x3040;
538 eeprom.m_au16Data[0x21] = 0x7061;
539 eeprom.m_au16Data[0x22] = 0x280C;
540 eeprom.m_au16Data[0x23] = 0x00C8;
541 eeprom.m_au16Data[0x24] = 0x00C8;
542 eeprom.m_au16Data[0x2F] = 0x0602;
543 updateChecksum();
544 };
545
546 /**
547 * Compute the checksum as required by E1000 and store it
548 * in the last word.
549 */
550 void updateChecksum()
551 {
552 uint16_t u16Checksum = 0;
553
554 for (int i = 0; i < eeprom.SIZE-1; i++)
555 u16Checksum += eeprom.m_au16Data[i];
556 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
557 };
558
559 /**
560 * First 6 bytes of EEPROM contain MAC address.
561 *
562 * @returns MAC address of E1000.
563 */
564 void getMac(PRTMAC pMac)
565 {
566 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
567 };
568
569 uint32_t read()
570 {
571 return eeprom.read();
572 }
573
574 void write(uint32_t u32Wires)
575 {
576 eeprom.write(u32Wires);
577 }
578
579 int load(PSSMHANDLE pSSM)
580 {
581 return eeprom.load(pSSM);
582 }
583
584 void save(PSSMHANDLE pSSM)
585 {
586 eeprom.save(pSSM);
587 }
588#endif /* IN_RING3 */
589};
590
591struct E1kRxDStatus
592{
593 /* Descriptor Status field */
594 unsigned fDD : 1;
595 unsigned fEOP : 1;
596 unsigned fIXSM : 1;
597 unsigned fVP : 1;
598 unsigned : 1;
599 unsigned fTCPCS : 1;
600 unsigned fIPCS : 1;
601 unsigned fPIF : 1;
602 /* Descriptor Errors field */
603 unsigned fCE : 1;
604 unsigned : 4;
605 unsigned fTCPE : 1;
606 unsigned fIPE : 1;
607 unsigned fRXE : 1;
608 /* Descriptor Special field */
609 unsigned u12VLAN : 12;
610 unsigned fCFI : 1;
611 unsigned u3PRI : 3;
612};
613typedef struct E1kRxDStatus E1KRXDST;
614
615struct E1kRxDesc_st
616{
617 uint64_t u64BufAddr; /**< Address of data buffer */
618 uint16_t u16Length; /**< Length of data in buffer */
619 uint16_t u16Checksum; /**< Packet checksum */
620 E1KRXDST status;
621};
622typedef struct E1kRxDesc_st E1KRXDESC;
623AssertCompileSize(E1KRXDESC, 16);
624
625#define E1K_DTYP_LEGACY -1
626#define E1K_DTYP_CONTEXT 0
627#define E1K_DTYP_DATA 1
628
629struct E1kTDLegacy
630{
631 uint64_t u64BufAddr; /**< Address of data buffer */
632 struct TDLCmd_st
633 {
634 unsigned u16Length : 16;
635 unsigned u8CSO : 8;
636 /* CMD field : 8 */
637 unsigned fEOP : 1;
638 unsigned fIFCS : 1;
639 unsigned fIC : 1;
640 unsigned fRS : 1;
641 unsigned fRSV : 1;
642 unsigned fDEXT : 1;
643 unsigned fVLE : 1;
644 unsigned fIDE : 1;
645 } cmd;
646 struct TDLDw3_st
647 {
648 /* STA field */
649 unsigned fDD : 1;
650 unsigned fEC : 1;
651 unsigned fLC : 1;
652 unsigned fTURSV : 1;
653 /* RSV field */
654 unsigned u4RSV : 4;
655 /* CSS field */
656 unsigned u8CSS : 8;
657 /* Special field*/
658 unsigned u12VLAN : 12;
659 unsigned fCFI : 1;
660 unsigned u3PRI : 3;
661 } dw3;
662};
663
664struct E1kTDContext
665{
666 struct CheckSum_st
667 {
668 unsigned u8CSS : 8;
669 unsigned u8CSO : 8;
670 unsigned u16CSE : 16;
671 } ip;
672 struct CheckSum_st tu;
673 struct TDCDw2_st
674 {
675 unsigned u20PAYLEN : 20;
676 unsigned u4DTYP : 4;
677 /* CMD field : 8 */
678 unsigned fTCP : 1;
679 unsigned fIP : 1;
680 unsigned fTSE : 1;
681 unsigned fRS : 1;
682 unsigned fRSV1 : 1;
683 unsigned fDEXT : 1;
684 unsigned fRSV2 : 1;
685 unsigned fIDE : 1;
686 } dw2;
687 struct TDCDw3_st
688 {
689 unsigned fDD : 1;
690 unsigned u7RSV : 7;
691 unsigned u8HDRLEN : 8;
692 unsigned u16MSS : 16;
693 } dw3;
694};
695typedef struct E1kTDContext E1KTXCTX;
696
697struct E1kTDData
698{
699 uint64_t u64BufAddr; /**< Address of data buffer */
700 struct TDDCmd_st
701 {
702 unsigned u20DTALEN : 20;
703 unsigned u4DTYP : 4;
704 /* DCMD field : 8 */
705 unsigned fEOP : 1;
706 unsigned fIFCS : 1;
707 unsigned fTSE : 1;
708 unsigned fRS : 1;
709 unsigned fRSV : 1;
710 unsigned fDEXT : 1;
711 unsigned fVLE : 1;
712 unsigned fIDE : 1;
713 } cmd;
714 struct TDDDw3_st
715 {
716 /* STA field */
717 unsigned fDD : 1;
718 unsigned fEC : 1;
719 unsigned fLC : 1;
720 unsigned fTURSV : 1;
721 /* RSV field */
722 unsigned u4RSV : 4;
723 /* POPTS field */
724 unsigned fIXSM : 1;
725 unsigned fTXSM : 1;
726 unsigned u6RSV : 6;
727 /* Special field*/
728 unsigned u12VLAN : 12;
729 unsigned fCFI : 1;
730 unsigned u3PRI : 3;
731 } dw3;
732};
733typedef struct E1kTDData E1KTXDAT;
734
735union E1kTxDesc
736{
737 struct E1kTDLegacy legacy;
738 struct E1kTDContext context;
739 struct E1kTDData data;
740};
741typedef union E1kTxDesc E1KTXDESC;
742AssertCompileSize(E1KTXDESC, 16);
743
744#define RA_CTL_AS 0x0003
745#define RA_CTL_AV 0x8000
746
747union E1kRecAddr
748{
749 uint32_t au32[32];
750 struct RAArray
751 {
752 uint8_t addr[6];
753 uint16_t ctl;
754 } array[16];
755};
756typedef struct E1kRecAddr::RAArray E1KRAELEM;
757typedef union E1kRecAddr E1KRA;
758AssertCompileSize(E1KRA, 8*16);
759
760#define E1K_IP_RF 0x8000 /* reserved fragment flag */
761#define E1K_IP_DF 0x4000 /* dont fragment flag */
762#define E1K_IP_MF 0x2000 /* more fragments flag */
763#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
764
765/** @todo use+extend RTNETIPV4 */
766struct E1kIpHeader
767{
768 /* type of service / version / header length */
769 uint16_t tos_ver_hl;
770 /* total length */
771 uint16_t total_len;
772 /* identification */
773 uint16_t ident;
774 /* fragment offset field */
775 uint16_t offset;
776 /* time to live / protocol*/
777 uint16_t ttl_proto;
778 /* checksum */
779 uint16_t chksum;
780 /* source IP address */
781 uint32_t src;
782 /* destination IP address */
783 uint32_t dest;
784};
785AssertCompileSize(struct E1kIpHeader, 20);
786
787#define E1K_TCP_FIN 0x01U
788#define E1K_TCP_SYN 0x02U
789#define E1K_TCP_RST 0x04U
790#define E1K_TCP_PSH 0x08U
791#define E1K_TCP_ACK 0x10U
792#define E1K_TCP_URG 0x20U
793#define E1K_TCP_ECE 0x40U
794#define E1K_TCP_CWR 0x80U
795
796#define E1K_TCP_FLAGS 0x3fU
797
798/** @todo use+extend RTNETTCP */
799struct E1kTcpHeader
800{
801 uint16_t src;
802 uint16_t dest;
803 uint32_t seqno;
804 uint32_t ackno;
805 uint16_t hdrlen_flags;
806 uint16_t wnd;
807 uint16_t chksum;
808 uint16_t urgp;
809};
810AssertCompileSize(struct E1kTcpHeader, 20);
811
812
813/** The current Saved state version. */
814#define E1K_SAVEDSTATE_VERSION 2
815/** Saved state version for VirtualBox 3.0 and earlier.
816 * This did not include the configuration part nor the E1kEEPROM. */
817#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
818
819/**
820 * Device state structure. Holds the current state of device.
821 */
822struct E1kState_st
823{
824 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
825 PDMIBASE IBase;
826 PDMINETWORKPORT INetworkPort;
827 PDMINETWORKCONFIG INetworkConfig;
828 PDMILEDPORTS ILeds; /**< LED interface */
829 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
830 R3PTRTYPE(PPDMINETWORKCONNECTOR) pDrv; /**< Connector of attached network driver. */
831 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
832
833 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
834 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
835 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
836 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
837 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
838 PTMTIMERR3 pTIDTimerR3; /**< Tranmsit Interrupt Delay Timer - R3. */
839 PTMTIMERR3 pTADTimerR3; /**< Tranmsit Absolute Delay Timer - R3. */
840 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
841
842 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
843 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
844 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
845 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
846 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
847 PTMTIMERR0 pTIDTimerR0; /**< Tranmsit Interrupt Delay Timer - R0. */
848 PTMTIMERR0 pTADTimerR0; /**< Tranmsit Absolute Delay Timer - R0. */
849 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
850
851 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
852 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
853 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
854 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
855 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
856 PTMTIMERRC pTIDTimerRC; /**< Tranmsit Interrupt Delay Timer - RC. */
857 PTMTIMERRC pTADTimerRC; /**< Tranmsit Absolute Delay Timer - RC. */
858 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
859
860 PTMTIMERR3 pLUTimer; /**< Link Up(/Restore) Timer. */
861 PPDMTHREAD pTxThread; /**< Transmit thread. */
862 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
863#ifndef E1K_GLOBAL_MUTEX
864 PDMCRITSECT csRx; /**< RX Critical section. */
865// PDMCRITSECT csTx; /**< TX Critical section. */
866#endif
867 /** Transmit thread blocker. */
868 RTSEMEVENT hTxSem;
869 /** Base address of memory-mapped registers. */
870 RTGCPHYS addrMMReg;
871 /** MAC address obtained from the configuration. */
872 RTMAC macConfigured;
873 /** Base port of I/O space region. */
874 RTIOPORT addrIOPort;
875 /** EMT: */
876 PCIDEVICE pciDevice;
877 /** EMT: Last time the interrupt was acknowledged. */
878 uint64_t u64AckedAt;
879 /** All: Used for eliminating spurious interrupts. */
880 bool fIntRaised;
881 /** EMT: */
882 bool fCableConnected;
883 /** EMT: */
884 bool fR0Enabled;
885 /** EMT: */
886 bool fGCEnabled;
887
888 /* All: Device register storage. */
889 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
890 /** TX/RX: Status LED. */
891 PDMLED led;
892 /** TX/RX: Number of packet being sent/received to show in debug log. */
893 uint32_t u32PktNo;
894
895 /** EMT: Offset of the register to be read via IO. */
896 uint32_t uSelectedReg;
897 /** EMT: Multicast Table Array. */
898 uint32_t auMTA[128];
899 /** EMT: Receive Address registers. */
900 E1KRA aRecAddr;
901 /** EMT: VLAN filter table array. */
902 uint32_t auVFTA[128];
903 /** EMT: Receive buffer size. */
904 uint16_t u16RxBSize;
905 /** EMT: Locked state -- no state alteration possible. */
906 bool fLocked;
907 /** EMT: */
908 bool fDelayInts;
909 /** All: */
910 bool fIntMaskUsed;
911
912 /** N/A: */
913 bool volatile fMaybeOutOfSpace;
914 /** EMT: Gets signalled when more RX descriptors become available. */
915 RTSEMEVENT hEventMoreRxDescAvail;
916
917 /** TX: Context used for TCP segmentation packets. */
918 E1KTXCTX contextTSE;
919 /** TX: Context used for ordinary packets. */
920 E1KTXCTX contextNormal;
921 /** TX: Transmit packet buffer. */
922 uint8_t aTxPacket[E1K_MAX_TX_PKT_SIZE];
923 /** TX: Number of bytes assembled in TX packet buffer. */
924 uint16_t u16TxPktLen;
925 /** TX: IP checksum has to be inserted if true. */
926 bool fIPcsum;
927 /** TX: TCP/UDP checksum has to be inserted if true. */
928 bool fTCPcsum;
929 /** TX: Number of payload bytes remaining in TSE context. */
930 uint32_t u32PayRemain;
931 /** TX: Number of header bytes remaining in TSE context. */
932 uint16_t u16HdrRemain;
933 /** TX: Flags from template header. */
934 uint16_t u16SavedFlags;
935 /** TX: Partial checksum from template header. */
936 uint32_t u32SavedCsum;
937 /** ?: Emulated controller type. */
938 E1KCHIP eChip;
939 uint32_t alignmentFix;
940
941 /** EMT: EEPROM emulation */
942 E1kEEPROM eeprom;
943 /** EMT: Physical interface emulation. */
944 PHY phy;
945
946 /** Alignment padding. */
947 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
948
949 STAMCOUNTER StatReceiveBytes;
950 STAMCOUNTER StatTransmitBytes;
951#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
952 STAMPROFILEADV StatMMIOReadGC;
953 STAMPROFILEADV StatMMIOReadHC;
954 STAMPROFILEADV StatMMIOWriteGC;
955 STAMPROFILEADV StatMMIOWriteHC;
956 STAMPROFILEADV StatEEPROMRead;
957 STAMPROFILEADV StatEEPROMWrite;
958 STAMPROFILEADV StatIOReadGC;
959 STAMPROFILEADV StatIOReadHC;
960 STAMPROFILEADV StatIOWriteGC;
961 STAMPROFILEADV StatIOWriteHC;
962 STAMPROFILEADV StatLateIntTimer;
963 STAMCOUNTER StatLateInts;
964 STAMCOUNTER StatIntsRaised;
965 STAMCOUNTER StatIntsPrevented;
966 STAMPROFILEADV StatReceive;
967 STAMPROFILEADV StatReceiveFilter;
968 STAMPROFILEADV StatReceiveStore;
969 STAMPROFILEADV StatTransmit;
970 STAMPROFILEADV StatTransmitSend;
971 STAMPROFILE StatRxOverflow;
972 STAMCOUNTER StatRxOverflowWakeup;
973 STAMCOUNTER StatTxDescLegacy;
974 STAMCOUNTER StatTxDescData;
975 STAMCOUNTER StatTxDescTSEData;
976 STAMCOUNTER StatPHYAccesses;
977
978#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
979
980#ifdef E1K_INT_STATS
981 /* Internal stats */
982 uint32_t uStatInt;
983 uint32_t uStatIntTry;
984 int32_t uStatIntLower;
985 uint32_t uStatIntDly;
986 int32_t iStatIntLost;
987 int32_t iStatIntLostOne;
988 uint32_t uStatDisDly;
989 uint32_t uStatIntSkip;
990 uint32_t uStatIntLate;
991 uint32_t uStatIntMasked;
992 uint32_t uStatIntEarly;
993 uint32_t uStatIntRx;
994 uint32_t uStatIntTx;
995 uint32_t uStatIntICS;
996 uint32_t uStatIntRDTR;
997 uint32_t uStatIntRXDMT0;
998 uint32_t uStatIntTXQE;
999 uint32_t uStatTxNoRS;
1000 uint32_t uStatTxIDE;
1001 uint32_t uStatTAD;
1002 uint32_t uStatTID;
1003 uint32_t uStatRAD;
1004 uint32_t uStatRID;
1005 uint32_t uStatRxFrm;
1006 uint32_t uStatTxFrm;
1007 uint32_t uStatDescCtx;
1008 uint32_t uStatDescDat;
1009 uint32_t uStatDescLeg;
1010#endif /* E1K_INT_STATS */
1011};
1012typedef struct E1kState_st E1KSTATE;
1013
1014#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1015
1016/* Forward declarations ******************************************************/
1017RT_C_DECLS_BEGIN
1018PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1019PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1020PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
1021PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
1022RT_C_DECLS_END
1023
1024static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1025static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1026static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1027static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1028static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1029#if 0 /* unused */
1030static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1031#endif
1032static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1033static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1034static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1035static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1036static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1037static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1038static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1039static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1040static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1041static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1042static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1043static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1044static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1045static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1046static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1047static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1048static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1049static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1050static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1051static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1052
1053/**
1054 * Register map table.
1055 *
1056 * Override fn_read and fn_write to get register-specific behavior.
1057 */
1058const static struct E1kRegMap_st
1059{
1060 /** Register offset in the register space. */
1061 uint32_t offset;
1062 /** Size in bytes. Registers of size > 4 are in fact tables. */
1063 uint32_t size;
1064 /** Readable bits. */
1065 uint32_t readable;
1066 /** Writable bits. */
1067 uint32_t writable;
1068 /** Read callback. */
1069 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1070 /** Write callback. */
1071 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1072 /** Abbreviated name. */
1073 const char *abbrev;
1074 /** Full name. */
1075 const char *name;
1076} s_e1kRegMap[E1K_NUM_OF_REGS] =
1077{
1078 /* offset size read mask write mask read callback write callback abbrev full name */
1079 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1080 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1081 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1082 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1083 { 0x00014, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "EERD" , "EEPROM Read" },
1084 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1085 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1086 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1087 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1088 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1089 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1090 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1091 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1092 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1093 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1094 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1095 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1096 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1097 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1098 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1099 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1100 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1101 { 0x00410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TIPG" , "Transmit IPG" },
1102 { 0x00458, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "AIFS" , "Adaptive IFS Throttle - AIT" },
1103 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1104 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1105 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1106 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1107 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1108 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1109 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1110 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1111 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1112 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1113 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1114 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1115 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1116 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1117 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1118 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1119 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1120 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1121 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1122 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1123 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1124 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1125 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1126 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1127 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1128 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1129 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1130 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1131 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1132 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1133 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1134 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1135 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSPMT" , "TCP Segmentation Pad and Threshold" },
1136 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1137 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1138 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1139 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1140 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1141 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1142 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1143 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1144 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1145 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1146 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1147 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1148 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1149 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1150 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1151 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1152 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1153 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1154 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1155 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1156 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1157 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1158 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1159 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1160 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1161 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1162 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1163 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1164 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1165 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1166 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1167 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1168 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1169 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1170 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1171 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1172 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1173 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1174 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1175 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1176 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1177 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1178 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1179 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1180 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1181 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1182 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1183 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1184 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1185 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1186 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1187 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1188 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1189 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1190 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1191 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1192 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1193 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1194 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1195 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1196 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1197 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1198 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1199 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1200 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1201 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1202 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1203 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1204 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1205 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1206 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1207 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1208 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1209 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1210 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1211 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1212 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1213 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1214};
1215
1216#ifdef DEBUG
1217/**
1218 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1219 *
1220 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1221 *
1222 * @returns The buffer.
1223 *
1224 * @param u32 The word to convert into string.
1225 * @param mask Selects which bytes to convert.
1226 * @param buf Where to put the result.
1227 */
1228static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1229{
1230 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1231 {
1232 if (mask & 0xF)
1233 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1234 else
1235 *ptr = '.';
1236 }
1237 buf[8] = 0;
1238 return buf;
1239}
1240
1241/**
1242 * Returns timer name for debug purposes.
1243 *
1244 * @returns The timer name.
1245 *
1246 * @param pState The device state structure.
1247 * @param pTimer The timer to get the name for.
1248 */
1249DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1250{
1251 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1252 return "TID";
1253 if (pTimer == pState->CTX_SUFF(pTADTimer))
1254 return "TAD";
1255 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1256 return "RID";
1257 if (pTimer == pState->CTX_SUFF(pRADTimer))
1258 return "RAD";
1259 if (pTimer == pState->CTX_SUFF(pIntTimer))
1260 return "Int";
1261 return "unknown";
1262}
1263#endif /* DEBUG */
1264
1265/**
1266 * Arm a timer.
1267 *
1268 * @param pState Pointer to the device state structure.
1269 * @param pTimer Pointer to the timer.
1270 * @param uExpireIn Expiration interval in microseconds.
1271 */
1272DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1273{
1274 if (pState->fLocked)
1275 return;
1276
1277 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1278 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1279 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1280 TMTimerGet(pTimer));
1281}
1282
1283/**
1284 * Cancel a timer.
1285 *
1286 * @param pState Pointer to the device state structure.
1287 * @param pTimer Pointer to the timer.
1288 */
1289DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1290{
1291 E1kLog2(("%s Stopping %s timer...\n",
1292 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1293 int rc = TMTimerStop(pTimer);
1294 if (RT_FAILURE(rc))
1295 {
1296 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1297 INSTANCE(pState), rc));
1298 }
1299}
1300
1301#ifdef E1K_GLOBAL_MUTEX
1302DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1303{
1304 return VINF_SUCCESS;
1305}
1306
1307DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1308{
1309}
1310
1311#define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1312#define e1kCsRxLeave(ps)
1313
1314#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1315#define e1kCsTxLeave(ps)
1316
1317
1318DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1319{
1320 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1321 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1322 {
1323 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1324 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1325 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1326 "%s Failed to enter critical section, rc=%Rrc\n",
1327 INSTANCE(pState), rc);
1328 }
1329 else
1330 {
1331 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1332 }
1333 return rc;
1334}
1335
1336DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1337{
1338 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1339 PDMCritSectLeave(&pState->cs);
1340}
1341
1342#else /* !E1K_GLOBAL_MUTEX */
1343#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1344#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1345
1346#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1347#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1348
1349#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1350#define e1kCsTxLeave(ps)
1351//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1352//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1353
1354#if 0
1355DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1356{
1357 int rc = PDMCritSectEnter(pCs, iBusyRc);
1358 if (RT_FAILURE(rc))
1359 {
1360 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1361 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1362 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1363 "%s Failed to enter critical section, rc=%Rrc\n",
1364 INSTANCE(pState), rc);
1365 }
1366 else
1367 {
1368 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1369 }
1370 return RT_SUCCESS(rc);
1371}
1372
1373DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1374{
1375 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1376 PDMCritSectLeave(&pState->cs);
1377}
1378#endif
1379DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1380{
1381 return VINF_SUCCESS;
1382}
1383
1384DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1385{
1386}
1387#endif /* !E1K_GLOBAL_MUTEX */
1388
1389#ifdef IN_RING3
1390/**
1391 * Wakeup the RX thread.
1392 */
1393static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1394{
1395 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1396 if ( pState->fMaybeOutOfSpace
1397 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1398 {
1399 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1400 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1401 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1402 }
1403}
1404
1405/**
1406 * Compute Internet checksum.
1407 *
1408 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1409 *
1410 * @param pState The device state structure.
1411 * @param cpPacket The packet.
1412 * @param cb The size of the packet.
1413 * @param cszText A string denoting direction of packet transfer.
1414 *
1415 * @return The 1's complement of the 1's complement sum.
1416 *
1417 * @thread E1000_TX
1418 */
1419static DECLCALLBACK(uint16_t) e1kCSum16(const void *pvBuf, size_t cb)
1420{
1421 uint32_t csum = 0;
1422 uint16_t *pu16 = (uint16_t *)pvBuf;
1423
1424 while (cb > 1)
1425 {
1426 csum += *pu16++;
1427 cb -= 2;
1428 }
1429 if (cb)
1430 csum += *(uint8_t*)pu16;
1431 while (csum >> 16)
1432 csum = (csum >> 16) + (csum & 0xFFFF);
1433 return ~csum;
1434}
1435
1436/**
1437 * Dump a packet to debug log.
1438 *
1439 * @param pState The device state structure.
1440 * @param cpPacket The packet.
1441 * @param cb The size of the packet.
1442 * @param cszText A string denoting direction of packet transfer.
1443 * @thread E1000_TX
1444 */
1445DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1446{
1447#ifdef DEBUG
1448 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1449 {
1450 E1kLog(("%s --- %s packet #%d: ---\n",
1451 INSTANCE(pState), cszText, ++pState->u32PktNo));
1452 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1453 e1kCsLeave(pState);
1454 }
1455#else
1456 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1457 {
1458 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1459 e1kCsLeave(pState);
1460 }
1461#endif
1462}
1463
1464/**
1465 * Determine the type of transmit descriptor.
1466 *
1467 * @returns Descriptor type. See E1K_DTYPE_XXX defines.
1468 *
1469 * @param pDesc Pointer to descriptor union.
1470 * @thread E1000_TX
1471 */
1472DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1473{
1474 if (pDesc->legacy.cmd.fDEXT)
1475 return pDesc->context.dw2.u4DTYP;
1476 return E1K_DTYP_LEGACY;
1477}
1478
1479/**
1480 * Dump receive descriptor to debug log.
1481 *
1482 * @param pState The device state structure.
1483 * @param pDesc Pointer to the descriptor.
1484 * @thread E1000_RX
1485 */
1486static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1487{
1488 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1489 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1490 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1491 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1492 pDesc->status.fPIF ? "PIF" : "pif",
1493 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1494 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1495 pDesc->status.fVP ? "VP" : "vp",
1496 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1497 pDesc->status.fEOP ? "EOP" : "eop",
1498 pDesc->status.fDD ? "DD" : "dd",
1499 pDesc->status.fRXE ? "RXE" : "rxe",
1500 pDesc->status.fIPE ? "IPE" : "ipe",
1501 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1502 pDesc->status.fCE ? "CE" : "ce",
1503 pDesc->status.fCFI ? "CFI" :"cfi",
1504 pDesc->status.u12VLAN,
1505 pDesc->status.u3PRI));
1506}
1507
1508/**
1509 * Dump transmit descriptor to debug log.
1510 *
1511 * @param pState The device state structure.
1512 * @param pDesc Pointer to descriptor union.
1513 * @param cszDir A string denoting direction of descriptor transfer
1514 * @thread E1000_TX
1515 */
1516static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1517{
1518 switch (e1kGetDescType(pDesc))
1519 {
1520 case E1K_DTYP_CONTEXT:
1521 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1522 INSTANCE(pState), cszDir, cszDir));
1523 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1524 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1525 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1526 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1527 pDesc->context.dw2.fIDE ? " IDE":"",
1528 pDesc->context.dw2.fRS ? " RS" :"",
1529 pDesc->context.dw2.fTSE ? " TSE":"",
1530 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1531 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1532 pDesc->context.dw2.u20PAYLEN,
1533 pDesc->context.dw3.u8HDRLEN,
1534 pDesc->context.dw3.u16MSS,
1535 pDesc->context.dw3.fDD?"DD":""));
1536 break;
1537 case E1K_DTYP_DATA:
1538 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1539 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1540 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1541 pDesc->data.u64BufAddr,
1542 pDesc->data.cmd.u20DTALEN));
1543 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1544 pDesc->data.cmd.fIDE ? " IDE" :"",
1545 pDesc->data.cmd.fVLE ? " VLE" :"",
1546 pDesc->data.cmd.fRS ? " RS" :"",
1547 pDesc->data.cmd.fTSE ? " TSE" :"",
1548 pDesc->data.cmd.fIFCS? " IFCS":"",
1549 pDesc->data.cmd.fEOP ? " EOP" :"",
1550 pDesc->data.dw3.fDD ? " DD" :"",
1551 pDesc->data.dw3.fEC ? " EC" :"",
1552 pDesc->data.dw3.fLC ? " LC" :"",
1553 pDesc->data.dw3.fTXSM? " TXSM":"",
1554 pDesc->data.dw3.fIXSM? " IXSM":"",
1555 pDesc->data.dw3.fCFI ? " CFI" :"",
1556 pDesc->data.dw3.u12VLAN,
1557 pDesc->data.dw3.u3PRI));
1558 break;
1559 case E1K_DTYP_LEGACY:
1560 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1561 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1562 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1563 pDesc->data.u64BufAddr,
1564 pDesc->legacy.cmd.u16Length));
1565 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1566 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1567 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1568 pDesc->legacy.cmd.fRS ? " RS" :"",
1569 pDesc->legacy.cmd.fIC ? " IC" :"",
1570 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1571 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1572 pDesc->legacy.dw3.fDD ? " DD" :"",
1573 pDesc->legacy.dw3.fEC ? " EC" :"",
1574 pDesc->legacy.dw3.fLC ? " LC" :"",
1575 pDesc->legacy.cmd.u8CSO,
1576 pDesc->legacy.dw3.u8CSS,
1577 pDesc->legacy.dw3.fCFI ? " CFI" :"",
1578 pDesc->legacy.dw3.u12VLAN,
1579 pDesc->legacy.dw3.u3PRI));
1580 break;
1581 default:
1582 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1583 INSTANCE(pState), cszDir, cszDir));
1584 break;
1585 }
1586}
1587#endif /* IN_RING3 */
1588
1589/**
1590 * Hardware reset. Revert all registers to initial values.
1591 *
1592 * @param pState The device state structure.
1593 */
1594PDMBOTHCBDECL(void) e1kHardReset(E1KSTATE *pState)
1595{
1596 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1597 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1598 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1599 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1600 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1601 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1602 Assert(GET_BITS(RCTL, BSIZE) == 0);
1603 pState->u16RxBSize = 2048;
1604}
1605
1606/**
1607 * Raise interrupt if not masked.
1608 *
1609 * @param pState The device state structure.
1610 */
1611PDMBOTHCBDECL(int) e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1612{
1613 int rc = e1kCsEnter(pState, rcBusy);
1614 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1615 return rc;
1616
1617 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1618 ICR |= u32IntCause;
1619 if (ICR & IMS)
1620 {
1621#if 0
1622 if (pState->fDelayInts)
1623 {
1624 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1625 pState->iStatIntLostOne = 1;
1626 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1627 INSTANCE(pState), ICR));
1628#define E1K_LOST_IRQ_THRSLD 20
1629//#define E1K_LOST_IRQ_THRSLD 200000000
1630 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1631 {
1632 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1633 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1634 pState->fIntMaskUsed = false;
1635 pState->uStatDisDly++;
1636 }
1637 }
1638 else
1639#endif
1640 if (pState->fIntRaised)
1641 {
1642 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1643 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1644 INSTANCE(pState), ICR & IMS));
1645 }
1646 else
1647 {
1648#ifdef E1K_ITR_ENABLED
1649 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1650 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1651 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1652 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1653 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1654 {
1655 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1656 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1657 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1658 }
1659 else
1660#endif
1661 {
1662
1663 /* Since we are delivering the interrupt now
1664 * there is no need to do it later -- stop the timer.
1665 */
1666 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1667 E1K_INC_ISTAT_CNT(pState->uStatInt);
1668 STAM_COUNTER_INC(&pState->StatIntsRaised);
1669 /* Got at least one unmasked interrupt cause */
1670 pState->fIntRaised = true;
1671 /* Raise(1) INTA(0) */
1672 //PDMDevHlpPCISetIrqNoWait(pState->CTXSUFF(pInst), 0, 1);
1673 //e1kMutexRelease(pState);
1674 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1675 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1676 //e1kMutexAcquire(pState, RT_SRC_POS);
1677 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1678 INSTANCE(pState), ICR & IMS));
1679 }
1680 }
1681 }
1682 else
1683 {
1684 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1685 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1686 INSTANCE(pState), ICR, IMS));
1687 }
1688 e1kCsLeave(pState);
1689 return VINF_SUCCESS;
1690}
1691
1692#ifdef IN_RING3
1693/**
1694 * Compute the physical address of the descriptor.
1695 *
1696 * @returns the physical address of the descriptor.
1697 *
1698 * @param baseHigh High-order 32 bits of descriptor table address.
1699 * @param baseLow Low-order 32 bits of descriptor table address.
1700 * @param idxDesc The descriptor index in the table.
1701 */
1702DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1703{
1704 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1705 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1706}
1707
1708/**
1709 * Advance the head pointer of the receive descriptor queue.
1710 *
1711 * @remarks RDH always points to the next available RX descriptor.
1712 *
1713 * @param pState The device state structure.
1714 */
1715DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1716{
1717 //e1kCsEnter(pState, RT_SRC_POS);
1718 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1719 RDH = 0;
1720 /*
1721 * Compute current recieve queue length and fire RXDMT0 interrupt
1722 * if we are low on recieve buffers
1723 */
1724 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1725 /*
1726 * The minimum threshold is controlled by RDMTS bits of RCTL:
1727 * 00 = 1/2 of RDLEN
1728 * 01 = 1/4 of RDLEN
1729 * 10 = 1/8 of RDLEN
1730 * 11 = reserved
1731 */
1732 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1733 if (uRQueueLen <= uMinRQThreshold)
1734 {
1735 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1736 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1737 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1738 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1739 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1740 }
1741 //e1kCsLeave(pState);
1742}
1743
1744/**
1745 * Store a fragment of received packet that fits into the next available RX
1746 * buffer.
1747 *
1748 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1749 *
1750 * @param pState The device state structure.
1751 * @param pDesc The next available RX descriptor.
1752 * @param pvBuf The fragment.
1753 * @param cb The size of the fragment.
1754 */
1755static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1756{
1757 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1758 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1759 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1760 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1761 /* Write back the descriptor */
1762 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1763 e1kPrintRDesc(pState, pDesc);
1764 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1765 /* Advance head */
1766 e1kAdvanceRDH(pState);
1767 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1768 if (pDesc->status.fEOP)
1769 {
1770 /* Complete packet has been stored -- it is time to let the guest know. */
1771#ifdef E1K_USE_RX_TIMERS
1772 if (RDTR)
1773 {
1774 /* Arm the timer to fire in RDTR usec (discard .024) */
1775 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1776 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1777 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1778 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1779 }
1780 else
1781 {
1782#endif
1783 /* 0 delay means immediate interrupt */
1784 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1785 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1786#ifdef E1K_USE_RX_TIMERS
1787 }
1788#endif
1789 }
1790 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1791}
1792
1793/**
1794 * Returns true if it is a broadcast packet.
1795 *
1796 * @returns true if destination address indicates broadcast.
1797 * @param pvBuf The ethernet packet.
1798 */
1799DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1800{
1801 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1802 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1803}
1804
1805/**
1806 * Returns true if it is a multicast packet.
1807 *
1808 * @remarks returns true for broadcast packets as well.
1809 * @returns true if destination address indicates multicast.
1810 * @param pvBuf The ethernet packet.
1811 */
1812DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1813{
1814 return (*(char*)pvBuf) & 1;
1815}
1816
1817/**
1818 * Set IXSM, IPCS and TCPCS flags according to the packet type.
1819 *
1820 * @remarks We emulate checksum offloading for major packets types only.
1821 *
1822 * @returns VBox status code.
1823 * @param pState The device state structure.
1824 * @param pFrame The available data.
1825 * @param cb Number of bytes available in the buffer.
1826 * @param status Bit fields containing status info.
1827 */
1828static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
1829{
1830 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
1831 PRTNETIPV4 pIpHdr4;
1832
1833 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", INSTANCE(pState), uEtherType));
1834
1835 //pStatus->fIPE = false;
1836 //pStatus->fTCPE = false;
1837 switch (uEtherType)
1838 {
1839 case 0x800: /* IPv4 */
1840 pStatus->fIXSM = false;
1841 pStatus->fIPCS = true;
1842 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
1843 /* TCP/UDP checksum offloading works with TCP and UDP only */
1844 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
1845 break;
1846 case 0x86DD: /* IPv6 */
1847 pStatus->fIXSM = false;
1848 pStatus->fIPCS = false;
1849 pStatus->fTCPCS = true;
1850 break;
1851 default: /* ARP, VLAN, etc. */
1852 pStatus->fIXSM = true;
1853 break;
1854 }
1855
1856 return VINF_SUCCESS;
1857}
1858
1859/**
1860 * Pad and store received packet.
1861 *
1862 * @remarks Make sure that the packet appears to upper layer as one coming
1863 * from real Ethernet: pad it and insert FCS.
1864 *
1865 * @returns VBox status code.
1866 * @param pState The device state structure.
1867 * @param pvBuf The available data.
1868 * @param cb Number of bytes available in the buffer.
1869 * @param status Bit fields containing status info.
1870 */
1871static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
1872{
1873 E1KRXDESC desc;
1874 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
1875 uint8_t *ptr = rxPacket;
1876
1877#ifndef E1K_GLOBAL_MUTEX
1878 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1879 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1880 return rc;
1881#endif
1882
1883#ifdef E1K_LEDS_WITH_MUTEX
1884 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1885 {
1886#endif /* E1K_LEDS_WITH_MUTEX */
1887 pState->led.Asserted.s.fReading = 1;
1888 pState->led.Actual.s.fReading = 1;
1889#ifdef E1K_LEDS_WITH_MUTEX
1890 e1kCsLeave(pState);
1891 }
1892#endif /* E1K_LEDS_WITH_MUTEX */
1893
1894 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
1895 memcpy(rxPacket, pvBuf, cb);
1896 /* Pad short packets */
1897 if (cb < 60)
1898 {
1899 memset(rxPacket + cb, 0, 60 - cb);
1900 cb = 60;
1901 }
1902 if (!(RCTL & RCTL_SECRC))
1903 {
1904 /* Add FCS if CRC stripping is not enabled */
1905 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
1906 cb += sizeof(uint32_t);
1907 }
1908 /* Compute checksum of complete packet */
1909 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
1910 e1kRxChecksumOffload(pState, rxPacket, cb, &status);
1911
1912 /* Update stats */
1913 E1K_INC_CNT32(GPRC);
1914 if (e1kIsBroadcast(pvBuf))
1915 E1K_INC_CNT32(BPRC);
1916 else if (e1kIsMulticast(pvBuf))
1917 E1K_INC_CNT32(MPRC);
1918 /* Update octet receive counter */
1919 E1K_ADD_CNT64(GORCL, GORCH, cb);
1920 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
1921 if (cb == 64)
1922 E1K_INC_CNT32(PRC64);
1923 else if (cb < 128)
1924 E1K_INC_CNT32(PRC127);
1925 else if (cb < 256)
1926 E1K_INC_CNT32(PRC255);
1927 else if (cb < 512)
1928 E1K_INC_CNT32(PRC511);
1929 else if (cb < 1024)
1930 E1K_INC_CNT32(PRC1023);
1931 else
1932 E1K_INC_CNT32(PRC1522);
1933
1934 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
1935
1936 if (RDH == RDT)
1937 {
1938 E1kLog(("%s Out of recieve buffers, dropping the packet",
1939 INSTANCE(pState)));
1940 }
1941 /* Store the packet to receive buffers */
1942 while (RDH != RDT)
1943 {
1944 /* Load the desciptor pointed by head */
1945 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
1946 &desc, sizeof(desc));
1947 if (desc.u64BufAddr)
1948 {
1949 /* Update descriptor */
1950 desc.status = status;
1951 desc.u16Checksum = checksum;
1952 desc.status.fDD = true;
1953
1954 /*
1955 * We need to leave Rx critical section here or we risk deadlocking
1956 * with EMT in e1kRegWriteRDT when the write is to an unallocated
1957 * page or has an access handler associated with it.
1958 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
1959 * modifies RDT only.
1960 */
1961 if(cb > pState->u16RxBSize)
1962 {
1963 desc.status.fEOP = false;
1964 e1kCsRxLeave(pState);
1965 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
1966 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1967 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1968 return rc;
1969 ptr += pState->u16RxBSize;
1970 cb -= pState->u16RxBSize;
1971 }
1972 else
1973 {
1974 desc.status.fEOP = true;
1975 e1kCsRxLeave(pState);
1976 e1kStoreRxFragment(pState, &desc, ptr, cb);
1977#ifdef E1K_LEDS_WITH_MUTEX
1978 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
1979 {
1980#endif /* E1K_LEDS_WITH_MUTEX */
1981 pState->led.Actual.s.fReading = 0;
1982#ifdef E1K_LEDS_WITH_MUTEX
1983 e1kCsLeave(pState);
1984 }
1985#endif /* E1K_LEDS_WITH_MUTEX */
1986 return VINF_SUCCESS;
1987 }
1988 /* Note: RDH is advanced by e1kStoreRxFragment! */
1989 }
1990 else
1991 {
1992 desc.status.fDD = true;
1993 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
1994 e1kDescAddr(RDBAH, RDBAL, RDH),
1995 &desc, sizeof(desc));
1996 e1kAdvanceRDH(pState);
1997 }
1998 }
1999#ifdef E1K_LEDS_WITH_MUTEX
2000 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2001 {
2002#endif /* E1K_LEDS_WITH_MUTEX */
2003 pState->led.Actual.s.fReading = 0;
2004#ifdef E1K_LEDS_WITH_MUTEX
2005 e1kCsLeave(pState);
2006 }
2007#endif /* E1K_LEDS_WITH_MUTEX */
2008
2009 e1kCsRxLeave(pState);
2010
2011 return VINF_SUCCESS;
2012}
2013
2014#endif /* IN_RING3 */
2015
2016#if 0 /* unused */
2017/**
2018 * Read handler for Device Status register.
2019 *
2020 * Get the link status from PHY.
2021 *
2022 * @returns VBox status code.
2023 *
2024 * @param pState The device state structure.
2025 * @param offset Register offset in memory-mapped frame.
2026 * @param index Register index in register array.
2027 * @param mask Used to implement partial reads (8 and 16-bit).
2028 */
2029static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2030{
2031 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2032 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2033 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2034 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2035 {
2036 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2037 if (Phy::readMDIO(&pState->phy))
2038 *pu32Value = CTRL | CTRL_MDIO;
2039 else
2040 *pu32Value = CTRL & ~CTRL_MDIO;
2041 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2042 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
2043 }
2044 else
2045 {
2046 /* MDIO pin is used for output, ignore it */
2047 *pu32Value = CTRL;
2048 }
2049 return VINF_SUCCESS;
2050}
2051#endif /* unused */
2052
2053/**
2054 * Write handler for Device Control register.
2055 *
2056 * Handles reset.
2057 *
2058 * @param pState The device state structure.
2059 * @param offset Register offset in memory-mapped frame.
2060 * @param index Register index in register array.
2061 * @param value The value to store.
2062 * @param mask Used to implement partial writes (8 and 16-bit).
2063 * @thread EMT
2064 */
2065static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2066{
2067 int rc = VINF_SUCCESS;
2068
2069 if (value & CTRL_RESET)
2070 { /* RST */
2071 e1kHardReset(pState);
2072 }
2073 else
2074 {
2075 if (value & CTRL_SLU)
2076 {
2077 /* The driver indicates that we should bring up the link */
2078 STATUS |= STATUS_LU;
2079 }
2080 if (value & CTRL_VME)
2081 {
2082 E1kLog(("%s VLAN Mode is not supported yet!\n", INSTANCE(pState)));
2083 }
2084 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2085 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2086 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2087 if (value & CTRL_MDC)
2088 {
2089 if (value & CTRL_MDIO_DIR)
2090 {
2091 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2092 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2093 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2094 }
2095 else
2096 {
2097 if (Phy::readMDIO(&pState->phy))
2098 value |= CTRL_MDIO;
2099 else
2100 value &= ~CTRL_MDIO;
2101 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2102 INSTANCE(pState), !!(value & CTRL_MDIO)));
2103 }
2104 }
2105 rc = e1kRegWriteDefault(pState, offset, index, value);
2106 }
2107
2108 return rc;
2109}
2110
2111/**
2112 * Write handler for EEPROM/Flash Control/Data register.
2113 *
2114 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2115 *
2116 * @param pState The device state structure.
2117 * @param offset Register offset in memory-mapped frame.
2118 * @param index Register index in register array.
2119 * @param value The value to store.
2120 * @param mask Used to implement partial writes (8 and 16-bit).
2121 * @thread EMT
2122 */
2123static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2124{
2125#ifdef IN_RING3
2126 /* So far we are conserned with lower byte only */
2127 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2128 {
2129 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2130 /* Note: 82543GC does not need to request EEPROM access */
2131 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2132 pState->eeprom.write(value & EECD_EE_WIRES);
2133 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2134 }
2135 if (value & EECD_EE_REQ)
2136 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2137 else
2138 EECD &= ~EECD_EE_GNT;
2139 //e1kRegWriteDefault(pState, offset, index, value );
2140
2141 return VINF_SUCCESS;
2142#else /* !IN_RING3 */
2143 return VINF_IOM_HC_MMIO_WRITE;
2144#endif /* !IN_RING3 */
2145}
2146
2147/**
2148 * Read handler for EEPROM/Flash Control/Data register.
2149 *
2150 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2151 *
2152 * @returns VBox status code.
2153 *
2154 * @param pState The device state structure.
2155 * @param offset Register offset in memory-mapped frame.
2156 * @param index Register index in register array.
2157 * @param mask Used to implement partial reads (8 and 16-bit).
2158 * @thread EMT
2159 */
2160static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2161{
2162#ifdef IN_RING3
2163 uint32_t value;
2164 int rc = e1kRegReadDefault(pState, offset, index, &value);
2165 if (RT_SUCCESS(rc))
2166 {
2167 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2168 {
2169 /* Note: 82543GC does not need to request EEPROM access */
2170 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2171 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2172 value |= pState->eeprom.read();
2173 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2174 }
2175 *pu32Value = value;
2176 }
2177
2178 return rc;
2179#else /* !IN_RING3 */
2180 return VINF_IOM_HC_MMIO_READ;
2181#endif /* !IN_RING3 */
2182}
2183
2184/**
2185 * Write handler for MDI Control register.
2186 *
2187 * Handles PHY read/write requests; forwards requests to internal PHY device.
2188 *
2189 * @param pState The device state structure.
2190 * @param offset Register offset in memory-mapped frame.
2191 * @param index Register index in register array.
2192 * @param value The value to store.
2193 * @param mask Used to implement partial writes (8 and 16-bit).
2194 * @thread EMT
2195 */
2196static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2197{
2198 if (value & MDIC_INT_EN)
2199 {
2200 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2201 INSTANCE(pState)));
2202 }
2203 else if (value & MDIC_READY)
2204 {
2205 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2206 INSTANCE(pState)));
2207 }
2208 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2209 {
2210 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2211 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2212 }
2213 else
2214 {
2215 /* Store the value */
2216 e1kRegWriteDefault(pState, offset, index, value);
2217 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2218 /* Forward op to PHY */
2219 if (value & MDIC_OP_READ)
2220 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2221 else
2222 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2223 /* Let software know that we are done */
2224 MDIC |= MDIC_READY;
2225 }
2226
2227 return VINF_SUCCESS;
2228}
2229
2230/**
2231 * Write handler for Interrupt Cause Read register.
2232 *
2233 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2234 *
2235 * @param pState The device state structure.
2236 * @param offset Register offset in memory-mapped frame.
2237 * @param index Register index in register array.
2238 * @param value The value to store.
2239 * @param mask Used to implement partial writes (8 and 16-bit).
2240 * @thread EMT
2241 */
2242static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2243{
2244 ICR &= ~value;
2245
2246 return VINF_SUCCESS;
2247}
2248
2249/**
2250 * Read handler for Interrupt Cause Read register.
2251 *
2252 * Reading this register acknowledges all interrupts.
2253 *
2254 * @returns VBox status code.
2255 *
2256 * @param pState The device state structure.
2257 * @param offset Register offset in memory-mapped frame.
2258 * @param index Register index in register array.
2259 * @param mask Not used.
2260 * @thread EMT
2261 */
2262static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2263{
2264 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2265 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2266 return rc;
2267
2268 uint32_t value = 0;
2269 rc = e1kRegReadDefault(pState, offset, index, &value);
2270 if (RT_SUCCESS(rc))
2271 {
2272 if (value)
2273 {
2274 /*
2275 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2276 * with disabled interrupts.
2277 */
2278 //if (IMS)
2279 if (1)
2280 {
2281 /*
2282 * Interrupts were enabled -- we are supposedly at the very
2283 * beginning of interrupt handler
2284 */
2285 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2286 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2287 /* Clear all pending interrupts */
2288 ICR = 0;
2289 pState->fIntRaised = false;
2290 /* Lower(0) INTA(0) */
2291 //PDMDevHlpPCISetIrqNoWait(pState->CTX_SUFF(pDevIns), 0, 0);
2292 //e1kMutexRelease(pState);
2293 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2294 //e1kMutexAcquire(pState, RT_SRC_POS);
2295
2296 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2297 if (pState->fIntMaskUsed)
2298 pState->fDelayInts = true;
2299 }
2300 else
2301 {
2302 /*
2303 * Interrupts are disabled -- in windows guests ICR read is done
2304 * just before re-enabling interrupts
2305 */
2306 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2307 }
2308 }
2309 *pu32Value = value;
2310 }
2311 e1kCsLeave(pState);
2312
2313 return rc;
2314}
2315
2316/**
2317 * Write handler for Interrupt Cause Set register.
2318 *
2319 * Bits corresponding to 1s in 'value' will be set in ICR register.
2320 *
2321 * @param pState The device state structure.
2322 * @param offset Register offset in memory-mapped frame.
2323 * @param index Register index in register array.
2324 * @param value The value to store.
2325 * @param mask Used to implement partial writes (8 and 16-bit).
2326 * @thread EMT
2327 */
2328static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2329{
2330 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2331 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2332}
2333
2334/**
2335 * Write handler for Interrupt Mask Set register.
2336 *
2337 * Will trigger pending interrupts.
2338 *
2339 * @param pState The device state structure.
2340 * @param offset Register offset in memory-mapped frame.
2341 * @param index Register index in register array.
2342 * @param value The value to store.
2343 * @param mask Used to implement partial writes (8 and 16-bit).
2344 * @thread EMT
2345 */
2346static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2347{
2348 IMS |= value;
2349 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2350 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2351 /* Mask changes, we need to raise pending interrupts. */
2352 if ((ICR & IMS) && !pState->fLocked)
2353 {
2354 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2355 INSTANCE(pState), ICR));
2356 //TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2357 // TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2358 e1kRaiseInterrupt(pState, VERR_SEM_BUSY);
2359 }
2360
2361 return VINF_SUCCESS;
2362}
2363
2364/**
2365 * Write handler for Interrupt Mask Clear register.
2366 *
2367 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2368 *
2369 * @param pState The device state structure.
2370 * @param offset Register offset in memory-mapped frame.
2371 * @param index Register index in register array.
2372 * @param value The value to store.
2373 * @param mask Used to implement partial writes (8 and 16-bit).
2374 * @thread EMT
2375 */
2376static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2377{
2378 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2379 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2380 return rc;
2381 if (pState->fIntRaised)
2382 {
2383 /*
2384 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2385 * Windows to freeze since it may receive an interrupt while still in the very beginning
2386 * of interrupt handler.
2387 */
2388 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2389 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2390 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2391 /* Lower(0) INTA(0) */
2392 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2393 pState->fIntRaised = false;
2394 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2395 }
2396 IMS &= ~value;
2397 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2398 e1kCsLeave(pState);
2399
2400 return VINF_SUCCESS;
2401}
2402
2403/**
2404 * Write handler for Receive Control register.
2405 *
2406 * @param pState The device state structure.
2407 * @param offset Register offset in memory-mapped frame.
2408 * @param index Register index in register array.
2409 * @param value The value to store.
2410 * @param mask Used to implement partial writes (8 and 16-bit).
2411 * @thread EMT
2412 */
2413static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2414{
2415 e1kRegWriteDefault(pState, offset, index, value);
2416 pState->u16RxBSize = 2048 >> GET_BITS(RCTL, BSIZE);
2417 if (RCTL & RCTL_BSEX)
2418 pState->u16RxBSize *= 16;
2419 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d\n",
2420 INSTANCE(pState), pState->u16RxBSize));
2421
2422 return VINF_SUCCESS;
2423}
2424
2425/**
2426 * Write handler for Packet Buffer Allocation register.
2427 *
2428 * TXA = 64 - RXA.
2429 *
2430 * @param pState The device state structure.
2431 * @param offset Register offset in memory-mapped frame.
2432 * @param index Register index in register array.
2433 * @param value The value to store.
2434 * @param mask Used to implement partial writes (8 and 16-bit).
2435 * @thread EMT
2436 */
2437static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2438{
2439 e1kRegWriteDefault(pState, offset, index, value);
2440 PBA_st->txa = 64 - PBA_st->rxa;
2441
2442 return VINF_SUCCESS;
2443}
2444
2445/**
2446 * Write handler for Receive Descriptor Tail register.
2447 *
2448 * @remarks Write into RDT forces switch to HC and signal to
2449 * e1kWaitReceiveAvail().
2450 *
2451 * @returns VBox status code.
2452 *
2453 * @param pState The device state structure.
2454 * @param offset Register offset in memory-mapped frame.
2455 * @param index Register index in register array.
2456 * @param value The value to store.
2457 * @param mask Used to implement partial writes (8 and 16-bit).
2458 * @thread EMT
2459 */
2460static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2461{
2462#ifndef IN_RING3
2463 /* XXX */
2464// return VINF_IOM_HC_MMIO_WRITE;
2465#endif
2466 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2467 if (RT_LIKELY(rc == VINF_SUCCESS))
2468 {
2469 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2470 rc = e1kRegWriteDefault(pState, offset, index, value);
2471 e1kCsRxLeave(pState);
2472 if (RT_SUCCESS(rc))
2473 {
2474#ifdef IN_RING3
2475 /* Signal that we have more receive descriptors avalable. */
2476 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2477#else
2478 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2479 if (pItem)
2480 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2481#endif
2482 }
2483 }
2484 return rc;
2485}
2486
2487/**
2488 * Write handler for Receive Delay Timer register.
2489 *
2490 * @param pState The device state structure.
2491 * @param offset Register offset in memory-mapped frame.
2492 * @param index Register index in register array.
2493 * @param value The value to store.
2494 * @param mask Used to implement partial writes (8 and 16-bit).
2495 * @thread EMT
2496 */
2497static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2498{
2499 e1kRegWriteDefault(pState, offset, index, value);
2500 if (value & RDTR_FPD)
2501 {
2502 /* Flush requested, cancel both timers and raise interrupt */
2503#ifdef E1K_USE_RX_TIMERS
2504 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2505 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2506#endif
2507 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2508 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2509 }
2510
2511 return VINF_SUCCESS;
2512}
2513
2514DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2515{
2516 /**
2517 * Make sure TDT won't change during computation. EMT may modify TDT at
2518 * any moment.
2519 */
2520 uint32_t tdt = TDT;
2521 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2522}
2523
2524#ifdef IN_RING3
2525#ifdef E1K_USE_TX_TIMERS
2526/**
2527 * Transmit Interrupt Delay Timer handler.
2528 *
2529 * @remarks We only get here when the timer expires.
2530 *
2531 * @param pDevIns Pointer to device instance structure.
2532 * @param pTimer Pointer to the timer.
2533 * @param pvUser NULL.
2534 * @thread EMT
2535 */
2536static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2537{
2538 E1KSTATE *pState = (E1KSTATE *)pvUser;
2539
2540 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2541 {
2542 E1K_INC_ISTAT_CNT(pState->uStatTID);
2543 /* Cancel absolute delay timer as we have already got attention */
2544#ifndef E1K_NO_TAD
2545 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2546#endif /* E1K_NO_TAD */
2547 e1kRaiseInterrupt(pState, ICR_TXDW);
2548 e1kMutexRelease(pState);
2549 }
2550}
2551
2552/**
2553 * Transmit Absolute Delay Timer handler.
2554 *
2555 * @remarks We only get here when the timer expires.
2556 *
2557 * @param pDevIns Pointer to device instance structure.
2558 * @param pTimer Pointer to the timer.
2559 * @param pvUser NULL.
2560 * @thread EMT
2561 */
2562static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2563{
2564 E1KSTATE *pState = (E1KSTATE *)pvUser;
2565
2566 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2567 {
2568 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2569 /* Cancel interrupt delay timer as we have already got attention */
2570 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2571 e1kRaiseInterrupt(pState, ICR_TXDW);
2572 e1kMutexRelease(pState);
2573 }
2574}
2575#endif /* E1K_USE_TX_TIMERS */
2576
2577#ifdef E1K_USE_RX_TIMERS
2578/**
2579 * Receive Interrupt Delay Timer handler.
2580 *
2581 * @remarks We only get here when the timer expires.
2582 *
2583 * @param pDevIns Pointer to device instance structure.
2584 * @param pTimer Pointer to the timer.
2585 * @param pvUser NULL.
2586 * @thread EMT
2587 */
2588static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2589{
2590 E1KSTATE *pState = (E1KSTATE *)pvUser;
2591
2592 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2593 {
2594 E1K_INC_ISTAT_CNT(pState->uStatRID);
2595 /* Cancel absolute delay timer as we have already got attention */
2596 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2597 e1kRaiseInterrupt(pState, ICR_RXT0);
2598 e1kMutexRelease(pState);
2599 }
2600}
2601
2602/**
2603 * Receive Absolute Delay Timer handler.
2604 *
2605 * @remarks We only get here when the timer expires.
2606 *
2607 * @param pDevIns Pointer to device instance structure.
2608 * @param pTimer Pointer to the timer.
2609 * @param pvUser NULL.
2610 * @thread EMT
2611 */
2612static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2613{
2614 E1KSTATE *pState = (E1KSTATE *)pvUser;
2615
2616 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2617 {
2618 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2619 /* Cancel interrupt delay timer as we have already got attention */
2620 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2621 e1kRaiseInterrupt(pState, ICR_RXT0);
2622 e1kMutexRelease(pState);
2623 }
2624}
2625#endif /* E1K_USE_RX_TIMERS */
2626
2627/**
2628 * Late Interrupt Timer handler.
2629 *
2630 * @param pDevIns Pointer to device instance structure.
2631 * @param pTimer Pointer to the timer.
2632 * @param pvUser NULL.
2633 * @thread EMT
2634 */
2635static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2636{
2637 E1KSTATE *pState = (E1KSTATE *)pvUser;
2638
2639 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2640 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2641 {
2642 STAM_COUNTER_INC(&pState->StatLateInts);
2643 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2644#if 0
2645 if (pState->iStatIntLost > -100)
2646 pState->iStatIntLost--;
2647#endif
2648 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2649 e1kMutexRelease(pState);
2650 }
2651 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2652}
2653
2654/**
2655 * Link Up Timer handler.
2656 *
2657 * @param pDevIns Pointer to device instance structure.
2658 * @param pTimer Pointer to the timer.
2659 * @param pvUser NULL.
2660 * @thread EMT
2661 */
2662static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2663{
2664 E1KSTATE *pState = (E1KSTATE *)pvUser;
2665
2666 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2667 {
2668 STATUS |= STATUS_LU;
2669 Phy::setLinkStatus(&pState->phy, true);
2670 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2671 e1kMutexRelease(pState);
2672 }
2673}
2674
2675
2676
2677
2678/**
2679 * Load transmit descriptor from guest memory.
2680 *
2681 * @param pState The device state structure.
2682 * @param pDesc Pointer to descriptor union.
2683 * @param addr Physical address in guest context.
2684 * @thread E1000_TX
2685 */
2686DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2687{
2688 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2689}
2690
2691/**
2692 * Write back transmit descriptor to guest memory.
2693 *
2694 * @param pState The device state structure.
2695 * @param pDesc Pointer to descriptor union.
2696 * @param addr Physical address in guest context.
2697 * @thread E1000_TX
2698 */
2699DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
2700{
2701 /* Only the last half of the descriptor has to be written back. */
2702 e1kPrintTDesc(pState, pDesc, "^^^");
2703 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
2704}
2705
2706/**
2707 * Transmit complete frame.
2708 *
2709 * @remarks Since we do not have real Ethernet medium between us and NAT (or
2710 * another connector) there is no need for padding and FCS.
2711 *
2712 * @param pState The device state structure.
2713 * @param pFrame Pointer to the frame buffer.
2714 * @param u16FrameLen Length of the frame.
2715 * @thread E1000_TX
2716 */
2717static void e1kTransmitFrame(E1KSTATE* pState, uint8_t *pFrame, uint16_t u16FrameLen)
2718{
2719/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
2720 "%.*Rhxd\n"
2721 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
2722 INSTANCE(pState), u16FrameLen, pFrame, INSTANCE(pState)));*/
2723#ifdef E1K_LEDS_WITH_MUTEX
2724 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2725 {
2726#endif /* E1K_LEDS_WITH_MUTEX */
2727 pState->led.Asserted.s.fWriting = 1;
2728 pState->led.Actual.s.fWriting = 1;
2729#ifdef E1K_LEDS_WITH_MUTEX
2730 e1kCsLeave(pState);
2731 }
2732#endif /* E1K_LEDS_WITH_MUTEX */
2733 /* Update the stats */
2734 E1K_INC_CNT32(TPT);
2735 E1K_ADD_CNT64(TOTL, TOTH, u16FrameLen);
2736 E1K_INC_CNT32(GPTC);
2737 if (e1kIsBroadcast(pFrame))
2738 E1K_INC_CNT32(BPTC);
2739 else if (e1kIsMulticast(pFrame))
2740 E1K_INC_CNT32(MPTC);
2741 /* Update octet transmit counter */
2742 E1K_ADD_CNT64(GOTCL, GOTCH, u16FrameLen);
2743 if (pState->pDrv)
2744 {
2745 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, u16FrameLen);
2746 }
2747 if (u16FrameLen == 64)
2748 E1K_INC_CNT32(PTC64);
2749 else if (u16FrameLen < 128)
2750 E1K_INC_CNT32(PTC127);
2751 else if (u16FrameLen < 256)
2752 E1K_INC_CNT32(PTC255);
2753 else if (u16FrameLen < 512)
2754 E1K_INC_CNT32(PTC511);
2755 else if (u16FrameLen < 1024)
2756 E1K_INC_CNT32(PTC1023);
2757 else
2758 E1K_INC_CNT32(PTC1522);
2759
2760 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
2761
2762 e1kPacketDump(pState, pFrame, u16FrameLen, "--> Outgoing");
2763
2764
2765 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
2766 {
2767 E1KRXDST status;
2768 status.fPIF = true;
2769 /* Loopback mode */
2770 e1kHandleRxPacket(pState, pFrame, u16FrameLen, status);
2771 }
2772 else if (pState->pDrv)
2773 {
2774 /* Release critical section to avoid deadlock in CanReceive */
2775 //e1kCsLeave(pState);
2776 e1kMutexRelease(pState);
2777 STAM_PROFILE_ADV_START(&pState->StatTransmitSend, a);
2778 int rc = pState->pDrv->pfnSend(pState->pDrv, pFrame, u16FrameLen);
2779 STAM_PROFILE_ADV_STOP(&pState->StatTransmitSend, a);
2780 if (rc != VINF_SUCCESS)
2781 {
2782 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
2783 }
2784 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
2785 //e1kCsEnter(pState, RT_SRC_POS);
2786 }
2787#ifdef E1K_LEDS_WITH_MUTEX
2788 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2789 {
2790#endif /* E1K_LEDS_WITH_MUTEX */
2791 pState->led.Actual.s.fWriting = 0;
2792#ifdef E1K_LEDS_WITH_MUTEX
2793 e1kCsLeave(pState);
2794 }
2795#endif /* E1K_LEDS_WITH_MUTEX */
2796}
2797
2798/**
2799 * Compute and write checksum at the specified offset.
2800 *
2801 * @param pState The device state structure.
2802 * @param pPkt Pointer to the packet.
2803 * @param u16PktLen Total length of the packet.
2804 * @param cso Offset in packet to write checksum at.
2805 * @param css Offset in packet to start computing
2806 * checksum from.
2807 * @param cse Offset in packet to stop computing
2808 * checksum at.
2809 * @thread E1000_TX
2810 */
2811static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
2812{
2813 if (cso > u16PktLen)
2814 {
2815 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
2816 INSTANCE(pState), cso, u16PktLen));
2817 return;
2818 }
2819
2820 if (cse == 0)
2821 cse = u16PktLen - 1;
2822 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
2823 e1kCSum16(pPkt + css, cse - css + 1), cso,
2824 *(uint16_t*)(pPkt + cso)));
2825 *(uint16_t*)(pPkt + cso) = e1kCSum16(pPkt + css, cse - css + 1);
2826}
2827
2828/**
2829 * Add a part of descriptor's buffer to transmit frame.
2830 *
2831 * @remarks data.u64BufAddr is used uncoditionally for both data
2832 * and legacy descriptors since it is identical to
2833 * legacy.u64BufAddr.
2834 *
2835 * @param pState The device state structure.
2836 * @param pDesc Pointer to the descriptor to transmit.
2837 * @param u16Len Length of buffer to the end of segment.
2838 * @param fSend Force packet sending.
2839 * @thread E1000_TX
2840 */
2841static void e1kAddSegment(E1KSTATE* pState, E1KTXDESC* pDesc, uint16_t u16Len, bool fSend)
2842{
2843 /* TCP header being transmitted */
2844 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
2845 (pState->aTxPacket + pState->contextTSE.tu.u8CSS);
2846 /* IP header being transmitted */
2847 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
2848 (pState->aTxPacket + pState->contextTSE.ip.u8CSS);
2849
2850 E1kLog3(("%s e1kAddSegment: Length=%x, remaining payload=%x, header=%x, send=%s\n",
2851 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain,
2852 fSend ? "true" : "false"));
2853 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
2854
2855 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr,
2856 pState->aTxPacket + pState->u16TxPktLen, u16Len);
2857 E1kLog3(("%s Dump of the segment:\n"
2858 "%.*Rhxd\n"
2859 "%s --- End of dump ---\n",
2860 INSTANCE(pState), u16Len, pState->aTxPacket + pState->u16TxPktLen, INSTANCE(pState)));
2861 pState->u16TxPktLen += u16Len;
2862 E1kLog3(("%s e1kAddSegment: pState->u16TxPktLen=%x\n",
2863 INSTANCE(pState), pState->u16TxPktLen));
2864 if (pState->u16HdrRemain > 0)
2865 {
2866 /* The header was not complete, check if it is now */
2867 if (u16Len >= pState->u16HdrRemain)
2868 {
2869 /* The rest is payload */
2870 u16Len -= pState->u16HdrRemain;
2871 pState->u16HdrRemain = 0;
2872 /* Save partial checksum and flags */
2873 pState->u32SavedCsum = pTcpHdr->chksum;
2874 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
2875 /* Clear FIN and PSH flags now and set them only in the last segment */
2876 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
2877 }
2878 else
2879 {
2880 /* Still not */
2881 pState->u16HdrRemain -= u16Len;
2882 E1kLog3(("%s e1kAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
2883 INSTANCE(pState), pState->u16HdrRemain));
2884 return;
2885 }
2886 }
2887
2888 pState->u32PayRemain -= u16Len;
2889
2890 if (fSend)
2891 {
2892 /* Leave ethernet header intact */
2893 /* IP Total Length = payload + headers - ethernet header */
2894 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
2895 E1kLog3(("%s e1kAddSegment: End of packet, pIpHdr->total_len=%x\n",
2896 INSTANCE(pState), ntohs(pIpHdr->total_len)));
2897 /* Update IP Checksum */
2898 pIpHdr->chksum = 0;
2899 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2900 pState->contextTSE.ip.u8CSO,
2901 pState->contextTSE.ip.u8CSS,
2902 pState->contextTSE.ip.u16CSE);
2903
2904 /* Update TCP flags */
2905 /* Restore original FIN and PSH flags for the last segment */
2906 if (pState->u32PayRemain == 0)
2907 {
2908 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
2909 E1K_INC_CNT32(TSCTC);
2910 }
2911 /* Add TCP length to partial pseudo header sum */
2912 uint32_t csum = pState->u32SavedCsum
2913 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
2914 while (csum >> 16)
2915 csum = (csum >> 16) + (csum & 0xFFFF);
2916 pTcpHdr->chksum = csum;
2917 /* Compute final checksum */
2918 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
2919 pState->contextTSE.tu.u8CSO,
2920 pState->contextTSE.tu.u8CSS,
2921 pState->contextTSE.tu.u16CSE);
2922 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
2923 /* Update Sequence Number */
2924 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
2925 - pState->contextTSE.dw3.u8HDRLEN);
2926 /* Increment IP identification */
2927 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
2928 }
2929}
2930
2931/**
2932 * Add descriptor's buffer to transmit frame.
2933 *
2934 * @remarks data.u64BufAddr is used uncoditionally for both data
2935 * and legacy descriptors since it is identical to
2936 * legacy.u64BufAddr.
2937 *
2938 * @param pState The device state structure.
2939 * @param pDesc Pointer to the descriptor to transmit.
2940 * @param u16PartLen Length of descriptor's buffer.
2941 * @thread E1000_TX
2942 */
2943static bool e1kAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t u32PartLen)
2944{
2945 if (e1kGetDescType(pDesc) == E1K_DTYP_DATA && pDesc->data.cmd.fTSE)
2946 {
2947 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
2948 Assert(u16MaxPktLen != 0);
2949 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
2950
2951 do {
2952 /* Calculate how many bytes have left in this TCP segment */
2953 uint32_t uLen = u16MaxPktLen - pState->u16TxPktLen;
2954 if (uLen > u32PartLen)
2955 {
2956 /* This descriptor fits completely into current segment */
2957 uLen = u32PartLen;
2958 e1kAddSegment(pState, pDesc, uLen, pDesc->data.cmd.fEOP);
2959 }
2960 else
2961 {
2962 e1kAddSegment(pState, pDesc, uLen, true);
2963 /*
2964 * Rewind the packet tail pointer to the beginning of payload,
2965 * so we continue writing right beyond the header.
2966 */
2967 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
2968 }
2969 pDesc->data.u64BufAddr += uLen;
2970 u32PartLen -= uLen;
2971 } while (u32PartLen > 0);
2972 if (pDesc->data.cmd.fEOP)
2973 {
2974 /* End of packet, next segment will contain header. */
2975 pState->u16TxPktLen = 0;
2976 }
2977 return false;
2978 }
2979 else
2980 {
2981 if (u32PartLen + pState->u16TxPktLen > E1K_MAX_TX_PKT_SIZE)
2982 {
2983 E1kLog(("%s Transmit packet is too large: %d > %d(max)\n",
2984 INSTANCE(pState), u32PartLen + pState->u16TxPktLen, E1K_MAX_TX_PKT_SIZE));
2985 return false;
2986 }
2987 else
2988 {
2989 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr, pState->aTxPacket + pState->u16TxPktLen, u32PartLen);
2990 pState->u16TxPktLen += u32PartLen;
2991 }
2992 }
2993
2994 return true;
2995}
2996
2997
2998/**
2999 * Write the descriptor back to guest memory and notify the guest.
3000 *
3001 * @param pState The device state structure.
3002 * @param pDesc Pointer to the descriptor have been transmited.
3003 * @param addr Physical address of the descriptor in guest memory.
3004 * @thread E1000_TX
3005 */
3006static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3007{
3008 /*
3009 * We fake descriptor write-back bursting. Descriptors are written back as they are
3010 * processed.
3011 */
3012 /* Let's pretend we process descriptors. Write back with DD set. */
3013 if (pDesc->legacy.cmd.fRS || (GET_BITS(TXDCTL, WTHRESH) > 0))
3014 {
3015 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
3016 e1kWriteBackDesc(pState, pDesc, addr);
3017 if (pDesc->legacy.cmd.fEOP)
3018 {
3019#ifdef E1K_USE_TX_TIMERS
3020 if (pDesc->legacy.cmd.fIDE)
3021 {
3022 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
3023 //if (pState->fIntRaised)
3024 //{
3025 // /* Interrupt is already pending, no need for timers */
3026 // ICR |= ICR_TXDW;
3027 //}
3028 //else {
3029 /* Arm the timer to fire in TIVD usec (discard .024) */
3030 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
3031#ifndef E1K_NO_TAD
3032 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
3033 E1kLog2(("%s Checking if TAD timer is running\n",
3034 INSTANCE(pState)));
3035 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
3036 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
3037#endif /* E1K_NO_TAD */
3038 }
3039 else
3040 {
3041 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
3042 INSTANCE(pState)));
3043#ifndef E1K_NO_TAD
3044 /* Cancel both timers if armed and fire immediately. */
3045 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
3046#endif /* E1K_NO_TAD */
3047#endif /* E1K_USE_TX_TIMERS */
3048 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
3049 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
3050#ifdef E1K_USE_TX_TIMERS
3051 }
3052#endif /* E1K_USE_TX_TIMERS */
3053 }
3054 }
3055 else
3056 {
3057 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
3058 }
3059}
3060
3061/**
3062 * Process Transmit Descriptor.
3063 *
3064 * E1000 supports three types of transmit descriptors:
3065 * - legacy data descriptors of older format (context-less).
3066 * - data the same as legacy but providing new offloading capabilities.
3067 * - context sets up the context for following data descriptors.
3068 *
3069 * @param pState The device state structure.
3070 * @param pDesc Pointer to descriptor union.
3071 * @param addr Physical address of descriptor in guest memory.
3072 * @thread E1000_TX
3073 */
3074static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3075{
3076 e1kPrintTDesc(pState, pDesc, "vvv");
3077
3078#ifdef E1K_USE_TX_TIMERS
3079 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3080#endif /* E1K_USE_TX_TIMERS */
3081
3082 switch (e1kGetDescType(pDesc))
3083 {
3084 case E1K_DTYP_CONTEXT:
3085 if (pDesc->context.dw2.fTSE)
3086 {
3087 pState->contextTSE = pDesc->context;
3088 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3089 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3090 }
3091 else
3092 pState->contextNormal = pDesc->context;
3093 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3094 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3095 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3096 pDesc->context.ip.u8CSS,
3097 pDesc->context.ip.u8CSO,
3098 pDesc->context.ip.u16CSE,
3099 pDesc->context.tu.u8CSS,
3100 pDesc->context.tu.u8CSO,
3101 pDesc->context.tu.u16CSE));
3102 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3103 e1kDescReport(pState, pDesc, addr);
3104 break;
3105 case E1K_DTYP_DATA:
3106 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3107 {
3108 E1kLog2(("% Empty descriptor, skipped.\n", INSTANCE(pState)));
3109 break;
3110 }
3111 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3112 &pState->StatTxDescTSEData:
3113 &pState->StatTxDescData);
3114 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3115 /* IXSM and TXSM options are valid in the first fragment only */
3116 if (pState->u16TxPktLen == 0)
3117 {
3118 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3119 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3120 E1kLog2(("%s Saving checksum flags:%s%s\n", INSTANCE(pState),
3121 pState->fIPcsum ? " IP" : "",
3122 pState->fTCPcsum ? " TCP/UDP" : ""));
3123 }
3124 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3125 if (e1kAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN) && pDesc->data.cmd.fEOP)
3126 {
3127 if (!pDesc->data.cmd.fTSE)
3128 {
3129 /*
3130 * We only insert checksums here if this packet was not segmented,
3131 * otherwise it has already been taken care of by e1kAddSegment().
3132 */
3133 if (pState->fIPcsum)
3134 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3135 pState->contextNormal.ip.u8CSO,
3136 pState->contextNormal.ip.u8CSS,
3137 pState->contextNormal.ip.u16CSE);
3138 if (pState->fTCPcsum)
3139 e1kInsertChecksum(pState, pState->aTxPacket, pState->u16TxPktLen,
3140 pState->contextNormal.tu.u8CSO,
3141 pState->contextNormal.tu.u8CSS,
3142 pState->contextNormal.tu.u16CSE);
3143 }
3144 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3145 /* Reset transmit packet storage. */
3146 pState->u16TxPktLen = 0;
3147 }
3148 e1kDescReport(pState, pDesc, addr);
3149 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3150 break;
3151 case E1K_DTYP_LEGACY:
3152 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3153 {
3154 E1kLog(("%s Empty descriptor, skipped.\n", INSTANCE(pState)));
3155 break;
3156 }
3157 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3158 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3159 if (e1kAddToFrame(pState, pDesc, pDesc->legacy.cmd.u16Length))
3160 {
3161 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3162 /** @todo Offload processing goes here. */
3163 if (pDesc->legacy.cmd.fEOP)
3164 {
3165 e1kTransmitFrame(pState, pState->aTxPacket, pState->u16TxPktLen);
3166 /* Reset transmit packet storage. */
3167 pState->u16TxPktLen = 0;
3168 }
3169 }
3170 e1kDescReport(pState, pDesc, addr);
3171 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3172 break;
3173 default:
3174 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3175 INSTANCE(pState), e1kGetDescType(pDesc)));
3176 break;
3177 }
3178}
3179
3180/**
3181 * Wake up callback for transmission thread.
3182 *
3183 * @returns VBox status code. Returning failure will naturally terminate the thread.
3184 * @param pDevIns The pcnet device instance.
3185 * @param pThread The thread.
3186 */
3187static DECLCALLBACK(int) e1kTxThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3188{
3189 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3190 int rc = RTSemEventSignal(pState->hTxSem);
3191 AssertRC(rc);
3192 return VINF_SUCCESS;
3193}
3194
3195/**
3196 * I/O thread for packet transmission.
3197 *
3198 * @returns VBox status code. Returning failure will naturally terminate the thread.
3199 * @param pDevIns Pointer to device instance structure.
3200 * @param pThread The thread.
3201 * @thread E1000_TX
3202 */
3203static DECLCALLBACK(int) e1kTxThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3204{
3205 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3206
3207 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3208 {
3209 int rc = RTSemEventWait(pState->hTxSem, RT_INDEFINITE_WAIT);
3210 AssertRCReturn(rc, rc);
3211 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3212 break;
3213
3214 if (pThread->enmState == PDMTHREADSTATE_RUNNING)
3215 {
3216 E1KTXDESC desc;
3217 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3218 AssertRCReturn(rc, rc);
3219 /* Do not process descriptors in locked state */
3220 while (TDH != TDT && !pState->fLocked)
3221 {
3222 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3223 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3224 //if (!e1kCsEnter(pState, RT_SRC_POS))
3225 // return VERR_PERMISSION_DENIED;
3226 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3227 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3228 if (++TDH * sizeof(desc) >= TDLEN)
3229 TDH = 0;
3230 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3231 {
3232 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3233 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3234 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3235 }
3236 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3237 //e1kCsLeave(pState);
3238 }
3239 /// @todo: uncomment: pState->uStatIntTXQE++;
3240 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3241 e1kMutexRelease(pState);
3242 }
3243 }
3244 return VINF_SUCCESS;
3245}
3246
3247/**
3248 * Callback for consuming from transmit queue. It gets called in R3 whenever
3249 * we enqueue something in R0/GC.
3250 *
3251 * @returns true
3252 * @param pDevIns Pointer to device instance structure.
3253 * @param pItem Pointer to the element being dequeued (not used).
3254 * @thread ???
3255 */
3256static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3257{
3258 NOREF(pItem);
3259 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3260 E1kLog2(("%s e1kTxQueueConsumer: Waking up TX thread...\n", INSTANCE(pState)));
3261 int rc = RTSemEventSignal(pState->hTxSem);
3262 AssertRC(rc);
3263 return true;
3264}
3265
3266/**
3267 * Handler for the wakeup signaller queue.
3268 */
3269static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3270{
3271 e1kWakeupReceive(pDevIns);
3272 return true;
3273}
3274
3275#endif /* IN_RING3 */
3276
3277/**
3278 * Write handler for Transmit Descriptor Tail register.
3279 *
3280 * @param pState The device state structure.
3281 * @param offset Register offset in memory-mapped frame.
3282 * @param index Register index in register array.
3283 * @param value The value to store.
3284 * @param mask Used to implement partial writes (8 and 16-bit).
3285 * @thread EMT
3286 */
3287static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3288{
3289#ifndef IN_RING3
3290// return VINF_IOM_HC_MMIO_WRITE;
3291#endif
3292 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
3293 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3294 return rc;
3295 rc = e1kRegWriteDefault(pState, offset, index, value);
3296 /* All descriptors starting with head and not including tail belong to us. */
3297 /* Process them. */
3298 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3299 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
3300 /* Ignore TDT writes when the link is down. */
3301 if (TDH != TDT && (STATUS & STATUS_LU))
3302 {
3303 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
3304 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
3305 INSTANCE(pState), e1kGetTxLen(pState)));
3306#ifdef IN_RING3
3307 rc = RTSemEventSignal(pState->hTxSem);
3308 AssertRC(rc);
3309#else
3310 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
3311 if (RT_UNLIKELY(pItem))
3312 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
3313#endif /* !IN_RING3 */
3314
3315 }
3316 e1kCsTxLeave(pState);
3317
3318 return rc;
3319}
3320
3321/**
3322 * Write handler for Multicast Table Array registers.
3323 *
3324 * @param pState The device state structure.
3325 * @param offset Register offset in memory-mapped frame.
3326 * @param index Register index in register array.
3327 * @param value The value to store.
3328 * @thread EMT
3329 */
3330static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3331{
3332 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3333 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
3334
3335 return VINF_SUCCESS;
3336}
3337
3338/**
3339 * Read handler for Multicast Table Array registers.
3340 *
3341 * @returns VBox status code.
3342 *
3343 * @param pState The device state structure.
3344 * @param offset Register offset in memory-mapped frame.
3345 * @param index Register index in register array.
3346 * @thread EMT
3347 */
3348static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3349{
3350 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3351 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
3352
3353 return VINF_SUCCESS;
3354}
3355
3356/**
3357 * Write handler for Receive Address registers.
3358 *
3359 * @param pState The device state structure.
3360 * @param offset Register offset in memory-mapped frame.
3361 * @param index Register index in register array.
3362 * @param value The value to store.
3363 * @thread EMT
3364 */
3365static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3366{
3367 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3368 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
3369
3370 return VINF_SUCCESS;
3371}
3372
3373/**
3374 * Read handler for Receive Address registers.
3375 *
3376 * @returns VBox status code.
3377 *
3378 * @param pState The device state structure.
3379 * @param offset Register offset in memory-mapped frame.
3380 * @param index Register index in register array.
3381 * @thread EMT
3382 */
3383static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3384{
3385 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3386 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
3387
3388 return VINF_SUCCESS;
3389}
3390
3391/**
3392 * Write handler for VLAN Filter Table Array registers.
3393 *
3394 * @param pState The device state structure.
3395 * @param offset Register offset in memory-mapped frame.
3396 * @param index Register index in register array.
3397 * @param value The value to store.
3398 * @thread EMT
3399 */
3400static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3401{
3402 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
3403 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
3404
3405 return VINF_SUCCESS;
3406}
3407
3408/**
3409 * Read handler for VLAN Filter Table Array registers.
3410 *
3411 * @returns VBox status code.
3412 *
3413 * @param pState The device state structure.
3414 * @param offset Register offset in memory-mapped frame.
3415 * @param index Register index in register array.
3416 * @thread EMT
3417 */
3418static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3419{
3420 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
3421 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
3422
3423 return VINF_SUCCESS;
3424}
3425
3426/**
3427 * Read handler for unimplemented registers.
3428 *
3429 * Merely reports reads from unimplemented registers.
3430 *
3431 * @returns VBox status code.
3432 *
3433 * @param pState The device state structure.
3434 * @param offset Register offset in memory-mapped frame.
3435 * @param index Register index in register array.
3436 * @thread EMT
3437 */
3438
3439static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3440{
3441 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
3442 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3443 *pu32Value = 0;
3444
3445 return VINF_SUCCESS;
3446}
3447
3448/**
3449 * Default register read handler with automatic clear operation.
3450 *
3451 * Retrieves the value of register from register array in device state structure.
3452 * Then resets all bits.
3453 *
3454 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3455 * done in the caller.
3456 *
3457 * @returns VBox status code.
3458 *
3459 * @param pState The device state structure.
3460 * @param offset Register offset in memory-mapped frame.
3461 * @param index Register index in register array.
3462 * @thread EMT
3463 */
3464
3465static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3466{
3467 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3468 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
3469 pState->auRegs[index] = 0;
3470
3471 return rc;
3472}
3473
3474/**
3475 * Default register read handler.
3476 *
3477 * Retrieves the value of register from register array in device state structure.
3478 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
3479 *
3480 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
3481 * done in the caller.
3482 *
3483 * @returns VBox status code.
3484 *
3485 * @param pState The device state structure.
3486 * @param offset Register offset in memory-mapped frame.
3487 * @param index Register index in register array.
3488 * @thread EMT
3489 */
3490
3491static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3492{
3493 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3494 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
3495
3496 return VINF_SUCCESS;
3497}
3498
3499/**
3500 * Write handler for unimplemented registers.
3501 *
3502 * Merely reports writes to unimplemented registers.
3503 *
3504 * @param pState The device state structure.
3505 * @param offset Register offset in memory-mapped frame.
3506 * @param index Register index in register array.
3507 * @param value The value to store.
3508 * @thread EMT
3509 */
3510
3511static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3512{
3513 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
3514 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3515
3516 return VINF_SUCCESS;
3517}
3518
3519/**
3520 * Default register write handler.
3521 *
3522 * Stores the value to the register array in device state structure. Only bits
3523 * corresponding to 1s both in 'writable' and 'mask' will be stored.
3524 *
3525 * @returns VBox status code.
3526 *
3527 * @param pState The device state structure.
3528 * @param offset Register offset in memory-mapped frame.
3529 * @param index Register index in register array.
3530 * @param value The value to store.
3531 * @param mask Used to implement partial writes (8 and 16-bit).
3532 * @thread EMT
3533 */
3534
3535static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3536{
3537 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
3538 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
3539 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
3540
3541 return VINF_SUCCESS;
3542}
3543
3544/**
3545 * Search register table for matching register.
3546 *
3547 * @returns Index in the register table or -1 if not found.
3548 *
3549 * @param pState The device state structure.
3550 * @param uOffset Register offset in memory-mapped region.
3551 * @thread EMT
3552 */
3553static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
3554{
3555 int index;
3556
3557 for (index = 0; index < E1K_NUM_OF_REGS; index++)
3558 {
3559 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
3560 {
3561 return index;
3562 }
3563 }
3564
3565 return -1;
3566}
3567
3568/**
3569 * Handle register read operation.
3570 *
3571 * Looks up and calls appropriate handler.
3572 *
3573 * @returns VBox status code.
3574 *
3575 * @param pState The device state structure.
3576 * @param uOffset Register offset in memory-mapped frame.
3577 * @param pv Where to store the result.
3578 * @param cb Number of bytes to read.
3579 * @thread EMT
3580 */
3581static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
3582{
3583 uint32_t u32 = 0;
3584 uint32_t mask = 0;
3585 uint32_t shift;
3586 int rc = VINF_SUCCESS;
3587 int index = e1kRegLookup(pState, uOffset);
3588 const char *szInst = INSTANCE(pState);
3589#ifdef DEBUG
3590 char buf[9];
3591#endif
3592
3593 /*
3594 * From the spec:
3595 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3596 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3597 */
3598
3599 /*
3600 * To be able to write bytes and short word we convert them
3601 * to properly shifted 32-bit words and masks. The idea is
3602 * to keep register-specific handlers simple. Most accesses
3603 * will be 32-bit anyway.
3604 */
3605 switch (cb)
3606 {
3607 case 1: mask = 0x000000FF; break;
3608 case 2: mask = 0x0000FFFF; break;
3609 case 4: mask = 0xFFFFFFFF; break;
3610 default:
3611 return PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3612 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
3613 szInst, uOffset, cb);
3614 }
3615 if (index != -1)
3616 {
3617 if (s_e1kRegMap[index].readable)
3618 {
3619 /* Make the mask correspond to the bits we are about to read. */
3620 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
3621 mask <<= shift;
3622 if (!mask)
3623 return PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
3624 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
3625 szInst, uOffset, cb);
3626 /*
3627 * Read it. Pass the mask so the handler knows what has to be read.
3628 * Mask out irrelevant bits.
3629 */
3630#ifdef E1K_GLOBAL_MUTEX
3631 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
3632#else
3633 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3634#endif
3635 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3636 return rc;
3637 //pState->fDelayInts = false;
3638 //pState->iStatIntLost += pState->iStatIntLostOne;
3639 //pState->iStatIntLostOne = 0;
3640 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32) & mask;
3641 //e1kCsLeave(pState);
3642 e1kMutexRelease(pState);
3643 E1kLog2(("%s At %08X read %s from %s (%s)\n",
3644 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3645 /* Shift back the result. */
3646 u32 >>= shift;
3647 }
3648 else
3649 {
3650 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
3651 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3652 }
3653 }
3654 else
3655 {
3656 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
3657 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
3658 }
3659
3660 memcpy(pv, &u32, cb);
3661 return rc;
3662}
3663
3664/**
3665 * Handle register write operation.
3666 *
3667 * Looks up and calls appropriate handler.
3668 *
3669 * @returns VBox status code.
3670 *
3671 * @param pState The device state structure.
3672 * @param uOffset Register offset in memory-mapped frame.
3673 * @param pv Where to fetch the value.
3674 * @param cb Number of bytes to write.
3675 * @thread EMT
3676 */
3677static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void *pv, unsigned cb)
3678{
3679 int rc = VINF_SUCCESS;
3680 int index = e1kRegLookup(pState, uOffset);
3681 uint32_t u32;
3682
3683 /*
3684 * From the spec:
3685 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
3686 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
3687 */
3688
3689 if (cb != 4)
3690 {
3691 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
3692 INSTANCE(pState), uOffset, cb));
3693 return VINF_SUCCESS;
3694 }
3695 if (uOffset & 3)
3696 {
3697 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
3698 INSTANCE(pState), uOffset, cb));
3699 return VINF_SUCCESS;
3700 }
3701 u32 = *(uint32_t*)pv;
3702 if (index != -1)
3703 {
3704 if (s_e1kRegMap[index].writable)
3705 {
3706 /*
3707 * Write it. Pass the mask so the handler knows what has to be written.
3708 * Mask out irrelevant bits.
3709 */
3710 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
3711 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3712#ifdef E1K_GLOBAL_MUTEX
3713 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
3714#else
3715 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
3716#endif
3717 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3718 return rc;
3719 //pState->fDelayInts = false;
3720 //pState->iStatIntLost += pState->iStatIntLostOne;
3721 //pState->iStatIntLostOne = 0;
3722 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
3723 //e1kCsLeave(pState);
3724 e1kMutexRelease(pState);
3725 }
3726 else
3727 {
3728 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
3729 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
3730 }
3731 }
3732 else
3733 {
3734 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
3735 INSTANCE(pState), uOffset, u32));
3736 }
3737 return rc;
3738}
3739
3740/**
3741 * I/O handler for memory-mapped read operations.
3742 *
3743 * @returns VBox status code.
3744 *
3745 * @param pDevIns The device instance.
3746 * @param pvUser User argument.
3747 * @param GCPhysAddr Physical address (in GC) where the read starts.
3748 * @param pv Where to store the result.
3749 * @param cb Number of bytes read.
3750 * @thread EMT
3751 */
3752PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
3753 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3754{
3755 NOREF(pvUser);
3756 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3757 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3758 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIORead), a);
3759
3760 Assert(uOffset < E1K_MM_SIZE);
3761
3762 int rc = e1kRegRead(pState, uOffset, pv, cb);
3763 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIORead), a);
3764 return rc;
3765}
3766
3767/**
3768 * Memory mapped I/O Handler for write operations.
3769 *
3770 * @returns VBox status code.
3771 *
3772 * @param pDevIns The device instance.
3773 * @param pvUser User argument.
3774 * @param GCPhysAddr Physical address (in GC) where the read starts.
3775 * @param pv Where to fetch the value.
3776 * @param cb Number of bytes to write.
3777 * @thread EMT
3778 */
3779PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
3780 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3781{
3782 NOREF(pvUser);
3783 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3784 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
3785 int rc;
3786 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIOWrite), a);
3787
3788 Assert(uOffset < E1K_MM_SIZE);
3789 if (cb != 4)
3790 {
3791 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
3792 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
3793 }
3794 else
3795 rc = e1kRegWrite(pState, uOffset, pv, cb);
3796
3797 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIOWrite), a);
3798 return rc;
3799}
3800
3801/**
3802 * Port I/O Handler for IN operations.
3803 *
3804 * @returns VBox status code.
3805 *
3806 * @param pDevIns The device instance.
3807 * @param pvUser Pointer to the device state structure.
3808 * @param port Port number used for the IN operation.
3809 * @param pu32 Where to store the result.
3810 * @param cb Number of bytes read.
3811 * @thread EMT
3812 */
3813PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
3814 RTIOPORT port, uint32_t *pu32, unsigned cb)
3815{
3816 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3817 int rc = VINF_SUCCESS;
3818 const char *szInst = INSTANCE(pState);
3819 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
3820
3821 port -= pState->addrIOPort;
3822 if (cb != 4)
3823 {
3824 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
3825 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3826 }
3827 else
3828 switch (port)
3829 {
3830 case 0x00: /* IOADDR */
3831 *pu32 = pState->uSelectedReg;
3832 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3833 break;
3834 case 0x04: /* IODATA */
3835 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
3836 /* @todo wrong return code triggers assertions in the debug build; fix please */
3837 if (rc == VINF_IOM_HC_MMIO_READ)
3838 rc = VINF_IOM_HC_IOPORT_READ;
3839
3840 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
3841 break;
3842 default:
3843 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
3844 //*pRC = VERR_IOM_IOPORT_UNUSED;
3845 }
3846
3847 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
3848 return rc;
3849}
3850
3851
3852/**
3853 * Port I/O Handler for OUT operations.
3854 *
3855 * @returns VBox status code.
3856 *
3857 * @param pDevIns The device instance.
3858 * @param pvUser User argument.
3859 * @param Port Port number used for the IN operation.
3860 * @param u32 The value to output.
3861 * @param cb The value size in bytes.
3862 * @thread EMT
3863 */
3864PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
3865 RTIOPORT port, uint32_t u32, unsigned cb)
3866{
3867 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3868 int rc = VINF_SUCCESS;
3869 const char *szInst = INSTANCE(pState);
3870 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
3871
3872 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
3873 if (cb != 4)
3874 {
3875 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
3876 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
3877 }
3878 else
3879 {
3880 port -= pState->addrIOPort;
3881 switch (port)
3882 {
3883 case 0x00: /* IOADDR */
3884 pState->uSelectedReg = u32;
3885 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
3886 break;
3887 case 0x04: /* IODATA */
3888 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
3889 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
3890 /* @todo wrong return code triggers assertions in the debug build; fix please */
3891 if (rc == VINF_IOM_HC_MMIO_WRITE)
3892 rc = VINF_IOM_HC_IOPORT_WRITE;
3893 break;
3894 default:
3895 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
3896 /** @todo Do we need to return an error here?
3897 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
3898 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
3899 rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
3900 }
3901 }
3902
3903 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
3904 return rc;
3905}
3906
3907#ifdef IN_RING3
3908/**
3909 * Dump complete device state to log.
3910 *
3911 * @param pState Pointer to device state.
3912 */
3913static void e1kDumpState(E1KSTATE *pState)
3914{
3915 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
3916 {
3917 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
3918 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
3919 }
3920#ifdef E1K_INT_STATS
3921 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
3922 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
3923 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
3924 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
3925 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
3926 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
3927 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
3928 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
3929 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
3930 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
3931 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
3932 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
3933 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
3934 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
3935 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
3936 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
3937 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
3938 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
3939 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
3940 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
3941 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
3942 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
3943 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
3944 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
3945 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
3946 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
3947 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
3948#endif /* E1K_INT_STATS */
3949}
3950
3951/**
3952 * Map PCI I/O region.
3953 *
3954 * @return VBox status code.
3955 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
3956 * @param iRegion The region number.
3957 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
3958 * I/O port, else it's a physical address.
3959 * This address is *NOT* relative to pci_mem_base like earlier!
3960 * @param cb Region size.
3961 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
3962 * @thread EMT
3963 */
3964static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
3965 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
3966{
3967 int rc;
3968 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
3969
3970 switch (enmType)
3971 {
3972 case PCI_ADDRESS_SPACE_IO:
3973 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
3974 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3975 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
3976 if (RT_FAILURE(rc))
3977 break;
3978 if (pState->fR0Enabled)
3979 {
3980 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3981 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
3982 if (RT_FAILURE(rc))
3983 break;
3984 }
3985 if (pState->fGCEnabled)
3986 {
3987 rc = PDMDevHlpIOPortRegisterGC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
3988 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
3989 }
3990 break;
3991 case PCI_ADDRESS_SPACE_MEM:
3992 pState->addrMMReg = GCPhysAddress;
3993 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
3994 e1kMMIOWrite, e1kMMIORead, NULL, "E1000");
3995 if (pState->fR0Enabled)
3996 {
3997 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, 0,
3998 "e1kMMIOWrite", "e1kMMIORead", NULL);
3999 if (RT_FAILURE(rc))
4000 break;
4001 }
4002 if (pState->fGCEnabled)
4003 {
4004 rc = PDMDevHlpMMIORegisterGC(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4005 "e1kMMIOWrite", "e1kMMIORead", NULL);
4006 }
4007 break;
4008 default:
4009 /* We should never get here */
4010 AssertMsgFailed(("Invalid PCI address space param in map callback"));
4011 rc = VERR_INTERNAL_ERROR;
4012 break;
4013 }
4014 return rc;
4015}
4016
4017/**
4018 * Check if the device can receive data now.
4019 * This must be called before the pfnRecieve() method is called.
4020 *
4021 * @returns Number of bytes the device can receive.
4022 * @param pInterface Pointer to the interface structure containing the called function pointer.
4023 * @thread EMT
4024 */
4025static int e1kCanReceive(E1KSTATE *pState)
4026{
4027 size_t cb;
4028
4029 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
4030 return VERR_NET_NO_BUFFER_SPACE;
4031 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
4032 return VERR_NET_NO_BUFFER_SPACE;
4033
4034 if (RDH < RDT)
4035 cb = (RDT - RDH) * pState->u16RxBSize;
4036 else if (RDH > RDT)
4037 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
4038 else
4039 {
4040 cb = 0;
4041 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
4042 }
4043
4044 e1kCsRxLeave(pState);
4045 e1kMutexRelease(pState);
4046 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
4047}
4048
4049static DECLCALLBACK(int) e1kWaitReceiveAvail(PPDMINETWORKPORT pInterface, unsigned cMillies)
4050{
4051 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkPort);
4052 int rc = e1kCanReceive(pState);
4053
4054 if (RT_SUCCESS(rc))
4055 return VINF_SUCCESS;
4056 if (RT_UNLIKELY(cMillies == 0))
4057 return VERR_NET_NO_BUFFER_SPACE;
4058
4059 rc = VERR_INTERRUPTED;
4060 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
4061 STAM_PROFILE_START(&pState->StatRxOverflow, a);
4062 while (RT_LIKELY(PDMDevHlpVMState(pState->CTX_SUFF(pDevIns)) == VMSTATE_RUNNING))
4063 {
4064 int rc2 = e1kCanReceive(pState);
4065 if (RT_SUCCESS(rc2))
4066 {
4067 rc = VINF_SUCCESS;
4068 break;
4069 }
4070 E1kLogRel(("E1000 e1kWaitReceiveAvail: waiting cMillies=%u...\n",
4071 cMillies));
4072 E1kLog(("%s e1kWaitReceiveAvail: waiting cMillies=%u...\n",
4073 INSTANCE(pState), cMillies));
4074 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
4075 }
4076 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
4077 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
4078
4079 return rc;
4080}
4081
4082
4083/**
4084 * Matches the packet addresses against Receive Address table. Looks for
4085 * exact matches only.
4086 *
4087 * @returns true if address matches.
4088 * @param pState Pointer to the state structure.
4089 * @param pvBuf The ethernet packet.
4090 * @param cb Number of bytes available in the packet.
4091 * @thread EMT
4092 */
4093static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4094{
4095 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4096 {
4097 E1KRAELEM* ra = pState->aRecAddr.array + i;
4098
4099 /* Valid address? */
4100 if (ra->ctl & RA_CTL_AV)
4101 {
4102 Assert((ra->ctl & RA_CTL_AS) < 2);
4103 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4104 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4105 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4106 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4107 /*
4108 * Address Select:
4109 * 00b = Destination address
4110 * 01b = Source address
4111 * 10b = Reserved
4112 * 11b = Reserved
4113 * Since ethernet header is (DA, SA, len) we can use address
4114 * select as index.
4115 */
4116 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4117 ra->addr, sizeof(ra->addr)) == 0)
4118 return true;
4119 }
4120 }
4121
4122 return false;
4123}
4124
4125/**
4126 * Matches the packet addresses against Multicast Table Array.
4127 *
4128 * @remarks This is imperfect match since it matches not exact address but
4129 * a subset of addresses.
4130 *
4131 * @returns true if address matches.
4132 * @param pState Pointer to the state structure.
4133 * @param pvBuf The ethernet packet.
4134 * @param cb Number of bytes available in the packet.
4135 * @thread EMT
4136 */
4137static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4138{
4139 /* Get bits 32..47 of destination address */
4140 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4141
4142 unsigned offset = GET_BITS(RCTL, MO);
4143 /*
4144 * offset means:
4145 * 00b = bits 36..47
4146 * 01b = bits 35..46
4147 * 10b = bits 34..45
4148 * 11b = bits 32..43
4149 */
4150 if (offset < 3)
4151 u16Bit = u16Bit >> (4 - offset);
4152 return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
4153}
4154
4155/**
4156 * Determines if the packet is to be delivered to upper layer. The following
4157 * filters supported:
4158 * - Exact Unicast/Multicast
4159 * - Promiscuous Unicast/Multicast
4160 * - Multicast
4161 * - VLAN
4162 *
4163 * @returns true if packet is intended for this node.
4164 * @param pState Pointer to the state structure.
4165 * @param pvBuf The ethernet packet.
4166 * @param cb Number of bytes available in the packet.
4167 * @param pStatus Bit field to store status bits.
4168 * @thread EMT
4169 */
4170static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4171{
4172 Assert(cb > 14);
4173 /* Assume that we fail to pass exact filter. */
4174 pStatus->fPIF = false;
4175 pStatus->fVP = false;
4176 /* Discard oversized packets */
4177 if (cb > E1K_MAX_RX_PKT_SIZE)
4178 {
4179 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4180 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4181 E1K_INC_CNT32(ROC);
4182 return false;
4183 }
4184 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4185 {
4186 /* When long packet reception is disabled packets over 1522 are discarded */
4187 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4188 INSTANCE(pState), cb));
4189 E1K_INC_CNT32(ROC);
4190 return false;
4191 }
4192
4193 /* Broadcast filtering */
4194 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4195 return true;
4196 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4197 if (e1kIsMulticast(pvBuf))
4198 {
4199 /* Is multicast promiscuous enabled? */
4200 if (RCTL & RCTL_MPE)
4201 return true;
4202 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4203 /* Try perfect matches first */
4204 if (e1kPerfectMatch(pState, pvBuf))
4205 {
4206 pStatus->fPIF = true;
4207 return true;
4208 }
4209 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4210 if (e1kImperfectMatch(pState, pvBuf))
4211 return true;
4212 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
4213 }
4214 else {
4215 /* Is unicast promiscuous enabled? */
4216 if (RCTL & RCTL_UPE)
4217 return true;
4218 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
4219 if (e1kPerfectMatch(pState, pvBuf))
4220 {
4221 pStatus->fPIF = true;
4222 return true;
4223 }
4224 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4225 }
4226 /* Is VLAN filtering enabled? */
4227 if (RCTL & RCTL_VFE)
4228 {
4229 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4230 /* Compare TPID with VLAN Ether Type */
4231 if (u16Ptr[6] == VET)
4232 {
4233 pStatus->fVP = true;
4234 /* It is 802.1q packet indeed, let's filter by VID */
4235 if (ASMBitTest(pState->auVFTA, RT_BE2H_U16(u16Ptr[7]) & 0xFFF))
4236 return true;
4237 E1kLog2(("%s Packet filter: no VLAN match\n", INSTANCE(pState)));
4238 }
4239 }
4240 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
4241 return false;
4242}
4243
4244/**
4245 * Receive data from the network.
4246 *
4247 * @returns VBox status code.
4248 * @param pInterface Pointer to the interface structure containing the called function pointer.
4249 * @param pvBuf The available data.
4250 * @param cb Number of bytes available in the buffer.
4251 * @thread ???
4252 */
4253static DECLCALLBACK(int) e1kReceive(PPDMINETWORKPORT pInterface, const void *pvBuf, size_t cb)
4254{
4255 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkPort);
4256 int rc = VINF_SUCCESS;
4257
4258 /* Discard incoming packets in locked state */
4259 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
4260 {
4261 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
4262 return VINF_SUCCESS;
4263 }
4264
4265 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
4266 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4267 if (RT_LIKELY(rc == VINF_SUCCESS))
4268 {
4269 //if (!e1kCsEnter(pState, RT_SRC_POS))
4270 // return VERR_PERMISSION_DENIED;
4271
4272 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
4273
4274 /* Update stats */
4275 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
4276 {
4277 E1K_INC_CNT32(TPR);
4278 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
4279 e1kCsLeave(pState);
4280 }
4281 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
4282 E1KRXDST status;
4283 memset(&status, 0, sizeof(status));
4284 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
4285 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
4286 if (fPassed)
4287 {
4288 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
4289 }
4290 //e1kCsLeave(pState);
4291 e1kMutexRelease(pState);
4292 }
4293 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
4294
4295 return rc;
4296}
4297
4298/**
4299 * Gets the pointer to the status LED of a unit.
4300 *
4301 * @returns VBox status code.
4302 * @param pInterface Pointer to the interface structure.
4303 * @param iLUN The unit which status LED we desire.
4304 * @param ppLed Where to store the LED pointer.
4305 * @thread EMT
4306 */
4307static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4308{
4309 E1KSTATE *pState = IFACE_TO_STATE(pInterface, ILeds);
4310 int rc = VERR_PDM_LUN_NOT_FOUND;
4311
4312 if (iLUN == 0)
4313 {
4314 *ppLed = &pState->led;
4315 rc = VINF_SUCCESS;
4316 }
4317 return rc;
4318}
4319
4320/**
4321 * Gets the current Media Access Control (MAC) address.
4322 *
4323 * @returns VBox status code.
4324 * @param pInterface Pointer to the interface structure containing the called function pointer.
4325 * @param pMac Where to store the MAC address.
4326 * @thread EMT
4327 */
4328static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4329{
4330 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4331 pState->eeprom.getMac(pMac);
4332 return VINF_SUCCESS;
4333}
4334
4335
4336/**
4337 * Gets the new link state.
4338 *
4339 * @returns The current link state.
4340 * @param pInterface Pointer to the interface structure containing the called function pointer.
4341 * @thread EMT
4342 */
4343static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
4344{
4345 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4346 if (STATUS & STATUS_LU)
4347 return PDMNETWORKLINKSTATE_UP;
4348 return PDMNETWORKLINKSTATE_DOWN;
4349}
4350
4351
4352/**
4353 * Sets the new link state.
4354 *
4355 * @returns VBox status code.
4356 * @param pInterface Pointer to the interface structure containing the called function pointer.
4357 * @param enmState The new link state
4358 * @thread EMT
4359 */
4360static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4361{
4362 E1KSTATE *pState = IFACE_TO_STATE(pInterface, INetworkConfig);
4363 bool fOldUp = !!(STATUS & STATUS_LU);
4364 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
4365
4366 if (fNewUp != fOldUp)
4367 {
4368 if (fNewUp)
4369 {
4370 E1kLog(("%s Link will be up in approximately 5 secs\n", INSTANCE(pState)));
4371 STATUS &= ~STATUS_LU;
4372 Phy::setLinkStatus(&pState->phy, false);
4373 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4374 /* Restore the link back in 5 second. */
4375 e1kArmTimer(pState, pState->pLUTimer, 5000000);
4376 }
4377 else
4378 {
4379 E1kLog(("%s Link is down\n", INSTANCE(pState)));
4380 STATUS &= ~STATUS_LU;
4381 Phy::setLinkStatus(&pState->phy, false);
4382 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4383 }
4384 if (pState->pDrv)
4385 pState->pDrv->pfnNotifyLinkChanged(pState->pDrv, enmState);
4386 }
4387 return VINF_SUCCESS;
4388}
4389
4390/**
4391 * Provides interfaces to the driver.
4392 *
4393 * @returns Pointer to interface. NULL if the interface is not supported.
4394 * @param pInterface Pointer to this interface structure.
4395 * @param enmInterface The requested interface identification.
4396 * @thread EMT
4397 */
4398static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, PDMINTERFACE enmInterface)
4399{
4400 E1KSTATE *pState = IFACE_TO_STATE(pInterface, IBase);
4401 Assert(&pState->IBase == pInterface);
4402 switch (enmInterface)
4403 {
4404 case PDMINTERFACE_BASE:
4405 return &pState->IBase;
4406 case PDMINTERFACE_NETWORK_PORT:
4407 return &pState->INetworkPort;
4408 case PDMINTERFACE_NETWORK_CONFIG:
4409 return &pState->INetworkConfig;
4410 case PDMINTERFACE_LED_PORTS:
4411 return &pState->ILeds;
4412 default:
4413 return NULL;
4414 }
4415}
4416
4417/**
4418 * Saves the configuration.
4419 *
4420 * @param pState The E1K state.
4421 * @param pSSM The handle to the saved state.
4422 */
4423static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
4424{
4425 SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
4426 SSMR3PutU32(pSSM, pState->eChip);
4427}
4428
4429/**
4430 * Live save - save basic configuration.
4431 *
4432 * @returns VBox status code.
4433 * @param pDevIns The device instance.
4434 * @param pSSM The handle to the saved state.
4435 * @param uPass
4436 */
4437static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
4438{
4439 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4440 e1kSaveConfig(pState, pSSM);
4441 return VINF_SSM_DONT_CALL_AGAIN;
4442}
4443
4444/**
4445 * Prepares for state saving.
4446 *
4447 * @returns VBox status code.
4448 * @param pDevIns The device instance.
4449 * @param pSSM The handle to the saved state.
4450 */
4451static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4452{
4453 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4454
4455 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4456 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4457 return rc;
4458 e1kCsLeave(pState);
4459 return VINF_SUCCESS;
4460#if 0
4461 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4462 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4463 return rc;
4464 /* 1) Prevent all threads from modifying the state and memory */
4465 //pState->fLocked = true;
4466 /* 2) Cancel all timers */
4467#ifdef E1K_USE_TX_TIMERS
4468 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
4469#ifndef E1K_NO_TAD
4470 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
4471#endif /* E1K_NO_TAD */
4472#endif /* E1K_USE_TX_TIMERS */
4473#ifdef E1K_USE_RX_TIMERS
4474 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
4475 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
4476#endif /* E1K_USE_RX_TIMERS */
4477 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
4478 /* 3) Did I forget anything? */
4479 E1kLog(("%s Locked\n", INSTANCE(pState)));
4480 e1kMutexRelease(pState);
4481 return VINF_SUCCESS;
4482#endif
4483}
4484
4485
4486/**
4487 * Saves the state of device.
4488 *
4489 * @returns VBox status code.
4490 * @param pDevIns The device instance.
4491 * @param pSSM The handle to the saved state.
4492 */
4493static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4494{
4495 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4496
4497 e1kSaveConfig(pState, pSSM);
4498 pState->eeprom.save(pSSM);
4499 e1kDumpState(pState);
4500 SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
4501 SSMR3PutBool(pSSM, pState->fIntRaised);
4502 Phy::saveState(pSSM, &pState->phy);
4503 SSMR3PutU32(pSSM, pState->uSelectedReg);
4504 SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
4505 SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
4506 SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
4507 SSMR3PutU64(pSSM, pState->u64AckedAt);
4508 SSMR3PutU16(pSSM, pState->u16RxBSize);
4509 //SSMR3PutBool(pSSM, pState->fDelayInts);
4510 //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
4511 SSMR3PutU16(pSSM, pState->u16TxPktLen);
4512 SSMR3PutMem(pSSM, pState->aTxPacket, pState->u16TxPktLen);
4513 SSMR3PutBool(pSSM, pState->fIPcsum);
4514 SSMR3PutBool(pSSM, pState->fTCPcsum);
4515 SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
4516 SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
4517 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
4518 return VINF_SUCCESS;
4519}
4520
4521#if 0
4522/**
4523 * Cleanup after saving.
4524 *
4525 * @returns VBox status code.
4526 * @param pDevIns The device instance.
4527 * @param pSSM The handle to the saved state.
4528 */
4529static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4530{
4531 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4532
4533 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4534 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4535 return rc;
4536 /* If VM is being powered off unlocking will result in assertions in PGM */
4537 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
4538 pState->fLocked = false;
4539 else
4540 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
4541 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
4542 e1kMutexRelease(pState);
4543 return VINF_SUCCESS;
4544}
4545#endif
4546
4547/**
4548 * Sync with .
4549 *
4550 * @returns VBox status code.
4551 * @param pDevIns The device instance.
4552 * @param pSSM The handle to the saved state.
4553 */
4554static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4555{
4556 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4557
4558 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
4559 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4560 return rc;
4561 e1kCsLeave(pState);
4562 return VINF_SUCCESS;
4563}
4564
4565/**
4566 * Restore previously saved state of device.
4567 *
4568 * @returns VBox status code.
4569 * @param pDevIns The device instance.
4570 * @param pSSM The handle to the saved state.
4571 * @param uVersion The data unit version number.
4572 * @param uPass The data pass.
4573 */
4574static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4575{
4576 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4577 int rc;
4578
4579 if ( uVersion != E1K_SAVEDSTATE_VERSION
4580 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
4581 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
4582
4583 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
4584 || uPass != SSM_PASS_FINAL)
4585 {
4586 /* config checks */
4587 RTMAC macConfigured;
4588 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
4589 AssertRCReturn(rc, rc);
4590 if ( memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
4591 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
4592 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", INSTANCE(pState), &pState->macConfigured, &macConfigured));
4593
4594 E1KCHIP eChip;
4595 rc = SSMR3GetU32(pSSM, &eChip);
4596 AssertRCReturn(rc, rc);
4597 if (eChip != pState->eChip)
4598 {
4599 LogRel(("%s: The mac address differs: config=%u saved=%u\n", INSTANCE(pState), pState->eChip, eChip));
4600 return VERR_SSM_LOAD_CONFIG_MISMATCH;
4601 }
4602 }
4603
4604 if (uPass == SSM_PASS_FINAL)
4605 {
4606 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
4607 {
4608 rc = pState->eeprom.load(pSSM);
4609 AssertRCReturn(rc, rc);
4610 }
4611 /* the state */
4612 SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
4613 SSMR3GetBool(pSSM, &pState->fIntRaised);
4614 /** @todo: PHY could be made a separate device with its own versioning */
4615 Phy::loadState(pSSM, &pState->phy);
4616 SSMR3GetU32(pSSM, &pState->uSelectedReg);
4617 SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
4618 SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
4619 SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
4620 SSMR3GetU64(pSSM, &pState->u64AckedAt);
4621 SSMR3GetU16(pSSM, &pState->u16RxBSize);
4622 //SSMR3GetBool(pSSM, pState->fDelayInts);
4623 //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
4624 SSMR3GetU16(pSSM, &pState->u16TxPktLen);
4625 SSMR3GetMem(pSSM, &pState->aTxPacket, pState->u16TxPktLen);
4626 SSMR3GetBool(pSSM, &pState->fIPcsum);
4627 SSMR3GetBool(pSSM, &pState->fTCPcsum);
4628 SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
4629 rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
4630 AssertRCReturn(rc, rc);
4631 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
4632 e1kDumpState(pState);
4633 }
4634 return VINF_SUCCESS;
4635}
4636
4637/**
4638 * Link status adjustments after loading.
4639 *
4640 * @returns VBox status code.
4641 * @param pDevIns The device instance.
4642 * @param pSSM The handle to the saved state.
4643 */
4644static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4645{
4646 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4647
4648 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4649 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4650 return rc;
4651 /*
4652 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
4653 * passed to us. We go through all this stuff if the link was up and we
4654 * wasn't teleported.
4655 */
4656 if ( (STATUS & STATUS_LU)
4657 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
4658 {
4659 E1kLog(("%s Link is down temporarily\n", INSTANCE(pState)));
4660 STATUS &= ~STATUS_LU;
4661 Phy::setLinkStatus(&pState->phy, false);
4662 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4663 /* Restore the link back in five seconds. */
4664 e1kArmTimer(pState, pState->pLUTimer, 5000000);
4665 }
4666 e1kMutexRelease(pState);
4667 return VINF_SUCCESS;
4668}
4669
4670/**
4671 * Sets 8-bit register in PCI configuration space.
4672 * @param refPciDev The PCI device.
4673 * @param uOffset The register offset.
4674 * @param u16Value The value to store in the register.
4675 * @thread EMT
4676 */
4677DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
4678{
4679 Assert(uOffset < sizeof(refPciDev.config));
4680 refPciDev.config[uOffset] = u8Value;
4681}
4682
4683/**
4684 * Sets 16-bit register in PCI configuration space.
4685 * @param refPciDev The PCI device.
4686 * @param uOffset The register offset.
4687 * @param u16Value The value to store in the register.
4688 * @thread EMT
4689 */
4690DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
4691{
4692 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
4693 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
4694}
4695
4696/**
4697 * Sets 32-bit register in PCI configuration space.
4698 * @param refPciDev The PCI device.
4699 * @param uOffset The register offset.
4700 * @param u32Value The value to store in the register.
4701 * @thread EMT
4702 */
4703DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
4704{
4705 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
4706 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
4707}
4708
4709/**
4710 * Set PCI configuration space registers.
4711 *
4712 * @param pci Reference to PCI device structure.
4713 * @thread EMT
4714 */
4715static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
4716{
4717 Assert(eChip < RT_ELEMENTS(g_Chips));
4718 /* Configure PCI Device, assume 32-bit mode ******************************/
4719 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
4720 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
4721 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
4722 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
4723
4724 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
4725 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
4726 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS, 0x0230);
4727 /* Stepping A2 */
4728 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
4729 /* Ethernet adapter */
4730 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
4731 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
4732 /* normal single function Ethernet controller */
4733 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
4734 /* Memory Register Base Address */
4735 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
4736 /* Memory Flash Base Address */
4737 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
4738 /* IO Register Base Address */
4739 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
4740 /* Expansion ROM Base Address */
4741 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
4742 /* Capabilities Pointer */
4743 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
4744 /* Interrupt Pin: INTA# */
4745 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
4746 /* Max_Lat/Min_Gnt: very high priority and time slice */
4747 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
4748 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
4749
4750 /* PCI Power Management Registers ****************************************/
4751 /* Capability ID: PCI Power Management Registers */
4752 e1kPCICfgSetU8( pci, 0xDC, 0x01);
4753 /* Next Item Pointer: PCI-X */
4754 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
4755 /* Power Management Capabilities: PM disabled, DSI */
4756 e1kPCICfgSetU16(pci, 0xDC + 2, 0x0022);
4757 /* Power Management Control / Status Register: PM disabled */
4758 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
4759 /* PMCSR_BSE Bridge Support Extensions: Not supported */
4760 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
4761 /* Data Register: PM disabled, always 0 */
4762 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
4763
4764 /* PCI-X Configuration Registers *****************************************/
4765 /* Capability ID: PCI-X Configuration Registers */
4766 e1kPCICfgSetU8( pci, 0xE4, 0x07);
4767 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
4768 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
4769 /* PCI-X Command: Enable Relaxed Ordering */
4770 e1kPCICfgSetU16(pci, 0xE4 + 2, 0x0002);
4771 /* PCI-X Status: 32-bit, 66MHz*/
4772 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
4773}
4774
4775/**
4776 * Construct a device instance for a VM.
4777 *
4778 * @returns VBox status.
4779 * @param pDevIns The device instance data.
4780 * If the registration structure is needed, pDevIns->pDevReg points to it.
4781 * @param iInstance Instance number. Use this to figure out which registers and such to use.
4782 * The device number is also found in pDevIns->iInstance, but since it's
4783 * likely to be freqently used PDM passes it as parameter.
4784 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
4785 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
4786 * iInstance it's expected to be used a bit in this function.
4787 * @thread EMT
4788 */
4789static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
4790{
4791 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
4792 int rc;
4793
4794 /* Init handles and log related stuff. */
4795 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
4796 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
4797 pState->hTxSem = NIL_RTSEMEVENT;
4798 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
4799
4800 /*
4801 * Validate configuration.
4802 */
4803 if (!CFGMR3AreValuesValid(pCfgHandle, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0"))
4804 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4805 N_("Invalid configuration for E1000 device"));
4806
4807 /** @todo: LineSpeed unused! */
4808
4809 /* Get config params */
4810 rc = CFGMR3QueryBytes(pCfgHandle, "MAC", pState->macConfigured.au8,
4811 sizeof(pState->macConfigured.au8));
4812 if (RT_FAILURE(rc))
4813 return PDMDEV_SET_ERROR(pDevIns, rc,
4814 N_("Configuration error: Failed to get MAC address"));
4815 rc = CFGMR3QueryBool(pCfgHandle, "CableConnected", &pState->fCableConnected);
4816 if (RT_FAILURE(rc))
4817 return PDMDEV_SET_ERROR(pDevIns, rc,
4818 N_("Configuration error: Failed to get the value of 'CableConnected'"));
4819 rc = CFGMR3QueryU32(pCfgHandle, "AdapterType", (uint32_t*)&pState->eChip);
4820 if (RT_FAILURE(rc))
4821 return PDMDEV_SET_ERROR(pDevIns, rc,
4822 N_("Configuration error: Failed to get the value of 'AdapterType'"));
4823 Assert(pState->eChip <= E1K_CHIP_82545EM);
4824
4825 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
4826
4827 /* Initialize state structure */
4828 pState->fR0Enabled = true;
4829 pState->fGCEnabled = true;
4830 pState->pDevInsR3 = pDevIns;
4831 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4832 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4833 pState->u16TxPktLen = 0;
4834 pState->fIPcsum = false;
4835 pState->fTCPcsum = false;
4836 pState->fIntMaskUsed = false;
4837 pState->fDelayInts = false;
4838 pState->fLocked = false;
4839 pState->u64AckedAt = 0;
4840 pState->led.u32Magic = PDMLED_MAGIC;
4841 pState->u32PktNo = 1;
4842
4843#ifdef E1K_INT_STATS
4844 pState->uStatInt = 0;
4845 pState->uStatIntTry = 0;
4846 pState->uStatIntLower = 0;
4847 pState->uStatIntDly = 0;
4848 pState->uStatDisDly = 0;
4849 pState->iStatIntLost = 0;
4850 pState->iStatIntLostOne = 0;
4851 pState->uStatIntLate = 0;
4852 pState->uStatIntMasked = 0;
4853 pState->uStatIntEarly = 0;
4854 pState->uStatIntRx = 0;
4855 pState->uStatIntTx = 0;
4856 pState->uStatIntICS = 0;
4857 pState->uStatIntRDTR = 0;
4858 pState->uStatIntRXDMT0 = 0;
4859 pState->uStatIntTXQE = 0;
4860 pState->uStatTxNoRS = 0;
4861 pState->uStatTxIDE = 0;
4862 pState->uStatTAD = 0;
4863 pState->uStatTID = 0;
4864 pState->uStatRAD = 0;
4865 pState->uStatRID = 0;
4866 pState->uStatRxFrm = 0;
4867 pState->uStatTxFrm = 0;
4868 pState->uStatDescCtx = 0;
4869 pState->uStatDescDat = 0;
4870 pState->uStatDescLeg = 0;
4871#endif /* E1K_INT_STATS */
4872
4873 /* Interfaces */
4874 pState->IBase.pfnQueryInterface = e1kQueryInterface;
4875 pState->INetworkPort.pfnWaitReceiveAvail = e1kWaitReceiveAvail;
4876 pState->INetworkPort.pfnReceive = e1kReceive;
4877 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
4878 pState->INetworkConfig.pfnGetMac = e1kGetMac;
4879 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
4880 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
4881
4882 /* Initialize the EEPROM */
4883 pState->eeprom.init(pState->macConfigured);
4884
4885 /* Initialize internal PHY */
4886 Phy::init(&pState->phy, iInstance,
4887 pState->eChip == E1K_CHIP_82543GC?
4888 PHY_EPID_M881000 : PHY_EPID_M881011);
4889 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
4890
4891 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
4892 NULL, e1kLiveExec, NULL,
4893 e1kSavePrep, e1kSaveExec, NULL,
4894 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
4895 if (RT_FAILURE(rc))
4896 return rc;
4897
4898 /* Initialize critical section */
4899 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, pState->szInstance);
4900 if (RT_FAILURE(rc))
4901 return rc;
4902#ifndef E1K_GLOBAL_MUTEX
4903 char szTmp[sizeof(pState->szInstance) + 2];
4904 RTStrPrintf(szTmp, sizeof(szTmp), "%sRX", pState->szInstance);
4905 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, szTmp);
4906 if (RT_FAILURE(rc))
4907 return rc;
4908#endif
4909
4910 /* Set PCI config registers */
4911 e1kConfigurePCI(pState->pciDevice, pState->eChip);
4912 /* Register PCI device */
4913 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
4914 if (RT_FAILURE(rc))
4915 return rc;
4916
4917 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
4918 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
4919 PCI_ADDRESS_SPACE_MEM, e1kMap);
4920 if (RT_FAILURE(rc))
4921 return rc;
4922 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
4923 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
4924 PCI_ADDRESS_SPACE_IO, e1kMap);
4925 if (RT_FAILURE(rc))
4926 return rc;
4927
4928 /* Create transmit queue */
4929 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4930 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3);
4931 if (RT_FAILURE(rc))
4932 return rc;
4933 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
4934 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
4935
4936 /* Create the RX notifier signaller. */
4937 rc = PDMDevHlpPDMQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
4938 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3);
4939 if (RT_FAILURE(rc))
4940 return rc;
4941 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
4942 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
4943
4944#ifdef E1K_USE_TX_TIMERS
4945 /* Create Transmit Interrupt Delay Timer */
4946 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pState,
4947 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4948 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
4949 if (RT_FAILURE(rc))
4950 return rc;
4951 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
4952 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
4953
4954# ifndef E1K_NO_TAD
4955 /* Create Transmit Absolute Delay Timer */
4956 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pState,
4957 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4958 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
4959 if (RT_FAILURE(rc))
4960 return rc;
4961 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
4962 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
4963# endif /* E1K_NO_TAD */
4964#endif /* E1K_USE_TX_TIMERS */
4965
4966#ifdef E1K_USE_RX_TIMERS
4967 /* Create Receive Interrupt Delay Timer */
4968 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pState,
4969 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4970 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
4971 if (RT_FAILURE(rc))
4972 return rc;
4973 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
4974 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
4975
4976 /* Create Receive Absolute Delay Timer */
4977 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pState,
4978 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4979 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
4980 if (RT_FAILURE(rc))
4981 return rc;
4982 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
4983 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
4984#endif /* E1K_USE_RX_TIMERS */
4985
4986 /* Create Late Interrupt Timer */
4987 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pState,
4988 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4989 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
4990 if (RT_FAILURE(rc))
4991 return rc;
4992 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
4993 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
4994
4995 /* Create Link Up Timer */
4996 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pState,
4997 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
4998 "E1000 Link Up Timer", &pState->pLUTimer);
4999 if (RT_FAILURE(rc))
5000 return rc;
5001
5002 /* Status driver */
5003 PPDMIBASE pBase;
5004 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
5005 if (RT_FAILURE(rc))
5006 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
5007 pState->pLedsConnector = (PPDMILEDCONNECTORS)pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
5008
5009 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5010 if (RT_SUCCESS(rc))
5011 {
5012 if (rc == VINF_NAT_DNS)
5013 {
5014 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5015 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5016 }
5017 pState->pDrv = (PPDMINETWORKCONNECTOR)
5018 pState->pDrvBase->pfnQueryInterface(pState->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
5019 if (!pState->pDrv)
5020 {
5021 AssertMsgFailed(("%s Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
5022 return VERR_PDM_MISSING_INTERFACE_BELOW;
5023 }
5024 }
5025 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5026 {
5027 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
5028 }
5029 else
5030 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
5031
5032 rc = RTSemEventCreate(&pState->hTxSem);
5033 if (RT_FAILURE(rc))
5034 return rc;
5035 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
5036 if (RT_FAILURE(rc))
5037 return rc;
5038
5039 e1kHardReset(pState);
5040
5041 rc = PDMDevHlpPDMThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");
5042 if (RT_FAILURE(rc))
5043 return rc;
5044
5045#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5046 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/E1k%d/MMIO/ReadGC", iInstance);
5047 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/E1k%d/MMIO/ReadHC", iInstance);
5048 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/E1k%d/MMIO/WriteGC", iInstance);
5049 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/E1k%d/MMIO/WriteHC", iInstance);
5050 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
5051 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
5052 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/E1k%d/IO/ReadGC", iInstance);
5053 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/E1k%d/IO/ReadHC", iInstance);
5054 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/E1k%d/IO/WriteGC", iInstance);
5055 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/E1k%d/IO/WriteHC", iInstance);
5056 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
5057 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
5058 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
5059 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
5060 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
5061 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
5062 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
5063 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
5064 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
5065#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5066 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
5067#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5068 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/E1k%d/Transmit/Total", iInstance);
5069#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5070 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
5071#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5072 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in HC", "/Devices/E1k%d/Transmit/Send", iInstance);
5073
5074 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
5075 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
5076 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
5077 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
5078#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5079
5080 return VINF_SUCCESS;
5081}
5082
5083/**
5084 * Destruct a device instance.
5085 *
5086 * We need to free non-VM resources only.
5087 *
5088 * @returns VBox status.
5089 * @param pDevIns The device instance data.
5090 * @thread EMT
5091 */
5092static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
5093{
5094 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5095
5096 e1kDumpState(pState);
5097 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
5098 if (PDMCritSectIsInitialized(&pState->cs))
5099 {
5100 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
5101 {
5102 RTSemEventSignal(pState->hEventMoreRxDescAvail);
5103 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
5104 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5105 }
5106 if (pState->hTxSem != NIL_RTSEMEVENT)
5107 {
5108 RTSemEventDestroy(pState->hTxSem);
5109 pState->hTxSem = NIL_RTSEMEVENT;
5110 }
5111#ifndef E1K_GLOBAL_MUTEX
5112 PDMR3CritSectDelete(&pState->csRx);
5113 //PDMR3CritSectDelete(&pState->csTx);
5114#endif
5115 PDMR3CritSectDelete(&pState->cs);
5116 }
5117 return VINF_SUCCESS;
5118}
5119
5120/**
5121 * Device relocation callback.
5122 *
5123 * When this callback is called the device instance data, and if the
5124 * device have a GC component, is being relocated, or/and the selectors
5125 * have been changed. The device must use the chance to perform the
5126 * necessary pointer relocations and data updates.
5127 *
5128 * Before the GC code is executed the first time, this function will be
5129 * called with a 0 delta so GC pointer calculations can be one in one place.
5130 *
5131 * @param pDevIns Pointer to the device instance.
5132 * @param offDelta The relocation delta relative to the old location.
5133 *
5134 * @remark A relocation CANNOT fail.
5135 */
5136static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5137{
5138 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5139 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5140 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5141 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5142#ifdef E1K_USE_RX_TIMERS
5143 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5144 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5145#endif /* E1K_USE_RX_TIMERS */
5146#ifdef E1K_USE_TX_TIMERS
5147 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5148# ifndef E1K_NO_TAD
5149 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5150# endif /* E1K_NO_TAD */
5151#endif /* E1K_USE_TX_TIMERS */
5152 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5153}
5154
5155/**
5156 * @copydoc FNPDMDEVSUSPEND
5157 */
5158static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
5159{
5160 /* Poke thread waiting for buffer space. */
5161 e1kWakeupReceive(pDevIns);
5162}
5163
5164
5165#ifdef VBOX_DYNAMIC_NET_ATTACH
5166/**
5167 * Detach notification.
5168 *
5169 * One port on the network card has been disconnected from the network.
5170 *
5171 * @param pDevIns The device instance.
5172 * @param iLUN The logical unit which is being detached.
5173 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5174 */
5175static DECLCALLBACK(void) e1kDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5176{
5177 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5178 Log(("%s e1kDetach:\n", INSTANCE(pState)));
5179
5180 AssertLogRelReturnVoid(iLUN == 0);
5181
5182 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5183
5184 /** @todo: r=pritesh still need to check if i missed
5185 * to clean something in this function
5186 */
5187
5188 /*
5189 * Zero some important members.
5190 */
5191 pState->pDrvBase = NULL;
5192 pState->pDrv = NULL;
5193
5194 PDMCritSectLeave(&pState->cs);
5195}
5196
5197
5198/**
5199 * Attach the Network attachment.
5200 *
5201 * One port on the network card has been connected to a network.
5202 *
5203 * @returns VBox status code.
5204 * @param pDevIns The device instance.
5205 * @param iLUN The logical unit which is being attached.
5206 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5207 *
5208 * @remarks This code path is not used during construction.
5209 */
5210static DECLCALLBACK(int) e1kAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5211{
5212 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5213 LogFlow(("%s e1kAttach:\n", INSTANCE(pState)));
5214
5215 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
5216
5217 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5218
5219 /*
5220 * Attach the driver.
5221 */
5222 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5223 if (RT_SUCCESS(rc))
5224 {
5225 if (rc == VINF_NAT_DNS)
5226 {
5227#ifdef RT_OS_LINUX
5228 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5229 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5230#else
5231 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5232 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5233#endif
5234 }
5235 pState->pDrv = (PPDMINETWORKCONNECTOR)pState->pDrvBase->pfnQueryInterface(pState->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
5236 if (!pState->pDrv)
5237 {
5238 AssertMsgFailed(("Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
5239 rc = VERR_PDM_MISSING_INTERFACE_BELOW;
5240 }
5241 }
5242 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5243 Log(("%s No attached driver!\n", INSTANCE(pState)));
5244
5245
5246 /*
5247 * Temporary set the link down if it was up so that the guest
5248 * will know that we have change the configuration of the
5249 * network card
5250 */
5251 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
5252 {
5253 STATUS &= ~STATUS_LU;
5254 Phy::setLinkStatus(&pState->phy, false);
5255 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5256 /* Restore the link back in 5 second. */
5257 e1kArmTimer(pState, pState->pLUTimer, 5000000);
5258 }
5259
5260 PDMCritSectLeave(&pState->cs);
5261 return rc;
5262
5263}
5264#endif /* VBOX_DYNAMIC_NET_ATTACH */
5265
5266
5267/**
5268 * @copydoc FNPDMDEVPOWEROFF
5269 */
5270static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
5271{
5272 /* Poke thread waiting for buffer space. */
5273 e1kWakeupReceive(pDevIns);
5274}
5275
5276/**
5277 * The device registration structure.
5278 */
5279const PDMDEVREG g_DeviceE1000 =
5280{
5281 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
5282 PDM_DEVREG_VERSION,
5283 /* Device name. */
5284 "e1000",
5285 /* Name of guest context module (no path).
5286 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5287 "VBoxDDGC.gc",
5288 /* Name of ring-0 module (no path).
5289 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5290 "VBoxDDR0.r0",
5291 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
5292 * remain unchanged from registration till VM destruction. */
5293 "Intel PRO/1000 MT Desktop Ethernet.\n",
5294
5295 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
5296 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5297 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
5298 PDM_DEVREG_CLASS_NETWORK,
5299 /* Maximum number of instances (per VM). */
5300 8,
5301 /* Size of the instance data. */
5302 sizeof(E1KSTATE),
5303
5304 /* Construct instance - required. */
5305 e1kConstruct,
5306 /* Destruct instance - optional. */
5307 e1kDestruct,
5308 /* Relocation command - optional. */
5309 e1kRelocate,
5310 /* I/O Control interface - optional. */
5311 NULL,
5312 /* Power on notification - optional. */
5313 NULL,
5314 /* Reset notification - optional. */
5315 NULL,
5316 /* Suspend notification - optional. */
5317 e1kSuspend,
5318 /* Resume notification - optional. */
5319 NULL,
5320#ifdef VBOX_DYNAMIC_NET_ATTACH
5321 /* Attach command - optional. */
5322 e1kAttach,
5323 /* Detach notification - optional. */
5324 e1kDetach,
5325#else /* !VBOX_DYNAMIC_NET_ATTACH */
5326 /* Attach command - optional. */
5327 NULL,
5328 /* Detach notification - optional. */
5329 NULL,
5330#endif /* !VBOX_DYNAMIC_NET_ATTACH */
5331 /* Query a LUN base interface - optional. */
5332 NULL,
5333 /* Init complete notification - optional. */
5334 NULL,
5335 /* Power off notification - optional. */
5336 e1kPowerOff,
5337 /* pfnSoftReset */
5338 NULL,
5339 /* u32VersionEnd */
5340 PDM_DEVREG_VERSION
5341};
5342
5343#endif /* IN_RING3 */
5344#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5345
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette