VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 28328

Last change on this file since 28328 was 28328, checked in by vboxsync, 15 years ago

Network/D*: Moving XMIT threads, part 2.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 228.0 KB
Line 
1/* $Id: DevE1000.cpp 28328 2010-04-14 20:46:56Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo VLAN checksum offloading support
14 * @todo Flexible Filter / Wakeup (optional?)
15 */
16
17/*
18 * Copyright (C) 2007-2010 Sun Microsystems, Inc.
19 *
20 * This file is part of VirtualBox Open Source Edition (OSE), as
21 * available from http://www.virtualbox.org. This file is free software;
22 * you can redistribute it and/or modify it under the terms of the GNU
23 * General Public License (GPL) as published by the Free Software
24 * Foundation, in version 2 as it comes in the "COPYING" file of the
25 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27 *
28 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
29 * Clara, CA 95054 USA or visit http://www.sun.com if you need
30 * additional information or have any questions.
31 */
32
33#define LOG_GROUP LOG_GROUP_DEV_E1000
34
35//#define E1kLogRel(a) LogRel(a)
36#define E1kLogRel(a)
37
38/* Options */
39#define E1K_INIT_RA0
40#define E1K_LSC_ON_SLU
41#define E1K_ITR_ENABLED
42//#define E1K_GLOBAL_MUTEX
43//#define E1K_USE_TX_TIMERS
44//#define E1K_NO_TAD
45//#define E1K_REL_DEBUG
46//#define E1K_INT_STATS
47//#define E1K_REL_STATS
48//#define E1K_USE_SUPLIB_SEMEVENT
49
50#include <iprt/crc32.h>
51#include <iprt/ctype.h>
52#include <iprt/net.h>
53#include <iprt/semaphore.h>
54#include <iprt/string.h>
55#include <iprt/uuid.h>
56#include <VBox/pdmdev.h>
57#include <VBox/pdmnetifs.h>
58#include <VBox/pdmnetinline.h>
59#include <VBox/param.h>
60#include <VBox/tm.h>
61#include <VBox/vm.h>
62#include "../Builtins.h"
63
64#include "DevEEPROM.h"
65#include "DevE1000Phy.h"
66
67/* Little helpers ************************************************************/
68#undef htons
69#undef ntohs
70#undef htonl
71#undef ntohl
72#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
73#define ntohs(x) htons(x)
74#define htonl(x) ASMByteSwapU32(x)
75#define ntohl(x) htonl(x)
76
77#ifndef DEBUG
78# ifdef E1K_REL_STATS
79# undef STAM_COUNTER_INC
80# undef STAM_PROFILE_ADV_START
81# undef STAM_PROFILE_ADV_STOP
82# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
83# define STAM_PROFILE_ADV_START STAM_REL_PROFILE_ADV_START
84# define STAM_PROFILE_ADV_STOP STAM_REL_PROFILE_ADV_STOP
85# endif
86# ifdef E1K_REL_DEBUG
87# define DEBUG
88# define E1kLog(a) LogRel(a)
89# define E1kLog2(a) LogRel(a)
90# define E1kLog3(a) LogRel(a)
91//# define E1kLog3(a) do {} while (0)
92# else
93# define E1kLog(a) do {} while (0)
94# define E1kLog2(a) do {} while (0)
95# define E1kLog3(a) do {} while (0)
96# endif
97#else
98# define E1kLog(a) Log(a)
99# define E1kLog2(a) Log2(a)
100# define E1kLog3(a) Log3(a)
101//# define E1kLog(a) do {} while (0)
102//# define E1kLog2(a) do {} while (0)
103//# define E1kLog3(a) do {} while (0)
104#endif
105
106//#undef DEBUG
107
108#define INSTANCE(pState) pState->szInstance
109#define STATE_TO_DEVINS(pState) (((E1KSTATE *)pState)->CTX_SUFF(pDevIns))
110#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
111
112#define E1K_INC_CNT32(cnt) \
113do { \
114 if (cnt < UINT32_MAX) \
115 cnt++; \
116} while (0)
117
118#define E1K_ADD_CNT64(cntLo, cntHi, val) \
119do { \
120 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
121 uint64_t tmp = u64Cnt; \
122 u64Cnt += val; \
123 if (tmp > u64Cnt ) \
124 u64Cnt = UINT64_MAX; \
125 cntLo = (uint32_t)u64Cnt; \
126 cntHi = (uint32_t)(u64Cnt >> 32); \
127} while (0)
128
129#ifdef E1K_INT_STATS
130# define E1K_INC_ISTAT_CNT(cnt) ++cnt
131#else /* E1K_INT_STATS */
132# define E1K_INC_ISTAT_CNT(cnt)
133#endif /* E1K_INT_STATS */
134
135
136/*****************************************************************************/
137
138typedef uint32_t E1KCHIP;
139#define E1K_CHIP_82540EM 0
140#define E1K_CHIP_82543GC 1
141#define E1K_CHIP_82545EM 2
142
143struct E1kChips
144{
145 uint16_t uPCIVendorId;
146 uint16_t uPCIDeviceId;
147 uint16_t uPCISubsystemVendorId;
148 uint16_t uPCISubsystemId;
149 const char *pcszName;
150} g_Chips[] =
151{
152 /* Vendor Device SSVendor SubSys Name */
153 { 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
154 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
155 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
156};
157
158
159/* The size of register area mapped to I/O space */
160#define E1K_IOPORT_SIZE 0x8
161/* The size of memory-mapped register area */
162#define E1K_MM_SIZE 0x20000
163
164#define E1K_MAX_TX_PKT_SIZE 16288
165#define E1K_MAX_RX_PKT_SIZE 16384
166
167/*****************************************************************************/
168
169/** Gets the specfieid bits from the register. */
170#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
171#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
172#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
173#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
174#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
175
176#define CTRL_SLU 0x00000040
177#define CTRL_MDIO 0x00100000
178#define CTRL_MDC 0x00200000
179#define CTRL_MDIO_DIR 0x01000000
180#define CTRL_MDC_DIR 0x02000000
181#define CTRL_RESET 0x04000000
182#define CTRL_VME 0x40000000
183
184#define STATUS_LU 0x00000002
185
186#define EECD_EE_WIRES 0x0F
187#define EECD_EE_REQ 0x40
188#define EECD_EE_GNT 0x80
189
190#define EERD_START 0x00000001
191#define EERD_DONE 0x00000010
192#define EERD_DATA_MASK 0xFFFF0000
193#define EERD_DATA_SHIFT 16
194#define EERD_ADDR_MASK 0x0000FF00
195#define EERD_ADDR_SHIFT 8
196
197#define MDIC_DATA_MASK 0x0000FFFF
198#define MDIC_DATA_SHIFT 0
199#define MDIC_REG_MASK 0x001F0000
200#define MDIC_REG_SHIFT 16
201#define MDIC_PHY_MASK 0x03E00000
202#define MDIC_PHY_SHIFT 21
203#define MDIC_OP_WRITE 0x04000000
204#define MDIC_OP_READ 0x08000000
205#define MDIC_READY 0x10000000
206#define MDIC_INT_EN 0x20000000
207#define MDIC_ERROR 0x40000000
208
209#define TCTL_EN 0x00000002
210#define TCTL_PSP 0x00000008
211
212#define RCTL_EN 0x00000002
213#define RCTL_UPE 0x00000008
214#define RCTL_MPE 0x00000010
215#define RCTL_LPE 0x00000020
216#define RCTL_LBM_MASK 0x000000C0
217#define RCTL_LBM_SHIFT 6
218#define RCTL_RDMTS_MASK 0x00000300
219#define RCTL_RDMTS_SHIFT 8
220#define RCTL_LBM_TCVR 3 /**< PHY or external SerDes loopback. */
221#define RCTL_MO_MASK 0x00003000
222#define RCTL_MO_SHIFT 12
223#define RCTL_BAM 0x00008000
224#define RCTL_BSIZE_MASK 0x00030000
225#define RCTL_BSIZE_SHIFT 16
226#define RCTL_VFE 0x00040000
227#define RCTL_BSEX 0x02000000
228#define RCTL_SECRC 0x04000000
229
230#define ICR_TXDW 0x00000001
231#define ICR_TXQE 0x00000002
232#define ICR_LSC 0x00000004
233#define ICR_RXDMT0 0x00000010
234#define ICR_RXT0 0x00000080
235#define ICR_TXD_LOW 0x00008000
236#define RDTR_FPD 0x80000000
237
238#define PBA_st ((PBAST*)(pState->auRegs + PBA_IDX))
239typedef struct
240{
241 unsigned rxa : 7;
242 unsigned rxa_r : 9;
243 unsigned txa : 16;
244} PBAST;
245AssertCompileSize(PBAST, 4);
246
247#define TXDCTL_WTHRESH_MASK 0x003F0000
248#define TXDCTL_WTHRESH_SHIFT 16
249#define TXDCTL_LWTHRESH_MASK 0xFE000000
250#define TXDCTL_LWTHRESH_SHIFT 25
251
252#define RXCSUM_PCSS_MASK 0x000000FF
253#define RXCSUM_PCSS_SHIFT 0
254
255/* Register access macros ****************************************************/
256#define CTRL pState->auRegs[CTRL_IDX]
257#define STATUS pState->auRegs[STATUS_IDX]
258#define EECD pState->auRegs[EECD_IDX]
259#define EERD pState->auRegs[EERD_IDX]
260#define CTRL_EXT pState->auRegs[CTRL_EXT_IDX]
261#define FLA pState->auRegs[FLA_IDX]
262#define MDIC pState->auRegs[MDIC_IDX]
263#define FCAL pState->auRegs[FCAL_IDX]
264#define FCAH pState->auRegs[FCAH_IDX]
265#define FCT pState->auRegs[FCT_IDX]
266#define VET pState->auRegs[VET_IDX]
267#define ICR pState->auRegs[ICR_IDX]
268#define ITR pState->auRegs[ITR_IDX]
269#define ICS pState->auRegs[ICS_IDX]
270#define IMS pState->auRegs[IMS_IDX]
271#define IMC pState->auRegs[IMC_IDX]
272#define RCTL pState->auRegs[RCTL_IDX]
273#define FCTTV pState->auRegs[FCTTV_IDX]
274#define TXCW pState->auRegs[TXCW_IDX]
275#define RXCW pState->auRegs[RXCW_IDX]
276#define TCTL pState->auRegs[TCTL_IDX]
277#define TIPG pState->auRegs[TIPG_IDX]
278#define AIFS pState->auRegs[AIFS_IDX]
279#define LEDCTL pState->auRegs[LEDCTL_IDX]
280#define PBA pState->auRegs[PBA_IDX]
281#define FCRTL pState->auRegs[FCRTL_IDX]
282#define FCRTH pState->auRegs[FCRTH_IDX]
283#define RDFH pState->auRegs[RDFH_IDX]
284#define RDFT pState->auRegs[RDFT_IDX]
285#define RDFHS pState->auRegs[RDFHS_IDX]
286#define RDFTS pState->auRegs[RDFTS_IDX]
287#define RDFPC pState->auRegs[RDFPC_IDX]
288#define RDBAL pState->auRegs[RDBAL_IDX]
289#define RDBAH pState->auRegs[RDBAH_IDX]
290#define RDLEN pState->auRegs[RDLEN_IDX]
291#define RDH pState->auRegs[RDH_IDX]
292#define RDT pState->auRegs[RDT_IDX]
293#define RDTR pState->auRegs[RDTR_IDX]
294#define RXDCTL pState->auRegs[RXDCTL_IDX]
295#define RADV pState->auRegs[RADV_IDX]
296#define RSRPD pState->auRegs[RSRPD_IDX]
297#define TXDMAC pState->auRegs[TXDMAC_IDX]
298#define TDFH pState->auRegs[TDFH_IDX]
299#define TDFT pState->auRegs[TDFT_IDX]
300#define TDFHS pState->auRegs[TDFHS_IDX]
301#define TDFTS pState->auRegs[TDFTS_IDX]
302#define TDFPC pState->auRegs[TDFPC_IDX]
303#define TDBAL pState->auRegs[TDBAL_IDX]
304#define TDBAH pState->auRegs[TDBAH_IDX]
305#define TDLEN pState->auRegs[TDLEN_IDX]
306#define TDH pState->auRegs[TDH_IDX]
307#define TDT pState->auRegs[TDT_IDX]
308#define TIDV pState->auRegs[TIDV_IDX]
309#define TXDCTL pState->auRegs[TXDCTL_IDX]
310#define TADV pState->auRegs[TADV_IDX]
311#define TSPMT pState->auRegs[TSPMT_IDX]
312#define CRCERRS pState->auRegs[CRCERRS_IDX]
313#define ALGNERRC pState->auRegs[ALGNERRC_IDX]
314#define SYMERRS pState->auRegs[SYMERRS_IDX]
315#define RXERRC pState->auRegs[RXERRC_IDX]
316#define MPC pState->auRegs[MPC_IDX]
317#define SCC pState->auRegs[SCC_IDX]
318#define ECOL pState->auRegs[ECOL_IDX]
319#define MCC pState->auRegs[MCC_IDX]
320#define LATECOL pState->auRegs[LATECOL_IDX]
321#define COLC pState->auRegs[COLC_IDX]
322#define DC pState->auRegs[DC_IDX]
323#define TNCRS pState->auRegs[TNCRS_IDX]
324#define SEC pState->auRegs[SEC_IDX]
325#define CEXTERR pState->auRegs[CEXTERR_IDX]
326#define RLEC pState->auRegs[RLEC_IDX]
327#define XONRXC pState->auRegs[XONRXC_IDX]
328#define XONTXC pState->auRegs[XONTXC_IDX]
329#define XOFFRXC pState->auRegs[XOFFRXC_IDX]
330#define XOFFTXC pState->auRegs[XOFFTXC_IDX]
331#define FCRUC pState->auRegs[FCRUC_IDX]
332#define PRC64 pState->auRegs[PRC64_IDX]
333#define PRC127 pState->auRegs[PRC127_IDX]
334#define PRC255 pState->auRegs[PRC255_IDX]
335#define PRC511 pState->auRegs[PRC511_IDX]
336#define PRC1023 pState->auRegs[PRC1023_IDX]
337#define PRC1522 pState->auRegs[PRC1522_IDX]
338#define GPRC pState->auRegs[GPRC_IDX]
339#define BPRC pState->auRegs[BPRC_IDX]
340#define MPRC pState->auRegs[MPRC_IDX]
341#define GPTC pState->auRegs[GPTC_IDX]
342#define GORCL pState->auRegs[GORCL_IDX]
343#define GORCH pState->auRegs[GORCH_IDX]
344#define GOTCL pState->auRegs[GOTCL_IDX]
345#define GOTCH pState->auRegs[GOTCH_IDX]
346#define RNBC pState->auRegs[RNBC_IDX]
347#define RUC pState->auRegs[RUC_IDX]
348#define RFC pState->auRegs[RFC_IDX]
349#define ROC pState->auRegs[ROC_IDX]
350#define RJC pState->auRegs[RJC_IDX]
351#define MGTPRC pState->auRegs[MGTPRC_IDX]
352#define MGTPDC pState->auRegs[MGTPDC_IDX]
353#define MGTPTC pState->auRegs[MGTPTC_IDX]
354#define TORL pState->auRegs[TORL_IDX]
355#define TORH pState->auRegs[TORH_IDX]
356#define TOTL pState->auRegs[TOTL_IDX]
357#define TOTH pState->auRegs[TOTH_IDX]
358#define TPR pState->auRegs[TPR_IDX]
359#define TPT pState->auRegs[TPT_IDX]
360#define PTC64 pState->auRegs[PTC64_IDX]
361#define PTC127 pState->auRegs[PTC127_IDX]
362#define PTC255 pState->auRegs[PTC255_IDX]
363#define PTC511 pState->auRegs[PTC511_IDX]
364#define PTC1023 pState->auRegs[PTC1023_IDX]
365#define PTC1522 pState->auRegs[PTC1522_IDX]
366#define MPTC pState->auRegs[MPTC_IDX]
367#define BPTC pState->auRegs[BPTC_IDX]
368#define TSCTC pState->auRegs[TSCTC_IDX]
369#define TSCTFC pState->auRegs[TSCTFC_IDX]
370#define RXCSUM pState->auRegs[RXCSUM_IDX]
371#define WUC pState->auRegs[WUC_IDX]
372#define WUFC pState->auRegs[WUFC_IDX]
373#define WUS pState->auRegs[WUS_IDX]
374#define MANC pState->auRegs[MANC_IDX]
375#define IPAV pState->auRegs[IPAV_IDX]
376#define WUPL pState->auRegs[WUPL_IDX]
377
378/**
379 * Indices of memory-mapped registers in register table
380 */
381typedef enum
382{
383 CTRL_IDX,
384 STATUS_IDX,
385 EECD_IDX,
386 EERD_IDX,
387 CTRL_EXT_IDX,
388 FLA_IDX,
389 MDIC_IDX,
390 FCAL_IDX,
391 FCAH_IDX,
392 FCT_IDX,
393 VET_IDX,
394 ICR_IDX,
395 ITR_IDX,
396 ICS_IDX,
397 IMS_IDX,
398 IMC_IDX,
399 RCTL_IDX,
400 FCTTV_IDX,
401 TXCW_IDX,
402 RXCW_IDX,
403 TCTL_IDX,
404 TIPG_IDX,
405 AIFS_IDX,
406 LEDCTL_IDX,
407 PBA_IDX,
408 FCRTL_IDX,
409 FCRTH_IDX,
410 RDFH_IDX,
411 RDFT_IDX,
412 RDFHS_IDX,
413 RDFTS_IDX,
414 RDFPC_IDX,
415 RDBAL_IDX,
416 RDBAH_IDX,
417 RDLEN_IDX,
418 RDH_IDX,
419 RDT_IDX,
420 RDTR_IDX,
421 RXDCTL_IDX,
422 RADV_IDX,
423 RSRPD_IDX,
424 TXDMAC_IDX,
425 TDFH_IDX,
426 TDFT_IDX,
427 TDFHS_IDX,
428 TDFTS_IDX,
429 TDFPC_IDX,
430 TDBAL_IDX,
431 TDBAH_IDX,
432 TDLEN_IDX,
433 TDH_IDX,
434 TDT_IDX,
435 TIDV_IDX,
436 TXDCTL_IDX,
437 TADV_IDX,
438 TSPMT_IDX,
439 CRCERRS_IDX,
440 ALGNERRC_IDX,
441 SYMERRS_IDX,
442 RXERRC_IDX,
443 MPC_IDX,
444 SCC_IDX,
445 ECOL_IDX,
446 MCC_IDX,
447 LATECOL_IDX,
448 COLC_IDX,
449 DC_IDX,
450 TNCRS_IDX,
451 SEC_IDX,
452 CEXTERR_IDX,
453 RLEC_IDX,
454 XONRXC_IDX,
455 XONTXC_IDX,
456 XOFFRXC_IDX,
457 XOFFTXC_IDX,
458 FCRUC_IDX,
459 PRC64_IDX,
460 PRC127_IDX,
461 PRC255_IDX,
462 PRC511_IDX,
463 PRC1023_IDX,
464 PRC1522_IDX,
465 GPRC_IDX,
466 BPRC_IDX,
467 MPRC_IDX,
468 GPTC_IDX,
469 GORCL_IDX,
470 GORCH_IDX,
471 GOTCL_IDX,
472 GOTCH_IDX,
473 RNBC_IDX,
474 RUC_IDX,
475 RFC_IDX,
476 ROC_IDX,
477 RJC_IDX,
478 MGTPRC_IDX,
479 MGTPDC_IDX,
480 MGTPTC_IDX,
481 TORL_IDX,
482 TORH_IDX,
483 TOTL_IDX,
484 TOTH_IDX,
485 TPR_IDX,
486 TPT_IDX,
487 PTC64_IDX,
488 PTC127_IDX,
489 PTC255_IDX,
490 PTC511_IDX,
491 PTC1023_IDX,
492 PTC1522_IDX,
493 MPTC_IDX,
494 BPTC_IDX,
495 TSCTC_IDX,
496 TSCTFC_IDX,
497 RXCSUM_IDX,
498 WUC_IDX,
499 WUFC_IDX,
500 WUS_IDX,
501 MANC_IDX,
502 IPAV_IDX,
503 WUPL_IDX,
504 MTA_IDX,
505 RA_IDX,
506 VFTA_IDX,
507 IP4AT_IDX,
508 IP6AT_IDX,
509 WUPM_IDX,
510 FFLT_IDX,
511 FFMT_IDX,
512 FFVT_IDX,
513 PBM_IDX,
514 RA_82542_IDX,
515 MTA_82542_IDX,
516 VFTA_82542_IDX,
517 E1K_NUM_OF_REGS
518} E1kRegIndex;
519
520#define E1K_NUM_OF_32BIT_REGS MTA_IDX
521
522
523/**
524 * Define E1000-specific EEPROM layout.
525 */
526class E1kEEPROM
527{
528 public:
529 EEPROM93C46 eeprom;
530
531#ifdef IN_RING3
532 /**
533 * Initialize EEPROM content.
534 *
535 * @param macAddr MAC address of E1000.
536 */
537 void init(RTMAC &macAddr)
538 {
539 eeprom.init();
540 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
541 eeprom.m_au16Data[0x04] = 0xFFFF;
542 /*
543 * bit 3 - full support for power management
544 * bit 10 - full duplex
545 */
546 eeprom.m_au16Data[0x0A] = 0x4408;
547 eeprom.m_au16Data[0x0B] = 0x001E;
548 eeprom.m_au16Data[0x0C] = 0x8086;
549 eeprom.m_au16Data[0x0D] = 0x100E;
550 eeprom.m_au16Data[0x0E] = 0x8086;
551 eeprom.m_au16Data[0x0F] = 0x3040;
552 eeprom.m_au16Data[0x21] = 0x7061;
553 eeprom.m_au16Data[0x22] = 0x280C;
554 eeprom.m_au16Data[0x23] = 0x00C8;
555 eeprom.m_au16Data[0x24] = 0x00C8;
556 eeprom.m_au16Data[0x2F] = 0x0602;
557 updateChecksum();
558 };
559
560 /**
561 * Compute the checksum as required by E1000 and store it
562 * in the last word.
563 */
564 void updateChecksum()
565 {
566 uint16_t u16Checksum = 0;
567
568 for (int i = 0; i < eeprom.SIZE-1; i++)
569 u16Checksum += eeprom.m_au16Data[i];
570 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
571 };
572
573 /**
574 * First 6 bytes of EEPROM contain MAC address.
575 *
576 * @returns MAC address of E1000.
577 */
578 void getMac(PRTMAC pMac)
579 {
580 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
581 };
582
583 uint32_t read()
584 {
585 return eeprom.read();
586 }
587
588 void write(uint32_t u32Wires)
589 {
590 eeprom.write(u32Wires);
591 }
592
593 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
594 {
595 return eeprom.readWord(u32Addr, pu16Value);
596 }
597
598 int load(PSSMHANDLE pSSM)
599 {
600 return eeprom.load(pSSM);
601 }
602
603 void save(PSSMHANDLE pSSM)
604 {
605 eeprom.save(pSSM);
606 }
607#endif /* IN_RING3 */
608};
609
610
611struct E1kRxDStatus
612{
613 /** @name Descriptor Status field (3.2.3.1)
614 * @{ */
615 unsigned fDD : 1; /**< Descriptor Done. */
616 unsigned fEOP : 1; /**< End of packet. */
617 unsigned fIXSM : 1; /**< Ignore checksum indication. */
618 unsigned fVP : 1; /**< VLAN, matches VET. */
619 unsigned : 1;
620 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
621 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
622 unsigned fPIF : 1; /**< Passed in-exact filter */
623 /** @} */
624 /** @name Descriptor Errors field (3.2.3.2)
625 * (Only valid when fEOP and fDD are set.)
626 * @{ */
627 unsigned fCE : 1; /**< CRC or alignment error. */
628 unsigned : 4; /**< Reserved, varies with different models... */
629 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
630 unsigned fIPE : 1; /**< IP Checksum error. */
631 unsigned fRXE : 1; /**< RX Data error. */
632 /** @} */
633 /** @name Descriptor Special field (3.2.3.3)
634 * @{ */
635 unsigned u12VLAN : 12; /**< VLAN identifier. */
636 unsigned fCFI : 1; /**< Canonical form indicator (VLAN). */
637 unsigned u3PRI : 3; /**< User priority (VLAN). */
638 /** @} */
639};
640typedef struct E1kRxDStatus E1KRXDST;
641
642struct E1kRxDesc_st
643{
644 uint64_t u64BufAddr; /**< Address of data buffer */
645 uint16_t u16Length; /**< Length of data in buffer */
646 uint16_t u16Checksum; /**< Packet checksum */
647 E1KRXDST status;
648};
649typedef struct E1kRxDesc_st E1KRXDESC;
650AssertCompileSize(E1KRXDESC, 16);
651
652#define E1K_DTYP_LEGACY -1
653#define E1K_DTYP_CONTEXT 0
654#define E1K_DTYP_DATA 1
655
656struct E1kTDLegacy
657{
658 uint64_t u64BufAddr; /**< Address of data buffer */
659 struct TDLCmd_st
660 {
661 unsigned u16Length : 16;
662 unsigned u8CSO : 8;
663 /* CMD field : 8 */
664 unsigned fEOP : 1;
665 unsigned fIFCS : 1;
666 unsigned fIC : 1;
667 unsigned fRS : 1;
668 unsigned fRSV : 1;
669 unsigned fDEXT : 1;
670 unsigned fVLE : 1;
671 unsigned fIDE : 1;
672 } cmd;
673 struct TDLDw3_st
674 {
675 /* STA field */
676 unsigned fDD : 1;
677 unsigned fEC : 1;
678 unsigned fLC : 1;
679 unsigned fTURSV : 1;
680 /* RSV field */
681 unsigned u4RSV : 4;
682 /* CSS field */
683 unsigned u8CSS : 8;
684 /* Special field*/
685 unsigned u12VLAN : 12;
686 unsigned fCFI : 1;
687 unsigned u3PRI : 3;
688 } dw3;
689};
690
691/**
692 * TCP/IP Context Transmit Descriptor, section 3.3.6.
693 */
694struct E1kTDContext
695{
696 struct CheckSum_st
697 {
698 /** TSE: Header start. !TSE: Checksum start. */
699 unsigned u8CSS : 8;
700 /** Checksum offset - where to store it. */
701 unsigned u8CSO : 8;
702 /** Checksum ending (inclusive) offset, 0 = end of packet. */
703 unsigned u16CSE : 16;
704 } ip;
705 struct CheckSum_st tu;
706 struct TDCDw2_st
707 {
708 /** TSE: The total number of payload bytes for this context. Sans header. */
709 unsigned u20PAYLEN : 20;
710 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
711 unsigned u4DTYP : 4;
712 /** TUCMD field, 8 bits
713 * @{ */
714 /** TSE: TCP (set) or UDP (clear). */
715 unsigned fTCP : 1;
716 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
717 * the IP header. Does not affect the checksumming.
718 * @remarks 82544GC/EI interprets a cleared field differently. */
719 unsigned fIP : 1;
720 /** TSE: TCP segmentation enable. When clear the context describes */
721 unsigned fTSE : 1;
722 /** Report status (only applies to dw3.fDD for here). */
723 unsigned fRS : 1;
724 /** Reserved, MBZ. */
725 unsigned fRSV1 : 1;
726 /** Descriptor extension, must be set for this descriptor type. */
727 unsigned fDEXT : 1;
728 /** Reserved, MBZ. */
729 unsigned fRSV2 : 1;
730 /** Interrupt delay enable. */
731 unsigned fIDE : 1;
732 /** @} */
733 } dw2;
734 struct TDCDw3_st
735 {
736 /** Descriptor Done. */
737 unsigned fDD : 1;
738 /** Reserved, MBZ. */
739 unsigned u7RSV : 7;
740 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
741 unsigned u8HDRLEN : 8;
742 /** TSO: Maximum segment size. */
743 unsigned u16MSS : 16;
744 } dw3;
745};
746typedef struct E1kTDContext E1KTXCTX;
747
748/**
749 * TCP/IP Data Transmit Descriptor, section 3.3.7.
750 */
751struct E1kTDData
752{
753 uint64_t u64BufAddr; /**< Address of data buffer */
754 struct TDDCmd_st
755 {
756 /** The total length of data pointed to by this descriptor. */
757 unsigned u20DTALEN : 20;
758 /** The descriptor type - E1K_DTYP_DATA (1). */
759 unsigned u4DTYP : 4;
760 /** @name DCMD field, 8 bits (3.3.7.1).
761 * @{ */
762 /** End of packet. Note TSCTFC update. */
763 unsigned fEOP : 1;
764 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
765 unsigned fIFCS : 1;
766 /** Use the TSE context when set and the normal when clear. */
767 unsigned fTSE : 1;
768 /** Report status (dw3.STA). */
769 unsigned fRS : 1;
770 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
771 unsigned fRSV : 1;
772 /** Descriptor extension, must be set for this descriptor type. */
773 unsigned fDEXT : 1;
774 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
775 * Insert dw3.SPECIAL after ethernet header. */
776 unsigned fVLE : 1;
777 /** Interrupt delay enable. */
778 unsigned fIDE : 1;
779 /** @} */
780 } cmd;
781 struct TDDDw3_st
782 {
783 /** @name STA field (3.3.7.2)
784 * @{ */
785 unsigned fDD : 1; /**< Descriptor done. */
786 unsigned fEC : 1; /**< Excess collision. */
787 unsigned fLC : 1; /**< Late collision. */
788 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
789 unsigned fTURSV : 1;
790 /** @} */
791 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
792 /** @name POPTS (Packet Option) field (3.3.7.3)
793 * @{ */
794 unsigned fIXSM : 1; /**< Insert IP checksum. */
795 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
796 unsigned u6RSV : 6; /**< Reserved, MBZ. */
797 /** @} */
798 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
799 * Requires fEOP, fVLE and CTRL.VME to be set.
800 * @{ */
801 unsigned u12VLAN : 12; /**< VLAN identifier. */
802 unsigned fCFI : 1; /**< Canonical form indicator (VLAN). */
803 unsigned u3PRI : 3; /**< User priority (VLAN). */
804 /** @} */
805 } dw3;
806};
807typedef struct E1kTDData E1KTXDAT;
808
809union E1kTxDesc
810{
811 struct E1kTDLegacy legacy;
812 struct E1kTDContext context;
813 struct E1kTDData data;
814};
815typedef union E1kTxDesc E1KTXDESC;
816AssertCompileSize(E1KTXDESC, 16);
817
818#define RA_CTL_AS 0x0003
819#define RA_CTL_AV 0x8000
820
821union E1kRecAddr
822{
823 uint32_t au32[32];
824 struct RAArray
825 {
826 uint8_t addr[6];
827 uint16_t ctl;
828 } array[16];
829};
830typedef struct E1kRecAddr::RAArray E1KRAELEM;
831typedef union E1kRecAddr E1KRA;
832AssertCompileSize(E1KRA, 8*16);
833
834#define E1K_IP_RF 0x8000 /* reserved fragment flag */
835#define E1K_IP_DF 0x4000 /* dont fragment flag */
836#define E1K_IP_MF 0x2000 /* more fragments flag */
837#define E1K_IP_OFFMASK 0x1fff /* mask for fragmenting bits */
838
839/** @todo use+extend RTNETIPV4 */
840struct E1kIpHeader
841{
842 /* type of service / version / header length */
843 uint16_t tos_ver_hl;
844 /* total length */
845 uint16_t total_len;
846 /* identification */
847 uint16_t ident;
848 /* fragment offset field */
849 uint16_t offset;
850 /* time to live / protocol*/
851 uint16_t ttl_proto;
852 /* checksum */
853 uint16_t chksum;
854 /* source IP address */
855 uint32_t src;
856 /* destination IP address */
857 uint32_t dest;
858};
859AssertCompileSize(struct E1kIpHeader, 20);
860
861#define E1K_TCP_FIN 0x01U
862#define E1K_TCP_SYN 0x02U
863#define E1K_TCP_RST 0x04U
864#define E1K_TCP_PSH 0x08U
865#define E1K_TCP_ACK 0x10U
866#define E1K_TCP_URG 0x20U
867#define E1K_TCP_ECE 0x40U
868#define E1K_TCP_CWR 0x80U
869
870#define E1K_TCP_FLAGS 0x3fU
871
872/** @todo use+extend RTNETTCP */
873struct E1kTcpHeader
874{
875 uint16_t src;
876 uint16_t dest;
877 uint32_t seqno;
878 uint32_t ackno;
879 uint16_t hdrlen_flags;
880 uint16_t wnd;
881 uint16_t chksum;
882 uint16_t urgp;
883};
884AssertCompileSize(struct E1kTcpHeader, 20);
885
886
887/** The current Saved state version. */
888#define E1K_SAVEDSTATE_VERSION 2
889/** Saved state version for VirtualBox 3.0 and earlier.
890 * This did not include the configuration part nor the E1kEEPROM. */
891#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
892
893/**
894 * Device state structure. Holds the current state of device.
895 *
896 * @implements PDMINETWORKDOWN
897 * @implements PDMINETWORKCONFIG
898 * @implements PDMILEDPORTS
899 */
900struct E1kState_st
901{
902 char szInstance[8]; /**< Instance name, e.g. E1000#1. */
903 PDMIBASE IBase;
904 PDMINETWORKDOWN INetworkDown;
905 PDMINETWORKCONFIG INetworkConfig;
906 PDMILEDPORTS ILeds; /**< LED interface */
907 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
908 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
909
910 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
911 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
912 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
913 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
914 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
915 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
916 PTMTIMERR3 pTIDTimerR3; /**< Tranmsit Interrupt Delay Timer - R3. */
917 PTMTIMERR3 pTADTimerR3; /**< Tranmsit Absolute Delay Timer - R3. */
918 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
919 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
920 /** The scatter / gather buffer used for the current outgoing packet - R3. */
921 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
922
923 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
924 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
925 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
926 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
927 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
928 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
929 PTMTIMERR0 pTIDTimerR0; /**< Tranmsit Interrupt Delay Timer - R0. */
930 PTMTIMERR0 pTADTimerR0; /**< Tranmsit Absolute Delay Timer - R0. */
931 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
932 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
933 /** The scatter / gather buffer used for the current outgoing packet - R0. */
934 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
935
936 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
937 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
938 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
939 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
940 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
941 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
942 PTMTIMERRC pTIDTimerRC; /**< Tranmsit Interrupt Delay Timer - RC. */
943 PTMTIMERRC pTADTimerRC; /**< Tranmsit Absolute Delay Timer - RC. */
944 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
945 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
946 /** The scatter / gather buffer used for the current outgoing packet - RC. */
947 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
948 RTRCPTR RCPtrAlignment;
949
950 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
951#ifndef E1K_GLOBAL_MUTEX
952 PDMCRITSECT csRx; /**< RX Critical section. */
953// PDMCRITSECT csTx; /**< TX Critical section. */
954#endif
955 /** Base address of memory-mapped registers. */
956 RTGCPHYS addrMMReg;
957 /** MAC address obtained from the configuration. */
958 RTMAC macConfigured;
959 /** Base port of I/O space region. */
960 RTIOPORT addrIOPort;
961 /** EMT: */
962 PCIDEVICE pciDevice;
963 /** EMT: Last time the interrupt was acknowledged. */
964 uint64_t u64AckedAt;
965 /** All: Used for eliminating spurious interrupts. */
966 bool fIntRaised;
967 /** EMT: false if the cable is disconnected by the GUI. */
968 bool fCableConnected;
969 /** EMT: */
970 bool fR0Enabled;
971 /** EMT: */
972 bool fGCEnabled;
973
974 /** All: Device register storage. */
975 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
976 /** TX/RX: Status LED. */
977 PDMLED led;
978 /** TX/RX: Number of packet being sent/received to show in debug log. */
979 uint32_t u32PktNo;
980
981 /** EMT: Offset of the register to be read via IO. */
982 uint32_t uSelectedReg;
983 /** EMT: Multicast Table Array. */
984 uint32_t auMTA[128];
985 /** EMT: Receive Address registers. */
986 E1KRA aRecAddr;
987 /** EMT: VLAN filter table array. */
988 uint32_t auVFTA[128];
989 /** EMT: Receive buffer size. */
990 uint16_t u16RxBSize;
991 /** EMT: Locked state -- no state alteration possible. */
992 bool fLocked;
993 /** EMT: */
994 bool fDelayInts;
995 /** All: */
996 bool fIntMaskUsed;
997
998 /** N/A: */
999 bool volatile fMaybeOutOfSpace;
1000 /** EMT: Gets signalled when more RX descriptors become available. */
1001 RTSEMEVENT hEventMoreRxDescAvail;
1002
1003 /** TX: Context used for TCP segmentation packets. */
1004 E1KTXCTX contextTSE;
1005 /** TX: Context used for ordinary packets. */
1006 E1KTXCTX contextNormal;
1007 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1008 * applicable to the current TSE mode. */
1009 PDMNETWORKGSO GsoCtx;
1010 /** Scratch space for holding the loopback / fallback scatter / gather
1011 * descriptor. */
1012 union
1013 {
1014 PDMSCATTERGATHER Sg;
1015 uint8_t padding[8 * sizeof(RTUINTPTR)];
1016 } uTxFallback;
1017 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1018 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1019 /** TX: Number of bytes assembled in TX packet buffer. */
1020 uint16_t u16TxPktLen;
1021 /** TX: IP checksum has to be inserted if true. */
1022 bool fIPcsum;
1023 /** TX: TCP/UDP checksum has to be inserted if true. */
1024 bool fTCPcsum;
1025 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1026 uint32_t u32PayRemain;
1027 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1028 uint16_t u16HdrRemain;
1029 /** TX TSE fallback: Flags from template header. */
1030 uint16_t u16SavedFlags;
1031 /** TX TSE fallback: Partial checksum from template header. */
1032 uint32_t u32SavedCsum;
1033 /** ?: Emulated controller type. */
1034 E1KCHIP eChip;
1035 uint32_t alignmentFix;
1036
1037 /** EMT: EEPROM emulation */
1038 E1kEEPROM eeprom;
1039 /** EMT: Physical interface emulation. */
1040 PHY phy;
1041
1042#if 0
1043 /** Alignment padding. */
1044 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1045#endif
1046
1047 STAMCOUNTER StatReceiveBytes;
1048 STAMCOUNTER StatTransmitBytes;
1049#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
1050 STAMPROFILEADV StatMMIOReadGC;
1051 STAMPROFILEADV StatMMIOReadHC;
1052 STAMPROFILEADV StatMMIOWriteGC;
1053 STAMPROFILEADV StatMMIOWriteHC;
1054 STAMPROFILEADV StatEEPROMRead;
1055 STAMPROFILEADV StatEEPROMWrite;
1056 STAMPROFILEADV StatIOReadGC;
1057 STAMPROFILEADV StatIOReadHC;
1058 STAMPROFILEADV StatIOWriteGC;
1059 STAMPROFILEADV StatIOWriteHC;
1060 STAMPROFILEADV StatLateIntTimer;
1061 STAMCOUNTER StatLateInts;
1062 STAMCOUNTER StatIntsRaised;
1063 STAMCOUNTER StatIntsPrevented;
1064 STAMPROFILEADV StatReceive;
1065 STAMPROFILEADV StatReceiveFilter;
1066 STAMPROFILEADV StatReceiveStore;
1067 STAMPROFILEADV StatTransmit;
1068 STAMPROFILE StatTransmitSend;
1069 STAMPROFILE StatRxOverflow;
1070 STAMCOUNTER StatRxOverflowWakeup;
1071 STAMCOUNTER StatTxDescCtxNormal;
1072 STAMCOUNTER StatTxDescCtxTSE;
1073 STAMCOUNTER StatTxDescLegacy;
1074 STAMCOUNTER StatTxDescData;
1075 STAMCOUNTER StatTxDescTSEData;
1076 STAMCOUNTER StatTxPathFallback;
1077 STAMCOUNTER StatTxPathGSO;
1078 STAMCOUNTER StatTxPathRegular;
1079 STAMCOUNTER StatPHYAccesses;
1080
1081#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
1082
1083#ifdef E1K_INT_STATS
1084 /* Internal stats */
1085 uint32_t uStatInt;
1086 uint32_t uStatIntTry;
1087 int32_t uStatIntLower;
1088 uint32_t uStatIntDly;
1089 int32_t iStatIntLost;
1090 int32_t iStatIntLostOne;
1091 uint32_t uStatDisDly;
1092 uint32_t uStatIntSkip;
1093 uint32_t uStatIntLate;
1094 uint32_t uStatIntMasked;
1095 uint32_t uStatIntEarly;
1096 uint32_t uStatIntRx;
1097 uint32_t uStatIntTx;
1098 uint32_t uStatIntICS;
1099 uint32_t uStatIntRDTR;
1100 uint32_t uStatIntRXDMT0;
1101 uint32_t uStatIntTXQE;
1102 uint32_t uStatTxNoRS;
1103 uint32_t uStatTxIDE;
1104 uint32_t uStatTAD;
1105 uint32_t uStatTID;
1106 uint32_t uStatRAD;
1107 uint32_t uStatRID;
1108 uint32_t uStatRxFrm;
1109 uint32_t uStatTxFrm;
1110 uint32_t uStatDescCtx;
1111 uint32_t uStatDescDat;
1112 uint32_t uStatDescLeg;
1113#endif /* E1K_INT_STATS */
1114};
1115typedef struct E1kState_st E1KSTATE;
1116
1117#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1118
1119/* Forward declarations ******************************************************/
1120RT_C_DECLS_BEGIN
1121PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1122PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
1123PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
1124PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
1125RT_C_DECLS_END
1126
1127static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread);
1128
1129static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1130static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1131static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1132static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1133static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1134#if 0 /* unused */
1135static int e1kRegReadCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1136#endif
1137static int e1kRegWriteCTRL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1138static int e1kRegReadEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1139static int e1kRegWriteEECD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1140static int e1kRegWriteEERD (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1141static int e1kRegWriteMDIC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1142static int e1kRegReadICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1143static int e1kRegWriteICR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1144static int e1kRegWriteICS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1145static int e1kRegWriteIMS (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1146static int e1kRegWriteIMC (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1147static int e1kRegWriteRCTL (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1148static int e1kRegWritePBA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1149static int e1kRegWriteRDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1150static int e1kRegWriteRDTR (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1151static int e1kRegWriteTDT (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1152static int e1kRegReadMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1153static int e1kRegWriteMTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1154static int e1kRegReadRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1155static int e1kRegWriteRA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1156static int e1kRegReadVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1157static int e1kRegWriteVFTA (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1158
1159/**
1160 * Register map table.
1161 *
1162 * Override fn_read and fn_write to get register-specific behavior.
1163 */
1164const static struct E1kRegMap_st
1165{
1166 /** Register offset in the register space. */
1167 uint32_t offset;
1168 /** Size in bytes. Registers of size > 4 are in fact tables. */
1169 uint32_t size;
1170 /** Readable bits. */
1171 uint32_t readable;
1172 /** Writable bits. */
1173 uint32_t writable;
1174 /** Read callback. */
1175 int (*pfnRead)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1176 /** Write callback. */
1177 int (*pfnWrite)(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
1178 /** Abbreviated name. */
1179 const char *abbrev;
1180 /** Full name. */
1181 const char *name;
1182} s_e1kRegMap[E1K_NUM_OF_REGS] =
1183{
1184 /* offset size read mask write mask read callback write callback abbrev full name */
1185 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1186 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1187 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1188 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1189 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1190 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1191 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1192 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1193 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1194 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1195 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1196 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1197 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1198 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1199 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1200 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1201 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1202 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1203 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1204 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1205 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1206 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1207 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1208 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1209 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1210 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1211 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1212 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1213 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1214 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1215 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1216 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1217 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1218 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1219 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1220 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1221 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1222 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1223 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1224 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1225 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1226 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1227 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1228 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1229 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1230 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1231 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1232 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1233 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1234 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1235 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1236 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1237 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1238 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1239 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1240 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1241 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1242 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1243 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1244 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1245 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1246 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1247 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1248 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1249 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1250 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1251 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1252 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1253 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1254 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1255 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1256 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1257 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1258 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1259 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1260 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1261 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1262 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1263 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1264 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1265 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1266 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1267 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1268 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1269 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1270 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1271 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1272 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1273 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1274 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1275 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1276 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1277 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1278 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1279 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1280 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1281 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1282 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1283 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1284 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1285 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1286 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1287 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1288 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1289 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1290 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1291 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1292 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1293 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1294 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1295 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1296 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1297 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1298 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1299 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1300 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1301 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1302 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1303 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1304 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1305 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1306 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1307 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1308 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1309 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1310 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1311 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1312 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1313 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1314 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1315 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1316 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1317 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
1318 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
1319 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
1320};
1321
1322#ifdef DEBUG
1323
1324/**
1325 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1326 *
1327 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1328 *
1329 * @returns The buffer.
1330 *
1331 * @param u32 The word to convert into string.
1332 * @param mask Selects which bytes to convert.
1333 * @param buf Where to put the result.
1334 */
1335static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1336{
1337 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1338 {
1339 if (mask & 0xF)
1340 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1341 else
1342 *ptr = '.';
1343 }
1344 buf[8] = 0;
1345 return buf;
1346}
1347
1348/**
1349 * Returns timer name for debug purposes.
1350 *
1351 * @returns The timer name.
1352 *
1353 * @param pState The device state structure.
1354 * @param pTimer The timer to get the name for.
1355 */
1356DECLINLINE(const char *) e1kGetTimerName(E1KSTATE *pState, PTMTIMER pTimer)
1357{
1358 if (pTimer == pState->CTX_SUFF(pTIDTimer))
1359 return "TID";
1360 if (pTimer == pState->CTX_SUFF(pTADTimer))
1361 return "TAD";
1362 if (pTimer == pState->CTX_SUFF(pRIDTimer))
1363 return "RID";
1364 if (pTimer == pState->CTX_SUFF(pRADTimer))
1365 return "RAD";
1366 if (pTimer == pState->CTX_SUFF(pIntTimer))
1367 return "Int";
1368 return "unknown";
1369}
1370
1371#endif /* DEBUG */
1372
1373/**
1374 * Arm a timer.
1375 *
1376 * @param pState Pointer to the device state structure.
1377 * @param pTimer Pointer to the timer.
1378 * @param uExpireIn Expiration interval in microseconds.
1379 */
1380DECLINLINE(void) e1kArmTimer(E1KSTATE *pState, PTMTIMER pTimer, uint32_t uExpireIn)
1381{
1382 if (pState->fLocked)
1383 return;
1384
1385 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1386 INSTANCE(pState), e1kGetTimerName(pState, pTimer), uExpireIn));
1387 TMTimerSet(pTimer, TMTimerFromMicro(pTimer, uExpireIn) +
1388 TMTimerGet(pTimer));
1389}
1390
1391/**
1392 * Cancel a timer.
1393 *
1394 * @param pState Pointer to the device state structure.
1395 * @param pTimer Pointer to the timer.
1396 */
1397DECLINLINE(void) e1kCancelTimer(E1KSTATE *pState, PTMTIMER pTimer)
1398{
1399 E1kLog2(("%s Stopping %s timer...\n",
1400 INSTANCE(pState), e1kGetTimerName(pState, pTimer)));
1401 int rc = TMTimerStop(pTimer);
1402 if (RT_FAILURE(rc))
1403 {
1404 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1405 INSTANCE(pState), rc));
1406 }
1407}
1408
1409#ifdef E1K_GLOBAL_MUTEX
1410DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, int iBusyRc)
1411{
1412 return VINF_SUCCESS;
1413}
1414
1415DECLINLINE(void) e1kCsLeave(E1KSTATE *pState)
1416{
1417}
1418
1419#define e1kCsRxEnter(ps, rc) VINF_SUCCESS
1420#define e1kCsRxLeave(ps) do { } while (0)
1421
1422#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1423#define e1kCsTxLeave(ps) do { } while (0)
1424
1425
1426DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1427{
1428 int rc = PDMCritSectEnter(&pState->cs, iBusyRc);
1429 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1430 {
1431 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
1432 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1433 PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1434 "%s Failed to enter critical section, rc=%Rrc\n",
1435 INSTANCE(pState), rc);
1436 }
1437 else
1438 {
1439 //E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1440 }
1441 return rc;
1442}
1443
1444DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1445{
1446 //E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
1447 PDMCritSectLeave(&pState->cs);
1448}
1449
1450#else /* !E1K_GLOBAL_MUTEX */
1451#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1452#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1453
1454#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1455#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1456
1457#define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1458#define e1kCsTxLeave(ps) do { } while (0)
1459//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1460//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1461
1462#if 0
1463DECLINLINE(int) e1kCsEnter(E1KSTATE *pState, PPDMCRITSECT pCs, int iBusyRc, RT_SRC_POS_DECL)
1464{
1465 int rc = PDMCritSectEnter(pCs, iBusyRc);
1466 if (RT_FAILURE(rc))
1467 {
1468 E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
1469 INSTANCE(pState), RT_SRC_POS_ARGS, rc));
1470 PDMDeviceDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS_ARGS,
1471 "%s Failed to enter critical section, rc=%Rrc\n",
1472 INSTANCE(pState), rc);
1473 }
1474 else
1475 {
1476 //E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
1477 }
1478 return RT_SUCCESS(rc);
1479}
1480
1481DECLINLINE(void) e1kCsLeave(E1KSTATE *pState, PPDMCRITSECT pCs)
1482{
1483 //E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
1484 PDMCritSectLeave(&pState->cs);
1485}
1486#endif
1487DECLINLINE(int) e1kMutexAcquire(E1KSTATE *pState, int iBusyRc, RT_SRC_POS_DECL)
1488{
1489 return VINF_SUCCESS;
1490}
1491
1492DECLINLINE(void) e1kMutexRelease(E1KSTATE *pState)
1493{
1494}
1495#endif /* !E1K_GLOBAL_MUTEX */
1496
1497#ifdef IN_RING3
1498/**
1499 * Wakeup the RX thread.
1500 */
1501static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1502{
1503 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
1504 if ( pState->fMaybeOutOfSpace
1505 && pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1506 {
1507 STAM_COUNTER_INC(&pState->StatRxOverflowWakeup);
1508 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", INSTANCE(pState)));
1509 RTSemEventSignal(pState->hEventMoreRxDescAvail);
1510 }
1511}
1512#endif
1513
1514/**
1515 * Compute Internet checksum.
1516 *
1517 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1518 *
1519 * @param pState The device state structure.
1520 * @param cpPacket The packet.
1521 * @param cb The size of the packet.
1522 * @param cszText A string denoting direction of packet transfer.
1523 *
1524 * @return The 1's complement of the 1's complement sum.
1525 *
1526 * @thread E1000_TX
1527 */
1528static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1529{
1530 uint32_t csum = 0;
1531 uint16_t *pu16 = (uint16_t *)pvBuf;
1532
1533 while (cb > 1)
1534 {
1535 csum += *pu16++;
1536 cb -= 2;
1537 }
1538 if (cb)
1539 csum += *(uint8_t*)pu16;
1540 while (csum >> 16)
1541 csum = (csum >> 16) + (csum & 0xFFFF);
1542 return ~csum;
1543}
1544
1545/**
1546 * Dump a packet to debug log.
1547 *
1548 * @param pState The device state structure.
1549 * @param cpPacket The packet.
1550 * @param cb The size of the packet.
1551 * @param cszText A string denoting direction of packet transfer.
1552 * @thread E1000_TX
1553 */
1554DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
1555{
1556#ifdef DEBUG
1557 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1558 {
1559 E1kLog(("%s --- %s packet #%d: ---\n",
1560 INSTANCE(pState), cszText, ++pState->u32PktNo));
1561 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1562 e1kCsLeave(pState);
1563 }
1564#else
1565 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY)) == VINF_SUCCESS)
1566 {
1567 E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
1568 e1kCsLeave(pState);
1569 }
1570#endif
1571}
1572
1573/**
1574 * Determine the type of transmit descriptor.
1575 *
1576 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1577 *
1578 * @param pDesc Pointer to descriptor union.
1579 * @thread E1000_TX
1580 */
1581DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1582{
1583 if (pDesc->legacy.cmd.fDEXT)
1584 return pDesc->context.dw2.u4DTYP;
1585 return E1K_DTYP_LEGACY;
1586}
1587
1588/**
1589 * Dump receive descriptor to debug log.
1590 *
1591 * @param pState The device state structure.
1592 * @param pDesc Pointer to the descriptor.
1593 * @thread E1000_RX
1594 */
1595static void e1kPrintRDesc(E1KSTATE* pState, E1KRXDESC* pDesc)
1596{
1597 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", INSTANCE(pState), pDesc->u16Length));
1598 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1599 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1600 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1601 pDesc->status.fPIF ? "PIF" : "pif",
1602 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1603 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1604 pDesc->status.fVP ? "VP" : "vp",
1605 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1606 pDesc->status.fEOP ? "EOP" : "eop",
1607 pDesc->status.fDD ? "DD" : "dd",
1608 pDesc->status.fRXE ? "RXE" : "rxe",
1609 pDesc->status.fIPE ? "IPE" : "ipe",
1610 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1611 pDesc->status.fCE ? "CE" : "ce",
1612 pDesc->status.fCFI ? "CFI" :"cfi",
1613 pDesc->status.u12VLAN,
1614 pDesc->status.u3PRI));
1615}
1616
1617/**
1618 * Dump transmit descriptor to debug log.
1619 *
1620 * @param pState The device state structure.
1621 * @param pDesc Pointer to descriptor union.
1622 * @param cszDir A string denoting direction of descriptor transfer
1623 * @thread E1000_TX
1624 */
1625static void e1kPrintTDesc(E1KSTATE* pState, E1KTXDESC* pDesc, const char* cszDir)
1626{
1627 switch (e1kGetDescType(pDesc))
1628 {
1629 case E1K_DTYP_CONTEXT:
1630 E1kLog2(("%s %s Context Transmit Descriptor %s\n",
1631 INSTANCE(pState), cszDir, cszDir));
1632 E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1633 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1634 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1635 E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1636 pDesc->context.dw2.fIDE ? " IDE":"",
1637 pDesc->context.dw2.fRS ? " RS" :"",
1638 pDesc->context.dw2.fTSE ? " TSE":"",
1639 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1640 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1641 pDesc->context.dw2.u20PAYLEN,
1642 pDesc->context.dw3.u8HDRLEN,
1643 pDesc->context.dw3.u16MSS,
1644 pDesc->context.dw3.fDD?"DD":""));
1645 break;
1646 case E1K_DTYP_DATA:
1647 E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1648 INSTANCE(pState), cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1649 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1650 pDesc->data.u64BufAddr,
1651 pDesc->data.cmd.u20DTALEN));
1652 E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1653 pDesc->data.cmd.fIDE ? " IDE" :"",
1654 pDesc->data.cmd.fVLE ? " VLE" :"",
1655 pDesc->data.cmd.fRS ? " RS" :"",
1656 pDesc->data.cmd.fTSE ? " TSE" :"",
1657 pDesc->data.cmd.fIFCS? " IFCS":"",
1658 pDesc->data.cmd.fEOP ? " EOP" :"",
1659 pDesc->data.dw3.fDD ? " DD" :"",
1660 pDesc->data.dw3.fEC ? " EC" :"",
1661 pDesc->data.dw3.fLC ? " LC" :"",
1662 pDesc->data.dw3.fTXSM? " TXSM":"",
1663 pDesc->data.dw3.fIXSM? " IXSM":"",
1664 pDesc->data.dw3.fCFI ? " CFI" :"",
1665 pDesc->data.dw3.u12VLAN,
1666 pDesc->data.dw3.u3PRI));
1667 break;
1668 case E1K_DTYP_LEGACY:
1669 E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1670 INSTANCE(pState), cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1671 E1kLog2((" Address=%16LX DTALEN=%05X\n",
1672 pDesc->data.u64BufAddr,
1673 pDesc->legacy.cmd.u16Length));
1674 E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1675 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1676 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1677 pDesc->legacy.cmd.fRS ? " RS" :"",
1678 pDesc->legacy.cmd.fIC ? " IC" :"",
1679 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1680 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1681 pDesc->legacy.dw3.fDD ? " DD" :"",
1682 pDesc->legacy.dw3.fEC ? " EC" :"",
1683 pDesc->legacy.dw3.fLC ? " LC" :"",
1684 pDesc->legacy.cmd.u8CSO,
1685 pDesc->legacy.dw3.u8CSS,
1686 pDesc->legacy.dw3.fCFI ? " CFI" :"",
1687 pDesc->legacy.dw3.u12VLAN,
1688 pDesc->legacy.dw3.u3PRI));
1689 break;
1690 default:
1691 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1692 INSTANCE(pState), cszDir, cszDir));
1693 break;
1694 }
1695}
1696
1697/**
1698 * Hardware reset. Revert all registers to initial values.
1699 *
1700 * @param pState The device state structure.
1701 */
1702PDMBOTHCBDECL(void) e1kHardReset(E1KSTATE *pState)
1703{
1704 E1kLog(("%s Hard reset triggered\n", INSTANCE(pState)));
1705 memset(pState->auRegs, 0, sizeof(pState->auRegs));
1706 memset(pState->aRecAddr.au32, 0, sizeof(pState->aRecAddr.au32));
1707#ifdef E1K_INIT_RA0
1708 memcpy(pState->aRecAddr.au32, pState->macConfigured.au8,
1709 sizeof(pState->macConfigured.au8));
1710 pState->aRecAddr.array[0].ctl |= RA_CTL_AV;
1711#endif /* E1K_INIT_RA0 */
1712 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1713 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1714 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1715 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1716 Assert(GET_BITS(RCTL, BSIZE) == 0);
1717 pState->u16RxBSize = 2048;
1718}
1719
1720/**
1721 * Raise interrupt if not masked.
1722 *
1723 * @param pState The device state structure.
1724 */
1725PDMBOTHCBDECL(int) e1kRaiseInterrupt(E1KSTATE *pState, int rcBusy, uint32_t u32IntCause = 0)
1726{
1727 int rc = e1kCsEnter(pState, rcBusy);
1728 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1729 return rc;
1730
1731 E1K_INC_ISTAT_CNT(pState->uStatIntTry);
1732 ICR |= u32IntCause;
1733 if (ICR & IMS)
1734 {
1735#if 0
1736 if (pState->fDelayInts)
1737 {
1738 E1K_INC_ISTAT_CNT(pState->uStatIntDly);
1739 pState->iStatIntLostOne = 1;
1740 E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
1741 INSTANCE(pState), ICR));
1742#define E1K_LOST_IRQ_THRSLD 20
1743//#define E1K_LOST_IRQ_THRSLD 200000000
1744 if (pState->iStatIntLost >= E1K_LOST_IRQ_THRSLD)
1745 {
1746 E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
1747 INSTANCE(pState), pState->uStatIntDly, pState->uStatIntLate));
1748 pState->fIntMaskUsed = false;
1749 pState->uStatDisDly++;
1750 }
1751 }
1752 else
1753#endif
1754 if (pState->fIntRaised)
1755 {
1756 E1K_INC_ISTAT_CNT(pState->uStatIntSkip);
1757 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1758 INSTANCE(pState), ICR & IMS));
1759 }
1760 else
1761 {
1762#ifdef E1K_ITR_ENABLED
1763 uint64_t tstamp = TMTimerGet(pState->CTX_SUFF(pIntTimer));
1764 /* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
1765 E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
1766 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1767 if (!!ITR && pState->fIntMaskUsed && tstamp - pState->u64AckedAt < ITR * 256)
1768 {
1769 E1K_INC_ISTAT_CNT(pState->uStatIntEarly);
1770 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1771 INSTANCE(pState), (uint32_t)(tstamp - pState->u64AckedAt), ITR * 256));
1772 }
1773 else
1774#endif
1775 {
1776
1777 /* Since we are delivering the interrupt now
1778 * there is no need to do it later -- stop the timer.
1779 */
1780 TMTimerStop(pState->CTX_SUFF(pIntTimer));
1781 E1K_INC_ISTAT_CNT(pState->uStatInt);
1782 STAM_COUNTER_INC(&pState->StatIntsRaised);
1783 /* Got at least one unmasked interrupt cause */
1784 pState->fIntRaised = true;
1785 /* Raise(1) INTA(0) */
1786 //PDMDevHlpPCISetIrqNoWait(pState->CTXSUFF(pInst), 0, 1);
1787 //e1kMutexRelease(pState);
1788 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1789 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 1);
1790 //e1kMutexAcquire(pState, RT_SRC_POS);
1791 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1792 INSTANCE(pState), ICR & IMS));
1793 }
1794 }
1795 }
1796 else
1797 {
1798 E1K_INC_ISTAT_CNT(pState->uStatIntMasked);
1799 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1800 INSTANCE(pState), ICR, IMS));
1801 }
1802 e1kCsLeave(pState);
1803 return VINF_SUCCESS;
1804}
1805
1806/**
1807 * Compute the physical address of the descriptor.
1808 *
1809 * @returns the physical address of the descriptor.
1810 *
1811 * @param baseHigh High-order 32 bits of descriptor table address.
1812 * @param baseLow Low-order 32 bits of descriptor table address.
1813 * @param idxDesc The descriptor index in the table.
1814 */
1815DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1816{
1817 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1818 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1819}
1820
1821/**
1822 * Advance the head pointer of the receive descriptor queue.
1823 *
1824 * @remarks RDH always points to the next available RX descriptor.
1825 *
1826 * @param pState The device state structure.
1827 */
1828DECLINLINE(void) e1kAdvanceRDH(E1KSTATE *pState)
1829{
1830 //e1kCsEnter(pState, RT_SRC_POS);
1831 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1832 RDH = 0;
1833 /*
1834 * Compute current recieve queue length and fire RXDMT0 interrupt
1835 * if we are low on recieve buffers
1836 */
1837 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1838 /*
1839 * The minimum threshold is controlled by RDMTS bits of RCTL:
1840 * 00 = 1/2 of RDLEN
1841 * 01 = 1/4 of RDLEN
1842 * 10 = 1/8 of RDLEN
1843 * 11 = reserved
1844 */
1845 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1846 if (uRQueueLen <= uMinRQThreshold)
1847 {
1848 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1849 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1850 INSTANCE(pState), RDH, RDT, uRQueueLen, uMinRQThreshold));
1851 E1K_INC_ISTAT_CNT(pState->uStatIntRXDMT0);
1852 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXDMT0);
1853 }
1854 //e1kCsLeave(pState);
1855}
1856
1857/**
1858 * Store a fragment of received packet that fits into the next available RX
1859 * buffer.
1860 *
1861 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
1862 *
1863 * @param pState The device state structure.
1864 * @param pDesc The next available RX descriptor.
1865 * @param pvBuf The fragment.
1866 * @param cb The size of the fragment.
1867 */
1868static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
1869{
1870 STAM_PROFILE_ADV_START(&pState->StatReceiveStore, a);
1871 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
1872 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
1873 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
1874 /* Write back the descriptor */
1875 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
1876 e1kPrintRDesc(pState, pDesc);
1877 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
1878 /* Advance head */
1879 e1kAdvanceRDH(pState);
1880 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
1881 if (pDesc->status.fEOP)
1882 {
1883 /* Complete packet has been stored -- it is time to let the guest know. */
1884#ifdef E1K_USE_RX_TIMERS
1885 if (RDTR)
1886 {
1887 /* Arm the timer to fire in RDTR usec (discard .024) */
1888 e1kArmTimer(pState, pState->CTX_SUFF(pRIDTimer), RDTR);
1889 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
1890 if (RADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pRADTimer)))
1891 e1kArmTimer(pState, pState->CTX_SUFF(pRADTimer), RADV);
1892 }
1893 else
1894 {
1895#endif
1896 /* 0 delay means immediate interrupt */
1897 E1K_INC_ISTAT_CNT(pState->uStatIntRx);
1898 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_RXT0);
1899#ifdef E1K_USE_RX_TIMERS
1900 }
1901#endif
1902 }
1903 STAM_PROFILE_ADV_STOP(&pState->StatReceiveStore, a);
1904}
1905
1906/**
1907 * Returns true if it is a broadcast packet.
1908 *
1909 * @returns true if destination address indicates broadcast.
1910 * @param pvBuf The ethernet packet.
1911 */
1912DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
1913{
1914 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1915 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
1916}
1917
1918/**
1919 * Returns true if it is a multicast packet.
1920 *
1921 * @remarks returns true for broadcast packets as well.
1922 * @returns true if destination address indicates multicast.
1923 * @param pvBuf The ethernet packet.
1924 */
1925DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
1926{
1927 return (*(char*)pvBuf) & 1;
1928}
1929
1930/**
1931 * Set IXSM, IPCS and TCPCS flags according to the packet type.
1932 *
1933 * @remarks We emulate checksum offloading for major packets types only.
1934 *
1935 * @returns VBox status code.
1936 * @param pState The device state structure.
1937 * @param pFrame The available data.
1938 * @param cb Number of bytes available in the buffer.
1939 * @param status Bit fields containing status info.
1940 */
1941static int e1kRxChecksumOffload(E1KSTATE* pState, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
1942{
1943 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
1944 PRTNETIPV4 pIpHdr4;
1945
1946 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", INSTANCE(pState), uEtherType));
1947
1948 switch (uEtherType)
1949 {
1950 /** @todo
1951 * It is not safe to bypass checksum verification for packets coming
1952 * from real wire. We currently unable to tell where packets are
1953 * coming from so we tell the driver to ignore our checksum flags
1954 * and do verification in software.
1955 */
1956#if 0
1957 case 0x800: /* IPv4 */
1958 pStatus->fIXSM = false;
1959 pStatus->fIPCS = true;
1960 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
1961 /* TCP/UDP checksum offloading works with TCP and UDP only */
1962 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
1963 break;
1964 case 0x86DD: /* IPv6 */
1965 pStatus->fIXSM = false;
1966 pStatus->fIPCS = false;
1967 pStatus->fTCPCS = true;
1968 break;
1969#endif
1970 default: /* ARP, VLAN, etc. */
1971 pStatus->fIXSM = true;
1972 break;
1973 }
1974
1975 return VINF_SUCCESS;
1976}
1977
1978/**
1979 * Pad and store received packet.
1980 *
1981 * @remarks Make sure that the packet appears to upper layer as one coming
1982 * from real Ethernet: pad it and insert FCS.
1983 *
1984 * @returns VBox status code.
1985 * @param pState The device state structure.
1986 * @param pvBuf The available data.
1987 * @param cb Number of bytes available in the buffer.
1988 * @param status Bit fields containing status info.
1989 */
1990static int e1kHandleRxPacket(E1KSTATE* pState, const void *pvBuf, size_t cb, E1KRXDST status)
1991{
1992 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
1993 uint8_t *ptr = rxPacket;
1994
1995#ifndef E1K_GLOBAL_MUTEX
1996 int rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
1997 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1998 return rc;
1999#endif
2000
2001 if (cb > 70) /* unqualified guess */
2002 pState->led.Asserted.s.fReading = pState->led.Actual.s.fReading = 1;
2003
2004 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2005 memcpy(rxPacket, pvBuf, cb);
2006 /* Pad short packets */
2007 if (cb < 60)
2008 {
2009 memset(rxPacket + cb, 0, 60 - cb);
2010 cb = 60;
2011 }
2012 if (!(RCTL & RCTL_SECRC))
2013 {
2014 /* Add FCS if CRC stripping is not enabled */
2015 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2016 cb += sizeof(uint32_t);
2017 }
2018 /* Compute checksum of complete packet */
2019 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2020 e1kRxChecksumOffload(pState, rxPacket, cb, &status);
2021
2022 /* Update stats */
2023 E1K_INC_CNT32(GPRC);
2024 if (e1kIsBroadcast(pvBuf))
2025 E1K_INC_CNT32(BPRC);
2026 else if (e1kIsMulticast(pvBuf))
2027 E1K_INC_CNT32(MPRC);
2028 /* Update octet receive counter */
2029 E1K_ADD_CNT64(GORCL, GORCH, cb);
2030 STAM_REL_COUNTER_ADD(&pState->StatReceiveBytes, cb);
2031 if (cb == 64)
2032 E1K_INC_CNT32(PRC64);
2033 else if (cb < 128)
2034 E1K_INC_CNT32(PRC127);
2035 else if (cb < 256)
2036 E1K_INC_CNT32(PRC255);
2037 else if (cb < 512)
2038 E1K_INC_CNT32(PRC511);
2039 else if (cb < 1024)
2040 E1K_INC_CNT32(PRC1023);
2041 else
2042 E1K_INC_CNT32(PRC1522);
2043
2044 E1K_INC_ISTAT_CNT(pState->uStatRxFrm);
2045
2046 if (RDH == RDT)
2047 {
2048 E1kLog(("%s Out of recieve buffers, dropping the packet",
2049 INSTANCE(pState)));
2050 }
2051 /* Store the packet to receive buffers */
2052 while (RDH != RDT)
2053 {
2054 /* Load the desciptor pointed by head */
2055 E1KRXDESC desc;
2056 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2057 &desc, sizeof(desc));
2058 if (desc.u64BufAddr)
2059 {
2060 /* Update descriptor */
2061 desc.status = status;
2062 desc.u16Checksum = checksum;
2063 desc.status.fDD = true;
2064
2065 /*
2066 * We need to leave Rx critical section here or we risk deadlocking
2067 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2068 * page or has an access handler associated with it.
2069 * Note that it is safe to leave the critical section here since e1kRegWriteRDT()
2070 * modifies RDT only.
2071 */
2072 if (cb > pState->u16RxBSize)
2073 {
2074 desc.status.fEOP = false;
2075 e1kCsRxLeave(pState);
2076 e1kStoreRxFragment(pState, &desc, ptr, pState->u16RxBSize);
2077 rc = e1kCsRxEnter(pState, VERR_SEM_BUSY);
2078 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2079 return rc;
2080 ptr += pState->u16RxBSize;
2081 cb -= pState->u16RxBSize;
2082 }
2083 else
2084 {
2085 desc.status.fEOP = true;
2086 e1kCsRxLeave(pState);
2087 e1kStoreRxFragment(pState, &desc, ptr, cb);
2088 pState->led.Actual.s.fReading = 0;
2089 return VINF_SUCCESS;
2090 }
2091 /* Note: RDH is advanced by e1kStoreRxFragment! */
2092 }
2093 else
2094 {
2095 desc.status.fDD = true;
2096 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns),
2097 e1kDescAddr(RDBAH, RDBAL, RDH),
2098 &desc, sizeof(desc));
2099 e1kAdvanceRDH(pState);
2100 }
2101 }
2102
2103 if (cb > 0)
2104 E1kLog(("%s Out of recieve buffers, dropping %u bytes", INSTANCE(pState), cb));
2105
2106 pState->led.Actual.s.fReading = 0;
2107
2108 e1kCsRxLeave(pState);
2109
2110 return VINF_SUCCESS;
2111}
2112
2113
2114#if 0 /* unused */
2115/**
2116 * Read handler for Device Status register.
2117 *
2118 * Get the link status from PHY.
2119 *
2120 * @returns VBox status code.
2121 *
2122 * @param pState The device state structure.
2123 * @param offset Register offset in memory-mapped frame.
2124 * @param index Register index in register array.
2125 * @param mask Used to implement partial reads (8 and 16-bit).
2126 */
2127static int e1kRegReadCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2128{
2129 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2130 INSTANCE(pState), (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2131 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2132 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2133 {
2134 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2135 if (Phy::readMDIO(&pState->phy))
2136 *pu32Value = CTRL | CTRL_MDIO;
2137 else
2138 *pu32Value = CTRL & ~CTRL_MDIO;
2139 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2140 INSTANCE(pState), !!(*pu32Value & CTRL_MDIO)));
2141 }
2142 else
2143 {
2144 /* MDIO pin is used for output, ignore it */
2145 *pu32Value = CTRL;
2146 }
2147 return VINF_SUCCESS;
2148}
2149#endif /* unused */
2150
2151/**
2152 * Write handler for Device Control register.
2153 *
2154 * Handles reset.
2155 *
2156 * @param pState The device state structure.
2157 * @param offset Register offset in memory-mapped frame.
2158 * @param index Register index in register array.
2159 * @param value The value to store.
2160 * @param mask Used to implement partial writes (8 and 16-bit).
2161 * @thread EMT
2162 */
2163static int e1kRegWriteCTRL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2164{
2165 int rc = VINF_SUCCESS;
2166
2167 if (value & CTRL_RESET)
2168 { /* RST */
2169 e1kHardReset(pState);
2170 }
2171 else
2172 {
2173 if ( (value & CTRL_SLU)
2174 && pState->fCableConnected
2175 && !(STATUS & STATUS_LU))
2176 {
2177 /* The driver indicates that we should bring up the link */
2178 /* Do so in 5 seconds. */
2179 e1kArmTimer(pState, pState->CTX_SUFF(pLUTimer), 5000000);
2180 /*
2181 * Change the status (but not PHY status) anyway as Windows expects
2182 * it for 82543GC.
2183 */
2184 STATUS |= STATUS_LU;
2185 }
2186 if (value & CTRL_VME)
2187 {
2188 E1kLog(("%s VLAN Mode is not supported yet!\n", INSTANCE(pState)));
2189 }
2190 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2191 INSTANCE(pState), (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2192 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2193 if (value & CTRL_MDC)
2194 {
2195 if (value & CTRL_MDIO_DIR)
2196 {
2197 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", INSTANCE(pState), !!(value & CTRL_MDIO)));
2198 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2199 Phy::writeMDIO(&pState->phy, !!(value & CTRL_MDIO));
2200 }
2201 else
2202 {
2203 if (Phy::readMDIO(&pState->phy))
2204 value |= CTRL_MDIO;
2205 else
2206 value &= ~CTRL_MDIO;
2207 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2208 INSTANCE(pState), !!(value & CTRL_MDIO)));
2209 }
2210 }
2211 rc = e1kRegWriteDefault(pState, offset, index, value);
2212 }
2213
2214 return rc;
2215}
2216
2217/**
2218 * Write handler for EEPROM/Flash Control/Data register.
2219 *
2220 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2221 *
2222 * @param pState The device state structure.
2223 * @param offset Register offset in memory-mapped frame.
2224 * @param index Register index in register array.
2225 * @param value The value to store.
2226 * @param mask Used to implement partial writes (8 and 16-bit).
2227 * @thread EMT
2228 */
2229static int e1kRegWriteEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2230{
2231#ifdef IN_RING3
2232 /* So far we are conserned with lower byte only */
2233 if ((EECD & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2234 {
2235 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2236 /* Note: 82543GC does not need to request EEPROM access */
2237 STAM_PROFILE_ADV_START(&pState->StatEEPROMWrite, a);
2238 pState->eeprom.write(value & EECD_EE_WIRES);
2239 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMWrite, a);
2240 }
2241 if (value & EECD_EE_REQ)
2242 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2243 else
2244 EECD &= ~EECD_EE_GNT;
2245 //e1kRegWriteDefault(pState, offset, index, value );
2246
2247 return VINF_SUCCESS;
2248#else /* !IN_RING3 */
2249 return VINF_IOM_HC_MMIO_WRITE;
2250#endif /* !IN_RING3 */
2251}
2252
2253/**
2254 * Read handler for EEPROM/Flash Control/Data register.
2255 *
2256 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2257 *
2258 * @returns VBox status code.
2259 *
2260 * @param pState The device state structure.
2261 * @param offset Register offset in memory-mapped frame.
2262 * @param index Register index in register array.
2263 * @param mask Used to implement partial reads (8 and 16-bit).
2264 * @thread EMT
2265 */
2266static int e1kRegReadEECD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2267{
2268#ifdef IN_RING3
2269 uint32_t value;
2270 int rc = e1kRegReadDefault(pState, offset, index, &value);
2271 if (RT_SUCCESS(rc))
2272 {
2273 if ((value & EECD_EE_GNT) || pState->eChip == E1K_CHIP_82543GC)
2274 {
2275 /* Note: 82543GC does not need to request EEPROM access */
2276 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2277 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2278 value |= pState->eeprom.read();
2279 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2280 }
2281 *pu32Value = value;
2282 }
2283
2284 return rc;
2285#else /* !IN_RING3 */
2286 return VINF_IOM_HC_MMIO_READ;
2287#endif /* !IN_RING3 */
2288}
2289
2290/**
2291 * Write handler for EEPROM Read register.
2292 *
2293 * Handles EEPROM word access requests, reads EEPROM and stores the result
2294 * into DATA field.
2295 *
2296 * @param pState The device state structure.
2297 * @param offset Register offset in memory-mapped frame.
2298 * @param index Register index in register array.
2299 * @param value The value to store.
2300 * @param mask Used to implement partial writes (8 and 16-bit).
2301 * @thread EMT
2302 */
2303static int e1kRegWriteEERD(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2304{
2305#ifdef IN_RING3
2306 /* Make use of 'writable' and 'readable' masks. */
2307 e1kRegWriteDefault(pState, offset, index, value);
2308 /* DONE and DATA are set only if read was triggered by START. */
2309 if (value & EERD_START)
2310 {
2311 uint16_t tmp;
2312 STAM_PROFILE_ADV_START(&pState->StatEEPROMRead, a);
2313 if (pState->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2314 SET_BITS(EERD, DATA, tmp);
2315 EERD |= EERD_DONE;
2316 STAM_PROFILE_ADV_STOP(&pState->StatEEPROMRead, a);
2317 }
2318
2319 return VINF_SUCCESS;
2320#else /* !IN_RING3 */
2321 return VINF_IOM_HC_MMIO_WRITE;
2322#endif /* !IN_RING3 */
2323}
2324
2325
2326/**
2327 * Write handler for MDI Control register.
2328 *
2329 * Handles PHY read/write requests; forwards requests to internal PHY device.
2330 *
2331 * @param pState The device state structure.
2332 * @param offset Register offset in memory-mapped frame.
2333 * @param index Register index in register array.
2334 * @param value The value to store.
2335 * @param mask Used to implement partial writes (8 and 16-bit).
2336 * @thread EMT
2337 */
2338static int e1kRegWriteMDIC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2339{
2340 if (value & MDIC_INT_EN)
2341 {
2342 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2343 INSTANCE(pState)));
2344 }
2345 else if (value & MDIC_READY)
2346 {
2347 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2348 INSTANCE(pState)));
2349 }
2350 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2351 {
2352 E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
2353 INSTANCE(pState), GET_BITS_V(value, MDIC, PHY)));
2354 }
2355 else
2356 {
2357 /* Store the value */
2358 e1kRegWriteDefault(pState, offset, index, value);
2359 STAM_COUNTER_INC(&pState->StatPHYAccesses);
2360 /* Forward op to PHY */
2361 if (value & MDIC_OP_READ)
2362 SET_BITS(MDIC, DATA, Phy::readRegister(&pState->phy, GET_BITS_V(value, MDIC, REG)));
2363 else
2364 Phy::writeRegister(&pState->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2365 /* Let software know that we are done */
2366 MDIC |= MDIC_READY;
2367 }
2368
2369 return VINF_SUCCESS;
2370}
2371
2372/**
2373 * Write handler for Interrupt Cause Read register.
2374 *
2375 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2376 *
2377 * @param pState The device state structure.
2378 * @param offset Register offset in memory-mapped frame.
2379 * @param index Register index in register array.
2380 * @param value The value to store.
2381 * @param mask Used to implement partial writes (8 and 16-bit).
2382 * @thread EMT
2383 */
2384static int e1kRegWriteICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2385{
2386 ICR &= ~value;
2387
2388 return VINF_SUCCESS;
2389}
2390
2391/**
2392 * Read handler for Interrupt Cause Read register.
2393 *
2394 * Reading this register acknowledges all interrupts.
2395 *
2396 * @returns VBox status code.
2397 *
2398 * @param pState The device state structure.
2399 * @param offset Register offset in memory-mapped frame.
2400 * @param index Register index in register array.
2401 * @param mask Not used.
2402 * @thread EMT
2403 */
2404static int e1kRegReadICR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2405{
2406 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_READ);
2407 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2408 return rc;
2409
2410 uint32_t value = 0;
2411 rc = e1kRegReadDefault(pState, offset, index, &value);
2412 if (RT_SUCCESS(rc))
2413 {
2414 if (value)
2415 {
2416 /*
2417 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2418 * with disabled interrupts.
2419 */
2420 //if (IMS)
2421 if (1)
2422 {
2423 /*
2424 * Interrupts were enabled -- we are supposedly at the very
2425 * beginning of interrupt handler
2426 */
2427 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2428 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", INSTANCE(pState), ICR));
2429 /* Clear all pending interrupts */
2430 ICR = 0;
2431 pState->fIntRaised = false;
2432 /* Lower(0) INTA(0) */
2433 //PDMDevHlpPCISetIrqNoWait(pState->CTX_SUFF(pDevIns), 0, 0);
2434 //e1kMutexRelease(pState);
2435 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2436 //e1kMutexAcquire(pState, RT_SRC_POS);
2437
2438 pState->u64AckedAt = TMTimerGet(pState->CTX_SUFF(pIntTimer));
2439 if (pState->fIntMaskUsed)
2440 pState->fDelayInts = true;
2441 }
2442 else
2443 {
2444 /*
2445 * Interrupts are disabled -- in windows guests ICR read is done
2446 * just before re-enabling interrupts
2447 */
2448 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
2449 }
2450 }
2451 *pu32Value = value;
2452 }
2453 e1kCsLeave(pState);
2454
2455 return rc;
2456}
2457
2458/**
2459 * Write handler for Interrupt Cause Set register.
2460 *
2461 * Bits corresponding to 1s in 'value' will be set in ICR register.
2462 *
2463 * @param pState The device state structure.
2464 * @param offset Register offset in memory-mapped frame.
2465 * @param index Register index in register array.
2466 * @param value The value to store.
2467 * @param mask Used to implement partial writes (8 and 16-bit).
2468 * @thread EMT
2469 */
2470static int e1kRegWriteICS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2471{
2472 E1K_INC_ISTAT_CNT(pState->uStatIntICS);
2473 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, value & s_e1kRegMap[ICS_IDX].writable);
2474}
2475
2476/**
2477 * Write handler for Interrupt Mask Set register.
2478 *
2479 * Will trigger pending interrupts.
2480 *
2481 * @param pState The device state structure.
2482 * @param offset Register offset in memory-mapped frame.
2483 * @param index Register index in register array.
2484 * @param value The value to store.
2485 * @param mask Used to implement partial writes (8 and 16-bit).
2486 * @thread EMT
2487 */
2488static int e1kRegWriteIMS(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2489{
2490 IMS |= value;
2491 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2492 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", INSTANCE(pState)));
2493 /* Mask changes, we need to raise pending interrupts. */
2494 if ((ICR & IMS) && !pState->fLocked)
2495 {
2496 E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
2497 INSTANCE(pState), ICR));
2498 //TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
2499 // TMTimerGet(pState->CTX_SUFF(pIntTimer)));
2500 e1kRaiseInterrupt(pState, VERR_SEM_BUSY);
2501 }
2502
2503 return VINF_SUCCESS;
2504}
2505
2506/**
2507 * Write handler for Interrupt Mask Clear register.
2508 *
2509 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2510 *
2511 * @param pState The device state structure.
2512 * @param offset Register offset in memory-mapped frame.
2513 * @param index Register index in register array.
2514 * @param value The value to store.
2515 * @param mask Used to implement partial writes (8 and 16-bit).
2516 * @thread EMT
2517 */
2518static int e1kRegWriteIMC(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2519{
2520 int rc = e1kCsEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2521 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2522 return rc;
2523 if (pState->fIntRaised)
2524 {
2525 /*
2526 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2527 * Windows to freeze since it may receive an interrupt while still in the very beginning
2528 * of interrupt handler.
2529 */
2530 E1K_INC_ISTAT_CNT(pState->uStatIntLower);
2531 STAM_COUNTER_INC(&pState->StatIntsPrevented);
2532 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2533 /* Lower(0) INTA(0) */
2534 PDMDevHlpPCISetIrq(pState->CTX_SUFF(pDevIns), 0, 0);
2535 pState->fIntRaised = false;
2536 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", INSTANCE(pState), ICR));
2537 }
2538 IMS &= ~value;
2539 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", INSTANCE(pState)));
2540 e1kCsLeave(pState);
2541
2542 return VINF_SUCCESS;
2543}
2544
2545/**
2546 * Write handler for Receive Control register.
2547 *
2548 * @param pState The device state structure.
2549 * @param offset Register offset in memory-mapped frame.
2550 * @param index Register index in register array.
2551 * @param value The value to store.
2552 * @param mask Used to implement partial writes (8 and 16-bit).
2553 * @thread EMT
2554 */
2555static int e1kRegWriteRCTL(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2556{
2557 e1kRegWriteDefault(pState, offset, index, value);
2558 pState->u16RxBSize = 2048 >> GET_BITS(RCTL, BSIZE);
2559 if (RCTL & RCTL_BSEX)
2560 pState->u16RxBSize *= 16;
2561 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d\n",
2562 INSTANCE(pState), pState->u16RxBSize));
2563
2564 return VINF_SUCCESS;
2565}
2566
2567/**
2568 * Write handler for Packet Buffer Allocation register.
2569 *
2570 * TXA = 64 - RXA.
2571 *
2572 * @param pState The device state structure.
2573 * @param offset Register offset in memory-mapped frame.
2574 * @param index Register index in register array.
2575 * @param value The value to store.
2576 * @param mask Used to implement partial writes (8 and 16-bit).
2577 * @thread EMT
2578 */
2579static int e1kRegWritePBA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2580{
2581 e1kRegWriteDefault(pState, offset, index, value);
2582 PBA_st->txa = 64 - PBA_st->rxa;
2583
2584 return VINF_SUCCESS;
2585}
2586
2587/**
2588 * Write handler for Receive Descriptor Tail register.
2589 *
2590 * @remarks Write into RDT forces switch to HC and signal to
2591 * e1kNetworkDown_WaitReceiveAvail().
2592 *
2593 * @returns VBox status code.
2594 *
2595 * @param pState The device state structure.
2596 * @param offset Register offset in memory-mapped frame.
2597 * @param index Register index in register array.
2598 * @param value The value to store.
2599 * @param mask Used to implement partial writes (8 and 16-bit).
2600 * @thread EMT
2601 */
2602static int e1kRegWriteRDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2603{
2604#ifndef IN_RING3
2605 /* XXX */
2606// return VINF_IOM_HC_MMIO_WRITE;
2607#endif
2608 int rc = e1kCsRxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
2609 if (RT_LIKELY(rc == VINF_SUCCESS))
2610 {
2611 E1kLog(("%s e1kRegWriteRDT\n", INSTANCE(pState)));
2612 rc = e1kRegWriteDefault(pState, offset, index, value);
2613 e1kCsRxLeave(pState);
2614 if (RT_SUCCESS(rc))
2615 {
2616#ifdef IN_RING3 /** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well. (reduces latency) */
2617 /* Signal that we have more receive descriptors avalable. */
2618 e1kWakeupReceive(pState->CTX_SUFF(pDevIns));
2619#else
2620 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pCanRxQueue));
2621 if (pItem)
2622 PDMQueueInsert(pState->CTX_SUFF(pCanRxQueue), pItem);
2623#endif
2624 }
2625 }
2626 return rc;
2627}
2628
2629/**
2630 * Write handler for Receive Delay Timer register.
2631 *
2632 * @param pState The device state structure.
2633 * @param offset Register offset in memory-mapped frame.
2634 * @param index Register index in register array.
2635 * @param value The value to store.
2636 * @param mask Used to implement partial writes (8 and 16-bit).
2637 * @thread EMT
2638 */
2639static int e1kRegWriteRDTR(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
2640{
2641 e1kRegWriteDefault(pState, offset, index, value);
2642 if (value & RDTR_FPD)
2643 {
2644 /* Flush requested, cancel both timers and raise interrupt */
2645#ifdef E1K_USE_RX_TIMERS
2646 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2647 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2648#endif
2649 E1K_INC_ISTAT_CNT(pState->uStatIntRDTR);
2650 return e1kRaiseInterrupt(pState, VINF_IOM_HC_MMIO_WRITE, ICR_RXT0);
2651 }
2652
2653 return VINF_SUCCESS;
2654}
2655
2656DECLINLINE(uint32_t) e1kGetTxLen(E1KSTATE* pState)
2657{
2658 /**
2659 * Make sure TDT won't change during computation. EMT may modify TDT at
2660 * any moment.
2661 */
2662 uint32_t tdt = TDT;
2663 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
2664}
2665
2666#ifdef IN_RING3
2667#ifdef E1K_USE_TX_TIMERS
2668
2669/**
2670 * Transmit Interrupt Delay Timer handler.
2671 *
2672 * @remarks We only get here when the timer expires.
2673 *
2674 * @param pDevIns Pointer to device instance structure.
2675 * @param pTimer Pointer to the timer.
2676 * @param pvUser NULL.
2677 * @thread EMT
2678 */
2679static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2680{
2681 E1KSTATE *pState = (E1KSTATE *)pvUser;
2682
2683 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2684 {
2685 E1K_INC_ISTAT_CNT(pState->uStatTID);
2686 /* Cancel absolute delay timer as we have already got attention */
2687#ifndef E1K_NO_TAD
2688 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
2689#endif /* E1K_NO_TAD */
2690 e1kRaiseInterrupt(pState, ICR_TXDW);
2691 e1kMutexRelease(pState);
2692 }
2693}
2694
2695/**
2696 * Transmit Absolute Delay Timer handler.
2697 *
2698 * @remarks We only get here when the timer expires.
2699 *
2700 * @param pDevIns Pointer to device instance structure.
2701 * @param pTimer Pointer to the timer.
2702 * @param pvUser NULL.
2703 * @thread EMT
2704 */
2705static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2706{
2707 E1KSTATE *pState = (E1KSTATE *)pvUser;
2708
2709 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2710 {
2711 E1K_INC_ISTAT_CNT(pState->uStatTAD);
2712 /* Cancel interrupt delay timer as we have already got attention */
2713 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
2714 e1kRaiseInterrupt(pState, ICR_TXDW);
2715 e1kMutexRelease(pState);
2716 }
2717}
2718
2719#endif /* E1K_USE_TX_TIMERS */
2720#ifdef E1K_USE_RX_TIMERS
2721
2722/**
2723 * Receive Interrupt Delay Timer handler.
2724 *
2725 * @remarks We only get here when the timer expires.
2726 *
2727 * @param pDevIns Pointer to device instance structure.
2728 * @param pTimer Pointer to the timer.
2729 * @param pvUser NULL.
2730 * @thread EMT
2731 */
2732static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2733{
2734 E1KSTATE *pState = (E1KSTATE *)pvUser;
2735
2736 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2737 {
2738 E1K_INC_ISTAT_CNT(pState->uStatRID);
2739 /* Cancel absolute delay timer as we have already got attention */
2740 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
2741 e1kRaiseInterrupt(pState, ICR_RXT0);
2742 e1kMutexRelease(pState);
2743 }
2744}
2745
2746/**
2747 * Receive Absolute Delay Timer handler.
2748 *
2749 * @remarks We only get here when the timer expires.
2750 *
2751 * @param pDevIns Pointer to device instance structure.
2752 * @param pTimer Pointer to the timer.
2753 * @param pvUser NULL.
2754 * @thread EMT
2755 */
2756static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2757{
2758 E1KSTATE *pState = (E1KSTATE *)pvUser;
2759
2760 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2761 {
2762 E1K_INC_ISTAT_CNT(pState->uStatRAD);
2763 /* Cancel interrupt delay timer as we have already got attention */
2764 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
2765 e1kRaiseInterrupt(pState, ICR_RXT0);
2766 e1kMutexRelease(pState);
2767 }
2768}
2769
2770#endif /* E1K_USE_RX_TIMERS */
2771
2772/**
2773 * Late Interrupt Timer handler.
2774 *
2775 * @param pDevIns Pointer to device instance structure.
2776 * @param pTimer Pointer to the timer.
2777 * @param pvUser NULL.
2778 * @thread EMT
2779 */
2780static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2781{
2782 E1KSTATE *pState = (E1KSTATE *)pvUser;
2783
2784 STAM_PROFILE_ADV_START(&pState->StatLateIntTimer, a);
2785 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2786 {
2787 STAM_COUNTER_INC(&pState->StatLateInts);
2788 E1K_INC_ISTAT_CNT(pState->uStatIntLate);
2789#if 0
2790 if (pState->iStatIntLost > -100)
2791 pState->iStatIntLost--;
2792#endif
2793 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, 0);
2794 e1kMutexRelease(pState);
2795 }
2796 STAM_PROFILE_ADV_STOP(&pState->StatLateIntTimer, a);
2797}
2798
2799/**
2800 * Link Up Timer handler.
2801 *
2802 * @param pDevIns Pointer to device instance structure.
2803 * @param pTimer Pointer to the timer.
2804 * @param pvUser NULL.
2805 * @thread EMT
2806 */
2807static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2808{
2809 E1KSTATE *pState = (E1KSTATE *)pvUser;
2810
2811 if (RT_LIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) == VINF_SUCCESS))
2812 {
2813 STATUS |= STATUS_LU;
2814 Phy::setLinkStatus(&pState->phy, true);
2815 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
2816 e1kMutexRelease(pState);
2817 }
2818}
2819
2820#endif /* IN_RING3 */
2821
2822/**
2823 * Sets up the GSO context according to the TSE new context descriptor.
2824 *
2825 * @param pGso The GSO context to setup.
2826 * @param pCtx The context descriptor.
2827 */
2828DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
2829{
2830 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
2831
2832 /*
2833 * See if the context descriptor describes something that could be TCP or
2834 * UDP over IPv[46].
2835 */
2836 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
2837 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
2838 {
2839 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
2840 return;
2841 }
2842 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
2843 {
2844 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
2845 return;
2846 }
2847 if (RT_UNLIKELY( pCtx->dw2.fTCP
2848 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
2849 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
2850 {
2851 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
2852 return;
2853 }
2854
2855 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
2856 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
2857 {
2858 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
2859 return;
2860 }
2861
2862 /* IPv4 checksum offset. */
2863 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
2864 {
2865 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
2866 return;
2867 }
2868
2869 /* TCP/UDP checksum offsets. */
2870 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
2871 != ( pCtx->dw2.fTCP
2872 ? RT_UOFFSETOF(RTNETTCP, th_sum)
2873 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
2874 {
2875 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
2876 return;
2877 }
2878
2879 /*
2880 * Because of internal networking using a 16-bit size field for GSO context
2881 * pluss frame, we have to make sure we don't exceed this.
2882 */
2883 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
2884 {
2885 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
2886 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
2887 return;
2888 }
2889
2890 /*
2891 * We're good for now - we'll do more checks when seeing the data.
2892 * So, figure the type of offloading and setup the context.
2893 */
2894 if (pCtx->dw2.fIP)
2895 {
2896 if (pCtx->dw2.fTCP)
2897 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
2898 else
2899 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
2900 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
2901 * this yet it seems)... */
2902 }
2903 else
2904 {
2905 if (pCtx->dw2.fTCP)
2906 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
2907 else
2908 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
2909 }
2910 pGso->offHdr1 = pCtx->ip.u8CSS;
2911 pGso->offHdr2 = pCtx->tu.u8CSS;
2912 pGso->cbHdrs = pCtx->dw3.u8HDRLEN;
2913 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
2914 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
2915 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdr1=%#x hdr2=%#x %s\n",
2916 pGso->cbMaxSeg, pGso->cbHdrs, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
2917}
2918
2919/**
2920 * Checks if we can use GSO processing for the current TSE frame.
2921 *
2922 * @param pGso The GSO context.
2923 * @param pData The first data descriptor of the frame.
2924 * @param pCtx The TSO context descriptor.
2925 */
2926DECLINLINE(bool) e1kCanDoGso(PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
2927{
2928 if (!pData->cmd.fTSE)
2929 {
2930 E1kLog2(("e1kCanDoGso: !TSE\n"));
2931 return false;
2932 }
2933 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
2934 {
2935 E1kLog(("e1kCanDoGso: VLE\n"));
2936 return false;
2937 }
2938
2939 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
2940 {
2941 case PDMNETWORKGSOTYPE_IPV4_TCP:
2942 case PDMNETWORKGSOTYPE_IPV4_UDP:
2943 if (!pData->dw3.fIXSM)
2944 {
2945 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
2946 return false;
2947 }
2948 if (!pData->dw3.fTXSM)
2949 {
2950 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
2951 return false;
2952 }
2953 /** @todo what more check should we perform here? Ethernet frame type? */
2954 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
2955 return true;
2956
2957 case PDMNETWORKGSOTYPE_IPV6_TCP:
2958 case PDMNETWORKGSOTYPE_IPV6_UDP:
2959 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
2960 {
2961 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
2962 return false;
2963 }
2964 if (!pData->dw3.fTXSM)
2965 {
2966 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
2967 return false;
2968 }
2969 /** @todo what more check should we perform here? Ethernet frame type? */
2970 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
2971 return true;
2972
2973 default:
2974 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
2975 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
2976 return false;
2977 }
2978}
2979
2980/**
2981 * Frees the current xmit buffer.
2982 *
2983 * @param pState The device state structure.
2984 */
2985static void e1kXmitFreeBuf(E1KSTATE *pState)
2986{
2987 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
2988 if (pSg)
2989 {
2990 pState->CTX_SUFF(pTxSg) = NULL;
2991
2992 if (pSg->pvAllocator != pState)
2993 {
2994 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
2995 if (pDrv)
2996 pDrv->pfnFreeBuf(pDrv, pSg);
2997 }
2998 else
2999 {
3000 /* loopback */
3001 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3002 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3003 pSg->fFlags = 0;
3004 pSg->pvAllocator = NULL;
3005 }
3006 }
3007}
3008
3009/**
3010 * Allocates a xmit buffer.
3011 *
3012 * Presently this will always return a buffer. Later on we'll have a
3013 * out-of-buffer mechanism in place where the driver calls us back when buffers
3014 * becomes available.
3015 *
3016 * @returns See PDMINETWORKUP::pfnAllocBuf.
3017 * @param pState The device state structure.
3018 * @param cbMin The minimum frame size.
3019 * @param fExactSize Whether cbMin is exact or if we have to max it
3020 * out to the max MTU size.
3021 * @param fGso Whether this is a GSO frame or not.
3022 */
3023DECLINLINE(int) e1kXmitAllocBuf(E1KSTATE *pState, size_t cbMin, bool fExactSize, bool fGso)
3024{
3025 /* Adjust cbMin if necessary. */
3026 if (!fExactSize)
3027 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3028
3029 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3030 if (RT_UNLIKELY(pState->CTX_SUFF(pTxSg)))
3031 e1kXmitFreeBuf(pState);
3032 Assert(pState->CTX_SUFF(pTxSg) == NULL);
3033
3034 /*
3035 * Allocate the buffer.
3036 */
3037 PPDMSCATTERGATHER pSg;
3038 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3039 {
3040 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3041 if (RT_UNLIKELY(!pDrv))
3042 return VERR_NET_DOWN;
3043 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pState->GsoCtx : NULL, &pSg);
3044 if (RT_FAILURE(rc))
3045 return rc;
3046 }
3047 else
3048 {
3049 /* Create a loopback using the fallback buffer and preallocated SG. */
3050 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3051 pSg = &pState->uTxFallback.Sg;
3052 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3053 pSg->cbUsed = 0;
3054 pSg->cbAvailable = 0;
3055 pSg->pvAllocator = pState;
3056 pSg->pvUser = NULL; /* No GSO here. */
3057 pSg->cSegs = 1;
3058 pSg->aSegs[0].pvSeg = pState->aTxPacketFallback;
3059 pSg->aSegs[0].cbSeg = sizeof(pState->aTxPacketFallback);
3060 }
3061
3062 pState->CTX_SUFF(pTxSg) = pSg;
3063 return VINF_SUCCESS;
3064}
3065
3066/**
3067 * Checks if it's a GSO buffer or not.
3068 *
3069 * @returns true / false.
3070 * @param pTxSg The scatter / gather buffer.
3071 */
3072DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3073{
3074#if 0
3075 if (!pTxSg)
3076 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3077 if (pTxSg && pTxSg->pvUser)
3078 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3079#endif
3080 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3081}
3082
3083/**
3084 * Load transmit descriptor from guest memory.
3085 *
3086 * @param pState The device state structure.
3087 * @param pDesc Pointer to descriptor union.
3088 * @param addr Physical address in guest context.
3089 * @thread E1000_TX
3090 */
3091DECLINLINE(void) e1kLoadDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3092{
3093 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3094}
3095
3096/**
3097 * Write back transmit descriptor to guest memory.
3098 *
3099 * @param pState The device state structure.
3100 * @param pDesc Pointer to descriptor union.
3101 * @param addr Physical address in guest context.
3102 * @thread E1000_TX
3103 */
3104DECLINLINE(void) e1kWriteBackDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3105{
3106 /* Only the last half of the descriptor has to be written back. */
3107 e1kPrintTDesc(pState, pDesc, "^^^");
3108 PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3109}
3110
3111/**
3112 * Transmit complete frame.
3113 *
3114 * @remarks We skip the FCS since we're not responsible for sending anything to
3115 * a real ethernet wire.
3116 *
3117 * @param pState The device state structure.
3118 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3119 * @thread E1000_TX
3120 */
3121static void e1kTransmitFrame(E1KSTATE* pState, bool fOnWorkerThread)
3122{
3123 PPDMSCATTERGATHER pSg = pState->CTX_SUFF(pTxSg);
3124 uint32_t const cbFrame = pSg ? (size_t)pSg->cbUsed : 0;
3125 Assert(!pSg || pSg->cSegs == 1);
3126
3127/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
3128 "%.*Rhxd\n"
3129 "%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
3130 INSTANCE(pState), cbFrame, pSg->aSegs[0].pvSeg, INSTANCE(pState)));*/
3131
3132 if (cbFrame > 70) /* unqualified guess */
3133 pState->led.Asserted.s.fWriting = pState->led.Actual.s.fWriting = 1;
3134
3135 /* Update the stats */
3136 E1K_INC_CNT32(TPT);
3137 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3138 E1K_INC_CNT32(GPTC);
3139 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3140 E1K_INC_CNT32(BPTC);
3141 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3142 E1K_INC_CNT32(MPTC);
3143 /* Update octet transmit counter */
3144 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3145 if (pState->CTX_SUFF(pDrv))
3146 STAM_REL_COUNTER_ADD(&pState->StatTransmitBytes, cbFrame);
3147 if (cbFrame == 64)
3148 E1K_INC_CNT32(PTC64);
3149 else if (cbFrame < 128)
3150 E1K_INC_CNT32(PTC127);
3151 else if (cbFrame < 256)
3152 E1K_INC_CNT32(PTC255);
3153 else if (cbFrame < 512)
3154 E1K_INC_CNT32(PTC511);
3155 else if (cbFrame < 1024)
3156 E1K_INC_CNT32(PTC1023);
3157 else
3158 E1K_INC_CNT32(PTC1522);
3159
3160 E1K_INC_ISTAT_CNT(pState->uStatTxFrm);
3161
3162 /*
3163 * Dump and send the packet.
3164 */
3165 int rc = VERR_NET_DOWN;
3166 if (pSg && pSg->pvAllocator != pState)
3167 {
3168 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3169
3170 pState->CTX_SUFF(pTxSg) = NULL;
3171 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3172 if (pDrv)
3173 {
3174 /* Release critical section to avoid deadlock in CanReceive */
3175 //e1kCsLeave(pState);
3176 e1kMutexRelease(pState);
3177 STAM_PROFILE_START(&pState->StatTransmitSend, a);
3178 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3179 STAM_PROFILE_STOP(&pState->StatTransmitSend, a);
3180 e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
3181 //e1kCsEnter(pState, RT_SRC_POS);
3182 }
3183 }
3184 else if (pSg)
3185 {
3186 Assert(pSg->aSegs[0].pvSeg == pState->aTxPacketFallback);
3187 e1kPacketDump(pState, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3188
3189 /** @todo do we actually need to check that we're in loopback mode here? */
3190 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3191 {
3192 E1KRXDST status;
3193 RT_ZERO(status);
3194 status.fPIF = true;
3195 e1kHandleRxPacket(pState, pSg->aSegs[0].pvSeg, cbFrame, status);
3196 rc = VINF_SUCCESS;
3197 }
3198 e1kXmitFreeBuf(pState);
3199 }
3200 else
3201 rc = VERR_NET_DOWN;
3202 if (RT_FAILURE(rc))
3203 {
3204 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3205 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3206 }
3207
3208 pState->led.Actual.s.fWriting = 0;
3209}
3210
3211/**
3212 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3213 *
3214 * @param pState The device state structure.
3215 * @param pPkt Pointer to the packet.
3216 * @param u16PktLen Total length of the packet.
3217 * @param cso Offset in packet to write checksum at.
3218 * @param css Offset in packet to start computing
3219 * checksum from.
3220 * @param cse Offset in packet to stop computing
3221 * checksum at.
3222 * @thread E1000_TX
3223 */
3224static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3225{
3226 if (cso > u16PktLen)
3227 {
3228 E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
3229 INSTANCE(pState), cso, u16PktLen));
3230 return;
3231 }
3232
3233 if (cse == 0)
3234 cse = u16PktLen - 1;
3235 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
3236 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", INSTANCE(pState),
3237 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
3238 *(uint16_t*)(pPkt + cso) = u16ChkSum;
3239}
3240
3241/**
3242 * Add a part of descriptor's buffer to transmit frame.
3243 *
3244 * @remarks data.u64BufAddr is used uncoditionally for both data
3245 * and legacy descriptors since it is identical to
3246 * legacy.u64BufAddr.
3247 *
3248 * @param pState The device state structure.
3249 * @param pDesc Pointer to the descriptor to transmit.
3250 * @param u16Len Length of buffer to the end of segment.
3251 * @param fSend Force packet sending.
3252 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3253 * @thread E1000_TX
3254 */
3255static void e1kFallbackAddSegment(E1KSTATE* pState, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
3256{
3257 /* TCP header being transmitted */
3258 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
3259 (pState->aTxPacketFallback + pState->contextTSE.tu.u8CSS);
3260 /* IP header being transmitted */
3261 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
3262 (pState->aTxPacketFallback + pState->contextTSE.ip.u8CSS);
3263
3264 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
3265 INSTANCE(pState), u16Len, pState->u32PayRemain, pState->u16HdrRemain, fSend));
3266 Assert(pState->u32PayRemain + pState->u16HdrRemain > 0);
3267
3268 PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), PhysAddr,
3269 pState->aTxPacketFallback + pState->u16TxPktLen, u16Len);
3270 E1kLog3(("%s Dump of the segment:\n"
3271 "%.*Rhxd\n"
3272 "%s --- End of dump ---\n",
3273 INSTANCE(pState), u16Len, pState->aTxPacketFallback + pState->u16TxPktLen, INSTANCE(pState)));
3274 pState->u16TxPktLen += u16Len;
3275 E1kLog3(("%s e1kFallbackAddSegment: pState->u16TxPktLen=%x\n",
3276 INSTANCE(pState), pState->u16TxPktLen));
3277 if (pState->u16HdrRemain > 0)
3278 {
3279 /* The header was not complete, check if it is now */
3280 if (u16Len >= pState->u16HdrRemain)
3281 {
3282 /* The rest is payload */
3283 u16Len -= pState->u16HdrRemain;
3284 pState->u16HdrRemain = 0;
3285 /* Save partial checksum and flags */
3286 pState->u32SavedCsum = pTcpHdr->chksum;
3287 pState->u16SavedFlags = pTcpHdr->hdrlen_flags;
3288 /* Clear FIN and PSH flags now and set them only in the last segment */
3289 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
3290 }
3291 else
3292 {
3293 /* Still not */
3294 pState->u16HdrRemain -= u16Len;
3295 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
3296 INSTANCE(pState), pState->u16HdrRemain));
3297 return;
3298 }
3299 }
3300
3301 pState->u32PayRemain -= u16Len;
3302
3303 if (fSend)
3304 {
3305 /* Leave ethernet header intact */
3306 /* IP Total Length = payload + headers - ethernet header */
3307 pIpHdr->total_len = htons(pState->u16TxPktLen - pState->contextTSE.ip.u8CSS);
3308 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
3309 INSTANCE(pState), ntohs(pIpHdr->total_len)));
3310 /* Update IP Checksum */
3311 pIpHdr->chksum = 0;
3312 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3313 pState->contextTSE.ip.u8CSO,
3314 pState->contextTSE.ip.u8CSS,
3315 pState->contextTSE.ip.u16CSE);
3316
3317 /* Update TCP flags */
3318 /* Restore original FIN and PSH flags for the last segment */
3319 if (pState->u32PayRemain == 0)
3320 {
3321 pTcpHdr->hdrlen_flags = pState->u16SavedFlags;
3322 E1K_INC_CNT32(TSCTC);
3323 }
3324 /* Add TCP length to partial pseudo header sum */
3325 uint32_t csum = pState->u32SavedCsum
3326 + htons(pState->u16TxPktLen - pState->contextTSE.tu.u8CSS);
3327 while (csum >> 16)
3328 csum = (csum >> 16) + (csum & 0xFFFF);
3329 pTcpHdr->chksum = csum;
3330 /* Compute final checksum */
3331 e1kInsertChecksum(pState, pState->aTxPacketFallback, pState->u16TxPktLen,
3332 pState->contextTSE.tu.u8CSO,
3333 pState->contextTSE.tu.u8CSS,
3334 pState->contextTSE.tu.u16CSE);
3335
3336 /*
3337 * Transmit it. If we've use the SG already, allocate a new one before
3338 * we copy of the data.
3339 */
3340 if (!pState->CTX_SUFF(pTxSg))
3341 e1kXmitAllocBuf(pState, pState->u16TxPktLen, true /*fExactSize*/, false /*fGso*/);
3342 if (pState->CTX_SUFF(pTxSg))
3343 {
3344 Assert(pState->u16TxPktLen <= pState->CTX_SUFF(pTxSg)->cbAvailable);
3345 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3346 if (pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pState->aTxPacketFallback)
3347 memcpy(pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->aTxPacketFallback, pState->u16TxPktLen);
3348 pState->CTX_SUFF(pTxSg)->cbUsed = pState->u16TxPktLen;
3349 pState->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pState->u16TxPktLen;
3350 }
3351 e1kTransmitFrame(pState, fOnWorkerThread);
3352
3353 /* Update Sequence Number */
3354 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pState->u16TxPktLen
3355 - pState->contextTSE.dw3.u8HDRLEN);
3356 /* Increment IP identification */
3357 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
3358 }
3359}
3360
3361/**
3362 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
3363 * frame.
3364 *
3365 * We construct the frame in the fallback buffer first and the copy it to the SG
3366 * buffer before passing it down to the network driver code.
3367 *
3368 * @returns true if the frame should be transmitted, false if not.
3369 *
3370 * @param pState The device state structure.
3371 * @param pDesc Pointer to the descriptor to transmit.
3372 * @param cbFragment Length of descriptor's buffer.
3373 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3374 * @thread E1000_TX
3375 */
3376static bool e1kFallbackAddToFrame(E1KSTATE* pState, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
3377{
3378 PPDMSCATTERGATHER pTxSg = pState->CTX_SUFF(pTxSg);
3379 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
3380 Assert(pDesc->data.cmd.fTSE);
3381 Assert(!e1kXmitIsGsoBuf(pTxSg));
3382
3383 uint16_t u16MaxPktLen = pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw3.u16MSS;
3384 Assert(u16MaxPktLen != 0);
3385 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
3386
3387 /*
3388 * Carve out segments.
3389 */
3390 do
3391 {
3392 /* Calculate how many bytes we have left in this TCP segment */
3393 uint32_t cb = u16MaxPktLen - pState->u16TxPktLen;
3394 if (cb > cbFragment)
3395 {
3396 /* This descriptor fits completely into current segment */
3397 cb = cbFragment;
3398 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
3399 }
3400 else
3401 {
3402 e1kFallbackAddSegment(pState, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
3403 /*
3404 * Rewind the packet tail pointer to the beginning of payload,
3405 * so we continue writing right beyond the header.
3406 */
3407 pState->u16TxPktLen = pState->contextTSE.dw3.u8HDRLEN;
3408 }
3409
3410 pDesc->data.u64BufAddr += cb;
3411 cbFragment -= cb;
3412 } while (cbFragment > 0);
3413
3414 if (pDesc->data.cmd.fEOP)
3415 {
3416 /* End of packet, next segment will contain header. */
3417 if (pState->u32PayRemain != 0)
3418 E1K_INC_CNT32(TSCTFC);
3419 pState->u16TxPktLen = 0;
3420 e1kXmitFreeBuf(pState);
3421 }
3422
3423 return false;
3424}
3425
3426
3427/**
3428 * Add descriptor's buffer to transmit frame.
3429 *
3430 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
3431 * TSE frames we cannot handle as GSO.
3432 *
3433 * @returns true on success, false on failure.
3434 *
3435 * @param pThis The device state structure.
3436 * @param PhysAddr The physical address of the descriptor buffer.
3437 * @param cbFragment Length of descriptor's buffer.
3438 * @thread E1000_TX
3439 */
3440static bool e1kAddToFrame(E1KSTATE *pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
3441{
3442 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
3443 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
3444 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
3445
3446 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
3447 {
3448 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", INSTANCE(pThis), cbNewPkt, E1K_MAX_TX_PKT_SIZE));
3449 return false;
3450 }
3451 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
3452 {
3453 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", INSTANCE(pThis), cbNewPkt, pTxSg->cbAvailable));
3454 return false;
3455 }
3456
3457 if (RT_LIKELY(pTxSg))
3458 {
3459 Assert(pTxSg->cSegs == 1);
3460 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
3461
3462 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
3463 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
3464
3465 pTxSg->cbUsed = cbNewPkt;
3466 }
3467 pThis->u16TxPktLen = cbNewPkt;
3468
3469 return true;
3470}
3471
3472
3473/**
3474 * Write the descriptor back to guest memory and notify the guest.
3475 *
3476 * @param pState The device state structure.
3477 * @param pDesc Pointer to the descriptor have been transmited.
3478 * @param addr Physical address of the descriptor in guest memory.
3479 * @thread E1000_TX
3480 */
3481static void e1kDescReport(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr)
3482{
3483 /*
3484 * We fake descriptor write-back bursting. Descriptors are written back as they are
3485 * processed.
3486 */
3487 /* Let's pretend we process descriptors. Write back with DD set. */
3488 if (pDesc->legacy.cmd.fRS || (GET_BITS(TXDCTL, WTHRESH) > 0))
3489 {
3490 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
3491 e1kWriteBackDesc(pState, pDesc, addr);
3492 if (pDesc->legacy.cmd.fEOP)
3493 {
3494#ifdef E1K_USE_TX_TIMERS
3495 if (pDesc->legacy.cmd.fIDE)
3496 {
3497 E1K_INC_ISTAT_CNT(pState->uStatTxIDE);
3498 //if (pState->fIntRaised)
3499 //{
3500 // /* Interrupt is already pending, no need for timers */
3501 // ICR |= ICR_TXDW;
3502 //}
3503 //else {
3504 /* Arm the timer to fire in TIVD usec (discard .024) */
3505 e1kArmTimer(pState, pState->CTX_SUFF(pTIDTimer), TIDV);
3506# ifndef E1K_NO_TAD
3507 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
3508 E1kLog2(("%s Checking if TAD timer is running\n",
3509 INSTANCE(pState)));
3510 if (TADV != 0 && !TMTimerIsActive(pState->CTX_SUFF(pTADTimer)))
3511 e1kArmTimer(pState, pState->CTX_SUFF(pTADTimer), TADV);
3512# endif /* E1K_NO_TAD */
3513 }
3514 else
3515 {
3516 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
3517 INSTANCE(pState)));
3518# ifndef E1K_NO_TAD
3519 /* Cancel both timers if armed and fire immediately. */
3520 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
3521# endif /* E1K_NO_TAD */
3522#endif /* E1K_USE_TX_TIMERS */
3523 E1K_INC_ISTAT_CNT(pState->uStatIntTx);
3524 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXDW);
3525#ifdef E1K_USE_TX_TIMERS
3526 }
3527#endif /* E1K_USE_TX_TIMERS */
3528 }
3529 }
3530 else
3531 {
3532 E1K_INC_ISTAT_CNT(pState->uStatTxNoRS);
3533 }
3534}
3535
3536/**
3537 * Process Transmit Descriptor.
3538 *
3539 * E1000 supports three types of transmit descriptors:
3540 * - legacy data descriptors of older format (context-less).
3541 * - data the same as legacy but providing new offloading capabilities.
3542 * - context sets up the context for following data descriptors.
3543 *
3544 * @param pState The device state structure.
3545 * @param pDesc Pointer to descriptor union.
3546 * @param addr Physical address of descriptor in guest memory.
3547 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3548 * @thread E1000_TX
3549 */
3550static void e1kXmitDesc(E1KSTATE* pState, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
3551{
3552 e1kPrintTDesc(pState, pDesc, "vvv");
3553
3554#ifdef E1K_USE_TX_TIMERS
3555 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
3556#endif /* E1K_USE_TX_TIMERS */
3557
3558 switch (e1kGetDescType(pDesc))
3559 {
3560 case E1K_DTYP_CONTEXT:
3561 if (pDesc->context.dw2.fTSE)
3562 {
3563 pState->contextTSE = pDesc->context;
3564 pState->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
3565 pState->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
3566 e1kSetupGsoCtx(&pState->GsoCtx, &pDesc->context);
3567 STAM_COUNTER_INC(&pState->StatTxDescCtxTSE);
3568 }
3569 else
3570 {
3571 pState->contextNormal = pDesc->context;
3572 STAM_COUNTER_INC(&pState->StatTxDescCtxNormal);
3573 }
3574 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
3575 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", INSTANCE(pState),
3576 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
3577 pDesc->context.ip.u8CSS,
3578 pDesc->context.ip.u8CSO,
3579 pDesc->context.ip.u16CSE,
3580 pDesc->context.tu.u8CSS,
3581 pDesc->context.tu.u8CSO,
3582 pDesc->context.tu.u16CSE));
3583 E1K_INC_ISTAT_CNT(pState->uStatDescCtx);
3584 e1kDescReport(pState, pDesc, addr);
3585 break;
3586
3587 case E1K_DTYP_DATA:
3588 {
3589 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
3590 {
3591 E1kLog2(("% Empty data descriptor, skipped.\n", INSTANCE(pState)));
3592 /** @todo Same as legacy when !TSE. See below. */
3593 break;
3594 }
3595 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
3596 &pState->StatTxDescTSEData:
3597 &pState->StatTxDescData);
3598 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3599 E1K_INC_ISTAT_CNT(pState->uStatDescDat);
3600
3601 /*
3602 * First fragment: Allocate new buffer and save the IXSM and TXSM
3603 * packet options as these are only valid in the first fragment.
3604 */
3605 if (pState->u16TxPktLen == 0)
3606 {
3607 pState->fIPcsum = pDesc->data.dw3.fIXSM;
3608 pState->fTCPcsum = pDesc->data.dw3.fTXSM;
3609 E1kLog2(("%s Saving checksum flags:%s%s; \n", INSTANCE(pState),
3610 pState->fIPcsum ? " IP" : "",
3611 pState->fTCPcsum ? " TCP/UDP" : ""));
3612 if (e1kCanDoGso(&pState->GsoCtx, &pDesc->data, &pState->contextTSE))
3613 e1kXmitAllocBuf(pState, pState->contextTSE.dw2.u20PAYLEN + pState->contextTSE.dw3.u8HDRLEN,
3614 true /*fExactSize*/, true /*fGso*/);
3615 else
3616 e1kXmitAllocBuf(pState, pState->contextTSE.dw3.u16MSS + pState->contextTSE.dw3.u8HDRLEN,
3617 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
3618 /** @todo Is there any way to indicating errors other than collisions? Like
3619 * VERR_NET_DOWN. */
3620 }
3621
3622 /*
3623 * Add the descriptor data to the frame. If the frame is complete,
3624 * transmit it and reset the u16TxPktLen field.
3625 */
3626 if (e1kXmitIsGsoBuf(pState->CTX_SUFF(pTxSg)))
3627 {
3628 STAM_COUNTER_INC(&pState->StatTxPathGSO);
3629 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3630 if (pDesc->data.cmd.fEOP)
3631 {
3632 if ( fRc
3633 && pState->CTX_SUFF(pTxSg)
3634 && pState->CTX_SUFF(pTxSg)->cbUsed == (size_t)pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN)
3635 {
3636 e1kTransmitFrame(pState, fOnWorkerThread);
3637 E1K_INC_CNT32(TSCTC);
3638 }
3639 else
3640 {
3641 if (fRc)
3642 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , INSTANCE(pState),
3643 pState->CTX_SUFF(pTxSg), pState->CTX_SUFF(pTxSg) ? pState->CTX_SUFF(pTxSg)->cbUsed : 0,
3644 pState->contextTSE.dw3.u8HDRLEN + pState->contextTSE.dw2.u20PAYLEN));
3645 e1kXmitFreeBuf(pState);
3646 E1K_INC_CNT32(TSCTFC);
3647 }
3648 pState->u16TxPktLen = 0;
3649 }
3650 }
3651 else if (!pDesc->data.cmd.fTSE)
3652 {
3653 STAM_COUNTER_INC(&pState->StatTxPathRegular);
3654 bool fRc = e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
3655 if (pDesc->data.cmd.fEOP)
3656 {
3657 if (fRc && pState->CTX_SUFF(pTxSg))
3658 {
3659 Assert(pState->CTX_SUFF(pTxSg)->cSegs == 1);
3660 if (pState->fIPcsum)
3661 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3662 pState->contextNormal.ip.u8CSO,
3663 pState->contextNormal.ip.u8CSS,
3664 pState->contextNormal.ip.u16CSE);
3665 if (pState->fTCPcsum)
3666 e1kInsertChecksum(pState, (uint8_t *)pState->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pState->u16TxPktLen,
3667 pState->contextNormal.tu.u8CSO,
3668 pState->contextNormal.tu.u8CSS,
3669 pState->contextNormal.tu.u16CSE);
3670 e1kTransmitFrame(pState, fOnWorkerThread);
3671 }
3672 else
3673 e1kXmitFreeBuf(pState);
3674 pState->u16TxPktLen = 0;
3675 }
3676 }
3677 else
3678 {
3679 STAM_COUNTER_INC(&pState->StatTxPathFallback);
3680 e1kFallbackAddToFrame(pState, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
3681 }
3682
3683 e1kDescReport(pState, pDesc, addr);
3684 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3685 break;
3686 }
3687
3688 case E1K_DTYP_LEGACY:
3689 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
3690 {
3691 E1kLog(("%s Empty legacy descriptor, skipped.\n", INSTANCE(pState)));
3692 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
3693 break;
3694 }
3695 STAM_COUNTER_INC(&pState->StatTxDescLegacy);
3696 STAM_PROFILE_ADV_START(&pState->StatTransmit, a);
3697
3698 /* First fragment: allocate new buffer. */
3699 if (pState->u16TxPktLen == 0)
3700 /** @todo reset status bits? */
3701 e1kXmitAllocBuf(pState, pDesc->legacy.cmd.u16Length, pDesc->legacy.cmd.fEOP, false /*fGso*/);
3702 /** @todo Is there any way to indicating errors other than collisions? Like
3703 * VERR_NET_DOWN. */
3704
3705 /* Add fragment to frame. */
3706 if (e1kAddToFrame(pState, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
3707 {
3708 E1K_INC_ISTAT_CNT(pState->uStatDescLeg);
3709
3710 /* Last fragment: Transmit and reset the packet storage counter. */
3711 if (pDesc->legacy.cmd.fEOP)
3712 {
3713 /** @todo Offload processing goes here. */
3714 e1kTransmitFrame(pState, fOnWorkerThread);
3715 pState->u16TxPktLen = 0;
3716 }
3717 }
3718 /* Last fragment + failure: free the buffer and reset the storage counter. */
3719 else if (pDesc->legacy.cmd.fEOP)
3720 {
3721 e1kXmitFreeBuf(pState);
3722 pState->u16TxPktLen = 0;
3723 }
3724
3725 e1kDescReport(pState, pDesc, addr);
3726 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3727 break;
3728
3729 default:
3730 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
3731 INSTANCE(pState), e1kGetDescType(pDesc)));
3732 break;
3733 }
3734}
3735
3736
3737/**
3738 * Transmit pending descriptors.
3739 *
3740 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
3741 *
3742 * @param pState The E1000 state.
3743 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
3744 */
3745static int e1kXmitPending(E1KSTATE *pState, bool fOnWorkerThread)
3746{
3747 int rc;
3748
3749 /*
3750 * Grab the xmit lock of the driver as well as the E1K device state.
3751 */
3752 PPDMINETWORKUP pDrv = pState->CTX_SUFF(pDrv);
3753 if (pDrv)
3754 {
3755 rc = pDrv->pfnBeginXmit(pDrv, true /*fOnWorkerThread*/);
3756 if (RT_FAILURE(rc))
3757 return rc;
3758 }
3759 rc = e1kMutexAcquire(pState, VERR_TRY_AGAIN, RT_SRC_POS);
3760 if (RT_SUCCESS(rc))
3761 {
3762 /*
3763 * Process all pending descriptors.
3764 * Note! Do not process descriptors in locked state
3765 */
3766 while (TDH != TDT && !pState->fLocked)
3767 {
3768 E1KTXDESC desc;
3769 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3770 INSTANCE(pState), TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
3771
3772 e1kLoadDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
3773 e1kXmitDesc(pState, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc), fOnWorkerThread);
3774 if (++TDH * sizeof(desc) >= TDLEN)
3775 TDH = 0;
3776
3777 if (e1kGetTxLen(pState) <= GET_BITS(TXDCTL, LWTHRESH)*8)
3778 {
3779 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
3780 INSTANCE(pState), e1kGetTxLen(pState), GET_BITS(TXDCTL, LWTHRESH)*8));
3781 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_TXD_LOW);
3782 }
3783
3784 STAM_PROFILE_ADV_STOP(&pState->StatTransmit, a);
3785 }
3786
3787 /// @todo: uncomment: pState->uStatIntTXQE++;
3788 /// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
3789
3790 /*
3791 * Release the locks.
3792 */
3793 e1kMutexRelease(pState);
3794 }
3795 if (pDrv)
3796 pDrv->pfnEndXmit(pDrv);
3797 return rc;
3798}
3799
3800#ifdef IN_RING3
3801
3802/**
3803 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
3804 */
3805static DECLCALLBACK(void) e1kNetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
3806{
3807 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
3808 e1kXmitPending(pState, true /*fOnWorkerThread*/);
3809}
3810
3811/**
3812 * Callback for consuming from transmit queue. It gets called in R3 whenever
3813 * we enqueue something in R0/GC.
3814 *
3815 * @returns true
3816 * @param pDevIns Pointer to device instance structure.
3817 * @param pItem Pointer to the element being dequeued (not used).
3818 * @thread ???
3819 */
3820static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3821{
3822 NOREF(pItem);
3823 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
3824 E1kLog2(("%s e1kTxQueueConsumer: Waking up TX thread...\n", INSTANCE(pState)));
3825
3826 int rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
3827 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3828
3829 return true;
3830}
3831
3832/**
3833 * Handler for the wakeup signaller queue.
3834 */
3835static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
3836{
3837 e1kWakeupReceive(pDevIns);
3838 return true;
3839}
3840
3841#endif /* IN_RING3 */
3842
3843/**
3844 * Write handler for Transmit Descriptor Tail register.
3845 *
3846 * @param pState The device state structure.
3847 * @param offset Register offset in memory-mapped frame.
3848 * @param index Register index in register array.
3849 * @param value The value to store.
3850 * @param mask Used to implement partial writes (8 and 16-bit).
3851 * @thread EMT
3852 */
3853static int e1kRegWriteTDT(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3854{
3855 int rc = e1kCsTxEnter(pState, VINF_IOM_HC_MMIO_WRITE);
3856 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3857 return rc;
3858 rc = e1kRegWriteDefault(pState, offset, index, value);
3859
3860 /* All descriptors starting with head and not including tail belong to us. */
3861 /* Process them. */
3862 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3863 INSTANCE(pState), TDBAL, TDBAH, TDLEN, TDH, TDT));
3864
3865 /* Ignore TDT writes when the link is down. */
3866 if (TDH != TDT && (STATUS & STATUS_LU))
3867 {
3868 E1kLogRel(("E1000: TDT write: %d descriptors to process\n", e1kGetTxLen(pState)));
3869 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
3870 INSTANCE(pState), e1kGetTxLen(pState)));
3871 e1kCsTxLeave(pState);
3872
3873 /* Transmit pending packets if possible, defere it if we cannot do it
3874 in the current context. */
3875# if defined(IN_RING0) || defined(IN_RC)
3876 if (!pState->CTX_SUFF(pDrv))
3877 {
3878 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pState->CTX_SUFF(pTxQueue));
3879 if (RT_UNLIKELY(pItem))
3880 PDMQueueInsert(pState->CTX_SUFF(pTxQueue), pItem);
3881 }
3882 else
3883# endif
3884 {
3885 rc = e1kXmitPending(pState, false /*fOnWorkerThread*/);
3886 if (rc == VERR_TRY_AGAIN)
3887 rc = VINF_SUCCESS;
3888 AssertRC(rc);
3889 }
3890 }
3891 else
3892 e1kCsTxLeave(pState);
3893
3894 return rc;
3895}
3896
3897/**
3898 * Write handler for Multicast Table Array registers.
3899 *
3900 * @param pState The device state structure.
3901 * @param offset Register offset in memory-mapped frame.
3902 * @param index Register index in register array.
3903 * @param value The value to store.
3904 * @thread EMT
3905 */
3906static int e1kRegWriteMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3907{
3908 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3909 pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])] = value;
3910
3911 return VINF_SUCCESS;
3912}
3913
3914/**
3915 * Read handler for Multicast Table Array registers.
3916 *
3917 * @returns VBox status code.
3918 *
3919 * @param pState The device state structure.
3920 * @param offset Register offset in memory-mapped frame.
3921 * @param index Register index in register array.
3922 * @thread EMT
3923 */
3924static int e1kRegReadMTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3925{
3926 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auMTA), VERR_DEV_IO_ERROR);
3927 *pu32Value = pState->auMTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auMTA[0])];
3928
3929 return VINF_SUCCESS;
3930}
3931
3932/**
3933 * Write handler for Receive Address registers.
3934 *
3935 * @param pState The device state structure.
3936 * @param offset Register offset in memory-mapped frame.
3937 * @param index Register index in register array.
3938 * @param value The value to store.
3939 * @thread EMT
3940 */
3941static int e1kRegWriteRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3942{
3943 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3944 pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
3945
3946 return VINF_SUCCESS;
3947}
3948
3949/**
3950 * Read handler for Receive Address registers.
3951 *
3952 * @returns VBox status code.
3953 *
3954 * @param pState The device state structure.
3955 * @param offset Register offset in memory-mapped frame.
3956 * @param index Register index in register array.
3957 * @thread EMT
3958 */
3959static int e1kRegReadRA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3960{
3961 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
3962 *pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
3963
3964 return VINF_SUCCESS;
3965}
3966
3967/**
3968 * Write handler for VLAN Filter Table Array registers.
3969 *
3970 * @param pState The device state structure.
3971 * @param offset Register offset in memory-mapped frame.
3972 * @param index Register index in register array.
3973 * @param value The value to store.
3974 * @thread EMT
3975 */
3976static int e1kRegWriteVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
3977{
3978 AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->auVFTA), VINF_SUCCESS);
3979 pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])] = value;
3980
3981 return VINF_SUCCESS;
3982}
3983
3984/**
3985 * Read handler for VLAN Filter Table Array registers.
3986 *
3987 * @returns VBox status code.
3988 *
3989 * @param pState The device state structure.
3990 * @param offset Register offset in memory-mapped frame.
3991 * @param index Register index in register array.
3992 * @thread EMT
3993 */
3994static int e1kRegReadVFTA(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3995{
3996 AssertReturn(offset - s_e1kRegMap[index].offset< sizeof(pState->auVFTA), VERR_DEV_IO_ERROR);
3997 *pu32Value = pState->auVFTA[(offset - s_e1kRegMap[index].offset)/sizeof(pState->auVFTA[0])];
3998
3999 return VINF_SUCCESS;
4000}
4001
4002/**
4003 * Read handler for unimplemented registers.
4004 *
4005 * Merely reports reads from unimplemented registers.
4006 *
4007 * @returns VBox status code.
4008 *
4009 * @param pState The device state structure.
4010 * @param offset Register offset in memory-mapped frame.
4011 * @param index Register index in register array.
4012 * @thread EMT
4013 */
4014
4015static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4016{
4017 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
4018 INSTANCE(pState), offset, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4019 *pu32Value = 0;
4020
4021 return VINF_SUCCESS;
4022}
4023
4024/**
4025 * Default register read handler with automatic clear operation.
4026 *
4027 * Retrieves the value of register from register array in device state structure.
4028 * Then resets all bits.
4029 *
4030 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4031 * done in the caller.
4032 *
4033 * @returns VBox status code.
4034 *
4035 * @param pState The device state structure.
4036 * @param offset Register offset in memory-mapped frame.
4037 * @param index Register index in register array.
4038 * @thread EMT
4039 */
4040
4041static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4042{
4043 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4044 int rc = e1kRegReadDefault(pState, offset, index, pu32Value);
4045 pState->auRegs[index] = 0;
4046
4047 return rc;
4048}
4049
4050/**
4051 * Default register read handler.
4052 *
4053 * Retrieves the value of register from register array in device state structure.
4054 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
4055 *
4056 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
4057 * done in the caller.
4058 *
4059 * @returns VBox status code.
4060 *
4061 * @param pState The device state structure.
4062 * @param offset Register offset in memory-mapped frame.
4063 * @param index Register index in register array.
4064 * @thread EMT
4065 */
4066
4067static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
4068{
4069 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4070 *pu32Value = pState->auRegs[index] & s_e1kRegMap[index].readable;
4071
4072 return VINF_SUCCESS;
4073}
4074
4075/**
4076 * Write handler for unimplemented registers.
4077 *
4078 * Merely reports writes to unimplemented registers.
4079 *
4080 * @param pState The device state structure.
4081 * @param offset Register offset in memory-mapped frame.
4082 * @param index Register index in register array.
4083 * @param value The value to store.
4084 * @thread EMT
4085 */
4086
4087 static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4088{
4089 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
4090 INSTANCE(pState), offset, value, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4091
4092 return VINF_SUCCESS;
4093}
4094
4095/**
4096 * Default register write handler.
4097 *
4098 * Stores the value to the register array in device state structure. Only bits
4099 * corresponding to 1s both in 'writable' and 'mask' will be stored.
4100 *
4101 * @returns VBox status code.
4102 *
4103 * @param pState The device state structure.
4104 * @param offset Register offset in memory-mapped frame.
4105 * @param index Register index in register array.
4106 * @param value The value to store.
4107 * @param mask Used to implement partial writes (8 and 16-bit).
4108 * @thread EMT
4109 */
4110
4111static int e1kRegWriteDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
4112{
4113 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
4114 pState->auRegs[index] = (value & s_e1kRegMap[index].writable) |
4115 (pState->auRegs[index] & ~s_e1kRegMap[index].writable);
4116
4117 return VINF_SUCCESS;
4118}
4119
4120/**
4121 * Search register table for matching register.
4122 *
4123 * @returns Index in the register table or -1 if not found.
4124 *
4125 * @param pState The device state structure.
4126 * @param uOffset Register offset in memory-mapped region.
4127 * @thread EMT
4128 */
4129static int e1kRegLookup(E1KSTATE *pState, uint32_t uOffset)
4130{
4131 int index;
4132
4133 for (index = 0; index < E1K_NUM_OF_REGS; index++)
4134 {
4135 if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
4136 {
4137 return index;
4138 }
4139 }
4140
4141 return -1;
4142}
4143
4144/**
4145 * Handle register read operation.
4146 *
4147 * Looks up and calls appropriate handler.
4148 *
4149 * @returns VBox status code.
4150 *
4151 * @param pState The device state structure.
4152 * @param uOffset Register offset in memory-mapped frame.
4153 * @param pv Where to store the result.
4154 * @param cb Number of bytes to read.
4155 * @thread EMT
4156 */
4157static int e1kRegRead(E1KSTATE *pState, uint32_t uOffset, void *pv, uint32_t cb)
4158{
4159 uint32_t u32 = 0;
4160 uint32_t mask = 0;
4161 uint32_t shift;
4162 int rc = VINF_SUCCESS;
4163 int index = e1kRegLookup(pState, uOffset);
4164 const char *szInst = INSTANCE(pState);
4165#ifdef DEBUG
4166 char buf[9];
4167#endif
4168
4169 /*
4170 * From the spec:
4171 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4172 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4173 */
4174
4175 /*
4176 * To be able to write bytes and short word we convert them
4177 * to properly shifted 32-bit words and masks. The idea is
4178 * to keep register-specific handlers simple. Most accesses
4179 * will be 32-bit anyway.
4180 */
4181 switch (cb)
4182 {
4183 case 1: mask = 0x000000FF; break;
4184 case 2: mask = 0x0000FFFF; break;
4185 case 4: mask = 0xFFFFFFFF; break;
4186 default:
4187 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4188 "%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
4189 szInst, uOffset, cb);
4190 }
4191 if (index != -1)
4192 {
4193 if (s_e1kRegMap[index].readable)
4194 {
4195 /* Make the mask correspond to the bits we are about to read. */
4196 shift = (uOffset - s_e1kRegMap[index].offset) % sizeof(uint32_t) * 8;
4197 mask <<= shift;
4198 if (!mask)
4199 return PDMDevHlpDBGFStop(pState->CTX_SUFF(pDevIns), RT_SRC_POS,
4200 "%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
4201 szInst, uOffset, cb);
4202 /*
4203 * Read it. Pass the mask so the handler knows what has to be read.
4204 * Mask out irrelevant bits.
4205 */
4206#ifdef E1K_GLOBAL_MUTEX
4207 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_READ, RT_SRC_POS);
4208#else
4209 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4210#endif
4211 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4212 return rc;
4213 //pState->fDelayInts = false;
4214 //pState->iStatIntLost += pState->iStatIntLostOne;
4215 //pState->iStatIntLostOne = 0;
4216 rc = s_e1kRegMap[index].pfnRead(pState, uOffset & 0xFFFFFFFC, index, &u32) & mask;
4217 //e1kCsLeave(pState);
4218 e1kMutexRelease(pState);
4219 E1kLog2(("%s At %08X read %s from %s (%s)\n",
4220 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4221 /* Shift back the result. */
4222 u32 >>= shift;
4223 }
4224 else
4225 {
4226 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
4227 szInst, uOffset, e1kU32toHex(u32, mask, buf), s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4228 }
4229 }
4230 else
4231 {
4232 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
4233 szInst, uOffset, e1kU32toHex(u32, mask, buf)));
4234 }
4235
4236 memcpy(pv, &u32, cb);
4237 return rc;
4238}
4239
4240/**
4241 * Handle register write operation.
4242 *
4243 * Looks up and calls appropriate handler.
4244 *
4245 * @returns VBox status code.
4246 *
4247 * @param pState The device state structure.
4248 * @param uOffset Register offset in memory-mapped frame.
4249 * @param pv Where to fetch the value.
4250 * @param cb Number of bytes to write.
4251 * @thread EMT
4252 */
4253static int e1kRegWrite(E1KSTATE *pState, uint32_t uOffset, void *pv, unsigned cb)
4254{
4255 int rc = VINF_SUCCESS;
4256 int index = e1kRegLookup(pState, uOffset);
4257 uint32_t u32;
4258
4259 /*
4260 * From the spec:
4261 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
4262 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
4263 */
4264
4265 if (cb != 4)
4266 {
4267 E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
4268 INSTANCE(pState), uOffset, cb));
4269 return VINF_SUCCESS;
4270 }
4271 if (uOffset & 3)
4272 {
4273 E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
4274 INSTANCE(pState), uOffset, cb));
4275 return VINF_SUCCESS;
4276 }
4277 u32 = *(uint32_t*)pv;
4278 if (index != -1)
4279 {
4280 if (s_e1kRegMap[index].writable)
4281 {
4282 /*
4283 * Write it. Pass the mask so the handler knows what has to be written.
4284 * Mask out irrelevant bits.
4285 */
4286 E1kLog2(("%s At %08X write %08X to %s (%s)\n",
4287 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4288#ifdef E1K_GLOBAL_MUTEX
4289 rc = e1kMutexAcquire(pState, VINF_IOM_HC_MMIO_WRITE, RT_SRC_POS);
4290#else
4291 //rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
4292#endif
4293 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4294 return rc;
4295 //pState->fDelayInts = false;
4296 //pState->iStatIntLost += pState->iStatIntLostOne;
4297 //pState->iStatIntLostOne = 0;
4298 rc = s_e1kRegMap[index].pfnWrite(pState, uOffset, index, u32);
4299 //e1kCsLeave(pState);
4300 e1kMutexRelease(pState);
4301 }
4302 else
4303 {
4304 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
4305 INSTANCE(pState), uOffset, u32, s_e1kRegMap[index].abbrev, s_e1kRegMap[index].name));
4306 }
4307 }
4308 else
4309 {
4310 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
4311 INSTANCE(pState), uOffset, u32));
4312 }
4313 return rc;
4314}
4315
4316/**
4317 * I/O handler for memory-mapped read operations.
4318 *
4319 * @returns VBox status code.
4320 *
4321 * @param pDevIns The device instance.
4322 * @param pvUser User argument.
4323 * @param GCPhysAddr Physical address (in GC) where the read starts.
4324 * @param pv Where to store the result.
4325 * @param cb Number of bytes read.
4326 * @thread EMT
4327 */
4328PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser,
4329 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4330{
4331 NOREF(pvUser);
4332 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4333 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4334 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIORead), a);
4335
4336 Assert(uOffset < E1K_MM_SIZE);
4337
4338 int rc = e1kRegRead(pState, uOffset, pv, cb);
4339 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIORead), a);
4340 return rc;
4341}
4342
4343/**
4344 * Memory mapped I/O Handler for write operations.
4345 *
4346 * @returns VBox status code.
4347 *
4348 * @param pDevIns The device instance.
4349 * @param pvUser User argument.
4350 * @param GCPhysAddr Physical address (in GC) where the read starts.
4351 * @param pv Where to fetch the value.
4352 * @param cb Number of bytes to write.
4353 * @thread EMT
4354 */
4355PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,
4356 RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4357{
4358 NOREF(pvUser);
4359 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4360 uint32_t uOffset = GCPhysAddr - pState->addrMMReg;
4361 int rc;
4362 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatMMIOWrite), a);
4363
4364 Assert(uOffset < E1K_MM_SIZE);
4365 if (cb != 4)
4366 {
4367 E1kLog(("%s e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x", pDevIns, uOffset, cb));
4368 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
4369 }
4370 else
4371 rc = e1kRegWrite(pState, uOffset, pv, cb);
4372
4373 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatMMIOWrite), a);
4374 return rc;
4375}
4376
4377/**
4378 * Port I/O Handler for IN operations.
4379 *
4380 * @returns VBox status code.
4381 *
4382 * @param pDevIns The device instance.
4383 * @param pvUser Pointer to the device state structure.
4384 * @param port Port number used for the IN operation.
4385 * @param pu32 Where to store the result.
4386 * @param cb Number of bytes read.
4387 * @thread EMT
4388 */
4389PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser,
4390 RTIOPORT port, uint32_t *pu32, unsigned cb)
4391{
4392 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4393 int rc = VINF_SUCCESS;
4394 const char *szInst = INSTANCE(pState);
4395 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIORead), a);
4396
4397 port -= pState->addrIOPort;
4398 if (cb != 4)
4399 {
4400 E1kLog(("%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x", szInst, port, cb));
4401 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4402 }
4403 else
4404 switch (port)
4405 {
4406 case 0x00: /* IOADDR */
4407 *pu32 = pState->uSelectedReg;
4408 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4409 break;
4410 case 0x04: /* IODATA */
4411 rc = e1kRegRead(pState, pState->uSelectedReg, pu32, cb);
4412 /** @todo wrong return code triggers assertions in the debug build; fix please */
4413 if (rc == VINF_IOM_HC_MMIO_READ)
4414 rc = VINF_IOM_HC_IOPORT_READ;
4415
4416 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
4417 break;
4418 default:
4419 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", szInst, port));
4420 //*pRC = VERR_IOM_IOPORT_UNUSED;
4421 }
4422
4423 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIORead), a);
4424 return rc;
4425}
4426
4427
4428/**
4429 * Port I/O Handler for OUT operations.
4430 *
4431 * @returns VBox status code.
4432 *
4433 * @param pDevIns The device instance.
4434 * @param pvUser User argument.
4435 * @param Port Port number used for the IN operation.
4436 * @param u32 The value to output.
4437 * @param cb The value size in bytes.
4438 * @thread EMT
4439 */
4440PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser,
4441 RTIOPORT port, uint32_t u32, unsigned cb)
4442{
4443 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE *);
4444 int rc = VINF_SUCCESS;
4445 const char *szInst = INSTANCE(pState);
4446 STAM_PROFILE_ADV_START(&pState->CTXSUFF(StatIOWrite), a);
4447
4448 E1kLog2(("%s e1kIOPortOut: port=%RTiop value=%08x\n", szInst, port, u32));
4449 if (cb != 4)
4450 {
4451 E1kLog(("%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb));
4452 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
4453 }
4454 else
4455 {
4456 port -= pState->addrIOPort;
4457 switch (port)
4458 {
4459 case 0x00: /* IOADDR */
4460 pState->uSelectedReg = u32;
4461 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", szInst, pState->uSelectedReg));
4462 break;
4463 case 0x04: /* IODATA */
4464 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
4465 rc = e1kRegWrite(pState, pState->uSelectedReg, &u32, cb);
4466 /** @todo wrong return code triggers assertions in the debug build; fix please */
4467 if (rc == VINF_IOM_HC_MMIO_WRITE)
4468 rc = VINF_IOM_HC_IOPORT_WRITE;
4469 break;
4470 default:
4471 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", szInst, port));
4472 /** @todo Do we need to return an error here?
4473 * bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
4474 * about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
4475 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "e1kIOPortOut: invalid port %#010x\n", port);
4476 }
4477 }
4478
4479 STAM_PROFILE_ADV_STOP(&pState->CTXSUFF(StatIOWrite), a);
4480 return rc;
4481}
4482
4483#ifdef IN_RING3
4484/**
4485 * Dump complete device state to log.
4486 *
4487 * @param pState Pointer to device state.
4488 */
4489static void e1kDumpState(E1KSTATE *pState)
4490{
4491 for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
4492 {
4493 E1kLog2(("%s %8.8s = %08x\n", INSTANCE(pState),
4494 s_e1kRegMap[i].abbrev, pState->auRegs[i]));
4495 }
4496#ifdef E1K_INT_STATS
4497 LogRel(("%s Interrupt attempts: %d\n", INSTANCE(pState), pState->uStatIntTry));
4498 LogRel(("%s Interrupts raised : %d\n", INSTANCE(pState), pState->uStatInt));
4499 LogRel(("%s Interrupts lowered: %d\n", INSTANCE(pState), pState->uStatIntLower));
4500 LogRel(("%s Interrupts delayed: %d\n", INSTANCE(pState), pState->uStatIntDly));
4501 LogRel(("%s Disabled delayed: %d\n", INSTANCE(pState), pState->uStatDisDly));
4502 LogRel(("%s Interrupts skipped: %d\n", INSTANCE(pState), pState->uStatIntSkip));
4503 LogRel(("%s Masked interrupts : %d\n", INSTANCE(pState), pState->uStatIntMasked));
4504 LogRel(("%s Early interrupts : %d\n", INSTANCE(pState), pState->uStatIntEarly));
4505 LogRel(("%s Late interrupts : %d\n", INSTANCE(pState), pState->uStatIntLate));
4506 LogRel(("%s Lost interrupts : %d\n", INSTANCE(pState), pState->iStatIntLost));
4507 LogRel(("%s Interrupts by RX : %d\n", INSTANCE(pState), pState->uStatIntRx));
4508 LogRel(("%s Interrupts by TX : %d\n", INSTANCE(pState), pState->uStatIntTx));
4509 LogRel(("%s Interrupts by ICS : %d\n", INSTANCE(pState), pState->uStatIntICS));
4510 LogRel(("%s Interrupts by RDTR: %d\n", INSTANCE(pState), pState->uStatIntRDTR));
4511 LogRel(("%s Interrupts by RDMT: %d\n", INSTANCE(pState), pState->uStatIntRXDMT0));
4512 LogRel(("%s Interrupts by TXQE: %d\n", INSTANCE(pState), pState->uStatIntTXQE));
4513 LogRel(("%s TX int delay asked: %d\n", INSTANCE(pState), pState->uStatTxIDE));
4514 LogRel(("%s TX no report asked: %d\n", INSTANCE(pState), pState->uStatTxNoRS));
4515 LogRel(("%s TX abs timer expd : %d\n", INSTANCE(pState), pState->uStatTAD));
4516 LogRel(("%s TX int timer expd : %d\n", INSTANCE(pState), pState->uStatTID));
4517 LogRel(("%s RX abs timer expd : %d\n", INSTANCE(pState), pState->uStatRAD));
4518 LogRel(("%s RX int timer expd : %d\n", INSTANCE(pState), pState->uStatRID));
4519 LogRel(("%s TX CTX descriptors: %d\n", INSTANCE(pState), pState->uStatDescCtx));
4520 LogRel(("%s TX DAT descriptors: %d\n", INSTANCE(pState), pState->uStatDescDat));
4521 LogRel(("%s TX LEG descriptors: %d\n", INSTANCE(pState), pState->uStatDescLeg));
4522 LogRel(("%s Received frames : %d\n", INSTANCE(pState), pState->uStatRxFrm));
4523 LogRel(("%s Transmitted frames: %d\n", INSTANCE(pState), pState->uStatTxFrm));
4524#endif /* E1K_INT_STATS */
4525}
4526
4527/**
4528 * Map PCI I/O region.
4529 *
4530 * @return VBox status code.
4531 * @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
4532 * @param iRegion The region number.
4533 * @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
4534 * I/O port, else it's a physical address.
4535 * This address is *NOT* relative to pci_mem_base like earlier!
4536 * @param cb Region size.
4537 * @param enmType One of the PCI_ADDRESS_SPACE_* values.
4538 * @thread EMT
4539 */
4540static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion,
4541 RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
4542{
4543 int rc;
4544 E1KSTATE *pState = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
4545
4546 switch (enmType)
4547 {
4548 case PCI_ADDRESS_SPACE_IO:
4549 pState->addrIOPort = (RTIOPORT)GCPhysAddress;
4550 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4551 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
4552 if (RT_FAILURE(rc))
4553 break;
4554 if (pState->fR0Enabled)
4555 {
4556 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4557 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4558 if (RT_FAILURE(rc))
4559 break;
4560 }
4561 if (pState->fGCEnabled)
4562 {
4563 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pState->addrIOPort, cb, 0,
4564 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
4565 }
4566 break;
4567 case PCI_ADDRESS_SPACE_MEM:
4568 pState->addrMMReg = GCPhysAddress;
4569 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4570 e1kMMIOWrite, e1kMMIORead, NULL, "E1000");
4571 if (pState->fR0Enabled)
4572 {
4573 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4574 "e1kMMIOWrite", "e1kMMIORead", NULL);
4575 if (RT_FAILURE(rc))
4576 break;
4577 }
4578 if (pState->fGCEnabled)
4579 {
4580 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, 0,
4581 "e1kMMIOWrite", "e1kMMIORead", NULL);
4582 }
4583 break;
4584 default:
4585 /* We should never get here */
4586 AssertMsgFailed(("Invalid PCI address space param in map callback"));
4587 rc = VERR_INTERNAL_ERROR;
4588 break;
4589 }
4590 return rc;
4591}
4592
4593/**
4594 * Check if the device can receive data now.
4595 * This must be called before the pfnRecieve() method is called.
4596 *
4597 * @returns Number of bytes the device can receive.
4598 * @param pInterface Pointer to the interface structure containing the called function pointer.
4599 * @thread EMT
4600 */
4601static int e1kCanReceive(E1KSTATE *pState)
4602{
4603 size_t cb;
4604
4605 if (RT_UNLIKELY(e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS) != VINF_SUCCESS))
4606 return VERR_NET_NO_BUFFER_SPACE;
4607 if (RT_UNLIKELY(e1kCsRxEnter(pState, VERR_SEM_BUSY) != VINF_SUCCESS))
4608 return VERR_NET_NO_BUFFER_SPACE;
4609
4610 if (RDH < RDT)
4611 cb = (RDT - RDH) * pState->u16RxBSize;
4612 else if (RDH > RDT)
4613 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pState->u16RxBSize;
4614 else
4615 {
4616 cb = 0;
4617 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
4618 }
4619
4620 e1kCsRxLeave(pState);
4621 e1kMutexRelease(pState);
4622 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
4623}
4624
4625/**
4626 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
4627 */
4628static DECLCALLBACK(int) e1kNetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
4629{
4630 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
4631 int rc = e1kCanReceive(pState);
4632
4633 if (RT_SUCCESS(rc))
4634 return VINF_SUCCESS;
4635 if (RT_UNLIKELY(cMillies == 0))
4636 return VERR_NET_NO_BUFFER_SPACE;
4637
4638 rc = VERR_INTERRUPTED;
4639 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, true);
4640 STAM_PROFILE_START(&pState->StatRxOverflow, a);
4641 VMSTATE enmVMState;
4642 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pState->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
4643 || enmVMState == VMSTATE_RUNNING_LS))
4644 {
4645 int rc2 = e1kCanReceive(pState);
4646 if (RT_SUCCESS(rc2))
4647 {
4648 rc = VINF_SUCCESS;
4649 break;
4650 }
4651 E1kLogRel(("E1000 e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4652 cMillies));
4653 E1kLog(("%s e1kNetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n",
4654 INSTANCE(pState), cMillies));
4655 RTSemEventWait(pState->hEventMoreRxDescAvail, cMillies);
4656 }
4657 STAM_PROFILE_STOP(&pState->StatRxOverflow, a);
4658 ASMAtomicXchgBool(&pState->fMaybeOutOfSpace, false);
4659
4660 return rc;
4661}
4662
4663
4664/**
4665 * Matches the packet addresses against Receive Address table. Looks for
4666 * exact matches only.
4667 *
4668 * @returns true if address matches.
4669 * @param pState Pointer to the state structure.
4670 * @param pvBuf The ethernet packet.
4671 * @param cb Number of bytes available in the packet.
4672 * @thread EMT
4673 */
4674static bool e1kPerfectMatch(E1KSTATE *pState, const void *pvBuf)
4675{
4676 for (unsigned i = 0; i < RT_ELEMENTS(pState->aRecAddr.array); i++)
4677 {
4678 E1KRAELEM* ra = pState->aRecAddr.array + i;
4679
4680 /* Valid address? */
4681 if (ra->ctl & RA_CTL_AV)
4682 {
4683 Assert((ra->ctl & RA_CTL_AS) < 2);
4684 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
4685 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
4686 // INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
4687 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
4688 /*
4689 * Address Select:
4690 * 00b = Destination address
4691 * 01b = Source address
4692 * 10b = Reserved
4693 * 11b = Reserved
4694 * Since ethernet header is (DA, SA, len) we can use address
4695 * select as index.
4696 */
4697 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
4698 ra->addr, sizeof(ra->addr)) == 0)
4699 return true;
4700 }
4701 }
4702
4703 return false;
4704}
4705
4706/**
4707 * Matches the packet addresses against Multicast Table Array.
4708 *
4709 * @remarks This is imperfect match since it matches not exact address but
4710 * a subset of addresses.
4711 *
4712 * @returns true if address matches.
4713 * @param pState Pointer to the state structure.
4714 * @param pvBuf The ethernet packet.
4715 * @param cb Number of bytes available in the packet.
4716 * @thread EMT
4717 */
4718static bool e1kImperfectMatch(E1KSTATE *pState, const void *pvBuf)
4719{
4720 /* Get bits 32..47 of destination address */
4721 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
4722
4723 unsigned offset = GET_BITS(RCTL, MO);
4724 /*
4725 * offset means:
4726 * 00b = bits 36..47
4727 * 01b = bits 35..46
4728 * 10b = bits 34..45
4729 * 11b = bits 32..43
4730 */
4731 if (offset < 3)
4732 u16Bit = u16Bit >> (4 - offset);
4733 return ASMBitTest(pState->auMTA, u16Bit & 0xFFF);
4734}
4735
4736/**
4737 * Determines if the packet is to be delivered to upper layer. The following
4738 * filters supported:
4739 * - Exact Unicast/Multicast
4740 * - Promiscuous Unicast/Multicast
4741 * - Multicast
4742 * - VLAN
4743 *
4744 * @returns true if packet is intended for this node.
4745 * @param pState Pointer to the state structure.
4746 * @param pvBuf The ethernet packet.
4747 * @param cb Number of bytes available in the packet.
4748 * @param pStatus Bit field to store status bits.
4749 * @thread EMT
4750 */
4751static bool e1kAddressFilter(E1KSTATE *pState, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
4752{
4753 Assert(cb > 14);
4754 /* Assume that we fail to pass exact filter. */
4755 pStatus->fPIF = false;
4756 pStatus->fVP = false;
4757 /* Discard oversized packets */
4758 if (cb > E1K_MAX_RX_PKT_SIZE)
4759 {
4760 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
4761 INSTANCE(pState), cb, E1K_MAX_RX_PKT_SIZE));
4762 E1K_INC_CNT32(ROC);
4763 return false;
4764 }
4765 else if (!(RCTL & RCTL_LPE) && cb > 1522)
4766 {
4767 /* When long packet reception is disabled packets over 1522 are discarded */
4768 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
4769 INSTANCE(pState), cb));
4770 E1K_INC_CNT32(ROC);
4771 return false;
4772 }
4773
4774 /* Broadcast filtering */
4775 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
4776 return true;
4777 E1kLog2(("%s Packet filter: not a broadcast\n", INSTANCE(pState)));
4778 if (e1kIsMulticast(pvBuf))
4779 {
4780 /* Is multicast promiscuous enabled? */
4781 if (RCTL & RCTL_MPE)
4782 return true;
4783 E1kLog2(("%s Packet filter: no promiscuous multicast\n", INSTANCE(pState)));
4784 /* Try perfect matches first */
4785 if (e1kPerfectMatch(pState, pvBuf))
4786 {
4787 pStatus->fPIF = true;
4788 return true;
4789 }
4790 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4791 if (e1kImperfectMatch(pState, pvBuf))
4792 return true;
4793 E1kLog2(("%s Packet filter: no imperfect match\n", INSTANCE(pState)));
4794 }
4795 else {
4796 /* Is unicast promiscuous enabled? */
4797 if (RCTL & RCTL_UPE)
4798 return true;
4799 E1kLog2(("%s Packet filter: no promiscuous unicast\n", INSTANCE(pState)));
4800 if (e1kPerfectMatch(pState, pvBuf))
4801 {
4802 pStatus->fPIF = true;
4803 return true;
4804 }
4805 E1kLog2(("%s Packet filter: no perfect match\n", INSTANCE(pState)));
4806 }
4807 /* Is VLAN filtering enabled? */
4808 if (RCTL & RCTL_VFE)
4809 {
4810 uint16_t *u16Ptr = (uint16_t*)pvBuf;
4811 /* Compare TPID with VLAN Ether Type */
4812 if (u16Ptr[6] == VET)
4813 {
4814 pStatus->fVP = true;
4815 /* It is 802.1q packet indeed, let's filter by VID */
4816 if (ASMBitTest(pState->auVFTA, RT_BE2H_U16(u16Ptr[7]) & 0xFFF))
4817 return true;
4818 E1kLog2(("%s Packet filter: no VLAN match\n", INSTANCE(pState)));
4819 }
4820 }
4821 E1kLog2(("%s Packet filter: packet discarded\n", INSTANCE(pState)));
4822 return false;
4823}
4824
4825/**
4826 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
4827 */
4828static DECLCALLBACK(int) e1kNetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
4829{
4830 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
4831 int rc = VINF_SUCCESS;
4832
4833 /*
4834 * Drop packets if the VM is not running yet/anymore.
4835 */
4836 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pState));
4837 if ( enmVMState != VMSTATE_RUNNING
4838 && enmVMState != VMSTATE_RUNNING_LS)
4839 {
4840 E1kLog(("%s Dropping incoming packet as VM is not running.\n", INSTANCE(pState)));
4841 return VINF_SUCCESS;
4842 }
4843
4844 /* Discard incoming packets in locked state */
4845 if (!(RCTL & RCTL_EN) || pState->fLocked || !(STATUS & STATUS_LU))
4846 {
4847 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", INSTANCE(pState)));
4848 return VINF_SUCCESS;
4849 }
4850
4851 STAM_PROFILE_ADV_START(&pState->StatReceive, a);
4852 rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
4853 if (RT_LIKELY(rc == VINF_SUCCESS))
4854 {
4855 //if (!e1kCsEnter(pState, RT_SRC_POS))
4856 // return VERR_PERMISSION_DENIED;
4857
4858 e1kPacketDump(pState, (const uint8_t*)pvBuf, cb, "<-- Incoming");
4859
4860 /* Update stats */
4861 if (RT_LIKELY(e1kCsEnter(pState, VERR_SEM_BUSY) == VINF_SUCCESS))
4862 {
4863 E1K_INC_CNT32(TPR);
4864 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
4865 e1kCsLeave(pState);
4866 }
4867 STAM_PROFILE_ADV_START(&pState->StatReceiveFilter, a);
4868 E1KRXDST status;
4869 RT_ZERO(status);
4870 bool fPassed = e1kAddressFilter(pState, pvBuf, cb, &status);
4871 STAM_PROFILE_ADV_STOP(&pState->StatReceiveFilter, a);
4872 if (fPassed)
4873 {
4874 rc = e1kHandleRxPacket(pState, pvBuf, cb, status);
4875 }
4876 //e1kCsLeave(pState);
4877 e1kMutexRelease(pState);
4878 }
4879 STAM_PROFILE_ADV_STOP(&pState->StatReceive, a);
4880
4881 return rc;
4882}
4883
4884/**
4885 * Gets the pointer to the status LED of a unit.
4886 *
4887 * @returns VBox status code.
4888 * @param pInterface Pointer to the interface structure.
4889 * @param iLUN The unit which status LED we desire.
4890 * @param ppLed Where to store the LED pointer.
4891 * @thread EMT
4892 */
4893static DECLCALLBACK(int) e1kQueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
4894{
4895 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
4896 int rc = VERR_PDM_LUN_NOT_FOUND;
4897
4898 if (iLUN == 0)
4899 {
4900 *ppLed = &pState->led;
4901 rc = VINF_SUCCESS;
4902 }
4903 return rc;
4904}
4905
4906/**
4907 * Gets the current Media Access Control (MAC) address.
4908 *
4909 * @returns VBox status code.
4910 * @param pInterface Pointer to the interface structure containing the called function pointer.
4911 * @param pMac Where to store the MAC address.
4912 * @thread EMT
4913 */
4914static DECLCALLBACK(int) e1kGetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
4915{
4916 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4917 pState->eeprom.getMac(pMac);
4918 return VINF_SUCCESS;
4919}
4920
4921
4922/**
4923 * Gets the new link state.
4924 *
4925 * @returns The current link state.
4926 * @param pInterface Pointer to the interface structure containing the called function pointer.
4927 * @thread EMT
4928 */
4929static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kGetLinkState(PPDMINETWORKCONFIG pInterface)
4930{
4931 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4932 if (STATUS & STATUS_LU)
4933 return PDMNETWORKLINKSTATE_UP;
4934 return PDMNETWORKLINKSTATE_DOWN;
4935}
4936
4937
4938/**
4939 * Sets the new link state.
4940 *
4941 * @returns VBox status code.
4942 * @param pInterface Pointer to the interface structure containing the called function pointer.
4943 * @param enmState The new link state
4944 * @thread EMT
4945 */
4946static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
4947{
4948 E1KSTATE *pState = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
4949 bool fOldUp = !!(STATUS & STATUS_LU);
4950 bool fNewUp = enmState == PDMNETWORKLINKSTATE_UP;
4951
4952 if (fNewUp != fOldUp)
4953 {
4954 if (fNewUp)
4955 {
4956 E1kLog(("%s Link will be up in approximately 5 secs\n", INSTANCE(pState)));
4957 pState->fCableConnected = true;
4958 STATUS &= ~STATUS_LU;
4959 Phy::setLinkStatus(&pState->phy, false);
4960 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4961 /* Restore the link back in 5 second. */
4962 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
4963 }
4964 else
4965 {
4966 E1kLog(("%s Link is down\n", INSTANCE(pState)));
4967 pState->fCableConnected = false;
4968 STATUS &= ~STATUS_LU;
4969 Phy::setLinkStatus(&pState->phy, false);
4970 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
4971 }
4972 if (pState->pDrvR3)
4973 pState->pDrvR3->pfnNotifyLinkChanged(pState->pDrvR3, enmState);
4974 }
4975 return VINF_SUCCESS;
4976}
4977
4978/**
4979 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4980 */
4981static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
4982{
4983 E1KSTATE *pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
4984 Assert(&pThis->IBase == pInterface);
4985
4986 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4987 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
4988 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
4989 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
4990 return NULL;
4991}
4992
4993/**
4994 * Saves the configuration.
4995 *
4996 * @param pState The E1K state.
4997 * @param pSSM The handle to the saved state.
4998 */
4999static void e1kSaveConfig(E1KSTATE *pState, PSSMHANDLE pSSM)
5000{
5001 SSMR3PutMem(pSSM, &pState->macConfigured, sizeof(pState->macConfigured));
5002 SSMR3PutU32(pSSM, pState->eChip);
5003}
5004
5005/**
5006 * Live save - save basic configuration.
5007 *
5008 * @returns VBox status code.
5009 * @param pDevIns The device instance.
5010 * @param pSSM The handle to the saved state.
5011 * @param uPass
5012 */
5013static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
5014{
5015 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5016 e1kSaveConfig(pState, pSSM);
5017 return VINF_SSM_DONT_CALL_AGAIN;
5018}
5019
5020/**
5021 * Prepares for state saving.
5022 *
5023 * @returns VBox status code.
5024 * @param pDevIns The device instance.
5025 * @param pSSM The handle to the saved state.
5026 */
5027static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5028{
5029 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5030
5031 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5032 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5033 return rc;
5034 e1kCsLeave(pState);
5035 return VINF_SUCCESS;
5036#if 0
5037 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5038 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5039 return rc;
5040 /* 1) Prevent all threads from modifying the state and memory */
5041 //pState->fLocked = true;
5042 /* 2) Cancel all timers */
5043#ifdef E1K_USE_TX_TIMERS
5044 e1kCancelTimer(pState, pState->CTX_SUFF(pTIDTimer));
5045#ifndef E1K_NO_TAD
5046 e1kCancelTimer(pState, pState->CTX_SUFF(pTADTimer));
5047#endif /* E1K_NO_TAD */
5048#endif /* E1K_USE_TX_TIMERS */
5049#ifdef E1K_USE_RX_TIMERS
5050 e1kCancelTimer(pState, pState->CTX_SUFF(pRIDTimer));
5051 e1kCancelTimer(pState, pState->CTX_SUFF(pRADTimer));
5052#endif /* E1K_USE_RX_TIMERS */
5053 e1kCancelTimer(pState, pState->CTX_SUFF(pIntTimer));
5054 /* 3) Did I forget anything? */
5055 E1kLog(("%s Locked\n", INSTANCE(pState)));
5056 e1kMutexRelease(pState);
5057 return VINF_SUCCESS;
5058#endif
5059}
5060
5061
5062/**
5063 * Saves the state of device.
5064 *
5065 * @returns VBox status code.
5066 * @param pDevIns The device instance.
5067 * @param pSSM The handle to the saved state.
5068 */
5069static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5070{
5071 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5072
5073 e1kSaveConfig(pState, pSSM);
5074 pState->eeprom.save(pSSM);
5075 e1kDumpState(pState);
5076 SSMR3PutMem(pSSM, pState->auRegs, sizeof(pState->auRegs));
5077 SSMR3PutBool(pSSM, pState->fIntRaised);
5078 Phy::saveState(pSSM, &pState->phy);
5079 SSMR3PutU32(pSSM, pState->uSelectedReg);
5080 SSMR3PutMem(pSSM, pState->auMTA, sizeof(pState->auMTA));
5081 SSMR3PutMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5082 SSMR3PutMem(pSSM, pState->auVFTA, sizeof(pState->auVFTA));
5083 SSMR3PutU64(pSSM, pState->u64AckedAt);
5084 SSMR3PutU16(pSSM, pState->u16RxBSize);
5085 //SSMR3PutBool(pSSM, pState->fDelayInts);
5086 //SSMR3PutBool(pSSM, pState->fIntMaskUsed);
5087 SSMR3PutU16(pSSM, pState->u16TxPktLen);
5088/** @todo State wrt to the TSE buffer is incomplete, so little point in
5089 * saving this actually. */
5090 SSMR3PutMem(pSSM, pState->aTxPacketFallback, pState->u16TxPktLen);
5091 SSMR3PutBool(pSSM, pState->fIPcsum);
5092 SSMR3PutBool(pSSM, pState->fTCPcsum);
5093 SSMR3PutMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5094 SSMR3PutMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5095/**@todo GSO requres some more state here. */
5096 E1kLog(("%s State has been saved\n", INSTANCE(pState)));
5097 return VINF_SUCCESS;
5098}
5099
5100#if 0
5101/**
5102 * Cleanup after saving.
5103 *
5104 * @returns VBox status code.
5105 * @param pDevIns The device instance.
5106 * @param pSSM The handle to the saved state.
5107 */
5108static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5109{
5110 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5111
5112 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5113 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5114 return rc;
5115 /* If VM is being powered off unlocking will result in assertions in PGM */
5116 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
5117 pState->fLocked = false;
5118 else
5119 E1kLog(("%s VM is not running -- remain locked\n", INSTANCE(pState)));
5120 E1kLog(("%s Unlocked\n", INSTANCE(pState)));
5121 e1kMutexRelease(pState);
5122 return VINF_SUCCESS;
5123}
5124#endif
5125
5126/**
5127 * Sync with .
5128 *
5129 * @returns VBox status code.
5130 * @param pDevIns The device instance.
5131 * @param pSSM The handle to the saved state.
5132 */
5133static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5134{
5135 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5136
5137 int rc = e1kCsEnter(pState, VERR_SEM_BUSY);
5138 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5139 return rc;
5140 e1kCsLeave(pState);
5141 return VINF_SUCCESS;
5142}
5143
5144/**
5145 * Restore previously saved state of device.
5146 *
5147 * @returns VBox status code.
5148 * @param pDevIns The device instance.
5149 * @param pSSM The handle to the saved state.
5150 * @param uVersion The data unit version number.
5151 * @param uPass The data pass.
5152 */
5153static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5154{
5155 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5156 int rc;
5157
5158 if ( uVersion != E1K_SAVEDSTATE_VERSION
5159 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
5160 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5161
5162 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
5163 || uPass != SSM_PASS_FINAL)
5164 {
5165 /* config checks */
5166 RTMAC macConfigured;
5167 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
5168 AssertRCReturn(rc, rc);
5169 if ( memcmp(&macConfigured, &pState->macConfigured, sizeof(macConfigured))
5170 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
5171 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", INSTANCE(pState), &pState->macConfigured, &macConfigured));
5172
5173 E1KCHIP eChip;
5174 rc = SSMR3GetU32(pSSM, &eChip);
5175 AssertRCReturn(rc, rc);
5176 if (eChip != pState->eChip)
5177 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pState->eChip, eChip);
5178 }
5179
5180 if (uPass == SSM_PASS_FINAL)
5181 {
5182 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
5183 {
5184 rc = pState->eeprom.load(pSSM);
5185 AssertRCReturn(rc, rc);
5186 }
5187 /* the state */
5188 SSMR3GetMem(pSSM, &pState->auRegs, sizeof(pState->auRegs));
5189 SSMR3GetBool(pSSM, &pState->fIntRaised);
5190 /** @todo: PHY could be made a separate device with its own versioning */
5191 Phy::loadState(pSSM, &pState->phy);
5192 SSMR3GetU32(pSSM, &pState->uSelectedReg);
5193 SSMR3GetMem(pSSM, &pState->auMTA, sizeof(pState->auMTA));
5194 SSMR3GetMem(pSSM, &pState->aRecAddr, sizeof(pState->aRecAddr));
5195 SSMR3GetMem(pSSM, &pState->auVFTA, sizeof(pState->auVFTA));
5196 SSMR3GetU64(pSSM, &pState->u64AckedAt);
5197 SSMR3GetU16(pSSM, &pState->u16RxBSize);
5198 //SSMR3GetBool(pSSM, pState->fDelayInts);
5199 //SSMR3GetBool(pSSM, pState->fIntMaskUsed);
5200 SSMR3GetU16(pSSM, &pState->u16TxPktLen);
5201 SSMR3GetMem(pSSM, &pState->aTxPacketFallback[0], pState->u16TxPktLen);
5202 SSMR3GetBool(pSSM, &pState->fIPcsum);
5203 SSMR3GetBool(pSSM, &pState->fTCPcsum);
5204 SSMR3GetMem(pSSM, &pState->contextTSE, sizeof(pState->contextTSE));
5205 rc = SSMR3GetMem(pSSM, &pState->contextNormal, sizeof(pState->contextNormal));
5206 AssertRCReturn(rc, rc);
5207
5208 /* derived state */
5209 e1kSetupGsoCtx(&pState->GsoCtx, &pState->contextTSE);
5210
5211 E1kLog(("%s State has been restored\n", INSTANCE(pState)));
5212 e1kDumpState(pState);
5213 }
5214 return VINF_SUCCESS;
5215}
5216
5217/**
5218 * Link status adjustments after loading.
5219 *
5220 * @returns VBox status code.
5221 * @param pDevIns The device instance.
5222 * @param pSSM The handle to the saved state.
5223 */
5224static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5225{
5226 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5227
5228 int rc = e1kMutexAcquire(pState, VERR_SEM_BUSY, RT_SRC_POS);
5229 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5230 return rc;
5231 /*
5232 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
5233 * passed to us. We go through all this stuff if the link was up and we
5234 * wasn't teleported.
5235 */
5236 if ( (STATUS & STATUS_LU)
5237 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns))
5238 {
5239 E1kLog(("%s Link is down temporarily\n", INSTANCE(pState)));
5240 STATUS &= ~STATUS_LU;
5241 Phy::setLinkStatus(&pState->phy, false);
5242 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5243 /* Restore the link back in five seconds. */
5244 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5245 }
5246 e1kMutexRelease(pState);
5247 return VINF_SUCCESS;
5248}
5249
5250/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
5251
5252#ifdef VBOX_DYNAMIC_NET_ATTACH
5253
5254/**
5255 * Detach notification.
5256 *
5257 * One port on the network card has been disconnected from the network.
5258 *
5259 * @param pDevIns The device instance.
5260 * @param iLUN The logical unit which is being detached.
5261 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5262 */
5263static DECLCALLBACK(void) e1kDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5264{
5265 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5266 Log(("%s e1kDetach:\n", INSTANCE(pState)));
5267
5268 AssertLogRelReturnVoid(iLUN == 0);
5269
5270 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5271
5272 /** @todo: r=pritesh still need to check if i missed
5273 * to clean something in this function
5274 */
5275
5276 /*
5277 * Zero some important members.
5278 */
5279 pState->pDrvBase = NULL;
5280 pState->pDrvR3 = NULL;
5281 pState->pDrvR0 = NIL_RTR0PTR;
5282 pState->pDrvRC = NIL_RTRCPTR;
5283
5284 PDMCritSectLeave(&pState->cs);
5285}
5286
5287
5288/**
5289 * Attach the Network attachment.
5290 *
5291 * One port on the network card has been connected to a network.
5292 *
5293 * @returns VBox status code.
5294 * @param pDevIns The device instance.
5295 * @param iLUN The logical unit which is being attached.
5296 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5297 *
5298 * @remarks This code path is not used during construction.
5299 */
5300static DECLCALLBACK(int) e1kAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
5301{
5302 E1KSTATE *pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5303 LogFlow(("%s e1kAttach:\n", INSTANCE(pState)));
5304
5305 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
5306
5307 PDMCritSectEnter(&pState->cs, VERR_SEM_BUSY);
5308
5309 /*
5310 * Attach the driver.
5311 */
5312 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5313 if (RT_SUCCESS(rc))
5314 {
5315 if (rc == VINF_NAT_DNS)
5316 {
5317#ifdef RT_OS_LINUX
5318 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5319 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5320#else
5321 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5322 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5323#endif
5324 }
5325 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5326 AssertMsgStmt(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5327 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
5328 if (RT_SUCCESS(rc))
5329 {
5330 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0);
5331 pState->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5332
5333 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC);
5334 pState->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
5335 }
5336 }
5337 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5338 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5339 {
5340 /* This should never happen because this function is not called
5341 * if there is no driver to attach! */
5342 Log(("%s No attached driver!\n", INSTANCE(pState)));
5343 }
5344
5345 /*
5346 * Temporary set the link down if it was up so that the guest
5347 * will know that we have change the configuration of the
5348 * network card
5349 */
5350 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
5351 {
5352 STATUS &= ~STATUS_LU;
5353 Phy::setLinkStatus(&pState->phy, false);
5354 e1kRaiseInterrupt(pState, VERR_SEM_BUSY, ICR_LSC);
5355 /* Restore the link back in 5 second. */
5356 e1kArmTimer(pState, pState->pLUTimerR3, 5000000);
5357 }
5358
5359 PDMCritSectLeave(&pState->cs);
5360 return rc;
5361
5362}
5363
5364#endif /* VBOX_DYNAMIC_NET_ATTACH */
5365
5366/**
5367 * @copydoc FNPDMDEVPOWEROFF
5368 */
5369static DECLCALLBACK(void) e1kPowerOff(PPDMDEVINS pDevIns)
5370{
5371 /* Poke thread waiting for buffer space. */
5372 e1kWakeupReceive(pDevIns);
5373}
5374
5375/**
5376 * @copydoc FNPDMDEVSUSPEND
5377 */
5378static DECLCALLBACK(void) e1kSuspend(PPDMDEVINS pDevIns)
5379{
5380 /* Poke thread waiting for buffer space. */
5381 e1kWakeupReceive(pDevIns);
5382}
5383
5384/**
5385 * Device relocation callback.
5386 *
5387 * When this callback is called the device instance data, and if the
5388 * device have a GC component, is being relocated, or/and the selectors
5389 * have been changed. The device must use the chance to perform the
5390 * necessary pointer relocations and data updates.
5391 *
5392 * Before the GC code is executed the first time, this function will be
5393 * called with a 0 delta so GC pointer calculations can be one in one place.
5394 *
5395 * @param pDevIns Pointer to the device instance.
5396 * @param offDelta The relocation delta relative to the old location.
5397 *
5398 * @remark A relocation CANNOT fail.
5399 */
5400static DECLCALLBACK(void) e1kRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
5401{
5402 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5403 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5404 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5405 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5406#ifdef E1K_USE_RX_TIMERS
5407 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5408 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5409#endif /* E1K_USE_RX_TIMERS */
5410#ifdef E1K_USE_TX_TIMERS
5411 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5412# ifndef E1K_NO_TAD
5413 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5414# endif /* E1K_NO_TAD */
5415#endif /* E1K_USE_TX_TIMERS */
5416 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5417 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5418}
5419
5420/**
5421 * Destruct a device instance.
5422 *
5423 * We need to free non-VM resources only.
5424 *
5425 * @returns VBox status.
5426 * @param pDevIns The device instance data.
5427 * @thread EMT
5428 */
5429static DECLCALLBACK(int) e1kDestruct(PPDMDEVINS pDevIns)
5430{
5431 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5432 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5433
5434 e1kDumpState(pState);
5435 E1kLog(("%s Destroying instance\n", INSTANCE(pState)));
5436 if (PDMCritSectIsInitialized(&pState->cs))
5437 {
5438 if (pState->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
5439 {
5440 RTSemEventSignal(pState->hEventMoreRxDescAvail);
5441 RTSemEventDestroy(pState->hEventMoreRxDescAvail);
5442 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5443 }
5444#ifndef E1K_GLOBAL_MUTEX
5445 PDMR3CritSectDelete(&pState->csRx);
5446 //PDMR3CritSectDelete(&pState->csTx);
5447#endif
5448 PDMR3CritSectDelete(&pState->cs);
5449 }
5450 return VINF_SUCCESS;
5451}
5452
5453/**
5454 * Sets 8-bit register in PCI configuration space.
5455 * @param refPciDev The PCI device.
5456 * @param uOffset The register offset.
5457 * @param u16Value The value to store in the register.
5458 * @thread EMT
5459 */
5460DECLINLINE(void) e1kPCICfgSetU8(PCIDEVICE& refPciDev, uint32_t uOffset, uint8_t u8Value)
5461{
5462 Assert(uOffset < sizeof(refPciDev.config));
5463 refPciDev.config[uOffset] = u8Value;
5464}
5465
5466/**
5467 * Sets 16-bit register in PCI configuration space.
5468 * @param refPciDev The PCI device.
5469 * @param uOffset The register offset.
5470 * @param u16Value The value to store in the register.
5471 * @thread EMT
5472 */
5473DECLINLINE(void) e1kPCICfgSetU16(PCIDEVICE& refPciDev, uint32_t uOffset, uint16_t u16Value)
5474{
5475 Assert(uOffset+sizeof(u16Value) <= sizeof(refPciDev.config));
5476 *(uint16_t*)&refPciDev.config[uOffset] = u16Value;
5477}
5478
5479/**
5480 * Sets 32-bit register in PCI configuration space.
5481 * @param refPciDev The PCI device.
5482 * @param uOffset The register offset.
5483 * @param u32Value The value to store in the register.
5484 * @thread EMT
5485 */
5486DECLINLINE(void) e1kPCICfgSetU32(PCIDEVICE& refPciDev, uint32_t uOffset, uint32_t u32Value)
5487{
5488 Assert(uOffset+sizeof(u32Value) <= sizeof(refPciDev.config));
5489 *(uint32_t*)&refPciDev.config[uOffset] = u32Value;
5490}
5491
5492/**
5493 * Set PCI configuration space registers.
5494 *
5495 * @param pci Reference to PCI device structure.
5496 * @thread EMT
5497 */
5498static DECLCALLBACK(void) e1kConfigurePCI(PCIDEVICE& pci, E1KCHIP eChip)
5499{
5500 Assert(eChip < RT_ELEMENTS(g_Chips));
5501 /* Configure PCI Device, assume 32-bit mode ******************************/
5502 PCIDevSetVendorId(&pci, g_Chips[eChip].uPCIVendorId);
5503 PCIDevSetDeviceId(&pci, g_Chips[eChip].uPCIDeviceId);
5504 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
5505 e1kPCICfgSetU16(pci, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
5506
5507 e1kPCICfgSetU16(pci, VBOX_PCI_COMMAND, 0x0000);
5508 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
5509 e1kPCICfgSetU16(pci, VBOX_PCI_STATUS, 0x0230);
5510 /* Stepping A2 */
5511 e1kPCICfgSetU8( pci, VBOX_PCI_REVISION_ID, 0x02);
5512 /* Ethernet adapter */
5513 e1kPCICfgSetU8( pci, VBOX_PCI_CLASS_PROG, 0x00);
5514 e1kPCICfgSetU16(pci, VBOX_PCI_CLASS_DEVICE, 0x0200);
5515 /* normal single function Ethernet controller */
5516 e1kPCICfgSetU8( pci, VBOX_PCI_HEADER_TYPE, 0x00);
5517 /* Memory Register Base Address */
5518 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
5519 /* Memory Flash Base Address */
5520 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
5521 /* IO Register Base Address */
5522 e1kPCICfgSetU32(pci, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
5523 /* Expansion ROM Base Address */
5524 e1kPCICfgSetU32(pci, VBOX_PCI_ROM_ADDRESS, 0x00000000);
5525 /* Capabilities Pointer */
5526 e1kPCICfgSetU8( pci, VBOX_PCI_CAPABILITY_LIST, 0xDC);
5527 /* Interrupt Pin: INTA# */
5528 e1kPCICfgSetU8( pci, VBOX_PCI_INTERRUPT_PIN, 0x01);
5529 /* Max_Lat/Min_Gnt: very high priority and time slice */
5530 e1kPCICfgSetU8( pci, VBOX_PCI_MIN_GNT, 0xFF);
5531 e1kPCICfgSetU8( pci, VBOX_PCI_MAX_LAT, 0x00);
5532
5533 /* PCI Power Management Registers ****************************************/
5534 /* Capability ID: PCI Power Management Registers */
5535 e1kPCICfgSetU8( pci, 0xDC, 0x01);
5536 /* Next Item Pointer: PCI-X */
5537 e1kPCICfgSetU8( pci, 0xDC + 1, 0xE4);
5538 /* Power Management Capabilities: PM disabled, DSI */
5539 e1kPCICfgSetU16(pci, 0xDC + 2, 0x0022);
5540 /* Power Management Control / Status Register: PM disabled */
5541 e1kPCICfgSetU16(pci, 0xDC + 4, 0x0000);
5542 /* PMCSR_BSE Bridge Support Extensions: Not supported */
5543 e1kPCICfgSetU8( pci, 0xDC + 6, 0x00);
5544 /* Data Register: PM disabled, always 0 */
5545 e1kPCICfgSetU8( pci, 0xDC + 7, 0x00);
5546
5547 /* PCI-X Configuration Registers *****************************************/
5548 /* Capability ID: PCI-X Configuration Registers */
5549 e1kPCICfgSetU8( pci, 0xE4, 0x07);
5550 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
5551 e1kPCICfgSetU8( pci, 0xE4 + 1, 0x00);
5552 /* PCI-X Command: Enable Relaxed Ordering */
5553 e1kPCICfgSetU16(pci, 0xE4 + 2, 0x0002);
5554 /* PCI-X Status: 32-bit, 66MHz*/
5555 e1kPCICfgSetU32(pci, 0xE4 + 4, 0x0040FFF8);
5556}
5557
5558/**
5559 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5560 */
5561static DECLCALLBACK(int) e1kConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5562{
5563 E1KSTATE* pState = PDMINS_2_DATA(pDevIns, E1KSTATE*);
5564 int rc;
5565 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5566
5567 /* Init handles and log related stuff. */
5568 RTStrPrintf(pState->szInstance, sizeof(pState->szInstance), "E1000#%d", iInstance);
5569 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
5570 pState->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
5571
5572 /*
5573 * Validate configuration.
5574 */
5575 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0" "LineSpeed\0"))
5576 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
5577 N_("Invalid configuration for E1000 device"));
5578
5579 /** @todo: LineSpeed unused! */
5580
5581 /* Get config params */
5582 rc = CFGMR3QueryBytes(pCfg, "MAC", pState->macConfigured.au8,
5583 sizeof(pState->macConfigured.au8));
5584 if (RT_FAILURE(rc))
5585 return PDMDEV_SET_ERROR(pDevIns, rc,
5586 N_("Configuration error: Failed to get MAC address"));
5587 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pState->fCableConnected);
5588 if (RT_FAILURE(rc))
5589 return PDMDEV_SET_ERROR(pDevIns, rc,
5590 N_("Configuration error: Failed to get the value of 'CableConnected'"));
5591 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pState->eChip);
5592 if (RT_FAILURE(rc))
5593 return PDMDEV_SET_ERROR(pDevIns, rc,
5594 N_("Configuration error: Failed to get the value of 'AdapterType'"));
5595 Assert(pState->eChip <= E1K_CHIP_82545EM);
5596
5597 E1kLog(("%s Chip=%s\n", INSTANCE(pState), g_Chips[pState->eChip].pcszName));
5598
5599 /* Initialize state structure */
5600 pState->fR0Enabled = true;
5601 pState->fGCEnabled = true;
5602 pState->pDevInsR3 = pDevIns;
5603 pState->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5604 pState->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5605 pState->u16TxPktLen = 0;
5606 pState->fIPcsum = false;
5607 pState->fTCPcsum = false;
5608 pState->fIntMaskUsed = false;
5609 pState->fDelayInts = false;
5610 pState->fLocked = false;
5611 pState->u64AckedAt = 0;
5612 pState->led.u32Magic = PDMLED_MAGIC;
5613 pState->u32PktNo = 1;
5614
5615#ifdef E1K_INT_STATS
5616 pState->uStatInt = 0;
5617 pState->uStatIntTry = 0;
5618 pState->uStatIntLower = 0;
5619 pState->uStatIntDly = 0;
5620 pState->uStatDisDly = 0;
5621 pState->iStatIntLost = 0;
5622 pState->iStatIntLostOne = 0;
5623 pState->uStatIntLate = 0;
5624 pState->uStatIntMasked = 0;
5625 pState->uStatIntEarly = 0;
5626 pState->uStatIntRx = 0;
5627 pState->uStatIntTx = 0;
5628 pState->uStatIntICS = 0;
5629 pState->uStatIntRDTR = 0;
5630 pState->uStatIntRXDMT0 = 0;
5631 pState->uStatIntTXQE = 0;
5632 pState->uStatTxNoRS = 0;
5633 pState->uStatTxIDE = 0;
5634 pState->uStatTAD = 0;
5635 pState->uStatTID = 0;
5636 pState->uStatRAD = 0;
5637 pState->uStatRID = 0;
5638 pState->uStatRxFrm = 0;
5639 pState->uStatTxFrm = 0;
5640 pState->uStatDescCtx = 0;
5641 pState->uStatDescDat = 0;
5642 pState->uStatDescLeg = 0;
5643#endif /* E1K_INT_STATS */
5644
5645 /* Interfaces */
5646 pState->IBase.pfnQueryInterface = e1kQueryInterface;
5647
5648 pState->INetworkDown.pfnWaitReceiveAvail = e1kNetworkDown_WaitReceiveAvail;
5649 pState->INetworkDown.pfnReceive = e1kNetworkDown_Receive;
5650 pState->INetworkDown.pfnXmitPending = e1kNetworkDown_XmitPending;
5651
5652 pState->ILeds.pfnQueryStatusLed = e1kQueryStatusLed;
5653
5654 pState->INetworkConfig.pfnGetMac = e1kGetMac;
5655 pState->INetworkConfig.pfnGetLinkState = e1kGetLinkState;
5656 pState->INetworkConfig.pfnSetLinkState = e1kSetLinkState;
5657
5658 /* Initialize the EEPROM */
5659 pState->eeprom.init(pState->macConfigured);
5660
5661 /* Initialize internal PHY */
5662 Phy::init(&pState->phy, iInstance,
5663 pState->eChip == E1K_CHIP_82543GC?
5664 PHY_EPID_M881000 : PHY_EPID_M881011);
5665 Phy::setLinkStatus(&pState->phy, pState->fCableConnected);
5666
5667 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
5668 NULL, e1kLiveExec, NULL,
5669 e1kSavePrep, e1kSaveExec, NULL,
5670 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
5671 if (RT_FAILURE(rc))
5672 return rc;
5673
5674 /* Initialize critical section */
5675 rc = PDMDevHlpCritSectInit(pDevIns, &pState->cs, RT_SRC_POS, "%s", pState->szInstance);
5676 if (RT_FAILURE(rc))
5677 return rc;
5678#ifndef E1K_GLOBAL_MUTEX
5679 rc = PDMDevHlpCritSectInit(pDevIns, &pState->csRx, RT_SRC_POS, "%sRX", pState->szInstance);
5680 if (RT_FAILURE(rc))
5681 return rc;
5682#endif
5683
5684 /* Set PCI config registers */
5685 e1kConfigurePCI(pState->pciDevice, pState->eChip);
5686 /* Register PCI device */
5687 rc = PDMDevHlpPCIRegister(pDevIns, &pState->pciDevice);
5688 if (RT_FAILURE(rc))
5689 return rc;
5690
5691 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
5692 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE,
5693 PCI_ADDRESS_SPACE_MEM, e1kMap);
5694 if (RT_FAILURE(rc))
5695 return rc;
5696 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
5697 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE,
5698 PCI_ADDRESS_SPACE_IO, e1kMap);
5699 if (RT_FAILURE(rc))
5700 return rc;
5701
5702 /* Create transmit queue */
5703 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5704 e1kTxQueueConsumer, true, "E1000-Xmit", &pState->pTxQueueR3);
5705 if (RT_FAILURE(rc))
5706 return rc;
5707 pState->pTxQueueR0 = PDMQueueR0Ptr(pState->pTxQueueR3);
5708 pState->pTxQueueRC = PDMQueueRCPtr(pState->pTxQueueR3);
5709
5710 /* Create the RX notifier signaller. */
5711 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
5712 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pState->pCanRxQueueR3);
5713 if (RT_FAILURE(rc))
5714 return rc;
5715 pState->pCanRxQueueR0 = PDMQueueR0Ptr(pState->pCanRxQueueR3);
5716 pState->pCanRxQueueRC = PDMQueueRCPtr(pState->pCanRxQueueR3);
5717
5718#ifdef E1K_USE_TX_TIMERS
5719 /* Create Transmit Interrupt Delay Timer */
5720 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pState,
5721 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5722 "E1000 Transmit Interrupt Delay Timer", &pState->pTIDTimerR3);
5723 if (RT_FAILURE(rc))
5724 return rc;
5725 pState->pTIDTimerR0 = TMTimerR0Ptr(pState->pTIDTimerR3);
5726 pState->pTIDTimerRC = TMTimerRCPtr(pState->pTIDTimerR3);
5727
5728# ifndef E1K_NO_TAD
5729 /* Create Transmit Absolute Delay Timer */
5730 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pState,
5731 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5732 "E1000 Transmit Absolute Delay Timer", &pState->pTADTimerR3);
5733 if (RT_FAILURE(rc))
5734 return rc;
5735 pState->pTADTimerR0 = TMTimerR0Ptr(pState->pTADTimerR3);
5736 pState->pTADTimerRC = TMTimerRCPtr(pState->pTADTimerR3);
5737# endif /* E1K_NO_TAD */
5738#endif /* E1K_USE_TX_TIMERS */
5739
5740#ifdef E1K_USE_RX_TIMERS
5741 /* Create Receive Interrupt Delay Timer */
5742 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pState,
5743 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5744 "E1000 Receive Interrupt Delay Timer", &pState->pRIDTimerR3);
5745 if (RT_FAILURE(rc))
5746 return rc;
5747 pState->pRIDTimerR0 = TMTimerR0Ptr(pState->pRIDTimerR3);
5748 pState->pRIDTimerRC = TMTimerRCPtr(pState->pRIDTimerR3);
5749
5750 /* Create Receive Absolute Delay Timer */
5751 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pState,
5752 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5753 "E1000 Receive Absolute Delay Timer", &pState->pRADTimerR3);
5754 if (RT_FAILURE(rc))
5755 return rc;
5756 pState->pRADTimerR0 = TMTimerR0Ptr(pState->pRADTimerR3);
5757 pState->pRADTimerRC = TMTimerRCPtr(pState->pRADTimerR3);
5758#endif /* E1K_USE_RX_TIMERS */
5759
5760 /* Create Late Interrupt Timer */
5761 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pState,
5762 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5763 "E1000 Late Interrupt Timer", &pState->pIntTimerR3);
5764 if (RT_FAILURE(rc))
5765 return rc;
5766 pState->pIntTimerR0 = TMTimerR0Ptr(pState->pIntTimerR3);
5767 pState->pIntTimerRC = TMTimerRCPtr(pState->pIntTimerR3);
5768
5769 /* Create Link Up Timer */
5770 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pState,
5771 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
5772 "E1000 Link Up Timer", &pState->pLUTimerR3);
5773 if (RT_FAILURE(rc))
5774 return rc;
5775 pState->pLUTimerR0 = TMTimerR0Ptr(pState->pLUTimerR3);
5776 pState->pLUTimerRC = TMTimerRCPtr(pState->pLUTimerR3);
5777
5778 /* Status driver */
5779 PPDMIBASE pBase;
5780 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pState->IBase, &pBase, "Status Port");
5781 if (RT_FAILURE(rc))
5782 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
5783 pState->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
5784
5785 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pState->IBase, &pState->pDrvBase, "Network Port");
5786 if (RT_SUCCESS(rc))
5787 {
5788 if (rc == VINF_NAT_DNS)
5789 {
5790 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
5791 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
5792 }
5793 pState->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMINETWORKUP);
5794 AssertMsgReturn(pState->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
5795 VERR_PDM_MISSING_INTERFACE_BELOW);
5796
5797 pState->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASER0), PDMINETWORKUP);
5798 pState->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pState->pDrvBase, PDMIBASERC), PDMINETWORKUP);
5799 }
5800 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
5801 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
5802 {
5803 /* No error! */
5804 E1kLog(("%s This adapter is not attached to any network!\n", INSTANCE(pState)));
5805 }
5806 else
5807 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
5808
5809 rc = RTSemEventCreate(&pState->hEventMoreRxDescAvail);
5810 if (RT_FAILURE(rc))
5811 return rc;
5812
5813 e1kHardReset(pState);
5814
5815#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5816 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/E1k%d/MMIO/ReadGC", iInstance);
5817 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/E1k%d/MMIO/ReadHC", iInstance);
5818 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/E1k%d/MMIO/WriteGC", iInstance);
5819 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/E1k%d/MMIO/WriteHC", iInstance);
5820 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
5821 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
5822 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/E1k%d/IO/ReadGC", iInstance);
5823 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/E1k%d/IO/ReadHC", iInstance);
5824 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/E1k%d/IO/WriteGC", iInstance);
5825 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/E1k%d/IO/WriteHC", iInstance);
5826 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
5827 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
5828 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
5829 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
5830 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
5831 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
5832 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
5833 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
5834 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
5835#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5836 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
5837#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5838 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/E1k%d/Transmit/Total", iInstance);
5839#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5840 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
5841#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
5842 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in HC", "/Devices/E1k%d/Transmit/Send", iInstance);
5843
5844 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
5845 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
5846 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
5847 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
5848 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
5849 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
5850 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
5851 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
5852 PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
5853#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
5854
5855 return VINF_SUCCESS;
5856}
5857
5858/**
5859 * The device registration structure.
5860 */
5861const PDMDEVREG g_DeviceE1000 =
5862{
5863 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
5864 PDM_DEVREG_VERSION,
5865 /* Device name. */
5866 "e1000",
5867 /* Name of guest context module (no path).
5868 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5869 "VBoxDDGC.gc",
5870 /* Name of ring-0 module (no path).
5871 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
5872 "VBoxDDR0.r0",
5873 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
5874 * remain unchanged from registration till VM destruction. */
5875 "Intel PRO/1000 MT Desktop Ethernet.\n",
5876
5877 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
5878 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
5879 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
5880 PDM_DEVREG_CLASS_NETWORK,
5881 /* Maximum number of instances (per VM). */
5882 8,
5883 /* Size of the instance data. */
5884 sizeof(E1KSTATE),
5885
5886 /* Construct instance - required. */
5887 e1kConstruct,
5888 /* Destruct instance - optional. */
5889 e1kDestruct,
5890 /* Relocation command - optional. */
5891 e1kRelocate,
5892 /* I/O Control interface - optional. */
5893 NULL,
5894 /* Power on notification - optional. */
5895 NULL,
5896 /* Reset notification - optional. */
5897 NULL,
5898 /* Suspend notification - optional. */
5899 e1kSuspend,
5900 /* Resume notification - optional. */
5901 NULL,
5902#ifdef VBOX_DYNAMIC_NET_ATTACH
5903 /* Attach command - optional. */
5904 e1kAttach,
5905 /* Detach notification - optional. */
5906 e1kDetach,
5907#else /* !VBOX_DYNAMIC_NET_ATTACH */
5908 /* Attach command - optional. */
5909 NULL,
5910 /* Detach notification - optional. */
5911 NULL,
5912#endif /* !VBOX_DYNAMIC_NET_ATTACH */
5913 /* Query a LUN base interface - optional. */
5914 NULL,
5915 /* Init complete notification - optional. */
5916 NULL,
5917 /* Power off notification - optional. */
5918 e1kPowerOff,
5919 /* pfnSoftReset */
5920 NULL,
5921 /* u32VersionEnd */
5922 PDM_DEVREG_VERSION
5923};
5924
5925#endif /* IN_RING3 */
5926#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5927
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette