VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 62528

Last change on this file since 62528 was 62511, checked in by vboxsync, 9 years ago

(C) 2016
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 317.0 KB
Line 
1/* $Id: DevE1000.cpp 62511 2016-07-22 19:12:58Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2016 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/* Options *******************************************************************/
51/** @def E1K_INIT_RA0
52 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
53 * table to MAC address obtained from CFGM. Most guests read MAC address from
54 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
55 * being already set (see @bugref{4657}).
56 */
57#define E1K_INIT_RA0
58/** @def E1K_LSC_ON_SLU
59 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
60 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
61 * that requires it is Mac OS X (see @bugref{4657}).
62 */
63#define E1K_LSC_ON_SLU
64/** @def E1K_TX_DELAY
65 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
66 * preventing packets to be sent immediately. It allows to send several
67 * packets in a batch reducing the number of acknowledgments. Note that it
68 * effectively disables R0 TX path, forcing sending in R3.
69 */
70//#define E1K_TX_DELAY 150
71/** @def E1K_USE_TX_TIMERS
72 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
73 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
74 * register. Enabling it showed no positive effects on existing guests so it
75 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
76 * Ethernet Controllers Software Developer’s Manual" for more detailed
77 * explanation.
78 */
79//#define E1K_USE_TX_TIMERS
80/** @def E1K_NO_TAD
81 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
82 * Transmit Absolute Delay time. This timer sets the maximum time interval
83 * during which TX interrupts can be postponed (delayed). It has no effect
84 * if E1K_USE_TX_TIMERS is not defined.
85 */
86//#define E1K_NO_TAD
87/** @def E1K_REL_DEBUG
88 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
89 */
90//#define E1K_REL_DEBUG
91/** @def E1K_INT_STATS
92 * E1K_INT_STATS enables collection of internal statistics used for
93 * debugging of delayed interrupts, etc.
94 */
95//#define E1K_INT_STATS
96/** @def E1K_WITH_MSI
97 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
98 */
99//#define E1K_WITH_MSI
100/** @def E1K_WITH_TX_CS
101 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
102 */
103#define E1K_WITH_TX_CS
104/** @def E1K_WITH_TXD_CACHE
105 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
106 * single physical memory read (or two if it wraps around the end of TX
107 * descriptor ring). It is required for proper functioning of bandwidth
108 * resource control as it allows to compute exact sizes of packets prior
109 * to allocating their buffers (see @bugref{5582}).
110 */
111#define E1K_WITH_TXD_CACHE
112/** @def E1K_WITH_RXD_CACHE
113 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
114 * single physical memory read (or two if it wraps around the end of RX
115 * descriptor ring). Intel's packet driver for DOS needs this option in
116 * order to work properly (see @bugref{6217}).
117 */
118#define E1K_WITH_RXD_CACHE
119/* End of Options ************************************************************/
120
121#ifdef E1K_WITH_TXD_CACHE
122/**
123 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
124 * in the state structure. It limits the amount of descriptors loaded in one
125 * batch read. For example, Linux guest may use up to 20 descriptors per
126 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
127 */
128# define E1K_TXD_CACHE_SIZE 64u
129#endif /* E1K_WITH_TXD_CACHE */
130
131#ifdef E1K_WITH_RXD_CACHE
132/**
133 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
134 * in the state structure. It limits the amount of descriptors loaded in one
135 * batch read. For example, XP guest adds 15 RX descriptors at a time.
136 */
137# define E1K_RXD_CACHE_SIZE 16u
138#endif /* E1K_WITH_RXD_CACHE */
139
140
141/* Little helpers ************************************************************/
142#undef htons
143#undef ntohs
144#undef htonl
145#undef ntohl
146#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
147#define ntohs(x) htons(x)
148#define htonl(x) ASMByteSwapU32(x)
149#define ntohl(x) htonl(x)
150
151#ifndef DEBUG
152# ifdef E1K_REL_DEBUG
153# define DEBUG
154# define E1kLog(a) LogRel(a)
155# define E1kLog2(a) LogRel(a)
156# define E1kLog3(a) LogRel(a)
157# define E1kLogX(x, a) LogRel(a)
158//# define E1kLog3(a) do {} while (0)
159# else
160# define E1kLog(a) do {} while (0)
161# define E1kLog2(a) do {} while (0)
162# define E1kLog3(a) do {} while (0)
163# define E1kLogX(x, a) do {} while (0)
164# endif
165#else
166# define E1kLog(a) Log(a)
167# define E1kLog2(a) Log2(a)
168# define E1kLog3(a) Log3(a)
169# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
170//# define E1kLog(a) do {} while (0)
171//# define E1kLog2(a) do {} while (0)
172//# define E1kLog3(a) do {} while (0)
173#endif
174
175#if 0
176# define LOG_ENABLED
177# define E1kLogRel(a) LogRel(a)
178# undef Log6
179# define Log6(a) LogRel(a)
180#else
181# define E1kLogRel(a) do { } while (0)
182#endif
183
184//#undef DEBUG
185
186#define STATE_TO_DEVINS(pThis) (((PE1KSTATE )pThis)->CTX_SUFF(pDevIns))
187#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
188
189#define E1K_INC_CNT32(cnt) \
190do { \
191 if (cnt < UINT32_MAX) \
192 cnt++; \
193} while (0)
194
195#define E1K_ADD_CNT64(cntLo, cntHi, val) \
196do { \
197 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
198 uint64_t tmp = u64Cnt; \
199 u64Cnt += val; \
200 if (tmp > u64Cnt ) \
201 u64Cnt = UINT64_MAX; \
202 cntLo = (uint32_t)u64Cnt; \
203 cntHi = (uint32_t)(u64Cnt >> 32); \
204} while (0)
205
206#ifdef E1K_INT_STATS
207# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
208#else /* E1K_INT_STATS */
209# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
210#endif /* E1K_INT_STATS */
211
212
213/*****************************************************************************/
214
215typedef uint32_t E1KCHIP;
216#define E1K_CHIP_82540EM 0
217#define E1K_CHIP_82543GC 1
218#define E1K_CHIP_82545EM 2
219
220/** Different E1000 chips. */
221static const struct E1kChips
222{
223 uint16_t uPCIVendorId;
224 uint16_t uPCIDeviceId;
225 uint16_t uPCISubsystemVendorId;
226 uint16_t uPCISubsystemId;
227 const char *pcszName;
228} g_Chips[] =
229{
230 /* Vendor Device SSVendor SubSys Name */
231 { 0x8086,
232 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
233#ifdef E1K_WITH_MSI
234 0x105E,
235#else
236 0x100E,
237#endif
238 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
239 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
240 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
241};
242
243
244/* The size of register area mapped to I/O space */
245#define E1K_IOPORT_SIZE 0x8
246/* The size of memory-mapped register area */
247#define E1K_MM_SIZE 0x20000
248
249#define E1K_MAX_TX_PKT_SIZE 16288
250#define E1K_MAX_RX_PKT_SIZE 16384
251
252/*****************************************************************************/
253
254/** Gets the specfieid bits from the register. */
255#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
256#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
257#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
258#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
259#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
260
261#define CTRL_SLU UINT32_C(0x00000040)
262#define CTRL_MDIO UINT32_C(0x00100000)
263#define CTRL_MDC UINT32_C(0x00200000)
264#define CTRL_MDIO_DIR UINT32_C(0x01000000)
265#define CTRL_MDC_DIR UINT32_C(0x02000000)
266#define CTRL_RESET UINT32_C(0x04000000)
267#define CTRL_VME UINT32_C(0x40000000)
268
269#define STATUS_LU UINT32_C(0x00000002)
270#define STATUS_TXOFF UINT32_C(0x00000010)
271
272#define EECD_EE_WIRES UINT32_C(0x0F)
273#define EECD_EE_REQ UINT32_C(0x40)
274#define EECD_EE_GNT UINT32_C(0x80)
275
276#define EERD_START UINT32_C(0x00000001)
277#define EERD_DONE UINT32_C(0x00000010)
278#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
279#define EERD_DATA_SHIFT 16
280#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
281#define EERD_ADDR_SHIFT 8
282
283#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
284#define MDIC_DATA_SHIFT 0
285#define MDIC_REG_MASK UINT32_C(0x001F0000)
286#define MDIC_REG_SHIFT 16
287#define MDIC_PHY_MASK UINT32_C(0x03E00000)
288#define MDIC_PHY_SHIFT 21
289#define MDIC_OP_WRITE UINT32_C(0x04000000)
290#define MDIC_OP_READ UINT32_C(0x08000000)
291#define MDIC_READY UINT32_C(0x10000000)
292#define MDIC_INT_EN UINT32_C(0x20000000)
293#define MDIC_ERROR UINT32_C(0x40000000)
294
295#define TCTL_EN UINT32_C(0x00000002)
296#define TCTL_PSP UINT32_C(0x00000008)
297
298#define RCTL_EN UINT32_C(0x00000002)
299#define RCTL_UPE UINT32_C(0x00000008)
300#define RCTL_MPE UINT32_C(0x00000010)
301#define RCTL_LPE UINT32_C(0x00000020)
302#define RCTL_LBM_MASK UINT32_C(0x000000C0)
303#define RCTL_LBM_SHIFT 6
304#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
305#define RCTL_RDMTS_SHIFT 8
306#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
307#define RCTL_MO_MASK UINT32_C(0x00003000)
308#define RCTL_MO_SHIFT 12
309#define RCTL_BAM UINT32_C(0x00008000)
310#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
311#define RCTL_BSIZE_SHIFT 16
312#define RCTL_VFE UINT32_C(0x00040000)
313#define RCTL_CFIEN UINT32_C(0x00080000)
314#define RCTL_CFI UINT32_C(0x00100000)
315#define RCTL_BSEX UINT32_C(0x02000000)
316#define RCTL_SECRC UINT32_C(0x04000000)
317
318#define ICR_TXDW UINT32_C(0x00000001)
319#define ICR_TXQE UINT32_C(0x00000002)
320#define ICR_LSC UINT32_C(0x00000004)
321#define ICR_RXDMT0 UINT32_C(0x00000010)
322#define ICR_RXT0 UINT32_C(0x00000080)
323#define ICR_TXD_LOW UINT32_C(0x00008000)
324#define RDTR_FPD UINT32_C(0x80000000)
325
326#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
327typedef struct
328{
329 unsigned rxa : 7;
330 unsigned rxa_r : 9;
331 unsigned txa : 16;
332} PBAST;
333AssertCompileSize(PBAST, 4);
334
335#define TXDCTL_WTHRESH_MASK 0x003F0000
336#define TXDCTL_WTHRESH_SHIFT 16
337#define TXDCTL_LWTHRESH_MASK 0xFE000000
338#define TXDCTL_LWTHRESH_SHIFT 25
339
340#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
341#define RXCSUM_PCSS_SHIFT 0
342
343/** @name Register access macros
344 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
345 * @{ */
346#define CTRL pThis->auRegs[CTRL_IDX]
347#define STATUS pThis->auRegs[STATUS_IDX]
348#define EECD pThis->auRegs[EECD_IDX]
349#define EERD pThis->auRegs[EERD_IDX]
350#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
351#define FLA pThis->auRegs[FLA_IDX]
352#define MDIC pThis->auRegs[MDIC_IDX]
353#define FCAL pThis->auRegs[FCAL_IDX]
354#define FCAH pThis->auRegs[FCAH_IDX]
355#define FCT pThis->auRegs[FCT_IDX]
356#define VET pThis->auRegs[VET_IDX]
357#define ICR pThis->auRegs[ICR_IDX]
358#define ITR pThis->auRegs[ITR_IDX]
359#define ICS pThis->auRegs[ICS_IDX]
360#define IMS pThis->auRegs[IMS_IDX]
361#define IMC pThis->auRegs[IMC_IDX]
362#define RCTL pThis->auRegs[RCTL_IDX]
363#define FCTTV pThis->auRegs[FCTTV_IDX]
364#define TXCW pThis->auRegs[TXCW_IDX]
365#define RXCW pThis->auRegs[RXCW_IDX]
366#define TCTL pThis->auRegs[TCTL_IDX]
367#define TIPG pThis->auRegs[TIPG_IDX]
368#define AIFS pThis->auRegs[AIFS_IDX]
369#define LEDCTL pThis->auRegs[LEDCTL_IDX]
370#define PBA pThis->auRegs[PBA_IDX]
371#define FCRTL pThis->auRegs[FCRTL_IDX]
372#define FCRTH pThis->auRegs[FCRTH_IDX]
373#define RDFH pThis->auRegs[RDFH_IDX]
374#define RDFT pThis->auRegs[RDFT_IDX]
375#define RDFHS pThis->auRegs[RDFHS_IDX]
376#define RDFTS pThis->auRegs[RDFTS_IDX]
377#define RDFPC pThis->auRegs[RDFPC_IDX]
378#define RDBAL pThis->auRegs[RDBAL_IDX]
379#define RDBAH pThis->auRegs[RDBAH_IDX]
380#define RDLEN pThis->auRegs[RDLEN_IDX]
381#define RDH pThis->auRegs[RDH_IDX]
382#define RDT pThis->auRegs[RDT_IDX]
383#define RDTR pThis->auRegs[RDTR_IDX]
384#define RXDCTL pThis->auRegs[RXDCTL_IDX]
385#define RADV pThis->auRegs[RADV_IDX]
386#define RSRPD pThis->auRegs[RSRPD_IDX]
387#define TXDMAC pThis->auRegs[TXDMAC_IDX]
388#define TDFH pThis->auRegs[TDFH_IDX]
389#define TDFT pThis->auRegs[TDFT_IDX]
390#define TDFHS pThis->auRegs[TDFHS_IDX]
391#define TDFTS pThis->auRegs[TDFTS_IDX]
392#define TDFPC pThis->auRegs[TDFPC_IDX]
393#define TDBAL pThis->auRegs[TDBAL_IDX]
394#define TDBAH pThis->auRegs[TDBAH_IDX]
395#define TDLEN pThis->auRegs[TDLEN_IDX]
396#define TDH pThis->auRegs[TDH_IDX]
397#define TDT pThis->auRegs[TDT_IDX]
398#define TIDV pThis->auRegs[TIDV_IDX]
399#define TXDCTL pThis->auRegs[TXDCTL_IDX]
400#define TADV pThis->auRegs[TADV_IDX]
401#define TSPMT pThis->auRegs[TSPMT_IDX]
402#define CRCERRS pThis->auRegs[CRCERRS_IDX]
403#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
404#define SYMERRS pThis->auRegs[SYMERRS_IDX]
405#define RXERRC pThis->auRegs[RXERRC_IDX]
406#define MPC pThis->auRegs[MPC_IDX]
407#define SCC pThis->auRegs[SCC_IDX]
408#define ECOL pThis->auRegs[ECOL_IDX]
409#define MCC pThis->auRegs[MCC_IDX]
410#define LATECOL pThis->auRegs[LATECOL_IDX]
411#define COLC pThis->auRegs[COLC_IDX]
412#define DC pThis->auRegs[DC_IDX]
413#define TNCRS pThis->auRegs[TNCRS_IDX]
414/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
415#define CEXTERR pThis->auRegs[CEXTERR_IDX]
416#define RLEC pThis->auRegs[RLEC_IDX]
417#define XONRXC pThis->auRegs[XONRXC_IDX]
418#define XONTXC pThis->auRegs[XONTXC_IDX]
419#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
420#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
421#define FCRUC pThis->auRegs[FCRUC_IDX]
422#define PRC64 pThis->auRegs[PRC64_IDX]
423#define PRC127 pThis->auRegs[PRC127_IDX]
424#define PRC255 pThis->auRegs[PRC255_IDX]
425#define PRC511 pThis->auRegs[PRC511_IDX]
426#define PRC1023 pThis->auRegs[PRC1023_IDX]
427#define PRC1522 pThis->auRegs[PRC1522_IDX]
428#define GPRC pThis->auRegs[GPRC_IDX]
429#define BPRC pThis->auRegs[BPRC_IDX]
430#define MPRC pThis->auRegs[MPRC_IDX]
431#define GPTC pThis->auRegs[GPTC_IDX]
432#define GORCL pThis->auRegs[GORCL_IDX]
433#define GORCH pThis->auRegs[GORCH_IDX]
434#define GOTCL pThis->auRegs[GOTCL_IDX]
435#define GOTCH pThis->auRegs[GOTCH_IDX]
436#define RNBC pThis->auRegs[RNBC_IDX]
437#define RUC pThis->auRegs[RUC_IDX]
438#define RFC pThis->auRegs[RFC_IDX]
439#define ROC pThis->auRegs[ROC_IDX]
440#define RJC pThis->auRegs[RJC_IDX]
441#define MGTPRC pThis->auRegs[MGTPRC_IDX]
442#define MGTPDC pThis->auRegs[MGTPDC_IDX]
443#define MGTPTC pThis->auRegs[MGTPTC_IDX]
444#define TORL pThis->auRegs[TORL_IDX]
445#define TORH pThis->auRegs[TORH_IDX]
446#define TOTL pThis->auRegs[TOTL_IDX]
447#define TOTH pThis->auRegs[TOTH_IDX]
448#define TPR pThis->auRegs[TPR_IDX]
449#define TPT pThis->auRegs[TPT_IDX]
450#define PTC64 pThis->auRegs[PTC64_IDX]
451#define PTC127 pThis->auRegs[PTC127_IDX]
452#define PTC255 pThis->auRegs[PTC255_IDX]
453#define PTC511 pThis->auRegs[PTC511_IDX]
454#define PTC1023 pThis->auRegs[PTC1023_IDX]
455#define PTC1522 pThis->auRegs[PTC1522_IDX]
456#define MPTC pThis->auRegs[MPTC_IDX]
457#define BPTC pThis->auRegs[BPTC_IDX]
458#define TSCTC pThis->auRegs[TSCTC_IDX]
459#define TSCTFC pThis->auRegs[TSCTFC_IDX]
460#define RXCSUM pThis->auRegs[RXCSUM_IDX]
461#define WUC pThis->auRegs[WUC_IDX]
462#define WUFC pThis->auRegs[WUFC_IDX]
463#define WUS pThis->auRegs[WUS_IDX]
464#define MANC pThis->auRegs[MANC_IDX]
465#define IPAV pThis->auRegs[IPAV_IDX]
466#define WUPL pThis->auRegs[WUPL_IDX]
467/** @} */
468
469/**
470 * Indices of memory-mapped registers in register table.
471 */
472typedef enum
473{
474 CTRL_IDX,
475 STATUS_IDX,
476 EECD_IDX,
477 EERD_IDX,
478 CTRL_EXT_IDX,
479 FLA_IDX,
480 MDIC_IDX,
481 FCAL_IDX,
482 FCAH_IDX,
483 FCT_IDX,
484 VET_IDX,
485 ICR_IDX,
486 ITR_IDX,
487 ICS_IDX,
488 IMS_IDX,
489 IMC_IDX,
490 RCTL_IDX,
491 FCTTV_IDX,
492 TXCW_IDX,
493 RXCW_IDX,
494 TCTL_IDX,
495 TIPG_IDX,
496 AIFS_IDX,
497 LEDCTL_IDX,
498 PBA_IDX,
499 FCRTL_IDX,
500 FCRTH_IDX,
501 RDFH_IDX,
502 RDFT_IDX,
503 RDFHS_IDX,
504 RDFTS_IDX,
505 RDFPC_IDX,
506 RDBAL_IDX,
507 RDBAH_IDX,
508 RDLEN_IDX,
509 RDH_IDX,
510 RDT_IDX,
511 RDTR_IDX,
512 RXDCTL_IDX,
513 RADV_IDX,
514 RSRPD_IDX,
515 TXDMAC_IDX,
516 TDFH_IDX,
517 TDFT_IDX,
518 TDFHS_IDX,
519 TDFTS_IDX,
520 TDFPC_IDX,
521 TDBAL_IDX,
522 TDBAH_IDX,
523 TDLEN_IDX,
524 TDH_IDX,
525 TDT_IDX,
526 TIDV_IDX,
527 TXDCTL_IDX,
528 TADV_IDX,
529 TSPMT_IDX,
530 CRCERRS_IDX,
531 ALGNERRC_IDX,
532 SYMERRS_IDX,
533 RXERRC_IDX,
534 MPC_IDX,
535 SCC_IDX,
536 ECOL_IDX,
537 MCC_IDX,
538 LATECOL_IDX,
539 COLC_IDX,
540 DC_IDX,
541 TNCRS_IDX,
542 SEC_IDX,
543 CEXTERR_IDX,
544 RLEC_IDX,
545 XONRXC_IDX,
546 XONTXC_IDX,
547 XOFFRXC_IDX,
548 XOFFTXC_IDX,
549 FCRUC_IDX,
550 PRC64_IDX,
551 PRC127_IDX,
552 PRC255_IDX,
553 PRC511_IDX,
554 PRC1023_IDX,
555 PRC1522_IDX,
556 GPRC_IDX,
557 BPRC_IDX,
558 MPRC_IDX,
559 GPTC_IDX,
560 GORCL_IDX,
561 GORCH_IDX,
562 GOTCL_IDX,
563 GOTCH_IDX,
564 RNBC_IDX,
565 RUC_IDX,
566 RFC_IDX,
567 ROC_IDX,
568 RJC_IDX,
569 MGTPRC_IDX,
570 MGTPDC_IDX,
571 MGTPTC_IDX,
572 TORL_IDX,
573 TORH_IDX,
574 TOTL_IDX,
575 TOTH_IDX,
576 TPR_IDX,
577 TPT_IDX,
578 PTC64_IDX,
579 PTC127_IDX,
580 PTC255_IDX,
581 PTC511_IDX,
582 PTC1023_IDX,
583 PTC1522_IDX,
584 MPTC_IDX,
585 BPTC_IDX,
586 TSCTC_IDX,
587 TSCTFC_IDX,
588 RXCSUM_IDX,
589 WUC_IDX,
590 WUFC_IDX,
591 WUS_IDX,
592 MANC_IDX,
593 IPAV_IDX,
594 WUPL_IDX,
595 MTA_IDX,
596 RA_IDX,
597 VFTA_IDX,
598 IP4AT_IDX,
599 IP6AT_IDX,
600 WUPM_IDX,
601 FFLT_IDX,
602 FFMT_IDX,
603 FFVT_IDX,
604 PBM_IDX,
605 RA_82542_IDX,
606 MTA_82542_IDX,
607 VFTA_82542_IDX,
608 E1K_NUM_OF_REGS
609} E1kRegIndex;
610
611#define E1K_NUM_OF_32BIT_REGS MTA_IDX
612/** The number of registers with strictly increasing offset. */
613#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
614
615
616/**
617 * Define E1000-specific EEPROM layout.
618 */
619struct E1kEEPROM
620{
621 public:
622 EEPROM93C46 eeprom;
623
624#ifdef IN_RING3
625 /**
626 * Initialize EEPROM content.
627 *
628 * @param macAddr MAC address of E1000.
629 */
630 void init(RTMAC &macAddr)
631 {
632 eeprom.init();
633 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
634 eeprom.m_au16Data[0x04] = 0xFFFF;
635 /*
636 * bit 3 - full support for power management
637 * bit 10 - full duplex
638 */
639 eeprom.m_au16Data[0x0A] = 0x4408;
640 eeprom.m_au16Data[0x0B] = 0x001E;
641 eeprom.m_au16Data[0x0C] = 0x8086;
642 eeprom.m_au16Data[0x0D] = 0x100E;
643 eeprom.m_au16Data[0x0E] = 0x8086;
644 eeprom.m_au16Data[0x0F] = 0x3040;
645 eeprom.m_au16Data[0x21] = 0x7061;
646 eeprom.m_au16Data[0x22] = 0x280C;
647 eeprom.m_au16Data[0x23] = 0x00C8;
648 eeprom.m_au16Data[0x24] = 0x00C8;
649 eeprom.m_au16Data[0x2F] = 0x0602;
650 updateChecksum();
651 };
652
653 /**
654 * Compute the checksum as required by E1000 and store it
655 * in the last word.
656 */
657 void updateChecksum()
658 {
659 uint16_t u16Checksum = 0;
660
661 for (int i = 0; i < eeprom.SIZE-1; i++)
662 u16Checksum += eeprom.m_au16Data[i];
663 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
664 };
665
666 /**
667 * First 6 bytes of EEPROM contain MAC address.
668 *
669 * @returns MAC address of E1000.
670 */
671 void getMac(PRTMAC pMac)
672 {
673 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
674 };
675
676 uint32_t read()
677 {
678 return eeprom.read();
679 }
680
681 void write(uint32_t u32Wires)
682 {
683 eeprom.write(u32Wires);
684 }
685
686 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
687 {
688 return eeprom.readWord(u32Addr, pu16Value);
689 }
690
691 int load(PSSMHANDLE pSSM)
692 {
693 return eeprom.load(pSSM);
694 }
695
696 void save(PSSMHANDLE pSSM)
697 {
698 eeprom.save(pSSM);
699 }
700#endif /* IN_RING3 */
701};
702
703
704#define E1K_SPEC_VLAN(s) (s & 0xFFF)
705#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
706#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
707
708struct E1kRxDStatus
709{
710 /** @name Descriptor Status field (3.2.3.1)
711 * @{ */
712 unsigned fDD : 1; /**< Descriptor Done. */
713 unsigned fEOP : 1; /**< End of packet. */
714 unsigned fIXSM : 1; /**< Ignore checksum indication. */
715 unsigned fVP : 1; /**< VLAN, matches VET. */
716 unsigned : 1;
717 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
718 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
719 unsigned fPIF : 1; /**< Passed in-exact filter */
720 /** @} */
721 /** @name Descriptor Errors field (3.2.3.2)
722 * (Only valid when fEOP and fDD are set.)
723 * @{ */
724 unsigned fCE : 1; /**< CRC or alignment error. */
725 unsigned : 4; /**< Reserved, varies with different models... */
726 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
727 unsigned fIPE : 1; /**< IP Checksum error. */
728 unsigned fRXE : 1; /**< RX Data error. */
729 /** @} */
730 /** @name Descriptor Special field (3.2.3.3)
731 * @{ */
732 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
733 /** @} */
734};
735typedef struct E1kRxDStatus E1KRXDST;
736
737struct E1kRxDesc_st
738{
739 uint64_t u64BufAddr; /**< Address of data buffer */
740 uint16_t u16Length; /**< Length of data in buffer */
741 uint16_t u16Checksum; /**< Packet checksum */
742 E1KRXDST status;
743};
744typedef struct E1kRxDesc_st E1KRXDESC;
745AssertCompileSize(E1KRXDESC, 16);
746
747#define E1K_DTYP_LEGACY -1
748#define E1K_DTYP_CONTEXT 0
749#define E1K_DTYP_DATA 1
750
751struct E1kTDLegacy
752{
753 uint64_t u64BufAddr; /**< Address of data buffer */
754 struct TDLCmd_st
755 {
756 unsigned u16Length : 16;
757 unsigned u8CSO : 8;
758 /* CMD field : 8 */
759 unsigned fEOP : 1;
760 unsigned fIFCS : 1;
761 unsigned fIC : 1;
762 unsigned fRS : 1;
763 unsigned fRPS : 1;
764 unsigned fDEXT : 1;
765 unsigned fVLE : 1;
766 unsigned fIDE : 1;
767 } cmd;
768 struct TDLDw3_st
769 {
770 /* STA field */
771 unsigned fDD : 1;
772 unsigned fEC : 1;
773 unsigned fLC : 1;
774 unsigned fTURSV : 1;
775 /* RSV field */
776 unsigned u4RSV : 4;
777 /* CSS field */
778 unsigned u8CSS : 8;
779 /* Special field*/
780 unsigned u16Special: 16;
781 } dw3;
782};
783
784/**
785 * TCP/IP Context Transmit Descriptor, section 3.3.6.
786 */
787struct E1kTDContext
788{
789 struct CheckSum_st
790 {
791 /** TSE: Header start. !TSE: Checksum start. */
792 unsigned u8CSS : 8;
793 /** Checksum offset - where to store it. */
794 unsigned u8CSO : 8;
795 /** Checksum ending (inclusive) offset, 0 = end of packet. */
796 unsigned u16CSE : 16;
797 } ip;
798 struct CheckSum_st tu;
799 struct TDCDw2_st
800 {
801 /** TSE: The total number of payload bytes for this context. Sans header. */
802 unsigned u20PAYLEN : 20;
803 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
804 unsigned u4DTYP : 4;
805 /** TUCMD field, 8 bits
806 * @{ */
807 /** TSE: TCP (set) or UDP (clear). */
808 unsigned fTCP : 1;
809 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
810 * the IP header. Does not affect the checksumming.
811 * @remarks 82544GC/EI interprets a cleared field differently. */
812 unsigned fIP : 1;
813 /** TSE: TCP segmentation enable. When clear the context describes */
814 unsigned fTSE : 1;
815 /** Report status (only applies to dw3.fDD for here). */
816 unsigned fRS : 1;
817 /** Reserved, MBZ. */
818 unsigned fRSV1 : 1;
819 /** Descriptor extension, must be set for this descriptor type. */
820 unsigned fDEXT : 1;
821 /** Reserved, MBZ. */
822 unsigned fRSV2 : 1;
823 /** Interrupt delay enable. */
824 unsigned fIDE : 1;
825 /** @} */
826 } dw2;
827 struct TDCDw3_st
828 {
829 /** Descriptor Done. */
830 unsigned fDD : 1;
831 /** Reserved, MBZ. */
832 unsigned u7RSV : 7;
833 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
834 unsigned u8HDRLEN : 8;
835 /** TSO: Maximum segment size. */
836 unsigned u16MSS : 16;
837 } dw3;
838};
839typedef struct E1kTDContext E1KTXCTX;
840
841/**
842 * TCP/IP Data Transmit Descriptor, section 3.3.7.
843 */
844struct E1kTDData
845{
846 uint64_t u64BufAddr; /**< Address of data buffer */
847 struct TDDCmd_st
848 {
849 /** The total length of data pointed to by this descriptor. */
850 unsigned u20DTALEN : 20;
851 /** The descriptor type - E1K_DTYP_DATA (1). */
852 unsigned u4DTYP : 4;
853 /** @name DCMD field, 8 bits (3.3.7.1).
854 * @{ */
855 /** End of packet. Note TSCTFC update. */
856 unsigned fEOP : 1;
857 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
858 unsigned fIFCS : 1;
859 /** Use the TSE context when set and the normal when clear. */
860 unsigned fTSE : 1;
861 /** Report status (dw3.STA). */
862 unsigned fRS : 1;
863 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
864 unsigned fRPS : 1;
865 /** Descriptor extension, must be set for this descriptor type. */
866 unsigned fDEXT : 1;
867 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
868 * Insert dw3.SPECIAL after ethernet header. */
869 unsigned fVLE : 1;
870 /** Interrupt delay enable. */
871 unsigned fIDE : 1;
872 /** @} */
873 } cmd;
874 struct TDDDw3_st
875 {
876 /** @name STA field (3.3.7.2)
877 * @{ */
878 unsigned fDD : 1; /**< Descriptor done. */
879 unsigned fEC : 1; /**< Excess collision. */
880 unsigned fLC : 1; /**< Late collision. */
881 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
882 unsigned fTURSV : 1;
883 /** @} */
884 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
885 /** @name POPTS (Packet Option) field (3.3.7.3)
886 * @{ */
887 unsigned fIXSM : 1; /**< Insert IP checksum. */
888 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
889 unsigned u6RSV : 6; /**< Reserved, MBZ. */
890 /** @} */
891 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
892 * Requires fEOP, fVLE and CTRL.VME to be set.
893 * @{ */
894 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
895 /** @} */
896 } dw3;
897};
898typedef struct E1kTDData E1KTXDAT;
899
900union E1kTxDesc
901{
902 struct E1kTDLegacy legacy;
903 struct E1kTDContext context;
904 struct E1kTDData data;
905};
906typedef union E1kTxDesc E1KTXDESC;
907AssertCompileSize(E1KTXDESC, 16);
908
909#define RA_CTL_AS 0x0003
910#define RA_CTL_AV 0x8000
911
912union E1kRecAddr
913{
914 uint32_t au32[32];
915 struct RAArray
916 {
917 uint8_t addr[6];
918 uint16_t ctl;
919 } array[16];
920};
921typedef struct E1kRecAddr::RAArray E1KRAELEM;
922typedef union E1kRecAddr E1KRA;
923AssertCompileSize(E1KRA, 8*16);
924
925#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
926#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
927#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
928#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
929
930/** @todo use+extend RTNETIPV4 */
931struct E1kIpHeader
932{
933 /* type of service / version / header length */
934 uint16_t tos_ver_hl;
935 /* total length */
936 uint16_t total_len;
937 /* identification */
938 uint16_t ident;
939 /* fragment offset field */
940 uint16_t offset;
941 /* time to live / protocol*/
942 uint16_t ttl_proto;
943 /* checksum */
944 uint16_t chksum;
945 /* source IP address */
946 uint32_t src;
947 /* destination IP address */
948 uint32_t dest;
949};
950AssertCompileSize(struct E1kIpHeader, 20);
951
952#define E1K_TCP_FIN UINT16_C(0x01)
953#define E1K_TCP_SYN UINT16_C(0x02)
954#define E1K_TCP_RST UINT16_C(0x04)
955#define E1K_TCP_PSH UINT16_C(0x08)
956#define E1K_TCP_ACK UINT16_C(0x10)
957#define E1K_TCP_URG UINT16_C(0x20)
958#define E1K_TCP_ECE UINT16_C(0x40)
959#define E1K_TCP_CWR UINT16_C(0x80)
960#define E1K_TCP_FLAGS UINT16_C(0x3f)
961
962/** @todo use+extend RTNETTCP */
963struct E1kTcpHeader
964{
965 uint16_t src;
966 uint16_t dest;
967 uint32_t seqno;
968 uint32_t ackno;
969 uint16_t hdrlen_flags;
970 uint16_t wnd;
971 uint16_t chksum;
972 uint16_t urgp;
973};
974AssertCompileSize(struct E1kTcpHeader, 20);
975
976
977#ifdef E1K_WITH_TXD_CACHE
978/** The current Saved state version. */
979# define E1K_SAVEDSTATE_VERSION 4
980/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
981# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
982#else /* !E1K_WITH_TXD_CACHE */
983/** The current Saved state version. */
984# define E1K_SAVEDSTATE_VERSION 3
985#endif /* !E1K_WITH_TXD_CACHE */
986/** Saved state version for VirtualBox 4.1 and earlier.
987 * These did not include VLAN tag fields. */
988#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
989/** Saved state version for VirtualBox 3.0 and earlier.
990 * This did not include the configuration part nor the E1kEEPROM. */
991#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
992
993/**
994 * Device state structure.
995 *
996 * Holds the current state of device.
997 *
998 * @implements PDMINETWORKDOWN
999 * @implements PDMINETWORKCONFIG
1000 * @implements PDMILEDPORTS
1001 */
1002struct E1kState_st
1003{
1004 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1005 PDMIBASE IBase;
1006 PDMINETWORKDOWN INetworkDown;
1007 PDMINETWORKCONFIG INetworkConfig;
1008 PDMILEDPORTS ILeds; /**< LED interface */
1009 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
1010 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1011
1012 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
1013 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
1014 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
1015 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
1016 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
1017 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
1018 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
1019 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
1020 PTMTIMERR3 pTXDTimerR3; /**< Transmit Delay Timer - R3. */
1021 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
1022 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
1023 /** The scatter / gather buffer used for the current outgoing packet - R3. */
1024 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1025
1026 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
1027 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
1028 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
1029 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
1030 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
1031 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
1032 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
1033 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
1034 PTMTIMERR0 pTXDTimerR0; /**< Transmit Delay Timer - R0. */
1035 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
1036 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
1037 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1038 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1039
1040 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
1041 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
1042 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
1043 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
1044 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
1045 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
1046 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
1047 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
1048 PTMTIMERRC pTXDTimerRC; /**< Transmit Delay Timer - RC. */
1049 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
1050 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
1051 /** The scatter / gather buffer used for the current outgoing packet - RC. */
1052 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1053 RTRCPTR RCPtrAlignment;
1054
1055#if HC_ARCH_BITS != 32
1056 uint32_t Alignment1;
1057#endif
1058 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
1059 PDMCRITSECT csRx; /**< RX Critical section. */
1060#ifdef E1K_WITH_TX_CS
1061 PDMCRITSECT csTx; /**< TX Critical section. */
1062#endif /* E1K_WITH_TX_CS */
1063 /** Base address of memory-mapped registers. */
1064 RTGCPHYS addrMMReg;
1065 /** MAC address obtained from the configuration. */
1066 RTMAC macConfigured;
1067 /** Base port of I/O space region. */
1068 RTIOPORT IOPortBase;
1069 /** EMT: */
1070 PCIDEVICE pciDevice;
1071 /** EMT: Last time the interrupt was acknowledged. */
1072 uint64_t u64AckedAt;
1073 /** All: Used for eliminating spurious interrupts. */
1074 bool fIntRaised;
1075 /** EMT: false if the cable is disconnected by the GUI. */
1076 bool fCableConnected;
1077 /** EMT: */
1078 bool fR0Enabled;
1079 /** EMT: */
1080 bool fRCEnabled;
1081 /** EMT: Compute Ethernet CRC for RX packets. */
1082 bool fEthernetCRC;
1083 /** All: throttle interrupts. */
1084 bool fItrEnabled;
1085 /** All: throttle RX interrupts. */
1086 bool fItrRxEnabled;
1087
1088 bool Alignment2;
1089 /** Link up delay (in milliseconds). */
1090 uint32_t cMsLinkUpDelay;
1091
1092 /** All: Device register storage. */
1093 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1094 /** TX/RX: Status LED. */
1095 PDMLED led;
1096 /** TX/RX: Number of packet being sent/received to show in debug log. */
1097 uint32_t u32PktNo;
1098
1099 /** EMT: Offset of the register to be read via IO. */
1100 uint32_t uSelectedReg;
1101 /** EMT: Multicast Table Array. */
1102 uint32_t auMTA[128];
1103 /** EMT: Receive Address registers. */
1104 E1KRA aRecAddr;
1105 /** EMT: VLAN filter table array. */
1106 uint32_t auVFTA[128];
1107 /** EMT: Receive buffer size. */
1108 uint16_t u16RxBSize;
1109 /** EMT: Locked state -- no state alteration possible. */
1110 bool fLocked;
1111 /** EMT: */
1112 bool fDelayInts;
1113 /** All: */
1114 bool fIntMaskUsed;
1115
1116 /** N/A: */
1117 bool volatile fMaybeOutOfSpace;
1118 /** EMT: Gets signalled when more RX descriptors become available. */
1119 RTSEMEVENT hEventMoreRxDescAvail;
1120#ifdef E1K_WITH_RXD_CACHE
1121 /** RX: Fetched RX descriptors. */
1122 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1123 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1124 /** RX: Actual number of fetched RX descriptors. */
1125 uint32_t nRxDFetched;
1126 /** RX: Index in cache of RX descriptor being processed. */
1127 uint32_t iRxDCurrent;
1128#endif /* E1K_WITH_RXD_CACHE */
1129
1130 /** TX: Context used for TCP segmentation packets. */
1131 E1KTXCTX contextTSE;
1132 /** TX: Context used for ordinary packets. */
1133 E1KTXCTX contextNormal;
1134#ifdef E1K_WITH_TXD_CACHE
1135 /** TX: Fetched TX descriptors. */
1136 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1137 /** TX: Actual number of fetched TX descriptors. */
1138 uint8_t nTxDFetched;
1139 /** TX: Index in cache of TX descriptor being processed. */
1140 uint8_t iTxDCurrent;
1141 /** TX: Will this frame be sent as GSO. */
1142 bool fGSO;
1143 /** Alignment padding. */
1144 bool fReserved;
1145 /** TX: Number of bytes in next packet. */
1146 uint32_t cbTxAlloc;
1147
1148#endif /* E1K_WITH_TXD_CACHE */
1149 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1150 * applicable to the current TSE mode. */
1151 PDMNETWORKGSO GsoCtx;
1152 /** Scratch space for holding the loopback / fallback scatter / gather
1153 * descriptor. */
1154 union
1155 {
1156 PDMSCATTERGATHER Sg;
1157 uint8_t padding[8 * sizeof(RTUINTPTR)];
1158 } uTxFallback;
1159 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1160 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1161 /** TX: Number of bytes assembled in TX packet buffer. */
1162 uint16_t u16TxPktLen;
1163 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1164 bool fGSOEnabled;
1165 /** TX: IP checksum has to be inserted if true. */
1166 bool fIPcsum;
1167 /** TX: TCP/UDP checksum has to be inserted if true. */
1168 bool fTCPcsum;
1169 /** TX: VLAN tag has to be inserted if true. */
1170 bool fVTag;
1171 /** TX: TCI part of VLAN tag to be inserted. */
1172 uint16_t u16VTagTCI;
1173 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1174 uint32_t u32PayRemain;
1175 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1176 uint16_t u16HdrRemain;
1177 /** TX TSE fallback: Flags from template header. */
1178 uint16_t u16SavedFlags;
1179 /** TX TSE fallback: Partial checksum from template header. */
1180 uint32_t u32SavedCsum;
1181 /** ?: Emulated controller type. */
1182 E1KCHIP eChip;
1183
1184 /** EMT: EEPROM emulation */
1185 E1kEEPROM eeprom;
1186 /** EMT: Physical interface emulation. */
1187 PHY phy;
1188
1189#if 0
1190 /** Alignment padding. */
1191 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1192#endif
1193
1194 STAMCOUNTER StatReceiveBytes;
1195 STAMCOUNTER StatTransmitBytes;
1196#if defined(VBOX_WITH_STATISTICS)
1197 STAMPROFILEADV StatMMIOReadRZ;
1198 STAMPROFILEADV StatMMIOReadR3;
1199 STAMPROFILEADV StatMMIOWriteRZ;
1200 STAMPROFILEADV StatMMIOWriteR3;
1201 STAMPROFILEADV StatEEPROMRead;
1202 STAMPROFILEADV StatEEPROMWrite;
1203 STAMPROFILEADV StatIOReadRZ;
1204 STAMPROFILEADV StatIOReadR3;
1205 STAMPROFILEADV StatIOWriteRZ;
1206 STAMPROFILEADV StatIOWriteR3;
1207 STAMPROFILEADV StatLateIntTimer;
1208 STAMCOUNTER StatLateInts;
1209 STAMCOUNTER StatIntsRaised;
1210 STAMCOUNTER StatIntsPrevented;
1211 STAMPROFILEADV StatReceive;
1212 STAMPROFILEADV StatReceiveCRC;
1213 STAMPROFILEADV StatReceiveFilter;
1214 STAMPROFILEADV StatReceiveStore;
1215 STAMPROFILEADV StatTransmitRZ;
1216 STAMPROFILEADV StatTransmitR3;
1217 STAMPROFILE StatTransmitSendRZ;
1218 STAMPROFILE StatTransmitSendR3;
1219 STAMPROFILE StatRxOverflow;
1220 STAMCOUNTER StatRxOverflowWakeup;
1221 STAMCOUNTER StatTxDescCtxNormal;
1222 STAMCOUNTER StatTxDescCtxTSE;
1223 STAMCOUNTER StatTxDescLegacy;
1224 STAMCOUNTER StatTxDescData;
1225 STAMCOUNTER StatTxDescTSEData;
1226 STAMCOUNTER StatTxPathFallback;
1227 STAMCOUNTER StatTxPathGSO;
1228 STAMCOUNTER StatTxPathRegular;
1229 STAMCOUNTER StatPHYAccesses;
1230 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1231 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1232#endif /* VBOX_WITH_STATISTICS */
1233
1234#ifdef E1K_INT_STATS
1235 /* Internal stats */
1236 uint64_t u64ArmedAt;
1237 uint64_t uStatMaxTxDelay;
1238 uint32_t uStatInt;
1239 uint32_t uStatIntTry;
1240 uint32_t uStatIntLower;
1241 uint32_t uStatIntDly;
1242 int32_t iStatIntLost;
1243 int32_t iStatIntLostOne;
1244 uint32_t uStatDisDly;
1245 uint32_t uStatIntSkip;
1246 uint32_t uStatIntLate;
1247 uint32_t uStatIntMasked;
1248 uint32_t uStatIntEarly;
1249 uint32_t uStatIntRx;
1250 uint32_t uStatIntTx;
1251 uint32_t uStatIntICS;
1252 uint32_t uStatIntRDTR;
1253 uint32_t uStatIntRXDMT0;
1254 uint32_t uStatIntTXQE;
1255 uint32_t uStatTxNoRS;
1256 uint32_t uStatTxIDE;
1257 uint32_t uStatTxDelayed;
1258 uint32_t uStatTxDelayExp;
1259 uint32_t uStatTAD;
1260 uint32_t uStatTID;
1261 uint32_t uStatRAD;
1262 uint32_t uStatRID;
1263 uint32_t uStatRxFrm;
1264 uint32_t uStatTxFrm;
1265 uint32_t uStatDescCtx;
1266 uint32_t uStatDescDat;
1267 uint32_t uStatDescLeg;
1268 uint32_t uStatTx1514;
1269 uint32_t uStatTx2962;
1270 uint32_t uStatTx4410;
1271 uint32_t uStatTx5858;
1272 uint32_t uStatTx7306;
1273 uint32_t uStatTx8754;
1274 uint32_t uStatTx16384;
1275 uint32_t uStatTx32768;
1276 uint32_t uStatTxLarge;
1277 uint32_t uStatAlign;
1278#endif /* E1K_INT_STATS */
1279};
1280typedef struct E1kState_st E1KSTATE;
1281/** Pointer to the E1000 device state. */
1282typedef E1KSTATE *PE1KSTATE;
1283
1284#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1285
1286/* Forward declarations ******************************************************/
1287static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread);
1288
1289static int e1kRegReadUnimplemented (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1290static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1291static int e1kRegReadAutoClear (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1292static int e1kRegReadDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1293static int e1kRegWriteDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1294#if 0 /* unused */
1295static int e1kRegReadCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1296#endif
1297static int e1kRegWriteCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1298static int e1kRegReadEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1299static int e1kRegWriteEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1300static int e1kRegWriteEERD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1301static int e1kRegWriteMDIC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1302static int e1kRegReadICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1303static int e1kRegWriteICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1304static int e1kRegWriteICS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1305static int e1kRegWriteIMS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1306static int e1kRegWriteIMC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1307static int e1kRegWriteRCTL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1308static int e1kRegWritePBA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1309static int e1kRegWriteRDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1310static int e1kRegWriteRDTR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1311static int e1kRegWriteTDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1312static int e1kRegReadMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1313static int e1kRegWriteMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1314static int e1kRegReadRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1315static int e1kRegWriteRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1316static int e1kRegReadVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1317static int e1kRegWriteVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1318
1319/**
1320 * Register map table.
1321 *
1322 * Override pfnRead and pfnWrite to get register-specific behavior.
1323 */
1324static const struct E1kRegMap_st
1325{
1326 /** Register offset in the register space. */
1327 uint32_t offset;
1328 /** Size in bytes. Registers of size > 4 are in fact tables. */
1329 uint32_t size;
1330 /** Readable bits. */
1331 uint32_t readable;
1332 /** Writable bits. */
1333 uint32_t writable;
1334 /** Read callback. */
1335 int (*pfnRead)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1336 /** Write callback. */
1337 int (*pfnWrite)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1338 /** Abbreviated name. */
1339 const char *abbrev;
1340 /** Full name. */
1341 const char *name;
1342} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1343{
1344 /* offset size read mask write mask read callback write callback abbrev full name */
1345 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1346 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1347 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1348 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1349 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1350 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1351 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1352 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1353 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1354 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1355 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1356 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1357 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1358 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1359 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1360 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1361 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1362 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1363 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1364 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1365 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1366 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1367 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1368 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1369 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1370 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1371 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1372 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1373 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1374 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1375 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1376 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1377 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1378 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1379 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1380 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1381 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1382 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1383 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1384 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1385 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1386 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1387 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1388 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1389 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1390 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1391 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1392 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1393 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1394 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1395 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1396 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1397 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1398 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1399 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1400 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1401 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1402 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1403 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1404 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1405 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1406 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1407 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1408 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1409 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1410 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1411 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1412 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1413 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1414 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1415 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1416 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1417 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1418 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1419 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1420 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1421 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1422 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1423 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1424 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1425 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1426 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1427 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1428 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1429 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1430 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1431 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1432 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1433 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1434 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1435 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1436 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1437 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1438 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1439 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1440 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1441 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1442 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1443 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1444 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1445 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1446 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1447 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1448 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1449 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1450 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1451 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1452 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1453 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1454 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1455 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1456 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1457 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1458 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1459 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1460 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1461 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1462 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1463 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1464 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1465 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1466 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1467 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1468 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1469 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1470 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1471 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1472 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1473 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1474 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1475 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1476 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1477 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1478 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1479 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1480};
1481
1482#ifdef LOG_ENABLED
1483
1484/**
1485 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1486 *
1487 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1488 *
1489 * @returns The buffer.
1490 *
1491 * @param u32 The word to convert into string.
1492 * @param mask Selects which bytes to convert.
1493 * @param buf Where to put the result.
1494 */
1495static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1496{
1497 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1498 {
1499 if (mask & 0xF)
1500 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1501 else
1502 *ptr = '.';
1503 }
1504 buf[8] = 0;
1505 return buf;
1506}
1507
1508/**
1509 * Returns timer name for debug purposes.
1510 *
1511 * @returns The timer name.
1512 *
1513 * @param pThis The device state structure.
1514 * @param pTimer The timer to get the name for.
1515 */
1516DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, PTMTIMER pTimer)
1517{
1518 if (pTimer == pThis->CTX_SUFF(pTIDTimer))
1519 return "TID";
1520 if (pTimer == pThis->CTX_SUFF(pTADTimer))
1521 return "TAD";
1522 if (pTimer == pThis->CTX_SUFF(pRIDTimer))
1523 return "RID";
1524 if (pTimer == pThis->CTX_SUFF(pRADTimer))
1525 return "RAD";
1526 if (pTimer == pThis->CTX_SUFF(pIntTimer))
1527 return "Int";
1528 if (pTimer == pThis->CTX_SUFF(pTXDTimer))
1529 return "TXD";
1530 if (pTimer == pThis->CTX_SUFF(pLUTimer))
1531 return "LinkUp";
1532 return "unknown";
1533}
1534
1535#endif /* DEBUG */
1536
1537/**
1538 * Arm a timer.
1539 *
1540 * @param pThis Pointer to the device state structure.
1541 * @param pTimer Pointer to the timer.
1542 * @param uExpireIn Expiration interval in microseconds.
1543 */
1544DECLINLINE(void) e1kArmTimer(PE1KSTATE pThis, PTMTIMER pTimer, uint32_t uExpireIn)
1545{
1546 if (pThis->fLocked)
1547 return;
1548
1549 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1550 pThis->szPrf, e1kGetTimerName(pThis, pTimer), uExpireIn));
1551 TMTimerSetMicro(pTimer, uExpireIn);
1552}
1553
1554/**
1555 * Cancel a timer.
1556 *
1557 * @param pThis Pointer to the device state structure.
1558 * @param pTimer Pointer to the timer.
1559 */
1560DECLINLINE(void) e1kCancelTimer(PE1KSTATE pThis, PTMTIMER pTimer)
1561{
1562 E1kLog2(("%s Stopping %s timer...\n",
1563 pThis->szPrf, e1kGetTimerName(pThis, pTimer)));
1564 int rc = TMTimerStop(pTimer);
1565 if (RT_FAILURE(rc))
1566 {
1567 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1568 pThis->szPrf, rc));
1569 }
1570}
1571
1572#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1573#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1574
1575#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1576#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1577#define e1kCsRxIsOwner(ps) PDMCritSectIsOwner(&ps->csRx)
1578
1579#ifndef E1K_WITH_TX_CS
1580# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1581# define e1kCsTxLeave(ps) do { } while (0)
1582#else /* E1K_WITH_TX_CS */
1583# define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1584# define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1585#endif /* E1K_WITH_TX_CS */
1586
1587#ifdef IN_RING3
1588
1589/**
1590 * Wakeup the RX thread.
1591 */
1592static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1593{
1594 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
1595 if ( pThis->fMaybeOutOfSpace
1596 && pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1597 {
1598 STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1599 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1600 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
1601 }
1602}
1603
1604/**
1605 * Hardware reset. Revert all registers to initial values.
1606 *
1607 * @param pThis The device state structure.
1608 */
1609static void e1kHardReset(PE1KSTATE pThis)
1610{
1611 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1612 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1613 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1614#ifdef E1K_INIT_RA0
1615 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1616 sizeof(pThis->macConfigured.au8));
1617 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1618#endif /* E1K_INIT_RA0 */
1619 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1620 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1621 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1622 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1623 Assert(GET_BITS(RCTL, BSIZE) == 0);
1624 pThis->u16RxBSize = 2048;
1625
1626 /* Reset promiscuous mode */
1627 if (pThis->pDrvR3)
1628 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, false);
1629
1630#ifdef E1K_WITH_TXD_CACHE
1631 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1632 if (RT_LIKELY(rc == VINF_SUCCESS))
1633 {
1634 pThis->nTxDFetched = 0;
1635 pThis->iTxDCurrent = 0;
1636 pThis->fGSO = false;
1637 pThis->cbTxAlloc = 0;
1638 e1kCsTxLeave(pThis);
1639 }
1640#endif /* E1K_WITH_TXD_CACHE */
1641#ifdef E1K_WITH_RXD_CACHE
1642 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1643 {
1644 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1645 e1kCsRxLeave(pThis);
1646 }
1647#endif /* E1K_WITH_RXD_CACHE */
1648}
1649
1650#endif /* IN_RING3 */
1651
1652/**
1653 * Compute Internet checksum.
1654 *
1655 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1656 *
1657 * @param pThis The device state structure.
1658 * @param cpPacket The packet.
1659 * @param cb The size of the packet.
1660 * @param cszText A string denoting direction of packet transfer.
1661 *
1662 * @return The 1's complement of the 1's complement sum.
1663 *
1664 * @thread E1000_TX
1665 */
1666static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1667{
1668 uint32_t csum = 0;
1669 uint16_t *pu16 = (uint16_t *)pvBuf;
1670
1671 while (cb > 1)
1672 {
1673 csum += *pu16++;
1674 cb -= 2;
1675 }
1676 if (cb)
1677 csum += *(uint8_t*)pu16;
1678 while (csum >> 16)
1679 csum = (csum >> 16) + (csum & 0xFFFF);
1680 return ~csum;
1681}
1682
1683/**
1684 * Dump a packet to debug log.
1685 *
1686 * @param pThis The device state structure.
1687 * @param cpPacket The packet.
1688 * @param cb The size of the packet.
1689 * @param cszText A string denoting direction of packet transfer.
1690 * @thread E1000_TX
1691 */
1692DECLINLINE(void) e1kPacketDump(PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *cszText)
1693{
1694#ifdef DEBUG
1695 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1696 {
1697 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1698 pThis->szPrf, cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1699 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1700 {
1701 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1702 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1703 if (*(cpPacket+14+6) == 0x6)
1704 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1705 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1706 }
1707 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1708 {
1709 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1710 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1711 if (*(cpPacket+14+6) == 0x6)
1712 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1713 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1714 }
1715 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1716 e1kCsLeave(pThis);
1717 }
1718#else
1719 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1720 {
1721 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1722 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1723 cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1724 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1725 else
1726 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1727 cszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1728 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1729 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1730 e1kCsLeave(pThis);
1731 }
1732#endif
1733}
1734
1735/**
1736 * Determine the type of transmit descriptor.
1737 *
1738 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1739 *
1740 * @param pDesc Pointer to descriptor union.
1741 * @thread E1000_TX
1742 */
1743DECLINLINE(int) e1kGetDescType(E1KTXDESC* pDesc)
1744{
1745 if (pDesc->legacy.cmd.fDEXT)
1746 return pDesc->context.dw2.u4DTYP;
1747 return E1K_DTYP_LEGACY;
1748}
1749
1750/**
1751 * Dump receive descriptor to debug log.
1752 *
1753 * @param pThis The device state structure.
1754 * @param pDesc Pointer to the descriptor.
1755 * @thread E1000_RX
1756 */
1757static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC* pDesc)
1758{
1759 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1760 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1761 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1762 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1763 pDesc->status.fPIF ? "PIF" : "pif",
1764 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1765 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1766 pDesc->status.fVP ? "VP" : "vp",
1767 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1768 pDesc->status.fEOP ? "EOP" : "eop",
1769 pDesc->status.fDD ? "DD" : "dd",
1770 pDesc->status.fRXE ? "RXE" : "rxe",
1771 pDesc->status.fIPE ? "IPE" : "ipe",
1772 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1773 pDesc->status.fCE ? "CE" : "ce",
1774 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1775 E1K_SPEC_VLAN(pDesc->status.u16Special),
1776 E1K_SPEC_PRI(pDesc->status.u16Special)));
1777}
1778
1779/**
1780 * Dump transmit descriptor to debug log.
1781 *
1782 * @param pThis The device state structure.
1783 * @param pDesc Pointer to descriptor union.
1784 * @param cszDir A string denoting direction of descriptor transfer
1785 * @thread E1000_TX
1786 */
1787static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, const char* cszDir,
1788 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1789{
1790 /*
1791 * Unfortunately we cannot use our format handler here, we want R0 logging
1792 * as well.
1793 */
1794 switch (e1kGetDescType(pDesc))
1795 {
1796 case E1K_DTYP_CONTEXT:
1797 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
1798 pThis->szPrf, cszDir, cszDir));
1799 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1800 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1801 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1802 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1803 pDesc->context.dw2.fIDE ? " IDE":"",
1804 pDesc->context.dw2.fRS ? " RS" :"",
1805 pDesc->context.dw2.fTSE ? " TSE":"",
1806 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1807 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1808 pDesc->context.dw2.u20PAYLEN,
1809 pDesc->context.dw3.u8HDRLEN,
1810 pDesc->context.dw3.u16MSS,
1811 pDesc->context.dw3.fDD?"DD":""));
1812 break;
1813 case E1K_DTYP_DATA:
1814 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1815 pThis->szPrf, cszDir, pDesc->data.cmd.u20DTALEN, cszDir));
1816 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1817 pDesc->data.u64BufAddr,
1818 pDesc->data.cmd.u20DTALEN));
1819 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1820 pDesc->data.cmd.fIDE ? " IDE" :"",
1821 pDesc->data.cmd.fVLE ? " VLE" :"",
1822 pDesc->data.cmd.fRPS ? " RPS" :"",
1823 pDesc->data.cmd.fRS ? " RS" :"",
1824 pDesc->data.cmd.fTSE ? " TSE" :"",
1825 pDesc->data.cmd.fIFCS? " IFCS":"",
1826 pDesc->data.cmd.fEOP ? " EOP" :"",
1827 pDesc->data.dw3.fDD ? " DD" :"",
1828 pDesc->data.dw3.fEC ? " EC" :"",
1829 pDesc->data.dw3.fLC ? " LC" :"",
1830 pDesc->data.dw3.fTXSM? " TXSM":"",
1831 pDesc->data.dw3.fIXSM? " IXSM":"",
1832 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
1833 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
1834 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
1835 break;
1836 case E1K_DTYP_LEGACY:
1837 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1838 pThis->szPrf, cszDir, pDesc->legacy.cmd.u16Length, cszDir));
1839 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1840 pDesc->data.u64BufAddr,
1841 pDesc->legacy.cmd.u16Length));
1842 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1843 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1844 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1845 pDesc->legacy.cmd.fRPS ? " RPS" :"",
1846 pDesc->legacy.cmd.fRS ? " RS" :"",
1847 pDesc->legacy.cmd.fIC ? " IC" :"",
1848 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1849 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1850 pDesc->legacy.dw3.fDD ? " DD" :"",
1851 pDesc->legacy.dw3.fEC ? " EC" :"",
1852 pDesc->legacy.dw3.fLC ? " LC" :"",
1853 pDesc->legacy.cmd.u8CSO,
1854 pDesc->legacy.dw3.u8CSS,
1855 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
1856 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
1857 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
1858 break;
1859 default:
1860 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1861 pThis->szPrf, cszDir, cszDir));
1862 break;
1863 }
1864}
1865
1866/**
1867 * Raise an interrupt later.
1868 *
1869 * @param pThis The device state structure.
1870 */
1871inline void e1kPostponeInterrupt(PE1KSTATE pThis, uint64_t uNanoseconds)
1872{
1873 if (!TMTimerIsActive(pThis->CTX_SUFF(pIntTimer)))
1874 TMTimerSetNano(pThis->CTX_SUFF(pIntTimer), uNanoseconds);
1875}
1876
1877/**
1878 * Raise interrupt if not masked.
1879 *
1880 * @param pThis The device state structure.
1881 */
1882static int e1kRaiseInterrupt(PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
1883{
1884 int rc = e1kCsEnter(pThis, rcBusy);
1885 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1886 return rc;
1887
1888 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
1889 ICR |= u32IntCause;
1890 if (ICR & IMS)
1891 {
1892 if (pThis->fIntRaised)
1893 {
1894 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
1895 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1896 pThis->szPrf, ICR & IMS));
1897 }
1898 else
1899 {
1900 uint64_t tsNow = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
1901 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
1902 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
1903 {
1904 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
1905 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1906 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
1907 e1kPostponeInterrupt(pThis, ITR * 256);
1908 }
1909 else
1910 {
1911
1912 /* Since we are delivering the interrupt now
1913 * there is no need to do it later -- stop the timer.
1914 */
1915 TMTimerStop(pThis->CTX_SUFF(pIntTimer));
1916 E1K_INC_ISTAT_CNT(pThis->uStatInt);
1917 STAM_COUNTER_INC(&pThis->StatIntsRaised);
1918 /* Got at least one unmasked interrupt cause */
1919 pThis->fIntRaised = true;
1920 /* Raise(1) INTA(0) */
1921 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1922 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
1923 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1924 pThis->szPrf, ICR & IMS));
1925 }
1926 }
1927 }
1928 else
1929 {
1930 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
1931 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1932 pThis->szPrf, ICR, IMS));
1933 }
1934 e1kCsLeave(pThis);
1935 return VINF_SUCCESS;
1936}
1937
1938/**
1939 * Compute the physical address of the descriptor.
1940 *
1941 * @returns the physical address of the descriptor.
1942 *
1943 * @param baseHigh High-order 32 bits of descriptor table address.
1944 * @param baseLow Low-order 32 bits of descriptor table address.
1945 * @param idxDesc The descriptor index in the table.
1946 */
1947DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1948{
1949 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1950 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1951}
1952
1953/**
1954 * Advance the head pointer of the receive descriptor queue.
1955 *
1956 * @remarks RDH always points to the next available RX descriptor.
1957 *
1958 * @param pThis The device state structure.
1959 */
1960DECLINLINE(void) e1kAdvanceRDH(PE1KSTATE pThis)
1961{
1962 Assert(e1kCsRxIsOwner(pThis));
1963 //e1kCsEnter(pThis, RT_SRC_POS);
1964 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1965 RDH = 0;
1966 /*
1967 * Compute current receive queue length and fire RXDMT0 interrupt
1968 * if we are low on receive buffers
1969 */
1970 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
1971 /*
1972 * The minimum threshold is controlled by RDMTS bits of RCTL:
1973 * 00 = 1/2 of RDLEN
1974 * 01 = 1/4 of RDLEN
1975 * 10 = 1/8 of RDLEN
1976 * 11 = reserved
1977 */
1978 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
1979 if (uRQueueLen <= uMinRQThreshold)
1980 {
1981 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
1982 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
1983 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
1984 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
1985 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXDMT0);
1986 }
1987 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
1988 pThis->szPrf, RDH, RDT, uRQueueLen));
1989 //e1kCsLeave(pThis);
1990}
1991
1992#ifdef E1K_WITH_RXD_CACHE
1993/**
1994 * Return the number of RX descriptor that belong to the hardware.
1995 *
1996 * @returns the number of available descriptors in RX ring.
1997 * @param pThis The device state structure.
1998 * @thread ???
1999 */
2000DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
2001{
2002 /**
2003 * Make sure RDT won't change during computation. EMT may modify RDT at
2004 * any moment.
2005 */
2006 uint32_t rdt = RDT;
2007 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
2008}
2009
2010DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
2011{
2012 return pThis->nRxDFetched > pThis->iRxDCurrent ?
2013 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
2014}
2015
2016DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
2017{
2018 return pThis->iRxDCurrent >= pThis->nRxDFetched;
2019}
2020
2021/**
2022 * Load receive descriptors from guest memory. The caller needs to be in Rx
2023 * critical section.
2024 *
2025 * We need two physical reads in case the tail wrapped around the end of RX
2026 * descriptor ring.
2027 *
2028 * @returns the actual number of descriptors fetched.
2029 * @param pThis The device state structure.
2030 * @param pDesc Pointer to descriptor union.
2031 * @param addr Physical address in guest context.
2032 * @thread EMT, RX
2033 */
2034DECLINLINE(unsigned) e1kRxDPrefetch(PE1KSTATE pThis)
2035{
2036 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
2037 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
2038 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
2039 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
2040 Assert(nDescsTotal != 0);
2041 if (nDescsTotal == 0)
2042 return 0;
2043 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
2044 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2045 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2046 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2047 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2048 nFirstNotLoaded, nDescsInSingleRead));
2049 if (nDescsToFetch == 0)
2050 return 0;
2051 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2052 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2053 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2054 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2055 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2056 // unsigned i, j;
2057 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2058 // {
2059 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2060 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2061 // }
2062 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2063 pThis->szPrf, nDescsInSingleRead,
2064 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
2065 nFirstNotLoaded, RDLEN, RDH, RDT));
2066 if (nDescsToFetch > nDescsInSingleRead)
2067 {
2068 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2069 ((uint64_t)RDBAH << 32) + RDBAL,
2070 pFirstEmptyDesc + nDescsInSingleRead,
2071 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2072 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2073 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2074 // {
2075 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2076 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2077 // }
2078 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2079 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2080 RDBAH, RDBAL));
2081 }
2082 pThis->nRxDFetched += nDescsToFetch;
2083 return nDescsToFetch;
2084}
2085
2086/**
2087 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2088 * RX ring if the cache is empty.
2089 *
2090 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2091 * go out of sync with RDH which will cause trouble when EMT checks if the
2092 * cache is empty to do pre-fetch @bugref(6217).
2093 *
2094 * @param pThis The device state structure.
2095 * @thread RX
2096 */
2097DECLINLINE(E1KRXDESC*) e1kRxDGet(PE1KSTATE pThis)
2098{
2099 Assert(e1kCsRxIsOwner(pThis));
2100 /* Check the cache first. */
2101 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2102 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2103 /* Cache is empty, reset it and check if we can fetch more. */
2104 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2105 if (e1kRxDPrefetch(pThis))
2106 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2107 /* Out of Rx descriptors. */
2108 return NULL;
2109}
2110
2111/**
2112 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2113 * pointer. The descriptor gets written back to the RXD ring.
2114 *
2115 * @param pThis The device state structure.
2116 * @param pDesc The descriptor being "returned" to the RX ring.
2117 * @thread RX
2118 */
2119DECLINLINE(void) e1kRxDPut(PE1KSTATE pThis, E1KRXDESC* pDesc)
2120{
2121 Assert(e1kCsRxIsOwner(pThis));
2122 pThis->iRxDCurrent++;
2123 // Assert(pDesc >= pThis->aRxDescriptors);
2124 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2125 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2126 // uint32_t rdh = RDH;
2127 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2128 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2129 e1kDescAddr(RDBAH, RDBAL, RDH),
2130 pDesc, sizeof(E1KRXDESC));
2131 e1kAdvanceRDH(pThis);
2132 e1kPrintRDesc(pThis, pDesc);
2133}
2134
2135/**
2136 * Store a fragment of received packet at the specifed address.
2137 *
2138 * @param pThis The device state structure.
2139 * @param pDesc The next available RX descriptor.
2140 * @param pvBuf The fragment.
2141 * @param cb The size of the fragment.
2142 */
2143static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2144{
2145 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2146 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2147 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2148 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2149 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2150 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2151}
2152
2153#else /* !E1K_WITH_RXD_CACHE */
2154
2155/**
2156 * Store a fragment of received packet that fits into the next available RX
2157 * buffer.
2158 *
2159 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2160 *
2161 * @param pThis The device state structure.
2162 * @param pDesc The next available RX descriptor.
2163 * @param pvBuf The fragment.
2164 * @param cb The size of the fragment.
2165 */
2166static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2167{
2168 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2169 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2170 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2171 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2172 /* Write back the descriptor */
2173 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2174 e1kPrintRDesc(pThis, pDesc);
2175 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2176 /* Advance head */
2177 e1kAdvanceRDH(pThis);
2178 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2179 if (pDesc->status.fEOP)
2180 {
2181 /* Complete packet has been stored -- it is time to let the guest know. */
2182#ifdef E1K_USE_RX_TIMERS
2183 if (RDTR)
2184 {
2185 /* Arm the timer to fire in RDTR usec (discard .024) */
2186 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2187 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2188 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2189 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2190 }
2191 else
2192 {
2193#endif
2194 /* 0 delay means immediate interrupt */
2195 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2196 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2197#ifdef E1K_USE_RX_TIMERS
2198 }
2199#endif
2200 }
2201 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2202}
2203#endif /* !E1K_WITH_RXD_CACHE */
2204
2205/**
2206 * Returns true if it is a broadcast packet.
2207 *
2208 * @returns true if destination address indicates broadcast.
2209 * @param pvBuf The ethernet packet.
2210 */
2211DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2212{
2213 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2214 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2215}
2216
2217/**
2218 * Returns true if it is a multicast packet.
2219 *
2220 * @remarks returns true for broadcast packets as well.
2221 * @returns true if destination address indicates multicast.
2222 * @param pvBuf The ethernet packet.
2223 */
2224DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2225{
2226 return (*(char*)pvBuf) & 1;
2227}
2228
2229/**
2230 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2231 *
2232 * @remarks We emulate checksum offloading for major packets types only.
2233 *
2234 * @returns VBox status code.
2235 * @param pThis The device state structure.
2236 * @param pFrame The available data.
2237 * @param cb Number of bytes available in the buffer.
2238 * @param status Bit fields containing status info.
2239 */
2240static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2241{
2242 /** @todo
2243 * It is not safe to bypass checksum verification for packets coming
2244 * from real wire. We currently unable to tell where packets are
2245 * coming from so we tell the driver to ignore our checksum flags
2246 * and do verification in software.
2247 */
2248#if 0
2249 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2250
2251 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2252
2253 switch (uEtherType)
2254 {
2255 case 0x800: /* IPv4 */
2256 {
2257 pStatus->fIXSM = false;
2258 pStatus->fIPCS = true;
2259 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2260 /* TCP/UDP checksum offloading works with TCP and UDP only */
2261 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2262 break;
2263 }
2264 case 0x86DD: /* IPv6 */
2265 pStatus->fIXSM = false;
2266 pStatus->fIPCS = false;
2267 pStatus->fTCPCS = true;
2268 break;
2269 default: /* ARP, VLAN, etc. */
2270 pStatus->fIXSM = true;
2271 break;
2272 }
2273#else
2274 pStatus->fIXSM = true;
2275#endif
2276 return VINF_SUCCESS;
2277}
2278
2279/**
2280 * Pad and store received packet.
2281 *
2282 * @remarks Make sure that the packet appears to upper layer as one coming
2283 * from real Ethernet: pad it and insert FCS.
2284 *
2285 * @returns VBox status code.
2286 * @param pThis The device state structure.
2287 * @param pvBuf The available data.
2288 * @param cb Number of bytes available in the buffer.
2289 * @param status Bit fields containing status info.
2290 */
2291static int e1kHandleRxPacket(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2292{
2293#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2294 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2295 uint8_t *ptr = rxPacket;
2296
2297 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2298 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2299 return rc;
2300
2301 if (cb > 70) /* unqualified guess */
2302 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2303
2304 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2305 Assert(cb > 16);
2306 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2307 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2308 if (status.fVP)
2309 {
2310 /* VLAN packet -- strip VLAN tag in VLAN mode */
2311 if ((CTRL & CTRL_VME) && cb > 16)
2312 {
2313 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2314 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2315 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2316 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2317 cb -= 4;
2318 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2319 pThis->szPrf, status.u16Special, cb));
2320 }
2321 else
2322 status.fVP = false; /* Set VP only if we stripped the tag */
2323 }
2324 else
2325 memcpy(rxPacket, pvBuf, cb);
2326 /* Pad short packets */
2327 if (cb < 60)
2328 {
2329 memset(rxPacket + cb, 0, 60 - cb);
2330 cb = 60;
2331 }
2332 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2333 {
2334 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2335 /*
2336 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2337 * is ignored by most of drivers we may as well save us the trouble
2338 * of calculating it (see EthernetCRC CFGM parameter).
2339 */
2340 if (pThis->fEthernetCRC)
2341 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2342 cb += sizeof(uint32_t);
2343 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2344 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2345 }
2346 /* Compute checksum of complete packet */
2347 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2348 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2349
2350 /* Update stats */
2351 E1K_INC_CNT32(GPRC);
2352 if (e1kIsBroadcast(pvBuf))
2353 E1K_INC_CNT32(BPRC);
2354 else if (e1kIsMulticast(pvBuf))
2355 E1K_INC_CNT32(MPRC);
2356 /* Update octet receive counter */
2357 E1K_ADD_CNT64(GORCL, GORCH, cb);
2358 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2359 if (cb == 64)
2360 E1K_INC_CNT32(PRC64);
2361 else if (cb < 128)
2362 E1K_INC_CNT32(PRC127);
2363 else if (cb < 256)
2364 E1K_INC_CNT32(PRC255);
2365 else if (cb < 512)
2366 E1K_INC_CNT32(PRC511);
2367 else if (cb < 1024)
2368 E1K_INC_CNT32(PRC1023);
2369 else
2370 E1K_INC_CNT32(PRC1522);
2371
2372 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2373
2374#ifdef E1K_WITH_RXD_CACHE
2375 while (cb > 0)
2376 {
2377 E1KRXDESC *pDesc = e1kRxDGet(pThis);
2378
2379 if (pDesc == NULL)
2380 {
2381 E1kLog(("%s Out of receive buffers, dropping the packet "
2382 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2383 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2384 break;
2385 }
2386#else /* !E1K_WITH_RXD_CACHE */
2387 if (RDH == RDT)
2388 {
2389 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2390 pThis->szPrf));
2391 }
2392 /* Store the packet to receive buffers */
2393 while (RDH != RDT)
2394 {
2395 /* Load the descriptor pointed by head */
2396 E1KRXDESC desc, *pDesc = &desc;
2397 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2398 &desc, sizeof(desc));
2399#endif /* !E1K_WITH_RXD_CACHE */
2400 if (pDesc->u64BufAddr)
2401 {
2402 /* Update descriptor */
2403 pDesc->status = status;
2404 pDesc->u16Checksum = checksum;
2405 pDesc->status.fDD = true;
2406
2407 /*
2408 * We need to leave Rx critical section here or we risk deadlocking
2409 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2410 * page or has an access handler associated with it.
2411 * Note that it is safe to leave the critical section here since
2412 * e1kRegWriteRDT() never modifies RDH. It never touches already
2413 * fetched RxD cache entries either.
2414 */
2415 if (cb > pThis->u16RxBSize)
2416 {
2417 pDesc->status.fEOP = false;
2418 e1kCsRxLeave(pThis);
2419 e1kStoreRxFragment(pThis, pDesc, ptr, pThis->u16RxBSize);
2420 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2421 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2422 return rc;
2423 ptr += pThis->u16RxBSize;
2424 cb -= pThis->u16RxBSize;
2425 }
2426 else
2427 {
2428 pDesc->status.fEOP = true;
2429 e1kCsRxLeave(pThis);
2430 e1kStoreRxFragment(pThis, pDesc, ptr, cb);
2431#ifdef E1K_WITH_RXD_CACHE
2432 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2433 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2434 return rc;
2435 cb = 0;
2436#else /* !E1K_WITH_RXD_CACHE */
2437 pThis->led.Actual.s.fReading = 0;
2438 return VINF_SUCCESS;
2439#endif /* !E1K_WITH_RXD_CACHE */
2440 }
2441 /*
2442 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2443 * is not defined.
2444 */
2445 }
2446#ifdef E1K_WITH_RXD_CACHE
2447 /* Write back the descriptor. */
2448 pDesc->status.fDD = true;
2449 e1kRxDPut(pThis, pDesc);
2450#else /* !E1K_WITH_RXD_CACHE */
2451 else
2452 {
2453 /* Write back the descriptor. */
2454 pDesc->status.fDD = true;
2455 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2456 e1kDescAddr(RDBAH, RDBAL, RDH),
2457 pDesc, sizeof(E1KRXDESC));
2458 e1kAdvanceRDH(pThis);
2459 }
2460#endif /* !E1K_WITH_RXD_CACHE */
2461 }
2462
2463 if (cb > 0)
2464 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2465
2466 pThis->led.Actual.s.fReading = 0;
2467
2468 e1kCsRxLeave(pThis);
2469#ifdef E1K_WITH_RXD_CACHE
2470 /* Complete packet has been stored -- it is time to let the guest know. */
2471# ifdef E1K_USE_RX_TIMERS
2472 if (RDTR)
2473 {
2474 /* Arm the timer to fire in RDTR usec (discard .024) */
2475 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2476 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2477 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2478 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2479 }
2480 else
2481 {
2482# endif /* E1K_USE_RX_TIMERS */
2483 /* 0 delay means immediate interrupt */
2484 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2485 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2486# ifdef E1K_USE_RX_TIMERS
2487 }
2488# endif /* E1K_USE_RX_TIMERS */
2489#endif /* E1K_WITH_RXD_CACHE */
2490
2491 return VINF_SUCCESS;
2492#else
2493 return VERR_INTERNAL_ERROR_2;
2494#endif
2495}
2496
2497
2498/**
2499 * Bring the link up after the configured delay, 5 seconds by default.
2500 *
2501 * @param pThis The device state structure.
2502 * @thread any
2503 */
2504DECLINLINE(void) e1kBringLinkUpDelayed(PE1KSTATE pThis)
2505{
2506 E1kLog(("%s Will bring up the link in %d seconds...\n",
2507 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2508 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
2509}
2510
2511#ifdef IN_RING3
2512/**
2513 * Bring up the link immediately.
2514 *
2515 * @param pThis The device state structure.
2516 */
2517DECLINLINE(void) e1kR3LinkUp(PE1KSTATE pThis)
2518{
2519 E1kLog(("%s Link is up\n", pThis->szPrf));
2520 STATUS |= STATUS_LU;
2521 Phy::setLinkStatus(&pThis->phy, true);
2522 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2523 if (pThis->pDrvR3)
2524 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_UP);
2525}
2526
2527/**
2528 * Bring down the link immediately.
2529 *
2530 * @param pThis The device state structure.
2531 */
2532DECLINLINE(void) e1kR3LinkDown(PE1KSTATE pThis)
2533{
2534 E1kLog(("%s Link is down\n", pThis->szPrf));
2535 STATUS &= ~STATUS_LU;
2536 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2537 if (pThis->pDrvR3)
2538 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2539}
2540
2541/**
2542 * Bring down the link temporarily.
2543 *
2544 * @param pThis The device state structure.
2545 */
2546DECLINLINE(void) e1kR3LinkDownTemp(PE1KSTATE pThis)
2547{
2548 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2549 STATUS &= ~STATUS_LU;
2550 Phy::setLinkStatus(&pThis->phy, false);
2551 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2552 /*
2553 * Notifying the associated driver that the link went down (even temporarily)
2554 * seems to be the right thing, but it was not done before. This may cause
2555 * a regression if the driver does not expect the link to go down as a result
2556 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2557 * of code notified the driver that the link was up! See @bugref{7057}.
2558 */
2559 if (pThis->pDrvR3)
2560 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2561 e1kBringLinkUpDelayed(pThis);
2562}
2563#endif /* IN_RING3 */
2564
2565#if 0 /* unused */
2566/**
2567 * Read handler for Device Status register.
2568 *
2569 * Get the link status from PHY.
2570 *
2571 * @returns VBox status code.
2572 *
2573 * @param pThis The device state structure.
2574 * @param offset Register offset in memory-mapped frame.
2575 * @param index Register index in register array.
2576 * @param mask Used to implement partial reads (8 and 16-bit).
2577 */
2578static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2579{
2580 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2581 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2582 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2583 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2584 {
2585 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2586 if (Phy::readMDIO(&pThis->phy))
2587 *pu32Value = CTRL | CTRL_MDIO;
2588 else
2589 *pu32Value = CTRL & ~CTRL_MDIO;
2590 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2591 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2592 }
2593 else
2594 {
2595 /* MDIO pin is used for output, ignore it */
2596 *pu32Value = CTRL;
2597 }
2598 return VINF_SUCCESS;
2599}
2600#endif /* unused */
2601
2602/**
2603 * Write handler for Device Control register.
2604 *
2605 * Handles reset.
2606 *
2607 * @param pThis The device state structure.
2608 * @param offset Register offset in memory-mapped frame.
2609 * @param index Register index in register array.
2610 * @param value The value to store.
2611 * @param mask Used to implement partial writes (8 and 16-bit).
2612 * @thread EMT
2613 */
2614static int e1kRegWriteCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2615{
2616 int rc = VINF_SUCCESS;
2617
2618 if (value & CTRL_RESET)
2619 { /* RST */
2620#ifndef IN_RING3
2621 return VINF_IOM_R3_MMIO_WRITE;
2622#else
2623 e1kHardReset(pThis);
2624#endif
2625 }
2626 else
2627 {
2628 if ( (value & CTRL_SLU)
2629 && pThis->fCableConnected
2630 && !(STATUS & STATUS_LU))
2631 {
2632 /* The driver indicates that we should bring up the link */
2633 /* Do so in 5 seconds (by default). */
2634 e1kBringLinkUpDelayed(pThis);
2635 /*
2636 * Change the status (but not PHY status) anyway as Windows expects
2637 * it for 82543GC.
2638 */
2639 STATUS |= STATUS_LU;
2640 }
2641 if (value & CTRL_VME)
2642 {
2643 E1kLog(("%s VLAN Mode Enabled\n", pThis->szPrf));
2644 }
2645 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2646 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2647 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2648 if (value & CTRL_MDC)
2649 {
2650 if (value & CTRL_MDIO_DIR)
2651 {
2652 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2653 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2654 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO));
2655 }
2656 else
2657 {
2658 if (Phy::readMDIO(&pThis->phy))
2659 value |= CTRL_MDIO;
2660 else
2661 value &= ~CTRL_MDIO;
2662 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2663 pThis->szPrf, !!(value & CTRL_MDIO)));
2664 }
2665 }
2666 rc = e1kRegWriteDefault(pThis, offset, index, value);
2667 }
2668
2669 return rc;
2670}
2671
2672/**
2673 * Write handler for EEPROM/Flash Control/Data register.
2674 *
2675 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2676 *
2677 * @param pThis The device state structure.
2678 * @param offset Register offset in memory-mapped frame.
2679 * @param index Register index in register array.
2680 * @param value The value to store.
2681 * @param mask Used to implement partial writes (8 and 16-bit).
2682 * @thread EMT
2683 */
2684static int e1kRegWriteEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2685{
2686#ifdef IN_RING3
2687 /* So far we are concerned with lower byte only */
2688 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2689 {
2690 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2691 /* Note: 82543GC does not need to request EEPROM access */
2692 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2693 pThis->eeprom.write(value & EECD_EE_WIRES);
2694 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2695 }
2696 if (value & EECD_EE_REQ)
2697 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2698 else
2699 EECD &= ~EECD_EE_GNT;
2700 //e1kRegWriteDefault(pThis, offset, index, value );
2701
2702 return VINF_SUCCESS;
2703#else /* !IN_RING3 */
2704 return VINF_IOM_R3_MMIO_WRITE;
2705#endif /* !IN_RING3 */
2706}
2707
2708/**
2709 * Read handler for EEPROM/Flash Control/Data register.
2710 *
2711 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2712 *
2713 * @returns VBox status code.
2714 *
2715 * @param pThis The device state structure.
2716 * @param offset Register offset in memory-mapped frame.
2717 * @param index Register index in register array.
2718 * @param mask Used to implement partial reads (8 and 16-bit).
2719 * @thread EMT
2720 */
2721static int e1kRegReadEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2722{
2723#ifdef IN_RING3
2724 uint32_t value;
2725 int rc = e1kRegReadDefault(pThis, offset, index, &value);
2726 if (RT_SUCCESS(rc))
2727 {
2728 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2729 {
2730 /* Note: 82543GC does not need to request EEPROM access */
2731 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2732 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2733 value |= pThis->eeprom.read();
2734 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2735 }
2736 *pu32Value = value;
2737 }
2738
2739 return rc;
2740#else /* !IN_RING3 */
2741 return VINF_IOM_R3_MMIO_READ;
2742#endif /* !IN_RING3 */
2743}
2744
2745/**
2746 * Write handler for EEPROM Read register.
2747 *
2748 * Handles EEPROM word access requests, reads EEPROM and stores the result
2749 * into DATA field.
2750 *
2751 * @param pThis The device state structure.
2752 * @param offset Register offset in memory-mapped frame.
2753 * @param index Register index in register array.
2754 * @param value The value to store.
2755 * @param mask Used to implement partial writes (8 and 16-bit).
2756 * @thread EMT
2757 */
2758static int e1kRegWriteEERD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2759{
2760#ifdef IN_RING3
2761 /* Make use of 'writable' and 'readable' masks. */
2762 e1kRegWriteDefault(pThis, offset, index, value);
2763 /* DONE and DATA are set only if read was triggered by START. */
2764 if (value & EERD_START)
2765 {
2766 uint16_t tmp;
2767 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2768 if (pThis->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2769 SET_BITS(EERD, DATA, tmp);
2770 EERD |= EERD_DONE;
2771 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2772 }
2773
2774 return VINF_SUCCESS;
2775#else /* !IN_RING3 */
2776 return VINF_IOM_R3_MMIO_WRITE;
2777#endif /* !IN_RING3 */
2778}
2779
2780
2781/**
2782 * Write handler for MDI Control register.
2783 *
2784 * Handles PHY read/write requests; forwards requests to internal PHY device.
2785 *
2786 * @param pThis The device state structure.
2787 * @param offset Register offset in memory-mapped frame.
2788 * @param index Register index in register array.
2789 * @param value The value to store.
2790 * @param mask Used to implement partial writes (8 and 16-bit).
2791 * @thread EMT
2792 */
2793static int e1kRegWriteMDIC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2794{
2795 if (value & MDIC_INT_EN)
2796 {
2797 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2798 pThis->szPrf));
2799 }
2800 else if (value & MDIC_READY)
2801 {
2802 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2803 pThis->szPrf));
2804 }
2805 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2806 {
2807 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
2808 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
2809 /*
2810 * Some drivers scan the MDIO bus for a PHY. We can work with these
2811 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
2812 * at the requested address, see @bugref{7346}.
2813 */
2814 MDIC = MDIC_READY | MDIC_ERROR;
2815 }
2816 else
2817 {
2818 /* Store the value */
2819 e1kRegWriteDefault(pThis, offset, index, value);
2820 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
2821 /* Forward op to PHY */
2822 if (value & MDIC_OP_READ)
2823 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG)));
2824 else
2825 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2826 /* Let software know that we are done */
2827 MDIC |= MDIC_READY;
2828 }
2829
2830 return VINF_SUCCESS;
2831}
2832
2833/**
2834 * Write handler for Interrupt Cause Read register.
2835 *
2836 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2837 *
2838 * @param pThis The device state structure.
2839 * @param offset Register offset in memory-mapped frame.
2840 * @param index Register index in register array.
2841 * @param value The value to store.
2842 * @param mask Used to implement partial writes (8 and 16-bit).
2843 * @thread EMT
2844 */
2845static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2846{
2847 ICR &= ~value;
2848
2849 return VINF_SUCCESS;
2850}
2851
2852/**
2853 * Read handler for Interrupt Cause Read register.
2854 *
2855 * Reading this register acknowledges all interrupts.
2856 *
2857 * @returns VBox status code.
2858 *
2859 * @param pThis The device state structure.
2860 * @param offset Register offset in memory-mapped frame.
2861 * @param index Register index in register array.
2862 * @param mask Not used.
2863 * @thread EMT
2864 */
2865static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2866{
2867 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
2868 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2869 return rc;
2870
2871 uint32_t value = 0;
2872 rc = e1kRegReadDefault(pThis, offset, index, &value);
2873 if (RT_SUCCESS(rc))
2874 {
2875 /* Do not return masked bits. */
2876 value &= IMS;
2877 if (value)
2878 {
2879 /*
2880 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2881 * with disabled interrupts.
2882 */
2883 //if (IMS)
2884 if (1)
2885 {
2886 /*
2887 * Interrupts were enabled -- we are supposedly at the very
2888 * beginning of interrupt handler
2889 */
2890 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2891 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
2892 /* Clear all pending interrupts */
2893 ICR = 0;
2894 pThis->fIntRaised = false;
2895 /* Lower(0) INTA(0) */
2896 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
2897
2898 pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
2899 if (pThis->fIntMaskUsed)
2900 pThis->fDelayInts = true;
2901 }
2902 else
2903 {
2904 /*
2905 * Interrupts are disabled -- in windows guests ICR read is done
2906 * just before re-enabling interrupts
2907 */
2908 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
2909 }
2910 }
2911 *pu32Value = value;
2912 }
2913 e1kCsLeave(pThis);
2914
2915 return rc;
2916}
2917
2918/**
2919 * Write handler for Interrupt Cause Set register.
2920 *
2921 * Bits corresponding to 1s in 'value' will be set in ICR register.
2922 *
2923 * @param pThis The device state structure.
2924 * @param offset Register offset in memory-mapped frame.
2925 * @param index Register index in register array.
2926 * @param value The value to store.
2927 * @param mask Used to implement partial writes (8 and 16-bit).
2928 * @thread EMT
2929 */
2930static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2931{
2932 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
2933 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
2934}
2935
2936/**
2937 * Write handler for Interrupt Mask Set register.
2938 *
2939 * Will trigger pending interrupts.
2940 *
2941 * @param pThis The device state structure.
2942 * @param offset Register offset in memory-mapped frame.
2943 * @param index Register index in register array.
2944 * @param value The value to store.
2945 * @param mask Used to implement partial writes (8 and 16-bit).
2946 * @thread EMT
2947 */
2948static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2949{
2950 IMS |= value;
2951 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
2952 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
2953 e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, 0);
2954
2955 return VINF_SUCCESS;
2956}
2957
2958/**
2959 * Write handler for Interrupt Mask Clear register.
2960 *
2961 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
2962 *
2963 * @param pThis The device state structure.
2964 * @param offset Register offset in memory-mapped frame.
2965 * @param index Register index in register array.
2966 * @param value The value to store.
2967 * @param mask Used to implement partial writes (8 and 16-bit).
2968 * @thread EMT
2969 */
2970static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2971{
2972 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
2973 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2974 return rc;
2975 if (pThis->fIntRaised)
2976 {
2977 /*
2978 * Technically we should reset fIntRaised in ICR read handler, but it will cause
2979 * Windows to freeze since it may receive an interrupt while still in the very beginning
2980 * of interrupt handler.
2981 */
2982 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
2983 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
2984 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
2985 /* Lower(0) INTA(0) */
2986 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
2987 pThis->fIntRaised = false;
2988 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
2989 }
2990 IMS &= ~value;
2991 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
2992 e1kCsLeave(pThis);
2993
2994 return VINF_SUCCESS;
2995}
2996
2997/**
2998 * Write handler for Receive Control register.
2999 *
3000 * @param pThis The device state structure.
3001 * @param offset Register offset in memory-mapped frame.
3002 * @param index Register index in register array.
3003 * @param value The value to store.
3004 * @param mask Used to implement partial writes (8 and 16-bit).
3005 * @thread EMT
3006 */
3007static int e1kRegWriteRCTL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3008{
3009 /* Update promiscuous mode */
3010 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3011 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3012 {
3013 /* Promiscuity has changed, pass the knowledge on. */
3014#ifndef IN_RING3
3015 return VINF_IOM_R3_MMIO_WRITE;
3016#else
3017 if (pThis->pDrvR3)
3018 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, fBecomePromiscous);
3019#endif
3020 }
3021
3022 /* Adjust receive buffer size */
3023 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3024 if (value & RCTL_BSEX)
3025 cbRxBuf *= 16;
3026 if (cbRxBuf != pThis->u16RxBSize)
3027 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3028 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3029 pThis->u16RxBSize = cbRxBuf;
3030
3031 /* Update the register */
3032 e1kRegWriteDefault(pThis, offset, index, value);
3033
3034 return VINF_SUCCESS;
3035}
3036
3037/**
3038 * Write handler for Packet Buffer Allocation register.
3039 *
3040 * TXA = 64 - RXA.
3041 *
3042 * @param pThis The device state structure.
3043 * @param offset Register offset in memory-mapped frame.
3044 * @param index Register index in register array.
3045 * @param value The value to store.
3046 * @param mask Used to implement partial writes (8 and 16-bit).
3047 * @thread EMT
3048 */
3049static int e1kRegWritePBA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3050{
3051 e1kRegWriteDefault(pThis, offset, index, value);
3052 PBA_st->txa = 64 - PBA_st->rxa;
3053
3054 return VINF_SUCCESS;
3055}
3056
3057/**
3058 * Write handler for Receive Descriptor Tail register.
3059 *
3060 * @remarks Write into RDT forces switch to HC and signal to
3061 * e1kR3NetworkDown_WaitReceiveAvail().
3062 *
3063 * @returns VBox status code.
3064 *
3065 * @param pThis The device state structure.
3066 * @param offset Register offset in memory-mapped frame.
3067 * @param index Register index in register array.
3068 * @param value The value to store.
3069 * @param mask Used to implement partial writes (8 and 16-bit).
3070 * @thread EMT
3071 */
3072static int e1kRegWriteRDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3073{
3074#ifndef IN_RING3
3075 /* XXX */
3076// return VINF_IOM_R3_MMIO_WRITE;
3077#endif
3078 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3079 if (RT_LIKELY(rc == VINF_SUCCESS))
3080 {
3081 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3082 /*
3083 * Some drivers advance RDT too far, so that it equals RDH. This
3084 * somehow manages to work with real hardware but not with this
3085 * emulated device. We can work with these drivers if we just
3086 * write 1 less when we see a driver writing RDT equal to RDH,
3087 * see @bugref{7346}.
3088 */
3089 if (value == RDH)
3090 {
3091 if (RDH == 0)
3092 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3093 else
3094 value = RDH - 1;
3095 }
3096 rc = e1kRegWriteDefault(pThis, offset, index, value);
3097#ifdef E1K_WITH_RXD_CACHE
3098 /*
3099 * We need to fetch descriptors now as RDT may go whole circle
3100 * before we attempt to store a received packet. For example,
3101 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3102 * size being only 8 descriptors! Note that we fetch descriptors
3103 * only when the cache is empty to reduce the number of memory reads
3104 * in case of frequent RDT writes. Don't fetch anything when the
3105 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3106 * messed up state.
3107 * Note that despite the cache may seem empty, meaning that there are
3108 * no more available descriptors in it, it may still be used by RX
3109 * thread which has not yet written the last descriptor back but has
3110 * temporarily released the RX lock in order to write the packet body
3111 * to descriptor's buffer. At this point we still going to do prefetch
3112 * but it won't actually fetch anything if there are no unused slots in
3113 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3114 * reset the cache here even if it appears empty. It will be reset at
3115 * a later point in e1kRxDGet().
3116 */
3117 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3118 e1kRxDPrefetch(pThis);
3119#endif /* E1K_WITH_RXD_CACHE */
3120 e1kCsRxLeave(pThis);
3121 if (RT_SUCCESS(rc))
3122 {
3123/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
3124 * without requiring any context switches. We should also check the
3125 * wait condition before bothering to queue the item as we're currently
3126 * queuing thousands of items per second here in a normal transmit
3127 * scenario. Expect performance changes when fixing this! */
3128#ifdef IN_RING3
3129 /* Signal that we have more receive descriptors available. */
3130 e1kWakeupReceive(pThis->CTX_SUFF(pDevIns));
3131#else
3132 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
3133 if (pItem)
3134 PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
3135#endif
3136 }
3137 }
3138 return rc;
3139}
3140
3141/**
3142 * Write handler for Receive Delay Timer register.
3143 *
3144 * @param pThis The device state structure.
3145 * @param offset Register offset in memory-mapped frame.
3146 * @param index Register index in register array.
3147 * @param value The value to store.
3148 * @param mask Used to implement partial writes (8 and 16-bit).
3149 * @thread EMT
3150 */
3151static int e1kRegWriteRDTR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3152{
3153 e1kRegWriteDefault(pThis, offset, index, value);
3154 if (value & RDTR_FPD)
3155 {
3156 /* Flush requested, cancel both timers and raise interrupt */
3157#ifdef E1K_USE_RX_TIMERS
3158 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3159 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3160#endif
3161 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3162 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3163 }
3164
3165 return VINF_SUCCESS;
3166}
3167
3168DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3169{
3170 /**
3171 * Make sure TDT won't change during computation. EMT may modify TDT at
3172 * any moment.
3173 */
3174 uint32_t tdt = TDT;
3175 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3176}
3177
3178#ifdef IN_RING3
3179#ifdef E1K_TX_DELAY
3180
3181/**
3182 * Transmit Delay Timer handler.
3183 *
3184 * @remarks We only get here when the timer expires.
3185 *
3186 * @param pDevIns Pointer to device instance structure.
3187 * @param pTimer Pointer to the timer.
3188 * @param pvUser NULL.
3189 * @thread EMT
3190 */
3191static DECLCALLBACK(void) e1kTxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3192{
3193 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3194 Assert(PDMCritSectIsOwner(&pThis->csTx));
3195
3196 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3197#ifdef E1K_INT_STATS
3198 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3199 if (u64Elapsed > pThis->uStatMaxTxDelay)
3200 pThis->uStatMaxTxDelay = u64Elapsed;
3201#endif
3202 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
3203 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3204}
3205#endif /* E1K_TX_DELAY */
3206
3207#ifdef E1K_USE_TX_TIMERS
3208
3209/**
3210 * Transmit Interrupt Delay Timer handler.
3211 *
3212 * @remarks We only get here when the timer expires.
3213 *
3214 * @param pDevIns Pointer to device instance structure.
3215 * @param pTimer Pointer to the timer.
3216 * @param pvUser NULL.
3217 * @thread EMT
3218 */
3219static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3220{
3221 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3222
3223 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3224 /* Cancel absolute delay timer as we have already got attention */
3225#ifndef E1K_NO_TAD
3226 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
3227#endif /* E1K_NO_TAD */
3228 e1kRaiseInterrupt(pThis, ICR_TXDW);
3229}
3230
3231/**
3232 * Transmit Absolute Delay Timer handler.
3233 *
3234 * @remarks We only get here when the timer expires.
3235 *
3236 * @param pDevIns Pointer to device instance structure.
3237 * @param pTimer Pointer to the timer.
3238 * @param pvUser NULL.
3239 * @thread EMT
3240 */
3241static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3242{
3243 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3244
3245 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3246 /* Cancel interrupt delay timer as we have already got attention */
3247 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
3248 e1kRaiseInterrupt(pThis, ICR_TXDW);
3249}
3250
3251#endif /* E1K_USE_TX_TIMERS */
3252#ifdef E1K_USE_RX_TIMERS
3253
3254/**
3255 * Receive Interrupt Delay Timer handler.
3256 *
3257 * @remarks We only get here when the timer expires.
3258 *
3259 * @param pDevIns Pointer to device instance structure.
3260 * @param pTimer Pointer to the timer.
3261 * @param pvUser NULL.
3262 * @thread EMT
3263 */
3264static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3265{
3266 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3267
3268 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3269 /* Cancel absolute delay timer as we have already got attention */
3270 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3271 e1kRaiseInterrupt(pThis, ICR_RXT0);
3272}
3273
3274/**
3275 * Receive Absolute Delay Timer handler.
3276 *
3277 * @remarks We only get here when the timer expires.
3278 *
3279 * @param pDevIns Pointer to device instance structure.
3280 * @param pTimer Pointer to the timer.
3281 * @param pvUser NULL.
3282 * @thread EMT
3283 */
3284static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3285{
3286 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3287
3288 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3289 /* Cancel interrupt delay timer as we have already got attention */
3290 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3291 e1kRaiseInterrupt(pThis, ICR_RXT0);
3292}
3293
3294#endif /* E1K_USE_RX_TIMERS */
3295
3296/**
3297 * Late Interrupt Timer handler.
3298 *
3299 * @param pDevIns Pointer to device instance structure.
3300 * @param pTimer Pointer to the timer.
3301 * @param pvUser NULL.
3302 * @thread EMT
3303 */
3304static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3305{
3306 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3307
3308 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3309 STAM_COUNTER_INC(&pThis->StatLateInts);
3310 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3311#if 0
3312 if (pThis->iStatIntLost > -100)
3313 pThis->iStatIntLost--;
3314#endif
3315 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, 0);
3316 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3317}
3318
3319/**
3320 * Link Up Timer handler.
3321 *
3322 * @param pDevIns Pointer to device instance structure.
3323 * @param pTimer Pointer to the timer.
3324 * @param pvUser NULL.
3325 * @thread EMT
3326 */
3327static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3328{
3329 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3330
3331 /*
3332 * This can happen if we set the link status to down when the Link up timer was
3333 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3334 * and connect+disconnect the cable very quick.
3335 */
3336 if (!pThis->fCableConnected)
3337 return;
3338
3339 e1kR3LinkUp(pThis);
3340}
3341
3342#endif /* IN_RING3 */
3343
3344/**
3345 * Sets up the GSO context according to the TSE new context descriptor.
3346 *
3347 * @param pGso The GSO context to setup.
3348 * @param pCtx The context descriptor.
3349 */
3350DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3351{
3352 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3353
3354 /*
3355 * See if the context descriptor describes something that could be TCP or
3356 * UDP over IPv[46].
3357 */
3358 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3359 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3360 {
3361 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3362 return;
3363 }
3364 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3365 {
3366 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3367 return;
3368 }
3369 if (RT_UNLIKELY( pCtx->dw2.fTCP
3370 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3371 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3372 {
3373 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3374 return;
3375 }
3376
3377 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3378 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3379 {
3380 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3381 return;
3382 }
3383
3384 /* IPv4 checksum offset. */
3385 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3386 {
3387 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3388 return;
3389 }
3390
3391 /* TCP/UDP checksum offsets. */
3392 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3393 != ( pCtx->dw2.fTCP
3394 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3395 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3396 {
3397 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3398 return;
3399 }
3400
3401 /*
3402 * Because of internal networking using a 16-bit size field for GSO context
3403 * plus frame, we have to make sure we don't exceed this.
3404 */
3405 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3406 {
3407 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3408 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3409 return;
3410 }
3411
3412 /*
3413 * We're good for now - we'll do more checks when seeing the data.
3414 * So, figure the type of offloading and setup the context.
3415 */
3416 if (pCtx->dw2.fIP)
3417 {
3418 if (pCtx->dw2.fTCP)
3419 {
3420 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3421 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3422 }
3423 else
3424 {
3425 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3426 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3427 }
3428 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3429 * this yet it seems)... */
3430 }
3431 else
3432 {
3433 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /* @todo IPv6 UFO */
3434 if (pCtx->dw2.fTCP)
3435 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3436 else
3437 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3438 }
3439 pGso->offHdr1 = pCtx->ip.u8CSS;
3440 pGso->offHdr2 = pCtx->tu.u8CSS;
3441 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3442 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3443 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3444 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3445 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3446}
3447
3448/**
3449 * Checks if we can use GSO processing for the current TSE frame.
3450 *
3451 * @param pThis The device state structure.
3452 * @param pGso The GSO context.
3453 * @param pData The first data descriptor of the frame.
3454 * @param pCtx The TSO context descriptor.
3455 */
3456DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3457{
3458 if (!pData->cmd.fTSE)
3459 {
3460 E1kLog2(("e1kCanDoGso: !TSE\n"));
3461 return false;
3462 }
3463 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3464 {
3465 E1kLog(("e1kCanDoGso: VLE\n"));
3466 return false;
3467 }
3468 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3469 {
3470 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3471 return false;
3472 }
3473
3474 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3475 {
3476 case PDMNETWORKGSOTYPE_IPV4_TCP:
3477 case PDMNETWORKGSOTYPE_IPV4_UDP:
3478 if (!pData->dw3.fIXSM)
3479 {
3480 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3481 return false;
3482 }
3483 if (!pData->dw3.fTXSM)
3484 {
3485 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3486 return false;
3487 }
3488 /** @todo what more check should we perform here? Ethernet frame type? */
3489 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3490 return true;
3491
3492 case PDMNETWORKGSOTYPE_IPV6_TCP:
3493 case PDMNETWORKGSOTYPE_IPV6_UDP:
3494 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3495 {
3496 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3497 return false;
3498 }
3499 if (!pData->dw3.fTXSM)
3500 {
3501 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3502 return false;
3503 }
3504 /** @todo what more check should we perform here? Ethernet frame type? */
3505 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3506 return true;
3507
3508 default:
3509 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3510 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3511 return false;
3512 }
3513}
3514
3515/**
3516 * Frees the current xmit buffer.
3517 *
3518 * @param pThis The device state structure.
3519 */
3520static void e1kXmitFreeBuf(PE1KSTATE pThis)
3521{
3522 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3523 if (pSg)
3524 {
3525 pThis->CTX_SUFF(pTxSg) = NULL;
3526
3527 if (pSg->pvAllocator != pThis)
3528 {
3529 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3530 if (pDrv)
3531 pDrv->pfnFreeBuf(pDrv, pSg);
3532 }
3533 else
3534 {
3535 /* loopback */
3536 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3537 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3538 pSg->fFlags = 0;
3539 pSg->pvAllocator = NULL;
3540 }
3541 }
3542}
3543
3544#ifndef E1K_WITH_TXD_CACHE
3545/**
3546 * Allocates an xmit buffer.
3547 *
3548 * @returns See PDMINETWORKUP::pfnAllocBuf.
3549 * @param pThis The device state structure.
3550 * @param cbMin The minimum frame size.
3551 * @param fExactSize Whether cbMin is exact or if we have to max it
3552 * out to the max MTU size.
3553 * @param fGso Whether this is a GSO frame or not.
3554 */
3555DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, size_t cbMin, bool fExactSize, bool fGso)
3556{
3557 /* Adjust cbMin if necessary. */
3558 if (!fExactSize)
3559 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3560
3561 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3562 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3563 e1kXmitFreeBuf(pThis);
3564 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3565
3566 /*
3567 * Allocate the buffer.
3568 */
3569 PPDMSCATTERGATHER pSg;
3570 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3571 {
3572 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3573 if (RT_UNLIKELY(!pDrv))
3574 return VERR_NET_DOWN;
3575 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3576 if (RT_FAILURE(rc))
3577 {
3578 /* Suspend TX as we are out of buffers atm */
3579 STATUS |= STATUS_TXOFF;
3580 return rc;
3581 }
3582 }
3583 else
3584 {
3585 /* Create a loopback using the fallback buffer and preallocated SG. */
3586 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3587 pSg = &pThis->uTxFallback.Sg;
3588 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3589 pSg->cbUsed = 0;
3590 pSg->cbAvailable = 0;
3591 pSg->pvAllocator = pThis;
3592 pSg->pvUser = NULL; /* No GSO here. */
3593 pSg->cSegs = 1;
3594 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3595 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3596 }
3597
3598 pThis->CTX_SUFF(pTxSg) = pSg;
3599 return VINF_SUCCESS;
3600}
3601#else /* E1K_WITH_TXD_CACHE */
3602/**
3603 * Allocates an xmit buffer.
3604 *
3605 * @returns See PDMINETWORKUP::pfnAllocBuf.
3606 * @param pThis The device state structure.
3607 * @param cbMin The minimum frame size.
3608 * @param fExactSize Whether cbMin is exact or if we have to max it
3609 * out to the max MTU size.
3610 * @param fGso Whether this is a GSO frame or not.
3611 */
3612DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, bool fGso)
3613{
3614 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3615 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3616 e1kXmitFreeBuf(pThis);
3617 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3618
3619 /*
3620 * Allocate the buffer.
3621 */
3622 PPDMSCATTERGATHER pSg;
3623 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3624 {
3625 if (pThis->cbTxAlloc == 0)
3626 {
3627 /* Zero packet, no need for the buffer */
3628 return VINF_SUCCESS;
3629 }
3630
3631 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3632 if (RT_UNLIKELY(!pDrv))
3633 return VERR_NET_DOWN;
3634 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3635 if (RT_FAILURE(rc))
3636 {
3637 /* Suspend TX as we are out of buffers atm */
3638 STATUS |= STATUS_TXOFF;
3639 return rc;
3640 }
3641 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3642 pThis->szPrf, pThis->cbTxAlloc,
3643 pThis->fVTag ? "VLAN " : "",
3644 pThis->fGSO ? "GSO " : ""));
3645 pThis->cbTxAlloc = 0;
3646 }
3647 else
3648 {
3649 /* Create a loopback using the fallback buffer and preallocated SG. */
3650 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3651 pSg = &pThis->uTxFallback.Sg;
3652 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3653 pSg->cbUsed = 0;
3654 pSg->cbAvailable = 0;
3655 pSg->pvAllocator = pThis;
3656 pSg->pvUser = NULL; /* No GSO here. */
3657 pSg->cSegs = 1;
3658 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3659 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3660 }
3661
3662 pThis->CTX_SUFF(pTxSg) = pSg;
3663 return VINF_SUCCESS;
3664}
3665#endif /* E1K_WITH_TXD_CACHE */
3666
3667/**
3668 * Checks if it's a GSO buffer or not.
3669 *
3670 * @returns true / false.
3671 * @param pTxSg The scatter / gather buffer.
3672 */
3673DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3674{
3675#if 0
3676 if (!pTxSg)
3677 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3678 if (pTxSg && pTxSg->pvUser)
3679 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3680#endif
3681 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3682}
3683
3684#ifndef E1K_WITH_TXD_CACHE
3685/**
3686 * Load transmit descriptor from guest memory.
3687 *
3688 * @param pThis The device state structure.
3689 * @param pDesc Pointer to descriptor union.
3690 * @param addr Physical address in guest context.
3691 * @thread E1000_TX
3692 */
3693DECLINLINE(void) e1kLoadDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
3694{
3695 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3696}
3697#else /* E1K_WITH_TXD_CACHE */
3698/**
3699 * Load transmit descriptors from guest memory.
3700 *
3701 * We need two physical reads in case the tail wrapped around the end of TX
3702 * descriptor ring.
3703 *
3704 * @returns the actual number of descriptors fetched.
3705 * @param pThis The device state structure.
3706 * @param pDesc Pointer to descriptor union.
3707 * @param addr Physical address in guest context.
3708 * @thread E1000_TX
3709 */
3710DECLINLINE(unsigned) e1kTxDLoadMore(PE1KSTATE pThis)
3711{
3712 Assert(pThis->iTxDCurrent == 0);
3713 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3714 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3715 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3716 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3717 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3718 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3719 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u "
3720 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3721 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3722 nFirstNotLoaded, nDescsInSingleRead));
3723 if (nDescsToFetch == 0)
3724 return 0;
3725 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3726 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3727 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3728 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3729 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3730 pThis->szPrf, nDescsInSingleRead,
3731 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3732 nFirstNotLoaded, TDLEN, TDH, TDT));
3733 if (nDescsToFetch > nDescsInSingleRead)
3734 {
3735 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3736 ((uint64_t)TDBAH << 32) + TDBAL,
3737 pFirstEmptyDesc + nDescsInSingleRead,
3738 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3739 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3740 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3741 TDBAH, TDBAL));
3742 }
3743 pThis->nTxDFetched += nDescsToFetch;
3744 return nDescsToFetch;
3745}
3746
3747/**
3748 * Load transmit descriptors from guest memory only if there are no loaded
3749 * descriptors.
3750 *
3751 * @returns true if there are descriptors in cache.
3752 * @param pThis The device state structure.
3753 * @param pDesc Pointer to descriptor union.
3754 * @param addr Physical address in guest context.
3755 * @thread E1000_TX
3756 */
3757DECLINLINE(bool) e1kTxDLazyLoad(PE1KSTATE pThis)
3758{
3759 if (pThis->nTxDFetched == 0)
3760 return e1kTxDLoadMore(pThis) != 0;
3761 return true;
3762}
3763#endif /* E1K_WITH_TXD_CACHE */
3764
3765/**
3766 * Write back transmit descriptor to guest memory.
3767 *
3768 * @param pThis The device state structure.
3769 * @param pDesc Pointer to descriptor union.
3770 * @param addr Physical address in guest context.
3771 * @thread E1000_TX
3772 */
3773DECLINLINE(void) e1kWriteBackDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
3774{
3775 /* Only the last half of the descriptor has to be written back. */
3776 e1kPrintTDesc(pThis, pDesc, "^^^");
3777 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3778}
3779
3780/**
3781 * Transmit complete frame.
3782 *
3783 * @remarks We skip the FCS since we're not responsible for sending anything to
3784 * a real ethernet wire.
3785 *
3786 * @param pThis The device state structure.
3787 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3788 * @thread E1000_TX
3789 */
3790static void e1kTransmitFrame(PE1KSTATE pThis, bool fOnWorkerThread)
3791{
3792 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3793 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
3794 Assert(!pSg || pSg->cSegs == 1);
3795
3796 if (cbFrame > 70) /* unqualified guess */
3797 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
3798
3799#ifdef E1K_INT_STATS
3800 if (cbFrame <= 1514)
3801 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
3802 else if (cbFrame <= 2962)
3803 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
3804 else if (cbFrame <= 4410)
3805 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
3806 else if (cbFrame <= 5858)
3807 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
3808 else if (cbFrame <= 7306)
3809 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
3810 else if (cbFrame <= 8754)
3811 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
3812 else if (cbFrame <= 16384)
3813 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
3814 else if (cbFrame <= 32768)
3815 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
3816 else
3817 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
3818#endif /* E1K_INT_STATS */
3819
3820 /* Add VLAN tag */
3821 if (cbFrame > 12 && pThis->fVTag)
3822 {
3823 E1kLog3(("%s Inserting VLAN tag %08x\n",
3824 pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
3825 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
3826 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
3827 pSg->cbUsed += 4;
3828 cbFrame += 4;
3829 Assert(pSg->cbUsed == cbFrame);
3830 Assert(pSg->cbUsed <= pSg->cbAvailable);
3831 }
3832/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
3833 "%.*Rhxd\n"
3834 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
3835 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
3836
3837 /* Update the stats */
3838 E1K_INC_CNT32(TPT);
3839 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3840 E1K_INC_CNT32(GPTC);
3841 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3842 E1K_INC_CNT32(BPTC);
3843 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3844 E1K_INC_CNT32(MPTC);
3845 /* Update octet transmit counter */
3846 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3847 if (pThis->CTX_SUFF(pDrv))
3848 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
3849 if (cbFrame == 64)
3850 E1K_INC_CNT32(PTC64);
3851 else if (cbFrame < 128)
3852 E1K_INC_CNT32(PTC127);
3853 else if (cbFrame < 256)
3854 E1K_INC_CNT32(PTC255);
3855 else if (cbFrame < 512)
3856 E1K_INC_CNT32(PTC511);
3857 else if (cbFrame < 1024)
3858 E1K_INC_CNT32(PTC1023);
3859 else
3860 E1K_INC_CNT32(PTC1522);
3861
3862 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
3863
3864 /*
3865 * Dump and send the packet.
3866 */
3867 int rc = VERR_NET_DOWN;
3868 if (pSg && pSg->pvAllocator != pThis)
3869 {
3870 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3871
3872 pThis->CTX_SUFF(pTxSg) = NULL;
3873 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3874 if (pDrv)
3875 {
3876 /* Release critical section to avoid deadlock in CanReceive */
3877 //e1kCsLeave(pThis);
3878 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3879 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3880 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3881 //e1kCsEnter(pThis, RT_SRC_POS);
3882 }
3883 }
3884 else if (pSg)
3885 {
3886 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
3887 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3888
3889 /** @todo do we actually need to check that we're in loopback mode here? */
3890 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3891 {
3892 E1KRXDST status;
3893 RT_ZERO(status);
3894 status.fPIF = true;
3895 e1kHandleRxPacket(pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
3896 rc = VINF_SUCCESS;
3897 }
3898 e1kXmitFreeBuf(pThis);
3899 }
3900 else
3901 rc = VERR_NET_DOWN;
3902 if (RT_FAILURE(rc))
3903 {
3904 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3905 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3906 }
3907
3908 pThis->led.Actual.s.fWriting = 0;
3909}
3910
3911/**
3912 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3913 *
3914 * @param pThis The device state structure.
3915 * @param pPkt Pointer to the packet.
3916 * @param u16PktLen Total length of the packet.
3917 * @param cso Offset in packet to write checksum at.
3918 * @param css Offset in packet to start computing
3919 * checksum from.
3920 * @param cse Offset in packet to stop computing
3921 * checksum at.
3922 * @thread E1000_TX
3923 */
3924static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3925{
3926 if (css >= u16PktLen)
3927 {
3928 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
3929 pThis->szPrf, cso, u16PktLen));
3930 return;
3931 }
3932
3933 if (cso >= u16PktLen - 1)
3934 {
3935 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
3936 pThis->szPrf, cso, u16PktLen));
3937 return;
3938 }
3939
3940 if (cse == 0)
3941 cse = u16PktLen - 1;
3942 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
3943 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
3944 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
3945 *(uint16_t*)(pPkt + cso) = u16ChkSum;
3946}
3947
3948/**
3949 * Add a part of descriptor's buffer to transmit frame.
3950 *
3951 * @remarks data.u64BufAddr is used unconditionally for both data
3952 * and legacy descriptors since it is identical to
3953 * legacy.u64BufAddr.
3954 *
3955 * @param pThis The device state structure.
3956 * @param pDesc Pointer to the descriptor to transmit.
3957 * @param u16Len Length of buffer to the end of segment.
3958 * @param fSend Force packet sending.
3959 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3960 * @thread E1000_TX
3961 */
3962#ifndef E1K_WITH_TXD_CACHE
3963static void e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
3964{
3965 /* TCP header being transmitted */
3966 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
3967 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
3968 /* IP header being transmitted */
3969 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
3970 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
3971
3972 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
3973 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
3974 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
3975
3976 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
3977 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
3978 E1kLog3(("%s Dump of the segment:\n"
3979 "%.*Rhxd\n"
3980 "%s --- End of dump ---\n",
3981 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
3982 pThis->u16TxPktLen += u16Len;
3983 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
3984 pThis->szPrf, pThis->u16TxPktLen));
3985 if (pThis->u16HdrRemain > 0)
3986 {
3987 /* The header was not complete, check if it is now */
3988 if (u16Len >= pThis->u16HdrRemain)
3989 {
3990 /* The rest is payload */
3991 u16Len -= pThis->u16HdrRemain;
3992 pThis->u16HdrRemain = 0;
3993 /* Save partial checksum and flags */
3994 pThis->u32SavedCsum = pTcpHdr->chksum;
3995 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
3996 /* Clear FIN and PSH flags now and set them only in the last segment */
3997 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
3998 }
3999 else
4000 {
4001 /* Still not */
4002 pThis->u16HdrRemain -= u16Len;
4003 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4004 pThis->szPrf, pThis->u16HdrRemain));
4005 return;
4006 }
4007 }
4008
4009 pThis->u32PayRemain -= u16Len;
4010
4011 if (fSend)
4012 {
4013 /* Leave ethernet header intact */
4014 /* IP Total Length = payload + headers - ethernet header */
4015 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4016 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4017 pThis->szPrf, ntohs(pIpHdr->total_len)));
4018 /* Update IP Checksum */
4019 pIpHdr->chksum = 0;
4020 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4021 pThis->contextTSE.ip.u8CSO,
4022 pThis->contextTSE.ip.u8CSS,
4023 pThis->contextTSE.ip.u16CSE);
4024
4025 /* Update TCP flags */
4026 /* Restore original FIN and PSH flags for the last segment */
4027 if (pThis->u32PayRemain == 0)
4028 {
4029 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4030 E1K_INC_CNT32(TSCTC);
4031 }
4032 /* Add TCP length to partial pseudo header sum */
4033 uint32_t csum = pThis->u32SavedCsum
4034 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4035 while (csum >> 16)
4036 csum = (csum >> 16) + (csum & 0xFFFF);
4037 pTcpHdr->chksum = csum;
4038 /* Compute final checksum */
4039 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4040 pThis->contextTSE.tu.u8CSO,
4041 pThis->contextTSE.tu.u8CSS,
4042 pThis->contextTSE.tu.u16CSE);
4043
4044 /*
4045 * Transmit it. If we've use the SG already, allocate a new one before
4046 * we copy of the data.
4047 */
4048 if (!pThis->CTX_SUFF(pTxSg))
4049 e1kXmitAllocBuf(pThis, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4050 if (pThis->CTX_SUFF(pTxSg))
4051 {
4052 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4053 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4054 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4055 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4056 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4057 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4058 }
4059 e1kTransmitFrame(pThis, fOnWorkerThread);
4060
4061 /* Update Sequence Number */
4062 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4063 - pThis->contextTSE.dw3.u8HDRLEN);
4064 /* Increment IP identification */
4065 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4066 }
4067}
4068#else /* E1K_WITH_TXD_CACHE */
4069static int e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4070{
4071 int rc = VINF_SUCCESS;
4072 /* TCP header being transmitted */
4073 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4074 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4075 /* IP header being transmitted */
4076 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4077 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4078
4079 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4080 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4081 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4082
4083 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4084 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4085 E1kLog3(("%s Dump of the segment:\n"
4086 "%.*Rhxd\n"
4087 "%s --- End of dump ---\n",
4088 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4089 pThis->u16TxPktLen += u16Len;
4090 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4091 pThis->szPrf, pThis->u16TxPktLen));
4092 if (pThis->u16HdrRemain > 0)
4093 {
4094 /* The header was not complete, check if it is now */
4095 if (u16Len >= pThis->u16HdrRemain)
4096 {
4097 /* The rest is payload */
4098 u16Len -= pThis->u16HdrRemain;
4099 pThis->u16HdrRemain = 0;
4100 /* Save partial checksum and flags */
4101 pThis->u32SavedCsum = pTcpHdr->chksum;
4102 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4103 /* Clear FIN and PSH flags now and set them only in the last segment */
4104 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4105 }
4106 else
4107 {
4108 /* Still not */
4109 pThis->u16HdrRemain -= u16Len;
4110 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4111 pThis->szPrf, pThis->u16HdrRemain));
4112 return rc;
4113 }
4114 }
4115
4116 pThis->u32PayRemain -= u16Len;
4117
4118 if (fSend)
4119 {
4120 /* Leave ethernet header intact */
4121 /* IP Total Length = payload + headers - ethernet header */
4122 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4123 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4124 pThis->szPrf, ntohs(pIpHdr->total_len)));
4125 /* Update IP Checksum */
4126 pIpHdr->chksum = 0;
4127 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4128 pThis->contextTSE.ip.u8CSO,
4129 pThis->contextTSE.ip.u8CSS,
4130 pThis->contextTSE.ip.u16CSE);
4131
4132 /* Update TCP flags */
4133 /* Restore original FIN and PSH flags for the last segment */
4134 if (pThis->u32PayRemain == 0)
4135 {
4136 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4137 E1K_INC_CNT32(TSCTC);
4138 }
4139 /* Add TCP length to partial pseudo header sum */
4140 uint32_t csum = pThis->u32SavedCsum
4141 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4142 while (csum >> 16)
4143 csum = (csum >> 16) + (csum & 0xFFFF);
4144 pTcpHdr->chksum = csum;
4145 /* Compute final checksum */
4146 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4147 pThis->contextTSE.tu.u8CSO,
4148 pThis->contextTSE.tu.u8CSS,
4149 pThis->contextTSE.tu.u16CSE);
4150
4151 /*
4152 * Transmit it.
4153 */
4154 if (pThis->CTX_SUFF(pTxSg))
4155 {
4156 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4157 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4158 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4159 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4160 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4161 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4162 }
4163 e1kTransmitFrame(pThis, fOnWorkerThread);
4164
4165 /* Update Sequence Number */
4166 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4167 - pThis->contextTSE.dw3.u8HDRLEN);
4168 /* Increment IP identification */
4169 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4170
4171 /* Allocate new buffer for the next segment. */
4172 if (pThis->u32PayRemain)
4173 {
4174 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4175 pThis->contextTSE.dw3.u16MSS)
4176 + pThis->contextTSE.dw3.u8HDRLEN
4177 + (pThis->fVTag ? 4 : 0);
4178 rc = e1kXmitAllocBuf(pThis, false /* fGSO */);
4179 }
4180 }
4181
4182 return rc;
4183}
4184#endif /* E1K_WITH_TXD_CACHE */
4185
4186#ifndef E1K_WITH_TXD_CACHE
4187/**
4188 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4189 * frame.
4190 *
4191 * We construct the frame in the fallback buffer first and the copy it to the SG
4192 * buffer before passing it down to the network driver code.
4193 *
4194 * @returns true if the frame should be transmitted, false if not.
4195 *
4196 * @param pThis The device state structure.
4197 * @param pDesc Pointer to the descriptor to transmit.
4198 * @param cbFragment Length of descriptor's buffer.
4199 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4200 * @thread E1000_TX
4201 */
4202static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4203{
4204 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4205 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4206 Assert(pDesc->data.cmd.fTSE);
4207 Assert(!e1kXmitIsGsoBuf(pTxSg));
4208
4209 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4210 Assert(u16MaxPktLen != 0);
4211 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4212
4213 /*
4214 * Carve out segments.
4215 */
4216 do
4217 {
4218 /* Calculate how many bytes we have left in this TCP segment */
4219 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4220 if (cb > cbFragment)
4221 {
4222 /* This descriptor fits completely into current segment */
4223 cb = cbFragment;
4224 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4225 }
4226 else
4227 {
4228 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4229 /*
4230 * Rewind the packet tail pointer to the beginning of payload,
4231 * so we continue writing right beyond the header.
4232 */
4233 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4234 }
4235
4236 pDesc->data.u64BufAddr += cb;
4237 cbFragment -= cb;
4238 } while (cbFragment > 0);
4239
4240 if (pDesc->data.cmd.fEOP)
4241 {
4242 /* End of packet, next segment will contain header. */
4243 if (pThis->u32PayRemain != 0)
4244 E1K_INC_CNT32(TSCTFC);
4245 pThis->u16TxPktLen = 0;
4246 e1kXmitFreeBuf(pThis);
4247 }
4248
4249 return false;
4250}
4251#else /* E1K_WITH_TXD_CACHE */
4252/**
4253 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4254 * frame.
4255 *
4256 * We construct the frame in the fallback buffer first and the copy it to the SG
4257 * buffer before passing it down to the network driver code.
4258 *
4259 * @returns error code
4260 *
4261 * @param pThis The device state structure.
4262 * @param pDesc Pointer to the descriptor to transmit.
4263 * @param cbFragment Length of descriptor's buffer.
4264 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4265 * @thread E1000_TX
4266 */
4267static int e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC* pDesc, bool fOnWorkerThread)
4268{
4269#ifdef VBOX_STRICT
4270 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4271 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4272 Assert(pDesc->data.cmd.fTSE);
4273 Assert(!e1kXmitIsGsoBuf(pTxSg));
4274#endif
4275
4276 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4277 Assert(u16MaxPktLen != 0);
4278 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4279
4280 /*
4281 * Carve out segments.
4282 */
4283 int rc;
4284 do
4285 {
4286 /* Calculate how many bytes we have left in this TCP segment */
4287 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4288 if (cb > pDesc->data.cmd.u20DTALEN)
4289 {
4290 /* This descriptor fits completely into current segment */
4291 cb = pDesc->data.cmd.u20DTALEN;
4292 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4293 }
4294 else
4295 {
4296 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4297 /*
4298 * Rewind the packet tail pointer to the beginning of payload,
4299 * so we continue writing right beyond the header.
4300 */
4301 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4302 }
4303
4304 pDesc->data.u64BufAddr += cb;
4305 pDesc->data.cmd.u20DTALEN -= cb;
4306 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4307
4308 if (pDesc->data.cmd.fEOP)
4309 {
4310 /* End of packet, next segment will contain header. */
4311 if (pThis->u32PayRemain != 0)
4312 E1K_INC_CNT32(TSCTFC);
4313 pThis->u16TxPktLen = 0;
4314 e1kXmitFreeBuf(pThis);
4315 }
4316
4317 return false;
4318}
4319#endif /* E1K_WITH_TXD_CACHE */
4320
4321
4322/**
4323 * Add descriptor's buffer to transmit frame.
4324 *
4325 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4326 * TSE frames we cannot handle as GSO.
4327 *
4328 * @returns true on success, false on failure.
4329 *
4330 * @param pThis The device state structure.
4331 * @param PhysAddr The physical address of the descriptor buffer.
4332 * @param cbFragment Length of descriptor's buffer.
4333 * @thread E1000_TX
4334 */
4335static bool e1kAddToFrame(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
4336{
4337 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4338 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4339 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4340
4341 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4342 {
4343 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4344 return false;
4345 }
4346 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
4347 {
4348 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4349 return false;
4350 }
4351
4352 if (RT_LIKELY(pTxSg))
4353 {
4354 Assert(pTxSg->cSegs == 1);
4355 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
4356
4357 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4358 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4359
4360 pTxSg->cbUsed = cbNewPkt;
4361 }
4362 pThis->u16TxPktLen = cbNewPkt;
4363
4364 return true;
4365}
4366
4367
4368/**
4369 * Write the descriptor back to guest memory and notify the guest.
4370 *
4371 * @param pThis The device state structure.
4372 * @param pDesc Pointer to the descriptor have been transmitted.
4373 * @param addr Physical address of the descriptor in guest memory.
4374 * @thread E1000_TX
4375 */
4376static void e1kDescReport(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr)
4377{
4378 /*
4379 * We fake descriptor write-back bursting. Descriptors are written back as they are
4380 * processed.
4381 */
4382 /* Let's pretend we process descriptors. Write back with DD set. */
4383 /*
4384 * Prior to r71586 we tried to accomodate the case when write-back bursts
4385 * are enabled without actually implementing bursting by writing back all
4386 * descriptors, even the ones that do not have RS set. This caused kernel
4387 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4388 * associated with written back descriptor if it happened to be a context
4389 * descriptor since context descriptors do not have skb associated to them.
4390 * Starting from r71586 we write back only the descriptors with RS set,
4391 * which is a little bit different from what the real hardware does in
4392 * case there is a chain of data descritors where some of them have RS set
4393 * and others do not. It is very uncommon scenario imho.
4394 * We need to check RPS as well since some legacy drivers use it instead of
4395 * RS even with newer cards.
4396 */
4397 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4398 {
4399 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4400 e1kWriteBackDesc(pThis, pDesc, addr);
4401 if (pDesc->legacy.cmd.fEOP)
4402 {
4403#ifdef E1K_USE_TX_TIMERS
4404 if (pDesc->legacy.cmd.fIDE)
4405 {
4406 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4407 //if (pThis->fIntRaised)
4408 //{
4409 // /* Interrupt is already pending, no need for timers */
4410 // ICR |= ICR_TXDW;
4411 //}
4412 //else {
4413 /* Arm the timer to fire in TIVD usec (discard .024) */
4414 e1kArmTimer(pThis, pThis->CTX_SUFF(pTIDTimer), TIDV);
4415# ifndef E1K_NO_TAD
4416 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4417 E1kLog2(("%s Checking if TAD timer is running\n",
4418 pThis->szPrf));
4419 if (TADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pTADTimer)))
4420 e1kArmTimer(pThis, pThis->CTX_SUFF(pTADTimer), TADV);
4421# endif /* E1K_NO_TAD */
4422 }
4423 else
4424 {
4425 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4426 pThis->szPrf));
4427# ifndef E1K_NO_TAD
4428 /* Cancel both timers if armed and fire immediately. */
4429 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
4430# endif /* E1K_NO_TAD */
4431#endif /* E1K_USE_TX_TIMERS */
4432 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4433 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXDW);
4434#ifdef E1K_USE_TX_TIMERS
4435 }
4436#endif /* E1K_USE_TX_TIMERS */
4437 }
4438 }
4439 else
4440 {
4441 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4442 }
4443}
4444
4445#ifndef E1K_WITH_TXD_CACHE
4446
4447/**
4448 * Process Transmit Descriptor.
4449 *
4450 * E1000 supports three types of transmit descriptors:
4451 * - legacy data descriptors of older format (context-less).
4452 * - data the same as legacy but providing new offloading capabilities.
4453 * - context sets up the context for following data descriptors.
4454 *
4455 * @param pThis The device state structure.
4456 * @param pDesc Pointer to descriptor union.
4457 * @param addr Physical address of descriptor in guest memory.
4458 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4459 * @thread E1000_TX
4460 */
4461static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr, bool fOnWorkerThread)
4462{
4463 int rc = VINF_SUCCESS;
4464 uint32_t cbVTag = 0;
4465
4466 e1kPrintTDesc(pThis, pDesc, "vvv");
4467
4468#ifdef E1K_USE_TX_TIMERS
4469 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4470#endif /* E1K_USE_TX_TIMERS */
4471
4472 switch (e1kGetDescType(pDesc))
4473 {
4474 case E1K_DTYP_CONTEXT:
4475 if (pDesc->context.dw2.fTSE)
4476 {
4477 pThis->contextTSE = pDesc->context;
4478 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4479 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4480 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4481 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4482 }
4483 else
4484 {
4485 pThis->contextNormal = pDesc->context;
4486 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4487 }
4488 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4489 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4490 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4491 pDesc->context.ip.u8CSS,
4492 pDesc->context.ip.u8CSO,
4493 pDesc->context.ip.u16CSE,
4494 pDesc->context.tu.u8CSS,
4495 pDesc->context.tu.u8CSO,
4496 pDesc->context.tu.u16CSE));
4497 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4498 e1kDescReport(pThis, pDesc, addr);
4499 break;
4500
4501 case E1K_DTYP_DATA:
4502 {
4503 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4504 {
4505 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4506 /** @todo Same as legacy when !TSE. See below. */
4507 break;
4508 }
4509 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4510 &pThis->StatTxDescTSEData:
4511 &pThis->StatTxDescData);
4512 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4513 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4514
4515 /*
4516 * The last descriptor of non-TSE packet must contain VLE flag.
4517 * TSE packets have VLE flag in the first descriptor. The later
4518 * case is taken care of a bit later when cbVTag gets assigned.
4519 *
4520 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4521 */
4522 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4523 {
4524 pThis->fVTag = pDesc->data.cmd.fVLE;
4525 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4526 }
4527 /*
4528 * First fragment: Allocate new buffer and save the IXSM and TXSM
4529 * packet options as these are only valid in the first fragment.
4530 */
4531 if (pThis->u16TxPktLen == 0)
4532 {
4533 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4534 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4535 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4536 pThis->fIPcsum ? " IP" : "",
4537 pThis->fTCPcsum ? " TCP/UDP" : ""));
4538 if (pDesc->data.cmd.fTSE)
4539 {
4540 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4541 pThis->fVTag = pDesc->data.cmd.fVLE;
4542 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4543 cbVTag = pThis->fVTag ? 4 : 0;
4544 }
4545 else if (pDesc->data.cmd.fEOP)
4546 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4547 else
4548 cbVTag = 4;
4549 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4550 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4551 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4552 true /*fExactSize*/, true /*fGso*/);
4553 else if (pDesc->data.cmd.fTSE)
4554 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4555 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4556 else
4557 rc = e1kXmitAllocBuf(pThis, pDesc->data.cmd.u20DTALEN + cbVTag,
4558 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4559
4560 /**
4561 * @todo: Perhaps it is not that simple for GSO packets! We may
4562 * need to unwind some changes.
4563 */
4564 if (RT_FAILURE(rc))
4565 {
4566 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4567 break;
4568 }
4569 /** @todo Is there any way to indicating errors other than collisions? Like
4570 * VERR_NET_DOWN. */
4571 }
4572
4573 /*
4574 * Add the descriptor data to the frame. If the frame is complete,
4575 * transmit it and reset the u16TxPktLen field.
4576 */
4577 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4578 {
4579 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4580 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4581 if (pDesc->data.cmd.fEOP)
4582 {
4583 if ( fRc
4584 && pThis->CTX_SUFF(pTxSg)
4585 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4586 {
4587 e1kTransmitFrame(pThis, fOnWorkerThread);
4588 E1K_INC_CNT32(TSCTC);
4589 }
4590 else
4591 {
4592 if (fRc)
4593 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4594 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4595 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4596 e1kXmitFreeBuf(pThis);
4597 E1K_INC_CNT32(TSCTFC);
4598 }
4599 pThis->u16TxPktLen = 0;
4600 }
4601 }
4602 else if (!pDesc->data.cmd.fTSE)
4603 {
4604 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4605 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4606 if (pDesc->data.cmd.fEOP)
4607 {
4608 if (fRc && pThis->CTX_SUFF(pTxSg))
4609 {
4610 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4611 if (pThis->fIPcsum)
4612 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4613 pThis->contextNormal.ip.u8CSO,
4614 pThis->contextNormal.ip.u8CSS,
4615 pThis->contextNormal.ip.u16CSE);
4616 if (pThis->fTCPcsum)
4617 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4618 pThis->contextNormal.tu.u8CSO,
4619 pThis->contextNormal.tu.u8CSS,
4620 pThis->contextNormal.tu.u16CSE);
4621 e1kTransmitFrame(pThis, fOnWorkerThread);
4622 }
4623 else
4624 e1kXmitFreeBuf(pThis);
4625 pThis->u16TxPktLen = 0;
4626 }
4627 }
4628 else
4629 {
4630 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4631 e1kFallbackAddToFrame(pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4632 }
4633
4634 e1kDescReport(pThis, pDesc, addr);
4635 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4636 break;
4637 }
4638
4639 case E1K_DTYP_LEGACY:
4640 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4641 {
4642 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4643 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4644 break;
4645 }
4646 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4647 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4648
4649 /* First fragment: allocate new buffer. */
4650 if (pThis->u16TxPktLen == 0)
4651 {
4652 if (pDesc->legacy.cmd.fEOP)
4653 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4654 else
4655 cbVTag = 4;
4656 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4657 /** @todo reset status bits? */
4658 rc = e1kXmitAllocBuf(pThis, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4659 if (RT_FAILURE(rc))
4660 {
4661 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4662 break;
4663 }
4664
4665 /** @todo Is there any way to indicating errors other than collisions? Like
4666 * VERR_NET_DOWN. */
4667 }
4668
4669 /* Add fragment to frame. */
4670 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4671 {
4672 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4673
4674 /* Last fragment: Transmit and reset the packet storage counter. */
4675 if (pDesc->legacy.cmd.fEOP)
4676 {
4677 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4678 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4679 /** @todo Offload processing goes here. */
4680 e1kTransmitFrame(pThis, fOnWorkerThread);
4681 pThis->u16TxPktLen = 0;
4682 }
4683 }
4684 /* Last fragment + failure: free the buffer and reset the storage counter. */
4685 else if (pDesc->legacy.cmd.fEOP)
4686 {
4687 e1kXmitFreeBuf(pThis);
4688 pThis->u16TxPktLen = 0;
4689 }
4690
4691 e1kDescReport(pThis, pDesc, addr);
4692 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4693 break;
4694
4695 default:
4696 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4697 pThis->szPrf, e1kGetDescType(pDesc)));
4698 break;
4699 }
4700
4701 return rc;
4702}
4703
4704#else /* E1K_WITH_TXD_CACHE */
4705
4706/**
4707 * Process Transmit Descriptor.
4708 *
4709 * E1000 supports three types of transmit descriptors:
4710 * - legacy data descriptors of older format (context-less).
4711 * - data the same as legacy but providing new offloading capabilities.
4712 * - context sets up the context for following data descriptors.
4713 *
4714 * @param pThis The device state structure.
4715 * @param pDesc Pointer to descriptor union.
4716 * @param addr Physical address of descriptor in guest memory.
4717 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4718 * @param cbPacketSize Size of the packet as previously computed.
4719 * @thread E1000_TX
4720 */
4721static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC* pDesc, RTGCPHYS addr,
4722 bool fOnWorkerThread)
4723{
4724 int rc = VINF_SUCCESS;
4725
4726 e1kPrintTDesc(pThis, pDesc, "vvv");
4727
4728#ifdef E1K_USE_TX_TIMERS
4729 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4730#endif /* E1K_USE_TX_TIMERS */
4731
4732 switch (e1kGetDescType(pDesc))
4733 {
4734 case E1K_DTYP_CONTEXT:
4735 /* The caller have already updated the context */
4736 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4737 e1kDescReport(pThis, pDesc, addr);
4738 break;
4739
4740 case E1K_DTYP_DATA:
4741 {
4742 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4743 &pThis->StatTxDescTSEData:
4744 &pThis->StatTxDescData);
4745 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4746 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4747 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4748 {
4749 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4750 }
4751 else
4752 {
4753 /*
4754 * Add the descriptor data to the frame. If the frame is complete,
4755 * transmit it and reset the u16TxPktLen field.
4756 */
4757 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4758 {
4759 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4760 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4761 if (pDesc->data.cmd.fEOP)
4762 {
4763 if ( fRc
4764 && pThis->CTX_SUFF(pTxSg)
4765 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4766 {
4767 e1kTransmitFrame(pThis, fOnWorkerThread);
4768 E1K_INC_CNT32(TSCTC);
4769 }
4770 else
4771 {
4772 if (fRc)
4773 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4774 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4775 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4776 e1kXmitFreeBuf(pThis);
4777 E1K_INC_CNT32(TSCTFC);
4778 }
4779 pThis->u16TxPktLen = 0;
4780 }
4781 }
4782 else if (!pDesc->data.cmd.fTSE)
4783 {
4784 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4785 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4786 if (pDesc->data.cmd.fEOP)
4787 {
4788 if (fRc && pThis->CTX_SUFF(pTxSg))
4789 {
4790 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4791 if (pThis->fIPcsum)
4792 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4793 pThis->contextNormal.ip.u8CSO,
4794 pThis->contextNormal.ip.u8CSS,
4795 pThis->contextNormal.ip.u16CSE);
4796 if (pThis->fTCPcsum)
4797 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4798 pThis->contextNormal.tu.u8CSO,
4799 pThis->contextNormal.tu.u8CSS,
4800 pThis->contextNormal.tu.u16CSE);
4801 e1kTransmitFrame(pThis, fOnWorkerThread);
4802 }
4803 else
4804 e1kXmitFreeBuf(pThis);
4805 pThis->u16TxPktLen = 0;
4806 }
4807 }
4808 else
4809 {
4810 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4811 rc = e1kFallbackAddToFrame(pThis, pDesc, fOnWorkerThread);
4812 }
4813 }
4814 e1kDescReport(pThis, pDesc, addr);
4815 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4816 break;
4817 }
4818
4819 case E1K_DTYP_LEGACY:
4820 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4821 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4822 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4823 {
4824 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4825 }
4826 else
4827 {
4828 /* Add fragment to frame. */
4829 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4830 {
4831 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4832
4833 /* Last fragment: Transmit and reset the packet storage counter. */
4834 if (pDesc->legacy.cmd.fEOP)
4835 {
4836 if (pDesc->legacy.cmd.fIC)
4837 {
4838 e1kInsertChecksum(pThis,
4839 (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
4840 pThis->u16TxPktLen,
4841 pDesc->legacy.cmd.u8CSO,
4842 pDesc->legacy.dw3.u8CSS,
4843 0);
4844 }
4845 e1kTransmitFrame(pThis, fOnWorkerThread);
4846 pThis->u16TxPktLen = 0;
4847 }
4848 }
4849 /* Last fragment + failure: free the buffer and reset the storage counter. */
4850 else if (pDesc->legacy.cmd.fEOP)
4851 {
4852 e1kXmitFreeBuf(pThis);
4853 pThis->u16TxPktLen = 0;
4854 }
4855 }
4856 e1kDescReport(pThis, pDesc, addr);
4857 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4858 break;
4859
4860 default:
4861 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4862 pThis->szPrf, e1kGetDescType(pDesc)));
4863 break;
4864 }
4865
4866 return rc;
4867}
4868
4869DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC* pDesc)
4870{
4871 if (pDesc->context.dw2.fTSE)
4872 {
4873 pThis->contextTSE = pDesc->context;
4874 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4875 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4876 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4877 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4878 }
4879 else
4880 {
4881 pThis->contextNormal = pDesc->context;
4882 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4883 }
4884 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4885 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4886 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4887 pDesc->context.ip.u8CSS,
4888 pDesc->context.ip.u8CSO,
4889 pDesc->context.ip.u16CSE,
4890 pDesc->context.tu.u8CSS,
4891 pDesc->context.tu.u8CSO,
4892 pDesc->context.tu.u16CSE));
4893}
4894
4895static bool e1kLocateTxPacket(PE1KSTATE pThis)
4896{
4897 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
4898 pThis->szPrf, pThis->cbTxAlloc));
4899 /* Check if we have located the packet already. */
4900 if (pThis->cbTxAlloc)
4901 {
4902 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
4903 pThis->szPrf, pThis->cbTxAlloc));
4904 return true;
4905 }
4906
4907 bool fTSE = false;
4908 uint32_t cbPacket = 0;
4909
4910 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
4911 {
4912 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
4913 switch (e1kGetDescType(pDesc))
4914 {
4915 case E1K_DTYP_CONTEXT:
4916 e1kUpdateTxContext(pThis, pDesc);
4917 continue;
4918 case E1K_DTYP_LEGACY:
4919 /* Skip empty descriptors. */
4920 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
4921 break;
4922 cbPacket += pDesc->legacy.cmd.u16Length;
4923 pThis->fGSO = false;
4924 break;
4925 case E1K_DTYP_DATA:
4926 /* Skip empty descriptors. */
4927 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
4928 break;
4929 if (cbPacket == 0)
4930 {
4931 /*
4932 * The first fragment: save IXSM and TXSM options
4933 * as these are only valid in the first fragment.
4934 */
4935 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4936 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4937 fTSE = pDesc->data.cmd.fTSE;
4938 /*
4939 * TSE descriptors have VLE bit properly set in
4940 * the first fragment.
4941 */
4942 if (fTSE)
4943 {
4944 pThis->fVTag = pDesc->data.cmd.fVLE;
4945 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4946 }
4947 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
4948 }
4949 cbPacket += pDesc->data.cmd.u20DTALEN;
4950 break;
4951 default:
4952 AssertMsgFailed(("Impossible descriptor type!"));
4953 }
4954 if (pDesc->legacy.cmd.fEOP)
4955 {
4956 /*
4957 * Non-TSE descriptors have VLE bit properly set in
4958 * the last fragment.
4959 */
4960 if (!fTSE)
4961 {
4962 pThis->fVTag = pDesc->data.cmd.fVLE;
4963 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4964 }
4965 /*
4966 * Compute the required buffer size. If we cannot do GSO but still
4967 * have to do segmentation we allocate the first segment only.
4968 */
4969 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
4970 cbPacket :
4971 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
4972 if (pThis->fVTag)
4973 pThis->cbTxAlloc += 4;
4974 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
4975 pThis->szPrf, pThis->cbTxAlloc));
4976 return true;
4977 }
4978 }
4979
4980 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
4981 {
4982 /* All descriptors were empty, we need to process them as a dummy packet */
4983 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
4984 pThis->szPrf, pThis->cbTxAlloc));
4985 return true;
4986 }
4987 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d\n",
4988 pThis->szPrf, pThis->cbTxAlloc));
4989 return false;
4990}
4991
4992static int e1kXmitPacket(PE1KSTATE pThis, bool fOnWorkerThread)
4993{
4994 int rc = VINF_SUCCESS;
4995
4996 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
4997 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
4998
4999 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5000 {
5001 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5002 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5003 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5004 rc = e1kXmitDesc(pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5005 if (RT_FAILURE(rc))
5006 break;
5007 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5008 TDH = 0;
5009 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5010 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5011 {
5012 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5013 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5014 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5015 }
5016 ++pThis->iTxDCurrent;
5017 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5018 break;
5019 }
5020
5021 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5022 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5023 return rc;
5024}
5025
5026#endif /* E1K_WITH_TXD_CACHE */
5027#ifndef E1K_WITH_TXD_CACHE
5028
5029/**
5030 * Transmit pending descriptors.
5031 *
5032 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5033 *
5034 * @param pThis The E1000 state.
5035 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5036 */
5037static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5038{
5039 int rc = VINF_SUCCESS;
5040
5041 /* Check if transmitter is enabled. */
5042 if (!(TCTL & TCTL_EN))
5043 return VINF_SUCCESS;
5044 /*
5045 * Grab the xmit lock of the driver as well as the E1K device state.
5046 */
5047 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5048 if (RT_LIKELY(rc == VINF_SUCCESS))
5049 {
5050 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5051 if (pDrv)
5052 {
5053 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5054 if (RT_FAILURE(rc))
5055 {
5056 e1kCsTxLeave(pThis);
5057 return rc;
5058 }
5059 }
5060 /*
5061 * Process all pending descriptors.
5062 * Note! Do not process descriptors in locked state
5063 */
5064 while (TDH != TDT && !pThis->fLocked)
5065 {
5066 E1KTXDESC desc;
5067 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5068 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5069
5070 e1kLoadDesc(pThis, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5071 rc = e1kXmitDesc(pThis, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5072 /* If we failed to transmit descriptor we will try it again later */
5073 if (RT_FAILURE(rc))
5074 break;
5075 if (++TDH * sizeof(desc) >= TDLEN)
5076 TDH = 0;
5077
5078 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5079 {
5080 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5081 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5082 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5083 }
5084
5085 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5086 }
5087
5088 /// @todo: uncomment: pThis->uStatIntTXQE++;
5089 /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5090 /*
5091 * Release the lock.
5092 */
5093 if (pDrv)
5094 pDrv->pfnEndXmit(pDrv);
5095 e1kCsTxLeave(pThis);
5096 }
5097
5098 return rc;
5099}
5100
5101#else /* E1K_WITH_TXD_CACHE */
5102
5103static void e1kDumpTxDCache(PE1KSTATE pThis)
5104{
5105 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5106 uint32_t tdh = TDH;
5107 LogRel(("-- Transmit Descriptors (%d total) --\n", cDescs));
5108 for (i = 0; i < cDescs; ++i)
5109 {
5110 E1KTXDESC desc;
5111 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
5112 &desc, sizeof(desc));
5113 if (i == tdh)
5114 LogRel((">>> "));
5115 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5116 }
5117 LogRel(("-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5118 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5119 if (tdh > pThis->iTxDCurrent)
5120 tdh -= pThis->iTxDCurrent;
5121 else
5122 tdh = cDescs + tdh - pThis->iTxDCurrent;
5123 for (i = 0; i < pThis->nTxDFetched; ++i)
5124 {
5125 if (i == pThis->iTxDCurrent)
5126 LogRel((">>> "));
5127 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5128 }
5129}
5130
5131/**
5132 * Transmit pending descriptors.
5133 *
5134 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5135 *
5136 * @param pThis The E1000 state.
5137 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5138 */
5139static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5140{
5141 int rc = VINF_SUCCESS;
5142
5143 /* Check if transmitter is enabled. */
5144 if (!(TCTL & TCTL_EN))
5145 return VINF_SUCCESS;
5146 /*
5147 * Grab the xmit lock of the driver as well as the E1K device state.
5148 */
5149 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5150 if (pDrv)
5151 {
5152 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5153 if (RT_FAILURE(rc))
5154 return rc;
5155 }
5156
5157 /*
5158 * Process all pending descriptors.
5159 * Note! Do not process descriptors in locked state
5160 */
5161 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5162 if (RT_LIKELY(rc == VINF_SUCCESS))
5163 {
5164 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5165 /*
5166 * fIncomplete is set whenever we try to fetch additional descriptors
5167 * for an incomplete packet. If fail to locate a complete packet on
5168 * the next iteration we need to reset the cache or we risk to get
5169 * stuck in this loop forever.
5170 */
5171 bool fIncomplete = false;
5172 while (!pThis->fLocked && e1kTxDLazyLoad(pThis))
5173 {
5174 while (e1kLocateTxPacket(pThis))
5175 {
5176 fIncomplete = false;
5177 /* Found a complete packet, allocate it. */
5178 rc = e1kXmitAllocBuf(pThis, pThis->fGSO);
5179 /* If we're out of bandwidth we'll come back later. */
5180 if (RT_FAILURE(rc))
5181 goto out;
5182 /* Copy the packet to allocated buffer and send it. */
5183 rc = e1kXmitPacket(pThis, fOnWorkerThread);
5184 /* If we're out of bandwidth we'll come back later. */
5185 if (RT_FAILURE(rc))
5186 goto out;
5187 }
5188 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5189 if (RT_UNLIKELY(fIncomplete))
5190 {
5191 static bool fTxDCacheDumped = false;
5192 /*
5193 * The descriptor cache is full, but we were unable to find
5194 * a complete packet in it. Drop the cache and hope that
5195 * the guest driver can recover from network card error.
5196 */
5197 LogRel(("%s No complete packets in%s TxD cache! "
5198 "Fetched=%d, current=%d, TX len=%d.\n",
5199 pThis->szPrf,
5200 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5201 pThis->nTxDFetched, pThis->iTxDCurrent,
5202 e1kGetTxLen(pThis)));
5203 if (!fTxDCacheDumped)
5204 {
5205 fTxDCacheDumped = true;
5206 e1kDumpTxDCache(pThis);
5207 }
5208 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5209 /*
5210 * Returning an error at this point means Guru in R0
5211 * (see @bugref{6428}).
5212 */
5213# ifdef IN_RING3
5214 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5215# else /* !IN_RING3 */
5216 rc = VINF_IOM_R3_MMIO_WRITE;
5217# endif /* !IN_RING3 */
5218 goto out;
5219 }
5220 if (u8Remain > 0)
5221 {
5222 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5223 "%d more are available\n",
5224 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5225 e1kGetTxLen(pThis) - u8Remain));
5226
5227 /*
5228 * A packet was partially fetched. Move incomplete packet to
5229 * the beginning of cache buffer, then load more descriptors.
5230 */
5231 memmove(pThis->aTxDescriptors,
5232 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5233 u8Remain * sizeof(E1KTXDESC));
5234 pThis->iTxDCurrent = 0;
5235 pThis->nTxDFetched = u8Remain;
5236 e1kTxDLoadMore(pThis);
5237 fIncomplete = true;
5238 }
5239 else
5240 pThis->nTxDFetched = 0;
5241 pThis->iTxDCurrent = 0;
5242 }
5243 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5244 {
5245 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5246 pThis->szPrf));
5247 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5248 }
5249out:
5250 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5251
5252 /// @todo: uncomment: pThis->uStatIntTXQE++;
5253 /// @todo: uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5254
5255 e1kCsTxLeave(pThis);
5256 }
5257
5258
5259 /*
5260 * Release the lock.
5261 */
5262 if (pDrv)
5263 pDrv->pfnEndXmit(pDrv);
5264 return rc;
5265}
5266
5267#endif /* E1K_WITH_TXD_CACHE */
5268#ifdef IN_RING3
5269
5270/**
5271 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5272 */
5273static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5274{
5275 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
5276 /* Resume suspended transmission */
5277 STATUS &= ~STATUS_TXOFF;
5278 e1kXmitPending(pThis, true /*fOnWorkerThread*/);
5279}
5280
5281/**
5282 * Callback for consuming from transmit queue. It gets called in R3 whenever
5283 * we enqueue something in R0/GC.
5284 *
5285 * @returns true
5286 * @param pDevIns Pointer to device instance structure.
5287 * @param pItem Pointer to the element being dequeued (not used).
5288 * @thread ???
5289 */
5290static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5291{
5292 NOREF(pItem);
5293 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5294 E1kLog2(("%s e1kTxQueueConsumer:\n", pThis->szPrf));
5295
5296 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5297 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
5298
5299 return true;
5300}
5301
5302/**
5303 * Handler for the wakeup signaller queue.
5304 */
5305static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5306{
5307 e1kWakeupReceive(pDevIns);
5308 return true;
5309}
5310
5311#endif /* IN_RING3 */
5312
5313/**
5314 * Write handler for Transmit Descriptor Tail register.
5315 *
5316 * @param pThis The device state structure.
5317 * @param offset Register offset in memory-mapped frame.
5318 * @param index Register index in register array.
5319 * @param value The value to store.
5320 * @param mask Used to implement partial writes (8 and 16-bit).
5321 * @thread EMT
5322 */
5323static int e1kRegWriteTDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5324{
5325 int rc = e1kRegWriteDefault(pThis, offset, index, value);
5326
5327 /* All descriptors starting with head and not including tail belong to us. */
5328 /* Process them. */
5329 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5330 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5331
5332 /* Ignore TDT writes when the link is down. */
5333 if (TDH != TDT && (STATUS & STATUS_LU))
5334 {
5335 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5336 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5337 pThis->szPrf, e1kGetTxLen(pThis)));
5338
5339 /* Transmit pending packets if possible, defer it if we cannot do it
5340 in the current context. */
5341#ifdef E1K_TX_DELAY
5342 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5343 if (RT_LIKELY(rc == VINF_SUCCESS))
5344 {
5345 if (!TMTimerIsActive(pThis->CTX_SUFF(pTXDTimer)))
5346 {
5347#ifdef E1K_INT_STATS
5348 pThis->u64ArmedAt = RTTimeNanoTS();
5349#endif
5350 e1kArmTimer(pThis, pThis->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
5351 }
5352 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5353 e1kCsTxLeave(pThis);
5354 return rc;
5355 }
5356 /* We failed to enter the TX critical section -- transmit as usual. */
5357#endif /* E1K_TX_DELAY */
5358#ifndef IN_RING3
5359 if (!pThis->CTX_SUFF(pDrv))
5360 {
5361 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
5362 if (RT_UNLIKELY(pItem))
5363 PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
5364 }
5365 else
5366#endif
5367 {
5368 rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5369 if (rc == VERR_TRY_AGAIN)
5370 rc = VINF_SUCCESS;
5371 else if (rc == VERR_SEM_BUSY)
5372 rc = VINF_IOM_R3_MMIO_WRITE;
5373 AssertRC(rc);
5374 }
5375 }
5376
5377 return rc;
5378}
5379
5380/**
5381 * Write handler for Multicast Table Array registers.
5382 *
5383 * @param pThis The device state structure.
5384 * @param offset Register offset in memory-mapped frame.
5385 * @param index Register index in register array.
5386 * @param value The value to store.
5387 * @thread EMT
5388 */
5389static int e1kRegWriteMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5390{
5391 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5392 pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])] = value;
5393
5394 return VINF_SUCCESS;
5395}
5396
5397/**
5398 * Read handler for Multicast Table Array registers.
5399 *
5400 * @returns VBox status code.
5401 *
5402 * @param pThis The device state structure.
5403 * @param offset Register offset in memory-mapped frame.
5404 * @param index Register index in register array.
5405 * @thread EMT
5406 */
5407static int e1kRegReadMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5408{
5409 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5410 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5411
5412 return VINF_SUCCESS;
5413}
5414
5415/**
5416 * Write handler for Receive Address registers.
5417 *
5418 * @param pThis The device state structure.
5419 * @param offset Register offset in memory-mapped frame.
5420 * @param index Register index in register array.
5421 * @param value The value to store.
5422 * @thread EMT
5423 */
5424static int e1kRegWriteRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5425{
5426 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5427 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5428
5429 return VINF_SUCCESS;
5430}
5431
5432/**
5433 * Read handler for Receive Address registers.
5434 *
5435 * @returns VBox status code.
5436 *
5437 * @param pThis The device state structure.
5438 * @param offset Register offset in memory-mapped frame.
5439 * @param index Register index in register array.
5440 * @thread EMT
5441 */
5442static int e1kRegReadRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5443{
5444 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5445 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5446
5447 return VINF_SUCCESS;
5448}
5449
5450/**
5451 * Write handler for VLAN Filter Table Array registers.
5452 *
5453 * @param pThis The device state structure.
5454 * @param offset Register offset in memory-mapped frame.
5455 * @param index Register index in register array.
5456 * @param value The value to store.
5457 * @thread EMT
5458 */
5459static int e1kRegWriteVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5460{
5461 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5462 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5463
5464 return VINF_SUCCESS;
5465}
5466
5467/**
5468 * Read handler for VLAN Filter Table Array registers.
5469 *
5470 * @returns VBox status code.
5471 *
5472 * @param pThis The device state structure.
5473 * @param offset Register offset in memory-mapped frame.
5474 * @param index Register index in register array.
5475 * @thread EMT
5476 */
5477static int e1kRegReadVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5478{
5479 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5480 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5481
5482 return VINF_SUCCESS;
5483}
5484
5485/**
5486 * Read handler for unimplemented registers.
5487 *
5488 * Merely reports reads from unimplemented registers.
5489 *
5490 * @returns VBox status code.
5491 *
5492 * @param pThis The device state structure.
5493 * @param offset Register offset in memory-mapped frame.
5494 * @param index Register index in register array.
5495 * @thread EMT
5496 */
5497static int e1kRegReadUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5498{
5499 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5500 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5501 *pu32Value = 0;
5502
5503 return VINF_SUCCESS;
5504}
5505
5506/**
5507 * Default register read handler with automatic clear operation.
5508 *
5509 * Retrieves the value of register from register array in device state structure.
5510 * Then resets all bits.
5511 *
5512 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5513 * done in the caller.
5514 *
5515 * @returns VBox status code.
5516 *
5517 * @param pThis The device state structure.
5518 * @param offset Register offset in memory-mapped frame.
5519 * @param index Register index in register array.
5520 * @thread EMT
5521 */
5522static int e1kRegReadAutoClear(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5523{
5524 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5525 int rc = e1kRegReadDefault(pThis, offset, index, pu32Value);
5526 pThis->auRegs[index] = 0;
5527
5528 return rc;
5529}
5530
5531/**
5532 * Default register read handler.
5533 *
5534 * Retrieves the value of register from register array in device state structure.
5535 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5536 *
5537 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5538 * done in the caller.
5539 *
5540 * @returns VBox status code.
5541 *
5542 * @param pThis The device state structure.
5543 * @param offset Register offset in memory-mapped frame.
5544 * @param index Register index in register array.
5545 * @thread EMT
5546 */
5547static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5548{
5549 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5550 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5551
5552 return VINF_SUCCESS;
5553}
5554
5555/**
5556 * Write handler for unimplemented registers.
5557 *
5558 * Merely reports writes to unimplemented registers.
5559 *
5560 * @param pThis The device state structure.
5561 * @param offset Register offset in memory-mapped frame.
5562 * @param index Register index in register array.
5563 * @param value The value to store.
5564 * @thread EMT
5565 */
5566
5567 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5568{
5569 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5570 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5571
5572 return VINF_SUCCESS;
5573}
5574
5575/**
5576 * Default register write handler.
5577 *
5578 * Stores the value to the register array in device state structure. Only bits
5579 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5580 *
5581 * @returns VBox status code.
5582 *
5583 * @param pThis The device state structure.
5584 * @param offset Register offset in memory-mapped frame.
5585 * @param index Register index in register array.
5586 * @param value The value to store.
5587 * @param mask Used to implement partial writes (8 and 16-bit).
5588 * @thread EMT
5589 */
5590
5591static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5592{
5593 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5594 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5595 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5596
5597 return VINF_SUCCESS;
5598}
5599
5600/**
5601 * Search register table for matching register.
5602 *
5603 * @returns Index in the register table or -1 if not found.
5604 *
5605 * @param pThis The device state structure.
5606 * @param offReg Register offset in memory-mapped region.
5607 * @thread EMT
5608 */
5609static int e1kRegLookup(PE1KSTATE pThis, uint32_t offReg)
5610{
5611#if 0
5612 int index;
5613
5614 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5615 {
5616 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5617 {
5618 return index;
5619 }
5620 }
5621#else
5622 int iStart = 0;
5623 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5624 for (;;)
5625 {
5626 int i = (iEnd - iStart) / 2 + iStart;
5627 uint32_t offCur = g_aE1kRegMap[i].offset;
5628 if (offReg < offCur)
5629 {
5630 if (i == iStart)
5631 break;
5632 iEnd = i;
5633 }
5634 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5635 {
5636 i++;
5637 if (i == iEnd)
5638 break;
5639 iStart = i;
5640 }
5641 else
5642 return i;
5643 Assert(iEnd > iStart);
5644 }
5645
5646 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5647 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5648 return i;
5649
5650# ifdef VBOX_STRICT
5651 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5652 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5653# endif
5654
5655#endif
5656
5657 return -1;
5658}
5659
5660/**
5661 * Handle unaligned register read operation.
5662 *
5663 * Looks up and calls appropriate handler.
5664 *
5665 * @returns VBox status code.
5666 *
5667 * @param pThis The device state structure.
5668 * @param offReg Register offset in memory-mapped frame.
5669 * @param pv Where to store the result.
5670 * @param cb Number of bytes to read.
5671 * @thread EMT
5672 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5673 * accesses we have to take care of that ourselves.
5674 */
5675static int e1kRegReadUnaligned(PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5676{
5677 uint32_t u32 = 0;
5678 uint32_t shift;
5679 int rc = VINF_SUCCESS;
5680 int index = e1kRegLookup(pThis, offReg);
5681#ifdef LOG_ENABLED
5682 char buf[9];
5683#endif
5684
5685 /*
5686 * From the spec:
5687 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
5688 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
5689 */
5690
5691 /*
5692 * To be able to read bytes and short word we convert them to properly
5693 * shifted 32-bit words and masks. The idea is to keep register-specific
5694 * handlers simple. Most accesses will be 32-bit anyway.
5695 */
5696 uint32_t mask;
5697 switch (cb)
5698 {
5699 case 4: mask = 0xFFFFFFFF; break;
5700 case 2: mask = 0x0000FFFF; break;
5701 case 1: mask = 0x000000FF; break;
5702 default:
5703 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5704 "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
5705 }
5706 if (index != -1)
5707 {
5708 if (g_aE1kRegMap[index].readable)
5709 {
5710 /* Make the mask correspond to the bits we are about to read. */
5711 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
5712 mask <<= shift;
5713 if (!mask)
5714 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
5715 /*
5716 * Read it. Pass the mask so the handler knows what has to be read.
5717 * Mask out irrelevant bits.
5718 */
5719 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5720 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5721 return rc;
5722 //pThis->fDelayInts = false;
5723 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5724 //pThis->iStatIntLostOne = 0;
5725 rc = g_aE1kRegMap[index].pfnRead(pThis, offReg & 0xFFFFFFFC, index, &u32);
5726 u32 &= mask;
5727 //e1kCsLeave(pThis);
5728 E1kLog2(("%s At %08X read %s from %s (%s)\n",
5729 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5730 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
5731 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5732 /* Shift back the result. */
5733 u32 >>= shift;
5734 }
5735 else
5736 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
5737 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5738 if (IOM_SUCCESS(rc))
5739 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
5740 }
5741 else
5742 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
5743 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
5744
5745 memcpy(pv, &u32, cb);
5746 return rc;
5747}
5748
5749/**
5750 * Handle 4 byte aligned and sized read operation.
5751 *
5752 * Looks up and calls appropriate handler.
5753 *
5754 * @returns VBox status code.
5755 *
5756 * @param pThis The device state structure.
5757 * @param offReg Register offset in memory-mapped frame.
5758 * @param pu32 Where to store the result.
5759 * @thread EMT
5760 */
5761static int e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
5762{
5763 Assert(!(offReg & 3));
5764
5765 /*
5766 * Lookup the register and check that it's readable.
5767 */
5768 int rc = VINF_SUCCESS;
5769 int idxReg = e1kRegLookup(pThis, offReg);
5770 if (RT_LIKELY(idxReg != -1))
5771 {
5772 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
5773 {
5774 /*
5775 * Read it. Pass the mask so the handler knows what has to be read.
5776 * Mask out irrelevant bits.
5777 */
5778 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5779 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5780 // return rc;
5781 //pThis->fDelayInts = false;
5782 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5783 //pThis->iStatIntLostOne = 0;
5784 rc = g_aE1kRegMap[idxReg].pfnRead(pThis, offReg & 0xFFFFFFFC, idxReg, pu32);
5785 //e1kCsLeave(pThis);
5786 Log6(("%s At %08X read %08X from %s (%s)\n",
5787 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5788 if (IOM_SUCCESS(rc))
5789 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
5790 }
5791 else
5792 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
5793 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5794 }
5795 else
5796 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
5797 return rc;
5798}
5799
5800/**
5801 * Handle 4 byte sized and aligned register write operation.
5802 *
5803 * Looks up and calls appropriate handler.
5804 *
5805 * @returns VBox status code.
5806 *
5807 * @param pThis The device state structure.
5808 * @param offReg Register offset in memory-mapped frame.
5809 * @param u32Value The value to write.
5810 * @thread EMT
5811 */
5812static int e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
5813{
5814 int rc = VINF_SUCCESS;
5815 int index = e1kRegLookup(pThis, offReg);
5816 if (RT_LIKELY(index != -1))
5817 {
5818 if (RT_LIKELY(g_aE1kRegMap[index].writable))
5819 {
5820 /*
5821 * Write it. Pass the mask so the handler knows what has to be written.
5822 * Mask out irrelevant bits.
5823 */
5824 Log6(("%s At %08X write %08X to %s (%s)\n",
5825 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5826 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5827 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5828 // return rc;
5829 //pThis->fDelayInts = false;
5830 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5831 //pThis->iStatIntLostOne = 0;
5832 rc = g_aE1kRegMap[index].pfnWrite(pThis, offReg, index, u32Value);
5833 //e1kCsLeave(pThis);
5834 }
5835 else
5836 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
5837 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5838 if (IOM_SUCCESS(rc))
5839 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
5840 }
5841 else
5842 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
5843 pThis->szPrf, offReg, u32Value));
5844 return rc;
5845}
5846
5847
5848/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
5849
5850/**
5851 * @callback_method_impl{FNIOMMMIOREAD}
5852 */
5853PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
5854{
5855 NOREF(pvUser);
5856 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5857 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5858
5859 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5860 Assert(offReg < E1K_MM_SIZE);
5861 Assert(cb == 4);
5862 Assert(!(GCPhysAddr & 3));
5863
5864 int rc = e1kRegReadAlignedU32(pThis, offReg, (uint32_t *)pv);
5865
5866 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5867 return rc;
5868}
5869
5870/**
5871 * @callback_method_impl{FNIOMMMIOWRITE}
5872 */
5873PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
5874{
5875 NOREF(pvUser);
5876 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5877 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5878
5879 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5880 Assert(offReg < E1K_MM_SIZE);
5881 Assert(cb == 4);
5882 Assert(!(GCPhysAddr & 3));
5883
5884 int rc = e1kRegWriteAlignedU32(pThis, offReg, *(uint32_t const *)pv);
5885
5886 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5887 return rc;
5888}
5889
5890/**
5891 * @callback_method_impl{FNIOMIOPORTIN}
5892 */
5893PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
5894{
5895 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5896 int rc;
5897 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
5898
5899 uPort -= pThis->IOPortBase;
5900 if (RT_LIKELY(cb == 4))
5901 switch (uPort)
5902 {
5903 case 0x00: /* IOADDR */
5904 *pu32 = pThis->uSelectedReg;
5905 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
5906 rc = VINF_SUCCESS;
5907 break;
5908
5909 case 0x04: /* IODATA */
5910 if (!(pThis->uSelectedReg & 3))
5911 rc = e1kRegReadAlignedU32(pThis, pThis->uSelectedReg, pu32);
5912 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
5913 rc = e1kRegReadUnaligned(pThis, pThis->uSelectedReg, pu32, cb);
5914 if (rc == VINF_IOM_R3_MMIO_READ)
5915 rc = VINF_IOM_R3_IOPORT_READ;
5916 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
5917 break;
5918
5919 default:
5920 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, uPort));
5921 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
5922 rc = VINF_SUCCESS;
5923 }
5924 else
5925 {
5926 E1kLog(("%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x", pThis->szPrf, uPort, cb));
5927 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb);
5928 }
5929 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
5930 return rc;
5931}
5932
5933
5934/**
5935 * @callback_method_impl{FNIOMIOPORTOUT}
5936 */
5937PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
5938{
5939 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5940 int rc;
5941 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
5942
5943 E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
5944 if (RT_LIKELY(cb == 4))
5945 {
5946 uPort -= pThis->IOPortBase;
5947 switch (uPort)
5948 {
5949 case 0x00: /* IOADDR */
5950 pThis->uSelectedReg = u32;
5951 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
5952 rc = VINF_SUCCESS;
5953 break;
5954
5955 case 0x04: /* IODATA */
5956 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
5957 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
5958 {
5959 rc = e1kRegWriteAlignedU32(pThis, pThis->uSelectedReg, u32);
5960 if (rc == VINF_IOM_R3_MMIO_WRITE)
5961 rc = VINF_IOM_R3_IOPORT_WRITE;
5962 }
5963 else
5964 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5965 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
5966 break;
5967
5968 default:
5969 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, uPort));
5970 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", uPort);
5971 }
5972 }
5973 else
5974 {
5975 E1kLog(("%s e1kIOPortOut: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb));
5976 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: uPort=%RTiop cb=%#x\n", pThis->szPrf, uPort, cb);
5977 }
5978
5979 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
5980 return rc;
5981}
5982
5983#ifdef IN_RING3
5984
5985/**
5986 * Dump complete device state to log.
5987 *
5988 * @param pThis Pointer to device state.
5989 */
5990static void e1kDumpState(PE1KSTATE pThis)
5991{
5992 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
5993 {
5994 E1kLog2(("%s %8.8s = %08x\n", pThis->szPrf,
5995 g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
5996 }
5997# ifdef E1K_INT_STATS
5998 LogRel(("%s Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
5999 LogRel(("%s Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6000 LogRel(("%s Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6001 LogRel(("%s Interrupts delayed: %d\n", pThis->szPrf, pThis->uStatIntDly));
6002 LogRel(("%s Disabled delayed: %d\n", pThis->szPrf, pThis->uStatDisDly));
6003 LogRel(("%s Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6004 LogRel(("%s Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6005 LogRel(("%s Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6006 LogRel(("%s Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6007 LogRel(("%s Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6008 LogRel(("%s Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6009 LogRel(("%s Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6010 LogRel(("%s Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6011 LogRel(("%s Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6012 LogRel(("%s Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6013 LogRel(("%s Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6014 LogRel(("%s TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6015 LogRel(("%s TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6016 LogRel(("%s TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6017 LogRel(("%s TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6018 LogRel(("%s TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6019 LogRel(("%s TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6020 LogRel(("%s RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6021 LogRel(("%s RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6022 LogRel(("%s TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6023 LogRel(("%s TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6024 LogRel(("%s TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6025 LogRel(("%s Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6026 LogRel(("%s Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6027 LogRel(("%s TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6028 LogRel(("%s TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6029 LogRel(("%s TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6030 LogRel(("%s TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6031 LogRel(("%s TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6032 LogRel(("%s TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6033 LogRel(("%s TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6034 LogRel(("%s TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6035 LogRel(("%s Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6036 LogRel(("%s Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6037# endif /* E1K_INT_STATS */
6038}
6039
6040/**
6041 * @callback_method_impl{FNPCIIOREGIONMAP}
6042 */
6043static DECLCALLBACK(int) e1kMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
6044{
6045 PE1KSTATE pThis = PDMINS_2_DATA(pPciDev->pDevIns, E1KSTATE*);
6046 int rc;
6047
6048 switch (enmType)
6049 {
6050 case PCI_ADDRESS_SPACE_IO:
6051 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
6052 rc = PDMDevHlpIOPortRegister(pPciDev->pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
6053 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
6054 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6055 rc = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
6056 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6057 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6058 rc = PDMDevHlpIOPortRegisterRC(pPciDev->pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
6059 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6060 break;
6061
6062 case PCI_ADDRESS_SPACE_MEM:
6063 /*
6064 * From the spec:
6065 * For registers that should be accessed as 32-bit double words,
6066 * partial writes (less than a 32-bit double word) is ignored.
6067 * Partial reads return all 32 bits of data regardless of the
6068 * byte enables.
6069 */
6070 pThis->addrMMReg = GCPhysAddress; Assert(!(GCPhysAddress & 7));
6071 rc = PDMDevHlpMMIORegister(pPciDev->pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
6072 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
6073 e1kMMIOWrite, e1kMMIORead, "E1000");
6074 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6075 rc = PDMDevHlpMMIORegisterR0(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
6076 "e1kMMIOWrite", "e1kMMIORead");
6077 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6078 rc = PDMDevHlpMMIORegisterRC(pPciDev->pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
6079 "e1kMMIOWrite", "e1kMMIORead");
6080 break;
6081
6082 default:
6083 /* We should never get here */
6084 AssertMsgFailed(("Invalid PCI address space param in map callback"));
6085 rc = VERR_INTERNAL_ERROR;
6086 break;
6087 }
6088 return rc;
6089}
6090
6091
6092/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6093
6094/**
6095 * Check if the device can receive data now.
6096 * This must be called before the pfnRecieve() method is called.
6097 *
6098 * @returns Number of bytes the device can receive.
6099 * @param pInterface Pointer to the interface structure containing the called function pointer.
6100 * @thread EMT
6101 */
6102static int e1kCanReceive(PE1KSTATE pThis)
6103{
6104#ifndef E1K_WITH_RXD_CACHE
6105 size_t cb;
6106
6107 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6108 return VERR_NET_NO_BUFFER_SPACE;
6109
6110 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6111 {
6112 E1KRXDESC desc;
6113 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6114 &desc, sizeof(desc));
6115 if (desc.status.fDD)
6116 cb = 0;
6117 else
6118 cb = pThis->u16RxBSize;
6119 }
6120 else if (RDH < RDT)
6121 cb = (RDT - RDH) * pThis->u16RxBSize;
6122 else if (RDH > RDT)
6123 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6124 else
6125 {
6126 cb = 0;
6127 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6128 }
6129 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6130 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6131
6132 e1kCsRxLeave(pThis);
6133 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6134#else /* E1K_WITH_RXD_CACHE */
6135 int rc = VINF_SUCCESS;
6136
6137 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6138 return VERR_NET_NO_BUFFER_SPACE;
6139
6140 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6141 {
6142 E1KRXDESC desc;
6143 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6144 &desc, sizeof(desc));
6145 if (desc.status.fDD)
6146 rc = VERR_NET_NO_BUFFER_SPACE;
6147 }
6148 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6149 {
6150 /* Cache is empty, so is the RX ring. */
6151 rc = VERR_NET_NO_BUFFER_SPACE;
6152 }
6153 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6154 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6155 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6156
6157 e1kCsRxLeave(pThis);
6158 return rc;
6159#endif /* E1K_WITH_RXD_CACHE */
6160}
6161
6162/**
6163 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6164 */
6165static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6166{
6167 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6168 int rc = e1kCanReceive(pThis);
6169
6170 if (RT_SUCCESS(rc))
6171 return VINF_SUCCESS;
6172 if (RT_UNLIKELY(cMillies == 0))
6173 return VERR_NET_NO_BUFFER_SPACE;
6174
6175 rc = VERR_INTERRUPTED;
6176 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6177 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6178 VMSTATE enmVMState;
6179 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
6180 || enmVMState == VMSTATE_RUNNING_LS))
6181 {
6182 int rc2 = e1kCanReceive(pThis);
6183 if (RT_SUCCESS(rc2))
6184 {
6185 rc = VINF_SUCCESS;
6186 break;
6187 }
6188 E1kLogRel(("E1000 e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6189 E1kLog(("%s e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6190 RTSemEventWait(pThis->hEventMoreRxDescAvail, cMillies);
6191 }
6192 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6193 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6194
6195 return rc;
6196}
6197
6198
6199/**
6200 * Matches the packet addresses against Receive Address table. Looks for
6201 * exact matches only.
6202 *
6203 * @returns true if address matches.
6204 * @param pThis Pointer to the state structure.
6205 * @param pvBuf The ethernet packet.
6206 * @param cb Number of bytes available in the packet.
6207 * @thread EMT
6208 */
6209static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6210{
6211 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6212 {
6213 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6214
6215 /* Valid address? */
6216 if (ra->ctl & RA_CTL_AV)
6217 {
6218 Assert((ra->ctl & RA_CTL_AS) < 2);
6219 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6220 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6221 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6222 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6223 /*
6224 * Address Select:
6225 * 00b = Destination address
6226 * 01b = Source address
6227 * 10b = Reserved
6228 * 11b = Reserved
6229 * Since ethernet header is (DA, SA, len) we can use address
6230 * select as index.
6231 */
6232 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6233 ra->addr, sizeof(ra->addr)) == 0)
6234 return true;
6235 }
6236 }
6237
6238 return false;
6239}
6240
6241/**
6242 * Matches the packet addresses against Multicast Table Array.
6243 *
6244 * @remarks This is imperfect match since it matches not exact address but
6245 * a subset of addresses.
6246 *
6247 * @returns true if address matches.
6248 * @param pThis Pointer to the state structure.
6249 * @param pvBuf The ethernet packet.
6250 * @param cb Number of bytes available in the packet.
6251 * @thread EMT
6252 */
6253static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6254{
6255 /* Get bits 32..47 of destination address */
6256 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6257
6258 unsigned offset = GET_BITS(RCTL, MO);
6259 /*
6260 * offset means:
6261 * 00b = bits 36..47
6262 * 01b = bits 35..46
6263 * 10b = bits 34..45
6264 * 11b = bits 32..43
6265 */
6266 if (offset < 3)
6267 u16Bit = u16Bit >> (4 - offset);
6268 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6269}
6270
6271/**
6272 * Determines if the packet is to be delivered to upper layer.
6273 *
6274 * The following filters supported:
6275 * - Exact Unicast/Multicast
6276 * - Promiscuous Unicast/Multicast
6277 * - Multicast
6278 * - VLAN
6279 *
6280 * @returns true if packet is intended for this node.
6281 * @param pThis Pointer to the state structure.
6282 * @param pvBuf The ethernet packet.
6283 * @param cb Number of bytes available in the packet.
6284 * @param pStatus Bit field to store status bits.
6285 * @thread EMT
6286 */
6287static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6288{
6289 Assert(cb > 14);
6290 /* Assume that we fail to pass exact filter. */
6291 pStatus->fPIF = false;
6292 pStatus->fVP = false;
6293 /* Discard oversized packets */
6294 if (cb > E1K_MAX_RX_PKT_SIZE)
6295 {
6296 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6297 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6298 E1K_INC_CNT32(ROC);
6299 return false;
6300 }
6301 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6302 {
6303 /* When long packet reception is disabled packets over 1522 are discarded */
6304 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6305 pThis->szPrf, cb));
6306 E1K_INC_CNT32(ROC);
6307 return false;
6308 }
6309
6310 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6311 /* Compare TPID with VLAN Ether Type */
6312 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6313 {
6314 pStatus->fVP = true;
6315 /* Is VLAN filtering enabled? */
6316 if (RCTL & RCTL_VFE)
6317 {
6318 /* It is 802.1q packet indeed, let's filter by VID */
6319 if (RCTL & RCTL_CFIEN)
6320 {
6321 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6322 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6323 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6324 !!(RCTL & RCTL_CFI)));
6325 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6326 {
6327 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6328 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6329 return false;
6330 }
6331 }
6332 else
6333 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6334 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6335 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6336 {
6337 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6338 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6339 return false;
6340 }
6341 }
6342 }
6343 /* Broadcast filtering */
6344 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6345 return true;
6346 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6347 if (e1kIsMulticast(pvBuf))
6348 {
6349 /* Is multicast promiscuous enabled? */
6350 if (RCTL & RCTL_MPE)
6351 return true;
6352 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6353 /* Try perfect matches first */
6354 if (e1kPerfectMatch(pThis, pvBuf))
6355 {
6356 pStatus->fPIF = true;
6357 return true;
6358 }
6359 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6360 if (e1kImperfectMatch(pThis, pvBuf))
6361 return true;
6362 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6363 }
6364 else {
6365 /* Is unicast promiscuous enabled? */
6366 if (RCTL & RCTL_UPE)
6367 return true;
6368 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6369 if (e1kPerfectMatch(pThis, pvBuf))
6370 {
6371 pStatus->fPIF = true;
6372 return true;
6373 }
6374 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6375 }
6376 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6377 return false;
6378}
6379
6380/**
6381 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6382 */
6383static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6384{
6385 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6386 int rc = VINF_SUCCESS;
6387
6388 /*
6389 * Drop packets if the VM is not running yet/anymore.
6390 */
6391 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pThis));
6392 if ( enmVMState != VMSTATE_RUNNING
6393 && enmVMState != VMSTATE_RUNNING_LS)
6394 {
6395 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6396 return VINF_SUCCESS;
6397 }
6398
6399 /* Discard incoming packets in locked state */
6400 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6401 {
6402 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6403 return VINF_SUCCESS;
6404 }
6405
6406 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6407
6408 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6409 // return VERR_PERMISSION_DENIED;
6410
6411 e1kPacketDump(pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6412
6413 /* Update stats */
6414 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6415 {
6416 E1K_INC_CNT32(TPR);
6417 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6418 e1kCsLeave(pThis);
6419 }
6420 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6421 E1KRXDST status;
6422 RT_ZERO(status);
6423 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6424 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6425 if (fPassed)
6426 {
6427 rc = e1kHandleRxPacket(pThis, pvBuf, cb, status);
6428 }
6429 //e1kCsLeave(pThis);
6430 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6431
6432 return rc;
6433}
6434
6435
6436/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6437
6438/**
6439 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6440 */
6441static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6442{
6443 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
6444 int rc = VERR_PDM_LUN_NOT_FOUND;
6445
6446 if (iLUN == 0)
6447 {
6448 *ppLed = &pThis->led;
6449 rc = VINF_SUCCESS;
6450 }
6451 return rc;
6452}
6453
6454
6455/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6456
6457/**
6458 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6459 */
6460static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6461{
6462 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6463 pThis->eeprom.getMac(pMac);
6464 return VINF_SUCCESS;
6465}
6466
6467/**
6468 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6469 */
6470static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6471{
6472 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6473 if (STATUS & STATUS_LU)
6474 return PDMNETWORKLINKSTATE_UP;
6475 return PDMNETWORKLINKSTATE_DOWN;
6476}
6477
6478/**
6479 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6480 */
6481static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6482{
6483 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6484
6485 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6486 switch (enmState)
6487 {
6488 case PDMNETWORKLINKSTATE_UP:
6489 pThis->fCableConnected = true;
6490 /* If link was down, bring it up after a while. */
6491 if (!(STATUS & STATUS_LU))
6492 e1kBringLinkUpDelayed(pThis);
6493 break;
6494 case PDMNETWORKLINKSTATE_DOWN:
6495 pThis->fCableConnected = false;
6496 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6497 * We might have to set the link state before the driver initializes us. */
6498 Phy::setLinkStatus(&pThis->phy, false);
6499 /* If link was up, bring it down. */
6500 if (STATUS & STATUS_LU)
6501 e1kR3LinkDown(pThis);
6502 break;
6503 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6504 /*
6505 * There is not much sense in bringing down the link if it has not come up yet.
6506 * If it is up though, we bring it down temporarely, then bring it up again.
6507 */
6508 if (STATUS & STATUS_LU)
6509 e1kR3LinkDownTemp(pThis);
6510 break;
6511 default:
6512 ;
6513 }
6514 return VINF_SUCCESS;
6515}
6516
6517
6518/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6519
6520/**
6521 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6522 */
6523static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6524{
6525 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
6526 Assert(&pThis->IBase == pInterface);
6527
6528 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
6529 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
6530 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
6531 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
6532 return NULL;
6533}
6534
6535
6536/* -=-=-=-=- Saved State -=-=-=-=- */
6537
6538/**
6539 * Saves the configuration.
6540 *
6541 * @param pThis The E1K state.
6542 * @param pSSM The handle to the saved state.
6543 */
6544static void e1kSaveConfig(PE1KSTATE pThis, PSSMHANDLE pSSM)
6545{
6546 SSMR3PutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6547 SSMR3PutU32(pSSM, pThis->eChip);
6548}
6549
6550/**
6551 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6552 */
6553static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6554{
6555 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6556 e1kSaveConfig(pThis, pSSM);
6557 return VINF_SSM_DONT_CALL_AGAIN;
6558}
6559
6560/**
6561 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6562 */
6563static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6564{
6565 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6566
6567 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6568 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6569 return rc;
6570 e1kCsLeave(pThis);
6571 return VINF_SUCCESS;
6572#if 0
6573 /* 1) Prevent all threads from modifying the state and memory */
6574 //pThis->fLocked = true;
6575 /* 2) Cancel all timers */
6576#ifdef E1K_TX_DELAY
6577 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6578#endif /* E1K_TX_DELAY */
6579#ifdef E1K_USE_TX_TIMERS
6580 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6581#ifndef E1K_NO_TAD
6582 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6583#endif /* E1K_NO_TAD */
6584#endif /* E1K_USE_TX_TIMERS */
6585#ifdef E1K_USE_RX_TIMERS
6586 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6587 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6588#endif /* E1K_USE_RX_TIMERS */
6589 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6590 /* 3) Did I forget anything? */
6591 E1kLog(("%s Locked\n", pThis->szPrf));
6592 return VINF_SUCCESS;
6593#endif
6594}
6595
6596/**
6597 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6598 */
6599static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6600{
6601 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6602
6603 e1kSaveConfig(pThis, pSSM);
6604 pThis->eeprom.save(pSSM);
6605 e1kDumpState(pThis);
6606 SSMR3PutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6607 SSMR3PutBool(pSSM, pThis->fIntRaised);
6608 Phy::saveState(pSSM, &pThis->phy);
6609 SSMR3PutU32(pSSM, pThis->uSelectedReg);
6610 SSMR3PutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6611 SSMR3PutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6612 SSMR3PutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6613 SSMR3PutU64(pSSM, pThis->u64AckedAt);
6614 SSMR3PutU16(pSSM, pThis->u16RxBSize);
6615 //SSMR3PutBool(pSSM, pThis->fDelayInts);
6616 //SSMR3PutBool(pSSM, pThis->fIntMaskUsed);
6617 SSMR3PutU16(pSSM, pThis->u16TxPktLen);
6618/** @todo State wrt to the TSE buffer is incomplete, so little point in
6619 * saving this actually. */
6620 SSMR3PutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6621 SSMR3PutBool(pSSM, pThis->fIPcsum);
6622 SSMR3PutBool(pSSM, pThis->fTCPcsum);
6623 SSMR3PutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6624 SSMR3PutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6625 SSMR3PutBool(pSSM, pThis->fVTag);
6626 SSMR3PutU16(pSSM, pThis->u16VTagTCI);
6627#ifdef E1K_WITH_TXD_CACHE
6628#if 0
6629 SSMR3PutU8(pSSM, pThis->nTxDFetched);
6630 SSMR3PutMem(pSSM, pThis->aTxDescriptors,
6631 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6632#else
6633 /*
6634 * There is no point in storing TX descriptor cache entries as we can simply
6635 * fetch them again. Moreover, normally the cache is always empty when we
6636 * save the state. Store zero entries for compatibility.
6637 */
6638 SSMR3PutU8(pSSM, 0);
6639#endif
6640#endif /* E1K_WITH_TXD_CACHE */
6641/**@todo GSO requires some more state here. */
6642 E1kLog(("%s State has been saved\n", pThis->szPrf));
6643 return VINF_SUCCESS;
6644}
6645
6646#if 0
6647/**
6648 * @callback_method_impl{FNSSMDEVSAVEDONE}
6649 */
6650static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6651{
6652 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6653
6654 /* If VM is being powered off unlocking will result in assertions in PGM */
6655 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6656 pThis->fLocked = false;
6657 else
6658 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6659 E1kLog(("%s Unlocked\n", pThis->szPrf));
6660 return VINF_SUCCESS;
6661}
6662#endif
6663
6664/**
6665 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6666 */
6667static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6668{
6669 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6670
6671 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6672 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6673 return rc;
6674 e1kCsLeave(pThis);
6675 return VINF_SUCCESS;
6676}
6677
6678/**
6679 * @callback_method_impl{FNSSMDEVLOADEXEC}
6680 */
6681static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6682{
6683 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6684 int rc;
6685
6686 if ( uVersion != E1K_SAVEDSTATE_VERSION
6687#ifdef E1K_WITH_TXD_CACHE
6688 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6689#endif /* E1K_WITH_TXD_CACHE */
6690 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6691 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6692 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6693
6694 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6695 || uPass != SSM_PASS_FINAL)
6696 {
6697 /* config checks */
6698 RTMAC macConfigured;
6699 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
6700 AssertRCReturn(rc, rc);
6701 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6702 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6703 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6704
6705 E1KCHIP eChip;
6706 rc = SSMR3GetU32(pSSM, &eChip);
6707 AssertRCReturn(rc, rc);
6708 if (eChip != pThis->eChip)
6709 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6710 }
6711
6712 if (uPass == SSM_PASS_FINAL)
6713 {
6714 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6715 {
6716 rc = pThis->eeprom.load(pSSM);
6717 AssertRCReturn(rc, rc);
6718 }
6719 /* the state */
6720 SSMR3GetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
6721 SSMR3GetBool(pSSM, &pThis->fIntRaised);
6722 /** @todo: PHY could be made a separate device with its own versioning */
6723 Phy::loadState(pSSM, &pThis->phy);
6724 SSMR3GetU32(pSSM, &pThis->uSelectedReg);
6725 SSMR3GetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
6726 SSMR3GetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6727 SSMR3GetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
6728 SSMR3GetU64(pSSM, &pThis->u64AckedAt);
6729 SSMR3GetU16(pSSM, &pThis->u16RxBSize);
6730 //SSMR3GetBool(pSSM, pThis->fDelayInts);
6731 //SSMR3GetBool(pSSM, pThis->fIntMaskUsed);
6732 SSMR3GetU16(pSSM, &pThis->u16TxPktLen);
6733 SSMR3GetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
6734 SSMR3GetBool(pSSM, &pThis->fIPcsum);
6735 SSMR3GetBool(pSSM, &pThis->fTCPcsum);
6736 SSMR3GetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6737 rc = SSMR3GetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6738 AssertRCReturn(rc, rc);
6739 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
6740 {
6741 SSMR3GetBool(pSSM, &pThis->fVTag);
6742 rc = SSMR3GetU16(pSSM, &pThis->u16VTagTCI);
6743 AssertRCReturn(rc, rc);
6744 }
6745 else
6746 {
6747 pThis->fVTag = false;
6748 pThis->u16VTagTCI = 0;
6749 }
6750#ifdef E1K_WITH_TXD_CACHE
6751 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
6752 {
6753 rc = SSMR3GetU8(pSSM, &pThis->nTxDFetched);
6754 AssertRCReturn(rc, rc);
6755 if (pThis->nTxDFetched)
6756 SSMR3GetMem(pSSM, pThis->aTxDescriptors,
6757 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6758 }
6759 else
6760 pThis->nTxDFetched = 0;
6761 /*
6762 * @todo: Perhaps we should not store TXD cache as the entries can be
6763 * simply fetched again from guest's memory. Or can't they?
6764 */
6765#endif /* E1K_WITH_TXD_CACHE */
6766#ifdef E1K_WITH_RXD_CACHE
6767 /*
6768 * There is no point in storing the RX descriptor cache in the saved
6769 * state, we just need to make sure it is empty.
6770 */
6771 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
6772#endif /* E1K_WITH_RXD_CACHE */
6773 /* derived state */
6774 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
6775
6776 E1kLog(("%s State has been restored\n", pThis->szPrf));
6777 e1kDumpState(pThis);
6778 }
6779 return VINF_SUCCESS;
6780}
6781
6782/**
6783 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
6784 */
6785static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6786{
6787 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6788
6789 /* Update promiscuous mode */
6790 if (pThis->pDrvR3)
6791 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3,
6792 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
6793
6794 /*
6795 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
6796 * passed to us. We go through all this stuff if the link was up and we
6797 * wasn't teleported.
6798 */
6799 if ( (STATUS & STATUS_LU)
6800 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
6801 && pThis->cMsLinkUpDelay)
6802 {
6803 e1kR3LinkDownTemp(pThis);
6804 }
6805 return VINF_SUCCESS;
6806}
6807
6808
6809
6810/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
6811
6812/**
6813 * @callback_method_impl{FNRTSTRFORMATTYPE}
6814 */
6815static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
6816 void *pvArgOutput,
6817 const char *pszType,
6818 void const *pvValue,
6819 int cchWidth,
6820 int cchPrecision,
6821 unsigned fFlags,
6822 void *pvUser)
6823{
6824 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
6825 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
6826 if (!pDesc)
6827 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
6828
6829 size_t cbPrintf = 0;
6830 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
6831 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
6832 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
6833 pDesc->status.fPIF ? "PIF" : "pif",
6834 pDesc->status.fIPCS ? "IPCS" : "ipcs",
6835 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
6836 pDesc->status.fVP ? "VP" : "vp",
6837 pDesc->status.fIXSM ? "IXSM" : "ixsm",
6838 pDesc->status.fEOP ? "EOP" : "eop",
6839 pDesc->status.fDD ? "DD" : "dd",
6840 pDesc->status.fRXE ? "RXE" : "rxe",
6841 pDesc->status.fIPE ? "IPE" : "ipe",
6842 pDesc->status.fTCPE ? "TCPE" : "tcpe",
6843 pDesc->status.fCE ? "CE" : "ce",
6844 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
6845 E1K_SPEC_VLAN(pDesc->status.u16Special),
6846 E1K_SPEC_PRI(pDesc->status.u16Special));
6847 return cbPrintf;
6848}
6849
6850/**
6851 * @callback_method_impl{FNRTSTRFORMATTYPE}
6852 */
6853static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
6854 void *pvArgOutput,
6855 const char *pszType,
6856 void const *pvValue,
6857 int cchWidth,
6858 int cchPrecision,
6859 unsigned fFlags,
6860 void *pvUser)
6861{
6862 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
6863 E1KTXDESC* pDesc = (E1KTXDESC*)pvValue;
6864 if (!pDesc)
6865 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
6866
6867 size_t cbPrintf = 0;
6868 switch (e1kGetDescType(pDesc))
6869 {
6870 case E1K_DTYP_CONTEXT:
6871 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
6872 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
6873 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
6874 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
6875 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
6876 pDesc->context.dw2.fIDE ? " IDE":"",
6877 pDesc->context.dw2.fRS ? " RS" :"",
6878 pDesc->context.dw2.fTSE ? " TSE":"",
6879 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
6880 pDesc->context.dw2.fTCP ? "TCP":"UDP",
6881 pDesc->context.dw2.u20PAYLEN,
6882 pDesc->context.dw3.u8HDRLEN,
6883 pDesc->context.dw3.u16MSS,
6884 pDesc->context.dw3.fDD?"DD":"");
6885 break;
6886 case E1K_DTYP_DATA:
6887 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
6888 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
6889 pDesc->data.u64BufAddr,
6890 pDesc->data.cmd.u20DTALEN,
6891 pDesc->data.cmd.fIDE ? " IDE" :"",
6892 pDesc->data.cmd.fVLE ? " VLE" :"",
6893 pDesc->data.cmd.fRPS ? " RPS" :"",
6894 pDesc->data.cmd.fRS ? " RS" :"",
6895 pDesc->data.cmd.fTSE ? " TSE" :"",
6896 pDesc->data.cmd.fIFCS? " IFCS":"",
6897 pDesc->data.cmd.fEOP ? " EOP" :"",
6898 pDesc->data.dw3.fDD ? " DD" :"",
6899 pDesc->data.dw3.fEC ? " EC" :"",
6900 pDesc->data.dw3.fLC ? " LC" :"",
6901 pDesc->data.dw3.fTXSM? " TXSM":"",
6902 pDesc->data.dw3.fIXSM? " IXSM":"",
6903 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
6904 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
6905 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
6906 break;
6907 case E1K_DTYP_LEGACY:
6908 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
6909 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
6910 pDesc->data.u64BufAddr,
6911 pDesc->legacy.cmd.u16Length,
6912 pDesc->legacy.cmd.fIDE ? " IDE" :"",
6913 pDesc->legacy.cmd.fVLE ? " VLE" :"",
6914 pDesc->legacy.cmd.fRPS ? " RPS" :"",
6915 pDesc->legacy.cmd.fRS ? " RS" :"",
6916 pDesc->legacy.cmd.fIC ? " IC" :"",
6917 pDesc->legacy.cmd.fIFCS? " IFCS":"",
6918 pDesc->legacy.cmd.fEOP ? " EOP" :"",
6919 pDesc->legacy.dw3.fDD ? " DD" :"",
6920 pDesc->legacy.dw3.fEC ? " EC" :"",
6921 pDesc->legacy.dw3.fLC ? " LC" :"",
6922 pDesc->legacy.cmd.u8CSO,
6923 pDesc->legacy.dw3.u8CSS,
6924 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
6925 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
6926 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
6927 break;
6928 default:
6929 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
6930 break;
6931 }
6932
6933 return cbPrintf;
6934}
6935
6936/** Initializes debug helpers (logging format types). */
6937static int e1kInitDebugHelpers(void)
6938{
6939 int rc = VINF_SUCCESS;
6940 static bool s_fHelpersRegistered = false;
6941 if (!s_fHelpersRegistered)
6942 {
6943 s_fHelpersRegistered = true;
6944 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
6945 AssertRCReturn(rc, rc);
6946 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
6947 AssertRCReturn(rc, rc);
6948 }
6949 return rc;
6950}
6951
6952/**
6953 * Status info callback.
6954 *
6955 * @param pDevIns The device instance.
6956 * @param pHlp The output helpers.
6957 * @param pszArgs The arguments.
6958 */
6959static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6960{
6961 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6962 unsigned i;
6963 // bool fRcvRing = false;
6964 // bool fXmtRing = false;
6965
6966 /*
6967 * Parse args.
6968 if (pszArgs)
6969 {
6970 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
6971 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
6972 }
6973 */
6974
6975 /*
6976 * Show info.
6977 */
6978 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
6979 pDevIns->iInstance, pThis->IOPortBase, pThis->addrMMReg,
6980 &pThis->macConfigured, g_Chips[pThis->eChip].pcszName,
6981 pThis->fRCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
6982
6983 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
6984
6985 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6986 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
6987
6988 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6989 {
6990 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6991 if (ra->ctl & RA_CTL_AV)
6992 {
6993 const char *pcszTmp;
6994 switch (ra->ctl & RA_CTL_AS)
6995 {
6996 case 0: pcszTmp = "DST"; break;
6997 case 1: pcszTmp = "SRC"; break;
6998 default: pcszTmp = "reserved";
6999 }
7000 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7001 }
7002 }
7003 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7004 uint32_t rdh = RDH;
7005 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7006 for (i = 0; i < cDescs; ++i)
7007 {
7008 E1KRXDESC desc;
7009 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7010 &desc, sizeof(desc));
7011 if (i == rdh)
7012 pHlp->pfnPrintf(pHlp, ">>> ");
7013 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7014 }
7015#ifdef E1K_WITH_RXD_CACHE
7016 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7017 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7018 if (rdh > pThis->iRxDCurrent)
7019 rdh -= pThis->iRxDCurrent;
7020 else
7021 rdh = cDescs + rdh - pThis->iRxDCurrent;
7022 for (i = 0; i < pThis->nRxDFetched; ++i)
7023 {
7024 if (i == pThis->iRxDCurrent)
7025 pHlp->pfnPrintf(pHlp, ">>> ");
7026 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7027 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7028 &pThis->aRxDescriptors[i]);
7029 }
7030#endif /* E1K_WITH_RXD_CACHE */
7031
7032 cDescs = TDLEN / sizeof(E1KTXDESC);
7033 uint32_t tdh = TDH;
7034 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7035 for (i = 0; i < cDescs; ++i)
7036 {
7037 E1KTXDESC desc;
7038 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7039 &desc, sizeof(desc));
7040 if (i == tdh)
7041 pHlp->pfnPrintf(pHlp, ">>> ");
7042 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7043 }
7044#ifdef E1K_WITH_TXD_CACHE
7045 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7046 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7047 if (tdh > pThis->iTxDCurrent)
7048 tdh -= pThis->iTxDCurrent;
7049 else
7050 tdh = cDescs + tdh - pThis->iTxDCurrent;
7051 for (i = 0; i < pThis->nTxDFetched; ++i)
7052 {
7053 if (i == pThis->iTxDCurrent)
7054 pHlp->pfnPrintf(pHlp, ">>> ");
7055 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7056 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7057 &pThis->aTxDescriptors[i]);
7058 }
7059#endif /* E1K_WITH_TXD_CACHE */
7060
7061
7062#ifdef E1K_INT_STATS
7063 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7064 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7065 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7066 pHlp->pfnPrintf(pHlp, "Interrupts delayed: %d\n", pThis->uStatIntDly);
7067 pHlp->pfnPrintf(pHlp, "Disabled delayed: %d\n", pThis->uStatDisDly);
7068 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7069 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7070 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7071 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7072 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7073 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7074 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7075 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7076 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7077 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7078 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7079 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7080 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7081 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7082 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7083 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7084 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7085 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7086 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7087 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7088 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7089 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7090 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7091 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7092 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7093 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7094 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7095 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7096 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7097 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7098 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7099 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7100 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7101#endif /* E1K_INT_STATS */
7102
7103 e1kCsLeave(pThis);
7104}
7105
7106
7107
7108/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7109
7110/**
7111 * Detach notification.
7112 *
7113 * One port on the network card has been disconnected from the network.
7114 *
7115 * @param pDevIns The device instance.
7116 * @param iLUN The logical unit which is being detached.
7117 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7118 */
7119static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7120{
7121 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7122 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7123
7124 AssertLogRelReturnVoid(iLUN == 0);
7125
7126 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7127
7128 /** @todo: r=pritesh still need to check if i missed
7129 * to clean something in this function
7130 */
7131
7132 /*
7133 * Zero some important members.
7134 */
7135 pThis->pDrvBase = NULL;
7136 pThis->pDrvR3 = NULL;
7137 pThis->pDrvR0 = NIL_RTR0PTR;
7138 pThis->pDrvRC = NIL_RTRCPTR;
7139
7140 PDMCritSectLeave(&pThis->cs);
7141}
7142
7143/**
7144 * Attach the Network attachment.
7145 *
7146 * One port on the network card has been connected to a network.
7147 *
7148 * @returns VBox status code.
7149 * @param pDevIns The device instance.
7150 * @param iLUN The logical unit which is being attached.
7151 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7152 *
7153 * @remarks This code path is not used during construction.
7154 */
7155static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7156{
7157 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7158 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7159
7160 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7161
7162 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7163
7164 /*
7165 * Attach the driver.
7166 */
7167 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7168 if (RT_SUCCESS(rc))
7169 {
7170 if (rc == VINF_NAT_DNS)
7171 {
7172#ifdef RT_OS_LINUX
7173 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7174 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7175#else
7176 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7177 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7178#endif
7179 }
7180 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7181 AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7182 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7183 if (RT_SUCCESS(rc))
7184 {
7185 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0);
7186 pThis->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7187
7188 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC);
7189 pThis->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7190 }
7191 }
7192 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7193 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7194 {
7195 /* This should never happen because this function is not called
7196 * if there is no driver to attach! */
7197 Log(("%s No attached driver!\n", pThis->szPrf));
7198 }
7199
7200 /*
7201 * Temporary set the link down if it was up so that the guest
7202 * will know that we have change the configuration of the
7203 * network card
7204 */
7205 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7206 e1kR3LinkDownTemp(pThis);
7207
7208 PDMCritSectLeave(&pThis->cs);
7209 return rc;
7210
7211}
7212
7213/**
7214 * @copydoc FNPDMDEVPOWEROFF
7215 */
7216static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7217{
7218 /* Poke thread waiting for buffer space. */
7219 e1kWakeupReceive(pDevIns);
7220}
7221
7222/**
7223 * @copydoc FNPDMDEVRESET
7224 */
7225static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7226{
7227 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7228#ifdef E1K_TX_DELAY
7229 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7230#endif /* E1K_TX_DELAY */
7231 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7232 e1kCancelTimer(pThis, pThis->CTX_SUFF(pLUTimer));
7233 e1kXmitFreeBuf(pThis);
7234 pThis->u16TxPktLen = 0;
7235 pThis->fIPcsum = false;
7236 pThis->fTCPcsum = false;
7237 pThis->fIntMaskUsed = false;
7238 pThis->fDelayInts = false;
7239 pThis->fLocked = false;
7240 pThis->u64AckedAt = 0;
7241 e1kHardReset(pThis);
7242}
7243
7244/**
7245 * @copydoc FNPDMDEVSUSPEND
7246 */
7247static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7248{
7249 /* Poke thread waiting for buffer space. */
7250 e1kWakeupReceive(pDevIns);
7251}
7252
7253/**
7254 * Device relocation callback.
7255 *
7256 * When this callback is called the device instance data, and if the
7257 * device have a GC component, is being relocated, or/and the selectors
7258 * have been changed. The device must use the chance to perform the
7259 * necessary pointer relocations and data updates.
7260 *
7261 * Before the GC code is executed the first time, this function will be
7262 * called with a 0 delta so GC pointer calculations can be one in one place.
7263 *
7264 * @param pDevIns Pointer to the device instance.
7265 * @param offDelta The relocation delta relative to the old location.
7266 *
7267 * @remark A relocation CANNOT fail.
7268 */
7269static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7270{
7271 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7272 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7273 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7274 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7275#ifdef E1K_USE_RX_TIMERS
7276 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7277 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7278#endif /* E1K_USE_RX_TIMERS */
7279#ifdef E1K_USE_TX_TIMERS
7280 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7281# ifndef E1K_NO_TAD
7282 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7283# endif /* E1K_NO_TAD */
7284#endif /* E1K_USE_TX_TIMERS */
7285#ifdef E1K_TX_DELAY
7286 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7287#endif /* E1K_TX_DELAY */
7288 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7289 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7290}
7291
7292/**
7293 * Destruct a device instance.
7294 *
7295 * We need to free non-VM resources only.
7296 *
7297 * @returns VBox status code.
7298 * @param pDevIns The device instance data.
7299 * @thread EMT
7300 */
7301static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7302{
7303 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7304 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7305
7306 e1kDumpState(pThis);
7307 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7308 if (PDMCritSectIsInitialized(&pThis->cs))
7309 {
7310 if (pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
7311 {
7312 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
7313 RTSemEventDestroy(pThis->hEventMoreRxDescAvail);
7314 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7315 }
7316#ifdef E1K_WITH_TX_CS
7317 PDMR3CritSectDelete(&pThis->csTx);
7318#endif /* E1K_WITH_TX_CS */
7319 PDMR3CritSectDelete(&pThis->csRx);
7320 PDMR3CritSectDelete(&pThis->cs);
7321 }
7322 return VINF_SUCCESS;
7323}
7324
7325
7326/**
7327 * Set PCI configuration space registers.
7328 *
7329 * @param pci Reference to PCI device structure.
7330 * @thread EMT
7331 */
7332static DECLCALLBACK(void) e1kConfigurePciDev(PPCIDEVICE pPciDev, E1KCHIP eChip)
7333{
7334 Assert(eChip < RT_ELEMENTS(g_Chips));
7335 /* Configure PCI Device, assume 32-bit mode ******************************/
7336 PCIDevSetVendorId(pPciDev, g_Chips[eChip].uPCIVendorId);
7337 PCIDevSetDeviceId(pPciDev, g_Chips[eChip].uPCIDeviceId);
7338 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_Chips[eChip].uPCISubsystemVendorId);
7339 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_Chips[eChip].uPCISubsystemId);
7340
7341 PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7342 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7343 PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
7344 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7345 /* Stepping A2 */
7346 PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7347 /* Ethernet adapter */
7348 PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7349 PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7350 /* normal single function Ethernet controller */
7351 PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7352 /* Memory Register Base Address */
7353 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7354 /* Memory Flash Base Address */
7355 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7356 /* IO Register Base Address */
7357 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7358 /* Expansion ROM Base Address */
7359 PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7360 /* Capabilities Pointer */
7361 PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7362 /* Interrupt Pin: INTA# */
7363 PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7364 /* Max_Lat/Min_Gnt: very high priority and time slice */
7365 PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7366 PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7367
7368 /* PCI Power Management Registers ****************************************/
7369 /* Capability ID: PCI Power Management Registers */
7370 PCIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7371 /* Next Item Pointer: PCI-X */
7372 PCIDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7373 /* Power Management Capabilities: PM disabled, DSI */
7374 PCIDevSetWord( pPciDev, 0xDC + 2,
7375 0x0002 | VBOX_PCI_PM_CAP_DSI);
7376 /* Power Management Control / Status Register: PM disabled */
7377 PCIDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7378 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7379 PCIDevSetByte( pPciDev, 0xDC + 6, 0x00);
7380 /* Data Register: PM disabled, always 0 */
7381 PCIDevSetByte( pPciDev, 0xDC + 7, 0x00);
7382
7383 /* PCI-X Configuration Registers *****************************************/
7384 /* Capability ID: PCI-X Configuration Registers */
7385 PCIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7386#ifdef E1K_WITH_MSI
7387 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7388#else
7389 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7390 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7391#endif
7392 /* PCI-X Command: Enable Relaxed Ordering */
7393 PCIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7394 /* PCI-X Status: 32-bit, 66MHz*/
7395 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7396 PCIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7397}
7398
7399/**
7400 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7401 */
7402static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7403{
7404 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7405 int rc;
7406 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7407
7408 /*
7409 * Initialize the instance data (state).
7410 * Note! Caller has initialized it to ZERO already.
7411 */
7412 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7413 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7414 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7415 pThis->pDevInsR3 = pDevIns;
7416 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7417 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7418 pThis->u16TxPktLen = 0;
7419 pThis->fIPcsum = false;
7420 pThis->fTCPcsum = false;
7421 pThis->fIntMaskUsed = false;
7422 pThis->fDelayInts = false;
7423 pThis->fLocked = false;
7424 pThis->u64AckedAt = 0;
7425 pThis->led.u32Magic = PDMLED_MAGIC;
7426 pThis->u32PktNo = 1;
7427
7428 /* Interfaces */
7429 pThis->IBase.pfnQueryInterface = e1kR3QueryInterface;
7430
7431 pThis->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7432 pThis->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7433 pThis->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7434
7435 pThis->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7436
7437 pThis->INetworkConfig.pfnGetMac = e1kR3GetMac;
7438 pThis->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7439 pThis->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7440
7441 /*
7442 * Internal validations.
7443 */
7444 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7445 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7446 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7447 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7448 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7449 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7450 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7451 VERR_INTERNAL_ERROR_4);
7452
7453 /*
7454 * Validate configuration.
7455 */
7456 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0"
7457 "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"
7458 "ItrEnabled\0" "ItrRxEnabled\0"
7459 "EthernetCRC\0" "GSOEnabled\0" "LinkUpDelay\0"))
7460 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7461 N_("Invalid configuration for E1000 device"));
7462
7463 /** @todo: LineSpeed unused! */
7464
7465 pThis->fR0Enabled = true;
7466 pThis->fRCEnabled = true;
7467 pThis->fEthernetCRC = true;
7468 pThis->fGSOEnabled = true;
7469 pThis->fItrEnabled = true;
7470 pThis->fItrRxEnabled = true;
7471
7472 /* Get config params */
7473 rc = CFGMR3QueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7474 if (RT_FAILURE(rc))
7475 return PDMDEV_SET_ERROR(pDevIns, rc,
7476 N_("Configuration error: Failed to get MAC address"));
7477 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7478 if (RT_FAILURE(rc))
7479 return PDMDEV_SET_ERROR(pDevIns, rc,
7480 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7481 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7482 if (RT_FAILURE(rc))
7483 return PDMDEV_SET_ERROR(pDevIns, rc,
7484 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7485 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7486 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fRCEnabled, true);
7487 if (RT_FAILURE(rc))
7488 return PDMDEV_SET_ERROR(pDevIns, rc,
7489 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
7490
7491 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
7492 if (RT_FAILURE(rc))
7493 return PDMDEV_SET_ERROR(pDevIns, rc,
7494 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
7495
7496 rc = CFGMR3QueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7497 if (RT_FAILURE(rc))
7498 return PDMDEV_SET_ERROR(pDevIns, rc,
7499 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7500
7501 rc = CFGMR3QueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7502 if (RT_FAILURE(rc))
7503 return PDMDEV_SET_ERROR(pDevIns, rc,
7504 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7505
7506 rc = CFGMR3QueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, true);
7507 if (RT_FAILURE(rc))
7508 return PDMDEV_SET_ERROR(pDevIns, rc,
7509 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7510
7511 rc = CFGMR3QueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7512 if (RT_FAILURE(rc))
7513 return PDMDEV_SET_ERROR(pDevIns, rc,
7514 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7515
7516 rc = CFGMR3QueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 5000); /* ms */
7517 if (RT_FAILURE(rc))
7518 return PDMDEV_SET_ERROR(pDevIns, rc,
7519 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7520 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7521 if (pThis->cMsLinkUpDelay > 5000)
7522 LogRel(("%s WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7523 else if (pThis->cMsLinkUpDelay == 0)
7524 LogRel(("%s WARNING! Link up delay is disabled!\n", pThis->szPrf));
7525
7526 LogRel(("%s Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s R0=%s GC=%s\n", pThis->szPrf,
7527 g_Chips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7528 pThis->fEthernetCRC ? "on" : "off",
7529 pThis->fGSOEnabled ? "enabled" : "disabled",
7530 pThis->fItrEnabled ? "enabled" : "disabled",
7531 pThis->fItrRxEnabled ? "enabled" : "disabled",
7532 pThis->fR0Enabled ? "enabled" : "disabled",
7533 pThis->fRCEnabled ? "enabled" : "disabled"));
7534
7535 /* Initialize the EEPROM. */
7536 pThis->eeprom.init(pThis->macConfigured);
7537
7538 /* Initialize internal PHY. */
7539 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7540 Phy::setLinkStatus(&pThis->phy, pThis->fCableConnected);
7541
7542 /* Initialize critical sections. We do our own locking. */
7543 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7544 AssertRCReturn(rc, rc);
7545
7546 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7547 if (RT_FAILURE(rc))
7548 return rc;
7549 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7550 if (RT_FAILURE(rc))
7551 return rc;
7552#ifdef E1K_WITH_TX_CS
7553 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7554 if (RT_FAILURE(rc))
7555 return rc;
7556#endif /* E1K_WITH_TX_CS */
7557
7558 /* Saved state registration. */
7559 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7560 NULL, e1kLiveExec, NULL,
7561 e1kSavePrep, e1kSaveExec, NULL,
7562 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7563 if (RT_FAILURE(rc))
7564 return rc;
7565
7566 /* Set PCI config registers and register ourselves with the PCI bus. */
7567 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip);
7568 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice);
7569 if (RT_FAILURE(rc))
7570 return rc;
7571
7572#ifdef E1K_WITH_MSI
7573 PDMMSIREG MsiReg;
7574 RT_ZERO(MsiReg);
7575 MsiReg.cMsiVectors = 1;
7576 MsiReg.iMsiCapOffset = 0x80;
7577 MsiReg.iMsiNextOffset = 0x0;
7578 MsiReg.fMsi64bit = false;
7579 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7580 AssertRCReturn(rc, rc);
7581#endif
7582
7583
7584 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
7585 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, e1kMap);
7586 if (RT_FAILURE(rc))
7587 return rc;
7588 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
7589 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE, PCI_ADDRESS_SPACE_IO, e1kMap);
7590 if (RT_FAILURE(rc))
7591 return rc;
7592
7593 /* Create transmit queue */
7594 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7595 e1kTxQueueConsumer, true, "E1000-Xmit", &pThis->pTxQueueR3);
7596 if (RT_FAILURE(rc))
7597 return rc;
7598 pThis->pTxQueueR0 = PDMQueueR0Ptr(pThis->pTxQueueR3);
7599 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7600
7601 /* Create the RX notifier signaller. */
7602 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7603 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pThis->pCanRxQueueR3);
7604 if (RT_FAILURE(rc))
7605 return rc;
7606 pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
7607 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7608
7609#ifdef E1K_TX_DELAY
7610 /* Create Transmit Delay Timer */
7611 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxDelayTimer, pThis,
7612 TMTIMER_FLAGS_NO_CRIT_SECT,
7613 "E1000 Transmit Delay Timer", &pThis->pTXDTimerR3);
7614 if (RT_FAILURE(rc))
7615 return rc;
7616 pThis->pTXDTimerR0 = TMTimerR0Ptr(pThis->pTXDTimerR3);
7617 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7618 TMR3TimerSetCritSect(pThis->pTXDTimerR3, &pThis->csTx);
7619#endif /* E1K_TX_DELAY */
7620
7621#ifdef E1K_USE_TX_TIMERS
7622 /* Create Transmit Interrupt Delay Timer */
7623 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pThis,
7624 TMTIMER_FLAGS_NO_CRIT_SECT,
7625 "E1000 Transmit Interrupt Delay Timer", &pThis->pTIDTimerR3);
7626 if (RT_FAILURE(rc))
7627 return rc;
7628 pThis->pTIDTimerR0 = TMTimerR0Ptr(pThis->pTIDTimerR3);
7629 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7630
7631# ifndef E1K_NO_TAD
7632 /* Create Transmit Absolute Delay Timer */
7633 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pThis,
7634 TMTIMER_FLAGS_NO_CRIT_SECT,
7635 "E1000 Transmit Absolute Delay Timer", &pThis->pTADTimerR3);
7636 if (RT_FAILURE(rc))
7637 return rc;
7638 pThis->pTADTimerR0 = TMTimerR0Ptr(pThis->pTADTimerR3);
7639 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7640# endif /* E1K_NO_TAD */
7641#endif /* E1K_USE_TX_TIMERS */
7642
7643#ifdef E1K_USE_RX_TIMERS
7644 /* Create Receive Interrupt Delay Timer */
7645 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pThis,
7646 TMTIMER_FLAGS_NO_CRIT_SECT,
7647 "E1000 Receive Interrupt Delay Timer", &pThis->pRIDTimerR3);
7648 if (RT_FAILURE(rc))
7649 return rc;
7650 pThis->pRIDTimerR0 = TMTimerR0Ptr(pThis->pRIDTimerR3);
7651 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7652
7653 /* Create Receive Absolute Delay Timer */
7654 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pThis,
7655 TMTIMER_FLAGS_NO_CRIT_SECT,
7656 "E1000 Receive Absolute Delay Timer", &pThis->pRADTimerR3);
7657 if (RT_FAILURE(rc))
7658 return rc;
7659 pThis->pRADTimerR0 = TMTimerR0Ptr(pThis->pRADTimerR3);
7660 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7661#endif /* E1K_USE_RX_TIMERS */
7662
7663 /* Create Late Interrupt Timer */
7664 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pThis,
7665 TMTIMER_FLAGS_NO_CRIT_SECT,
7666 "E1000 Late Interrupt Timer", &pThis->pIntTimerR3);
7667 if (RT_FAILURE(rc))
7668 return rc;
7669 pThis->pIntTimerR0 = TMTimerR0Ptr(pThis->pIntTimerR3);
7670 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7671
7672 /* Create Link Up Timer */
7673 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pThis,
7674 TMTIMER_FLAGS_NO_CRIT_SECT,
7675 "E1000 Link Up Timer", &pThis->pLUTimerR3);
7676 if (RT_FAILURE(rc))
7677 return rc;
7678 pThis->pLUTimerR0 = TMTimerR0Ptr(pThis->pLUTimerR3);
7679 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7680
7681 /* Register the info item */
7682 char szTmp[20];
7683 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7684 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7685
7686 /* Status driver */
7687 PPDMIBASE pBase;
7688 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
7689 if (RT_FAILURE(rc))
7690 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7691 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7692
7693 /* Network driver */
7694 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7695 if (RT_SUCCESS(rc))
7696 {
7697 if (rc == VINF_NAT_DNS)
7698 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7699 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7700 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7701 AssertMsgReturn(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7702
7703 pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7704 pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7705 }
7706 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7707 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7708 {
7709 /* No error! */
7710 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7711 }
7712 else
7713 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7714
7715 rc = RTSemEventCreate(&pThis->hEventMoreRxDescAvail);
7716 if (RT_FAILURE(rc))
7717 return rc;
7718
7719 rc = e1kInitDebugHelpers();
7720 if (RT_FAILURE(rc))
7721 return rc;
7722
7723 e1kHardReset(pThis);
7724
7725 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Public/Net/E1k%u/BytesReceived", iInstance);
7726 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Public/Net/E1k%u/BytesTransmitted", iInstance);
7727
7728 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
7729 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
7730
7731#if defined(VBOX_WITH_STATISTICS)
7732 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
7733 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
7734 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
7735 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
7736 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
7737 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
7738 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
7739 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
7740 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
7741 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
7742 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
7743 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
7744 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
7745 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
7746 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
7747 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming", "/Devices/E1k%d/Receive/CRC", iInstance);
7748 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
7749 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
7750 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
7751 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
7752 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
7753 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
7754 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
7755 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
7756
7757 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
7758 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
7759 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
7760 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
7761 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
7762 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
7763 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
7764 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
7765 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
7766 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
7767 {
7768 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7769 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Reads", iInstance, g_aE1kRegMap[iReg].abbrev);
7770 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7771 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Writes", iInstance, g_aE1kRegMap[iReg].abbrev);
7772 }
7773#endif /* VBOX_WITH_STATISTICS */
7774
7775#ifdef E1K_INT_STATS
7776 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "u64ArmedAt", "/Devices/E1k%d/u64ArmedAt", iInstance);
7777 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatMaxTxDelay", "/Devices/E1k%d/uStatMaxTxDelay", iInstance);
7778 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatInt, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatInt", "/Devices/E1k%d/uStatInt", iInstance);
7779 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTry", "/Devices/E1k%d/uStatIntTry", iInstance);
7780 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLower", "/Devices/E1k%d/uStatIntLower", iInstance);
7781 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntDly", "/Devices/E1k%d/uStatIntDly", iInstance);
7782 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLost", "/Devices/E1k%d/iStatIntLost", iInstance);
7783 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLostOne", "/Devices/E1k%d/iStatIntLostOne", iInstance);
7784 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDisDly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDisDly", "/Devices/E1k%d/uStatDisDly", iInstance);
7785 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntSkip", "/Devices/E1k%d/uStatIntSkip", iInstance);
7786 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLate", "/Devices/E1k%d/uStatIntLate", iInstance);
7787 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntMasked", "/Devices/E1k%d/uStatIntMasked", iInstance);
7788 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntEarly", "/Devices/E1k%d/uStatIntEarly", iInstance);
7789 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRx", "/Devices/E1k%d/uStatIntRx", iInstance);
7790 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTx", "/Devices/E1k%d/uStatIntTx", iInstance);
7791 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntICS", "/Devices/E1k%d/uStatIntICS", iInstance);
7792 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRDTR", "/Devices/E1k%d/uStatIntRDTR", iInstance);
7793 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRXDMT0", "/Devices/E1k%d/uStatIntRXDMT0", iInstance);
7794 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTXQE", "/Devices/E1k%d/uStatIntTXQE", iInstance);
7795 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxNoRS", "/Devices/E1k%d/uStatTxNoRS", iInstance);
7796 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxIDE", "/Devices/E1k%d/uStatTxIDE", iInstance);
7797 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayed", "/Devices/E1k%d/uStatTxDelayed", iInstance);
7798 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayExp", "/Devices/E1k%d/uStatTxDelayExp", iInstance);
7799 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTAD", "/Devices/E1k%d/uStatTAD", iInstance);
7800 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTID", "/Devices/E1k%d/uStatTID", iInstance);
7801 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRAD", "/Devices/E1k%d/uStatRAD", iInstance);
7802 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRID", "/Devices/E1k%d/uStatRID", iInstance);
7803 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRxFrm", "/Devices/E1k%d/uStatRxFrm", iInstance);
7804 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxFrm", "/Devices/E1k%d/uStatTxFrm", iInstance);
7805 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescCtx", "/Devices/E1k%d/uStatDescCtx", iInstance);
7806 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescDat", "/Devices/E1k%d/uStatDescDat", iInstance);
7807 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescLeg", "/Devices/E1k%d/uStatDescLeg", iInstance);
7808 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx1514", "/Devices/E1k%d/uStatTx1514", iInstance);
7809 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx2962", "/Devices/E1k%d/uStatTx2962", iInstance);
7810 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx4410", "/Devices/E1k%d/uStatTx4410", iInstance);
7811 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx5858", "/Devices/E1k%d/uStatTx5858", iInstance);
7812 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx7306", "/Devices/E1k%d/uStatTx7306", iInstance);
7813 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx8754", "/Devices/E1k%d/uStatTx8754", iInstance);
7814 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx16384", "/Devices/E1k%d/uStatTx16384", iInstance);
7815 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx32768", "/Devices/E1k%d/uStatTx32768", iInstance);
7816 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxLarge", "/Devices/E1k%d/uStatTxLarge", iInstance);
7817#endif /* E1K_INT_STATS */
7818
7819 return VINF_SUCCESS;
7820}
7821
7822/**
7823 * The device registration structure.
7824 */
7825const PDMDEVREG g_DeviceE1000 =
7826{
7827 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
7828 PDM_DEVREG_VERSION,
7829 /* Device name. */
7830 "e1000",
7831 /* Name of guest context module (no path).
7832 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7833 "VBoxDDRC.rc",
7834 /* Name of ring-0 module (no path).
7835 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7836 "VBoxDDR0.r0",
7837 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
7838 * remain unchanged from registration till VM destruction. */
7839 "Intel PRO/1000 MT Desktop Ethernet.\n",
7840
7841 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
7842 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
7843 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
7844 PDM_DEVREG_CLASS_NETWORK,
7845 /* Maximum number of instances (per VM). */
7846 ~0U,
7847 /* Size of the instance data. */
7848 sizeof(E1KSTATE),
7849
7850 /* pfnConstruct */
7851 e1kR3Construct,
7852 /* pfnDestruct */
7853 e1kR3Destruct,
7854 /* pfnRelocate */
7855 e1kR3Relocate,
7856 /* pfnMemSetup */
7857 NULL,
7858 /* pfnPowerOn */
7859 NULL,
7860 /* pfnReset */
7861 e1kR3Reset,
7862 /* pfnSuspend */
7863 e1kR3Suspend,
7864 /* pfnResume */
7865 NULL,
7866 /* pfnAttach */
7867 e1kR3Attach,
7868 /* pfnDeatch */
7869 e1kR3Detach,
7870 /* pfnQueryInterface */
7871 NULL,
7872 /* pfnInitComplete */
7873 NULL,
7874 /* pfnPowerOff */
7875 e1kR3PowerOff,
7876 /* pfnSoftReset */
7877 NULL,
7878
7879 /* u32VersionEnd */
7880 PDM_DEVREG_VERSION
7881};
7882
7883#endif /* IN_RING3 */
7884#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette