VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 64700

Last change on this file since 64700 was 64684, checked in by vboxsync, 8 years ago

Dev/E1000: (bugref:8624) Delay interrupts in IMS handler, enable internal stats.
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1/* $Id: DevE1000.cpp 64684 2016-11-16 15:14:26Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2016 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_SLU
63 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
64 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
65 * that requires it is Mac OS X (see @bugref{4657}).
66 */
67#define E1K_LSC_ON_SLU
68/** @def E1K_INIT_LINKUP_DELAY
69 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
70 * in init (see @bugref{8624}).
71 */
72#define E1K_INIT_LINKUP_DELAY (500 * 1000)
73/** @def E1K_IMS_INT_DELAY_NS
74 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
75 * interrupts (see @bugref{8624}).
76 */
77#define E1K_IMS_INT_DELAY_NS 100
78/** @def E1K_TX_DELAY
79 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
80 * preventing packets to be sent immediately. It allows to send several
81 * packets in a batch reducing the number of acknowledgments. Note that it
82 * effectively disables R0 TX path, forcing sending in R3.
83 */
84//#define E1K_TX_DELAY 150
85/** @def E1K_USE_TX_TIMERS
86 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
87 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
88 * register. Enabling it showed no positive effects on existing guests so it
89 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
90 * Ethernet Controllers Software Developer’s Manual" for more detailed
91 * explanation.
92 */
93//#define E1K_USE_TX_TIMERS
94/** @def E1K_NO_TAD
95 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
96 * Transmit Absolute Delay time. This timer sets the maximum time interval
97 * during which TX interrupts can be postponed (delayed). It has no effect
98 * if E1K_USE_TX_TIMERS is not defined.
99 */
100//#define E1K_NO_TAD
101/** @def E1K_REL_DEBUG
102 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
103 */
104//#define E1K_REL_DEBUG
105/** @def E1K_INT_STATS
106 * E1K_INT_STATS enables collection of internal statistics used for
107 * debugging of delayed interrupts, etc.
108 */
109#define E1K_INT_STATS
110/** @def E1K_WITH_MSI
111 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
112 */
113//#define E1K_WITH_MSI
114/** @def E1K_WITH_TX_CS
115 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
116 */
117#define E1K_WITH_TX_CS
118/** @def E1K_WITH_TXD_CACHE
119 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
120 * single physical memory read (or two if it wraps around the end of TX
121 * descriptor ring). It is required for proper functioning of bandwidth
122 * resource control as it allows to compute exact sizes of packets prior
123 * to allocating their buffers (see @bugref{5582}).
124 */
125#define E1K_WITH_TXD_CACHE
126/** @def E1K_WITH_RXD_CACHE
127 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
128 * single physical memory read (or two if it wraps around the end of RX
129 * descriptor ring). Intel's packet driver for DOS needs this option in
130 * order to work properly (see @bugref{6217}).
131 */
132#define E1K_WITH_RXD_CACHE
133/** @def E1K_WITH_PREREG_MMIO
134 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
135 * currently only done for testing the relateted PDM, IOM and PGM code. */
136//#define E1K_WITH_PREREG_MMIO
137/* @} */
138/* End of Options ************************************************************/
139
140#ifdef E1K_WITH_TXD_CACHE
141/**
142 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
143 * in the state structure. It limits the amount of descriptors loaded in one
144 * batch read. For example, Linux guest may use up to 20 descriptors per
145 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
146 */
147# define E1K_TXD_CACHE_SIZE 64u
148#endif /* E1K_WITH_TXD_CACHE */
149
150#ifdef E1K_WITH_RXD_CACHE
151/**
152 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
153 * in the state structure. It limits the amount of descriptors loaded in one
154 * batch read. For example, XP guest adds 15 RX descriptors at a time.
155 */
156# define E1K_RXD_CACHE_SIZE 16u
157#endif /* E1K_WITH_RXD_CACHE */
158
159
160/* Little helpers ************************************************************/
161#undef htons
162#undef ntohs
163#undef htonl
164#undef ntohl
165#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
166#define ntohs(x) htons(x)
167#define htonl(x) ASMByteSwapU32(x)
168#define ntohl(x) htonl(x)
169
170#ifndef DEBUG
171# ifdef E1K_REL_DEBUG
172# define DEBUG
173# define E1kLog(a) LogRel(a)
174# define E1kLog2(a) LogRel(a)
175# define E1kLog3(a) LogRel(a)
176# define E1kLogX(x, a) LogRel(a)
177//# define E1kLog3(a) do {} while (0)
178# else
179# define E1kLog(a) do {} while (0)
180# define E1kLog2(a) do {} while (0)
181# define E1kLog3(a) do {} while (0)
182# define E1kLogX(x, a) do {} while (0)
183# endif
184#else
185# define E1kLog(a) Log(a)
186# define E1kLog2(a) Log2(a)
187# define E1kLog3(a) Log3(a)
188# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
189//# define E1kLog(a) do {} while (0)
190//# define E1kLog2(a) do {} while (0)
191//# define E1kLog3(a) do {} while (0)
192#endif
193
194#if 0
195# define LOG_ENABLED
196# define E1kLogRel(a) LogRel(a)
197# undef Log6
198# define Log6(a) LogRel(a)
199#else
200# define E1kLogRel(a) do { } while (0)
201#endif
202
203//#undef DEBUG
204
205#define STATE_TO_DEVINS(pThis) (((PE1KSTATE )pThis)->CTX_SUFF(pDevIns))
206#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
207
208#define E1K_INC_CNT32(cnt) \
209do { \
210 if (cnt < UINT32_MAX) \
211 cnt++; \
212} while (0)
213
214#define E1K_ADD_CNT64(cntLo, cntHi, val) \
215do { \
216 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
217 uint64_t tmp = u64Cnt; \
218 u64Cnt += val; \
219 if (tmp > u64Cnt ) \
220 u64Cnt = UINT64_MAX; \
221 cntLo = (uint32_t)u64Cnt; \
222 cntHi = (uint32_t)(u64Cnt >> 32); \
223} while (0)
224
225#ifdef E1K_INT_STATS
226# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
227#else /* E1K_INT_STATS */
228# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
229#endif /* E1K_INT_STATS */
230
231
232/*****************************************************************************/
233
234typedef uint32_t E1KCHIP;
235#define E1K_CHIP_82540EM 0
236#define E1K_CHIP_82543GC 1
237#define E1K_CHIP_82545EM 2
238
239#ifdef IN_RING3
240/** Different E1000 chips. */
241static const struct E1kChips
242{
243 uint16_t uPCIVendorId;
244 uint16_t uPCIDeviceId;
245 uint16_t uPCISubsystemVendorId;
246 uint16_t uPCISubsystemId;
247 const char *pcszName;
248} g_aChips[] =
249{
250 /* Vendor Device SSVendor SubSys Name */
251 { 0x8086,
252 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
253# ifdef E1K_WITH_MSI
254 0x105E,
255# else
256 0x100E,
257# endif
258 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
259 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
260 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
261};
262#endif /* IN_RING3 */
263
264
265/* The size of register area mapped to I/O space */
266#define E1K_IOPORT_SIZE 0x8
267/* The size of memory-mapped register area */
268#define E1K_MM_SIZE 0x20000
269
270#define E1K_MAX_TX_PKT_SIZE 16288
271#define E1K_MAX_RX_PKT_SIZE 16384
272
273/*****************************************************************************/
274
275/** Gets the specfieid bits from the register. */
276#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
277#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
278#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
279#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
280#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
281
282#define CTRL_SLU UINT32_C(0x00000040)
283#define CTRL_MDIO UINT32_C(0x00100000)
284#define CTRL_MDC UINT32_C(0x00200000)
285#define CTRL_MDIO_DIR UINT32_C(0x01000000)
286#define CTRL_MDC_DIR UINT32_C(0x02000000)
287#define CTRL_RESET UINT32_C(0x04000000)
288#define CTRL_VME UINT32_C(0x40000000)
289
290#define STATUS_LU UINT32_C(0x00000002)
291#define STATUS_TXOFF UINT32_C(0x00000010)
292
293#define EECD_EE_WIRES UINT32_C(0x0F)
294#define EECD_EE_REQ UINT32_C(0x40)
295#define EECD_EE_GNT UINT32_C(0x80)
296
297#define EERD_START UINT32_C(0x00000001)
298#define EERD_DONE UINT32_C(0x00000010)
299#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
300#define EERD_DATA_SHIFT 16
301#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
302#define EERD_ADDR_SHIFT 8
303
304#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
305#define MDIC_DATA_SHIFT 0
306#define MDIC_REG_MASK UINT32_C(0x001F0000)
307#define MDIC_REG_SHIFT 16
308#define MDIC_PHY_MASK UINT32_C(0x03E00000)
309#define MDIC_PHY_SHIFT 21
310#define MDIC_OP_WRITE UINT32_C(0x04000000)
311#define MDIC_OP_READ UINT32_C(0x08000000)
312#define MDIC_READY UINT32_C(0x10000000)
313#define MDIC_INT_EN UINT32_C(0x20000000)
314#define MDIC_ERROR UINT32_C(0x40000000)
315
316#define TCTL_EN UINT32_C(0x00000002)
317#define TCTL_PSP UINT32_C(0x00000008)
318
319#define RCTL_EN UINT32_C(0x00000002)
320#define RCTL_UPE UINT32_C(0x00000008)
321#define RCTL_MPE UINT32_C(0x00000010)
322#define RCTL_LPE UINT32_C(0x00000020)
323#define RCTL_LBM_MASK UINT32_C(0x000000C0)
324#define RCTL_LBM_SHIFT 6
325#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
326#define RCTL_RDMTS_SHIFT 8
327#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
328#define RCTL_MO_MASK UINT32_C(0x00003000)
329#define RCTL_MO_SHIFT 12
330#define RCTL_BAM UINT32_C(0x00008000)
331#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
332#define RCTL_BSIZE_SHIFT 16
333#define RCTL_VFE UINT32_C(0x00040000)
334#define RCTL_CFIEN UINT32_C(0x00080000)
335#define RCTL_CFI UINT32_C(0x00100000)
336#define RCTL_BSEX UINT32_C(0x02000000)
337#define RCTL_SECRC UINT32_C(0x04000000)
338
339#define ICR_TXDW UINT32_C(0x00000001)
340#define ICR_TXQE UINT32_C(0x00000002)
341#define ICR_LSC UINT32_C(0x00000004)
342#define ICR_RXDMT0 UINT32_C(0x00000010)
343#define ICR_RXT0 UINT32_C(0x00000080)
344#define ICR_TXD_LOW UINT32_C(0x00008000)
345#define RDTR_FPD UINT32_C(0x80000000)
346
347#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
348typedef struct
349{
350 unsigned rxa : 7;
351 unsigned rxa_r : 9;
352 unsigned txa : 16;
353} PBAST;
354AssertCompileSize(PBAST, 4);
355
356#define TXDCTL_WTHRESH_MASK 0x003F0000
357#define TXDCTL_WTHRESH_SHIFT 16
358#define TXDCTL_LWTHRESH_MASK 0xFE000000
359#define TXDCTL_LWTHRESH_SHIFT 25
360
361#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
362#define RXCSUM_PCSS_SHIFT 0
363
364/** @name Register access macros
365 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
366 * @{ */
367#define CTRL pThis->auRegs[CTRL_IDX]
368#define STATUS pThis->auRegs[STATUS_IDX]
369#define EECD pThis->auRegs[EECD_IDX]
370#define EERD pThis->auRegs[EERD_IDX]
371#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
372#define FLA pThis->auRegs[FLA_IDX]
373#define MDIC pThis->auRegs[MDIC_IDX]
374#define FCAL pThis->auRegs[FCAL_IDX]
375#define FCAH pThis->auRegs[FCAH_IDX]
376#define FCT pThis->auRegs[FCT_IDX]
377#define VET pThis->auRegs[VET_IDX]
378#define ICR pThis->auRegs[ICR_IDX]
379#define ITR pThis->auRegs[ITR_IDX]
380#define ICS pThis->auRegs[ICS_IDX]
381#define IMS pThis->auRegs[IMS_IDX]
382#define IMC pThis->auRegs[IMC_IDX]
383#define RCTL pThis->auRegs[RCTL_IDX]
384#define FCTTV pThis->auRegs[FCTTV_IDX]
385#define TXCW pThis->auRegs[TXCW_IDX]
386#define RXCW pThis->auRegs[RXCW_IDX]
387#define TCTL pThis->auRegs[TCTL_IDX]
388#define TIPG pThis->auRegs[TIPG_IDX]
389#define AIFS pThis->auRegs[AIFS_IDX]
390#define LEDCTL pThis->auRegs[LEDCTL_IDX]
391#define PBA pThis->auRegs[PBA_IDX]
392#define FCRTL pThis->auRegs[FCRTL_IDX]
393#define FCRTH pThis->auRegs[FCRTH_IDX]
394#define RDFH pThis->auRegs[RDFH_IDX]
395#define RDFT pThis->auRegs[RDFT_IDX]
396#define RDFHS pThis->auRegs[RDFHS_IDX]
397#define RDFTS pThis->auRegs[RDFTS_IDX]
398#define RDFPC pThis->auRegs[RDFPC_IDX]
399#define RDBAL pThis->auRegs[RDBAL_IDX]
400#define RDBAH pThis->auRegs[RDBAH_IDX]
401#define RDLEN pThis->auRegs[RDLEN_IDX]
402#define RDH pThis->auRegs[RDH_IDX]
403#define RDT pThis->auRegs[RDT_IDX]
404#define RDTR pThis->auRegs[RDTR_IDX]
405#define RXDCTL pThis->auRegs[RXDCTL_IDX]
406#define RADV pThis->auRegs[RADV_IDX]
407#define RSRPD pThis->auRegs[RSRPD_IDX]
408#define TXDMAC pThis->auRegs[TXDMAC_IDX]
409#define TDFH pThis->auRegs[TDFH_IDX]
410#define TDFT pThis->auRegs[TDFT_IDX]
411#define TDFHS pThis->auRegs[TDFHS_IDX]
412#define TDFTS pThis->auRegs[TDFTS_IDX]
413#define TDFPC pThis->auRegs[TDFPC_IDX]
414#define TDBAL pThis->auRegs[TDBAL_IDX]
415#define TDBAH pThis->auRegs[TDBAH_IDX]
416#define TDLEN pThis->auRegs[TDLEN_IDX]
417#define TDH pThis->auRegs[TDH_IDX]
418#define TDT pThis->auRegs[TDT_IDX]
419#define TIDV pThis->auRegs[TIDV_IDX]
420#define TXDCTL pThis->auRegs[TXDCTL_IDX]
421#define TADV pThis->auRegs[TADV_IDX]
422#define TSPMT pThis->auRegs[TSPMT_IDX]
423#define CRCERRS pThis->auRegs[CRCERRS_IDX]
424#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
425#define SYMERRS pThis->auRegs[SYMERRS_IDX]
426#define RXERRC pThis->auRegs[RXERRC_IDX]
427#define MPC pThis->auRegs[MPC_IDX]
428#define SCC pThis->auRegs[SCC_IDX]
429#define ECOL pThis->auRegs[ECOL_IDX]
430#define MCC pThis->auRegs[MCC_IDX]
431#define LATECOL pThis->auRegs[LATECOL_IDX]
432#define COLC pThis->auRegs[COLC_IDX]
433#define DC pThis->auRegs[DC_IDX]
434#define TNCRS pThis->auRegs[TNCRS_IDX]
435/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
436#define CEXTERR pThis->auRegs[CEXTERR_IDX]
437#define RLEC pThis->auRegs[RLEC_IDX]
438#define XONRXC pThis->auRegs[XONRXC_IDX]
439#define XONTXC pThis->auRegs[XONTXC_IDX]
440#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
441#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
442#define FCRUC pThis->auRegs[FCRUC_IDX]
443#define PRC64 pThis->auRegs[PRC64_IDX]
444#define PRC127 pThis->auRegs[PRC127_IDX]
445#define PRC255 pThis->auRegs[PRC255_IDX]
446#define PRC511 pThis->auRegs[PRC511_IDX]
447#define PRC1023 pThis->auRegs[PRC1023_IDX]
448#define PRC1522 pThis->auRegs[PRC1522_IDX]
449#define GPRC pThis->auRegs[GPRC_IDX]
450#define BPRC pThis->auRegs[BPRC_IDX]
451#define MPRC pThis->auRegs[MPRC_IDX]
452#define GPTC pThis->auRegs[GPTC_IDX]
453#define GORCL pThis->auRegs[GORCL_IDX]
454#define GORCH pThis->auRegs[GORCH_IDX]
455#define GOTCL pThis->auRegs[GOTCL_IDX]
456#define GOTCH pThis->auRegs[GOTCH_IDX]
457#define RNBC pThis->auRegs[RNBC_IDX]
458#define RUC pThis->auRegs[RUC_IDX]
459#define RFC pThis->auRegs[RFC_IDX]
460#define ROC pThis->auRegs[ROC_IDX]
461#define RJC pThis->auRegs[RJC_IDX]
462#define MGTPRC pThis->auRegs[MGTPRC_IDX]
463#define MGTPDC pThis->auRegs[MGTPDC_IDX]
464#define MGTPTC pThis->auRegs[MGTPTC_IDX]
465#define TORL pThis->auRegs[TORL_IDX]
466#define TORH pThis->auRegs[TORH_IDX]
467#define TOTL pThis->auRegs[TOTL_IDX]
468#define TOTH pThis->auRegs[TOTH_IDX]
469#define TPR pThis->auRegs[TPR_IDX]
470#define TPT pThis->auRegs[TPT_IDX]
471#define PTC64 pThis->auRegs[PTC64_IDX]
472#define PTC127 pThis->auRegs[PTC127_IDX]
473#define PTC255 pThis->auRegs[PTC255_IDX]
474#define PTC511 pThis->auRegs[PTC511_IDX]
475#define PTC1023 pThis->auRegs[PTC1023_IDX]
476#define PTC1522 pThis->auRegs[PTC1522_IDX]
477#define MPTC pThis->auRegs[MPTC_IDX]
478#define BPTC pThis->auRegs[BPTC_IDX]
479#define TSCTC pThis->auRegs[TSCTC_IDX]
480#define TSCTFC pThis->auRegs[TSCTFC_IDX]
481#define RXCSUM pThis->auRegs[RXCSUM_IDX]
482#define WUC pThis->auRegs[WUC_IDX]
483#define WUFC pThis->auRegs[WUFC_IDX]
484#define WUS pThis->auRegs[WUS_IDX]
485#define MANC pThis->auRegs[MANC_IDX]
486#define IPAV pThis->auRegs[IPAV_IDX]
487#define WUPL pThis->auRegs[WUPL_IDX]
488/** @} */
489
490/**
491 * Indices of memory-mapped registers in register table.
492 */
493typedef enum
494{
495 CTRL_IDX,
496 STATUS_IDX,
497 EECD_IDX,
498 EERD_IDX,
499 CTRL_EXT_IDX,
500 FLA_IDX,
501 MDIC_IDX,
502 FCAL_IDX,
503 FCAH_IDX,
504 FCT_IDX,
505 VET_IDX,
506 ICR_IDX,
507 ITR_IDX,
508 ICS_IDX,
509 IMS_IDX,
510 IMC_IDX,
511 RCTL_IDX,
512 FCTTV_IDX,
513 TXCW_IDX,
514 RXCW_IDX,
515 TCTL_IDX,
516 TIPG_IDX,
517 AIFS_IDX,
518 LEDCTL_IDX,
519 PBA_IDX,
520 FCRTL_IDX,
521 FCRTH_IDX,
522 RDFH_IDX,
523 RDFT_IDX,
524 RDFHS_IDX,
525 RDFTS_IDX,
526 RDFPC_IDX,
527 RDBAL_IDX,
528 RDBAH_IDX,
529 RDLEN_IDX,
530 RDH_IDX,
531 RDT_IDX,
532 RDTR_IDX,
533 RXDCTL_IDX,
534 RADV_IDX,
535 RSRPD_IDX,
536 TXDMAC_IDX,
537 TDFH_IDX,
538 TDFT_IDX,
539 TDFHS_IDX,
540 TDFTS_IDX,
541 TDFPC_IDX,
542 TDBAL_IDX,
543 TDBAH_IDX,
544 TDLEN_IDX,
545 TDH_IDX,
546 TDT_IDX,
547 TIDV_IDX,
548 TXDCTL_IDX,
549 TADV_IDX,
550 TSPMT_IDX,
551 CRCERRS_IDX,
552 ALGNERRC_IDX,
553 SYMERRS_IDX,
554 RXERRC_IDX,
555 MPC_IDX,
556 SCC_IDX,
557 ECOL_IDX,
558 MCC_IDX,
559 LATECOL_IDX,
560 COLC_IDX,
561 DC_IDX,
562 TNCRS_IDX,
563 SEC_IDX,
564 CEXTERR_IDX,
565 RLEC_IDX,
566 XONRXC_IDX,
567 XONTXC_IDX,
568 XOFFRXC_IDX,
569 XOFFTXC_IDX,
570 FCRUC_IDX,
571 PRC64_IDX,
572 PRC127_IDX,
573 PRC255_IDX,
574 PRC511_IDX,
575 PRC1023_IDX,
576 PRC1522_IDX,
577 GPRC_IDX,
578 BPRC_IDX,
579 MPRC_IDX,
580 GPTC_IDX,
581 GORCL_IDX,
582 GORCH_IDX,
583 GOTCL_IDX,
584 GOTCH_IDX,
585 RNBC_IDX,
586 RUC_IDX,
587 RFC_IDX,
588 ROC_IDX,
589 RJC_IDX,
590 MGTPRC_IDX,
591 MGTPDC_IDX,
592 MGTPTC_IDX,
593 TORL_IDX,
594 TORH_IDX,
595 TOTL_IDX,
596 TOTH_IDX,
597 TPR_IDX,
598 TPT_IDX,
599 PTC64_IDX,
600 PTC127_IDX,
601 PTC255_IDX,
602 PTC511_IDX,
603 PTC1023_IDX,
604 PTC1522_IDX,
605 MPTC_IDX,
606 BPTC_IDX,
607 TSCTC_IDX,
608 TSCTFC_IDX,
609 RXCSUM_IDX,
610 WUC_IDX,
611 WUFC_IDX,
612 WUS_IDX,
613 MANC_IDX,
614 IPAV_IDX,
615 WUPL_IDX,
616 MTA_IDX,
617 RA_IDX,
618 VFTA_IDX,
619 IP4AT_IDX,
620 IP6AT_IDX,
621 WUPM_IDX,
622 FFLT_IDX,
623 FFMT_IDX,
624 FFVT_IDX,
625 PBM_IDX,
626 RA_82542_IDX,
627 MTA_82542_IDX,
628 VFTA_82542_IDX,
629 E1K_NUM_OF_REGS
630} E1kRegIndex;
631
632#define E1K_NUM_OF_32BIT_REGS MTA_IDX
633/** The number of registers with strictly increasing offset. */
634#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
635
636
637/**
638 * Define E1000-specific EEPROM layout.
639 */
640struct E1kEEPROM
641{
642 public:
643 EEPROM93C46 eeprom;
644
645#ifdef IN_RING3
646 /**
647 * Initialize EEPROM content.
648 *
649 * @param macAddr MAC address of E1000.
650 */
651 void init(RTMAC &macAddr)
652 {
653 eeprom.init();
654 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
655 eeprom.m_au16Data[0x04] = 0xFFFF;
656 /*
657 * bit 3 - full support for power management
658 * bit 10 - full duplex
659 */
660 eeprom.m_au16Data[0x0A] = 0x4408;
661 eeprom.m_au16Data[0x0B] = 0x001E;
662 eeprom.m_au16Data[0x0C] = 0x8086;
663 eeprom.m_au16Data[0x0D] = 0x100E;
664 eeprom.m_au16Data[0x0E] = 0x8086;
665 eeprom.m_au16Data[0x0F] = 0x3040;
666 eeprom.m_au16Data[0x21] = 0x7061;
667 eeprom.m_au16Data[0x22] = 0x280C;
668 eeprom.m_au16Data[0x23] = 0x00C8;
669 eeprom.m_au16Data[0x24] = 0x00C8;
670 eeprom.m_au16Data[0x2F] = 0x0602;
671 updateChecksum();
672 };
673
674 /**
675 * Compute the checksum as required by E1000 and store it
676 * in the last word.
677 */
678 void updateChecksum()
679 {
680 uint16_t u16Checksum = 0;
681
682 for (int i = 0; i < eeprom.SIZE-1; i++)
683 u16Checksum += eeprom.m_au16Data[i];
684 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
685 };
686
687 /**
688 * First 6 bytes of EEPROM contain MAC address.
689 *
690 * @returns MAC address of E1000.
691 */
692 void getMac(PRTMAC pMac)
693 {
694 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
695 };
696
697 uint32_t read()
698 {
699 return eeprom.read();
700 }
701
702 void write(uint32_t u32Wires)
703 {
704 eeprom.write(u32Wires);
705 }
706
707 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
708 {
709 return eeprom.readWord(u32Addr, pu16Value);
710 }
711
712 int load(PSSMHANDLE pSSM)
713 {
714 return eeprom.load(pSSM);
715 }
716
717 void save(PSSMHANDLE pSSM)
718 {
719 eeprom.save(pSSM);
720 }
721#endif /* IN_RING3 */
722};
723
724
725#define E1K_SPEC_VLAN(s) (s & 0xFFF)
726#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
727#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
728
729struct E1kRxDStatus
730{
731 /** @name Descriptor Status field (3.2.3.1)
732 * @{ */
733 unsigned fDD : 1; /**< Descriptor Done. */
734 unsigned fEOP : 1; /**< End of packet. */
735 unsigned fIXSM : 1; /**< Ignore checksum indication. */
736 unsigned fVP : 1; /**< VLAN, matches VET. */
737 unsigned : 1;
738 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
739 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
740 unsigned fPIF : 1; /**< Passed in-exact filter */
741 /** @} */
742 /** @name Descriptor Errors field (3.2.3.2)
743 * (Only valid when fEOP and fDD are set.)
744 * @{ */
745 unsigned fCE : 1; /**< CRC or alignment error. */
746 unsigned : 4; /**< Reserved, varies with different models... */
747 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
748 unsigned fIPE : 1; /**< IP Checksum error. */
749 unsigned fRXE : 1; /**< RX Data error. */
750 /** @} */
751 /** @name Descriptor Special field (3.2.3.3)
752 * @{ */
753 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
754 /** @} */
755};
756typedef struct E1kRxDStatus E1KRXDST;
757
758struct E1kRxDesc_st
759{
760 uint64_t u64BufAddr; /**< Address of data buffer */
761 uint16_t u16Length; /**< Length of data in buffer */
762 uint16_t u16Checksum; /**< Packet checksum */
763 E1KRXDST status;
764};
765typedef struct E1kRxDesc_st E1KRXDESC;
766AssertCompileSize(E1KRXDESC, 16);
767
768#define E1K_DTYP_LEGACY -1
769#define E1K_DTYP_CONTEXT 0
770#define E1K_DTYP_DATA 1
771
772struct E1kTDLegacy
773{
774 uint64_t u64BufAddr; /**< Address of data buffer */
775 struct TDLCmd_st
776 {
777 unsigned u16Length : 16;
778 unsigned u8CSO : 8;
779 /* CMD field : 8 */
780 unsigned fEOP : 1;
781 unsigned fIFCS : 1;
782 unsigned fIC : 1;
783 unsigned fRS : 1;
784 unsigned fRPS : 1;
785 unsigned fDEXT : 1;
786 unsigned fVLE : 1;
787 unsigned fIDE : 1;
788 } cmd;
789 struct TDLDw3_st
790 {
791 /* STA field */
792 unsigned fDD : 1;
793 unsigned fEC : 1;
794 unsigned fLC : 1;
795 unsigned fTURSV : 1;
796 /* RSV field */
797 unsigned u4RSV : 4;
798 /* CSS field */
799 unsigned u8CSS : 8;
800 /* Special field*/
801 unsigned u16Special: 16;
802 } dw3;
803};
804
805/**
806 * TCP/IP Context Transmit Descriptor, section 3.3.6.
807 */
808struct E1kTDContext
809{
810 struct CheckSum_st
811 {
812 /** TSE: Header start. !TSE: Checksum start. */
813 unsigned u8CSS : 8;
814 /** Checksum offset - where to store it. */
815 unsigned u8CSO : 8;
816 /** Checksum ending (inclusive) offset, 0 = end of packet. */
817 unsigned u16CSE : 16;
818 } ip;
819 struct CheckSum_st tu;
820 struct TDCDw2_st
821 {
822 /** TSE: The total number of payload bytes for this context. Sans header. */
823 unsigned u20PAYLEN : 20;
824 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
825 unsigned u4DTYP : 4;
826 /** TUCMD field, 8 bits
827 * @{ */
828 /** TSE: TCP (set) or UDP (clear). */
829 unsigned fTCP : 1;
830 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
831 * the IP header. Does not affect the checksumming.
832 * @remarks 82544GC/EI interprets a cleared field differently. */
833 unsigned fIP : 1;
834 /** TSE: TCP segmentation enable. When clear the context describes */
835 unsigned fTSE : 1;
836 /** Report status (only applies to dw3.fDD for here). */
837 unsigned fRS : 1;
838 /** Reserved, MBZ. */
839 unsigned fRSV1 : 1;
840 /** Descriptor extension, must be set for this descriptor type. */
841 unsigned fDEXT : 1;
842 /** Reserved, MBZ. */
843 unsigned fRSV2 : 1;
844 /** Interrupt delay enable. */
845 unsigned fIDE : 1;
846 /** @} */
847 } dw2;
848 struct TDCDw3_st
849 {
850 /** Descriptor Done. */
851 unsigned fDD : 1;
852 /** Reserved, MBZ. */
853 unsigned u7RSV : 7;
854 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
855 unsigned u8HDRLEN : 8;
856 /** TSO: Maximum segment size. */
857 unsigned u16MSS : 16;
858 } dw3;
859};
860typedef struct E1kTDContext E1KTXCTX;
861
862/**
863 * TCP/IP Data Transmit Descriptor, section 3.3.7.
864 */
865struct E1kTDData
866{
867 uint64_t u64BufAddr; /**< Address of data buffer */
868 struct TDDCmd_st
869 {
870 /** The total length of data pointed to by this descriptor. */
871 unsigned u20DTALEN : 20;
872 /** The descriptor type - E1K_DTYP_DATA (1). */
873 unsigned u4DTYP : 4;
874 /** @name DCMD field, 8 bits (3.3.7.1).
875 * @{ */
876 /** End of packet. Note TSCTFC update. */
877 unsigned fEOP : 1;
878 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
879 unsigned fIFCS : 1;
880 /** Use the TSE context when set and the normal when clear. */
881 unsigned fTSE : 1;
882 /** Report status (dw3.STA). */
883 unsigned fRS : 1;
884 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
885 unsigned fRPS : 1;
886 /** Descriptor extension, must be set for this descriptor type. */
887 unsigned fDEXT : 1;
888 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
889 * Insert dw3.SPECIAL after ethernet header. */
890 unsigned fVLE : 1;
891 /** Interrupt delay enable. */
892 unsigned fIDE : 1;
893 /** @} */
894 } cmd;
895 struct TDDDw3_st
896 {
897 /** @name STA field (3.3.7.2)
898 * @{ */
899 unsigned fDD : 1; /**< Descriptor done. */
900 unsigned fEC : 1; /**< Excess collision. */
901 unsigned fLC : 1; /**< Late collision. */
902 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
903 unsigned fTURSV : 1;
904 /** @} */
905 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
906 /** @name POPTS (Packet Option) field (3.3.7.3)
907 * @{ */
908 unsigned fIXSM : 1; /**< Insert IP checksum. */
909 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
910 unsigned u6RSV : 6; /**< Reserved, MBZ. */
911 /** @} */
912 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
913 * Requires fEOP, fVLE and CTRL.VME to be set.
914 * @{ */
915 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
916 /** @} */
917 } dw3;
918};
919typedef struct E1kTDData E1KTXDAT;
920
921union E1kTxDesc
922{
923 struct E1kTDLegacy legacy;
924 struct E1kTDContext context;
925 struct E1kTDData data;
926};
927typedef union E1kTxDesc E1KTXDESC;
928AssertCompileSize(E1KTXDESC, 16);
929
930#define RA_CTL_AS 0x0003
931#define RA_CTL_AV 0x8000
932
933union E1kRecAddr
934{
935 uint32_t au32[32];
936 struct RAArray
937 {
938 uint8_t addr[6];
939 uint16_t ctl;
940 } array[16];
941};
942typedef struct E1kRecAddr::RAArray E1KRAELEM;
943typedef union E1kRecAddr E1KRA;
944AssertCompileSize(E1KRA, 8*16);
945
946#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
947#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
948#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
949#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
950
951/** @todo use+extend RTNETIPV4 */
952struct E1kIpHeader
953{
954 /* type of service / version / header length */
955 uint16_t tos_ver_hl;
956 /* total length */
957 uint16_t total_len;
958 /* identification */
959 uint16_t ident;
960 /* fragment offset field */
961 uint16_t offset;
962 /* time to live / protocol*/
963 uint16_t ttl_proto;
964 /* checksum */
965 uint16_t chksum;
966 /* source IP address */
967 uint32_t src;
968 /* destination IP address */
969 uint32_t dest;
970};
971AssertCompileSize(struct E1kIpHeader, 20);
972
973#define E1K_TCP_FIN UINT16_C(0x01)
974#define E1K_TCP_SYN UINT16_C(0x02)
975#define E1K_TCP_RST UINT16_C(0x04)
976#define E1K_TCP_PSH UINT16_C(0x08)
977#define E1K_TCP_ACK UINT16_C(0x10)
978#define E1K_TCP_URG UINT16_C(0x20)
979#define E1K_TCP_ECE UINT16_C(0x40)
980#define E1K_TCP_CWR UINT16_C(0x80)
981#define E1K_TCP_FLAGS UINT16_C(0x3f)
982
983/** @todo use+extend RTNETTCP */
984struct E1kTcpHeader
985{
986 uint16_t src;
987 uint16_t dest;
988 uint32_t seqno;
989 uint32_t ackno;
990 uint16_t hdrlen_flags;
991 uint16_t wnd;
992 uint16_t chksum;
993 uint16_t urgp;
994};
995AssertCompileSize(struct E1kTcpHeader, 20);
996
997
998#ifdef E1K_WITH_TXD_CACHE
999/** The current Saved state version. */
1000# define E1K_SAVEDSTATE_VERSION 4
1001/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1002# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1003#else /* !E1K_WITH_TXD_CACHE */
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 3
1006#endif /* !E1K_WITH_TXD_CACHE */
1007/** Saved state version for VirtualBox 4.1 and earlier.
1008 * These did not include VLAN tag fields. */
1009#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1010/** Saved state version for VirtualBox 3.0 and earlier.
1011 * This did not include the configuration part nor the E1kEEPROM. */
1012#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1013
1014/**
1015 * Device state structure.
1016 *
1017 * Holds the current state of device.
1018 *
1019 * @implements PDMINETWORKDOWN
1020 * @implements PDMINETWORKCONFIG
1021 * @implements PDMILEDPORTS
1022 */
1023struct E1kState_st
1024{
1025 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1026 PDMIBASE IBase;
1027 PDMINETWORKDOWN INetworkDown;
1028 PDMINETWORKCONFIG INetworkConfig;
1029 PDMILEDPORTS ILeds; /**< LED interface */
1030 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
1031 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1032
1033 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
1034 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
1035 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
1036 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
1037 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
1038 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
1039 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
1040 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
1041 PTMTIMERR3 pTXDTimerR3; /**< Transmit Delay Timer - R3. */
1042 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
1043 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
1044 /** The scatter / gather buffer used for the current outgoing packet - R3. */
1045 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1046
1047 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
1048 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
1049 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
1050 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
1051 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
1052 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
1053 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
1054 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
1055 PTMTIMERR0 pTXDTimerR0; /**< Transmit Delay Timer - R0. */
1056 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
1057 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
1058 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1059 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1060
1061 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
1062 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
1063 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
1064 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
1065 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
1066 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
1067 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
1068 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
1069 PTMTIMERRC pTXDTimerRC; /**< Transmit Delay Timer - RC. */
1070 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
1071 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
1072 /** The scatter / gather buffer used for the current outgoing packet - RC. */
1073 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1074 RTRCPTR RCPtrAlignment;
1075
1076#if HC_ARCH_BITS != 32
1077 uint32_t Alignment1;
1078#endif
1079 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
1080 PDMCRITSECT csRx; /**< RX Critical section. */
1081#ifdef E1K_WITH_TX_CS
1082 PDMCRITSECT csTx; /**< TX Critical section. */
1083#endif /* E1K_WITH_TX_CS */
1084 /** Base address of memory-mapped registers. */
1085 RTGCPHYS addrMMReg;
1086 /** MAC address obtained from the configuration. */
1087 RTMAC macConfigured;
1088 /** Base port of I/O space region. */
1089 RTIOPORT IOPortBase;
1090 /** EMT: */
1091 PDMPCIDEV pciDevice;
1092 /** EMT: Last time the interrupt was acknowledged. */
1093 uint64_t u64AckedAt;
1094 /** All: Used for eliminating spurious interrupts. */
1095 bool fIntRaised;
1096 /** EMT: false if the cable is disconnected by the GUI. */
1097 bool fCableConnected;
1098 /** EMT: */
1099 bool fR0Enabled;
1100 /** EMT: */
1101 bool fRCEnabled;
1102 /** EMT: Compute Ethernet CRC for RX packets. */
1103 bool fEthernetCRC;
1104 /** All: throttle interrupts. */
1105 bool fItrEnabled;
1106 /** All: throttle RX interrupts. */
1107 bool fItrRxEnabled;
1108 /** All: Delay TX interrupts using TIDV/TADV. */
1109 bool fTidEnabled;
1110 /** Link up delay (in milliseconds). */
1111 uint32_t cMsLinkUpDelay;
1112
1113 /** All: Device register storage. */
1114 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1115 /** TX/RX: Status LED. */
1116 PDMLED led;
1117 /** TX/RX: Number of packet being sent/received to show in debug log. */
1118 uint32_t u32PktNo;
1119
1120 /** EMT: Offset of the register to be read via IO. */
1121 uint32_t uSelectedReg;
1122 /** EMT: Multicast Table Array. */
1123 uint32_t auMTA[128];
1124 /** EMT: Receive Address registers. */
1125 E1KRA aRecAddr;
1126 /** EMT: VLAN filter table array. */
1127 uint32_t auVFTA[128];
1128 /** EMT: Receive buffer size. */
1129 uint16_t u16RxBSize;
1130 /** EMT: Locked state -- no state alteration possible. */
1131 bool fLocked;
1132 /** EMT: */
1133 bool fDelayInts;
1134 /** All: */
1135 bool fIntMaskUsed;
1136
1137 /** N/A: */
1138 bool volatile fMaybeOutOfSpace;
1139 /** EMT: Gets signalled when more RX descriptors become available. */
1140 RTSEMEVENT hEventMoreRxDescAvail;
1141#ifdef E1K_WITH_RXD_CACHE
1142 /** RX: Fetched RX descriptors. */
1143 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1144 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1145 /** RX: Actual number of fetched RX descriptors. */
1146 uint32_t nRxDFetched;
1147 /** RX: Index in cache of RX descriptor being processed. */
1148 uint32_t iRxDCurrent;
1149#endif /* E1K_WITH_RXD_CACHE */
1150
1151 /** TX: Context used for TCP segmentation packets. */
1152 E1KTXCTX contextTSE;
1153 /** TX: Context used for ordinary packets. */
1154 E1KTXCTX contextNormal;
1155#ifdef E1K_WITH_TXD_CACHE
1156 /** TX: Fetched TX descriptors. */
1157 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1158 /** TX: Actual number of fetched TX descriptors. */
1159 uint8_t nTxDFetched;
1160 /** TX: Index in cache of TX descriptor being processed. */
1161 uint8_t iTxDCurrent;
1162 /** TX: Will this frame be sent as GSO. */
1163 bool fGSO;
1164 /** Alignment padding. */
1165 bool fReserved;
1166 /** TX: Number of bytes in next packet. */
1167 uint32_t cbTxAlloc;
1168
1169#endif /* E1K_WITH_TXD_CACHE */
1170 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1171 * applicable to the current TSE mode. */
1172 PDMNETWORKGSO GsoCtx;
1173 /** Scratch space for holding the loopback / fallback scatter / gather
1174 * descriptor. */
1175 union
1176 {
1177 PDMSCATTERGATHER Sg;
1178 uint8_t padding[8 * sizeof(RTUINTPTR)];
1179 } uTxFallback;
1180 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1181 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1182 /** TX: Number of bytes assembled in TX packet buffer. */
1183 uint16_t u16TxPktLen;
1184 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1185 bool fGSOEnabled;
1186 /** TX: IP checksum has to be inserted if true. */
1187 bool fIPcsum;
1188 /** TX: TCP/UDP checksum has to be inserted if true. */
1189 bool fTCPcsum;
1190 /** TX: VLAN tag has to be inserted if true. */
1191 bool fVTag;
1192 /** TX: TCI part of VLAN tag to be inserted. */
1193 uint16_t u16VTagTCI;
1194 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1195 uint32_t u32PayRemain;
1196 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1197 uint16_t u16HdrRemain;
1198 /** TX TSE fallback: Flags from template header. */
1199 uint16_t u16SavedFlags;
1200 /** TX TSE fallback: Partial checksum from template header. */
1201 uint32_t u32SavedCsum;
1202 /** ?: Emulated controller type. */
1203 E1KCHIP eChip;
1204
1205 /** EMT: EEPROM emulation */
1206 E1kEEPROM eeprom;
1207 /** EMT: Physical interface emulation. */
1208 PHY phy;
1209
1210#if 0
1211 /** Alignment padding. */
1212 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1213#endif
1214
1215 STAMCOUNTER StatReceiveBytes;
1216 STAMCOUNTER StatTransmitBytes;
1217#if defined(VBOX_WITH_STATISTICS)
1218 STAMPROFILEADV StatMMIOReadRZ;
1219 STAMPROFILEADV StatMMIOReadR3;
1220 STAMPROFILEADV StatMMIOWriteRZ;
1221 STAMPROFILEADV StatMMIOWriteR3;
1222 STAMPROFILEADV StatEEPROMRead;
1223 STAMPROFILEADV StatEEPROMWrite;
1224 STAMPROFILEADV StatIOReadRZ;
1225 STAMPROFILEADV StatIOReadR3;
1226 STAMPROFILEADV StatIOWriteRZ;
1227 STAMPROFILEADV StatIOWriteR3;
1228 STAMPROFILEADV StatLateIntTimer;
1229 STAMCOUNTER StatLateInts;
1230 STAMCOUNTER StatIntsRaised;
1231 STAMCOUNTER StatIntsPrevented;
1232 STAMPROFILEADV StatReceive;
1233 STAMPROFILEADV StatReceiveCRC;
1234 STAMPROFILEADV StatReceiveFilter;
1235 STAMPROFILEADV StatReceiveStore;
1236 STAMPROFILEADV StatTransmitRZ;
1237 STAMPROFILEADV StatTransmitR3;
1238 STAMPROFILE StatTransmitSendRZ;
1239 STAMPROFILE StatTransmitSendR3;
1240 STAMPROFILE StatRxOverflow;
1241 STAMCOUNTER StatRxOverflowWakeup;
1242 STAMCOUNTER StatTxDescCtxNormal;
1243 STAMCOUNTER StatTxDescCtxTSE;
1244 STAMCOUNTER StatTxDescLegacy;
1245 STAMCOUNTER StatTxDescData;
1246 STAMCOUNTER StatTxDescTSEData;
1247 STAMCOUNTER StatTxPathFallback;
1248 STAMCOUNTER StatTxPathGSO;
1249 STAMCOUNTER StatTxPathRegular;
1250 STAMCOUNTER StatPHYAccesses;
1251 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1252 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1253#endif /* VBOX_WITH_STATISTICS */
1254
1255#ifdef E1K_INT_STATS
1256 /* Internal stats */
1257 uint64_t u64ArmedAt;
1258 uint64_t uStatMaxTxDelay;
1259 uint32_t uStatInt;
1260 uint32_t uStatIntTry;
1261 uint32_t uStatIntLower;
1262 uint32_t uStatNoIntICR;
1263 int32_t iStatIntLost;
1264 int32_t iStatIntLostOne;
1265 uint32_t uStatIntIMS;
1266 uint32_t uStatIntSkip;
1267 uint32_t uStatIntLate;
1268 uint32_t uStatIntMasked;
1269 uint32_t uStatIntEarly;
1270 uint32_t uStatIntRx;
1271 uint32_t uStatIntTx;
1272 uint32_t uStatIntICS;
1273 uint32_t uStatIntRDTR;
1274 uint32_t uStatIntRXDMT0;
1275 uint32_t uStatIntTXQE;
1276 uint32_t uStatTxNoRS;
1277 uint32_t uStatTxIDE;
1278 uint32_t uStatTxDelayed;
1279 uint32_t uStatTxDelayExp;
1280 uint32_t uStatTAD;
1281 uint32_t uStatTID;
1282 uint32_t uStatRAD;
1283 uint32_t uStatRID;
1284 uint32_t uStatRxFrm;
1285 uint32_t uStatTxFrm;
1286 uint32_t uStatDescCtx;
1287 uint32_t uStatDescDat;
1288 uint32_t uStatDescLeg;
1289 uint32_t uStatTx1514;
1290 uint32_t uStatTx2962;
1291 uint32_t uStatTx4410;
1292 uint32_t uStatTx5858;
1293 uint32_t uStatTx7306;
1294 uint32_t uStatTx8754;
1295 uint32_t uStatTx16384;
1296 uint32_t uStatTx32768;
1297 uint32_t uStatTxLarge;
1298 uint32_t uStatAlign;
1299#endif /* E1K_INT_STATS */
1300};
1301typedef struct E1kState_st E1KSTATE;
1302/** Pointer to the E1000 device state. */
1303typedef E1KSTATE *PE1KSTATE;
1304
1305#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1306
1307/* Forward declarations ******************************************************/
1308static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread);
1309
1310static int e1kRegReadUnimplemented (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1311static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1312static int e1kRegReadAutoClear (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1313static int e1kRegReadDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1314static int e1kRegWriteDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1315#if 0 /* unused */
1316static int e1kRegReadCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1317#endif
1318static int e1kRegWriteCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1319static int e1kRegReadEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1320static int e1kRegWriteEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1321static int e1kRegWriteEERD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1322static int e1kRegWriteMDIC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1323static int e1kRegReadICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1324static int e1kRegWriteICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1325static int e1kRegWriteICS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1326static int e1kRegWriteIMS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1327static int e1kRegWriteIMC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1328static int e1kRegWriteRCTL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1329static int e1kRegWritePBA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1330static int e1kRegWriteRDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1331static int e1kRegWriteRDTR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1332static int e1kRegWriteTDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1333static int e1kRegReadMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1334static int e1kRegWriteMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1335static int e1kRegReadRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1336static int e1kRegWriteRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1337static int e1kRegReadVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1338static int e1kRegWriteVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1339
1340/**
1341 * Register map table.
1342 *
1343 * Override pfnRead and pfnWrite to get register-specific behavior.
1344 */
1345static const struct E1kRegMap_st
1346{
1347 /** Register offset in the register space. */
1348 uint32_t offset;
1349 /** Size in bytes. Registers of size > 4 are in fact tables. */
1350 uint32_t size;
1351 /** Readable bits. */
1352 uint32_t readable;
1353 /** Writable bits. */
1354 uint32_t writable;
1355 /** Read callback. */
1356 int (*pfnRead)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1357 /** Write callback. */
1358 int (*pfnWrite)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1359 /** Abbreviated name. */
1360 const char *abbrev;
1361 /** Full name. */
1362 const char *name;
1363} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1364{
1365 /* offset size read mask write mask read callback write callback abbrev full name */
1366 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1367 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1368 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1369 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1370 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1371 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1372 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1373 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1374 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1375 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1376 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1377 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1378 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1379 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1380 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1381 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1382 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1383 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1384 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1385 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1386 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1387 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1388 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1389 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1390 { 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
1391 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1392 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1393 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1394 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1395 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1396 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1397 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1398 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1399 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1400 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1401 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1402 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1403 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1404 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1405 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1406 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1407 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1408 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1409 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1410 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1411 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1412 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1413 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1414 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1415 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1416 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1417 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1418 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1419 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1420 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1421 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1422 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1423 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1424 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1425 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1426 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1427 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1428 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1429 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1430 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1431 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1432 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1433 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1434 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1435 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1436 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1437 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1438 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1439 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1440 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1441 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1442 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1443 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1444 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1445 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1446 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1447 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1448 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1449 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1450 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1451 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1452 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1453 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1454 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1455 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1456 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1457 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1458 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1459 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1460 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1461 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1462 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1463 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1464 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1465 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1466 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1467 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1468 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1469 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1470 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1471 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1472 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1473 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1474 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1475 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1476 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1477 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1478 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1479 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1480 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1481 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1482 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1483 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1484 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1485 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1486 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1487 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1488 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1489 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1490 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1491 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1492 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1493 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1494 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1495 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1496 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1497 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1498 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1499 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1500 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1501};
1502
1503#ifdef LOG_ENABLED
1504
1505/**
1506 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1507 *
1508 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1509 *
1510 * @returns The buffer.
1511 *
1512 * @param u32 The word to convert into string.
1513 * @param mask Selects which bytes to convert.
1514 * @param buf Where to put the result.
1515 */
1516static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1517{
1518 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1519 {
1520 if (mask & 0xF)
1521 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1522 else
1523 *ptr = '.';
1524 }
1525 buf[8] = 0;
1526 return buf;
1527}
1528
1529/**
1530 * Returns timer name for debug purposes.
1531 *
1532 * @returns The timer name.
1533 *
1534 * @param pThis The device state structure.
1535 * @param pTimer The timer to get the name for.
1536 */
1537DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, PTMTIMER pTimer)
1538{
1539 if (pTimer == pThis->CTX_SUFF(pTIDTimer))
1540 return "TID";
1541 if (pTimer == pThis->CTX_SUFF(pTADTimer))
1542 return "TAD";
1543 if (pTimer == pThis->CTX_SUFF(pRIDTimer))
1544 return "RID";
1545 if (pTimer == pThis->CTX_SUFF(pRADTimer))
1546 return "RAD";
1547 if (pTimer == pThis->CTX_SUFF(pIntTimer))
1548 return "Int";
1549 if (pTimer == pThis->CTX_SUFF(pTXDTimer))
1550 return "TXD";
1551 if (pTimer == pThis->CTX_SUFF(pLUTimer))
1552 return "LinkUp";
1553 return "unknown";
1554}
1555
1556#endif /* DEBUG */
1557
1558/**
1559 * Arm a timer.
1560 *
1561 * @param pThis Pointer to the device state structure.
1562 * @param pTimer Pointer to the timer.
1563 * @param uExpireIn Expiration interval in microseconds.
1564 */
1565DECLINLINE(void) e1kArmTimer(PE1KSTATE pThis, PTMTIMER pTimer, uint32_t uExpireIn)
1566{
1567 if (pThis->fLocked)
1568 return;
1569
1570 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1571 pThis->szPrf, e1kGetTimerName(pThis, pTimer), uExpireIn));
1572 TMTimerSetMicro(pTimer, uExpireIn);
1573}
1574
1575#ifdef IN_RING3
1576/**
1577 * Cancel a timer.
1578 *
1579 * @param pThis Pointer to the device state structure.
1580 * @param pTimer Pointer to the timer.
1581 */
1582DECLINLINE(void) e1kCancelTimer(PE1KSTATE pThis, PTMTIMER pTimer)
1583{
1584 E1kLog2(("%s Stopping %s timer...\n",
1585 pThis->szPrf, e1kGetTimerName(pThis, pTimer)));
1586 int rc = TMTimerStop(pTimer);
1587 if (RT_FAILURE(rc))
1588 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1589 pThis->szPrf, rc));
1590 RT_NOREF1(pThis);
1591}
1592#endif /* IN_RING3 */
1593
1594#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1595#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1596
1597#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1598#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1599#define e1kCsRxIsOwner(ps) PDMCritSectIsOwner(&ps->csRx)
1600
1601#ifndef E1K_WITH_TX_CS
1602# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1603# define e1kCsTxLeave(ps) do { } while (0)
1604#else /* E1K_WITH_TX_CS */
1605# define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1606# define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1607#endif /* E1K_WITH_TX_CS */
1608
1609#ifdef IN_RING3
1610
1611/**
1612 * Wakeup the RX thread.
1613 */
1614static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1615{
1616 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
1617 if ( pThis->fMaybeOutOfSpace
1618 && pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1619 {
1620 STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1621 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1622 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
1623 }
1624}
1625
1626/**
1627 * Hardware reset. Revert all registers to initial values.
1628 *
1629 * @param pThis The device state structure.
1630 */
1631static void e1kHardReset(PE1KSTATE pThis)
1632{
1633 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1634 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1635 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1636#ifdef E1K_INIT_RA0
1637 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1638 sizeof(pThis->macConfigured.au8));
1639 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1640#endif /* E1K_INIT_RA0 */
1641 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1642 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1643 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1644 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1645 Assert(GET_BITS(RCTL, BSIZE) == 0);
1646 pThis->u16RxBSize = 2048;
1647
1648 /* Reset promiscuous mode */
1649 if (pThis->pDrvR3)
1650 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, false);
1651
1652#ifdef E1K_WITH_TXD_CACHE
1653 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1654 if (RT_LIKELY(rc == VINF_SUCCESS))
1655 {
1656 pThis->nTxDFetched = 0;
1657 pThis->iTxDCurrent = 0;
1658 pThis->fGSO = false;
1659 pThis->cbTxAlloc = 0;
1660 e1kCsTxLeave(pThis);
1661 }
1662#endif /* E1K_WITH_TXD_CACHE */
1663#ifdef E1K_WITH_RXD_CACHE
1664 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1665 {
1666 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1667 e1kCsRxLeave(pThis);
1668 }
1669#endif /* E1K_WITH_RXD_CACHE */
1670}
1671
1672#endif /* IN_RING3 */
1673
1674/**
1675 * Compute Internet checksum.
1676 *
1677 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1678 *
1679 * @param pThis The device state structure.
1680 * @param cpPacket The packet.
1681 * @param cb The size of the packet.
1682 * @param pszText A string denoting direction of packet transfer.
1683 *
1684 * @return The 1's complement of the 1's complement sum.
1685 *
1686 * @thread E1000_TX
1687 */
1688static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1689{
1690 uint32_t csum = 0;
1691 uint16_t *pu16 = (uint16_t *)pvBuf;
1692
1693 while (cb > 1)
1694 {
1695 csum += *pu16++;
1696 cb -= 2;
1697 }
1698 if (cb)
1699 csum += *(uint8_t*)pu16;
1700 while (csum >> 16)
1701 csum = (csum >> 16) + (csum & 0xFFFF);
1702 return ~csum;
1703}
1704
1705/**
1706 * Dump a packet to debug log.
1707 *
1708 * @param pThis The device state structure.
1709 * @param cpPacket The packet.
1710 * @param cb The size of the packet.
1711 * @param pszText A string denoting direction of packet transfer.
1712 * @thread E1000_TX
1713 */
1714DECLINLINE(void) e1kPacketDump(PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1715{
1716#ifdef DEBUG
1717 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1718 {
1719 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1720 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1721 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1722 {
1723 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1724 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1725 if (*(cpPacket+14+6) == 0x6)
1726 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1727 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1728 }
1729 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1730 {
1731 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1732 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1733 if (*(cpPacket+14+6) == 0x6)
1734 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1735 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1736 }
1737 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1738 e1kCsLeave(pThis);
1739 }
1740#else
1741 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1742 {
1743 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1744 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1745 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1746 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1747 else
1748 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1749 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1750 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1751 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1752 e1kCsLeave(pThis);
1753 }
1754 RT_NOREF2(cb, pszText);
1755#endif
1756}
1757
1758/**
1759 * Determine the type of transmit descriptor.
1760 *
1761 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1762 *
1763 * @param pDesc Pointer to descriptor union.
1764 * @thread E1000_TX
1765 */
1766DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1767{
1768 if (pDesc->legacy.cmd.fDEXT)
1769 return pDesc->context.dw2.u4DTYP;
1770 return E1K_DTYP_LEGACY;
1771}
1772
1773
1774#if defined(E1K_WITH_RXD_CACHE) && defined(IN_RING3) /* currently only used in ring-3 due to stack space requirements of the caller */
1775/**
1776 * Dump receive descriptor to debug log.
1777 *
1778 * @param pThis The device state structure.
1779 * @param pDesc Pointer to the descriptor.
1780 * @thread E1000_RX
1781 */
1782static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
1783{
1784 RT_NOREF2(pThis, pDesc);
1785 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1786 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1787 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1788 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1789 pDesc->status.fPIF ? "PIF" : "pif",
1790 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1791 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1792 pDesc->status.fVP ? "VP" : "vp",
1793 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1794 pDesc->status.fEOP ? "EOP" : "eop",
1795 pDesc->status.fDD ? "DD" : "dd",
1796 pDesc->status.fRXE ? "RXE" : "rxe",
1797 pDesc->status.fIPE ? "IPE" : "ipe",
1798 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1799 pDesc->status.fCE ? "CE" : "ce",
1800 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1801 E1K_SPEC_VLAN(pDesc->status.u16Special),
1802 E1K_SPEC_PRI(pDesc->status.u16Special)));
1803}
1804#endif /* E1K_WITH_RXD_CACHE && IN_RING3 */
1805
1806/**
1807 * Dump transmit descriptor to debug log.
1808 *
1809 * @param pThis The device state structure.
1810 * @param pDesc Pointer to descriptor union.
1811 * @param pszDir A string denoting direction of descriptor transfer
1812 * @thread E1000_TX
1813 */
1814static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
1815 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1816{
1817 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
1818
1819 /*
1820 * Unfortunately we cannot use our format handler here, we want R0 logging
1821 * as well.
1822 */
1823 switch (e1kGetDescType(pDesc))
1824 {
1825 case E1K_DTYP_CONTEXT:
1826 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
1827 pThis->szPrf, pszDir, pszDir));
1828 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1829 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1830 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1831 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1832 pDesc->context.dw2.fIDE ? " IDE":"",
1833 pDesc->context.dw2.fRS ? " RS" :"",
1834 pDesc->context.dw2.fTSE ? " TSE":"",
1835 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1836 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1837 pDesc->context.dw2.u20PAYLEN,
1838 pDesc->context.dw3.u8HDRLEN,
1839 pDesc->context.dw3.u16MSS,
1840 pDesc->context.dw3.fDD?"DD":""));
1841 break;
1842 case E1K_DTYP_DATA:
1843 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1844 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
1845 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1846 pDesc->data.u64BufAddr,
1847 pDesc->data.cmd.u20DTALEN));
1848 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1849 pDesc->data.cmd.fIDE ? " IDE" :"",
1850 pDesc->data.cmd.fVLE ? " VLE" :"",
1851 pDesc->data.cmd.fRPS ? " RPS" :"",
1852 pDesc->data.cmd.fRS ? " RS" :"",
1853 pDesc->data.cmd.fTSE ? " TSE" :"",
1854 pDesc->data.cmd.fIFCS? " IFCS":"",
1855 pDesc->data.cmd.fEOP ? " EOP" :"",
1856 pDesc->data.dw3.fDD ? " DD" :"",
1857 pDesc->data.dw3.fEC ? " EC" :"",
1858 pDesc->data.dw3.fLC ? " LC" :"",
1859 pDesc->data.dw3.fTXSM? " TXSM":"",
1860 pDesc->data.dw3.fIXSM? " IXSM":"",
1861 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
1862 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
1863 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
1864 break;
1865 case E1K_DTYP_LEGACY:
1866 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1867 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
1868 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1869 pDesc->data.u64BufAddr,
1870 pDesc->legacy.cmd.u16Length));
1871 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1872 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1873 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1874 pDesc->legacy.cmd.fRPS ? " RPS" :"",
1875 pDesc->legacy.cmd.fRS ? " RS" :"",
1876 pDesc->legacy.cmd.fIC ? " IC" :"",
1877 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1878 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1879 pDesc->legacy.dw3.fDD ? " DD" :"",
1880 pDesc->legacy.dw3.fEC ? " EC" :"",
1881 pDesc->legacy.dw3.fLC ? " LC" :"",
1882 pDesc->legacy.cmd.u8CSO,
1883 pDesc->legacy.dw3.u8CSS,
1884 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
1885 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
1886 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
1887 break;
1888 default:
1889 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
1890 pThis->szPrf, pszDir, pszDir));
1891 break;
1892 }
1893}
1894
1895/**
1896 * Raise an interrupt later.
1897 *
1898 * @param pThis The device state structure.
1899 */
1900inline void e1kPostponeInterrupt(PE1KSTATE pThis, uint64_t uNanoseconds)
1901{
1902 if (!TMTimerIsActive(pThis->CTX_SUFF(pIntTimer)))
1903 TMTimerSetNano(pThis->CTX_SUFF(pIntTimer), uNanoseconds);
1904}
1905
1906/**
1907 * Raise interrupt if not masked.
1908 *
1909 * @param pThis The device state structure.
1910 */
1911static int e1kRaiseInterrupt(PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
1912{
1913 int rc = e1kCsEnter(pThis, rcBusy);
1914 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1915 return rc;
1916
1917 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
1918 ICR |= u32IntCause;
1919 if (ICR & IMS)
1920 {
1921 if (pThis->fIntRaised)
1922 {
1923 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
1924 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
1925 pThis->szPrf, ICR & IMS));
1926 }
1927 else
1928 {
1929 uint64_t tsNow = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
1930 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
1931 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
1932 {
1933 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
1934 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
1935 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
1936 e1kPostponeInterrupt(pThis, ITR * 256);
1937 }
1938 else
1939 {
1940
1941 /* Since we are delivering the interrupt now
1942 * there is no need to do it later -- stop the timer.
1943 */
1944 TMTimerStop(pThis->CTX_SUFF(pIntTimer));
1945 E1K_INC_ISTAT_CNT(pThis->uStatInt);
1946 STAM_COUNTER_INC(&pThis->StatIntsRaised);
1947 /* Got at least one unmasked interrupt cause */
1948 pThis->fIntRaised = true;
1949 /* Raise(1) INTA(0) */
1950 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
1951 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
1952 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
1953 pThis->szPrf, ICR & IMS));
1954 }
1955 }
1956 }
1957 else
1958 {
1959 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
1960 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
1961 pThis->szPrf, ICR, IMS));
1962 }
1963 e1kCsLeave(pThis);
1964 return VINF_SUCCESS;
1965}
1966
1967/**
1968 * Compute the physical address of the descriptor.
1969 *
1970 * @returns the physical address of the descriptor.
1971 *
1972 * @param baseHigh High-order 32 bits of descriptor table address.
1973 * @param baseLow Low-order 32 bits of descriptor table address.
1974 * @param idxDesc The descriptor index in the table.
1975 */
1976DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
1977{
1978 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
1979 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
1980}
1981
1982#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
1983/**
1984 * Advance the head pointer of the receive descriptor queue.
1985 *
1986 * @remarks RDH always points to the next available RX descriptor.
1987 *
1988 * @param pThis The device state structure.
1989 */
1990DECLINLINE(void) e1kAdvanceRDH(PE1KSTATE pThis)
1991{
1992 Assert(e1kCsRxIsOwner(pThis));
1993 //e1kCsEnter(pThis, RT_SRC_POS);
1994 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
1995 RDH = 0;
1996 /*
1997 * Compute current receive queue length and fire RXDMT0 interrupt
1998 * if we are low on receive buffers
1999 */
2000 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
2001 /*
2002 * The minimum threshold is controlled by RDMTS bits of RCTL:
2003 * 00 = 1/2 of RDLEN
2004 * 01 = 1/4 of RDLEN
2005 * 10 = 1/8 of RDLEN
2006 * 11 = reserved
2007 */
2008 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2009 if (uRQueueLen <= uMinRQThreshold)
2010 {
2011 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
2012 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2013 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
2014 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2015 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2016 }
2017 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2018 pThis->szPrf, RDH, RDT, uRQueueLen));
2019 //e1kCsLeave(pThis);
2020}
2021#endif /* IN_RING3 */
2022
2023#ifdef E1K_WITH_RXD_CACHE
2024
2025/**
2026 * Return the number of RX descriptor that belong to the hardware.
2027 *
2028 * @returns the number of available descriptors in RX ring.
2029 * @param pThis The device state structure.
2030 * @thread ???
2031 */
2032DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
2033{
2034 /**
2035 * Make sure RDT won't change during computation. EMT may modify RDT at
2036 * any moment.
2037 */
2038 uint32_t rdt = RDT;
2039 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
2040}
2041
2042DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
2043{
2044 return pThis->nRxDFetched > pThis->iRxDCurrent ?
2045 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
2046}
2047
2048DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
2049{
2050 return pThis->iRxDCurrent >= pThis->nRxDFetched;
2051}
2052
2053/**
2054 * Load receive descriptors from guest memory. The caller needs to be in Rx
2055 * critical section.
2056 *
2057 * We need two physical reads in case the tail wrapped around the end of RX
2058 * descriptor ring.
2059 *
2060 * @returns the actual number of descriptors fetched.
2061 * @param pThis The device state structure.
2062 * @param pDesc Pointer to descriptor union.
2063 * @param addr Physical address in guest context.
2064 * @thread EMT, RX
2065 */
2066DECLINLINE(unsigned) e1kRxDPrefetch(PE1KSTATE pThis)
2067{
2068 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
2069 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
2070 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
2071 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
2072 Assert(nDescsTotal != 0);
2073 if (nDescsTotal == 0)
2074 return 0;
2075 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
2076 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2077 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2078 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2079 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2080 nFirstNotLoaded, nDescsInSingleRead));
2081 if (nDescsToFetch == 0)
2082 return 0;
2083 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2084 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2085 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2086 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2087 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2088 // unsigned i, j;
2089 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2090 // {
2091 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2092 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2093 // }
2094 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2095 pThis->szPrf, nDescsInSingleRead,
2096 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
2097 nFirstNotLoaded, RDLEN, RDH, RDT));
2098 if (nDescsToFetch > nDescsInSingleRead)
2099 {
2100 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
2101 ((uint64_t)RDBAH << 32) + RDBAL,
2102 pFirstEmptyDesc + nDescsInSingleRead,
2103 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2104 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2105 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2106 // {
2107 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2108 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2109 // }
2110 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2111 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2112 RDBAH, RDBAL));
2113 }
2114 pThis->nRxDFetched += nDescsToFetch;
2115 return nDescsToFetch;
2116}
2117
2118# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2119
2120/**
2121 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2122 * RX ring if the cache is empty.
2123 *
2124 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2125 * go out of sync with RDH which will cause trouble when EMT checks if the
2126 * cache is empty to do pre-fetch @bugref(6217).
2127 *
2128 * @param pThis The device state structure.
2129 * @thread RX
2130 */
2131DECLINLINE(E1KRXDESC*) e1kRxDGet(PE1KSTATE pThis)
2132{
2133 Assert(e1kCsRxIsOwner(pThis));
2134 /* Check the cache first. */
2135 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2136 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2137 /* Cache is empty, reset it and check if we can fetch more. */
2138 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2139 if (e1kRxDPrefetch(pThis))
2140 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2141 /* Out of Rx descriptors. */
2142 return NULL;
2143}
2144
2145
2146/**
2147 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2148 * pointer. The descriptor gets written back to the RXD ring.
2149 *
2150 * @param pThis The device state structure.
2151 * @param pDesc The descriptor being "returned" to the RX ring.
2152 * @thread RX
2153 */
2154DECLINLINE(void) e1kRxDPut(PE1KSTATE pThis, E1KRXDESC* pDesc)
2155{
2156 Assert(e1kCsRxIsOwner(pThis));
2157 pThis->iRxDCurrent++;
2158 // Assert(pDesc >= pThis->aRxDescriptors);
2159 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2160 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2161 // uint32_t rdh = RDH;
2162 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2163 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2164 e1kDescAddr(RDBAH, RDBAL, RDH),
2165 pDesc, sizeof(E1KRXDESC));
2166 e1kAdvanceRDH(pThis);
2167 e1kPrintRDesc(pThis, pDesc);
2168}
2169
2170/**
2171 * Store a fragment of received packet at the specifed address.
2172 *
2173 * @param pThis The device state structure.
2174 * @param pDesc The next available RX descriptor.
2175 * @param pvBuf The fragment.
2176 * @param cb The size of the fragment.
2177 */
2178static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2179{
2180 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2181 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2182 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2183 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2184 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2185 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2186}
2187
2188# endif
2189
2190#else /* !E1K_WITH_RXD_CACHE */
2191
2192/**
2193 * Store a fragment of received packet that fits into the next available RX
2194 * buffer.
2195 *
2196 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2197 *
2198 * @param pThis The device state structure.
2199 * @param pDesc The next available RX descriptor.
2200 * @param pvBuf The fragment.
2201 * @param cb The size of the fragment.
2202 */
2203static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2204{
2205 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2206 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2207 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2208 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2209 /* Write back the descriptor */
2210 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2211 e1kPrintRDesc(pThis, pDesc);
2212 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2213 /* Advance head */
2214 e1kAdvanceRDH(pThis);
2215 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2216 if (pDesc->status.fEOP)
2217 {
2218 /* Complete packet has been stored -- it is time to let the guest know. */
2219#ifdef E1K_USE_RX_TIMERS
2220 if (RDTR)
2221 {
2222 /* Arm the timer to fire in RDTR usec (discard .024) */
2223 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2224 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2225 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2226 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2227 }
2228 else
2229 {
2230#endif
2231 /* 0 delay means immediate interrupt */
2232 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2233 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2234#ifdef E1K_USE_RX_TIMERS
2235 }
2236#endif
2237 }
2238 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2239}
2240
2241#endif /* !E1K_WITH_RXD_CACHE */
2242
2243/**
2244 * Returns true if it is a broadcast packet.
2245 *
2246 * @returns true if destination address indicates broadcast.
2247 * @param pvBuf The ethernet packet.
2248 */
2249DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2250{
2251 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2252 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2253}
2254
2255/**
2256 * Returns true if it is a multicast packet.
2257 *
2258 * @remarks returns true for broadcast packets as well.
2259 * @returns true if destination address indicates multicast.
2260 * @param pvBuf The ethernet packet.
2261 */
2262DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2263{
2264 return (*(char*)pvBuf) & 1;
2265}
2266
2267#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2268/**
2269 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2270 *
2271 * @remarks We emulate checksum offloading for major packets types only.
2272 *
2273 * @returns VBox status code.
2274 * @param pThis The device state structure.
2275 * @param pFrame The available data.
2276 * @param cb Number of bytes available in the buffer.
2277 * @param status Bit fields containing status info.
2278 */
2279static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2280{
2281 /** @todo
2282 * It is not safe to bypass checksum verification for packets coming
2283 * from real wire. We currently unable to tell where packets are
2284 * coming from so we tell the driver to ignore our checksum flags
2285 * and do verification in software.
2286 */
2287# if 0
2288 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2289
2290 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2291
2292 switch (uEtherType)
2293 {
2294 case 0x800: /* IPv4 */
2295 {
2296 pStatus->fIXSM = false;
2297 pStatus->fIPCS = true;
2298 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2299 /* TCP/UDP checksum offloading works with TCP and UDP only */
2300 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2301 break;
2302 }
2303 case 0x86DD: /* IPv6 */
2304 pStatus->fIXSM = false;
2305 pStatus->fIPCS = false;
2306 pStatus->fTCPCS = true;
2307 break;
2308 default: /* ARP, VLAN, etc. */
2309 pStatus->fIXSM = true;
2310 break;
2311 }
2312# else
2313 pStatus->fIXSM = true;
2314 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2315# endif
2316 return VINF_SUCCESS;
2317}
2318#endif /* IN_RING3 */
2319
2320/**
2321 * Pad and store received packet.
2322 *
2323 * @remarks Make sure that the packet appears to upper layer as one coming
2324 * from real Ethernet: pad it and insert FCS.
2325 *
2326 * @returns VBox status code.
2327 * @param pThis The device state structure.
2328 * @param pvBuf The available data.
2329 * @param cb Number of bytes available in the buffer.
2330 * @param status Bit fields containing status info.
2331 */
2332static int e1kHandleRxPacket(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2333{
2334#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2335 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2336 uint8_t *ptr = rxPacket;
2337
2338 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2339 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2340 return rc;
2341
2342 if (cb > 70) /* unqualified guess */
2343 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2344
2345 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2346 Assert(cb > 16);
2347 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2348 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2349 if (status.fVP)
2350 {
2351 /* VLAN packet -- strip VLAN tag in VLAN mode */
2352 if ((CTRL & CTRL_VME) && cb > 16)
2353 {
2354 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2355 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2356 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2357 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2358 cb -= 4;
2359 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2360 pThis->szPrf, status.u16Special, cb));
2361 }
2362 else
2363 status.fVP = false; /* Set VP only if we stripped the tag */
2364 }
2365 else
2366 memcpy(rxPacket, pvBuf, cb);
2367 /* Pad short packets */
2368 if (cb < 60)
2369 {
2370 memset(rxPacket + cb, 0, 60 - cb);
2371 cb = 60;
2372 }
2373 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2374 {
2375 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2376 /*
2377 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2378 * is ignored by most of drivers we may as well save us the trouble
2379 * of calculating it (see EthernetCRC CFGM parameter).
2380 */
2381 if (pThis->fEthernetCRC)
2382 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2383 cb += sizeof(uint32_t);
2384 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2385 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2386 }
2387 /* Compute checksum of complete packet */
2388 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2389 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2390
2391 /* Update stats */
2392 E1K_INC_CNT32(GPRC);
2393 if (e1kIsBroadcast(pvBuf))
2394 E1K_INC_CNT32(BPRC);
2395 else if (e1kIsMulticast(pvBuf))
2396 E1K_INC_CNT32(MPRC);
2397 /* Update octet receive counter */
2398 E1K_ADD_CNT64(GORCL, GORCH, cb);
2399 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2400 if (cb == 64)
2401 E1K_INC_CNT32(PRC64);
2402 else if (cb < 128)
2403 E1K_INC_CNT32(PRC127);
2404 else if (cb < 256)
2405 E1K_INC_CNT32(PRC255);
2406 else if (cb < 512)
2407 E1K_INC_CNT32(PRC511);
2408 else if (cb < 1024)
2409 E1K_INC_CNT32(PRC1023);
2410 else
2411 E1K_INC_CNT32(PRC1522);
2412
2413 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2414
2415# ifdef E1K_WITH_RXD_CACHE
2416 while (cb > 0)
2417 {
2418 E1KRXDESC *pDesc = e1kRxDGet(pThis);
2419
2420 if (pDesc == NULL)
2421 {
2422 E1kLog(("%s Out of receive buffers, dropping the packet "
2423 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2424 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2425 break;
2426 }
2427# else /* !E1K_WITH_RXD_CACHE */
2428 if (RDH == RDT)
2429 {
2430 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2431 pThis->szPrf));
2432 }
2433 /* Store the packet to receive buffers */
2434 while (RDH != RDT)
2435 {
2436 /* Load the descriptor pointed by head */
2437 E1KRXDESC desc, *pDesc = &desc;
2438 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2439 &desc, sizeof(desc));
2440# endif /* !E1K_WITH_RXD_CACHE */
2441 if (pDesc->u64BufAddr)
2442 {
2443 /* Update descriptor */
2444 pDesc->status = status;
2445 pDesc->u16Checksum = checksum;
2446 pDesc->status.fDD = true;
2447
2448 /*
2449 * We need to leave Rx critical section here or we risk deadlocking
2450 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2451 * page or has an access handler associated with it.
2452 * Note that it is safe to leave the critical section here since
2453 * e1kRegWriteRDT() never modifies RDH. It never touches already
2454 * fetched RxD cache entries either.
2455 */
2456 if (cb > pThis->u16RxBSize)
2457 {
2458 pDesc->status.fEOP = false;
2459 e1kCsRxLeave(pThis);
2460 e1kStoreRxFragment(pThis, pDesc, ptr, pThis->u16RxBSize);
2461 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2462 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2463 return rc;
2464 ptr += pThis->u16RxBSize;
2465 cb -= pThis->u16RxBSize;
2466 }
2467 else
2468 {
2469 pDesc->status.fEOP = true;
2470 e1kCsRxLeave(pThis);
2471 e1kStoreRxFragment(pThis, pDesc, ptr, cb);
2472# ifdef E1K_WITH_RXD_CACHE
2473 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2474 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2475 return rc;
2476 cb = 0;
2477# else /* !E1K_WITH_RXD_CACHE */
2478 pThis->led.Actual.s.fReading = 0;
2479 return VINF_SUCCESS;
2480# endif /* !E1K_WITH_RXD_CACHE */
2481 }
2482 /*
2483 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2484 * is not defined.
2485 */
2486 }
2487# ifdef E1K_WITH_RXD_CACHE
2488 /* Write back the descriptor. */
2489 pDesc->status.fDD = true;
2490 e1kRxDPut(pThis, pDesc);
2491# else /* !E1K_WITH_RXD_CACHE */
2492 else
2493 {
2494 /* Write back the descriptor. */
2495 pDesc->status.fDD = true;
2496 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2497 e1kDescAddr(RDBAH, RDBAL, RDH),
2498 pDesc, sizeof(E1KRXDESC));
2499 e1kAdvanceRDH(pThis);
2500 }
2501# endif /* !E1K_WITH_RXD_CACHE */
2502 }
2503
2504 if (cb > 0)
2505 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2506
2507 pThis->led.Actual.s.fReading = 0;
2508
2509 e1kCsRxLeave(pThis);
2510# ifdef E1K_WITH_RXD_CACHE
2511 /* Complete packet has been stored -- it is time to let the guest know. */
2512# ifdef E1K_USE_RX_TIMERS
2513 if (RDTR)
2514 {
2515 /* Arm the timer to fire in RDTR usec (discard .024) */
2516 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2517 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2518 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2519 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2520 }
2521 else
2522 {
2523# endif /* E1K_USE_RX_TIMERS */
2524 /* 0 delay means immediate interrupt */
2525 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2526 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2527# ifdef E1K_USE_RX_TIMERS
2528 }
2529# endif /* E1K_USE_RX_TIMERS */
2530# endif /* E1K_WITH_RXD_CACHE */
2531
2532 return VINF_SUCCESS;
2533#else /* !IN_RING3 */
2534 RT_NOREF_PV(pThis); RT_NOREF_PV(pvBuf); RT_NOREF_PV(cb); RT_NOREF_PV(status);
2535 return VERR_INTERNAL_ERROR_2;
2536#endif /* !IN_RING3 */
2537}
2538
2539
2540#ifdef IN_RING3
2541/**
2542 * Bring the link up after the configured delay, 5 seconds by default.
2543 *
2544 * @param pThis The device state structure.
2545 * @thread any
2546 */
2547DECLINLINE(void) e1kBringLinkUpDelayed(PE1KSTATE pThis)
2548{
2549 E1kLog(("%s Will bring up the link in %d seconds...\n",
2550 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2551 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
2552}
2553
2554/**
2555 * Bring up the link immediately.
2556 *
2557 * @param pThis The device state structure.
2558 */
2559DECLINLINE(void) e1kR3LinkUp(PE1KSTATE pThis)
2560{
2561 E1kLog(("%s Link is up\n", pThis->szPrf));
2562 STATUS |= STATUS_LU;
2563 Phy::setLinkStatus(&pThis->phy, true);
2564 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2565 if (pThis->pDrvR3)
2566 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_UP);
2567}
2568
2569/**
2570 * Bring down the link immediately.
2571 *
2572 * @param pThis The device state structure.
2573 */
2574DECLINLINE(void) e1kR3LinkDown(PE1KSTATE pThis)
2575{
2576 E1kLog(("%s Link is down\n", pThis->szPrf));
2577 STATUS &= ~STATUS_LU;
2578 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2579 if (pThis->pDrvR3)
2580 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2581}
2582
2583/**
2584 * Bring down the link temporarily.
2585 *
2586 * @param pThis The device state structure.
2587 */
2588DECLINLINE(void) e1kR3LinkDownTemp(PE1KSTATE pThis)
2589{
2590 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2591 STATUS &= ~STATUS_LU;
2592 Phy::setLinkStatus(&pThis->phy, false);
2593 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2594 /*
2595 * Notifying the associated driver that the link went down (even temporarily)
2596 * seems to be the right thing, but it was not done before. This may cause
2597 * a regression if the driver does not expect the link to go down as a result
2598 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2599 * of code notified the driver that the link was up! See @bugref{7057}.
2600 */
2601 if (pThis->pDrvR3)
2602 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2603 e1kBringLinkUpDelayed(pThis);
2604}
2605#endif /* IN_RING3 */
2606
2607#if 0 /* unused */
2608/**
2609 * Read handler for Device Status register.
2610 *
2611 * Get the link status from PHY.
2612 *
2613 * @returns VBox status code.
2614 *
2615 * @param pThis The device state structure.
2616 * @param offset Register offset in memory-mapped frame.
2617 * @param index Register index in register array.
2618 * @param mask Used to implement partial reads (8 and 16-bit).
2619 */
2620static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2621{
2622 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2623 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2624 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2625 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2626 {
2627 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2628 if (Phy::readMDIO(&pThis->phy))
2629 *pu32Value = CTRL | CTRL_MDIO;
2630 else
2631 *pu32Value = CTRL & ~CTRL_MDIO;
2632 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2633 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2634 }
2635 else
2636 {
2637 /* MDIO pin is used for output, ignore it */
2638 *pu32Value = CTRL;
2639 }
2640 return VINF_SUCCESS;
2641}
2642#endif /* unused */
2643
2644/**
2645 * Write handler for Device Control register.
2646 *
2647 * Handles reset.
2648 *
2649 * @param pThis The device state structure.
2650 * @param offset Register offset in memory-mapped frame.
2651 * @param index Register index in register array.
2652 * @param value The value to store.
2653 * @param mask Used to implement partial writes (8 and 16-bit).
2654 * @thread EMT
2655 */
2656static int e1kRegWriteCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2657{
2658 int rc = VINF_SUCCESS;
2659
2660 if (value & CTRL_RESET)
2661 { /* RST */
2662#ifndef IN_RING3
2663 return VINF_IOM_R3_MMIO_WRITE;
2664#else
2665 e1kHardReset(pThis);
2666#endif
2667 }
2668 else
2669 {
2670 /*
2671 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2672 * the link is down and the cable is connected, and if they are we
2673 * bring the link up, see @bugref{8624}.
2674 */
2675 if ( (value & CTRL_SLU)
2676 && !(CTRL & CTRL_SLU)
2677 && pThis->fCableConnected
2678 && !(STATUS & STATUS_LU))
2679 {
2680 /*
2681 * The driver indicates that we should bring up the link. Our default 5-second delay is too long,
2682 * as Linux guests detect Tx hang after 2 seconds. Let's use 500 ms delay instead. */
2683 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), E1K_INIT_LINKUP_DELAY);
2684 }
2685 if (value & CTRL_VME)
2686 {
2687 E1kLog(("%s VLAN Mode Enabled\n", pThis->szPrf));
2688 }
2689 E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2690 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2691 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2692 if (value & CTRL_MDC)
2693 {
2694 if (value & CTRL_MDIO_DIR)
2695 {
2696 E1kLog(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2697 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2698 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO));
2699 }
2700 else
2701 {
2702 if (Phy::readMDIO(&pThis->phy))
2703 value |= CTRL_MDIO;
2704 else
2705 value &= ~CTRL_MDIO;
2706 E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
2707 pThis->szPrf, !!(value & CTRL_MDIO)));
2708 }
2709 }
2710 rc = e1kRegWriteDefault(pThis, offset, index, value);
2711 }
2712
2713 return rc;
2714}
2715
2716/**
2717 * Write handler for EEPROM/Flash Control/Data register.
2718 *
2719 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2720 *
2721 * @param pThis The device state structure.
2722 * @param offset Register offset in memory-mapped frame.
2723 * @param index Register index in register array.
2724 * @param value The value to store.
2725 * @param mask Used to implement partial writes (8 and 16-bit).
2726 * @thread EMT
2727 */
2728static int e1kRegWriteEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2729{
2730 RT_NOREF(offset, index);
2731#ifdef IN_RING3
2732 /* So far we are concerned with lower byte only */
2733 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2734 {
2735 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2736 /* Note: 82543GC does not need to request EEPROM access */
2737 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2738 pThis->eeprom.write(value & EECD_EE_WIRES);
2739 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2740 }
2741 if (value & EECD_EE_REQ)
2742 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2743 else
2744 EECD &= ~EECD_EE_GNT;
2745 //e1kRegWriteDefault(pThis, offset, index, value );
2746
2747 return VINF_SUCCESS;
2748#else /* !IN_RING3 */
2749 RT_NOREF(pThis, value);
2750 return VINF_IOM_R3_MMIO_WRITE;
2751#endif /* !IN_RING3 */
2752}
2753
2754/**
2755 * Read handler for EEPROM/Flash Control/Data register.
2756 *
2757 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2758 *
2759 * @returns VBox status code.
2760 *
2761 * @param pThis The device state structure.
2762 * @param offset Register offset in memory-mapped frame.
2763 * @param index Register index in register array.
2764 * @param mask Used to implement partial reads (8 and 16-bit).
2765 * @thread EMT
2766 */
2767static int e1kRegReadEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2768{
2769#ifdef IN_RING3
2770 uint32_t value;
2771 int rc = e1kRegReadDefault(pThis, offset, index, &value);
2772 if (RT_SUCCESS(rc))
2773 {
2774 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2775 {
2776 /* Note: 82543GC does not need to request EEPROM access */
2777 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2778 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2779 value |= pThis->eeprom.read();
2780 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2781 }
2782 *pu32Value = value;
2783 }
2784
2785 return rc;
2786#else /* !IN_RING3 */
2787 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
2788 return VINF_IOM_R3_MMIO_READ;
2789#endif /* !IN_RING3 */
2790}
2791
2792/**
2793 * Write handler for EEPROM Read register.
2794 *
2795 * Handles EEPROM word access requests, reads EEPROM and stores the result
2796 * into DATA field.
2797 *
2798 * @param pThis The device state structure.
2799 * @param offset Register offset in memory-mapped frame.
2800 * @param index Register index in register array.
2801 * @param value The value to store.
2802 * @param mask Used to implement partial writes (8 and 16-bit).
2803 * @thread EMT
2804 */
2805static int e1kRegWriteEERD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2806{
2807#ifdef IN_RING3
2808 /* Make use of 'writable' and 'readable' masks. */
2809 e1kRegWriteDefault(pThis, offset, index, value);
2810 /* DONE and DATA are set only if read was triggered by START. */
2811 if (value & EERD_START)
2812 {
2813 uint16_t tmp;
2814 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2815 if (pThis->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2816 SET_BITS(EERD, DATA, tmp);
2817 EERD |= EERD_DONE;
2818 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2819 }
2820
2821 return VINF_SUCCESS;
2822#else /* !IN_RING3 */
2823 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
2824 return VINF_IOM_R3_MMIO_WRITE;
2825#endif /* !IN_RING3 */
2826}
2827
2828
2829/**
2830 * Write handler for MDI Control register.
2831 *
2832 * Handles PHY read/write requests; forwards requests to internal PHY device.
2833 *
2834 * @param pThis The device state structure.
2835 * @param offset Register offset in memory-mapped frame.
2836 * @param index Register index in register array.
2837 * @param value The value to store.
2838 * @param mask Used to implement partial writes (8 and 16-bit).
2839 * @thread EMT
2840 */
2841static int e1kRegWriteMDIC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2842{
2843 if (value & MDIC_INT_EN)
2844 {
2845 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2846 pThis->szPrf));
2847 }
2848 else if (value & MDIC_READY)
2849 {
2850 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2851 pThis->szPrf));
2852 }
2853 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2854 {
2855 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
2856 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
2857 /*
2858 * Some drivers scan the MDIO bus for a PHY. We can work with these
2859 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
2860 * at the requested address, see @bugref{7346}.
2861 */
2862 MDIC = MDIC_READY | MDIC_ERROR;
2863 }
2864 else
2865 {
2866 /* Store the value */
2867 e1kRegWriteDefault(pThis, offset, index, value);
2868 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
2869 /* Forward op to PHY */
2870 if (value & MDIC_OP_READ)
2871 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG)));
2872 else
2873 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2874 /* Let software know that we are done */
2875 MDIC |= MDIC_READY;
2876 }
2877
2878 return VINF_SUCCESS;
2879}
2880
2881/**
2882 * Write handler for Interrupt Cause Read register.
2883 *
2884 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2885 *
2886 * @param pThis The device state structure.
2887 * @param offset Register offset in memory-mapped frame.
2888 * @param index Register index in register array.
2889 * @param value The value to store.
2890 * @param mask Used to implement partial writes (8 and 16-bit).
2891 * @thread EMT
2892 */
2893static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2894{
2895 ICR &= ~value;
2896
2897 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
2898 return VINF_SUCCESS;
2899}
2900
2901/**
2902 * Read handler for Interrupt Cause Read register.
2903 *
2904 * Reading this register acknowledges all interrupts.
2905 *
2906 * @returns VBox status code.
2907 *
2908 * @param pThis The device state structure.
2909 * @param offset Register offset in memory-mapped frame.
2910 * @param index Register index in register array.
2911 * @param mask Not used.
2912 * @thread EMT
2913 */
2914static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2915{
2916 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
2917 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2918 return rc;
2919
2920 uint32_t value = 0;
2921 rc = e1kRegReadDefault(pThis, offset, index, &value);
2922 if (RT_SUCCESS(rc))
2923 {
2924 if (value)
2925 {
2926 if (!pThis->fIntRaised)
2927 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
2928 /*
2929 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
2930 * with disabled interrupts.
2931 */
2932 //if (IMS)
2933 if (1)
2934 {
2935 /*
2936 * Interrupts were enabled -- we are supposedly at the very
2937 * beginning of interrupt handler
2938 */
2939 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
2940 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
2941 /* Clear all pending interrupts */
2942 ICR = 0;
2943 pThis->fIntRaised = false;
2944 /* Lower(0) INTA(0) */
2945 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
2946
2947 pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
2948 if (pThis->fIntMaskUsed)
2949 pThis->fDelayInts = true;
2950 }
2951 else
2952 {
2953 /*
2954 * Interrupts are disabled -- in windows guests ICR read is done
2955 * just before re-enabling interrupts
2956 */
2957 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
2958 }
2959 }
2960 *pu32Value = value;
2961 }
2962 e1kCsLeave(pThis);
2963
2964 return rc;
2965}
2966
2967/**
2968 * Write handler for Interrupt Cause Set register.
2969 *
2970 * Bits corresponding to 1s in 'value' will be set in ICR register.
2971 *
2972 * @param pThis The device state structure.
2973 * @param offset Register offset in memory-mapped frame.
2974 * @param index Register index in register array.
2975 * @param value The value to store.
2976 * @param mask Used to implement partial writes (8 and 16-bit).
2977 * @thread EMT
2978 */
2979static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2980{
2981 RT_NOREF_PV(offset); RT_NOREF_PV(index);
2982 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
2983 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
2984}
2985
2986/**
2987 * Write handler for Interrupt Mask Set register.
2988 *
2989 * Will trigger pending interrupts.
2990 *
2991 * @param pThis The device state structure.
2992 * @param offset Register offset in memory-mapped frame.
2993 * @param index Register index in register array.
2994 * @param value The value to store.
2995 * @param mask Used to implement partial writes (8 and 16-bit).
2996 * @thread EMT
2997 */
2998static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2999{
3000 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3001
3002 IMS |= value;
3003 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3004 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3005 /*
3006 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3007 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3008 */
3009 if ((ICR & IMS) && !pThis->fLocked)
3010 {
3011 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3012 e1kPostponeInterrupt(pThis, E1K_IMS_INT_DELAY_NS);
3013 }
3014
3015 return VINF_SUCCESS;
3016}
3017
3018/**
3019 * Write handler for Interrupt Mask Clear register.
3020 *
3021 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3022 *
3023 * @param pThis The device state structure.
3024 * @param offset Register offset in memory-mapped frame.
3025 * @param index Register index in register array.
3026 * @param value The value to store.
3027 * @param mask Used to implement partial writes (8 and 16-bit).
3028 * @thread EMT
3029 */
3030static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3031{
3032 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3033
3034 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3035 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3036 return rc;
3037 if (pThis->fIntRaised)
3038 {
3039 /*
3040 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3041 * Windows to freeze since it may receive an interrupt while still in the very beginning
3042 * of interrupt handler.
3043 */
3044 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3045 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3046 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3047 /* Lower(0) INTA(0) */
3048 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
3049 pThis->fIntRaised = false;
3050 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3051 }
3052 IMS &= ~value;
3053 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3054 e1kCsLeave(pThis);
3055
3056 return VINF_SUCCESS;
3057}
3058
3059/**
3060 * Write handler for Receive Control register.
3061 *
3062 * @param pThis The device state structure.
3063 * @param offset Register offset in memory-mapped frame.
3064 * @param index Register index in register array.
3065 * @param value The value to store.
3066 * @param mask Used to implement partial writes (8 and 16-bit).
3067 * @thread EMT
3068 */
3069static int e1kRegWriteRCTL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3070{
3071 /* Update promiscuous mode */
3072 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3073 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3074 {
3075 /* Promiscuity has changed, pass the knowledge on. */
3076#ifndef IN_RING3
3077 return VINF_IOM_R3_MMIO_WRITE;
3078#else
3079 if (pThis->pDrvR3)
3080 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, fBecomePromiscous);
3081#endif
3082 }
3083
3084 /* Adjust receive buffer size */
3085 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3086 if (value & RCTL_BSEX)
3087 cbRxBuf *= 16;
3088 if (cbRxBuf != pThis->u16RxBSize)
3089 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3090 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3091 pThis->u16RxBSize = cbRxBuf;
3092
3093 /* Update the register */
3094 e1kRegWriteDefault(pThis, offset, index, value);
3095
3096 return VINF_SUCCESS;
3097}
3098
3099/**
3100 * Write handler for Packet Buffer Allocation register.
3101 *
3102 * TXA = 64 - RXA.
3103 *
3104 * @param pThis The device state structure.
3105 * @param offset Register offset in memory-mapped frame.
3106 * @param index Register index in register array.
3107 * @param value The value to store.
3108 * @param mask Used to implement partial writes (8 and 16-bit).
3109 * @thread EMT
3110 */
3111static int e1kRegWritePBA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3112{
3113 e1kRegWriteDefault(pThis, offset, index, value);
3114 PBA_st->txa = 64 - PBA_st->rxa;
3115
3116 return VINF_SUCCESS;
3117}
3118
3119/**
3120 * Write handler for Receive Descriptor Tail register.
3121 *
3122 * @remarks Write into RDT forces switch to HC and signal to
3123 * e1kR3NetworkDown_WaitReceiveAvail().
3124 *
3125 * @returns VBox status code.
3126 *
3127 * @param pThis The device state structure.
3128 * @param offset Register offset in memory-mapped frame.
3129 * @param index Register index in register array.
3130 * @param value The value to store.
3131 * @param mask Used to implement partial writes (8 and 16-bit).
3132 * @thread EMT
3133 */
3134static int e1kRegWriteRDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3135{
3136#ifndef IN_RING3
3137 /* XXX */
3138// return VINF_IOM_R3_MMIO_WRITE;
3139#endif
3140 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3141 if (RT_LIKELY(rc == VINF_SUCCESS))
3142 {
3143 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3144 /*
3145 * Some drivers advance RDT too far, so that it equals RDH. This
3146 * somehow manages to work with real hardware but not with this
3147 * emulated device. We can work with these drivers if we just
3148 * write 1 less when we see a driver writing RDT equal to RDH,
3149 * see @bugref{7346}.
3150 */
3151 if (value == RDH)
3152 {
3153 if (RDH == 0)
3154 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3155 else
3156 value = RDH - 1;
3157 }
3158 rc = e1kRegWriteDefault(pThis, offset, index, value);
3159#ifdef E1K_WITH_RXD_CACHE
3160 /*
3161 * We need to fetch descriptors now as RDT may go whole circle
3162 * before we attempt to store a received packet. For example,
3163 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3164 * size being only 8 descriptors! Note that we fetch descriptors
3165 * only when the cache is empty to reduce the number of memory reads
3166 * in case of frequent RDT writes. Don't fetch anything when the
3167 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3168 * messed up state.
3169 * Note that despite the cache may seem empty, meaning that there are
3170 * no more available descriptors in it, it may still be used by RX
3171 * thread which has not yet written the last descriptor back but has
3172 * temporarily released the RX lock in order to write the packet body
3173 * to descriptor's buffer. At this point we still going to do prefetch
3174 * but it won't actually fetch anything if there are no unused slots in
3175 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3176 * reset the cache here even if it appears empty. It will be reset at
3177 * a later point in e1kRxDGet().
3178 */
3179 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3180 e1kRxDPrefetch(pThis);
3181#endif /* E1K_WITH_RXD_CACHE */
3182 e1kCsRxLeave(pThis);
3183 if (RT_SUCCESS(rc))
3184 {
3185/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
3186 * without requiring any context switches. We should also check the
3187 * wait condition before bothering to queue the item as we're currently
3188 * queuing thousands of items per second here in a normal transmit
3189 * scenario. Expect performance changes when fixing this! */
3190#ifdef IN_RING3
3191 /* Signal that we have more receive descriptors available. */
3192 e1kWakeupReceive(pThis->CTX_SUFF(pDevIns));
3193#else
3194 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
3195 if (pItem)
3196 PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
3197#endif
3198 }
3199 }
3200 return rc;
3201}
3202
3203/**
3204 * Write handler for Receive Delay Timer register.
3205 *
3206 * @param pThis The device state structure.
3207 * @param offset Register offset in memory-mapped frame.
3208 * @param index Register index in register array.
3209 * @param value The value to store.
3210 * @param mask Used to implement partial writes (8 and 16-bit).
3211 * @thread EMT
3212 */
3213static int e1kRegWriteRDTR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3214{
3215 e1kRegWriteDefault(pThis, offset, index, value);
3216 if (value & RDTR_FPD)
3217 {
3218 /* Flush requested, cancel both timers and raise interrupt */
3219#ifdef E1K_USE_RX_TIMERS
3220 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3221 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3222#endif
3223 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3224 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3225 }
3226
3227 return VINF_SUCCESS;
3228}
3229
3230DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3231{
3232 /**
3233 * Make sure TDT won't change during computation. EMT may modify TDT at
3234 * any moment.
3235 */
3236 uint32_t tdt = TDT;
3237 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3238}
3239
3240#ifdef IN_RING3
3241
3242# ifdef E1K_TX_DELAY
3243/**
3244 * Transmit Delay Timer handler.
3245 *
3246 * @remarks We only get here when the timer expires.
3247 *
3248 * @param pDevIns Pointer to device instance structure.
3249 * @param pTimer Pointer to the timer.
3250 * @param pvUser NULL.
3251 * @thread EMT
3252 */
3253static DECLCALLBACK(void) e1kTxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3254{
3255 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3256 Assert(PDMCritSectIsOwner(&pThis->csTx));
3257
3258 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3259# ifdef E1K_INT_STATS
3260 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3261 if (u64Elapsed > pThis->uStatMaxTxDelay)
3262 pThis->uStatMaxTxDelay = u64Elapsed;
3263# endif
3264 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
3265 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3266}
3267# endif /* E1K_TX_DELAY */
3268
3269//# ifdef E1K_USE_TX_TIMERS
3270
3271/**
3272 * Transmit Interrupt Delay Timer handler.
3273 *
3274 * @remarks We only get here when the timer expires.
3275 *
3276 * @param pDevIns Pointer to device instance structure.
3277 * @param pTimer Pointer to the timer.
3278 * @param pvUser NULL.
3279 * @thread EMT
3280 */
3281static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3282{
3283 RT_NOREF(pDevIns);
3284 RT_NOREF(pTimer);
3285 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3286
3287 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3288 /* Cancel absolute delay timer as we have already got attention */
3289# ifndef E1K_NO_TAD
3290 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
3291# endif
3292 e1kRaiseInterrupt(pThis, ICR_TXDW);
3293}
3294
3295/**
3296 * Transmit Absolute Delay Timer handler.
3297 *
3298 * @remarks We only get here when the timer expires.
3299 *
3300 * @param pDevIns Pointer to device instance structure.
3301 * @param pTimer Pointer to the timer.
3302 * @param pvUser NULL.
3303 * @thread EMT
3304 */
3305static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3306{
3307 RT_NOREF(pDevIns);
3308 RT_NOREF(pTimer);
3309 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3310
3311 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3312 /* Cancel interrupt delay timer as we have already got attention */
3313 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
3314 e1kRaiseInterrupt(pThis, ICR_TXDW);
3315}
3316
3317//# endif /* E1K_USE_TX_TIMERS */
3318# ifdef E1K_USE_RX_TIMERS
3319
3320/**
3321 * Receive Interrupt Delay Timer handler.
3322 *
3323 * @remarks We only get here when the timer expires.
3324 *
3325 * @param pDevIns Pointer to device instance structure.
3326 * @param pTimer Pointer to the timer.
3327 * @param pvUser NULL.
3328 * @thread EMT
3329 */
3330static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3331{
3332 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3333
3334 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3335 /* Cancel absolute delay timer as we have already got attention */
3336 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3337 e1kRaiseInterrupt(pThis, ICR_RXT0);
3338}
3339
3340/**
3341 * Receive Absolute Delay Timer handler.
3342 *
3343 * @remarks We only get here when the timer expires.
3344 *
3345 * @param pDevIns Pointer to device instance structure.
3346 * @param pTimer Pointer to the timer.
3347 * @param pvUser NULL.
3348 * @thread EMT
3349 */
3350static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3351{
3352 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3353
3354 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3355 /* Cancel interrupt delay timer as we have already got attention */
3356 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3357 e1kRaiseInterrupt(pThis, ICR_RXT0);
3358}
3359
3360# endif /* E1K_USE_RX_TIMERS */
3361
3362/**
3363 * Late Interrupt Timer handler.
3364 *
3365 * @param pDevIns Pointer to device instance structure.
3366 * @param pTimer Pointer to the timer.
3367 * @param pvUser NULL.
3368 * @thread EMT
3369 */
3370static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3371{
3372 RT_NOREF(pDevIns, pTimer);
3373 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3374
3375 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3376 STAM_COUNTER_INC(&pThis->StatLateInts);
3377 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3378# if 0
3379 if (pThis->iStatIntLost > -100)
3380 pThis->iStatIntLost--;
3381# endif
3382 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, 0);
3383 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3384}
3385
3386/**
3387 * Link Up Timer handler.
3388 *
3389 * @param pDevIns Pointer to device instance structure.
3390 * @param pTimer Pointer to the timer.
3391 * @param pvUser NULL.
3392 * @thread EMT
3393 */
3394static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3395{
3396 RT_NOREF(pDevIns, pTimer);
3397 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3398
3399 /*
3400 * This can happen if we set the link status to down when the Link up timer was
3401 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3402 * and connect+disconnect the cable very quick.
3403 */
3404 if (!pThis->fCableConnected)
3405 return;
3406
3407 e1kR3LinkUp(pThis);
3408}
3409
3410#endif /* IN_RING3 */
3411
3412/**
3413 * Sets up the GSO context according to the TSE new context descriptor.
3414 *
3415 * @param pGso The GSO context to setup.
3416 * @param pCtx The context descriptor.
3417 */
3418DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3419{
3420 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3421
3422 /*
3423 * See if the context descriptor describes something that could be TCP or
3424 * UDP over IPv[46].
3425 */
3426 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3427 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3428 {
3429 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3430 return;
3431 }
3432 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3433 {
3434 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3435 return;
3436 }
3437 if (RT_UNLIKELY( pCtx->dw2.fTCP
3438 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3439 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3440 {
3441 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3442 return;
3443 }
3444
3445 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3446 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3447 {
3448 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3449 return;
3450 }
3451
3452 /* IPv4 checksum offset. */
3453 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3454 {
3455 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3456 return;
3457 }
3458
3459 /* TCP/UDP checksum offsets. */
3460 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3461 != ( pCtx->dw2.fTCP
3462 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3463 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3464 {
3465 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3466 return;
3467 }
3468
3469 /*
3470 * Because of internal networking using a 16-bit size field for GSO context
3471 * plus frame, we have to make sure we don't exceed this.
3472 */
3473 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3474 {
3475 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3476 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3477 return;
3478 }
3479
3480 /*
3481 * We're good for now - we'll do more checks when seeing the data.
3482 * So, figure the type of offloading and setup the context.
3483 */
3484 if (pCtx->dw2.fIP)
3485 {
3486 if (pCtx->dw2.fTCP)
3487 {
3488 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3489 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3490 }
3491 else
3492 {
3493 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3494 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3495 }
3496 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3497 * this yet it seems)... */
3498 }
3499 else
3500 {
3501 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3502 if (pCtx->dw2.fTCP)
3503 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3504 else
3505 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3506 }
3507 pGso->offHdr1 = pCtx->ip.u8CSS;
3508 pGso->offHdr2 = pCtx->tu.u8CSS;
3509 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3510 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3511 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3512 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3513 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3514}
3515
3516/**
3517 * Checks if we can use GSO processing for the current TSE frame.
3518 *
3519 * @param pThis The device state structure.
3520 * @param pGso The GSO context.
3521 * @param pData The first data descriptor of the frame.
3522 * @param pCtx The TSO context descriptor.
3523 */
3524DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3525{
3526 if (!pData->cmd.fTSE)
3527 {
3528 E1kLog2(("e1kCanDoGso: !TSE\n"));
3529 return false;
3530 }
3531 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3532 {
3533 E1kLog(("e1kCanDoGso: VLE\n"));
3534 return false;
3535 }
3536 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3537 {
3538 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3539 return false;
3540 }
3541
3542 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3543 {
3544 case PDMNETWORKGSOTYPE_IPV4_TCP:
3545 case PDMNETWORKGSOTYPE_IPV4_UDP:
3546 if (!pData->dw3.fIXSM)
3547 {
3548 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3549 return false;
3550 }
3551 if (!pData->dw3.fTXSM)
3552 {
3553 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3554 return false;
3555 }
3556 /** @todo what more check should we perform here? Ethernet frame type? */
3557 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3558 return true;
3559
3560 case PDMNETWORKGSOTYPE_IPV6_TCP:
3561 case PDMNETWORKGSOTYPE_IPV6_UDP:
3562 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3563 {
3564 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3565 return false;
3566 }
3567 if (!pData->dw3.fTXSM)
3568 {
3569 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3570 return false;
3571 }
3572 /** @todo what more check should we perform here? Ethernet frame type? */
3573 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3574 return true;
3575
3576 default:
3577 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3578 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3579 return false;
3580 }
3581}
3582
3583/**
3584 * Frees the current xmit buffer.
3585 *
3586 * @param pThis The device state structure.
3587 */
3588static void e1kXmitFreeBuf(PE1KSTATE pThis)
3589{
3590 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3591 if (pSg)
3592 {
3593 pThis->CTX_SUFF(pTxSg) = NULL;
3594
3595 if (pSg->pvAllocator != pThis)
3596 {
3597 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3598 if (pDrv)
3599 pDrv->pfnFreeBuf(pDrv, pSg);
3600 }
3601 else
3602 {
3603 /* loopback */
3604 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3605 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3606 pSg->fFlags = 0;
3607 pSg->pvAllocator = NULL;
3608 }
3609 }
3610}
3611
3612#ifndef E1K_WITH_TXD_CACHE
3613/**
3614 * Allocates an xmit buffer.
3615 *
3616 * @returns See PDMINETWORKUP::pfnAllocBuf.
3617 * @param pThis The device state structure.
3618 * @param cbMin The minimum frame size.
3619 * @param fExactSize Whether cbMin is exact or if we have to max it
3620 * out to the max MTU size.
3621 * @param fGso Whether this is a GSO frame or not.
3622 */
3623DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, size_t cbMin, bool fExactSize, bool fGso)
3624{
3625 /* Adjust cbMin if necessary. */
3626 if (!fExactSize)
3627 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3628
3629 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3630 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3631 e1kXmitFreeBuf(pThis);
3632 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3633
3634 /*
3635 * Allocate the buffer.
3636 */
3637 PPDMSCATTERGATHER pSg;
3638 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3639 {
3640 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3641 if (RT_UNLIKELY(!pDrv))
3642 return VERR_NET_DOWN;
3643 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3644 if (RT_FAILURE(rc))
3645 {
3646 /* Suspend TX as we are out of buffers atm */
3647 STATUS |= STATUS_TXOFF;
3648 return rc;
3649 }
3650 }
3651 else
3652 {
3653 /* Create a loopback using the fallback buffer and preallocated SG. */
3654 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3655 pSg = &pThis->uTxFallback.Sg;
3656 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3657 pSg->cbUsed = 0;
3658 pSg->cbAvailable = 0;
3659 pSg->pvAllocator = pThis;
3660 pSg->pvUser = NULL; /* No GSO here. */
3661 pSg->cSegs = 1;
3662 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3663 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3664 }
3665
3666 pThis->CTX_SUFF(pTxSg) = pSg;
3667 return VINF_SUCCESS;
3668}
3669#else /* E1K_WITH_TXD_CACHE */
3670/**
3671 * Allocates an xmit buffer.
3672 *
3673 * @returns See PDMINETWORKUP::pfnAllocBuf.
3674 * @param pThis The device state structure.
3675 * @param cbMin The minimum frame size.
3676 * @param fExactSize Whether cbMin is exact or if we have to max it
3677 * out to the max MTU size.
3678 * @param fGso Whether this is a GSO frame or not.
3679 */
3680DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, bool fGso)
3681{
3682 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3683 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3684 e1kXmitFreeBuf(pThis);
3685 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3686
3687 /*
3688 * Allocate the buffer.
3689 */
3690 PPDMSCATTERGATHER pSg;
3691 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3692 {
3693 if (pThis->cbTxAlloc == 0)
3694 {
3695 /* Zero packet, no need for the buffer */
3696 return VINF_SUCCESS;
3697 }
3698
3699 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3700 if (RT_UNLIKELY(!pDrv))
3701 return VERR_NET_DOWN;
3702 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3703 if (RT_FAILURE(rc))
3704 {
3705 /* Suspend TX as we are out of buffers atm */
3706 STATUS |= STATUS_TXOFF;
3707 return rc;
3708 }
3709 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3710 pThis->szPrf, pThis->cbTxAlloc,
3711 pThis->fVTag ? "VLAN " : "",
3712 pThis->fGSO ? "GSO " : ""));
3713 pThis->cbTxAlloc = 0;
3714 }
3715 else
3716 {
3717 /* Create a loopback using the fallback buffer and preallocated SG. */
3718 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3719 pSg = &pThis->uTxFallback.Sg;
3720 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3721 pSg->cbUsed = 0;
3722 pSg->cbAvailable = 0;
3723 pSg->pvAllocator = pThis;
3724 pSg->pvUser = NULL; /* No GSO here. */
3725 pSg->cSegs = 1;
3726 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3727 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3728 }
3729
3730 pThis->CTX_SUFF(pTxSg) = pSg;
3731 return VINF_SUCCESS;
3732}
3733#endif /* E1K_WITH_TXD_CACHE */
3734
3735/**
3736 * Checks if it's a GSO buffer or not.
3737 *
3738 * @returns true / false.
3739 * @param pTxSg The scatter / gather buffer.
3740 */
3741DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3742{
3743#if 0
3744 if (!pTxSg)
3745 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3746 if (pTxSg && pTxSg->pvUser)
3747 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3748#endif
3749 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3750}
3751
3752#ifndef E1K_WITH_TXD_CACHE
3753/**
3754 * Load transmit descriptor from guest memory.
3755 *
3756 * @param pThis The device state structure.
3757 * @param pDesc Pointer to descriptor union.
3758 * @param addr Physical address in guest context.
3759 * @thread E1000_TX
3760 */
3761DECLINLINE(void) e1kLoadDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3762{
3763 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3764}
3765#else /* E1K_WITH_TXD_CACHE */
3766/**
3767 * Load transmit descriptors from guest memory.
3768 *
3769 * We need two physical reads in case the tail wrapped around the end of TX
3770 * descriptor ring.
3771 *
3772 * @returns the actual number of descriptors fetched.
3773 * @param pThis The device state structure.
3774 * @param pDesc Pointer to descriptor union.
3775 * @param addr Physical address in guest context.
3776 * @thread E1000_TX
3777 */
3778DECLINLINE(unsigned) e1kTxDLoadMore(PE1KSTATE pThis)
3779{
3780 Assert(pThis->iTxDCurrent == 0);
3781 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3782 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3783 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3784 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3785 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3786 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3787 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u "
3788 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3789 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3790 nFirstNotLoaded, nDescsInSingleRead));
3791 if (nDescsToFetch == 0)
3792 return 0;
3793 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3794 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3795 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3796 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3797 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3798 pThis->szPrf, nDescsInSingleRead,
3799 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3800 nFirstNotLoaded, TDLEN, TDH, TDT));
3801 if (nDescsToFetch > nDescsInSingleRead)
3802 {
3803 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3804 ((uint64_t)TDBAH << 32) + TDBAL,
3805 pFirstEmptyDesc + nDescsInSingleRead,
3806 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3807 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3808 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3809 TDBAH, TDBAL));
3810 }
3811 pThis->nTxDFetched += nDescsToFetch;
3812 return nDescsToFetch;
3813}
3814
3815/**
3816 * Load transmit descriptors from guest memory only if there are no loaded
3817 * descriptors.
3818 *
3819 * @returns true if there are descriptors in cache.
3820 * @param pThis The device state structure.
3821 * @param pDesc Pointer to descriptor union.
3822 * @param addr Physical address in guest context.
3823 * @thread E1000_TX
3824 */
3825DECLINLINE(bool) e1kTxDLazyLoad(PE1KSTATE pThis)
3826{
3827 if (pThis->nTxDFetched == 0)
3828 return e1kTxDLoadMore(pThis) != 0;
3829 return true;
3830}
3831#endif /* E1K_WITH_TXD_CACHE */
3832
3833/**
3834 * Write back transmit descriptor to guest memory.
3835 *
3836 * @param pThis The device state structure.
3837 * @param pDesc Pointer to descriptor union.
3838 * @param addr Physical address in guest context.
3839 * @thread E1000_TX
3840 */
3841DECLINLINE(void) e1kWriteBackDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3842{
3843 /* Only the last half of the descriptor has to be written back. */
3844 e1kPrintTDesc(pThis, pDesc, "^^^");
3845 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3846}
3847
3848/**
3849 * Transmit complete frame.
3850 *
3851 * @remarks We skip the FCS since we're not responsible for sending anything to
3852 * a real ethernet wire.
3853 *
3854 * @param pThis The device state structure.
3855 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3856 * @thread E1000_TX
3857 */
3858static void e1kTransmitFrame(PE1KSTATE pThis, bool fOnWorkerThread)
3859{
3860 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3861 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
3862 Assert(!pSg || pSg->cSegs == 1);
3863
3864 if (cbFrame > 70) /* unqualified guess */
3865 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
3866
3867#ifdef E1K_INT_STATS
3868 if (cbFrame <= 1514)
3869 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
3870 else if (cbFrame <= 2962)
3871 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
3872 else if (cbFrame <= 4410)
3873 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
3874 else if (cbFrame <= 5858)
3875 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
3876 else if (cbFrame <= 7306)
3877 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
3878 else if (cbFrame <= 8754)
3879 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
3880 else if (cbFrame <= 16384)
3881 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
3882 else if (cbFrame <= 32768)
3883 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
3884 else
3885 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
3886#endif /* E1K_INT_STATS */
3887
3888 /* Add VLAN tag */
3889 if (cbFrame > 12 && pThis->fVTag)
3890 {
3891 E1kLog3(("%s Inserting VLAN tag %08x\n",
3892 pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
3893 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
3894 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
3895 pSg->cbUsed += 4;
3896 cbFrame += 4;
3897 Assert(pSg->cbUsed == cbFrame);
3898 Assert(pSg->cbUsed <= pSg->cbAvailable);
3899 }
3900/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
3901 "%.*Rhxd\n"
3902 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
3903 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
3904
3905 /* Update the stats */
3906 E1K_INC_CNT32(TPT);
3907 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3908 E1K_INC_CNT32(GPTC);
3909 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3910 E1K_INC_CNT32(BPTC);
3911 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3912 E1K_INC_CNT32(MPTC);
3913 /* Update octet transmit counter */
3914 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3915 if (pThis->CTX_SUFF(pDrv))
3916 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
3917 if (cbFrame == 64)
3918 E1K_INC_CNT32(PTC64);
3919 else if (cbFrame < 128)
3920 E1K_INC_CNT32(PTC127);
3921 else if (cbFrame < 256)
3922 E1K_INC_CNT32(PTC255);
3923 else if (cbFrame < 512)
3924 E1K_INC_CNT32(PTC511);
3925 else if (cbFrame < 1024)
3926 E1K_INC_CNT32(PTC1023);
3927 else
3928 E1K_INC_CNT32(PTC1522);
3929
3930 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
3931
3932 /*
3933 * Dump and send the packet.
3934 */
3935 int rc = VERR_NET_DOWN;
3936 if (pSg && pSg->pvAllocator != pThis)
3937 {
3938 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
3939
3940 pThis->CTX_SUFF(pTxSg) = NULL;
3941 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3942 if (pDrv)
3943 {
3944 /* Release critical section to avoid deadlock in CanReceive */
3945 //e1kCsLeave(pThis);
3946 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3947 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
3948 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
3949 //e1kCsEnter(pThis, RT_SRC_POS);
3950 }
3951 }
3952 else if (pSg)
3953 {
3954 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
3955 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
3956
3957 /** @todo do we actually need to check that we're in loopback mode here? */
3958 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
3959 {
3960 E1KRXDST status;
3961 RT_ZERO(status);
3962 status.fPIF = true;
3963 e1kHandleRxPacket(pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
3964 rc = VINF_SUCCESS;
3965 }
3966 e1kXmitFreeBuf(pThis);
3967 }
3968 else
3969 rc = VERR_NET_DOWN;
3970 if (RT_FAILURE(rc))
3971 {
3972 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
3973 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
3974 }
3975
3976 pThis->led.Actual.s.fWriting = 0;
3977}
3978
3979/**
3980 * Compute and write internet checksum (e1kCSum16) at the specified offset.
3981 *
3982 * @param pThis The device state structure.
3983 * @param pPkt Pointer to the packet.
3984 * @param u16PktLen Total length of the packet.
3985 * @param cso Offset in packet to write checksum at.
3986 * @param css Offset in packet to start computing
3987 * checksum from.
3988 * @param cse Offset in packet to stop computing
3989 * checksum at.
3990 * @thread E1000_TX
3991 */
3992static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
3993{
3994 RT_NOREF1(pThis);
3995
3996 if (css >= u16PktLen)
3997 {
3998 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
3999 pThis->szPrf, cso, u16PktLen));
4000 return;
4001 }
4002
4003 if (cso >= u16PktLen - 1)
4004 {
4005 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4006 pThis->szPrf, cso, u16PktLen));
4007 return;
4008 }
4009
4010 if (cse == 0)
4011 cse = u16PktLen - 1;
4012 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4013 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4014 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4015 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4016}
4017
4018/**
4019 * Add a part of descriptor's buffer to transmit frame.
4020 *
4021 * @remarks data.u64BufAddr is used unconditionally for both data
4022 * and legacy descriptors since it is identical to
4023 * legacy.u64BufAddr.
4024 *
4025 * @param pThis The device state structure.
4026 * @param pDesc Pointer to the descriptor to transmit.
4027 * @param u16Len Length of buffer to the end of segment.
4028 * @param fSend Force packet sending.
4029 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4030 * @thread E1000_TX
4031 */
4032#ifndef E1K_WITH_TXD_CACHE
4033static void e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4034{
4035 /* TCP header being transmitted */
4036 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4037 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4038 /* IP header being transmitted */
4039 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4040 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4041
4042 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4043 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4044 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4045
4046 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4047 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4048 E1kLog3(("%s Dump of the segment:\n"
4049 "%.*Rhxd\n"
4050 "%s --- End of dump ---\n",
4051 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4052 pThis->u16TxPktLen += u16Len;
4053 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4054 pThis->szPrf, pThis->u16TxPktLen));
4055 if (pThis->u16HdrRemain > 0)
4056 {
4057 /* The header was not complete, check if it is now */
4058 if (u16Len >= pThis->u16HdrRemain)
4059 {
4060 /* The rest is payload */
4061 u16Len -= pThis->u16HdrRemain;
4062 pThis->u16HdrRemain = 0;
4063 /* Save partial checksum and flags */
4064 pThis->u32SavedCsum = pTcpHdr->chksum;
4065 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4066 /* Clear FIN and PSH flags now and set them only in the last segment */
4067 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4068 }
4069 else
4070 {
4071 /* Still not */
4072 pThis->u16HdrRemain -= u16Len;
4073 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4074 pThis->szPrf, pThis->u16HdrRemain));
4075 return;
4076 }
4077 }
4078
4079 pThis->u32PayRemain -= u16Len;
4080
4081 if (fSend)
4082 {
4083 /* Leave ethernet header intact */
4084 /* IP Total Length = payload + headers - ethernet header */
4085 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4086 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4087 pThis->szPrf, ntohs(pIpHdr->total_len)));
4088 /* Update IP Checksum */
4089 pIpHdr->chksum = 0;
4090 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4091 pThis->contextTSE.ip.u8CSO,
4092 pThis->contextTSE.ip.u8CSS,
4093 pThis->contextTSE.ip.u16CSE);
4094
4095 /* Update TCP flags */
4096 /* Restore original FIN and PSH flags for the last segment */
4097 if (pThis->u32PayRemain == 0)
4098 {
4099 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4100 E1K_INC_CNT32(TSCTC);
4101 }
4102 /* Add TCP length to partial pseudo header sum */
4103 uint32_t csum = pThis->u32SavedCsum
4104 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4105 while (csum >> 16)
4106 csum = (csum >> 16) + (csum & 0xFFFF);
4107 pTcpHdr->chksum = csum;
4108 /* Compute final checksum */
4109 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4110 pThis->contextTSE.tu.u8CSO,
4111 pThis->contextTSE.tu.u8CSS,
4112 pThis->contextTSE.tu.u16CSE);
4113
4114 /*
4115 * Transmit it. If we've use the SG already, allocate a new one before
4116 * we copy of the data.
4117 */
4118 if (!pThis->CTX_SUFF(pTxSg))
4119 e1kXmitAllocBuf(pThis, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4120 if (pThis->CTX_SUFF(pTxSg))
4121 {
4122 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4123 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4124 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4125 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4126 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4127 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4128 }
4129 e1kTransmitFrame(pThis, fOnWorkerThread);
4130
4131 /* Update Sequence Number */
4132 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4133 - pThis->contextTSE.dw3.u8HDRLEN);
4134 /* Increment IP identification */
4135 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4136 }
4137}
4138#else /* E1K_WITH_TXD_CACHE */
4139static int e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4140{
4141 int rc = VINF_SUCCESS;
4142 /* TCP header being transmitted */
4143 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4144 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4145 /* IP header being transmitted */
4146 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4147 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4148
4149 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4150 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4151 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4152
4153 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4154 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4155 E1kLog3(("%s Dump of the segment:\n"
4156 "%.*Rhxd\n"
4157 "%s --- End of dump ---\n",
4158 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4159 pThis->u16TxPktLen += u16Len;
4160 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4161 pThis->szPrf, pThis->u16TxPktLen));
4162 if (pThis->u16HdrRemain > 0)
4163 {
4164 /* The header was not complete, check if it is now */
4165 if (u16Len >= pThis->u16HdrRemain)
4166 {
4167 /* The rest is payload */
4168 u16Len -= pThis->u16HdrRemain;
4169 pThis->u16HdrRemain = 0;
4170 /* Save partial checksum and flags */
4171 pThis->u32SavedCsum = pTcpHdr->chksum;
4172 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4173 /* Clear FIN and PSH flags now and set them only in the last segment */
4174 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4175 }
4176 else
4177 {
4178 /* Still not */
4179 pThis->u16HdrRemain -= u16Len;
4180 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4181 pThis->szPrf, pThis->u16HdrRemain));
4182 return rc;
4183 }
4184 }
4185
4186 pThis->u32PayRemain -= u16Len;
4187
4188 if (fSend)
4189 {
4190 /* Leave ethernet header intact */
4191 /* IP Total Length = payload + headers - ethernet header */
4192 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4193 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4194 pThis->szPrf, ntohs(pIpHdr->total_len)));
4195 /* Update IP Checksum */
4196 pIpHdr->chksum = 0;
4197 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4198 pThis->contextTSE.ip.u8CSO,
4199 pThis->contextTSE.ip.u8CSS,
4200 pThis->contextTSE.ip.u16CSE);
4201
4202 /* Update TCP flags */
4203 /* Restore original FIN and PSH flags for the last segment */
4204 if (pThis->u32PayRemain == 0)
4205 {
4206 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4207 E1K_INC_CNT32(TSCTC);
4208 }
4209 /* Add TCP length to partial pseudo header sum */
4210 uint32_t csum = pThis->u32SavedCsum
4211 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4212 while (csum >> 16)
4213 csum = (csum >> 16) + (csum & 0xFFFF);
4214 pTcpHdr->chksum = csum;
4215 /* Compute final checksum */
4216 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4217 pThis->contextTSE.tu.u8CSO,
4218 pThis->contextTSE.tu.u8CSS,
4219 pThis->contextTSE.tu.u16CSE);
4220
4221 /*
4222 * Transmit it.
4223 */
4224 if (pThis->CTX_SUFF(pTxSg))
4225 {
4226 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4227 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4228 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4229 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4230 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4231 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4232 }
4233 e1kTransmitFrame(pThis, fOnWorkerThread);
4234
4235 /* Update Sequence Number */
4236 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4237 - pThis->contextTSE.dw3.u8HDRLEN);
4238 /* Increment IP identification */
4239 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4240
4241 /* Allocate new buffer for the next segment. */
4242 if (pThis->u32PayRemain)
4243 {
4244 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4245 pThis->contextTSE.dw3.u16MSS)
4246 + pThis->contextTSE.dw3.u8HDRLEN
4247 + (pThis->fVTag ? 4 : 0);
4248 rc = e1kXmitAllocBuf(pThis, false /* fGSO */);
4249 }
4250 }
4251
4252 return rc;
4253}
4254#endif /* E1K_WITH_TXD_CACHE */
4255
4256#ifndef E1K_WITH_TXD_CACHE
4257/**
4258 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4259 * frame.
4260 *
4261 * We construct the frame in the fallback buffer first and the copy it to the SG
4262 * buffer before passing it down to the network driver code.
4263 *
4264 * @returns true if the frame should be transmitted, false if not.
4265 *
4266 * @param pThis The device state structure.
4267 * @param pDesc Pointer to the descriptor to transmit.
4268 * @param cbFragment Length of descriptor's buffer.
4269 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4270 * @thread E1000_TX
4271 */
4272static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4273{
4274 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4275 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4276 Assert(pDesc->data.cmd.fTSE);
4277 Assert(!e1kXmitIsGsoBuf(pTxSg));
4278
4279 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4280 Assert(u16MaxPktLen != 0);
4281 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4282
4283 /*
4284 * Carve out segments.
4285 */
4286 do
4287 {
4288 /* Calculate how many bytes we have left in this TCP segment */
4289 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4290 if (cb > cbFragment)
4291 {
4292 /* This descriptor fits completely into current segment */
4293 cb = cbFragment;
4294 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4295 }
4296 else
4297 {
4298 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4299 /*
4300 * Rewind the packet tail pointer to the beginning of payload,
4301 * so we continue writing right beyond the header.
4302 */
4303 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4304 }
4305
4306 pDesc->data.u64BufAddr += cb;
4307 cbFragment -= cb;
4308 } while (cbFragment > 0);
4309
4310 if (pDesc->data.cmd.fEOP)
4311 {
4312 /* End of packet, next segment will contain header. */
4313 if (pThis->u32PayRemain != 0)
4314 E1K_INC_CNT32(TSCTFC);
4315 pThis->u16TxPktLen = 0;
4316 e1kXmitFreeBuf(pThis);
4317 }
4318
4319 return false;
4320}
4321#else /* E1K_WITH_TXD_CACHE */
4322/**
4323 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4324 * frame.
4325 *
4326 * We construct the frame in the fallback buffer first and the copy it to the SG
4327 * buffer before passing it down to the network driver code.
4328 *
4329 * @returns error code
4330 *
4331 * @param pThis The device state structure.
4332 * @param pDesc Pointer to the descriptor to transmit.
4333 * @param cbFragment Length of descriptor's buffer.
4334 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4335 * @thread E1000_TX
4336 */
4337static int e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4338{
4339#ifdef VBOX_STRICT
4340 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4341 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4342 Assert(pDesc->data.cmd.fTSE);
4343 Assert(!e1kXmitIsGsoBuf(pTxSg));
4344#endif
4345
4346 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4347 Assert(u16MaxPktLen != 0);
4348 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4349
4350 /*
4351 * Carve out segments.
4352 */
4353 int rc;
4354 do
4355 {
4356 /* Calculate how many bytes we have left in this TCP segment */
4357 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4358 if (cb > pDesc->data.cmd.u20DTALEN)
4359 {
4360 /* This descriptor fits completely into current segment */
4361 cb = pDesc->data.cmd.u20DTALEN;
4362 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4363 }
4364 else
4365 {
4366 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4367 /*
4368 * Rewind the packet tail pointer to the beginning of payload,
4369 * so we continue writing right beyond the header.
4370 */
4371 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4372 }
4373
4374 pDesc->data.u64BufAddr += cb;
4375 pDesc->data.cmd.u20DTALEN -= cb;
4376 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4377
4378 if (pDesc->data.cmd.fEOP)
4379 {
4380 /* End of packet, next segment will contain header. */
4381 if (pThis->u32PayRemain != 0)
4382 E1K_INC_CNT32(TSCTFC);
4383 pThis->u16TxPktLen = 0;
4384 e1kXmitFreeBuf(pThis);
4385 }
4386
4387 return false;
4388}
4389#endif /* E1K_WITH_TXD_CACHE */
4390
4391
4392/**
4393 * Add descriptor's buffer to transmit frame.
4394 *
4395 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4396 * TSE frames we cannot handle as GSO.
4397 *
4398 * @returns true on success, false on failure.
4399 *
4400 * @param pThis The device state structure.
4401 * @param PhysAddr The physical address of the descriptor buffer.
4402 * @param cbFragment Length of descriptor's buffer.
4403 * @thread E1000_TX
4404 */
4405static bool e1kAddToFrame(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
4406{
4407 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4408 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4409 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4410
4411 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4412 {
4413 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4414 return false;
4415 }
4416 if (RT_UNLIKELY( fGso && cbNewPkt > pTxSg->cbAvailable ))
4417 {
4418 E1kLog(("%s Transmit packet is too large: %u > %u(max)/GSO\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4419 return false;
4420 }
4421
4422 if (RT_LIKELY(pTxSg))
4423 {
4424 Assert(pTxSg->cSegs == 1);
4425 Assert(pTxSg->cbUsed == pThis->u16TxPktLen);
4426
4427 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4428 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4429
4430 pTxSg->cbUsed = cbNewPkt;
4431 }
4432 pThis->u16TxPktLen = cbNewPkt;
4433
4434 return true;
4435}
4436
4437
4438/**
4439 * Write the descriptor back to guest memory and notify the guest.
4440 *
4441 * @param pThis The device state structure.
4442 * @param pDesc Pointer to the descriptor have been transmitted.
4443 * @param addr Physical address of the descriptor in guest memory.
4444 * @thread E1000_TX
4445 */
4446static void e1kDescReport(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4447{
4448 /*
4449 * We fake descriptor write-back bursting. Descriptors are written back as they are
4450 * processed.
4451 */
4452 /* Let's pretend we process descriptors. Write back with DD set. */
4453 /*
4454 * Prior to r71586 we tried to accomodate the case when write-back bursts
4455 * are enabled without actually implementing bursting by writing back all
4456 * descriptors, even the ones that do not have RS set. This caused kernel
4457 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4458 * associated with written back descriptor if it happened to be a context
4459 * descriptor since context descriptors do not have skb associated to them.
4460 * Starting from r71586 we write back only the descriptors with RS set,
4461 * which is a little bit different from what the real hardware does in
4462 * case there is a chain of data descritors where some of them have RS set
4463 * and others do not. It is very uncommon scenario imho.
4464 * We need to check RPS as well since some legacy drivers use it instead of
4465 * RS even with newer cards.
4466 */
4467 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4468 {
4469 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4470 e1kWriteBackDesc(pThis, pDesc, addr);
4471 if (pDesc->legacy.cmd.fEOP)
4472 {
4473//#ifdef E1K_USE_TX_TIMERS
4474 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4475 {
4476 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4477 //if (pThis->fIntRaised)
4478 //{
4479 // /* Interrupt is already pending, no need for timers */
4480 // ICR |= ICR_TXDW;
4481 //}
4482 //else {
4483 /* Arm the timer to fire in TIVD usec (discard .024) */
4484 e1kArmTimer(pThis, pThis->CTX_SUFF(pTIDTimer), TIDV);
4485# ifndef E1K_NO_TAD
4486 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4487 E1kLog2(("%s Checking if TAD timer is running\n",
4488 pThis->szPrf));
4489 if (TADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pTADTimer)))
4490 e1kArmTimer(pThis, pThis->CTX_SUFF(pTADTimer), TADV);
4491# endif /* E1K_NO_TAD */
4492 }
4493 else
4494 {
4495 if (pThis->fTidEnabled)
4496 {
4497 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4498 pThis->szPrf));
4499 /* Cancel both timers if armed and fire immediately. */
4500# ifndef E1K_NO_TAD
4501 TMTimerStop(pThis->CTX_SUFF(pTADTimer));
4502# endif
4503 TMTimerStop(pThis->CTX_SUFF(pTIDTimer));
4504 }
4505//#endif /* E1K_USE_TX_TIMERS */
4506 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4507 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXDW);
4508//#ifdef E1K_USE_TX_TIMERS
4509 }
4510//#endif /* E1K_USE_TX_TIMERS */
4511 }
4512 }
4513 else
4514 {
4515 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4516 }
4517}
4518
4519#ifndef E1K_WITH_TXD_CACHE
4520
4521/**
4522 * Process Transmit Descriptor.
4523 *
4524 * E1000 supports three types of transmit descriptors:
4525 * - legacy data descriptors of older format (context-less).
4526 * - data the same as legacy but providing new offloading capabilities.
4527 * - context sets up the context for following data descriptors.
4528 *
4529 * @param pThis The device state structure.
4530 * @param pDesc Pointer to descriptor union.
4531 * @param addr Physical address of descriptor in guest memory.
4532 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4533 * @thread E1000_TX
4534 */
4535static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr, bool fOnWorkerThread)
4536{
4537 int rc = VINF_SUCCESS;
4538 uint32_t cbVTag = 0;
4539
4540 e1kPrintTDesc(pThis, pDesc, "vvv");
4541
4542//#ifdef E1K_USE_TX_TIMERS
4543 if (pThis->fTidEnabled)
4544 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4545//#endif /* E1K_USE_TX_TIMERS */
4546
4547 switch (e1kGetDescType(pDesc))
4548 {
4549 case E1K_DTYP_CONTEXT:
4550 if (pDesc->context.dw2.fTSE)
4551 {
4552 pThis->contextTSE = pDesc->context;
4553 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4554 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4555 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4556 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4557 }
4558 else
4559 {
4560 pThis->contextNormal = pDesc->context;
4561 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4562 }
4563 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4564 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4565 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4566 pDesc->context.ip.u8CSS,
4567 pDesc->context.ip.u8CSO,
4568 pDesc->context.ip.u16CSE,
4569 pDesc->context.tu.u8CSS,
4570 pDesc->context.tu.u8CSO,
4571 pDesc->context.tu.u16CSE));
4572 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4573 e1kDescReport(pThis, pDesc, addr);
4574 break;
4575
4576 case E1K_DTYP_DATA:
4577 {
4578 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4579 {
4580 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4581 /** @todo Same as legacy when !TSE. See below. */
4582 break;
4583 }
4584 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4585 &pThis->StatTxDescTSEData:
4586 &pThis->StatTxDescData);
4587 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4588 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4589
4590 /*
4591 * The last descriptor of non-TSE packet must contain VLE flag.
4592 * TSE packets have VLE flag in the first descriptor. The later
4593 * case is taken care of a bit later when cbVTag gets assigned.
4594 *
4595 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4596 */
4597 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4598 {
4599 pThis->fVTag = pDesc->data.cmd.fVLE;
4600 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4601 }
4602 /*
4603 * First fragment: Allocate new buffer and save the IXSM and TXSM
4604 * packet options as these are only valid in the first fragment.
4605 */
4606 if (pThis->u16TxPktLen == 0)
4607 {
4608 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4609 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4610 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4611 pThis->fIPcsum ? " IP" : "",
4612 pThis->fTCPcsum ? " TCP/UDP" : ""));
4613 if (pDesc->data.cmd.fTSE)
4614 {
4615 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4616 pThis->fVTag = pDesc->data.cmd.fVLE;
4617 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4618 cbVTag = pThis->fVTag ? 4 : 0;
4619 }
4620 else if (pDesc->data.cmd.fEOP)
4621 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4622 else
4623 cbVTag = 4;
4624 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4625 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4626 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4627 true /*fExactSize*/, true /*fGso*/);
4628 else if (pDesc->data.cmd.fTSE)
4629 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4630 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4631 else
4632 rc = e1kXmitAllocBuf(pThis, pDesc->data.cmd.u20DTALEN + cbVTag,
4633 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4634
4635 /**
4636 * @todo: Perhaps it is not that simple for GSO packets! We may
4637 * need to unwind some changes.
4638 */
4639 if (RT_FAILURE(rc))
4640 {
4641 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4642 break;
4643 }
4644 /** @todo Is there any way to indicating errors other than collisions? Like
4645 * VERR_NET_DOWN. */
4646 }
4647
4648 /*
4649 * Add the descriptor data to the frame. If the frame is complete,
4650 * transmit it and reset the u16TxPktLen field.
4651 */
4652 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4653 {
4654 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4655 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4656 if (pDesc->data.cmd.fEOP)
4657 {
4658 if ( fRc
4659 && pThis->CTX_SUFF(pTxSg)
4660 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4661 {
4662 e1kTransmitFrame(pThis, fOnWorkerThread);
4663 E1K_INC_CNT32(TSCTC);
4664 }
4665 else
4666 {
4667 if (fRc)
4668 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4669 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4670 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4671 e1kXmitFreeBuf(pThis);
4672 E1K_INC_CNT32(TSCTFC);
4673 }
4674 pThis->u16TxPktLen = 0;
4675 }
4676 }
4677 else if (!pDesc->data.cmd.fTSE)
4678 {
4679 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4680 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4681 if (pDesc->data.cmd.fEOP)
4682 {
4683 if (fRc && pThis->CTX_SUFF(pTxSg))
4684 {
4685 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4686 if (pThis->fIPcsum)
4687 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4688 pThis->contextNormal.ip.u8CSO,
4689 pThis->contextNormal.ip.u8CSS,
4690 pThis->contextNormal.ip.u16CSE);
4691 if (pThis->fTCPcsum)
4692 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4693 pThis->contextNormal.tu.u8CSO,
4694 pThis->contextNormal.tu.u8CSS,
4695 pThis->contextNormal.tu.u16CSE);
4696 e1kTransmitFrame(pThis, fOnWorkerThread);
4697 }
4698 else
4699 e1kXmitFreeBuf(pThis);
4700 pThis->u16TxPktLen = 0;
4701 }
4702 }
4703 else
4704 {
4705 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4706 e1kFallbackAddToFrame(pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4707 }
4708
4709 e1kDescReport(pThis, pDesc, addr);
4710 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4711 break;
4712 }
4713
4714 case E1K_DTYP_LEGACY:
4715 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4716 {
4717 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4718 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4719 break;
4720 }
4721 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4722 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4723
4724 /* First fragment: allocate new buffer. */
4725 if (pThis->u16TxPktLen == 0)
4726 {
4727 if (pDesc->legacy.cmd.fEOP)
4728 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4729 else
4730 cbVTag = 4;
4731 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4732 /** @todo reset status bits? */
4733 rc = e1kXmitAllocBuf(pThis, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4734 if (RT_FAILURE(rc))
4735 {
4736 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4737 break;
4738 }
4739
4740 /** @todo Is there any way to indicating errors other than collisions? Like
4741 * VERR_NET_DOWN. */
4742 }
4743
4744 /* Add fragment to frame. */
4745 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4746 {
4747 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4748
4749 /* Last fragment: Transmit and reset the packet storage counter. */
4750 if (pDesc->legacy.cmd.fEOP)
4751 {
4752 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4753 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4754 /** @todo Offload processing goes here. */
4755 e1kTransmitFrame(pThis, fOnWorkerThread);
4756 pThis->u16TxPktLen = 0;
4757 }
4758 }
4759 /* Last fragment + failure: free the buffer and reset the storage counter. */
4760 else if (pDesc->legacy.cmd.fEOP)
4761 {
4762 e1kXmitFreeBuf(pThis);
4763 pThis->u16TxPktLen = 0;
4764 }
4765
4766 e1kDescReport(pThis, pDesc, addr);
4767 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4768 break;
4769
4770 default:
4771 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4772 pThis->szPrf, e1kGetDescType(pDesc)));
4773 break;
4774 }
4775
4776 return rc;
4777}
4778
4779#else /* E1K_WITH_TXD_CACHE */
4780
4781/**
4782 * Process Transmit Descriptor.
4783 *
4784 * E1000 supports three types of transmit descriptors:
4785 * - legacy data descriptors of older format (context-less).
4786 * - data the same as legacy but providing new offloading capabilities.
4787 * - context sets up the context for following data descriptors.
4788 *
4789 * @param pThis The device state structure.
4790 * @param pDesc Pointer to descriptor union.
4791 * @param addr Physical address of descriptor in guest memory.
4792 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4793 * @param cbPacketSize Size of the packet as previously computed.
4794 * @thread E1000_TX
4795 */
4796static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr,
4797 bool fOnWorkerThread)
4798{
4799 int rc = VINF_SUCCESS;
4800
4801 e1kPrintTDesc(pThis, pDesc, "vvv");
4802
4803//#ifdef E1K_USE_TX_TIMERS
4804 if (pThis->fTidEnabled)
4805 TMTimerStop(pThis->CTX_SUFF(pTIDTimer));
4806//#endif /* E1K_USE_TX_TIMERS */
4807
4808 switch (e1kGetDescType(pDesc))
4809 {
4810 case E1K_DTYP_CONTEXT:
4811 /* The caller have already updated the context */
4812 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4813 e1kDescReport(pThis, pDesc, addr);
4814 break;
4815
4816 case E1K_DTYP_DATA:
4817 {
4818 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4819 &pThis->StatTxDescTSEData:
4820 &pThis->StatTxDescData);
4821 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4822 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4823 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4824 {
4825 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4826 }
4827 else
4828 {
4829 /*
4830 * Add the descriptor data to the frame. If the frame is complete,
4831 * transmit it and reset the u16TxPktLen field.
4832 */
4833 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4834 {
4835 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4836 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4837 if (pDesc->data.cmd.fEOP)
4838 {
4839 if ( fRc
4840 && pThis->CTX_SUFF(pTxSg)
4841 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4842 {
4843 e1kTransmitFrame(pThis, fOnWorkerThread);
4844 E1K_INC_CNT32(TSCTC);
4845 }
4846 else
4847 {
4848 if (fRc)
4849 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4850 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4851 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4852 e1kXmitFreeBuf(pThis);
4853 E1K_INC_CNT32(TSCTFC);
4854 }
4855 pThis->u16TxPktLen = 0;
4856 }
4857 }
4858 else if (!pDesc->data.cmd.fTSE)
4859 {
4860 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4861 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4862 if (pDesc->data.cmd.fEOP)
4863 {
4864 if (fRc && pThis->CTX_SUFF(pTxSg))
4865 {
4866 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4867 if (pThis->fIPcsum)
4868 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4869 pThis->contextNormal.ip.u8CSO,
4870 pThis->contextNormal.ip.u8CSS,
4871 pThis->contextNormal.ip.u16CSE);
4872 if (pThis->fTCPcsum)
4873 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4874 pThis->contextNormal.tu.u8CSO,
4875 pThis->contextNormal.tu.u8CSS,
4876 pThis->contextNormal.tu.u16CSE);
4877 e1kTransmitFrame(pThis, fOnWorkerThread);
4878 }
4879 else
4880 e1kXmitFreeBuf(pThis);
4881 pThis->u16TxPktLen = 0;
4882 }
4883 }
4884 else
4885 {
4886 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4887 rc = e1kFallbackAddToFrame(pThis, pDesc, fOnWorkerThread);
4888 }
4889 }
4890 e1kDescReport(pThis, pDesc, addr);
4891 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4892 break;
4893 }
4894
4895 case E1K_DTYP_LEGACY:
4896 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4897 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4898 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4899 {
4900 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4901 }
4902 else
4903 {
4904 /* Add fragment to frame. */
4905 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4906 {
4907 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4908
4909 /* Last fragment: Transmit and reset the packet storage counter. */
4910 if (pDesc->legacy.cmd.fEOP)
4911 {
4912 if (pDesc->legacy.cmd.fIC)
4913 {
4914 e1kInsertChecksum(pThis,
4915 (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
4916 pThis->u16TxPktLen,
4917 pDesc->legacy.cmd.u8CSO,
4918 pDesc->legacy.dw3.u8CSS,
4919 0);
4920 }
4921 e1kTransmitFrame(pThis, fOnWorkerThread);
4922 pThis->u16TxPktLen = 0;
4923 }
4924 }
4925 /* Last fragment + failure: free the buffer and reset the storage counter. */
4926 else if (pDesc->legacy.cmd.fEOP)
4927 {
4928 e1kXmitFreeBuf(pThis);
4929 pThis->u16TxPktLen = 0;
4930 }
4931 }
4932 e1kDescReport(pThis, pDesc, addr);
4933 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4934 break;
4935
4936 default:
4937 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4938 pThis->szPrf, e1kGetDescType(pDesc)));
4939 break;
4940 }
4941
4942 return rc;
4943}
4944
4945DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
4946{
4947 if (pDesc->context.dw2.fTSE)
4948 {
4949 pThis->contextTSE = pDesc->context;
4950 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4951 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4952 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4953 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4954 }
4955 else
4956 {
4957 pThis->contextNormal = pDesc->context;
4958 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4959 }
4960 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4961 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4962 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4963 pDesc->context.ip.u8CSS,
4964 pDesc->context.ip.u8CSO,
4965 pDesc->context.ip.u16CSE,
4966 pDesc->context.tu.u8CSS,
4967 pDesc->context.tu.u8CSO,
4968 pDesc->context.tu.u16CSE));
4969}
4970
4971static bool e1kLocateTxPacket(PE1KSTATE pThis)
4972{
4973 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
4974 pThis->szPrf, pThis->cbTxAlloc));
4975 /* Check if we have located the packet already. */
4976 if (pThis->cbTxAlloc)
4977 {
4978 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
4979 pThis->szPrf, pThis->cbTxAlloc));
4980 return true;
4981 }
4982
4983 bool fTSE = false;
4984 uint32_t cbPacket = 0;
4985
4986 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
4987 {
4988 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
4989 switch (e1kGetDescType(pDesc))
4990 {
4991 case E1K_DTYP_CONTEXT:
4992 e1kUpdateTxContext(pThis, pDesc);
4993 continue;
4994 case E1K_DTYP_LEGACY:
4995 /* Skip empty descriptors. */
4996 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
4997 break;
4998 cbPacket += pDesc->legacy.cmd.u16Length;
4999 pThis->fGSO = false;
5000 break;
5001 case E1K_DTYP_DATA:
5002 /* Skip empty descriptors. */
5003 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5004 break;
5005 if (cbPacket == 0)
5006 {
5007 /*
5008 * The first fragment: save IXSM and TXSM options
5009 * as these are only valid in the first fragment.
5010 */
5011 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5012 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5013 fTSE = pDesc->data.cmd.fTSE;
5014 /*
5015 * TSE descriptors have VLE bit properly set in
5016 * the first fragment.
5017 */
5018 if (fTSE)
5019 {
5020 pThis->fVTag = pDesc->data.cmd.fVLE;
5021 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5022 }
5023 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5024 }
5025 cbPacket += pDesc->data.cmd.u20DTALEN;
5026 break;
5027 default:
5028 AssertMsgFailed(("Impossible descriptor type!"));
5029 }
5030 if (pDesc->legacy.cmd.fEOP)
5031 {
5032 /*
5033 * Non-TSE descriptors have VLE bit properly set in
5034 * the last fragment.
5035 */
5036 if (!fTSE)
5037 {
5038 pThis->fVTag = pDesc->data.cmd.fVLE;
5039 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5040 }
5041 /*
5042 * Compute the required buffer size. If we cannot do GSO but still
5043 * have to do segmentation we allocate the first segment only.
5044 */
5045 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5046 cbPacket :
5047 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5048 if (pThis->fVTag)
5049 pThis->cbTxAlloc += 4;
5050 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5051 pThis->szPrf, pThis->cbTxAlloc));
5052 return true;
5053 }
5054 }
5055
5056 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5057 {
5058 /* All descriptors were empty, we need to process them as a dummy packet */
5059 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5060 pThis->szPrf, pThis->cbTxAlloc));
5061 return true;
5062 }
5063 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d\n",
5064 pThis->szPrf, pThis->cbTxAlloc));
5065 return false;
5066}
5067
5068static int e1kXmitPacket(PE1KSTATE pThis, bool fOnWorkerThread)
5069{
5070 int rc = VINF_SUCCESS;
5071
5072 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5073 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5074
5075 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5076 {
5077 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5078 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5079 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5080 rc = e1kXmitDesc(pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5081 if (RT_FAILURE(rc))
5082 break;
5083 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5084 TDH = 0;
5085 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5086 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5087 {
5088 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5089 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5090 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5091 }
5092 ++pThis->iTxDCurrent;
5093 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5094 break;
5095 }
5096
5097 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5098 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5099 return rc;
5100}
5101
5102#endif /* E1K_WITH_TXD_CACHE */
5103#ifndef E1K_WITH_TXD_CACHE
5104
5105/**
5106 * Transmit pending descriptors.
5107 *
5108 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5109 *
5110 * @param pThis The E1000 state.
5111 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5112 */
5113static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5114{
5115 int rc = VINF_SUCCESS;
5116
5117 /* Check if transmitter is enabled. */
5118 if (!(TCTL & TCTL_EN))
5119 return VINF_SUCCESS;
5120 /*
5121 * Grab the xmit lock of the driver as well as the E1K device state.
5122 */
5123 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5124 if (RT_LIKELY(rc == VINF_SUCCESS))
5125 {
5126 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5127 if (pDrv)
5128 {
5129 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5130 if (RT_FAILURE(rc))
5131 {
5132 e1kCsTxLeave(pThis);
5133 return rc;
5134 }
5135 }
5136 /*
5137 * Process all pending descriptors.
5138 * Note! Do not process descriptors in locked state
5139 */
5140 while (TDH != TDT && !pThis->fLocked)
5141 {
5142 E1KTXDESC desc;
5143 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5144 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5145
5146 e1kLoadDesc(pThis, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5147 rc = e1kXmitDesc(pThis, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5148 /* If we failed to transmit descriptor we will try it again later */
5149 if (RT_FAILURE(rc))
5150 break;
5151 if (++TDH * sizeof(desc) >= TDLEN)
5152 TDH = 0;
5153
5154 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5155 {
5156 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5157 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5158 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5159 }
5160
5161 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5162 }
5163
5164 /// @todo uncomment: pThis->uStatIntTXQE++;
5165 /// @todo uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5166 /*
5167 * Release the lock.
5168 */
5169 if (pDrv)
5170 pDrv->pfnEndXmit(pDrv);
5171 e1kCsTxLeave(pThis);
5172 }
5173
5174 return rc;
5175}
5176
5177#else /* E1K_WITH_TXD_CACHE */
5178
5179static void e1kDumpTxDCache(PE1KSTATE pThis)
5180{
5181 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5182 uint32_t tdh = TDH;
5183 LogRel(("-- Transmit Descriptors (%d total) --\n", cDescs));
5184 for (i = 0; i < cDescs; ++i)
5185 {
5186 E1KTXDESC desc;
5187 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
5188 &desc, sizeof(desc));
5189 if (i == tdh)
5190 LogRel((">>> "));
5191 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5192 }
5193 LogRel(("-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5194 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5195 if (tdh > pThis->iTxDCurrent)
5196 tdh -= pThis->iTxDCurrent;
5197 else
5198 tdh = cDescs + tdh - pThis->iTxDCurrent;
5199 for (i = 0; i < pThis->nTxDFetched; ++i)
5200 {
5201 if (i == pThis->iTxDCurrent)
5202 LogRel((">>> "));
5203 LogRel(("%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5204 }
5205}
5206
5207/**
5208 * Transmit pending descriptors.
5209 *
5210 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5211 *
5212 * @param pThis The E1000 state.
5213 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5214 */
5215static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5216{
5217 int rc = VINF_SUCCESS;
5218
5219 /* Check if transmitter is enabled. */
5220 if (!(TCTL & TCTL_EN))
5221 return VINF_SUCCESS;
5222 /*
5223 * Grab the xmit lock of the driver as well as the E1K device state.
5224 */
5225 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5226 if (pDrv)
5227 {
5228 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5229 if (RT_FAILURE(rc))
5230 return rc;
5231 }
5232
5233 /*
5234 * Process all pending descriptors.
5235 * Note! Do not process descriptors in locked state
5236 */
5237 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5238 if (RT_LIKELY(rc == VINF_SUCCESS))
5239 {
5240 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5241 /*
5242 * fIncomplete is set whenever we try to fetch additional descriptors
5243 * for an incomplete packet. If fail to locate a complete packet on
5244 * the next iteration we need to reset the cache or we risk to get
5245 * stuck in this loop forever.
5246 */
5247 bool fIncomplete = false;
5248 while (!pThis->fLocked && e1kTxDLazyLoad(pThis))
5249 {
5250 while (e1kLocateTxPacket(pThis))
5251 {
5252 fIncomplete = false;
5253 /* Found a complete packet, allocate it. */
5254 rc = e1kXmitAllocBuf(pThis, pThis->fGSO);
5255 /* If we're out of bandwidth we'll come back later. */
5256 if (RT_FAILURE(rc))
5257 goto out;
5258 /* Copy the packet to allocated buffer and send it. */
5259 rc = e1kXmitPacket(pThis, fOnWorkerThread);
5260 /* If we're out of bandwidth we'll come back later. */
5261 if (RT_FAILURE(rc))
5262 goto out;
5263 }
5264 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5265 if (RT_UNLIKELY(fIncomplete))
5266 {
5267 static bool fTxDCacheDumped = false;
5268 /*
5269 * The descriptor cache is full, but we were unable to find
5270 * a complete packet in it. Drop the cache and hope that
5271 * the guest driver can recover from network card error.
5272 */
5273 LogRel(("%s No complete packets in%s TxD cache! "
5274 "Fetched=%d, current=%d, TX len=%d.\n",
5275 pThis->szPrf,
5276 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5277 pThis->nTxDFetched, pThis->iTxDCurrent,
5278 e1kGetTxLen(pThis)));
5279 if (!fTxDCacheDumped)
5280 {
5281 fTxDCacheDumped = true;
5282 e1kDumpTxDCache(pThis);
5283 }
5284 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5285 /*
5286 * Returning an error at this point means Guru in R0
5287 * (see @bugref{6428}).
5288 */
5289# ifdef IN_RING3
5290 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5291# else /* !IN_RING3 */
5292 rc = VINF_IOM_R3_MMIO_WRITE;
5293# endif /* !IN_RING3 */
5294 goto out;
5295 }
5296 if (u8Remain > 0)
5297 {
5298 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5299 "%d more are available\n",
5300 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5301 e1kGetTxLen(pThis) - u8Remain));
5302
5303 /*
5304 * A packet was partially fetched. Move incomplete packet to
5305 * the beginning of cache buffer, then load more descriptors.
5306 */
5307 memmove(pThis->aTxDescriptors,
5308 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5309 u8Remain * sizeof(E1KTXDESC));
5310 pThis->iTxDCurrent = 0;
5311 pThis->nTxDFetched = u8Remain;
5312 e1kTxDLoadMore(pThis);
5313 fIncomplete = true;
5314 }
5315 else
5316 pThis->nTxDFetched = 0;
5317 pThis->iTxDCurrent = 0;
5318 }
5319 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5320 {
5321 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5322 pThis->szPrf));
5323 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5324 }
5325out:
5326 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5327
5328 /// @todo uncomment: pThis->uStatIntTXQE++;
5329 /// @todo uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5330
5331 e1kCsTxLeave(pThis);
5332 }
5333
5334
5335 /*
5336 * Release the lock.
5337 */
5338 if (pDrv)
5339 pDrv->pfnEndXmit(pDrv);
5340 return rc;
5341}
5342
5343#endif /* E1K_WITH_TXD_CACHE */
5344#ifdef IN_RING3
5345
5346/**
5347 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5348 */
5349static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5350{
5351 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
5352 /* Resume suspended transmission */
5353 STATUS &= ~STATUS_TXOFF;
5354 e1kXmitPending(pThis, true /*fOnWorkerThread*/);
5355}
5356
5357/**
5358 * Callback for consuming from transmit queue. It gets called in R3 whenever
5359 * we enqueue something in R0/GC.
5360 *
5361 * @returns true
5362 * @param pDevIns Pointer to device instance structure.
5363 * @param pItem Pointer to the element being dequeued (not used).
5364 * @thread ???
5365 */
5366static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5367{
5368 NOREF(pItem);
5369 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5370 E1kLog2(("%s e1kTxQueueConsumer:\n", pThis->szPrf));
5371
5372 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/); NOREF(rc);
5373#ifndef DEBUG_andy /** @todo r=andy Happens for me a lot, mute this for me. */
5374 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
5375#endif
5376 return true;
5377}
5378
5379/**
5380 * Handler for the wakeup signaller queue.
5381 */
5382static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5383{
5384 RT_NOREF(pItem);
5385 e1kWakeupReceive(pDevIns);
5386 return true;
5387}
5388
5389#endif /* IN_RING3 */
5390
5391/**
5392 * Write handler for Transmit Descriptor Tail register.
5393 *
5394 * @param pThis The device state structure.
5395 * @param offset Register offset in memory-mapped frame.
5396 * @param index Register index in register array.
5397 * @param value The value to store.
5398 * @param mask Used to implement partial writes (8 and 16-bit).
5399 * @thread EMT
5400 */
5401static int e1kRegWriteTDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5402{
5403 int rc = e1kRegWriteDefault(pThis, offset, index, value);
5404
5405 /* All descriptors starting with head and not including tail belong to us. */
5406 /* Process them. */
5407 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5408 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5409
5410 /* Ignore TDT writes when the link is down. */
5411 if (TDH != TDT && (STATUS & STATUS_LU))
5412 {
5413 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5414 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5415 pThis->szPrf, e1kGetTxLen(pThis)));
5416
5417 /* Transmit pending packets if possible, defer it if we cannot do it
5418 in the current context. */
5419#ifdef E1K_TX_DELAY
5420 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5421 if (RT_LIKELY(rc == VINF_SUCCESS))
5422 {
5423 if (!TMTimerIsActive(pThis->CTX_SUFF(pTXDTimer)))
5424 {
5425#ifdef E1K_INT_STATS
5426 pThis->u64ArmedAt = RTTimeNanoTS();
5427#endif
5428 e1kArmTimer(pThis, pThis->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
5429 }
5430 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5431 e1kCsTxLeave(pThis);
5432 return rc;
5433 }
5434 /* We failed to enter the TX critical section -- transmit as usual. */
5435#endif /* E1K_TX_DELAY */
5436#ifndef IN_RING3
5437 if (!pThis->CTX_SUFF(pDrv))
5438 {
5439 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
5440 if (RT_UNLIKELY(pItem))
5441 PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
5442 }
5443 else
5444#endif
5445 {
5446 rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5447 if (rc == VERR_TRY_AGAIN)
5448 rc = VINF_SUCCESS;
5449 else if (rc == VERR_SEM_BUSY)
5450 rc = VINF_IOM_R3_MMIO_WRITE;
5451 AssertRC(rc);
5452 }
5453 }
5454
5455 return rc;
5456}
5457
5458/**
5459 * Write handler for Multicast Table Array registers.
5460 *
5461 * @param pThis The device state structure.
5462 * @param offset Register offset in memory-mapped frame.
5463 * @param index Register index in register array.
5464 * @param value The value to store.
5465 * @thread EMT
5466 */
5467static int e1kRegWriteMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5468{
5469 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5470 pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])] = value;
5471
5472 return VINF_SUCCESS;
5473}
5474
5475/**
5476 * Read handler for Multicast Table Array registers.
5477 *
5478 * @returns VBox status code.
5479 *
5480 * @param pThis The device state structure.
5481 * @param offset Register offset in memory-mapped frame.
5482 * @param index Register index in register array.
5483 * @thread EMT
5484 */
5485static int e1kRegReadMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5486{
5487 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5488 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5489
5490 return VINF_SUCCESS;
5491}
5492
5493/**
5494 * Write handler for Receive Address registers.
5495 *
5496 * @param pThis The device state structure.
5497 * @param offset Register offset in memory-mapped frame.
5498 * @param index Register index in register array.
5499 * @param value The value to store.
5500 * @thread EMT
5501 */
5502static int e1kRegWriteRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5503{
5504 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5505 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5506
5507 return VINF_SUCCESS;
5508}
5509
5510/**
5511 * Read handler for Receive Address registers.
5512 *
5513 * @returns VBox status code.
5514 *
5515 * @param pThis The device state structure.
5516 * @param offset Register offset in memory-mapped frame.
5517 * @param index Register index in register array.
5518 * @thread EMT
5519 */
5520static int e1kRegReadRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5521{
5522 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5523 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5524
5525 return VINF_SUCCESS;
5526}
5527
5528/**
5529 * Write handler for VLAN Filter Table Array registers.
5530 *
5531 * @param pThis The device state structure.
5532 * @param offset Register offset in memory-mapped frame.
5533 * @param index Register index in register array.
5534 * @param value The value to store.
5535 * @thread EMT
5536 */
5537static int e1kRegWriteVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5538{
5539 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5540 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5541
5542 return VINF_SUCCESS;
5543}
5544
5545/**
5546 * Read handler for VLAN Filter Table Array registers.
5547 *
5548 * @returns VBox status code.
5549 *
5550 * @param pThis The device state structure.
5551 * @param offset Register offset in memory-mapped frame.
5552 * @param index Register index in register array.
5553 * @thread EMT
5554 */
5555static int e1kRegReadVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5556{
5557 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5558 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5559
5560 return VINF_SUCCESS;
5561}
5562
5563/**
5564 * Read handler for unimplemented registers.
5565 *
5566 * Merely reports reads from unimplemented registers.
5567 *
5568 * @returns VBox status code.
5569 *
5570 * @param pThis The device state structure.
5571 * @param offset Register offset in memory-mapped frame.
5572 * @param index Register index in register array.
5573 * @thread EMT
5574 */
5575static int e1kRegReadUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5576{
5577 RT_NOREF3(pThis, offset, index);
5578 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5579 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5580 *pu32Value = 0;
5581
5582 return VINF_SUCCESS;
5583}
5584
5585/**
5586 * Default register read handler with automatic clear operation.
5587 *
5588 * Retrieves the value of register from register array in device state structure.
5589 * Then resets all bits.
5590 *
5591 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5592 * done in the caller.
5593 *
5594 * @returns VBox status code.
5595 *
5596 * @param pThis The device state structure.
5597 * @param offset Register offset in memory-mapped frame.
5598 * @param index Register index in register array.
5599 * @thread EMT
5600 */
5601static int e1kRegReadAutoClear(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5602{
5603 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5604 int rc = e1kRegReadDefault(pThis, offset, index, pu32Value);
5605 pThis->auRegs[index] = 0;
5606
5607 return rc;
5608}
5609
5610/**
5611 * Default register read handler.
5612 *
5613 * Retrieves the value of register from register array in device state structure.
5614 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5615 *
5616 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5617 * done in the caller.
5618 *
5619 * @returns VBox status code.
5620 *
5621 * @param pThis The device state structure.
5622 * @param offset Register offset in memory-mapped frame.
5623 * @param index Register index in register array.
5624 * @thread EMT
5625 */
5626static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5627{
5628 RT_NOREF_PV(offset);
5629
5630 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5631 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5632
5633 return VINF_SUCCESS;
5634}
5635
5636/**
5637 * Write handler for unimplemented registers.
5638 *
5639 * Merely reports writes to unimplemented registers.
5640 *
5641 * @param pThis The device state structure.
5642 * @param offset Register offset in memory-mapped frame.
5643 * @param index Register index in register array.
5644 * @param value The value to store.
5645 * @thread EMT
5646 */
5647
5648 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5649{
5650 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
5651
5652 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5653 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5654
5655 return VINF_SUCCESS;
5656}
5657
5658/**
5659 * Default register write handler.
5660 *
5661 * Stores the value to the register array in device state structure. Only bits
5662 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5663 *
5664 * @returns VBox status code.
5665 *
5666 * @param pThis The device state structure.
5667 * @param offset Register offset in memory-mapped frame.
5668 * @param index Register index in register array.
5669 * @param value The value to store.
5670 * @param mask Used to implement partial writes (8 and 16-bit).
5671 * @thread EMT
5672 */
5673
5674static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5675{
5676 RT_NOREF_PV(offset);
5677
5678 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5679 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5680 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5681
5682 return VINF_SUCCESS;
5683}
5684
5685/**
5686 * Search register table for matching register.
5687 *
5688 * @returns Index in the register table or -1 if not found.
5689 *
5690 * @param offReg Register offset in memory-mapped region.
5691 * @thread EMT
5692 */
5693static int e1kRegLookup(uint32_t offReg)
5694{
5695
5696#if 0
5697 int index;
5698
5699 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5700 {
5701 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5702 {
5703 return index;
5704 }
5705 }
5706#else
5707 int iStart = 0;
5708 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5709 for (;;)
5710 {
5711 int i = (iEnd - iStart) / 2 + iStart;
5712 uint32_t offCur = g_aE1kRegMap[i].offset;
5713 if (offReg < offCur)
5714 {
5715 if (i == iStart)
5716 break;
5717 iEnd = i;
5718 }
5719 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5720 {
5721 i++;
5722 if (i == iEnd)
5723 break;
5724 iStart = i;
5725 }
5726 else
5727 return i;
5728 Assert(iEnd > iStart);
5729 }
5730
5731 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5732 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5733 return i;
5734
5735# ifdef VBOX_STRICT
5736 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5737 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5738# endif
5739
5740#endif
5741
5742 return -1;
5743}
5744
5745/**
5746 * Handle unaligned register read operation.
5747 *
5748 * Looks up and calls appropriate handler.
5749 *
5750 * @returns VBox status code.
5751 *
5752 * @param pThis The device state structure.
5753 * @param offReg Register offset in memory-mapped frame.
5754 * @param pv Where to store the result.
5755 * @param cb Number of bytes to read.
5756 * @thread EMT
5757 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5758 * accesses we have to take care of that ourselves.
5759 */
5760static int e1kRegReadUnaligned(PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5761{
5762 uint32_t u32 = 0;
5763 uint32_t shift;
5764 int rc = VINF_SUCCESS;
5765 int index = e1kRegLookup(offReg);
5766#ifdef LOG_ENABLED
5767 char buf[9];
5768#endif
5769
5770 /*
5771 * From the spec:
5772 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
5773 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
5774 */
5775
5776 /*
5777 * To be able to read bytes and short word we convert them to properly
5778 * shifted 32-bit words and masks. The idea is to keep register-specific
5779 * handlers simple. Most accesses will be 32-bit anyway.
5780 */
5781 uint32_t mask;
5782 switch (cb)
5783 {
5784 case 4: mask = 0xFFFFFFFF; break;
5785 case 2: mask = 0x0000FFFF; break;
5786 case 1: mask = 0x000000FF; break;
5787 default:
5788 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5789 "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
5790 }
5791 if (index != -1)
5792 {
5793 if (g_aE1kRegMap[index].readable)
5794 {
5795 /* Make the mask correspond to the bits we are about to read. */
5796 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
5797 mask <<= shift;
5798 if (!mask)
5799 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
5800 /*
5801 * Read it. Pass the mask so the handler knows what has to be read.
5802 * Mask out irrelevant bits.
5803 */
5804 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5805 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5806 return rc;
5807 //pThis->fDelayInts = false;
5808 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5809 //pThis->iStatIntLostOne = 0;
5810 rc = g_aE1kRegMap[index].pfnRead(pThis, offReg & 0xFFFFFFFC, index, &u32);
5811 u32 &= mask;
5812 //e1kCsLeave(pThis);
5813 E1kLog2(("%s At %08X read %s from %s (%s)\n",
5814 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5815 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
5816 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5817 /* Shift back the result. */
5818 u32 >>= shift;
5819 }
5820 else
5821 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
5822 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5823 if (IOM_SUCCESS(rc))
5824 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
5825 }
5826 else
5827 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
5828 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
5829
5830 memcpy(pv, &u32, cb);
5831 return rc;
5832}
5833
5834/**
5835 * Handle 4 byte aligned and sized read operation.
5836 *
5837 * Looks up and calls appropriate handler.
5838 *
5839 * @returns VBox status code.
5840 *
5841 * @param pThis The device state structure.
5842 * @param offReg Register offset in memory-mapped frame.
5843 * @param pu32 Where to store the result.
5844 * @thread EMT
5845 */
5846static int e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
5847{
5848 Assert(!(offReg & 3));
5849
5850 /*
5851 * Lookup the register and check that it's readable.
5852 */
5853 int rc = VINF_SUCCESS;
5854 int idxReg = e1kRegLookup(offReg);
5855 if (RT_LIKELY(idxReg != -1))
5856 {
5857 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
5858 {
5859 /*
5860 * Read it. Pass the mask so the handler knows what has to be read.
5861 * Mask out irrelevant bits.
5862 */
5863 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5864 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5865 // return rc;
5866 //pThis->fDelayInts = false;
5867 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5868 //pThis->iStatIntLostOne = 0;
5869 rc = g_aE1kRegMap[idxReg].pfnRead(pThis, offReg & 0xFFFFFFFC, idxReg, pu32);
5870 //e1kCsLeave(pThis);
5871 Log6(("%s At %08X read %08X from %s (%s)\n",
5872 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5873 if (IOM_SUCCESS(rc))
5874 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
5875 }
5876 else
5877 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
5878 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
5879 }
5880 else
5881 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
5882 return rc;
5883}
5884
5885/**
5886 * Handle 4 byte sized and aligned register write operation.
5887 *
5888 * Looks up and calls appropriate handler.
5889 *
5890 * @returns VBox status code.
5891 *
5892 * @param pThis The device state structure.
5893 * @param offReg Register offset in memory-mapped frame.
5894 * @param u32Value The value to write.
5895 * @thread EMT
5896 */
5897static int e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
5898{
5899 int rc = VINF_SUCCESS;
5900 int index = e1kRegLookup(offReg);
5901 if (RT_LIKELY(index != -1))
5902 {
5903 if (RT_LIKELY(g_aE1kRegMap[index].writable))
5904 {
5905 /*
5906 * Write it. Pass the mask so the handler knows what has to be written.
5907 * Mask out irrelevant bits.
5908 */
5909 Log6(("%s At %08X write %08X to %s (%s)\n",
5910 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5911 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5912 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
5913 // return rc;
5914 //pThis->fDelayInts = false;
5915 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5916 //pThis->iStatIntLostOne = 0;
5917 rc = g_aE1kRegMap[index].pfnWrite(pThis, offReg, index, u32Value);
5918 //e1kCsLeave(pThis);
5919 }
5920 else
5921 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
5922 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5923 if (IOM_SUCCESS(rc))
5924 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
5925 }
5926 else
5927 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
5928 pThis->szPrf, offReg, u32Value));
5929 return rc;
5930}
5931
5932
5933/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
5934
5935/**
5936 * @callback_method_impl{FNIOMMMIOREAD}
5937 */
5938PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
5939{
5940 RT_NOREF2(pvUser, cb);
5941 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5942 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5943
5944 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5945 Assert(offReg < E1K_MM_SIZE);
5946 Assert(cb == 4);
5947 Assert(!(GCPhysAddr & 3));
5948
5949 int rc = e1kRegReadAlignedU32(pThis, offReg, (uint32_t *)pv);
5950
5951 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
5952 return rc;
5953}
5954
5955/**
5956 * @callback_method_impl{FNIOMMMIOWRITE}
5957 */
5958PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
5959{
5960 RT_NOREF2(pvUser, cb);
5961 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5962 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5963
5964 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
5965 Assert(offReg < E1K_MM_SIZE);
5966 Assert(cb == 4);
5967 Assert(!(GCPhysAddr & 3));
5968
5969 int rc = e1kRegWriteAlignedU32(pThis, offReg, *(uint32_t const *)pv);
5970
5971 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
5972 return rc;
5973}
5974
5975/**
5976 * @callback_method_impl{FNIOMIOPORTIN}
5977 */
5978PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
5979{
5980 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5981 int rc;
5982 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
5983 RT_NOREF_PV(pvUser);
5984
5985 uPort -= pThis->IOPortBase;
5986 if (RT_LIKELY(cb == 4))
5987 switch (uPort)
5988 {
5989 case 0x00: /* IOADDR */
5990 *pu32 = pThis->uSelectedReg;
5991 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
5992 rc = VINF_SUCCESS;
5993 break;
5994
5995 case 0x04: /* IODATA */
5996 if (!(pThis->uSelectedReg & 3))
5997 rc = e1kRegReadAlignedU32(pThis, pThis->uSelectedReg, pu32);
5998 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
5999 rc = e1kRegReadUnaligned(pThis, pThis->uSelectedReg, pu32, cb);
6000 if (rc == VINF_IOM_R3_MMIO_READ)
6001 rc = VINF_IOM_R3_IOPORT_READ;
6002 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6003 break;
6004
6005 default:
6006 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, uPort));
6007 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6008 rc = VINF_SUCCESS;
6009 }
6010 else
6011 {
6012 E1kLog(("%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x", pThis->szPrf, uPort, cb));
6013 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb);
6014 }
6015 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6016 return rc;
6017}
6018
6019
6020/**
6021 * @callback_method_impl{FNIOMIOPORTOUT}
6022 */
6023PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
6024{
6025 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
6026 int rc;
6027 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6028 RT_NOREF_PV(pvUser);
6029
6030 E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
6031 if (RT_LIKELY(cb == 4))
6032 {
6033 uPort -= pThis->IOPortBase;
6034 switch (uPort)
6035 {
6036 case 0x00: /* IOADDR */
6037 pThis->uSelectedReg = u32;
6038 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6039 rc = VINF_SUCCESS;
6040 break;
6041
6042 case 0x04: /* IODATA */
6043 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6044 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6045 {
6046 rc = e1kRegWriteAlignedU32(pThis, pThis->uSelectedReg, u32);
6047 if (rc == VINF_IOM_R3_MMIO_WRITE)
6048 rc = VINF_IOM_R3_IOPORT_WRITE;
6049 }
6050 else
6051 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
6052 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6053 break;
6054
6055 default:
6056 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, uPort));
6057 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", uPort);
6058 }
6059 }
6060 else
6061 {
6062 E1kLog(("%s e1kIOPortOut: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb));
6063 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: uPort=%RTiop cb=%#x\n", pThis->szPrf, uPort, cb);
6064 }
6065
6066 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6067 return rc;
6068}
6069
6070#ifdef IN_RING3
6071
6072/**
6073 * Dump complete device state to log.
6074 *
6075 * @param pThis Pointer to device state.
6076 */
6077static void e1kDumpState(PE1KSTATE pThis)
6078{
6079 RT_NOREF(pThis);
6080 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6081 E1kLog2(("%s %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6082# ifdef E1K_INT_STATS
6083 LogRel(("%s Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6084 LogRel(("%s Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6085 LogRel(("%s Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6086 LogRel(("%s ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6087 LogRel(("%s IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6088 LogRel(("%s Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6089 LogRel(("%s Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6090 LogRel(("%s Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6091 LogRel(("%s Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6092 LogRel(("%s Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6093 LogRel(("%s Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6094 LogRel(("%s Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6095 LogRel(("%s Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6096 LogRel(("%s Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6097 LogRel(("%s Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6098 LogRel(("%s Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6099 LogRel(("%s TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6100 LogRel(("%s TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6101 LogRel(("%s TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6102 LogRel(("%s TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6103 LogRel(("%s TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6104 LogRel(("%s TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6105 LogRel(("%s RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6106 LogRel(("%s RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6107 LogRel(("%s TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6108 LogRel(("%s TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6109 LogRel(("%s TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6110 LogRel(("%s Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6111 LogRel(("%s Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6112 LogRel(("%s TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6113 LogRel(("%s TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6114 LogRel(("%s TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6115 LogRel(("%s TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6116 LogRel(("%s TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6117 LogRel(("%s TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6118 LogRel(("%s TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6119 LogRel(("%s TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6120 LogRel(("%s Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6121 LogRel(("%s Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6122# endif /* E1K_INT_STATS */
6123}
6124
6125/**
6126 * @callback_method_impl{FNPCIIOREGIONMAP}
6127 */
6128static DECLCALLBACK(int) e1kMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6129 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
6130{
6131 RT_NOREF(pPciDev, iRegion);
6132 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);
6133 int rc;
6134
6135 switch (enmType)
6136 {
6137 case PCI_ADDRESS_SPACE_IO:
6138 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
6139 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
6140 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
6141 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6142 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
6143 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6144 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6145 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
6146 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6147 break;
6148
6149 case PCI_ADDRESS_SPACE_MEM:
6150 /*
6151 * From the spec:
6152 * For registers that should be accessed as 32-bit double words,
6153 * partial writes (less than a 32-bit double word) is ignored.
6154 * Partial reads return all 32 bits of data regardless of the
6155 * byte enables.
6156 */
6157#ifdef E1K_WITH_PREREG_MMIO
6158 pThis->addrMMReg = GCPhysAddress;
6159 if (GCPhysAddress == NIL_RTGCPHYS)
6160 rc = VINF_SUCCESS;
6161 else
6162 {
6163 Assert(!(GCPhysAddress & 7));
6164 rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
6165 }
6166#else
6167 pThis->addrMMReg = GCPhysAddress; Assert(!(GCPhysAddress & 7));
6168 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
6169 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
6170 e1kMMIOWrite, e1kMMIORead, "E1000");
6171 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6172 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
6173 "e1kMMIOWrite", "e1kMMIORead");
6174 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6175 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
6176 "e1kMMIOWrite", "e1kMMIORead");
6177#endif
6178 break;
6179
6180 default:
6181 /* We should never get here */
6182 AssertMsgFailed(("Invalid PCI address space param in map callback"));
6183 rc = VERR_INTERNAL_ERROR;
6184 break;
6185 }
6186 return rc;
6187}
6188
6189
6190/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6191
6192/**
6193 * Check if the device can receive data now.
6194 * This must be called before the pfnRecieve() method is called.
6195 *
6196 * @returns Number of bytes the device can receive.
6197 * @param pInterface Pointer to the interface structure containing the called function pointer.
6198 * @thread EMT
6199 */
6200static int e1kCanReceive(PE1KSTATE pThis)
6201{
6202#ifndef E1K_WITH_RXD_CACHE
6203 size_t cb;
6204
6205 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6206 return VERR_NET_NO_BUFFER_SPACE;
6207
6208 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6209 {
6210 E1KRXDESC desc;
6211 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6212 &desc, sizeof(desc));
6213 if (desc.status.fDD)
6214 cb = 0;
6215 else
6216 cb = pThis->u16RxBSize;
6217 }
6218 else if (RDH < RDT)
6219 cb = (RDT - RDH) * pThis->u16RxBSize;
6220 else if (RDH > RDT)
6221 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6222 else
6223 {
6224 cb = 0;
6225 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6226 }
6227 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6228 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6229
6230 e1kCsRxLeave(pThis);
6231 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6232#else /* E1K_WITH_RXD_CACHE */
6233 int rc = VINF_SUCCESS;
6234
6235 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6236 return VERR_NET_NO_BUFFER_SPACE;
6237
6238 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6239 {
6240 E1KRXDESC desc;
6241 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6242 &desc, sizeof(desc));
6243 if (desc.status.fDD)
6244 rc = VERR_NET_NO_BUFFER_SPACE;
6245 }
6246 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6247 {
6248 /* Cache is empty, so is the RX ring. */
6249 rc = VERR_NET_NO_BUFFER_SPACE;
6250 }
6251 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6252 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6253 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6254
6255 e1kCsRxLeave(pThis);
6256 return rc;
6257#endif /* E1K_WITH_RXD_CACHE */
6258}
6259
6260/**
6261 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6262 */
6263static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6264{
6265 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6266 int rc = e1kCanReceive(pThis);
6267
6268 if (RT_SUCCESS(rc))
6269 return VINF_SUCCESS;
6270 if (RT_UNLIKELY(cMillies == 0))
6271 return VERR_NET_NO_BUFFER_SPACE;
6272
6273 rc = VERR_INTERRUPTED;
6274 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6275 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6276 VMSTATE enmVMState;
6277 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
6278 || enmVMState == VMSTATE_RUNNING_LS))
6279 {
6280 int rc2 = e1kCanReceive(pThis);
6281 if (RT_SUCCESS(rc2))
6282 {
6283 rc = VINF_SUCCESS;
6284 break;
6285 }
6286 E1kLogRel(("E1000 e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6287 E1kLog(("%s e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6288 RTSemEventWait(pThis->hEventMoreRxDescAvail, cMillies);
6289 }
6290 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6291 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6292
6293 return rc;
6294}
6295
6296
6297/**
6298 * Matches the packet addresses against Receive Address table. Looks for
6299 * exact matches only.
6300 *
6301 * @returns true if address matches.
6302 * @param pThis Pointer to the state structure.
6303 * @param pvBuf The ethernet packet.
6304 * @param cb Number of bytes available in the packet.
6305 * @thread EMT
6306 */
6307static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6308{
6309 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6310 {
6311 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6312
6313 /* Valid address? */
6314 if (ra->ctl & RA_CTL_AV)
6315 {
6316 Assert((ra->ctl & RA_CTL_AS) < 2);
6317 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6318 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6319 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6320 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6321 /*
6322 * Address Select:
6323 * 00b = Destination address
6324 * 01b = Source address
6325 * 10b = Reserved
6326 * 11b = Reserved
6327 * Since ethernet header is (DA, SA, len) we can use address
6328 * select as index.
6329 */
6330 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6331 ra->addr, sizeof(ra->addr)) == 0)
6332 return true;
6333 }
6334 }
6335
6336 return false;
6337}
6338
6339/**
6340 * Matches the packet addresses against Multicast Table Array.
6341 *
6342 * @remarks This is imperfect match since it matches not exact address but
6343 * a subset of addresses.
6344 *
6345 * @returns true if address matches.
6346 * @param pThis Pointer to the state structure.
6347 * @param pvBuf The ethernet packet.
6348 * @param cb Number of bytes available in the packet.
6349 * @thread EMT
6350 */
6351static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6352{
6353 /* Get bits 32..47 of destination address */
6354 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6355
6356 unsigned offset = GET_BITS(RCTL, MO);
6357 /*
6358 * offset means:
6359 * 00b = bits 36..47
6360 * 01b = bits 35..46
6361 * 10b = bits 34..45
6362 * 11b = bits 32..43
6363 */
6364 if (offset < 3)
6365 u16Bit = u16Bit >> (4 - offset);
6366 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6367}
6368
6369/**
6370 * Determines if the packet is to be delivered to upper layer.
6371 *
6372 * The following filters supported:
6373 * - Exact Unicast/Multicast
6374 * - Promiscuous Unicast/Multicast
6375 * - Multicast
6376 * - VLAN
6377 *
6378 * @returns true if packet is intended for this node.
6379 * @param pThis Pointer to the state structure.
6380 * @param pvBuf The ethernet packet.
6381 * @param cb Number of bytes available in the packet.
6382 * @param pStatus Bit field to store status bits.
6383 * @thread EMT
6384 */
6385static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6386{
6387 Assert(cb > 14);
6388 /* Assume that we fail to pass exact filter. */
6389 pStatus->fPIF = false;
6390 pStatus->fVP = false;
6391 /* Discard oversized packets */
6392 if (cb > E1K_MAX_RX_PKT_SIZE)
6393 {
6394 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6395 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6396 E1K_INC_CNT32(ROC);
6397 return false;
6398 }
6399 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6400 {
6401 /* When long packet reception is disabled packets over 1522 are discarded */
6402 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6403 pThis->szPrf, cb));
6404 E1K_INC_CNT32(ROC);
6405 return false;
6406 }
6407
6408 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6409 /* Compare TPID with VLAN Ether Type */
6410 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6411 {
6412 pStatus->fVP = true;
6413 /* Is VLAN filtering enabled? */
6414 if (RCTL & RCTL_VFE)
6415 {
6416 /* It is 802.1q packet indeed, let's filter by VID */
6417 if (RCTL & RCTL_CFIEN)
6418 {
6419 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6420 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6421 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6422 !!(RCTL & RCTL_CFI)));
6423 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6424 {
6425 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6426 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6427 return false;
6428 }
6429 }
6430 else
6431 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6432 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6433 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6434 {
6435 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6436 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6437 return false;
6438 }
6439 }
6440 }
6441 /* Broadcast filtering */
6442 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6443 return true;
6444 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6445 if (e1kIsMulticast(pvBuf))
6446 {
6447 /* Is multicast promiscuous enabled? */
6448 if (RCTL & RCTL_MPE)
6449 return true;
6450 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6451 /* Try perfect matches first */
6452 if (e1kPerfectMatch(pThis, pvBuf))
6453 {
6454 pStatus->fPIF = true;
6455 return true;
6456 }
6457 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6458 if (e1kImperfectMatch(pThis, pvBuf))
6459 return true;
6460 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6461 }
6462 else {
6463 /* Is unicast promiscuous enabled? */
6464 if (RCTL & RCTL_UPE)
6465 return true;
6466 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6467 if (e1kPerfectMatch(pThis, pvBuf))
6468 {
6469 pStatus->fPIF = true;
6470 return true;
6471 }
6472 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6473 }
6474 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6475 return false;
6476}
6477
6478/**
6479 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6480 */
6481static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6482{
6483 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6484 int rc = VINF_SUCCESS;
6485
6486 /*
6487 * Drop packets if the VM is not running yet/anymore.
6488 */
6489 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pThis));
6490 if ( enmVMState != VMSTATE_RUNNING
6491 && enmVMState != VMSTATE_RUNNING_LS)
6492 {
6493 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6494 return VINF_SUCCESS;
6495 }
6496
6497 /* Discard incoming packets in locked state */
6498 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6499 {
6500 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6501 return VINF_SUCCESS;
6502 }
6503
6504 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6505
6506 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6507 // return VERR_PERMISSION_DENIED;
6508
6509 e1kPacketDump(pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6510
6511 /* Update stats */
6512 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6513 {
6514 E1K_INC_CNT32(TPR);
6515 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6516 e1kCsLeave(pThis);
6517 }
6518 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6519 E1KRXDST status;
6520 RT_ZERO(status);
6521 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6522 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6523 if (fPassed)
6524 {
6525 rc = e1kHandleRxPacket(pThis, pvBuf, cb, status);
6526 }
6527 //e1kCsLeave(pThis);
6528 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6529
6530 return rc;
6531}
6532
6533
6534/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6535
6536/**
6537 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6538 */
6539static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6540{
6541 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
6542 int rc = VERR_PDM_LUN_NOT_FOUND;
6543
6544 if (iLUN == 0)
6545 {
6546 *ppLed = &pThis->led;
6547 rc = VINF_SUCCESS;
6548 }
6549 return rc;
6550}
6551
6552
6553/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6554
6555/**
6556 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6557 */
6558static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6559{
6560 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6561 pThis->eeprom.getMac(pMac);
6562 return VINF_SUCCESS;
6563}
6564
6565/**
6566 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6567 */
6568static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6569{
6570 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6571 if (STATUS & STATUS_LU)
6572 return PDMNETWORKLINKSTATE_UP;
6573 return PDMNETWORKLINKSTATE_DOWN;
6574}
6575
6576/**
6577 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6578 */
6579static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6580{
6581 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6582
6583 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6584 switch (enmState)
6585 {
6586 case PDMNETWORKLINKSTATE_UP:
6587 pThis->fCableConnected = true;
6588 /* If link was down, bring it up after a while. */
6589 if (!(STATUS & STATUS_LU))
6590 e1kBringLinkUpDelayed(pThis);
6591 break;
6592 case PDMNETWORKLINKSTATE_DOWN:
6593 pThis->fCableConnected = false;
6594 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6595 * We might have to set the link state before the driver initializes us. */
6596 Phy::setLinkStatus(&pThis->phy, false);
6597 /* If link was up, bring it down. */
6598 if (STATUS & STATUS_LU)
6599 e1kR3LinkDown(pThis);
6600 break;
6601 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6602 /*
6603 * There is not much sense in bringing down the link if it has not come up yet.
6604 * If it is up though, we bring it down temporarely, then bring it up again.
6605 */
6606 if (STATUS & STATUS_LU)
6607 e1kR3LinkDownTemp(pThis);
6608 break;
6609 default:
6610 ;
6611 }
6612 return VINF_SUCCESS;
6613}
6614
6615
6616/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6617
6618/**
6619 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6620 */
6621static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6622{
6623 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
6624 Assert(&pThis->IBase == pInterface);
6625
6626 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
6627 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
6628 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
6629 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
6630 return NULL;
6631}
6632
6633
6634/* -=-=-=-=- Saved State -=-=-=-=- */
6635
6636/**
6637 * Saves the configuration.
6638 *
6639 * @param pThis The E1K state.
6640 * @param pSSM The handle to the saved state.
6641 */
6642static void e1kSaveConfig(PE1KSTATE pThis, PSSMHANDLE pSSM)
6643{
6644 SSMR3PutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6645 SSMR3PutU32(pSSM, pThis->eChip);
6646}
6647
6648/**
6649 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6650 */
6651static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6652{
6653 RT_NOREF(uPass);
6654 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6655 e1kSaveConfig(pThis, pSSM);
6656 return VINF_SSM_DONT_CALL_AGAIN;
6657}
6658
6659/**
6660 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6661 */
6662static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6663{
6664 RT_NOREF(pSSM);
6665 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6666
6667 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6668 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6669 return rc;
6670 e1kCsLeave(pThis);
6671 return VINF_SUCCESS;
6672#if 0
6673 /* 1) Prevent all threads from modifying the state and memory */
6674 //pThis->fLocked = true;
6675 /* 2) Cancel all timers */
6676#ifdef E1K_TX_DELAY
6677 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6678#endif /* E1K_TX_DELAY */
6679//#ifdef E1K_USE_TX_TIMERS
6680 if (pThis->fTidEnabled)
6681 {
6682 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6683#ifndef E1K_NO_TAD
6684 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6685#endif /* E1K_NO_TAD */
6686 }
6687//#endif /* E1K_USE_TX_TIMERS */
6688#ifdef E1K_USE_RX_TIMERS
6689 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6690 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6691#endif /* E1K_USE_RX_TIMERS */
6692 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6693 /* 3) Did I forget anything? */
6694 E1kLog(("%s Locked\n", pThis->szPrf));
6695 return VINF_SUCCESS;
6696#endif
6697}
6698
6699/**
6700 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6701 */
6702static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6703{
6704 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6705
6706 e1kSaveConfig(pThis, pSSM);
6707 pThis->eeprom.save(pSSM);
6708 e1kDumpState(pThis);
6709 SSMR3PutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6710 SSMR3PutBool(pSSM, pThis->fIntRaised);
6711 Phy::saveState(pSSM, &pThis->phy);
6712 SSMR3PutU32(pSSM, pThis->uSelectedReg);
6713 SSMR3PutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6714 SSMR3PutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6715 SSMR3PutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6716 SSMR3PutU64(pSSM, pThis->u64AckedAt);
6717 SSMR3PutU16(pSSM, pThis->u16RxBSize);
6718 //SSMR3PutBool(pSSM, pThis->fDelayInts);
6719 //SSMR3PutBool(pSSM, pThis->fIntMaskUsed);
6720 SSMR3PutU16(pSSM, pThis->u16TxPktLen);
6721/** @todo State wrt to the TSE buffer is incomplete, so little point in
6722 * saving this actually. */
6723 SSMR3PutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6724 SSMR3PutBool(pSSM, pThis->fIPcsum);
6725 SSMR3PutBool(pSSM, pThis->fTCPcsum);
6726 SSMR3PutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6727 SSMR3PutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6728 SSMR3PutBool(pSSM, pThis->fVTag);
6729 SSMR3PutU16(pSSM, pThis->u16VTagTCI);
6730#ifdef E1K_WITH_TXD_CACHE
6731#if 0
6732 SSMR3PutU8(pSSM, pThis->nTxDFetched);
6733 SSMR3PutMem(pSSM, pThis->aTxDescriptors,
6734 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6735#else
6736 /*
6737 * There is no point in storing TX descriptor cache entries as we can simply
6738 * fetch them again. Moreover, normally the cache is always empty when we
6739 * save the state. Store zero entries for compatibility.
6740 */
6741 SSMR3PutU8(pSSM, 0);
6742#endif
6743#endif /* E1K_WITH_TXD_CACHE */
6744/** @todo GSO requires some more state here. */
6745 E1kLog(("%s State has been saved\n", pThis->szPrf));
6746 return VINF_SUCCESS;
6747}
6748
6749#if 0
6750/**
6751 * @callback_method_impl{FNSSMDEVSAVEDONE}
6752 */
6753static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6754{
6755 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6756
6757 /* If VM is being powered off unlocking will result in assertions in PGM */
6758 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6759 pThis->fLocked = false;
6760 else
6761 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6762 E1kLog(("%s Unlocked\n", pThis->szPrf));
6763 return VINF_SUCCESS;
6764}
6765#endif
6766
6767/**
6768 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6769 */
6770static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6771{
6772 RT_NOREF(pSSM);
6773 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6774
6775 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6776 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6777 return rc;
6778 e1kCsLeave(pThis);
6779 return VINF_SUCCESS;
6780}
6781
6782/**
6783 * @callback_method_impl{FNSSMDEVLOADEXEC}
6784 */
6785static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6786{
6787 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6788 int rc;
6789
6790 if ( uVersion != E1K_SAVEDSTATE_VERSION
6791#ifdef E1K_WITH_TXD_CACHE
6792 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6793#endif /* E1K_WITH_TXD_CACHE */
6794 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6795 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6796 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6797
6798 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6799 || uPass != SSM_PASS_FINAL)
6800 {
6801 /* config checks */
6802 RTMAC macConfigured;
6803 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
6804 AssertRCReturn(rc, rc);
6805 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6806 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6807 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6808
6809 E1KCHIP eChip;
6810 rc = SSMR3GetU32(pSSM, &eChip);
6811 AssertRCReturn(rc, rc);
6812 if (eChip != pThis->eChip)
6813 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6814 }
6815
6816 if (uPass == SSM_PASS_FINAL)
6817 {
6818 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6819 {
6820 rc = pThis->eeprom.load(pSSM);
6821 AssertRCReturn(rc, rc);
6822 }
6823 /* the state */
6824 SSMR3GetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
6825 SSMR3GetBool(pSSM, &pThis->fIntRaised);
6826 /** @todo PHY could be made a separate device with its own versioning */
6827 Phy::loadState(pSSM, &pThis->phy);
6828 SSMR3GetU32(pSSM, &pThis->uSelectedReg);
6829 SSMR3GetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
6830 SSMR3GetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6831 SSMR3GetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
6832 SSMR3GetU64(pSSM, &pThis->u64AckedAt);
6833 SSMR3GetU16(pSSM, &pThis->u16RxBSize);
6834 //SSMR3GetBool(pSSM, pThis->fDelayInts);
6835 //SSMR3GetBool(pSSM, pThis->fIntMaskUsed);
6836 SSMR3GetU16(pSSM, &pThis->u16TxPktLen);
6837 SSMR3GetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
6838 SSMR3GetBool(pSSM, &pThis->fIPcsum);
6839 SSMR3GetBool(pSSM, &pThis->fTCPcsum);
6840 SSMR3GetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6841 rc = SSMR3GetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6842 AssertRCReturn(rc, rc);
6843 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
6844 {
6845 SSMR3GetBool(pSSM, &pThis->fVTag);
6846 rc = SSMR3GetU16(pSSM, &pThis->u16VTagTCI);
6847 AssertRCReturn(rc, rc);
6848 }
6849 else
6850 {
6851 pThis->fVTag = false;
6852 pThis->u16VTagTCI = 0;
6853 }
6854#ifdef E1K_WITH_TXD_CACHE
6855 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
6856 {
6857 rc = SSMR3GetU8(pSSM, &pThis->nTxDFetched);
6858 AssertRCReturn(rc, rc);
6859 if (pThis->nTxDFetched)
6860 SSMR3GetMem(pSSM, pThis->aTxDescriptors,
6861 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6862 }
6863 else
6864 pThis->nTxDFetched = 0;
6865 /*
6866 * @todo: Perhaps we should not store TXD cache as the entries can be
6867 * simply fetched again from guest's memory. Or can't they?
6868 */
6869#endif /* E1K_WITH_TXD_CACHE */
6870#ifdef E1K_WITH_RXD_CACHE
6871 /*
6872 * There is no point in storing the RX descriptor cache in the saved
6873 * state, we just need to make sure it is empty.
6874 */
6875 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
6876#endif /* E1K_WITH_RXD_CACHE */
6877 /* derived state */
6878 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
6879
6880 E1kLog(("%s State has been restored\n", pThis->szPrf));
6881 e1kDumpState(pThis);
6882 }
6883 return VINF_SUCCESS;
6884}
6885
6886/**
6887 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
6888 */
6889static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6890{
6891 RT_NOREF(pSSM);
6892 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6893
6894 /* Update promiscuous mode */
6895 if (pThis->pDrvR3)
6896 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3,
6897 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
6898
6899 /*
6900 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
6901 * passed to us. We go through all this stuff if the link was up and we
6902 * wasn't teleported.
6903 */
6904 if ( (STATUS & STATUS_LU)
6905 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
6906 && pThis->cMsLinkUpDelay)
6907 {
6908 e1kR3LinkDownTemp(pThis);
6909 }
6910 return VINF_SUCCESS;
6911}
6912
6913
6914
6915/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
6916
6917/**
6918 * @callback_method_impl{FNRTSTRFORMATTYPE}
6919 */
6920static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
6921 void *pvArgOutput,
6922 const char *pszType,
6923 void const *pvValue,
6924 int cchWidth,
6925 int cchPrecision,
6926 unsigned fFlags,
6927 void *pvUser)
6928{
6929 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
6930 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
6931 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
6932 if (!pDesc)
6933 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
6934
6935 size_t cbPrintf = 0;
6936 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
6937 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
6938 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
6939 pDesc->status.fPIF ? "PIF" : "pif",
6940 pDesc->status.fIPCS ? "IPCS" : "ipcs",
6941 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
6942 pDesc->status.fVP ? "VP" : "vp",
6943 pDesc->status.fIXSM ? "IXSM" : "ixsm",
6944 pDesc->status.fEOP ? "EOP" : "eop",
6945 pDesc->status.fDD ? "DD" : "dd",
6946 pDesc->status.fRXE ? "RXE" : "rxe",
6947 pDesc->status.fIPE ? "IPE" : "ipe",
6948 pDesc->status.fTCPE ? "TCPE" : "tcpe",
6949 pDesc->status.fCE ? "CE" : "ce",
6950 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
6951 E1K_SPEC_VLAN(pDesc->status.u16Special),
6952 E1K_SPEC_PRI(pDesc->status.u16Special));
6953 return cbPrintf;
6954}
6955
6956/**
6957 * @callback_method_impl{FNRTSTRFORMATTYPE}
6958 */
6959static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
6960 void *pvArgOutput,
6961 const char *pszType,
6962 void const *pvValue,
6963 int cchWidth,
6964 int cchPrecision,
6965 unsigned fFlags,
6966 void *pvUser)
6967{
6968 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
6969 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
6970 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
6971 if (!pDesc)
6972 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
6973
6974 size_t cbPrintf = 0;
6975 switch (e1kGetDescType(pDesc))
6976 {
6977 case E1K_DTYP_CONTEXT:
6978 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
6979 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
6980 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
6981 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
6982 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
6983 pDesc->context.dw2.fIDE ? " IDE":"",
6984 pDesc->context.dw2.fRS ? " RS" :"",
6985 pDesc->context.dw2.fTSE ? " TSE":"",
6986 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
6987 pDesc->context.dw2.fTCP ? "TCP":"UDP",
6988 pDesc->context.dw2.u20PAYLEN,
6989 pDesc->context.dw3.u8HDRLEN,
6990 pDesc->context.dw3.u16MSS,
6991 pDesc->context.dw3.fDD?"DD":"");
6992 break;
6993 case E1K_DTYP_DATA:
6994 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
6995 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
6996 pDesc->data.u64BufAddr,
6997 pDesc->data.cmd.u20DTALEN,
6998 pDesc->data.cmd.fIDE ? " IDE" :"",
6999 pDesc->data.cmd.fVLE ? " VLE" :"",
7000 pDesc->data.cmd.fRPS ? " RPS" :"",
7001 pDesc->data.cmd.fRS ? " RS" :"",
7002 pDesc->data.cmd.fTSE ? " TSE" :"",
7003 pDesc->data.cmd.fIFCS? " IFCS":"",
7004 pDesc->data.cmd.fEOP ? " EOP" :"",
7005 pDesc->data.dw3.fDD ? " DD" :"",
7006 pDesc->data.dw3.fEC ? " EC" :"",
7007 pDesc->data.dw3.fLC ? " LC" :"",
7008 pDesc->data.dw3.fTXSM? " TXSM":"",
7009 pDesc->data.dw3.fIXSM? " IXSM":"",
7010 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7011 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7012 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7013 break;
7014 case E1K_DTYP_LEGACY:
7015 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7016 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7017 pDesc->data.u64BufAddr,
7018 pDesc->legacy.cmd.u16Length,
7019 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7020 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7021 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7022 pDesc->legacy.cmd.fRS ? " RS" :"",
7023 pDesc->legacy.cmd.fIC ? " IC" :"",
7024 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7025 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7026 pDesc->legacy.dw3.fDD ? " DD" :"",
7027 pDesc->legacy.dw3.fEC ? " EC" :"",
7028 pDesc->legacy.dw3.fLC ? " LC" :"",
7029 pDesc->legacy.cmd.u8CSO,
7030 pDesc->legacy.dw3.u8CSS,
7031 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7032 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7033 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7034 break;
7035 default:
7036 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7037 break;
7038 }
7039
7040 return cbPrintf;
7041}
7042
7043/** Initializes debug helpers (logging format types). */
7044static int e1kInitDebugHelpers(void)
7045{
7046 int rc = VINF_SUCCESS;
7047 static bool s_fHelpersRegistered = false;
7048 if (!s_fHelpersRegistered)
7049 {
7050 s_fHelpersRegistered = true;
7051 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7052 AssertRCReturn(rc, rc);
7053 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7054 AssertRCReturn(rc, rc);
7055 }
7056 return rc;
7057}
7058
7059/**
7060 * Status info callback.
7061 *
7062 * @param pDevIns The device instance.
7063 * @param pHlp The output helpers.
7064 * @param pszArgs The arguments.
7065 */
7066static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7067{
7068 RT_NOREF(pszArgs);
7069 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7070 unsigned i;
7071 // bool fRcvRing = false;
7072 // bool fXmtRing = false;
7073
7074 /*
7075 * Parse args.
7076 if (pszArgs)
7077 {
7078 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7079 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7080 }
7081 */
7082
7083 /*
7084 * Show info.
7085 */
7086 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7087 pDevIns->iInstance, pThis->IOPortBase, pThis->addrMMReg,
7088 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7089 pThis->fRCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
7090
7091 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7092
7093 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7094 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7095
7096 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7097 {
7098 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7099 if (ra->ctl & RA_CTL_AV)
7100 {
7101 const char *pcszTmp;
7102 switch (ra->ctl & RA_CTL_AS)
7103 {
7104 case 0: pcszTmp = "DST"; break;
7105 case 1: pcszTmp = "SRC"; break;
7106 default: pcszTmp = "reserved";
7107 }
7108 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7109 }
7110 }
7111 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7112 uint32_t rdh = RDH;
7113 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7114 for (i = 0; i < cDescs; ++i)
7115 {
7116 E1KRXDESC desc;
7117 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7118 &desc, sizeof(desc));
7119 if (i == rdh)
7120 pHlp->pfnPrintf(pHlp, ">>> ");
7121 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7122 }
7123#ifdef E1K_WITH_RXD_CACHE
7124 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7125 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7126 if (rdh > pThis->iRxDCurrent)
7127 rdh -= pThis->iRxDCurrent;
7128 else
7129 rdh = cDescs + rdh - pThis->iRxDCurrent;
7130 for (i = 0; i < pThis->nRxDFetched; ++i)
7131 {
7132 if (i == pThis->iRxDCurrent)
7133 pHlp->pfnPrintf(pHlp, ">>> ");
7134 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7135 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7136 &pThis->aRxDescriptors[i]);
7137 }
7138#endif /* E1K_WITH_RXD_CACHE */
7139
7140 cDescs = TDLEN / sizeof(E1KTXDESC);
7141 uint32_t tdh = TDH;
7142 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7143 for (i = 0; i < cDescs; ++i)
7144 {
7145 E1KTXDESC desc;
7146 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7147 &desc, sizeof(desc));
7148 if (i == tdh)
7149 pHlp->pfnPrintf(pHlp, ">>> ");
7150 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7151 }
7152#ifdef E1K_WITH_TXD_CACHE
7153 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7154 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7155 if (tdh > pThis->iTxDCurrent)
7156 tdh -= pThis->iTxDCurrent;
7157 else
7158 tdh = cDescs + tdh - pThis->iTxDCurrent;
7159 for (i = 0; i < pThis->nTxDFetched; ++i)
7160 {
7161 if (i == pThis->iTxDCurrent)
7162 pHlp->pfnPrintf(pHlp, ">>> ");
7163 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7164 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7165 &pThis->aTxDescriptors[i]);
7166 }
7167#endif /* E1K_WITH_TXD_CACHE */
7168
7169
7170#ifdef E1K_INT_STATS
7171 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7172 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7173 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7174 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7175 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7176 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7177 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7178 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7179 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7180 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7181 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7182 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7183 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7184 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7185 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7186 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7187 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7188 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7189 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7190 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7191 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7192 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7193 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7194 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7195 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7196 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7197 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7198 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7199 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7200 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7201 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7202 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7203 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7204 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7205 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7206 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7207 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7208 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7209#endif /* E1K_INT_STATS */
7210
7211 e1kCsLeave(pThis);
7212}
7213
7214
7215
7216/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7217
7218/**
7219 * Detach notification.
7220 *
7221 * One port on the network card has been disconnected from the network.
7222 *
7223 * @param pDevIns The device instance.
7224 * @param iLUN The logical unit which is being detached.
7225 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7226 */
7227static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7228{
7229 RT_NOREF(fFlags);
7230 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7231 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7232
7233 AssertLogRelReturnVoid(iLUN == 0);
7234
7235 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7236
7237 /** @todo r=pritesh still need to check if i missed
7238 * to clean something in this function
7239 */
7240
7241 /*
7242 * Zero some important members.
7243 */
7244 pThis->pDrvBase = NULL;
7245 pThis->pDrvR3 = NULL;
7246 pThis->pDrvR0 = NIL_RTR0PTR;
7247 pThis->pDrvRC = NIL_RTRCPTR;
7248
7249 PDMCritSectLeave(&pThis->cs);
7250}
7251
7252/**
7253 * Attach the Network attachment.
7254 *
7255 * One port on the network card has been connected to a network.
7256 *
7257 * @returns VBox status code.
7258 * @param pDevIns The device instance.
7259 * @param iLUN The logical unit which is being attached.
7260 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7261 *
7262 * @remarks This code path is not used during construction.
7263 */
7264static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7265{
7266 RT_NOREF(fFlags);
7267 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7268 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7269
7270 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7271
7272 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7273
7274 /*
7275 * Attach the driver.
7276 */
7277 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7278 if (RT_SUCCESS(rc))
7279 {
7280 if (rc == VINF_NAT_DNS)
7281 {
7282#ifdef RT_OS_LINUX
7283 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7284 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7285#else
7286 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7287 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7288#endif
7289 }
7290 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7291 AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7292 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7293 if (RT_SUCCESS(rc))
7294 {
7295 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0);
7296 pThis->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7297
7298 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC);
7299 pThis->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7300 }
7301 }
7302 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7303 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7304 {
7305 /* This should never happen because this function is not called
7306 * if there is no driver to attach! */
7307 Log(("%s No attached driver!\n", pThis->szPrf));
7308 }
7309
7310 /*
7311 * Temporary set the link down if it was up so that the guest
7312 * will know that we have change the configuration of the
7313 * network card
7314 */
7315 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7316 e1kR3LinkDownTemp(pThis);
7317
7318 PDMCritSectLeave(&pThis->cs);
7319 return rc;
7320
7321}
7322
7323/**
7324 * @copydoc FNPDMDEVPOWEROFF
7325 */
7326static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7327{
7328 /* Poke thread waiting for buffer space. */
7329 e1kWakeupReceive(pDevIns);
7330}
7331
7332/**
7333 * @copydoc FNPDMDEVRESET
7334 */
7335static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7336{
7337 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7338#ifdef E1K_TX_DELAY
7339 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7340#endif /* E1K_TX_DELAY */
7341 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7342 e1kCancelTimer(pThis, pThis->CTX_SUFF(pLUTimer));
7343 e1kXmitFreeBuf(pThis);
7344 pThis->u16TxPktLen = 0;
7345 pThis->fIPcsum = false;
7346 pThis->fTCPcsum = false;
7347 pThis->fIntMaskUsed = false;
7348 pThis->fDelayInts = false;
7349 pThis->fLocked = false;
7350 pThis->u64AckedAt = 0;
7351 e1kHardReset(pThis);
7352}
7353
7354/**
7355 * @copydoc FNPDMDEVSUSPEND
7356 */
7357static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7358{
7359 /* Poke thread waiting for buffer space. */
7360 e1kWakeupReceive(pDevIns);
7361}
7362
7363/**
7364 * Device relocation callback.
7365 *
7366 * When this callback is called the device instance data, and if the
7367 * device have a GC component, is being relocated, or/and the selectors
7368 * have been changed. The device must use the chance to perform the
7369 * necessary pointer relocations and data updates.
7370 *
7371 * Before the GC code is executed the first time, this function will be
7372 * called with a 0 delta so GC pointer calculations can be one in one place.
7373 *
7374 * @param pDevIns Pointer to the device instance.
7375 * @param offDelta The relocation delta relative to the old location.
7376 *
7377 * @remark A relocation CANNOT fail.
7378 */
7379static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7380{
7381 RT_NOREF(offDelta);
7382 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7383 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7384 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7385 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7386#ifdef E1K_USE_RX_TIMERS
7387 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7388 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7389#endif /* E1K_USE_RX_TIMERS */
7390//#ifdef E1K_USE_TX_TIMERS
7391 if (pThis->fTidEnabled)
7392 {
7393 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7394# ifndef E1K_NO_TAD
7395 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7396# endif /* E1K_NO_TAD */
7397 }
7398//#endif /* E1K_USE_TX_TIMERS */
7399#ifdef E1K_TX_DELAY
7400 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7401#endif /* E1K_TX_DELAY */
7402 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7403 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7404}
7405
7406/**
7407 * Destruct a device instance.
7408 *
7409 * We need to free non-VM resources only.
7410 *
7411 * @returns VBox status code.
7412 * @param pDevIns The device instance data.
7413 * @thread EMT
7414 */
7415static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7416{
7417 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7418 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7419
7420 e1kDumpState(pThis);
7421 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7422 if (PDMCritSectIsInitialized(&pThis->cs))
7423 {
7424 if (pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
7425 {
7426 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
7427 RTSemEventDestroy(pThis->hEventMoreRxDescAvail);
7428 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7429 }
7430#ifdef E1K_WITH_TX_CS
7431 PDMR3CritSectDelete(&pThis->csTx);
7432#endif /* E1K_WITH_TX_CS */
7433 PDMR3CritSectDelete(&pThis->csRx);
7434 PDMR3CritSectDelete(&pThis->cs);
7435 }
7436 return VINF_SUCCESS;
7437}
7438
7439
7440/**
7441 * Set PCI configuration space registers.
7442 *
7443 * @param pci Reference to PCI device structure.
7444 * @thread EMT
7445 */
7446static DECLCALLBACK(void) e1kConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7447{
7448 Assert(eChip < RT_ELEMENTS(g_aChips));
7449 /* Configure PCI Device, assume 32-bit mode ******************************/
7450 PCIDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7451 PCIDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7452 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7453 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7454
7455 PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7456 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7457 PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
7458 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7459 /* Stepping A2 */
7460 PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7461 /* Ethernet adapter */
7462 PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7463 PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7464 /* normal single function Ethernet controller */
7465 PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7466 /* Memory Register Base Address */
7467 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7468 /* Memory Flash Base Address */
7469 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7470 /* IO Register Base Address */
7471 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7472 /* Expansion ROM Base Address */
7473 PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7474 /* Capabilities Pointer */
7475 PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7476 /* Interrupt Pin: INTA# */
7477 PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7478 /* Max_Lat/Min_Gnt: very high priority and time slice */
7479 PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7480 PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7481
7482 /* PCI Power Management Registers ****************************************/
7483 /* Capability ID: PCI Power Management Registers */
7484 PCIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7485 /* Next Item Pointer: PCI-X */
7486 PCIDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7487 /* Power Management Capabilities: PM disabled, DSI */
7488 PCIDevSetWord( pPciDev, 0xDC + 2,
7489 0x0002 | VBOX_PCI_PM_CAP_DSI);
7490 /* Power Management Control / Status Register: PM disabled */
7491 PCIDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7492 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7493 PCIDevSetByte( pPciDev, 0xDC + 6, 0x00);
7494 /* Data Register: PM disabled, always 0 */
7495 PCIDevSetByte( pPciDev, 0xDC + 7, 0x00);
7496
7497 /* PCI-X Configuration Registers *****************************************/
7498 /* Capability ID: PCI-X Configuration Registers */
7499 PCIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7500#ifdef E1K_WITH_MSI
7501 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7502#else
7503 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7504 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7505#endif
7506 /* PCI-X Command: Enable Relaxed Ordering */
7507 PCIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7508 /* PCI-X Status: 32-bit, 66MHz*/
7509 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7510 PCIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7511}
7512
7513/**
7514 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7515 */
7516static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7517{
7518 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7519 int rc;
7520 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7521
7522 /*
7523 * Initialize the instance data (state).
7524 * Note! Caller has initialized it to ZERO already.
7525 */
7526 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7527 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7528 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7529 pThis->pDevInsR3 = pDevIns;
7530 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7531 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7532 pThis->u16TxPktLen = 0;
7533 pThis->fIPcsum = false;
7534 pThis->fTCPcsum = false;
7535 pThis->fIntMaskUsed = false;
7536 pThis->fDelayInts = false;
7537 pThis->fLocked = false;
7538 pThis->u64AckedAt = 0;
7539 pThis->led.u32Magic = PDMLED_MAGIC;
7540 pThis->u32PktNo = 1;
7541
7542 /* Interfaces */
7543 pThis->IBase.pfnQueryInterface = e1kR3QueryInterface;
7544
7545 pThis->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7546 pThis->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7547 pThis->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7548
7549 pThis->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7550
7551 pThis->INetworkConfig.pfnGetMac = e1kR3GetMac;
7552 pThis->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7553 pThis->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7554
7555 /*
7556 * Internal validations.
7557 */
7558 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7559 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7560 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7561 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7562 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7563 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7564 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7565 VERR_INTERNAL_ERROR_4);
7566
7567 /*
7568 * Validate configuration.
7569 */
7570 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0"
7571 "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"
7572 "ItrEnabled\0" "ItrRxEnabled\0"
7573 "EthernetCRC\0" "GSOEnabled\0" "LinkUpDelay\0"))
7574 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7575 N_("Invalid configuration for E1000 device"));
7576
7577 /** @todo LineSpeed unused! */
7578
7579 /* Get config params */
7580 rc = CFGMR3QueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7581 if (RT_FAILURE(rc))
7582 return PDMDEV_SET_ERROR(pDevIns, rc,
7583 N_("Configuration error: Failed to get MAC address"));
7584 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7585 if (RT_FAILURE(rc))
7586 return PDMDEV_SET_ERROR(pDevIns, rc,
7587 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7588 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7589 if (RT_FAILURE(rc))
7590 return PDMDEV_SET_ERROR(pDevIns, rc,
7591 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7592 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7593 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fRCEnabled, true);
7594 if (RT_FAILURE(rc))
7595 return PDMDEV_SET_ERROR(pDevIns, rc,
7596 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
7597
7598 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
7599 if (RT_FAILURE(rc))
7600 return PDMDEV_SET_ERROR(pDevIns, rc,
7601 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
7602
7603 rc = CFGMR3QueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7604 if (RT_FAILURE(rc))
7605 return PDMDEV_SET_ERROR(pDevIns, rc,
7606 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7607
7608 rc = CFGMR3QueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7609 if (RT_FAILURE(rc))
7610 return PDMDEV_SET_ERROR(pDevIns, rc,
7611 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7612
7613 rc = CFGMR3QueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7614 if (RT_FAILURE(rc))
7615 return PDMDEV_SET_ERROR(pDevIns, rc,
7616 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7617
7618 rc = CFGMR3QueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7619 if (RT_FAILURE(rc))
7620 return PDMDEV_SET_ERROR(pDevIns, rc,
7621 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7622
7623 rc = CFGMR3QueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7624 if (RT_FAILURE(rc))
7625 return PDMDEV_SET_ERROR(pDevIns, rc,
7626 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7627
7628 rc = CFGMR3QueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 5000); /* ms */
7629 if (RT_FAILURE(rc))
7630 return PDMDEV_SET_ERROR(pDevIns, rc,
7631 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7632 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7633 if (pThis->cMsLinkUpDelay > 5000)
7634 LogRel(("%s WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7635 else if (pThis->cMsLinkUpDelay == 0)
7636 LogRel(("%s WARNING! Link up delay is disabled!\n", pThis->szPrf));
7637
7638 LogRel(("%s Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s GC=%s\n", pThis->szPrf,
7639 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7640 pThis->fEthernetCRC ? "on" : "off",
7641 pThis->fGSOEnabled ? "enabled" : "disabled",
7642 pThis->fItrEnabled ? "enabled" : "disabled",
7643 pThis->fItrRxEnabled ? "enabled" : "disabled",
7644 pThis->fTidEnabled ? "enabled" : "disabled",
7645 pThis->fR0Enabled ? "enabled" : "disabled",
7646 pThis->fRCEnabled ? "enabled" : "disabled"));
7647
7648 /* Initialize the EEPROM. */
7649 pThis->eeprom.init(pThis->macConfigured);
7650
7651 /* Initialize internal PHY. */
7652 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7653 Phy::setLinkStatus(&pThis->phy, pThis->fCableConnected);
7654
7655 /* Initialize critical sections. We do our own locking. */
7656 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7657 AssertRCReturn(rc, rc);
7658
7659 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7660 if (RT_FAILURE(rc))
7661 return rc;
7662 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7663 if (RT_FAILURE(rc))
7664 return rc;
7665#ifdef E1K_WITH_TX_CS
7666 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7667 if (RT_FAILURE(rc))
7668 return rc;
7669#endif /* E1K_WITH_TX_CS */
7670
7671 /* Saved state registration. */
7672 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7673 NULL, e1kLiveExec, NULL,
7674 e1kSavePrep, e1kSaveExec, NULL,
7675 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7676 if (RT_FAILURE(rc))
7677 return rc;
7678
7679 /* Set PCI config registers and register ourselves with the PCI bus. */
7680 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip);
7681 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice);
7682 if (RT_FAILURE(rc))
7683 return rc;
7684
7685#ifdef E1K_WITH_MSI
7686 PDMMSIREG MsiReg;
7687 RT_ZERO(MsiReg);
7688 MsiReg.cMsiVectors = 1;
7689 MsiReg.iMsiCapOffset = 0x80;
7690 MsiReg.iMsiNextOffset = 0x0;
7691 MsiReg.fMsi64bit = false;
7692 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7693 AssertRCReturn(rc, rc);
7694#endif
7695
7696
7697 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
7698 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, e1kMap);
7699 if (RT_FAILURE(rc))
7700 return rc;
7701#ifdef E1K_WITH_PREREG_MMIO
7702 rc = PDMDevHlpMMIOExPreRegister(pDevIns, 0, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD, "E1000",
7703 NULL /*pvUserR3*/, e1kMMIOWrite, e1kMMIORead, NULL /*pfnFillR3*/,
7704 NIL_RTR0PTR /*pvUserR0*/, pThis->fR0Enabled ? "e1kMMIOWrite" : NULL,
7705 pThis->fR0Enabled ? "e1kMMIORead" : NULL, NULL /*pszFillR0*/,
7706 NIL_RTRCPTR /*pvUserRC*/, pThis->fRCEnabled ? "e1kMMIOWrite" : NULL,
7707 pThis->fRCEnabled ? "e1kMMIORead" : NULL, NULL /*pszFillRC*/);
7708 AssertLogRelRCReturn(rc, rc);
7709#endif
7710 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
7711 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE, PCI_ADDRESS_SPACE_IO, e1kMap);
7712 if (RT_FAILURE(rc))
7713 return rc;
7714
7715 /* Create transmit queue */
7716 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7717 e1kTxQueueConsumer, true, "E1000-Xmit", &pThis->pTxQueueR3);
7718 if (RT_FAILURE(rc))
7719 return rc;
7720 pThis->pTxQueueR0 = PDMQueueR0Ptr(pThis->pTxQueueR3);
7721 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7722
7723 /* Create the RX notifier signaller. */
7724 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7725 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pThis->pCanRxQueueR3);
7726 if (RT_FAILURE(rc))
7727 return rc;
7728 pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
7729 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7730
7731#ifdef E1K_TX_DELAY
7732 /* Create Transmit Delay Timer */
7733 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxDelayTimer, pThis,
7734 TMTIMER_FLAGS_NO_CRIT_SECT,
7735 "E1000 Transmit Delay Timer", &pThis->pTXDTimerR3);
7736 if (RT_FAILURE(rc))
7737 return rc;
7738 pThis->pTXDTimerR0 = TMTimerR0Ptr(pThis->pTXDTimerR3);
7739 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7740 TMR3TimerSetCritSect(pThis->pTXDTimerR3, &pThis->csTx);
7741#endif /* E1K_TX_DELAY */
7742
7743//#ifdef E1K_USE_TX_TIMERS
7744 if (pThis->fTidEnabled)
7745 {
7746 /* Create Transmit Interrupt Delay Timer */
7747 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pThis,
7748 TMTIMER_FLAGS_NO_CRIT_SECT,
7749 "E1000 Transmit Interrupt Delay Timer", &pThis->pTIDTimerR3);
7750 if (RT_FAILURE(rc))
7751 return rc;
7752 pThis->pTIDTimerR0 = TMTimerR0Ptr(pThis->pTIDTimerR3);
7753 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7754
7755# ifndef E1K_NO_TAD
7756 /* Create Transmit Absolute Delay Timer */
7757 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pThis,
7758 TMTIMER_FLAGS_NO_CRIT_SECT,
7759 "E1000 Transmit Absolute Delay Timer", &pThis->pTADTimerR3);
7760 if (RT_FAILURE(rc))
7761 return rc;
7762 pThis->pTADTimerR0 = TMTimerR0Ptr(pThis->pTADTimerR3);
7763 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7764# endif /* E1K_NO_TAD */
7765 }
7766//#endif /* E1K_USE_TX_TIMERS */
7767
7768#ifdef E1K_USE_RX_TIMERS
7769 /* Create Receive Interrupt Delay Timer */
7770 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pThis,
7771 TMTIMER_FLAGS_NO_CRIT_SECT,
7772 "E1000 Receive Interrupt Delay Timer", &pThis->pRIDTimerR3);
7773 if (RT_FAILURE(rc))
7774 return rc;
7775 pThis->pRIDTimerR0 = TMTimerR0Ptr(pThis->pRIDTimerR3);
7776 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7777
7778 /* Create Receive Absolute Delay Timer */
7779 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pThis,
7780 TMTIMER_FLAGS_NO_CRIT_SECT,
7781 "E1000 Receive Absolute Delay Timer", &pThis->pRADTimerR3);
7782 if (RT_FAILURE(rc))
7783 return rc;
7784 pThis->pRADTimerR0 = TMTimerR0Ptr(pThis->pRADTimerR3);
7785 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7786#endif /* E1K_USE_RX_TIMERS */
7787
7788 /* Create Late Interrupt Timer */
7789 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pThis,
7790 TMTIMER_FLAGS_NO_CRIT_SECT,
7791 "E1000 Late Interrupt Timer", &pThis->pIntTimerR3);
7792 if (RT_FAILURE(rc))
7793 return rc;
7794 pThis->pIntTimerR0 = TMTimerR0Ptr(pThis->pIntTimerR3);
7795 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7796
7797 /* Create Link Up Timer */
7798 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pThis,
7799 TMTIMER_FLAGS_NO_CRIT_SECT,
7800 "E1000 Link Up Timer", &pThis->pLUTimerR3);
7801 if (RT_FAILURE(rc))
7802 return rc;
7803 pThis->pLUTimerR0 = TMTimerR0Ptr(pThis->pLUTimerR3);
7804 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7805
7806 /* Register the info item */
7807 char szTmp[20];
7808 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7809 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7810
7811 /* Status driver */
7812 PPDMIBASE pBase;
7813 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
7814 if (RT_FAILURE(rc))
7815 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7816 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7817
7818 /* Network driver */
7819 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7820 if (RT_SUCCESS(rc))
7821 {
7822 if (rc == VINF_NAT_DNS)
7823 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7824 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7825 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7826 AssertMsgReturn(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7827
7828 pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7829 pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7830 }
7831 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7832 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7833 {
7834 /* No error! */
7835 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7836 }
7837 else
7838 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7839
7840 rc = RTSemEventCreate(&pThis->hEventMoreRxDescAvail);
7841 if (RT_FAILURE(rc))
7842 return rc;
7843
7844 rc = e1kInitDebugHelpers();
7845 if (RT_FAILURE(rc))
7846 return rc;
7847
7848 e1kHardReset(pThis);
7849
7850 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Public/Net/E1k%u/BytesReceived", iInstance);
7851 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Public/Net/E1k%u/BytesTransmitted", iInstance);
7852
7853 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
7854 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
7855
7856#if defined(VBOX_WITH_STATISTICS)
7857 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
7858 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
7859 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
7860 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
7861 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
7862 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
7863 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
7864 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
7865 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
7866 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
7867 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
7868 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
7869 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
7870 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
7871 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
7872 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming", "/Devices/E1k%d/Receive/CRC", iInstance);
7873 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
7874 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
7875 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
7876 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
7877 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
7878 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
7879 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
7880 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
7881
7882 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
7883 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
7884 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
7885 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
7886 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
7887 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
7888 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
7889 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
7890 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
7891 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
7892 {
7893 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7894 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Reads", iInstance, g_aE1kRegMap[iReg].abbrev);
7895 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
7896 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Writes", iInstance, g_aE1kRegMap[iReg].abbrev);
7897 }
7898#endif /* VBOX_WITH_STATISTICS */
7899
7900#ifdef E1K_INT_STATS
7901 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "u64ArmedAt", "/Devices/E1k%d/u64ArmedAt", iInstance);
7902 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatMaxTxDelay", "/Devices/E1k%d/uStatMaxTxDelay", iInstance);
7903 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatInt, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatInt", "/Devices/E1k%d/uStatInt", iInstance);
7904 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTry", "/Devices/E1k%d/uStatIntTry", iInstance);
7905 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLower", "/Devices/E1k%d/uStatIntLower", iInstance);
7906 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatNoIntICR", "/Devices/E1k%d/uStatNoIntICR", iInstance);
7907 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLost", "/Devices/E1k%d/iStatIntLost", iInstance);
7908 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLostOne", "/Devices/E1k%d/iStatIntLostOne", iInstance);
7909 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntIMS", "/Devices/E1k%d/uStatIntIMS", iInstance);
7910 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntSkip", "/Devices/E1k%d/uStatIntSkip", iInstance);
7911 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLate", "/Devices/E1k%d/uStatIntLate", iInstance);
7912 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntMasked", "/Devices/E1k%d/uStatIntMasked", iInstance);
7913 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntEarly", "/Devices/E1k%d/uStatIntEarly", iInstance);
7914 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRx", "/Devices/E1k%d/uStatIntRx", iInstance);
7915 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTx", "/Devices/E1k%d/uStatIntTx", iInstance);
7916 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntICS", "/Devices/E1k%d/uStatIntICS", iInstance);
7917 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRDTR", "/Devices/E1k%d/uStatIntRDTR", iInstance);
7918 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRXDMT0", "/Devices/E1k%d/uStatIntRXDMT0", iInstance);
7919 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTXQE", "/Devices/E1k%d/uStatIntTXQE", iInstance);
7920 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxNoRS", "/Devices/E1k%d/uStatTxNoRS", iInstance);
7921 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxIDE", "/Devices/E1k%d/uStatTxIDE", iInstance);
7922 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayed", "/Devices/E1k%d/uStatTxDelayed", iInstance);
7923 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayExp", "/Devices/E1k%d/uStatTxDelayExp", iInstance);
7924 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTAD", "/Devices/E1k%d/uStatTAD", iInstance);
7925 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTID", "/Devices/E1k%d/uStatTID", iInstance);
7926 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRAD", "/Devices/E1k%d/uStatRAD", iInstance);
7927 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRID", "/Devices/E1k%d/uStatRID", iInstance);
7928 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRxFrm", "/Devices/E1k%d/uStatRxFrm", iInstance);
7929 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxFrm", "/Devices/E1k%d/uStatTxFrm", iInstance);
7930 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescCtx", "/Devices/E1k%d/uStatDescCtx", iInstance);
7931 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescDat", "/Devices/E1k%d/uStatDescDat", iInstance);
7932 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescLeg", "/Devices/E1k%d/uStatDescLeg", iInstance);
7933 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx1514", "/Devices/E1k%d/uStatTx1514", iInstance);
7934 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx2962", "/Devices/E1k%d/uStatTx2962", iInstance);
7935 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx4410", "/Devices/E1k%d/uStatTx4410", iInstance);
7936 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx5858", "/Devices/E1k%d/uStatTx5858", iInstance);
7937 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx7306", "/Devices/E1k%d/uStatTx7306", iInstance);
7938 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx8754", "/Devices/E1k%d/uStatTx8754", iInstance);
7939 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx16384", "/Devices/E1k%d/uStatTx16384", iInstance);
7940 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx32768", "/Devices/E1k%d/uStatTx32768", iInstance);
7941 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxLarge", "/Devices/E1k%d/uStatTxLarge", iInstance);
7942#endif /* E1K_INT_STATS */
7943
7944 return VINF_SUCCESS;
7945}
7946
7947/**
7948 * The device registration structure.
7949 */
7950const PDMDEVREG g_DeviceE1000 =
7951{
7952 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
7953 PDM_DEVREG_VERSION,
7954 /* Device name. */
7955 "e1000",
7956 /* Name of guest context module (no path).
7957 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7958 "VBoxDDRC.rc",
7959 /* Name of ring-0 module (no path).
7960 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
7961 "VBoxDDR0.r0",
7962 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
7963 * remain unchanged from registration till VM destruction. */
7964 "Intel PRO/1000 MT Desktop Ethernet.\n",
7965
7966 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
7967 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
7968 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
7969 PDM_DEVREG_CLASS_NETWORK,
7970 /* Maximum number of instances (per VM). */
7971 ~0U,
7972 /* Size of the instance data. */
7973 sizeof(E1KSTATE),
7974
7975 /* pfnConstruct */
7976 e1kR3Construct,
7977 /* pfnDestruct */
7978 e1kR3Destruct,
7979 /* pfnRelocate */
7980 e1kR3Relocate,
7981 /* pfnMemSetup */
7982 NULL,
7983 /* pfnPowerOn */
7984 NULL,
7985 /* pfnReset */
7986 e1kR3Reset,
7987 /* pfnSuspend */
7988 e1kR3Suspend,
7989 /* pfnResume */
7990 NULL,
7991 /* pfnAttach */
7992 e1kR3Attach,
7993 /* pfnDeatch */
7994 e1kR3Detach,
7995 /* pfnQueryInterface */
7996 NULL,
7997 /* pfnInitComplete */
7998 NULL,
7999 /* pfnPowerOff */
8000 e1kR3PowerOff,
8001 /* pfnSoftReset */
8002 NULL,
8003
8004 /* u32VersionEnd */
8005 PDM_DEVREG_VERSION
8006};
8007
8008#endif /* IN_RING3 */
8009#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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