VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 78115

Last change on this file since 78115 was 78115, checked in by vboxsync, 6 years ago

Dev/E1000: (bugref:9427) Skip invalid TX descriptors.
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1/* $Id: DevE1000.cpp 78115 2019-04-12 07:43:08Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2019 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define STATE_TO_DEVINS(pThis) (((PE1KSTATE )pThis)->CTX_SUFF(pDevIns))
212#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
213
214#define E1K_INC_CNT32(cnt) \
215do { \
216 if (cnt < UINT32_MAX) \
217 cnt++; \
218} while (0)
219
220#define E1K_ADD_CNT64(cntLo, cntHi, val) \
221do { \
222 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
223 uint64_t tmp = u64Cnt; \
224 u64Cnt += val; \
225 if (tmp > u64Cnt ) \
226 u64Cnt = UINT64_MAX; \
227 cntLo = (uint32_t)u64Cnt; \
228 cntHi = (uint32_t)(u64Cnt >> 32); \
229} while (0)
230
231#ifdef E1K_INT_STATS
232# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
233#else /* E1K_INT_STATS */
234# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
235#endif /* E1K_INT_STATS */
236
237
238/*****************************************************************************/
239
240typedef uint32_t E1KCHIP;
241#define E1K_CHIP_82540EM 0
242#define E1K_CHIP_82543GC 1
243#define E1K_CHIP_82545EM 2
244
245#ifdef IN_RING3
246/** Different E1000 chips. */
247static const struct E1kChips
248{
249 uint16_t uPCIVendorId;
250 uint16_t uPCIDeviceId;
251 uint16_t uPCISubsystemVendorId;
252 uint16_t uPCISubsystemId;
253 const char *pcszName;
254} g_aChips[] =
255{
256 /* Vendor Device SSVendor SubSys Name */
257 { 0x8086,
258 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
259# ifdef E1K_WITH_MSI
260 0x105E,
261# else
262 0x100E,
263# endif
264 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
265 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
266 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
267};
268#endif /* IN_RING3 */
269
270
271/* The size of register area mapped to I/O space */
272#define E1K_IOPORT_SIZE 0x8
273/* The size of memory-mapped register area */
274#define E1K_MM_SIZE 0x20000
275
276#define E1K_MAX_TX_PKT_SIZE 16288
277#define E1K_MAX_RX_PKT_SIZE 16384
278
279/*****************************************************************************/
280
281/** Gets the specfieid bits from the register. */
282#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
284#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
285#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
287
288#define CTRL_SLU UINT32_C(0x00000040)
289#define CTRL_MDIO UINT32_C(0x00100000)
290#define CTRL_MDC UINT32_C(0x00200000)
291#define CTRL_MDIO_DIR UINT32_C(0x01000000)
292#define CTRL_MDC_DIR UINT32_C(0x02000000)
293#define CTRL_RESET UINT32_C(0x04000000)
294#define CTRL_VME UINT32_C(0x40000000)
295
296#define STATUS_LU UINT32_C(0x00000002)
297#define STATUS_TXOFF UINT32_C(0x00000010)
298
299#define EECD_EE_WIRES UINT32_C(0x0F)
300#define EECD_EE_REQ UINT32_C(0x40)
301#define EECD_EE_GNT UINT32_C(0x80)
302
303#define EERD_START UINT32_C(0x00000001)
304#define EERD_DONE UINT32_C(0x00000010)
305#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
306#define EERD_DATA_SHIFT 16
307#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
308#define EERD_ADDR_SHIFT 8
309
310#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
311#define MDIC_DATA_SHIFT 0
312#define MDIC_REG_MASK UINT32_C(0x001F0000)
313#define MDIC_REG_SHIFT 16
314#define MDIC_PHY_MASK UINT32_C(0x03E00000)
315#define MDIC_PHY_SHIFT 21
316#define MDIC_OP_WRITE UINT32_C(0x04000000)
317#define MDIC_OP_READ UINT32_C(0x08000000)
318#define MDIC_READY UINT32_C(0x10000000)
319#define MDIC_INT_EN UINT32_C(0x20000000)
320#define MDIC_ERROR UINT32_C(0x40000000)
321
322#define TCTL_EN UINT32_C(0x00000002)
323#define TCTL_PSP UINT32_C(0x00000008)
324
325#define RCTL_EN UINT32_C(0x00000002)
326#define RCTL_UPE UINT32_C(0x00000008)
327#define RCTL_MPE UINT32_C(0x00000010)
328#define RCTL_LPE UINT32_C(0x00000020)
329#define RCTL_LBM_MASK UINT32_C(0x000000C0)
330#define RCTL_LBM_SHIFT 6
331#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
332#define RCTL_RDMTS_SHIFT 8
333#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
334#define RCTL_MO_MASK UINT32_C(0x00003000)
335#define RCTL_MO_SHIFT 12
336#define RCTL_BAM UINT32_C(0x00008000)
337#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
338#define RCTL_BSIZE_SHIFT 16
339#define RCTL_VFE UINT32_C(0x00040000)
340#define RCTL_CFIEN UINT32_C(0x00080000)
341#define RCTL_CFI UINT32_C(0x00100000)
342#define RCTL_BSEX UINT32_C(0x02000000)
343#define RCTL_SECRC UINT32_C(0x04000000)
344
345#define ICR_TXDW UINT32_C(0x00000001)
346#define ICR_TXQE UINT32_C(0x00000002)
347#define ICR_LSC UINT32_C(0x00000004)
348#define ICR_RXDMT0 UINT32_C(0x00000010)
349#define ICR_RXT0 UINT32_C(0x00000080)
350#define ICR_TXD_LOW UINT32_C(0x00008000)
351#define RDTR_FPD UINT32_C(0x80000000)
352
353#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
354typedef struct
355{
356 unsigned rxa : 7;
357 unsigned rxa_r : 9;
358 unsigned txa : 16;
359} PBAST;
360AssertCompileSize(PBAST, 4);
361
362#define TXDCTL_WTHRESH_MASK 0x003F0000
363#define TXDCTL_WTHRESH_SHIFT 16
364#define TXDCTL_LWTHRESH_MASK 0xFE000000
365#define TXDCTL_LWTHRESH_SHIFT 25
366
367#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
368#define RXCSUM_PCSS_SHIFT 0
369
370/** @name Register access macros
371 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
372 * @{ */
373#define CTRL pThis->auRegs[CTRL_IDX]
374#define STATUS pThis->auRegs[STATUS_IDX]
375#define EECD pThis->auRegs[EECD_IDX]
376#define EERD pThis->auRegs[EERD_IDX]
377#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
378#define FLA pThis->auRegs[FLA_IDX]
379#define MDIC pThis->auRegs[MDIC_IDX]
380#define FCAL pThis->auRegs[FCAL_IDX]
381#define FCAH pThis->auRegs[FCAH_IDX]
382#define FCT pThis->auRegs[FCT_IDX]
383#define VET pThis->auRegs[VET_IDX]
384#define ICR pThis->auRegs[ICR_IDX]
385#define ITR pThis->auRegs[ITR_IDX]
386#define ICS pThis->auRegs[ICS_IDX]
387#define IMS pThis->auRegs[IMS_IDX]
388#define IMC pThis->auRegs[IMC_IDX]
389#define RCTL pThis->auRegs[RCTL_IDX]
390#define FCTTV pThis->auRegs[FCTTV_IDX]
391#define TXCW pThis->auRegs[TXCW_IDX]
392#define RXCW pThis->auRegs[RXCW_IDX]
393#define TCTL pThis->auRegs[TCTL_IDX]
394#define TIPG pThis->auRegs[TIPG_IDX]
395#define AIFS pThis->auRegs[AIFS_IDX]
396#define LEDCTL pThis->auRegs[LEDCTL_IDX]
397#define PBA pThis->auRegs[PBA_IDX]
398#define FCRTL pThis->auRegs[FCRTL_IDX]
399#define FCRTH pThis->auRegs[FCRTH_IDX]
400#define RDFH pThis->auRegs[RDFH_IDX]
401#define RDFT pThis->auRegs[RDFT_IDX]
402#define RDFHS pThis->auRegs[RDFHS_IDX]
403#define RDFTS pThis->auRegs[RDFTS_IDX]
404#define RDFPC pThis->auRegs[RDFPC_IDX]
405#define RDBAL pThis->auRegs[RDBAL_IDX]
406#define RDBAH pThis->auRegs[RDBAH_IDX]
407#define RDLEN pThis->auRegs[RDLEN_IDX]
408#define RDH pThis->auRegs[RDH_IDX]
409#define RDT pThis->auRegs[RDT_IDX]
410#define RDTR pThis->auRegs[RDTR_IDX]
411#define RXDCTL pThis->auRegs[RXDCTL_IDX]
412#define RADV pThis->auRegs[RADV_IDX]
413#define RSRPD pThis->auRegs[RSRPD_IDX]
414#define TXDMAC pThis->auRegs[TXDMAC_IDX]
415#define TDFH pThis->auRegs[TDFH_IDX]
416#define TDFT pThis->auRegs[TDFT_IDX]
417#define TDFHS pThis->auRegs[TDFHS_IDX]
418#define TDFTS pThis->auRegs[TDFTS_IDX]
419#define TDFPC pThis->auRegs[TDFPC_IDX]
420#define TDBAL pThis->auRegs[TDBAL_IDX]
421#define TDBAH pThis->auRegs[TDBAH_IDX]
422#define TDLEN pThis->auRegs[TDLEN_IDX]
423#define TDH pThis->auRegs[TDH_IDX]
424#define TDT pThis->auRegs[TDT_IDX]
425#define TIDV pThis->auRegs[TIDV_IDX]
426#define TXDCTL pThis->auRegs[TXDCTL_IDX]
427#define TADV pThis->auRegs[TADV_IDX]
428#define TSPMT pThis->auRegs[TSPMT_IDX]
429#define CRCERRS pThis->auRegs[CRCERRS_IDX]
430#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
431#define SYMERRS pThis->auRegs[SYMERRS_IDX]
432#define RXERRC pThis->auRegs[RXERRC_IDX]
433#define MPC pThis->auRegs[MPC_IDX]
434#define SCC pThis->auRegs[SCC_IDX]
435#define ECOL pThis->auRegs[ECOL_IDX]
436#define MCC pThis->auRegs[MCC_IDX]
437#define LATECOL pThis->auRegs[LATECOL_IDX]
438#define COLC pThis->auRegs[COLC_IDX]
439#define DC pThis->auRegs[DC_IDX]
440#define TNCRS pThis->auRegs[TNCRS_IDX]
441/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
442#define CEXTERR pThis->auRegs[CEXTERR_IDX]
443#define RLEC pThis->auRegs[RLEC_IDX]
444#define XONRXC pThis->auRegs[XONRXC_IDX]
445#define XONTXC pThis->auRegs[XONTXC_IDX]
446#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
447#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
448#define FCRUC pThis->auRegs[FCRUC_IDX]
449#define PRC64 pThis->auRegs[PRC64_IDX]
450#define PRC127 pThis->auRegs[PRC127_IDX]
451#define PRC255 pThis->auRegs[PRC255_IDX]
452#define PRC511 pThis->auRegs[PRC511_IDX]
453#define PRC1023 pThis->auRegs[PRC1023_IDX]
454#define PRC1522 pThis->auRegs[PRC1522_IDX]
455#define GPRC pThis->auRegs[GPRC_IDX]
456#define BPRC pThis->auRegs[BPRC_IDX]
457#define MPRC pThis->auRegs[MPRC_IDX]
458#define GPTC pThis->auRegs[GPTC_IDX]
459#define GORCL pThis->auRegs[GORCL_IDX]
460#define GORCH pThis->auRegs[GORCH_IDX]
461#define GOTCL pThis->auRegs[GOTCL_IDX]
462#define GOTCH pThis->auRegs[GOTCH_IDX]
463#define RNBC pThis->auRegs[RNBC_IDX]
464#define RUC pThis->auRegs[RUC_IDX]
465#define RFC pThis->auRegs[RFC_IDX]
466#define ROC pThis->auRegs[ROC_IDX]
467#define RJC pThis->auRegs[RJC_IDX]
468#define MGTPRC pThis->auRegs[MGTPRC_IDX]
469#define MGTPDC pThis->auRegs[MGTPDC_IDX]
470#define MGTPTC pThis->auRegs[MGTPTC_IDX]
471#define TORL pThis->auRegs[TORL_IDX]
472#define TORH pThis->auRegs[TORH_IDX]
473#define TOTL pThis->auRegs[TOTL_IDX]
474#define TOTH pThis->auRegs[TOTH_IDX]
475#define TPR pThis->auRegs[TPR_IDX]
476#define TPT pThis->auRegs[TPT_IDX]
477#define PTC64 pThis->auRegs[PTC64_IDX]
478#define PTC127 pThis->auRegs[PTC127_IDX]
479#define PTC255 pThis->auRegs[PTC255_IDX]
480#define PTC511 pThis->auRegs[PTC511_IDX]
481#define PTC1023 pThis->auRegs[PTC1023_IDX]
482#define PTC1522 pThis->auRegs[PTC1522_IDX]
483#define MPTC pThis->auRegs[MPTC_IDX]
484#define BPTC pThis->auRegs[BPTC_IDX]
485#define TSCTC pThis->auRegs[TSCTC_IDX]
486#define TSCTFC pThis->auRegs[TSCTFC_IDX]
487#define RXCSUM pThis->auRegs[RXCSUM_IDX]
488#define WUC pThis->auRegs[WUC_IDX]
489#define WUFC pThis->auRegs[WUFC_IDX]
490#define WUS pThis->auRegs[WUS_IDX]
491#define MANC pThis->auRegs[MANC_IDX]
492#define IPAV pThis->auRegs[IPAV_IDX]
493#define WUPL pThis->auRegs[WUPL_IDX]
494/** @} */
495
496/**
497 * Indices of memory-mapped registers in register table.
498 */
499typedef enum
500{
501 CTRL_IDX,
502 STATUS_IDX,
503 EECD_IDX,
504 EERD_IDX,
505 CTRL_EXT_IDX,
506 FLA_IDX,
507 MDIC_IDX,
508 FCAL_IDX,
509 FCAH_IDX,
510 FCT_IDX,
511 VET_IDX,
512 ICR_IDX,
513 ITR_IDX,
514 ICS_IDX,
515 IMS_IDX,
516 IMC_IDX,
517 RCTL_IDX,
518 FCTTV_IDX,
519 TXCW_IDX,
520 RXCW_IDX,
521 TCTL_IDX,
522 TIPG_IDX,
523 AIFS_IDX,
524 LEDCTL_IDX,
525 PBA_IDX,
526 FCRTL_IDX,
527 FCRTH_IDX,
528 RDFH_IDX,
529 RDFT_IDX,
530 RDFHS_IDX,
531 RDFTS_IDX,
532 RDFPC_IDX,
533 RDBAL_IDX,
534 RDBAH_IDX,
535 RDLEN_IDX,
536 RDH_IDX,
537 RDT_IDX,
538 RDTR_IDX,
539 RXDCTL_IDX,
540 RADV_IDX,
541 RSRPD_IDX,
542 TXDMAC_IDX,
543 TDFH_IDX,
544 TDFT_IDX,
545 TDFHS_IDX,
546 TDFTS_IDX,
547 TDFPC_IDX,
548 TDBAL_IDX,
549 TDBAH_IDX,
550 TDLEN_IDX,
551 TDH_IDX,
552 TDT_IDX,
553 TIDV_IDX,
554 TXDCTL_IDX,
555 TADV_IDX,
556 TSPMT_IDX,
557 CRCERRS_IDX,
558 ALGNERRC_IDX,
559 SYMERRS_IDX,
560 RXERRC_IDX,
561 MPC_IDX,
562 SCC_IDX,
563 ECOL_IDX,
564 MCC_IDX,
565 LATECOL_IDX,
566 COLC_IDX,
567 DC_IDX,
568 TNCRS_IDX,
569 SEC_IDX,
570 CEXTERR_IDX,
571 RLEC_IDX,
572 XONRXC_IDX,
573 XONTXC_IDX,
574 XOFFRXC_IDX,
575 XOFFTXC_IDX,
576 FCRUC_IDX,
577 PRC64_IDX,
578 PRC127_IDX,
579 PRC255_IDX,
580 PRC511_IDX,
581 PRC1023_IDX,
582 PRC1522_IDX,
583 GPRC_IDX,
584 BPRC_IDX,
585 MPRC_IDX,
586 GPTC_IDX,
587 GORCL_IDX,
588 GORCH_IDX,
589 GOTCL_IDX,
590 GOTCH_IDX,
591 RNBC_IDX,
592 RUC_IDX,
593 RFC_IDX,
594 ROC_IDX,
595 RJC_IDX,
596 MGTPRC_IDX,
597 MGTPDC_IDX,
598 MGTPTC_IDX,
599 TORL_IDX,
600 TORH_IDX,
601 TOTL_IDX,
602 TOTH_IDX,
603 TPR_IDX,
604 TPT_IDX,
605 PTC64_IDX,
606 PTC127_IDX,
607 PTC255_IDX,
608 PTC511_IDX,
609 PTC1023_IDX,
610 PTC1522_IDX,
611 MPTC_IDX,
612 BPTC_IDX,
613 TSCTC_IDX,
614 TSCTFC_IDX,
615 RXCSUM_IDX,
616 WUC_IDX,
617 WUFC_IDX,
618 WUS_IDX,
619 MANC_IDX,
620 IPAV_IDX,
621 WUPL_IDX,
622 MTA_IDX,
623 RA_IDX,
624 VFTA_IDX,
625 IP4AT_IDX,
626 IP6AT_IDX,
627 WUPM_IDX,
628 FFLT_IDX,
629 FFMT_IDX,
630 FFVT_IDX,
631 PBM_IDX,
632 RA_82542_IDX,
633 MTA_82542_IDX,
634 VFTA_82542_IDX,
635 E1K_NUM_OF_REGS
636} E1kRegIndex;
637
638#define E1K_NUM_OF_32BIT_REGS MTA_IDX
639/** The number of registers with strictly increasing offset. */
640#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
641
642
643/**
644 * Define E1000-specific EEPROM layout.
645 */
646struct E1kEEPROM
647{
648 public:
649 EEPROM93C46 eeprom;
650
651#ifdef IN_RING3
652 /**
653 * Initialize EEPROM content.
654 *
655 * @param macAddr MAC address of E1000.
656 */
657 void init(RTMAC &macAddr)
658 {
659 eeprom.init();
660 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
661 eeprom.m_au16Data[0x04] = 0xFFFF;
662 /*
663 * bit 3 - full support for power management
664 * bit 10 - full duplex
665 */
666 eeprom.m_au16Data[0x0A] = 0x4408;
667 eeprom.m_au16Data[0x0B] = 0x001E;
668 eeprom.m_au16Data[0x0C] = 0x8086;
669 eeprom.m_au16Data[0x0D] = 0x100E;
670 eeprom.m_au16Data[0x0E] = 0x8086;
671 eeprom.m_au16Data[0x0F] = 0x3040;
672 eeprom.m_au16Data[0x21] = 0x7061;
673 eeprom.m_au16Data[0x22] = 0x280C;
674 eeprom.m_au16Data[0x23] = 0x00C8;
675 eeprom.m_au16Data[0x24] = 0x00C8;
676 eeprom.m_au16Data[0x2F] = 0x0602;
677 updateChecksum();
678 };
679
680 /**
681 * Compute the checksum as required by E1000 and store it
682 * in the last word.
683 */
684 void updateChecksum()
685 {
686 uint16_t u16Checksum = 0;
687
688 for (int i = 0; i < eeprom.SIZE-1; i++)
689 u16Checksum += eeprom.m_au16Data[i];
690 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
691 };
692
693 /**
694 * First 6 bytes of EEPROM contain MAC address.
695 *
696 * @returns MAC address of E1000.
697 */
698 void getMac(PRTMAC pMac)
699 {
700 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
701 };
702
703 uint32_t read()
704 {
705 return eeprom.read();
706 }
707
708 void write(uint32_t u32Wires)
709 {
710 eeprom.write(u32Wires);
711 }
712
713 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
714 {
715 return eeprom.readWord(u32Addr, pu16Value);
716 }
717
718 int load(PSSMHANDLE pSSM)
719 {
720 return eeprom.load(pSSM);
721 }
722
723 void save(PSSMHANDLE pSSM)
724 {
725 eeprom.save(pSSM);
726 }
727#endif /* IN_RING3 */
728};
729
730
731#define E1K_SPEC_VLAN(s) (s & 0xFFF)
732#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
733#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
734
735struct E1kRxDStatus
736{
737 /** @name Descriptor Status field (3.2.3.1)
738 * @{ */
739 unsigned fDD : 1; /**< Descriptor Done. */
740 unsigned fEOP : 1; /**< End of packet. */
741 unsigned fIXSM : 1; /**< Ignore checksum indication. */
742 unsigned fVP : 1; /**< VLAN, matches VET. */
743 unsigned : 1;
744 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
745 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
746 unsigned fPIF : 1; /**< Passed in-exact filter */
747 /** @} */
748 /** @name Descriptor Errors field (3.2.3.2)
749 * (Only valid when fEOP and fDD are set.)
750 * @{ */
751 unsigned fCE : 1; /**< CRC or alignment error. */
752 unsigned : 4; /**< Reserved, varies with different models... */
753 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
754 unsigned fIPE : 1; /**< IP Checksum error. */
755 unsigned fRXE : 1; /**< RX Data error. */
756 /** @} */
757 /** @name Descriptor Special field (3.2.3.3)
758 * @{ */
759 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
760 /** @} */
761};
762typedef struct E1kRxDStatus E1KRXDST;
763
764struct E1kRxDesc_st
765{
766 uint64_t u64BufAddr; /**< Address of data buffer */
767 uint16_t u16Length; /**< Length of data in buffer */
768 uint16_t u16Checksum; /**< Packet checksum */
769 E1KRXDST status;
770};
771typedef struct E1kRxDesc_st E1KRXDESC;
772AssertCompileSize(E1KRXDESC, 16);
773
774#define E1K_DTYP_LEGACY -1
775#define E1K_DTYP_CONTEXT 0
776#define E1K_DTYP_DATA 1
777
778struct E1kTDLegacy
779{
780 uint64_t u64BufAddr; /**< Address of data buffer */
781 struct TDLCmd_st
782 {
783 unsigned u16Length : 16;
784 unsigned u8CSO : 8;
785 /* CMD field : 8 */
786 unsigned fEOP : 1;
787 unsigned fIFCS : 1;
788 unsigned fIC : 1;
789 unsigned fRS : 1;
790 unsigned fRPS : 1;
791 unsigned fDEXT : 1;
792 unsigned fVLE : 1;
793 unsigned fIDE : 1;
794 } cmd;
795 struct TDLDw3_st
796 {
797 /* STA field */
798 unsigned fDD : 1;
799 unsigned fEC : 1;
800 unsigned fLC : 1;
801 unsigned fTURSV : 1;
802 /* RSV field */
803 unsigned u4RSV : 4;
804 /* CSS field */
805 unsigned u8CSS : 8;
806 /* Special field*/
807 unsigned u16Special: 16;
808 } dw3;
809};
810
811/**
812 * TCP/IP Context Transmit Descriptor, section 3.3.6.
813 */
814struct E1kTDContext
815{
816 struct CheckSum_st
817 {
818 /** TSE: Header start. !TSE: Checksum start. */
819 unsigned u8CSS : 8;
820 /** Checksum offset - where to store it. */
821 unsigned u8CSO : 8;
822 /** Checksum ending (inclusive) offset, 0 = end of packet. */
823 unsigned u16CSE : 16;
824 } ip;
825 struct CheckSum_st tu;
826 struct TDCDw2_st
827 {
828 /** TSE: The total number of payload bytes for this context. Sans header. */
829 unsigned u20PAYLEN : 20;
830 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
831 unsigned u4DTYP : 4;
832 /** TUCMD field, 8 bits
833 * @{ */
834 /** TSE: TCP (set) or UDP (clear). */
835 unsigned fTCP : 1;
836 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
837 * the IP header. Does not affect the checksumming.
838 * @remarks 82544GC/EI interprets a cleared field differently. */
839 unsigned fIP : 1;
840 /** TSE: TCP segmentation enable. When clear the context describes */
841 unsigned fTSE : 1;
842 /** Report status (only applies to dw3.fDD for here). */
843 unsigned fRS : 1;
844 /** Reserved, MBZ. */
845 unsigned fRSV1 : 1;
846 /** Descriptor extension, must be set for this descriptor type. */
847 unsigned fDEXT : 1;
848 /** Reserved, MBZ. */
849 unsigned fRSV2 : 1;
850 /** Interrupt delay enable. */
851 unsigned fIDE : 1;
852 /** @} */
853 } dw2;
854 struct TDCDw3_st
855 {
856 /** Descriptor Done. */
857 unsigned fDD : 1;
858 /** Reserved, MBZ. */
859 unsigned u7RSV : 7;
860 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
861 unsigned u8HDRLEN : 8;
862 /** TSO: Maximum segment size. */
863 unsigned u16MSS : 16;
864 } dw3;
865};
866typedef struct E1kTDContext E1KTXCTX;
867
868/**
869 * TCP/IP Data Transmit Descriptor, section 3.3.7.
870 */
871struct E1kTDData
872{
873 uint64_t u64BufAddr; /**< Address of data buffer */
874 struct TDDCmd_st
875 {
876 /** The total length of data pointed to by this descriptor. */
877 unsigned u20DTALEN : 20;
878 /** The descriptor type - E1K_DTYP_DATA (1). */
879 unsigned u4DTYP : 4;
880 /** @name DCMD field, 8 bits (3.3.7.1).
881 * @{ */
882 /** End of packet. Note TSCTFC update. */
883 unsigned fEOP : 1;
884 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
885 unsigned fIFCS : 1;
886 /** Use the TSE context when set and the normal when clear. */
887 unsigned fTSE : 1;
888 /** Report status (dw3.STA). */
889 unsigned fRS : 1;
890 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
891 unsigned fRPS : 1;
892 /** Descriptor extension, must be set for this descriptor type. */
893 unsigned fDEXT : 1;
894 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
895 * Insert dw3.SPECIAL after ethernet header. */
896 unsigned fVLE : 1;
897 /** Interrupt delay enable. */
898 unsigned fIDE : 1;
899 /** @} */
900 } cmd;
901 struct TDDDw3_st
902 {
903 /** @name STA field (3.3.7.2)
904 * @{ */
905 unsigned fDD : 1; /**< Descriptor done. */
906 unsigned fEC : 1; /**< Excess collision. */
907 unsigned fLC : 1; /**< Late collision. */
908 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
909 unsigned fTURSV : 1;
910 /** @} */
911 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
912 /** @name POPTS (Packet Option) field (3.3.7.3)
913 * @{ */
914 unsigned fIXSM : 1; /**< Insert IP checksum. */
915 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
916 unsigned u6RSV : 6; /**< Reserved, MBZ. */
917 /** @} */
918 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
919 * Requires fEOP, fVLE and CTRL.VME to be set.
920 * @{ */
921 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
922 /** @} */
923 } dw3;
924};
925typedef struct E1kTDData E1KTXDAT;
926
927union E1kTxDesc
928{
929 struct E1kTDLegacy legacy;
930 struct E1kTDContext context;
931 struct E1kTDData data;
932};
933typedef union E1kTxDesc E1KTXDESC;
934AssertCompileSize(E1KTXDESC, 16);
935
936#define RA_CTL_AS 0x0003
937#define RA_CTL_AV 0x8000
938
939union E1kRecAddr
940{
941 uint32_t au32[32];
942 struct RAArray
943 {
944 uint8_t addr[6];
945 uint16_t ctl;
946 } array[16];
947};
948typedef struct E1kRecAddr::RAArray E1KRAELEM;
949typedef union E1kRecAddr E1KRA;
950AssertCompileSize(E1KRA, 8*16);
951
952#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
953#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
954#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
955#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
956
957/** @todo use+extend RTNETIPV4 */
958struct E1kIpHeader
959{
960 /* type of service / version / header length */
961 uint16_t tos_ver_hl;
962 /* total length */
963 uint16_t total_len;
964 /* identification */
965 uint16_t ident;
966 /* fragment offset field */
967 uint16_t offset;
968 /* time to live / protocol*/
969 uint16_t ttl_proto;
970 /* checksum */
971 uint16_t chksum;
972 /* source IP address */
973 uint32_t src;
974 /* destination IP address */
975 uint32_t dest;
976};
977AssertCompileSize(struct E1kIpHeader, 20);
978
979#define E1K_TCP_FIN UINT16_C(0x01)
980#define E1K_TCP_SYN UINT16_C(0x02)
981#define E1K_TCP_RST UINT16_C(0x04)
982#define E1K_TCP_PSH UINT16_C(0x08)
983#define E1K_TCP_ACK UINT16_C(0x10)
984#define E1K_TCP_URG UINT16_C(0x20)
985#define E1K_TCP_ECE UINT16_C(0x40)
986#define E1K_TCP_CWR UINT16_C(0x80)
987#define E1K_TCP_FLAGS UINT16_C(0x3f)
988
989/** @todo use+extend RTNETTCP */
990struct E1kTcpHeader
991{
992 uint16_t src;
993 uint16_t dest;
994 uint32_t seqno;
995 uint32_t ackno;
996 uint16_t hdrlen_flags;
997 uint16_t wnd;
998 uint16_t chksum;
999 uint16_t urgp;
1000};
1001AssertCompileSize(struct E1kTcpHeader, 20);
1002
1003
1004#ifdef E1K_WITH_TXD_CACHE
1005/** The current Saved state version. */
1006# define E1K_SAVEDSTATE_VERSION 4
1007/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1008# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1009#else /* !E1K_WITH_TXD_CACHE */
1010/** The current Saved state version. */
1011# define E1K_SAVEDSTATE_VERSION 3
1012#endif /* !E1K_WITH_TXD_CACHE */
1013/** Saved state version for VirtualBox 4.1 and earlier.
1014 * These did not include VLAN tag fields. */
1015#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1016/** Saved state version for VirtualBox 3.0 and earlier.
1017 * This did not include the configuration part nor the E1kEEPROM. */
1018#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1019
1020/**
1021 * Device state structure.
1022 *
1023 * Holds the current state of device.
1024 *
1025 * @implements PDMINETWORKDOWN
1026 * @implements PDMINETWORKCONFIG
1027 * @implements PDMILEDPORTS
1028 */
1029struct E1kState_st
1030{
1031 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1032 PDMIBASE IBase;
1033 PDMINETWORKDOWN INetworkDown;
1034 PDMINETWORKCONFIG INetworkConfig;
1035 PDMILEDPORTS ILeds; /**< LED interface */
1036 R3PTRTYPE(PPDMIBASE) pDrvBase; /**< Attached network driver. */
1037 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1038
1039 PPDMDEVINSR3 pDevInsR3; /**< Device instance - R3. */
1040 R3PTRTYPE(PPDMQUEUE) pTxQueueR3; /**< Transmit queue - R3. */
1041 R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3; /**< Rx wakeup signaller - R3. */
1042 PPDMINETWORKUPR3 pDrvR3; /**< Attached network driver - R3. */
1043 PTMTIMERR3 pRIDTimerR3; /**< Receive Interrupt Delay Timer - R3. */
1044 PTMTIMERR3 pRADTimerR3; /**< Receive Absolute Delay Timer - R3. */
1045 PTMTIMERR3 pTIDTimerR3; /**< Transmit Interrupt Delay Timer - R3. */
1046 PTMTIMERR3 pTADTimerR3; /**< Transmit Absolute Delay Timer - R3. */
1047 PTMTIMERR3 pTXDTimerR3; /**< Transmit Delay Timer - R3. */
1048 PTMTIMERR3 pIntTimerR3; /**< Late Interrupt Timer - R3. */
1049 PTMTIMERR3 pLUTimerR3; /**< Link Up(/Restore) Timer. */
1050 /** The scatter / gather buffer used for the current outgoing packet - R3. */
1051 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1052
1053 PPDMDEVINSR0 pDevInsR0; /**< Device instance - R0. */
1054 R0PTRTYPE(PPDMQUEUE) pTxQueueR0; /**< Transmit queue - R0. */
1055 R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0; /**< Rx wakeup signaller - R0. */
1056 PPDMINETWORKUPR0 pDrvR0; /**< Attached network driver - R0. */
1057 PTMTIMERR0 pRIDTimerR0; /**< Receive Interrupt Delay Timer - R0. */
1058 PTMTIMERR0 pRADTimerR0; /**< Receive Absolute Delay Timer - R0. */
1059 PTMTIMERR0 pTIDTimerR0; /**< Transmit Interrupt Delay Timer - R0. */
1060 PTMTIMERR0 pTADTimerR0; /**< Transmit Absolute Delay Timer - R0. */
1061 PTMTIMERR0 pTXDTimerR0; /**< Transmit Delay Timer - R0. */
1062 PTMTIMERR0 pIntTimerR0; /**< Late Interrupt Timer - R0. */
1063 PTMTIMERR0 pLUTimerR0; /**< Link Up(/Restore) Timer - R0. */
1064 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1065 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1066
1067 PPDMDEVINSRC pDevInsRC; /**< Device instance - RC. */
1068 RCPTRTYPE(PPDMQUEUE) pTxQueueRC; /**< Transmit queue - RC. */
1069 RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC; /**< Rx wakeup signaller - RC. */
1070 PPDMINETWORKUPRC pDrvRC; /**< Attached network driver - RC. */
1071 PTMTIMERRC pRIDTimerRC; /**< Receive Interrupt Delay Timer - RC. */
1072 PTMTIMERRC pRADTimerRC; /**< Receive Absolute Delay Timer - RC. */
1073 PTMTIMERRC pTIDTimerRC; /**< Transmit Interrupt Delay Timer - RC. */
1074 PTMTIMERRC pTADTimerRC; /**< Transmit Absolute Delay Timer - RC. */
1075 PTMTIMERRC pTXDTimerRC; /**< Transmit Delay Timer - RC. */
1076 PTMTIMERRC pIntTimerRC; /**< Late Interrupt Timer - RC. */
1077 PTMTIMERRC pLUTimerRC; /**< Link Up(/Restore) Timer - RC. */
1078 /** The scatter / gather buffer used for the current outgoing packet - RC. */
1079 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1080 RTRCPTR RCPtrAlignment;
1081
1082#if HC_ARCH_BITS != 32
1083 uint32_t Alignment1;
1084#endif
1085 PDMCRITSECT cs; /**< Critical section - what is it protecting? */
1086 PDMCRITSECT csRx; /**< RX Critical section. */
1087#ifdef E1K_WITH_TX_CS
1088 PDMCRITSECT csTx; /**< TX Critical section. */
1089#endif /* E1K_WITH_TX_CS */
1090 /** Base address of memory-mapped registers. */
1091 RTGCPHYS addrMMReg;
1092 /** MAC address obtained from the configuration. */
1093 RTMAC macConfigured;
1094 /** Base port of I/O space region. */
1095 RTIOPORT IOPortBase;
1096 /** EMT: */
1097 PDMPCIDEV pciDevice;
1098 /** EMT: Last time the interrupt was acknowledged. */
1099 uint64_t u64AckedAt;
1100 /** All: Used for eliminating spurious interrupts. */
1101 bool fIntRaised;
1102 /** EMT: false if the cable is disconnected by the GUI. */
1103 bool fCableConnected;
1104 /** EMT: */
1105 bool fR0Enabled;
1106 /** EMT: */
1107 bool fRCEnabled;
1108 /** EMT: Compute Ethernet CRC for RX packets. */
1109 bool fEthernetCRC;
1110 /** All: throttle interrupts. */
1111 bool fItrEnabled;
1112 /** All: throttle RX interrupts. */
1113 bool fItrRxEnabled;
1114 /** All: Delay TX interrupts using TIDV/TADV. */
1115 bool fTidEnabled;
1116 /** Link up delay (in milliseconds). */
1117 uint32_t cMsLinkUpDelay;
1118
1119 /** All: Device register storage. */
1120 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1121 /** TX/RX: Status LED. */
1122 PDMLED led;
1123 /** TX/RX: Number of packet being sent/received to show in debug log. */
1124 uint32_t u32PktNo;
1125
1126 /** EMT: Offset of the register to be read via IO. */
1127 uint32_t uSelectedReg;
1128 /** EMT: Multicast Table Array. */
1129 uint32_t auMTA[128];
1130 /** EMT: Receive Address registers. */
1131 E1KRA aRecAddr;
1132 /** EMT: VLAN filter table array. */
1133 uint32_t auVFTA[128];
1134 /** EMT: Receive buffer size. */
1135 uint16_t u16RxBSize;
1136 /** EMT: Locked state -- no state alteration possible. */
1137 bool fLocked;
1138 /** EMT: */
1139 bool fDelayInts;
1140 /** All: */
1141 bool fIntMaskUsed;
1142
1143 /** N/A: */
1144 bool volatile fMaybeOutOfSpace;
1145 /** EMT: Gets signalled when more RX descriptors become available. */
1146 RTSEMEVENT hEventMoreRxDescAvail;
1147#ifdef E1K_WITH_RXD_CACHE
1148 /** RX: Fetched RX descriptors. */
1149 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1150 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1151 /** RX: Actual number of fetched RX descriptors. */
1152 uint32_t nRxDFetched;
1153 /** RX: Index in cache of RX descriptor being processed. */
1154 uint32_t iRxDCurrent;
1155#endif /* E1K_WITH_RXD_CACHE */
1156
1157 /** TX: Context used for TCP segmentation packets. */
1158 E1KTXCTX contextTSE;
1159 /** TX: Context used for ordinary packets. */
1160 E1KTXCTX contextNormal;
1161#ifdef E1K_WITH_TXD_CACHE
1162 /** TX: Fetched TX descriptors. */
1163 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1164 /** TX: Actual number of fetched TX descriptors. */
1165 uint8_t nTxDFetched;
1166 /** TX: Index in cache of TX descriptor being processed. */
1167 uint8_t iTxDCurrent;
1168 /** TX: Will this frame be sent as GSO. */
1169 bool fGSO;
1170 /** Alignment padding. */
1171 bool fReserved;
1172 /** TX: Number of bytes in next packet. */
1173 uint32_t cbTxAlloc;
1174
1175#endif /* E1K_WITH_TXD_CACHE */
1176 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1177 * applicable to the current TSE mode. */
1178 PDMNETWORKGSO GsoCtx;
1179 /** Scratch space for holding the loopback / fallback scatter / gather
1180 * descriptor. */
1181 union
1182 {
1183 PDMSCATTERGATHER Sg;
1184 uint8_t padding[8 * sizeof(RTUINTPTR)];
1185 } uTxFallback;
1186 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1187 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1188 /** TX: Number of bytes assembled in TX packet buffer. */
1189 uint16_t u16TxPktLen;
1190 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1191 bool fGSOEnabled;
1192 /** TX: IP checksum has to be inserted if true. */
1193 bool fIPcsum;
1194 /** TX: TCP/UDP checksum has to be inserted if true. */
1195 bool fTCPcsum;
1196 /** TX: VLAN tag has to be inserted if true. */
1197 bool fVTag;
1198 /** TX: TCI part of VLAN tag to be inserted. */
1199 uint16_t u16VTagTCI;
1200 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1201 uint32_t u32PayRemain;
1202 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1203 uint16_t u16HdrRemain;
1204 /** TX TSE fallback: Flags from template header. */
1205 uint16_t u16SavedFlags;
1206 /** TX TSE fallback: Partial checksum from template header. */
1207 uint32_t u32SavedCsum;
1208 /** ?: Emulated controller type. */
1209 E1KCHIP eChip;
1210
1211 /** EMT: EEPROM emulation */
1212 E1kEEPROM eeprom;
1213 /** EMT: Physical interface emulation. */
1214 PHY phy;
1215
1216#if 0
1217 /** Alignment padding. */
1218 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1219#endif
1220
1221 STAMCOUNTER StatReceiveBytes;
1222 STAMCOUNTER StatTransmitBytes;
1223#if defined(VBOX_WITH_STATISTICS)
1224 STAMPROFILEADV StatMMIOReadRZ;
1225 STAMPROFILEADV StatMMIOReadR3;
1226 STAMPROFILEADV StatMMIOWriteRZ;
1227 STAMPROFILEADV StatMMIOWriteR3;
1228 STAMPROFILEADV StatEEPROMRead;
1229 STAMPROFILEADV StatEEPROMWrite;
1230 STAMPROFILEADV StatIOReadRZ;
1231 STAMPROFILEADV StatIOReadR3;
1232 STAMPROFILEADV StatIOWriteRZ;
1233 STAMPROFILEADV StatIOWriteR3;
1234 STAMPROFILEADV StatLateIntTimer;
1235 STAMCOUNTER StatLateInts;
1236 STAMCOUNTER StatIntsRaised;
1237 STAMCOUNTER StatIntsPrevented;
1238 STAMPROFILEADV StatReceive;
1239 STAMPROFILEADV StatReceiveCRC;
1240 STAMPROFILEADV StatReceiveFilter;
1241 STAMPROFILEADV StatReceiveStore;
1242 STAMPROFILEADV StatTransmitRZ;
1243 STAMPROFILEADV StatTransmitR3;
1244 STAMPROFILE StatTransmitSendRZ;
1245 STAMPROFILE StatTransmitSendR3;
1246 STAMPROFILE StatRxOverflow;
1247 STAMCOUNTER StatRxOverflowWakeup;
1248 STAMCOUNTER StatTxDescCtxNormal;
1249 STAMCOUNTER StatTxDescCtxTSE;
1250 STAMCOUNTER StatTxDescLegacy;
1251 STAMCOUNTER StatTxDescData;
1252 STAMCOUNTER StatTxDescTSEData;
1253 STAMCOUNTER StatTxPathFallback;
1254 STAMCOUNTER StatTxPathGSO;
1255 STAMCOUNTER StatTxPathRegular;
1256 STAMCOUNTER StatPHYAccesses;
1257 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1258 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1259#endif /* VBOX_WITH_STATISTICS */
1260
1261#ifdef E1K_INT_STATS
1262 /* Internal stats */
1263 uint64_t u64ArmedAt;
1264 uint64_t uStatMaxTxDelay;
1265 uint32_t uStatInt;
1266 uint32_t uStatIntTry;
1267 uint32_t uStatIntLower;
1268 uint32_t uStatNoIntICR;
1269 int32_t iStatIntLost;
1270 int32_t iStatIntLostOne;
1271 uint32_t uStatIntIMS;
1272 uint32_t uStatIntSkip;
1273 uint32_t uStatIntLate;
1274 uint32_t uStatIntMasked;
1275 uint32_t uStatIntEarly;
1276 uint32_t uStatIntRx;
1277 uint32_t uStatIntTx;
1278 uint32_t uStatIntICS;
1279 uint32_t uStatIntRDTR;
1280 uint32_t uStatIntRXDMT0;
1281 uint32_t uStatIntTXQE;
1282 uint32_t uStatTxNoRS;
1283 uint32_t uStatTxIDE;
1284 uint32_t uStatTxDelayed;
1285 uint32_t uStatTxDelayExp;
1286 uint32_t uStatTAD;
1287 uint32_t uStatTID;
1288 uint32_t uStatRAD;
1289 uint32_t uStatRID;
1290 uint32_t uStatRxFrm;
1291 uint32_t uStatTxFrm;
1292 uint32_t uStatDescCtx;
1293 uint32_t uStatDescDat;
1294 uint32_t uStatDescLeg;
1295 uint32_t uStatTx1514;
1296 uint32_t uStatTx2962;
1297 uint32_t uStatTx4410;
1298 uint32_t uStatTx5858;
1299 uint32_t uStatTx7306;
1300 uint32_t uStatTx8754;
1301 uint32_t uStatTx16384;
1302 uint32_t uStatTx32768;
1303 uint32_t uStatTxLarge;
1304 uint32_t uStatAlign;
1305#endif /* E1K_INT_STATS */
1306};
1307typedef struct E1kState_st E1KSTATE;
1308/** Pointer to the E1000 device state. */
1309typedef E1KSTATE *PE1KSTATE;
1310
1311#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1312
1313/* Forward declarations ******************************************************/
1314static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread);
1315
1316static int e1kRegReadUnimplemented (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1317static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1318static int e1kRegReadAutoClear (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1319static int e1kRegReadDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1320static int e1kRegWriteDefault (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1321#if 0 /* unused */
1322static int e1kRegReadCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1323#endif
1324static int e1kRegWriteCTRL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1325static int e1kRegReadEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1326static int e1kRegWriteEECD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1327static int e1kRegWriteEERD (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1328static int e1kRegWriteMDIC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1329static int e1kRegReadICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1330static int e1kRegWriteICR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1331static int e1kRegWriteICS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1332static int e1kRegWriteIMS (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1333static int e1kRegWriteIMC (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1334static int e1kRegWriteRCTL (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1335static int e1kRegWritePBA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1336static int e1kRegWriteRDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1337static int e1kRegWriteRDTR (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1338static int e1kRegWriteTDT (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1339static int e1kRegReadMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1340static int e1kRegWriteMTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1341static int e1kRegReadRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1342static int e1kRegWriteRA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1343static int e1kRegReadVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1344static int e1kRegWriteVFTA (PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1345
1346/**
1347 * Register map table.
1348 *
1349 * Override pfnRead and pfnWrite to get register-specific behavior.
1350 */
1351static const struct E1kRegMap_st
1352{
1353 /** Register offset in the register space. */
1354 uint32_t offset;
1355 /** Size in bytes. Registers of size > 4 are in fact tables. */
1356 uint32_t size;
1357 /** Readable bits. */
1358 uint32_t readable;
1359 /** Writable bits. */
1360 uint32_t writable;
1361 /** Read callback. */
1362 int (*pfnRead)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1363 /** Write callback. */
1364 int (*pfnWrite)(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1365 /** Abbreviated name. */
1366 const char *abbrev;
1367 /** Full name. */
1368 const char *name;
1369} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1370{
1371 /* offset size read mask write mask read callback write callback abbrev full name */
1372 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1373 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1374 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1375 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1376 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1377 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1378 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1379 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1380 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1381 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1382 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1383 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1384 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1385 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1386 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1387 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1388 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1389 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1390 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1391 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1392 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1393 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1394 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1395 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1396 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1397 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1398 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1399 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1400 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1401 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1402 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1403 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1404 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1405 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1406 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1407 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1408 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1409 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1410 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1411 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1412 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1413 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1414 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1415 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1416 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1417 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1418 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1419 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1420 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1421 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1422 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1423 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1424 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1425 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1426 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1427 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1428 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1429 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1430 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1431 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1432 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1433 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1434 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1435 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1436 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1437 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1438 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1439 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1440 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1441 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1442 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1443 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1444 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1445 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1446 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1447 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1448 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1449 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1450 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1451 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1452 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1453 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1454 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1455 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1456 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1457 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1458 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1459 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1460 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1461 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1462 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1463 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1464 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1465 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1466 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1467 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1468 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1469 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1470 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1471 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1472 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1473 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1474 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1475 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1476 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1477 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1478 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1479 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1480 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1481 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1482 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1483 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1484 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1485 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1486 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1487 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1488 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1489 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1490 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1491 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1492 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1493 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1494 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1495 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1496 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1497 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1498 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1499 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1500 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1501 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1502 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1503 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1504 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1505 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1506 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1507};
1508
1509#ifdef LOG_ENABLED
1510
1511/**
1512 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1513 *
1514 * @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
1515 *
1516 * @returns The buffer.
1517 *
1518 * @param u32 The word to convert into string.
1519 * @param mask Selects which bytes to convert.
1520 * @param buf Where to put the result.
1521 */
1522static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1523{
1524 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1525 {
1526 if (mask & 0xF)
1527 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1528 else
1529 *ptr = '.';
1530 }
1531 buf[8] = 0;
1532 return buf;
1533}
1534
1535/**
1536 * Returns timer name for debug purposes.
1537 *
1538 * @returns The timer name.
1539 *
1540 * @param pThis The device state structure.
1541 * @param pTimer The timer to get the name for.
1542 */
1543DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, PTMTIMER pTimer)
1544{
1545 if (pTimer == pThis->CTX_SUFF(pTIDTimer))
1546 return "TID";
1547 if (pTimer == pThis->CTX_SUFF(pTADTimer))
1548 return "TAD";
1549 if (pTimer == pThis->CTX_SUFF(pRIDTimer))
1550 return "RID";
1551 if (pTimer == pThis->CTX_SUFF(pRADTimer))
1552 return "RAD";
1553 if (pTimer == pThis->CTX_SUFF(pIntTimer))
1554 return "Int";
1555 if (pTimer == pThis->CTX_SUFF(pTXDTimer))
1556 return "TXD";
1557 if (pTimer == pThis->CTX_SUFF(pLUTimer))
1558 return "LinkUp";
1559 return "unknown";
1560}
1561
1562#endif /* DEBUG */
1563
1564/**
1565 * Arm a timer.
1566 *
1567 * @param pThis Pointer to the device state structure.
1568 * @param pTimer Pointer to the timer.
1569 * @param uExpireIn Expiration interval in microseconds.
1570 */
1571DECLINLINE(void) e1kArmTimer(PE1KSTATE pThis, PTMTIMER pTimer, uint32_t uExpireIn)
1572{
1573 if (pThis->fLocked)
1574 return;
1575
1576 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1577 pThis->szPrf, e1kGetTimerName(pThis, pTimer), uExpireIn));
1578 TMTimerSetMicro(pTimer, uExpireIn);
1579}
1580
1581#ifdef IN_RING3
1582/**
1583 * Cancel a timer.
1584 *
1585 * @param pThis Pointer to the device state structure.
1586 * @param pTimer Pointer to the timer.
1587 */
1588DECLINLINE(void) e1kCancelTimer(PE1KSTATE pThis, PTMTIMER pTimer)
1589{
1590 E1kLog2(("%s Stopping %s timer...\n",
1591 pThis->szPrf, e1kGetTimerName(pThis, pTimer)));
1592 int rc = TMTimerStop(pTimer);
1593 if (RT_FAILURE(rc))
1594 E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
1595 pThis->szPrf, rc));
1596 RT_NOREF1(pThis);
1597}
1598#endif /* IN_RING3 */
1599
1600#define e1kCsEnter(ps, rc) PDMCritSectEnter(&ps->cs, rc)
1601#define e1kCsLeave(ps) PDMCritSectLeave(&ps->cs)
1602
1603#define e1kCsRxEnter(ps, rc) PDMCritSectEnter(&ps->csRx, rc)
1604#define e1kCsRxLeave(ps) PDMCritSectLeave(&ps->csRx)
1605#define e1kCsRxIsOwner(ps) PDMCritSectIsOwner(&ps->csRx)
1606
1607#ifndef E1K_WITH_TX_CS
1608# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1609# define e1kCsTxLeave(ps) do { } while (0)
1610#else /* E1K_WITH_TX_CS */
1611# define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
1612# define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
1613#endif /* E1K_WITH_TX_CS */
1614
1615#ifdef IN_RING3
1616
1617/**
1618 * Wakeup the RX thread.
1619 */
1620static void e1kWakeupReceive(PPDMDEVINS pDevIns)
1621{
1622 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
1623 if ( pThis->fMaybeOutOfSpace
1624 && pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
1625 {
1626 STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);
1627 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1628 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
1629 }
1630}
1631
1632/**
1633 * Hardware reset. Revert all registers to initial values.
1634 *
1635 * @param pThis The device state structure.
1636 */
1637static void e1kHardReset(PE1KSTATE pThis)
1638{
1639 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1640 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1641 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1642#ifdef E1K_INIT_RA0
1643 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1644 sizeof(pThis->macConfigured.au8));
1645 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1646#endif /* E1K_INIT_RA0 */
1647 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1648 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1649 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1650 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1651 Assert(GET_BITS(RCTL, BSIZE) == 0);
1652 pThis->u16RxBSize = 2048;
1653
1654 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1655 pThis->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1656 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1657
1658 /* Reset promiscuous mode */
1659 if (pThis->pDrvR3)
1660 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, false);
1661
1662#ifdef E1K_WITH_TXD_CACHE
1663 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1664 if (RT_LIKELY(rc == VINF_SUCCESS))
1665 {
1666 pThis->nTxDFetched = 0;
1667 pThis->iTxDCurrent = 0;
1668 pThis->fGSO = false;
1669 pThis->cbTxAlloc = 0;
1670 e1kCsTxLeave(pThis);
1671 }
1672#endif /* E1K_WITH_TXD_CACHE */
1673#ifdef E1K_WITH_RXD_CACHE
1674 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1675 {
1676 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1677 e1kCsRxLeave(pThis);
1678 }
1679#endif /* E1K_WITH_RXD_CACHE */
1680#ifdef E1K_LSC_ON_RESET
1681 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1682 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1683 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
1684#endif /* E1K_LSC_ON_RESET */
1685}
1686
1687#endif /* IN_RING3 */
1688
1689/**
1690 * Compute Internet checksum.
1691 *
1692 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1693 *
1694 * @param pThis The device state structure.
1695 * @param cpPacket The packet.
1696 * @param cb The size of the packet.
1697 * @param pszText A string denoting direction of packet transfer.
1698 *
1699 * @return The 1's complement of the 1's complement sum.
1700 *
1701 * @thread E1000_TX
1702 */
1703static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1704{
1705 uint32_t csum = 0;
1706 uint16_t *pu16 = (uint16_t *)pvBuf;
1707
1708 while (cb > 1)
1709 {
1710 csum += *pu16++;
1711 cb -= 2;
1712 }
1713 if (cb)
1714 csum += *(uint8_t*)pu16;
1715 while (csum >> 16)
1716 csum = (csum >> 16) + (csum & 0xFFFF);
1717 return ~csum;
1718}
1719
1720/**
1721 * Dump a packet to debug log.
1722 *
1723 * @param pThis The device state structure.
1724 * @param cpPacket The packet.
1725 * @param cb The size of the packet.
1726 * @param pszText A string denoting direction of packet transfer.
1727 * @thread E1000_TX
1728 */
1729DECLINLINE(void) e1kPacketDump(PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1730{
1731#ifdef DEBUG
1732 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1733 {
1734 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1735 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1736 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1737 {
1738 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1739 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1740 if (*(cpPacket+14+6) == 0x6)
1741 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1742 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1743 }
1744 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1745 {
1746 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1747 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1748 if (*(cpPacket+14+6) == 0x6)
1749 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1750 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1751 }
1752 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1753 e1kCsLeave(pThis);
1754 }
1755#else
1756 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1757 {
1758 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1759 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1760 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1761 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1762 else
1763 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1764 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1765 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1766 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1767 e1kCsLeave(pThis);
1768 }
1769 RT_NOREF2(cb, pszText);
1770#endif
1771}
1772
1773/**
1774 * Determine the type of transmit descriptor.
1775 *
1776 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1777 *
1778 * @param pDesc Pointer to descriptor union.
1779 * @thread E1000_TX
1780 */
1781DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1782{
1783 if (pDesc->legacy.cmd.fDEXT)
1784 return pDesc->context.dw2.u4DTYP;
1785 return E1K_DTYP_LEGACY;
1786}
1787
1788
1789#ifdef E1K_WITH_RXD_CACHE
1790/**
1791 * Return the number of RX descriptor that belong to the hardware.
1792 *
1793 * @returns the number of available descriptors in RX ring.
1794 * @param pThis The device state structure.
1795 * @thread ???
1796 */
1797DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
1798{
1799 /**
1800 * Make sure RDT won't change during computation. EMT may modify RDT at
1801 * any moment.
1802 */
1803 uint32_t rdt = RDT;
1804 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
1805}
1806
1807DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1808{
1809 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1810 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1811}
1812
1813DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1814{
1815 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1816}
1817
1818/**
1819 * Load receive descriptors from guest memory. The caller needs to be in Rx
1820 * critical section.
1821 *
1822 * We need two physical reads in case the tail wrapped around the end of RX
1823 * descriptor ring.
1824 *
1825 * @returns the actual number of descriptors fetched.
1826 * @param pThis The device state structure.
1827 * @param pDesc Pointer to descriptor union.
1828 * @param addr Physical address in guest context.
1829 * @thread EMT, RX
1830 */
1831DECLINLINE(unsigned) e1kRxDPrefetch(PE1KSTATE pThis)
1832{
1833 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1834 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
1835 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1836 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
1837 Assert(nDescsTotal != 0);
1838 if (nDescsTotal == 0)
1839 return 0;
1840 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
1841 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
1842 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
1843 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
1844 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
1845 nFirstNotLoaded, nDescsInSingleRead));
1846 if (nDescsToFetch == 0)
1847 return 0;
1848 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
1849 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
1850 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
1851 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
1852 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
1853 // unsigned i, j;
1854 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
1855 // {
1856 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
1857 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1858 // }
1859 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
1860 pThis->szPrf, nDescsInSingleRead,
1861 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
1862 nFirstNotLoaded, RDLEN, RDH, RDT));
1863 if (nDescsToFetch > nDescsInSingleRead)
1864 {
1865 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
1866 ((uint64_t)RDBAH << 32) + RDBAL,
1867 pFirstEmptyDesc + nDescsInSingleRead,
1868 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
1869 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
1870 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
1871 // {
1872 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
1873 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1874 // }
1875 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
1876 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
1877 RDBAH, RDBAL));
1878 }
1879 pThis->nRxDFetched += nDescsToFetch;
1880 return nDescsToFetch;
1881}
1882
1883# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
1884/**
1885 * Dump receive descriptor to debug log.
1886 *
1887 * @param pThis The device state structure.
1888 * @param pDesc Pointer to the descriptor.
1889 * @thread E1000_RX
1890 */
1891static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
1892{
1893 RT_NOREF2(pThis, pDesc);
1894 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1895 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1896 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1897 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1898 pDesc->status.fPIF ? "PIF" : "pif",
1899 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1900 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1901 pDesc->status.fVP ? "VP" : "vp",
1902 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1903 pDesc->status.fEOP ? "EOP" : "eop",
1904 pDesc->status.fDD ? "DD" : "dd",
1905 pDesc->status.fRXE ? "RXE" : "rxe",
1906 pDesc->status.fIPE ? "IPE" : "ipe",
1907 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1908 pDesc->status.fCE ? "CE" : "ce",
1909 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1910 E1K_SPEC_VLAN(pDesc->status.u16Special),
1911 E1K_SPEC_PRI(pDesc->status.u16Special)));
1912}
1913# endif /* IN_RING3 */
1914#endif /* E1K_WITH_RXD_CACHE */
1915
1916/**
1917 * Dump transmit descriptor to debug log.
1918 *
1919 * @param pThis The device state structure.
1920 * @param pDesc Pointer to descriptor union.
1921 * @param pszDir A string denoting direction of descriptor transfer
1922 * @thread E1000_TX
1923 */
1924static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
1925 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1926{
1927 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
1928
1929 /*
1930 * Unfortunately we cannot use our format handler here, we want R0 logging
1931 * as well.
1932 */
1933 switch (e1kGetDescType(pDesc))
1934 {
1935 case E1K_DTYP_CONTEXT:
1936 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
1937 pThis->szPrf, pszDir, pszDir));
1938 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
1939 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
1940 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
1941 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
1942 pDesc->context.dw2.fIDE ? " IDE":"",
1943 pDesc->context.dw2.fRS ? " RS" :"",
1944 pDesc->context.dw2.fTSE ? " TSE":"",
1945 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
1946 pDesc->context.dw2.fTCP ? "TCP":"UDP",
1947 pDesc->context.dw2.u20PAYLEN,
1948 pDesc->context.dw3.u8HDRLEN,
1949 pDesc->context.dw3.u16MSS,
1950 pDesc->context.dw3.fDD?"DD":""));
1951 break;
1952 case E1K_DTYP_DATA:
1953 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
1954 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
1955 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1956 pDesc->data.u64BufAddr,
1957 pDesc->data.cmd.u20DTALEN));
1958 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
1959 pDesc->data.cmd.fIDE ? " IDE" :"",
1960 pDesc->data.cmd.fVLE ? " VLE" :"",
1961 pDesc->data.cmd.fRPS ? " RPS" :"",
1962 pDesc->data.cmd.fRS ? " RS" :"",
1963 pDesc->data.cmd.fTSE ? " TSE" :"",
1964 pDesc->data.cmd.fIFCS? " IFCS":"",
1965 pDesc->data.cmd.fEOP ? " EOP" :"",
1966 pDesc->data.dw3.fDD ? " DD" :"",
1967 pDesc->data.dw3.fEC ? " EC" :"",
1968 pDesc->data.dw3.fLC ? " LC" :"",
1969 pDesc->data.dw3.fTXSM? " TXSM":"",
1970 pDesc->data.dw3.fIXSM? " IXSM":"",
1971 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
1972 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
1973 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
1974 break;
1975 case E1K_DTYP_LEGACY:
1976 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
1977 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
1978 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
1979 pDesc->data.u64BufAddr,
1980 pDesc->legacy.cmd.u16Length));
1981 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
1982 pDesc->legacy.cmd.fIDE ? " IDE" :"",
1983 pDesc->legacy.cmd.fVLE ? " VLE" :"",
1984 pDesc->legacy.cmd.fRPS ? " RPS" :"",
1985 pDesc->legacy.cmd.fRS ? " RS" :"",
1986 pDesc->legacy.cmd.fIC ? " IC" :"",
1987 pDesc->legacy.cmd.fIFCS? " IFCS":"",
1988 pDesc->legacy.cmd.fEOP ? " EOP" :"",
1989 pDesc->legacy.dw3.fDD ? " DD" :"",
1990 pDesc->legacy.dw3.fEC ? " EC" :"",
1991 pDesc->legacy.dw3.fLC ? " LC" :"",
1992 pDesc->legacy.cmd.u8CSO,
1993 pDesc->legacy.dw3.u8CSS,
1994 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
1995 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
1996 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
1997 break;
1998 default:
1999 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2000 pThis->szPrf, pszDir, pszDir));
2001 break;
2002 }
2003}
2004
2005/**
2006 * Raise an interrupt later.
2007 *
2008 * @param pThis The device state structure.
2009 */
2010inline void e1kPostponeInterrupt(PE1KSTATE pThis, uint64_t uNanoseconds)
2011{
2012 if (!TMTimerIsActive(pThis->CTX_SUFF(pIntTimer)))
2013 TMTimerSetNano(pThis->CTX_SUFF(pIntTimer), uNanoseconds);
2014}
2015
2016/**
2017 * Raise interrupt if not masked.
2018 *
2019 * @param pThis The device state structure.
2020 */
2021static int e1kRaiseInterrupt(PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
2022{
2023 int rc = e1kCsEnter(pThis, rcBusy);
2024 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2025 return rc;
2026
2027 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2028 ICR |= u32IntCause;
2029 if (ICR & IMS)
2030 {
2031 if (pThis->fIntRaised)
2032 {
2033 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2034 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2035 pThis->szPrf, ICR & IMS));
2036 }
2037 else
2038 {
2039 uint64_t tsNow = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
2040 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2041 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2042 {
2043 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2044 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2045 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2046 e1kPostponeInterrupt(pThis, ITR * 256);
2047 }
2048 else
2049 {
2050
2051 /* Since we are delivering the interrupt now
2052 * there is no need to do it later -- stop the timer.
2053 */
2054 TMTimerStop(pThis->CTX_SUFF(pIntTimer));
2055 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2056 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2057 /* Got at least one unmasked interrupt cause */
2058 pThis->fIntRaised = true;
2059 /* Raise(1) INTA(0) */
2060 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2061 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 1);
2062 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2063 pThis->szPrf, ICR & IMS));
2064 }
2065 }
2066 }
2067 else
2068 {
2069 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2070 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2071 pThis->szPrf, ICR, IMS));
2072 }
2073 e1kCsLeave(pThis);
2074 return VINF_SUCCESS;
2075}
2076
2077/**
2078 * Compute the physical address of the descriptor.
2079 *
2080 * @returns the physical address of the descriptor.
2081 *
2082 * @param baseHigh High-order 32 bits of descriptor table address.
2083 * @param baseLow Low-order 32 bits of descriptor table address.
2084 * @param idxDesc The descriptor index in the table.
2085 */
2086DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2087{
2088 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2089 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2090}
2091
2092#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2093/**
2094 * Advance the head pointer of the receive descriptor queue.
2095 *
2096 * @remarks RDH always points to the next available RX descriptor.
2097 *
2098 * @param pThis The device state structure.
2099 */
2100DECLINLINE(void) e1kAdvanceRDH(PE1KSTATE pThis)
2101{
2102 Assert(e1kCsRxIsOwner(pThis));
2103 //e1kCsEnter(pThis, RT_SRC_POS);
2104 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
2105 RDH = 0;
2106#ifdef E1K_WITH_RXD_CACHE
2107 /*
2108 * We need to fetch descriptors now as the guest may advance RDT all the way
2109 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2110 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2111 * check if the receiver is enabled. It must be, otherwise we won't get here
2112 * in the first place.
2113 *
2114 * Note that we should have moved both RDH and iRxDCurrent by now.
2115 */
2116 if (e1kRxDIsCacheEmpty(pThis))
2117 {
2118 /* Cache is empty, reset it and check if we can fetch more. */
2119 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2120 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2121 "iRxDCurrent=%x nRxDFetched=%x\n",
2122 pThis->szPrf, RDH, RDT, pThis->iRxDCurrent, pThis->nRxDFetched));
2123 e1kRxDPrefetch(pThis);
2124 }
2125#endif /* E1K_WITH_RXD_CACHE */
2126 /*
2127 * Compute current receive queue length and fire RXDMT0 interrupt
2128 * if we are low on receive buffers
2129 */
2130 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
2131 /*
2132 * The minimum threshold is controlled by RDMTS bits of RCTL:
2133 * 00 = 1/2 of RDLEN
2134 * 01 = 1/4 of RDLEN
2135 * 10 = 1/8 of RDLEN
2136 * 11 = reserved
2137 */
2138 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2139 if (uRQueueLen <= uMinRQThreshold)
2140 {
2141 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
2142 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2143 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
2144 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2145 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2146 }
2147 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2148 pThis->szPrf, RDH, RDT, uRQueueLen));
2149 //e1kCsLeave(pThis);
2150}
2151#endif /* IN_RING3 */
2152
2153#ifdef E1K_WITH_RXD_CACHE
2154
2155# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2156
2157/**
2158 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2159 * RX ring if the cache is empty.
2160 *
2161 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2162 * go out of sync with RDH which will cause trouble when EMT checks if the
2163 * cache is empty to do pre-fetch @bugref(6217).
2164 *
2165 * @param pThis The device state structure.
2166 * @thread RX
2167 */
2168DECLINLINE(E1KRXDESC*) e1kRxDGet(PE1KSTATE pThis)
2169{
2170 Assert(e1kCsRxIsOwner(pThis));
2171 /* Check the cache first. */
2172 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2173 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2174 /* Cache is empty, reset it and check if we can fetch more. */
2175 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2176 if (e1kRxDPrefetch(pThis))
2177 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2178 /* Out of Rx descriptors. */
2179 return NULL;
2180}
2181
2182
2183/**
2184 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2185 * pointer. The descriptor gets written back to the RXD ring.
2186 *
2187 * @param pThis The device state structure.
2188 * @param pDesc The descriptor being "returned" to the RX ring.
2189 * @thread RX
2190 */
2191DECLINLINE(void) e1kRxDPut(PE1KSTATE pThis, E1KRXDESC* pDesc)
2192{
2193 Assert(e1kCsRxIsOwner(pThis));
2194 pThis->iRxDCurrent++;
2195 // Assert(pDesc >= pThis->aRxDescriptors);
2196 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2197 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2198 // uint32_t rdh = RDH;
2199 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2200 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2201 e1kDescAddr(RDBAH, RDBAL, RDH),
2202 pDesc, sizeof(E1KRXDESC));
2203 /*
2204 * We need to print the descriptor before advancing RDH as it may fetch new
2205 * descriptors into the cache.
2206 */
2207 e1kPrintRDesc(pThis, pDesc);
2208 e1kAdvanceRDH(pThis);
2209}
2210
2211/**
2212 * Store a fragment of received packet at the specifed address.
2213 *
2214 * @param pThis The device state structure.
2215 * @param pDesc The next available RX descriptor.
2216 * @param pvBuf The fragment.
2217 * @param cb The size of the fragment.
2218 */
2219static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2220{
2221 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2222 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2223 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2224 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2225 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2226 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2227}
2228
2229# endif /* IN_RING3 */
2230
2231#else /* !E1K_WITH_RXD_CACHE */
2232
2233/**
2234 * Store a fragment of received packet that fits into the next available RX
2235 * buffer.
2236 *
2237 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2238 *
2239 * @param pThis The device state structure.
2240 * @param pDesc The next available RX descriptor.
2241 * @param pvBuf The fragment.
2242 * @param cb The size of the fragment.
2243 */
2244static DECLCALLBACK(void) e1kStoreRxFragment(PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2245{
2246 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2247 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2248 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->u64BufAddr, pvBuf, cb);
2249 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2250 /* Write back the descriptor */
2251 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2252 e1kPrintRDesc(pThis, pDesc);
2253 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2254 /* Advance head */
2255 e1kAdvanceRDH(pThis);
2256 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2257 if (pDesc->status.fEOP)
2258 {
2259 /* Complete packet has been stored -- it is time to let the guest know. */
2260#ifdef E1K_USE_RX_TIMERS
2261 if (RDTR)
2262 {
2263 /* Arm the timer to fire in RDTR usec (discard .024) */
2264 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2265 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2266 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2267 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2268 }
2269 else
2270 {
2271#endif
2272 /* 0 delay means immediate interrupt */
2273 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2274 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2275#ifdef E1K_USE_RX_TIMERS
2276 }
2277#endif
2278 }
2279 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2280}
2281
2282#endif /* !E1K_WITH_RXD_CACHE */
2283
2284/**
2285 * Returns true if it is a broadcast packet.
2286 *
2287 * @returns true if destination address indicates broadcast.
2288 * @param pvBuf The ethernet packet.
2289 */
2290DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2291{
2292 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2293 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2294}
2295
2296/**
2297 * Returns true if it is a multicast packet.
2298 *
2299 * @remarks returns true for broadcast packets as well.
2300 * @returns true if destination address indicates multicast.
2301 * @param pvBuf The ethernet packet.
2302 */
2303DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2304{
2305 return (*(char*)pvBuf) & 1;
2306}
2307
2308#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2309/**
2310 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2311 *
2312 * @remarks We emulate checksum offloading for major packets types only.
2313 *
2314 * @returns VBox status code.
2315 * @param pThis The device state structure.
2316 * @param pFrame The available data.
2317 * @param cb Number of bytes available in the buffer.
2318 * @param status Bit fields containing status info.
2319 */
2320static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2321{
2322 /** @todo
2323 * It is not safe to bypass checksum verification for packets coming
2324 * from real wire. We currently unable to tell where packets are
2325 * coming from so we tell the driver to ignore our checksum flags
2326 * and do verification in software.
2327 */
2328# if 0
2329 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2330
2331 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2332
2333 switch (uEtherType)
2334 {
2335 case 0x800: /* IPv4 */
2336 {
2337 pStatus->fIXSM = false;
2338 pStatus->fIPCS = true;
2339 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2340 /* TCP/UDP checksum offloading works with TCP and UDP only */
2341 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2342 break;
2343 }
2344 case 0x86DD: /* IPv6 */
2345 pStatus->fIXSM = false;
2346 pStatus->fIPCS = false;
2347 pStatus->fTCPCS = true;
2348 break;
2349 default: /* ARP, VLAN, etc. */
2350 pStatus->fIXSM = true;
2351 break;
2352 }
2353# else
2354 pStatus->fIXSM = true;
2355 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2356# endif
2357 return VINF_SUCCESS;
2358}
2359#endif /* IN_RING3 */
2360
2361/**
2362 * Pad and store received packet.
2363 *
2364 * @remarks Make sure that the packet appears to upper layer as one coming
2365 * from real Ethernet: pad it and insert FCS.
2366 *
2367 * @returns VBox status code.
2368 * @param pThis The device state structure.
2369 * @param pvBuf The available data.
2370 * @param cb Number of bytes available in the buffer.
2371 * @param status Bit fields containing status info.
2372 */
2373static int e1kHandleRxPacket(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2374{
2375#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2376 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2377 uint8_t *ptr = rxPacket;
2378
2379 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2380 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2381 return rc;
2382
2383 if (cb > 70) /* unqualified guess */
2384 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2385
2386 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2387 Assert(cb > 16);
2388 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2389 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2390 if (status.fVP)
2391 {
2392 /* VLAN packet -- strip VLAN tag in VLAN mode */
2393 if ((CTRL & CTRL_VME) && cb > 16)
2394 {
2395 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2396 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2397 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2398 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2399 cb -= 4;
2400 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2401 pThis->szPrf, status.u16Special, cb));
2402 }
2403 else
2404 status.fVP = false; /* Set VP only if we stripped the tag */
2405 }
2406 else
2407 memcpy(rxPacket, pvBuf, cb);
2408 /* Pad short packets */
2409 if (cb < 60)
2410 {
2411 memset(rxPacket + cb, 0, 60 - cb);
2412 cb = 60;
2413 }
2414 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2415 {
2416 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2417 /*
2418 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2419 * is ignored by most of drivers we may as well save us the trouble
2420 * of calculating it (see EthernetCRC CFGM parameter).
2421 */
2422 if (pThis->fEthernetCRC)
2423 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2424 cb += sizeof(uint32_t);
2425 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2426 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2427 }
2428 /* Compute checksum of complete packet */
2429 uint16_t checksum = e1kCSum16(rxPacket + GET_BITS(RXCSUM, PCSS), cb);
2430 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2431
2432 /* Update stats */
2433 E1K_INC_CNT32(GPRC);
2434 if (e1kIsBroadcast(pvBuf))
2435 E1K_INC_CNT32(BPRC);
2436 else if (e1kIsMulticast(pvBuf))
2437 E1K_INC_CNT32(MPRC);
2438 /* Update octet receive counter */
2439 E1K_ADD_CNT64(GORCL, GORCH, cb);
2440 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2441 if (cb == 64)
2442 E1K_INC_CNT32(PRC64);
2443 else if (cb < 128)
2444 E1K_INC_CNT32(PRC127);
2445 else if (cb < 256)
2446 E1K_INC_CNT32(PRC255);
2447 else if (cb < 512)
2448 E1K_INC_CNT32(PRC511);
2449 else if (cb < 1024)
2450 E1K_INC_CNT32(PRC1023);
2451 else
2452 E1K_INC_CNT32(PRC1522);
2453
2454 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2455
2456# ifdef E1K_WITH_RXD_CACHE
2457 while (cb > 0)
2458 {
2459 E1KRXDESC *pDesc = e1kRxDGet(pThis);
2460
2461 if (pDesc == NULL)
2462 {
2463 E1kLog(("%s Out of receive buffers, dropping the packet "
2464 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2465 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2466 break;
2467 }
2468# else /* !E1K_WITH_RXD_CACHE */
2469 if (RDH == RDT)
2470 {
2471 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2472 pThis->szPrf));
2473 }
2474 /* Store the packet to receive buffers */
2475 while (RDH != RDT)
2476 {
2477 /* Load the descriptor pointed by head */
2478 E1KRXDESC desc, *pDesc = &desc;
2479 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
2480 &desc, sizeof(desc));
2481# endif /* !E1K_WITH_RXD_CACHE */
2482 if (pDesc->u64BufAddr)
2483 {
2484 /* Update descriptor */
2485 pDesc->status = status;
2486 pDesc->u16Checksum = checksum;
2487 pDesc->status.fDD = true;
2488
2489 /*
2490 * We need to leave Rx critical section here or we risk deadlocking
2491 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2492 * page or has an access handler associated with it.
2493 * Note that it is safe to leave the critical section here since
2494 * e1kRegWriteRDT() never modifies RDH. It never touches already
2495 * fetched RxD cache entries either.
2496 */
2497 if (cb > pThis->u16RxBSize)
2498 {
2499 pDesc->status.fEOP = false;
2500 e1kCsRxLeave(pThis);
2501 e1kStoreRxFragment(pThis, pDesc, ptr, pThis->u16RxBSize);
2502 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2503 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2504 return rc;
2505 ptr += pThis->u16RxBSize;
2506 cb -= pThis->u16RxBSize;
2507 }
2508 else
2509 {
2510 pDesc->status.fEOP = true;
2511 e1kCsRxLeave(pThis);
2512 e1kStoreRxFragment(pThis, pDesc, ptr, cb);
2513# ifdef E1K_WITH_RXD_CACHE
2514 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2515 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2516 return rc;
2517 cb = 0;
2518# else /* !E1K_WITH_RXD_CACHE */
2519 pThis->led.Actual.s.fReading = 0;
2520 return VINF_SUCCESS;
2521# endif /* !E1K_WITH_RXD_CACHE */
2522 }
2523 /*
2524 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2525 * is not defined.
2526 */
2527 }
2528# ifdef E1K_WITH_RXD_CACHE
2529 /* Write back the descriptor. */
2530 pDesc->status.fDD = true;
2531 e1kRxDPut(pThis, pDesc);
2532# else /* !E1K_WITH_RXD_CACHE */
2533 else
2534 {
2535 /* Write back the descriptor. */
2536 pDesc->status.fDD = true;
2537 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
2538 e1kDescAddr(RDBAH, RDBAL, RDH),
2539 pDesc, sizeof(E1KRXDESC));
2540 e1kAdvanceRDH(pThis);
2541 }
2542# endif /* !E1K_WITH_RXD_CACHE */
2543 }
2544
2545 if (cb > 0)
2546 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2547
2548 pThis->led.Actual.s.fReading = 0;
2549
2550 e1kCsRxLeave(pThis);
2551# ifdef E1K_WITH_RXD_CACHE
2552 /* Complete packet has been stored -- it is time to let the guest know. */
2553# ifdef E1K_USE_RX_TIMERS
2554 if (RDTR)
2555 {
2556 /* Arm the timer to fire in RDTR usec (discard .024) */
2557 e1kArmTimer(pThis, pThis->CTX_SUFF(pRIDTimer), RDTR);
2558 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2559 if (RADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pRADTimer)))
2560 e1kArmTimer(pThis, pThis->CTX_SUFF(pRADTimer), RADV);
2561 }
2562 else
2563 {
2564# endif /* E1K_USE_RX_TIMERS */
2565 /* 0 delay means immediate interrupt */
2566 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2567 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0);
2568# ifdef E1K_USE_RX_TIMERS
2569 }
2570# endif /* E1K_USE_RX_TIMERS */
2571# endif /* E1K_WITH_RXD_CACHE */
2572
2573 return VINF_SUCCESS;
2574#else /* !IN_RING3 */
2575 RT_NOREF_PV(pThis); RT_NOREF_PV(pvBuf); RT_NOREF_PV(cb); RT_NOREF_PV(status);
2576 return VERR_INTERNAL_ERROR_2;
2577#endif /* !IN_RING3 */
2578}
2579
2580
2581#ifdef IN_RING3
2582/**
2583 * Bring the link up after the configured delay, 5 seconds by default.
2584 *
2585 * @param pThis The device state structure.
2586 * @thread any
2587 */
2588DECLINLINE(void) e1kBringLinkUpDelayed(PE1KSTATE pThis)
2589{
2590 E1kLog(("%s Will bring up the link in %d seconds...\n",
2591 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2592 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), pThis->cMsLinkUpDelay * 1000);
2593}
2594
2595/**
2596 * Bring up the link immediately.
2597 *
2598 * @param pThis The device state structure.
2599 */
2600DECLINLINE(void) e1kR3LinkUp(PE1KSTATE pThis)
2601{
2602 E1kLog(("%s Link is up\n", pThis->szPrf));
2603 STATUS |= STATUS_LU;
2604 Phy::setLinkStatus(&pThis->phy, true);
2605 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2606 if (pThis->pDrvR3)
2607 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_UP);
2608 /* Process pending TX descriptors (see @bugref{8942}) */
2609 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
2610 if (RT_UNLIKELY(pItem))
2611 PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
2612}
2613
2614/**
2615 * Bring down the link immediately.
2616 *
2617 * @param pThis The device state structure.
2618 */
2619DECLINLINE(void) e1kR3LinkDown(PE1KSTATE pThis)
2620{
2621 E1kLog(("%s Link is down\n", pThis->szPrf));
2622 STATUS &= ~STATUS_LU;
2623#ifdef E1K_LSC_ON_RESET
2624 Phy::setLinkStatus(&pThis->phy, false);
2625#endif /* E1K_LSC_ON_RESET */
2626 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2627 if (pThis->pDrvR3)
2628 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2629}
2630
2631/**
2632 * Bring down the link temporarily.
2633 *
2634 * @param pThis The device state structure.
2635 */
2636DECLINLINE(void) e1kR3LinkDownTemp(PE1KSTATE pThis)
2637{
2638 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2639 STATUS &= ~STATUS_LU;
2640 Phy::setLinkStatus(&pThis->phy, false);
2641 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_LSC);
2642 /*
2643 * Notifying the associated driver that the link went down (even temporarily)
2644 * seems to be the right thing, but it was not done before. This may cause
2645 * a regression if the driver does not expect the link to go down as a result
2646 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2647 * of code notified the driver that the link was up! See @bugref{7057}.
2648 */
2649 if (pThis->pDrvR3)
2650 pThis->pDrvR3->pfnNotifyLinkChanged(pThis->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2651 e1kBringLinkUpDelayed(pThis);
2652}
2653#endif /* IN_RING3 */
2654
2655#if 0 /* unused */
2656/**
2657 * Read handler for Device Status register.
2658 *
2659 * Get the link status from PHY.
2660 *
2661 * @returns VBox status code.
2662 *
2663 * @param pThis The device state structure.
2664 * @param offset Register offset in memory-mapped frame.
2665 * @param index Register index in register array.
2666 * @param mask Used to implement partial reads (8 and 16-bit).
2667 */
2668static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2669{
2670 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2671 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2672 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2673 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2674 {
2675 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2676 if (Phy::readMDIO(&pThis->phy))
2677 *pu32Value = CTRL | CTRL_MDIO;
2678 else
2679 *pu32Value = CTRL & ~CTRL_MDIO;
2680 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2681 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2682 }
2683 else
2684 {
2685 /* MDIO pin is used for output, ignore it */
2686 *pu32Value = CTRL;
2687 }
2688 return VINF_SUCCESS;
2689}
2690#endif /* unused */
2691
2692/**
2693 * A callback used by PHY to indicate that the link needs to be updated due to
2694 * reset of PHY.
2695 *
2696 * @param pPhy A pointer to phy member of the device state structure.
2697 * @thread any
2698 */
2699void e1kPhyLinkResetCallback(PPHY pPhy)
2700{
2701 /* PHY is aggregated into e1000, get pThis from pPhy. */
2702 PE1KSTATE pThis = RT_FROM_MEMBER(pPhy, E1KSTATE, phy);
2703 /* Make sure we have cable connected and MAC can talk to PHY */
2704 if (pThis->fCableConnected && (CTRL & CTRL_SLU))
2705 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), E1K_INIT_LINKUP_DELAY_US);
2706}
2707
2708/**
2709 * Write handler for Device Control register.
2710 *
2711 * Handles reset.
2712 *
2713 * @param pThis The device state structure.
2714 * @param offset Register offset in memory-mapped frame.
2715 * @param index Register index in register array.
2716 * @param value The value to store.
2717 * @param mask Used to implement partial writes (8 and 16-bit).
2718 * @thread EMT
2719 */
2720static int e1kRegWriteCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2721{
2722 int rc = VINF_SUCCESS;
2723
2724 if (value & CTRL_RESET)
2725 { /* RST */
2726#ifndef IN_RING3
2727 return VINF_IOM_R3_MMIO_WRITE;
2728#else
2729 e1kHardReset(pThis);
2730#endif
2731 }
2732 else
2733 {
2734#ifdef E1K_LSC_ON_SLU
2735 /*
2736 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2737 * the link is down and the cable is connected, and if they are we
2738 * bring the link up, see @bugref{8624}.
2739 */
2740 if ( (value & CTRL_SLU)
2741 && !(CTRL & CTRL_SLU)
2742 && pThis->fCableConnected
2743 && !(STATUS & STATUS_LU))
2744 {
2745 /* It should take about 2 seconds for the link to come up */
2746 e1kArmTimer(pThis, pThis->CTX_SUFF(pLUTimer), E1K_INIT_LINKUP_DELAY_US);
2747 }
2748#else /* !E1K_LSC_ON_SLU */
2749 if ( (value & CTRL_SLU)
2750 && !(CTRL & CTRL_SLU)
2751 && pThis->fCableConnected
2752 && !TMTimerIsActive(pThis->CTX_SUFF(pLUTimer)))
2753 {
2754 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2755 STATUS |= STATUS_LU;
2756 }
2757#endif /* !E1K_LSC_ON_SLU */
2758 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2759 {
2760 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2761 }
2762 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2763 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2764 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2765 if (value & CTRL_MDC)
2766 {
2767 if (value & CTRL_MDIO_DIR)
2768 {
2769 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2770 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2771 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO));
2772 }
2773 else
2774 {
2775 if (Phy::readMDIO(&pThis->phy))
2776 value |= CTRL_MDIO;
2777 else
2778 value &= ~CTRL_MDIO;
2779 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2780 }
2781 }
2782 rc = e1kRegWriteDefault(pThis, offset, index, value);
2783 }
2784
2785 return rc;
2786}
2787
2788/**
2789 * Write handler for EEPROM/Flash Control/Data register.
2790 *
2791 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2792 *
2793 * @param pThis The device state structure.
2794 * @param offset Register offset in memory-mapped frame.
2795 * @param index Register index in register array.
2796 * @param value The value to store.
2797 * @param mask Used to implement partial writes (8 and 16-bit).
2798 * @thread EMT
2799 */
2800static int e1kRegWriteEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2801{
2802 RT_NOREF(offset, index);
2803#ifdef IN_RING3
2804 /* So far we are concerned with lower byte only */
2805 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2806 {
2807 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2808 /* Note: 82543GC does not need to request EEPROM access */
2809 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2810 pThis->eeprom.write(value & EECD_EE_WIRES);
2811 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2812 }
2813 if (value & EECD_EE_REQ)
2814 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2815 else
2816 EECD &= ~EECD_EE_GNT;
2817 //e1kRegWriteDefault(pThis, offset, index, value );
2818
2819 return VINF_SUCCESS;
2820#else /* !IN_RING3 */
2821 RT_NOREF(pThis, value);
2822 return VINF_IOM_R3_MMIO_WRITE;
2823#endif /* !IN_RING3 */
2824}
2825
2826/**
2827 * Read handler for EEPROM/Flash Control/Data register.
2828 *
2829 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2830 *
2831 * @returns VBox status code.
2832 *
2833 * @param pThis The device state structure.
2834 * @param offset Register offset in memory-mapped frame.
2835 * @param index Register index in register array.
2836 * @param mask Used to implement partial reads (8 and 16-bit).
2837 * @thread EMT
2838 */
2839static int e1kRegReadEECD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2840{
2841#ifdef IN_RING3
2842 uint32_t value;
2843 int rc = e1kRegReadDefault(pThis, offset, index, &value);
2844 if (RT_SUCCESS(rc))
2845 {
2846 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2847 {
2848 /* Note: 82543GC does not need to request EEPROM access */
2849 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2850 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2851 value |= pThis->eeprom.read();
2852 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2853 }
2854 *pu32Value = value;
2855 }
2856
2857 return rc;
2858#else /* !IN_RING3 */
2859 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
2860 return VINF_IOM_R3_MMIO_READ;
2861#endif /* !IN_RING3 */
2862}
2863
2864/**
2865 * Write handler for EEPROM Read register.
2866 *
2867 * Handles EEPROM word access requests, reads EEPROM and stores the result
2868 * into DATA field.
2869 *
2870 * @param pThis The device state structure.
2871 * @param offset Register offset in memory-mapped frame.
2872 * @param index Register index in register array.
2873 * @param value The value to store.
2874 * @param mask Used to implement partial writes (8 and 16-bit).
2875 * @thread EMT
2876 */
2877static int e1kRegWriteEERD(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2878{
2879#ifdef IN_RING3
2880 /* Make use of 'writable' and 'readable' masks. */
2881 e1kRegWriteDefault(pThis, offset, index, value);
2882 /* DONE and DATA are set only if read was triggered by START. */
2883 if (value & EERD_START)
2884 {
2885 uint16_t tmp;
2886 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2887 if (pThis->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2888 SET_BITS(EERD, DATA, tmp);
2889 EERD |= EERD_DONE;
2890 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2891 }
2892
2893 return VINF_SUCCESS;
2894#else /* !IN_RING3 */
2895 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
2896 return VINF_IOM_R3_MMIO_WRITE;
2897#endif /* !IN_RING3 */
2898}
2899
2900
2901/**
2902 * Write handler for MDI Control register.
2903 *
2904 * Handles PHY read/write requests; forwards requests to internal PHY device.
2905 *
2906 * @param pThis The device state structure.
2907 * @param offset Register offset in memory-mapped frame.
2908 * @param index Register index in register array.
2909 * @param value The value to store.
2910 * @param mask Used to implement partial writes (8 and 16-bit).
2911 * @thread EMT
2912 */
2913static int e1kRegWriteMDIC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2914{
2915 if (value & MDIC_INT_EN)
2916 {
2917 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2918 pThis->szPrf));
2919 }
2920 else if (value & MDIC_READY)
2921 {
2922 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
2923 pThis->szPrf));
2924 }
2925 else if (GET_BITS_V(value, MDIC, PHY) != 1)
2926 {
2927 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
2928 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
2929 /*
2930 * Some drivers scan the MDIO bus for a PHY. We can work with these
2931 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
2932 * at the requested address, see @bugref{7346}.
2933 */
2934 MDIC = MDIC_READY | MDIC_ERROR;
2935 }
2936 else
2937 {
2938 /* Store the value */
2939 e1kRegWriteDefault(pThis, offset, index, value);
2940 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
2941 /* Forward op to PHY */
2942 if (value & MDIC_OP_READ)
2943 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG)));
2944 else
2945 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK);
2946 /* Let software know that we are done */
2947 MDIC |= MDIC_READY;
2948 }
2949
2950 return VINF_SUCCESS;
2951}
2952
2953/**
2954 * Write handler for Interrupt Cause Read register.
2955 *
2956 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
2957 *
2958 * @param pThis The device state structure.
2959 * @param offset Register offset in memory-mapped frame.
2960 * @param index Register index in register array.
2961 * @param value The value to store.
2962 * @param mask Used to implement partial writes (8 and 16-bit).
2963 * @thread EMT
2964 */
2965static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2966{
2967 ICR &= ~value;
2968
2969 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
2970 return VINF_SUCCESS;
2971}
2972
2973/**
2974 * Read handler for Interrupt Cause Read register.
2975 *
2976 * Reading this register acknowledges all interrupts.
2977 *
2978 * @returns VBox status code.
2979 *
2980 * @param pThis The device state structure.
2981 * @param offset Register offset in memory-mapped frame.
2982 * @param index Register index in register array.
2983 * @param mask Not used.
2984 * @thread EMT
2985 */
2986static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2987{
2988 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
2989 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2990 return rc;
2991
2992 uint32_t value = 0;
2993 rc = e1kRegReadDefault(pThis, offset, index, &value);
2994 if (RT_SUCCESS(rc))
2995 {
2996 if (value)
2997 {
2998 if (!pThis->fIntRaised)
2999 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3000 /*
3001 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3002 * with disabled interrupts.
3003 */
3004 //if (IMS)
3005 if (1)
3006 {
3007 /*
3008 * Interrupts were enabled -- we are supposedly at the very
3009 * beginning of interrupt handler
3010 */
3011 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3012 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3013 /* Clear all pending interrupts */
3014 ICR = 0;
3015 pThis->fIntRaised = false;
3016 /* Lower(0) INTA(0) */
3017 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
3018
3019 pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
3020 if (pThis->fIntMaskUsed)
3021 pThis->fDelayInts = true;
3022 }
3023 else
3024 {
3025 /*
3026 * Interrupts are disabled -- in windows guests ICR read is done
3027 * just before re-enabling interrupts
3028 */
3029 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3030 }
3031 }
3032 *pu32Value = value;
3033 }
3034 e1kCsLeave(pThis);
3035
3036 return rc;
3037}
3038
3039/**
3040 * Write handler for Interrupt Cause Set register.
3041 *
3042 * Bits corresponding to 1s in 'value' will be set in ICR register.
3043 *
3044 * @param pThis The device state structure.
3045 * @param offset Register offset in memory-mapped frame.
3046 * @param index Register index in register array.
3047 * @param value The value to store.
3048 * @param mask Used to implement partial writes (8 and 16-bit).
3049 * @thread EMT
3050 */
3051static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3052{
3053 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3054 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3055 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3056}
3057
3058/**
3059 * Write handler for Interrupt Mask Set register.
3060 *
3061 * Will trigger pending interrupts.
3062 *
3063 * @param pThis The device state structure.
3064 * @param offset Register offset in memory-mapped frame.
3065 * @param index Register index in register array.
3066 * @param value The value to store.
3067 * @param mask Used to implement partial writes (8 and 16-bit).
3068 * @thread EMT
3069 */
3070static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3071{
3072 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3073
3074 IMS |= value;
3075 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3076 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3077 /*
3078 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3079 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3080 */
3081 if ((ICR & IMS) && !pThis->fLocked)
3082 {
3083 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3084 e1kPostponeInterrupt(pThis, E1K_IMS_INT_DELAY_NS);
3085 }
3086
3087 return VINF_SUCCESS;
3088}
3089
3090/**
3091 * Write handler for Interrupt Mask Clear register.
3092 *
3093 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3094 *
3095 * @param pThis The device state structure.
3096 * @param offset Register offset in memory-mapped frame.
3097 * @param index Register index in register array.
3098 * @param value The value to store.
3099 * @param mask Used to implement partial writes (8 and 16-bit).
3100 * @thread EMT
3101 */
3102static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3103{
3104 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3105
3106 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3107 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3108 return rc;
3109 if (pThis->fIntRaised)
3110 {
3111 /*
3112 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3113 * Windows to freeze since it may receive an interrupt while still in the very beginning
3114 * of interrupt handler.
3115 */
3116 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3117 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3118 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3119 /* Lower(0) INTA(0) */
3120 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
3121 pThis->fIntRaised = false;
3122 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3123 }
3124 IMS &= ~value;
3125 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3126 e1kCsLeave(pThis);
3127
3128 return VINF_SUCCESS;
3129}
3130
3131/**
3132 * Write handler for Receive Control register.
3133 *
3134 * @param pThis The device state structure.
3135 * @param offset Register offset in memory-mapped frame.
3136 * @param index Register index in register array.
3137 * @param value The value to store.
3138 * @param mask Used to implement partial writes (8 and 16-bit).
3139 * @thread EMT
3140 */
3141static int e1kRegWriteRCTL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3142{
3143 /* Update promiscuous mode */
3144 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3145 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3146 {
3147 /* Promiscuity has changed, pass the knowledge on. */
3148#ifndef IN_RING3
3149 return VINF_IOM_R3_MMIO_WRITE;
3150#else
3151 if (pThis->pDrvR3)
3152 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3, fBecomePromiscous);
3153#endif
3154 }
3155
3156 /* Adjust receive buffer size */
3157 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3158 if (value & RCTL_BSEX)
3159 cbRxBuf *= 16;
3160 if (cbRxBuf != pThis->u16RxBSize)
3161 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3162 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3163 pThis->u16RxBSize = cbRxBuf;
3164
3165 /* Update the register */
3166 e1kRegWriteDefault(pThis, offset, index, value);
3167
3168 return VINF_SUCCESS;
3169}
3170
3171/**
3172 * Write handler for Packet Buffer Allocation register.
3173 *
3174 * TXA = 64 - RXA.
3175 *
3176 * @param pThis The device state structure.
3177 * @param offset Register offset in memory-mapped frame.
3178 * @param index Register index in register array.
3179 * @param value The value to store.
3180 * @param mask Used to implement partial writes (8 and 16-bit).
3181 * @thread EMT
3182 */
3183static int e1kRegWritePBA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3184{
3185 e1kRegWriteDefault(pThis, offset, index, value);
3186 PBA_st->txa = 64 - PBA_st->rxa;
3187
3188 return VINF_SUCCESS;
3189}
3190
3191/**
3192 * Write handler for Receive Descriptor Tail register.
3193 *
3194 * @remarks Write into RDT forces switch to HC and signal to
3195 * e1kR3NetworkDown_WaitReceiveAvail().
3196 *
3197 * @returns VBox status code.
3198 *
3199 * @param pThis The device state structure.
3200 * @param offset Register offset in memory-mapped frame.
3201 * @param index Register index in register array.
3202 * @param value The value to store.
3203 * @param mask Used to implement partial writes (8 and 16-bit).
3204 * @thread EMT
3205 */
3206static int e1kRegWriteRDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3207{
3208#ifndef IN_RING3
3209 /* XXX */
3210// return VINF_IOM_R3_MMIO_WRITE;
3211#endif
3212 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3213 if (RT_LIKELY(rc == VINF_SUCCESS))
3214 {
3215 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3216#ifndef E1K_WITH_RXD_CACHE
3217 /*
3218 * Some drivers advance RDT too far, so that it equals RDH. This
3219 * somehow manages to work with real hardware but not with this
3220 * emulated device. We can work with these drivers if we just
3221 * write 1 less when we see a driver writing RDT equal to RDH,
3222 * see @bugref{7346}.
3223 */
3224 if (value == RDH)
3225 {
3226 if (RDH == 0)
3227 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3228 else
3229 value = RDH - 1;
3230 }
3231#endif /* !E1K_WITH_RXD_CACHE */
3232 rc = e1kRegWriteDefault(pThis, offset, index, value);
3233#ifdef E1K_WITH_RXD_CACHE
3234 /*
3235 * We need to fetch descriptors now as RDT may go whole circle
3236 * before we attempt to store a received packet. For example,
3237 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3238 * size being only 8 descriptors! Note that we fetch descriptors
3239 * only when the cache is empty to reduce the number of memory reads
3240 * in case of frequent RDT writes. Don't fetch anything when the
3241 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3242 * messed up state.
3243 * Note that despite the cache may seem empty, meaning that there are
3244 * no more available descriptors in it, it may still be used by RX
3245 * thread which has not yet written the last descriptor back but has
3246 * temporarily released the RX lock in order to write the packet body
3247 * to descriptor's buffer. At this point we still going to do prefetch
3248 * but it won't actually fetch anything if there are no unused slots in
3249 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3250 * reset the cache here even if it appears empty. It will be reset at
3251 * a later point in e1kRxDGet().
3252 */
3253 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3254 e1kRxDPrefetch(pThis);
3255#endif /* E1K_WITH_RXD_CACHE */
3256 e1kCsRxLeave(pThis);
3257 if (RT_SUCCESS(rc))
3258 {
3259/** @todo bird: Use SUPSem* for this so we can signal it in ring-0 as well
3260 * without requiring any context switches. We should also check the
3261 * wait condition before bothering to queue the item as we're currently
3262 * queuing thousands of items per second here in a normal transmit
3263 * scenario. Expect performance changes when fixing this! */
3264#ifdef IN_RING3
3265 /* Signal that we have more receive descriptors available. */
3266 e1kWakeupReceive(pThis->CTX_SUFF(pDevIns));
3267#else
3268 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));
3269 if (pItem)
3270 PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);
3271#endif
3272 }
3273 }
3274 return rc;
3275}
3276
3277/**
3278 * Write handler for Receive Delay Timer register.
3279 *
3280 * @param pThis The device state structure.
3281 * @param offset Register offset in memory-mapped frame.
3282 * @param index Register index in register array.
3283 * @param value The value to store.
3284 * @param mask Used to implement partial writes (8 and 16-bit).
3285 * @thread EMT
3286 */
3287static int e1kRegWriteRDTR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3288{
3289 e1kRegWriteDefault(pThis, offset, index, value);
3290 if (value & RDTR_FPD)
3291 {
3292 /* Flush requested, cancel both timers and raise interrupt */
3293#ifdef E1K_USE_RX_TIMERS
3294 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3295 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3296#endif
3297 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3298 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3299 }
3300
3301 return VINF_SUCCESS;
3302}
3303
3304DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3305{
3306 /**
3307 * Make sure TDT won't change during computation. EMT may modify TDT at
3308 * any moment.
3309 */
3310 uint32_t tdt = TDT;
3311 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3312}
3313
3314#ifdef IN_RING3
3315
3316# ifdef E1K_TX_DELAY
3317/**
3318 * Transmit Delay Timer handler.
3319 *
3320 * @remarks We only get here when the timer expires.
3321 *
3322 * @param pDevIns Pointer to device instance structure.
3323 * @param pTimer Pointer to the timer.
3324 * @param pvUser NULL.
3325 * @thread EMT
3326 */
3327static DECLCALLBACK(void) e1kTxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3328{
3329 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3330 Assert(PDMCritSectIsOwner(&pThis->csTx));
3331
3332 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3333# ifdef E1K_INT_STATS
3334 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3335 if (u64Elapsed > pThis->uStatMaxTxDelay)
3336 pThis->uStatMaxTxDelay = u64Elapsed;
3337# endif
3338 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
3339 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3340}
3341# endif /* E1K_TX_DELAY */
3342
3343//# ifdef E1K_USE_TX_TIMERS
3344
3345/**
3346 * Transmit Interrupt Delay Timer handler.
3347 *
3348 * @remarks We only get here when the timer expires.
3349 *
3350 * @param pDevIns Pointer to device instance structure.
3351 * @param pTimer Pointer to the timer.
3352 * @param pvUser NULL.
3353 * @thread EMT
3354 */
3355static DECLCALLBACK(void) e1kTxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3356{
3357 RT_NOREF(pDevIns);
3358 RT_NOREF(pTimer);
3359 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3360
3361 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3362 /* Cancel absolute delay timer as we have already got attention */
3363# ifndef E1K_NO_TAD
3364 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
3365# endif
3366 e1kRaiseInterrupt(pThis, ICR_TXDW);
3367}
3368
3369/**
3370 * Transmit Absolute Delay Timer handler.
3371 *
3372 * @remarks We only get here when the timer expires.
3373 *
3374 * @param pDevIns Pointer to device instance structure.
3375 * @param pTimer Pointer to the timer.
3376 * @param pvUser NULL.
3377 * @thread EMT
3378 */
3379static DECLCALLBACK(void) e1kTxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3380{
3381 RT_NOREF(pDevIns);
3382 RT_NOREF(pTimer);
3383 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3384
3385 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3386 /* Cancel interrupt delay timer as we have already got attention */
3387 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
3388 e1kRaiseInterrupt(pThis, ICR_TXDW);
3389}
3390
3391//# endif /* E1K_USE_TX_TIMERS */
3392# ifdef E1K_USE_RX_TIMERS
3393
3394/**
3395 * Receive Interrupt Delay Timer handler.
3396 *
3397 * @remarks We only get here when the timer expires.
3398 *
3399 * @param pDevIns Pointer to device instance structure.
3400 * @param pTimer Pointer to the timer.
3401 * @param pvUser NULL.
3402 * @thread EMT
3403 */
3404static DECLCALLBACK(void) e1kRxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3405{
3406 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3407
3408 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3409 /* Cancel absolute delay timer as we have already got attention */
3410 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
3411 e1kRaiseInterrupt(pThis, ICR_RXT0);
3412}
3413
3414/**
3415 * Receive Absolute Delay Timer handler.
3416 *
3417 * @remarks We only get here when the timer expires.
3418 *
3419 * @param pDevIns Pointer to device instance structure.
3420 * @param pTimer Pointer to the timer.
3421 * @param pvUser NULL.
3422 * @thread EMT
3423 */
3424static DECLCALLBACK(void) e1kRxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3425{
3426 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3427
3428 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3429 /* Cancel interrupt delay timer as we have already got attention */
3430 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
3431 e1kRaiseInterrupt(pThis, ICR_RXT0);
3432}
3433
3434# endif /* E1K_USE_RX_TIMERS */
3435
3436/**
3437 * Late Interrupt Timer handler.
3438 *
3439 * @param pDevIns Pointer to device instance structure.
3440 * @param pTimer Pointer to the timer.
3441 * @param pvUser NULL.
3442 * @thread EMT
3443 */
3444static DECLCALLBACK(void) e1kLateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3445{
3446 RT_NOREF(pDevIns, pTimer);
3447 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3448
3449 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3450 STAM_COUNTER_INC(&pThis->StatLateInts);
3451 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3452# if 0
3453 if (pThis->iStatIntLost > -100)
3454 pThis->iStatIntLost--;
3455# endif
3456 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, 0);
3457 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3458}
3459
3460/**
3461 * Link Up Timer handler.
3462 *
3463 * @param pDevIns Pointer to device instance structure.
3464 * @param pTimer Pointer to the timer.
3465 * @param pvUser NULL.
3466 * @thread EMT
3467 */
3468static DECLCALLBACK(void) e1kLinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3469{
3470 RT_NOREF(pDevIns, pTimer);
3471 PE1KSTATE pThis = (PE1KSTATE )pvUser;
3472
3473 /*
3474 * This can happen if we set the link status to down when the Link up timer was
3475 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3476 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3477 * on reset even if the cable is unplugged (see @bugref{8942}).
3478 */
3479 if (pThis->fCableConnected)
3480 {
3481 /* 82543GC does not have an internal PHY */
3482 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3483 e1kR3LinkUp(pThis);
3484 }
3485#ifdef E1K_LSC_ON_RESET
3486 else if (pThis->eChip == E1K_CHIP_82543GC)
3487 e1kR3LinkDown(pThis);
3488#endif /* E1K_LSC_ON_RESET */
3489}
3490
3491#endif /* IN_RING3 */
3492
3493/**
3494 * Sets up the GSO context according to the TSE new context descriptor.
3495 *
3496 * @param pGso The GSO context to setup.
3497 * @param pCtx The context descriptor.
3498 */
3499DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3500{
3501 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3502
3503 /*
3504 * See if the context descriptor describes something that could be TCP or
3505 * UDP over IPv[46].
3506 */
3507 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3508 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3509 {
3510 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3511 return;
3512 }
3513 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3514 {
3515 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3516 return;
3517 }
3518 if (RT_UNLIKELY( pCtx->dw2.fTCP
3519 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3520 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3521 {
3522 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3523 return;
3524 }
3525
3526 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3527 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3528 {
3529 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3530 return;
3531 }
3532
3533 /* IPv4 checksum offset. */
3534 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3535 {
3536 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3537 return;
3538 }
3539
3540 /* TCP/UDP checksum offsets. */
3541 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3542 != ( pCtx->dw2.fTCP
3543 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3544 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3545 {
3546 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3547 return;
3548 }
3549
3550 /*
3551 * Because of internal networking using a 16-bit size field for GSO context
3552 * plus frame, we have to make sure we don't exceed this.
3553 */
3554 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3555 {
3556 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3557 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3558 return;
3559 }
3560
3561 /*
3562 * We're good for now - we'll do more checks when seeing the data.
3563 * So, figure the type of offloading and setup the context.
3564 */
3565 if (pCtx->dw2.fIP)
3566 {
3567 if (pCtx->dw2.fTCP)
3568 {
3569 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3570 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3571 }
3572 else
3573 {
3574 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3575 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3576 }
3577 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3578 * this yet it seems)... */
3579 }
3580 else
3581 {
3582 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3583 if (pCtx->dw2.fTCP)
3584 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3585 else
3586 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3587 }
3588 pGso->offHdr1 = pCtx->ip.u8CSS;
3589 pGso->offHdr2 = pCtx->tu.u8CSS;
3590 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3591 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3592 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3593 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3594 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3595}
3596
3597/**
3598 * Checks if we can use GSO processing for the current TSE frame.
3599 *
3600 * @param pThis The device state structure.
3601 * @param pGso The GSO context.
3602 * @param pData The first data descriptor of the frame.
3603 * @param pCtx The TSO context descriptor.
3604 */
3605DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3606{
3607 if (!pData->cmd.fTSE)
3608 {
3609 E1kLog2(("e1kCanDoGso: !TSE\n"));
3610 return false;
3611 }
3612 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3613 {
3614 E1kLog(("e1kCanDoGso: VLE\n"));
3615 return false;
3616 }
3617 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3618 {
3619 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3620 return false;
3621 }
3622
3623 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3624 {
3625 case PDMNETWORKGSOTYPE_IPV4_TCP:
3626 case PDMNETWORKGSOTYPE_IPV4_UDP:
3627 if (!pData->dw3.fIXSM)
3628 {
3629 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3630 return false;
3631 }
3632 if (!pData->dw3.fTXSM)
3633 {
3634 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3635 return false;
3636 }
3637 /** @todo what more check should we perform here? Ethernet frame type? */
3638 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3639 return true;
3640
3641 case PDMNETWORKGSOTYPE_IPV6_TCP:
3642 case PDMNETWORKGSOTYPE_IPV6_UDP:
3643 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3644 {
3645 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3646 return false;
3647 }
3648 if (!pData->dw3.fTXSM)
3649 {
3650 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3651 return false;
3652 }
3653 /** @todo what more check should we perform here? Ethernet frame type? */
3654 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3655 return true;
3656
3657 default:
3658 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3659 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3660 return false;
3661 }
3662}
3663
3664/**
3665 * Frees the current xmit buffer.
3666 *
3667 * @param pThis The device state structure.
3668 */
3669static void e1kXmitFreeBuf(PE1KSTATE pThis)
3670{
3671 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3672 if (pSg)
3673 {
3674 pThis->CTX_SUFF(pTxSg) = NULL;
3675
3676 if (pSg->pvAllocator != pThis)
3677 {
3678 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3679 if (pDrv)
3680 pDrv->pfnFreeBuf(pDrv, pSg);
3681 }
3682 else
3683 {
3684 /* loopback */
3685 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3686 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3687 pSg->fFlags = 0;
3688 pSg->pvAllocator = NULL;
3689 }
3690 }
3691}
3692
3693#ifndef E1K_WITH_TXD_CACHE
3694/**
3695 * Allocates an xmit buffer.
3696 *
3697 * @returns See PDMINETWORKUP::pfnAllocBuf.
3698 * @param pThis The device state structure.
3699 * @param cbMin The minimum frame size.
3700 * @param fExactSize Whether cbMin is exact or if we have to max it
3701 * out to the max MTU size.
3702 * @param fGso Whether this is a GSO frame or not.
3703 */
3704DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, size_t cbMin, bool fExactSize, bool fGso)
3705{
3706 /* Adjust cbMin if necessary. */
3707 if (!fExactSize)
3708 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3709
3710 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3711 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3712 e1kXmitFreeBuf(pThis);
3713 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3714
3715 /*
3716 * Allocate the buffer.
3717 */
3718 PPDMSCATTERGATHER pSg;
3719 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3720 {
3721 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3722 if (RT_UNLIKELY(!pDrv))
3723 return VERR_NET_DOWN;
3724 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3725 if (RT_FAILURE(rc))
3726 {
3727 /* Suspend TX as we are out of buffers atm */
3728 STATUS |= STATUS_TXOFF;
3729 return rc;
3730 }
3731 }
3732 else
3733 {
3734 /* Create a loopback using the fallback buffer and preallocated SG. */
3735 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3736 pSg = &pThis->uTxFallback.Sg;
3737 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3738 pSg->cbUsed = 0;
3739 pSg->cbAvailable = 0;
3740 pSg->pvAllocator = pThis;
3741 pSg->pvUser = NULL; /* No GSO here. */
3742 pSg->cSegs = 1;
3743 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3744 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3745 }
3746
3747 pThis->CTX_SUFF(pTxSg) = pSg;
3748 return VINF_SUCCESS;
3749}
3750#else /* E1K_WITH_TXD_CACHE */
3751/**
3752 * Allocates an xmit buffer.
3753 *
3754 * @returns See PDMINETWORKUP::pfnAllocBuf.
3755 * @param pThis The device state structure.
3756 * @param cbMin The minimum frame size.
3757 * @param fExactSize Whether cbMin is exact or if we have to max it
3758 * out to the max MTU size.
3759 * @param fGso Whether this is a GSO frame or not.
3760 */
3761DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, bool fGso)
3762{
3763 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3764 if (RT_UNLIKELY(pThis->CTX_SUFF(pTxSg)))
3765 e1kXmitFreeBuf(pThis);
3766 Assert(pThis->CTX_SUFF(pTxSg) == NULL);
3767
3768 /*
3769 * Allocate the buffer.
3770 */
3771 PPDMSCATTERGATHER pSg;
3772 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3773 {
3774 if (pThis->cbTxAlloc == 0)
3775 {
3776 /* Zero packet, no need for the buffer */
3777 return VINF_SUCCESS;
3778 }
3779
3780 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
3781 if (RT_UNLIKELY(!pDrv))
3782 return VERR_NET_DOWN;
3783 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3784 if (RT_FAILURE(rc))
3785 {
3786 /* Suspend TX as we are out of buffers atm */
3787 STATUS |= STATUS_TXOFF;
3788 return rc;
3789 }
3790 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3791 pThis->szPrf, pThis->cbTxAlloc,
3792 pThis->fVTag ? "VLAN " : "",
3793 pThis->fGSO ? "GSO " : ""));
3794 }
3795 else
3796 {
3797 /* Create a loopback using the fallback buffer and preallocated SG. */
3798 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3799 pSg = &pThis->uTxFallback.Sg;
3800 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3801 pSg->cbUsed = 0;
3802 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
3803 pSg->pvAllocator = pThis;
3804 pSg->pvUser = NULL; /* No GSO here. */
3805 pSg->cSegs = 1;
3806 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3807 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3808 }
3809 pThis->cbTxAlloc = 0;
3810
3811 pThis->CTX_SUFF(pTxSg) = pSg;
3812 return VINF_SUCCESS;
3813}
3814#endif /* E1K_WITH_TXD_CACHE */
3815
3816/**
3817 * Checks if it's a GSO buffer or not.
3818 *
3819 * @returns true / false.
3820 * @param pTxSg The scatter / gather buffer.
3821 */
3822DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3823{
3824#if 0
3825 if (!pTxSg)
3826 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3827 if (pTxSg && pTxSg->pvUser)
3828 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3829#endif
3830 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3831}
3832
3833#ifndef E1K_WITH_TXD_CACHE
3834/**
3835 * Load transmit descriptor from guest memory.
3836 *
3837 * @param pThis The device state structure.
3838 * @param pDesc Pointer to descriptor union.
3839 * @param addr Physical address in guest context.
3840 * @thread E1000_TX
3841 */
3842DECLINLINE(void) e1kLoadDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3843{
3844 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3845}
3846#else /* E1K_WITH_TXD_CACHE */
3847/**
3848 * Load transmit descriptors from guest memory.
3849 *
3850 * We need two physical reads in case the tail wrapped around the end of TX
3851 * descriptor ring.
3852 *
3853 * @returns the actual number of descriptors fetched.
3854 * @param pThis The device state structure.
3855 * @param pDesc Pointer to descriptor union.
3856 * @param addr Physical address in guest context.
3857 * @thread E1000_TX
3858 */
3859DECLINLINE(unsigned) e1kTxDLoadMore(PE1KSTATE pThis)
3860{
3861 Assert(pThis->iTxDCurrent == 0);
3862 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3863 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3864 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3865 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3866 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3867 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3868 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u "
3869 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3870 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3871 nFirstNotLoaded, nDescsInSingleRead));
3872 if (nDescsToFetch == 0)
3873 return 0;
3874 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3875 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3876 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3877 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3878 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3879 pThis->szPrf, nDescsInSingleRead,
3880 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3881 nFirstNotLoaded, TDLEN, TDH, TDT));
3882 if (nDescsToFetch > nDescsInSingleRead)
3883 {
3884 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
3885 ((uint64_t)TDBAH << 32) + TDBAL,
3886 pFirstEmptyDesc + nDescsInSingleRead,
3887 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3888 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3889 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3890 TDBAH, TDBAL));
3891 }
3892 pThis->nTxDFetched += nDescsToFetch;
3893 return nDescsToFetch;
3894}
3895
3896/**
3897 * Load transmit descriptors from guest memory only if there are no loaded
3898 * descriptors.
3899 *
3900 * @returns true if there are descriptors in cache.
3901 * @param pThis The device state structure.
3902 * @param pDesc Pointer to descriptor union.
3903 * @param addr Physical address in guest context.
3904 * @thread E1000_TX
3905 */
3906DECLINLINE(bool) e1kTxDLazyLoad(PE1KSTATE pThis)
3907{
3908 if (pThis->nTxDFetched == 0)
3909 return e1kTxDLoadMore(pThis) != 0;
3910 return true;
3911}
3912#endif /* E1K_WITH_TXD_CACHE */
3913
3914/**
3915 * Write back transmit descriptor to guest memory.
3916 *
3917 * @param pThis The device state structure.
3918 * @param pDesc Pointer to descriptor union.
3919 * @param addr Physical address in guest context.
3920 * @thread E1000_TX
3921 */
3922DECLINLINE(void) e1kWriteBackDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3923{
3924 /* Only the last half of the descriptor has to be written back. */
3925 e1kPrintTDesc(pThis, pDesc, "^^^");
3926 PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), addr, pDesc, sizeof(E1KTXDESC));
3927}
3928
3929/**
3930 * Transmit complete frame.
3931 *
3932 * @remarks We skip the FCS since we're not responsible for sending anything to
3933 * a real ethernet wire.
3934 *
3935 * @param pThis The device state structure.
3936 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
3937 * @thread E1000_TX
3938 */
3939static void e1kTransmitFrame(PE1KSTATE pThis, bool fOnWorkerThread)
3940{
3941 PPDMSCATTERGATHER pSg = pThis->CTX_SUFF(pTxSg);
3942 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
3943 Assert(!pSg || pSg->cSegs == 1);
3944
3945 if (cbFrame > 70) /* unqualified guess */
3946 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
3947
3948#ifdef E1K_INT_STATS
3949 if (cbFrame <= 1514)
3950 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
3951 else if (cbFrame <= 2962)
3952 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
3953 else if (cbFrame <= 4410)
3954 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
3955 else if (cbFrame <= 5858)
3956 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
3957 else if (cbFrame <= 7306)
3958 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
3959 else if (cbFrame <= 8754)
3960 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
3961 else if (cbFrame <= 16384)
3962 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
3963 else if (cbFrame <= 32768)
3964 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
3965 else
3966 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
3967#endif /* E1K_INT_STATS */
3968
3969 /* Add VLAN tag */
3970 if (cbFrame > 12 && pThis->fVTag)
3971 {
3972 E1kLog3(("%s Inserting VLAN tag %08x\n",
3973 pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
3974 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
3975 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
3976 pSg->cbUsed += 4;
3977 cbFrame += 4;
3978 Assert(pSg->cbUsed == cbFrame);
3979 Assert(pSg->cbUsed <= pSg->cbAvailable);
3980 }
3981/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
3982 "%.*Rhxd\n"
3983 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
3984 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
3985
3986 /* Update the stats */
3987 E1K_INC_CNT32(TPT);
3988 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
3989 E1K_INC_CNT32(GPTC);
3990 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
3991 E1K_INC_CNT32(BPTC);
3992 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
3993 E1K_INC_CNT32(MPTC);
3994 /* Update octet transmit counter */
3995 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
3996 if (pThis->CTX_SUFF(pDrv))
3997 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
3998 if (cbFrame == 64)
3999 E1K_INC_CNT32(PTC64);
4000 else if (cbFrame < 128)
4001 E1K_INC_CNT32(PTC127);
4002 else if (cbFrame < 256)
4003 E1K_INC_CNT32(PTC255);
4004 else if (cbFrame < 512)
4005 E1K_INC_CNT32(PTC511);
4006 else if (cbFrame < 1024)
4007 E1K_INC_CNT32(PTC1023);
4008 else
4009 E1K_INC_CNT32(PTC1522);
4010
4011 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4012
4013 /*
4014 * Dump and send the packet.
4015 */
4016 int rc = VERR_NET_DOWN;
4017 if (pSg && pSg->pvAllocator != pThis)
4018 {
4019 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4020
4021 pThis->CTX_SUFF(pTxSg) = NULL;
4022 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
4023 if (pDrv)
4024 {
4025 /* Release critical section to avoid deadlock in CanReceive */
4026 //e1kCsLeave(pThis);
4027 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4028 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4029 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4030 //e1kCsEnter(pThis, RT_SRC_POS);
4031 }
4032 }
4033 else if (pSg)
4034 {
4035 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4036 e1kPacketDump(pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4037
4038 /** @todo do we actually need to check that we're in loopback mode here? */
4039 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4040 {
4041 E1KRXDST status;
4042 RT_ZERO(status);
4043 status.fPIF = true;
4044 e1kHandleRxPacket(pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4045 rc = VINF_SUCCESS;
4046 }
4047 e1kXmitFreeBuf(pThis);
4048 }
4049 else
4050 rc = VERR_NET_DOWN;
4051 if (RT_FAILURE(rc))
4052 {
4053 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4054 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4055 }
4056
4057 pThis->led.Actual.s.fWriting = 0;
4058}
4059
4060/**
4061 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4062 *
4063 * @param pThis The device state structure.
4064 * @param pPkt Pointer to the packet.
4065 * @param u16PktLen Total length of the packet.
4066 * @param cso Offset in packet to write checksum at.
4067 * @param css Offset in packet to start computing
4068 * checksum from.
4069 * @param cse Offset in packet to stop computing
4070 * checksum at.
4071 * @thread E1000_TX
4072 */
4073static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
4074{
4075 RT_NOREF1(pThis);
4076
4077 if (css >= u16PktLen)
4078 {
4079 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4080 pThis->szPrf, cso, u16PktLen));
4081 return;
4082 }
4083
4084 if (cso >= u16PktLen - 1)
4085 {
4086 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4087 pThis->szPrf, cso, u16PktLen));
4088 return;
4089 }
4090
4091 if (cse == 0)
4092 cse = u16PktLen - 1;
4093 else if (cse < css)
4094 {
4095 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4096 pThis->szPrf, css, cse));
4097 return;
4098 }
4099
4100 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4101 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4102 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4103 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4104}
4105
4106/**
4107 * Add a part of descriptor's buffer to transmit frame.
4108 *
4109 * @remarks data.u64BufAddr is used unconditionally for both data
4110 * and legacy descriptors since it is identical to
4111 * legacy.u64BufAddr.
4112 *
4113 * @param pThis The device state structure.
4114 * @param pDesc Pointer to the descriptor to transmit.
4115 * @param u16Len Length of buffer to the end of segment.
4116 * @param fSend Force packet sending.
4117 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4118 * @thread E1000_TX
4119 */
4120#ifndef E1K_WITH_TXD_CACHE
4121static void e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4122{
4123 /* TCP header being transmitted */
4124 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4125 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4126 /* IP header being transmitted */
4127 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4128 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4129
4130 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4131 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4132 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4133
4134 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4135 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4136 E1kLog3(("%s Dump of the segment:\n"
4137 "%.*Rhxd\n"
4138 "%s --- End of dump ---\n",
4139 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4140 pThis->u16TxPktLen += u16Len;
4141 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4142 pThis->szPrf, pThis->u16TxPktLen));
4143 if (pThis->u16HdrRemain > 0)
4144 {
4145 /* The header was not complete, check if it is now */
4146 if (u16Len >= pThis->u16HdrRemain)
4147 {
4148 /* The rest is payload */
4149 u16Len -= pThis->u16HdrRemain;
4150 pThis->u16HdrRemain = 0;
4151 /* Save partial checksum and flags */
4152 pThis->u32SavedCsum = pTcpHdr->chksum;
4153 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4154 /* Clear FIN and PSH flags now and set them only in the last segment */
4155 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4156 }
4157 else
4158 {
4159 /* Still not */
4160 pThis->u16HdrRemain -= u16Len;
4161 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4162 pThis->szPrf, pThis->u16HdrRemain));
4163 return;
4164 }
4165 }
4166
4167 pThis->u32PayRemain -= u16Len;
4168
4169 if (fSend)
4170 {
4171 /* Leave ethernet header intact */
4172 /* IP Total Length = payload + headers - ethernet header */
4173 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4174 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4175 pThis->szPrf, ntohs(pIpHdr->total_len)));
4176 /* Update IP Checksum */
4177 pIpHdr->chksum = 0;
4178 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4179 pThis->contextTSE.ip.u8CSO,
4180 pThis->contextTSE.ip.u8CSS,
4181 pThis->contextTSE.ip.u16CSE);
4182
4183 /* Update TCP flags */
4184 /* Restore original FIN and PSH flags for the last segment */
4185 if (pThis->u32PayRemain == 0)
4186 {
4187 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4188 E1K_INC_CNT32(TSCTC);
4189 }
4190 /* Add TCP length to partial pseudo header sum */
4191 uint32_t csum = pThis->u32SavedCsum
4192 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4193 while (csum >> 16)
4194 csum = (csum >> 16) + (csum & 0xFFFF);
4195 pTcpHdr->chksum = csum;
4196 /* Compute final checksum */
4197 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4198 pThis->contextTSE.tu.u8CSO,
4199 pThis->contextTSE.tu.u8CSS,
4200 pThis->contextTSE.tu.u16CSE);
4201
4202 /*
4203 * Transmit it. If we've use the SG already, allocate a new one before
4204 * we copy of the data.
4205 */
4206 if (!pThis->CTX_SUFF(pTxSg))
4207 e1kXmitAllocBuf(pThis, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4208 if (pThis->CTX_SUFF(pTxSg))
4209 {
4210 Assert(pThis->u16TxPktLen <= pThis->CTX_SUFF(pTxSg)->cbAvailable);
4211 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4212 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4213 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4214 pThis->CTX_SUFF(pTxSg)->cbUsed = pThis->u16TxPktLen;
4215 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = pThis->u16TxPktLen;
4216 }
4217 e1kTransmitFrame(pThis, fOnWorkerThread);
4218
4219 /* Update Sequence Number */
4220 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4221 - pThis->contextTSE.dw3.u8HDRLEN);
4222 /* Increment IP identification */
4223 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4224 }
4225}
4226#else /* E1K_WITH_TXD_CACHE */
4227static int e1kFallbackAddSegment(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4228{
4229 int rc = VINF_SUCCESS;
4230 /* TCP header being transmitted */
4231 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)
4232 (pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4233 /* IP header being transmitted */
4234 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)
4235 (pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4236
4237 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4238 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4239 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4240
4241 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4242 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4243 pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4244 else
4245 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4246 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4247 E1kLog3(("%s Dump of the segment:\n"
4248 "%.*Rhxd\n"
4249 "%s --- End of dump ---\n",
4250 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4251 pThis->u16TxPktLen += u16Len;
4252 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4253 pThis->szPrf, pThis->u16TxPktLen));
4254 if (pThis->u16HdrRemain > 0)
4255 {
4256 /* The header was not complete, check if it is now */
4257 if (u16Len >= pThis->u16HdrRemain)
4258 {
4259 /* The rest is payload */
4260 u16Len -= pThis->u16HdrRemain;
4261 pThis->u16HdrRemain = 0;
4262 /* Save partial checksum and flags */
4263 pThis->u32SavedCsum = pTcpHdr->chksum;
4264 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4265 /* Clear FIN and PSH flags now and set them only in the last segment */
4266 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4267 }
4268 else
4269 {
4270 /* Still not */
4271 pThis->u16HdrRemain -= u16Len;
4272 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4273 pThis->szPrf, pThis->u16HdrRemain));
4274 return rc;
4275 }
4276 }
4277
4278 pThis->u32PayRemain -= u16Len;
4279
4280 if (fSend)
4281 {
4282 /* Leave ethernet header intact */
4283 /* IP Total Length = payload + headers - ethernet header */
4284 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4285 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4286 pThis->szPrf, ntohs(pIpHdr->total_len)));
4287 /* Update IP Checksum */
4288 pIpHdr->chksum = 0;
4289 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4290 pThis->contextTSE.ip.u8CSO,
4291 pThis->contextTSE.ip.u8CSS,
4292 pThis->contextTSE.ip.u16CSE);
4293
4294 /* Update TCP flags */
4295 /* Restore original FIN and PSH flags for the last segment */
4296 if (pThis->u32PayRemain == 0)
4297 {
4298 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4299 E1K_INC_CNT32(TSCTC);
4300 }
4301 /* Add TCP length to partial pseudo header sum */
4302 uint32_t csum = pThis->u32SavedCsum
4303 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4304 while (csum >> 16)
4305 csum = (csum >> 16) + (csum & 0xFFFF);
4306 pTcpHdr->chksum = csum;
4307 /* Compute final checksum */
4308 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4309 pThis->contextTSE.tu.u8CSO,
4310 pThis->contextTSE.tu.u8CSS,
4311 pThis->contextTSE.tu.u16CSE);
4312
4313 /*
4314 * Transmit it.
4315 */
4316 if (pThis->CTX_SUFF(pTxSg))
4317 {
4318 /* Make sure the packet fits into the allocated buffer */
4319 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThis->CTX_SUFF(pTxSg)->cbAvailable);
4320#ifdef DEBUG
4321 if (pThis->u16TxPktLen > pThis->CTX_SUFF(pTxSg)->cbAvailable)
4322 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4323 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen,
4324 pThis->CTX_SUFF(pTxSg)->cbAvailable, pThis->CTX_SUFF(pTxSg)->cbAvailable));
4325#endif /* DEBUG */
4326 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4327 if (pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4328 memcpy(pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4329 pThis->CTX_SUFF(pTxSg)->cbUsed = cbCopy;
4330 pThis->CTX_SUFF(pTxSg)->aSegs[0].cbSeg = cbCopy;
4331 }
4332 e1kTransmitFrame(pThis, fOnWorkerThread);
4333
4334 /* Update Sequence Number */
4335 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4336 - pThis->contextTSE.dw3.u8HDRLEN);
4337 /* Increment IP identification */
4338 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4339
4340 /* Allocate new buffer for the next segment. */
4341 if (pThis->u32PayRemain)
4342 {
4343 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4344 pThis->contextTSE.dw3.u16MSS)
4345 + pThis->contextTSE.dw3.u8HDRLEN
4346 + (pThis->fVTag ? 4 : 0);
4347 rc = e1kXmitAllocBuf(pThis, false /* fGSO */);
4348 }
4349 }
4350
4351 return rc;
4352}
4353#endif /* E1K_WITH_TXD_CACHE */
4354
4355#ifndef E1K_WITH_TXD_CACHE
4356/**
4357 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4358 * frame.
4359 *
4360 * We construct the frame in the fallback buffer first and the copy it to the SG
4361 * buffer before passing it down to the network driver code.
4362 *
4363 * @returns true if the frame should be transmitted, false if not.
4364 *
4365 * @param pThis The device state structure.
4366 * @param pDesc Pointer to the descriptor to transmit.
4367 * @param cbFragment Length of descriptor's buffer.
4368 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4369 * @thread E1000_TX
4370 */
4371static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4372{
4373 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4374 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4375 Assert(pDesc->data.cmd.fTSE);
4376 Assert(!e1kXmitIsGsoBuf(pTxSg));
4377
4378 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4379 Assert(u16MaxPktLen != 0);
4380 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4381
4382 /*
4383 * Carve out segments.
4384 */
4385 do
4386 {
4387 /* Calculate how many bytes we have left in this TCP segment */
4388 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4389 if (cb > cbFragment)
4390 {
4391 /* This descriptor fits completely into current segment */
4392 cb = cbFragment;
4393 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4394 }
4395 else
4396 {
4397 e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4398 /*
4399 * Rewind the packet tail pointer to the beginning of payload,
4400 * so we continue writing right beyond the header.
4401 */
4402 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4403 }
4404
4405 pDesc->data.u64BufAddr += cb;
4406 cbFragment -= cb;
4407 } while (cbFragment > 0);
4408
4409 if (pDesc->data.cmd.fEOP)
4410 {
4411 /* End of packet, next segment will contain header. */
4412 if (pThis->u32PayRemain != 0)
4413 E1K_INC_CNT32(TSCTFC);
4414 pThis->u16TxPktLen = 0;
4415 e1kXmitFreeBuf(pThis);
4416 }
4417
4418 return false;
4419}
4420#else /* E1K_WITH_TXD_CACHE */
4421/**
4422 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4423 * frame.
4424 *
4425 * We construct the frame in the fallback buffer first and the copy it to the SG
4426 * buffer before passing it down to the network driver code.
4427 *
4428 * @returns error code
4429 *
4430 * @param pThis The device state structure.
4431 * @param pDesc Pointer to the descriptor to transmit.
4432 * @param cbFragment Length of descriptor's buffer.
4433 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4434 * @thread E1000_TX
4435 */
4436static int e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4437{
4438#ifdef VBOX_STRICT
4439 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4440 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4441 Assert(pDesc->data.cmd.fTSE);
4442 Assert(!e1kXmitIsGsoBuf(pTxSg));
4443#endif
4444
4445 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4446
4447 /*
4448 * Carve out segments.
4449 */
4450 int rc = VINF_SUCCESS;
4451 do
4452 {
4453 /* Calculate how many bytes we have left in this TCP segment */
4454 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4455 if (cb > pDesc->data.cmd.u20DTALEN)
4456 {
4457 /* This descriptor fits completely into current segment */
4458 cb = pDesc->data.cmd.u20DTALEN;
4459 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4460 }
4461 else
4462 {
4463 rc = e1kFallbackAddSegment(pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4464 /*
4465 * Rewind the packet tail pointer to the beginning of payload,
4466 * so we continue writing right beyond the header.
4467 */
4468 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4469 }
4470
4471 pDesc->data.u64BufAddr += cb;
4472 pDesc->data.cmd.u20DTALEN -= cb;
4473 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4474
4475 if (pDesc->data.cmd.fEOP)
4476 {
4477 /* End of packet, next segment will contain header. */
4478 if (pThis->u32PayRemain != 0)
4479 E1K_INC_CNT32(TSCTFC);
4480 pThis->u16TxPktLen = 0;
4481 e1kXmitFreeBuf(pThis);
4482 }
4483
4484 return VINF_SUCCESS; /// @todo consider rc;
4485}
4486#endif /* E1K_WITH_TXD_CACHE */
4487
4488
4489/**
4490 * Add descriptor's buffer to transmit frame.
4491 *
4492 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4493 * TSE frames we cannot handle as GSO.
4494 *
4495 * @returns true on success, false on failure.
4496 *
4497 * @param pThis The device state structure.
4498 * @param PhysAddr The physical address of the descriptor buffer.
4499 * @param cbFragment Length of descriptor's buffer.
4500 * @thread E1000_TX
4501 */
4502static bool e1kAddToFrame(PE1KSTATE pThis, RTGCPHYS PhysAddr, uint32_t cbFragment)
4503{
4504 PPDMSCATTERGATHER pTxSg = pThis->CTX_SUFF(pTxSg);
4505 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4506 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4507
4508 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4509 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4510 fGso ? "true" : "false"));
4511 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4512 {
4513 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4514 return false;
4515 }
4516 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4517 {
4518 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4519 return false;
4520 }
4521
4522 if (RT_LIKELY(pTxSg))
4523 {
4524 Assert(pTxSg->cSegs == 1);
4525 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4526 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4527 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4528
4529 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), PhysAddr,
4530 (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4531
4532 pTxSg->cbUsed = cbNewPkt;
4533 }
4534 pThis->u16TxPktLen = cbNewPkt;
4535
4536 return true;
4537}
4538
4539
4540/**
4541 * Write the descriptor back to guest memory and notify the guest.
4542 *
4543 * @param pThis The device state structure.
4544 * @param pDesc Pointer to the descriptor have been transmitted.
4545 * @param addr Physical address of the descriptor in guest memory.
4546 * @thread E1000_TX
4547 */
4548static void e1kDescReport(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4549{
4550 /*
4551 * We fake descriptor write-back bursting. Descriptors are written back as they are
4552 * processed.
4553 */
4554 /* Let's pretend we process descriptors. Write back with DD set. */
4555 /*
4556 * Prior to r71586 we tried to accomodate the case when write-back bursts
4557 * are enabled without actually implementing bursting by writing back all
4558 * descriptors, even the ones that do not have RS set. This caused kernel
4559 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4560 * associated with written back descriptor if it happened to be a context
4561 * descriptor since context descriptors do not have skb associated to them.
4562 * Starting from r71586 we write back only the descriptors with RS set,
4563 * which is a little bit different from what the real hardware does in
4564 * case there is a chain of data descritors where some of them have RS set
4565 * and others do not. It is very uncommon scenario imho.
4566 * We need to check RPS as well since some legacy drivers use it instead of
4567 * RS even with newer cards.
4568 */
4569 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4570 {
4571 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4572 e1kWriteBackDesc(pThis, pDesc, addr);
4573 if (pDesc->legacy.cmd.fEOP)
4574 {
4575//#ifdef E1K_USE_TX_TIMERS
4576 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4577 {
4578 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4579 //if (pThis->fIntRaised)
4580 //{
4581 // /* Interrupt is already pending, no need for timers */
4582 // ICR |= ICR_TXDW;
4583 //}
4584 //else {
4585 /* Arm the timer to fire in TIVD usec (discard .024) */
4586 e1kArmTimer(pThis, pThis->CTX_SUFF(pTIDTimer), TIDV);
4587# ifndef E1K_NO_TAD
4588 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4589 E1kLog2(("%s Checking if TAD timer is running\n",
4590 pThis->szPrf));
4591 if (TADV != 0 && !TMTimerIsActive(pThis->CTX_SUFF(pTADTimer)))
4592 e1kArmTimer(pThis, pThis->CTX_SUFF(pTADTimer), TADV);
4593# endif /* E1K_NO_TAD */
4594 }
4595 else
4596 {
4597 if (pThis->fTidEnabled)
4598 {
4599 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4600 pThis->szPrf));
4601 /* Cancel both timers if armed and fire immediately. */
4602# ifndef E1K_NO_TAD
4603 TMTimerStop(pThis->CTX_SUFF(pTADTimer));
4604# endif
4605 TMTimerStop(pThis->CTX_SUFF(pTIDTimer));
4606 }
4607//#endif /* E1K_USE_TX_TIMERS */
4608 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4609 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXDW);
4610//#ifdef E1K_USE_TX_TIMERS
4611 }
4612//#endif /* E1K_USE_TX_TIMERS */
4613 }
4614 }
4615 else
4616 {
4617 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4618 }
4619}
4620
4621#ifndef E1K_WITH_TXD_CACHE
4622
4623/**
4624 * Process Transmit Descriptor.
4625 *
4626 * E1000 supports three types of transmit descriptors:
4627 * - legacy data descriptors of older format (context-less).
4628 * - data the same as legacy but providing new offloading capabilities.
4629 * - context sets up the context for following data descriptors.
4630 *
4631 * @param pThis The device state structure.
4632 * @param pDesc Pointer to descriptor union.
4633 * @param addr Physical address of descriptor in guest memory.
4634 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4635 * @thread E1000_TX
4636 */
4637static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr, bool fOnWorkerThread)
4638{
4639 int rc = VINF_SUCCESS;
4640 uint32_t cbVTag = 0;
4641
4642 e1kPrintTDesc(pThis, pDesc, "vvv");
4643
4644//#ifdef E1K_USE_TX_TIMERS
4645 if (pThis->fTidEnabled)
4646 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
4647//#endif /* E1K_USE_TX_TIMERS */
4648
4649 switch (e1kGetDescType(pDesc))
4650 {
4651 case E1K_DTYP_CONTEXT:
4652 if (pDesc->context.dw2.fTSE)
4653 {
4654 pThis->contextTSE = pDesc->context;
4655 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4656 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4657 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4658 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4659 }
4660 else
4661 {
4662 pThis->contextNormal = pDesc->context;
4663 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4664 }
4665 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4666 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4667 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4668 pDesc->context.ip.u8CSS,
4669 pDesc->context.ip.u8CSO,
4670 pDesc->context.ip.u16CSE,
4671 pDesc->context.tu.u8CSS,
4672 pDesc->context.tu.u8CSO,
4673 pDesc->context.tu.u16CSE));
4674 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4675 e1kDescReport(pThis, pDesc, addr);
4676 break;
4677
4678 case E1K_DTYP_DATA:
4679 {
4680 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4681 {
4682 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4683 /** @todo Same as legacy when !TSE. See below. */
4684 break;
4685 }
4686 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4687 &pThis->StatTxDescTSEData:
4688 &pThis->StatTxDescData);
4689 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4690 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4691
4692 /*
4693 * The last descriptor of non-TSE packet must contain VLE flag.
4694 * TSE packets have VLE flag in the first descriptor. The later
4695 * case is taken care of a bit later when cbVTag gets assigned.
4696 *
4697 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4698 */
4699 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4700 {
4701 pThis->fVTag = pDesc->data.cmd.fVLE;
4702 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4703 }
4704 /*
4705 * First fragment: Allocate new buffer and save the IXSM and TXSM
4706 * packet options as these are only valid in the first fragment.
4707 */
4708 if (pThis->u16TxPktLen == 0)
4709 {
4710 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4711 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4712 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4713 pThis->fIPcsum ? " IP" : "",
4714 pThis->fTCPcsum ? " TCP/UDP" : ""));
4715 if (pDesc->data.cmd.fTSE)
4716 {
4717 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4718 pThis->fVTag = pDesc->data.cmd.fVLE;
4719 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4720 cbVTag = pThis->fVTag ? 4 : 0;
4721 }
4722 else if (pDesc->data.cmd.fEOP)
4723 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4724 else
4725 cbVTag = 4;
4726 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4727 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4728 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4729 true /*fExactSize*/, true /*fGso*/);
4730 else if (pDesc->data.cmd.fTSE)
4731 rc = e1kXmitAllocBuf(pThis, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4732 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4733 else
4734 rc = e1kXmitAllocBuf(pThis, pDesc->data.cmd.u20DTALEN + cbVTag,
4735 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4736
4737 /**
4738 * @todo: Perhaps it is not that simple for GSO packets! We may
4739 * need to unwind some changes.
4740 */
4741 if (RT_FAILURE(rc))
4742 {
4743 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4744 break;
4745 }
4746 /** @todo Is there any way to indicating errors other than collisions? Like
4747 * VERR_NET_DOWN. */
4748 }
4749
4750 /*
4751 * Add the descriptor data to the frame. If the frame is complete,
4752 * transmit it and reset the u16TxPktLen field.
4753 */
4754 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4755 {
4756 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4757 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4758 if (pDesc->data.cmd.fEOP)
4759 {
4760 if ( fRc
4761 && pThis->CTX_SUFF(pTxSg)
4762 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4763 {
4764 e1kTransmitFrame(pThis, fOnWorkerThread);
4765 E1K_INC_CNT32(TSCTC);
4766 }
4767 else
4768 {
4769 if (fRc)
4770 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4771 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4772 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4773 e1kXmitFreeBuf(pThis);
4774 E1K_INC_CNT32(TSCTFC);
4775 }
4776 pThis->u16TxPktLen = 0;
4777 }
4778 }
4779 else if (!pDesc->data.cmd.fTSE)
4780 {
4781 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4782 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4783 if (pDesc->data.cmd.fEOP)
4784 {
4785 if (fRc && pThis->CTX_SUFF(pTxSg))
4786 {
4787 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4788 if (pThis->fIPcsum)
4789 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4790 pThis->contextNormal.ip.u8CSO,
4791 pThis->contextNormal.ip.u8CSS,
4792 pThis->contextNormal.ip.u16CSE);
4793 if (pThis->fTCPcsum)
4794 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4795 pThis->contextNormal.tu.u8CSO,
4796 pThis->contextNormal.tu.u8CSS,
4797 pThis->contextNormal.tu.u16CSE);
4798 e1kTransmitFrame(pThis, fOnWorkerThread);
4799 }
4800 else
4801 e1kXmitFreeBuf(pThis);
4802 pThis->u16TxPktLen = 0;
4803 }
4804 }
4805 else
4806 {
4807 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4808 e1kFallbackAddToFrame(pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4809 }
4810
4811 e1kDescReport(pThis, pDesc, addr);
4812 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4813 break;
4814 }
4815
4816 case E1K_DTYP_LEGACY:
4817 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4818 {
4819 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4820 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4821 break;
4822 }
4823 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4824 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4825
4826 /* First fragment: allocate new buffer. */
4827 if (pThis->u16TxPktLen == 0)
4828 {
4829 if (pDesc->legacy.cmd.fEOP)
4830 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4831 else
4832 cbVTag = 4;
4833 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4834 /** @todo reset status bits? */
4835 rc = e1kXmitAllocBuf(pThis, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4836 if (RT_FAILURE(rc))
4837 {
4838 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4839 break;
4840 }
4841
4842 /** @todo Is there any way to indicating errors other than collisions? Like
4843 * VERR_NET_DOWN. */
4844 }
4845
4846 /* Add fragment to frame. */
4847 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4848 {
4849 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4850
4851 /* Last fragment: Transmit and reset the packet storage counter. */
4852 if (pDesc->legacy.cmd.fEOP)
4853 {
4854 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4855 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4856 /** @todo Offload processing goes here. */
4857 e1kTransmitFrame(pThis, fOnWorkerThread);
4858 pThis->u16TxPktLen = 0;
4859 }
4860 }
4861 /* Last fragment + failure: free the buffer and reset the storage counter. */
4862 else if (pDesc->legacy.cmd.fEOP)
4863 {
4864 e1kXmitFreeBuf(pThis);
4865 pThis->u16TxPktLen = 0;
4866 }
4867
4868 e1kDescReport(pThis, pDesc, addr);
4869 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4870 break;
4871
4872 default:
4873 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4874 pThis->szPrf, e1kGetDescType(pDesc)));
4875 break;
4876 }
4877
4878 return rc;
4879}
4880
4881#else /* E1K_WITH_TXD_CACHE */
4882
4883/**
4884 * Process Transmit Descriptor.
4885 *
4886 * E1000 supports three types of transmit descriptors:
4887 * - legacy data descriptors of older format (context-less).
4888 * - data the same as legacy but providing new offloading capabilities.
4889 * - context sets up the context for following data descriptors.
4890 *
4891 * @param pThis The device state structure.
4892 * @param pDesc Pointer to descriptor union.
4893 * @param addr Physical address of descriptor in guest memory.
4894 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4895 * @param cbPacketSize Size of the packet as previously computed.
4896 * @thread E1000_TX
4897 */
4898static int e1kXmitDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr,
4899 bool fOnWorkerThread)
4900{
4901 int rc = VINF_SUCCESS;
4902
4903 e1kPrintTDesc(pThis, pDesc, "vvv");
4904
4905 if (pDesc->legacy.dw3.fDD)
4906 {
4907 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
4908 e1kDescReport(pThis, pDesc, addr);
4909 return VINF_SUCCESS;
4910 }
4911
4912//#ifdef E1K_USE_TX_TIMERS
4913 if (pThis->fTidEnabled)
4914 TMTimerStop(pThis->CTX_SUFF(pTIDTimer));
4915//#endif /* E1K_USE_TX_TIMERS */
4916
4917 switch (e1kGetDescType(pDesc))
4918 {
4919 case E1K_DTYP_CONTEXT:
4920 /* The caller have already updated the context */
4921 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4922 e1kDescReport(pThis, pDesc, addr);
4923 break;
4924
4925 case E1K_DTYP_DATA:
4926 {
4927 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4928 &pThis->StatTxDescTSEData:
4929 &pThis->StatTxDescData);
4930 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4931 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4932 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4933 {
4934 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4935 if (pDesc->data.cmd.fEOP)
4936 {
4937 e1kTransmitFrame(pThis, fOnWorkerThread);
4938 pThis->u16TxPktLen = 0;
4939 }
4940 }
4941 else
4942 {
4943 /*
4944 * Add the descriptor data to the frame. If the frame is complete,
4945 * transmit it and reset the u16TxPktLen field.
4946 */
4947 if (e1kXmitIsGsoBuf(pThis->CTX_SUFF(pTxSg)))
4948 {
4949 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4950 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4951 if (pDesc->data.cmd.fEOP)
4952 {
4953 if ( fRc
4954 && pThis->CTX_SUFF(pTxSg)
4955 && pThis->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4956 {
4957 e1kTransmitFrame(pThis, fOnWorkerThread);
4958 E1K_INC_CNT32(TSCTC);
4959 }
4960 else
4961 {
4962 if (fRc)
4963 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4964 pThis->CTX_SUFF(pTxSg), pThis->CTX_SUFF(pTxSg) ? pThis->CTX_SUFF(pTxSg)->cbUsed : 0,
4965 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4966 e1kXmitFreeBuf(pThis);
4967 E1K_INC_CNT32(TSCTFC);
4968 }
4969 pThis->u16TxPktLen = 0;
4970 }
4971 }
4972 else if (!pDesc->data.cmd.fTSE)
4973 {
4974 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4975 bool fRc = e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4976 if (pDesc->data.cmd.fEOP)
4977 {
4978 if (fRc && pThis->CTX_SUFF(pTxSg))
4979 {
4980 Assert(pThis->CTX_SUFF(pTxSg)->cSegs == 1);
4981 if (pThis->fIPcsum)
4982 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4983 pThis->contextNormal.ip.u8CSO,
4984 pThis->contextNormal.ip.u8CSS,
4985 pThis->contextNormal.ip.u16CSE);
4986 if (pThis->fTCPcsum)
4987 e1kInsertChecksum(pThis, (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4988 pThis->contextNormal.tu.u8CSO,
4989 pThis->contextNormal.tu.u8CSS,
4990 pThis->contextNormal.tu.u16CSE);
4991 e1kTransmitFrame(pThis, fOnWorkerThread);
4992 }
4993 else
4994 e1kXmitFreeBuf(pThis);
4995 pThis->u16TxPktLen = 0;
4996 }
4997 }
4998 else
4999 {
5000 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5001 rc = e1kFallbackAddToFrame(pThis, pDesc, fOnWorkerThread);
5002 }
5003 }
5004 e1kDescReport(pThis, pDesc, addr);
5005 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5006 break;
5007 }
5008
5009 case E1K_DTYP_LEGACY:
5010 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5011 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5012 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5013 {
5014 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5015 }
5016 else
5017 {
5018 /* Add fragment to frame. */
5019 if (e1kAddToFrame(pThis, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5020 {
5021 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5022
5023 /* Last fragment: Transmit and reset the packet storage counter. */
5024 if (pDesc->legacy.cmd.fEOP)
5025 {
5026 if (pDesc->legacy.cmd.fIC)
5027 {
5028 e1kInsertChecksum(pThis,
5029 (uint8_t *)pThis->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5030 pThis->u16TxPktLen,
5031 pDesc->legacy.cmd.u8CSO,
5032 pDesc->legacy.dw3.u8CSS,
5033 0);
5034 }
5035 e1kTransmitFrame(pThis, fOnWorkerThread);
5036 pThis->u16TxPktLen = 0;
5037 }
5038 }
5039 /* Last fragment + failure: free the buffer and reset the storage counter. */
5040 else if (pDesc->legacy.cmd.fEOP)
5041 {
5042 e1kXmitFreeBuf(pThis);
5043 pThis->u16TxPktLen = 0;
5044 }
5045 }
5046 e1kDescReport(pThis, pDesc, addr);
5047 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5048 break;
5049
5050 default:
5051 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5052 pThis->szPrf, e1kGetDescType(pDesc)));
5053 break;
5054 }
5055
5056 return rc;
5057}
5058
5059DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5060{
5061 if (pDesc->context.dw2.fTSE)
5062 {
5063 pThis->contextTSE = pDesc->context;
5064 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5065 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5066 {
5067 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5068 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5069 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5070 }
5071 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5072 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5073 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5074 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5075 }
5076 else
5077 {
5078 pThis->contextNormal = pDesc->context;
5079 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5080 }
5081 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5082 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5083 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5084 pDesc->context.ip.u8CSS,
5085 pDesc->context.ip.u8CSO,
5086 pDesc->context.ip.u16CSE,
5087 pDesc->context.tu.u8CSS,
5088 pDesc->context.tu.u8CSO,
5089 pDesc->context.tu.u16CSE));
5090}
5091
5092static bool e1kLocateTxPacket(PE1KSTATE pThis)
5093{
5094 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5095 pThis->szPrf, pThis->cbTxAlloc));
5096 /* Check if we have located the packet already. */
5097 if (pThis->cbTxAlloc)
5098 {
5099 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5100 pThis->szPrf, pThis->cbTxAlloc));
5101 return true;
5102 }
5103
5104 bool fTSE = false;
5105 uint32_t cbPacket = 0;
5106
5107 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5108 {
5109 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5110 switch (e1kGetDescType(pDesc))
5111 {
5112 case E1K_DTYP_CONTEXT:
5113 if (cbPacket == 0)
5114 e1kUpdateTxContext(pThis, pDesc);
5115 else
5116 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5117 pThis->szPrf, cbPacket));
5118 continue;
5119 case E1K_DTYP_LEGACY:
5120 /* Skip invalid descriptors. */
5121 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5122 {
5123 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5124 pThis->szPrf, cbPacket));
5125 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5126 continue;
5127 }
5128 /* Skip empty descriptors. */
5129 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5130 break;
5131 cbPacket += pDesc->legacy.cmd.u16Length;
5132 pThis->fGSO = false;
5133 break;
5134 case E1K_DTYP_DATA:
5135 /* Skip invalid descriptors. */
5136 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5137 {
5138 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5139 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5140 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5141 continue;
5142 }
5143 /* Skip empty descriptors. */
5144 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5145 break;
5146 if (cbPacket == 0)
5147 {
5148 /*
5149 * The first fragment: save IXSM and TXSM options
5150 * as these are only valid in the first fragment.
5151 */
5152 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5153 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5154 fTSE = pDesc->data.cmd.fTSE;
5155 /*
5156 * TSE descriptors have VLE bit properly set in
5157 * the first fragment.
5158 */
5159 if (fTSE)
5160 {
5161 pThis->fVTag = pDesc->data.cmd.fVLE;
5162 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5163 }
5164 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5165 }
5166 cbPacket += pDesc->data.cmd.u20DTALEN;
5167 break;
5168 default:
5169 AssertMsgFailed(("Impossible descriptor type!"));
5170 }
5171 if (pDesc->legacy.cmd.fEOP)
5172 {
5173 /*
5174 * Non-TSE descriptors have VLE bit properly set in
5175 * the last fragment.
5176 */
5177 if (!fTSE)
5178 {
5179 pThis->fVTag = pDesc->data.cmd.fVLE;
5180 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5181 }
5182 /*
5183 * Compute the required buffer size. If we cannot do GSO but still
5184 * have to do segmentation we allocate the first segment only.
5185 */
5186 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5187 cbPacket :
5188 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5189 if (pThis->fVTag)
5190 pThis->cbTxAlloc += 4;
5191 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5192 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5193 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5194 return true;
5195 }
5196 }
5197
5198 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5199 {
5200 /* All descriptors were empty, we need to process them as a dummy packet */
5201 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5202 pThis->szPrf, pThis->cbTxAlloc));
5203 return true;
5204 }
5205 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5206 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5207 return false;
5208}
5209
5210static int e1kXmitPacket(PE1KSTATE pThis, bool fOnWorkerThread)
5211{
5212 int rc = VINF_SUCCESS;
5213
5214 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5215 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5216
5217 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5218 {
5219 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5220 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5221 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5222 rc = e1kXmitDesc(pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5223 if (RT_FAILURE(rc))
5224 break;
5225 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5226 TDH = 0;
5227 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5228 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5229 {
5230 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5231 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5232 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5233 }
5234 ++pThis->iTxDCurrent;
5235 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5236 break;
5237 }
5238
5239 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5240 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5241 return rc;
5242}
5243
5244#endif /* E1K_WITH_TXD_CACHE */
5245#ifndef E1K_WITH_TXD_CACHE
5246
5247/**
5248 * Transmit pending descriptors.
5249 *
5250 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5251 *
5252 * @param pThis The E1000 state.
5253 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5254 */
5255static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5256{
5257 int rc = VINF_SUCCESS;
5258
5259 /* Check if transmitter is enabled. */
5260 if (!(TCTL & TCTL_EN))
5261 return VINF_SUCCESS;
5262 /*
5263 * Grab the xmit lock of the driver as well as the E1K device state.
5264 */
5265 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5266 if (RT_LIKELY(rc == VINF_SUCCESS))
5267 {
5268 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5269 if (pDrv)
5270 {
5271 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5272 if (RT_FAILURE(rc))
5273 {
5274 e1kCsTxLeave(pThis);
5275 return rc;
5276 }
5277 }
5278 /*
5279 * Process all pending descriptors.
5280 * Note! Do not process descriptors in locked state
5281 */
5282 while (TDH != TDT && !pThis->fLocked)
5283 {
5284 E1KTXDESC desc;
5285 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5286 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5287
5288 e1kLoadDesc(pThis, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5289 rc = e1kXmitDesc(pThis, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5290 /* If we failed to transmit descriptor we will try it again later */
5291 if (RT_FAILURE(rc))
5292 break;
5293 if (++TDH * sizeof(desc) >= TDLEN)
5294 TDH = 0;
5295
5296 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5297 {
5298 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5299 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5300 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5301 }
5302
5303 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5304 }
5305
5306 /// @todo uncomment: pThis->uStatIntTXQE++;
5307 /// @todo uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5308 /*
5309 * Release the lock.
5310 */
5311 if (pDrv)
5312 pDrv->pfnEndXmit(pDrv);
5313 e1kCsTxLeave(pThis);
5314 }
5315
5316 return rc;
5317}
5318
5319#else /* E1K_WITH_TXD_CACHE */
5320
5321static void e1kDumpTxDCache(PE1KSTATE pThis)
5322{
5323 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5324 uint32_t tdh = TDH;
5325 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5326 for (i = 0; i < cDescs; ++i)
5327 {
5328 E1KTXDESC desc;
5329 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(TDBAH, TDBAL, i),
5330 &desc, sizeof(desc));
5331 if (i == tdh)
5332 LogRel(("E1000: >>> "));
5333 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5334 }
5335 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5336 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5337 if (tdh > pThis->iTxDCurrent)
5338 tdh -= pThis->iTxDCurrent;
5339 else
5340 tdh = cDescs + tdh - pThis->iTxDCurrent;
5341 for (i = 0; i < pThis->nTxDFetched; ++i)
5342 {
5343 if (i == pThis->iTxDCurrent)
5344 LogRel(("E1000: >>> "));
5345 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5346 }
5347}
5348
5349/**
5350 * Transmit pending descriptors.
5351 *
5352 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5353 *
5354 * @param pThis The E1000 state.
5355 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5356 */
5357static int e1kXmitPending(PE1KSTATE pThis, bool fOnWorkerThread)
5358{
5359 int rc = VINF_SUCCESS;
5360
5361 /* Check if transmitter is enabled. */
5362 if (!(TCTL & TCTL_EN))
5363 return VINF_SUCCESS;
5364 /*
5365 * Grab the xmit lock of the driver as well as the E1K device state.
5366 */
5367 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5368 if (pDrv)
5369 {
5370 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5371 if (RT_FAILURE(rc))
5372 return rc;
5373 }
5374
5375 /*
5376 * Process all pending descriptors.
5377 * Note! Do not process descriptors in locked state
5378 */
5379 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5380 if (RT_LIKELY(rc == VINF_SUCCESS))
5381 {
5382 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5383 /*
5384 * fIncomplete is set whenever we try to fetch additional descriptors
5385 * for an incomplete packet. If fail to locate a complete packet on
5386 * the next iteration we need to reset the cache or we risk to get
5387 * stuck in this loop forever.
5388 */
5389 bool fIncomplete = false;
5390 while (!pThis->fLocked && e1kTxDLazyLoad(pThis))
5391 {
5392 while (e1kLocateTxPacket(pThis))
5393 {
5394 fIncomplete = false;
5395 /* Found a complete packet, allocate it. */
5396 rc = e1kXmitAllocBuf(pThis, pThis->fGSO);
5397 /* If we're out of bandwidth we'll come back later. */
5398 if (RT_FAILURE(rc))
5399 goto out;
5400 /* Copy the packet to allocated buffer and send it. */
5401 rc = e1kXmitPacket(pThis, fOnWorkerThread);
5402 /* If we're out of bandwidth we'll come back later. */
5403 if (RT_FAILURE(rc))
5404 goto out;
5405 }
5406 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5407 if (RT_UNLIKELY(fIncomplete))
5408 {
5409 static bool fTxDCacheDumped = false;
5410 /*
5411 * The descriptor cache is full, but we were unable to find
5412 * a complete packet in it. Drop the cache and hope that
5413 * the guest driver can recover from network card error.
5414 */
5415 LogRel(("%s: No complete packets in%s TxD cache! "
5416 "Fetched=%d, current=%d, TX len=%d.\n",
5417 pThis->szPrf,
5418 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5419 pThis->nTxDFetched, pThis->iTxDCurrent,
5420 e1kGetTxLen(pThis)));
5421 if (!fTxDCacheDumped)
5422 {
5423 fTxDCacheDumped = true;
5424 e1kDumpTxDCache(pThis);
5425 }
5426 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5427 /*
5428 * Returning an error at this point means Guru in R0
5429 * (see @bugref{6428}).
5430 */
5431# ifdef IN_RING3
5432 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5433# else /* !IN_RING3 */
5434 rc = VINF_IOM_R3_MMIO_WRITE;
5435# endif /* !IN_RING3 */
5436 goto out;
5437 }
5438 if (u8Remain > 0)
5439 {
5440 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5441 "%d more are available\n",
5442 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5443 e1kGetTxLen(pThis) - u8Remain));
5444
5445 /*
5446 * A packet was partially fetched. Move incomplete packet to
5447 * the beginning of cache buffer, then load more descriptors.
5448 */
5449 memmove(pThis->aTxDescriptors,
5450 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5451 u8Remain * sizeof(E1KTXDESC));
5452 pThis->iTxDCurrent = 0;
5453 pThis->nTxDFetched = u8Remain;
5454 e1kTxDLoadMore(pThis);
5455 fIncomplete = true;
5456 }
5457 else
5458 pThis->nTxDFetched = 0;
5459 pThis->iTxDCurrent = 0;
5460 }
5461 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5462 {
5463 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5464 pThis->szPrf));
5465 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5466 }
5467out:
5468 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5469
5470 /// @todo uncomment: pThis->uStatIntTXQE++;
5471 /// @todo uncomment: e1kRaiseInterrupt(pThis, ICR_TXQE);
5472
5473 e1kCsTxLeave(pThis);
5474 }
5475
5476
5477 /*
5478 * Release the lock.
5479 */
5480 if (pDrv)
5481 pDrv->pfnEndXmit(pDrv);
5482 return rc;
5483}
5484
5485#endif /* E1K_WITH_TXD_CACHE */
5486#ifdef IN_RING3
5487
5488/**
5489 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5490 */
5491static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5492{
5493 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
5494 /* Resume suspended transmission */
5495 STATUS &= ~STATUS_TXOFF;
5496 e1kXmitPending(pThis, true /*fOnWorkerThread*/);
5497}
5498
5499/**
5500 * Callback for consuming from transmit queue. It gets called in R3 whenever
5501 * we enqueue something in R0/GC.
5502 *
5503 * @returns true
5504 * @param pDevIns Pointer to device instance structure.
5505 * @param pItem Pointer to the element being dequeued (not used).
5506 * @thread ???
5507 */
5508static DECLCALLBACK(bool) e1kTxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5509{
5510 NOREF(pItem);
5511 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
5512 E1kLog2(("%s e1kTxQueueConsumer:\n", pThis->szPrf));
5513
5514 int rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/); NOREF(rc);
5515#ifndef DEBUG_andy /** @todo r=andy Happens for me a lot, mute this for me. */
5516 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
5517#endif
5518 return true;
5519}
5520
5521/**
5522 * Handler for the wakeup signaller queue.
5523 */
5524static DECLCALLBACK(bool) e1kCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)
5525{
5526 RT_NOREF(pItem);
5527 e1kWakeupReceive(pDevIns);
5528 return true;
5529}
5530
5531#endif /* IN_RING3 */
5532
5533/**
5534 * Write handler for Transmit Descriptor Tail register.
5535 *
5536 * @param pThis The device state structure.
5537 * @param offset Register offset in memory-mapped frame.
5538 * @param index Register index in register array.
5539 * @param value The value to store.
5540 * @param mask Used to implement partial writes (8 and 16-bit).
5541 * @thread EMT
5542 */
5543static int e1kRegWriteTDT(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5544{
5545 int rc = e1kRegWriteDefault(pThis, offset, index, value);
5546
5547 /* All descriptors starting with head and not including tail belong to us. */
5548 /* Process them. */
5549 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5550 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5551
5552 /* Ignore TDT writes when the link is down. */
5553 if (TDH != TDT && (STATUS & STATUS_LU))
5554 {
5555 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5556 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5557 pThis->szPrf, e1kGetTxLen(pThis)));
5558
5559 /* Transmit pending packets if possible, defer it if we cannot do it
5560 in the current context. */
5561#ifdef E1K_TX_DELAY
5562 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5563 if (RT_LIKELY(rc == VINF_SUCCESS))
5564 {
5565 if (!TMTimerIsActive(pThis->CTX_SUFF(pTXDTimer)))
5566 {
5567#ifdef E1K_INT_STATS
5568 pThis->u64ArmedAt = RTTimeNanoTS();
5569#endif
5570 e1kArmTimer(pThis, pThis->CTX_SUFF(pTXDTimer), E1K_TX_DELAY);
5571 }
5572 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5573 e1kCsTxLeave(pThis);
5574 return rc;
5575 }
5576 /* We failed to enter the TX critical section -- transmit as usual. */
5577#endif /* E1K_TX_DELAY */
5578#ifndef IN_RING3
5579 if (!pThis->CTX_SUFF(pDrv))
5580 {
5581 PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pTxQueue));
5582 if (RT_UNLIKELY(pItem))
5583 PDMQueueInsert(pThis->CTX_SUFF(pTxQueue), pItem);
5584 }
5585 else
5586#endif
5587 {
5588 rc = e1kXmitPending(pThis, false /*fOnWorkerThread*/);
5589 if (rc == VERR_TRY_AGAIN)
5590 rc = VINF_SUCCESS;
5591 else if (rc == VERR_SEM_BUSY)
5592 rc = VINF_IOM_R3_MMIO_WRITE;
5593 AssertRC(rc);
5594 }
5595 }
5596
5597 return rc;
5598}
5599
5600/**
5601 * Write handler for Multicast Table Array registers.
5602 *
5603 * @param pThis The device state structure.
5604 * @param offset Register offset in memory-mapped frame.
5605 * @param index Register index in register array.
5606 * @param value The value to store.
5607 * @thread EMT
5608 */
5609static int e1kRegWriteMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5610{
5611 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5612 pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])] = value;
5613
5614 return VINF_SUCCESS;
5615}
5616
5617/**
5618 * Read handler for Multicast Table Array registers.
5619 *
5620 * @returns VBox status code.
5621 *
5622 * @param pThis The device state structure.
5623 * @param offset Register offset in memory-mapped frame.
5624 * @param index Register index in register array.
5625 * @thread EMT
5626 */
5627static int e1kRegReadMTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5628{
5629 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5630 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5631
5632 return VINF_SUCCESS;
5633}
5634
5635/**
5636 * Write handler for Receive Address registers.
5637 *
5638 * @param pThis The device state structure.
5639 * @param offset Register offset in memory-mapped frame.
5640 * @param index Register index in register array.
5641 * @param value The value to store.
5642 * @thread EMT
5643 */
5644static int e1kRegWriteRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5645{
5646 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5647 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5648
5649 return VINF_SUCCESS;
5650}
5651
5652/**
5653 * Read handler for Receive Address registers.
5654 *
5655 * @returns VBox status code.
5656 *
5657 * @param pThis The device state structure.
5658 * @param offset Register offset in memory-mapped frame.
5659 * @param index Register index in register array.
5660 * @thread EMT
5661 */
5662static int e1kRegReadRA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5663{
5664 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5665 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5666
5667 return VINF_SUCCESS;
5668}
5669
5670/**
5671 * Write handler for VLAN Filter Table Array registers.
5672 *
5673 * @param pThis The device state structure.
5674 * @param offset Register offset in memory-mapped frame.
5675 * @param index Register index in register array.
5676 * @param value The value to store.
5677 * @thread EMT
5678 */
5679static int e1kRegWriteVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5680{
5681 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5682 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5683
5684 return VINF_SUCCESS;
5685}
5686
5687/**
5688 * Read handler for VLAN Filter Table Array registers.
5689 *
5690 * @returns VBox status code.
5691 *
5692 * @param pThis The device state structure.
5693 * @param offset Register offset in memory-mapped frame.
5694 * @param index Register index in register array.
5695 * @thread EMT
5696 */
5697static int e1kRegReadVFTA(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5698{
5699 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5700 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5701
5702 return VINF_SUCCESS;
5703}
5704
5705/**
5706 * Read handler for unimplemented registers.
5707 *
5708 * Merely reports reads from unimplemented registers.
5709 *
5710 * @returns VBox status code.
5711 *
5712 * @param pThis The device state structure.
5713 * @param offset Register offset in memory-mapped frame.
5714 * @param index Register index in register array.
5715 * @thread EMT
5716 */
5717static int e1kRegReadUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5718{
5719 RT_NOREF3(pThis, offset, index);
5720 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5721 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5722 *pu32Value = 0;
5723
5724 return VINF_SUCCESS;
5725}
5726
5727/**
5728 * Default register read handler with automatic clear operation.
5729 *
5730 * Retrieves the value of register from register array in device state structure.
5731 * Then resets all bits.
5732 *
5733 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5734 * done in the caller.
5735 *
5736 * @returns VBox status code.
5737 *
5738 * @param pThis The device state structure.
5739 * @param offset Register offset in memory-mapped frame.
5740 * @param index Register index in register array.
5741 * @thread EMT
5742 */
5743static int e1kRegReadAutoClear(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5744{
5745 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5746 int rc = e1kRegReadDefault(pThis, offset, index, pu32Value);
5747 pThis->auRegs[index] = 0;
5748
5749 return rc;
5750}
5751
5752/**
5753 * Default register read handler.
5754 *
5755 * Retrieves the value of register from register array in device state structure.
5756 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5757 *
5758 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5759 * done in the caller.
5760 *
5761 * @returns VBox status code.
5762 *
5763 * @param pThis The device state structure.
5764 * @param offset Register offset in memory-mapped frame.
5765 * @param index Register index in register array.
5766 * @thread EMT
5767 */
5768static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5769{
5770 RT_NOREF_PV(offset);
5771
5772 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5773 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5774
5775 return VINF_SUCCESS;
5776}
5777
5778/**
5779 * Write handler for unimplemented registers.
5780 *
5781 * Merely reports writes to unimplemented registers.
5782 *
5783 * @param pThis The device state structure.
5784 * @param offset Register offset in memory-mapped frame.
5785 * @param index Register index in register array.
5786 * @param value The value to store.
5787 * @thread EMT
5788 */
5789
5790 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5791{
5792 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
5793
5794 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5795 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5796
5797 return VINF_SUCCESS;
5798}
5799
5800/**
5801 * Default register write handler.
5802 *
5803 * Stores the value to the register array in device state structure. Only bits
5804 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5805 *
5806 * @returns VBox status code.
5807 *
5808 * @param pThis The device state structure.
5809 * @param offset Register offset in memory-mapped frame.
5810 * @param index Register index in register array.
5811 * @param value The value to store.
5812 * @param mask Used to implement partial writes (8 and 16-bit).
5813 * @thread EMT
5814 */
5815
5816static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5817{
5818 RT_NOREF_PV(offset);
5819
5820 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5821 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5822 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5823
5824 return VINF_SUCCESS;
5825}
5826
5827/**
5828 * Search register table for matching register.
5829 *
5830 * @returns Index in the register table or -1 if not found.
5831 *
5832 * @param offReg Register offset in memory-mapped region.
5833 * @thread EMT
5834 */
5835static int e1kRegLookup(uint32_t offReg)
5836{
5837
5838#if 0
5839 int index;
5840
5841 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5842 {
5843 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5844 {
5845 return index;
5846 }
5847 }
5848#else
5849 int iStart = 0;
5850 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5851 for (;;)
5852 {
5853 int i = (iEnd - iStart) / 2 + iStart;
5854 uint32_t offCur = g_aE1kRegMap[i].offset;
5855 if (offReg < offCur)
5856 {
5857 if (i == iStart)
5858 break;
5859 iEnd = i;
5860 }
5861 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5862 {
5863 i++;
5864 if (i == iEnd)
5865 break;
5866 iStart = i;
5867 }
5868 else
5869 return i;
5870 Assert(iEnd > iStart);
5871 }
5872
5873 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5874 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5875 return i;
5876
5877# ifdef VBOX_STRICT
5878 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5879 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5880# endif
5881
5882#endif
5883
5884 return -1;
5885}
5886
5887/**
5888 * Handle unaligned register read operation.
5889 *
5890 * Looks up and calls appropriate handler.
5891 *
5892 * @returns VBox status code.
5893 *
5894 * @param pThis The device state structure.
5895 * @param offReg Register offset in memory-mapped frame.
5896 * @param pv Where to store the result.
5897 * @param cb Number of bytes to read.
5898 * @thread EMT
5899 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5900 * accesses we have to take care of that ourselves.
5901 */
5902static int e1kRegReadUnaligned(PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5903{
5904 uint32_t u32 = 0;
5905 uint32_t shift;
5906 int rc = VINF_SUCCESS;
5907 int index = e1kRegLookup(offReg);
5908#ifdef LOG_ENABLED
5909 char buf[9];
5910#endif
5911
5912 /*
5913 * From the spec:
5914 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
5915 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
5916 */
5917
5918 /*
5919 * To be able to read bytes and short word we convert them to properly
5920 * shifted 32-bit words and masks. The idea is to keep register-specific
5921 * handlers simple. Most accesses will be 32-bit anyway.
5922 */
5923 uint32_t mask;
5924 switch (cb)
5925 {
5926 case 4: mask = 0xFFFFFFFF; break;
5927 case 2: mask = 0x0000FFFF; break;
5928 case 1: mask = 0x000000FF; break;
5929 default:
5930 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
5931 "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
5932 }
5933 if (index != -1)
5934 {
5935 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
5936 if (g_aE1kRegMap[index].readable)
5937 {
5938 /* Make the mask correspond to the bits we are about to read. */
5939 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
5940 mask <<= shift;
5941 if (!mask)
5942 return PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
5943 /*
5944 * Read it. Pass the mask so the handler knows what has to be read.
5945 * Mask out irrelevant bits.
5946 */
5947 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
5948 if (RT_UNLIKELY(rc != VINF_SUCCESS))
5949 return rc;
5950 //pThis->fDelayInts = false;
5951 //pThis->iStatIntLost += pThis->iStatIntLostOne;
5952 //pThis->iStatIntLostOne = 0;
5953 rc = g_aE1kRegMap[index].pfnRead(pThis, offReg & 0xFFFFFFFC, index, &u32);
5954 u32 &= mask;
5955 //e1kCsLeave(pThis);
5956 E1kLog2(("%s At %08X read %s from %s (%s)\n",
5957 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5958 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
5959 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5960 /* Shift back the result. */
5961 u32 >>= shift;
5962 }
5963 else
5964 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
5965 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5966 if (IOM_SUCCESS(rc))
5967 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
5968 }
5969 else
5970 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
5971 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
5972
5973 memcpy(pv, &u32, cb);
5974 return rc;
5975}
5976
5977/**
5978 * Handle 4 byte aligned and sized read operation.
5979 *
5980 * Looks up and calls appropriate handler.
5981 *
5982 * @returns VBox status code.
5983 *
5984 * @param pThis The device state structure.
5985 * @param offReg Register offset in memory-mapped frame.
5986 * @param pu32 Where to store the result.
5987 * @thread EMT
5988 */
5989static int e1kRegReadAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
5990{
5991 Assert(!(offReg & 3));
5992
5993 /*
5994 * Lookup the register and check that it's readable.
5995 */
5996 int rc = VINF_SUCCESS;
5997 int idxReg = e1kRegLookup(offReg);
5998 if (RT_LIKELY(idxReg != -1))
5999 {
6000 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6001 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6002 {
6003 /*
6004 * Read it. Pass the mask so the handler knows what has to be read.
6005 * Mask out irrelevant bits.
6006 */
6007 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6008 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6009 // return rc;
6010 //pThis->fDelayInts = false;
6011 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6012 //pThis->iStatIntLostOne = 0;
6013 rc = g_aE1kRegMap[idxReg].pfnRead(pThis, offReg & 0xFFFFFFFC, idxReg, pu32);
6014 //e1kCsLeave(pThis);
6015 Log6(("%s At %08X read %08X from %s (%s)\n",
6016 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6017 if (IOM_SUCCESS(rc))
6018 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6019 }
6020 else
6021 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6022 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6023 }
6024 else
6025 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6026 return rc;
6027}
6028
6029/**
6030 * Handle 4 byte sized and aligned register write operation.
6031 *
6032 * Looks up and calls appropriate handler.
6033 *
6034 * @returns VBox status code.
6035 *
6036 * @param pThis The device state structure.
6037 * @param offReg Register offset in memory-mapped frame.
6038 * @param u32Value The value to write.
6039 * @thread EMT
6040 */
6041static int e1kRegWriteAlignedU32(PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6042{
6043 int rc = VINF_SUCCESS;
6044 int index = e1kRegLookup(offReg);
6045 if (RT_LIKELY(index != -1))
6046 {
6047 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6048 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6049 {
6050 /*
6051 * Write it. Pass the mask so the handler knows what has to be written.
6052 * Mask out irrelevant bits.
6053 */
6054 Log6(("%s At %08X write %08X to %s (%s)\n",
6055 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6056 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6057 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6058 // return rc;
6059 //pThis->fDelayInts = false;
6060 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6061 //pThis->iStatIntLostOne = 0;
6062 rc = g_aE1kRegMap[index].pfnWrite(pThis, offReg, index, u32Value);
6063 //e1kCsLeave(pThis);
6064 }
6065 else
6066 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6067 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6068 if (IOM_SUCCESS(rc))
6069 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6070 }
6071 else
6072 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6073 pThis->szPrf, offReg, u32Value));
6074 return rc;
6075}
6076
6077
6078/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6079
6080/**
6081 * @callback_method_impl{FNIOMMMIOREAD}
6082 */
6083PDMBOTHCBDECL(int) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
6084{
6085 RT_NOREF2(pvUser, cb);
6086 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
6087 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6088
6089 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
6090 Assert(offReg < E1K_MM_SIZE);
6091 Assert(cb == 4);
6092 Assert(!(GCPhysAddr & 3));
6093
6094 int rc = e1kRegReadAlignedU32(pThis, offReg, (uint32_t *)pv);
6095
6096 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6097 return rc;
6098}
6099
6100/**
6101 * @callback_method_impl{FNIOMMMIOWRITE}
6102 */
6103PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
6104{
6105 RT_NOREF2(pvUser, cb);
6106 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
6107 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6108
6109 uint32_t offReg = GCPhysAddr - pThis->addrMMReg;
6110 Assert(offReg < E1K_MM_SIZE);
6111 Assert(cb == 4);
6112 Assert(!(GCPhysAddr & 3));
6113
6114 int rc = e1kRegWriteAlignedU32(pThis, offReg, *(uint32_t const *)pv);
6115
6116 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6117 return rc;
6118}
6119
6120/**
6121 * @callback_method_impl{FNIOMIOPORTIN}
6122 */
6123PDMBOTHCBDECL(int) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t *pu32, unsigned cb)
6124{
6125 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
6126 int rc;
6127 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6128 RT_NOREF_PV(pvUser);
6129
6130 uPort -= pThis->IOPortBase;
6131 if (RT_LIKELY(cb == 4))
6132 switch (uPort)
6133 {
6134 case 0x00: /* IOADDR */
6135 *pu32 = pThis->uSelectedReg;
6136 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6137 rc = VINF_SUCCESS;
6138 break;
6139
6140 case 0x04: /* IODATA */
6141 if (!(pThis->uSelectedReg & 3))
6142 rc = e1kRegReadAlignedU32(pThis, pThis->uSelectedReg, pu32);
6143 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6144 rc = e1kRegReadUnaligned(pThis, pThis->uSelectedReg, pu32, cb);
6145 if (rc == VINF_IOM_R3_MMIO_READ)
6146 rc = VINF_IOM_R3_IOPORT_READ;
6147 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6148 break;
6149
6150 default:
6151 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, uPort));
6152 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6153 rc = VINF_SUCCESS;
6154 }
6155 else
6156 {
6157 E1kLog(("%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x", pThis->szPrf, uPort, cb));
6158 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb);
6159 }
6160 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6161 return rc;
6162}
6163
6164
6165/**
6166 * @callback_method_impl{FNIOMIOPORTOUT}
6167 */
6168PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT uPort, uint32_t u32, unsigned cb)
6169{
6170 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, PE1KSTATE);
6171 int rc;
6172 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6173 RT_NOREF_PV(pvUser);
6174
6175 E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
6176 if (RT_LIKELY(cb == 4))
6177 {
6178 uPort -= pThis->IOPortBase;
6179 switch (uPort)
6180 {
6181 case 0x00: /* IOADDR */
6182 pThis->uSelectedReg = u32;
6183 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6184 rc = VINF_SUCCESS;
6185 break;
6186
6187 case 0x04: /* IODATA */
6188 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6189 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6190 {
6191 rc = e1kRegWriteAlignedU32(pThis, pThis->uSelectedReg, u32);
6192 if (rc == VINF_IOM_R3_MMIO_WRITE)
6193 rc = VINF_IOM_R3_IOPORT_WRITE;
6194 }
6195 else
6196 rc = PDMDevHlpDBGFStop(pThis->CTX_SUFF(pDevIns), RT_SRC_POS,
6197 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6198 break;
6199
6200 default:
6201 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, uPort));
6202 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", uPort);
6203 }
6204 }
6205 else
6206 {
6207 E1kLog(("%s e1kIOPortOut: invalid op size: uPort=%RTiop cb=%08x\n", pThis->szPrf, uPort, cb));
6208 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: uPort=%RTiop cb=%#x\n", pThis->szPrf, uPort, cb);
6209 }
6210
6211 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6212 return rc;
6213}
6214
6215#ifdef IN_RING3
6216
6217/**
6218 * Dump complete device state to log.
6219 *
6220 * @param pThis Pointer to device state.
6221 */
6222static void e1kDumpState(PE1KSTATE pThis)
6223{
6224 RT_NOREF(pThis);
6225 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6226 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6227# ifdef E1K_INT_STATS
6228 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6229 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6230 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6231 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6232 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6233 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6234 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6235 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6236 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6237 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6238 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6239 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6240 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6241 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6242 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6243 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6244 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6245 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6246 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6247 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6248 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6249 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6250 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6251 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6252 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6253 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6254 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6255 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6256 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6257 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6258 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6259 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6260 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6261 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6262 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6263 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6264 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6265 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6266 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6267# endif /* E1K_INT_STATS */
6268}
6269
6270/**
6271 * @callback_method_impl{FNPCIIOREGIONMAP}
6272 */
6273static DECLCALLBACK(int) e1kMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
6274 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
6275{
6276 RT_NOREF(pPciDev, iRegion);
6277 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE *);
6278 int rc;
6279
6280 switch (enmType)
6281 {
6282 case PCI_ADDRESS_SPACE_IO:
6283 pThis->IOPortBase = (RTIOPORT)GCPhysAddress;
6284 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, cb, NULL /*pvUser*/,
6285 e1kIOPortOut, e1kIOPortIn, NULL, NULL, "E1000");
6286 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6287 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, cb, NIL_RTR0PTR /*pvUser*/,
6288 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6289 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6290 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, cb, NIL_RTRCPTR /*pvUser*/,
6291 "e1kIOPortOut", "e1kIOPortIn", NULL, NULL, "E1000");
6292 break;
6293
6294 case PCI_ADDRESS_SPACE_MEM:
6295 /*
6296 * From the spec:
6297 * For registers that should be accessed as 32-bit double words,
6298 * partial writes (less than a 32-bit double word) is ignored.
6299 * Partial reads return all 32 bits of data regardless of the
6300 * byte enables.
6301 */
6302#ifdef E1K_WITH_PREREG_MMIO
6303 pThis->addrMMReg = GCPhysAddress;
6304 if (GCPhysAddress == NIL_RTGCPHYS)
6305 rc = VINF_SUCCESS;
6306 else
6307 {
6308 Assert(!(GCPhysAddress & 7));
6309 rc = PDMDevHlpMMIOExMap(pDevIns, pPciDev, iRegion, GCPhysAddress);
6310 }
6311#else
6312 pThis->addrMMReg = GCPhysAddress; Assert(!(GCPhysAddress & 7));
6313 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
6314 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
6315 e1kMMIOWrite, e1kMMIORead, "E1000");
6316 if (pThis->fR0Enabled && RT_SUCCESS(rc))
6317 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
6318 "e1kMMIOWrite", "e1kMMIORead");
6319 if (pThis->fRCEnabled && RT_SUCCESS(rc))
6320 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
6321 "e1kMMIOWrite", "e1kMMIORead");
6322#endif
6323 break;
6324
6325 default:
6326 /* We should never get here */
6327 AssertMsgFailed(("Invalid PCI address space param in map callback"));
6328 rc = VERR_INTERNAL_ERROR;
6329 break;
6330 }
6331 return rc;
6332}
6333
6334
6335/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6336
6337/**
6338 * Check if the device can receive data now.
6339 * This must be called before the pfnRecieve() method is called.
6340 *
6341 * @returns Number of bytes the device can receive.
6342 * @param pInterface Pointer to the interface structure containing the called function pointer.
6343 * @thread EMT
6344 */
6345static int e1kCanReceive(PE1KSTATE pThis)
6346{
6347#ifndef E1K_WITH_RXD_CACHE
6348 size_t cb;
6349
6350 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6351 return VERR_NET_NO_BUFFER_SPACE;
6352
6353 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6354 {
6355 E1KRXDESC desc;
6356 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6357 &desc, sizeof(desc));
6358 if (desc.status.fDD)
6359 cb = 0;
6360 else
6361 cb = pThis->u16RxBSize;
6362 }
6363 else if (RDH < RDT)
6364 cb = (RDT - RDH) * pThis->u16RxBSize;
6365 else if (RDH > RDT)
6366 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6367 else
6368 {
6369 cb = 0;
6370 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6371 }
6372 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6373 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6374
6375 e1kCsRxLeave(pThis);
6376 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6377#else /* E1K_WITH_RXD_CACHE */
6378 int rc = VINF_SUCCESS;
6379
6380 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6381 return VERR_NET_NO_BUFFER_SPACE;
6382
6383 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6384 {
6385 E1KRXDESC desc;
6386 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH),
6387 &desc, sizeof(desc));
6388 if (desc.status.fDD)
6389 rc = VERR_NET_NO_BUFFER_SPACE;
6390 }
6391 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6392 {
6393 /* Cache is empty, so is the RX ring. */
6394 rc = VERR_NET_NO_BUFFER_SPACE;
6395 }
6396 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6397 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6398 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6399
6400 e1kCsRxLeave(pThis);
6401 return rc;
6402#endif /* E1K_WITH_RXD_CACHE */
6403}
6404
6405/**
6406 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6407 */
6408static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6409{
6410 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6411 int rc = e1kCanReceive(pThis);
6412
6413 if (RT_SUCCESS(rc))
6414 return VINF_SUCCESS;
6415 if (RT_UNLIKELY(cMillies == 0))
6416 return VERR_NET_NO_BUFFER_SPACE;
6417
6418 rc = VERR_INTERRUPTED;
6419 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6420 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6421 VMSTATE enmVMState;
6422 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pThis->CTX_SUFF(pDevIns))) == VMSTATE_RUNNING
6423 || enmVMState == VMSTATE_RUNNING_LS))
6424 {
6425 int rc2 = e1kCanReceive(pThis);
6426 if (RT_SUCCESS(rc2))
6427 {
6428 rc = VINF_SUCCESS;
6429 break;
6430 }
6431 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6432 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6433 RTSemEventWait(pThis->hEventMoreRxDescAvail, cMillies);
6434 }
6435 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6436 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6437
6438 return rc;
6439}
6440
6441
6442/**
6443 * Matches the packet addresses against Receive Address table. Looks for
6444 * exact matches only.
6445 *
6446 * @returns true if address matches.
6447 * @param pThis Pointer to the state structure.
6448 * @param pvBuf The ethernet packet.
6449 * @param cb Number of bytes available in the packet.
6450 * @thread EMT
6451 */
6452static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6453{
6454 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6455 {
6456 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6457
6458 /* Valid address? */
6459 if (ra->ctl & RA_CTL_AV)
6460 {
6461 Assert((ra->ctl & RA_CTL_AS) < 2);
6462 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6463 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6464 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6465 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6466 /*
6467 * Address Select:
6468 * 00b = Destination address
6469 * 01b = Source address
6470 * 10b = Reserved
6471 * 11b = Reserved
6472 * Since ethernet header is (DA, SA, len) we can use address
6473 * select as index.
6474 */
6475 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6476 ra->addr, sizeof(ra->addr)) == 0)
6477 return true;
6478 }
6479 }
6480
6481 return false;
6482}
6483
6484/**
6485 * Matches the packet addresses against Multicast Table Array.
6486 *
6487 * @remarks This is imperfect match since it matches not exact address but
6488 * a subset of addresses.
6489 *
6490 * @returns true if address matches.
6491 * @param pThis Pointer to the state structure.
6492 * @param pvBuf The ethernet packet.
6493 * @param cb Number of bytes available in the packet.
6494 * @thread EMT
6495 */
6496static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6497{
6498 /* Get bits 32..47 of destination address */
6499 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6500
6501 unsigned offset = GET_BITS(RCTL, MO);
6502 /*
6503 * offset means:
6504 * 00b = bits 36..47
6505 * 01b = bits 35..46
6506 * 10b = bits 34..45
6507 * 11b = bits 32..43
6508 */
6509 if (offset < 3)
6510 u16Bit = u16Bit >> (4 - offset);
6511 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6512}
6513
6514/**
6515 * Determines if the packet is to be delivered to upper layer.
6516 *
6517 * The following filters supported:
6518 * - Exact Unicast/Multicast
6519 * - Promiscuous Unicast/Multicast
6520 * - Multicast
6521 * - VLAN
6522 *
6523 * @returns true if packet is intended for this node.
6524 * @param pThis Pointer to the state structure.
6525 * @param pvBuf The ethernet packet.
6526 * @param cb Number of bytes available in the packet.
6527 * @param pStatus Bit field to store status bits.
6528 * @thread EMT
6529 */
6530static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6531{
6532 Assert(cb > 14);
6533 /* Assume that we fail to pass exact filter. */
6534 pStatus->fPIF = false;
6535 pStatus->fVP = false;
6536 /* Discard oversized packets */
6537 if (cb > E1K_MAX_RX_PKT_SIZE)
6538 {
6539 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6540 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6541 E1K_INC_CNT32(ROC);
6542 return false;
6543 }
6544 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6545 {
6546 /* When long packet reception is disabled packets over 1522 are discarded */
6547 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6548 pThis->szPrf, cb));
6549 E1K_INC_CNT32(ROC);
6550 return false;
6551 }
6552
6553 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6554 /* Compare TPID with VLAN Ether Type */
6555 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6556 {
6557 pStatus->fVP = true;
6558 /* Is VLAN filtering enabled? */
6559 if (RCTL & RCTL_VFE)
6560 {
6561 /* It is 802.1q packet indeed, let's filter by VID */
6562 if (RCTL & RCTL_CFIEN)
6563 {
6564 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6565 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6566 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6567 !!(RCTL & RCTL_CFI)));
6568 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6569 {
6570 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6571 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6572 return false;
6573 }
6574 }
6575 else
6576 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6577 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6578 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6579 {
6580 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6581 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6582 return false;
6583 }
6584 }
6585 }
6586 /* Broadcast filtering */
6587 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6588 return true;
6589 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6590 if (e1kIsMulticast(pvBuf))
6591 {
6592 /* Is multicast promiscuous enabled? */
6593 if (RCTL & RCTL_MPE)
6594 return true;
6595 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6596 /* Try perfect matches first */
6597 if (e1kPerfectMatch(pThis, pvBuf))
6598 {
6599 pStatus->fPIF = true;
6600 return true;
6601 }
6602 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6603 if (e1kImperfectMatch(pThis, pvBuf))
6604 return true;
6605 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6606 }
6607 else {
6608 /* Is unicast promiscuous enabled? */
6609 if (RCTL & RCTL_UPE)
6610 return true;
6611 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6612 if (e1kPerfectMatch(pThis, pvBuf))
6613 {
6614 pStatus->fPIF = true;
6615 return true;
6616 }
6617 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6618 }
6619 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6620 return false;
6621}
6622
6623/**
6624 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6625 */
6626static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6627{
6628 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkDown);
6629 int rc = VINF_SUCCESS;
6630
6631 /*
6632 * Drop packets if the VM is not running yet/anymore.
6633 */
6634 VMSTATE enmVMState = PDMDevHlpVMState(STATE_TO_DEVINS(pThis));
6635 if ( enmVMState != VMSTATE_RUNNING
6636 && enmVMState != VMSTATE_RUNNING_LS)
6637 {
6638 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6639 return VINF_SUCCESS;
6640 }
6641
6642 /* Discard incoming packets in locked state */
6643 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6644 {
6645 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6646 return VINF_SUCCESS;
6647 }
6648
6649 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6650
6651 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6652 // return VERR_PERMISSION_DENIED;
6653
6654 e1kPacketDump(pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6655
6656 /* Update stats */
6657 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6658 {
6659 E1K_INC_CNT32(TPR);
6660 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6661 e1kCsLeave(pThis);
6662 }
6663 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6664 E1KRXDST status;
6665 RT_ZERO(status);
6666 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6667 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6668 if (fPassed)
6669 {
6670 rc = e1kHandleRxPacket(pThis, pvBuf, cb, status);
6671 }
6672 //e1kCsLeave(pThis);
6673 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6674
6675 return rc;
6676}
6677
6678
6679/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6680
6681/**
6682 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6683 */
6684static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6685{
6686 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, ILeds);
6687 int rc = VERR_PDM_LUN_NOT_FOUND;
6688
6689 if (iLUN == 0)
6690 {
6691 *ppLed = &pThis->led;
6692 rc = VINF_SUCCESS;
6693 }
6694 return rc;
6695}
6696
6697
6698/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6699
6700/**
6701 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6702 */
6703static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6704{
6705 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6706 pThis->eeprom.getMac(pMac);
6707 return VINF_SUCCESS;
6708}
6709
6710/**
6711 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6712 */
6713static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6714{
6715 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6716 if (STATUS & STATUS_LU)
6717 return PDMNETWORKLINKSTATE_UP;
6718 return PDMNETWORKLINKSTATE_DOWN;
6719}
6720
6721/**
6722 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6723 */
6724static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6725{
6726 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, INetworkConfig);
6727
6728 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6729 switch (enmState)
6730 {
6731 case PDMNETWORKLINKSTATE_UP:
6732 pThis->fCableConnected = true;
6733 /* If link was down, bring it up after a while. */
6734 if (!(STATUS & STATUS_LU))
6735 e1kBringLinkUpDelayed(pThis);
6736 break;
6737 case PDMNETWORKLINKSTATE_DOWN:
6738 pThis->fCableConnected = false;
6739 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6740 * We might have to set the link state before the driver initializes us. */
6741 Phy::setLinkStatus(&pThis->phy, false);
6742 /* If link was up, bring it down. */
6743 if (STATUS & STATUS_LU)
6744 e1kR3LinkDown(pThis);
6745 break;
6746 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6747 /*
6748 * There is not much sense in bringing down the link if it has not come up yet.
6749 * If it is up though, we bring it down temporarely, then bring it up again.
6750 */
6751 if (STATUS & STATUS_LU)
6752 e1kR3LinkDownTemp(pThis);
6753 break;
6754 default:
6755 ;
6756 }
6757 return VINF_SUCCESS;
6758}
6759
6760
6761/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6762
6763/**
6764 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6765 */
6766static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6767{
6768 PE1KSTATE pThis = RT_FROM_MEMBER(pInterface, E1KSTATE, IBase);
6769 Assert(&pThis->IBase == pInterface);
6770
6771 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
6772 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThis->INetworkDown);
6773 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThis->INetworkConfig);
6774 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
6775 return NULL;
6776}
6777
6778
6779/* -=-=-=-=- Saved State -=-=-=-=- */
6780
6781/**
6782 * Saves the configuration.
6783 *
6784 * @param pThis The E1K state.
6785 * @param pSSM The handle to the saved state.
6786 */
6787static void e1kSaveConfig(PE1KSTATE pThis, PSSMHANDLE pSSM)
6788{
6789 SSMR3PutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6790 SSMR3PutU32(pSSM, pThis->eChip);
6791}
6792
6793/**
6794 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6795 */
6796static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6797{
6798 RT_NOREF(uPass);
6799 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6800 e1kSaveConfig(pThis, pSSM);
6801 return VINF_SSM_DONT_CALL_AGAIN;
6802}
6803
6804/**
6805 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6806 */
6807static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6808{
6809 RT_NOREF(pSSM);
6810 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6811
6812 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6813 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6814 return rc;
6815 e1kCsLeave(pThis);
6816 return VINF_SUCCESS;
6817#if 0
6818 /* 1) Prevent all threads from modifying the state and memory */
6819 //pThis->fLocked = true;
6820 /* 2) Cancel all timers */
6821#ifdef E1K_TX_DELAY
6822 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6823#endif /* E1K_TX_DELAY */
6824//#ifdef E1K_USE_TX_TIMERS
6825 if (pThis->fTidEnabled)
6826 {
6827 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6828#ifndef E1K_NO_TAD
6829 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6830#endif /* E1K_NO_TAD */
6831 }
6832//#endif /* E1K_USE_TX_TIMERS */
6833#ifdef E1K_USE_RX_TIMERS
6834 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6835 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6836#endif /* E1K_USE_RX_TIMERS */
6837 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6838 /* 3) Did I forget anything? */
6839 E1kLog(("%s Locked\n", pThis->szPrf));
6840 return VINF_SUCCESS;
6841#endif
6842}
6843
6844/**
6845 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6846 */
6847static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6848{
6849 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6850
6851 e1kSaveConfig(pThis, pSSM);
6852 pThis->eeprom.save(pSSM);
6853 e1kDumpState(pThis);
6854 SSMR3PutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6855 SSMR3PutBool(pSSM, pThis->fIntRaised);
6856 Phy::saveState(pSSM, &pThis->phy);
6857 SSMR3PutU32(pSSM, pThis->uSelectedReg);
6858 SSMR3PutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6859 SSMR3PutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6860 SSMR3PutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6861 SSMR3PutU64(pSSM, pThis->u64AckedAt);
6862 SSMR3PutU16(pSSM, pThis->u16RxBSize);
6863 //SSMR3PutBool(pSSM, pThis->fDelayInts);
6864 //SSMR3PutBool(pSSM, pThis->fIntMaskUsed);
6865 SSMR3PutU16(pSSM, pThis->u16TxPktLen);
6866/** @todo State wrt to the TSE buffer is incomplete, so little point in
6867 * saving this actually. */
6868 SSMR3PutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6869 SSMR3PutBool(pSSM, pThis->fIPcsum);
6870 SSMR3PutBool(pSSM, pThis->fTCPcsum);
6871 SSMR3PutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6872 SSMR3PutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6873 SSMR3PutBool(pSSM, pThis->fVTag);
6874 SSMR3PutU16(pSSM, pThis->u16VTagTCI);
6875#ifdef E1K_WITH_TXD_CACHE
6876#if 0
6877 SSMR3PutU8(pSSM, pThis->nTxDFetched);
6878 SSMR3PutMem(pSSM, pThis->aTxDescriptors,
6879 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6880#else
6881 /*
6882 * There is no point in storing TX descriptor cache entries as we can simply
6883 * fetch them again. Moreover, normally the cache is always empty when we
6884 * save the state. Store zero entries for compatibility.
6885 */
6886 SSMR3PutU8(pSSM, 0);
6887#endif
6888#endif /* E1K_WITH_TXD_CACHE */
6889/** @todo GSO requires some more state here. */
6890 E1kLog(("%s State has been saved\n", pThis->szPrf));
6891 return VINF_SUCCESS;
6892}
6893
6894#if 0
6895/**
6896 * @callback_method_impl{FNSSMDEVSAVEDONE}
6897 */
6898static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6899{
6900 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6901
6902 /* If VM is being powered off unlocking will result in assertions in PGM */
6903 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6904 pThis->fLocked = false;
6905 else
6906 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6907 E1kLog(("%s Unlocked\n", pThis->szPrf));
6908 return VINF_SUCCESS;
6909}
6910#endif
6911
6912/**
6913 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6914 */
6915static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6916{
6917 RT_NOREF(pSSM);
6918 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6919
6920 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6921 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6922 return rc;
6923 e1kCsLeave(pThis);
6924 return VINF_SUCCESS;
6925}
6926
6927/**
6928 * @callback_method_impl{FNSSMDEVLOADEXEC}
6929 */
6930static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6931{
6932 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
6933 int rc;
6934
6935 if ( uVersion != E1K_SAVEDSTATE_VERSION
6936#ifdef E1K_WITH_TXD_CACHE
6937 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6938#endif /* E1K_WITH_TXD_CACHE */
6939 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6940 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6941 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6942
6943 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6944 || uPass != SSM_PASS_FINAL)
6945 {
6946 /* config checks */
6947 RTMAC macConfigured;
6948 rc = SSMR3GetMem(pSSM, &macConfigured, sizeof(macConfigured));
6949 AssertRCReturn(rc, rc);
6950 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6951 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6952 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6953
6954 E1KCHIP eChip;
6955 rc = SSMR3GetU32(pSSM, &eChip);
6956 AssertRCReturn(rc, rc);
6957 if (eChip != pThis->eChip)
6958 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6959 }
6960
6961 if (uPass == SSM_PASS_FINAL)
6962 {
6963 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6964 {
6965 rc = pThis->eeprom.load(pSSM);
6966 AssertRCReturn(rc, rc);
6967 }
6968 /* the state */
6969 SSMR3GetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
6970 SSMR3GetBool(pSSM, &pThis->fIntRaised);
6971 /** @todo PHY could be made a separate device with its own versioning */
6972 Phy::loadState(pSSM, &pThis->phy);
6973 SSMR3GetU32(pSSM, &pThis->uSelectedReg);
6974 SSMR3GetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
6975 SSMR3GetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6976 SSMR3GetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
6977 SSMR3GetU64(pSSM, &pThis->u64AckedAt);
6978 SSMR3GetU16(pSSM, &pThis->u16RxBSize);
6979 //SSMR3GetBool(pSSM, pThis->fDelayInts);
6980 //SSMR3GetBool(pSSM, pThis->fIntMaskUsed);
6981 SSMR3GetU16(pSSM, &pThis->u16TxPktLen);
6982 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
6983 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
6984 SSMR3GetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
6985 SSMR3GetBool(pSSM, &pThis->fIPcsum);
6986 SSMR3GetBool(pSSM, &pThis->fTCPcsum);
6987 SSMR3GetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6988 rc = SSMR3GetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6989 AssertRCReturn(rc, rc);
6990 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
6991 {
6992 SSMR3GetBool(pSSM, &pThis->fVTag);
6993 rc = SSMR3GetU16(pSSM, &pThis->u16VTagTCI);
6994 AssertRCReturn(rc, rc);
6995 }
6996 else
6997 {
6998 pThis->fVTag = false;
6999 pThis->u16VTagTCI = 0;
7000 }
7001#ifdef E1K_WITH_TXD_CACHE
7002 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7003 {
7004 rc = SSMR3GetU8(pSSM, &pThis->nTxDFetched);
7005 AssertRCReturn(rc, rc);
7006 if (pThis->nTxDFetched)
7007 SSMR3GetMem(pSSM, pThis->aTxDescriptors,
7008 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7009 }
7010 else
7011 pThis->nTxDFetched = 0;
7012 /*
7013 * @todo: Perhaps we should not store TXD cache as the entries can be
7014 * simply fetched again from guest's memory. Or can't they?
7015 */
7016#endif /* E1K_WITH_TXD_CACHE */
7017#ifdef E1K_WITH_RXD_CACHE
7018 /*
7019 * There is no point in storing the RX descriptor cache in the saved
7020 * state, we just need to make sure it is empty.
7021 */
7022 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7023#endif /* E1K_WITH_RXD_CACHE */
7024 /* derived state */
7025 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7026
7027 E1kLog(("%s State has been restored\n", pThis->szPrf));
7028 e1kDumpState(pThis);
7029 }
7030 return VINF_SUCCESS;
7031}
7032
7033/**
7034 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7035 */
7036static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7037{
7038 RT_NOREF(pSSM);
7039 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7040
7041 /* Update promiscuous mode */
7042 if (pThis->pDrvR3)
7043 pThis->pDrvR3->pfnSetPromiscuousMode(pThis->pDrvR3,
7044 !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7045
7046 /*
7047 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7048 * passed to us. We go through all this stuff if the link was up and we
7049 * wasn't teleported.
7050 */
7051 if ( (STATUS & STATUS_LU)
7052 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7053 && pThis->cMsLinkUpDelay)
7054 {
7055 e1kR3LinkDownTemp(pThis);
7056 }
7057 return VINF_SUCCESS;
7058}
7059
7060
7061
7062/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7063
7064/**
7065 * @callback_method_impl{FNRTSTRFORMATTYPE}
7066 */
7067static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7068 void *pvArgOutput,
7069 const char *pszType,
7070 void const *pvValue,
7071 int cchWidth,
7072 int cchPrecision,
7073 unsigned fFlags,
7074 void *pvUser)
7075{
7076 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7077 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7078 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7079 if (!pDesc)
7080 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7081
7082 size_t cbPrintf = 0;
7083 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7084 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7085 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7086 pDesc->status.fPIF ? "PIF" : "pif",
7087 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7088 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7089 pDesc->status.fVP ? "VP" : "vp",
7090 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7091 pDesc->status.fEOP ? "EOP" : "eop",
7092 pDesc->status.fDD ? "DD" : "dd",
7093 pDesc->status.fRXE ? "RXE" : "rxe",
7094 pDesc->status.fIPE ? "IPE" : "ipe",
7095 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7096 pDesc->status.fCE ? "CE" : "ce",
7097 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7098 E1K_SPEC_VLAN(pDesc->status.u16Special),
7099 E1K_SPEC_PRI(pDesc->status.u16Special));
7100 return cbPrintf;
7101}
7102
7103/**
7104 * @callback_method_impl{FNRTSTRFORMATTYPE}
7105 */
7106static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7107 void *pvArgOutput,
7108 const char *pszType,
7109 void const *pvValue,
7110 int cchWidth,
7111 int cchPrecision,
7112 unsigned fFlags,
7113 void *pvUser)
7114{
7115 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7116 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7117 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7118 if (!pDesc)
7119 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7120
7121 size_t cbPrintf = 0;
7122 switch (e1kGetDescType(pDesc))
7123 {
7124 case E1K_DTYP_CONTEXT:
7125 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7126 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7127 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7128 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7129 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7130 pDesc->context.dw2.fIDE ? " IDE":"",
7131 pDesc->context.dw2.fRS ? " RS" :"",
7132 pDesc->context.dw2.fTSE ? " TSE":"",
7133 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7134 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7135 pDesc->context.dw2.u20PAYLEN,
7136 pDesc->context.dw3.u8HDRLEN,
7137 pDesc->context.dw3.u16MSS,
7138 pDesc->context.dw3.fDD?"DD":"");
7139 break;
7140 case E1K_DTYP_DATA:
7141 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7142 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7143 pDesc->data.u64BufAddr,
7144 pDesc->data.cmd.u20DTALEN,
7145 pDesc->data.cmd.fIDE ? " IDE" :"",
7146 pDesc->data.cmd.fVLE ? " VLE" :"",
7147 pDesc->data.cmd.fRPS ? " RPS" :"",
7148 pDesc->data.cmd.fRS ? " RS" :"",
7149 pDesc->data.cmd.fTSE ? " TSE" :"",
7150 pDesc->data.cmd.fIFCS? " IFCS":"",
7151 pDesc->data.cmd.fEOP ? " EOP" :"",
7152 pDesc->data.dw3.fDD ? " DD" :"",
7153 pDesc->data.dw3.fEC ? " EC" :"",
7154 pDesc->data.dw3.fLC ? " LC" :"",
7155 pDesc->data.dw3.fTXSM? " TXSM":"",
7156 pDesc->data.dw3.fIXSM? " IXSM":"",
7157 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7158 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7159 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7160 break;
7161 case E1K_DTYP_LEGACY:
7162 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7163 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7164 pDesc->data.u64BufAddr,
7165 pDesc->legacy.cmd.u16Length,
7166 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7167 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7168 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7169 pDesc->legacy.cmd.fRS ? " RS" :"",
7170 pDesc->legacy.cmd.fIC ? " IC" :"",
7171 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7172 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7173 pDesc->legacy.dw3.fDD ? " DD" :"",
7174 pDesc->legacy.dw3.fEC ? " EC" :"",
7175 pDesc->legacy.dw3.fLC ? " LC" :"",
7176 pDesc->legacy.cmd.u8CSO,
7177 pDesc->legacy.dw3.u8CSS,
7178 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7179 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7180 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7181 break;
7182 default:
7183 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7184 break;
7185 }
7186
7187 return cbPrintf;
7188}
7189
7190/** Initializes debug helpers (logging format types). */
7191static int e1kInitDebugHelpers(void)
7192{
7193 int rc = VINF_SUCCESS;
7194 static bool s_fHelpersRegistered = false;
7195 if (!s_fHelpersRegistered)
7196 {
7197 s_fHelpersRegistered = true;
7198 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7199 AssertRCReturn(rc, rc);
7200 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7201 AssertRCReturn(rc, rc);
7202 }
7203 return rc;
7204}
7205
7206/**
7207 * Status info callback.
7208 *
7209 * @param pDevIns The device instance.
7210 * @param pHlp The output helpers.
7211 * @param pszArgs The arguments.
7212 */
7213static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7214{
7215 RT_NOREF(pszArgs);
7216 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7217 unsigned i;
7218 // bool fRcvRing = false;
7219 // bool fXmtRing = false;
7220
7221 /*
7222 * Parse args.
7223 if (pszArgs)
7224 {
7225 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7226 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7227 }
7228 */
7229
7230 /*
7231 * Show info.
7232 */
7233 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%RTiop mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7234 pDevIns->iInstance, pThis->IOPortBase, pThis->addrMMReg,
7235 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7236 pThis->fRCEnabled ? " GC" : "", pThis->fR0Enabled ? " R0" : "");
7237
7238 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7239
7240 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7241 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7242
7243 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7244 {
7245 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7246 if (ra->ctl & RA_CTL_AV)
7247 {
7248 const char *pcszTmp;
7249 switch (ra->ctl & RA_CTL_AS)
7250 {
7251 case 0: pcszTmp = "DST"; break;
7252 case 1: pcszTmp = "SRC"; break;
7253 default: pcszTmp = "reserved";
7254 }
7255 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7256 }
7257 }
7258 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7259 uint32_t rdh = RDH;
7260 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7261 for (i = 0; i < cDescs; ++i)
7262 {
7263 E1KRXDESC desc;
7264 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7265 &desc, sizeof(desc));
7266 if (i == rdh)
7267 pHlp->pfnPrintf(pHlp, ">>> ");
7268 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7269 }
7270#ifdef E1K_WITH_RXD_CACHE
7271 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7272 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7273 if (rdh > pThis->iRxDCurrent)
7274 rdh -= pThis->iRxDCurrent;
7275 else
7276 rdh = cDescs + rdh - pThis->iRxDCurrent;
7277 for (i = 0; i < pThis->nRxDFetched; ++i)
7278 {
7279 if (i == pThis->iRxDCurrent)
7280 pHlp->pfnPrintf(pHlp, ">>> ");
7281 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7282 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7283 &pThis->aRxDescriptors[i]);
7284 }
7285#endif /* E1K_WITH_RXD_CACHE */
7286
7287 cDescs = TDLEN / sizeof(E1KTXDESC);
7288 uint32_t tdh = TDH;
7289 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7290 for (i = 0; i < cDescs; ++i)
7291 {
7292 E1KTXDESC desc;
7293 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7294 &desc, sizeof(desc));
7295 if (i == tdh)
7296 pHlp->pfnPrintf(pHlp, ">>> ");
7297 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7298 }
7299#ifdef E1K_WITH_TXD_CACHE
7300 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7301 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7302 if (tdh > pThis->iTxDCurrent)
7303 tdh -= pThis->iTxDCurrent;
7304 else
7305 tdh = cDescs + tdh - pThis->iTxDCurrent;
7306 for (i = 0; i < pThis->nTxDFetched; ++i)
7307 {
7308 if (i == pThis->iTxDCurrent)
7309 pHlp->pfnPrintf(pHlp, ">>> ");
7310 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7311 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7312 &pThis->aTxDescriptors[i]);
7313 }
7314#endif /* E1K_WITH_TXD_CACHE */
7315
7316
7317#ifdef E1K_INT_STATS
7318 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7319 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7320 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7321 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7322 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7323 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7324 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7325 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7326 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7327 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7328 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7329 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7330 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7331 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7332 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7333 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7334 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7335 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7336 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7337 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7338 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7339 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7340 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7341 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7342 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7343 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7344 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7345 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7346 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7347 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7348 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7349 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7350 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7351 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7352 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7353 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7354 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7355 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7356#endif /* E1K_INT_STATS */
7357
7358 e1kCsLeave(pThis);
7359}
7360
7361
7362
7363/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7364
7365/**
7366 * Detach notification.
7367 *
7368 * One port on the network card has been disconnected from the network.
7369 *
7370 * @param pDevIns The device instance.
7371 * @param iLUN The logical unit which is being detached.
7372 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7373 */
7374static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7375{
7376 RT_NOREF(fFlags);
7377 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7378 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7379
7380 AssertLogRelReturnVoid(iLUN == 0);
7381
7382 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7383
7384 /** @todo r=pritesh still need to check if i missed
7385 * to clean something in this function
7386 */
7387
7388 /*
7389 * Zero some important members.
7390 */
7391 pThis->pDrvBase = NULL;
7392 pThis->pDrvR3 = NULL;
7393 pThis->pDrvR0 = NIL_RTR0PTR;
7394 pThis->pDrvRC = NIL_RTRCPTR;
7395
7396 PDMCritSectLeave(&pThis->cs);
7397}
7398
7399/**
7400 * Attach the Network attachment.
7401 *
7402 * One port on the network card has been connected to a network.
7403 *
7404 * @returns VBox status code.
7405 * @param pDevIns The device instance.
7406 * @param iLUN The logical unit which is being attached.
7407 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7408 *
7409 * @remarks This code path is not used during construction.
7410 */
7411static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7412{
7413 RT_NOREF(fFlags);
7414 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7415 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7416
7417 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7418
7419 PDMCritSectEnter(&pThis->cs, VERR_SEM_BUSY);
7420
7421 /*
7422 * Attach the driver.
7423 */
7424 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7425 if (RT_SUCCESS(rc))
7426 {
7427 if (rc == VINF_NAT_DNS)
7428 {
7429#ifdef RT_OS_LINUX
7430 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7431 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7432#else
7433 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7434 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7435#endif
7436 }
7437 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7438 AssertMsgStmt(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7439 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7440 if (RT_SUCCESS(rc))
7441 {
7442 PPDMIBASER0 pBaseR0 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0);
7443 pThis->pDrvR0 = pBaseR0 ? pBaseR0->pfnQueryInterface(pBaseR0, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7444
7445 PPDMIBASERC pBaseRC = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC);
7446 pThis->pDrvRC = pBaseRC ? pBaseRC->pfnQueryInterface(pBaseRC, PDMINETWORKUP_IID) : NIL_RTR0PTR;
7447 }
7448 }
7449 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7450 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7451 {
7452 /* This should never happen because this function is not called
7453 * if there is no driver to attach! */
7454 Log(("%s No attached driver!\n", pThis->szPrf));
7455 }
7456
7457 /*
7458 * Temporary set the link down if it was up so that the guest
7459 * will know that we have change the configuration of the
7460 * network card
7461 */
7462 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7463 e1kR3LinkDownTemp(pThis);
7464
7465 PDMCritSectLeave(&pThis->cs);
7466 return rc;
7467
7468}
7469
7470/**
7471 * @copydoc FNPDMDEVPOWEROFF
7472 */
7473static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7474{
7475 /* Poke thread waiting for buffer space. */
7476 e1kWakeupReceive(pDevIns);
7477}
7478
7479/**
7480 * @copydoc FNPDMDEVRESET
7481 */
7482static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7483{
7484 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7485#ifdef E1K_TX_DELAY
7486 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7487#endif /* E1K_TX_DELAY */
7488 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7489 e1kCancelTimer(pThis, pThis->CTX_SUFF(pLUTimer));
7490 e1kXmitFreeBuf(pThis);
7491 pThis->u16TxPktLen = 0;
7492 pThis->fIPcsum = false;
7493 pThis->fTCPcsum = false;
7494 pThis->fIntMaskUsed = false;
7495 pThis->fDelayInts = false;
7496 pThis->fLocked = false;
7497 pThis->u64AckedAt = 0;
7498 e1kHardReset(pThis);
7499}
7500
7501/**
7502 * @copydoc FNPDMDEVSUSPEND
7503 */
7504static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7505{
7506 /* Poke thread waiting for buffer space. */
7507 e1kWakeupReceive(pDevIns);
7508}
7509
7510/**
7511 * Device relocation callback.
7512 *
7513 * When this callback is called the device instance data, and if the
7514 * device have a GC component, is being relocated, or/and the selectors
7515 * have been changed. The device must use the chance to perform the
7516 * necessary pointer relocations and data updates.
7517 *
7518 * Before the GC code is executed the first time, this function will be
7519 * called with a 0 delta so GC pointer calculations can be one in one place.
7520 *
7521 * @param pDevIns Pointer to the device instance.
7522 * @param offDelta The relocation delta relative to the old location.
7523 *
7524 * @remark A relocation CANNOT fail.
7525 */
7526static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7527{
7528 RT_NOREF(offDelta);
7529 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7530 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7531 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7532 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7533#ifdef E1K_USE_RX_TIMERS
7534 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7535 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7536#endif /* E1K_USE_RX_TIMERS */
7537//#ifdef E1K_USE_TX_TIMERS
7538 if (pThis->fTidEnabled)
7539 {
7540 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7541# ifndef E1K_NO_TAD
7542 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7543# endif /* E1K_NO_TAD */
7544 }
7545//#endif /* E1K_USE_TX_TIMERS */
7546#ifdef E1K_TX_DELAY
7547 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7548#endif /* E1K_TX_DELAY */
7549 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7550 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7551}
7552
7553/**
7554 * Destruct a device instance.
7555 *
7556 * We need to free non-VM resources only.
7557 *
7558 * @returns VBox status code.
7559 * @param pDevIns The device instance data.
7560 * @thread EMT
7561 */
7562static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7563{
7564 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7565 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7566
7567 e1kDumpState(pThis);
7568 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7569 if (PDMCritSectIsInitialized(&pThis->cs))
7570 {
7571 if (pThis->hEventMoreRxDescAvail != NIL_RTSEMEVENT)
7572 {
7573 RTSemEventSignal(pThis->hEventMoreRxDescAvail);
7574 RTSemEventDestroy(pThis->hEventMoreRxDescAvail);
7575 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7576 }
7577#ifdef E1K_WITH_TX_CS
7578 PDMR3CritSectDelete(&pThis->csTx);
7579#endif /* E1K_WITH_TX_CS */
7580 PDMR3CritSectDelete(&pThis->csRx);
7581 PDMR3CritSectDelete(&pThis->cs);
7582 }
7583 return VINF_SUCCESS;
7584}
7585
7586
7587/**
7588 * Set PCI configuration space registers.
7589 *
7590 * @param pci Reference to PCI device structure.
7591 * @thread EMT
7592 */
7593static DECLCALLBACK(void) e1kConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7594{
7595 Assert(eChip < RT_ELEMENTS(g_aChips));
7596 /* Configure PCI Device, assume 32-bit mode ******************************/
7597 PCIDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7598 PCIDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7599 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7600 PCIDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7601
7602 PCIDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7603 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7604 PCIDevSetWord( pPciDev, VBOX_PCI_STATUS,
7605 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7606 /* Stepping A2 */
7607 PCIDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7608 /* Ethernet adapter */
7609 PCIDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7610 PCIDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7611 /* normal single function Ethernet controller */
7612 PCIDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7613 /* Memory Register Base Address */
7614 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7615 /* Memory Flash Base Address */
7616 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7617 /* IO Register Base Address */
7618 PCIDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7619 /* Expansion ROM Base Address */
7620 PCIDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7621 /* Capabilities Pointer */
7622 PCIDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7623 /* Interrupt Pin: INTA# */
7624 PCIDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7625 /* Max_Lat/Min_Gnt: very high priority and time slice */
7626 PCIDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7627 PCIDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7628
7629 /* PCI Power Management Registers ****************************************/
7630 /* Capability ID: PCI Power Management Registers */
7631 PCIDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7632 /* Next Item Pointer: PCI-X */
7633 PCIDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7634 /* Power Management Capabilities: PM disabled, DSI */
7635 PCIDevSetWord( pPciDev, 0xDC + 2,
7636 0x0002 | VBOX_PCI_PM_CAP_DSI);
7637 /* Power Management Control / Status Register: PM disabled */
7638 PCIDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7639 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7640 PCIDevSetByte( pPciDev, 0xDC + 6, 0x00);
7641 /* Data Register: PM disabled, always 0 */
7642 PCIDevSetByte( pPciDev, 0xDC + 7, 0x00);
7643
7644 /* PCI-X Configuration Registers *****************************************/
7645 /* Capability ID: PCI-X Configuration Registers */
7646 PCIDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7647#ifdef E1K_WITH_MSI
7648 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7649#else
7650 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7651 PCIDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7652#endif
7653 /* PCI-X Command: Enable Relaxed Ordering */
7654 PCIDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7655 /* PCI-X Status: 32-bit, 66MHz*/
7656 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7657 PCIDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7658}
7659
7660/**
7661 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7662 */
7663static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7664{
7665 PE1KSTATE pThis = PDMINS_2_DATA(pDevIns, E1KSTATE*);
7666 int rc;
7667 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7668
7669 /*
7670 * Initialize the instance data (state).
7671 * Note! Caller has initialized it to ZERO already.
7672 */
7673 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7674 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7675 pThis->hEventMoreRxDescAvail = NIL_RTSEMEVENT;
7676 pThis->pDevInsR3 = pDevIns;
7677 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
7678 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7679 pThis->u16TxPktLen = 0;
7680 pThis->fIPcsum = false;
7681 pThis->fTCPcsum = false;
7682 pThis->fIntMaskUsed = false;
7683 pThis->fDelayInts = false;
7684 pThis->fLocked = false;
7685 pThis->u64AckedAt = 0;
7686 pThis->led.u32Magic = PDMLED_MAGIC;
7687 pThis->u32PktNo = 1;
7688
7689 /* Interfaces */
7690 pThis->IBase.pfnQueryInterface = e1kR3QueryInterface;
7691
7692 pThis->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7693 pThis->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7694 pThis->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7695
7696 pThis->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7697
7698 pThis->INetworkConfig.pfnGetMac = e1kR3GetMac;
7699 pThis->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7700 pThis->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7701
7702 /*
7703 * Internal validations.
7704 */
7705 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7706 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7707 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7708 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7709 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7710 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7711 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7712 VERR_INTERNAL_ERROR_4);
7713
7714 /*
7715 * Validate configuration.
7716 */
7717 if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "AdapterType\0"
7718 "LineSpeed\0" "GCEnabled\0" "R0Enabled\0"
7719 "ItrEnabled\0" "ItrRxEnabled\0"
7720 "EthernetCRC\0" "GSOEnabled\0" "LinkUpDelay\0"))
7721 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
7722 N_("Invalid configuration for E1000 device"));
7723
7724 /** @todo LineSpeed unused! */
7725
7726 /* Get config params */
7727 rc = CFGMR3QueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7728 if (RT_FAILURE(rc))
7729 return PDMDEV_SET_ERROR(pDevIns, rc,
7730 N_("Configuration error: Failed to get MAC address"));
7731 rc = CFGMR3QueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7732 if (RT_FAILURE(rc))
7733 return PDMDEV_SET_ERROR(pDevIns, rc,
7734 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7735 rc = CFGMR3QueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7736 if (RT_FAILURE(rc))
7737 return PDMDEV_SET_ERROR(pDevIns, rc,
7738 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7739 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7740 rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &pThis->fRCEnabled, true);
7741 if (RT_FAILURE(rc))
7742 return PDMDEV_SET_ERROR(pDevIns, rc,
7743 N_("Configuration error: Failed to get the value of 'GCEnabled'"));
7744
7745 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, true);
7746 if (RT_FAILURE(rc))
7747 return PDMDEV_SET_ERROR(pDevIns, rc,
7748 N_("Configuration error: Failed to get the value of 'R0Enabled'"));
7749
7750 rc = CFGMR3QueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7751 if (RT_FAILURE(rc))
7752 return PDMDEV_SET_ERROR(pDevIns, rc,
7753 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7754
7755 rc = CFGMR3QueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7756 if (RT_FAILURE(rc))
7757 return PDMDEV_SET_ERROR(pDevIns, rc,
7758 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7759
7760 rc = CFGMR3QueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7761 if (RT_FAILURE(rc))
7762 return PDMDEV_SET_ERROR(pDevIns, rc,
7763 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7764
7765 rc = CFGMR3QueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7766 if (RT_FAILURE(rc))
7767 return PDMDEV_SET_ERROR(pDevIns, rc,
7768 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7769
7770 rc = CFGMR3QueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7771 if (RT_FAILURE(rc))
7772 return PDMDEV_SET_ERROR(pDevIns, rc,
7773 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7774
7775 rc = CFGMR3QueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7776 if (RT_FAILURE(rc))
7777 return PDMDEV_SET_ERROR(pDevIns, rc,
7778 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7779 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7780 if (pThis->cMsLinkUpDelay > 5000)
7781 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7782 else if (pThis->cMsLinkUpDelay == 0)
7783 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7784
7785 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s GC=%s\n", pThis->szPrf,
7786 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7787 pThis->fEthernetCRC ? "on" : "off",
7788 pThis->fGSOEnabled ? "enabled" : "disabled",
7789 pThis->fItrEnabled ? "enabled" : "disabled",
7790 pThis->fItrRxEnabled ? "enabled" : "disabled",
7791 pThis->fTidEnabled ? "enabled" : "disabled",
7792 pThis->fR0Enabled ? "enabled" : "disabled",
7793 pThis->fRCEnabled ? "enabled" : "disabled"));
7794
7795 /* Initialize the EEPROM. */
7796 pThis->eeprom.init(pThis->macConfigured);
7797
7798 /* Initialize internal PHY. */
7799 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7800
7801 /* Initialize critical sections. We do our own locking. */
7802 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7803 AssertRCReturn(rc, rc);
7804
7805 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7806 if (RT_FAILURE(rc))
7807 return rc;
7808 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7809 if (RT_FAILURE(rc))
7810 return rc;
7811#ifdef E1K_WITH_TX_CS
7812 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7813 if (RT_FAILURE(rc))
7814 return rc;
7815#endif /* E1K_WITH_TX_CS */
7816
7817 /* Saved state registration. */
7818 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7819 NULL, e1kLiveExec, NULL,
7820 e1kSavePrep, e1kSaveExec, NULL,
7821 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7822 if (RT_FAILURE(rc))
7823 return rc;
7824
7825 /* Set PCI config registers and register ourselves with the PCI bus. */
7826 e1kConfigurePciDev(&pThis->pciDevice, pThis->eChip);
7827 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->pciDevice);
7828 if (RT_FAILURE(rc))
7829 return rc;
7830
7831#ifdef E1K_WITH_MSI
7832 PDMMSIREG MsiReg;
7833 RT_ZERO(MsiReg);
7834 MsiReg.cMsiVectors = 1;
7835 MsiReg.iMsiCapOffset = 0x80;
7836 MsiReg.iMsiNextOffset = 0x0;
7837 MsiReg.fMsi64bit = false;
7838 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7839 AssertRCReturn(rc, rc);
7840#endif
7841
7842
7843 /* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
7844 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, e1kMap);
7845 if (RT_FAILURE(rc))
7846 return rc;
7847#ifdef E1K_WITH_PREREG_MMIO
7848 rc = PDMDevHlpMMIOExPreRegister(pDevIns, 0, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD, "E1000",
7849 NULL /*pvUserR3*/, e1kMMIOWrite, e1kMMIORead, NULL /*pfnFillR3*/,
7850 NIL_RTR0PTR /*pvUserR0*/, pThis->fR0Enabled ? "e1kMMIOWrite" : NULL,
7851 pThis->fR0Enabled ? "e1kMMIORead" : NULL, NULL /*pszFillR0*/,
7852 NIL_RTRCPTR /*pvUserRC*/, pThis->fRCEnabled ? "e1kMMIOWrite" : NULL,
7853 pThis->fRCEnabled ? "e1kMMIORead" : NULL, NULL /*pszFillRC*/);
7854 AssertLogRelRCReturn(rc, rc);
7855#endif
7856 /* Map our registers to IO space (region 2, see e1kConfigurePCI) */
7857 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2, E1K_IOPORT_SIZE, PCI_ADDRESS_SPACE_IO, e1kMap);
7858 if (RT_FAILURE(rc))
7859 return rc;
7860
7861 /* Create transmit queue */
7862 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7863 e1kTxQueueConsumer, true, "E1000-Xmit", &pThis->pTxQueueR3);
7864 if (RT_FAILURE(rc))
7865 return rc;
7866 pThis->pTxQueueR0 = PDMQueueR0Ptr(pThis->pTxQueueR3);
7867 pThis->pTxQueueRC = PDMQueueRCPtr(pThis->pTxQueueR3);
7868
7869 /* Create the RX notifier signaller. */
7870 rc = PDMDevHlpQueueCreate(pDevIns, sizeof(PDMQUEUEITEMCORE), 1, 0,
7871 e1kCanRxQueueConsumer, true, "E1000-Rcv", &pThis->pCanRxQueueR3);
7872 if (RT_FAILURE(rc))
7873 return rc;
7874 pThis->pCanRxQueueR0 = PDMQueueR0Ptr(pThis->pCanRxQueueR3);
7875 pThis->pCanRxQueueRC = PDMQueueRCPtr(pThis->pCanRxQueueR3);
7876
7877#ifdef E1K_TX_DELAY
7878 /* Create Transmit Delay Timer */
7879 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxDelayTimer, pThis,
7880 TMTIMER_FLAGS_NO_CRIT_SECT,
7881 "E1000 Transmit Delay Timer", &pThis->pTXDTimerR3);
7882 if (RT_FAILURE(rc))
7883 return rc;
7884 pThis->pTXDTimerR0 = TMTimerR0Ptr(pThis->pTXDTimerR3);
7885 pThis->pTXDTimerRC = TMTimerRCPtr(pThis->pTXDTimerR3);
7886 TMR3TimerSetCritSect(pThis->pTXDTimerR3, &pThis->csTx);
7887#endif /* E1K_TX_DELAY */
7888
7889//#ifdef E1K_USE_TX_TIMERS
7890 if (pThis->fTidEnabled)
7891 {
7892 /* Create Transmit Interrupt Delay Timer */
7893 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxIntDelayTimer, pThis,
7894 TMTIMER_FLAGS_NO_CRIT_SECT,
7895 "E1000 Transmit Interrupt Delay Timer", &pThis->pTIDTimerR3);
7896 if (RT_FAILURE(rc))
7897 return rc;
7898 pThis->pTIDTimerR0 = TMTimerR0Ptr(pThis->pTIDTimerR3);
7899 pThis->pTIDTimerRC = TMTimerRCPtr(pThis->pTIDTimerR3);
7900
7901# ifndef E1K_NO_TAD
7902 /* Create Transmit Absolute Delay Timer */
7903 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kTxAbsDelayTimer, pThis,
7904 TMTIMER_FLAGS_NO_CRIT_SECT,
7905 "E1000 Transmit Absolute Delay Timer", &pThis->pTADTimerR3);
7906 if (RT_FAILURE(rc))
7907 return rc;
7908 pThis->pTADTimerR0 = TMTimerR0Ptr(pThis->pTADTimerR3);
7909 pThis->pTADTimerRC = TMTimerRCPtr(pThis->pTADTimerR3);
7910# endif /* E1K_NO_TAD */
7911 }
7912//#endif /* E1K_USE_TX_TIMERS */
7913
7914#ifdef E1K_USE_RX_TIMERS
7915 /* Create Receive Interrupt Delay Timer */
7916 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxIntDelayTimer, pThis,
7917 TMTIMER_FLAGS_NO_CRIT_SECT,
7918 "E1000 Receive Interrupt Delay Timer", &pThis->pRIDTimerR3);
7919 if (RT_FAILURE(rc))
7920 return rc;
7921 pThis->pRIDTimerR0 = TMTimerR0Ptr(pThis->pRIDTimerR3);
7922 pThis->pRIDTimerRC = TMTimerRCPtr(pThis->pRIDTimerR3);
7923
7924 /* Create Receive Absolute Delay Timer */
7925 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kRxAbsDelayTimer, pThis,
7926 TMTIMER_FLAGS_NO_CRIT_SECT,
7927 "E1000 Receive Absolute Delay Timer", &pThis->pRADTimerR3);
7928 if (RT_FAILURE(rc))
7929 return rc;
7930 pThis->pRADTimerR0 = TMTimerR0Ptr(pThis->pRADTimerR3);
7931 pThis->pRADTimerRC = TMTimerRCPtr(pThis->pRADTimerR3);
7932#endif /* E1K_USE_RX_TIMERS */
7933
7934 /* Create Late Interrupt Timer */
7935 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLateIntTimer, pThis,
7936 TMTIMER_FLAGS_NO_CRIT_SECT,
7937 "E1000 Late Interrupt Timer", &pThis->pIntTimerR3);
7938 if (RT_FAILURE(rc))
7939 return rc;
7940 pThis->pIntTimerR0 = TMTimerR0Ptr(pThis->pIntTimerR3);
7941 pThis->pIntTimerRC = TMTimerRCPtr(pThis->pIntTimerR3);
7942
7943 /* Create Link Up Timer */
7944 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kLinkUpTimer, pThis,
7945 TMTIMER_FLAGS_NO_CRIT_SECT,
7946 "E1000 Link Up Timer", &pThis->pLUTimerR3);
7947 if (RT_FAILURE(rc))
7948 return rc;
7949 pThis->pLUTimerR0 = TMTimerR0Ptr(pThis->pLUTimerR3);
7950 pThis->pLUTimerRC = TMTimerRCPtr(pThis->pLUTimerR3);
7951
7952 /* Register the info item */
7953 char szTmp[20];
7954 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7955 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7956
7957 /* Status driver */
7958 PPDMIBASE pBase;
7959 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
7960 if (RT_FAILURE(rc))
7961 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7962 pThis->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7963
7964 /* Network driver */
7965 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThis->IBase, &pThis->pDrvBase, "Network Port");
7966 if (RT_SUCCESS(rc))
7967 {
7968 if (rc == VINF_NAT_DNS)
7969 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "NoDNSforNAT",
7970 N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
7971 pThis->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMINETWORKUP);
7972 AssertMsgReturn(pThis->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7973
7974 pThis->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7975 pThis->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7976 }
7977 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7978 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7979 {
7980 /* No error! */
7981 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7982 }
7983 else
7984 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7985
7986 rc = RTSemEventCreate(&pThis->hEventMoreRxDescAvail);
7987 if (RT_FAILURE(rc))
7988 return rc;
7989
7990 rc = e1kInitDebugHelpers();
7991 if (RT_FAILURE(rc))
7992 return rc;
7993
7994 e1kHardReset(pThis);
7995
7996 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Public/Net/E1k%u/BytesReceived", iInstance);
7997 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Public/Net/E1k%u/BytesTransmitted", iInstance);
7998
7999 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
8000 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
8001
8002#if defined(VBOX_WITH_STATISTICS)
8003 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ", "/Devices/E1k%d/MMIO/ReadRZ", iInstance);
8004 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3", "/Devices/E1k%d/MMIO/ReadR3", iInstance);
8005 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ", "/Devices/E1k%d/MMIO/WriteRZ", iInstance);
8006 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3", "/Devices/E1k%d/MMIO/WriteR3", iInstance);
8007 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
8008 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
8009 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ", "/Devices/E1k%d/IO/ReadRZ", iInstance);
8010 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3", "/Devices/E1k%d/IO/ReadR3", iInstance);
8011 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ", "/Devices/E1k%d/IO/WriteRZ", iInstance);
8012 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3", "/Devices/E1k%d/IO/WriteR3", iInstance);
8013 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
8014 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
8015 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
8016 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
8017 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
8018 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming", "/Devices/E1k%d/Receive/CRC", iInstance);
8019 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
8020 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
8021 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
8022 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
8023 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ", "/Devices/E1k%d/Transmit/TotalRZ", iInstance);
8024 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3", "/Devices/E1k%d/Transmit/TotalR3", iInstance);
8025 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ", "/Devices/E1k%d/Transmit/SendRZ", iInstance);
8026 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3", "/Devices/E1k%d/Transmit/SendR3", iInstance);
8027
8028 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of normal context descriptors","/Devices/E1k%d/TxDesc/ContexNormal", iInstance);
8029 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSE context descriptors", "/Devices/E1k%d/TxDesc/ContextTSE", iInstance);
8030 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
8031 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
8032 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
8033 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Fallback TSE descriptor path", "/Devices/E1k%d/TxPath/Fallback", iInstance);
8034 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "GSO TSE descriptor path", "/Devices/E1k%d/TxPath/GSO", iInstance);
8035 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Regular descriptor path", "/Devices/E1k%d/TxPath/Normal", iInstance);
8036 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
8037 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8038 {
8039 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8040 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Reads", iInstance, g_aE1kRegMap[iReg].abbrev);
8041 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8042 g_aE1kRegMap[iReg].name, "/Devices/E1k%d/Regs/%s-Writes", iInstance, g_aE1kRegMap[iReg].abbrev);
8043 }
8044#endif /* VBOX_WITH_STATISTICS */
8045
8046#ifdef E1K_INT_STATS
8047 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "u64ArmedAt", "/Devices/E1k%d/u64ArmedAt", iInstance);
8048 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatMaxTxDelay", "/Devices/E1k%d/uStatMaxTxDelay", iInstance);
8049 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatInt, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatInt", "/Devices/E1k%d/uStatInt", iInstance);
8050 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTry", "/Devices/E1k%d/uStatIntTry", iInstance);
8051 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLower", "/Devices/E1k%d/uStatIntLower", iInstance);
8052 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatNoIntICR", "/Devices/E1k%d/uStatNoIntICR", iInstance);
8053 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLost", "/Devices/E1k%d/iStatIntLost", iInstance);
8054 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "iStatIntLostOne", "/Devices/E1k%d/iStatIntLostOne", iInstance);
8055 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntIMS", "/Devices/E1k%d/uStatIntIMS", iInstance);
8056 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntSkip", "/Devices/E1k%d/uStatIntSkip", iInstance);
8057 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntLate", "/Devices/E1k%d/uStatIntLate", iInstance);
8058 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntMasked", "/Devices/E1k%d/uStatIntMasked", iInstance);
8059 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntEarly", "/Devices/E1k%d/uStatIntEarly", iInstance);
8060 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRx", "/Devices/E1k%d/uStatIntRx", iInstance);
8061 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTx", "/Devices/E1k%d/uStatIntTx", iInstance);
8062 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntICS", "/Devices/E1k%d/uStatIntICS", iInstance);
8063 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRDTR", "/Devices/E1k%d/uStatIntRDTR", iInstance);
8064 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntRXDMT0", "/Devices/E1k%d/uStatIntRXDMT0", iInstance);
8065 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatIntTXQE", "/Devices/E1k%d/uStatIntTXQE", iInstance);
8066 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxNoRS", "/Devices/E1k%d/uStatTxNoRS", iInstance);
8067 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxIDE", "/Devices/E1k%d/uStatTxIDE", iInstance);
8068 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayed", "/Devices/E1k%d/uStatTxDelayed", iInstance);
8069 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxDelayExp", "/Devices/E1k%d/uStatTxDelayExp", iInstance);
8070 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTAD", "/Devices/E1k%d/uStatTAD", iInstance);
8071 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTID", "/Devices/E1k%d/uStatTID", iInstance);
8072 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRAD", "/Devices/E1k%d/uStatRAD", iInstance);
8073 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRID, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRID", "/Devices/E1k%d/uStatRID", iInstance);
8074 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatRxFrm", "/Devices/E1k%d/uStatRxFrm", iInstance);
8075 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxFrm", "/Devices/E1k%d/uStatTxFrm", iInstance);
8076 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescCtx", "/Devices/E1k%d/uStatDescCtx", iInstance);
8077 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescDat", "/Devices/E1k%d/uStatDescDat", iInstance);
8078 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatDescLeg", "/Devices/E1k%d/uStatDescLeg", iInstance);
8079 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx1514", "/Devices/E1k%d/uStatTx1514", iInstance);
8080 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx2962", "/Devices/E1k%d/uStatTx2962", iInstance);
8081 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx4410", "/Devices/E1k%d/uStatTx4410", iInstance);
8082 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx5858", "/Devices/E1k%d/uStatTx5858", iInstance);
8083 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx7306", "/Devices/E1k%d/uStatTx7306", iInstance);
8084 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx8754", "/Devices/E1k%d/uStatTx8754", iInstance);
8085 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx16384", "/Devices/E1k%d/uStatTx16384", iInstance);
8086 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTx32768", "/Devices/E1k%d/uStatTx32768", iInstance);
8087 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NS, "uStatTxLarge", "/Devices/E1k%d/uStatTxLarge", iInstance);
8088#endif /* E1K_INT_STATS */
8089
8090 return VINF_SUCCESS;
8091}
8092
8093/**
8094 * The device registration structure.
8095 */
8096const PDMDEVREG g_DeviceE1000 =
8097{
8098 /* Structure version. PDM_DEVREG_VERSION defines the current version. */
8099 PDM_DEVREG_VERSION,
8100 /* Device name. */
8101 "e1000",
8102 /* Name of guest context module (no path).
8103 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
8104 "VBoxDDRC.rc",
8105 /* Name of ring-0 module (no path).
8106 * Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
8107 "VBoxDDR0.r0",
8108 /* The description of the device. The UTF-8 string pointed to shall, like this structure,
8109 * remain unchanged from registration till VM destruction. */
8110 "Intel PRO/1000 MT Desktop Ethernet.\n",
8111
8112 /* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
8113 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
8114 /* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
8115 PDM_DEVREG_CLASS_NETWORK,
8116 /* Maximum number of instances (per VM). */
8117 ~0U,
8118 /* Size of the instance data. */
8119 sizeof(E1KSTATE),
8120
8121 /* pfnConstruct */
8122 e1kR3Construct,
8123 /* pfnDestruct */
8124 e1kR3Destruct,
8125 /* pfnRelocate */
8126 e1kR3Relocate,
8127 /* pfnMemSetup */
8128 NULL,
8129 /* pfnPowerOn */
8130 NULL,
8131 /* pfnReset */
8132 e1kR3Reset,
8133 /* pfnSuspend */
8134 e1kR3Suspend,
8135 /* pfnResume */
8136 NULL,
8137 /* pfnAttach */
8138 e1kR3Attach,
8139 /* pfnDeatch */
8140 e1kR3Detach,
8141 /* pfnQueryInterface */
8142 NULL,
8143 /* pfnInitComplete */
8144 NULL,
8145 /* pfnPowerOff */
8146 e1kR3PowerOff,
8147 /* pfnSoftReset */
8148 NULL,
8149
8150 /* u32VersionEnd */
8151 PDM_DEVREG_VERSION
8152};
8153
8154#endif /* IN_RING3 */
8155#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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