VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 82129

Last change on this file since 82129 was 82129, checked in by vboxsync, 5 years ago

Devices/Network: Don't decorate the public stats with device, just use the main adapter number. Moved to different sub-folder to avoid confusion.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 324.3 KB
Line 
1/* $Id: DevE1000.cpp 82129 2019-11-23 17:28:03Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2019 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280/** Gets the specfieid bits from the register. */
281#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
282#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
284#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
285#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286
287#define CTRL_SLU UINT32_C(0x00000040)
288#define CTRL_MDIO UINT32_C(0x00100000)
289#define CTRL_MDC UINT32_C(0x00200000)
290#define CTRL_MDIO_DIR UINT32_C(0x01000000)
291#define CTRL_MDC_DIR UINT32_C(0x02000000)
292#define CTRL_RESET UINT32_C(0x04000000)
293#define CTRL_VME UINT32_C(0x40000000)
294
295#define STATUS_LU UINT32_C(0x00000002)
296#define STATUS_TXOFF UINT32_C(0x00000010)
297
298#define EECD_EE_WIRES UINT32_C(0x0F)
299#define EECD_EE_REQ UINT32_C(0x40)
300#define EECD_EE_GNT UINT32_C(0x80)
301
302#define EERD_START UINT32_C(0x00000001)
303#define EERD_DONE UINT32_C(0x00000010)
304#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
305#define EERD_DATA_SHIFT 16
306#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
307#define EERD_ADDR_SHIFT 8
308
309#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
310#define MDIC_DATA_SHIFT 0
311#define MDIC_REG_MASK UINT32_C(0x001F0000)
312#define MDIC_REG_SHIFT 16
313#define MDIC_PHY_MASK UINT32_C(0x03E00000)
314#define MDIC_PHY_SHIFT 21
315#define MDIC_OP_WRITE UINT32_C(0x04000000)
316#define MDIC_OP_READ UINT32_C(0x08000000)
317#define MDIC_READY UINT32_C(0x10000000)
318#define MDIC_INT_EN UINT32_C(0x20000000)
319#define MDIC_ERROR UINT32_C(0x40000000)
320
321#define TCTL_EN UINT32_C(0x00000002)
322#define TCTL_PSP UINT32_C(0x00000008)
323
324#define RCTL_EN UINT32_C(0x00000002)
325#define RCTL_UPE UINT32_C(0x00000008)
326#define RCTL_MPE UINT32_C(0x00000010)
327#define RCTL_LPE UINT32_C(0x00000020)
328#define RCTL_LBM_MASK UINT32_C(0x000000C0)
329#define RCTL_LBM_SHIFT 6
330#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
331#define RCTL_RDMTS_SHIFT 8
332#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
333#define RCTL_MO_MASK UINT32_C(0x00003000)
334#define RCTL_MO_SHIFT 12
335#define RCTL_BAM UINT32_C(0x00008000)
336#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
337#define RCTL_BSIZE_SHIFT 16
338#define RCTL_VFE UINT32_C(0x00040000)
339#define RCTL_CFIEN UINT32_C(0x00080000)
340#define RCTL_CFI UINT32_C(0x00100000)
341#define RCTL_BSEX UINT32_C(0x02000000)
342#define RCTL_SECRC UINT32_C(0x04000000)
343
344#define ICR_TXDW UINT32_C(0x00000001)
345#define ICR_TXQE UINT32_C(0x00000002)
346#define ICR_LSC UINT32_C(0x00000004)
347#define ICR_RXDMT0 UINT32_C(0x00000010)
348#define ICR_RXT0 UINT32_C(0x00000080)
349#define ICR_TXD_LOW UINT32_C(0x00008000)
350#define RDTR_FPD UINT32_C(0x80000000)
351
352#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
353typedef struct
354{
355 unsigned rxa : 7;
356 unsigned rxa_r : 9;
357 unsigned txa : 16;
358} PBAST;
359AssertCompileSize(PBAST, 4);
360
361#define TXDCTL_WTHRESH_MASK 0x003F0000
362#define TXDCTL_WTHRESH_SHIFT 16
363#define TXDCTL_LWTHRESH_MASK 0xFE000000
364#define TXDCTL_LWTHRESH_SHIFT 25
365
366#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
367#define RXCSUM_PCSS_SHIFT 0
368
369/** @name Register access macros
370 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
371 * @{ */
372#define CTRL pThis->auRegs[CTRL_IDX]
373#define STATUS pThis->auRegs[STATUS_IDX]
374#define EECD pThis->auRegs[EECD_IDX]
375#define EERD pThis->auRegs[EERD_IDX]
376#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
377#define FLA pThis->auRegs[FLA_IDX]
378#define MDIC pThis->auRegs[MDIC_IDX]
379#define FCAL pThis->auRegs[FCAL_IDX]
380#define FCAH pThis->auRegs[FCAH_IDX]
381#define FCT pThis->auRegs[FCT_IDX]
382#define VET pThis->auRegs[VET_IDX]
383#define ICR pThis->auRegs[ICR_IDX]
384#define ITR pThis->auRegs[ITR_IDX]
385#define ICS pThis->auRegs[ICS_IDX]
386#define IMS pThis->auRegs[IMS_IDX]
387#define IMC pThis->auRegs[IMC_IDX]
388#define RCTL pThis->auRegs[RCTL_IDX]
389#define FCTTV pThis->auRegs[FCTTV_IDX]
390#define TXCW pThis->auRegs[TXCW_IDX]
391#define RXCW pThis->auRegs[RXCW_IDX]
392#define TCTL pThis->auRegs[TCTL_IDX]
393#define TIPG pThis->auRegs[TIPG_IDX]
394#define AIFS pThis->auRegs[AIFS_IDX]
395#define LEDCTL pThis->auRegs[LEDCTL_IDX]
396#define PBA pThis->auRegs[PBA_IDX]
397#define FCRTL pThis->auRegs[FCRTL_IDX]
398#define FCRTH pThis->auRegs[FCRTH_IDX]
399#define RDFH pThis->auRegs[RDFH_IDX]
400#define RDFT pThis->auRegs[RDFT_IDX]
401#define RDFHS pThis->auRegs[RDFHS_IDX]
402#define RDFTS pThis->auRegs[RDFTS_IDX]
403#define RDFPC pThis->auRegs[RDFPC_IDX]
404#define RDBAL pThis->auRegs[RDBAL_IDX]
405#define RDBAH pThis->auRegs[RDBAH_IDX]
406#define RDLEN pThis->auRegs[RDLEN_IDX]
407#define RDH pThis->auRegs[RDH_IDX]
408#define RDT pThis->auRegs[RDT_IDX]
409#define RDTR pThis->auRegs[RDTR_IDX]
410#define RXDCTL pThis->auRegs[RXDCTL_IDX]
411#define RADV pThis->auRegs[RADV_IDX]
412#define RSRPD pThis->auRegs[RSRPD_IDX]
413#define TXDMAC pThis->auRegs[TXDMAC_IDX]
414#define TDFH pThis->auRegs[TDFH_IDX]
415#define TDFT pThis->auRegs[TDFT_IDX]
416#define TDFHS pThis->auRegs[TDFHS_IDX]
417#define TDFTS pThis->auRegs[TDFTS_IDX]
418#define TDFPC pThis->auRegs[TDFPC_IDX]
419#define TDBAL pThis->auRegs[TDBAL_IDX]
420#define TDBAH pThis->auRegs[TDBAH_IDX]
421#define TDLEN pThis->auRegs[TDLEN_IDX]
422#define TDH pThis->auRegs[TDH_IDX]
423#define TDT pThis->auRegs[TDT_IDX]
424#define TIDV pThis->auRegs[TIDV_IDX]
425#define TXDCTL pThis->auRegs[TXDCTL_IDX]
426#define TADV pThis->auRegs[TADV_IDX]
427#define TSPMT pThis->auRegs[TSPMT_IDX]
428#define CRCERRS pThis->auRegs[CRCERRS_IDX]
429#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
430#define SYMERRS pThis->auRegs[SYMERRS_IDX]
431#define RXERRC pThis->auRegs[RXERRC_IDX]
432#define MPC pThis->auRegs[MPC_IDX]
433#define SCC pThis->auRegs[SCC_IDX]
434#define ECOL pThis->auRegs[ECOL_IDX]
435#define MCC pThis->auRegs[MCC_IDX]
436#define LATECOL pThis->auRegs[LATECOL_IDX]
437#define COLC pThis->auRegs[COLC_IDX]
438#define DC pThis->auRegs[DC_IDX]
439#define TNCRS pThis->auRegs[TNCRS_IDX]
440/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
441#define CEXTERR pThis->auRegs[CEXTERR_IDX]
442#define RLEC pThis->auRegs[RLEC_IDX]
443#define XONRXC pThis->auRegs[XONRXC_IDX]
444#define XONTXC pThis->auRegs[XONTXC_IDX]
445#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
446#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
447#define FCRUC pThis->auRegs[FCRUC_IDX]
448#define PRC64 pThis->auRegs[PRC64_IDX]
449#define PRC127 pThis->auRegs[PRC127_IDX]
450#define PRC255 pThis->auRegs[PRC255_IDX]
451#define PRC511 pThis->auRegs[PRC511_IDX]
452#define PRC1023 pThis->auRegs[PRC1023_IDX]
453#define PRC1522 pThis->auRegs[PRC1522_IDX]
454#define GPRC pThis->auRegs[GPRC_IDX]
455#define BPRC pThis->auRegs[BPRC_IDX]
456#define MPRC pThis->auRegs[MPRC_IDX]
457#define GPTC pThis->auRegs[GPTC_IDX]
458#define GORCL pThis->auRegs[GORCL_IDX]
459#define GORCH pThis->auRegs[GORCH_IDX]
460#define GOTCL pThis->auRegs[GOTCL_IDX]
461#define GOTCH pThis->auRegs[GOTCH_IDX]
462#define RNBC pThis->auRegs[RNBC_IDX]
463#define RUC pThis->auRegs[RUC_IDX]
464#define RFC pThis->auRegs[RFC_IDX]
465#define ROC pThis->auRegs[ROC_IDX]
466#define RJC pThis->auRegs[RJC_IDX]
467#define MGTPRC pThis->auRegs[MGTPRC_IDX]
468#define MGTPDC pThis->auRegs[MGTPDC_IDX]
469#define MGTPTC pThis->auRegs[MGTPTC_IDX]
470#define TORL pThis->auRegs[TORL_IDX]
471#define TORH pThis->auRegs[TORH_IDX]
472#define TOTL pThis->auRegs[TOTL_IDX]
473#define TOTH pThis->auRegs[TOTH_IDX]
474#define TPR pThis->auRegs[TPR_IDX]
475#define TPT pThis->auRegs[TPT_IDX]
476#define PTC64 pThis->auRegs[PTC64_IDX]
477#define PTC127 pThis->auRegs[PTC127_IDX]
478#define PTC255 pThis->auRegs[PTC255_IDX]
479#define PTC511 pThis->auRegs[PTC511_IDX]
480#define PTC1023 pThis->auRegs[PTC1023_IDX]
481#define PTC1522 pThis->auRegs[PTC1522_IDX]
482#define MPTC pThis->auRegs[MPTC_IDX]
483#define BPTC pThis->auRegs[BPTC_IDX]
484#define TSCTC pThis->auRegs[TSCTC_IDX]
485#define TSCTFC pThis->auRegs[TSCTFC_IDX]
486#define RXCSUM pThis->auRegs[RXCSUM_IDX]
487#define WUC pThis->auRegs[WUC_IDX]
488#define WUFC pThis->auRegs[WUFC_IDX]
489#define WUS pThis->auRegs[WUS_IDX]
490#define MANC pThis->auRegs[MANC_IDX]
491#define IPAV pThis->auRegs[IPAV_IDX]
492#define WUPL pThis->auRegs[WUPL_IDX]
493/** @} */
494
495/**
496 * Indices of memory-mapped registers in register table.
497 */
498typedef enum
499{
500 CTRL_IDX,
501 STATUS_IDX,
502 EECD_IDX,
503 EERD_IDX,
504 CTRL_EXT_IDX,
505 FLA_IDX,
506 MDIC_IDX,
507 FCAL_IDX,
508 FCAH_IDX,
509 FCT_IDX,
510 VET_IDX,
511 ICR_IDX,
512 ITR_IDX,
513 ICS_IDX,
514 IMS_IDX,
515 IMC_IDX,
516 RCTL_IDX,
517 FCTTV_IDX,
518 TXCW_IDX,
519 RXCW_IDX,
520 TCTL_IDX,
521 TIPG_IDX,
522 AIFS_IDX,
523 LEDCTL_IDX,
524 PBA_IDX,
525 FCRTL_IDX,
526 FCRTH_IDX,
527 RDFH_IDX,
528 RDFT_IDX,
529 RDFHS_IDX,
530 RDFTS_IDX,
531 RDFPC_IDX,
532 RDBAL_IDX,
533 RDBAH_IDX,
534 RDLEN_IDX,
535 RDH_IDX,
536 RDT_IDX,
537 RDTR_IDX,
538 RXDCTL_IDX,
539 RADV_IDX,
540 RSRPD_IDX,
541 TXDMAC_IDX,
542 TDFH_IDX,
543 TDFT_IDX,
544 TDFHS_IDX,
545 TDFTS_IDX,
546 TDFPC_IDX,
547 TDBAL_IDX,
548 TDBAH_IDX,
549 TDLEN_IDX,
550 TDH_IDX,
551 TDT_IDX,
552 TIDV_IDX,
553 TXDCTL_IDX,
554 TADV_IDX,
555 TSPMT_IDX,
556 CRCERRS_IDX,
557 ALGNERRC_IDX,
558 SYMERRS_IDX,
559 RXERRC_IDX,
560 MPC_IDX,
561 SCC_IDX,
562 ECOL_IDX,
563 MCC_IDX,
564 LATECOL_IDX,
565 COLC_IDX,
566 DC_IDX,
567 TNCRS_IDX,
568 SEC_IDX,
569 CEXTERR_IDX,
570 RLEC_IDX,
571 XONRXC_IDX,
572 XONTXC_IDX,
573 XOFFRXC_IDX,
574 XOFFTXC_IDX,
575 FCRUC_IDX,
576 PRC64_IDX,
577 PRC127_IDX,
578 PRC255_IDX,
579 PRC511_IDX,
580 PRC1023_IDX,
581 PRC1522_IDX,
582 GPRC_IDX,
583 BPRC_IDX,
584 MPRC_IDX,
585 GPTC_IDX,
586 GORCL_IDX,
587 GORCH_IDX,
588 GOTCL_IDX,
589 GOTCH_IDX,
590 RNBC_IDX,
591 RUC_IDX,
592 RFC_IDX,
593 ROC_IDX,
594 RJC_IDX,
595 MGTPRC_IDX,
596 MGTPDC_IDX,
597 MGTPTC_IDX,
598 TORL_IDX,
599 TORH_IDX,
600 TOTL_IDX,
601 TOTH_IDX,
602 TPR_IDX,
603 TPT_IDX,
604 PTC64_IDX,
605 PTC127_IDX,
606 PTC255_IDX,
607 PTC511_IDX,
608 PTC1023_IDX,
609 PTC1522_IDX,
610 MPTC_IDX,
611 BPTC_IDX,
612 TSCTC_IDX,
613 TSCTFC_IDX,
614 RXCSUM_IDX,
615 WUC_IDX,
616 WUFC_IDX,
617 WUS_IDX,
618 MANC_IDX,
619 IPAV_IDX,
620 WUPL_IDX,
621 MTA_IDX,
622 RA_IDX,
623 VFTA_IDX,
624 IP4AT_IDX,
625 IP6AT_IDX,
626 WUPM_IDX,
627 FFLT_IDX,
628 FFMT_IDX,
629 FFVT_IDX,
630 PBM_IDX,
631 RA_82542_IDX,
632 MTA_82542_IDX,
633 VFTA_82542_IDX,
634 E1K_NUM_OF_REGS
635} E1kRegIndex;
636
637#define E1K_NUM_OF_32BIT_REGS MTA_IDX
638/** The number of registers with strictly increasing offset. */
639#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
640
641
642/**
643 * Define E1000-specific EEPROM layout.
644 */
645struct E1kEEPROM
646{
647 public:
648 EEPROM93C46 eeprom;
649
650#ifdef IN_RING3
651 /**
652 * Initialize EEPROM content.
653 *
654 * @param macAddr MAC address of E1000.
655 */
656 void init(RTMAC &macAddr)
657 {
658 eeprom.init();
659 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
660 eeprom.m_au16Data[0x04] = 0xFFFF;
661 /*
662 * bit 3 - full support for power management
663 * bit 10 - full duplex
664 */
665 eeprom.m_au16Data[0x0A] = 0x4408;
666 eeprom.m_au16Data[0x0B] = 0x001E;
667 eeprom.m_au16Data[0x0C] = 0x8086;
668 eeprom.m_au16Data[0x0D] = 0x100E;
669 eeprom.m_au16Data[0x0E] = 0x8086;
670 eeprom.m_au16Data[0x0F] = 0x3040;
671 eeprom.m_au16Data[0x21] = 0x7061;
672 eeprom.m_au16Data[0x22] = 0x280C;
673 eeprom.m_au16Data[0x23] = 0x00C8;
674 eeprom.m_au16Data[0x24] = 0x00C8;
675 eeprom.m_au16Data[0x2F] = 0x0602;
676 updateChecksum();
677 };
678
679 /**
680 * Compute the checksum as required by E1000 and store it
681 * in the last word.
682 */
683 void updateChecksum()
684 {
685 uint16_t u16Checksum = 0;
686
687 for (int i = 0; i < eeprom.SIZE-1; i++)
688 u16Checksum += eeprom.m_au16Data[i];
689 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
690 };
691
692 /**
693 * First 6 bytes of EEPROM contain MAC address.
694 *
695 * @returns MAC address of E1000.
696 */
697 void getMac(PRTMAC pMac)
698 {
699 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
700 };
701
702 uint32_t read()
703 {
704 return eeprom.read();
705 }
706
707 void write(uint32_t u32Wires)
708 {
709 eeprom.write(u32Wires);
710 }
711
712 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
713 {
714 return eeprom.readWord(u32Addr, pu16Value);
715 }
716
717 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
718 {
719 return eeprom.load(pHlp, pSSM);
720 }
721
722 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
723 {
724 eeprom.save(pHlp, pSSM);
725 }
726#endif /* IN_RING3 */
727};
728
729
730#define E1K_SPEC_VLAN(s) (s & 0xFFF)
731#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
732#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
733
734struct E1kRxDStatus
735{
736 /** @name Descriptor Status field (3.2.3.1)
737 * @{ */
738 unsigned fDD : 1; /**< Descriptor Done. */
739 unsigned fEOP : 1; /**< End of packet. */
740 unsigned fIXSM : 1; /**< Ignore checksum indication. */
741 unsigned fVP : 1; /**< VLAN, matches VET. */
742 unsigned : 1;
743 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
744 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
745 unsigned fPIF : 1; /**< Passed in-exact filter */
746 /** @} */
747 /** @name Descriptor Errors field (3.2.3.2)
748 * (Only valid when fEOP and fDD are set.)
749 * @{ */
750 unsigned fCE : 1; /**< CRC or alignment error. */
751 unsigned : 4; /**< Reserved, varies with different models... */
752 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
753 unsigned fIPE : 1; /**< IP Checksum error. */
754 unsigned fRXE : 1; /**< RX Data error. */
755 /** @} */
756 /** @name Descriptor Special field (3.2.3.3)
757 * @{ */
758 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
759 /** @} */
760};
761typedef struct E1kRxDStatus E1KRXDST;
762
763struct E1kRxDesc_st
764{
765 uint64_t u64BufAddr; /**< Address of data buffer */
766 uint16_t u16Length; /**< Length of data in buffer */
767 uint16_t u16Checksum; /**< Packet checksum */
768 E1KRXDST status;
769};
770typedef struct E1kRxDesc_st E1KRXDESC;
771AssertCompileSize(E1KRXDESC, 16);
772
773#define E1K_DTYP_LEGACY -1
774#define E1K_DTYP_CONTEXT 0
775#define E1K_DTYP_DATA 1
776
777struct E1kTDLegacy
778{
779 uint64_t u64BufAddr; /**< Address of data buffer */
780 struct TDLCmd_st
781 {
782 unsigned u16Length : 16;
783 unsigned u8CSO : 8;
784 /* CMD field : 8 */
785 unsigned fEOP : 1;
786 unsigned fIFCS : 1;
787 unsigned fIC : 1;
788 unsigned fRS : 1;
789 unsigned fRPS : 1;
790 unsigned fDEXT : 1;
791 unsigned fVLE : 1;
792 unsigned fIDE : 1;
793 } cmd;
794 struct TDLDw3_st
795 {
796 /* STA field */
797 unsigned fDD : 1;
798 unsigned fEC : 1;
799 unsigned fLC : 1;
800 unsigned fTURSV : 1;
801 /* RSV field */
802 unsigned u4RSV : 4;
803 /* CSS field */
804 unsigned u8CSS : 8;
805 /* Special field*/
806 unsigned u16Special: 16;
807 } dw3;
808};
809
810/**
811 * TCP/IP Context Transmit Descriptor, section 3.3.6.
812 */
813struct E1kTDContext
814{
815 struct CheckSum_st
816 {
817 /** TSE: Header start. !TSE: Checksum start. */
818 unsigned u8CSS : 8;
819 /** Checksum offset - where to store it. */
820 unsigned u8CSO : 8;
821 /** Checksum ending (inclusive) offset, 0 = end of packet. */
822 unsigned u16CSE : 16;
823 } ip;
824 struct CheckSum_st tu;
825 struct TDCDw2_st
826 {
827 /** TSE: The total number of payload bytes for this context. Sans header. */
828 unsigned u20PAYLEN : 20;
829 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
830 unsigned u4DTYP : 4;
831 /** TUCMD field, 8 bits
832 * @{ */
833 /** TSE: TCP (set) or UDP (clear). */
834 unsigned fTCP : 1;
835 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
836 * the IP header. Does not affect the checksumming.
837 * @remarks 82544GC/EI interprets a cleared field differently. */
838 unsigned fIP : 1;
839 /** TSE: TCP segmentation enable. When clear the context describes */
840 unsigned fTSE : 1;
841 /** Report status (only applies to dw3.fDD for here). */
842 unsigned fRS : 1;
843 /** Reserved, MBZ. */
844 unsigned fRSV1 : 1;
845 /** Descriptor extension, must be set for this descriptor type. */
846 unsigned fDEXT : 1;
847 /** Reserved, MBZ. */
848 unsigned fRSV2 : 1;
849 /** Interrupt delay enable. */
850 unsigned fIDE : 1;
851 /** @} */
852 } dw2;
853 struct TDCDw3_st
854 {
855 /** Descriptor Done. */
856 unsigned fDD : 1;
857 /** Reserved, MBZ. */
858 unsigned u7RSV : 7;
859 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
860 unsigned u8HDRLEN : 8;
861 /** TSO: Maximum segment size. */
862 unsigned u16MSS : 16;
863 } dw3;
864};
865typedef struct E1kTDContext E1KTXCTX;
866
867/**
868 * TCP/IP Data Transmit Descriptor, section 3.3.7.
869 */
870struct E1kTDData
871{
872 uint64_t u64BufAddr; /**< Address of data buffer */
873 struct TDDCmd_st
874 {
875 /** The total length of data pointed to by this descriptor. */
876 unsigned u20DTALEN : 20;
877 /** The descriptor type - E1K_DTYP_DATA (1). */
878 unsigned u4DTYP : 4;
879 /** @name DCMD field, 8 bits (3.3.7.1).
880 * @{ */
881 /** End of packet. Note TSCTFC update. */
882 unsigned fEOP : 1;
883 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
884 unsigned fIFCS : 1;
885 /** Use the TSE context when set and the normal when clear. */
886 unsigned fTSE : 1;
887 /** Report status (dw3.STA). */
888 unsigned fRS : 1;
889 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
890 unsigned fRPS : 1;
891 /** Descriptor extension, must be set for this descriptor type. */
892 unsigned fDEXT : 1;
893 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
894 * Insert dw3.SPECIAL after ethernet header. */
895 unsigned fVLE : 1;
896 /** Interrupt delay enable. */
897 unsigned fIDE : 1;
898 /** @} */
899 } cmd;
900 struct TDDDw3_st
901 {
902 /** @name STA field (3.3.7.2)
903 * @{ */
904 unsigned fDD : 1; /**< Descriptor done. */
905 unsigned fEC : 1; /**< Excess collision. */
906 unsigned fLC : 1; /**< Late collision. */
907 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
908 unsigned fTURSV : 1;
909 /** @} */
910 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
911 /** @name POPTS (Packet Option) field (3.3.7.3)
912 * @{ */
913 unsigned fIXSM : 1; /**< Insert IP checksum. */
914 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
915 unsigned u6RSV : 6; /**< Reserved, MBZ. */
916 /** @} */
917 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
918 * Requires fEOP, fVLE and CTRL.VME to be set.
919 * @{ */
920 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
921 /** @} */
922 } dw3;
923};
924typedef struct E1kTDData E1KTXDAT;
925
926union E1kTxDesc
927{
928 struct E1kTDLegacy legacy;
929 struct E1kTDContext context;
930 struct E1kTDData data;
931};
932typedef union E1kTxDesc E1KTXDESC;
933AssertCompileSize(E1KTXDESC, 16);
934
935#define RA_CTL_AS 0x0003
936#define RA_CTL_AV 0x8000
937
938union E1kRecAddr
939{
940 uint32_t au32[32];
941 struct RAArray
942 {
943 uint8_t addr[6];
944 uint16_t ctl;
945 } array[16];
946};
947typedef struct E1kRecAddr::RAArray E1KRAELEM;
948typedef union E1kRecAddr E1KRA;
949AssertCompileSize(E1KRA, 8*16);
950
951#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
952#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
953#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
954#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
955
956/** @todo use+extend RTNETIPV4 */
957struct E1kIpHeader
958{
959 /* type of service / version / header length */
960 uint16_t tos_ver_hl;
961 /* total length */
962 uint16_t total_len;
963 /* identification */
964 uint16_t ident;
965 /* fragment offset field */
966 uint16_t offset;
967 /* time to live / protocol*/
968 uint16_t ttl_proto;
969 /* checksum */
970 uint16_t chksum;
971 /* source IP address */
972 uint32_t src;
973 /* destination IP address */
974 uint32_t dest;
975};
976AssertCompileSize(struct E1kIpHeader, 20);
977
978#define E1K_TCP_FIN UINT16_C(0x01)
979#define E1K_TCP_SYN UINT16_C(0x02)
980#define E1K_TCP_RST UINT16_C(0x04)
981#define E1K_TCP_PSH UINT16_C(0x08)
982#define E1K_TCP_ACK UINT16_C(0x10)
983#define E1K_TCP_URG UINT16_C(0x20)
984#define E1K_TCP_ECE UINT16_C(0x40)
985#define E1K_TCP_CWR UINT16_C(0x80)
986#define E1K_TCP_FLAGS UINT16_C(0x3f)
987
988/** @todo use+extend RTNETTCP */
989struct E1kTcpHeader
990{
991 uint16_t src;
992 uint16_t dest;
993 uint32_t seqno;
994 uint32_t ackno;
995 uint16_t hdrlen_flags;
996 uint16_t wnd;
997 uint16_t chksum;
998 uint16_t urgp;
999};
1000AssertCompileSize(struct E1kTcpHeader, 20);
1001
1002
1003#ifdef E1K_WITH_TXD_CACHE
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 4
1006/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1007# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1008#else /* !E1K_WITH_TXD_CACHE */
1009/** The current Saved state version. */
1010# define E1K_SAVEDSTATE_VERSION 3
1011#endif /* !E1K_WITH_TXD_CACHE */
1012/** Saved state version for VirtualBox 4.1 and earlier.
1013 * These did not include VLAN tag fields. */
1014#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1015/** Saved state version for VirtualBox 3.0 and earlier.
1016 * This did not include the configuration part nor the E1kEEPROM. */
1017#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1018
1019/**
1020 * E1000 shared device state.
1021 *
1022 * This is shared between ring-0 and ring-3.
1023 */
1024typedef struct E1KSTATE
1025{
1026 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1027
1028 /** Handle to PCI region \#0, the MMIO region. */
1029 IOMIOPORTHANDLE hMmioRegion;
1030 /** Handle to PCI region \#2, the I/O ports. */
1031 IOMIOPORTHANDLE hIoPorts;
1032
1033 /** Receive Interrupt Delay Timer. */
1034 TMTIMERHANDLE hRIDTimer;
1035 /** Receive Absolute Delay Timer. */
1036 TMTIMERHANDLE hRADTimer;
1037 /** Transmit Interrupt Delay Timer. */
1038 TMTIMERHANDLE hTIDTimer;
1039 /** Transmit Absolute Delay Timer. */
1040 TMTIMERHANDLE hTADTimer;
1041 /** Transmit Delay Timer. */
1042 TMTIMERHANDLE hTXDTimer;
1043 /** Late Interrupt Timer. */
1044 TMTIMERHANDLE hIntTimer;
1045 /** Link Up(/Restore) Timer. */
1046 TMTIMERHANDLE hLUTimer;
1047
1048 /** Transmit task. */
1049 PDMTASKHANDLE hTxTask;
1050
1051 /** Critical section - what is it protecting? */
1052 PDMCRITSECT cs;
1053 /** RX Critical section. */
1054 PDMCRITSECT csRx;
1055#ifdef E1K_WITH_TX_CS
1056 /** TX Critical section. */
1057 PDMCRITSECT csTx;
1058#endif /* E1K_WITH_TX_CS */
1059 /** MAC address obtained from the configuration. */
1060 RTMAC macConfigured;
1061 uint16_t u16Padding0;
1062 /** EMT: Last time the interrupt was acknowledged. */
1063 uint64_t u64AckedAt;
1064 /** All: Used for eliminating spurious interrupts. */
1065 bool fIntRaised;
1066 /** EMT: false if the cable is disconnected by the GUI. */
1067 bool fCableConnected;
1068 /** EMT: Compute Ethernet CRC for RX packets. */
1069 bool fEthernetCRC;
1070 /** All: throttle interrupts. */
1071 bool fItrEnabled;
1072 /** All: throttle RX interrupts. */
1073 bool fItrRxEnabled;
1074 /** All: Delay TX interrupts using TIDV/TADV. */
1075 bool fTidEnabled;
1076 bool afPadding[2];
1077 /** Link up delay (in milliseconds). */
1078 uint32_t cMsLinkUpDelay;
1079
1080 /** All: Device register storage. */
1081 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1082 /** TX/RX: Status LED. */
1083 PDMLED led;
1084 /** TX/RX: Number of packet being sent/received to show in debug log. */
1085 uint32_t u32PktNo;
1086
1087 /** EMT: Offset of the register to be read via IO. */
1088 uint32_t uSelectedReg;
1089 /** EMT: Multicast Table Array. */
1090 uint32_t auMTA[128];
1091 /** EMT: Receive Address registers. */
1092 E1KRA aRecAddr;
1093 /** EMT: VLAN filter table array. */
1094 uint32_t auVFTA[128];
1095 /** EMT: Receive buffer size. */
1096 uint16_t u16RxBSize;
1097 /** EMT: Locked state -- no state alteration possible. */
1098 bool fLocked;
1099 /** EMT: */
1100 bool fDelayInts;
1101 /** All: */
1102 bool fIntMaskUsed;
1103
1104 /** N/A: */
1105 bool volatile fMaybeOutOfSpace;
1106 /** EMT: Gets signalled when more RX descriptors become available. */
1107 SUPSEMEVENT hEventMoreRxDescAvail;
1108#ifdef E1K_WITH_RXD_CACHE
1109 /** RX: Fetched RX descriptors. */
1110 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1111 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1112 /** RX: Actual number of fetched RX descriptors. */
1113 uint32_t nRxDFetched;
1114 /** RX: Index in cache of RX descriptor being processed. */
1115 uint32_t iRxDCurrent;
1116#endif /* E1K_WITH_RXD_CACHE */
1117
1118 /** TX: Context used for TCP segmentation packets. */
1119 E1KTXCTX contextTSE;
1120 /** TX: Context used for ordinary packets. */
1121 E1KTXCTX contextNormal;
1122#ifdef E1K_WITH_TXD_CACHE
1123 /** TX: Fetched TX descriptors. */
1124 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1125 /** TX: Actual number of fetched TX descriptors. */
1126 uint8_t nTxDFetched;
1127 /** TX: Index in cache of TX descriptor being processed. */
1128 uint8_t iTxDCurrent;
1129 /** TX: Will this frame be sent as GSO. */
1130 bool fGSO;
1131 /** Alignment padding. */
1132 bool fReserved;
1133 /** TX: Number of bytes in next packet. */
1134 uint32_t cbTxAlloc;
1135
1136#endif /* E1K_WITH_TXD_CACHE */
1137 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1138 * applicable to the current TSE mode. */
1139 PDMNETWORKGSO GsoCtx;
1140 /** Scratch space for holding the loopback / fallback scatter / gather
1141 * descriptor. */
1142 union
1143 {
1144 PDMSCATTERGATHER Sg;
1145 uint8_t padding[8 * sizeof(RTUINTPTR)];
1146 } uTxFallback;
1147 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1148 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1149 /** TX: Number of bytes assembled in TX packet buffer. */
1150 uint16_t u16TxPktLen;
1151 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1152 bool fGSOEnabled;
1153 /** TX: IP checksum has to be inserted if true. */
1154 bool fIPcsum;
1155 /** TX: TCP/UDP checksum has to be inserted if true. */
1156 bool fTCPcsum;
1157 /** TX: VLAN tag has to be inserted if true. */
1158 bool fVTag;
1159 /** TX: TCI part of VLAN tag to be inserted. */
1160 uint16_t u16VTagTCI;
1161 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1162 uint32_t u32PayRemain;
1163 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1164 uint16_t u16HdrRemain;
1165 /** TX TSE fallback: Flags from template header. */
1166 uint16_t u16SavedFlags;
1167 /** TX TSE fallback: Partial checksum from template header. */
1168 uint32_t u32SavedCsum;
1169 /** ?: Emulated controller type. */
1170 E1KCHIP eChip;
1171
1172 /** EMT: Physical interface emulation. */
1173 PHY phy;
1174
1175#if 0
1176 /** Alignment padding. */
1177 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1178#endif
1179
1180 STAMCOUNTER StatReceiveBytes;
1181 STAMCOUNTER StatTransmitBytes;
1182#if defined(VBOX_WITH_STATISTICS)
1183 STAMPROFILEADV StatMMIOReadRZ;
1184 STAMPROFILEADV StatMMIOReadR3;
1185 STAMPROFILEADV StatMMIOWriteRZ;
1186 STAMPROFILEADV StatMMIOWriteR3;
1187 STAMPROFILEADV StatEEPROMRead;
1188 STAMPROFILEADV StatEEPROMWrite;
1189 STAMPROFILEADV StatIOReadRZ;
1190 STAMPROFILEADV StatIOReadR3;
1191 STAMPROFILEADV StatIOWriteRZ;
1192 STAMPROFILEADV StatIOWriteR3;
1193 STAMPROFILEADV StatLateIntTimer;
1194 STAMCOUNTER StatLateInts;
1195 STAMCOUNTER StatIntsRaised;
1196 STAMCOUNTER StatIntsPrevented;
1197 STAMPROFILEADV StatReceive;
1198 STAMPROFILEADV StatReceiveCRC;
1199 STAMPROFILEADV StatReceiveFilter;
1200 STAMPROFILEADV StatReceiveStore;
1201 STAMPROFILEADV StatTransmitRZ;
1202 STAMPROFILEADV StatTransmitR3;
1203 STAMPROFILE StatTransmitSendRZ;
1204 STAMPROFILE StatTransmitSendR3;
1205 STAMPROFILE StatRxOverflow;
1206 STAMCOUNTER StatRxOverflowWakeupRZ;
1207 STAMCOUNTER StatRxOverflowWakeupR3;
1208 STAMCOUNTER StatTxDescCtxNormal;
1209 STAMCOUNTER StatTxDescCtxTSE;
1210 STAMCOUNTER StatTxDescLegacy;
1211 STAMCOUNTER StatTxDescData;
1212 STAMCOUNTER StatTxDescTSEData;
1213 STAMCOUNTER StatTxPathFallback;
1214 STAMCOUNTER StatTxPathGSO;
1215 STAMCOUNTER StatTxPathRegular;
1216 STAMCOUNTER StatPHYAccesses;
1217 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1218 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1219#endif /* VBOX_WITH_STATISTICS */
1220
1221#ifdef E1K_INT_STATS
1222 /* Internal stats */
1223 uint64_t u64ArmedAt;
1224 uint64_t uStatMaxTxDelay;
1225 uint32_t uStatInt;
1226 uint32_t uStatIntTry;
1227 uint32_t uStatIntLower;
1228 uint32_t uStatNoIntICR;
1229 int32_t iStatIntLost;
1230 int32_t iStatIntLostOne;
1231 uint32_t uStatIntIMS;
1232 uint32_t uStatIntSkip;
1233 uint32_t uStatIntLate;
1234 uint32_t uStatIntMasked;
1235 uint32_t uStatIntEarly;
1236 uint32_t uStatIntRx;
1237 uint32_t uStatIntTx;
1238 uint32_t uStatIntICS;
1239 uint32_t uStatIntRDTR;
1240 uint32_t uStatIntRXDMT0;
1241 uint32_t uStatIntTXQE;
1242 uint32_t uStatTxNoRS;
1243 uint32_t uStatTxIDE;
1244 uint32_t uStatTxDelayed;
1245 uint32_t uStatTxDelayExp;
1246 uint32_t uStatTAD;
1247 uint32_t uStatTID;
1248 uint32_t uStatRAD;
1249 uint32_t uStatRID;
1250 uint32_t uStatRxFrm;
1251 uint32_t uStatTxFrm;
1252 uint32_t uStatDescCtx;
1253 uint32_t uStatDescDat;
1254 uint32_t uStatDescLeg;
1255 uint32_t uStatTx1514;
1256 uint32_t uStatTx2962;
1257 uint32_t uStatTx4410;
1258 uint32_t uStatTx5858;
1259 uint32_t uStatTx7306;
1260 uint32_t uStatTx8754;
1261 uint32_t uStatTx16384;
1262 uint32_t uStatTx32768;
1263 uint32_t uStatTxLarge;
1264 uint32_t uStatAlign;
1265#endif /* E1K_INT_STATS */
1266} E1KSTATE;
1267/** Pointer to the E1000 device state. */
1268typedef E1KSTATE *PE1KSTATE;
1269
1270/**
1271 * E1000 ring-3 device state
1272 *
1273 * @implements PDMINETWORKDOWN
1274 * @implements PDMINETWORKCONFIG
1275 * @implements PDMILEDPORTS
1276 */
1277typedef struct E1KSTATER3
1278{
1279 PDMIBASE IBase;
1280 PDMINETWORKDOWN INetworkDown;
1281 PDMINETWORKCONFIG INetworkConfig;
1282 /** LED interface */
1283 PDMILEDPORTS ILeds;
1284 /** Attached network driver. */
1285 R3PTRTYPE(PPDMIBASE) pDrvBase;
1286 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1287
1288 /** Pointer to the shared state. */
1289 R3PTRTYPE(PE1KSTATE) pShared;
1290
1291 /** Device instance. */
1292 PPDMDEVINSR3 pDevInsR3;
1293 /** Attached network driver. */
1294 PPDMINETWORKUPR3 pDrvR3;
1295 /** The scatter / gather buffer used for the current outgoing packet. */
1296 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1297
1298 /** EMT: EEPROM emulation */
1299 E1kEEPROM eeprom;
1300} E1KSTATER3;
1301/** Pointer to the E1000 ring-3 device state. */
1302typedef E1KSTATER3 *PE1KSTATER3;
1303
1304
1305/**
1306 * E1000 ring-0 device state
1307 */
1308typedef struct E1KSTATER0
1309{
1310 /** Device instance. */
1311 PPDMDEVINSR0 pDevInsR0;
1312 /** Attached network driver. */
1313 PPDMINETWORKUPR0 pDrvR0;
1314 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1315 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1316} E1KSTATER0;
1317/** Pointer to the E1000 ring-0 device state. */
1318typedef E1KSTATER0 *PE1KSTATER0;
1319
1320
1321/**
1322 * E1000 raw-mode device state
1323 */
1324typedef struct E1KSTATERC
1325{
1326 /** Device instance. */
1327 PPDMDEVINSRC pDevInsRC;
1328 /** Attached network driver. */
1329 PPDMINETWORKUPRC pDrvRC;
1330 /** The scatter / gather buffer used for the current outgoing packet. */
1331 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1332} E1KSTATERC;
1333/** Pointer to the E1000 raw-mode device state. */
1334typedef E1KSTATERC *PE1KSTATERC;
1335
1336
1337/** @def PE1KSTATECC
1338 * Pointer to the instance data for the current context. */
1339#ifdef IN_RING3
1340typedef E1KSTATER3 E1KSTATECC;
1341typedef PE1KSTATER3 PE1KSTATECC;
1342#elif defined(IN_RING0)
1343typedef E1KSTATER0 E1KSTATECC;
1344typedef PE1KSTATER0 PE1KSTATECC;
1345#elif defined(IN_RC)
1346typedef E1KSTATERC E1KSTATECC;
1347typedef PE1KSTATERC PE1KSTATECC;
1348#else
1349# error "Not IN_RING3, IN_RING0 or IN_RC"
1350#endif
1351
1352
1353#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1354
1355/* Forward declarations ******************************************************/
1356static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1357
1358/**
1359 * E1000 register read handler.
1360 */
1361typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1362/**
1363 * E1000 register write handler.
1364 */
1365typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1366
1367static FNE1KREGREAD e1kRegReadUnimplemented;
1368static FNE1KREGWRITE e1kRegWriteUnimplemented;
1369static FNE1KREGREAD e1kRegReadAutoClear;
1370static FNE1KREGREAD e1kRegReadDefault;
1371static FNE1KREGWRITE e1kRegWriteDefault;
1372#if 0 /* unused */
1373static FNE1KREGREAD e1kRegReadCTRL;
1374#endif
1375static FNE1KREGWRITE e1kRegWriteCTRL;
1376static FNE1KREGREAD e1kRegReadEECD;
1377static FNE1KREGWRITE e1kRegWriteEECD;
1378static FNE1KREGWRITE e1kRegWriteEERD;
1379static FNE1KREGWRITE e1kRegWriteMDIC;
1380static FNE1KREGREAD e1kRegReadICR;
1381static FNE1KREGWRITE e1kRegWriteICR;
1382static FNE1KREGWRITE e1kRegWriteICS;
1383static FNE1KREGWRITE e1kRegWriteIMS;
1384static FNE1KREGWRITE e1kRegWriteIMC;
1385static FNE1KREGWRITE e1kRegWriteRCTL;
1386static FNE1KREGWRITE e1kRegWritePBA;
1387static FNE1KREGWRITE e1kRegWriteRDT;
1388static FNE1KREGWRITE e1kRegWriteRDTR;
1389static FNE1KREGWRITE e1kRegWriteTDT;
1390static FNE1KREGREAD e1kRegReadMTA;
1391static FNE1KREGWRITE e1kRegWriteMTA;
1392static FNE1KREGREAD e1kRegReadRA;
1393static FNE1KREGWRITE e1kRegWriteRA;
1394static FNE1KREGREAD e1kRegReadVFTA;
1395static FNE1KREGWRITE e1kRegWriteVFTA;
1396
1397/**
1398 * Register map table.
1399 *
1400 * Override pfnRead and pfnWrite to get register-specific behavior.
1401 */
1402static const struct E1kRegMap_st
1403{
1404 /** Register offset in the register space. */
1405 uint32_t offset;
1406 /** Size in bytes. Registers of size > 4 are in fact tables. */
1407 uint32_t size;
1408 /** Readable bits. */
1409 uint32_t readable;
1410 /** Writable bits. */
1411 uint32_t writable;
1412 /** Read callback. */
1413 FNE1KREGREAD *pfnRead;
1414 /** Write callback. */
1415 FNE1KREGWRITE *pfnWrite;
1416 /** Abbreviated name. */
1417 const char *abbrev;
1418 /** Full name. */
1419 const char *name;
1420} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1421{
1422 /* offset size read mask write mask read callback write callback abbrev full name */
1423 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1424 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1425 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1426 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1427 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1428 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1429 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1430 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1431 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1432 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1433 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1434 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1435 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1436 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1437 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1438 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1439 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1440 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1441 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1442 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1443 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1444 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1445 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1446 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1447 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1448 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1449 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1450 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1451 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1452 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1453 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1454 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1455 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1456 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1457 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1458 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1459 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1460 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1461 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1462 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1463 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1464 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1465 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1466 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1467 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1468 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1469 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1470 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1471 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1472 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1473 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1474 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1475 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1476 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1477 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1478 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1479 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1480 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1481 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1482 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1483 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1484 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1485 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1486 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1487 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1488 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1489 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1490 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1491 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1492 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1493 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1494 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1495 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1496 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1497 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1498 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1499 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1500 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1501 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1502 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1503 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1504 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1505 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1506 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1507 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1508 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1509 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1510 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1511 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1512 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1513 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1514 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1515 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1516 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1517 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1518 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1519 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1520 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1521 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1522 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1523 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1524 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1525 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1526 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1527 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1528 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1529 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1530 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1531 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1532 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1533 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1534 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1535 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1536 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1537 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1538 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1539 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1540 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1541 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1542 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1543 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1544 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1545 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1546 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1547 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1548 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1549 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1550 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1551 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1552 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1553 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1554 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1555 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1556 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1557 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1558};
1559
1560#ifdef LOG_ENABLED
1561
1562/**
1563 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1564 *
1565 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1566 *
1567 * @returns The buffer.
1568 *
1569 * @param u32 The word to convert into string.
1570 * @param mask Selects which bytes to convert.
1571 * @param buf Where to put the result.
1572 */
1573static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1574{
1575 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1576 {
1577 if (mask & 0xF)
1578 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1579 else
1580 *ptr = '.';
1581 }
1582 buf[8] = 0;
1583 return buf;
1584}
1585
1586/**
1587 * Returns timer name for debug purposes.
1588 *
1589 * @returns The timer name.
1590 *
1591 * @param pThis The device state structure.
1592 * @param hTimer The timer to name.
1593 */
1594DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1595{
1596 if (hTimer == pThis->hTIDTimer)
1597 return "TID";
1598 if (hTimer == pThis->hTADTimer)
1599 return "TAD";
1600 if (hTimer == pThis->hRIDTimer)
1601 return "RID";
1602 if (hTimer == pThis->hRADTimer)
1603 return "RAD";
1604 if (hTimer == pThis->hIntTimer)
1605 return "Int";
1606 if (hTimer == pThis->hTXDTimer)
1607 return "TXD";
1608 if (hTimer == pThis->hLUTimer)
1609 return "LinkUp";
1610 return "unknown";
1611}
1612
1613#endif /* LOG_ENABLED */
1614
1615/**
1616 * Arm a timer.
1617 *
1618 * @param pDevIns The device instance.
1619 * @param pThis Pointer to the device state structure.
1620 * @param hTimer The timer to arm.
1621 * @param uExpireIn Expiration interval in microseconds.
1622 */
1623DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1624{
1625 if (pThis->fLocked)
1626 return;
1627
1628 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1629 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1630 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1631 AssertRC(rc);
1632}
1633
1634#ifdef IN_RING3
1635/**
1636 * Cancel a timer.
1637 *
1638 * @param pDevIns The device instance.
1639 * @param pThis Pointer to the device state structure.
1640 * @param pTimer Pointer to the timer.
1641 */
1642DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1643{
1644 E1kLog2(("%s Stopping %s timer...\n",
1645 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1646 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1647 if (RT_FAILURE(rc))
1648 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1649 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1650 RT_NOREF_PV(pThis);
1651}
1652#endif /* IN_RING3 */
1653
1654#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1655#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1656
1657#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1658#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1659#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1660
1661#ifndef E1K_WITH_TX_CS
1662# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1663# define e1kCsTxLeave(ps) do { } while (0)
1664#else /* E1K_WITH_TX_CS */
1665# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1666# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1667#endif /* E1K_WITH_TX_CS */
1668
1669
1670/**
1671 * Wakeup the RX thread.
1672 */
1673static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1674{
1675 if ( pThis->fMaybeOutOfSpace
1676 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1677 {
1678 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1679 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1680 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1681 AssertRC(rc);
1682 }
1683}
1684
1685#ifdef IN_RING3
1686
1687/**
1688 * Hardware reset. Revert all registers to initial values.
1689 *
1690 * @param pDevIns The device instance.
1691 * @param pThis The device state structure.
1692 * @param pThisCC The current context instance data.
1693 */
1694static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1695{
1696 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1697 /* No interrupts should survive device reset, see @bugref(9556). */
1698 if (pThis->fIntRaised)
1699 {
1700 /* Lower(0) INTA(0) */
1701 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1702 pThis->fIntRaised = false;
1703 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1704 }
1705 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1706 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1707#ifdef E1K_INIT_RA0
1708 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1709 sizeof(pThis->macConfigured.au8));
1710 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1711#endif /* E1K_INIT_RA0 */
1712 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1713 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1714 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1715 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1716 Assert(GET_BITS(RCTL, BSIZE) == 0);
1717 pThis->u16RxBSize = 2048;
1718
1719 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1720 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1721 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1722
1723 /* Reset promiscuous mode */
1724 if (pThisCC->pDrvR3)
1725 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1726
1727#ifdef E1K_WITH_TXD_CACHE
1728 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1729 if (RT_LIKELY(rc == VINF_SUCCESS))
1730 {
1731 pThis->nTxDFetched = 0;
1732 pThis->iTxDCurrent = 0;
1733 pThis->fGSO = false;
1734 pThis->cbTxAlloc = 0;
1735 e1kCsTxLeave(pThis);
1736 }
1737#endif /* E1K_WITH_TXD_CACHE */
1738#ifdef E1K_WITH_RXD_CACHE
1739 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1740 {
1741 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1742 e1kCsRxLeave(pThis);
1743 }
1744#endif /* E1K_WITH_RXD_CACHE */
1745#ifdef E1K_LSC_ON_RESET
1746 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1747 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1748 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1749#endif /* E1K_LSC_ON_RESET */
1750}
1751
1752#endif /* IN_RING3 */
1753
1754/**
1755 * Compute Internet checksum.
1756 *
1757 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1758 *
1759 * @param pThis The device state structure.
1760 * @param cpPacket The packet.
1761 * @param cb The size of the packet.
1762 * @param pszText A string denoting direction of packet transfer.
1763 *
1764 * @return The 1's complement of the 1's complement sum.
1765 *
1766 * @thread E1000_TX
1767 */
1768static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1769{
1770 uint32_t csum = 0;
1771 uint16_t *pu16 = (uint16_t *)pvBuf;
1772
1773 while (cb > 1)
1774 {
1775 csum += *pu16++;
1776 cb -= 2;
1777 }
1778 if (cb)
1779 csum += *(uint8_t*)pu16;
1780 while (csum >> 16)
1781 csum = (csum >> 16) + (csum & 0xFFFF);
1782 return ~csum;
1783}
1784
1785/**
1786 * Dump a packet to debug log.
1787 *
1788 * @param pDevIns The device instance.
1789 * @param pThis The device state structure.
1790 * @param cpPacket The packet.
1791 * @param cb The size of the packet.
1792 * @param pszText A string denoting direction of packet transfer.
1793 * @thread E1000_TX
1794 */
1795DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1796{
1797#ifdef DEBUG
1798 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1799 {
1800 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1801 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1802 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1803 {
1804 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1805 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1806 if (*(cpPacket+14+6) == 0x6)
1807 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1808 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1809 }
1810 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1811 {
1812 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1813 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1814 if (*(cpPacket+14+6) == 0x6)
1815 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1816 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1817 }
1818 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1819 e1kCsLeave(pThis);
1820 }
1821#else
1822 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1823 {
1824 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1825 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1826 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1827 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1828 else
1829 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1830 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1831 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1832 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1833 e1kCsLeave(pThis);
1834 }
1835 RT_NOREF2(cb, pszText);
1836#endif
1837}
1838
1839/**
1840 * Determine the type of transmit descriptor.
1841 *
1842 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1843 *
1844 * @param pDesc Pointer to descriptor union.
1845 * @thread E1000_TX
1846 */
1847DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1848{
1849 if (pDesc->legacy.cmd.fDEXT)
1850 return pDesc->context.dw2.u4DTYP;
1851 return E1K_DTYP_LEGACY;
1852}
1853
1854
1855#ifdef E1K_WITH_RXD_CACHE
1856/**
1857 * Return the number of RX descriptor that belong to the hardware.
1858 *
1859 * @returns the number of available descriptors in RX ring.
1860 * @param pThis The device state structure.
1861 * @thread ???
1862 */
1863DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
1864{
1865 /**
1866 * Make sure RDT won't change during computation. EMT may modify RDT at
1867 * any moment.
1868 */
1869 uint32_t rdt = RDT;
1870 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
1871}
1872
1873DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1874{
1875 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1876 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1877}
1878
1879DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1880{
1881 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1882}
1883
1884/**
1885 * Load receive descriptors from guest memory. The caller needs to be in Rx
1886 * critical section.
1887 *
1888 * We need two physical reads in case the tail wrapped around the end of RX
1889 * descriptor ring.
1890 *
1891 * @returns the actual number of descriptors fetched.
1892 * @param pDevIns The device instance.
1893 * @param pThis The device state structure.
1894 * @thread EMT, RX
1895 */
1896DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1897{
1898 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1899 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
1900 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1901 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
1902 Assert(nDescsTotal != 0);
1903 if (nDescsTotal == 0)
1904 return 0;
1905 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
1906 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
1907 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
1908 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
1909 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
1910 nFirstNotLoaded, nDescsInSingleRead));
1911 if (nDescsToFetch == 0)
1912 return 0;
1913 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
1914 PDMDevHlpPhysRead(pDevIns,
1915 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
1916 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
1917 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
1918 // unsigned i, j;
1919 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
1920 // {
1921 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
1922 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1923 // }
1924 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
1925 pThis->szPrf, nDescsInSingleRead,
1926 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
1927 nFirstNotLoaded, RDLEN, RDH, RDT));
1928 if (nDescsToFetch > nDescsInSingleRead)
1929 {
1930 PDMDevHlpPhysRead(pDevIns,
1931 ((uint64_t)RDBAH << 32) + RDBAL,
1932 pFirstEmptyDesc + nDescsInSingleRead,
1933 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
1934 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
1935 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
1936 // {
1937 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
1938 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1939 // }
1940 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
1941 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
1942 RDBAH, RDBAL));
1943 }
1944 pThis->nRxDFetched += nDescsToFetch;
1945 return nDescsToFetch;
1946}
1947
1948# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
1949/**
1950 * Dump receive descriptor to debug log.
1951 *
1952 * @param pThis The device state structure.
1953 * @param pDesc Pointer to the descriptor.
1954 * @thread E1000_RX
1955 */
1956static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
1957{
1958 RT_NOREF2(pThis, pDesc);
1959 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1960 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1961 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1962 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1963 pDesc->status.fPIF ? "PIF" : "pif",
1964 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1965 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1966 pDesc->status.fVP ? "VP" : "vp",
1967 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1968 pDesc->status.fEOP ? "EOP" : "eop",
1969 pDesc->status.fDD ? "DD" : "dd",
1970 pDesc->status.fRXE ? "RXE" : "rxe",
1971 pDesc->status.fIPE ? "IPE" : "ipe",
1972 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1973 pDesc->status.fCE ? "CE" : "ce",
1974 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1975 E1K_SPEC_VLAN(pDesc->status.u16Special),
1976 E1K_SPEC_PRI(pDesc->status.u16Special)));
1977}
1978# endif /* IN_RING3 */
1979#endif /* E1K_WITH_RXD_CACHE */
1980
1981/**
1982 * Dump transmit descriptor to debug log.
1983 *
1984 * @param pThis The device state structure.
1985 * @param pDesc Pointer to descriptor union.
1986 * @param pszDir A string denoting direction of descriptor transfer
1987 * @thread E1000_TX
1988 */
1989static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
1990 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1991{
1992 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
1993
1994 /*
1995 * Unfortunately we cannot use our format handler here, we want R0 logging
1996 * as well.
1997 */
1998 switch (e1kGetDescType(pDesc))
1999 {
2000 case E1K_DTYP_CONTEXT:
2001 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2002 pThis->szPrf, pszDir, pszDir));
2003 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2004 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2005 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2006 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2007 pDesc->context.dw2.fIDE ? " IDE":"",
2008 pDesc->context.dw2.fRS ? " RS" :"",
2009 pDesc->context.dw2.fTSE ? " TSE":"",
2010 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2011 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2012 pDesc->context.dw2.u20PAYLEN,
2013 pDesc->context.dw3.u8HDRLEN,
2014 pDesc->context.dw3.u16MSS,
2015 pDesc->context.dw3.fDD?"DD":""));
2016 break;
2017 case E1K_DTYP_DATA:
2018 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2019 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2020 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2021 pDesc->data.u64BufAddr,
2022 pDesc->data.cmd.u20DTALEN));
2023 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2024 pDesc->data.cmd.fIDE ? " IDE" :"",
2025 pDesc->data.cmd.fVLE ? " VLE" :"",
2026 pDesc->data.cmd.fRPS ? " RPS" :"",
2027 pDesc->data.cmd.fRS ? " RS" :"",
2028 pDesc->data.cmd.fTSE ? " TSE" :"",
2029 pDesc->data.cmd.fIFCS? " IFCS":"",
2030 pDesc->data.cmd.fEOP ? " EOP" :"",
2031 pDesc->data.dw3.fDD ? " DD" :"",
2032 pDesc->data.dw3.fEC ? " EC" :"",
2033 pDesc->data.dw3.fLC ? " LC" :"",
2034 pDesc->data.dw3.fTXSM? " TXSM":"",
2035 pDesc->data.dw3.fIXSM? " IXSM":"",
2036 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2037 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2038 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2039 break;
2040 case E1K_DTYP_LEGACY:
2041 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2042 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2043 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2044 pDesc->data.u64BufAddr,
2045 pDesc->legacy.cmd.u16Length));
2046 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2047 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2048 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2049 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2050 pDesc->legacy.cmd.fRS ? " RS" :"",
2051 pDesc->legacy.cmd.fIC ? " IC" :"",
2052 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2053 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2054 pDesc->legacy.dw3.fDD ? " DD" :"",
2055 pDesc->legacy.dw3.fEC ? " EC" :"",
2056 pDesc->legacy.dw3.fLC ? " LC" :"",
2057 pDesc->legacy.cmd.u8CSO,
2058 pDesc->legacy.dw3.u8CSS,
2059 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2060 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2061 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2062 break;
2063 default:
2064 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2065 pThis->szPrf, pszDir, pszDir));
2066 break;
2067 }
2068}
2069
2070/**
2071 * Raise an interrupt later.
2072 *
2073 * @param pThis The device state structure.
2074 */
2075DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2076{
2077 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2078 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2079}
2080
2081/**
2082 * Raise interrupt if not masked.
2083 *
2084 * @param pThis The device state structure.
2085 */
2086static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
2087{
2088 int rc = e1kCsEnter(pThis, rcBusy);
2089 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2090 return rc;
2091
2092 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2093 ICR |= u32IntCause;
2094 if (ICR & IMS)
2095 {
2096 if (pThis->fIntRaised)
2097 {
2098 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2099 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2100 pThis->szPrf, ICR & IMS));
2101 }
2102 else
2103 {
2104 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2105 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2106 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2107 {
2108 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2109 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2110 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2111 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2112 }
2113 else
2114 {
2115
2116 /* Since we are delivering the interrupt now
2117 * there is no need to do it later -- stop the timer.
2118 */
2119 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2120 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2121 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2122 /* Got at least one unmasked interrupt cause */
2123 pThis->fIntRaised = true;
2124 /* Raise(1) INTA(0) */
2125 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2126 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2127 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2128 pThis->szPrf, ICR & IMS));
2129 }
2130 }
2131 }
2132 else
2133 {
2134 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2135 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2136 pThis->szPrf, ICR, IMS));
2137 }
2138 e1kCsLeave(pThis);
2139 return VINF_SUCCESS;
2140}
2141
2142/**
2143 * Compute the physical address of the descriptor.
2144 *
2145 * @returns the physical address of the descriptor.
2146 *
2147 * @param baseHigh High-order 32 bits of descriptor table address.
2148 * @param baseLow Low-order 32 bits of descriptor table address.
2149 * @param idxDesc The descriptor index in the table.
2150 */
2151DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2152{
2153 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2154 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2155}
2156
2157#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2158/**
2159 * Advance the head pointer of the receive descriptor queue.
2160 *
2161 * @remarks RDH always points to the next available RX descriptor.
2162 *
2163 * @param pDevIns The device instance.
2164 * @param pThis The device state structure.
2165 */
2166DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2167{
2168 Assert(e1kCsRxIsOwner(pThis));
2169 //e1kCsEnter(pThis, RT_SRC_POS);
2170 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
2171 RDH = 0;
2172#ifdef E1K_WITH_RXD_CACHE
2173 /*
2174 * We need to fetch descriptors now as the guest may advance RDT all the way
2175 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2176 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2177 * check if the receiver is enabled. It must be, otherwise we won't get here
2178 * in the first place.
2179 *
2180 * Note that we should have moved both RDH and iRxDCurrent by now.
2181 */
2182 if (e1kRxDIsCacheEmpty(pThis))
2183 {
2184 /* Cache is empty, reset it and check if we can fetch more. */
2185 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2186 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2187 "iRxDCurrent=%x nRxDFetched=%x\n",
2188 pThis->szPrf, RDH, RDT, pThis->iRxDCurrent, pThis->nRxDFetched));
2189 e1kRxDPrefetch(pDevIns, pThis);
2190 }
2191#endif /* E1K_WITH_RXD_CACHE */
2192 /*
2193 * Compute current receive queue length and fire RXDMT0 interrupt
2194 * if we are low on receive buffers
2195 */
2196 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
2197 /*
2198 * The minimum threshold is controlled by RDMTS bits of RCTL:
2199 * 00 = 1/2 of RDLEN
2200 * 01 = 1/4 of RDLEN
2201 * 10 = 1/8 of RDLEN
2202 * 11 = reserved
2203 */
2204 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2205 if (uRQueueLen <= uMinRQThreshold)
2206 {
2207 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
2208 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2209 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
2210 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2211 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2212 }
2213 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2214 pThis->szPrf, RDH, RDT, uRQueueLen));
2215 //e1kCsLeave(pThis);
2216}
2217#endif /* IN_RING3 */
2218
2219#ifdef E1K_WITH_RXD_CACHE
2220
2221# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2222
2223/**
2224 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2225 * RX ring if the cache is empty.
2226 *
2227 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2228 * go out of sync with RDH which will cause trouble when EMT checks if the
2229 * cache is empty to do pre-fetch @bugref(6217).
2230 *
2231 * @param pDevIns The device instance.
2232 * @param pThis The device state structure.
2233 * @thread RX
2234 */
2235DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2236{
2237 Assert(e1kCsRxIsOwner(pThis));
2238 /* Check the cache first. */
2239 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2240 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2241 /* Cache is empty, reset it and check if we can fetch more. */
2242 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2243 if (e1kRxDPrefetch(pDevIns, pThis))
2244 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2245 /* Out of Rx descriptors. */
2246 return NULL;
2247}
2248
2249
2250/**
2251 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2252 * pointer. The descriptor gets written back to the RXD ring.
2253 *
2254 * @param pDevIns The device instance.
2255 * @param pThis The device state structure.
2256 * @param pDesc The descriptor being "returned" to the RX ring.
2257 * @thread RX
2258 */
2259DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc)
2260{
2261 Assert(e1kCsRxIsOwner(pThis));
2262 pThis->iRxDCurrent++;
2263 // Assert(pDesc >= pThis->aRxDescriptors);
2264 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2265 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2266 // uint32_t rdh = RDH;
2267 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2268 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2269 /*
2270 * We need to print the descriptor before advancing RDH as it may fetch new
2271 * descriptors into the cache.
2272 */
2273 e1kPrintRDesc(pThis, pDesc);
2274 e1kAdvanceRDH(pDevIns, pThis);
2275}
2276
2277/**
2278 * Store a fragment of received packet at the specifed address.
2279 *
2280 * @param pDevIns The device instance.
2281 * @param pThis The device state structure.
2282 * @param pDesc The next available RX descriptor.
2283 * @param pvBuf The fragment.
2284 * @param cb The size of the fragment.
2285 */
2286static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2287{
2288 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2289 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2290 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2291 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2292 pDesc->u16Length = (uint16_t)cb;
2293 Assert(pDesc->u16Length == cb);
2294 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2295 RT_NOREF(pThis);
2296}
2297
2298# endif /* IN_RING3 */
2299
2300#else /* !E1K_WITH_RXD_CACHE */
2301
2302/**
2303 * Store a fragment of received packet that fits into the next available RX
2304 * buffer.
2305 *
2306 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2307 *
2308 * @param pDevIns The device instance.
2309 * @param pThis The device state structure.
2310 * @param pDesc The next available RX descriptor.
2311 * @param pvBuf The fragment.
2312 * @param cb The size of the fragment.
2313 */
2314static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2315{
2316 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2317 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2318 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2319 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2320 /* Write back the descriptor */
2321 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2322 e1kPrintRDesc(pThis, pDesc);
2323 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2324 /* Advance head */
2325 e1kAdvanceRDH(pDevIns, pThis);
2326 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2327 if (pDesc->status.fEOP)
2328 {
2329 /* Complete packet has been stored -- it is time to let the guest know. */
2330#ifdef E1K_USE_RX_TIMERS
2331 if (RDTR)
2332 {
2333 /* Arm the timer to fire in RDTR usec (discard .024) */
2334 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2335 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2336 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2337 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2338 }
2339 else
2340 {
2341#endif
2342 /* 0 delay means immediate interrupt */
2343 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2344 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2345#ifdef E1K_USE_RX_TIMERS
2346 }
2347#endif
2348 }
2349 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2350}
2351
2352#endif /* !E1K_WITH_RXD_CACHE */
2353
2354/**
2355 * Returns true if it is a broadcast packet.
2356 *
2357 * @returns true if destination address indicates broadcast.
2358 * @param pvBuf The ethernet packet.
2359 */
2360DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2361{
2362 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2363 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2364}
2365
2366/**
2367 * Returns true if it is a multicast packet.
2368 *
2369 * @remarks returns true for broadcast packets as well.
2370 * @returns true if destination address indicates multicast.
2371 * @param pvBuf The ethernet packet.
2372 */
2373DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2374{
2375 return (*(char*)pvBuf) & 1;
2376}
2377
2378#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2379/**
2380 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2381 *
2382 * @remarks We emulate checksum offloading for major packets types only.
2383 *
2384 * @returns VBox status code.
2385 * @param pThis The device state structure.
2386 * @param pFrame The available data.
2387 * @param cb Number of bytes available in the buffer.
2388 * @param status Bit fields containing status info.
2389 */
2390static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2391{
2392 /** @todo
2393 * It is not safe to bypass checksum verification for packets coming
2394 * from real wire. We currently unable to tell where packets are
2395 * coming from so we tell the driver to ignore our checksum flags
2396 * and do verification in software.
2397 */
2398# if 0
2399 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2400
2401 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2402
2403 switch (uEtherType)
2404 {
2405 case 0x800: /* IPv4 */
2406 {
2407 pStatus->fIXSM = false;
2408 pStatus->fIPCS = true;
2409 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2410 /* TCP/UDP checksum offloading works with TCP and UDP only */
2411 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2412 break;
2413 }
2414 case 0x86DD: /* IPv6 */
2415 pStatus->fIXSM = false;
2416 pStatus->fIPCS = false;
2417 pStatus->fTCPCS = true;
2418 break;
2419 default: /* ARP, VLAN, etc. */
2420 pStatus->fIXSM = true;
2421 break;
2422 }
2423# else
2424 pStatus->fIXSM = true;
2425 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2426# endif
2427 return VINF_SUCCESS;
2428}
2429#endif /* IN_RING3 */
2430
2431/**
2432 * Pad and store received packet.
2433 *
2434 * @remarks Make sure that the packet appears to upper layer as one coming
2435 * from real Ethernet: pad it and insert FCS.
2436 *
2437 * @returns VBox status code.
2438 * @param pDevIns The device instance.
2439 * @param pThis The device state structure.
2440 * @param pvBuf The available data.
2441 * @param cb Number of bytes available in the buffer.
2442 * @param status Bit fields containing status info.
2443 */
2444static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2445{
2446#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2447 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2448 uint8_t *ptr = rxPacket;
2449
2450 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2451 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2452 return rc;
2453
2454 if (cb > 70) /* unqualified guess */
2455 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2456
2457 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2458 Assert(cb > 16);
2459 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2460 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2461 if (status.fVP)
2462 {
2463 /* VLAN packet -- strip VLAN tag in VLAN mode */
2464 if ((CTRL & CTRL_VME) && cb > 16)
2465 {
2466 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2467 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2468 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2469 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2470 cb -= 4;
2471 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2472 pThis->szPrf, status.u16Special, cb));
2473 }
2474 else
2475 status.fVP = false; /* Set VP only if we stripped the tag */
2476 }
2477 else
2478 memcpy(rxPacket, pvBuf, cb);
2479 /* Pad short packets */
2480 if (cb < 60)
2481 {
2482 memset(rxPacket + cb, 0, 60 - cb);
2483 cb = 60;
2484 }
2485 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2486 {
2487 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2488 /*
2489 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2490 * is ignored by most of drivers we may as well save us the trouble
2491 * of calculating it (see EthernetCRC CFGM parameter).
2492 */
2493 if (pThis->fEthernetCRC)
2494 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2495 cb += sizeof(uint32_t);
2496 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2497 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2498 }
2499 /* Compute checksum of complete packet */
2500 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2501 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2502 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2503
2504 /* Update stats */
2505 E1K_INC_CNT32(GPRC);
2506 if (e1kIsBroadcast(pvBuf))
2507 E1K_INC_CNT32(BPRC);
2508 else if (e1kIsMulticast(pvBuf))
2509 E1K_INC_CNT32(MPRC);
2510 /* Update octet receive counter */
2511 E1K_ADD_CNT64(GORCL, GORCH, cb);
2512 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2513 if (cb == 64)
2514 E1K_INC_CNT32(PRC64);
2515 else if (cb < 128)
2516 E1K_INC_CNT32(PRC127);
2517 else if (cb < 256)
2518 E1K_INC_CNT32(PRC255);
2519 else if (cb < 512)
2520 E1K_INC_CNT32(PRC511);
2521 else if (cb < 1024)
2522 E1K_INC_CNT32(PRC1023);
2523 else
2524 E1K_INC_CNT32(PRC1522);
2525
2526 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2527
2528# ifdef E1K_WITH_RXD_CACHE
2529 while (cb > 0)
2530 {
2531 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis);
2532
2533 if (pDesc == NULL)
2534 {
2535 E1kLog(("%s Out of receive buffers, dropping the packet "
2536 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2537 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2538 break;
2539 }
2540# else /* !E1K_WITH_RXD_CACHE */
2541 if (RDH == RDT)
2542 {
2543 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2544 pThis->szPrf));
2545 }
2546 /* Store the packet to receive buffers */
2547 while (RDH != RDT)
2548 {
2549 /* Load the descriptor pointed by head */
2550 E1KRXDESC desc, *pDesc = &desc;
2551 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2552# endif /* !E1K_WITH_RXD_CACHE */
2553 if (pDesc->u64BufAddr)
2554 {
2555 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2556
2557 /* Update descriptor */
2558 pDesc->status = status;
2559 pDesc->u16Checksum = checksum;
2560 pDesc->status.fDD = true;
2561
2562 /*
2563 * We need to leave Rx critical section here or we risk deadlocking
2564 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2565 * page or has an access handler associated with it.
2566 * Note that it is safe to leave the critical section here since
2567 * e1kRegWriteRDT() never modifies RDH. It never touches already
2568 * fetched RxD cache entries either.
2569 */
2570 if (cb > u16RxBufferSize)
2571 {
2572 pDesc->status.fEOP = false;
2573 e1kCsRxLeave(pThis);
2574 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2575 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2576 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2577 return rc;
2578 ptr += u16RxBufferSize;
2579 cb -= u16RxBufferSize;
2580 }
2581 else
2582 {
2583 pDesc->status.fEOP = true;
2584 e1kCsRxLeave(pThis);
2585 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2586# ifdef E1K_WITH_RXD_CACHE
2587 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2588 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2589 return rc;
2590 cb = 0;
2591# else /* !E1K_WITH_RXD_CACHE */
2592 pThis->led.Actual.s.fReading = 0;
2593 return VINF_SUCCESS;
2594# endif /* !E1K_WITH_RXD_CACHE */
2595 }
2596 /*
2597 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2598 * is not defined.
2599 */
2600 }
2601# ifdef E1K_WITH_RXD_CACHE
2602 /* Write back the descriptor. */
2603 pDesc->status.fDD = true;
2604 e1kRxDPut(pDevIns, pThis, pDesc);
2605# else /* !E1K_WITH_RXD_CACHE */
2606 else
2607 {
2608 /* Write back the descriptor. */
2609 pDesc->status.fDD = true;
2610 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2611 e1kAdvanceRDH(pDevIns, pThis);
2612 }
2613# endif /* !E1K_WITH_RXD_CACHE */
2614 }
2615
2616 if (cb > 0)
2617 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2618
2619 pThis->led.Actual.s.fReading = 0;
2620
2621 e1kCsRxLeave(pThis);
2622# ifdef E1K_WITH_RXD_CACHE
2623 /* Complete packet has been stored -- it is time to let the guest know. */
2624# ifdef E1K_USE_RX_TIMERS
2625 if (RDTR)
2626 {
2627 /* Arm the timer to fire in RDTR usec (discard .024) */
2628 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2629 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2630 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2631 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2632 }
2633 else
2634 {
2635# endif /* E1K_USE_RX_TIMERS */
2636 /* 0 delay means immediate interrupt */
2637 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2638 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2639# ifdef E1K_USE_RX_TIMERS
2640 }
2641# endif /* E1K_USE_RX_TIMERS */
2642# endif /* E1K_WITH_RXD_CACHE */
2643
2644 return VINF_SUCCESS;
2645#else /* !IN_RING3 */
2646 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2647 return VERR_INTERNAL_ERROR_2;
2648#endif /* !IN_RING3 */
2649}
2650
2651
2652#ifdef IN_RING3
2653/**
2654 * Bring the link up after the configured delay, 5 seconds by default.
2655 *
2656 * @param pDevIns The device instance.
2657 * @param pThis The device state structure.
2658 * @thread any
2659 */
2660DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2661{
2662 E1kLog(("%s Will bring up the link in %d seconds...\n",
2663 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2664 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2665}
2666
2667/**
2668 * Bring up the link immediately.
2669 *
2670 * @param pDevIns The device instance.
2671 * @param pThis The device state structure.
2672 * @param pThisCC The current context instance data.
2673 */
2674DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2675{
2676 E1kLog(("%s Link is up\n", pThis->szPrf));
2677 STATUS |= STATUS_LU;
2678 Phy::setLinkStatus(&pThis->phy, true);
2679 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2680 if (pThisCC->pDrvR3)
2681 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2682 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2683 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2684}
2685
2686/**
2687 * Bring down the link immediately.
2688 *
2689 * @param pDevIns The device instance.
2690 * @param pThis The device state structure.
2691 * @param pThisCC The current context instance data.
2692 */
2693DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2694{
2695 E1kLog(("%s Link is down\n", pThis->szPrf));
2696 STATUS &= ~STATUS_LU;
2697#ifdef E1K_LSC_ON_RESET
2698 Phy::setLinkStatus(&pThis->phy, false);
2699#endif /* E1K_LSC_ON_RESET */
2700 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2701 if (pThisCC->pDrvR3)
2702 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2703}
2704
2705/**
2706 * Bring down the link temporarily.
2707 *
2708 * @param pDevIns The device instance.
2709 * @param pThis The device state structure.
2710 * @param pThisCC The current context instance data.
2711 */
2712DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2713{
2714 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2715 STATUS &= ~STATUS_LU;
2716 Phy::setLinkStatus(&pThis->phy, false);
2717 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2718 /*
2719 * Notifying the associated driver that the link went down (even temporarily)
2720 * seems to be the right thing, but it was not done before. This may cause
2721 * a regression if the driver does not expect the link to go down as a result
2722 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2723 * of code notified the driver that the link was up! See @bugref{7057}.
2724 */
2725 if (pThisCC->pDrvR3)
2726 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2727 e1kBringLinkUpDelayed(pDevIns, pThis);
2728}
2729#endif /* IN_RING3 */
2730
2731#if 0 /* unused */
2732/**
2733 * Read handler for Device Status register.
2734 *
2735 * Get the link status from PHY.
2736 *
2737 * @returns VBox status code.
2738 *
2739 * @param pThis The device state structure.
2740 * @param offset Register offset in memory-mapped frame.
2741 * @param index Register index in register array.
2742 * @param mask Used to implement partial reads (8 and 16-bit).
2743 */
2744static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2745{
2746 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2747 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2748 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2749 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2750 {
2751 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2752 if (Phy::readMDIO(&pThis->phy))
2753 *pu32Value = CTRL | CTRL_MDIO;
2754 else
2755 *pu32Value = CTRL & ~CTRL_MDIO;
2756 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2757 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2758 }
2759 else
2760 {
2761 /* MDIO pin is used for output, ignore it */
2762 *pu32Value = CTRL;
2763 }
2764 return VINF_SUCCESS;
2765}
2766#endif /* unused */
2767
2768/**
2769 * A callback used by PHY to indicate that the link needs to be updated due to
2770 * reset of PHY.
2771 *
2772 * @param pDevIns The device instance.
2773 * @thread any
2774 */
2775void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2776{
2777 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2778
2779 /* Make sure we have cable connected and MAC can talk to PHY */
2780 if (pThis->fCableConnected && (CTRL & CTRL_SLU))
2781 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2782}
2783
2784/**
2785 * Write handler for Device Control register.
2786 *
2787 * Handles reset.
2788 *
2789 * @param pThis The device state structure.
2790 * @param offset Register offset in memory-mapped frame.
2791 * @param index Register index in register array.
2792 * @param value The value to store.
2793 * @param mask Used to implement partial writes (8 and 16-bit).
2794 * @thread EMT
2795 */
2796static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2797{
2798 int rc = VINF_SUCCESS;
2799
2800 if (value & CTRL_RESET)
2801 { /* RST */
2802#ifndef IN_RING3
2803 return VINF_IOM_R3_MMIO_WRITE;
2804#else
2805 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2806#endif
2807 }
2808 else
2809 {
2810#ifdef E1K_LSC_ON_SLU
2811 /*
2812 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2813 * the link is down and the cable is connected, and if they are we
2814 * bring the link up, see @bugref{8624}.
2815 */
2816 if ( (value & CTRL_SLU)
2817 && !(CTRL & CTRL_SLU)
2818 && pThis->fCableConnected
2819 && !(STATUS & STATUS_LU))
2820 {
2821 /* It should take about 2 seconds for the link to come up */
2822 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2823 }
2824#else /* !E1K_LSC_ON_SLU */
2825 if ( (value & CTRL_SLU)
2826 && !(CTRL & CTRL_SLU)
2827 && pThis->fCableConnected
2828 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2829 {
2830 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2831 STATUS |= STATUS_LU;
2832 }
2833#endif /* !E1K_LSC_ON_SLU */
2834 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2835 {
2836 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2837 }
2838 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2839 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2840 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2841 if (value & CTRL_MDC)
2842 {
2843 if (value & CTRL_MDIO_DIR)
2844 {
2845 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2846 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2847 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2848 }
2849 else
2850 {
2851 if (Phy::readMDIO(&pThis->phy))
2852 value |= CTRL_MDIO;
2853 else
2854 value &= ~CTRL_MDIO;
2855 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2856 }
2857 }
2858 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2859 }
2860
2861 return rc;
2862}
2863
2864/**
2865 * Write handler for EEPROM/Flash Control/Data register.
2866 *
2867 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2868 *
2869 * @param pThis The device state structure.
2870 * @param offset Register offset in memory-mapped frame.
2871 * @param index Register index in register array.
2872 * @param value The value to store.
2873 * @param mask Used to implement partial writes (8 and 16-bit).
2874 * @thread EMT
2875 */
2876static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2877{
2878 RT_NOREF(pDevIns, offset, index);
2879#ifdef IN_RING3
2880 /* So far we are concerned with lower byte only */
2881 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2882 {
2883 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2884 /* Note: 82543GC does not need to request EEPROM access */
2885 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2886 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2887 pThisCC->eeprom.write(value & EECD_EE_WIRES);
2888 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2889 }
2890 if (value & EECD_EE_REQ)
2891 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2892 else
2893 EECD &= ~EECD_EE_GNT;
2894 //e1kRegWriteDefault(pThis, offset, index, value );
2895
2896 return VINF_SUCCESS;
2897#else /* !IN_RING3 */
2898 RT_NOREF(pThis, value);
2899 return VINF_IOM_R3_MMIO_WRITE;
2900#endif /* !IN_RING3 */
2901}
2902
2903/**
2904 * Read handler for EEPROM/Flash Control/Data register.
2905 *
2906 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2907 *
2908 * @returns VBox status code.
2909 *
2910 * @param pThis The device state structure.
2911 * @param offset Register offset in memory-mapped frame.
2912 * @param index Register index in register array.
2913 * @param mask Used to implement partial reads (8 and 16-bit).
2914 * @thread EMT
2915 */
2916static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2917{
2918#ifdef IN_RING3
2919 uint32_t value;
2920 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
2921 if (RT_SUCCESS(rc))
2922 {
2923 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2924 {
2925 /* Note: 82543GC does not need to request EEPROM access */
2926 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2927 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2928 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2929 value |= pThisCC->eeprom.read();
2930 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2931 }
2932 *pu32Value = value;
2933 }
2934
2935 return rc;
2936#else /* !IN_RING3 */
2937 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
2938 return VINF_IOM_R3_MMIO_READ;
2939#endif /* !IN_RING3 */
2940}
2941
2942/**
2943 * Write handler for EEPROM Read register.
2944 *
2945 * Handles EEPROM word access requests, reads EEPROM and stores the result
2946 * into DATA field.
2947 *
2948 * @param pThis The device state structure.
2949 * @param offset Register offset in memory-mapped frame.
2950 * @param index Register index in register array.
2951 * @param value The value to store.
2952 * @param mask Used to implement partial writes (8 and 16-bit).
2953 * @thread EMT
2954 */
2955static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2956{
2957#ifdef IN_RING3
2958 /* Make use of 'writable' and 'readable' masks. */
2959 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2960 /* DONE and DATA are set only if read was triggered by START. */
2961 if (value & EERD_START)
2962 {
2963 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2964 uint16_t tmp;
2965 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2966 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2967 SET_BITS(EERD, DATA, tmp);
2968 EERD |= EERD_DONE;
2969 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2970 }
2971
2972 return VINF_SUCCESS;
2973#else /* !IN_RING3 */
2974 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
2975 return VINF_IOM_R3_MMIO_WRITE;
2976#endif /* !IN_RING3 */
2977}
2978
2979
2980/**
2981 * Write handler for MDI Control register.
2982 *
2983 * Handles PHY read/write requests; forwards requests to internal PHY device.
2984 *
2985 * @param pThis The device state structure.
2986 * @param offset Register offset in memory-mapped frame.
2987 * @param index Register index in register array.
2988 * @param value The value to store.
2989 * @param mask Used to implement partial writes (8 and 16-bit).
2990 * @thread EMT
2991 */
2992static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2993{
2994 if (value & MDIC_INT_EN)
2995 {
2996 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2997 pThis->szPrf));
2998 }
2999 else if (value & MDIC_READY)
3000 {
3001 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3002 pThis->szPrf));
3003 }
3004 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3005 {
3006 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3007 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3008 /*
3009 * Some drivers scan the MDIO bus for a PHY. We can work with these
3010 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3011 * at the requested address, see @bugref{7346}.
3012 */
3013 MDIC = MDIC_READY | MDIC_ERROR;
3014 }
3015 else
3016 {
3017 /* Store the value */
3018 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3019 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3020 /* Forward op to PHY */
3021 if (value & MDIC_OP_READ)
3022 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3023 else
3024 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3025 /* Let software know that we are done */
3026 MDIC |= MDIC_READY;
3027 }
3028
3029 return VINF_SUCCESS;
3030}
3031
3032/**
3033 * Write handler for Interrupt Cause Read register.
3034 *
3035 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3036 *
3037 * @param pThis The device state structure.
3038 * @param offset Register offset in memory-mapped frame.
3039 * @param index Register index in register array.
3040 * @param value The value to store.
3041 * @param mask Used to implement partial writes (8 and 16-bit).
3042 * @thread EMT
3043 */
3044static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3045{
3046 ICR &= ~value;
3047
3048 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3049 return VINF_SUCCESS;
3050}
3051
3052/**
3053 * Read handler for Interrupt Cause Read register.
3054 *
3055 * Reading this register acknowledges all interrupts.
3056 *
3057 * @returns VBox status code.
3058 *
3059 * @param pThis The device state structure.
3060 * @param offset Register offset in memory-mapped frame.
3061 * @param index Register index in register array.
3062 * @param mask Not used.
3063 * @thread EMT
3064 */
3065static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3066{
3067 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3068 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3069 return rc;
3070
3071 uint32_t value = 0;
3072 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3073 if (RT_SUCCESS(rc))
3074 {
3075 if (value)
3076 {
3077 if (!pThis->fIntRaised)
3078 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3079 /*
3080 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3081 * with disabled interrupts.
3082 */
3083 //if (IMS)
3084 if (1)
3085 {
3086 /*
3087 * Interrupts were enabled -- we are supposedly at the very
3088 * beginning of interrupt handler
3089 */
3090 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3091 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3092 /* Clear all pending interrupts */
3093 ICR = 0;
3094 pThis->fIntRaised = false;
3095 /* Lower(0) INTA(0) */
3096 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3097
3098 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3099 if (pThis->fIntMaskUsed)
3100 pThis->fDelayInts = true;
3101 }
3102 else
3103 {
3104 /*
3105 * Interrupts are disabled -- in windows guests ICR read is done
3106 * just before re-enabling interrupts
3107 */
3108 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3109 }
3110 }
3111 *pu32Value = value;
3112 }
3113 e1kCsLeave(pThis);
3114
3115 return rc;
3116}
3117
3118/**
3119 * Write handler for Interrupt Cause Set register.
3120 *
3121 * Bits corresponding to 1s in 'value' will be set in ICR register.
3122 *
3123 * @param pThis The device state structure.
3124 * @param offset Register offset in memory-mapped frame.
3125 * @param index Register index in register array.
3126 * @param value The value to store.
3127 * @param mask Used to implement partial writes (8 and 16-bit).
3128 * @thread EMT
3129 */
3130static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3131{
3132 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3133 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3134 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3135}
3136
3137/**
3138 * Write handler for Interrupt Mask Set register.
3139 *
3140 * Will trigger pending interrupts.
3141 *
3142 * @param pThis The device state structure.
3143 * @param offset Register offset in memory-mapped frame.
3144 * @param index Register index in register array.
3145 * @param value The value to store.
3146 * @param mask Used to implement partial writes (8 and 16-bit).
3147 * @thread EMT
3148 */
3149static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3150{
3151 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3152
3153 IMS |= value;
3154 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3155 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3156 /*
3157 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3158 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3159 */
3160 if ((ICR & IMS) && !pThis->fLocked)
3161 {
3162 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3163 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3164 }
3165
3166 return VINF_SUCCESS;
3167}
3168
3169/**
3170 * Write handler for Interrupt Mask Clear register.
3171 *
3172 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3173 *
3174 * @param pThis The device state structure.
3175 * @param offset Register offset in memory-mapped frame.
3176 * @param index Register index in register array.
3177 * @param value The value to store.
3178 * @param mask Used to implement partial writes (8 and 16-bit).
3179 * @thread EMT
3180 */
3181static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3182{
3183 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3184
3185 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3186 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3187 return rc;
3188 if (pThis->fIntRaised)
3189 {
3190 /*
3191 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3192 * Windows to freeze since it may receive an interrupt while still in the very beginning
3193 * of interrupt handler.
3194 */
3195 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3196 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3197 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3198 /* Lower(0) INTA(0) */
3199 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3200 pThis->fIntRaised = false;
3201 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3202 }
3203 IMS &= ~value;
3204 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3205 e1kCsLeave(pThis);
3206
3207 return VINF_SUCCESS;
3208}
3209
3210/**
3211 * Write handler for Receive Control register.
3212 *
3213 * @param pThis The device state structure.
3214 * @param offset Register offset in memory-mapped frame.
3215 * @param index Register index in register array.
3216 * @param value The value to store.
3217 * @param mask Used to implement partial writes (8 and 16-bit).
3218 * @thread EMT
3219 */
3220static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3221{
3222 /* Update promiscuous mode */
3223 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3224 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3225 {
3226 /* Promiscuity has changed, pass the knowledge on. */
3227#ifndef IN_RING3
3228 return VINF_IOM_R3_MMIO_WRITE;
3229#else
3230 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3231 if (pThisCC->pDrvR3)
3232 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3233#endif
3234 }
3235
3236 /* Adjust receive buffer size */
3237 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3238 if (value & RCTL_BSEX)
3239 cbRxBuf *= 16;
3240 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3241 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3242 if (cbRxBuf != pThis->u16RxBSize)
3243 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3244 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3245 pThis->u16RxBSize = cbRxBuf;
3246
3247 /* Update the register */
3248 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3249}
3250
3251/**
3252 * Write handler for Packet Buffer Allocation register.
3253 *
3254 * TXA = 64 - RXA.
3255 *
3256 * @param pThis The device state structure.
3257 * @param offset Register offset in memory-mapped frame.
3258 * @param index Register index in register array.
3259 * @param value The value to store.
3260 * @param mask Used to implement partial writes (8 and 16-bit).
3261 * @thread EMT
3262 */
3263static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3264{
3265 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3266 PBA_st->txa = 64 - PBA_st->rxa;
3267
3268 return VINF_SUCCESS;
3269}
3270
3271/**
3272 * Write handler for Receive Descriptor Tail register.
3273 *
3274 * @remarks Write into RDT forces switch to HC and signal to
3275 * e1kR3NetworkDown_WaitReceiveAvail().
3276 *
3277 * @returns VBox status code.
3278 *
3279 * @param pThis The device state structure.
3280 * @param offset Register offset in memory-mapped frame.
3281 * @param index Register index in register array.
3282 * @param value The value to store.
3283 * @param mask Used to implement partial writes (8 and 16-bit).
3284 * @thread EMT
3285 */
3286static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3287{
3288#ifndef IN_RING3
3289 /* XXX */
3290// return VINF_IOM_R3_MMIO_WRITE;
3291#endif
3292 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3293 if (RT_LIKELY(rc == VINF_SUCCESS))
3294 {
3295 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3296#ifndef E1K_WITH_RXD_CACHE
3297 /*
3298 * Some drivers advance RDT too far, so that it equals RDH. This
3299 * somehow manages to work with real hardware but not with this
3300 * emulated device. We can work with these drivers if we just
3301 * write 1 less when we see a driver writing RDT equal to RDH,
3302 * see @bugref{7346}.
3303 */
3304 if (value == RDH)
3305 {
3306 if (RDH == 0)
3307 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3308 else
3309 value = RDH - 1;
3310 }
3311#endif /* !E1K_WITH_RXD_CACHE */
3312 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3313#ifdef E1K_WITH_RXD_CACHE
3314 /*
3315 * We need to fetch descriptors now as RDT may go whole circle
3316 * before we attempt to store a received packet. For example,
3317 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3318 * size being only 8 descriptors! Note that we fetch descriptors
3319 * only when the cache is empty to reduce the number of memory reads
3320 * in case of frequent RDT writes. Don't fetch anything when the
3321 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3322 * messed up state.
3323 * Note that despite the cache may seem empty, meaning that there are
3324 * no more available descriptors in it, it may still be used by RX
3325 * thread which has not yet written the last descriptor back but has
3326 * temporarily released the RX lock in order to write the packet body
3327 * to descriptor's buffer. At this point we still going to do prefetch
3328 * but it won't actually fetch anything if there are no unused slots in
3329 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3330 * reset the cache here even if it appears empty. It will be reset at
3331 * a later point in e1kRxDGet().
3332 */
3333 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3334 e1kRxDPrefetch(pDevIns, pThis);
3335#endif /* E1K_WITH_RXD_CACHE */
3336 e1kCsRxLeave(pThis);
3337 if (RT_SUCCESS(rc))
3338 {
3339 /* Signal that we have more receive descriptors available. */
3340 e1kWakeupReceive(pDevIns, pThis);
3341 }
3342 }
3343 return rc;
3344}
3345
3346/**
3347 * Write handler for Receive Delay Timer register.
3348 *
3349 * @param pThis The device state structure.
3350 * @param offset Register offset in memory-mapped frame.
3351 * @param index Register index in register array.
3352 * @param value The value to store.
3353 * @param mask Used to implement partial writes (8 and 16-bit).
3354 * @thread EMT
3355 */
3356static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3357{
3358 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3359 if (value & RDTR_FPD)
3360 {
3361 /* Flush requested, cancel both timers and raise interrupt */
3362#ifdef E1K_USE_RX_TIMERS
3363 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3364 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3365#endif
3366 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3367 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3368 }
3369
3370 return VINF_SUCCESS;
3371}
3372
3373DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3374{
3375 /**
3376 * Make sure TDT won't change during computation. EMT may modify TDT at
3377 * any moment.
3378 */
3379 uint32_t tdt = TDT;
3380 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3381}
3382
3383#ifdef IN_RING3
3384
3385# ifdef E1K_TX_DELAY
3386/**
3387 * Transmit Delay Timer handler.
3388 *
3389 * @remarks We only get here when the timer expires.
3390 *
3391 * @param pDevIns Pointer to device instance structure.
3392 * @param pTimer Pointer to the timer.
3393 * @param pvUser NULL.
3394 * @thread EMT
3395 */
3396static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3397{
3398 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3399 Assert(PDMCritSectIsOwner(&pThis->csTx));
3400
3401 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3402# ifdef E1K_INT_STATS
3403 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3404 if (u64Elapsed > pThis->uStatMaxTxDelay)
3405 pThis->uStatMaxTxDelay = u64Elapsed;
3406# endif
3407 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3408 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3409}
3410# endif /* E1K_TX_DELAY */
3411
3412//# ifdef E1K_USE_TX_TIMERS
3413
3414/**
3415 * Transmit Interrupt Delay Timer handler.
3416 *
3417 * @remarks We only get here when the timer expires.
3418 *
3419 * @param pDevIns Pointer to device instance structure.
3420 * @param pTimer Pointer to the timer.
3421 * @param pvUser NULL.
3422 * @thread EMT
3423 */
3424static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3425{
3426 RT_NOREF(pDevIns);
3427 RT_NOREF(pTimer);
3428 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3429
3430 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3431 /* Cancel absolute delay timer as we have already got attention */
3432# ifndef E1K_NO_TAD
3433 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3434# endif
3435 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3436}
3437
3438/**
3439 * Transmit Absolute Delay Timer handler.
3440 *
3441 * @remarks We only get here when the timer expires.
3442 *
3443 * @param pDevIns Pointer to device instance structure.
3444 * @param pTimer Pointer to the timer.
3445 * @param pvUser NULL.
3446 * @thread EMT
3447 */
3448static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3449{
3450 RT_NOREF(pDevIns);
3451 RT_NOREF(pTimer);
3452 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3453
3454 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3455 /* Cancel interrupt delay timer as we have already got attention */
3456 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3457 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3458}
3459
3460//# endif /* E1K_USE_TX_TIMERS */
3461# ifdef E1K_USE_RX_TIMERS
3462
3463/**
3464 * Receive Interrupt Delay Timer handler.
3465 *
3466 * @remarks We only get here when the timer expires.
3467 *
3468 * @param pDevIns Pointer to device instance structure.
3469 * @param pTimer Pointer to the timer.
3470 * @param pvUser NULL.
3471 * @thread EMT
3472 */
3473static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3474{
3475 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3476
3477 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3478 /* Cancel absolute delay timer as we have already got attention */
3479 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3480 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3481}
3482
3483/**
3484 * Receive Absolute Delay Timer handler.
3485 *
3486 * @remarks We only get here when the timer expires.
3487 *
3488 * @param pDevIns Pointer to device instance structure.
3489 * @param pTimer Pointer to the timer.
3490 * @param pvUser NULL.
3491 * @thread EMT
3492 */
3493static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3494{
3495 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3496
3497 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3498 /* Cancel interrupt delay timer as we have already got attention */
3499 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3500 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3501}
3502
3503# endif /* E1K_USE_RX_TIMERS */
3504
3505/**
3506 * Late Interrupt Timer handler.
3507 *
3508 * @param pDevIns Pointer to device instance structure.
3509 * @param pTimer Pointer to the timer.
3510 * @param pvUser NULL.
3511 * @thread EMT
3512 */
3513static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3514{
3515 RT_NOREF(pDevIns, pTimer);
3516 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3517
3518 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3519 STAM_COUNTER_INC(&pThis->StatLateInts);
3520 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3521# if 0
3522 if (pThis->iStatIntLost > -100)
3523 pThis->iStatIntLost--;
3524# endif
3525 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3526 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3527}
3528
3529/**
3530 * Link Up Timer handler.
3531 *
3532 * @param pDevIns Pointer to device instance structure.
3533 * @param pTimer Pointer to the timer.
3534 * @param pvUser NULL.
3535 * @thread EMT
3536 */
3537static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3538{
3539 RT_NOREF(pTimer);
3540 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3541 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3542
3543 /*
3544 * This can happen if we set the link status to down when the Link up timer was
3545 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3546 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3547 * on reset even if the cable is unplugged (see @bugref{8942}).
3548 */
3549 if (pThis->fCableConnected)
3550 {
3551 /* 82543GC does not have an internal PHY */
3552 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3553 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3554 }
3555# ifdef E1K_LSC_ON_RESET
3556 else if (pThis->eChip == E1K_CHIP_82543GC)
3557 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3558# endif /* E1K_LSC_ON_RESET */
3559}
3560
3561#endif /* IN_RING3 */
3562
3563/**
3564 * Sets up the GSO context according to the TSE new context descriptor.
3565 *
3566 * @param pGso The GSO context to setup.
3567 * @param pCtx The context descriptor.
3568 */
3569DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3570{
3571 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3572
3573 /*
3574 * See if the context descriptor describes something that could be TCP or
3575 * UDP over IPv[46].
3576 */
3577 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3578 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3579 {
3580 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3581 return;
3582 }
3583 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3584 {
3585 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3586 return;
3587 }
3588 if (RT_UNLIKELY( pCtx->dw2.fTCP
3589 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3590 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3591 {
3592 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3593 return;
3594 }
3595
3596 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3597 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3598 {
3599 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3600 return;
3601 }
3602
3603 /* IPv4 checksum offset. */
3604 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3605 {
3606 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3607 return;
3608 }
3609
3610 /* TCP/UDP checksum offsets. */
3611 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3612 != ( pCtx->dw2.fTCP
3613 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3614 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3615 {
3616 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3617 return;
3618 }
3619
3620 /*
3621 * Because of internal networking using a 16-bit size field for GSO context
3622 * plus frame, we have to make sure we don't exceed this.
3623 */
3624 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3625 {
3626 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3627 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3628 return;
3629 }
3630
3631 /*
3632 * We're good for now - we'll do more checks when seeing the data.
3633 * So, figure the type of offloading and setup the context.
3634 */
3635 if (pCtx->dw2.fIP)
3636 {
3637 if (pCtx->dw2.fTCP)
3638 {
3639 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3640 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3641 }
3642 else
3643 {
3644 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3645 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3646 }
3647 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3648 * this yet it seems)... */
3649 }
3650 else
3651 {
3652 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3653 if (pCtx->dw2.fTCP)
3654 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3655 else
3656 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3657 }
3658 pGso->offHdr1 = pCtx->ip.u8CSS;
3659 pGso->offHdr2 = pCtx->tu.u8CSS;
3660 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3661 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3662 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3663 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3664 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3665}
3666
3667/**
3668 * Checks if we can use GSO processing for the current TSE frame.
3669 *
3670 * @param pThis The device state structure.
3671 * @param pGso The GSO context.
3672 * @param pData The first data descriptor of the frame.
3673 * @param pCtx The TSO context descriptor.
3674 */
3675DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3676{
3677 if (!pData->cmd.fTSE)
3678 {
3679 E1kLog2(("e1kCanDoGso: !TSE\n"));
3680 return false;
3681 }
3682 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3683 {
3684 E1kLog(("e1kCanDoGso: VLE\n"));
3685 return false;
3686 }
3687 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3688 {
3689 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3690 return false;
3691 }
3692
3693 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3694 {
3695 case PDMNETWORKGSOTYPE_IPV4_TCP:
3696 case PDMNETWORKGSOTYPE_IPV4_UDP:
3697 if (!pData->dw3.fIXSM)
3698 {
3699 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3700 return false;
3701 }
3702 if (!pData->dw3.fTXSM)
3703 {
3704 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3705 return false;
3706 }
3707 /** @todo what more check should we perform here? Ethernet frame type? */
3708 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3709 return true;
3710
3711 case PDMNETWORKGSOTYPE_IPV6_TCP:
3712 case PDMNETWORKGSOTYPE_IPV6_UDP:
3713 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3714 {
3715 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3716 return false;
3717 }
3718 if (!pData->dw3.fTXSM)
3719 {
3720 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3721 return false;
3722 }
3723 /** @todo what more check should we perform here? Ethernet frame type? */
3724 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3725 return true;
3726
3727 default:
3728 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3729 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3730 return false;
3731 }
3732}
3733
3734/**
3735 * Frees the current xmit buffer.
3736 *
3737 * @param pThis The device state structure.
3738 */
3739static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3740{
3741 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3742 if (pSg)
3743 {
3744 pThisCC->CTX_SUFF(pTxSg) = NULL;
3745
3746 if (pSg->pvAllocator != pThis)
3747 {
3748 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3749 if (pDrv)
3750 pDrv->pfnFreeBuf(pDrv, pSg);
3751 }
3752 else
3753 {
3754 /* loopback */
3755 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3756 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3757 pSg->fFlags = 0;
3758 pSg->pvAllocator = NULL;
3759 }
3760 }
3761}
3762
3763#ifndef E1K_WITH_TXD_CACHE
3764/**
3765 * Allocates an xmit buffer.
3766 *
3767 * @returns See PDMINETWORKUP::pfnAllocBuf.
3768 * @param pThis The device state structure.
3769 * @param cbMin The minimum frame size.
3770 * @param fExactSize Whether cbMin is exact or if we have to max it
3771 * out to the max MTU size.
3772 * @param fGso Whether this is a GSO frame or not.
3773 */
3774DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3775{
3776 /* Adjust cbMin if necessary. */
3777 if (!fExactSize)
3778 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3779
3780 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3781 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3782 e1kXmitFreeBuf(pThis, pThisCC);
3783 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3784
3785 /*
3786 * Allocate the buffer.
3787 */
3788 PPDMSCATTERGATHER pSg;
3789 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3790 {
3791 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3792 if (RT_UNLIKELY(!pDrv))
3793 return VERR_NET_DOWN;
3794 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3795 if (RT_FAILURE(rc))
3796 {
3797 /* Suspend TX as we are out of buffers atm */
3798 STATUS |= STATUS_TXOFF;
3799 return rc;
3800 }
3801 }
3802 else
3803 {
3804 /* Create a loopback using the fallback buffer and preallocated SG. */
3805 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3806 pSg = &pThis->uTxFallback.Sg;
3807 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3808 pSg->cbUsed = 0;
3809 pSg->cbAvailable = 0;
3810 pSg->pvAllocator = pThis;
3811 pSg->pvUser = NULL; /* No GSO here. */
3812 pSg->cSegs = 1;
3813 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3814 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3815 }
3816
3817 pThisCC->CTX_SUFF(pTxSg) = pSg;
3818 return VINF_SUCCESS;
3819}
3820#else /* E1K_WITH_TXD_CACHE */
3821/**
3822 * Allocates an xmit buffer.
3823 *
3824 * @returns See PDMINETWORKUP::pfnAllocBuf.
3825 * @param pThis The device state structure.
3826 * @param cbMin The minimum frame size.
3827 * @param fExactSize Whether cbMin is exact or if we have to max it
3828 * out to the max MTU size.
3829 * @param fGso Whether this is a GSO frame or not.
3830 */
3831DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3832{
3833 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3834 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3835 e1kXmitFreeBuf(pThis, pThisCC);
3836 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3837
3838 /*
3839 * Allocate the buffer.
3840 */
3841 PPDMSCATTERGATHER pSg;
3842 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3843 {
3844 if (pThis->cbTxAlloc == 0)
3845 {
3846 /* Zero packet, no need for the buffer */
3847 return VINF_SUCCESS;
3848 }
3849
3850 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3851 if (RT_UNLIKELY(!pDrv))
3852 return VERR_NET_DOWN;
3853 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3854 if (RT_FAILURE(rc))
3855 {
3856 /* Suspend TX as we are out of buffers atm */
3857 STATUS |= STATUS_TXOFF;
3858 return rc;
3859 }
3860 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3861 pThis->szPrf, pThis->cbTxAlloc,
3862 pThis->fVTag ? "VLAN " : "",
3863 pThis->fGSO ? "GSO " : ""));
3864 }
3865 else
3866 {
3867 /* Create a loopback using the fallback buffer and preallocated SG. */
3868 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3869 pSg = &pThis->uTxFallback.Sg;
3870 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3871 pSg->cbUsed = 0;
3872 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
3873 pSg->pvAllocator = pThis;
3874 pSg->pvUser = NULL; /* No GSO here. */
3875 pSg->cSegs = 1;
3876 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3877 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3878 }
3879 pThis->cbTxAlloc = 0;
3880
3881 pThisCC->CTX_SUFF(pTxSg) = pSg;
3882 return VINF_SUCCESS;
3883}
3884#endif /* E1K_WITH_TXD_CACHE */
3885
3886/**
3887 * Checks if it's a GSO buffer or not.
3888 *
3889 * @returns true / false.
3890 * @param pTxSg The scatter / gather buffer.
3891 */
3892DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3893{
3894#if 0
3895 if (!pTxSg)
3896 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3897 if (pTxSg && pTxSg->pvUser)
3898 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3899#endif
3900 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3901}
3902
3903#ifndef E1K_WITH_TXD_CACHE
3904/**
3905 * Load transmit descriptor from guest memory.
3906 *
3907 * @param pDevIns The device instance.
3908 * @param pDesc Pointer to descriptor union.
3909 * @param addr Physical address in guest context.
3910 * @thread E1000_TX
3911 */
3912DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
3913{
3914 PDMDevHlpPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
3915}
3916#else /* E1K_WITH_TXD_CACHE */
3917/**
3918 * Load transmit descriptors from guest memory.
3919 *
3920 * We need two physical reads in case the tail wrapped around the end of TX
3921 * descriptor ring.
3922 *
3923 * @returns the actual number of descriptors fetched.
3924 * @param pDevIns The device instance.
3925 * @param pThis The device state structure.
3926 * @thread E1000_TX
3927 */
3928DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3929{
3930 Assert(pThis->iTxDCurrent == 0);
3931 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3932 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3933 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3934 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3935 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3936 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3937 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3938 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3939 nFirstNotLoaded, nDescsInSingleRead));
3940 if (nDescsToFetch == 0)
3941 return 0;
3942 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3943 PDMDevHlpPhysRead(pDevIns,
3944 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3945 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3946 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3947 pThis->szPrf, nDescsInSingleRead,
3948 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3949 nFirstNotLoaded, TDLEN, TDH, TDT));
3950 if (nDescsToFetch > nDescsInSingleRead)
3951 {
3952 PDMDevHlpPhysRead(pDevIns,
3953 ((uint64_t)TDBAH << 32) + TDBAL,
3954 pFirstEmptyDesc + nDescsInSingleRead,
3955 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3956 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3957 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3958 TDBAH, TDBAL));
3959 }
3960 pThis->nTxDFetched += nDescsToFetch;
3961 return nDescsToFetch;
3962}
3963
3964/**
3965 * Load transmit descriptors from guest memory only if there are no loaded
3966 * descriptors.
3967 *
3968 * @returns true if there are descriptors in cache.
3969 * @param pDevIns The device instance.
3970 * @param pThis The device state structure.
3971 * @thread E1000_TX
3972 */
3973DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3974{
3975 if (pThis->nTxDFetched == 0)
3976 return e1kTxDLoadMore(pDevIns, pThis) != 0;
3977 return true;
3978}
3979#endif /* E1K_WITH_TXD_CACHE */
3980
3981/**
3982 * Write back transmit descriptor to guest memory.
3983 *
3984 * @param pDevIns The device instance.
3985 * @param pThis The device state structure.
3986 * @param pDesc Pointer to descriptor union.
3987 * @param addr Physical address in guest context.
3988 * @thread E1000_TX
3989 */
3990DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3991{
3992 /* Only the last half of the descriptor has to be written back. */
3993 e1kPrintTDesc(pThis, pDesc, "^^^");
3994 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
3995}
3996
3997/**
3998 * Transmit complete frame.
3999 *
4000 * @remarks We skip the FCS since we're not responsible for sending anything to
4001 * a real ethernet wire.
4002 *
4003 * @param pDevIns The device instance.
4004 * @param pThis The device state structure.
4005 * @param pThisCC The current context instance data.
4006 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4007 * @thread E1000_TX
4008 */
4009static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4010{
4011 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4012 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4013 Assert(!pSg || pSg->cSegs == 1);
4014
4015 if (cbFrame > 70) /* unqualified guess */
4016 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4017
4018#ifdef E1K_INT_STATS
4019 if (cbFrame <= 1514)
4020 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4021 else if (cbFrame <= 2962)
4022 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4023 else if (cbFrame <= 4410)
4024 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4025 else if (cbFrame <= 5858)
4026 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4027 else if (cbFrame <= 7306)
4028 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4029 else if (cbFrame <= 8754)
4030 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4031 else if (cbFrame <= 16384)
4032 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4033 else if (cbFrame <= 32768)
4034 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4035 else
4036 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4037#endif /* E1K_INT_STATS */
4038
4039 /* Add VLAN tag */
4040 if (cbFrame > 12 && pThis->fVTag)
4041 {
4042 E1kLog3(("%s Inserting VLAN tag %08x\n",
4043 pThis->szPrf, RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4044 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4045 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16(VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4046 pSg->cbUsed += 4;
4047 cbFrame += 4;
4048 Assert(pSg->cbUsed == cbFrame);
4049 Assert(pSg->cbUsed <= pSg->cbAvailable);
4050 }
4051/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4052 "%.*Rhxd\n"
4053 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4054 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4055
4056 /* Update the stats */
4057 E1K_INC_CNT32(TPT);
4058 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4059 E1K_INC_CNT32(GPTC);
4060 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4061 E1K_INC_CNT32(BPTC);
4062 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4063 E1K_INC_CNT32(MPTC);
4064 /* Update octet transmit counter */
4065 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4066 if (pThisCC->CTX_SUFF(pDrv))
4067 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4068 if (cbFrame == 64)
4069 E1K_INC_CNT32(PTC64);
4070 else if (cbFrame < 128)
4071 E1K_INC_CNT32(PTC127);
4072 else if (cbFrame < 256)
4073 E1K_INC_CNT32(PTC255);
4074 else if (cbFrame < 512)
4075 E1K_INC_CNT32(PTC511);
4076 else if (cbFrame < 1024)
4077 E1K_INC_CNT32(PTC1023);
4078 else
4079 E1K_INC_CNT32(PTC1522);
4080
4081 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4082
4083 /*
4084 * Dump and send the packet.
4085 */
4086 int rc = VERR_NET_DOWN;
4087 if (pSg && pSg->pvAllocator != pThis)
4088 {
4089 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4090
4091 pThisCC->CTX_SUFF(pTxSg) = NULL;
4092 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4093 if (pDrv)
4094 {
4095 /* Release critical section to avoid deadlock in CanReceive */
4096 //e1kCsLeave(pThis);
4097 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4098 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4099 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4100 //e1kCsEnter(pThis, RT_SRC_POS);
4101 }
4102 }
4103 else if (pSg)
4104 {
4105 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4106 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4107
4108 /** @todo do we actually need to check that we're in loopback mode here? */
4109 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4110 {
4111 E1KRXDST status;
4112 RT_ZERO(status);
4113 status.fPIF = true;
4114 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4115 rc = VINF_SUCCESS;
4116 }
4117 e1kXmitFreeBuf(pThis, pThisCC);
4118 }
4119 else
4120 rc = VERR_NET_DOWN;
4121 if (RT_FAILURE(rc))
4122 {
4123 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4124 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4125 }
4126
4127 pThis->led.Actual.s.fWriting = 0;
4128}
4129
4130/**
4131 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4132 *
4133 * @param pThis The device state structure.
4134 * @param pPkt Pointer to the packet.
4135 * @param u16PktLen Total length of the packet.
4136 * @param cso Offset in packet to write checksum at.
4137 * @param css Offset in packet to start computing
4138 * checksum from.
4139 * @param cse Offset in packet to stop computing
4140 * checksum at.
4141 * @thread E1000_TX
4142 */
4143static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
4144{
4145 RT_NOREF1(pThis);
4146
4147 if (css >= u16PktLen)
4148 {
4149 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4150 pThis->szPrf, cso, u16PktLen));
4151 return;
4152 }
4153
4154 if (cso >= u16PktLen - 1)
4155 {
4156 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4157 pThis->szPrf, cso, u16PktLen));
4158 return;
4159 }
4160
4161 if (cse == 0)
4162 cse = u16PktLen - 1;
4163 else if (cse < css)
4164 {
4165 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4166 pThis->szPrf, css, cse));
4167 return;
4168 }
4169
4170 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4171 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4172 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4173 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4174}
4175
4176/**
4177 * Add a part of descriptor's buffer to transmit frame.
4178 *
4179 * @remarks data.u64BufAddr is used unconditionally for both data
4180 * and legacy descriptors since it is identical to
4181 * legacy.u64BufAddr.
4182 *
4183 * @param pDevIns The device instance.
4184 * @param pThis The device state structure.
4185 * @param pDesc Pointer to the descriptor to transmit.
4186 * @param u16Len Length of buffer to the end of segment.
4187 * @param fSend Force packet sending.
4188 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4189 * @thread E1000_TX
4190 */
4191#ifndef E1K_WITH_TXD_CACHE
4192static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4193{
4194 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4195 /* TCP header being transmitted */
4196 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4197 /* IP header being transmitted */
4198 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4199
4200 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4201 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4202 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4203
4204 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4205 E1kLog3(("%s Dump of the segment:\n"
4206 "%.*Rhxd\n"
4207 "%s --- End of dump ---\n",
4208 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4209 pThis->u16TxPktLen += u16Len;
4210 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4211 pThis->szPrf, pThis->u16TxPktLen));
4212 if (pThis->u16HdrRemain > 0)
4213 {
4214 /* The header was not complete, check if it is now */
4215 if (u16Len >= pThis->u16HdrRemain)
4216 {
4217 /* The rest is payload */
4218 u16Len -= pThis->u16HdrRemain;
4219 pThis->u16HdrRemain = 0;
4220 /* Save partial checksum and flags */
4221 pThis->u32SavedCsum = pTcpHdr->chksum;
4222 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4223 /* Clear FIN and PSH flags now and set them only in the last segment */
4224 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4225 }
4226 else
4227 {
4228 /* Still not */
4229 pThis->u16HdrRemain -= u16Len;
4230 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4231 pThis->szPrf, pThis->u16HdrRemain));
4232 return;
4233 }
4234 }
4235
4236 pThis->u32PayRemain -= u16Len;
4237
4238 if (fSend)
4239 {
4240 /* Leave ethernet header intact */
4241 /* IP Total Length = payload + headers - ethernet header */
4242 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4243 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4244 pThis->szPrf, ntohs(pIpHdr->total_len)));
4245 /* Update IP Checksum */
4246 pIpHdr->chksum = 0;
4247 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4248 pThis->contextTSE.ip.u8CSO,
4249 pThis->contextTSE.ip.u8CSS,
4250 pThis->contextTSE.ip.u16CSE);
4251
4252 /* Update TCP flags */
4253 /* Restore original FIN and PSH flags for the last segment */
4254 if (pThis->u32PayRemain == 0)
4255 {
4256 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4257 E1K_INC_CNT32(TSCTC);
4258 }
4259 /* Add TCP length to partial pseudo header sum */
4260 uint32_t csum = pThis->u32SavedCsum
4261 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4262 while (csum >> 16)
4263 csum = (csum >> 16) + (csum & 0xFFFF);
4264 pTcpHdr->chksum = csum;
4265 /* Compute final checksum */
4266 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4267 pThis->contextTSE.tu.u8CSO,
4268 pThis->contextTSE.tu.u8CSS,
4269 pThis->contextTSE.tu.u16CSE);
4270
4271 /*
4272 * Transmit it. If we've use the SG already, allocate a new one before
4273 * we copy of the data.
4274 */
4275 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4276 if (!pTxSg)
4277 {
4278 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4279 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4280 }
4281 if (pTxSg)
4282 {
4283 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4284 Assert(pTxSg->cSegs == 1);
4285 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4286 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4287 pTxSg->cbUsed = pThis->u16TxPktLen;
4288 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4289 }
4290 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4291
4292 /* Update Sequence Number */
4293 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4294 - pThis->contextTSE.dw3.u8HDRLEN);
4295 /* Increment IP identification */
4296 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4297 }
4298}
4299#else /* E1K_WITH_TXD_CACHE */
4300static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4301{
4302 int rc = VINF_SUCCESS;
4303 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4304 /* TCP header being transmitted */
4305 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4306 /* IP header being transmitted */
4307 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4308
4309 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4310 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4311 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4312
4313 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4314 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4315 else
4316 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4317 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4318 E1kLog3(("%s Dump of the segment:\n"
4319 "%.*Rhxd\n"
4320 "%s --- End of dump ---\n",
4321 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4322 pThis->u16TxPktLen += u16Len;
4323 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4324 pThis->szPrf, pThis->u16TxPktLen));
4325 if (pThis->u16HdrRemain > 0)
4326 {
4327 /* The header was not complete, check if it is now */
4328 if (u16Len >= pThis->u16HdrRemain)
4329 {
4330 /* The rest is payload */
4331 u16Len -= pThis->u16HdrRemain;
4332 pThis->u16HdrRemain = 0;
4333 /* Save partial checksum and flags */
4334 pThis->u32SavedCsum = pTcpHdr->chksum;
4335 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4336 /* Clear FIN and PSH flags now and set them only in the last segment */
4337 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4338 }
4339 else
4340 {
4341 /* Still not */
4342 pThis->u16HdrRemain -= u16Len;
4343 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4344 pThis->szPrf, pThis->u16HdrRemain));
4345 return rc;
4346 }
4347 }
4348
4349 if (u16Len > pThis->u32PayRemain)
4350 pThis->u32PayRemain = 0;
4351 else
4352 pThis->u32PayRemain -= u16Len;
4353
4354 if (fSend)
4355 {
4356 /* Leave ethernet header intact */
4357 /* IP Total Length = payload + headers - ethernet header */
4358 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4359 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4360 pThis->szPrf, ntohs(pIpHdr->total_len)));
4361 /* Update IP Checksum */
4362 pIpHdr->chksum = 0;
4363 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4364 pThis->contextTSE.ip.u8CSO,
4365 pThis->contextTSE.ip.u8CSS,
4366 pThis->contextTSE.ip.u16CSE);
4367
4368 /* Update TCP flags */
4369 /* Restore original FIN and PSH flags for the last segment */
4370 if (pThis->u32PayRemain == 0)
4371 {
4372 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4373 E1K_INC_CNT32(TSCTC);
4374 }
4375 /* Add TCP length to partial pseudo header sum */
4376 uint32_t csum = pThis->u32SavedCsum
4377 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4378 while (csum >> 16)
4379 csum = (csum >> 16) + (csum & 0xFFFF);
4380 pTcpHdr->chksum = csum;
4381 /* Compute final checksum */
4382 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4383 pThis->contextTSE.tu.u8CSO,
4384 pThis->contextTSE.tu.u8CSS,
4385 pThis->contextTSE.tu.u16CSE);
4386
4387 /*
4388 * Transmit it.
4389 */
4390 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4391 if (pTxSg)
4392 {
4393 /* Make sure the packet fits into the allocated buffer */
4394 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4395#ifdef DEBUG
4396 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4397 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4398 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4399#endif /* DEBUG */
4400 Assert(pTxSg->cSegs == 1);
4401 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4402 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4403 pTxSg->cbUsed = cbCopy;
4404 pTxSg->aSegs[0].cbSeg = cbCopy;
4405 }
4406 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4407
4408 /* Update Sequence Number */
4409 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4410 - pThis->contextTSE.dw3.u8HDRLEN);
4411 /* Increment IP identification */
4412 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4413
4414 /* Allocate new buffer for the next segment. */
4415 if (pThis->u32PayRemain)
4416 {
4417 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4418 pThis->contextTSE.dw3.u16MSS)
4419 + pThis->contextTSE.dw3.u8HDRLEN
4420 + (pThis->fVTag ? 4 : 0);
4421 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4422 }
4423 }
4424
4425 return rc;
4426}
4427#endif /* E1K_WITH_TXD_CACHE */
4428
4429#ifndef E1K_WITH_TXD_CACHE
4430/**
4431 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4432 * frame.
4433 *
4434 * We construct the frame in the fallback buffer first and the copy it to the SG
4435 * buffer before passing it down to the network driver code.
4436 *
4437 * @returns true if the frame should be transmitted, false if not.
4438 *
4439 * @param pThis The device state structure.
4440 * @param pDesc Pointer to the descriptor to transmit.
4441 * @param cbFragment Length of descriptor's buffer.
4442 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4443 * @thread E1000_TX
4444 */
4445static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4446{
4447 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4448 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4449 Assert(pDesc->data.cmd.fTSE);
4450 Assert(!e1kXmitIsGsoBuf(pTxSg));
4451
4452 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4453 Assert(u16MaxPktLen != 0);
4454 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4455
4456 /*
4457 * Carve out segments.
4458 */
4459 do
4460 {
4461 /* Calculate how many bytes we have left in this TCP segment */
4462 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4463 if (cb > cbFragment)
4464 {
4465 /* This descriptor fits completely into current segment */
4466 cb = cbFragment;
4467 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4468 }
4469 else
4470 {
4471 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4472 /*
4473 * Rewind the packet tail pointer to the beginning of payload,
4474 * so we continue writing right beyond the header.
4475 */
4476 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4477 }
4478
4479 pDesc->data.u64BufAddr += cb;
4480 cbFragment -= cb;
4481 } while (cbFragment > 0);
4482
4483 if (pDesc->data.cmd.fEOP)
4484 {
4485 /* End of packet, next segment will contain header. */
4486 if (pThis->u32PayRemain != 0)
4487 E1K_INC_CNT32(TSCTFC);
4488 pThis->u16TxPktLen = 0;
4489 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4490 }
4491
4492 return false;
4493}
4494#else /* E1K_WITH_TXD_CACHE */
4495/**
4496 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4497 * frame.
4498 *
4499 * We construct the frame in the fallback buffer first and the copy it to the SG
4500 * buffer before passing it down to the network driver code.
4501 *
4502 * @returns error code
4503 *
4504 * @param pDevIns The device instance.
4505 * @param pThis The device state structure.
4506 * @param pDesc Pointer to the descriptor to transmit.
4507 * @param cbFragment Length of descriptor's buffer.
4508 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4509 * @thread E1000_TX
4510 */
4511static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4512{
4513#ifdef VBOX_STRICT
4514 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4515 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4516 Assert(pDesc->data.cmd.fTSE);
4517 Assert(!e1kXmitIsGsoBuf(pTxSg));
4518#endif
4519
4520 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4521 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4522 if (u16MaxPktLen == 0)
4523 return VINF_SUCCESS;
4524
4525 /*
4526 * Carve out segments.
4527 */
4528 int rc = VINF_SUCCESS;
4529 do
4530 {
4531 /* Calculate how many bytes we have left in this TCP segment */
4532 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4533 if (cb > pDesc->data.cmd.u20DTALEN)
4534 {
4535 /* This descriptor fits completely into current segment */
4536 cb = pDesc->data.cmd.u20DTALEN;
4537 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4538 }
4539 else
4540 {
4541 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4542 /*
4543 * Rewind the packet tail pointer to the beginning of payload,
4544 * so we continue writing right beyond the header.
4545 */
4546 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4547 }
4548
4549 pDesc->data.u64BufAddr += cb;
4550 pDesc->data.cmd.u20DTALEN -= cb;
4551 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4552
4553 if (pDesc->data.cmd.fEOP)
4554 {
4555 /* End of packet, next segment will contain header. */
4556 if (pThis->u32PayRemain != 0)
4557 E1K_INC_CNT32(TSCTFC);
4558 pThis->u16TxPktLen = 0;
4559 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4560 }
4561
4562 return VINF_SUCCESS; /// @todo consider rc;
4563}
4564#endif /* E1K_WITH_TXD_CACHE */
4565
4566
4567/**
4568 * Add descriptor's buffer to transmit frame.
4569 *
4570 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4571 * TSE frames we cannot handle as GSO.
4572 *
4573 * @returns true on success, false on failure.
4574 *
4575 * @param pDevIns The device instance.
4576 * @param pThisCC The current context instance data.
4577 * @param pThis The device state structure.
4578 * @param PhysAddr The physical address of the descriptor buffer.
4579 * @param cbFragment Length of descriptor's buffer.
4580 * @thread E1000_TX
4581 */
4582static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4583{
4584 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4585 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4586 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4587
4588 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4589 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4590 fGso ? "true" : "false"));
4591 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4592 {
4593 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4594 return false;
4595 }
4596 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4597 {
4598 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4599 return false;
4600 }
4601
4602 if (RT_LIKELY(pTxSg))
4603 {
4604 Assert(pTxSg->cSegs == 1);
4605 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4606 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4607 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4608
4609 PDMDevHlpPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4610
4611 pTxSg->cbUsed = cbNewPkt;
4612 }
4613 pThis->u16TxPktLen = cbNewPkt;
4614
4615 return true;
4616}
4617
4618
4619/**
4620 * Write the descriptor back to guest memory and notify the guest.
4621 *
4622 * @param pThis The device state structure.
4623 * @param pDesc Pointer to the descriptor have been transmitted.
4624 * @param addr Physical address of the descriptor in guest memory.
4625 * @thread E1000_TX
4626 */
4627static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4628{
4629 /*
4630 * We fake descriptor write-back bursting. Descriptors are written back as they are
4631 * processed.
4632 */
4633 /* Let's pretend we process descriptors. Write back with DD set. */
4634 /*
4635 * Prior to r71586 we tried to accomodate the case when write-back bursts
4636 * are enabled without actually implementing bursting by writing back all
4637 * descriptors, even the ones that do not have RS set. This caused kernel
4638 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4639 * associated with written back descriptor if it happened to be a context
4640 * descriptor since context descriptors do not have skb associated to them.
4641 * Starting from r71586 we write back only the descriptors with RS set,
4642 * which is a little bit different from what the real hardware does in
4643 * case there is a chain of data descritors where some of them have RS set
4644 * and others do not. It is very uncommon scenario imho.
4645 * We need to check RPS as well since some legacy drivers use it instead of
4646 * RS even with newer cards.
4647 */
4648 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4649 {
4650 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4651 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4652 if (pDesc->legacy.cmd.fEOP)
4653 {
4654//#ifdef E1K_USE_TX_TIMERS
4655 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4656 {
4657 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4658 //if (pThis->fIntRaised)
4659 //{
4660 // /* Interrupt is already pending, no need for timers */
4661 // ICR |= ICR_TXDW;
4662 //}
4663 //else {
4664 /* Arm the timer to fire in TIVD usec (discard .024) */
4665 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4666# ifndef E1K_NO_TAD
4667 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4668 E1kLog2(("%s Checking if TAD timer is running\n",
4669 pThis->szPrf));
4670 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4671 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4672# endif /* E1K_NO_TAD */
4673 }
4674 else
4675 {
4676 if (pThis->fTidEnabled)
4677 {
4678 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4679 pThis->szPrf));
4680 /* Cancel both timers if armed and fire immediately. */
4681# ifndef E1K_NO_TAD
4682 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4683# endif
4684 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4685 }
4686//#endif /* E1K_USE_TX_TIMERS */
4687 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4688 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4689//#ifdef E1K_USE_TX_TIMERS
4690 }
4691//#endif /* E1K_USE_TX_TIMERS */
4692 }
4693 }
4694 else
4695 {
4696 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4697 }
4698}
4699
4700#ifndef E1K_WITH_TXD_CACHE
4701
4702/**
4703 * Process Transmit Descriptor.
4704 *
4705 * E1000 supports three types of transmit descriptors:
4706 * - legacy data descriptors of older format (context-less).
4707 * - data the same as legacy but providing new offloading capabilities.
4708 * - context sets up the context for following data descriptors.
4709 *
4710 * @param pDevIns The device instance.
4711 * @param pThis The device state structure.
4712 * @param pThisCC The current context instance data.
4713 * @param pDesc Pointer to descriptor union.
4714 * @param addr Physical address of descriptor in guest memory.
4715 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4716 * @thread E1000_TX
4717 */
4718static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4719 RTGCPHYS addr, bool fOnWorkerThread)
4720{
4721 int rc = VINF_SUCCESS;
4722 uint32_t cbVTag = 0;
4723
4724 e1kPrintTDesc(pThis, pDesc, "vvv");
4725
4726//#ifdef E1K_USE_TX_TIMERS
4727 if (pThis->fTidEnabled)
4728 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4729//#endif /* E1K_USE_TX_TIMERS */
4730
4731 switch (e1kGetDescType(pDesc))
4732 {
4733 case E1K_DTYP_CONTEXT:
4734 if (pDesc->context.dw2.fTSE)
4735 {
4736 pThis->contextTSE = pDesc->context;
4737 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4738 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4739 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4740 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4741 }
4742 else
4743 {
4744 pThis->contextNormal = pDesc->context;
4745 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4746 }
4747 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4748 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4749 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4750 pDesc->context.ip.u8CSS,
4751 pDesc->context.ip.u8CSO,
4752 pDesc->context.ip.u16CSE,
4753 pDesc->context.tu.u8CSS,
4754 pDesc->context.tu.u8CSO,
4755 pDesc->context.tu.u16CSE));
4756 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4757 e1kDescReport(pThis, pDesc, addr);
4758 break;
4759
4760 case E1K_DTYP_DATA:
4761 {
4762 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4763 {
4764 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4765 /** @todo Same as legacy when !TSE. See below. */
4766 break;
4767 }
4768 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4769 &pThis->StatTxDescTSEData:
4770 &pThis->StatTxDescData);
4771 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4772 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4773
4774 /*
4775 * The last descriptor of non-TSE packet must contain VLE flag.
4776 * TSE packets have VLE flag in the first descriptor. The later
4777 * case is taken care of a bit later when cbVTag gets assigned.
4778 *
4779 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4780 */
4781 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4782 {
4783 pThis->fVTag = pDesc->data.cmd.fVLE;
4784 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4785 }
4786 /*
4787 * First fragment: Allocate new buffer and save the IXSM and TXSM
4788 * packet options as these are only valid in the first fragment.
4789 */
4790 if (pThis->u16TxPktLen == 0)
4791 {
4792 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4793 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4794 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4795 pThis->fIPcsum ? " IP" : "",
4796 pThis->fTCPcsum ? " TCP/UDP" : ""));
4797 if (pDesc->data.cmd.fTSE)
4798 {
4799 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4800 pThis->fVTag = pDesc->data.cmd.fVLE;
4801 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4802 cbVTag = pThis->fVTag ? 4 : 0;
4803 }
4804 else if (pDesc->data.cmd.fEOP)
4805 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4806 else
4807 cbVTag = 4;
4808 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4809 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4810 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4811 true /*fExactSize*/, true /*fGso*/);
4812 else if (pDesc->data.cmd.fTSE)
4813 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4814 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4815 else
4816 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4817 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4818
4819 /**
4820 * @todo: Perhaps it is not that simple for GSO packets! We may
4821 * need to unwind some changes.
4822 */
4823 if (RT_FAILURE(rc))
4824 {
4825 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4826 break;
4827 }
4828 /** @todo Is there any way to indicating errors other than collisions? Like
4829 * VERR_NET_DOWN. */
4830 }
4831
4832 /*
4833 * Add the descriptor data to the frame. If the frame is complete,
4834 * transmit it and reset the u16TxPktLen field.
4835 */
4836 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
4837 {
4838 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4839 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4840 if (pDesc->data.cmd.fEOP)
4841 {
4842 if ( fRc
4843 && pThisCC->CTX_SUFF(pTxSg)
4844 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4845 {
4846 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4847 E1K_INC_CNT32(TSCTC);
4848 }
4849 else
4850 {
4851 if (fRc)
4852 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4853 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
4854 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4855 e1kXmitFreeBuf(pThis);
4856 E1K_INC_CNT32(TSCTFC);
4857 }
4858 pThis->u16TxPktLen = 0;
4859 }
4860 }
4861 else if (!pDesc->data.cmd.fTSE)
4862 {
4863 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4864 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4865 if (pDesc->data.cmd.fEOP)
4866 {
4867 if (fRc && pThisCC->CTX_SUFF(pTxSg))
4868 {
4869 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
4870 if (pThis->fIPcsum)
4871 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4872 pThis->contextNormal.ip.u8CSO,
4873 pThis->contextNormal.ip.u8CSS,
4874 pThis->contextNormal.ip.u16CSE);
4875 if (pThis->fTCPcsum)
4876 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4877 pThis->contextNormal.tu.u8CSO,
4878 pThis->contextNormal.tu.u8CSS,
4879 pThis->contextNormal.tu.u16CSE);
4880 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4881 }
4882 else
4883 e1kXmitFreeBuf(pThis);
4884 pThis->u16TxPktLen = 0;
4885 }
4886 }
4887 else
4888 {
4889 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4890 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4891 }
4892
4893 e1kDescReport(pThis, pDesc, addr);
4894 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4895 break;
4896 }
4897
4898 case E1K_DTYP_LEGACY:
4899 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4900 {
4901 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4902 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4903 break;
4904 }
4905 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4906 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4907
4908 /* First fragment: allocate new buffer. */
4909 if (pThis->u16TxPktLen == 0)
4910 {
4911 if (pDesc->legacy.cmd.fEOP)
4912 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4913 else
4914 cbVTag = 4;
4915 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4916 /** @todo reset status bits? */
4917 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4918 if (RT_FAILURE(rc))
4919 {
4920 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4921 break;
4922 }
4923
4924 /** @todo Is there any way to indicating errors other than collisions? Like
4925 * VERR_NET_DOWN. */
4926 }
4927
4928 /* Add fragment to frame. */
4929 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4930 {
4931 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4932
4933 /* Last fragment: Transmit and reset the packet storage counter. */
4934 if (pDesc->legacy.cmd.fEOP)
4935 {
4936 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4937 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4938 /** @todo Offload processing goes here. */
4939 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4940 pThis->u16TxPktLen = 0;
4941 }
4942 }
4943 /* Last fragment + failure: free the buffer and reset the storage counter. */
4944 else if (pDesc->legacy.cmd.fEOP)
4945 {
4946 e1kXmitFreeBuf(pThis);
4947 pThis->u16TxPktLen = 0;
4948 }
4949
4950 e1kDescReport(pThis, pDesc, addr);
4951 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4952 break;
4953
4954 default:
4955 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4956 pThis->szPrf, e1kGetDescType(pDesc)));
4957 break;
4958 }
4959
4960 return rc;
4961}
4962
4963#else /* E1K_WITH_TXD_CACHE */
4964
4965/**
4966 * Process Transmit Descriptor.
4967 *
4968 * E1000 supports three types of transmit descriptors:
4969 * - legacy data descriptors of older format (context-less).
4970 * - data the same as legacy but providing new offloading capabilities.
4971 * - context sets up the context for following data descriptors.
4972 *
4973 * @param pDevIns The device instance.
4974 * @param pThis The device state structure.
4975 * @param pThisCC The current context instance data.
4976 * @param pDesc Pointer to descriptor union.
4977 * @param addr Physical address of descriptor in guest memory.
4978 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4979 * @param cbPacketSize Size of the packet as previously computed.
4980 * @thread E1000_TX
4981 */
4982static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4983 RTGCPHYS addr, bool fOnWorkerThread)
4984{
4985 int rc = VINF_SUCCESS;
4986
4987 e1kPrintTDesc(pThis, pDesc, "vvv");
4988
4989 if (pDesc->legacy.dw3.fDD)
4990 {
4991 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
4992 e1kDescReport(pDevIns, pThis, pDesc, addr);
4993 return VINF_SUCCESS;
4994 }
4995
4996//#ifdef E1K_USE_TX_TIMERS
4997 if (pThis->fTidEnabled)
4998 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4999//#endif /* E1K_USE_TX_TIMERS */
5000
5001 switch (e1kGetDescType(pDesc))
5002 {
5003 case E1K_DTYP_CONTEXT:
5004 /* The caller have already updated the context */
5005 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5006 e1kDescReport(pDevIns, pThis, pDesc, addr);
5007 break;
5008
5009 case E1K_DTYP_DATA:
5010 {
5011 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5012 &pThis->StatTxDescTSEData:
5013 &pThis->StatTxDescData);
5014 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5015 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5016 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5017 {
5018 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
5019 if (pDesc->data.cmd.fEOP)
5020 {
5021 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5022 pThis->u16TxPktLen = 0;
5023 }
5024 }
5025 else
5026 {
5027 /*
5028 * Add the descriptor data to the frame. If the frame is complete,
5029 * transmit it and reset the u16TxPktLen field.
5030 */
5031 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5032 {
5033 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5034 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5035 if (pDesc->data.cmd.fEOP)
5036 {
5037 if ( fRc
5038 && pThisCC->CTX_SUFF(pTxSg)
5039 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5040 {
5041 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5042 E1K_INC_CNT32(TSCTC);
5043 }
5044 else
5045 {
5046 if (fRc)
5047 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5048 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5049 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5050 e1kXmitFreeBuf(pThis, pThisCC);
5051 E1K_INC_CNT32(TSCTFC);
5052 }
5053 pThis->u16TxPktLen = 0;
5054 }
5055 }
5056 else if (!pDesc->data.cmd.fTSE)
5057 {
5058 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5059 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5060 if (pDesc->data.cmd.fEOP)
5061 {
5062 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5063 {
5064 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5065 if (pThis->fIPcsum)
5066 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5067 pThis->contextNormal.ip.u8CSO,
5068 pThis->contextNormal.ip.u8CSS,
5069 pThis->contextNormal.ip.u16CSE);
5070 if (pThis->fTCPcsum)
5071 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5072 pThis->contextNormal.tu.u8CSO,
5073 pThis->contextNormal.tu.u8CSS,
5074 pThis->contextNormal.tu.u16CSE);
5075 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5076 }
5077 else
5078 e1kXmitFreeBuf(pThis, pThisCC);
5079 pThis->u16TxPktLen = 0;
5080 }
5081 }
5082 else
5083 {
5084 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5085 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5086 }
5087 }
5088 e1kDescReport(pDevIns, pThis, pDesc, addr);
5089 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5090 break;
5091 }
5092
5093 case E1K_DTYP_LEGACY:
5094 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5095 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5096 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5097 {
5098 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5099 }
5100 else
5101 {
5102 /* Add fragment to frame. */
5103 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5104 {
5105 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5106
5107 /* Last fragment: Transmit and reset the packet storage counter. */
5108 if (pDesc->legacy.cmd.fEOP)
5109 {
5110 if (pDesc->legacy.cmd.fIC)
5111 {
5112 e1kInsertChecksum(pThis,
5113 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5114 pThis->u16TxPktLen,
5115 pDesc->legacy.cmd.u8CSO,
5116 pDesc->legacy.dw3.u8CSS,
5117 0);
5118 }
5119 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5120 pThis->u16TxPktLen = 0;
5121 }
5122 }
5123 /* Last fragment + failure: free the buffer and reset the storage counter. */
5124 else if (pDesc->legacy.cmd.fEOP)
5125 {
5126 e1kXmitFreeBuf(pThis, pThisCC);
5127 pThis->u16TxPktLen = 0;
5128 }
5129 }
5130 e1kDescReport(pDevIns, pThis, pDesc, addr);
5131 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5132 break;
5133
5134 default:
5135 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5136 pThis->szPrf, e1kGetDescType(pDesc)));
5137 break;
5138 }
5139
5140 return rc;
5141}
5142
5143DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5144{
5145 if (pDesc->context.dw2.fTSE)
5146 {
5147 pThis->contextTSE = pDesc->context;
5148 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5149 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5150 {
5151 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5152 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5153 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5154 }
5155 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5156 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5157 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5158 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5159 }
5160 else
5161 {
5162 pThis->contextNormal = pDesc->context;
5163 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5164 }
5165 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5166 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5167 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5168 pDesc->context.ip.u8CSS,
5169 pDesc->context.ip.u8CSO,
5170 pDesc->context.ip.u16CSE,
5171 pDesc->context.tu.u8CSS,
5172 pDesc->context.tu.u8CSO,
5173 pDesc->context.tu.u16CSE));
5174}
5175
5176static bool e1kLocateTxPacket(PE1KSTATE pThis)
5177{
5178 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5179 pThis->szPrf, pThis->cbTxAlloc));
5180 /* Check if we have located the packet already. */
5181 if (pThis->cbTxAlloc)
5182 {
5183 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5184 pThis->szPrf, pThis->cbTxAlloc));
5185 return true;
5186 }
5187
5188 bool fTSE = false;
5189 uint32_t cbPacket = 0;
5190
5191 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5192 {
5193 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5194 switch (e1kGetDescType(pDesc))
5195 {
5196 case E1K_DTYP_CONTEXT:
5197 if (cbPacket == 0)
5198 e1kUpdateTxContext(pThis, pDesc);
5199 else
5200 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5201 pThis->szPrf, cbPacket));
5202 continue;
5203 case E1K_DTYP_LEGACY:
5204 /* Skip invalid descriptors. */
5205 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5206 {
5207 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5208 pThis->szPrf, cbPacket));
5209 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5210 continue;
5211 }
5212 /* Skip empty descriptors. */
5213 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5214 break;
5215 cbPacket += pDesc->legacy.cmd.u16Length;
5216 pThis->fGSO = false;
5217 break;
5218 case E1K_DTYP_DATA:
5219 /* Skip invalid descriptors. */
5220 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5221 {
5222 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5223 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5224 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5225 continue;
5226 }
5227 /* Skip empty descriptors. */
5228 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5229 break;
5230 if (cbPacket == 0)
5231 {
5232 /*
5233 * The first fragment: save IXSM and TXSM options
5234 * as these are only valid in the first fragment.
5235 */
5236 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5237 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5238 fTSE = pDesc->data.cmd.fTSE;
5239 /*
5240 * TSE descriptors have VLE bit properly set in
5241 * the first fragment.
5242 */
5243 if (fTSE)
5244 {
5245 pThis->fVTag = pDesc->data.cmd.fVLE;
5246 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5247 }
5248 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5249 }
5250 cbPacket += pDesc->data.cmd.u20DTALEN;
5251 break;
5252 default:
5253 AssertMsgFailed(("Impossible descriptor type!"));
5254 }
5255 if (pDesc->legacy.cmd.fEOP)
5256 {
5257 /*
5258 * Non-TSE descriptors have VLE bit properly set in
5259 * the last fragment.
5260 */
5261 if (!fTSE)
5262 {
5263 pThis->fVTag = pDesc->data.cmd.fVLE;
5264 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5265 }
5266 /*
5267 * Compute the required buffer size. If we cannot do GSO but still
5268 * have to do segmentation we allocate the first segment only.
5269 */
5270 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5271 cbPacket :
5272 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5273 if (pThis->fVTag)
5274 pThis->cbTxAlloc += 4;
5275 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5276 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5277 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5278 return true;
5279 }
5280 }
5281
5282 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5283 {
5284 /* All descriptors were empty, we need to process them as a dummy packet */
5285 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5286 pThis->szPrf, pThis->cbTxAlloc));
5287 return true;
5288 }
5289 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5290 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5291 return false;
5292}
5293
5294static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5295{
5296 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5297 int rc = VINF_SUCCESS;
5298
5299 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5300 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5301
5302 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5303 {
5304 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5305 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5306 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5307 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5308 if (RT_FAILURE(rc))
5309 break;
5310 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5311 TDH = 0;
5312 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5313 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5314 {
5315 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5316 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5317 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5318 }
5319 ++pThis->iTxDCurrent;
5320 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5321 break;
5322 }
5323
5324 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5325 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5326 return rc;
5327}
5328
5329#endif /* E1K_WITH_TXD_CACHE */
5330#ifndef E1K_WITH_TXD_CACHE
5331
5332/**
5333 * Transmit pending descriptors.
5334 *
5335 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5336 *
5337 * @param pDevIns The device instance.
5338 * @param pThis The E1000 state.
5339 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5340 */
5341static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5342{
5343 int rc = VINF_SUCCESS;
5344 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5345
5346 /* Check if transmitter is enabled. */
5347 if (!(TCTL & TCTL_EN))
5348 return VINF_SUCCESS;
5349 /*
5350 * Grab the xmit lock of the driver as well as the E1K device state.
5351 */
5352 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5353 if (RT_LIKELY(rc == VINF_SUCCESS))
5354 {
5355 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5356 if (pDrv)
5357 {
5358 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5359 if (RT_FAILURE(rc))
5360 {
5361 e1kCsTxLeave(pThis);
5362 return rc;
5363 }
5364 }
5365 /*
5366 * Process all pending descriptors.
5367 * Note! Do not process descriptors in locked state
5368 */
5369 while (TDH != TDT && !pThis->fLocked)
5370 {
5371 E1KTXDESC desc;
5372 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5373 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5374
5375 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5376 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5377 /* If we failed to transmit descriptor we will try it again later */
5378 if (RT_FAILURE(rc))
5379 break;
5380 if (++TDH * sizeof(desc) >= TDLEN)
5381 TDH = 0;
5382
5383 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5384 {
5385 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5386 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5387 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5388 }
5389
5390 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5391 }
5392
5393 /// @todo uncomment: pThis->uStatIntTXQE++;
5394 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5395 /*
5396 * Release the lock.
5397 */
5398 if (pDrv)
5399 pDrv->pfnEndXmit(pDrv);
5400 e1kCsTxLeave(pThis);
5401 }
5402
5403 return rc;
5404}
5405
5406#else /* E1K_WITH_TXD_CACHE */
5407
5408static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis)
5409{
5410 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5411 uint32_t tdh = TDH;
5412 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5413 for (i = 0; i < cDescs; ++i)
5414 {
5415 E1KTXDESC desc;
5416 PDMDevHlpPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5417 if (i == tdh)
5418 LogRel(("E1000: >>> "));
5419 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5420 }
5421 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5422 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5423 if (tdh > pThis->iTxDCurrent)
5424 tdh -= pThis->iTxDCurrent;
5425 else
5426 tdh = cDescs + tdh - pThis->iTxDCurrent;
5427 for (i = 0; i < pThis->nTxDFetched; ++i)
5428 {
5429 if (i == pThis->iTxDCurrent)
5430 LogRel(("E1000: >>> "));
5431 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5432 }
5433}
5434
5435/**
5436 * Transmit pending descriptors.
5437 *
5438 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5439 *
5440 * @param pDevIns The device instance.
5441 * @param pThis The E1000 state.
5442 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5443 */
5444static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5445{
5446 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5447 int rc = VINF_SUCCESS;
5448
5449 /* Check if transmitter is enabled. */
5450 if (!(TCTL & TCTL_EN))
5451 return VINF_SUCCESS;
5452 /*
5453 * Grab the xmit lock of the driver as well as the E1K device state.
5454 */
5455 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5456 if (pDrv)
5457 {
5458 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5459 if (RT_FAILURE(rc))
5460 return rc;
5461 }
5462
5463 /*
5464 * Process all pending descriptors.
5465 * Note! Do not process descriptors in locked state
5466 */
5467 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5468 if (RT_LIKELY(rc == VINF_SUCCESS))
5469 {
5470 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5471 /*
5472 * fIncomplete is set whenever we try to fetch additional descriptors
5473 * for an incomplete packet. If fail to locate a complete packet on
5474 * the next iteration we need to reset the cache or we risk to get
5475 * stuck in this loop forever.
5476 */
5477 bool fIncomplete = false;
5478 while (!pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis))
5479 {
5480 while (e1kLocateTxPacket(pThis))
5481 {
5482 fIncomplete = false;
5483 /* Found a complete packet, allocate it. */
5484 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5485 /* If we're out of bandwidth we'll come back later. */
5486 if (RT_FAILURE(rc))
5487 goto out;
5488 /* Copy the packet to allocated buffer and send it. */
5489 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread);
5490 /* If we're out of bandwidth we'll come back later. */
5491 if (RT_FAILURE(rc))
5492 goto out;
5493 }
5494 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5495 if (RT_UNLIKELY(fIncomplete))
5496 {
5497 static bool fTxDCacheDumped = false;
5498 /*
5499 * The descriptor cache is full, but we were unable to find
5500 * a complete packet in it. Drop the cache and hope that
5501 * the guest driver can recover from network card error.
5502 */
5503 LogRel(("%s: No complete packets in%s TxD cache! "
5504 "Fetched=%d, current=%d, TX len=%d.\n",
5505 pThis->szPrf,
5506 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5507 pThis->nTxDFetched, pThis->iTxDCurrent,
5508 e1kGetTxLen(pThis)));
5509 if (!fTxDCacheDumped)
5510 {
5511 fTxDCacheDumped = true;
5512 e1kDumpTxDCache(pDevIns, pThis);
5513 }
5514 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5515 /*
5516 * Returning an error at this point means Guru in R0
5517 * (see @bugref{6428}).
5518 */
5519# ifdef IN_RING3
5520 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5521# else /* !IN_RING3 */
5522 rc = VINF_IOM_R3_MMIO_WRITE;
5523# endif /* !IN_RING3 */
5524 goto out;
5525 }
5526 if (u8Remain > 0)
5527 {
5528 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5529 "%d more are available\n",
5530 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5531 e1kGetTxLen(pThis) - u8Remain));
5532
5533 /*
5534 * A packet was partially fetched. Move incomplete packet to
5535 * the beginning of cache buffer, then load more descriptors.
5536 */
5537 memmove(pThis->aTxDescriptors,
5538 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5539 u8Remain * sizeof(E1KTXDESC));
5540 pThis->iTxDCurrent = 0;
5541 pThis->nTxDFetched = u8Remain;
5542 e1kTxDLoadMore(pDevIns, pThis);
5543 fIncomplete = true;
5544 }
5545 else
5546 pThis->nTxDFetched = 0;
5547 pThis->iTxDCurrent = 0;
5548 }
5549 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5550 {
5551 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5552 pThis->szPrf));
5553 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5554 }
5555out:
5556 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5557
5558 /// @todo uncomment: pThis->uStatIntTXQE++;
5559 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5560
5561 e1kCsTxLeave(pThis);
5562 }
5563
5564
5565 /*
5566 * Release the lock.
5567 */
5568 if (pDrv)
5569 pDrv->pfnEndXmit(pDrv);
5570 return rc;
5571}
5572
5573#endif /* E1K_WITH_TXD_CACHE */
5574#ifdef IN_RING3
5575
5576/**
5577 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5578 */
5579static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5580{
5581 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5582 PE1KSTATE pThis = pThisCC->pShared;
5583 /* Resume suspended transmission */
5584 STATUS &= ~STATUS_TXOFF;
5585 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5586}
5587
5588/**
5589 * @callback_method_impl{FNPDMTASKDEV,
5590 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5591 * @note Not executed on EMT.
5592 */
5593static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5594{
5595 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5596 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5597
5598 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5599 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5600
5601 RT_NOREF(rc, pvUser);
5602}
5603
5604#endif /* IN_RING3 */
5605
5606/**
5607 * Write handler for Transmit Descriptor Tail register.
5608 *
5609 * @param pThis The device state structure.
5610 * @param offset Register offset in memory-mapped frame.
5611 * @param index Register index in register array.
5612 * @param value The value to store.
5613 * @param mask Used to implement partial writes (8 and 16-bit).
5614 * @thread EMT
5615 */
5616static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5617{
5618 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5619
5620 /* All descriptors starting with head and not including tail belong to us. */
5621 /* Process them. */
5622 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5623 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5624
5625 /* Ignore TDT writes when the link is down. */
5626 if (TDH != TDT && (STATUS & STATUS_LU))
5627 {
5628 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5629 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5630 pThis->szPrf, e1kGetTxLen(pThis)));
5631
5632 /* Transmit pending packets if possible, defer it if we cannot do it
5633 in the current context. */
5634#ifdef E1K_TX_DELAY
5635 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5636 if (RT_LIKELY(rc == VINF_SUCCESS))
5637 {
5638 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5639 {
5640# ifdef E1K_INT_STATS
5641 pThis->u64ArmedAt = RTTimeNanoTS();
5642# endif
5643 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5644 }
5645 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5646 e1kCsTxLeave(pThis);
5647 return rc;
5648 }
5649 /* We failed to enter the TX critical section -- transmit as usual. */
5650#endif /* E1K_TX_DELAY */
5651#ifndef IN_RING3
5652 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5653 if (!pThisCC->CTX_SUFF(pDrv))
5654 {
5655 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5656 rc = VINF_SUCCESS;
5657 }
5658 else
5659#endif
5660 {
5661 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5662 if (rc == VERR_TRY_AGAIN)
5663 rc = VINF_SUCCESS;
5664#ifndef IN_RING3
5665 else if (rc == VERR_SEM_BUSY)
5666 rc = VINF_IOM_R3_MMIO_WRITE;
5667#endif
5668 AssertRC(rc);
5669 }
5670 }
5671
5672 return rc;
5673}
5674
5675/**
5676 * Write handler for Multicast Table Array registers.
5677 *
5678 * @param pThis The device state structure.
5679 * @param offset Register offset in memory-mapped frame.
5680 * @param index Register index in register array.
5681 * @param value The value to store.
5682 * @thread EMT
5683 */
5684static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5685{
5686 RT_NOREF_PV(pDevIns);
5687 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5688 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5689
5690 return VINF_SUCCESS;
5691}
5692
5693/**
5694 * Read handler for Multicast Table Array registers.
5695 *
5696 * @returns VBox status code.
5697 *
5698 * @param pThis The device state structure.
5699 * @param offset Register offset in memory-mapped frame.
5700 * @param index Register index in register array.
5701 * @thread EMT
5702 */
5703static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5704{
5705 RT_NOREF_PV(pDevIns);
5706 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5707 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5708
5709 return VINF_SUCCESS;
5710}
5711
5712/**
5713 * Write handler for Receive Address registers.
5714 *
5715 * @param pThis The device state structure.
5716 * @param offset Register offset in memory-mapped frame.
5717 * @param index Register index in register array.
5718 * @param value The value to store.
5719 * @thread EMT
5720 */
5721static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5722{
5723 RT_NOREF_PV(pDevIns);
5724 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5725 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5726
5727 return VINF_SUCCESS;
5728}
5729
5730/**
5731 * Read handler for Receive Address registers.
5732 *
5733 * @returns VBox status code.
5734 *
5735 * @param pThis The device state structure.
5736 * @param offset Register offset in memory-mapped frame.
5737 * @param index Register index in register array.
5738 * @thread EMT
5739 */
5740static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5741{
5742 RT_NOREF_PV(pDevIns);
5743 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5744 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5745
5746 return VINF_SUCCESS;
5747}
5748
5749/**
5750 * Write handler for VLAN Filter Table Array registers.
5751 *
5752 * @param pThis The device state structure.
5753 * @param offset Register offset in memory-mapped frame.
5754 * @param index Register index in register array.
5755 * @param value The value to store.
5756 * @thread EMT
5757 */
5758static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5759{
5760 RT_NOREF_PV(pDevIns);
5761 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5762 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5763
5764 return VINF_SUCCESS;
5765}
5766
5767/**
5768 * Read handler for VLAN Filter Table Array registers.
5769 *
5770 * @returns VBox status code.
5771 *
5772 * @param pThis The device state structure.
5773 * @param offset Register offset in memory-mapped frame.
5774 * @param index Register index in register array.
5775 * @thread EMT
5776 */
5777static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5778{
5779 RT_NOREF_PV(pDevIns);
5780 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5781 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5782
5783 return VINF_SUCCESS;
5784}
5785
5786/**
5787 * Read handler for unimplemented registers.
5788 *
5789 * Merely reports reads from unimplemented registers.
5790 *
5791 * @returns VBox status code.
5792 *
5793 * @param pThis The device state structure.
5794 * @param offset Register offset in memory-mapped frame.
5795 * @param index Register index in register array.
5796 * @thread EMT
5797 */
5798static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5799{
5800 RT_NOREF(pDevIns, pThis, offset, index);
5801 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5802 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5803 *pu32Value = 0;
5804
5805 return VINF_SUCCESS;
5806}
5807
5808/**
5809 * Default register read handler with automatic clear operation.
5810 *
5811 * Retrieves the value of register from register array in device state structure.
5812 * Then resets all bits.
5813 *
5814 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5815 * done in the caller.
5816 *
5817 * @returns VBox status code.
5818 *
5819 * @param pThis The device state structure.
5820 * @param offset Register offset in memory-mapped frame.
5821 * @param index Register index in register array.
5822 * @thread EMT
5823 */
5824static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5825{
5826 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5827 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
5828 pThis->auRegs[index] = 0;
5829
5830 return rc;
5831}
5832
5833/**
5834 * Default register read handler.
5835 *
5836 * Retrieves the value of register from register array in device state structure.
5837 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5838 *
5839 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5840 * done in the caller.
5841 *
5842 * @returns VBox status code.
5843 *
5844 * @param pThis The device state structure.
5845 * @param offset Register offset in memory-mapped frame.
5846 * @param index Register index in register array.
5847 * @thread EMT
5848 */
5849static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5850{
5851 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
5852
5853 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5854 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5855
5856 return VINF_SUCCESS;
5857}
5858
5859/**
5860 * Write handler for unimplemented registers.
5861 *
5862 * Merely reports writes to unimplemented registers.
5863 *
5864 * @param pThis The device state structure.
5865 * @param offset Register offset in memory-mapped frame.
5866 * @param index Register index in register array.
5867 * @param value The value to store.
5868 * @thread EMT
5869 */
5870
5871 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5872{
5873 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
5874
5875 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5876 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5877
5878 return VINF_SUCCESS;
5879}
5880
5881/**
5882 * Default register write handler.
5883 *
5884 * Stores the value to the register array in device state structure. Only bits
5885 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5886 *
5887 * @returns VBox status code.
5888 *
5889 * @param pThis The device state structure.
5890 * @param offset Register offset in memory-mapped frame.
5891 * @param index Register index in register array.
5892 * @param value The value to store.
5893 * @param mask Used to implement partial writes (8 and 16-bit).
5894 * @thread EMT
5895 */
5896
5897static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5898{
5899 RT_NOREF(pDevIns, offset);
5900
5901 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5902 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5903 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5904
5905 return VINF_SUCCESS;
5906}
5907
5908/**
5909 * Search register table for matching register.
5910 *
5911 * @returns Index in the register table or -1 if not found.
5912 *
5913 * @param offReg Register offset in memory-mapped region.
5914 * @thread EMT
5915 */
5916static int e1kRegLookup(uint32_t offReg)
5917{
5918
5919#if 0
5920 int index;
5921
5922 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5923 {
5924 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5925 {
5926 return index;
5927 }
5928 }
5929#else
5930 int iStart = 0;
5931 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5932 for (;;)
5933 {
5934 int i = (iEnd - iStart) / 2 + iStart;
5935 uint32_t offCur = g_aE1kRegMap[i].offset;
5936 if (offReg < offCur)
5937 {
5938 if (i == iStart)
5939 break;
5940 iEnd = i;
5941 }
5942 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5943 {
5944 i++;
5945 if (i == iEnd)
5946 break;
5947 iStart = i;
5948 }
5949 else
5950 return i;
5951 Assert(iEnd > iStart);
5952 }
5953
5954 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5955 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5956 return i;
5957
5958# ifdef VBOX_STRICT
5959 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5960 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5961# endif
5962
5963#endif
5964
5965 return -1;
5966}
5967
5968/**
5969 * Handle unaligned register read operation.
5970 *
5971 * Looks up and calls appropriate handler.
5972 *
5973 * @returns VBox status code.
5974 *
5975 * @param pDevIns The device instance.
5976 * @param pThis The device state structure.
5977 * @param offReg Register offset in memory-mapped frame.
5978 * @param pv Where to store the result.
5979 * @param cb Number of bytes to read.
5980 * @thread EMT
5981 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5982 * accesses we have to take care of that ourselves.
5983 */
5984static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5985{
5986 uint32_t u32 = 0;
5987 uint32_t shift;
5988 int rc = VINF_SUCCESS;
5989 int index = e1kRegLookup(offReg);
5990#ifdef LOG_ENABLED
5991 char buf[9];
5992#endif
5993
5994 /*
5995 * From the spec:
5996 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
5997 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
5998 */
5999
6000 /*
6001 * To be able to read bytes and short word we convert them to properly
6002 * shifted 32-bit words and masks. The idea is to keep register-specific
6003 * handlers simple. Most accesses will be 32-bit anyway.
6004 */
6005 uint32_t mask;
6006 switch (cb)
6007 {
6008 case 4: mask = 0xFFFFFFFF; break;
6009 case 2: mask = 0x0000FFFF; break;
6010 case 1: mask = 0x000000FF; break;
6011 default:
6012 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6013 }
6014 if (index != -1)
6015 {
6016 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6017 if (g_aE1kRegMap[index].readable)
6018 {
6019 /* Make the mask correspond to the bits we are about to read. */
6020 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6021 mask <<= shift;
6022 if (!mask)
6023 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6024 /*
6025 * Read it. Pass the mask so the handler knows what has to be read.
6026 * Mask out irrelevant bits.
6027 */
6028 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6029 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6030 return rc;
6031 //pThis->fDelayInts = false;
6032 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6033 //pThis->iStatIntLostOne = 0;
6034 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, index, &u32);
6035 u32 &= mask;
6036 //e1kCsLeave(pThis);
6037 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6038 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6039 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6040 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6041 /* Shift back the result. */
6042 u32 >>= shift;
6043 }
6044 else
6045 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6046 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6047 if (IOM_SUCCESS(rc))
6048 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6049 }
6050 else
6051 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6052 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6053
6054 memcpy(pv, &u32, cb);
6055 return rc;
6056}
6057
6058/**
6059 * Handle 4 byte aligned and sized read operation.
6060 *
6061 * Looks up and calls appropriate handler.
6062 *
6063 * @returns VBox status code.
6064 *
6065 * @param pDevIns The device instance.
6066 * @param pThis The device state structure.
6067 * @param offReg Register offset in memory-mapped frame.
6068 * @param pu32 Where to store the result.
6069 * @thread EMT
6070 */
6071static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6072{
6073 Assert(!(offReg & 3));
6074
6075 /*
6076 * Lookup the register and check that it's readable.
6077 */
6078 VBOXSTRICTRC rc = VINF_SUCCESS;
6079 int idxReg = e1kRegLookup(offReg);
6080 if (RT_LIKELY(idxReg != -1))
6081 {
6082 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6083 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6084 {
6085 /*
6086 * Read it. Pass the mask so the handler knows what has to be read.
6087 * Mask out irrelevant bits.
6088 */
6089 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6090 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6091 // return rc;
6092 //pThis->fDelayInts = false;
6093 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6094 //pThis->iStatIntLostOne = 0;
6095 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, idxReg, pu32);
6096 //e1kCsLeave(pThis);
6097 Log6(("%s At %08X read %08X from %s (%s)\n",
6098 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6099 if (IOM_SUCCESS(rc))
6100 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6101 }
6102 else
6103 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6104 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6105 }
6106 else
6107 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6108 return rc;
6109}
6110
6111/**
6112 * Handle 4 byte sized and aligned register write operation.
6113 *
6114 * Looks up and calls appropriate handler.
6115 *
6116 * @returns VBox status code.
6117 *
6118 * @param pDevIns The device instance.
6119 * @param pThis The device state structure.
6120 * @param offReg Register offset in memory-mapped frame.
6121 * @param u32Value The value to write.
6122 * @thread EMT
6123 */
6124static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6125{
6126 VBOXSTRICTRC rc = VINF_SUCCESS;
6127 int index = e1kRegLookup(offReg);
6128 if (RT_LIKELY(index != -1))
6129 {
6130 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6131 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6132 {
6133 /*
6134 * Write it. Pass the mask so the handler knows what has to be written.
6135 * Mask out irrelevant bits.
6136 */
6137 Log6(("%s At %08X write %08X to %s (%s)\n",
6138 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6139 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6140 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6141 // return rc;
6142 //pThis->fDelayInts = false;
6143 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6144 //pThis->iStatIntLostOne = 0;
6145 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, index, u32Value);
6146 //e1kCsLeave(pThis);
6147 }
6148 else
6149 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6150 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6151 if (IOM_SUCCESS(rc))
6152 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6153 }
6154 else
6155 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6156 pThis->szPrf, offReg, u32Value));
6157 return rc;
6158}
6159
6160
6161/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6162
6163/**
6164 * @callback_method_impl{FNIOMMMIONEWREAD}
6165 */
6166static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6167{
6168 RT_NOREF2(pvUser, cb);
6169 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6170 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6171
6172 Assert(off < E1K_MM_SIZE);
6173 Assert(cb == 4);
6174 Assert(!(off & 3));
6175
6176 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6177
6178 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6179 return rcStrict;
6180}
6181
6182/**
6183 * @callback_method_impl{FNIOMMMIONEWWRITE}
6184 */
6185static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6186{
6187 RT_NOREF2(pvUser, cb);
6188 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6189 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6190
6191 Assert(off < E1K_MM_SIZE);
6192 Assert(cb == 4);
6193 Assert(!(off & 3));
6194
6195 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6196
6197 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6198 return rcStrict;
6199}
6200
6201/**
6202 * @callback_method_impl{FNIOMIOPORTNEWIN}
6203 */
6204static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6205{
6206 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6207 VBOXSTRICTRC rc;
6208 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6209 RT_NOREF_PV(pvUser);
6210
6211 if (RT_LIKELY(cb == 4))
6212 switch (offPort)
6213 {
6214 case 0x00: /* IOADDR */
6215 *pu32 = pThis->uSelectedReg;
6216 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6217 rc = VINF_SUCCESS;
6218 break;
6219
6220 case 0x04: /* IODATA */
6221 if (!(pThis->uSelectedReg & 3))
6222 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6223 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6224 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6225 if (rc == VINF_IOM_R3_MMIO_READ)
6226 rc = VINF_IOM_R3_IOPORT_READ;
6227 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6228 break;
6229
6230 default:
6231 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6232 /** @todo r=bird: Check what real hardware returns here. */
6233 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6234 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6235 break;
6236 }
6237 else
6238 {
6239 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6240 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6241 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6242 }
6243 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6244 return rc;
6245}
6246
6247
6248/**
6249 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6250 */
6251static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6252{
6253 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6254 VBOXSTRICTRC rc;
6255 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6256 RT_NOREF_PV(pvUser);
6257
6258 E1kLog2(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6259 if (RT_LIKELY(cb == 4))
6260 {
6261 switch (offPort)
6262 {
6263 case 0x00: /* IOADDR */
6264 pThis->uSelectedReg = u32;
6265 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6266 rc = VINF_SUCCESS;
6267 break;
6268
6269 case 0x04: /* IODATA */
6270 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6271 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6272 {
6273 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6274 if (rc == VINF_IOM_R3_MMIO_WRITE)
6275 rc = VINF_IOM_R3_IOPORT_WRITE;
6276 }
6277 else
6278 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6279 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6280 break;
6281
6282 default:
6283 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6284 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6285 }
6286 }
6287 else
6288 {
6289 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6290 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6291 }
6292
6293 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6294 return rc;
6295}
6296
6297#ifdef IN_RING3
6298
6299/**
6300 * Dump complete device state to log.
6301 *
6302 * @param pThis Pointer to device state.
6303 */
6304static void e1kDumpState(PE1KSTATE pThis)
6305{
6306 RT_NOREF(pThis);
6307 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6308 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6309# ifdef E1K_INT_STATS
6310 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6311 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6312 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6313 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6314 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6315 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6316 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6317 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6318 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6319 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6320 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6321 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6322 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6323 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6324 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6325 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6326 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6327 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6328 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6329 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6330 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6331 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6332 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6333 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6334 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6335 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6336 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6337 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6338 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6339 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6340 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6341 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6342 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6343 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6344 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6345 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6346 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6347 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6348 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6349# endif /* E1K_INT_STATS */
6350}
6351
6352
6353/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6354
6355/**
6356 * Check if the device can receive data now.
6357 * This must be called before the pfnRecieve() method is called.
6358 *
6359 * @returns Number of bytes the device can receive.
6360 * @param pDevIns The device instance.
6361 * @param pThis The instance data.
6362 * @thread EMT
6363 */
6364static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6365{
6366#ifndef E1K_WITH_RXD_CACHE
6367 size_t cb;
6368
6369 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6370 return VERR_NET_NO_BUFFER_SPACE;
6371
6372 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6373 {
6374 E1KRXDESC desc;
6375 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6376 if (desc.status.fDD)
6377 cb = 0;
6378 else
6379 cb = pThis->u16RxBSize;
6380 }
6381 else if (RDH < RDT)
6382 cb = (RDT - RDH) * pThis->u16RxBSize;
6383 else if (RDH > RDT)
6384 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6385 else
6386 {
6387 cb = 0;
6388 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6389 }
6390 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6391 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6392
6393 e1kCsRxLeave(pThis);
6394 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6395#else /* E1K_WITH_RXD_CACHE */
6396 int rc = VINF_SUCCESS;
6397
6398 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6399 return VERR_NET_NO_BUFFER_SPACE;
6400
6401 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6402 {
6403 E1KRXDESC desc;
6404 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6405 if (desc.status.fDD)
6406 rc = VERR_NET_NO_BUFFER_SPACE;
6407 }
6408 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6409 {
6410 /* Cache is empty, so is the RX ring. */
6411 rc = VERR_NET_NO_BUFFER_SPACE;
6412 }
6413 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6414 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6415 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6416
6417 e1kCsRxLeave(pThis);
6418 return rc;
6419#endif /* E1K_WITH_RXD_CACHE */
6420}
6421
6422/**
6423 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6424 */
6425static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6426{
6427 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6428 PE1KSTATE pThis = pThisCC->pShared;
6429 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6430
6431 int rc = e1kCanReceive(pDevIns, pThis);
6432
6433 if (RT_SUCCESS(rc))
6434 return VINF_SUCCESS;
6435 if (RT_UNLIKELY(cMillies == 0))
6436 return VERR_NET_NO_BUFFER_SPACE;
6437
6438 rc = VERR_INTERRUPTED;
6439 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6440 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6441 VMSTATE enmVMState;
6442 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6443 || enmVMState == VMSTATE_RUNNING_LS))
6444 {
6445 int rc2 = e1kCanReceive(pDevIns, pThis);
6446 if (RT_SUCCESS(rc2))
6447 {
6448 rc = VINF_SUCCESS;
6449 break;
6450 }
6451 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6452 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6453 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6454 }
6455 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6456 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6457
6458 return rc;
6459}
6460
6461
6462/**
6463 * Matches the packet addresses against Receive Address table. Looks for
6464 * exact matches only.
6465 *
6466 * @returns true if address matches.
6467 * @param pThis Pointer to the state structure.
6468 * @param pvBuf The ethernet packet.
6469 * @param cb Number of bytes available in the packet.
6470 * @thread EMT
6471 */
6472static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6473{
6474 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6475 {
6476 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6477
6478 /* Valid address? */
6479 if (ra->ctl & RA_CTL_AV)
6480 {
6481 Assert((ra->ctl & RA_CTL_AS) < 2);
6482 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6483 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6484 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6485 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6486 /*
6487 * Address Select:
6488 * 00b = Destination address
6489 * 01b = Source address
6490 * 10b = Reserved
6491 * 11b = Reserved
6492 * Since ethernet header is (DA, SA, len) we can use address
6493 * select as index.
6494 */
6495 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6496 ra->addr, sizeof(ra->addr)) == 0)
6497 return true;
6498 }
6499 }
6500
6501 return false;
6502}
6503
6504/**
6505 * Matches the packet addresses against Multicast Table Array.
6506 *
6507 * @remarks This is imperfect match since it matches not exact address but
6508 * a subset of addresses.
6509 *
6510 * @returns true if address matches.
6511 * @param pThis Pointer to the state structure.
6512 * @param pvBuf The ethernet packet.
6513 * @param cb Number of bytes available in the packet.
6514 * @thread EMT
6515 */
6516static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6517{
6518 /* Get bits 32..47 of destination address */
6519 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6520
6521 unsigned offset = GET_BITS(RCTL, MO);
6522 /*
6523 * offset means:
6524 * 00b = bits 36..47
6525 * 01b = bits 35..46
6526 * 10b = bits 34..45
6527 * 11b = bits 32..43
6528 */
6529 if (offset < 3)
6530 u16Bit = u16Bit >> (4 - offset);
6531 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6532}
6533
6534/**
6535 * Determines if the packet is to be delivered to upper layer.
6536 *
6537 * The following filters supported:
6538 * - Exact Unicast/Multicast
6539 * - Promiscuous Unicast/Multicast
6540 * - Multicast
6541 * - VLAN
6542 *
6543 * @returns true if packet is intended for this node.
6544 * @param pThis Pointer to the state structure.
6545 * @param pvBuf The ethernet packet.
6546 * @param cb Number of bytes available in the packet.
6547 * @param pStatus Bit field to store status bits.
6548 * @thread EMT
6549 */
6550static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6551{
6552 Assert(cb > 14);
6553 /* Assume that we fail to pass exact filter. */
6554 pStatus->fPIF = false;
6555 pStatus->fVP = false;
6556 /* Discard oversized packets */
6557 if (cb > E1K_MAX_RX_PKT_SIZE)
6558 {
6559 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6560 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6561 E1K_INC_CNT32(ROC);
6562 return false;
6563 }
6564 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6565 {
6566 /* When long packet reception is disabled packets over 1522 are discarded */
6567 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6568 pThis->szPrf, cb));
6569 E1K_INC_CNT32(ROC);
6570 return false;
6571 }
6572
6573 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6574 /* Compare TPID with VLAN Ether Type */
6575 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6576 {
6577 pStatus->fVP = true;
6578 /* Is VLAN filtering enabled? */
6579 if (RCTL & RCTL_VFE)
6580 {
6581 /* It is 802.1q packet indeed, let's filter by VID */
6582 if (RCTL & RCTL_CFIEN)
6583 {
6584 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6585 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6586 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6587 !!(RCTL & RCTL_CFI)));
6588 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6589 {
6590 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6591 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6592 return false;
6593 }
6594 }
6595 else
6596 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6597 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6598 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6599 {
6600 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6601 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6602 return false;
6603 }
6604 }
6605 }
6606 /* Broadcast filtering */
6607 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6608 return true;
6609 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6610 if (e1kIsMulticast(pvBuf))
6611 {
6612 /* Is multicast promiscuous enabled? */
6613 if (RCTL & RCTL_MPE)
6614 return true;
6615 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6616 /* Try perfect matches first */
6617 if (e1kPerfectMatch(pThis, pvBuf))
6618 {
6619 pStatus->fPIF = true;
6620 return true;
6621 }
6622 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6623 if (e1kImperfectMatch(pThis, pvBuf))
6624 return true;
6625 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6626 }
6627 else {
6628 /* Is unicast promiscuous enabled? */
6629 if (RCTL & RCTL_UPE)
6630 return true;
6631 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6632 if (e1kPerfectMatch(pThis, pvBuf))
6633 {
6634 pStatus->fPIF = true;
6635 return true;
6636 }
6637 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6638 }
6639 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6640 return false;
6641}
6642
6643/**
6644 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6645 */
6646static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6647{
6648 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6649 PE1KSTATE pThis = pThisCC->pShared;
6650 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6651 int rc = VINF_SUCCESS;
6652
6653 /*
6654 * Drop packets if the VM is not running yet/anymore.
6655 */
6656 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6657 if ( enmVMState != VMSTATE_RUNNING
6658 && enmVMState != VMSTATE_RUNNING_LS)
6659 {
6660 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6661 return VINF_SUCCESS;
6662 }
6663
6664 /* Discard incoming packets in locked state */
6665 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6666 {
6667 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6668 return VINF_SUCCESS;
6669 }
6670
6671 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6672
6673 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6674 // return VERR_PERMISSION_DENIED;
6675
6676 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6677
6678 /* Update stats */
6679 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6680 {
6681 E1K_INC_CNT32(TPR);
6682 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6683 e1kCsLeave(pThis);
6684 }
6685 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6686 E1KRXDST status;
6687 RT_ZERO(status);
6688 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6689 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6690 if (fPassed)
6691 {
6692 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6693 }
6694 //e1kCsLeave(pThis);
6695 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6696
6697 return rc;
6698}
6699
6700
6701/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6702
6703/**
6704 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6705 */
6706static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6707{
6708 if (iLUN == 0)
6709 {
6710 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6711 *ppLed = &pThisCC->pShared->led;
6712 return VINF_SUCCESS;
6713 }
6714 return VERR_PDM_LUN_NOT_FOUND;
6715}
6716
6717
6718/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6719
6720/**
6721 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6722 */
6723static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6724{
6725 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6726 pThisCC->eeprom.getMac(pMac);
6727 return VINF_SUCCESS;
6728}
6729
6730/**
6731 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6732 */
6733static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6734{
6735 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6736 PE1KSTATE pThis = pThisCC->pShared;
6737 if (STATUS & STATUS_LU)
6738 return PDMNETWORKLINKSTATE_UP;
6739 return PDMNETWORKLINKSTATE_DOWN;
6740}
6741
6742/**
6743 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6744 */
6745static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6746{
6747 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6748 PE1KSTATE pThis = pThisCC->pShared;
6749 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6750
6751 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6752 switch (enmState)
6753 {
6754 case PDMNETWORKLINKSTATE_UP:
6755 pThis->fCableConnected = true;
6756 /* If link was down, bring it up after a while. */
6757 if (!(STATUS & STATUS_LU))
6758 e1kBringLinkUpDelayed(pDevIns, pThis);
6759 break;
6760 case PDMNETWORKLINKSTATE_DOWN:
6761 pThis->fCableConnected = false;
6762 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6763 * We might have to set the link state before the driver initializes us. */
6764 Phy::setLinkStatus(&pThis->phy, false);
6765 /* If link was up, bring it down. */
6766 if (STATUS & STATUS_LU)
6767 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6768 break;
6769 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6770 /*
6771 * There is not much sense in bringing down the link if it has not come up yet.
6772 * If it is up though, we bring it down temporarely, then bring it up again.
6773 */
6774 if (STATUS & STATUS_LU)
6775 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6776 break;
6777 default:
6778 ;
6779 }
6780 return VINF_SUCCESS;
6781}
6782
6783
6784/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6785
6786/**
6787 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6788 */
6789static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6790{
6791 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6792 Assert(&pThisCC->IBase == pInterface);
6793
6794 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6795 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6796 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6797 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6798 return NULL;
6799}
6800
6801
6802/* -=-=-=-=- Saved State -=-=-=-=- */
6803
6804/**
6805 * Saves the configuration.
6806 *
6807 * @param pThis The E1K state.
6808 * @param pSSM The handle to the saved state.
6809 */
6810static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
6811{
6812 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6813 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
6814}
6815
6816/**
6817 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6818 */
6819static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6820{
6821 RT_NOREF(uPass);
6822 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
6823 return VINF_SSM_DONT_CALL_AGAIN;
6824}
6825
6826/**
6827 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6828 */
6829static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6830{
6831 RT_NOREF(pSSM);
6832 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6833
6834 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6835 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6836 return rc;
6837 e1kCsLeave(pThis);
6838 return VINF_SUCCESS;
6839#if 0
6840 /* 1) Prevent all threads from modifying the state and memory */
6841 //pThis->fLocked = true;
6842 /* 2) Cancel all timers */
6843#ifdef E1K_TX_DELAY
6844 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6845#endif /* E1K_TX_DELAY */
6846//#ifdef E1K_USE_TX_TIMERS
6847 if (pThis->fTidEnabled)
6848 {
6849 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6850#ifndef E1K_NO_TAD
6851 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6852#endif /* E1K_NO_TAD */
6853 }
6854//#endif /* E1K_USE_TX_TIMERS */
6855#ifdef E1K_USE_RX_TIMERS
6856 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6857 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6858#endif /* E1K_USE_RX_TIMERS */
6859 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6860 /* 3) Did I forget anything? */
6861 E1kLog(("%s Locked\n", pThis->szPrf));
6862 return VINF_SUCCESS;
6863#endif
6864}
6865
6866/**
6867 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6868 */
6869static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6870{
6871 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6872 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6873 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6874
6875 e1kSaveConfig(pHlp, pThis, pSSM);
6876 pThisCC->eeprom.save(pHlp, pSSM);
6877 e1kDumpState(pThis);
6878 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6879 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
6880 Phy::saveState(pHlp, pSSM, &pThis->phy);
6881 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
6882 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6883 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6884 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6885 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
6886 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
6887 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
6888 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
6889 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
6890/** @todo State wrt to the TSE buffer is incomplete, so little point in
6891 * saving this actually. */
6892 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6893 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
6894 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
6895 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6896 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6897 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
6898 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
6899#ifdef E1K_WITH_TXD_CACHE
6900# if 0
6901 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
6902 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
6903 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6904# else
6905 /*
6906 * There is no point in storing TX descriptor cache entries as we can simply
6907 * fetch them again. Moreover, normally the cache is always empty when we
6908 * save the state. Store zero entries for compatibility.
6909 */
6910 pHlp->pfnSSMPutU8(pSSM, 0);
6911# endif
6912#endif /* E1K_WITH_TXD_CACHE */
6913/** @todo GSO requires some more state here. */
6914 E1kLog(("%s State has been saved\n", pThis->szPrf));
6915 return VINF_SUCCESS;
6916}
6917
6918#if 0
6919/**
6920 * @callback_method_impl{FNSSMDEVSAVEDONE}
6921 */
6922static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6923{
6924 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6925
6926 /* If VM is being powered off unlocking will result in assertions in PGM */
6927 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6928 pThis->fLocked = false;
6929 else
6930 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6931 E1kLog(("%s Unlocked\n", pThis->szPrf));
6932 return VINF_SUCCESS;
6933}
6934#endif
6935
6936/**
6937 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6938 */
6939static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6940{
6941 RT_NOREF(pSSM);
6942 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6943
6944 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6945 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6946 return rc;
6947 e1kCsLeave(pThis);
6948 return VINF_SUCCESS;
6949}
6950
6951/**
6952 * @callback_method_impl{FNSSMDEVLOADEXEC}
6953 */
6954static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6955{
6956 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6957 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6958 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6959 int rc;
6960
6961 if ( uVersion != E1K_SAVEDSTATE_VERSION
6962#ifdef E1K_WITH_TXD_CACHE
6963 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6964#endif /* E1K_WITH_TXD_CACHE */
6965 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6966 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6967 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6968
6969 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6970 || uPass != SSM_PASS_FINAL)
6971 {
6972 /* config checks */
6973 RTMAC macConfigured;
6974 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
6975 AssertRCReturn(rc, rc);
6976 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6977 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6978 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6979
6980 E1KCHIP eChip;
6981 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
6982 AssertRCReturn(rc, rc);
6983 if (eChip != pThis->eChip)
6984 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6985 }
6986
6987 if (uPass == SSM_PASS_FINAL)
6988 {
6989 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6990 {
6991 rc = pThisCC->eeprom.load(pHlp, pSSM);
6992 AssertRCReturn(rc, rc);
6993 }
6994 /* the state */
6995 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
6996 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
6997 /** @todo PHY could be made a separate device with its own versioning */
6998 Phy::loadState(pHlp, pSSM, &pThis->phy);
6999 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7000 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7001 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7002 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7003 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7004 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7005 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7006 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7007 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7008 AssertRCReturn(rc, rc);
7009 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7010 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7011 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7012 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7013 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7014 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7015 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7016 AssertRCReturn(rc, rc);
7017 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7018 {
7019 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7020 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7021 AssertRCReturn(rc, rc);
7022 }
7023 else
7024 {
7025 pThis->fVTag = false;
7026 pThis->u16VTagTCI = 0;
7027 }
7028#ifdef E1K_WITH_TXD_CACHE
7029 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7030 {
7031 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7032 AssertRCReturn(rc, rc);
7033 if (pThis->nTxDFetched)
7034 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7035 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7036 }
7037 else
7038 pThis->nTxDFetched = 0;
7039 /**
7040 * @todo Perhaps we should not store TXD cache as the entries can be
7041 * simply fetched again from guest's memory. Or can't they?
7042 */
7043#endif /* E1K_WITH_TXD_CACHE */
7044#ifdef E1K_WITH_RXD_CACHE
7045 /*
7046 * There is no point in storing the RX descriptor cache in the saved
7047 * state, we just need to make sure it is empty.
7048 */
7049 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7050#endif /* E1K_WITH_RXD_CACHE */
7051 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7052 AssertRCReturn(rc, rc);
7053
7054 /* derived state */
7055 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7056
7057 E1kLog(("%s State has been restored\n", pThis->szPrf));
7058 e1kDumpState(pThis);
7059 }
7060 return VINF_SUCCESS;
7061}
7062
7063/**
7064 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7065 */
7066static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7067{
7068 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7069 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7070 RT_NOREF(pSSM);
7071
7072 /* Update promiscuous mode */
7073 if (pThisCC->pDrvR3)
7074 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7075
7076 /*
7077 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7078 * passed to us. We go through all this stuff if the link was up and we
7079 * wasn't teleported.
7080 */
7081 if ( (STATUS & STATUS_LU)
7082 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7083 && pThis->cMsLinkUpDelay)
7084 {
7085 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7086 }
7087 return VINF_SUCCESS;
7088}
7089
7090
7091
7092/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7093
7094/**
7095 * @callback_method_impl{FNRTSTRFORMATTYPE}
7096 */
7097static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7098 void *pvArgOutput,
7099 const char *pszType,
7100 void const *pvValue,
7101 int cchWidth,
7102 int cchPrecision,
7103 unsigned fFlags,
7104 void *pvUser)
7105{
7106 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7107 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7108 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7109 if (!pDesc)
7110 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7111
7112 size_t cbPrintf = 0;
7113 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7114 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7115 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7116 pDesc->status.fPIF ? "PIF" : "pif",
7117 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7118 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7119 pDesc->status.fVP ? "VP" : "vp",
7120 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7121 pDesc->status.fEOP ? "EOP" : "eop",
7122 pDesc->status.fDD ? "DD" : "dd",
7123 pDesc->status.fRXE ? "RXE" : "rxe",
7124 pDesc->status.fIPE ? "IPE" : "ipe",
7125 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7126 pDesc->status.fCE ? "CE" : "ce",
7127 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7128 E1K_SPEC_VLAN(pDesc->status.u16Special),
7129 E1K_SPEC_PRI(pDesc->status.u16Special));
7130 return cbPrintf;
7131}
7132
7133/**
7134 * @callback_method_impl{FNRTSTRFORMATTYPE}
7135 */
7136static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7137 void *pvArgOutput,
7138 const char *pszType,
7139 void const *pvValue,
7140 int cchWidth,
7141 int cchPrecision,
7142 unsigned fFlags,
7143 void *pvUser)
7144{
7145 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7146 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7147 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7148 if (!pDesc)
7149 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7150
7151 size_t cbPrintf = 0;
7152 switch (e1kGetDescType(pDesc))
7153 {
7154 case E1K_DTYP_CONTEXT:
7155 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7156 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7157 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7158 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7159 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7160 pDesc->context.dw2.fIDE ? " IDE":"",
7161 pDesc->context.dw2.fRS ? " RS" :"",
7162 pDesc->context.dw2.fTSE ? " TSE":"",
7163 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7164 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7165 pDesc->context.dw2.u20PAYLEN,
7166 pDesc->context.dw3.u8HDRLEN,
7167 pDesc->context.dw3.u16MSS,
7168 pDesc->context.dw3.fDD?"DD":"");
7169 break;
7170 case E1K_DTYP_DATA:
7171 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7172 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7173 pDesc->data.u64BufAddr,
7174 pDesc->data.cmd.u20DTALEN,
7175 pDesc->data.cmd.fIDE ? " IDE" :"",
7176 pDesc->data.cmd.fVLE ? " VLE" :"",
7177 pDesc->data.cmd.fRPS ? " RPS" :"",
7178 pDesc->data.cmd.fRS ? " RS" :"",
7179 pDesc->data.cmd.fTSE ? " TSE" :"",
7180 pDesc->data.cmd.fIFCS? " IFCS":"",
7181 pDesc->data.cmd.fEOP ? " EOP" :"",
7182 pDesc->data.dw3.fDD ? " DD" :"",
7183 pDesc->data.dw3.fEC ? " EC" :"",
7184 pDesc->data.dw3.fLC ? " LC" :"",
7185 pDesc->data.dw3.fTXSM? " TXSM":"",
7186 pDesc->data.dw3.fIXSM? " IXSM":"",
7187 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7188 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7189 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7190 break;
7191 case E1K_DTYP_LEGACY:
7192 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7193 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7194 pDesc->data.u64BufAddr,
7195 pDesc->legacy.cmd.u16Length,
7196 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7197 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7198 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7199 pDesc->legacy.cmd.fRS ? " RS" :"",
7200 pDesc->legacy.cmd.fIC ? " IC" :"",
7201 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7202 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7203 pDesc->legacy.dw3.fDD ? " DD" :"",
7204 pDesc->legacy.dw3.fEC ? " EC" :"",
7205 pDesc->legacy.dw3.fLC ? " LC" :"",
7206 pDesc->legacy.cmd.u8CSO,
7207 pDesc->legacy.dw3.u8CSS,
7208 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7209 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7210 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7211 break;
7212 default:
7213 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7214 break;
7215 }
7216
7217 return cbPrintf;
7218}
7219
7220/** Initializes debug helpers (logging format types). */
7221static int e1kInitDebugHelpers(void)
7222{
7223 int rc = VINF_SUCCESS;
7224 static bool s_fHelpersRegistered = false;
7225 if (!s_fHelpersRegistered)
7226 {
7227 s_fHelpersRegistered = true;
7228 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7229 AssertRCReturn(rc, rc);
7230 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7231 AssertRCReturn(rc, rc);
7232 }
7233 return rc;
7234}
7235
7236/**
7237 * Status info callback.
7238 *
7239 * @param pDevIns The device instance.
7240 * @param pHlp The output helpers.
7241 * @param pszArgs The arguments.
7242 */
7243static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7244{
7245 RT_NOREF(pszArgs);
7246 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7247 unsigned i;
7248 // bool fRcvRing = false;
7249 // bool fXmtRing = false;
7250
7251 /*
7252 * Parse args.
7253 if (pszArgs)
7254 {
7255 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7256 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7257 }
7258 */
7259
7260 /*
7261 * Show info.
7262 */
7263 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7264 pDevIns->iInstance,
7265 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7266 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7267 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7268 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7269
7270 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7271
7272 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7273 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7274
7275 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7276 {
7277 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7278 if (ra->ctl & RA_CTL_AV)
7279 {
7280 const char *pcszTmp;
7281 switch (ra->ctl & RA_CTL_AS)
7282 {
7283 case 0: pcszTmp = "DST"; break;
7284 case 1: pcszTmp = "SRC"; break;
7285 default: pcszTmp = "reserved";
7286 }
7287 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7288 }
7289 }
7290 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7291 uint32_t rdh = RDH;
7292 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7293 for (i = 0; i < cDescs; ++i)
7294 {
7295 E1KRXDESC desc;
7296 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7297 &desc, sizeof(desc));
7298 if (i == rdh)
7299 pHlp->pfnPrintf(pHlp, ">>> ");
7300 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7301 }
7302#ifdef E1K_WITH_RXD_CACHE
7303 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7304 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7305 if (rdh > pThis->iRxDCurrent)
7306 rdh -= pThis->iRxDCurrent;
7307 else
7308 rdh = cDescs + rdh - pThis->iRxDCurrent;
7309 for (i = 0; i < pThis->nRxDFetched; ++i)
7310 {
7311 if (i == pThis->iRxDCurrent)
7312 pHlp->pfnPrintf(pHlp, ">>> ");
7313 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7314 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7315 &pThis->aRxDescriptors[i]);
7316 }
7317#endif /* E1K_WITH_RXD_CACHE */
7318
7319 cDescs = TDLEN / sizeof(E1KTXDESC);
7320 uint32_t tdh = TDH;
7321 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7322 for (i = 0; i < cDescs; ++i)
7323 {
7324 E1KTXDESC desc;
7325 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7326 &desc, sizeof(desc));
7327 if (i == tdh)
7328 pHlp->pfnPrintf(pHlp, ">>> ");
7329 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7330 }
7331#ifdef E1K_WITH_TXD_CACHE
7332 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7333 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7334 if (tdh > pThis->iTxDCurrent)
7335 tdh -= pThis->iTxDCurrent;
7336 else
7337 tdh = cDescs + tdh - pThis->iTxDCurrent;
7338 for (i = 0; i < pThis->nTxDFetched; ++i)
7339 {
7340 if (i == pThis->iTxDCurrent)
7341 pHlp->pfnPrintf(pHlp, ">>> ");
7342 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7343 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7344 &pThis->aTxDescriptors[i]);
7345 }
7346#endif /* E1K_WITH_TXD_CACHE */
7347
7348
7349#ifdef E1K_INT_STATS
7350 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7351 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7352 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7353 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7354 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7355 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7356 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7357 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7358 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7359 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7360 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7361 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7362 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7363 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7364 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7365 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7366 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7367 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7368 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7369 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7370 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7371 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7372 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7373 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7374 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7375 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7376 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7377 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7378 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7379 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7380 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7381 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7382 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7383 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7384 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7385 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7386 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7387 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7388#endif /* E1K_INT_STATS */
7389
7390 e1kCsLeave(pThis);
7391}
7392
7393
7394
7395/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7396
7397/**
7398 * Detach notification.
7399 *
7400 * One port on the network card has been disconnected from the network.
7401 *
7402 * @param pDevIns The device instance.
7403 * @param iLUN The logical unit which is being detached.
7404 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7405 */
7406static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7407{
7408 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7409 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7410 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7411 RT_NOREF(fFlags);
7412
7413 AssertLogRelReturnVoid(iLUN == 0);
7414
7415 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7416
7417 /** @todo r=pritesh still need to check if i missed
7418 * to clean something in this function
7419 */
7420
7421 /*
7422 * Zero some important members.
7423 */
7424 pThisCC->pDrvBase = NULL;
7425 pThisCC->pDrvR3 = NULL;
7426#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7427 pThisR0->pDrvR0 = NIL_RTR0PTR;
7428 pThisRC->pDrvRC = NIL_RTRCPTR;
7429#endif
7430
7431 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7432}
7433
7434/**
7435 * Attach the Network attachment.
7436 *
7437 * One port on the network card has been connected to a network.
7438 *
7439 * @returns VBox status code.
7440 * @param pDevIns The device instance.
7441 * @param iLUN The logical unit which is being attached.
7442 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7443 *
7444 * @remarks This code path is not used during construction.
7445 */
7446static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7447{
7448 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7449 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7450 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7451 RT_NOREF(fFlags);
7452
7453 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7454
7455 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7456
7457 /*
7458 * Attach the driver.
7459 */
7460 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7461 if (RT_SUCCESS(rc))
7462 {
7463 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7464 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7465 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7466 if (RT_SUCCESS(rc))
7467 {
7468#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7469 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7470 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7471#endif
7472 }
7473 }
7474 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7475 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7476 {
7477 /* This should never happen because this function is not called
7478 * if there is no driver to attach! */
7479 Log(("%s No attached driver!\n", pThis->szPrf));
7480 }
7481
7482 /*
7483 * Temporary set the link down if it was up so that the guest will know
7484 * that we have change the configuration of the network card
7485 */
7486 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7487 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7488
7489 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7490 return rc;
7491}
7492
7493/**
7494 * @copydoc FNPDMDEVPOWEROFF
7495 */
7496static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7497{
7498 /* Poke thread waiting for buffer space. */
7499 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7500}
7501
7502/**
7503 * @copydoc FNPDMDEVRESET
7504 */
7505static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7506{
7507 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7508 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7509#ifdef E1K_TX_DELAY
7510 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7511#endif /* E1K_TX_DELAY */
7512 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7513 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7514 e1kXmitFreeBuf(pThis, pThisCC);
7515 pThis->u16TxPktLen = 0;
7516 pThis->fIPcsum = false;
7517 pThis->fTCPcsum = false;
7518 pThis->fIntMaskUsed = false;
7519 pThis->fDelayInts = false;
7520 pThis->fLocked = false;
7521 pThis->u64AckedAt = 0;
7522 e1kR3HardReset(pDevIns, pThis, pThisCC);
7523}
7524
7525/**
7526 * @copydoc FNPDMDEVSUSPEND
7527 */
7528static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7529{
7530 /* Poke thread waiting for buffer space. */
7531 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7532}
7533
7534/**
7535 * Device relocation callback.
7536 *
7537 * When this callback is called the device instance data, and if the
7538 * device have a GC component, is being relocated, or/and the selectors
7539 * have been changed. The device must use the chance to perform the
7540 * necessary pointer relocations and data updates.
7541 *
7542 * Before the GC code is executed the first time, this function will be
7543 * called with a 0 delta so GC pointer calculations can be one in one place.
7544 *
7545 * @param pDevIns Pointer to the device instance.
7546 * @param offDelta The relocation delta relative to the old location.
7547 *
7548 * @remark A relocation CANNOT fail.
7549 */
7550static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7551{
7552 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7553 if (pThisRC)
7554 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7555 RT_NOREF(offDelta);
7556}
7557
7558/**
7559 * Destruct a device instance.
7560 *
7561 * We need to free non-VM resources only.
7562 *
7563 * @returns VBox status code.
7564 * @param pDevIns The device instance data.
7565 * @thread EMT
7566 */
7567static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7568{
7569 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7570 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7571
7572 e1kDumpState(pThis);
7573 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7574 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7575 {
7576 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7577 {
7578 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7579 RTThreadYield();
7580 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7581 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7582 }
7583#ifdef E1K_WITH_TX_CS
7584 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7585#endif /* E1K_WITH_TX_CS */
7586 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7587 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7588 }
7589 return VINF_SUCCESS;
7590}
7591
7592
7593/**
7594 * Set PCI configuration space registers.
7595 *
7596 * @param pci Reference to PCI device structure.
7597 * @thread EMT
7598 */
7599static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7600{
7601 Assert(eChip < RT_ELEMENTS(g_aChips));
7602 /* Configure PCI Device, assume 32-bit mode ******************************/
7603 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7604 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7605 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7606 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7607
7608 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7609 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7610 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7611 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7612 /* Stepping A2 */
7613 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7614 /* Ethernet adapter */
7615 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7616 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7617 /* normal single function Ethernet controller */
7618 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7619 /* Memory Register Base Address */
7620 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7621 /* Memory Flash Base Address */
7622 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7623 /* IO Register Base Address */
7624 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7625 /* Expansion ROM Base Address */
7626 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7627 /* Capabilities Pointer */
7628 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7629 /* Interrupt Pin: INTA# */
7630 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7631 /* Max_Lat/Min_Gnt: very high priority and time slice */
7632 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7633 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7634
7635 /* PCI Power Management Registers ****************************************/
7636 /* Capability ID: PCI Power Management Registers */
7637 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7638 /* Next Item Pointer: PCI-X */
7639 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7640 /* Power Management Capabilities: PM disabled, DSI */
7641 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7642 0x0002 | VBOX_PCI_PM_CAP_DSI);
7643 /* Power Management Control / Status Register: PM disabled */
7644 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7645 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7646 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7647 /* Data Register: PM disabled, always 0 */
7648 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7649
7650 /* PCI-X Configuration Registers *****************************************/
7651 /* Capability ID: PCI-X Configuration Registers */
7652 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7653#ifdef E1K_WITH_MSI
7654 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7655#else
7656 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7657 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7658#endif
7659 /* PCI-X Command: Enable Relaxed Ordering */
7660 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7661 /* PCI-X Status: 32-bit, 66MHz*/
7662 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7663 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7664}
7665
7666/**
7667 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7668 */
7669static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7670{
7671 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7672 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7673 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7674 int rc;
7675
7676 /*
7677 * Initialize the instance data (state).
7678 * Note! Caller has initialized it to ZERO already.
7679 */
7680 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7681 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7682 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7683 pThis->u16TxPktLen = 0;
7684 pThis->fIPcsum = false;
7685 pThis->fTCPcsum = false;
7686 pThis->fIntMaskUsed = false;
7687 pThis->fDelayInts = false;
7688 pThis->fLocked = false;
7689 pThis->u64AckedAt = 0;
7690 pThis->led.u32Magic = PDMLED_MAGIC;
7691 pThis->u32PktNo = 1;
7692
7693 pThisCC->pDevInsR3 = pDevIns;
7694 pThisCC->pShared = pThis;
7695
7696 /* Interfaces */
7697 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7698
7699 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7700 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7701 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7702
7703 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7704
7705 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7706 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7707 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7708
7709 /*
7710 * Internal validations.
7711 */
7712 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7713 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7714 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7715 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7716 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7717 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7718 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7719 VERR_INTERNAL_ERROR_4);
7720
7721 /*
7722 * Validate configuration.
7723 */
7724 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7725 "MAC|"
7726 "CableConnected|"
7727 "AdapterType|"
7728 "LineSpeed|"
7729 "ItrEnabled|"
7730 "ItrRxEnabled|"
7731 "EthernetCRC|"
7732 "GSOEnabled|"
7733 "LinkUpDelay|"
7734 "StatNo",
7735 "");
7736
7737 /** @todo LineSpeed unused! */
7738
7739 /*
7740 * Get config params
7741 */
7742 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7743 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7744 if (RT_FAILURE(rc))
7745 return PDMDEV_SET_ERROR(pDevIns, rc,
7746 N_("Configuration error: Failed to get MAC address"));
7747 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7748 if (RT_FAILURE(rc))
7749 return PDMDEV_SET_ERROR(pDevIns, rc,
7750 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7751 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7752 if (RT_FAILURE(rc))
7753 return PDMDEV_SET_ERROR(pDevIns, rc,
7754 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7755 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7756
7757 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7758 if (RT_FAILURE(rc))
7759 return PDMDEV_SET_ERROR(pDevIns, rc,
7760 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7761
7762 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7763 if (RT_FAILURE(rc))
7764 return PDMDEV_SET_ERROR(pDevIns, rc,
7765 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7766
7767 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7768 if (RT_FAILURE(rc))
7769 return PDMDEV_SET_ERROR(pDevIns, rc,
7770 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7771
7772 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7773 if (RT_FAILURE(rc))
7774 return PDMDEV_SET_ERROR(pDevIns, rc,
7775 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7776
7777 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7778 if (RT_FAILURE(rc))
7779 return PDMDEV_SET_ERROR(pDevIns, rc,
7780 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7781
7782 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7783 if (RT_FAILURE(rc))
7784 return PDMDEV_SET_ERROR(pDevIns, rc,
7785 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7786 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7787 if (pThis->cMsLinkUpDelay > 5000)
7788 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7789 else if (pThis->cMsLinkUpDelay == 0)
7790 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7791
7792 uint32_t uStatNo = iInstance;
7793 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, iInstance);
7794 if (RT_FAILURE(rc))
7795 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7796
7797 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7798 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7799 pThis->fEthernetCRC ? "on" : "off",
7800 pThis->fGSOEnabled ? "enabled" : "disabled",
7801 pThis->fItrEnabled ? "enabled" : "disabled",
7802 pThis->fItrRxEnabled ? "enabled" : "disabled",
7803 pThis->fTidEnabled ? "enabled" : "disabled",
7804 pDevIns->fR0Enabled ? "enabled" : "disabled",
7805 pDevIns->fRCEnabled ? "enabled" : "disabled"));
7806
7807 /*
7808 * Initialize sub-components and register everything with the VMM.
7809 */
7810
7811 /* Initialize the EEPROM. */
7812 pThisCC->eeprom.init(pThis->macConfigured);
7813
7814 /* Initialize internal PHY. */
7815 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7816
7817 /* Initialize critical sections. We do our own locking. */
7818 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7819 AssertRCReturn(rc, rc);
7820
7821 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7822 AssertRCReturn(rc, rc);
7823 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7824 AssertRCReturn(rc, rc);
7825#ifdef E1K_WITH_TX_CS
7826 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7827 AssertRCReturn(rc, rc);
7828#endif
7829
7830 /* Saved state registration. */
7831 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7832 NULL, e1kLiveExec, NULL,
7833 e1kSavePrep, e1kSaveExec, NULL,
7834 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7835 AssertRCReturn(rc, rc);
7836
7837 /* Set PCI config registers and register ourselves with the PCI bus. */
7838 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
7839 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
7840 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
7841 AssertRCReturn(rc, rc);
7842
7843#ifdef E1K_WITH_MSI
7844 PDMMSIREG MsiReg;
7845 RT_ZERO(MsiReg);
7846 MsiReg.cMsiVectors = 1;
7847 MsiReg.iMsiCapOffset = 0x80;
7848 MsiReg.iMsiNextOffset = 0x0;
7849 MsiReg.fMsi64bit = false;
7850 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7851 AssertRCReturn(rc, rc);
7852#endif
7853
7854 /*
7855 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
7856 * From the spec (regarding flags):
7857 * For registers that should be accessed as 32-bit double words,
7858 * partial writes (less than a 32-bit double word) is ignored.
7859 * Partial reads return all 32 bits of data regardless of the
7860 * byte enables.
7861 */
7862 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
7863 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
7864 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
7865 AssertRCReturn(rc, rc);
7866 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
7867 AssertRCReturn(rc, rc);
7868
7869 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
7870 static IOMIOPORTDESC const s_aExtDescs[] =
7871 {
7872 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7873 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7874 { NULL, NULL, NULL, NULL }
7875 };
7876 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
7877 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
7878 AssertRCReturn(rc, rc);
7879 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
7880 AssertRCReturn(rc, rc);
7881
7882 /* Create transmit queue */
7883 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
7884 AssertRCReturn(rc, rc);
7885
7886#ifdef E1K_TX_DELAY
7887 /* Create Transmit Delay Timer */
7888 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7889 "E1000 Transmit Delay Timer", &pThis->hTXDTimer);
7890 AssertRCReturn(rc, rc);
7891 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
7892 AssertRCReturn(rc, rc);
7893#endif /* E1K_TX_DELAY */
7894
7895//#ifdef E1K_USE_TX_TIMERS
7896 if (pThis->fTidEnabled)
7897 {
7898 /* Create Transmit Interrupt Delay Timer */
7899 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7900 "E1000 Transmit Interrupt Delay Timer", &pThis->hTIDTimer);
7901 AssertRCReturn(rc, rc);
7902
7903# ifndef E1K_NO_TAD
7904 /* Create Transmit Absolute Delay Timer */
7905 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7906 "E1000 Transmit Absolute Delay Timer", &pThis->hTADTimer);
7907 AssertRCReturn(rc, rc);
7908# endif /* E1K_NO_TAD */
7909 }
7910//#endif /* E1K_USE_TX_TIMERS */
7911
7912#ifdef E1K_USE_RX_TIMERS
7913 /* Create Receive Interrupt Delay Timer */
7914 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7915 "E1000 Receive Interrupt Delay Timer", &pThis->hRIDTimer);
7916 AssertRCReturn(rc, rc);
7917
7918 /* Create Receive Absolute Delay Timer */
7919 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7920 "E1000 Receive Absolute Delay Timer", &pThis->hRADTimer);
7921 AssertRCReturn(rc, rc);
7922#endif /* E1K_USE_RX_TIMERS */
7923
7924 /* Create Late Interrupt Timer */
7925 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7926 "E1000 Late Interrupt Timer", &pThis->hIntTimer);
7927 AssertRCReturn(rc, rc);
7928
7929 /* Create Link Up Timer */
7930 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7931 "E1000 Link Up Timer", &pThis->hLUTimer);
7932 AssertRCReturn(rc, rc);
7933
7934 /* Register the info item */
7935 char szTmp[20];
7936 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7937 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7938
7939 /* Status driver */
7940 PPDMIBASE pBase;
7941 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
7942 if (RT_FAILURE(rc))
7943 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7944 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7945
7946 /* Network driver */
7947 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7948 if (RT_SUCCESS(rc))
7949 {
7950 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7951 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7952
7953#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7954 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7955 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7956#endif
7957 }
7958 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7959 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7960 {
7961 /* No error! */
7962 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7963 }
7964 else
7965 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7966
7967 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
7968 AssertRCReturn(rc, rc);
7969
7970 rc = e1kInitDebugHelpers();
7971 AssertRCReturn(rc, rc);
7972
7973 e1kR3HardReset(pDevIns, pThis, pThisCC);
7974
7975 /*
7976 * Register statistics.
7977 * The /Public/ bits are official and used by session info in the GUI.
7978 */
7979 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7980 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
7981 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7982 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
7983 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
7984 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
7985
7986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
7987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
7988
7989#if defined(VBOX_WITH_STATISTICS)
7990 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
7991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
7992 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
7993 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
7994 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
7995 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
7996 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
7997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
7998 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
7999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8000 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8001 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8003 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8006 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8007 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8013 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8015
8016 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8025 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8026 {
8027 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8028 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8029 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8030 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8031 }
8032#endif /* VBOX_WITH_STATISTICS */
8033
8034#ifdef E1K_INT_STATS
8035 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8036 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8037 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8038 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8039 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8040 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8041 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8042 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8043 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8044 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8045 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8046 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8047 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8048 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8049 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8050 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8051 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8052 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8053 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8054 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8055 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8056 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8057 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8058 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8059 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8060 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8061 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8062 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8063 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8064 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8065 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8066 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8067 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8068 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8069 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8070 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8071 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8072 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8073 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8074 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8075 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8076#endif /* E1K_INT_STATS */
8077
8078 return VINF_SUCCESS;
8079}
8080
8081#else /* !IN_RING3 */
8082
8083/**
8084 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8085 */
8086static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8087{
8088 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8089 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8090 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8091
8092 /* Initialize context specific state data: */
8093 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8094 /** @todo @bugref{9218} ring-0 driver stuff */
8095 pThisCC->CTX_SUFF(pDrv) = NULL;
8096 pThisCC->CTX_SUFF(pTxSg) = NULL;
8097
8098 /* Configure critical sections the same way: */
8099 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8100 AssertRCReturn(rc, rc);
8101
8102 /* Set up MMIO and I/O port callbacks for this context: */
8103 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8104 AssertRCReturn(rc, rc);
8105
8106 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8107 AssertRCReturn(rc, rc);
8108
8109 return VINF_SUCCESS;
8110}
8111
8112#endif /* !IN_RING3 */
8113
8114/**
8115 * The device registration structure.
8116 */
8117const PDMDEVREG g_DeviceE1000 =
8118{
8119 /* .u32version = */ PDM_DEVREG_VERSION,
8120 /* .uReserved0 = */ 0,
8121 /* .szName = */ "e1000",
8122 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8123 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8124 /* .cMaxInstances = */ ~0U,
8125 /* .uSharedVersion = */ 42,
8126 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8127 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8128 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8129 /* .cMaxPciDevices = */ 1,
8130 /* .cMaxMsixVectors = */ 0,
8131 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8132#if defined(IN_RING3)
8133 /* .pszRCMod = */ "VBoxDDRC.rc",
8134 /* .pszR0Mod = */ "VBoxDDR0.r0",
8135 /* .pfnConstruct = */ e1kR3Construct,
8136 /* .pfnDestruct = */ e1kR3Destruct,
8137 /* .pfnRelocate = */ e1kR3Relocate,
8138 /* .pfnMemSetup = */ NULL,
8139 /* .pfnPowerOn = */ NULL,
8140 /* .pfnReset = */ e1kR3Reset,
8141 /* .pfnSuspend = */ e1kR3Suspend,
8142 /* .pfnResume = */ NULL,
8143 /* .pfnAttach = */ e1kR3Attach,
8144 /* .pfnDeatch = */ e1kR3Detach,
8145 /* .pfnQueryInterface = */ NULL,
8146 /* .pfnInitComplete = */ NULL,
8147 /* .pfnPowerOff = */ e1kR3PowerOff,
8148 /* .pfnSoftReset = */ NULL,
8149 /* .pfnReserved0 = */ NULL,
8150 /* .pfnReserved1 = */ NULL,
8151 /* .pfnReserved2 = */ NULL,
8152 /* .pfnReserved3 = */ NULL,
8153 /* .pfnReserved4 = */ NULL,
8154 /* .pfnReserved5 = */ NULL,
8155 /* .pfnReserved6 = */ NULL,
8156 /* .pfnReserved7 = */ NULL,
8157#elif defined(IN_RING0)
8158 /* .pfnEarlyConstruct = */ NULL,
8159 /* .pfnConstruct = */ e1kRZConstruct,
8160 /* .pfnDestruct = */ NULL,
8161 /* .pfnFinalDestruct = */ NULL,
8162 /* .pfnRequest = */ NULL,
8163 /* .pfnReserved0 = */ NULL,
8164 /* .pfnReserved1 = */ NULL,
8165 /* .pfnReserved2 = */ NULL,
8166 /* .pfnReserved3 = */ NULL,
8167 /* .pfnReserved4 = */ NULL,
8168 /* .pfnReserved5 = */ NULL,
8169 /* .pfnReserved6 = */ NULL,
8170 /* .pfnReserved7 = */ NULL,
8171#elif defined(IN_RC)
8172 /* .pfnConstruct = */ e1kRZConstruct,
8173 /* .pfnReserved0 = */ NULL,
8174 /* .pfnReserved1 = */ NULL,
8175 /* .pfnReserved2 = */ NULL,
8176 /* .pfnReserved3 = */ NULL,
8177 /* .pfnReserved4 = */ NULL,
8178 /* .pfnReserved5 = */ NULL,
8179 /* .pfnReserved6 = */ NULL,
8180 /* .pfnReserved7 = */ NULL,
8181#else
8182# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8183#endif
8184 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8185};
8186
8187#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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