VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 82652

Last change on this file since 82652 was 82368, checked in by vboxsync, 5 years ago

Dev/E1000: Another trivial issue detected by parfait.
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1/* $Id: DevE1000.cpp 82368 2019-12-04 09:47:53Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2019 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280/** Gets the specfieid bits from the register. */
281#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
282#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
284#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
285#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286
287#define CTRL_SLU UINT32_C(0x00000040)
288#define CTRL_MDIO UINT32_C(0x00100000)
289#define CTRL_MDC UINT32_C(0x00200000)
290#define CTRL_MDIO_DIR UINT32_C(0x01000000)
291#define CTRL_MDC_DIR UINT32_C(0x02000000)
292#define CTRL_RESET UINT32_C(0x04000000)
293#define CTRL_VME UINT32_C(0x40000000)
294
295#define STATUS_LU UINT32_C(0x00000002)
296#define STATUS_TXOFF UINT32_C(0x00000010)
297
298#define EECD_EE_WIRES UINT32_C(0x0F)
299#define EECD_EE_REQ UINT32_C(0x40)
300#define EECD_EE_GNT UINT32_C(0x80)
301
302#define EERD_START UINT32_C(0x00000001)
303#define EERD_DONE UINT32_C(0x00000010)
304#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
305#define EERD_DATA_SHIFT 16
306#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
307#define EERD_ADDR_SHIFT 8
308
309#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
310#define MDIC_DATA_SHIFT 0
311#define MDIC_REG_MASK UINT32_C(0x001F0000)
312#define MDIC_REG_SHIFT 16
313#define MDIC_PHY_MASK UINT32_C(0x03E00000)
314#define MDIC_PHY_SHIFT 21
315#define MDIC_OP_WRITE UINT32_C(0x04000000)
316#define MDIC_OP_READ UINT32_C(0x08000000)
317#define MDIC_READY UINT32_C(0x10000000)
318#define MDIC_INT_EN UINT32_C(0x20000000)
319#define MDIC_ERROR UINT32_C(0x40000000)
320
321#define TCTL_EN UINT32_C(0x00000002)
322#define TCTL_PSP UINT32_C(0x00000008)
323
324#define RCTL_EN UINT32_C(0x00000002)
325#define RCTL_UPE UINT32_C(0x00000008)
326#define RCTL_MPE UINT32_C(0x00000010)
327#define RCTL_LPE UINT32_C(0x00000020)
328#define RCTL_LBM_MASK UINT32_C(0x000000C0)
329#define RCTL_LBM_SHIFT 6
330#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
331#define RCTL_RDMTS_SHIFT 8
332#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
333#define RCTL_MO_MASK UINT32_C(0x00003000)
334#define RCTL_MO_SHIFT 12
335#define RCTL_BAM UINT32_C(0x00008000)
336#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
337#define RCTL_BSIZE_SHIFT 16
338#define RCTL_VFE UINT32_C(0x00040000)
339#define RCTL_CFIEN UINT32_C(0x00080000)
340#define RCTL_CFI UINT32_C(0x00100000)
341#define RCTL_BSEX UINT32_C(0x02000000)
342#define RCTL_SECRC UINT32_C(0x04000000)
343
344#define ICR_TXDW UINT32_C(0x00000001)
345#define ICR_TXQE UINT32_C(0x00000002)
346#define ICR_LSC UINT32_C(0x00000004)
347#define ICR_RXDMT0 UINT32_C(0x00000010)
348#define ICR_RXT0 UINT32_C(0x00000080)
349#define ICR_TXD_LOW UINT32_C(0x00008000)
350#define RDTR_FPD UINT32_C(0x80000000)
351
352#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
353typedef struct
354{
355 unsigned rxa : 7;
356 unsigned rxa_r : 9;
357 unsigned txa : 16;
358} PBAST;
359AssertCompileSize(PBAST, 4);
360
361#define TXDCTL_WTHRESH_MASK 0x003F0000
362#define TXDCTL_WTHRESH_SHIFT 16
363#define TXDCTL_LWTHRESH_MASK 0xFE000000
364#define TXDCTL_LWTHRESH_SHIFT 25
365
366#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
367#define RXCSUM_PCSS_SHIFT 0
368
369/** @name Register access macros
370 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
371 * @{ */
372#define CTRL pThis->auRegs[CTRL_IDX]
373#define STATUS pThis->auRegs[STATUS_IDX]
374#define EECD pThis->auRegs[EECD_IDX]
375#define EERD pThis->auRegs[EERD_IDX]
376#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
377#define FLA pThis->auRegs[FLA_IDX]
378#define MDIC pThis->auRegs[MDIC_IDX]
379#define FCAL pThis->auRegs[FCAL_IDX]
380#define FCAH pThis->auRegs[FCAH_IDX]
381#define FCT pThis->auRegs[FCT_IDX]
382#define VET pThis->auRegs[VET_IDX]
383#define ICR pThis->auRegs[ICR_IDX]
384#define ITR pThis->auRegs[ITR_IDX]
385#define ICS pThis->auRegs[ICS_IDX]
386#define IMS pThis->auRegs[IMS_IDX]
387#define IMC pThis->auRegs[IMC_IDX]
388#define RCTL pThis->auRegs[RCTL_IDX]
389#define FCTTV pThis->auRegs[FCTTV_IDX]
390#define TXCW pThis->auRegs[TXCW_IDX]
391#define RXCW pThis->auRegs[RXCW_IDX]
392#define TCTL pThis->auRegs[TCTL_IDX]
393#define TIPG pThis->auRegs[TIPG_IDX]
394#define AIFS pThis->auRegs[AIFS_IDX]
395#define LEDCTL pThis->auRegs[LEDCTL_IDX]
396#define PBA pThis->auRegs[PBA_IDX]
397#define FCRTL pThis->auRegs[FCRTL_IDX]
398#define FCRTH pThis->auRegs[FCRTH_IDX]
399#define RDFH pThis->auRegs[RDFH_IDX]
400#define RDFT pThis->auRegs[RDFT_IDX]
401#define RDFHS pThis->auRegs[RDFHS_IDX]
402#define RDFTS pThis->auRegs[RDFTS_IDX]
403#define RDFPC pThis->auRegs[RDFPC_IDX]
404#define RDBAL pThis->auRegs[RDBAL_IDX]
405#define RDBAH pThis->auRegs[RDBAH_IDX]
406#define RDLEN pThis->auRegs[RDLEN_IDX]
407#define RDH pThis->auRegs[RDH_IDX]
408#define RDT pThis->auRegs[RDT_IDX]
409#define RDTR pThis->auRegs[RDTR_IDX]
410#define RXDCTL pThis->auRegs[RXDCTL_IDX]
411#define RADV pThis->auRegs[RADV_IDX]
412#define RSRPD pThis->auRegs[RSRPD_IDX]
413#define TXDMAC pThis->auRegs[TXDMAC_IDX]
414#define TDFH pThis->auRegs[TDFH_IDX]
415#define TDFT pThis->auRegs[TDFT_IDX]
416#define TDFHS pThis->auRegs[TDFHS_IDX]
417#define TDFTS pThis->auRegs[TDFTS_IDX]
418#define TDFPC pThis->auRegs[TDFPC_IDX]
419#define TDBAL pThis->auRegs[TDBAL_IDX]
420#define TDBAH pThis->auRegs[TDBAH_IDX]
421#define TDLEN pThis->auRegs[TDLEN_IDX]
422#define TDH pThis->auRegs[TDH_IDX]
423#define TDT pThis->auRegs[TDT_IDX]
424#define TIDV pThis->auRegs[TIDV_IDX]
425#define TXDCTL pThis->auRegs[TXDCTL_IDX]
426#define TADV pThis->auRegs[TADV_IDX]
427#define TSPMT pThis->auRegs[TSPMT_IDX]
428#define CRCERRS pThis->auRegs[CRCERRS_IDX]
429#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
430#define SYMERRS pThis->auRegs[SYMERRS_IDX]
431#define RXERRC pThis->auRegs[RXERRC_IDX]
432#define MPC pThis->auRegs[MPC_IDX]
433#define SCC pThis->auRegs[SCC_IDX]
434#define ECOL pThis->auRegs[ECOL_IDX]
435#define MCC pThis->auRegs[MCC_IDX]
436#define LATECOL pThis->auRegs[LATECOL_IDX]
437#define COLC pThis->auRegs[COLC_IDX]
438#define DC pThis->auRegs[DC_IDX]
439#define TNCRS pThis->auRegs[TNCRS_IDX]
440/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
441#define CEXTERR pThis->auRegs[CEXTERR_IDX]
442#define RLEC pThis->auRegs[RLEC_IDX]
443#define XONRXC pThis->auRegs[XONRXC_IDX]
444#define XONTXC pThis->auRegs[XONTXC_IDX]
445#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
446#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
447#define FCRUC pThis->auRegs[FCRUC_IDX]
448#define PRC64 pThis->auRegs[PRC64_IDX]
449#define PRC127 pThis->auRegs[PRC127_IDX]
450#define PRC255 pThis->auRegs[PRC255_IDX]
451#define PRC511 pThis->auRegs[PRC511_IDX]
452#define PRC1023 pThis->auRegs[PRC1023_IDX]
453#define PRC1522 pThis->auRegs[PRC1522_IDX]
454#define GPRC pThis->auRegs[GPRC_IDX]
455#define BPRC pThis->auRegs[BPRC_IDX]
456#define MPRC pThis->auRegs[MPRC_IDX]
457#define GPTC pThis->auRegs[GPTC_IDX]
458#define GORCL pThis->auRegs[GORCL_IDX]
459#define GORCH pThis->auRegs[GORCH_IDX]
460#define GOTCL pThis->auRegs[GOTCL_IDX]
461#define GOTCH pThis->auRegs[GOTCH_IDX]
462#define RNBC pThis->auRegs[RNBC_IDX]
463#define RUC pThis->auRegs[RUC_IDX]
464#define RFC pThis->auRegs[RFC_IDX]
465#define ROC pThis->auRegs[ROC_IDX]
466#define RJC pThis->auRegs[RJC_IDX]
467#define MGTPRC pThis->auRegs[MGTPRC_IDX]
468#define MGTPDC pThis->auRegs[MGTPDC_IDX]
469#define MGTPTC pThis->auRegs[MGTPTC_IDX]
470#define TORL pThis->auRegs[TORL_IDX]
471#define TORH pThis->auRegs[TORH_IDX]
472#define TOTL pThis->auRegs[TOTL_IDX]
473#define TOTH pThis->auRegs[TOTH_IDX]
474#define TPR pThis->auRegs[TPR_IDX]
475#define TPT pThis->auRegs[TPT_IDX]
476#define PTC64 pThis->auRegs[PTC64_IDX]
477#define PTC127 pThis->auRegs[PTC127_IDX]
478#define PTC255 pThis->auRegs[PTC255_IDX]
479#define PTC511 pThis->auRegs[PTC511_IDX]
480#define PTC1023 pThis->auRegs[PTC1023_IDX]
481#define PTC1522 pThis->auRegs[PTC1522_IDX]
482#define MPTC pThis->auRegs[MPTC_IDX]
483#define BPTC pThis->auRegs[BPTC_IDX]
484#define TSCTC pThis->auRegs[TSCTC_IDX]
485#define TSCTFC pThis->auRegs[TSCTFC_IDX]
486#define RXCSUM pThis->auRegs[RXCSUM_IDX]
487#define WUC pThis->auRegs[WUC_IDX]
488#define WUFC pThis->auRegs[WUFC_IDX]
489#define WUS pThis->auRegs[WUS_IDX]
490#define MANC pThis->auRegs[MANC_IDX]
491#define IPAV pThis->auRegs[IPAV_IDX]
492#define WUPL pThis->auRegs[WUPL_IDX]
493/** @} */
494
495/**
496 * Indices of memory-mapped registers in register table.
497 */
498typedef enum
499{
500 CTRL_IDX,
501 STATUS_IDX,
502 EECD_IDX,
503 EERD_IDX,
504 CTRL_EXT_IDX,
505 FLA_IDX,
506 MDIC_IDX,
507 FCAL_IDX,
508 FCAH_IDX,
509 FCT_IDX,
510 VET_IDX,
511 ICR_IDX,
512 ITR_IDX,
513 ICS_IDX,
514 IMS_IDX,
515 IMC_IDX,
516 RCTL_IDX,
517 FCTTV_IDX,
518 TXCW_IDX,
519 RXCW_IDX,
520 TCTL_IDX,
521 TIPG_IDX,
522 AIFS_IDX,
523 LEDCTL_IDX,
524 PBA_IDX,
525 FCRTL_IDX,
526 FCRTH_IDX,
527 RDFH_IDX,
528 RDFT_IDX,
529 RDFHS_IDX,
530 RDFTS_IDX,
531 RDFPC_IDX,
532 RDBAL_IDX,
533 RDBAH_IDX,
534 RDLEN_IDX,
535 RDH_IDX,
536 RDT_IDX,
537 RDTR_IDX,
538 RXDCTL_IDX,
539 RADV_IDX,
540 RSRPD_IDX,
541 TXDMAC_IDX,
542 TDFH_IDX,
543 TDFT_IDX,
544 TDFHS_IDX,
545 TDFTS_IDX,
546 TDFPC_IDX,
547 TDBAL_IDX,
548 TDBAH_IDX,
549 TDLEN_IDX,
550 TDH_IDX,
551 TDT_IDX,
552 TIDV_IDX,
553 TXDCTL_IDX,
554 TADV_IDX,
555 TSPMT_IDX,
556 CRCERRS_IDX,
557 ALGNERRC_IDX,
558 SYMERRS_IDX,
559 RXERRC_IDX,
560 MPC_IDX,
561 SCC_IDX,
562 ECOL_IDX,
563 MCC_IDX,
564 LATECOL_IDX,
565 COLC_IDX,
566 DC_IDX,
567 TNCRS_IDX,
568 SEC_IDX,
569 CEXTERR_IDX,
570 RLEC_IDX,
571 XONRXC_IDX,
572 XONTXC_IDX,
573 XOFFRXC_IDX,
574 XOFFTXC_IDX,
575 FCRUC_IDX,
576 PRC64_IDX,
577 PRC127_IDX,
578 PRC255_IDX,
579 PRC511_IDX,
580 PRC1023_IDX,
581 PRC1522_IDX,
582 GPRC_IDX,
583 BPRC_IDX,
584 MPRC_IDX,
585 GPTC_IDX,
586 GORCL_IDX,
587 GORCH_IDX,
588 GOTCL_IDX,
589 GOTCH_IDX,
590 RNBC_IDX,
591 RUC_IDX,
592 RFC_IDX,
593 ROC_IDX,
594 RJC_IDX,
595 MGTPRC_IDX,
596 MGTPDC_IDX,
597 MGTPTC_IDX,
598 TORL_IDX,
599 TORH_IDX,
600 TOTL_IDX,
601 TOTH_IDX,
602 TPR_IDX,
603 TPT_IDX,
604 PTC64_IDX,
605 PTC127_IDX,
606 PTC255_IDX,
607 PTC511_IDX,
608 PTC1023_IDX,
609 PTC1522_IDX,
610 MPTC_IDX,
611 BPTC_IDX,
612 TSCTC_IDX,
613 TSCTFC_IDX,
614 RXCSUM_IDX,
615 WUC_IDX,
616 WUFC_IDX,
617 WUS_IDX,
618 MANC_IDX,
619 IPAV_IDX,
620 WUPL_IDX,
621 MTA_IDX,
622 RA_IDX,
623 VFTA_IDX,
624 IP4AT_IDX,
625 IP6AT_IDX,
626 WUPM_IDX,
627 FFLT_IDX,
628 FFMT_IDX,
629 FFVT_IDX,
630 PBM_IDX,
631 RA_82542_IDX,
632 MTA_82542_IDX,
633 VFTA_82542_IDX,
634 E1K_NUM_OF_REGS
635} E1kRegIndex;
636
637#define E1K_NUM_OF_32BIT_REGS MTA_IDX
638/** The number of registers with strictly increasing offset. */
639#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
640
641
642/**
643 * Define E1000-specific EEPROM layout.
644 */
645struct E1kEEPROM
646{
647 public:
648 EEPROM93C46 eeprom;
649
650#ifdef IN_RING3
651 /**
652 * Initialize EEPROM content.
653 *
654 * @param macAddr MAC address of E1000.
655 */
656 void init(RTMAC &macAddr)
657 {
658 eeprom.init();
659 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
660 eeprom.m_au16Data[0x04] = 0xFFFF;
661 /*
662 * bit 3 - full support for power management
663 * bit 10 - full duplex
664 */
665 eeprom.m_au16Data[0x0A] = 0x4408;
666 eeprom.m_au16Data[0x0B] = 0x001E;
667 eeprom.m_au16Data[0x0C] = 0x8086;
668 eeprom.m_au16Data[0x0D] = 0x100E;
669 eeprom.m_au16Data[0x0E] = 0x8086;
670 eeprom.m_au16Data[0x0F] = 0x3040;
671 eeprom.m_au16Data[0x21] = 0x7061;
672 eeprom.m_au16Data[0x22] = 0x280C;
673 eeprom.m_au16Data[0x23] = 0x00C8;
674 eeprom.m_au16Data[0x24] = 0x00C8;
675 eeprom.m_au16Data[0x2F] = 0x0602;
676 updateChecksum();
677 };
678
679 /**
680 * Compute the checksum as required by E1000 and store it
681 * in the last word.
682 */
683 void updateChecksum()
684 {
685 uint16_t u16Checksum = 0;
686
687 for (int i = 0; i < eeprom.SIZE-1; i++)
688 u16Checksum += eeprom.m_au16Data[i];
689 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
690 };
691
692 /**
693 * First 6 bytes of EEPROM contain MAC address.
694 *
695 * @returns MAC address of E1000.
696 */
697 void getMac(PRTMAC pMac)
698 {
699 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
700 };
701
702 uint32_t read()
703 {
704 return eeprom.read();
705 }
706
707 void write(uint32_t u32Wires)
708 {
709 eeprom.write(u32Wires);
710 }
711
712 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
713 {
714 return eeprom.readWord(u32Addr, pu16Value);
715 }
716
717 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
718 {
719 return eeprom.load(pHlp, pSSM);
720 }
721
722 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
723 {
724 eeprom.save(pHlp, pSSM);
725 }
726#endif /* IN_RING3 */
727};
728
729
730#define E1K_SPEC_VLAN(s) (s & 0xFFF)
731#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
732#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
733
734struct E1kRxDStatus
735{
736 /** @name Descriptor Status field (3.2.3.1)
737 * @{ */
738 unsigned fDD : 1; /**< Descriptor Done. */
739 unsigned fEOP : 1; /**< End of packet. */
740 unsigned fIXSM : 1; /**< Ignore checksum indication. */
741 unsigned fVP : 1; /**< VLAN, matches VET. */
742 unsigned : 1;
743 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
744 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
745 unsigned fPIF : 1; /**< Passed in-exact filter */
746 /** @} */
747 /** @name Descriptor Errors field (3.2.3.2)
748 * (Only valid when fEOP and fDD are set.)
749 * @{ */
750 unsigned fCE : 1; /**< CRC or alignment error. */
751 unsigned : 4; /**< Reserved, varies with different models... */
752 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
753 unsigned fIPE : 1; /**< IP Checksum error. */
754 unsigned fRXE : 1; /**< RX Data error. */
755 /** @} */
756 /** @name Descriptor Special field (3.2.3.3)
757 * @{ */
758 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
759 /** @} */
760};
761typedef struct E1kRxDStatus E1KRXDST;
762
763struct E1kRxDesc_st
764{
765 uint64_t u64BufAddr; /**< Address of data buffer */
766 uint16_t u16Length; /**< Length of data in buffer */
767 uint16_t u16Checksum; /**< Packet checksum */
768 E1KRXDST status;
769};
770typedef struct E1kRxDesc_st E1KRXDESC;
771AssertCompileSize(E1KRXDESC, 16);
772
773#define E1K_DTYP_LEGACY -1
774#define E1K_DTYP_CONTEXT 0
775#define E1K_DTYP_DATA 1
776
777struct E1kTDLegacy
778{
779 uint64_t u64BufAddr; /**< Address of data buffer */
780 struct TDLCmd_st
781 {
782 unsigned u16Length : 16;
783 unsigned u8CSO : 8;
784 /* CMD field : 8 */
785 unsigned fEOP : 1;
786 unsigned fIFCS : 1;
787 unsigned fIC : 1;
788 unsigned fRS : 1;
789 unsigned fRPS : 1;
790 unsigned fDEXT : 1;
791 unsigned fVLE : 1;
792 unsigned fIDE : 1;
793 } cmd;
794 struct TDLDw3_st
795 {
796 /* STA field */
797 unsigned fDD : 1;
798 unsigned fEC : 1;
799 unsigned fLC : 1;
800 unsigned fTURSV : 1;
801 /* RSV field */
802 unsigned u4RSV : 4;
803 /* CSS field */
804 unsigned u8CSS : 8;
805 /* Special field*/
806 unsigned u16Special: 16;
807 } dw3;
808};
809
810/**
811 * TCP/IP Context Transmit Descriptor, section 3.3.6.
812 */
813struct E1kTDContext
814{
815 struct CheckSum_st
816 {
817 /** TSE: Header start. !TSE: Checksum start. */
818 unsigned u8CSS : 8;
819 /** Checksum offset - where to store it. */
820 unsigned u8CSO : 8;
821 /** Checksum ending (inclusive) offset, 0 = end of packet. */
822 unsigned u16CSE : 16;
823 } ip;
824 struct CheckSum_st tu;
825 struct TDCDw2_st
826 {
827 /** TSE: The total number of payload bytes for this context. Sans header. */
828 unsigned u20PAYLEN : 20;
829 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
830 unsigned u4DTYP : 4;
831 /** TUCMD field, 8 bits
832 * @{ */
833 /** TSE: TCP (set) or UDP (clear). */
834 unsigned fTCP : 1;
835 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
836 * the IP header. Does not affect the checksumming.
837 * @remarks 82544GC/EI interprets a cleared field differently. */
838 unsigned fIP : 1;
839 /** TSE: TCP segmentation enable. When clear the context describes */
840 unsigned fTSE : 1;
841 /** Report status (only applies to dw3.fDD for here). */
842 unsigned fRS : 1;
843 /** Reserved, MBZ. */
844 unsigned fRSV1 : 1;
845 /** Descriptor extension, must be set for this descriptor type. */
846 unsigned fDEXT : 1;
847 /** Reserved, MBZ. */
848 unsigned fRSV2 : 1;
849 /** Interrupt delay enable. */
850 unsigned fIDE : 1;
851 /** @} */
852 } dw2;
853 struct TDCDw3_st
854 {
855 /** Descriptor Done. */
856 unsigned fDD : 1;
857 /** Reserved, MBZ. */
858 unsigned u7RSV : 7;
859 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
860 unsigned u8HDRLEN : 8;
861 /** TSO: Maximum segment size. */
862 unsigned u16MSS : 16;
863 } dw3;
864};
865typedef struct E1kTDContext E1KTXCTX;
866
867/**
868 * TCP/IP Data Transmit Descriptor, section 3.3.7.
869 */
870struct E1kTDData
871{
872 uint64_t u64BufAddr; /**< Address of data buffer */
873 struct TDDCmd_st
874 {
875 /** The total length of data pointed to by this descriptor. */
876 unsigned u20DTALEN : 20;
877 /** The descriptor type - E1K_DTYP_DATA (1). */
878 unsigned u4DTYP : 4;
879 /** @name DCMD field, 8 bits (3.3.7.1).
880 * @{ */
881 /** End of packet. Note TSCTFC update. */
882 unsigned fEOP : 1;
883 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
884 unsigned fIFCS : 1;
885 /** Use the TSE context when set and the normal when clear. */
886 unsigned fTSE : 1;
887 /** Report status (dw3.STA). */
888 unsigned fRS : 1;
889 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
890 unsigned fRPS : 1;
891 /** Descriptor extension, must be set for this descriptor type. */
892 unsigned fDEXT : 1;
893 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
894 * Insert dw3.SPECIAL after ethernet header. */
895 unsigned fVLE : 1;
896 /** Interrupt delay enable. */
897 unsigned fIDE : 1;
898 /** @} */
899 } cmd;
900 struct TDDDw3_st
901 {
902 /** @name STA field (3.3.7.2)
903 * @{ */
904 unsigned fDD : 1; /**< Descriptor done. */
905 unsigned fEC : 1; /**< Excess collision. */
906 unsigned fLC : 1; /**< Late collision. */
907 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
908 unsigned fTURSV : 1;
909 /** @} */
910 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
911 /** @name POPTS (Packet Option) field (3.3.7.3)
912 * @{ */
913 unsigned fIXSM : 1; /**< Insert IP checksum. */
914 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
915 unsigned u6RSV : 6; /**< Reserved, MBZ. */
916 /** @} */
917 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
918 * Requires fEOP, fVLE and CTRL.VME to be set.
919 * @{ */
920 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
921 /** @} */
922 } dw3;
923};
924typedef struct E1kTDData E1KTXDAT;
925
926union E1kTxDesc
927{
928 struct E1kTDLegacy legacy;
929 struct E1kTDContext context;
930 struct E1kTDData data;
931};
932typedef union E1kTxDesc E1KTXDESC;
933AssertCompileSize(E1KTXDESC, 16);
934
935#define RA_CTL_AS 0x0003
936#define RA_CTL_AV 0x8000
937
938union E1kRecAddr
939{
940 uint32_t au32[32];
941 struct RAArray
942 {
943 uint8_t addr[6];
944 uint16_t ctl;
945 } array[16];
946};
947typedef struct E1kRecAddr::RAArray E1KRAELEM;
948typedef union E1kRecAddr E1KRA;
949AssertCompileSize(E1KRA, 8*16);
950
951#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
952#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
953#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
954#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
955
956/** @todo use+extend RTNETIPV4 */
957struct E1kIpHeader
958{
959 /* type of service / version / header length */
960 uint16_t tos_ver_hl;
961 /* total length */
962 uint16_t total_len;
963 /* identification */
964 uint16_t ident;
965 /* fragment offset field */
966 uint16_t offset;
967 /* time to live / protocol*/
968 uint16_t ttl_proto;
969 /* checksum */
970 uint16_t chksum;
971 /* source IP address */
972 uint32_t src;
973 /* destination IP address */
974 uint32_t dest;
975};
976AssertCompileSize(struct E1kIpHeader, 20);
977
978#define E1K_TCP_FIN UINT16_C(0x01)
979#define E1K_TCP_SYN UINT16_C(0x02)
980#define E1K_TCP_RST UINT16_C(0x04)
981#define E1K_TCP_PSH UINT16_C(0x08)
982#define E1K_TCP_ACK UINT16_C(0x10)
983#define E1K_TCP_URG UINT16_C(0x20)
984#define E1K_TCP_ECE UINT16_C(0x40)
985#define E1K_TCP_CWR UINT16_C(0x80)
986#define E1K_TCP_FLAGS UINT16_C(0x3f)
987
988/** @todo use+extend RTNETTCP */
989struct E1kTcpHeader
990{
991 uint16_t src;
992 uint16_t dest;
993 uint32_t seqno;
994 uint32_t ackno;
995 uint16_t hdrlen_flags;
996 uint16_t wnd;
997 uint16_t chksum;
998 uint16_t urgp;
999};
1000AssertCompileSize(struct E1kTcpHeader, 20);
1001
1002
1003#ifdef E1K_WITH_TXD_CACHE
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 4
1006/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1007# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1008#else /* !E1K_WITH_TXD_CACHE */
1009/** The current Saved state version. */
1010# define E1K_SAVEDSTATE_VERSION 3
1011#endif /* !E1K_WITH_TXD_CACHE */
1012/** Saved state version for VirtualBox 4.1 and earlier.
1013 * These did not include VLAN tag fields. */
1014#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1015/** Saved state version for VirtualBox 3.0 and earlier.
1016 * This did not include the configuration part nor the E1kEEPROM. */
1017#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1018
1019/**
1020 * E1000 shared device state.
1021 *
1022 * This is shared between ring-0 and ring-3.
1023 */
1024typedef struct E1KSTATE
1025{
1026 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1027
1028 /** Handle to PCI region \#0, the MMIO region. */
1029 IOMIOPORTHANDLE hMmioRegion;
1030 /** Handle to PCI region \#2, the I/O ports. */
1031 IOMIOPORTHANDLE hIoPorts;
1032
1033 /** Receive Interrupt Delay Timer. */
1034 TMTIMERHANDLE hRIDTimer;
1035 /** Receive Absolute Delay Timer. */
1036 TMTIMERHANDLE hRADTimer;
1037 /** Transmit Interrupt Delay Timer. */
1038 TMTIMERHANDLE hTIDTimer;
1039 /** Transmit Absolute Delay Timer. */
1040 TMTIMERHANDLE hTADTimer;
1041 /** Transmit Delay Timer. */
1042 TMTIMERHANDLE hTXDTimer;
1043 /** Late Interrupt Timer. */
1044 TMTIMERHANDLE hIntTimer;
1045 /** Link Up(/Restore) Timer. */
1046 TMTIMERHANDLE hLUTimer;
1047
1048 /** Transmit task. */
1049 PDMTASKHANDLE hTxTask;
1050
1051 /** Critical section - what is it protecting? */
1052 PDMCRITSECT cs;
1053 /** RX Critical section. */
1054 PDMCRITSECT csRx;
1055#ifdef E1K_WITH_TX_CS
1056 /** TX Critical section. */
1057 PDMCRITSECT csTx;
1058#endif /* E1K_WITH_TX_CS */
1059 /** MAC address obtained from the configuration. */
1060 RTMAC macConfigured;
1061 uint16_t u16Padding0;
1062 /** EMT: Last time the interrupt was acknowledged. */
1063 uint64_t u64AckedAt;
1064 /** All: Used for eliminating spurious interrupts. */
1065 bool fIntRaised;
1066 /** EMT: false if the cable is disconnected by the GUI. */
1067 bool fCableConnected;
1068 /** EMT: Compute Ethernet CRC for RX packets. */
1069 bool fEthernetCRC;
1070 /** All: throttle interrupts. */
1071 bool fItrEnabled;
1072 /** All: throttle RX interrupts. */
1073 bool fItrRxEnabled;
1074 /** All: Delay TX interrupts using TIDV/TADV. */
1075 bool fTidEnabled;
1076 bool afPadding[2];
1077 /** Link up delay (in milliseconds). */
1078 uint32_t cMsLinkUpDelay;
1079
1080 /** All: Device register storage. */
1081 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1082 /** TX/RX: Status LED. */
1083 PDMLED led;
1084 /** TX/RX: Number of packet being sent/received to show in debug log. */
1085 uint32_t u32PktNo;
1086
1087 /** EMT: Offset of the register to be read via IO. */
1088 uint32_t uSelectedReg;
1089 /** EMT: Multicast Table Array. */
1090 uint32_t auMTA[128];
1091 /** EMT: Receive Address registers. */
1092 E1KRA aRecAddr;
1093 /** EMT: VLAN filter table array. */
1094 uint32_t auVFTA[128];
1095 /** EMT: Receive buffer size. */
1096 uint16_t u16RxBSize;
1097 /** EMT: Locked state -- no state alteration possible. */
1098 bool fLocked;
1099 /** EMT: */
1100 bool fDelayInts;
1101 /** All: */
1102 bool fIntMaskUsed;
1103
1104 /** N/A: */
1105 bool volatile fMaybeOutOfSpace;
1106 /** EMT: Gets signalled when more RX descriptors become available. */
1107 SUPSEMEVENT hEventMoreRxDescAvail;
1108#ifdef E1K_WITH_RXD_CACHE
1109 /** RX: Fetched RX descriptors. */
1110 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1111 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1112 /** RX: Actual number of fetched RX descriptors. */
1113 uint32_t nRxDFetched;
1114 /** RX: Index in cache of RX descriptor being processed. */
1115 uint32_t iRxDCurrent;
1116#endif /* E1K_WITH_RXD_CACHE */
1117
1118 /** TX: Context used for TCP segmentation packets. */
1119 E1KTXCTX contextTSE;
1120 /** TX: Context used for ordinary packets. */
1121 E1KTXCTX contextNormal;
1122#ifdef E1K_WITH_TXD_CACHE
1123 /** TX: Fetched TX descriptors. */
1124 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1125 /** TX: Actual number of fetched TX descriptors. */
1126 uint8_t nTxDFetched;
1127 /** TX: Index in cache of TX descriptor being processed. */
1128 uint8_t iTxDCurrent;
1129 /** TX: Will this frame be sent as GSO. */
1130 bool fGSO;
1131 /** Alignment padding. */
1132 bool fReserved;
1133 /** TX: Number of bytes in next packet. */
1134 uint32_t cbTxAlloc;
1135
1136#endif /* E1K_WITH_TXD_CACHE */
1137 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1138 * applicable to the current TSE mode. */
1139 PDMNETWORKGSO GsoCtx;
1140 /** Scratch space for holding the loopback / fallback scatter / gather
1141 * descriptor. */
1142 union
1143 {
1144 PDMSCATTERGATHER Sg;
1145 uint8_t padding[8 * sizeof(RTUINTPTR)];
1146 } uTxFallback;
1147 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1148 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1149 /** TX: Number of bytes assembled in TX packet buffer. */
1150 uint16_t u16TxPktLen;
1151 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1152 bool fGSOEnabled;
1153 /** TX: IP checksum has to be inserted if true. */
1154 bool fIPcsum;
1155 /** TX: TCP/UDP checksum has to be inserted if true. */
1156 bool fTCPcsum;
1157 /** TX: VLAN tag has to be inserted if true. */
1158 bool fVTag;
1159 /** TX: TCI part of VLAN tag to be inserted. */
1160 uint16_t u16VTagTCI;
1161 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1162 uint32_t u32PayRemain;
1163 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1164 uint16_t u16HdrRemain;
1165 /** TX TSE fallback: Flags from template header. */
1166 uint16_t u16SavedFlags;
1167 /** TX TSE fallback: Partial checksum from template header. */
1168 uint32_t u32SavedCsum;
1169 /** ?: Emulated controller type. */
1170 E1KCHIP eChip;
1171
1172 /** EMT: Physical interface emulation. */
1173 PHY phy;
1174
1175#if 0
1176 /** Alignment padding. */
1177 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1178#endif
1179
1180 STAMCOUNTER StatReceiveBytes;
1181 STAMCOUNTER StatTransmitBytes;
1182#if defined(VBOX_WITH_STATISTICS)
1183 STAMPROFILEADV StatMMIOReadRZ;
1184 STAMPROFILEADV StatMMIOReadR3;
1185 STAMPROFILEADV StatMMIOWriteRZ;
1186 STAMPROFILEADV StatMMIOWriteR3;
1187 STAMPROFILEADV StatEEPROMRead;
1188 STAMPROFILEADV StatEEPROMWrite;
1189 STAMPROFILEADV StatIOReadRZ;
1190 STAMPROFILEADV StatIOReadR3;
1191 STAMPROFILEADV StatIOWriteRZ;
1192 STAMPROFILEADV StatIOWriteR3;
1193 STAMPROFILEADV StatLateIntTimer;
1194 STAMCOUNTER StatLateInts;
1195 STAMCOUNTER StatIntsRaised;
1196 STAMCOUNTER StatIntsPrevented;
1197 STAMPROFILEADV StatReceive;
1198 STAMPROFILEADV StatReceiveCRC;
1199 STAMPROFILEADV StatReceiveFilter;
1200 STAMPROFILEADV StatReceiveStore;
1201 STAMPROFILEADV StatTransmitRZ;
1202 STAMPROFILEADV StatTransmitR3;
1203 STAMPROFILE StatTransmitSendRZ;
1204 STAMPROFILE StatTransmitSendR3;
1205 STAMPROFILE StatRxOverflow;
1206 STAMCOUNTER StatRxOverflowWakeupRZ;
1207 STAMCOUNTER StatRxOverflowWakeupR3;
1208 STAMCOUNTER StatTxDescCtxNormal;
1209 STAMCOUNTER StatTxDescCtxTSE;
1210 STAMCOUNTER StatTxDescLegacy;
1211 STAMCOUNTER StatTxDescData;
1212 STAMCOUNTER StatTxDescTSEData;
1213 STAMCOUNTER StatTxPathFallback;
1214 STAMCOUNTER StatTxPathGSO;
1215 STAMCOUNTER StatTxPathRegular;
1216 STAMCOUNTER StatPHYAccesses;
1217 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1218 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1219#endif /* VBOX_WITH_STATISTICS */
1220
1221#ifdef E1K_INT_STATS
1222 /* Internal stats */
1223 uint64_t u64ArmedAt;
1224 uint64_t uStatMaxTxDelay;
1225 uint32_t uStatInt;
1226 uint32_t uStatIntTry;
1227 uint32_t uStatIntLower;
1228 uint32_t uStatNoIntICR;
1229 int32_t iStatIntLost;
1230 int32_t iStatIntLostOne;
1231 uint32_t uStatIntIMS;
1232 uint32_t uStatIntSkip;
1233 uint32_t uStatIntLate;
1234 uint32_t uStatIntMasked;
1235 uint32_t uStatIntEarly;
1236 uint32_t uStatIntRx;
1237 uint32_t uStatIntTx;
1238 uint32_t uStatIntICS;
1239 uint32_t uStatIntRDTR;
1240 uint32_t uStatIntRXDMT0;
1241 uint32_t uStatIntTXQE;
1242 uint32_t uStatTxNoRS;
1243 uint32_t uStatTxIDE;
1244 uint32_t uStatTxDelayed;
1245 uint32_t uStatTxDelayExp;
1246 uint32_t uStatTAD;
1247 uint32_t uStatTID;
1248 uint32_t uStatRAD;
1249 uint32_t uStatRID;
1250 uint32_t uStatRxFrm;
1251 uint32_t uStatTxFrm;
1252 uint32_t uStatDescCtx;
1253 uint32_t uStatDescDat;
1254 uint32_t uStatDescLeg;
1255 uint32_t uStatTx1514;
1256 uint32_t uStatTx2962;
1257 uint32_t uStatTx4410;
1258 uint32_t uStatTx5858;
1259 uint32_t uStatTx7306;
1260 uint32_t uStatTx8754;
1261 uint32_t uStatTx16384;
1262 uint32_t uStatTx32768;
1263 uint32_t uStatTxLarge;
1264 uint32_t uStatAlign;
1265#endif /* E1K_INT_STATS */
1266} E1KSTATE;
1267/** Pointer to the E1000 device state. */
1268typedef E1KSTATE *PE1KSTATE;
1269
1270/**
1271 * E1000 ring-3 device state
1272 *
1273 * @implements PDMINETWORKDOWN
1274 * @implements PDMINETWORKCONFIG
1275 * @implements PDMILEDPORTS
1276 */
1277typedef struct E1KSTATER3
1278{
1279 PDMIBASE IBase;
1280 PDMINETWORKDOWN INetworkDown;
1281 PDMINETWORKCONFIG INetworkConfig;
1282 /** LED interface */
1283 PDMILEDPORTS ILeds;
1284 /** Attached network driver. */
1285 R3PTRTYPE(PPDMIBASE) pDrvBase;
1286 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1287
1288 /** Pointer to the shared state. */
1289 R3PTRTYPE(PE1KSTATE) pShared;
1290
1291 /** Device instance. */
1292 PPDMDEVINSR3 pDevInsR3;
1293 /** Attached network driver. */
1294 PPDMINETWORKUPR3 pDrvR3;
1295 /** The scatter / gather buffer used for the current outgoing packet. */
1296 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1297
1298 /** EMT: EEPROM emulation */
1299 E1kEEPROM eeprom;
1300} E1KSTATER3;
1301/** Pointer to the E1000 ring-3 device state. */
1302typedef E1KSTATER3 *PE1KSTATER3;
1303
1304
1305/**
1306 * E1000 ring-0 device state
1307 */
1308typedef struct E1KSTATER0
1309{
1310 /** Device instance. */
1311 PPDMDEVINSR0 pDevInsR0;
1312 /** Attached network driver. */
1313 PPDMINETWORKUPR0 pDrvR0;
1314 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1315 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1316} E1KSTATER0;
1317/** Pointer to the E1000 ring-0 device state. */
1318typedef E1KSTATER0 *PE1KSTATER0;
1319
1320
1321/**
1322 * E1000 raw-mode device state
1323 */
1324typedef struct E1KSTATERC
1325{
1326 /** Device instance. */
1327 PPDMDEVINSRC pDevInsRC;
1328 /** Attached network driver. */
1329 PPDMINETWORKUPRC pDrvRC;
1330 /** The scatter / gather buffer used for the current outgoing packet. */
1331 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1332} E1KSTATERC;
1333/** Pointer to the E1000 raw-mode device state. */
1334typedef E1KSTATERC *PE1KSTATERC;
1335
1336
1337/** @def PE1KSTATECC
1338 * Pointer to the instance data for the current context. */
1339#ifdef IN_RING3
1340typedef E1KSTATER3 E1KSTATECC;
1341typedef PE1KSTATER3 PE1KSTATECC;
1342#elif defined(IN_RING0)
1343typedef E1KSTATER0 E1KSTATECC;
1344typedef PE1KSTATER0 PE1KSTATECC;
1345#elif defined(IN_RC)
1346typedef E1KSTATERC E1KSTATECC;
1347typedef PE1KSTATERC PE1KSTATECC;
1348#else
1349# error "Not IN_RING3, IN_RING0 or IN_RC"
1350#endif
1351
1352
1353#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1354
1355/* Forward declarations ******************************************************/
1356static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1357
1358/**
1359 * E1000 register read handler.
1360 */
1361typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1362/**
1363 * E1000 register write handler.
1364 */
1365typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1366
1367static FNE1KREGREAD e1kRegReadUnimplemented;
1368static FNE1KREGWRITE e1kRegWriteUnimplemented;
1369static FNE1KREGREAD e1kRegReadAutoClear;
1370static FNE1KREGREAD e1kRegReadDefault;
1371static FNE1KREGWRITE e1kRegWriteDefault;
1372#if 0 /* unused */
1373static FNE1KREGREAD e1kRegReadCTRL;
1374#endif
1375static FNE1KREGWRITE e1kRegWriteCTRL;
1376static FNE1KREGREAD e1kRegReadEECD;
1377static FNE1KREGWRITE e1kRegWriteEECD;
1378static FNE1KREGWRITE e1kRegWriteEERD;
1379static FNE1KREGWRITE e1kRegWriteMDIC;
1380static FNE1KREGREAD e1kRegReadICR;
1381static FNE1KREGWRITE e1kRegWriteICR;
1382static FNE1KREGWRITE e1kRegWriteICS;
1383static FNE1KREGWRITE e1kRegWriteIMS;
1384static FNE1KREGWRITE e1kRegWriteIMC;
1385static FNE1KREGWRITE e1kRegWriteRCTL;
1386static FNE1KREGWRITE e1kRegWritePBA;
1387static FNE1KREGWRITE e1kRegWriteRDT;
1388static FNE1KREGWRITE e1kRegWriteRDTR;
1389static FNE1KREGWRITE e1kRegWriteTDT;
1390static FNE1KREGREAD e1kRegReadMTA;
1391static FNE1KREGWRITE e1kRegWriteMTA;
1392static FNE1KREGREAD e1kRegReadRA;
1393static FNE1KREGWRITE e1kRegWriteRA;
1394static FNE1KREGREAD e1kRegReadVFTA;
1395static FNE1KREGWRITE e1kRegWriteVFTA;
1396
1397/**
1398 * Register map table.
1399 *
1400 * Override pfnRead and pfnWrite to get register-specific behavior.
1401 */
1402static const struct E1kRegMap_st
1403{
1404 /** Register offset in the register space. */
1405 uint32_t offset;
1406 /** Size in bytes. Registers of size > 4 are in fact tables. */
1407 uint32_t size;
1408 /** Readable bits. */
1409 uint32_t readable;
1410 /** Writable bits. */
1411 uint32_t writable;
1412 /** Read callback. */
1413 FNE1KREGREAD *pfnRead;
1414 /** Write callback. */
1415 FNE1KREGWRITE *pfnWrite;
1416 /** Abbreviated name. */
1417 const char *abbrev;
1418 /** Full name. */
1419 const char *name;
1420} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1421{
1422 /* offset size read mask write mask read callback write callback abbrev full name */
1423 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1424 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1425 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1426 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1427 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1428 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1429 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1430 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1431 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1432 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1433 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1434 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1435 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1436 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1437 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1438 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1439 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1440 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1441 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1442 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1443 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1444 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1445 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1446 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1447 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1448 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1449 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1450 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1451 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1452 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1453 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1454 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1455 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1456 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1457 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1458 { 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1459 { 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1460 { 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1461 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1462 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1463 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1464 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1465 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1466 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1467 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1468 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1469 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1470 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1471 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1472 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1473 { 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1474 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1475 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1476 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1477 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1478 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1479 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1480 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1481 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1482 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1483 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1484 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1485 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1486 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1487 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1488 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1489 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1490 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1491 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1492 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1493 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1494 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1495 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1496 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1497 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1498 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1499 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1500 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1501 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1502 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1503 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1504 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1505 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1506 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1507 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1508 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1509 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1510 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1511 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1512 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1513 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1514 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1515 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1516 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1517 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1518 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1519 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1520 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1521 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1522 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1523 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1524 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1525 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1526 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1527 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1528 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1529 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1530 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1531 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1532 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1533 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1534 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1535 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1536 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1537 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1538 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1539 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1540 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1541 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1542 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1543 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1544 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1545 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1546 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1547 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1548 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1549 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1550 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1551 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1552 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1553 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1554 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1555 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1556 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1557 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1558};
1559
1560#ifdef LOG_ENABLED
1561
1562/**
1563 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1564 *
1565 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1566 *
1567 * @returns The buffer.
1568 *
1569 * @param u32 The word to convert into string.
1570 * @param mask Selects which bytes to convert.
1571 * @param buf Where to put the result.
1572 */
1573static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1574{
1575 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1576 {
1577 if (mask & 0xF)
1578 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1579 else
1580 *ptr = '.';
1581 }
1582 buf[8] = 0;
1583 return buf;
1584}
1585
1586/**
1587 * Returns timer name for debug purposes.
1588 *
1589 * @returns The timer name.
1590 *
1591 * @param pThis The device state structure.
1592 * @param hTimer The timer to name.
1593 */
1594DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1595{
1596 if (hTimer == pThis->hTIDTimer)
1597 return "TID";
1598 if (hTimer == pThis->hTADTimer)
1599 return "TAD";
1600 if (hTimer == pThis->hRIDTimer)
1601 return "RID";
1602 if (hTimer == pThis->hRADTimer)
1603 return "RAD";
1604 if (hTimer == pThis->hIntTimer)
1605 return "Int";
1606 if (hTimer == pThis->hTXDTimer)
1607 return "TXD";
1608 if (hTimer == pThis->hLUTimer)
1609 return "LinkUp";
1610 return "unknown";
1611}
1612
1613#endif /* LOG_ENABLED */
1614
1615/**
1616 * Arm a timer.
1617 *
1618 * @param pDevIns The device instance.
1619 * @param pThis Pointer to the device state structure.
1620 * @param hTimer The timer to arm.
1621 * @param uExpireIn Expiration interval in microseconds.
1622 */
1623DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1624{
1625 if (pThis->fLocked)
1626 return;
1627
1628 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1629 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1630 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1631 AssertRC(rc);
1632}
1633
1634#ifdef IN_RING3
1635/**
1636 * Cancel a timer.
1637 *
1638 * @param pDevIns The device instance.
1639 * @param pThis Pointer to the device state structure.
1640 * @param pTimer Pointer to the timer.
1641 */
1642DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1643{
1644 E1kLog2(("%s Stopping %s timer...\n",
1645 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1646 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1647 if (RT_FAILURE(rc))
1648 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1649 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1650 RT_NOREF_PV(pThis);
1651}
1652#endif /* IN_RING3 */
1653
1654#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1655#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1656
1657#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1658#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1659#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1660
1661#ifndef E1K_WITH_TX_CS
1662# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1663# define e1kCsTxLeave(ps) do { } while (0)
1664#else /* E1K_WITH_TX_CS */
1665# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1666# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1667#endif /* E1K_WITH_TX_CS */
1668
1669
1670/**
1671 * Wakeup the RX thread.
1672 */
1673static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1674{
1675 if ( pThis->fMaybeOutOfSpace
1676 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1677 {
1678 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1679 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1680 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1681 AssertRC(rc);
1682 }
1683}
1684
1685#ifdef IN_RING3
1686
1687/**
1688 * Hardware reset. Revert all registers to initial values.
1689 *
1690 * @param pDevIns The device instance.
1691 * @param pThis The device state structure.
1692 * @param pThisCC The current context instance data.
1693 */
1694static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1695{
1696 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1697 /* No interrupts should survive device reset, see @bugref(9556). */
1698 if (pThis->fIntRaised)
1699 {
1700 /* Lower(0) INTA(0) */
1701 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1702 pThis->fIntRaised = false;
1703 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1704 }
1705 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1706 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1707#ifdef E1K_INIT_RA0
1708 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1709 sizeof(pThis->macConfigured.au8));
1710 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1711#endif /* E1K_INIT_RA0 */
1712 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1713 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1714 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1715 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1716 Assert(GET_BITS(RCTL, BSIZE) == 0);
1717 pThis->u16RxBSize = 2048;
1718
1719 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1720 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1721 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1722
1723 /* Reset promiscuous mode */
1724 if (pThisCC->pDrvR3)
1725 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1726
1727#ifdef E1K_WITH_TXD_CACHE
1728 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1729 if (RT_LIKELY(rc == VINF_SUCCESS))
1730 {
1731 pThis->nTxDFetched = 0;
1732 pThis->iTxDCurrent = 0;
1733 pThis->fGSO = false;
1734 pThis->cbTxAlloc = 0;
1735 e1kCsTxLeave(pThis);
1736 }
1737#endif /* E1K_WITH_TXD_CACHE */
1738#ifdef E1K_WITH_RXD_CACHE
1739 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1740 {
1741 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1742 e1kCsRxLeave(pThis);
1743 }
1744#endif /* E1K_WITH_RXD_CACHE */
1745#ifdef E1K_LSC_ON_RESET
1746 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1747 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1748 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1749#endif /* E1K_LSC_ON_RESET */
1750}
1751
1752#endif /* IN_RING3 */
1753
1754/**
1755 * Compute Internet checksum.
1756 *
1757 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1758 *
1759 * @param pThis The device state structure.
1760 * @param cpPacket The packet.
1761 * @param cb The size of the packet.
1762 * @param pszText A string denoting direction of packet transfer.
1763 *
1764 * @return The 1's complement of the 1's complement sum.
1765 *
1766 * @thread E1000_TX
1767 */
1768static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1769{
1770 uint32_t csum = 0;
1771 uint16_t *pu16 = (uint16_t *)pvBuf;
1772
1773 while (cb > 1)
1774 {
1775 csum += *pu16++;
1776 cb -= 2;
1777 }
1778 if (cb)
1779 csum += *(uint8_t*)pu16;
1780 while (csum >> 16)
1781 csum = (csum >> 16) + (csum & 0xFFFF);
1782 Assert(csum < 65536);
1783 return (uint16_t)~csum;
1784}
1785
1786/**
1787 * Dump a packet to debug log.
1788 *
1789 * @param pDevIns The device instance.
1790 * @param pThis The device state structure.
1791 * @param cpPacket The packet.
1792 * @param cb The size of the packet.
1793 * @param pszText A string denoting direction of packet transfer.
1794 * @thread E1000_TX
1795 */
1796DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1797{
1798#ifdef DEBUG
1799 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1800 {
1801 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1802 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1803 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1804 {
1805 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1806 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1807 if (*(cpPacket+14+6) == 0x6)
1808 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1809 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1810 }
1811 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1812 {
1813 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1814 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1815 if (*(cpPacket+14+6) == 0x6)
1816 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1817 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1818 }
1819 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1820 e1kCsLeave(pThis);
1821 }
1822#else
1823 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1824 {
1825 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1826 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1827 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1828 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1829 else
1830 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1831 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1832 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1833 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1834 e1kCsLeave(pThis);
1835 }
1836 RT_NOREF2(cb, pszText);
1837#endif
1838}
1839
1840/**
1841 * Determine the type of transmit descriptor.
1842 *
1843 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1844 *
1845 * @param pDesc Pointer to descriptor union.
1846 * @thread E1000_TX
1847 */
1848DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1849{
1850 if (pDesc->legacy.cmd.fDEXT)
1851 return pDesc->context.dw2.u4DTYP;
1852 return E1K_DTYP_LEGACY;
1853}
1854
1855
1856#ifdef E1K_WITH_RXD_CACHE
1857/**
1858 * Return the number of RX descriptor that belong to the hardware.
1859 *
1860 * @returns the number of available descriptors in RX ring.
1861 * @param pThis The device state structure.
1862 * @thread ???
1863 */
1864DECLINLINE(uint32_t) e1kGetRxLen(PE1KSTATE pThis)
1865{
1866 /**
1867 * Make sure RDT won't change during computation. EMT may modify RDT at
1868 * any moment.
1869 */
1870 uint32_t rdt = RDT;
1871 return (RDH > rdt ? RDLEN/sizeof(E1KRXDESC) : 0) + rdt - RDH;
1872}
1873
1874DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1875{
1876 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1877 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1878}
1879
1880DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1881{
1882 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1883}
1884
1885/**
1886 * Load receive descriptors from guest memory. The caller needs to be in Rx
1887 * critical section.
1888 *
1889 * We need two physical reads in case the tail wrapped around the end of RX
1890 * descriptor ring.
1891 *
1892 * @returns the actual number of descriptors fetched.
1893 * @param pDevIns The device instance.
1894 * @param pThis The device state structure.
1895 * @thread EMT, RX
1896 */
1897DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1898{
1899 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1900 unsigned nDescsAvailable = e1kGetRxLen(pThis) - e1kRxDInCache(pThis);
1901 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1902 unsigned nDescsTotal = RDLEN / sizeof(E1KRXDESC);
1903 Assert(nDescsTotal != 0);
1904 if (nDescsTotal == 0)
1905 return 0;
1906 unsigned nFirstNotLoaded = (RDH + e1kRxDInCache(pThis)) % nDescsTotal;
1907 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
1908 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
1909 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
1910 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
1911 nFirstNotLoaded, nDescsInSingleRead));
1912 if (nDescsToFetch == 0)
1913 return 0;
1914 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
1915 PDMDevHlpPhysRead(pDevIns,
1916 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
1917 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
1918 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
1919 // unsigned i, j;
1920 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
1921 // {
1922 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
1923 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1924 // }
1925 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
1926 pThis->szPrf, nDescsInSingleRead,
1927 RDBAH, RDBAL + RDH * sizeof(E1KRXDESC),
1928 nFirstNotLoaded, RDLEN, RDH, RDT));
1929 if (nDescsToFetch > nDescsInSingleRead)
1930 {
1931 PDMDevHlpPhysRead(pDevIns,
1932 ((uint64_t)RDBAH << 32) + RDBAL,
1933 pFirstEmptyDesc + nDescsInSingleRead,
1934 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
1935 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
1936 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
1937 // {
1938 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
1939 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
1940 // }
1941 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
1942 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
1943 RDBAH, RDBAL));
1944 }
1945 pThis->nRxDFetched += nDescsToFetch;
1946 return nDescsToFetch;
1947}
1948
1949# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
1950/**
1951 * Dump receive descriptor to debug log.
1952 *
1953 * @param pThis The device state structure.
1954 * @param pDesc Pointer to the descriptor.
1955 * @thread E1000_RX
1956 */
1957static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
1958{
1959 RT_NOREF2(pThis, pDesc);
1960 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
1961 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
1962 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
1963 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
1964 pDesc->status.fPIF ? "PIF" : "pif",
1965 pDesc->status.fIPCS ? "IPCS" : "ipcs",
1966 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
1967 pDesc->status.fVP ? "VP" : "vp",
1968 pDesc->status.fIXSM ? "IXSM" : "ixsm",
1969 pDesc->status.fEOP ? "EOP" : "eop",
1970 pDesc->status.fDD ? "DD" : "dd",
1971 pDesc->status.fRXE ? "RXE" : "rxe",
1972 pDesc->status.fIPE ? "IPE" : "ipe",
1973 pDesc->status.fTCPE ? "TCPE" : "tcpe",
1974 pDesc->status.fCE ? "CE" : "ce",
1975 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
1976 E1K_SPEC_VLAN(pDesc->status.u16Special),
1977 E1K_SPEC_PRI(pDesc->status.u16Special)));
1978}
1979# endif /* IN_RING3 */
1980#endif /* E1K_WITH_RXD_CACHE */
1981
1982/**
1983 * Dump transmit descriptor to debug log.
1984 *
1985 * @param pThis The device state structure.
1986 * @param pDesc Pointer to descriptor union.
1987 * @param pszDir A string denoting direction of descriptor transfer
1988 * @thread E1000_TX
1989 */
1990static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
1991 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
1992{
1993 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
1994
1995 /*
1996 * Unfortunately we cannot use our format handler here, we want R0 logging
1997 * as well.
1998 */
1999 switch (e1kGetDescType(pDesc))
2000 {
2001 case E1K_DTYP_CONTEXT:
2002 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2003 pThis->szPrf, pszDir, pszDir));
2004 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2005 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2006 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2007 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2008 pDesc->context.dw2.fIDE ? " IDE":"",
2009 pDesc->context.dw2.fRS ? " RS" :"",
2010 pDesc->context.dw2.fTSE ? " TSE":"",
2011 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2012 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2013 pDesc->context.dw2.u20PAYLEN,
2014 pDesc->context.dw3.u8HDRLEN,
2015 pDesc->context.dw3.u16MSS,
2016 pDesc->context.dw3.fDD?"DD":""));
2017 break;
2018 case E1K_DTYP_DATA:
2019 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2020 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2021 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2022 pDesc->data.u64BufAddr,
2023 pDesc->data.cmd.u20DTALEN));
2024 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2025 pDesc->data.cmd.fIDE ? " IDE" :"",
2026 pDesc->data.cmd.fVLE ? " VLE" :"",
2027 pDesc->data.cmd.fRPS ? " RPS" :"",
2028 pDesc->data.cmd.fRS ? " RS" :"",
2029 pDesc->data.cmd.fTSE ? " TSE" :"",
2030 pDesc->data.cmd.fIFCS? " IFCS":"",
2031 pDesc->data.cmd.fEOP ? " EOP" :"",
2032 pDesc->data.dw3.fDD ? " DD" :"",
2033 pDesc->data.dw3.fEC ? " EC" :"",
2034 pDesc->data.dw3.fLC ? " LC" :"",
2035 pDesc->data.dw3.fTXSM? " TXSM":"",
2036 pDesc->data.dw3.fIXSM? " IXSM":"",
2037 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2038 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2039 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2040 break;
2041 case E1K_DTYP_LEGACY:
2042 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2043 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2044 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2045 pDesc->data.u64BufAddr,
2046 pDesc->legacy.cmd.u16Length));
2047 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2048 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2049 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2050 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2051 pDesc->legacy.cmd.fRS ? " RS" :"",
2052 pDesc->legacy.cmd.fIC ? " IC" :"",
2053 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2054 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2055 pDesc->legacy.dw3.fDD ? " DD" :"",
2056 pDesc->legacy.dw3.fEC ? " EC" :"",
2057 pDesc->legacy.dw3.fLC ? " LC" :"",
2058 pDesc->legacy.cmd.u8CSO,
2059 pDesc->legacy.dw3.u8CSS,
2060 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2061 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2062 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2063 break;
2064 default:
2065 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2066 pThis->szPrf, pszDir, pszDir));
2067 break;
2068 }
2069}
2070
2071/**
2072 * Raise an interrupt later.
2073 *
2074 * @param pThis The device state structure.
2075 */
2076DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2077{
2078 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2079 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2080}
2081
2082/**
2083 * Raise interrupt if not masked.
2084 *
2085 * @param pThis The device state structure.
2086 */
2087static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause = 0)
2088{
2089 int rc = e1kCsEnter(pThis, rcBusy);
2090 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2091 return rc;
2092
2093 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2094 ICR |= u32IntCause;
2095 if (ICR & IMS)
2096 {
2097 if (pThis->fIntRaised)
2098 {
2099 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2100 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2101 pThis->szPrf, ICR & IMS));
2102 }
2103 else
2104 {
2105 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2106 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2107 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2108 {
2109 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2110 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2111 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2112 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2113 }
2114 else
2115 {
2116
2117 /* Since we are delivering the interrupt now
2118 * there is no need to do it later -- stop the timer.
2119 */
2120 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2121 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2122 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2123 /* Got at least one unmasked interrupt cause */
2124 pThis->fIntRaised = true;
2125 /* Raise(1) INTA(0) */
2126 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2127 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2128 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2129 pThis->szPrf, ICR & IMS));
2130 }
2131 }
2132 }
2133 else
2134 {
2135 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2136 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2137 pThis->szPrf, ICR, IMS));
2138 }
2139 e1kCsLeave(pThis);
2140 return VINF_SUCCESS;
2141}
2142
2143/**
2144 * Compute the physical address of the descriptor.
2145 *
2146 * @returns the physical address of the descriptor.
2147 *
2148 * @param baseHigh High-order 32 bits of descriptor table address.
2149 * @param baseLow Low-order 32 bits of descriptor table address.
2150 * @param idxDesc The descriptor index in the table.
2151 */
2152DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2153{
2154 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2155 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2156}
2157
2158#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2159/**
2160 * Advance the head pointer of the receive descriptor queue.
2161 *
2162 * @remarks RDH always points to the next available RX descriptor.
2163 *
2164 * @param pDevIns The device instance.
2165 * @param pThis The device state structure.
2166 */
2167DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2168{
2169 Assert(e1kCsRxIsOwner(pThis));
2170 //e1kCsEnter(pThis, RT_SRC_POS);
2171 if (++RDH * sizeof(E1KRXDESC) >= RDLEN)
2172 RDH = 0;
2173#ifdef E1K_WITH_RXD_CACHE
2174 /*
2175 * We need to fetch descriptors now as the guest may advance RDT all the way
2176 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2177 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2178 * check if the receiver is enabled. It must be, otherwise we won't get here
2179 * in the first place.
2180 *
2181 * Note that we should have moved both RDH and iRxDCurrent by now.
2182 */
2183 if (e1kRxDIsCacheEmpty(pThis))
2184 {
2185 /* Cache is empty, reset it and check if we can fetch more. */
2186 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2187 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2188 "iRxDCurrent=%x nRxDFetched=%x\n",
2189 pThis->szPrf, RDH, RDT, pThis->iRxDCurrent, pThis->nRxDFetched));
2190 e1kRxDPrefetch(pDevIns, pThis);
2191 }
2192#endif /* E1K_WITH_RXD_CACHE */
2193 /*
2194 * Compute current receive queue length and fire RXDMT0 interrupt
2195 * if we are low on receive buffers
2196 */
2197 uint32_t uRQueueLen = RDH>RDT ? RDLEN/sizeof(E1KRXDESC)-RDH+RDT : RDT-RDH;
2198 /*
2199 * The minimum threshold is controlled by RDMTS bits of RCTL:
2200 * 00 = 1/2 of RDLEN
2201 * 01 = 1/4 of RDLEN
2202 * 10 = 1/8 of RDLEN
2203 * 11 = reserved
2204 */
2205 uint32_t uMinRQThreshold = RDLEN / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2206 if (uRQueueLen <= uMinRQThreshold)
2207 {
2208 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
2209 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2210 pThis->szPrf, RDH, RDT, uRQueueLen, uMinRQThreshold));
2211 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2212 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2213 }
2214 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2215 pThis->szPrf, RDH, RDT, uRQueueLen));
2216 //e1kCsLeave(pThis);
2217}
2218#endif /* IN_RING3 */
2219
2220#ifdef E1K_WITH_RXD_CACHE
2221
2222# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2223
2224/**
2225 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2226 * RX ring if the cache is empty.
2227 *
2228 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2229 * go out of sync with RDH which will cause trouble when EMT checks if the
2230 * cache is empty to do pre-fetch @bugref(6217).
2231 *
2232 * @param pDevIns The device instance.
2233 * @param pThis The device state structure.
2234 * @thread RX
2235 */
2236DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2237{
2238 Assert(e1kCsRxIsOwner(pThis));
2239 /* Check the cache first. */
2240 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2241 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2242 /* Cache is empty, reset it and check if we can fetch more. */
2243 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2244 if (e1kRxDPrefetch(pDevIns, pThis))
2245 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2246 /* Out of Rx descriptors. */
2247 return NULL;
2248}
2249
2250
2251/**
2252 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2253 * pointer. The descriptor gets written back to the RXD ring.
2254 *
2255 * @param pDevIns The device instance.
2256 * @param pThis The device state structure.
2257 * @param pDesc The descriptor being "returned" to the RX ring.
2258 * @thread RX
2259 */
2260DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc)
2261{
2262 Assert(e1kCsRxIsOwner(pThis));
2263 pThis->iRxDCurrent++;
2264 // Assert(pDesc >= pThis->aRxDescriptors);
2265 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2266 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2267 // uint32_t rdh = RDH;
2268 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2269 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2270 /*
2271 * We need to print the descriptor before advancing RDH as it may fetch new
2272 * descriptors into the cache.
2273 */
2274 e1kPrintRDesc(pThis, pDesc);
2275 e1kAdvanceRDH(pDevIns, pThis);
2276}
2277
2278/**
2279 * Store a fragment of received packet at the specifed address.
2280 *
2281 * @param pDevIns The device instance.
2282 * @param pThis The device state structure.
2283 * @param pDesc The next available RX descriptor.
2284 * @param pvBuf The fragment.
2285 * @param cb The size of the fragment.
2286 */
2287static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2288{
2289 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2290 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2291 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2292 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2293 pDesc->u16Length = (uint16_t)cb;
2294 Assert(pDesc->u16Length == cb);
2295 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2296 RT_NOREF(pThis);
2297}
2298
2299# endif /* IN_RING3 */
2300
2301#else /* !E1K_WITH_RXD_CACHE */
2302
2303/**
2304 * Store a fragment of received packet that fits into the next available RX
2305 * buffer.
2306 *
2307 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2308 *
2309 * @param pDevIns The device instance.
2310 * @param pThis The device state structure.
2311 * @param pDesc The next available RX descriptor.
2312 * @param pvBuf The fragment.
2313 * @param cb The size of the fragment.
2314 */
2315static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2316{
2317 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2318 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2319 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2320 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2321 /* Write back the descriptor */
2322 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2323 e1kPrintRDesc(pThis, pDesc);
2324 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2325 /* Advance head */
2326 e1kAdvanceRDH(pDevIns, pThis);
2327 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2328 if (pDesc->status.fEOP)
2329 {
2330 /* Complete packet has been stored -- it is time to let the guest know. */
2331#ifdef E1K_USE_RX_TIMERS
2332 if (RDTR)
2333 {
2334 /* Arm the timer to fire in RDTR usec (discard .024) */
2335 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2336 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2337 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2338 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2339 }
2340 else
2341 {
2342#endif
2343 /* 0 delay means immediate interrupt */
2344 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2345 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2346#ifdef E1K_USE_RX_TIMERS
2347 }
2348#endif
2349 }
2350 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2351}
2352
2353#endif /* !E1K_WITH_RXD_CACHE */
2354
2355/**
2356 * Returns true if it is a broadcast packet.
2357 *
2358 * @returns true if destination address indicates broadcast.
2359 * @param pvBuf The ethernet packet.
2360 */
2361DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2362{
2363 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2364 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2365}
2366
2367/**
2368 * Returns true if it is a multicast packet.
2369 *
2370 * @remarks returns true for broadcast packets as well.
2371 * @returns true if destination address indicates multicast.
2372 * @param pvBuf The ethernet packet.
2373 */
2374DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2375{
2376 return (*(char*)pvBuf) & 1;
2377}
2378
2379#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2380/**
2381 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2382 *
2383 * @remarks We emulate checksum offloading for major packets types only.
2384 *
2385 * @returns VBox status code.
2386 * @param pThis The device state structure.
2387 * @param pFrame The available data.
2388 * @param cb Number of bytes available in the buffer.
2389 * @param status Bit fields containing status info.
2390 */
2391static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2392{
2393 /** @todo
2394 * It is not safe to bypass checksum verification for packets coming
2395 * from real wire. We currently unable to tell where packets are
2396 * coming from so we tell the driver to ignore our checksum flags
2397 * and do verification in software.
2398 */
2399# if 0
2400 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2401
2402 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2403
2404 switch (uEtherType)
2405 {
2406 case 0x800: /* IPv4 */
2407 {
2408 pStatus->fIXSM = false;
2409 pStatus->fIPCS = true;
2410 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2411 /* TCP/UDP checksum offloading works with TCP and UDP only */
2412 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2413 break;
2414 }
2415 case 0x86DD: /* IPv6 */
2416 pStatus->fIXSM = false;
2417 pStatus->fIPCS = false;
2418 pStatus->fTCPCS = true;
2419 break;
2420 default: /* ARP, VLAN, etc. */
2421 pStatus->fIXSM = true;
2422 break;
2423 }
2424# else
2425 pStatus->fIXSM = true;
2426 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2427# endif
2428 return VINF_SUCCESS;
2429}
2430#endif /* IN_RING3 */
2431
2432/**
2433 * Pad and store received packet.
2434 *
2435 * @remarks Make sure that the packet appears to upper layer as one coming
2436 * from real Ethernet: pad it and insert FCS.
2437 *
2438 * @returns VBox status code.
2439 * @param pDevIns The device instance.
2440 * @param pThis The device state structure.
2441 * @param pvBuf The available data.
2442 * @param cb Number of bytes available in the buffer.
2443 * @param status Bit fields containing status info.
2444 */
2445static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2446{
2447#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2448 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2449 uint8_t *ptr = rxPacket;
2450
2451 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2452 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2453 return rc;
2454
2455 if (cb > 70) /* unqualified guess */
2456 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2457
2458 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2459 Assert(cb > 16);
2460 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2461 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2462 if (status.fVP)
2463 {
2464 /* VLAN packet -- strip VLAN tag in VLAN mode */
2465 if ((CTRL & CTRL_VME) && cb > 16)
2466 {
2467 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2468 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2469 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2470 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2471 cb -= 4;
2472 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2473 pThis->szPrf, status.u16Special, cb));
2474 }
2475 else
2476 status.fVP = false; /* Set VP only if we stripped the tag */
2477 }
2478 else
2479 memcpy(rxPacket, pvBuf, cb);
2480 /* Pad short packets */
2481 if (cb < 60)
2482 {
2483 memset(rxPacket + cb, 0, 60 - cb);
2484 cb = 60;
2485 }
2486 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2487 {
2488 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2489 /*
2490 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2491 * is ignored by most of drivers we may as well save us the trouble
2492 * of calculating it (see EthernetCRC CFGM parameter).
2493 */
2494 if (pThis->fEthernetCRC)
2495 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2496 cb += sizeof(uint32_t);
2497 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2498 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2499 }
2500 /* Compute checksum of complete packet */
2501 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2502 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2503 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2504
2505 /* Update stats */
2506 E1K_INC_CNT32(GPRC);
2507 if (e1kIsBroadcast(pvBuf))
2508 E1K_INC_CNT32(BPRC);
2509 else if (e1kIsMulticast(pvBuf))
2510 E1K_INC_CNT32(MPRC);
2511 /* Update octet receive counter */
2512 E1K_ADD_CNT64(GORCL, GORCH, cb);
2513 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2514 if (cb == 64)
2515 E1K_INC_CNT32(PRC64);
2516 else if (cb < 128)
2517 E1K_INC_CNT32(PRC127);
2518 else if (cb < 256)
2519 E1K_INC_CNT32(PRC255);
2520 else if (cb < 512)
2521 E1K_INC_CNT32(PRC511);
2522 else if (cb < 1024)
2523 E1K_INC_CNT32(PRC1023);
2524 else
2525 E1K_INC_CNT32(PRC1522);
2526
2527 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2528
2529# ifdef E1K_WITH_RXD_CACHE
2530 while (cb > 0)
2531 {
2532 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis);
2533
2534 if (pDesc == NULL)
2535 {
2536 E1kLog(("%s Out of receive buffers, dropping the packet "
2537 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2538 pThis->szPrf, cb, e1kRxDInCache(pThis), RDH, RDT));
2539 break;
2540 }
2541# else /* !E1K_WITH_RXD_CACHE */
2542 if (RDH == RDT)
2543 {
2544 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2545 pThis->szPrf));
2546 }
2547 /* Store the packet to receive buffers */
2548 while (RDH != RDT)
2549 {
2550 /* Load the descriptor pointed by head */
2551 E1KRXDESC desc, *pDesc = &desc;
2552 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2553# endif /* !E1K_WITH_RXD_CACHE */
2554 if (pDesc->u64BufAddr)
2555 {
2556 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2557
2558 /* Update descriptor */
2559 pDesc->status = status;
2560 pDesc->u16Checksum = checksum;
2561 pDesc->status.fDD = true;
2562
2563 /*
2564 * We need to leave Rx critical section here or we risk deadlocking
2565 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2566 * page or has an access handler associated with it.
2567 * Note that it is safe to leave the critical section here since
2568 * e1kRegWriteRDT() never modifies RDH. It never touches already
2569 * fetched RxD cache entries either.
2570 */
2571 if (cb > u16RxBufferSize)
2572 {
2573 pDesc->status.fEOP = false;
2574 e1kCsRxLeave(pThis);
2575 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2576 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2577 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2578 return rc;
2579 ptr += u16RxBufferSize;
2580 cb -= u16RxBufferSize;
2581 }
2582 else
2583 {
2584 pDesc->status.fEOP = true;
2585 e1kCsRxLeave(pThis);
2586 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2587# ifdef E1K_WITH_RXD_CACHE
2588 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2589 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2590 return rc;
2591 cb = 0;
2592# else /* !E1K_WITH_RXD_CACHE */
2593 pThis->led.Actual.s.fReading = 0;
2594 return VINF_SUCCESS;
2595# endif /* !E1K_WITH_RXD_CACHE */
2596 }
2597 /*
2598 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2599 * is not defined.
2600 */
2601 }
2602# ifdef E1K_WITH_RXD_CACHE
2603 /* Write back the descriptor. */
2604 pDesc->status.fDD = true;
2605 e1kRxDPut(pDevIns, pThis, pDesc);
2606# else /* !E1K_WITH_RXD_CACHE */
2607 else
2608 {
2609 /* Write back the descriptor. */
2610 pDesc->status.fDD = true;
2611 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2612 e1kAdvanceRDH(pDevIns, pThis);
2613 }
2614# endif /* !E1K_WITH_RXD_CACHE */
2615 }
2616
2617 if (cb > 0)
2618 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2619
2620 pThis->led.Actual.s.fReading = 0;
2621
2622 e1kCsRxLeave(pThis);
2623# ifdef E1K_WITH_RXD_CACHE
2624 /* Complete packet has been stored -- it is time to let the guest know. */
2625# ifdef E1K_USE_RX_TIMERS
2626 if (RDTR)
2627 {
2628 /* Arm the timer to fire in RDTR usec (discard .024) */
2629 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2630 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2631 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2632 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2633 }
2634 else
2635 {
2636# endif /* E1K_USE_RX_TIMERS */
2637 /* 0 delay means immediate interrupt */
2638 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2639 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2640# ifdef E1K_USE_RX_TIMERS
2641 }
2642# endif /* E1K_USE_RX_TIMERS */
2643# endif /* E1K_WITH_RXD_CACHE */
2644
2645 return VINF_SUCCESS;
2646#else /* !IN_RING3 */
2647 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2648 return VERR_INTERNAL_ERROR_2;
2649#endif /* !IN_RING3 */
2650}
2651
2652
2653#ifdef IN_RING3
2654/**
2655 * Bring the link up after the configured delay, 5 seconds by default.
2656 *
2657 * @param pDevIns The device instance.
2658 * @param pThis The device state structure.
2659 * @thread any
2660 */
2661DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2662{
2663 E1kLog(("%s Will bring up the link in %d seconds...\n",
2664 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2665 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2666}
2667
2668/**
2669 * Bring up the link immediately.
2670 *
2671 * @param pDevIns The device instance.
2672 * @param pThis The device state structure.
2673 * @param pThisCC The current context instance data.
2674 */
2675DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2676{
2677 E1kLog(("%s Link is up\n", pThis->szPrf));
2678 STATUS |= STATUS_LU;
2679 Phy::setLinkStatus(&pThis->phy, true);
2680 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2681 if (pThisCC->pDrvR3)
2682 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2683 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2684 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2685}
2686
2687/**
2688 * Bring down the link immediately.
2689 *
2690 * @param pDevIns The device instance.
2691 * @param pThis The device state structure.
2692 * @param pThisCC The current context instance data.
2693 */
2694DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2695{
2696 E1kLog(("%s Link is down\n", pThis->szPrf));
2697 STATUS &= ~STATUS_LU;
2698#ifdef E1K_LSC_ON_RESET
2699 Phy::setLinkStatus(&pThis->phy, false);
2700#endif /* E1K_LSC_ON_RESET */
2701 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2702 if (pThisCC->pDrvR3)
2703 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2704}
2705
2706/**
2707 * Bring down the link temporarily.
2708 *
2709 * @param pDevIns The device instance.
2710 * @param pThis The device state structure.
2711 * @param pThisCC The current context instance data.
2712 */
2713DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2714{
2715 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2716 STATUS &= ~STATUS_LU;
2717 Phy::setLinkStatus(&pThis->phy, false);
2718 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2719 /*
2720 * Notifying the associated driver that the link went down (even temporarily)
2721 * seems to be the right thing, but it was not done before. This may cause
2722 * a regression if the driver does not expect the link to go down as a result
2723 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2724 * of code notified the driver that the link was up! See @bugref{7057}.
2725 */
2726 if (pThisCC->pDrvR3)
2727 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2728 e1kBringLinkUpDelayed(pDevIns, pThis);
2729}
2730#endif /* IN_RING3 */
2731
2732#if 0 /* unused */
2733/**
2734 * Read handler for Device Status register.
2735 *
2736 * Get the link status from PHY.
2737 *
2738 * @returns VBox status code.
2739 *
2740 * @param pThis The device state structure.
2741 * @param offset Register offset in memory-mapped frame.
2742 * @param index Register index in register array.
2743 * @param mask Used to implement partial reads (8 and 16-bit).
2744 */
2745static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2746{
2747 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2748 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2749 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2750 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2751 {
2752 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2753 if (Phy::readMDIO(&pThis->phy))
2754 *pu32Value = CTRL | CTRL_MDIO;
2755 else
2756 *pu32Value = CTRL & ~CTRL_MDIO;
2757 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2758 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2759 }
2760 else
2761 {
2762 /* MDIO pin is used for output, ignore it */
2763 *pu32Value = CTRL;
2764 }
2765 return VINF_SUCCESS;
2766}
2767#endif /* unused */
2768
2769/**
2770 * A callback used by PHY to indicate that the link needs to be updated due to
2771 * reset of PHY.
2772 *
2773 * @param pDevIns The device instance.
2774 * @thread any
2775 */
2776void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2777{
2778 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2779
2780 /* Make sure we have cable connected and MAC can talk to PHY */
2781 if (pThis->fCableConnected && (CTRL & CTRL_SLU))
2782 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2783}
2784
2785/**
2786 * Write handler for Device Control register.
2787 *
2788 * Handles reset.
2789 *
2790 * @param pThis The device state structure.
2791 * @param offset Register offset in memory-mapped frame.
2792 * @param index Register index in register array.
2793 * @param value The value to store.
2794 * @param mask Used to implement partial writes (8 and 16-bit).
2795 * @thread EMT
2796 */
2797static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2798{
2799 int rc = VINF_SUCCESS;
2800
2801 if (value & CTRL_RESET)
2802 { /* RST */
2803#ifndef IN_RING3
2804 return VINF_IOM_R3_MMIO_WRITE;
2805#else
2806 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2807#endif
2808 }
2809 else
2810 {
2811#ifdef E1K_LSC_ON_SLU
2812 /*
2813 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2814 * the link is down and the cable is connected, and if they are we
2815 * bring the link up, see @bugref{8624}.
2816 */
2817 if ( (value & CTRL_SLU)
2818 && !(CTRL & CTRL_SLU)
2819 && pThis->fCableConnected
2820 && !(STATUS & STATUS_LU))
2821 {
2822 /* It should take about 2 seconds for the link to come up */
2823 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2824 }
2825#else /* !E1K_LSC_ON_SLU */
2826 if ( (value & CTRL_SLU)
2827 && !(CTRL & CTRL_SLU)
2828 && pThis->fCableConnected
2829 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2830 {
2831 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2832 STATUS |= STATUS_LU;
2833 }
2834#endif /* !E1K_LSC_ON_SLU */
2835 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2836 {
2837 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2838 }
2839 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2840 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2841 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2842 if (value & CTRL_MDC)
2843 {
2844 if (value & CTRL_MDIO_DIR)
2845 {
2846 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2847 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2848 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2849 }
2850 else
2851 {
2852 if (Phy::readMDIO(&pThis->phy))
2853 value |= CTRL_MDIO;
2854 else
2855 value &= ~CTRL_MDIO;
2856 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2857 }
2858 }
2859 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2860 }
2861
2862 return rc;
2863}
2864
2865/**
2866 * Write handler for EEPROM/Flash Control/Data register.
2867 *
2868 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2869 *
2870 * @param pThis The device state structure.
2871 * @param offset Register offset in memory-mapped frame.
2872 * @param index Register index in register array.
2873 * @param value The value to store.
2874 * @param mask Used to implement partial writes (8 and 16-bit).
2875 * @thread EMT
2876 */
2877static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2878{
2879 RT_NOREF(pDevIns, offset, index);
2880#ifdef IN_RING3
2881 /* So far we are concerned with lower byte only */
2882 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2883 {
2884 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
2885 /* Note: 82543GC does not need to request EEPROM access */
2886 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
2887 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2888 pThisCC->eeprom.write(value & EECD_EE_WIRES);
2889 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
2890 }
2891 if (value & EECD_EE_REQ)
2892 EECD |= EECD_EE_REQ|EECD_EE_GNT;
2893 else
2894 EECD &= ~EECD_EE_GNT;
2895 //e1kRegWriteDefault(pThis, offset, index, value );
2896
2897 return VINF_SUCCESS;
2898#else /* !IN_RING3 */
2899 RT_NOREF(pThis, value);
2900 return VINF_IOM_R3_MMIO_WRITE;
2901#endif /* !IN_RING3 */
2902}
2903
2904/**
2905 * Read handler for EEPROM/Flash Control/Data register.
2906 *
2907 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
2908 *
2909 * @returns VBox status code.
2910 *
2911 * @param pThis The device state structure.
2912 * @param offset Register offset in memory-mapped frame.
2913 * @param index Register index in register array.
2914 * @param mask Used to implement partial reads (8 and 16-bit).
2915 * @thread EMT
2916 */
2917static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2918{
2919#ifdef IN_RING3
2920 uint32_t value = 0; /* Get rid of false positive in parfait. */
2921 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
2922 if (RT_SUCCESS(rc))
2923 {
2924 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2925 {
2926 /* Note: 82543GC does not need to request EEPROM access */
2927 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
2928 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2929 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2930 value |= pThisCC->eeprom.read();
2931 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2932 }
2933 *pu32Value = value;
2934 }
2935
2936 return rc;
2937#else /* !IN_RING3 */
2938 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
2939 return VINF_IOM_R3_MMIO_READ;
2940#endif /* !IN_RING3 */
2941}
2942
2943/**
2944 * Write handler for EEPROM Read register.
2945 *
2946 * Handles EEPROM word access requests, reads EEPROM and stores the result
2947 * into DATA field.
2948 *
2949 * @param pThis The device state structure.
2950 * @param offset Register offset in memory-mapped frame.
2951 * @param index Register index in register array.
2952 * @param value The value to store.
2953 * @param mask Used to implement partial writes (8 and 16-bit).
2954 * @thread EMT
2955 */
2956static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2957{
2958#ifdef IN_RING3
2959 /* Make use of 'writable' and 'readable' masks. */
2960 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2961 /* DONE and DATA are set only if read was triggered by START. */
2962 if (value & EERD_START)
2963 {
2964 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
2965 uint16_t tmp;
2966 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2967 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
2968 SET_BITS(EERD, DATA, tmp);
2969 EERD |= EERD_DONE;
2970 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
2971 }
2972
2973 return VINF_SUCCESS;
2974#else /* !IN_RING3 */
2975 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
2976 return VINF_IOM_R3_MMIO_WRITE;
2977#endif /* !IN_RING3 */
2978}
2979
2980
2981/**
2982 * Write handler for MDI Control register.
2983 *
2984 * Handles PHY read/write requests; forwards requests to internal PHY device.
2985 *
2986 * @param pThis The device state structure.
2987 * @param offset Register offset in memory-mapped frame.
2988 * @param index Register index in register array.
2989 * @param value The value to store.
2990 * @param mask Used to implement partial writes (8 and 16-bit).
2991 * @thread EMT
2992 */
2993static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2994{
2995 if (value & MDIC_INT_EN)
2996 {
2997 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
2998 pThis->szPrf));
2999 }
3000 else if (value & MDIC_READY)
3001 {
3002 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3003 pThis->szPrf));
3004 }
3005 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3006 {
3007 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3008 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3009 /*
3010 * Some drivers scan the MDIO bus for a PHY. We can work with these
3011 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3012 * at the requested address, see @bugref{7346}.
3013 */
3014 MDIC = MDIC_READY | MDIC_ERROR;
3015 }
3016 else
3017 {
3018 /* Store the value */
3019 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3020 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3021 /* Forward op to PHY */
3022 if (value & MDIC_OP_READ)
3023 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3024 else
3025 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3026 /* Let software know that we are done */
3027 MDIC |= MDIC_READY;
3028 }
3029
3030 return VINF_SUCCESS;
3031}
3032
3033/**
3034 * Write handler for Interrupt Cause Read register.
3035 *
3036 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3037 *
3038 * @param pThis The device state structure.
3039 * @param offset Register offset in memory-mapped frame.
3040 * @param index Register index in register array.
3041 * @param value The value to store.
3042 * @param mask Used to implement partial writes (8 and 16-bit).
3043 * @thread EMT
3044 */
3045static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3046{
3047 ICR &= ~value;
3048
3049 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3050 return VINF_SUCCESS;
3051}
3052
3053/**
3054 * Read handler for Interrupt Cause Read register.
3055 *
3056 * Reading this register acknowledges all interrupts.
3057 *
3058 * @returns VBox status code.
3059 *
3060 * @param pThis The device state structure.
3061 * @param offset Register offset in memory-mapped frame.
3062 * @param index Register index in register array.
3063 * @param mask Not used.
3064 * @thread EMT
3065 */
3066static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3067{
3068 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3069 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3070 return rc;
3071
3072 uint32_t value = 0;
3073 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3074 if (RT_SUCCESS(rc))
3075 {
3076 if (value)
3077 {
3078 if (!pThis->fIntRaised)
3079 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3080 /*
3081 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3082 * with disabled interrupts.
3083 */
3084 //if (IMS)
3085 if (1)
3086 {
3087 /*
3088 * Interrupts were enabled -- we are supposedly at the very
3089 * beginning of interrupt handler
3090 */
3091 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3092 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3093 /* Clear all pending interrupts */
3094 ICR = 0;
3095 pThis->fIntRaised = false;
3096 /* Lower(0) INTA(0) */
3097 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3098
3099 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3100 if (pThis->fIntMaskUsed)
3101 pThis->fDelayInts = true;
3102 }
3103 else
3104 {
3105 /*
3106 * Interrupts are disabled -- in windows guests ICR read is done
3107 * just before re-enabling interrupts
3108 */
3109 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3110 }
3111 }
3112 *pu32Value = value;
3113 }
3114 e1kCsLeave(pThis);
3115
3116 return rc;
3117}
3118
3119/**
3120 * Write handler for Interrupt Cause Set register.
3121 *
3122 * Bits corresponding to 1s in 'value' will be set in ICR register.
3123 *
3124 * @param pThis The device state structure.
3125 * @param offset Register offset in memory-mapped frame.
3126 * @param index Register index in register array.
3127 * @param value The value to store.
3128 * @param mask Used to implement partial writes (8 and 16-bit).
3129 * @thread EMT
3130 */
3131static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3132{
3133 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3134 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3135 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3136}
3137
3138/**
3139 * Write handler for Interrupt Mask Set register.
3140 *
3141 * Will trigger pending interrupts.
3142 *
3143 * @param pThis The device state structure.
3144 * @param offset Register offset in memory-mapped frame.
3145 * @param index Register index in register array.
3146 * @param value The value to store.
3147 * @param mask Used to implement partial writes (8 and 16-bit).
3148 * @thread EMT
3149 */
3150static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3151{
3152 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3153
3154 IMS |= value;
3155 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3156 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3157 /*
3158 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3159 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3160 */
3161 if ((ICR & IMS) && !pThis->fLocked)
3162 {
3163 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3164 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3165 }
3166
3167 return VINF_SUCCESS;
3168}
3169
3170/**
3171 * Write handler for Interrupt Mask Clear register.
3172 *
3173 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3174 *
3175 * @param pThis The device state structure.
3176 * @param offset Register offset in memory-mapped frame.
3177 * @param index Register index in register array.
3178 * @param value The value to store.
3179 * @param mask Used to implement partial writes (8 and 16-bit).
3180 * @thread EMT
3181 */
3182static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3183{
3184 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3185
3186 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3187 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3188 return rc;
3189 if (pThis->fIntRaised)
3190 {
3191 /*
3192 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3193 * Windows to freeze since it may receive an interrupt while still in the very beginning
3194 * of interrupt handler.
3195 */
3196 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3197 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3198 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3199 /* Lower(0) INTA(0) */
3200 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3201 pThis->fIntRaised = false;
3202 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3203 }
3204 IMS &= ~value;
3205 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3206 e1kCsLeave(pThis);
3207
3208 return VINF_SUCCESS;
3209}
3210
3211/**
3212 * Write handler for Receive Control register.
3213 *
3214 * @param pThis The device state structure.
3215 * @param offset Register offset in memory-mapped frame.
3216 * @param index Register index in register array.
3217 * @param value The value to store.
3218 * @param mask Used to implement partial writes (8 and 16-bit).
3219 * @thread EMT
3220 */
3221static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3222{
3223 /* Update promiscuous mode */
3224 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3225 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3226 {
3227 /* Promiscuity has changed, pass the knowledge on. */
3228#ifndef IN_RING3
3229 return VINF_IOM_R3_MMIO_WRITE;
3230#else
3231 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3232 if (pThisCC->pDrvR3)
3233 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3234#endif
3235 }
3236
3237 /* Adjust receive buffer size */
3238 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3239 if (value & RCTL_BSEX)
3240 cbRxBuf *= 16;
3241 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3242 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3243 if (cbRxBuf != pThis->u16RxBSize)
3244 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3245 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3246 Assert(cbRxBuf < 65536);
3247 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3248
3249 /* Update the register */
3250 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3251}
3252
3253/**
3254 * Write handler for Packet Buffer Allocation register.
3255 *
3256 * TXA = 64 - RXA.
3257 *
3258 * @param pThis The device state structure.
3259 * @param offset Register offset in memory-mapped frame.
3260 * @param index Register index in register array.
3261 * @param value The value to store.
3262 * @param mask Used to implement partial writes (8 and 16-bit).
3263 * @thread EMT
3264 */
3265static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3266{
3267 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3268 PBA_st->txa = 64 - PBA_st->rxa;
3269
3270 return VINF_SUCCESS;
3271}
3272
3273/**
3274 * Write handler for Receive Descriptor Tail register.
3275 *
3276 * @remarks Write into RDT forces switch to HC and signal to
3277 * e1kR3NetworkDown_WaitReceiveAvail().
3278 *
3279 * @returns VBox status code.
3280 *
3281 * @param pThis The device state structure.
3282 * @param offset Register offset in memory-mapped frame.
3283 * @param index Register index in register array.
3284 * @param value The value to store.
3285 * @param mask Used to implement partial writes (8 and 16-bit).
3286 * @thread EMT
3287 */
3288static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3289{
3290#ifndef IN_RING3
3291 /* XXX */
3292// return VINF_IOM_R3_MMIO_WRITE;
3293#endif
3294 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3295 if (RT_LIKELY(rc == VINF_SUCCESS))
3296 {
3297 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3298#ifndef E1K_WITH_RXD_CACHE
3299 /*
3300 * Some drivers advance RDT too far, so that it equals RDH. This
3301 * somehow manages to work with real hardware but not with this
3302 * emulated device. We can work with these drivers if we just
3303 * write 1 less when we see a driver writing RDT equal to RDH,
3304 * see @bugref{7346}.
3305 */
3306 if (value == RDH)
3307 {
3308 if (RDH == 0)
3309 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3310 else
3311 value = RDH - 1;
3312 }
3313#endif /* !E1K_WITH_RXD_CACHE */
3314 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3315#ifdef E1K_WITH_RXD_CACHE
3316 /*
3317 * We need to fetch descriptors now as RDT may go whole circle
3318 * before we attempt to store a received packet. For example,
3319 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3320 * size being only 8 descriptors! Note that we fetch descriptors
3321 * only when the cache is empty to reduce the number of memory reads
3322 * in case of frequent RDT writes. Don't fetch anything when the
3323 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3324 * messed up state.
3325 * Note that despite the cache may seem empty, meaning that there are
3326 * no more available descriptors in it, it may still be used by RX
3327 * thread which has not yet written the last descriptor back but has
3328 * temporarily released the RX lock in order to write the packet body
3329 * to descriptor's buffer. At this point we still going to do prefetch
3330 * but it won't actually fetch anything if there are no unused slots in
3331 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3332 * reset the cache here even if it appears empty. It will be reset at
3333 * a later point in e1kRxDGet().
3334 */
3335 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3336 e1kRxDPrefetch(pDevIns, pThis);
3337#endif /* E1K_WITH_RXD_CACHE */
3338 e1kCsRxLeave(pThis);
3339 if (RT_SUCCESS(rc))
3340 {
3341 /* Signal that we have more receive descriptors available. */
3342 e1kWakeupReceive(pDevIns, pThis);
3343 }
3344 }
3345 return rc;
3346}
3347
3348/**
3349 * Write handler for Receive Delay Timer register.
3350 *
3351 * @param pThis The device state structure.
3352 * @param offset Register offset in memory-mapped frame.
3353 * @param index Register index in register array.
3354 * @param value The value to store.
3355 * @param mask Used to implement partial writes (8 and 16-bit).
3356 * @thread EMT
3357 */
3358static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3359{
3360 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3361 if (value & RDTR_FPD)
3362 {
3363 /* Flush requested, cancel both timers and raise interrupt */
3364#ifdef E1K_USE_RX_TIMERS
3365 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3366 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3367#endif
3368 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3369 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3370 }
3371
3372 return VINF_SUCCESS;
3373}
3374
3375DECLINLINE(uint32_t) e1kGetTxLen(PE1KSTATE pThis)
3376{
3377 /**
3378 * Make sure TDT won't change during computation. EMT may modify TDT at
3379 * any moment.
3380 */
3381 uint32_t tdt = TDT;
3382 return (TDH>tdt ? TDLEN/sizeof(E1KTXDESC) : 0) + tdt - TDH;
3383}
3384
3385#ifdef IN_RING3
3386
3387# ifdef E1K_TX_DELAY
3388/**
3389 * Transmit Delay Timer handler.
3390 *
3391 * @remarks We only get here when the timer expires.
3392 *
3393 * @param pDevIns Pointer to device instance structure.
3394 * @param pTimer Pointer to the timer.
3395 * @param pvUser NULL.
3396 * @thread EMT
3397 */
3398static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3399{
3400 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3401 Assert(PDMCritSectIsOwner(&pThis->csTx));
3402
3403 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3404# ifdef E1K_INT_STATS
3405 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3406 if (u64Elapsed > pThis->uStatMaxTxDelay)
3407 pThis->uStatMaxTxDelay = u64Elapsed;
3408# endif
3409 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3410 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3411}
3412# endif /* E1K_TX_DELAY */
3413
3414//# ifdef E1K_USE_TX_TIMERS
3415
3416/**
3417 * Transmit Interrupt Delay Timer handler.
3418 *
3419 * @remarks We only get here when the timer expires.
3420 *
3421 * @param pDevIns Pointer to device instance structure.
3422 * @param pTimer Pointer to the timer.
3423 * @param pvUser NULL.
3424 * @thread EMT
3425 */
3426static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3427{
3428 RT_NOREF(pDevIns);
3429 RT_NOREF(pTimer);
3430 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3431
3432 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3433 /* Cancel absolute delay timer as we have already got attention */
3434# ifndef E1K_NO_TAD
3435 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3436# endif
3437 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3438}
3439
3440/**
3441 * Transmit Absolute Delay Timer handler.
3442 *
3443 * @remarks We only get here when the timer expires.
3444 *
3445 * @param pDevIns Pointer to device instance structure.
3446 * @param pTimer Pointer to the timer.
3447 * @param pvUser NULL.
3448 * @thread EMT
3449 */
3450static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3451{
3452 RT_NOREF(pDevIns);
3453 RT_NOREF(pTimer);
3454 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3455
3456 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3457 /* Cancel interrupt delay timer as we have already got attention */
3458 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3459 e1kRaiseInterrupt(pDevIns, pThis, ICR_TXDW);
3460}
3461
3462//# endif /* E1K_USE_TX_TIMERS */
3463# ifdef E1K_USE_RX_TIMERS
3464
3465/**
3466 * Receive Interrupt Delay Timer handler.
3467 *
3468 * @remarks We only get here when the timer expires.
3469 *
3470 * @param pDevIns Pointer to device instance structure.
3471 * @param pTimer Pointer to the timer.
3472 * @param pvUser NULL.
3473 * @thread EMT
3474 */
3475static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3476{
3477 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3478
3479 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3480 /* Cancel absolute delay timer as we have already got attention */
3481 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3482 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3483}
3484
3485/**
3486 * Receive Absolute Delay Timer handler.
3487 *
3488 * @remarks We only get here when the timer expires.
3489 *
3490 * @param pDevIns Pointer to device instance structure.
3491 * @param pTimer Pointer to the timer.
3492 * @param pvUser NULL.
3493 * @thread EMT
3494 */
3495static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3496{
3497 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3498
3499 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3500 /* Cancel interrupt delay timer as we have already got attention */
3501 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3502 e1kRaiseInterrupt(pDevIns, pThis, ICR_RXT0);
3503}
3504
3505# endif /* E1K_USE_RX_TIMERS */
3506
3507/**
3508 * Late Interrupt Timer handler.
3509 *
3510 * @param pDevIns Pointer to device instance structure.
3511 * @param pTimer Pointer to the timer.
3512 * @param pvUser NULL.
3513 * @thread EMT
3514 */
3515static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3516{
3517 RT_NOREF(pDevIns, pTimer);
3518 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3519
3520 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3521 STAM_COUNTER_INC(&pThis->StatLateInts);
3522 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3523# if 0
3524 if (pThis->iStatIntLost > -100)
3525 pThis->iStatIntLost--;
3526# endif
3527 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3528 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3529}
3530
3531/**
3532 * Link Up Timer handler.
3533 *
3534 * @param pDevIns Pointer to device instance structure.
3535 * @param pTimer Pointer to the timer.
3536 * @param pvUser NULL.
3537 * @thread EMT
3538 */
3539static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3540{
3541 RT_NOREF(pTimer);
3542 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3543 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3544
3545 /*
3546 * This can happen if we set the link status to down when the Link up timer was
3547 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3548 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3549 * on reset even if the cable is unplugged (see @bugref{8942}).
3550 */
3551 if (pThis->fCableConnected)
3552 {
3553 /* 82543GC does not have an internal PHY */
3554 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3555 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3556 }
3557# ifdef E1K_LSC_ON_RESET
3558 else if (pThis->eChip == E1K_CHIP_82543GC)
3559 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3560# endif /* E1K_LSC_ON_RESET */
3561}
3562
3563#endif /* IN_RING3 */
3564
3565/**
3566 * Sets up the GSO context according to the TSE new context descriptor.
3567 *
3568 * @param pGso The GSO context to setup.
3569 * @param pCtx The context descriptor.
3570 */
3571DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3572{
3573 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3574
3575 /*
3576 * See if the context descriptor describes something that could be TCP or
3577 * UDP over IPv[46].
3578 */
3579 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3580 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3581 {
3582 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3583 return;
3584 }
3585 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3586 {
3587 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3588 return;
3589 }
3590 if (RT_UNLIKELY( pCtx->dw2.fTCP
3591 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3592 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3593 {
3594 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3595 return;
3596 }
3597
3598 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3599 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3600 {
3601 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3602 return;
3603 }
3604
3605 /* IPv4 checksum offset. */
3606 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3607 {
3608 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3609 return;
3610 }
3611
3612 /* TCP/UDP checksum offsets. */
3613 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3614 != ( pCtx->dw2.fTCP
3615 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3616 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3617 {
3618 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3619 return;
3620 }
3621
3622 /*
3623 * Because of internal networking using a 16-bit size field for GSO context
3624 * plus frame, we have to make sure we don't exceed this.
3625 */
3626 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3627 {
3628 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3629 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3630 return;
3631 }
3632
3633 /*
3634 * We're good for now - we'll do more checks when seeing the data.
3635 * So, figure the type of offloading and setup the context.
3636 */
3637 if (pCtx->dw2.fIP)
3638 {
3639 if (pCtx->dw2.fTCP)
3640 {
3641 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3642 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3643 }
3644 else
3645 {
3646 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3647 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3648 }
3649 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3650 * this yet it seems)... */
3651 }
3652 else
3653 {
3654 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3655 if (pCtx->dw2.fTCP)
3656 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3657 else
3658 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3659 }
3660 pGso->offHdr1 = pCtx->ip.u8CSS;
3661 pGso->offHdr2 = pCtx->tu.u8CSS;
3662 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3663 pGso->cbMaxSeg = pCtx->dw3.u16MSS;
3664 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3665 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3666 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3667}
3668
3669/**
3670 * Checks if we can use GSO processing for the current TSE frame.
3671 *
3672 * @param pThis The device state structure.
3673 * @param pGso The GSO context.
3674 * @param pData The first data descriptor of the frame.
3675 * @param pCtx The TSO context descriptor.
3676 */
3677DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3678{
3679 if (!pData->cmd.fTSE)
3680 {
3681 E1kLog2(("e1kCanDoGso: !TSE\n"));
3682 return false;
3683 }
3684 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3685 {
3686 E1kLog(("e1kCanDoGso: VLE\n"));
3687 return false;
3688 }
3689 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3690 {
3691 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3692 return false;
3693 }
3694
3695 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3696 {
3697 case PDMNETWORKGSOTYPE_IPV4_TCP:
3698 case PDMNETWORKGSOTYPE_IPV4_UDP:
3699 if (!pData->dw3.fIXSM)
3700 {
3701 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3702 return false;
3703 }
3704 if (!pData->dw3.fTXSM)
3705 {
3706 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3707 return false;
3708 }
3709 /** @todo what more check should we perform here? Ethernet frame type? */
3710 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3711 return true;
3712
3713 case PDMNETWORKGSOTYPE_IPV6_TCP:
3714 case PDMNETWORKGSOTYPE_IPV6_UDP:
3715 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3716 {
3717 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3718 return false;
3719 }
3720 if (!pData->dw3.fTXSM)
3721 {
3722 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3723 return false;
3724 }
3725 /** @todo what more check should we perform here? Ethernet frame type? */
3726 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3727 return true;
3728
3729 default:
3730 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3731 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3732 return false;
3733 }
3734}
3735
3736/**
3737 * Frees the current xmit buffer.
3738 *
3739 * @param pThis The device state structure.
3740 */
3741static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3742{
3743 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3744 if (pSg)
3745 {
3746 pThisCC->CTX_SUFF(pTxSg) = NULL;
3747
3748 if (pSg->pvAllocator != pThis)
3749 {
3750 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3751 if (pDrv)
3752 pDrv->pfnFreeBuf(pDrv, pSg);
3753 }
3754 else
3755 {
3756 /* loopback */
3757 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3758 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3759 pSg->fFlags = 0;
3760 pSg->pvAllocator = NULL;
3761 }
3762 }
3763}
3764
3765#ifndef E1K_WITH_TXD_CACHE
3766/**
3767 * Allocates an xmit buffer.
3768 *
3769 * @returns See PDMINETWORKUP::pfnAllocBuf.
3770 * @param pThis The device state structure.
3771 * @param cbMin The minimum frame size.
3772 * @param fExactSize Whether cbMin is exact or if we have to max it
3773 * out to the max MTU size.
3774 * @param fGso Whether this is a GSO frame or not.
3775 */
3776DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3777{
3778 /* Adjust cbMin if necessary. */
3779 if (!fExactSize)
3780 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3781
3782 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3783 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3784 e1kXmitFreeBuf(pThis, pThisCC);
3785 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3786
3787 /*
3788 * Allocate the buffer.
3789 */
3790 PPDMSCATTERGATHER pSg;
3791 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3792 {
3793 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3794 if (RT_UNLIKELY(!pDrv))
3795 return VERR_NET_DOWN;
3796 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3797 if (RT_FAILURE(rc))
3798 {
3799 /* Suspend TX as we are out of buffers atm */
3800 STATUS |= STATUS_TXOFF;
3801 return rc;
3802 }
3803 }
3804 else
3805 {
3806 /* Create a loopback using the fallback buffer and preallocated SG. */
3807 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3808 pSg = &pThis->uTxFallback.Sg;
3809 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3810 pSg->cbUsed = 0;
3811 pSg->cbAvailable = 0;
3812 pSg->pvAllocator = pThis;
3813 pSg->pvUser = NULL; /* No GSO here. */
3814 pSg->cSegs = 1;
3815 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3816 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3817 }
3818
3819 pThisCC->CTX_SUFF(pTxSg) = pSg;
3820 return VINF_SUCCESS;
3821}
3822#else /* E1K_WITH_TXD_CACHE */
3823/**
3824 * Allocates an xmit buffer.
3825 *
3826 * @returns See PDMINETWORKUP::pfnAllocBuf.
3827 * @param pThis The device state structure.
3828 * @param cbMin The minimum frame size.
3829 * @param fExactSize Whether cbMin is exact or if we have to max it
3830 * out to the max MTU size.
3831 * @param fGso Whether this is a GSO frame or not.
3832 */
3833DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3834{
3835 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3836 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3837 e1kXmitFreeBuf(pThis, pThisCC);
3838 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3839
3840 /*
3841 * Allocate the buffer.
3842 */
3843 PPDMSCATTERGATHER pSg;
3844 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3845 {
3846 if (pThis->cbTxAlloc == 0)
3847 {
3848 /* Zero packet, no need for the buffer */
3849 return VINF_SUCCESS;
3850 }
3851
3852 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3853 if (RT_UNLIKELY(!pDrv))
3854 return VERR_NET_DOWN;
3855 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3856 if (RT_FAILURE(rc))
3857 {
3858 /* Suspend TX as we are out of buffers atm */
3859 STATUS |= STATUS_TXOFF;
3860 return rc;
3861 }
3862 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3863 pThis->szPrf, pThis->cbTxAlloc,
3864 pThis->fVTag ? "VLAN " : "",
3865 pThis->fGSO ? "GSO " : ""));
3866 }
3867 else
3868 {
3869 /* Create a loopback using the fallback buffer and preallocated SG. */
3870 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3871 pSg = &pThis->uTxFallback.Sg;
3872 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3873 pSg->cbUsed = 0;
3874 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
3875 pSg->pvAllocator = pThis;
3876 pSg->pvUser = NULL; /* No GSO here. */
3877 pSg->cSegs = 1;
3878 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3879 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3880 }
3881 pThis->cbTxAlloc = 0;
3882
3883 pThisCC->CTX_SUFF(pTxSg) = pSg;
3884 return VINF_SUCCESS;
3885}
3886#endif /* E1K_WITH_TXD_CACHE */
3887
3888/**
3889 * Checks if it's a GSO buffer or not.
3890 *
3891 * @returns true / false.
3892 * @param pTxSg The scatter / gather buffer.
3893 */
3894DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3895{
3896#if 0
3897 if (!pTxSg)
3898 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3899 if (pTxSg && pTxSg->pvUser)
3900 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3901#endif
3902 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3903}
3904
3905#ifndef E1K_WITH_TXD_CACHE
3906/**
3907 * Load transmit descriptor from guest memory.
3908 *
3909 * @param pDevIns The device instance.
3910 * @param pDesc Pointer to descriptor union.
3911 * @param addr Physical address in guest context.
3912 * @thread E1000_TX
3913 */
3914DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
3915{
3916 PDMDevHlpPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
3917}
3918#else /* E1K_WITH_TXD_CACHE */
3919/**
3920 * Load transmit descriptors from guest memory.
3921 *
3922 * We need two physical reads in case the tail wrapped around the end of TX
3923 * descriptor ring.
3924 *
3925 * @returns the actual number of descriptors fetched.
3926 * @param pDevIns The device instance.
3927 * @param pThis The device state structure.
3928 * @thread E1000_TX
3929 */
3930DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3931{
3932 Assert(pThis->iTxDCurrent == 0);
3933 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
3934 unsigned nDescsAvailable = e1kGetTxLen(pThis) - pThis->nTxDFetched;
3935 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
3936 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
3937 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
3938 unsigned nDescsTotal = TDLEN / sizeof(E1KTXDESC);
3939 unsigned nFirstNotLoaded = (TDH + pThis->nTxDFetched) % nDescsTotal;
3940 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
3941 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
3942 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
3943 nFirstNotLoaded, nDescsInSingleRead));
3944 if (nDescsToFetch == 0)
3945 return 0;
3946 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
3947 PDMDevHlpPhysRead(pDevIns,
3948 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
3949 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
3950 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
3951 pThis->szPrf, nDescsInSingleRead,
3952 TDBAH, TDBAL + TDH * sizeof(E1KTXDESC),
3953 nFirstNotLoaded, TDLEN, TDH, TDT));
3954 if (nDescsToFetch > nDescsInSingleRead)
3955 {
3956 PDMDevHlpPhysRead(pDevIns,
3957 ((uint64_t)TDBAH << 32) + TDBAL,
3958 pFirstEmptyDesc + nDescsInSingleRead,
3959 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
3960 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
3961 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
3962 TDBAH, TDBAL));
3963 }
3964 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
3965 return nDescsToFetch;
3966}
3967
3968/**
3969 * Load transmit descriptors from guest memory only if there are no loaded
3970 * descriptors.
3971 *
3972 * @returns true if there are descriptors in cache.
3973 * @param pDevIns The device instance.
3974 * @param pThis The device state structure.
3975 * @thread E1000_TX
3976 */
3977DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis)
3978{
3979 if (pThis->nTxDFetched == 0)
3980 return e1kTxDLoadMore(pDevIns, pThis) != 0;
3981 return true;
3982}
3983#endif /* E1K_WITH_TXD_CACHE */
3984
3985/**
3986 * Write back transmit descriptor to guest memory.
3987 *
3988 * @param pDevIns The device instance.
3989 * @param pThis The device state structure.
3990 * @param pDesc Pointer to descriptor union.
3991 * @param addr Physical address in guest context.
3992 * @thread E1000_TX
3993 */
3994DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
3995{
3996 /* Only the last half of the descriptor has to be written back. */
3997 e1kPrintTDesc(pThis, pDesc, "^^^");
3998 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
3999}
4000
4001/**
4002 * Transmit complete frame.
4003 *
4004 * @remarks We skip the FCS since we're not responsible for sending anything to
4005 * a real ethernet wire.
4006 *
4007 * @param pDevIns The device instance.
4008 * @param pThis The device state structure.
4009 * @param pThisCC The current context instance data.
4010 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4011 * @thread E1000_TX
4012 */
4013static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4014{
4015 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4016 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4017 Assert(!pSg || pSg->cSegs == 1);
4018
4019 if (cbFrame > 70) /* unqualified guess */
4020 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4021
4022#ifdef E1K_INT_STATS
4023 if (cbFrame <= 1514)
4024 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4025 else if (cbFrame <= 2962)
4026 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4027 else if (cbFrame <= 4410)
4028 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4029 else if (cbFrame <= 5858)
4030 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4031 else if (cbFrame <= 7306)
4032 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4033 else if (cbFrame <= 8754)
4034 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4035 else if (cbFrame <= 16384)
4036 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4037 else if (cbFrame <= 32768)
4038 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4039 else
4040 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4041#endif /* E1K_INT_STATS */
4042
4043 /* Add VLAN tag */
4044 if (cbFrame > 12 && pThis->fVTag)
4045 {
4046 E1kLog3(("%s Inserting VLAN tag %08x\n",
4047 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4048 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4049 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4050 pSg->cbUsed += 4;
4051 cbFrame += 4;
4052 Assert(pSg->cbUsed == cbFrame);
4053 Assert(pSg->cbUsed <= pSg->cbAvailable);
4054 }
4055/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4056 "%.*Rhxd\n"
4057 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4058 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4059
4060 /* Update the stats */
4061 E1K_INC_CNT32(TPT);
4062 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4063 E1K_INC_CNT32(GPTC);
4064 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4065 E1K_INC_CNT32(BPTC);
4066 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4067 E1K_INC_CNT32(MPTC);
4068 /* Update octet transmit counter */
4069 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4070 if (pThisCC->CTX_SUFF(pDrv))
4071 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4072 if (cbFrame == 64)
4073 E1K_INC_CNT32(PTC64);
4074 else if (cbFrame < 128)
4075 E1K_INC_CNT32(PTC127);
4076 else if (cbFrame < 256)
4077 E1K_INC_CNT32(PTC255);
4078 else if (cbFrame < 512)
4079 E1K_INC_CNT32(PTC511);
4080 else if (cbFrame < 1024)
4081 E1K_INC_CNT32(PTC1023);
4082 else
4083 E1K_INC_CNT32(PTC1522);
4084
4085 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4086
4087 /*
4088 * Dump and send the packet.
4089 */
4090 int rc = VERR_NET_DOWN;
4091 if (pSg && pSg->pvAllocator != pThis)
4092 {
4093 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4094
4095 pThisCC->CTX_SUFF(pTxSg) = NULL;
4096 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4097 if (pDrv)
4098 {
4099 /* Release critical section to avoid deadlock in CanReceive */
4100 //e1kCsLeave(pThis);
4101 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4102 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4103 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4104 //e1kCsEnter(pThis, RT_SRC_POS);
4105 }
4106 }
4107 else if (pSg)
4108 {
4109 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4110 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4111
4112 /** @todo do we actually need to check that we're in loopback mode here? */
4113 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4114 {
4115 E1KRXDST status;
4116 RT_ZERO(status);
4117 status.fPIF = true;
4118 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4119 rc = VINF_SUCCESS;
4120 }
4121 e1kXmitFreeBuf(pThis, pThisCC);
4122 }
4123 else
4124 rc = VERR_NET_DOWN;
4125 if (RT_FAILURE(rc))
4126 {
4127 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4128 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4129 }
4130
4131 pThis->led.Actual.s.fWriting = 0;
4132}
4133
4134/**
4135 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4136 *
4137 * @param pThis The device state structure.
4138 * @param pPkt Pointer to the packet.
4139 * @param u16PktLen Total length of the packet.
4140 * @param cso Offset in packet to write checksum at.
4141 * @param css Offset in packet to start computing
4142 * checksum from.
4143 * @param cse Offset in packet to stop computing
4144 * checksum at.
4145 * @thread E1000_TX
4146 */
4147static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
4148{
4149 RT_NOREF1(pThis);
4150
4151 if (css >= u16PktLen)
4152 {
4153 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4154 pThis->szPrf, cso, u16PktLen));
4155 return;
4156 }
4157
4158 if (cso >= u16PktLen - 1)
4159 {
4160 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4161 pThis->szPrf, cso, u16PktLen));
4162 return;
4163 }
4164
4165 if (cse == 0)
4166 cse = u16PktLen - 1;
4167 else if (cse < css)
4168 {
4169 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4170 pThis->szPrf, css, cse));
4171 return;
4172 }
4173
4174 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4175 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4176 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4177 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4178}
4179
4180/**
4181 * Add a part of descriptor's buffer to transmit frame.
4182 *
4183 * @remarks data.u64BufAddr is used unconditionally for both data
4184 * and legacy descriptors since it is identical to
4185 * legacy.u64BufAddr.
4186 *
4187 * @param pDevIns The device instance.
4188 * @param pThis The device state structure.
4189 * @param pDesc Pointer to the descriptor to transmit.
4190 * @param u16Len Length of buffer to the end of segment.
4191 * @param fSend Force packet sending.
4192 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4193 * @thread E1000_TX
4194 */
4195#ifndef E1K_WITH_TXD_CACHE
4196static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4197{
4198 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4199 /* TCP header being transmitted */
4200 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4201 /* IP header being transmitted */
4202 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4203
4204 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4205 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4206 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4207
4208 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4209 E1kLog3(("%s Dump of the segment:\n"
4210 "%.*Rhxd\n"
4211 "%s --- End of dump ---\n",
4212 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4213 pThis->u16TxPktLen += u16Len;
4214 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4215 pThis->szPrf, pThis->u16TxPktLen));
4216 if (pThis->u16HdrRemain > 0)
4217 {
4218 /* The header was not complete, check if it is now */
4219 if (u16Len >= pThis->u16HdrRemain)
4220 {
4221 /* The rest is payload */
4222 u16Len -= pThis->u16HdrRemain;
4223 pThis->u16HdrRemain = 0;
4224 /* Save partial checksum and flags */
4225 pThis->u32SavedCsum = pTcpHdr->chksum;
4226 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4227 /* Clear FIN and PSH flags now and set them only in the last segment */
4228 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4229 }
4230 else
4231 {
4232 /* Still not */
4233 pThis->u16HdrRemain -= u16Len;
4234 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4235 pThis->szPrf, pThis->u16HdrRemain));
4236 return;
4237 }
4238 }
4239
4240 pThis->u32PayRemain -= u16Len;
4241
4242 if (fSend)
4243 {
4244 /* Leave ethernet header intact */
4245 /* IP Total Length = payload + headers - ethernet header */
4246 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4247 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4248 pThis->szPrf, ntohs(pIpHdr->total_len)));
4249 /* Update IP Checksum */
4250 pIpHdr->chksum = 0;
4251 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4252 pThis->contextTSE.ip.u8CSO,
4253 pThis->contextTSE.ip.u8CSS,
4254 pThis->contextTSE.ip.u16CSE);
4255
4256 /* Update TCP flags */
4257 /* Restore original FIN and PSH flags for the last segment */
4258 if (pThis->u32PayRemain == 0)
4259 {
4260 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4261 E1K_INC_CNT32(TSCTC);
4262 }
4263 /* Add TCP length to partial pseudo header sum */
4264 uint32_t csum = pThis->u32SavedCsum
4265 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4266 while (csum >> 16)
4267 csum = (csum >> 16) + (csum & 0xFFFF);
4268 pTcpHdr->chksum = csum;
4269 /* Compute final checksum */
4270 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4271 pThis->contextTSE.tu.u8CSO,
4272 pThis->contextTSE.tu.u8CSS,
4273 pThis->contextTSE.tu.u16CSE);
4274
4275 /*
4276 * Transmit it. If we've use the SG already, allocate a new one before
4277 * we copy of the data.
4278 */
4279 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4280 if (!pTxSg)
4281 {
4282 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4283 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4284 }
4285 if (pTxSg)
4286 {
4287 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4288 Assert(pTxSg->cSegs == 1);
4289 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4290 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4291 pTxSg->cbUsed = pThis->u16TxPktLen;
4292 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4293 }
4294 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4295
4296 /* Update Sequence Number */
4297 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4298 - pThis->contextTSE.dw3.u8HDRLEN);
4299 /* Increment IP identification */
4300 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4301 }
4302}
4303#else /* E1K_WITH_TXD_CACHE */
4304static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4305{
4306 int rc = VINF_SUCCESS;
4307 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4308 /* TCP header being transmitted */
4309 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4310 /* IP header being transmitted */
4311 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4312
4313 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4314 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4315 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4316
4317 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4318 PDMDevHlpPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4319 else
4320 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4321 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4322 E1kLog3(("%s Dump of the segment:\n"
4323 "%.*Rhxd\n"
4324 "%s --- End of dump ---\n",
4325 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4326 pThis->u16TxPktLen += u16Len;
4327 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4328 pThis->szPrf, pThis->u16TxPktLen));
4329 if (pThis->u16HdrRemain > 0)
4330 {
4331 /* The header was not complete, check if it is now */
4332 if (u16Len >= pThis->u16HdrRemain)
4333 {
4334 /* The rest is payload */
4335 u16Len -= pThis->u16HdrRemain;
4336 pThis->u16HdrRemain = 0;
4337 /* Save partial checksum and flags */
4338 pThis->u32SavedCsum = pTcpHdr->chksum;
4339 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4340 /* Clear FIN and PSH flags now and set them only in the last segment */
4341 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4342 }
4343 else
4344 {
4345 /* Still not */
4346 pThis->u16HdrRemain -= u16Len;
4347 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4348 pThis->szPrf, pThis->u16HdrRemain));
4349 return rc;
4350 }
4351 }
4352
4353 if (u16Len > pThis->u32PayRemain)
4354 pThis->u32PayRemain = 0;
4355 else
4356 pThis->u32PayRemain -= u16Len;
4357
4358 if (fSend)
4359 {
4360 /* Leave ethernet header intact */
4361 /* IP Total Length = payload + headers - ethernet header */
4362 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4363 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4364 pThis->szPrf, ntohs(pIpHdr->total_len)));
4365 /* Update IP Checksum */
4366 pIpHdr->chksum = 0;
4367 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4368 pThis->contextTSE.ip.u8CSO,
4369 pThis->contextTSE.ip.u8CSS,
4370 pThis->contextTSE.ip.u16CSE);
4371
4372 /* Update TCP flags */
4373 /* Restore original FIN and PSH flags for the last segment */
4374 if (pThis->u32PayRemain == 0)
4375 {
4376 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4377 E1K_INC_CNT32(TSCTC);
4378 }
4379 /* Add TCP length to partial pseudo header sum */
4380 uint32_t csum = pThis->u32SavedCsum
4381 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4382 while (csum >> 16)
4383 csum = (csum >> 16) + (csum & 0xFFFF);
4384 Assert(csum < 65536);
4385 pTcpHdr->chksum = (uint16_t)csum;
4386 /* Compute final checksum */
4387 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4388 pThis->contextTSE.tu.u8CSO,
4389 pThis->contextTSE.tu.u8CSS,
4390 pThis->contextTSE.tu.u16CSE);
4391
4392 /*
4393 * Transmit it.
4394 */
4395 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4396 if (pTxSg)
4397 {
4398 /* Make sure the packet fits into the allocated buffer */
4399 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4400#ifdef DEBUG
4401 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4402 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4403 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4404#endif /* DEBUG */
4405 Assert(pTxSg->cSegs == 1);
4406 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4407 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4408 pTxSg->cbUsed = cbCopy;
4409 pTxSg->aSegs[0].cbSeg = cbCopy;
4410 }
4411 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4412
4413 /* Update Sequence Number */
4414 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4415 - pThis->contextTSE.dw3.u8HDRLEN);
4416 /* Increment IP identification */
4417 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4418
4419 /* Allocate new buffer for the next segment. */
4420 if (pThis->u32PayRemain)
4421 {
4422 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4423 pThis->contextTSE.dw3.u16MSS)
4424 + pThis->contextTSE.dw3.u8HDRLEN
4425 + (pThis->fVTag ? 4 : 0);
4426 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4427 }
4428 }
4429
4430 return rc;
4431}
4432#endif /* E1K_WITH_TXD_CACHE */
4433
4434#ifndef E1K_WITH_TXD_CACHE
4435/**
4436 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4437 * frame.
4438 *
4439 * We construct the frame in the fallback buffer first and the copy it to the SG
4440 * buffer before passing it down to the network driver code.
4441 *
4442 * @returns true if the frame should be transmitted, false if not.
4443 *
4444 * @param pThis The device state structure.
4445 * @param pDesc Pointer to the descriptor to transmit.
4446 * @param cbFragment Length of descriptor's buffer.
4447 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4448 * @thread E1000_TX
4449 */
4450static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4451{
4452 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4453 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4454 Assert(pDesc->data.cmd.fTSE);
4455 Assert(!e1kXmitIsGsoBuf(pTxSg));
4456
4457 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4458 Assert(u16MaxPktLen != 0);
4459 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4460
4461 /*
4462 * Carve out segments.
4463 */
4464 do
4465 {
4466 /* Calculate how many bytes we have left in this TCP segment */
4467 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4468 if (cb > cbFragment)
4469 {
4470 /* This descriptor fits completely into current segment */
4471 cb = cbFragment;
4472 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4473 }
4474 else
4475 {
4476 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4477 /*
4478 * Rewind the packet tail pointer to the beginning of payload,
4479 * so we continue writing right beyond the header.
4480 */
4481 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4482 }
4483
4484 pDesc->data.u64BufAddr += cb;
4485 cbFragment -= cb;
4486 } while (cbFragment > 0);
4487
4488 if (pDesc->data.cmd.fEOP)
4489 {
4490 /* End of packet, next segment will contain header. */
4491 if (pThis->u32PayRemain != 0)
4492 E1K_INC_CNT32(TSCTFC);
4493 pThis->u16TxPktLen = 0;
4494 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4495 }
4496
4497 return false;
4498}
4499#else /* E1K_WITH_TXD_CACHE */
4500/**
4501 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4502 * frame.
4503 *
4504 * We construct the frame in the fallback buffer first and the copy it to the SG
4505 * buffer before passing it down to the network driver code.
4506 *
4507 * @returns error code
4508 *
4509 * @param pDevIns The device instance.
4510 * @param pThis The device state structure.
4511 * @param pDesc Pointer to the descriptor to transmit.
4512 * @param cbFragment Length of descriptor's buffer.
4513 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4514 * @thread E1000_TX
4515 */
4516static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4517{
4518#ifdef VBOX_STRICT
4519 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4520 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4521 Assert(pDesc->data.cmd.fTSE);
4522 Assert(!e1kXmitIsGsoBuf(pTxSg));
4523#endif
4524
4525 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4526 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4527 if (u16MaxPktLen == 0)
4528 return VINF_SUCCESS;
4529
4530 /*
4531 * Carve out segments.
4532 */
4533 int rc = VINF_SUCCESS;
4534 do
4535 {
4536 /* Calculate how many bytes we have left in this TCP segment */
4537 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4538 if (cb > pDesc->data.cmd.u20DTALEN)
4539 {
4540 /* This descriptor fits completely into current segment */
4541 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4542 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4543 }
4544 else
4545 {
4546 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4547 /*
4548 * Rewind the packet tail pointer to the beginning of payload,
4549 * so we continue writing right beyond the header.
4550 */
4551 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4552 }
4553
4554 pDesc->data.u64BufAddr += cb;
4555 pDesc->data.cmd.u20DTALEN -= cb;
4556 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4557
4558 if (pDesc->data.cmd.fEOP)
4559 {
4560 /* End of packet, next segment will contain header. */
4561 if (pThis->u32PayRemain != 0)
4562 E1K_INC_CNT32(TSCTFC);
4563 pThis->u16TxPktLen = 0;
4564 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4565 }
4566
4567 return VINF_SUCCESS; /// @todo consider rc;
4568}
4569#endif /* E1K_WITH_TXD_CACHE */
4570
4571
4572/**
4573 * Add descriptor's buffer to transmit frame.
4574 *
4575 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4576 * TSE frames we cannot handle as GSO.
4577 *
4578 * @returns true on success, false on failure.
4579 *
4580 * @param pDevIns The device instance.
4581 * @param pThisCC The current context instance data.
4582 * @param pThis The device state structure.
4583 * @param PhysAddr The physical address of the descriptor buffer.
4584 * @param cbFragment Length of descriptor's buffer.
4585 * @thread E1000_TX
4586 */
4587static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4588{
4589 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4590 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4591 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4592
4593 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4594 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4595 fGso ? "true" : "false"));
4596 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4597 {
4598 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4599 return false;
4600 }
4601 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4602 {
4603 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4604 return false;
4605 }
4606
4607 if (RT_LIKELY(pTxSg))
4608 {
4609 Assert(pTxSg->cSegs == 1);
4610 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4611 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4612 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4613
4614 PDMDevHlpPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4615
4616 pTxSg->cbUsed = cbNewPkt;
4617 }
4618 pThis->u16TxPktLen = cbNewPkt;
4619
4620 return true;
4621}
4622
4623
4624/**
4625 * Write the descriptor back to guest memory and notify the guest.
4626 *
4627 * @param pThis The device state structure.
4628 * @param pDesc Pointer to the descriptor have been transmitted.
4629 * @param addr Physical address of the descriptor in guest memory.
4630 * @thread E1000_TX
4631 */
4632static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4633{
4634 /*
4635 * We fake descriptor write-back bursting. Descriptors are written back as they are
4636 * processed.
4637 */
4638 /* Let's pretend we process descriptors. Write back with DD set. */
4639 /*
4640 * Prior to r71586 we tried to accomodate the case when write-back bursts
4641 * are enabled without actually implementing bursting by writing back all
4642 * descriptors, even the ones that do not have RS set. This caused kernel
4643 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4644 * associated with written back descriptor if it happened to be a context
4645 * descriptor since context descriptors do not have skb associated to them.
4646 * Starting from r71586 we write back only the descriptors with RS set,
4647 * which is a little bit different from what the real hardware does in
4648 * case there is a chain of data descritors where some of them have RS set
4649 * and others do not. It is very uncommon scenario imho.
4650 * We need to check RPS as well since some legacy drivers use it instead of
4651 * RS even with newer cards.
4652 */
4653 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4654 {
4655 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4656 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4657 if (pDesc->legacy.cmd.fEOP)
4658 {
4659//#ifdef E1K_USE_TX_TIMERS
4660 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4661 {
4662 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4663 //if (pThis->fIntRaised)
4664 //{
4665 // /* Interrupt is already pending, no need for timers */
4666 // ICR |= ICR_TXDW;
4667 //}
4668 //else {
4669 /* Arm the timer to fire in TIVD usec (discard .024) */
4670 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4671# ifndef E1K_NO_TAD
4672 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4673 E1kLog2(("%s Checking if TAD timer is running\n",
4674 pThis->szPrf));
4675 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4676 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4677# endif /* E1K_NO_TAD */
4678 }
4679 else
4680 {
4681 if (pThis->fTidEnabled)
4682 {
4683 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4684 pThis->szPrf));
4685 /* Cancel both timers if armed and fire immediately. */
4686# ifndef E1K_NO_TAD
4687 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4688# endif
4689 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4690 }
4691//#endif /* E1K_USE_TX_TIMERS */
4692 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4693 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4694//#ifdef E1K_USE_TX_TIMERS
4695 }
4696//#endif /* E1K_USE_TX_TIMERS */
4697 }
4698 }
4699 else
4700 {
4701 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4702 }
4703}
4704
4705#ifndef E1K_WITH_TXD_CACHE
4706
4707/**
4708 * Process Transmit Descriptor.
4709 *
4710 * E1000 supports three types of transmit descriptors:
4711 * - legacy data descriptors of older format (context-less).
4712 * - data the same as legacy but providing new offloading capabilities.
4713 * - context sets up the context for following data descriptors.
4714 *
4715 * @param pDevIns The device instance.
4716 * @param pThis The device state structure.
4717 * @param pThisCC The current context instance data.
4718 * @param pDesc Pointer to descriptor union.
4719 * @param addr Physical address of descriptor in guest memory.
4720 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4721 * @thread E1000_TX
4722 */
4723static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4724 RTGCPHYS addr, bool fOnWorkerThread)
4725{
4726 int rc = VINF_SUCCESS;
4727 uint32_t cbVTag = 0;
4728
4729 e1kPrintTDesc(pThis, pDesc, "vvv");
4730
4731//#ifdef E1K_USE_TX_TIMERS
4732 if (pThis->fTidEnabled)
4733 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4734//#endif /* E1K_USE_TX_TIMERS */
4735
4736 switch (e1kGetDescType(pDesc))
4737 {
4738 case E1K_DTYP_CONTEXT:
4739 if (pDesc->context.dw2.fTSE)
4740 {
4741 pThis->contextTSE = pDesc->context;
4742 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4743 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4744 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4745 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4746 }
4747 else
4748 {
4749 pThis->contextNormal = pDesc->context;
4750 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4751 }
4752 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4753 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4754 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4755 pDesc->context.ip.u8CSS,
4756 pDesc->context.ip.u8CSO,
4757 pDesc->context.ip.u16CSE,
4758 pDesc->context.tu.u8CSS,
4759 pDesc->context.tu.u8CSO,
4760 pDesc->context.tu.u16CSE));
4761 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4762 e1kDescReport(pThis, pDesc, addr);
4763 break;
4764
4765 case E1K_DTYP_DATA:
4766 {
4767 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4768 {
4769 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4770 /** @todo Same as legacy when !TSE. See below. */
4771 break;
4772 }
4773 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4774 &pThis->StatTxDescTSEData:
4775 &pThis->StatTxDescData);
4776 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4777 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4778
4779 /*
4780 * The last descriptor of non-TSE packet must contain VLE flag.
4781 * TSE packets have VLE flag in the first descriptor. The later
4782 * case is taken care of a bit later when cbVTag gets assigned.
4783 *
4784 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4785 */
4786 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4787 {
4788 pThis->fVTag = pDesc->data.cmd.fVLE;
4789 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4790 }
4791 /*
4792 * First fragment: Allocate new buffer and save the IXSM and TXSM
4793 * packet options as these are only valid in the first fragment.
4794 */
4795 if (pThis->u16TxPktLen == 0)
4796 {
4797 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4798 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4799 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4800 pThis->fIPcsum ? " IP" : "",
4801 pThis->fTCPcsum ? " TCP/UDP" : ""));
4802 if (pDesc->data.cmd.fTSE)
4803 {
4804 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4805 pThis->fVTag = pDesc->data.cmd.fVLE;
4806 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4807 cbVTag = pThis->fVTag ? 4 : 0;
4808 }
4809 else if (pDesc->data.cmd.fEOP)
4810 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4811 else
4812 cbVTag = 4;
4813 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4814 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4815 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4816 true /*fExactSize*/, true /*fGso*/);
4817 else if (pDesc->data.cmd.fTSE)
4818 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4819 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4820 else
4821 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4822 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4823
4824 /**
4825 * @todo: Perhaps it is not that simple for GSO packets! We may
4826 * need to unwind some changes.
4827 */
4828 if (RT_FAILURE(rc))
4829 {
4830 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4831 break;
4832 }
4833 /** @todo Is there any way to indicating errors other than collisions? Like
4834 * VERR_NET_DOWN. */
4835 }
4836
4837 /*
4838 * Add the descriptor data to the frame. If the frame is complete,
4839 * transmit it and reset the u16TxPktLen field.
4840 */
4841 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
4842 {
4843 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4844 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4845 if (pDesc->data.cmd.fEOP)
4846 {
4847 if ( fRc
4848 && pThisCC->CTX_SUFF(pTxSg)
4849 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4850 {
4851 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4852 E1K_INC_CNT32(TSCTC);
4853 }
4854 else
4855 {
4856 if (fRc)
4857 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4858 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
4859 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4860 e1kXmitFreeBuf(pThis);
4861 E1K_INC_CNT32(TSCTFC);
4862 }
4863 pThis->u16TxPktLen = 0;
4864 }
4865 }
4866 else if (!pDesc->data.cmd.fTSE)
4867 {
4868 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4869 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4870 if (pDesc->data.cmd.fEOP)
4871 {
4872 if (fRc && pThisCC->CTX_SUFF(pTxSg))
4873 {
4874 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
4875 if (pThis->fIPcsum)
4876 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4877 pThis->contextNormal.ip.u8CSO,
4878 pThis->contextNormal.ip.u8CSS,
4879 pThis->contextNormal.ip.u16CSE);
4880 if (pThis->fTCPcsum)
4881 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4882 pThis->contextNormal.tu.u8CSO,
4883 pThis->contextNormal.tu.u8CSS,
4884 pThis->contextNormal.tu.u16CSE);
4885 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4886 }
4887 else
4888 e1kXmitFreeBuf(pThis);
4889 pThis->u16TxPktLen = 0;
4890 }
4891 }
4892 else
4893 {
4894 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
4895 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
4896 }
4897
4898 e1kDescReport(pThis, pDesc, addr);
4899 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4900 break;
4901 }
4902
4903 case E1K_DTYP_LEGACY:
4904 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
4905 {
4906 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
4907 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
4908 break;
4909 }
4910 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
4911 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4912
4913 /* First fragment: allocate new buffer. */
4914 if (pThis->u16TxPktLen == 0)
4915 {
4916 if (pDesc->legacy.cmd.fEOP)
4917 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
4918 else
4919 cbVTag = 4;
4920 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4921 /** @todo reset status bits? */
4922 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
4923 if (RT_FAILURE(rc))
4924 {
4925 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4926 break;
4927 }
4928
4929 /** @todo Is there any way to indicating errors other than collisions? Like
4930 * VERR_NET_DOWN. */
4931 }
4932
4933 /* Add fragment to frame. */
4934 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
4935 {
4936 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
4937
4938 /* Last fragment: Transmit and reset the packet storage counter. */
4939 if (pDesc->legacy.cmd.fEOP)
4940 {
4941 pThis->fVTag = pDesc->legacy.cmd.fVLE;
4942 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
4943 /** @todo Offload processing goes here. */
4944 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4945 pThis->u16TxPktLen = 0;
4946 }
4947 }
4948 /* Last fragment + failure: free the buffer and reset the storage counter. */
4949 else if (pDesc->legacy.cmd.fEOP)
4950 {
4951 e1kXmitFreeBuf(pThis);
4952 pThis->u16TxPktLen = 0;
4953 }
4954
4955 e1kDescReport(pThis, pDesc, addr);
4956 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4957 break;
4958
4959 default:
4960 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
4961 pThis->szPrf, e1kGetDescType(pDesc)));
4962 break;
4963 }
4964
4965 return rc;
4966}
4967
4968#else /* E1K_WITH_TXD_CACHE */
4969
4970/**
4971 * Process Transmit Descriptor.
4972 *
4973 * E1000 supports three types of transmit descriptors:
4974 * - legacy data descriptors of older format (context-less).
4975 * - data the same as legacy but providing new offloading capabilities.
4976 * - context sets up the context for following data descriptors.
4977 *
4978 * @param pDevIns The device instance.
4979 * @param pThis The device state structure.
4980 * @param pThisCC The current context instance data.
4981 * @param pDesc Pointer to descriptor union.
4982 * @param addr Physical address of descriptor in guest memory.
4983 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4984 * @param cbPacketSize Size of the packet as previously computed.
4985 * @thread E1000_TX
4986 */
4987static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4988 RTGCPHYS addr, bool fOnWorkerThread)
4989{
4990 int rc = VINF_SUCCESS;
4991
4992 e1kPrintTDesc(pThis, pDesc, "vvv");
4993
4994 if (pDesc->legacy.dw3.fDD)
4995 {
4996 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
4997 e1kDescReport(pDevIns, pThis, pDesc, addr);
4998 return VINF_SUCCESS;
4999 }
5000
5001//#ifdef E1K_USE_TX_TIMERS
5002 if (pThis->fTidEnabled)
5003 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5004//#endif /* E1K_USE_TX_TIMERS */
5005
5006 switch (e1kGetDescType(pDesc))
5007 {
5008 case E1K_DTYP_CONTEXT:
5009 /* The caller have already updated the context */
5010 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5011 e1kDescReport(pDevIns, pThis, pDesc, addr);
5012 break;
5013
5014 case E1K_DTYP_DATA:
5015 {
5016 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5017 &pThis->StatTxDescTSEData:
5018 &pThis->StatTxDescData);
5019 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5020 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5021 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5022 {
5023 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
5024 if (pDesc->data.cmd.fEOP)
5025 {
5026 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5027 pThis->u16TxPktLen = 0;
5028 }
5029 }
5030 else
5031 {
5032 /*
5033 * Add the descriptor data to the frame. If the frame is complete,
5034 * transmit it and reset the u16TxPktLen field.
5035 */
5036 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5037 {
5038 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5039 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5040 if (pDesc->data.cmd.fEOP)
5041 {
5042 if ( fRc
5043 && pThisCC->CTX_SUFF(pTxSg)
5044 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5045 {
5046 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5047 E1K_INC_CNT32(TSCTC);
5048 }
5049 else
5050 {
5051 if (fRc)
5052 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5053 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5054 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5055 e1kXmitFreeBuf(pThis, pThisCC);
5056 E1K_INC_CNT32(TSCTFC);
5057 }
5058 pThis->u16TxPktLen = 0;
5059 }
5060 }
5061 else if (!pDesc->data.cmd.fTSE)
5062 {
5063 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5064 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5065 if (pDesc->data.cmd.fEOP)
5066 {
5067 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5068 {
5069 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5070 if (pThis->fIPcsum)
5071 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5072 pThis->contextNormal.ip.u8CSO,
5073 pThis->contextNormal.ip.u8CSS,
5074 pThis->contextNormal.ip.u16CSE);
5075 if (pThis->fTCPcsum)
5076 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5077 pThis->contextNormal.tu.u8CSO,
5078 pThis->contextNormal.tu.u8CSS,
5079 pThis->contextNormal.tu.u16CSE);
5080 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5081 }
5082 else
5083 e1kXmitFreeBuf(pThis, pThisCC);
5084 pThis->u16TxPktLen = 0;
5085 }
5086 }
5087 else
5088 {
5089 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5090 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5091 }
5092 }
5093 e1kDescReport(pDevIns, pThis, pDesc, addr);
5094 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5095 break;
5096 }
5097
5098 case E1K_DTYP_LEGACY:
5099 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5100 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5101 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5102 {
5103 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5104 }
5105 else
5106 {
5107 /* Add fragment to frame. */
5108 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5109 {
5110 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5111
5112 /* Last fragment: Transmit and reset the packet storage counter. */
5113 if (pDesc->legacy.cmd.fEOP)
5114 {
5115 if (pDesc->legacy.cmd.fIC)
5116 {
5117 e1kInsertChecksum(pThis,
5118 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5119 pThis->u16TxPktLen,
5120 pDesc->legacy.cmd.u8CSO,
5121 pDesc->legacy.dw3.u8CSS,
5122 0);
5123 }
5124 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5125 pThis->u16TxPktLen = 0;
5126 }
5127 }
5128 /* Last fragment + failure: free the buffer and reset the storage counter. */
5129 else if (pDesc->legacy.cmd.fEOP)
5130 {
5131 e1kXmitFreeBuf(pThis, pThisCC);
5132 pThis->u16TxPktLen = 0;
5133 }
5134 }
5135 e1kDescReport(pDevIns, pThis, pDesc, addr);
5136 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5137 break;
5138
5139 default:
5140 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5141 pThis->szPrf, e1kGetDescType(pDesc)));
5142 break;
5143 }
5144
5145 return rc;
5146}
5147
5148DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5149{
5150 if (pDesc->context.dw2.fTSE)
5151 {
5152 pThis->contextTSE = pDesc->context;
5153 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5154 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5155 {
5156 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5157 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5158 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5159 }
5160 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5161 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5162 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5163 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5164 }
5165 else
5166 {
5167 pThis->contextNormal = pDesc->context;
5168 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5169 }
5170 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5171 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5172 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5173 pDesc->context.ip.u8CSS,
5174 pDesc->context.ip.u8CSO,
5175 pDesc->context.ip.u16CSE,
5176 pDesc->context.tu.u8CSS,
5177 pDesc->context.tu.u8CSO,
5178 pDesc->context.tu.u16CSE));
5179}
5180
5181static bool e1kLocateTxPacket(PE1KSTATE pThis)
5182{
5183 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5184 pThis->szPrf, pThis->cbTxAlloc));
5185 /* Check if we have located the packet already. */
5186 if (pThis->cbTxAlloc)
5187 {
5188 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5189 pThis->szPrf, pThis->cbTxAlloc));
5190 return true;
5191 }
5192
5193 bool fTSE = false;
5194 uint32_t cbPacket = 0;
5195
5196 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5197 {
5198 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5199 switch (e1kGetDescType(pDesc))
5200 {
5201 case E1K_DTYP_CONTEXT:
5202 if (cbPacket == 0)
5203 e1kUpdateTxContext(pThis, pDesc);
5204 else
5205 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5206 pThis->szPrf, cbPacket));
5207 continue;
5208 case E1K_DTYP_LEGACY:
5209 /* Skip invalid descriptors. */
5210 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5211 {
5212 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5213 pThis->szPrf, cbPacket));
5214 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5215 continue;
5216 }
5217 /* Skip empty descriptors. */
5218 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5219 break;
5220 cbPacket += pDesc->legacy.cmd.u16Length;
5221 pThis->fGSO = false;
5222 break;
5223 case E1K_DTYP_DATA:
5224 /* Skip invalid descriptors. */
5225 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5226 {
5227 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5228 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5229 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5230 continue;
5231 }
5232 /* Skip empty descriptors. */
5233 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5234 break;
5235 if (cbPacket == 0)
5236 {
5237 /*
5238 * The first fragment: save IXSM and TXSM options
5239 * as these are only valid in the first fragment.
5240 */
5241 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5242 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5243 fTSE = pDesc->data.cmd.fTSE;
5244 /*
5245 * TSE descriptors have VLE bit properly set in
5246 * the first fragment.
5247 */
5248 if (fTSE)
5249 {
5250 pThis->fVTag = pDesc->data.cmd.fVLE;
5251 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5252 }
5253 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5254 }
5255 cbPacket += pDesc->data.cmd.u20DTALEN;
5256 break;
5257 default:
5258 AssertMsgFailed(("Impossible descriptor type!"));
5259 }
5260 if (pDesc->legacy.cmd.fEOP)
5261 {
5262 /*
5263 * Non-TSE descriptors have VLE bit properly set in
5264 * the last fragment.
5265 */
5266 if (!fTSE)
5267 {
5268 pThis->fVTag = pDesc->data.cmd.fVLE;
5269 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5270 }
5271 /*
5272 * Compute the required buffer size. If we cannot do GSO but still
5273 * have to do segmentation we allocate the first segment only.
5274 */
5275 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5276 cbPacket :
5277 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5278 if (pThis->fVTag)
5279 pThis->cbTxAlloc += 4;
5280 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5281 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5282 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5283 return true;
5284 }
5285 }
5286
5287 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5288 {
5289 /* All descriptors were empty, we need to process them as a dummy packet */
5290 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5291 pThis->szPrf, pThis->cbTxAlloc));
5292 return true;
5293 }
5294 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5295 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5296 return false;
5297}
5298
5299static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5300{
5301 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5302 int rc = VINF_SUCCESS;
5303
5304 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5305 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5306
5307 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5308 {
5309 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5310 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5311 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(E1KTXDESC), TDLEN, TDH, TDT));
5312 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5313 if (RT_FAILURE(rc))
5314 break;
5315 if (++TDH * sizeof(E1KTXDESC) >= TDLEN)
5316 TDH = 0;
5317 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5318 if (uLowThreshold != 0 && e1kGetTxLen(pThis) <= uLowThreshold)
5319 {
5320 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5321 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5322 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5323 }
5324 ++pThis->iTxDCurrent;
5325 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5326 break;
5327 }
5328
5329 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5330 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5331 return rc;
5332}
5333
5334#endif /* E1K_WITH_TXD_CACHE */
5335#ifndef E1K_WITH_TXD_CACHE
5336
5337/**
5338 * Transmit pending descriptors.
5339 *
5340 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5341 *
5342 * @param pDevIns The device instance.
5343 * @param pThis The E1000 state.
5344 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5345 */
5346static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5347{
5348 int rc = VINF_SUCCESS;
5349 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5350
5351 /* Check if transmitter is enabled. */
5352 if (!(TCTL & TCTL_EN))
5353 return VINF_SUCCESS;
5354 /*
5355 * Grab the xmit lock of the driver as well as the E1K device state.
5356 */
5357 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5358 if (RT_LIKELY(rc == VINF_SUCCESS))
5359 {
5360 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5361 if (pDrv)
5362 {
5363 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5364 if (RT_FAILURE(rc))
5365 {
5366 e1kCsTxLeave(pThis);
5367 return rc;
5368 }
5369 }
5370 /*
5371 * Process all pending descriptors.
5372 * Note! Do not process descriptors in locked state
5373 */
5374 while (TDH != TDT && !pThis->fLocked)
5375 {
5376 E1KTXDESC desc;
5377 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5378 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5379
5380 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5381 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5382 /* If we failed to transmit descriptor we will try it again later */
5383 if (RT_FAILURE(rc))
5384 break;
5385 if (++TDH * sizeof(desc) >= TDLEN)
5386 TDH = 0;
5387
5388 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5389 {
5390 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5391 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5392 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5393 }
5394
5395 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5396 }
5397
5398 /// @todo uncomment: pThis->uStatIntTXQE++;
5399 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5400 /*
5401 * Release the lock.
5402 */
5403 if (pDrv)
5404 pDrv->pfnEndXmit(pDrv);
5405 e1kCsTxLeave(pThis);
5406 }
5407
5408 return rc;
5409}
5410
5411#else /* E1K_WITH_TXD_CACHE */
5412
5413static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis)
5414{
5415 unsigned i, cDescs = TDLEN / sizeof(E1KTXDESC);
5416 uint32_t tdh = TDH;
5417 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5418 for (i = 0; i < cDescs; ++i)
5419 {
5420 E1KTXDESC desc;
5421 PDMDevHlpPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5422 if (i == tdh)
5423 LogRel(("E1000: >>> "));
5424 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5425 }
5426 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5427 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5428 if (tdh > pThis->iTxDCurrent)
5429 tdh -= pThis->iTxDCurrent;
5430 else
5431 tdh = cDescs + tdh - pThis->iTxDCurrent;
5432 for (i = 0; i < pThis->nTxDFetched; ++i)
5433 {
5434 if (i == pThis->iTxDCurrent)
5435 LogRel(("E1000: >>> "));
5436 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5437 }
5438}
5439
5440/**
5441 * Transmit pending descriptors.
5442 *
5443 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5444 *
5445 * @param pDevIns The device instance.
5446 * @param pThis The E1000 state.
5447 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5448 */
5449static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5450{
5451 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5452 int rc = VINF_SUCCESS;
5453
5454 /* Check if transmitter is enabled. */
5455 if (!(TCTL & TCTL_EN))
5456 return VINF_SUCCESS;
5457 /*
5458 * Grab the xmit lock of the driver as well as the E1K device state.
5459 */
5460 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5461 if (pDrv)
5462 {
5463 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5464 if (RT_FAILURE(rc))
5465 return rc;
5466 }
5467
5468 /*
5469 * Process all pending descriptors.
5470 * Note! Do not process descriptors in locked state
5471 */
5472 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5473 if (RT_LIKELY(rc == VINF_SUCCESS))
5474 {
5475 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5476 /*
5477 * fIncomplete is set whenever we try to fetch additional descriptors
5478 * for an incomplete packet. If fail to locate a complete packet on
5479 * the next iteration we need to reset the cache or we risk to get
5480 * stuck in this loop forever.
5481 */
5482 bool fIncomplete = false;
5483 while (!pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis))
5484 {
5485 while (e1kLocateTxPacket(pThis))
5486 {
5487 fIncomplete = false;
5488 /* Found a complete packet, allocate it. */
5489 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5490 /* If we're out of bandwidth we'll come back later. */
5491 if (RT_FAILURE(rc))
5492 goto out;
5493 /* Copy the packet to allocated buffer and send it. */
5494 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread);
5495 /* If we're out of bandwidth we'll come back later. */
5496 if (RT_FAILURE(rc))
5497 goto out;
5498 }
5499 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5500 if (RT_UNLIKELY(fIncomplete))
5501 {
5502 static bool fTxDCacheDumped = false;
5503 /*
5504 * The descriptor cache is full, but we were unable to find
5505 * a complete packet in it. Drop the cache and hope that
5506 * the guest driver can recover from network card error.
5507 */
5508 LogRel(("%s: No complete packets in%s TxD cache! "
5509 "Fetched=%d, current=%d, TX len=%d.\n",
5510 pThis->szPrf,
5511 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5512 pThis->nTxDFetched, pThis->iTxDCurrent,
5513 e1kGetTxLen(pThis)));
5514 if (!fTxDCacheDumped)
5515 {
5516 fTxDCacheDumped = true;
5517 e1kDumpTxDCache(pDevIns, pThis);
5518 }
5519 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5520 /*
5521 * Returning an error at this point means Guru in R0
5522 * (see @bugref{6428}).
5523 */
5524# ifdef IN_RING3
5525 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5526# else /* !IN_RING3 */
5527 rc = VINF_IOM_R3_MMIO_WRITE;
5528# endif /* !IN_RING3 */
5529 goto out;
5530 }
5531 if (u8Remain > 0)
5532 {
5533 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5534 "%d more are available\n",
5535 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5536 e1kGetTxLen(pThis) - u8Remain));
5537
5538 /*
5539 * A packet was partially fetched. Move incomplete packet to
5540 * the beginning of cache buffer, then load more descriptors.
5541 */
5542 memmove(pThis->aTxDescriptors,
5543 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5544 u8Remain * sizeof(E1KTXDESC));
5545 pThis->iTxDCurrent = 0;
5546 pThis->nTxDFetched = u8Remain;
5547 e1kTxDLoadMore(pDevIns, pThis);
5548 fIncomplete = true;
5549 }
5550 else
5551 pThis->nTxDFetched = 0;
5552 pThis->iTxDCurrent = 0;
5553 }
5554 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5555 {
5556 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5557 pThis->szPrf));
5558 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5559 }
5560out:
5561 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5562
5563 /// @todo uncomment: pThis->uStatIntTXQE++;
5564 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5565
5566 e1kCsTxLeave(pThis);
5567 }
5568
5569
5570 /*
5571 * Release the lock.
5572 */
5573 if (pDrv)
5574 pDrv->pfnEndXmit(pDrv);
5575 return rc;
5576}
5577
5578#endif /* E1K_WITH_TXD_CACHE */
5579#ifdef IN_RING3
5580
5581/**
5582 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5583 */
5584static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5585{
5586 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5587 PE1KSTATE pThis = pThisCC->pShared;
5588 /* Resume suspended transmission */
5589 STATUS &= ~STATUS_TXOFF;
5590 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5591}
5592
5593/**
5594 * @callback_method_impl{FNPDMTASKDEV,
5595 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5596 * @note Not executed on EMT.
5597 */
5598static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5599{
5600 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5601 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5602
5603 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5604 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5605
5606 RT_NOREF(rc, pvUser);
5607}
5608
5609#endif /* IN_RING3 */
5610
5611/**
5612 * Write handler for Transmit Descriptor Tail register.
5613 *
5614 * @param pThis The device state structure.
5615 * @param offset Register offset in memory-mapped frame.
5616 * @param index Register index in register array.
5617 * @param value The value to store.
5618 * @param mask Used to implement partial writes (8 and 16-bit).
5619 * @thread EMT
5620 */
5621static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5622{
5623 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5624
5625 /* All descriptors starting with head and not including tail belong to us. */
5626 /* Process them. */
5627 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5628 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5629
5630 /* Ignore TDT writes when the link is down. */
5631 if (TDH != TDT && (STATUS & STATUS_LU))
5632 {
5633 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", TDH, TDT, e1kGetTxLen(pThis)));
5634 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5635 pThis->szPrf, e1kGetTxLen(pThis)));
5636
5637 /* Transmit pending packets if possible, defer it if we cannot do it
5638 in the current context. */
5639#ifdef E1K_TX_DELAY
5640 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5641 if (RT_LIKELY(rc == VINF_SUCCESS))
5642 {
5643 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5644 {
5645# ifdef E1K_INT_STATS
5646 pThis->u64ArmedAt = RTTimeNanoTS();
5647# endif
5648 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5649 }
5650 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5651 e1kCsTxLeave(pThis);
5652 return rc;
5653 }
5654 /* We failed to enter the TX critical section -- transmit as usual. */
5655#endif /* E1K_TX_DELAY */
5656#ifndef IN_RING3
5657 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5658 if (!pThisCC->CTX_SUFF(pDrv))
5659 {
5660 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5661 rc = VINF_SUCCESS;
5662 }
5663 else
5664#endif
5665 {
5666 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5667 if (rc == VERR_TRY_AGAIN)
5668 rc = VINF_SUCCESS;
5669#ifndef IN_RING3
5670 else if (rc == VERR_SEM_BUSY)
5671 rc = VINF_IOM_R3_MMIO_WRITE;
5672#endif
5673 AssertRC(rc);
5674 }
5675 }
5676
5677 return rc;
5678}
5679
5680/**
5681 * Write handler for Multicast Table Array registers.
5682 *
5683 * @param pThis The device state structure.
5684 * @param offset Register offset in memory-mapped frame.
5685 * @param index Register index in register array.
5686 * @param value The value to store.
5687 * @thread EMT
5688 */
5689static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5690{
5691 RT_NOREF_PV(pDevIns);
5692 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5693 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5694
5695 return VINF_SUCCESS;
5696}
5697
5698/**
5699 * Read handler for Multicast Table Array registers.
5700 *
5701 * @returns VBox status code.
5702 *
5703 * @param pThis The device state structure.
5704 * @param offset Register offset in memory-mapped frame.
5705 * @param index Register index in register array.
5706 * @thread EMT
5707 */
5708static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5709{
5710 RT_NOREF_PV(pDevIns);
5711 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5712 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5713
5714 return VINF_SUCCESS;
5715}
5716
5717/**
5718 * Write handler for Receive Address registers.
5719 *
5720 * @param pThis The device state structure.
5721 * @param offset Register offset in memory-mapped frame.
5722 * @param index Register index in register array.
5723 * @param value The value to store.
5724 * @thread EMT
5725 */
5726static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5727{
5728 RT_NOREF_PV(pDevIns);
5729 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5730 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5731
5732 return VINF_SUCCESS;
5733}
5734
5735/**
5736 * Read handler for Receive Address registers.
5737 *
5738 * @returns VBox status code.
5739 *
5740 * @param pThis The device state structure.
5741 * @param offset Register offset in memory-mapped frame.
5742 * @param index Register index in register array.
5743 * @thread EMT
5744 */
5745static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5746{
5747 RT_NOREF_PV(pDevIns);
5748 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5749 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5750
5751 return VINF_SUCCESS;
5752}
5753
5754/**
5755 * Write handler for VLAN Filter Table Array registers.
5756 *
5757 * @param pThis The device state structure.
5758 * @param offset Register offset in memory-mapped frame.
5759 * @param index Register index in register array.
5760 * @param value The value to store.
5761 * @thread EMT
5762 */
5763static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5764{
5765 RT_NOREF_PV(pDevIns);
5766 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5767 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5768
5769 return VINF_SUCCESS;
5770}
5771
5772/**
5773 * Read handler for VLAN Filter Table Array registers.
5774 *
5775 * @returns VBox status code.
5776 *
5777 * @param pThis The device state structure.
5778 * @param offset Register offset in memory-mapped frame.
5779 * @param index Register index in register array.
5780 * @thread EMT
5781 */
5782static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5783{
5784 RT_NOREF_PV(pDevIns);
5785 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5786 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5787
5788 return VINF_SUCCESS;
5789}
5790
5791/**
5792 * Read handler for unimplemented registers.
5793 *
5794 * Merely reports reads from unimplemented registers.
5795 *
5796 * @returns VBox status code.
5797 *
5798 * @param pThis The device state structure.
5799 * @param offset Register offset in memory-mapped frame.
5800 * @param index Register index in register array.
5801 * @thread EMT
5802 */
5803static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5804{
5805 RT_NOREF(pDevIns, pThis, offset, index);
5806 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5807 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5808 *pu32Value = 0;
5809
5810 return VINF_SUCCESS;
5811}
5812
5813/**
5814 * Default register read handler with automatic clear operation.
5815 *
5816 * Retrieves the value of register from register array in device state structure.
5817 * Then resets all bits.
5818 *
5819 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5820 * done in the caller.
5821 *
5822 * @returns VBox status code.
5823 *
5824 * @param pThis The device state structure.
5825 * @param offset Register offset in memory-mapped frame.
5826 * @param index Register index in register array.
5827 * @thread EMT
5828 */
5829static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5830{
5831 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5832 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
5833 pThis->auRegs[index] = 0;
5834
5835 return rc;
5836}
5837
5838/**
5839 * Default register read handler.
5840 *
5841 * Retrieves the value of register from register array in device state structure.
5842 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5843 *
5844 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5845 * done in the caller.
5846 *
5847 * @returns VBox status code.
5848 *
5849 * @param pThis The device state structure.
5850 * @param offset Register offset in memory-mapped frame.
5851 * @param index Register index in register array.
5852 * @thread EMT
5853 */
5854static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5855{
5856 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
5857
5858 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5859 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5860
5861 return VINF_SUCCESS;
5862}
5863
5864/**
5865 * Write handler for unimplemented registers.
5866 *
5867 * Merely reports writes to unimplemented registers.
5868 *
5869 * @param pThis The device state structure.
5870 * @param offset Register offset in memory-mapped frame.
5871 * @param index Register index in register array.
5872 * @param value The value to store.
5873 * @thread EMT
5874 */
5875
5876 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5877{
5878 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
5879
5880 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
5881 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5882
5883 return VINF_SUCCESS;
5884}
5885
5886/**
5887 * Default register write handler.
5888 *
5889 * Stores the value to the register array in device state structure. Only bits
5890 * corresponding to 1s both in 'writable' and 'mask' will be stored.
5891 *
5892 * @returns VBox status code.
5893 *
5894 * @param pThis The device state structure.
5895 * @param offset Register offset in memory-mapped frame.
5896 * @param index Register index in register array.
5897 * @param value The value to store.
5898 * @param mask Used to implement partial writes (8 and 16-bit).
5899 * @thread EMT
5900 */
5901
5902static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5903{
5904 RT_NOREF(pDevIns, offset);
5905
5906 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5907 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
5908 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
5909
5910 return VINF_SUCCESS;
5911}
5912
5913/**
5914 * Search register table for matching register.
5915 *
5916 * @returns Index in the register table or -1 if not found.
5917 *
5918 * @param offReg Register offset in memory-mapped region.
5919 * @thread EMT
5920 */
5921static int e1kRegLookup(uint32_t offReg)
5922{
5923
5924#if 0
5925 int index;
5926
5927 for (index = 0; index < E1K_NUM_OF_REGS; index++)
5928 {
5929 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
5930 {
5931 return index;
5932 }
5933 }
5934#else
5935 int iStart = 0;
5936 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
5937 for (;;)
5938 {
5939 int i = (iEnd - iStart) / 2 + iStart;
5940 uint32_t offCur = g_aE1kRegMap[i].offset;
5941 if (offReg < offCur)
5942 {
5943 if (i == iStart)
5944 break;
5945 iEnd = i;
5946 }
5947 else if (offReg >= offCur + g_aE1kRegMap[i].size)
5948 {
5949 i++;
5950 if (i == iEnd)
5951 break;
5952 iStart = i;
5953 }
5954 else
5955 return i;
5956 Assert(iEnd > iStart);
5957 }
5958
5959 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5960 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
5961 return (int)i;
5962
5963# ifdef VBOX_STRICT
5964 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
5965 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
5966# endif
5967
5968#endif
5969
5970 return -1;
5971}
5972
5973/**
5974 * Handle unaligned register read operation.
5975 *
5976 * Looks up and calls appropriate handler.
5977 *
5978 * @returns VBox status code.
5979 *
5980 * @param pDevIns The device instance.
5981 * @param pThis The device state structure.
5982 * @param offReg Register offset in memory-mapped frame.
5983 * @param pv Where to store the result.
5984 * @param cb Number of bytes to read.
5985 * @thread EMT
5986 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
5987 * accesses we have to take care of that ourselves.
5988 */
5989static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
5990{
5991 uint32_t u32 = 0;
5992 uint32_t shift;
5993 int rc = VINF_SUCCESS;
5994 int index = e1kRegLookup(offReg);
5995#ifdef LOG_ENABLED
5996 char buf[9];
5997#endif
5998
5999 /*
6000 * From the spec:
6001 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6002 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6003 */
6004
6005 /*
6006 * To be able to read bytes and short word we convert them to properly
6007 * shifted 32-bit words and masks. The idea is to keep register-specific
6008 * handlers simple. Most accesses will be 32-bit anyway.
6009 */
6010 uint32_t mask;
6011 switch (cb)
6012 {
6013 case 4: mask = 0xFFFFFFFF; break;
6014 case 2: mask = 0x0000FFFF; break;
6015 case 1: mask = 0x000000FF; break;
6016 default:
6017 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6018 }
6019 if (index >= 0)
6020 {
6021 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6022 if (g_aE1kRegMap[index].readable)
6023 {
6024 /* Make the mask correspond to the bits we are about to read. */
6025 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6026 mask <<= shift;
6027 if (!mask)
6028 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6029 /*
6030 * Read it. Pass the mask so the handler knows what has to be read.
6031 * Mask out irrelevant bits.
6032 */
6033 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6034 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6035 return rc;
6036 //pThis->fDelayInts = false;
6037 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6038 //pThis->iStatIntLostOne = 0;
6039 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6040 u32 &= mask;
6041 //e1kCsLeave(pThis);
6042 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6043 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6044 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6045 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6046 /* Shift back the result. */
6047 u32 >>= shift;
6048 }
6049 else
6050 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6051 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6052 if (IOM_SUCCESS(rc))
6053 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6054 }
6055 else
6056 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6057 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6058
6059 memcpy(pv, &u32, cb);
6060 return rc;
6061}
6062
6063/**
6064 * Handle 4 byte aligned and sized read operation.
6065 *
6066 * Looks up and calls appropriate handler.
6067 *
6068 * @returns VBox status code.
6069 *
6070 * @param pDevIns The device instance.
6071 * @param pThis The device state structure.
6072 * @param offReg Register offset in memory-mapped frame.
6073 * @param pu32 Where to store the result.
6074 * @thread EMT
6075 */
6076static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6077{
6078 Assert(!(offReg & 3));
6079
6080 /*
6081 * Lookup the register and check that it's readable.
6082 */
6083 VBOXSTRICTRC rc = VINF_SUCCESS;
6084 int idxReg = e1kRegLookup(offReg);
6085 if (RT_LIKELY(idxReg >= 0))
6086 {
6087 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6088 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6089 {
6090 /*
6091 * Read it. Pass the mask so the handler knows what has to be read.
6092 * Mask out irrelevant bits.
6093 */
6094 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6095 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6096 // return rc;
6097 //pThis->fDelayInts = false;
6098 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6099 //pThis->iStatIntLostOne = 0;
6100 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6101 //e1kCsLeave(pThis);
6102 Log6(("%s At %08X read %08X from %s (%s)\n",
6103 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6104 if (IOM_SUCCESS(rc))
6105 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6106 }
6107 else
6108 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6109 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6110 }
6111 else
6112 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6113 return rc;
6114}
6115
6116/**
6117 * Handle 4 byte sized and aligned register write operation.
6118 *
6119 * Looks up and calls appropriate handler.
6120 *
6121 * @returns VBox status code.
6122 *
6123 * @param pDevIns The device instance.
6124 * @param pThis The device state structure.
6125 * @param offReg Register offset in memory-mapped frame.
6126 * @param u32Value The value to write.
6127 * @thread EMT
6128 */
6129static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6130{
6131 VBOXSTRICTRC rc = VINF_SUCCESS;
6132 int index = e1kRegLookup(offReg);
6133 if (RT_LIKELY(index >= 0))
6134 {
6135 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6136 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6137 {
6138 /*
6139 * Write it. Pass the mask so the handler knows what has to be written.
6140 * Mask out irrelevant bits.
6141 */
6142 Log6(("%s At %08X write %08X to %s (%s)\n",
6143 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6144 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6145 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6146 // return rc;
6147 //pThis->fDelayInts = false;
6148 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6149 //pThis->iStatIntLostOne = 0;
6150 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6151 //e1kCsLeave(pThis);
6152 }
6153 else
6154 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6155 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6156 if (IOM_SUCCESS(rc))
6157 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6158 }
6159 else
6160 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6161 pThis->szPrf, offReg, u32Value));
6162 return rc;
6163}
6164
6165
6166/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6167
6168/**
6169 * @callback_method_impl{FNIOMMMIONEWREAD}
6170 */
6171static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6172{
6173 RT_NOREF2(pvUser, cb);
6174 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6175 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6176
6177 Assert(off < E1K_MM_SIZE);
6178 Assert(cb == 4);
6179 Assert(!(off & 3));
6180
6181 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6182
6183 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6184 return rcStrict;
6185}
6186
6187/**
6188 * @callback_method_impl{FNIOMMMIONEWWRITE}
6189 */
6190static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6191{
6192 RT_NOREF2(pvUser, cb);
6193 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6194 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6195
6196 Assert(off < E1K_MM_SIZE);
6197 Assert(cb == 4);
6198 Assert(!(off & 3));
6199
6200 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6201
6202 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6203 return rcStrict;
6204}
6205
6206/**
6207 * @callback_method_impl{FNIOMIOPORTNEWIN}
6208 */
6209static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6210{
6211 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6212 VBOXSTRICTRC rc;
6213 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6214 RT_NOREF_PV(pvUser);
6215
6216 if (RT_LIKELY(cb == 4))
6217 switch (offPort)
6218 {
6219 case 0x00: /* IOADDR */
6220 *pu32 = pThis->uSelectedReg;
6221 E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6222 rc = VINF_SUCCESS;
6223 break;
6224
6225 case 0x04: /* IODATA */
6226 if (!(pThis->uSelectedReg & 3))
6227 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6228 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6229 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6230 if (rc == VINF_IOM_R3_MMIO_READ)
6231 rc = VINF_IOM_R3_IOPORT_READ;
6232 E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6233 break;
6234
6235 default:
6236 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6237 /** @todo r=bird: Check what real hardware returns here. */
6238 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6239 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6240 break;
6241 }
6242 else
6243 {
6244 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6245 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6246 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6247 }
6248 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6249 return rc;
6250}
6251
6252
6253/**
6254 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6255 */
6256static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6257{
6258 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6259 VBOXSTRICTRC rc;
6260 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6261 RT_NOREF_PV(pvUser);
6262
6263 E1kLog2(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6264 if (RT_LIKELY(cb == 4))
6265 {
6266 switch (offPort)
6267 {
6268 case 0x00: /* IOADDR */
6269 pThis->uSelectedReg = u32;
6270 E1kLog2(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6271 rc = VINF_SUCCESS;
6272 break;
6273
6274 case 0x04: /* IODATA */
6275 E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6276 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6277 {
6278 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6279 if (rc == VINF_IOM_R3_MMIO_WRITE)
6280 rc = VINF_IOM_R3_IOPORT_WRITE;
6281 }
6282 else
6283 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6284 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6285 break;
6286
6287 default:
6288 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6289 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6290 }
6291 }
6292 else
6293 {
6294 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6295 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6296 }
6297
6298 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6299 return rc;
6300}
6301
6302#ifdef IN_RING3
6303
6304/**
6305 * Dump complete device state to log.
6306 *
6307 * @param pThis Pointer to device state.
6308 */
6309static void e1kDumpState(PE1KSTATE pThis)
6310{
6311 RT_NOREF(pThis);
6312 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6313 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6314# ifdef E1K_INT_STATS
6315 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6316 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6317 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6318 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6319 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6320 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6321 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6322 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6323 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6324 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6325 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6326 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6327 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6328 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6329 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6330 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6331 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6332 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6333 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6334 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6335 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6336 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6337 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6338 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6339 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6340 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6341 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6342 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6343 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6344 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6345 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6346 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6347 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6348 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6349 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6350 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6351 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6352 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6353 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6354# endif /* E1K_INT_STATS */
6355}
6356
6357
6358/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6359
6360/**
6361 * Check if the device can receive data now.
6362 * This must be called before the pfnRecieve() method is called.
6363 *
6364 * @returns Number of bytes the device can receive.
6365 * @param pDevIns The device instance.
6366 * @param pThis The instance data.
6367 * @thread EMT
6368 */
6369static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6370{
6371#ifndef E1K_WITH_RXD_CACHE
6372 size_t cb;
6373
6374 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6375 return VERR_NET_NO_BUFFER_SPACE;
6376
6377 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6378 {
6379 E1KRXDESC desc;
6380 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6381 if (desc.status.fDD)
6382 cb = 0;
6383 else
6384 cb = pThis->u16RxBSize;
6385 }
6386 else if (RDH < RDT)
6387 cb = (RDT - RDH) * pThis->u16RxBSize;
6388 else if (RDH > RDT)
6389 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6390 else
6391 {
6392 cb = 0;
6393 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6394 }
6395 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6396 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6397
6398 e1kCsRxLeave(pThis);
6399 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6400#else /* E1K_WITH_RXD_CACHE */
6401 int rc = VINF_SUCCESS;
6402
6403 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6404 return VERR_NET_NO_BUFFER_SPACE;
6405
6406 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6407 {
6408 E1KRXDESC desc;
6409 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6410 if (desc.status.fDD)
6411 rc = VERR_NET_NO_BUFFER_SPACE;
6412 }
6413 else if (e1kRxDIsCacheEmpty(pThis) && RDH == RDT)
6414 {
6415 /* Cache is empty, so is the RX ring. */
6416 rc = VERR_NET_NO_BUFFER_SPACE;
6417 }
6418 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6419 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6420 e1kRxDInCache(pThis), RDH, RDT, RDLEN, pThis->u16RxBSize, rc));
6421
6422 e1kCsRxLeave(pThis);
6423 return rc;
6424#endif /* E1K_WITH_RXD_CACHE */
6425}
6426
6427/**
6428 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6429 */
6430static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6431{
6432 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6433 PE1KSTATE pThis = pThisCC->pShared;
6434 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6435
6436 int rc = e1kCanReceive(pDevIns, pThis);
6437
6438 if (RT_SUCCESS(rc))
6439 return VINF_SUCCESS;
6440 if (RT_UNLIKELY(cMillies == 0))
6441 return VERR_NET_NO_BUFFER_SPACE;
6442
6443 rc = VERR_INTERRUPTED;
6444 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6445 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6446 VMSTATE enmVMState;
6447 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6448 || enmVMState == VMSTATE_RUNNING_LS))
6449 {
6450 int rc2 = e1kCanReceive(pDevIns, pThis);
6451 if (RT_SUCCESS(rc2))
6452 {
6453 rc = VINF_SUCCESS;
6454 break;
6455 }
6456 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6457 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6458 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6459 }
6460 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6461 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6462
6463 return rc;
6464}
6465
6466
6467/**
6468 * Matches the packet addresses against Receive Address table. Looks for
6469 * exact matches only.
6470 *
6471 * @returns true if address matches.
6472 * @param pThis Pointer to the state structure.
6473 * @param pvBuf The ethernet packet.
6474 * @param cb Number of bytes available in the packet.
6475 * @thread EMT
6476 */
6477static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6478{
6479 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6480 {
6481 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6482
6483 /* Valid address? */
6484 if (ra->ctl & RA_CTL_AV)
6485 {
6486 Assert((ra->ctl & RA_CTL_AS) < 2);
6487 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6488 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6489 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6490 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6491 /*
6492 * Address Select:
6493 * 00b = Destination address
6494 * 01b = Source address
6495 * 10b = Reserved
6496 * 11b = Reserved
6497 * Since ethernet header is (DA, SA, len) we can use address
6498 * select as index.
6499 */
6500 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6501 ra->addr, sizeof(ra->addr)) == 0)
6502 return true;
6503 }
6504 }
6505
6506 return false;
6507}
6508
6509/**
6510 * Matches the packet addresses against Multicast Table Array.
6511 *
6512 * @remarks This is imperfect match since it matches not exact address but
6513 * a subset of addresses.
6514 *
6515 * @returns true if address matches.
6516 * @param pThis Pointer to the state structure.
6517 * @param pvBuf The ethernet packet.
6518 * @param cb Number of bytes available in the packet.
6519 * @thread EMT
6520 */
6521static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6522{
6523 /* Get bits 32..47 of destination address */
6524 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6525
6526 unsigned offset = GET_BITS(RCTL, MO);
6527 /*
6528 * offset means:
6529 * 00b = bits 36..47
6530 * 01b = bits 35..46
6531 * 10b = bits 34..45
6532 * 11b = bits 32..43
6533 */
6534 if (offset < 3)
6535 u16Bit = u16Bit >> (4 - offset);
6536 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6537}
6538
6539/**
6540 * Determines if the packet is to be delivered to upper layer.
6541 *
6542 * The following filters supported:
6543 * - Exact Unicast/Multicast
6544 * - Promiscuous Unicast/Multicast
6545 * - Multicast
6546 * - VLAN
6547 *
6548 * @returns true if packet is intended for this node.
6549 * @param pThis Pointer to the state structure.
6550 * @param pvBuf The ethernet packet.
6551 * @param cb Number of bytes available in the packet.
6552 * @param pStatus Bit field to store status bits.
6553 * @thread EMT
6554 */
6555static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6556{
6557 Assert(cb > 14);
6558 /* Assume that we fail to pass exact filter. */
6559 pStatus->fPIF = false;
6560 pStatus->fVP = false;
6561 /* Discard oversized packets */
6562 if (cb > E1K_MAX_RX_PKT_SIZE)
6563 {
6564 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6565 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6566 E1K_INC_CNT32(ROC);
6567 return false;
6568 }
6569 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6570 {
6571 /* When long packet reception is disabled packets over 1522 are discarded */
6572 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6573 pThis->szPrf, cb));
6574 E1K_INC_CNT32(ROC);
6575 return false;
6576 }
6577
6578 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6579 /* Compare TPID with VLAN Ether Type */
6580 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6581 {
6582 pStatus->fVP = true;
6583 /* Is VLAN filtering enabled? */
6584 if (RCTL & RCTL_VFE)
6585 {
6586 /* It is 802.1q packet indeed, let's filter by VID */
6587 if (RCTL & RCTL_CFIEN)
6588 {
6589 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6590 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6591 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6592 !!(RCTL & RCTL_CFI)));
6593 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6594 {
6595 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6596 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6597 return false;
6598 }
6599 }
6600 else
6601 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6602 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6603 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6604 {
6605 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6606 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6607 return false;
6608 }
6609 }
6610 }
6611 /* Broadcast filtering */
6612 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6613 return true;
6614 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6615 if (e1kIsMulticast(pvBuf))
6616 {
6617 /* Is multicast promiscuous enabled? */
6618 if (RCTL & RCTL_MPE)
6619 return true;
6620 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6621 /* Try perfect matches first */
6622 if (e1kPerfectMatch(pThis, pvBuf))
6623 {
6624 pStatus->fPIF = true;
6625 return true;
6626 }
6627 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6628 if (e1kImperfectMatch(pThis, pvBuf))
6629 return true;
6630 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6631 }
6632 else {
6633 /* Is unicast promiscuous enabled? */
6634 if (RCTL & RCTL_UPE)
6635 return true;
6636 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6637 if (e1kPerfectMatch(pThis, pvBuf))
6638 {
6639 pStatus->fPIF = true;
6640 return true;
6641 }
6642 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6643 }
6644 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6645 return false;
6646}
6647
6648/**
6649 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6650 */
6651static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6652{
6653 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6654 PE1KSTATE pThis = pThisCC->pShared;
6655 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6656 int rc = VINF_SUCCESS;
6657
6658 /*
6659 * Drop packets if the VM is not running yet/anymore.
6660 */
6661 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6662 if ( enmVMState != VMSTATE_RUNNING
6663 && enmVMState != VMSTATE_RUNNING_LS)
6664 {
6665 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6666 return VINF_SUCCESS;
6667 }
6668
6669 /* Discard incoming packets in locked state */
6670 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6671 {
6672 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6673 return VINF_SUCCESS;
6674 }
6675
6676 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6677
6678 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6679 // return VERR_PERMISSION_DENIED;
6680
6681 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6682
6683 /* Update stats */
6684 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6685 {
6686 E1K_INC_CNT32(TPR);
6687 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6688 e1kCsLeave(pThis);
6689 }
6690 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6691 E1KRXDST status;
6692 RT_ZERO(status);
6693 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6694 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6695 if (fPassed)
6696 {
6697 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6698 }
6699 //e1kCsLeave(pThis);
6700 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6701
6702 return rc;
6703}
6704
6705
6706/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6707
6708/**
6709 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6710 */
6711static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6712{
6713 if (iLUN == 0)
6714 {
6715 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6716 *ppLed = &pThisCC->pShared->led;
6717 return VINF_SUCCESS;
6718 }
6719 return VERR_PDM_LUN_NOT_FOUND;
6720}
6721
6722
6723/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6724
6725/**
6726 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6727 */
6728static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6729{
6730 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6731 pThisCC->eeprom.getMac(pMac);
6732 return VINF_SUCCESS;
6733}
6734
6735/**
6736 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6737 */
6738static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6739{
6740 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6741 PE1KSTATE pThis = pThisCC->pShared;
6742 if (STATUS & STATUS_LU)
6743 return PDMNETWORKLINKSTATE_UP;
6744 return PDMNETWORKLINKSTATE_DOWN;
6745}
6746
6747/**
6748 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6749 */
6750static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6751{
6752 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6753 PE1KSTATE pThis = pThisCC->pShared;
6754 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6755
6756 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6757 switch (enmState)
6758 {
6759 case PDMNETWORKLINKSTATE_UP:
6760 pThis->fCableConnected = true;
6761 /* If link was down, bring it up after a while. */
6762 if (!(STATUS & STATUS_LU))
6763 e1kBringLinkUpDelayed(pDevIns, pThis);
6764 break;
6765 case PDMNETWORKLINKSTATE_DOWN:
6766 pThis->fCableConnected = false;
6767 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6768 * We might have to set the link state before the driver initializes us. */
6769 Phy::setLinkStatus(&pThis->phy, false);
6770 /* If link was up, bring it down. */
6771 if (STATUS & STATUS_LU)
6772 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6773 break;
6774 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6775 /*
6776 * There is not much sense in bringing down the link if it has not come up yet.
6777 * If it is up though, we bring it down temporarely, then bring it up again.
6778 */
6779 if (STATUS & STATUS_LU)
6780 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6781 break;
6782 default:
6783 ;
6784 }
6785 return VINF_SUCCESS;
6786}
6787
6788
6789/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6790
6791/**
6792 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6793 */
6794static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6795{
6796 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6797 Assert(&pThisCC->IBase == pInterface);
6798
6799 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6800 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6801 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6802 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6803 return NULL;
6804}
6805
6806
6807/* -=-=-=-=- Saved State -=-=-=-=- */
6808
6809/**
6810 * Saves the configuration.
6811 *
6812 * @param pThis The E1K state.
6813 * @param pSSM The handle to the saved state.
6814 */
6815static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
6816{
6817 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6818 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
6819}
6820
6821/**
6822 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6823 */
6824static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6825{
6826 RT_NOREF(uPass);
6827 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
6828 return VINF_SSM_DONT_CALL_AGAIN;
6829}
6830
6831/**
6832 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6833 */
6834static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6835{
6836 RT_NOREF(pSSM);
6837 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6838
6839 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6840 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6841 return rc;
6842 e1kCsLeave(pThis);
6843 return VINF_SUCCESS;
6844#if 0
6845 /* 1) Prevent all threads from modifying the state and memory */
6846 //pThis->fLocked = true;
6847 /* 2) Cancel all timers */
6848#ifdef E1K_TX_DELAY
6849 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6850#endif /* E1K_TX_DELAY */
6851//#ifdef E1K_USE_TX_TIMERS
6852 if (pThis->fTidEnabled)
6853 {
6854 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6855#ifndef E1K_NO_TAD
6856 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6857#endif /* E1K_NO_TAD */
6858 }
6859//#endif /* E1K_USE_TX_TIMERS */
6860#ifdef E1K_USE_RX_TIMERS
6861 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6862 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6863#endif /* E1K_USE_RX_TIMERS */
6864 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6865 /* 3) Did I forget anything? */
6866 E1kLog(("%s Locked\n", pThis->szPrf));
6867 return VINF_SUCCESS;
6868#endif
6869}
6870
6871/**
6872 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6873 */
6874static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6875{
6876 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6877 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6878 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6879
6880 e1kSaveConfig(pHlp, pThis, pSSM);
6881 pThisCC->eeprom.save(pHlp, pSSM);
6882 e1kDumpState(pThis);
6883 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
6884 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
6885 Phy::saveState(pHlp, pSSM, &pThis->phy);
6886 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
6887 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
6888 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
6889 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
6890 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
6891 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
6892 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
6893 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
6894 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
6895/** @todo State wrt to the TSE buffer is incomplete, so little point in
6896 * saving this actually. */
6897 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
6898 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
6899 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
6900 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
6901 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
6902 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
6903 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
6904#ifdef E1K_WITH_TXD_CACHE
6905# if 0
6906 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
6907 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
6908 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
6909# else
6910 /*
6911 * There is no point in storing TX descriptor cache entries as we can simply
6912 * fetch them again. Moreover, normally the cache is always empty when we
6913 * save the state. Store zero entries for compatibility.
6914 */
6915 pHlp->pfnSSMPutU8(pSSM, 0);
6916# endif
6917#endif /* E1K_WITH_TXD_CACHE */
6918/** @todo GSO requires some more state here. */
6919 E1kLog(("%s State has been saved\n", pThis->szPrf));
6920 return VINF_SUCCESS;
6921}
6922
6923#if 0
6924/**
6925 * @callback_method_impl{FNSSMDEVSAVEDONE}
6926 */
6927static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6928{
6929 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6930
6931 /* If VM is being powered off unlocking will result in assertions in PGM */
6932 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
6933 pThis->fLocked = false;
6934 else
6935 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
6936 E1kLog(("%s Unlocked\n", pThis->szPrf));
6937 return VINF_SUCCESS;
6938}
6939#endif
6940
6941/**
6942 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
6943 */
6944static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6945{
6946 RT_NOREF(pSSM);
6947 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6948
6949 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6950 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6951 return rc;
6952 e1kCsLeave(pThis);
6953 return VINF_SUCCESS;
6954}
6955
6956/**
6957 * @callback_method_impl{FNSSMDEVLOADEXEC}
6958 */
6959static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6960{
6961 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6962 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
6963 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6964 int rc;
6965
6966 if ( uVersion != E1K_SAVEDSTATE_VERSION
6967#ifdef E1K_WITH_TXD_CACHE
6968 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
6969#endif /* E1K_WITH_TXD_CACHE */
6970 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
6971 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
6972 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6973
6974 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
6975 || uPass != SSM_PASS_FINAL)
6976 {
6977 /* config checks */
6978 RTMAC macConfigured;
6979 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
6980 AssertRCReturn(rc, rc);
6981 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
6982 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
6983 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
6984
6985 E1KCHIP eChip;
6986 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
6987 AssertRCReturn(rc, rc);
6988 if (eChip != pThis->eChip)
6989 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
6990 }
6991
6992 if (uPass == SSM_PASS_FINAL)
6993 {
6994 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
6995 {
6996 rc = pThisCC->eeprom.load(pHlp, pSSM);
6997 AssertRCReturn(rc, rc);
6998 }
6999 /* the state */
7000 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7001 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7002 /** @todo PHY could be made a separate device with its own versioning */
7003 Phy::loadState(pHlp, pSSM, &pThis->phy);
7004 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7005 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7006 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7007 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7008 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7009 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7010 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7011 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7012 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7013 AssertRCReturn(rc, rc);
7014 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7015 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7016 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7017 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7018 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7019 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7020 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7021 AssertRCReturn(rc, rc);
7022 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7023 {
7024 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7025 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7026 AssertRCReturn(rc, rc);
7027 }
7028 else
7029 {
7030 pThis->fVTag = false;
7031 pThis->u16VTagTCI = 0;
7032 }
7033#ifdef E1K_WITH_TXD_CACHE
7034 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7035 {
7036 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7037 AssertRCReturn(rc, rc);
7038 if (pThis->nTxDFetched)
7039 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7040 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7041 }
7042 else
7043 pThis->nTxDFetched = 0;
7044 /**
7045 * @todo Perhaps we should not store TXD cache as the entries can be
7046 * simply fetched again from guest's memory. Or can't they?
7047 */
7048#endif /* E1K_WITH_TXD_CACHE */
7049#ifdef E1K_WITH_RXD_CACHE
7050 /*
7051 * There is no point in storing the RX descriptor cache in the saved
7052 * state, we just need to make sure it is empty.
7053 */
7054 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7055#endif /* E1K_WITH_RXD_CACHE */
7056 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7057 AssertRCReturn(rc, rc);
7058
7059 /* derived state */
7060 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7061
7062 E1kLog(("%s State has been restored\n", pThis->szPrf));
7063 e1kDumpState(pThis);
7064 }
7065 return VINF_SUCCESS;
7066}
7067
7068/**
7069 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7070 */
7071static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7072{
7073 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7074 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7075 RT_NOREF(pSSM);
7076
7077 /* Update promiscuous mode */
7078 if (pThisCC->pDrvR3)
7079 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7080
7081 /*
7082 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7083 * passed to us. We go through all this stuff if the link was up and we
7084 * wasn't teleported.
7085 */
7086 if ( (STATUS & STATUS_LU)
7087 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7088 && pThis->cMsLinkUpDelay)
7089 {
7090 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7091 }
7092 return VINF_SUCCESS;
7093}
7094
7095
7096
7097/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7098
7099/**
7100 * @callback_method_impl{FNRTSTRFORMATTYPE}
7101 */
7102static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7103 void *pvArgOutput,
7104 const char *pszType,
7105 void const *pvValue,
7106 int cchWidth,
7107 int cchPrecision,
7108 unsigned fFlags,
7109 void *pvUser)
7110{
7111 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7112 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7113 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7114 if (!pDesc)
7115 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7116
7117 size_t cbPrintf = 0;
7118 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7119 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7120 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7121 pDesc->status.fPIF ? "PIF" : "pif",
7122 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7123 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7124 pDesc->status.fVP ? "VP" : "vp",
7125 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7126 pDesc->status.fEOP ? "EOP" : "eop",
7127 pDesc->status.fDD ? "DD" : "dd",
7128 pDesc->status.fRXE ? "RXE" : "rxe",
7129 pDesc->status.fIPE ? "IPE" : "ipe",
7130 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7131 pDesc->status.fCE ? "CE" : "ce",
7132 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7133 E1K_SPEC_VLAN(pDesc->status.u16Special),
7134 E1K_SPEC_PRI(pDesc->status.u16Special));
7135 return cbPrintf;
7136}
7137
7138/**
7139 * @callback_method_impl{FNRTSTRFORMATTYPE}
7140 */
7141static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7142 void *pvArgOutput,
7143 const char *pszType,
7144 void const *pvValue,
7145 int cchWidth,
7146 int cchPrecision,
7147 unsigned fFlags,
7148 void *pvUser)
7149{
7150 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7151 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7152 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7153 if (!pDesc)
7154 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7155
7156 size_t cbPrintf = 0;
7157 switch (e1kGetDescType(pDesc))
7158 {
7159 case E1K_DTYP_CONTEXT:
7160 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7161 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7162 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7163 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7164 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7165 pDesc->context.dw2.fIDE ? " IDE":"",
7166 pDesc->context.dw2.fRS ? " RS" :"",
7167 pDesc->context.dw2.fTSE ? " TSE":"",
7168 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7169 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7170 pDesc->context.dw2.u20PAYLEN,
7171 pDesc->context.dw3.u8HDRLEN,
7172 pDesc->context.dw3.u16MSS,
7173 pDesc->context.dw3.fDD?"DD":"");
7174 break;
7175 case E1K_DTYP_DATA:
7176 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7177 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7178 pDesc->data.u64BufAddr,
7179 pDesc->data.cmd.u20DTALEN,
7180 pDesc->data.cmd.fIDE ? " IDE" :"",
7181 pDesc->data.cmd.fVLE ? " VLE" :"",
7182 pDesc->data.cmd.fRPS ? " RPS" :"",
7183 pDesc->data.cmd.fRS ? " RS" :"",
7184 pDesc->data.cmd.fTSE ? " TSE" :"",
7185 pDesc->data.cmd.fIFCS? " IFCS":"",
7186 pDesc->data.cmd.fEOP ? " EOP" :"",
7187 pDesc->data.dw3.fDD ? " DD" :"",
7188 pDesc->data.dw3.fEC ? " EC" :"",
7189 pDesc->data.dw3.fLC ? " LC" :"",
7190 pDesc->data.dw3.fTXSM? " TXSM":"",
7191 pDesc->data.dw3.fIXSM? " IXSM":"",
7192 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7193 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7194 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7195 break;
7196 case E1K_DTYP_LEGACY:
7197 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7198 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7199 pDesc->data.u64BufAddr,
7200 pDesc->legacy.cmd.u16Length,
7201 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7202 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7203 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7204 pDesc->legacy.cmd.fRS ? " RS" :"",
7205 pDesc->legacy.cmd.fIC ? " IC" :"",
7206 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7207 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7208 pDesc->legacy.dw3.fDD ? " DD" :"",
7209 pDesc->legacy.dw3.fEC ? " EC" :"",
7210 pDesc->legacy.dw3.fLC ? " LC" :"",
7211 pDesc->legacy.cmd.u8CSO,
7212 pDesc->legacy.dw3.u8CSS,
7213 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7214 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7215 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7216 break;
7217 default:
7218 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7219 break;
7220 }
7221
7222 return cbPrintf;
7223}
7224
7225/** Initializes debug helpers (logging format types). */
7226static int e1kInitDebugHelpers(void)
7227{
7228 int rc = VINF_SUCCESS;
7229 static bool s_fHelpersRegistered = false;
7230 if (!s_fHelpersRegistered)
7231 {
7232 s_fHelpersRegistered = true;
7233 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7234 AssertRCReturn(rc, rc);
7235 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7236 AssertRCReturn(rc, rc);
7237 }
7238 return rc;
7239}
7240
7241/**
7242 * Status info callback.
7243 *
7244 * @param pDevIns The device instance.
7245 * @param pHlp The output helpers.
7246 * @param pszArgs The arguments.
7247 */
7248static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7249{
7250 RT_NOREF(pszArgs);
7251 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7252 unsigned i;
7253 // bool fRcvRing = false;
7254 // bool fXmtRing = false;
7255
7256 /*
7257 * Parse args.
7258 if (pszArgs)
7259 {
7260 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7261 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7262 }
7263 */
7264
7265 /*
7266 * Show info.
7267 */
7268 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7269 pDevIns->iInstance,
7270 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7271 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7272 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7273 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7274
7275 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7276
7277 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7278 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7279
7280 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7281 {
7282 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7283 if (ra->ctl & RA_CTL_AV)
7284 {
7285 const char *pcszTmp;
7286 switch (ra->ctl & RA_CTL_AS)
7287 {
7288 case 0: pcszTmp = "DST"; break;
7289 case 1: pcszTmp = "SRC"; break;
7290 default: pcszTmp = "reserved";
7291 }
7292 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7293 }
7294 }
7295 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7296 uint32_t rdh = RDH;
7297 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7298 for (i = 0; i < cDescs; ++i)
7299 {
7300 E1KRXDESC desc;
7301 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7302 &desc, sizeof(desc));
7303 if (i == rdh)
7304 pHlp->pfnPrintf(pHlp, ">>> ");
7305 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7306 }
7307#ifdef E1K_WITH_RXD_CACHE
7308 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7309 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7310 if (rdh > pThis->iRxDCurrent)
7311 rdh -= pThis->iRxDCurrent;
7312 else
7313 rdh = cDescs + rdh - pThis->iRxDCurrent;
7314 for (i = 0; i < pThis->nRxDFetched; ++i)
7315 {
7316 if (i == pThis->iRxDCurrent)
7317 pHlp->pfnPrintf(pHlp, ">>> ");
7318 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7319 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7320 &pThis->aRxDescriptors[i]);
7321 }
7322#endif /* E1K_WITH_RXD_CACHE */
7323
7324 cDescs = TDLEN / sizeof(E1KTXDESC);
7325 uint32_t tdh = TDH;
7326 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7327 for (i = 0; i < cDescs; ++i)
7328 {
7329 E1KTXDESC desc;
7330 PDMDevHlpPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7331 &desc, sizeof(desc));
7332 if (i == tdh)
7333 pHlp->pfnPrintf(pHlp, ">>> ");
7334 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7335 }
7336#ifdef E1K_WITH_TXD_CACHE
7337 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7338 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7339 if (tdh > pThis->iTxDCurrent)
7340 tdh -= pThis->iTxDCurrent;
7341 else
7342 tdh = cDescs + tdh - pThis->iTxDCurrent;
7343 for (i = 0; i < pThis->nTxDFetched; ++i)
7344 {
7345 if (i == pThis->iTxDCurrent)
7346 pHlp->pfnPrintf(pHlp, ">>> ");
7347 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7348 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7349 &pThis->aTxDescriptors[i]);
7350 }
7351#endif /* E1K_WITH_TXD_CACHE */
7352
7353
7354#ifdef E1K_INT_STATS
7355 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7356 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7357 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7358 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7359 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7360 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7361 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7362 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7363 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7364 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7365 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7366 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7367 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7368 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7369 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7370 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7371 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7372 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7373 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7374 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7375 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7376 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7377 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7378 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7379 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7380 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7381 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7382 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7383 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7384 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7385 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7386 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7387 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7388 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7389 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7390 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7391 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7392 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7393#endif /* E1K_INT_STATS */
7394
7395 e1kCsLeave(pThis);
7396}
7397
7398
7399
7400/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7401
7402/**
7403 * Detach notification.
7404 *
7405 * One port on the network card has been disconnected from the network.
7406 *
7407 * @param pDevIns The device instance.
7408 * @param iLUN The logical unit which is being detached.
7409 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7410 */
7411static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7412{
7413 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7414 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7415 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7416 RT_NOREF(fFlags);
7417
7418 AssertLogRelReturnVoid(iLUN == 0);
7419
7420 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7421
7422 /** @todo r=pritesh still need to check if i missed
7423 * to clean something in this function
7424 */
7425
7426 /*
7427 * Zero some important members.
7428 */
7429 pThisCC->pDrvBase = NULL;
7430 pThisCC->pDrvR3 = NULL;
7431#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7432 pThisR0->pDrvR0 = NIL_RTR0PTR;
7433 pThisRC->pDrvRC = NIL_RTRCPTR;
7434#endif
7435
7436 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7437}
7438
7439/**
7440 * Attach the Network attachment.
7441 *
7442 * One port on the network card has been connected to a network.
7443 *
7444 * @returns VBox status code.
7445 * @param pDevIns The device instance.
7446 * @param iLUN The logical unit which is being attached.
7447 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7448 *
7449 * @remarks This code path is not used during construction.
7450 */
7451static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7452{
7453 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7454 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7455 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7456 RT_NOREF(fFlags);
7457
7458 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7459
7460 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7461
7462 /*
7463 * Attach the driver.
7464 */
7465 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7466 if (RT_SUCCESS(rc))
7467 {
7468 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7469 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7470 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7471 if (RT_SUCCESS(rc))
7472 {
7473#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7474 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7475 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7476#endif
7477 }
7478 }
7479 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7480 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7481 {
7482 /* This should never happen because this function is not called
7483 * if there is no driver to attach! */
7484 Log(("%s No attached driver!\n", pThis->szPrf));
7485 }
7486
7487 /*
7488 * Temporary set the link down if it was up so that the guest will know
7489 * that we have change the configuration of the network card
7490 */
7491 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7492 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7493
7494 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7495 return rc;
7496}
7497
7498/**
7499 * @copydoc FNPDMDEVPOWEROFF
7500 */
7501static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7502{
7503 /* Poke thread waiting for buffer space. */
7504 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7505}
7506
7507/**
7508 * @copydoc FNPDMDEVRESET
7509 */
7510static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7511{
7512 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7513 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7514#ifdef E1K_TX_DELAY
7515 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7516#endif /* E1K_TX_DELAY */
7517 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7518 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7519 e1kXmitFreeBuf(pThis, pThisCC);
7520 pThis->u16TxPktLen = 0;
7521 pThis->fIPcsum = false;
7522 pThis->fTCPcsum = false;
7523 pThis->fIntMaskUsed = false;
7524 pThis->fDelayInts = false;
7525 pThis->fLocked = false;
7526 pThis->u64AckedAt = 0;
7527 e1kR3HardReset(pDevIns, pThis, pThisCC);
7528}
7529
7530/**
7531 * @copydoc FNPDMDEVSUSPEND
7532 */
7533static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7534{
7535 /* Poke thread waiting for buffer space. */
7536 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7537}
7538
7539/**
7540 * Device relocation callback.
7541 *
7542 * When this callback is called the device instance data, and if the
7543 * device have a GC component, is being relocated, or/and the selectors
7544 * have been changed. The device must use the chance to perform the
7545 * necessary pointer relocations and data updates.
7546 *
7547 * Before the GC code is executed the first time, this function will be
7548 * called with a 0 delta so GC pointer calculations can be one in one place.
7549 *
7550 * @param pDevIns Pointer to the device instance.
7551 * @param offDelta The relocation delta relative to the old location.
7552 *
7553 * @remark A relocation CANNOT fail.
7554 */
7555static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7556{
7557 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7558 if (pThisRC)
7559 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7560 RT_NOREF(offDelta);
7561}
7562
7563/**
7564 * Destruct a device instance.
7565 *
7566 * We need to free non-VM resources only.
7567 *
7568 * @returns VBox status code.
7569 * @param pDevIns The device instance data.
7570 * @thread EMT
7571 */
7572static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7573{
7574 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7575 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7576
7577 e1kDumpState(pThis);
7578 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7579 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7580 {
7581 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7582 {
7583 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7584 RTThreadYield();
7585 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7586 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7587 }
7588#ifdef E1K_WITH_TX_CS
7589 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7590#endif /* E1K_WITH_TX_CS */
7591 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7592 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7593 }
7594 return VINF_SUCCESS;
7595}
7596
7597
7598/**
7599 * Set PCI configuration space registers.
7600 *
7601 * @param pci Reference to PCI device structure.
7602 * @thread EMT
7603 */
7604static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7605{
7606 Assert(eChip < RT_ELEMENTS(g_aChips));
7607 /* Configure PCI Device, assume 32-bit mode ******************************/
7608 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7609 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7610 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7611 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7612
7613 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7614 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7615 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7616 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7617 /* Stepping A2 */
7618 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7619 /* Ethernet adapter */
7620 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7621 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7622 /* normal single function Ethernet controller */
7623 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7624 /* Memory Register Base Address */
7625 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7626 /* Memory Flash Base Address */
7627 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7628 /* IO Register Base Address */
7629 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7630 /* Expansion ROM Base Address */
7631 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7632 /* Capabilities Pointer */
7633 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7634 /* Interrupt Pin: INTA# */
7635 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7636 /* Max_Lat/Min_Gnt: very high priority and time slice */
7637 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7638 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7639
7640 /* PCI Power Management Registers ****************************************/
7641 /* Capability ID: PCI Power Management Registers */
7642 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7643 /* Next Item Pointer: PCI-X */
7644 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7645 /* Power Management Capabilities: PM disabled, DSI */
7646 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7647 0x0002 | VBOX_PCI_PM_CAP_DSI);
7648 /* Power Management Control / Status Register: PM disabled */
7649 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7650 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7651 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7652 /* Data Register: PM disabled, always 0 */
7653 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7654
7655 /* PCI-X Configuration Registers *****************************************/
7656 /* Capability ID: PCI-X Configuration Registers */
7657 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7658#ifdef E1K_WITH_MSI
7659 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7660#else
7661 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7662 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7663#endif
7664 /* PCI-X Command: Enable Relaxed Ordering */
7665 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7666 /* PCI-X Status: 32-bit, 66MHz*/
7667 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7668 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7669}
7670
7671/**
7672 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7673 */
7674static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7675{
7676 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7677 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7678 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7679 int rc;
7680
7681 /*
7682 * Initialize the instance data (state).
7683 * Note! Caller has initialized it to ZERO already.
7684 */
7685 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7686 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7687 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7688 pThis->u16TxPktLen = 0;
7689 pThis->fIPcsum = false;
7690 pThis->fTCPcsum = false;
7691 pThis->fIntMaskUsed = false;
7692 pThis->fDelayInts = false;
7693 pThis->fLocked = false;
7694 pThis->u64AckedAt = 0;
7695 pThis->led.u32Magic = PDMLED_MAGIC;
7696 pThis->u32PktNo = 1;
7697
7698 pThisCC->pDevInsR3 = pDevIns;
7699 pThisCC->pShared = pThis;
7700
7701 /* Interfaces */
7702 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7703
7704 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7705 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7706 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7707
7708 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7709
7710 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7711 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7712 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7713
7714 /*
7715 * Internal validations.
7716 */
7717 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7718 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7719 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7720 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7721 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7722 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7723 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7724 VERR_INTERNAL_ERROR_4);
7725
7726 /*
7727 * Validate configuration.
7728 */
7729 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7730 "MAC|"
7731 "CableConnected|"
7732 "AdapterType|"
7733 "LineSpeed|"
7734 "ItrEnabled|"
7735 "ItrRxEnabled|"
7736 "EthernetCRC|"
7737 "GSOEnabled|"
7738 "LinkUpDelay|"
7739 "StatNo",
7740 "");
7741
7742 /** @todo LineSpeed unused! */
7743
7744 /*
7745 * Get config params
7746 */
7747 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7748 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7749 if (RT_FAILURE(rc))
7750 return PDMDEV_SET_ERROR(pDevIns, rc,
7751 N_("Configuration error: Failed to get MAC address"));
7752 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7753 if (RT_FAILURE(rc))
7754 return PDMDEV_SET_ERROR(pDevIns, rc,
7755 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7756 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7757 if (RT_FAILURE(rc))
7758 return PDMDEV_SET_ERROR(pDevIns, rc,
7759 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7760 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7761
7762 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7763 if (RT_FAILURE(rc))
7764 return PDMDEV_SET_ERROR(pDevIns, rc,
7765 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7766
7767 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7768 if (RT_FAILURE(rc))
7769 return PDMDEV_SET_ERROR(pDevIns, rc,
7770 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7771
7772 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7773 if (RT_FAILURE(rc))
7774 return PDMDEV_SET_ERROR(pDevIns, rc,
7775 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7776
7777 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7778 if (RT_FAILURE(rc))
7779 return PDMDEV_SET_ERROR(pDevIns, rc,
7780 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7781
7782 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7783 if (RT_FAILURE(rc))
7784 return PDMDEV_SET_ERROR(pDevIns, rc,
7785 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7786
7787 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7788 if (RT_FAILURE(rc))
7789 return PDMDEV_SET_ERROR(pDevIns, rc,
7790 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7791 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7792 if (pThis->cMsLinkUpDelay > 5000)
7793 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7794 else if (pThis->cMsLinkUpDelay == 0)
7795 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7796
7797 uint32_t uStatNo = (uint32_t)iInstance;
7798 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7799 if (RT_FAILURE(rc))
7800 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7801
7802 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7803 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7804 pThis->fEthernetCRC ? "on" : "off",
7805 pThis->fGSOEnabled ? "enabled" : "disabled",
7806 pThis->fItrEnabled ? "enabled" : "disabled",
7807 pThis->fItrRxEnabled ? "enabled" : "disabled",
7808 pThis->fTidEnabled ? "enabled" : "disabled",
7809 pDevIns->fR0Enabled ? "enabled" : "disabled",
7810 pDevIns->fRCEnabled ? "enabled" : "disabled"));
7811
7812 /*
7813 * Initialize sub-components and register everything with the VMM.
7814 */
7815
7816 /* Initialize the EEPROM. */
7817 pThisCC->eeprom.init(pThis->macConfigured);
7818
7819 /* Initialize internal PHY. */
7820 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7821
7822 /* Initialize critical sections. We do our own locking. */
7823 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7824 AssertRCReturn(rc, rc);
7825
7826 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7827 AssertRCReturn(rc, rc);
7828 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7829 AssertRCReturn(rc, rc);
7830#ifdef E1K_WITH_TX_CS
7831 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7832 AssertRCReturn(rc, rc);
7833#endif
7834
7835 /* Saved state registration. */
7836 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7837 NULL, e1kLiveExec, NULL,
7838 e1kSavePrep, e1kSaveExec, NULL,
7839 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7840 AssertRCReturn(rc, rc);
7841
7842 /* Set PCI config registers and register ourselves with the PCI bus. */
7843 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
7844 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
7845 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
7846 AssertRCReturn(rc, rc);
7847
7848#ifdef E1K_WITH_MSI
7849 PDMMSIREG MsiReg;
7850 RT_ZERO(MsiReg);
7851 MsiReg.cMsiVectors = 1;
7852 MsiReg.iMsiCapOffset = 0x80;
7853 MsiReg.iMsiNextOffset = 0x0;
7854 MsiReg.fMsi64bit = false;
7855 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7856 AssertRCReturn(rc, rc);
7857#endif
7858
7859 /*
7860 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
7861 * From the spec (regarding flags):
7862 * For registers that should be accessed as 32-bit double words,
7863 * partial writes (less than a 32-bit double word) is ignored.
7864 * Partial reads return all 32 bits of data regardless of the
7865 * byte enables.
7866 */
7867 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
7868 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
7869 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
7870 AssertRCReturn(rc, rc);
7871 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
7872 AssertRCReturn(rc, rc);
7873
7874 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
7875 static IOMIOPORTDESC const s_aExtDescs[] =
7876 {
7877 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7878 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
7879 { NULL, NULL, NULL, NULL }
7880 };
7881 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
7882 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
7883 AssertRCReturn(rc, rc);
7884 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
7885 AssertRCReturn(rc, rc);
7886
7887 /* Create transmit queue */
7888 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
7889 AssertRCReturn(rc, rc);
7890
7891#ifdef E1K_TX_DELAY
7892 /* Create Transmit Delay Timer */
7893 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7894 "E1000 Transmit Delay Timer", &pThis->hTXDTimer);
7895 AssertRCReturn(rc, rc);
7896 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
7897 AssertRCReturn(rc, rc);
7898#endif /* E1K_TX_DELAY */
7899
7900//#ifdef E1K_USE_TX_TIMERS
7901 if (pThis->fTidEnabled)
7902 {
7903 /* Create Transmit Interrupt Delay Timer */
7904 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7905 "E1000 Transmit Interrupt Delay Timer", &pThis->hTIDTimer);
7906 AssertRCReturn(rc, rc);
7907
7908# ifndef E1K_NO_TAD
7909 /* Create Transmit Absolute Delay Timer */
7910 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7911 "E1000 Transmit Absolute Delay Timer", &pThis->hTADTimer);
7912 AssertRCReturn(rc, rc);
7913# endif /* E1K_NO_TAD */
7914 }
7915//#endif /* E1K_USE_TX_TIMERS */
7916
7917#ifdef E1K_USE_RX_TIMERS
7918 /* Create Receive Interrupt Delay Timer */
7919 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7920 "E1000 Receive Interrupt Delay Timer", &pThis->hRIDTimer);
7921 AssertRCReturn(rc, rc);
7922
7923 /* Create Receive Absolute Delay Timer */
7924 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7925 "E1000 Receive Absolute Delay Timer", &pThis->hRADTimer);
7926 AssertRCReturn(rc, rc);
7927#endif /* E1K_USE_RX_TIMERS */
7928
7929 /* Create Late Interrupt Timer */
7930 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7931 "E1000 Late Interrupt Timer", &pThis->hIntTimer);
7932 AssertRCReturn(rc, rc);
7933
7934 /* Create Link Up Timer */
7935 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis, TMTIMER_FLAGS_NO_CRIT_SECT,
7936 "E1000 Link Up Timer", &pThis->hLUTimer);
7937 AssertRCReturn(rc, rc);
7938
7939 /* Register the info item */
7940 char szTmp[20];
7941 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
7942 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
7943
7944 /* Status driver */
7945 PPDMIBASE pBase;
7946 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
7947 if (RT_FAILURE(rc))
7948 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
7949 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
7950
7951 /* Network driver */
7952 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7953 if (RT_SUCCESS(rc))
7954 {
7955 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7956 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
7957
7958#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7959 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7960 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7961#endif
7962 }
7963 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7964 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7965 {
7966 /* No error! */
7967 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
7968 }
7969 else
7970 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
7971
7972 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
7973 AssertRCReturn(rc, rc);
7974
7975 rc = e1kInitDebugHelpers();
7976 AssertRCReturn(rc, rc);
7977
7978 e1kR3HardReset(pDevIns, pThis, pThisCC);
7979
7980 /*
7981 * Register statistics.
7982 * The /Public/ bits are official and used by session info in the GUI.
7983 */
7984 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7985 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
7986 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
7987 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
7988 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
7989 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
7990
7991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
7992 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
7993
7994#if defined(VBOX_WITH_STATISTICS)
7995 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
7996 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
7997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
7998 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
7999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8000 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8001 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8003 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8006 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8007 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8013 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8015 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8016 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8020
8021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8030 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8031 {
8032 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8033 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8034 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8035 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8036 }
8037#endif /* VBOX_WITH_STATISTICS */
8038
8039#ifdef E1K_INT_STATS
8040 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8041 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8042 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8043 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8044 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8045 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8046 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8047 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8048 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8049 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8050 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8051 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8052 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8053 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8054 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8055 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8056 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8057 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8058 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8059 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8060 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8061 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8062 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8063 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8064 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8065 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8066 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8067 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8068 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8069 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8070 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8071 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8072 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8073 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8074 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8075 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8076 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8077 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8078 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8079 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8080 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8081#endif /* E1K_INT_STATS */
8082
8083 return VINF_SUCCESS;
8084}
8085
8086#else /* !IN_RING3 */
8087
8088/**
8089 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8090 */
8091static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8092{
8093 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8094 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8095 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8096
8097 /* Initialize context specific state data: */
8098 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8099 /** @todo @bugref{9218} ring-0 driver stuff */
8100 pThisCC->CTX_SUFF(pDrv) = NULL;
8101 pThisCC->CTX_SUFF(pTxSg) = NULL;
8102
8103 /* Configure critical sections the same way: */
8104 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8105 AssertRCReturn(rc, rc);
8106
8107 /* Set up MMIO and I/O port callbacks for this context: */
8108 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8109 AssertRCReturn(rc, rc);
8110
8111 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8112 AssertRCReturn(rc, rc);
8113
8114 return VINF_SUCCESS;
8115}
8116
8117#endif /* !IN_RING3 */
8118
8119/**
8120 * The device registration structure.
8121 */
8122const PDMDEVREG g_DeviceE1000 =
8123{
8124 /* .u32version = */ PDM_DEVREG_VERSION,
8125 /* .uReserved0 = */ 0,
8126 /* .szName = */ "e1000",
8127 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8128 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8129 /* .cMaxInstances = */ ~0U,
8130 /* .uSharedVersion = */ 42,
8131 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8132 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8133 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8134 /* .cMaxPciDevices = */ 1,
8135 /* .cMaxMsixVectors = */ 0,
8136 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8137#if defined(IN_RING3)
8138 /* .pszRCMod = */ "VBoxDDRC.rc",
8139 /* .pszR0Mod = */ "VBoxDDR0.r0",
8140 /* .pfnConstruct = */ e1kR3Construct,
8141 /* .pfnDestruct = */ e1kR3Destruct,
8142 /* .pfnRelocate = */ e1kR3Relocate,
8143 /* .pfnMemSetup = */ NULL,
8144 /* .pfnPowerOn = */ NULL,
8145 /* .pfnReset = */ e1kR3Reset,
8146 /* .pfnSuspend = */ e1kR3Suspend,
8147 /* .pfnResume = */ NULL,
8148 /* .pfnAttach = */ e1kR3Attach,
8149 /* .pfnDeatch = */ e1kR3Detach,
8150 /* .pfnQueryInterface = */ NULL,
8151 /* .pfnInitComplete = */ NULL,
8152 /* .pfnPowerOff = */ e1kR3PowerOff,
8153 /* .pfnSoftReset = */ NULL,
8154 /* .pfnReserved0 = */ NULL,
8155 /* .pfnReserved1 = */ NULL,
8156 /* .pfnReserved2 = */ NULL,
8157 /* .pfnReserved3 = */ NULL,
8158 /* .pfnReserved4 = */ NULL,
8159 /* .pfnReserved5 = */ NULL,
8160 /* .pfnReserved6 = */ NULL,
8161 /* .pfnReserved7 = */ NULL,
8162#elif defined(IN_RING0)
8163 /* .pfnEarlyConstruct = */ NULL,
8164 /* .pfnConstruct = */ e1kRZConstruct,
8165 /* .pfnDestruct = */ NULL,
8166 /* .pfnFinalDestruct = */ NULL,
8167 /* .pfnRequest = */ NULL,
8168 /* .pfnReserved0 = */ NULL,
8169 /* .pfnReserved1 = */ NULL,
8170 /* .pfnReserved2 = */ NULL,
8171 /* .pfnReserved3 = */ NULL,
8172 /* .pfnReserved4 = */ NULL,
8173 /* .pfnReserved5 = */ NULL,
8174 /* .pfnReserved6 = */ NULL,
8175 /* .pfnReserved7 = */ NULL,
8176#elif defined(IN_RC)
8177 /* .pfnConstruct = */ e1kRZConstruct,
8178 /* .pfnReserved0 = */ NULL,
8179 /* .pfnReserved1 = */ NULL,
8180 /* .pfnReserved2 = */ NULL,
8181 /* .pfnReserved3 = */ NULL,
8182 /* .pfnReserved4 = */ NULL,
8183 /* .pfnReserved5 = */ NULL,
8184 /* .pfnReserved6 = */ NULL,
8185 /* .pfnReserved7 = */ NULL,
8186#else
8187# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8188#endif
8189 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8190};
8191
8192#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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