VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 87999

Last change on this file since 87999 was 87773, checked in by vboxsync, 4 years ago

VMM/TM,Devices: Store the timer name in the TMTIMER structure and limit it to 31 characters. Shortened most timer names. bugref:9943
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1/* $Id: DevE1000.cpp 87773 2021-02-16 23:36:15Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2020 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280/** Gets the specfieid bits from the register. */
281#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
282#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
284#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
285#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286
287#define CTRL_SLU UINT32_C(0x00000040)
288#define CTRL_MDIO UINT32_C(0x00100000)
289#define CTRL_MDC UINT32_C(0x00200000)
290#define CTRL_MDIO_DIR UINT32_C(0x01000000)
291#define CTRL_MDC_DIR UINT32_C(0x02000000)
292#define CTRL_RESET UINT32_C(0x04000000)
293#define CTRL_VME UINT32_C(0x40000000)
294
295#define STATUS_LU UINT32_C(0x00000002)
296#define STATUS_TXOFF UINT32_C(0x00000010)
297
298#define EECD_EE_WIRES UINT32_C(0x0F)
299#define EECD_EE_REQ UINT32_C(0x40)
300#define EECD_EE_GNT UINT32_C(0x80)
301
302#define EERD_START UINT32_C(0x00000001)
303#define EERD_DONE UINT32_C(0x00000010)
304#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
305#define EERD_DATA_SHIFT 16
306#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
307#define EERD_ADDR_SHIFT 8
308
309#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
310#define MDIC_DATA_SHIFT 0
311#define MDIC_REG_MASK UINT32_C(0x001F0000)
312#define MDIC_REG_SHIFT 16
313#define MDIC_PHY_MASK UINT32_C(0x03E00000)
314#define MDIC_PHY_SHIFT 21
315#define MDIC_OP_WRITE UINT32_C(0x04000000)
316#define MDIC_OP_READ UINT32_C(0x08000000)
317#define MDIC_READY UINT32_C(0x10000000)
318#define MDIC_INT_EN UINT32_C(0x20000000)
319#define MDIC_ERROR UINT32_C(0x40000000)
320
321#define TCTL_EN UINT32_C(0x00000002)
322#define TCTL_PSP UINT32_C(0x00000008)
323
324#define RCTL_EN UINT32_C(0x00000002)
325#define RCTL_UPE UINT32_C(0x00000008)
326#define RCTL_MPE UINT32_C(0x00000010)
327#define RCTL_LPE UINT32_C(0x00000020)
328#define RCTL_LBM_MASK UINT32_C(0x000000C0)
329#define RCTL_LBM_SHIFT 6
330#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
331#define RCTL_RDMTS_SHIFT 8
332#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
333#define RCTL_MO_MASK UINT32_C(0x00003000)
334#define RCTL_MO_SHIFT 12
335#define RCTL_BAM UINT32_C(0x00008000)
336#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
337#define RCTL_BSIZE_SHIFT 16
338#define RCTL_VFE UINT32_C(0x00040000)
339#define RCTL_CFIEN UINT32_C(0x00080000)
340#define RCTL_CFI UINT32_C(0x00100000)
341#define RCTL_BSEX UINT32_C(0x02000000)
342#define RCTL_SECRC UINT32_C(0x04000000)
343
344#define ICR_TXDW UINT32_C(0x00000001)
345#define ICR_TXQE UINT32_C(0x00000002)
346#define ICR_LSC UINT32_C(0x00000004)
347#define ICR_RXDMT0 UINT32_C(0x00000010)
348#define ICR_RXT0 UINT32_C(0x00000080)
349#define ICR_TXD_LOW UINT32_C(0x00008000)
350#define RDTR_FPD UINT32_C(0x80000000)
351
352#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
353typedef struct
354{
355 unsigned rxa : 7;
356 unsigned rxa_r : 9;
357 unsigned txa : 16;
358} PBAST;
359AssertCompileSize(PBAST, 4);
360
361#define TXDCTL_WTHRESH_MASK 0x003F0000
362#define TXDCTL_WTHRESH_SHIFT 16
363#define TXDCTL_LWTHRESH_MASK 0xFE000000
364#define TXDCTL_LWTHRESH_SHIFT 25
365
366#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
367#define RXCSUM_PCSS_SHIFT 0
368
369/** @name Register access macros
370 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
371 * @{ */
372#define CTRL pThis->auRegs[CTRL_IDX]
373#define STATUS pThis->auRegs[STATUS_IDX]
374#define EECD pThis->auRegs[EECD_IDX]
375#define EERD pThis->auRegs[EERD_IDX]
376#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
377#define FLA pThis->auRegs[FLA_IDX]
378#define MDIC pThis->auRegs[MDIC_IDX]
379#define FCAL pThis->auRegs[FCAL_IDX]
380#define FCAH pThis->auRegs[FCAH_IDX]
381#define FCT pThis->auRegs[FCT_IDX]
382#define VET pThis->auRegs[VET_IDX]
383#define ICR pThis->auRegs[ICR_IDX]
384#define ITR pThis->auRegs[ITR_IDX]
385#define ICS pThis->auRegs[ICS_IDX]
386#define IMS pThis->auRegs[IMS_IDX]
387#define IMC pThis->auRegs[IMC_IDX]
388#define RCTL pThis->auRegs[RCTL_IDX]
389#define FCTTV pThis->auRegs[FCTTV_IDX]
390#define TXCW pThis->auRegs[TXCW_IDX]
391#define RXCW pThis->auRegs[RXCW_IDX]
392#define TCTL pThis->auRegs[TCTL_IDX]
393#define TIPG pThis->auRegs[TIPG_IDX]
394#define AIFS pThis->auRegs[AIFS_IDX]
395#define LEDCTL pThis->auRegs[LEDCTL_IDX]
396#define PBA pThis->auRegs[PBA_IDX]
397#define FCRTL pThis->auRegs[FCRTL_IDX]
398#define FCRTH pThis->auRegs[FCRTH_IDX]
399#define RDFH pThis->auRegs[RDFH_IDX]
400#define RDFT pThis->auRegs[RDFT_IDX]
401#define RDFHS pThis->auRegs[RDFHS_IDX]
402#define RDFTS pThis->auRegs[RDFTS_IDX]
403#define RDFPC pThis->auRegs[RDFPC_IDX]
404#define RDBAL pThis->auRegs[RDBAL_IDX]
405#define RDBAH pThis->auRegs[RDBAH_IDX]
406#define RDLEN pThis->auRegs[RDLEN_IDX]
407#define RDH pThis->auRegs[RDH_IDX]
408#define RDT pThis->auRegs[RDT_IDX]
409#define RDTR pThis->auRegs[RDTR_IDX]
410#define RXDCTL pThis->auRegs[RXDCTL_IDX]
411#define RADV pThis->auRegs[RADV_IDX]
412#define RSRPD pThis->auRegs[RSRPD_IDX]
413#define TXDMAC pThis->auRegs[TXDMAC_IDX]
414#define TDFH pThis->auRegs[TDFH_IDX]
415#define TDFT pThis->auRegs[TDFT_IDX]
416#define TDFHS pThis->auRegs[TDFHS_IDX]
417#define TDFTS pThis->auRegs[TDFTS_IDX]
418#define TDFPC pThis->auRegs[TDFPC_IDX]
419#define TDBAL pThis->auRegs[TDBAL_IDX]
420#define TDBAH pThis->auRegs[TDBAH_IDX]
421#define TDLEN pThis->auRegs[TDLEN_IDX]
422#define TDH pThis->auRegs[TDH_IDX]
423#define TDT pThis->auRegs[TDT_IDX]
424#define TIDV pThis->auRegs[TIDV_IDX]
425#define TXDCTL pThis->auRegs[TXDCTL_IDX]
426#define TADV pThis->auRegs[TADV_IDX]
427#define TSPMT pThis->auRegs[TSPMT_IDX]
428#define CRCERRS pThis->auRegs[CRCERRS_IDX]
429#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
430#define SYMERRS pThis->auRegs[SYMERRS_IDX]
431#define RXERRC pThis->auRegs[RXERRC_IDX]
432#define MPC pThis->auRegs[MPC_IDX]
433#define SCC pThis->auRegs[SCC_IDX]
434#define ECOL pThis->auRegs[ECOL_IDX]
435#define MCC pThis->auRegs[MCC_IDX]
436#define LATECOL pThis->auRegs[LATECOL_IDX]
437#define COLC pThis->auRegs[COLC_IDX]
438#define DC pThis->auRegs[DC_IDX]
439#define TNCRS pThis->auRegs[TNCRS_IDX]
440/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
441#define CEXTERR pThis->auRegs[CEXTERR_IDX]
442#define RLEC pThis->auRegs[RLEC_IDX]
443#define XONRXC pThis->auRegs[XONRXC_IDX]
444#define XONTXC pThis->auRegs[XONTXC_IDX]
445#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
446#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
447#define FCRUC pThis->auRegs[FCRUC_IDX]
448#define PRC64 pThis->auRegs[PRC64_IDX]
449#define PRC127 pThis->auRegs[PRC127_IDX]
450#define PRC255 pThis->auRegs[PRC255_IDX]
451#define PRC511 pThis->auRegs[PRC511_IDX]
452#define PRC1023 pThis->auRegs[PRC1023_IDX]
453#define PRC1522 pThis->auRegs[PRC1522_IDX]
454#define GPRC pThis->auRegs[GPRC_IDX]
455#define BPRC pThis->auRegs[BPRC_IDX]
456#define MPRC pThis->auRegs[MPRC_IDX]
457#define GPTC pThis->auRegs[GPTC_IDX]
458#define GORCL pThis->auRegs[GORCL_IDX]
459#define GORCH pThis->auRegs[GORCH_IDX]
460#define GOTCL pThis->auRegs[GOTCL_IDX]
461#define GOTCH pThis->auRegs[GOTCH_IDX]
462#define RNBC pThis->auRegs[RNBC_IDX]
463#define RUC pThis->auRegs[RUC_IDX]
464#define RFC pThis->auRegs[RFC_IDX]
465#define ROC pThis->auRegs[ROC_IDX]
466#define RJC pThis->auRegs[RJC_IDX]
467#define MGTPRC pThis->auRegs[MGTPRC_IDX]
468#define MGTPDC pThis->auRegs[MGTPDC_IDX]
469#define MGTPTC pThis->auRegs[MGTPTC_IDX]
470#define TORL pThis->auRegs[TORL_IDX]
471#define TORH pThis->auRegs[TORH_IDX]
472#define TOTL pThis->auRegs[TOTL_IDX]
473#define TOTH pThis->auRegs[TOTH_IDX]
474#define TPR pThis->auRegs[TPR_IDX]
475#define TPT pThis->auRegs[TPT_IDX]
476#define PTC64 pThis->auRegs[PTC64_IDX]
477#define PTC127 pThis->auRegs[PTC127_IDX]
478#define PTC255 pThis->auRegs[PTC255_IDX]
479#define PTC511 pThis->auRegs[PTC511_IDX]
480#define PTC1023 pThis->auRegs[PTC1023_IDX]
481#define PTC1522 pThis->auRegs[PTC1522_IDX]
482#define MPTC pThis->auRegs[MPTC_IDX]
483#define BPTC pThis->auRegs[BPTC_IDX]
484#define TSCTC pThis->auRegs[TSCTC_IDX]
485#define TSCTFC pThis->auRegs[TSCTFC_IDX]
486#define RXCSUM pThis->auRegs[RXCSUM_IDX]
487#define WUC pThis->auRegs[WUC_IDX]
488#define WUFC pThis->auRegs[WUFC_IDX]
489#define WUS pThis->auRegs[WUS_IDX]
490#define MANC pThis->auRegs[MANC_IDX]
491#define IPAV pThis->auRegs[IPAV_IDX]
492#define WUPL pThis->auRegs[WUPL_IDX]
493/** @} */
494
495/**
496 * Indices of memory-mapped registers in register table.
497 */
498typedef enum
499{
500 CTRL_IDX,
501 STATUS_IDX,
502 EECD_IDX,
503 EERD_IDX,
504 CTRL_EXT_IDX,
505 FLA_IDX,
506 MDIC_IDX,
507 FCAL_IDX,
508 FCAH_IDX,
509 FCT_IDX,
510 VET_IDX,
511 ICR_IDX,
512 ITR_IDX,
513 ICS_IDX,
514 IMS_IDX,
515 IMC_IDX,
516 RCTL_IDX,
517 FCTTV_IDX,
518 TXCW_IDX,
519 RXCW_IDX,
520 TCTL_IDX,
521 TIPG_IDX,
522 AIFS_IDX,
523 LEDCTL_IDX,
524 PBA_IDX,
525 FCRTL_IDX,
526 FCRTH_IDX,
527 RDFH_IDX,
528 RDFT_IDX,
529 RDFHS_IDX,
530 RDFTS_IDX,
531 RDFPC_IDX,
532 RDBAL_IDX,
533 RDBAH_IDX,
534 RDLEN_IDX,
535 RDH_IDX,
536 RDT_IDX,
537 RDTR_IDX,
538 RXDCTL_IDX,
539 RADV_IDX,
540 RSRPD_IDX,
541 TXDMAC_IDX,
542 TDFH_IDX,
543 TDFT_IDX,
544 TDFHS_IDX,
545 TDFTS_IDX,
546 TDFPC_IDX,
547 TDBAL_IDX,
548 TDBAH_IDX,
549 TDLEN_IDX,
550 TDH_IDX,
551 TDT_IDX,
552 TIDV_IDX,
553 TXDCTL_IDX,
554 TADV_IDX,
555 TSPMT_IDX,
556 CRCERRS_IDX,
557 ALGNERRC_IDX,
558 SYMERRS_IDX,
559 RXERRC_IDX,
560 MPC_IDX,
561 SCC_IDX,
562 ECOL_IDX,
563 MCC_IDX,
564 LATECOL_IDX,
565 COLC_IDX,
566 DC_IDX,
567 TNCRS_IDX,
568 SEC_IDX,
569 CEXTERR_IDX,
570 RLEC_IDX,
571 XONRXC_IDX,
572 XONTXC_IDX,
573 XOFFRXC_IDX,
574 XOFFTXC_IDX,
575 FCRUC_IDX,
576 PRC64_IDX,
577 PRC127_IDX,
578 PRC255_IDX,
579 PRC511_IDX,
580 PRC1023_IDX,
581 PRC1522_IDX,
582 GPRC_IDX,
583 BPRC_IDX,
584 MPRC_IDX,
585 GPTC_IDX,
586 GORCL_IDX,
587 GORCH_IDX,
588 GOTCL_IDX,
589 GOTCH_IDX,
590 RNBC_IDX,
591 RUC_IDX,
592 RFC_IDX,
593 ROC_IDX,
594 RJC_IDX,
595 MGTPRC_IDX,
596 MGTPDC_IDX,
597 MGTPTC_IDX,
598 TORL_IDX,
599 TORH_IDX,
600 TOTL_IDX,
601 TOTH_IDX,
602 TPR_IDX,
603 TPT_IDX,
604 PTC64_IDX,
605 PTC127_IDX,
606 PTC255_IDX,
607 PTC511_IDX,
608 PTC1023_IDX,
609 PTC1522_IDX,
610 MPTC_IDX,
611 BPTC_IDX,
612 TSCTC_IDX,
613 TSCTFC_IDX,
614 RXCSUM_IDX,
615 WUC_IDX,
616 WUFC_IDX,
617 WUS_IDX,
618 MANC_IDX,
619 IPAV_IDX,
620 WUPL_IDX,
621 MTA_IDX,
622 RA_IDX,
623 VFTA_IDX,
624 IP4AT_IDX,
625 IP6AT_IDX,
626 WUPM_IDX,
627 FFLT_IDX,
628 FFMT_IDX,
629 FFVT_IDX,
630 PBM_IDX,
631 RA_82542_IDX,
632 MTA_82542_IDX,
633 VFTA_82542_IDX,
634 E1K_NUM_OF_REGS
635} E1kRegIndex;
636
637#define E1K_NUM_OF_32BIT_REGS MTA_IDX
638/** The number of registers with strictly increasing offset. */
639#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
640
641
642/**
643 * Define E1000-specific EEPROM layout.
644 */
645struct E1kEEPROM
646{
647 public:
648 EEPROM93C46 eeprom;
649
650#ifdef IN_RING3
651 /**
652 * Initialize EEPROM content.
653 *
654 * @param macAddr MAC address of E1000.
655 */
656 void init(RTMAC &macAddr)
657 {
658 eeprom.init();
659 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
660 eeprom.m_au16Data[0x04] = 0xFFFF;
661 /*
662 * bit 3 - full support for power management
663 * bit 10 - full duplex
664 */
665 eeprom.m_au16Data[0x0A] = 0x4408;
666 eeprom.m_au16Data[0x0B] = 0x001E;
667 eeprom.m_au16Data[0x0C] = 0x8086;
668 eeprom.m_au16Data[0x0D] = 0x100E;
669 eeprom.m_au16Data[0x0E] = 0x8086;
670 eeprom.m_au16Data[0x0F] = 0x3040;
671 eeprom.m_au16Data[0x21] = 0x7061;
672 eeprom.m_au16Data[0x22] = 0x280C;
673 eeprom.m_au16Data[0x23] = 0x00C8;
674 eeprom.m_au16Data[0x24] = 0x00C8;
675 eeprom.m_au16Data[0x2F] = 0x0602;
676 updateChecksum();
677 };
678
679 /**
680 * Compute the checksum as required by E1000 and store it
681 * in the last word.
682 */
683 void updateChecksum()
684 {
685 uint16_t u16Checksum = 0;
686
687 for (int i = 0; i < eeprom.SIZE-1; i++)
688 u16Checksum += eeprom.m_au16Data[i];
689 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
690 };
691
692 /**
693 * First 6 bytes of EEPROM contain MAC address.
694 *
695 * @returns MAC address of E1000.
696 */
697 void getMac(PRTMAC pMac)
698 {
699 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
700 };
701
702 uint32_t read()
703 {
704 return eeprom.read();
705 }
706
707 void write(uint32_t u32Wires)
708 {
709 eeprom.write(u32Wires);
710 }
711
712 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
713 {
714 return eeprom.readWord(u32Addr, pu16Value);
715 }
716
717 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
718 {
719 return eeprom.load(pHlp, pSSM);
720 }
721
722 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
723 {
724 eeprom.save(pHlp, pSSM);
725 }
726#endif /* IN_RING3 */
727};
728
729
730#define E1K_SPEC_VLAN(s) (s & 0xFFF)
731#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
732#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
733
734struct E1kRxDStatus
735{
736 /** @name Descriptor Status field (3.2.3.1)
737 * @{ */
738 unsigned fDD : 1; /**< Descriptor Done. */
739 unsigned fEOP : 1; /**< End of packet. */
740 unsigned fIXSM : 1; /**< Ignore checksum indication. */
741 unsigned fVP : 1; /**< VLAN, matches VET. */
742 unsigned : 1;
743 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
744 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
745 unsigned fPIF : 1; /**< Passed in-exact filter */
746 /** @} */
747 /** @name Descriptor Errors field (3.2.3.2)
748 * (Only valid when fEOP and fDD are set.)
749 * @{ */
750 unsigned fCE : 1; /**< CRC or alignment error. */
751 unsigned : 4; /**< Reserved, varies with different models... */
752 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
753 unsigned fIPE : 1; /**< IP Checksum error. */
754 unsigned fRXE : 1; /**< RX Data error. */
755 /** @} */
756 /** @name Descriptor Special field (3.2.3.3)
757 * @{ */
758 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
759 /** @} */
760};
761typedef struct E1kRxDStatus E1KRXDST;
762
763struct E1kRxDesc_st
764{
765 uint64_t u64BufAddr; /**< Address of data buffer */
766 uint16_t u16Length; /**< Length of data in buffer */
767 uint16_t u16Checksum; /**< Packet checksum */
768 E1KRXDST status;
769};
770typedef struct E1kRxDesc_st E1KRXDESC;
771AssertCompileSize(E1KRXDESC, 16);
772
773#define E1K_DTYP_LEGACY -1
774#define E1K_DTYP_CONTEXT 0
775#define E1K_DTYP_DATA 1
776
777struct E1kTDLegacy
778{
779 uint64_t u64BufAddr; /**< Address of data buffer */
780 struct TDLCmd_st
781 {
782 unsigned u16Length : 16;
783 unsigned u8CSO : 8;
784 /* CMD field : 8 */
785 unsigned fEOP : 1;
786 unsigned fIFCS : 1;
787 unsigned fIC : 1;
788 unsigned fRS : 1;
789 unsigned fRPS : 1;
790 unsigned fDEXT : 1;
791 unsigned fVLE : 1;
792 unsigned fIDE : 1;
793 } cmd;
794 struct TDLDw3_st
795 {
796 /* STA field */
797 unsigned fDD : 1;
798 unsigned fEC : 1;
799 unsigned fLC : 1;
800 unsigned fTURSV : 1;
801 /* RSV field */
802 unsigned u4RSV : 4;
803 /* CSS field */
804 unsigned u8CSS : 8;
805 /* Special field*/
806 unsigned u16Special: 16;
807 } dw3;
808};
809
810/**
811 * TCP/IP Context Transmit Descriptor, section 3.3.6.
812 */
813struct E1kTDContext
814{
815 struct CheckSum_st
816 {
817 /** TSE: Header start. !TSE: Checksum start. */
818 unsigned u8CSS : 8;
819 /** Checksum offset - where to store it. */
820 unsigned u8CSO : 8;
821 /** Checksum ending (inclusive) offset, 0 = end of packet. */
822 unsigned u16CSE : 16;
823 } ip;
824 struct CheckSum_st tu;
825 struct TDCDw2_st
826 {
827 /** TSE: The total number of payload bytes for this context. Sans header. */
828 unsigned u20PAYLEN : 20;
829 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
830 unsigned u4DTYP : 4;
831 /** TUCMD field, 8 bits
832 * @{ */
833 /** TSE: TCP (set) or UDP (clear). */
834 unsigned fTCP : 1;
835 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
836 * the IP header. Does not affect the checksumming.
837 * @remarks 82544GC/EI interprets a cleared field differently. */
838 unsigned fIP : 1;
839 /** TSE: TCP segmentation enable. When clear the context describes */
840 unsigned fTSE : 1;
841 /** Report status (only applies to dw3.fDD for here). */
842 unsigned fRS : 1;
843 /** Reserved, MBZ. */
844 unsigned fRSV1 : 1;
845 /** Descriptor extension, must be set for this descriptor type. */
846 unsigned fDEXT : 1;
847 /** Reserved, MBZ. */
848 unsigned fRSV2 : 1;
849 /** Interrupt delay enable. */
850 unsigned fIDE : 1;
851 /** @} */
852 } dw2;
853 struct TDCDw3_st
854 {
855 /** Descriptor Done. */
856 unsigned fDD : 1;
857 /** Reserved, MBZ. */
858 unsigned u7RSV : 7;
859 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
860 unsigned u8HDRLEN : 8;
861 /** TSO: Maximum segment size. */
862 unsigned u16MSS : 16;
863 } dw3;
864};
865typedef struct E1kTDContext E1KTXCTX;
866
867/**
868 * TCP/IP Data Transmit Descriptor, section 3.3.7.
869 */
870struct E1kTDData
871{
872 uint64_t u64BufAddr; /**< Address of data buffer */
873 struct TDDCmd_st
874 {
875 /** The total length of data pointed to by this descriptor. */
876 unsigned u20DTALEN : 20;
877 /** The descriptor type - E1K_DTYP_DATA (1). */
878 unsigned u4DTYP : 4;
879 /** @name DCMD field, 8 bits (3.3.7.1).
880 * @{ */
881 /** End of packet. Note TSCTFC update. */
882 unsigned fEOP : 1;
883 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
884 unsigned fIFCS : 1;
885 /** Use the TSE context when set and the normal when clear. */
886 unsigned fTSE : 1;
887 /** Report status (dw3.STA). */
888 unsigned fRS : 1;
889 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
890 unsigned fRPS : 1;
891 /** Descriptor extension, must be set for this descriptor type. */
892 unsigned fDEXT : 1;
893 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
894 * Insert dw3.SPECIAL after ethernet header. */
895 unsigned fVLE : 1;
896 /** Interrupt delay enable. */
897 unsigned fIDE : 1;
898 /** @} */
899 } cmd;
900 struct TDDDw3_st
901 {
902 /** @name STA field (3.3.7.2)
903 * @{ */
904 unsigned fDD : 1; /**< Descriptor done. */
905 unsigned fEC : 1; /**< Excess collision. */
906 unsigned fLC : 1; /**< Late collision. */
907 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
908 unsigned fTURSV : 1;
909 /** @} */
910 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
911 /** @name POPTS (Packet Option) field (3.3.7.3)
912 * @{ */
913 unsigned fIXSM : 1; /**< Insert IP checksum. */
914 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
915 unsigned u6RSV : 6; /**< Reserved, MBZ. */
916 /** @} */
917 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
918 * Requires fEOP, fVLE and CTRL.VME to be set.
919 * @{ */
920 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
921 /** @} */
922 } dw3;
923};
924typedef struct E1kTDData E1KTXDAT;
925
926union E1kTxDesc
927{
928 struct E1kTDLegacy legacy;
929 struct E1kTDContext context;
930 struct E1kTDData data;
931};
932typedef union E1kTxDesc E1KTXDESC;
933AssertCompileSize(E1KTXDESC, 16);
934
935#define RA_CTL_AS 0x0003
936#define RA_CTL_AV 0x8000
937
938union E1kRecAddr
939{
940 uint32_t au32[32];
941 struct RAArray
942 {
943 uint8_t addr[6];
944 uint16_t ctl;
945 } array[16];
946};
947typedef struct E1kRecAddr::RAArray E1KRAELEM;
948typedef union E1kRecAddr E1KRA;
949AssertCompileSize(E1KRA, 8*16);
950
951#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
952#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
953#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
954#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
955
956/** @todo use+extend RTNETIPV4 */
957struct E1kIpHeader
958{
959 /* type of service / version / header length */
960 uint16_t tos_ver_hl;
961 /* total length */
962 uint16_t total_len;
963 /* identification */
964 uint16_t ident;
965 /* fragment offset field */
966 uint16_t offset;
967 /* time to live / protocol*/
968 uint16_t ttl_proto;
969 /* checksum */
970 uint16_t chksum;
971 /* source IP address */
972 uint32_t src;
973 /* destination IP address */
974 uint32_t dest;
975};
976AssertCompileSize(struct E1kIpHeader, 20);
977
978#define E1K_TCP_FIN UINT16_C(0x01)
979#define E1K_TCP_SYN UINT16_C(0x02)
980#define E1K_TCP_RST UINT16_C(0x04)
981#define E1K_TCP_PSH UINT16_C(0x08)
982#define E1K_TCP_ACK UINT16_C(0x10)
983#define E1K_TCP_URG UINT16_C(0x20)
984#define E1K_TCP_ECE UINT16_C(0x40)
985#define E1K_TCP_CWR UINT16_C(0x80)
986#define E1K_TCP_FLAGS UINT16_C(0x3f)
987
988/** @todo use+extend RTNETTCP */
989struct E1kTcpHeader
990{
991 uint16_t src;
992 uint16_t dest;
993 uint32_t seqno;
994 uint32_t ackno;
995 uint16_t hdrlen_flags;
996 uint16_t wnd;
997 uint16_t chksum;
998 uint16_t urgp;
999};
1000AssertCompileSize(struct E1kTcpHeader, 20);
1001
1002
1003#ifdef E1K_WITH_TXD_CACHE
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 4
1006/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1007# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1008#else /* !E1K_WITH_TXD_CACHE */
1009/** The current Saved state version. */
1010# define E1K_SAVEDSTATE_VERSION 3
1011#endif /* !E1K_WITH_TXD_CACHE */
1012/** Saved state version for VirtualBox 4.1 and earlier.
1013 * These did not include VLAN tag fields. */
1014#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1015/** Saved state version for VirtualBox 3.0 and earlier.
1016 * This did not include the configuration part nor the E1kEEPROM. */
1017#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1018
1019/**
1020 * E1000 shared device state.
1021 *
1022 * This is shared between ring-0 and ring-3.
1023 */
1024typedef struct E1KSTATE
1025{
1026 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1027
1028 /** Handle to PCI region \#0, the MMIO region. */
1029 IOMIOPORTHANDLE hMmioRegion;
1030 /** Handle to PCI region \#2, the I/O ports. */
1031 IOMIOPORTHANDLE hIoPorts;
1032
1033 /** Receive Interrupt Delay Timer. */
1034 TMTIMERHANDLE hRIDTimer;
1035 /** Receive Absolute Delay Timer. */
1036 TMTIMERHANDLE hRADTimer;
1037 /** Transmit Interrupt Delay Timer. */
1038 TMTIMERHANDLE hTIDTimer;
1039 /** Transmit Absolute Delay Timer. */
1040 TMTIMERHANDLE hTADTimer;
1041 /** Transmit Delay Timer. */
1042 TMTIMERHANDLE hTXDTimer;
1043 /** Late Interrupt Timer. */
1044 TMTIMERHANDLE hIntTimer;
1045 /** Link Up(/Restore) Timer. */
1046 TMTIMERHANDLE hLUTimer;
1047
1048 /** Transmit task. */
1049 PDMTASKHANDLE hTxTask;
1050
1051 /** Critical section - what is it protecting? */
1052 PDMCRITSECT cs;
1053 /** RX Critical section. */
1054 PDMCRITSECT csRx;
1055#ifdef E1K_WITH_TX_CS
1056 /** TX Critical section. */
1057 PDMCRITSECT csTx;
1058#endif /* E1K_WITH_TX_CS */
1059 /** MAC address obtained from the configuration. */
1060 RTMAC macConfigured;
1061 uint16_t u16Padding0;
1062 /** EMT: Last time the interrupt was acknowledged. */
1063 uint64_t u64AckedAt;
1064 /** All: Used for eliminating spurious interrupts. */
1065 bool fIntRaised;
1066 /** EMT: false if the cable is disconnected by the GUI. */
1067 bool fCableConnected;
1068 /** EMT: Compute Ethernet CRC for RX packets. */
1069 bool fEthernetCRC;
1070 /** All: throttle interrupts. */
1071 bool fItrEnabled;
1072 /** All: throttle RX interrupts. */
1073 bool fItrRxEnabled;
1074 /** All: Delay TX interrupts using TIDV/TADV. */
1075 bool fTidEnabled;
1076 bool afPadding[2];
1077 /** Link up delay (in milliseconds). */
1078 uint32_t cMsLinkUpDelay;
1079
1080 /** All: Device register storage. */
1081 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1082 /** TX/RX: Status LED. */
1083 PDMLED led;
1084 /** TX/RX: Number of packet being sent/received to show in debug log. */
1085 uint32_t u32PktNo;
1086
1087 /** EMT: Offset of the register to be read via IO. */
1088 uint32_t uSelectedReg;
1089 /** EMT: Multicast Table Array. */
1090 uint32_t auMTA[128];
1091 /** EMT: Receive Address registers. */
1092 E1KRA aRecAddr;
1093 /** EMT: VLAN filter table array. */
1094 uint32_t auVFTA[128];
1095 /** EMT: Receive buffer size. */
1096 uint16_t u16RxBSize;
1097 /** EMT: Locked state -- no state alteration possible. */
1098 bool fLocked;
1099 /** EMT: */
1100 bool fDelayInts;
1101 /** All: */
1102 bool fIntMaskUsed;
1103
1104 /** N/A: */
1105 bool volatile fMaybeOutOfSpace;
1106 /** EMT: Gets signalled when more RX descriptors become available. */
1107 SUPSEMEVENT hEventMoreRxDescAvail;
1108#ifdef E1K_WITH_RXD_CACHE
1109 /** RX: Fetched RX descriptors. */
1110 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1111 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1112 /** RX: Actual number of fetched RX descriptors. */
1113 uint32_t nRxDFetched;
1114 /** RX: Index in cache of RX descriptor being processed. */
1115 uint32_t iRxDCurrent;
1116#endif /* E1K_WITH_RXD_CACHE */
1117
1118 /** TX: Context used for TCP segmentation packets. */
1119 E1KTXCTX contextTSE;
1120 /** TX: Context used for ordinary packets. */
1121 E1KTXCTX contextNormal;
1122#ifdef E1K_WITH_TXD_CACHE
1123 /** TX: Fetched TX descriptors. */
1124 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1125 /** TX: Actual number of fetched TX descriptors. */
1126 uint8_t nTxDFetched;
1127 /** TX: Index in cache of TX descriptor being processed. */
1128 uint8_t iTxDCurrent;
1129 /** TX: Will this frame be sent as GSO. */
1130 bool fGSO;
1131 /** Alignment padding. */
1132 bool fReserved;
1133 /** TX: Number of bytes in next packet. */
1134 uint32_t cbTxAlloc;
1135
1136#endif /* E1K_WITH_TXD_CACHE */
1137 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1138 * applicable to the current TSE mode. */
1139 PDMNETWORKGSO GsoCtx;
1140 /** Scratch space for holding the loopback / fallback scatter / gather
1141 * descriptor. */
1142 union
1143 {
1144 PDMSCATTERGATHER Sg;
1145 uint8_t padding[8 * sizeof(RTUINTPTR)];
1146 } uTxFallback;
1147 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1148 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1149 /** TX: Number of bytes assembled in TX packet buffer. */
1150 uint16_t u16TxPktLen;
1151 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1152 bool fGSOEnabled;
1153 /** TX: IP checksum has to be inserted if true. */
1154 bool fIPcsum;
1155 /** TX: TCP/UDP checksum has to be inserted if true. */
1156 bool fTCPcsum;
1157 /** TX: VLAN tag has to be inserted if true. */
1158 bool fVTag;
1159 /** TX: TCI part of VLAN tag to be inserted. */
1160 uint16_t u16VTagTCI;
1161 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1162 uint32_t u32PayRemain;
1163 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1164 uint16_t u16HdrRemain;
1165 /** TX TSE fallback: Flags from template header. */
1166 uint16_t u16SavedFlags;
1167 /** TX TSE fallback: Partial checksum from template header. */
1168 uint32_t u32SavedCsum;
1169 /** ?: Emulated controller type. */
1170 E1KCHIP eChip;
1171
1172 /** EMT: Physical interface emulation. */
1173 PHY phy;
1174
1175#if 0
1176 /** Alignment padding. */
1177 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1178#endif
1179
1180 STAMCOUNTER StatReceiveBytes;
1181 STAMCOUNTER StatTransmitBytes;
1182#if defined(VBOX_WITH_STATISTICS)
1183 STAMPROFILEADV StatMMIOReadRZ;
1184 STAMPROFILEADV StatMMIOReadR3;
1185 STAMPROFILEADV StatMMIOWriteRZ;
1186 STAMPROFILEADV StatMMIOWriteR3;
1187 STAMPROFILEADV StatEEPROMRead;
1188 STAMPROFILEADV StatEEPROMWrite;
1189 STAMPROFILEADV StatIOReadRZ;
1190 STAMPROFILEADV StatIOReadR3;
1191 STAMPROFILEADV StatIOWriteRZ;
1192 STAMPROFILEADV StatIOWriteR3;
1193 STAMPROFILEADV StatLateIntTimer;
1194 STAMCOUNTER StatLateInts;
1195 STAMCOUNTER StatIntsRaised;
1196 STAMCOUNTER StatIntsPrevented;
1197 STAMPROFILEADV StatReceive;
1198 STAMPROFILEADV StatReceiveCRC;
1199 STAMPROFILEADV StatReceiveFilter;
1200 STAMPROFILEADV StatReceiveStore;
1201 STAMPROFILEADV StatTransmitRZ;
1202 STAMPROFILEADV StatTransmitR3;
1203 STAMPROFILE StatTransmitSendRZ;
1204 STAMPROFILE StatTransmitSendR3;
1205 STAMPROFILE StatRxOverflow;
1206 STAMCOUNTER StatRxOverflowWakeupRZ;
1207 STAMCOUNTER StatRxOverflowWakeupR3;
1208 STAMCOUNTER StatTxDescCtxNormal;
1209 STAMCOUNTER StatTxDescCtxTSE;
1210 STAMCOUNTER StatTxDescLegacy;
1211 STAMCOUNTER StatTxDescData;
1212 STAMCOUNTER StatTxDescTSEData;
1213 STAMCOUNTER StatTxPathFallback;
1214 STAMCOUNTER StatTxPathGSO;
1215 STAMCOUNTER StatTxPathRegular;
1216 STAMCOUNTER StatPHYAccesses;
1217 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1218 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1219#endif /* VBOX_WITH_STATISTICS */
1220
1221#ifdef E1K_INT_STATS
1222 /* Internal stats */
1223 uint64_t u64ArmedAt;
1224 uint64_t uStatMaxTxDelay;
1225 uint32_t uStatInt;
1226 uint32_t uStatIntTry;
1227 uint32_t uStatIntLower;
1228 uint32_t uStatNoIntICR;
1229 int32_t iStatIntLost;
1230 int32_t iStatIntLostOne;
1231 uint32_t uStatIntIMS;
1232 uint32_t uStatIntSkip;
1233 uint32_t uStatIntLate;
1234 uint32_t uStatIntMasked;
1235 uint32_t uStatIntEarly;
1236 uint32_t uStatIntRx;
1237 uint32_t uStatIntTx;
1238 uint32_t uStatIntICS;
1239 uint32_t uStatIntRDTR;
1240 uint32_t uStatIntRXDMT0;
1241 uint32_t uStatIntTXQE;
1242 uint32_t uStatTxNoRS;
1243 uint32_t uStatTxIDE;
1244 uint32_t uStatTxDelayed;
1245 uint32_t uStatTxDelayExp;
1246 uint32_t uStatTAD;
1247 uint32_t uStatTID;
1248 uint32_t uStatRAD;
1249 uint32_t uStatRID;
1250 uint32_t uStatRxFrm;
1251 uint32_t uStatTxFrm;
1252 uint32_t uStatDescCtx;
1253 uint32_t uStatDescDat;
1254 uint32_t uStatDescLeg;
1255 uint32_t uStatTx1514;
1256 uint32_t uStatTx2962;
1257 uint32_t uStatTx4410;
1258 uint32_t uStatTx5858;
1259 uint32_t uStatTx7306;
1260 uint32_t uStatTx8754;
1261 uint32_t uStatTx16384;
1262 uint32_t uStatTx32768;
1263 uint32_t uStatTxLarge;
1264 uint32_t uStatAlign;
1265#endif /* E1K_INT_STATS */
1266} E1KSTATE;
1267/** Pointer to the E1000 device state. */
1268typedef E1KSTATE *PE1KSTATE;
1269
1270/**
1271 * E1000 ring-3 device state
1272 *
1273 * @implements PDMINETWORKDOWN
1274 * @implements PDMINETWORKCONFIG
1275 * @implements PDMILEDPORTS
1276 */
1277typedef struct E1KSTATER3
1278{
1279 PDMIBASE IBase;
1280 PDMINETWORKDOWN INetworkDown;
1281 PDMINETWORKCONFIG INetworkConfig;
1282 /** LED interface */
1283 PDMILEDPORTS ILeds;
1284 /** Attached network driver. */
1285 R3PTRTYPE(PPDMIBASE) pDrvBase;
1286 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1287
1288 /** Pointer to the shared state. */
1289 R3PTRTYPE(PE1KSTATE) pShared;
1290
1291 /** Device instance. */
1292 PPDMDEVINSR3 pDevInsR3;
1293 /** Attached network driver. */
1294 PPDMINETWORKUPR3 pDrvR3;
1295 /** The scatter / gather buffer used for the current outgoing packet. */
1296 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1297
1298 /** EMT: EEPROM emulation */
1299 E1kEEPROM eeprom;
1300} E1KSTATER3;
1301/** Pointer to the E1000 ring-3 device state. */
1302typedef E1KSTATER3 *PE1KSTATER3;
1303
1304
1305/**
1306 * E1000 ring-0 device state
1307 */
1308typedef struct E1KSTATER0
1309{
1310 /** Device instance. */
1311 PPDMDEVINSR0 pDevInsR0;
1312 /** Attached network driver. */
1313 PPDMINETWORKUPR0 pDrvR0;
1314 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1315 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1316} E1KSTATER0;
1317/** Pointer to the E1000 ring-0 device state. */
1318typedef E1KSTATER0 *PE1KSTATER0;
1319
1320
1321/**
1322 * E1000 raw-mode device state
1323 */
1324typedef struct E1KSTATERC
1325{
1326 /** Device instance. */
1327 PPDMDEVINSRC pDevInsRC;
1328 /** Attached network driver. */
1329 PPDMINETWORKUPRC pDrvRC;
1330 /** The scatter / gather buffer used for the current outgoing packet. */
1331 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1332} E1KSTATERC;
1333/** Pointer to the E1000 raw-mode device state. */
1334typedef E1KSTATERC *PE1KSTATERC;
1335
1336
1337/** @def PE1KSTATECC
1338 * Pointer to the instance data for the current context. */
1339#ifdef IN_RING3
1340typedef E1KSTATER3 E1KSTATECC;
1341typedef PE1KSTATER3 PE1KSTATECC;
1342#elif defined(IN_RING0)
1343typedef E1KSTATER0 E1KSTATECC;
1344typedef PE1KSTATER0 PE1KSTATECC;
1345#elif defined(IN_RC)
1346typedef E1KSTATERC E1KSTATECC;
1347typedef PE1KSTATERC PE1KSTATECC;
1348#else
1349# error "Not IN_RING3, IN_RING0 or IN_RC"
1350#endif
1351
1352
1353#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1354
1355/* Forward declarations ******************************************************/
1356static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1357
1358/**
1359 * E1000 register read handler.
1360 */
1361typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1362/**
1363 * E1000 register write handler.
1364 */
1365typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1366
1367static FNE1KREGREAD e1kRegReadUnimplemented;
1368static FNE1KREGWRITE e1kRegWriteUnimplemented;
1369static FNE1KREGREAD e1kRegReadAutoClear;
1370static FNE1KREGREAD e1kRegReadDefault;
1371static FNE1KREGWRITE e1kRegWriteDefault;
1372#if 0 /* unused */
1373static FNE1KREGREAD e1kRegReadCTRL;
1374#endif
1375static FNE1KREGWRITE e1kRegWriteCTRL;
1376static FNE1KREGREAD e1kRegReadEECD;
1377static FNE1KREGWRITE e1kRegWriteEECD;
1378static FNE1KREGWRITE e1kRegWriteEERD;
1379static FNE1KREGWRITE e1kRegWriteMDIC;
1380static FNE1KREGREAD e1kRegReadICR;
1381static FNE1KREGWRITE e1kRegWriteICR;
1382static FNE1KREGWRITE e1kRegWriteICS;
1383static FNE1KREGWRITE e1kRegWriteIMS;
1384static FNE1KREGWRITE e1kRegWriteIMC;
1385static FNE1KREGWRITE e1kRegWriteRCTL;
1386static FNE1KREGWRITE e1kRegWritePBA;
1387static FNE1KREGWRITE e1kRegWriteRDT;
1388static FNE1KREGWRITE e1kRegWriteRDTR;
1389static FNE1KREGWRITE e1kRegWriteTDT;
1390static FNE1KREGREAD e1kRegReadMTA;
1391static FNE1KREGWRITE e1kRegWriteMTA;
1392static FNE1KREGREAD e1kRegReadRA;
1393static FNE1KREGWRITE e1kRegWriteRA;
1394static FNE1KREGREAD e1kRegReadVFTA;
1395static FNE1KREGWRITE e1kRegWriteVFTA;
1396
1397/**
1398 * Register map table.
1399 *
1400 * Override pfnRead and pfnWrite to get register-specific behavior.
1401 */
1402static const struct E1kRegMap_st
1403{
1404 /** Register offset in the register space. */
1405 uint32_t offset;
1406 /** Size in bytes. Registers of size > 4 are in fact tables. */
1407 uint32_t size;
1408 /** Readable bits. */
1409 uint32_t readable;
1410 /** Writable bits. */
1411 uint32_t writable;
1412 /** Read callback. */
1413 FNE1KREGREAD *pfnRead;
1414 /** Write callback. */
1415 FNE1KREGWRITE *pfnWrite;
1416 /** Abbreviated name. */
1417 const char *abbrev;
1418 /** Full name. */
1419 const char *name;
1420} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1421{
1422 /* offset size read mask write mask read callback write callback abbrev full name */
1423 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1424 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1425 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1426 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1427 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1428 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1429 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1430 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1431 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1432 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1433 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1434 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1435 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1436 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1437 { 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1438 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1439 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1440 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1441 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1442 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1443 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1444 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1445 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1446 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1447 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1448 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1449 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1450 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1451 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1452 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1453 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1454 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1455 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1456 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1457 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1458 { 0x02808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1459 { 0x02810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1460 { 0x02818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1461 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1462 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1463 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1464 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1465 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1466 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1467 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1468 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1469 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1470 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1471 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1472 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1473 { 0x03808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1474 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1475 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1476 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1477 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1478 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1479 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1480 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1481 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1482 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1483 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1484 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1485 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1486 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1487 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1488 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1489 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1490 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1491 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1492 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1493 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1494 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1495 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1496 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1497 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1498 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1499 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1500 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1501 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1502 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1503 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1504 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1505 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1506 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1507 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1508 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1509 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1510 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1511 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1512 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1513 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1514 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1515 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1516 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1517 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1518 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1519 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1520 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1521 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1522 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1523 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1524 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1525 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1526 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1527 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1528 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1529 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1530 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1531 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1532 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1533 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1534 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1535 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1536 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1537 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1538 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1539 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1540 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1541 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1542 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1543 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1544 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1545 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1546 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1547 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1548 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1549 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1550 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1551 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1552 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1553 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1554 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1555 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1556 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1557 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1558};
1559
1560#ifdef LOG_ENABLED
1561
1562/**
1563 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1564 *
1565 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1566 *
1567 * @returns The buffer.
1568 *
1569 * @param u32 The word to convert into string.
1570 * @param mask Selects which bytes to convert.
1571 * @param buf Where to put the result.
1572 */
1573static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1574{
1575 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1576 {
1577 if (mask & 0xF)
1578 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1579 else
1580 *ptr = '.';
1581 }
1582 buf[8] = 0;
1583 return buf;
1584}
1585
1586/**
1587 * Returns timer name for debug purposes.
1588 *
1589 * @returns The timer name.
1590 *
1591 * @param pThis The device state structure.
1592 * @param hTimer The timer to name.
1593 */
1594DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1595{
1596 if (hTimer == pThis->hTIDTimer)
1597 return "TID";
1598 if (hTimer == pThis->hTADTimer)
1599 return "TAD";
1600 if (hTimer == pThis->hRIDTimer)
1601 return "RID";
1602 if (hTimer == pThis->hRADTimer)
1603 return "RAD";
1604 if (hTimer == pThis->hIntTimer)
1605 return "Int";
1606 if (hTimer == pThis->hTXDTimer)
1607 return "TXD";
1608 if (hTimer == pThis->hLUTimer)
1609 return "LinkUp";
1610 return "unknown";
1611}
1612
1613#endif /* LOG_ENABLED */
1614
1615/**
1616 * Arm a timer.
1617 *
1618 * @param pDevIns The device instance.
1619 * @param pThis Pointer to the device state structure.
1620 * @param hTimer The timer to arm.
1621 * @param uExpireIn Expiration interval in microseconds.
1622 */
1623DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1624{
1625 if (pThis->fLocked)
1626 return;
1627
1628 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1629 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1630 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1631 AssertRC(rc);
1632}
1633
1634#ifdef IN_RING3
1635/**
1636 * Cancel a timer.
1637 *
1638 * @param pDevIns The device instance.
1639 * @param pThis Pointer to the device state structure.
1640 * @param pTimer Pointer to the timer.
1641 */
1642DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1643{
1644 E1kLog2(("%s Stopping %s timer...\n",
1645 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1646 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1647 if (RT_FAILURE(rc))
1648 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1649 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1650 RT_NOREF_PV(pThis);
1651}
1652#endif /* IN_RING3 */
1653
1654#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1655#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1656
1657#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1658#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1659#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1660
1661#ifndef E1K_WITH_TX_CS
1662# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1663# define e1kCsTxLeave(ps) do { } while (0)
1664#else /* E1K_WITH_TX_CS */
1665# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1666# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1667# define e1kCsTxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csTx)
1668#endif /* E1K_WITH_TX_CS */
1669
1670
1671#ifdef E1K_WITH_TXD_CACHE
1672/*
1673 * Transmit Descriptor Register Context
1674 */
1675struct E1kTxDContext
1676{
1677 uint32_t tdlen;
1678 uint32_t tdh;
1679 uint32_t tdt;
1680};
1681typedef struct E1kTxDContext E1KTXDC, *PE1KTXDC;
1682
1683DECLINLINE(bool) e1kUpdateTxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pContext)
1684{
1685 Assert(e1kCsTxIsOwner(pThis));
1686 if (!e1kCsTxIsOwner(pThis))
1687 {
1688 memset(pContext, 0, sizeof(E1KTXDC));
1689 return false;
1690 }
1691 pContext->tdlen = TDLEN;
1692 pContext->tdh = TDH;
1693 pContext->tdt = TDT;
1694 uint32_t cTxRingSize = pContext->tdlen / sizeof(E1KTXDESC);
1695#ifdef DEBUG
1696 if (pContext->tdh >= cTxRingSize)
1697 {
1698 Log(("%s e1kUpdateTxDContext: will return false because TDH too big (%u >= %u)\n",
1699 pThis->szPrf, pContext->tdh, cTxRingSize));
1700 return VINF_SUCCESS;
1701 }
1702 if (pContext->tdt >= cTxRingSize)
1703 {
1704 Log(("%s e1kUpdateTxDContext: will return false because TDT too big (%u >= %u)\n",
1705 pThis->szPrf, pContext->tdt, cTxRingSize));
1706 return VINF_SUCCESS;
1707 }
1708#endif /* DEBUG */
1709 return pContext->tdh < cTxRingSize && pContext->tdt < cTxRingSize;
1710}
1711#endif /* E1K_WITH_TXD_CACHE */
1712#ifdef E1K_WITH_RXD_CACHE
1713/*
1714 * Receive Descriptor Register Context
1715 */
1716struct E1kRxDContext
1717{
1718 uint32_t rdlen;
1719 uint32_t rdh;
1720 uint32_t rdt;
1721};
1722typedef struct E1kRxDContext E1KRXDC, *PE1KRXDC;
1723
1724DECLINLINE(bool) e1kUpdateRxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pContext, const char *pcszCallee)
1725{
1726 Assert(e1kCsRxIsOwner(pThis));
1727 if (!e1kCsRxIsOwner(pThis))
1728 return false;
1729 pContext->rdlen = RDLEN;
1730 pContext->rdh = RDH;
1731 pContext->rdt = RDT;
1732 uint32_t cRxRingSize = pContext->rdlen / sizeof(E1KRXDESC);
1733#ifdef DEBUG
1734 if (pContext->rdh >= cRxRingSize)
1735 {
1736 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDH too big (%u >= %u)\n",
1737 pThis->szPrf, pcszCallee, pContext->rdh, cRxRingSize));
1738 return VINF_SUCCESS;
1739 }
1740 if (pContext->rdt >= cRxRingSize)
1741 {
1742 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDT too big (%u >= %u)\n",
1743 pThis->szPrf, pcszCallee, pContext->rdt, cRxRingSize));
1744 return VINF_SUCCESS;
1745 }
1746#else /* !DEBUG */
1747 RT_NOREF(pcszCallee);
1748#endif /* !DEBUG */
1749 return pContext->rdh < cRxRingSize && pContext->rdt < cRxRingSize; // && (RCTL & RCTL_EN);
1750}
1751#endif /* E1K_WITH_RXD_CACHE */
1752
1753/**
1754 * Wakeup the RX thread.
1755 */
1756static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1757{
1758 if ( pThis->fMaybeOutOfSpace
1759 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1760 {
1761 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1762 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1763 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1764 AssertRC(rc);
1765 }
1766}
1767
1768#ifdef IN_RING3
1769
1770/**
1771 * Hardware reset. Revert all registers to initial values.
1772 *
1773 * @param pDevIns The device instance.
1774 * @param pThis The device state structure.
1775 * @param pThisCC The current context instance data.
1776 */
1777static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1778{
1779 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1780 /* No interrupts should survive device reset, see @bugref(9556). */
1781 if (pThis->fIntRaised)
1782 {
1783 /* Lower(0) INTA(0) */
1784 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1785 pThis->fIntRaised = false;
1786 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1787 }
1788 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1789 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1790#ifdef E1K_INIT_RA0
1791 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1792 sizeof(pThis->macConfigured.au8));
1793 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1794#endif /* E1K_INIT_RA0 */
1795 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1796 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1797 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1798 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1799 Assert(GET_BITS(RCTL, BSIZE) == 0);
1800 pThis->u16RxBSize = 2048;
1801
1802 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1803 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1804 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1805
1806 /* Reset promiscuous mode */
1807 if (pThisCC->pDrvR3)
1808 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1809
1810#ifdef E1K_WITH_TXD_CACHE
1811 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1812 if (RT_LIKELY(rc == VINF_SUCCESS))
1813 {
1814 pThis->nTxDFetched = 0;
1815 pThis->iTxDCurrent = 0;
1816 pThis->fGSO = false;
1817 pThis->cbTxAlloc = 0;
1818 e1kCsTxLeave(pThis);
1819 }
1820#endif /* E1K_WITH_TXD_CACHE */
1821#ifdef E1K_WITH_RXD_CACHE
1822 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1823 {
1824 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1825 e1kCsRxLeave(pThis);
1826 }
1827#endif /* E1K_WITH_RXD_CACHE */
1828#ifdef E1K_LSC_ON_RESET
1829 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1830 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1831 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1832#endif /* E1K_LSC_ON_RESET */
1833}
1834
1835#endif /* IN_RING3 */
1836
1837/**
1838 * Compute Internet checksum.
1839 *
1840 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1841 *
1842 * @param pThis The device state structure.
1843 * @param cpPacket The packet.
1844 * @param cb The size of the packet.
1845 * @param pszText A string denoting direction of packet transfer.
1846 *
1847 * @return The 1's complement of the 1's complement sum.
1848 *
1849 * @thread E1000_TX
1850 */
1851static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1852{
1853 uint32_t csum = 0;
1854 uint16_t *pu16 = (uint16_t *)pvBuf;
1855
1856 while (cb > 1)
1857 {
1858 csum += *pu16++;
1859 cb -= 2;
1860 }
1861 if (cb)
1862 csum += *(uint8_t*)pu16;
1863 while (csum >> 16)
1864 csum = (csum >> 16) + (csum & 0xFFFF);
1865 Assert(csum < 65536);
1866 return (uint16_t)~csum;
1867}
1868
1869/**
1870 * Dump a packet to debug log.
1871 *
1872 * @param pDevIns The device instance.
1873 * @param pThis The device state structure.
1874 * @param cpPacket The packet.
1875 * @param cb The size of the packet.
1876 * @param pszText A string denoting direction of packet transfer.
1877 * @thread E1000_TX
1878 */
1879DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1880{
1881#ifdef DEBUG
1882 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1883 {
1884 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1885 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1886 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1887 {
1888 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1889 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1890 if (*(cpPacket+14+6) == 0x6)
1891 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1892 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1893 }
1894 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1895 {
1896 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1897 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1898 if (*(cpPacket+14+6) == 0x6)
1899 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1900 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1901 }
1902 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1903 e1kCsLeave(pThis);
1904 }
1905#else
1906 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1907 {
1908 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1909 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1910 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1911 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1912 else
1913 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1914 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1915 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1916 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1917 e1kCsLeave(pThis);
1918 }
1919 RT_NOREF2(cb, pszText);
1920#endif
1921}
1922
1923/**
1924 * Determine the type of transmit descriptor.
1925 *
1926 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1927 *
1928 * @param pDesc Pointer to descriptor union.
1929 * @thread E1000_TX
1930 */
1931DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1932{
1933 if (pDesc->legacy.cmd.fDEXT)
1934 return pDesc->context.dw2.u4DTYP;
1935 return E1K_DTYP_LEGACY;
1936}
1937
1938
1939#ifdef E1K_WITH_RXD_CACHE
1940/**
1941 * Return the number of RX descriptor that belong to the hardware.
1942 *
1943 * @returns the number of available descriptors in RX ring.
1944 * @param pRxdc The receive descriptor register context.
1945 * @thread ???
1946 */
1947DECLINLINE(uint32_t) e1kGetRxLen(PE1KRXDC pRxdc)
1948{
1949 /**
1950 * Make sure RDT won't change during computation. EMT may modify RDT at
1951 * any moment.
1952 */
1953 uint32_t rdt = pRxdc->rdt;
1954 return (pRxdc->rdh > rdt ? pRxdc->rdlen/sizeof(E1KRXDESC) : 0) + rdt - pRxdc->rdh;
1955}
1956
1957DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1958{
1959 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1960 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1961}
1962
1963DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1964{
1965 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1966}
1967
1968/**
1969 * Load receive descriptors from guest memory. The caller needs to be in Rx
1970 * critical section.
1971 *
1972 * We need two physical reads in case the tail wrapped around the end of RX
1973 * descriptor ring.
1974 *
1975 * @returns the actual number of descriptors fetched.
1976 * @param pDevIns The device instance.
1977 * @param pThis The device state structure.
1978 * @thread EMT, RX
1979 */
1980DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
1981{
1982 E1kLog3(("%s e1kRxDPrefetch: RDH=%x RDT=%x RDLEN=%x "
1983 "iRxDCurrent=%x nRxDFetched=%x\n",
1984 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pRxdc->rdlen, pThis->iRxDCurrent, pThis->nRxDFetched));
1985 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1986 unsigned nDescsAvailable = e1kGetRxLen(pRxdc) - e1kRxDInCache(pThis);
1987 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1988 unsigned nDescsTotal = pRxdc->rdlen / sizeof(E1KRXDESC);
1989 Assert(nDescsTotal != 0);
1990 if (nDescsTotal == 0)
1991 return 0;
1992 unsigned nFirstNotLoaded = (pRxdc->rdh + e1kRxDInCache(pThis)) % nDescsTotal;
1993 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
1994 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
1995 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
1996 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
1997 nFirstNotLoaded, nDescsInSingleRead));
1998 if (nDescsToFetch == 0)
1999 return 0;
2000 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2001 PDMDevHlpPCIPhysRead(pDevIns,
2002 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2003 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2004 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2005 // unsigned i, j;
2006 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2007 // {
2008 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2009 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2010 // }
2011 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2012 pThis->szPrf, nDescsInSingleRead,
2013 RDBAH, RDBAL + pRxdc->rdh * sizeof(E1KRXDESC),
2014 nFirstNotLoaded, pRxdc->rdlen, pRxdc->rdh, pRxdc->rdt));
2015 if (nDescsToFetch > nDescsInSingleRead)
2016 {
2017 PDMDevHlpPCIPhysRead(pDevIns,
2018 ((uint64_t)RDBAH << 32) + RDBAL,
2019 pFirstEmptyDesc + nDescsInSingleRead,
2020 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2021 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2022 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2023 // {
2024 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2025 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2026 // }
2027 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2028 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2029 RDBAH, RDBAL));
2030 }
2031 pThis->nRxDFetched += nDescsToFetch;
2032 return nDescsToFetch;
2033}
2034
2035# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2036/**
2037 * Dump receive descriptor to debug log.
2038 *
2039 * @param pThis The device state structure.
2040 * @param pDesc Pointer to the descriptor.
2041 * @thread E1000_RX
2042 */
2043static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
2044{
2045 RT_NOREF2(pThis, pDesc);
2046 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
2047 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
2048 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
2049 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
2050 pDesc->status.fPIF ? "PIF" : "pif",
2051 pDesc->status.fIPCS ? "IPCS" : "ipcs",
2052 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
2053 pDesc->status.fVP ? "VP" : "vp",
2054 pDesc->status.fIXSM ? "IXSM" : "ixsm",
2055 pDesc->status.fEOP ? "EOP" : "eop",
2056 pDesc->status.fDD ? "DD" : "dd",
2057 pDesc->status.fRXE ? "RXE" : "rxe",
2058 pDesc->status.fIPE ? "IPE" : "ipe",
2059 pDesc->status.fTCPE ? "TCPE" : "tcpe",
2060 pDesc->status.fCE ? "CE" : "ce",
2061 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
2062 E1K_SPEC_VLAN(pDesc->status.u16Special),
2063 E1K_SPEC_PRI(pDesc->status.u16Special)));
2064}
2065# endif /* IN_RING3 */
2066#endif /* E1K_WITH_RXD_CACHE */
2067
2068/**
2069 * Dump transmit descriptor to debug log.
2070 *
2071 * @param pThis The device state structure.
2072 * @param pDesc Pointer to descriptor union.
2073 * @param pszDir A string denoting direction of descriptor transfer
2074 * @thread E1000_TX
2075 */
2076static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
2077 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
2078{
2079 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
2080
2081 /*
2082 * Unfortunately we cannot use our format handler here, we want R0 logging
2083 * as well.
2084 */
2085 switch (e1kGetDescType(pDesc))
2086 {
2087 case E1K_DTYP_CONTEXT:
2088 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2089 pThis->szPrf, pszDir, pszDir));
2090 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2091 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2092 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2093 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2094 pDesc->context.dw2.fIDE ? " IDE":"",
2095 pDesc->context.dw2.fRS ? " RS" :"",
2096 pDesc->context.dw2.fTSE ? " TSE":"",
2097 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2098 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2099 pDesc->context.dw2.u20PAYLEN,
2100 pDesc->context.dw3.u8HDRLEN,
2101 pDesc->context.dw3.u16MSS,
2102 pDesc->context.dw3.fDD?"DD":""));
2103 break;
2104 case E1K_DTYP_DATA:
2105 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2106 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2107 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2108 pDesc->data.u64BufAddr,
2109 pDesc->data.cmd.u20DTALEN));
2110 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2111 pDesc->data.cmd.fIDE ? " IDE" :"",
2112 pDesc->data.cmd.fVLE ? " VLE" :"",
2113 pDesc->data.cmd.fRPS ? " RPS" :"",
2114 pDesc->data.cmd.fRS ? " RS" :"",
2115 pDesc->data.cmd.fTSE ? " TSE" :"",
2116 pDesc->data.cmd.fIFCS? " IFCS":"",
2117 pDesc->data.cmd.fEOP ? " EOP" :"",
2118 pDesc->data.dw3.fDD ? " DD" :"",
2119 pDesc->data.dw3.fEC ? " EC" :"",
2120 pDesc->data.dw3.fLC ? " LC" :"",
2121 pDesc->data.dw3.fTXSM? " TXSM":"",
2122 pDesc->data.dw3.fIXSM? " IXSM":"",
2123 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2124 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2125 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2126 break;
2127 case E1K_DTYP_LEGACY:
2128 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2129 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2130 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2131 pDesc->data.u64BufAddr,
2132 pDesc->legacy.cmd.u16Length));
2133 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2134 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2135 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2136 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2137 pDesc->legacy.cmd.fRS ? " RS" :"",
2138 pDesc->legacy.cmd.fIC ? " IC" :"",
2139 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2140 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2141 pDesc->legacy.dw3.fDD ? " DD" :"",
2142 pDesc->legacy.dw3.fEC ? " EC" :"",
2143 pDesc->legacy.dw3.fLC ? " LC" :"",
2144 pDesc->legacy.cmd.u8CSO,
2145 pDesc->legacy.dw3.u8CSS,
2146 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2147 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2148 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2149 break;
2150 default:
2151 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2152 pThis->szPrf, pszDir, pszDir));
2153 break;
2154 }
2155}
2156
2157/**
2158 * Raise an interrupt later.
2159 *
2160 * @param pThis The device state structure.
2161 */
2162DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2163{
2164 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2165 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2166}
2167
2168/**
2169 * Raise interrupt if not masked.
2170 *
2171 * @param pThis The device state structure.
2172 */
2173static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause)
2174{
2175 int rc = e1kCsEnter(pThis, rcBusy);
2176 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2177 return rc;
2178
2179 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2180 ICR |= u32IntCause;
2181 if (ICR & IMS)
2182 {
2183 if (pThis->fIntRaised)
2184 {
2185 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2186 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2187 pThis->szPrf, ICR & IMS));
2188 }
2189 else
2190 {
2191 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2192 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2193 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2194 {
2195 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2196 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2197 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2198 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2199 }
2200 else
2201 {
2202
2203 /* Since we are delivering the interrupt now
2204 * there is no need to do it later -- stop the timer.
2205 */
2206 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2207 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2208 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2209 /* Got at least one unmasked interrupt cause */
2210 pThis->fIntRaised = true;
2211 /* Raise(1) INTA(0) */
2212 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2213 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2214 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2215 pThis->szPrf, ICR & IMS));
2216 }
2217 }
2218 }
2219 else
2220 {
2221 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2222 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2223 pThis->szPrf, ICR, IMS));
2224 }
2225 e1kCsLeave(pThis);
2226 return VINF_SUCCESS;
2227}
2228
2229/**
2230 * Compute the physical address of the descriptor.
2231 *
2232 * @returns the physical address of the descriptor.
2233 *
2234 * @param baseHigh High-order 32 bits of descriptor table address.
2235 * @param baseLow Low-order 32 bits of descriptor table address.
2236 * @param idxDesc The descriptor index in the table.
2237 */
2238DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2239{
2240 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2241 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2242}
2243
2244#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2245/**
2246 * Advance the head pointer of the receive descriptor queue.
2247 *
2248 * @remarks RDH always points to the next available RX descriptor.
2249 *
2250 * @param pDevIns The device instance.
2251 * @param pThis The device state structure.
2252 */
2253DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2254{
2255 Assert(e1kCsRxIsOwner(pThis));
2256 //e1kCsEnter(pThis, RT_SRC_POS);
2257 if (++pRxdc->rdh * sizeof(E1KRXDESC) >= pRxdc->rdlen)
2258 pRxdc->rdh = 0;
2259 RDH = pRxdc->rdh; /* Sync the actual register and RXDC */
2260#ifdef E1K_WITH_RXD_CACHE
2261 /*
2262 * We need to fetch descriptors now as the guest may advance RDT all the way
2263 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2264 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2265 * check if the receiver is enabled. It must be, otherwise we won't get here
2266 * in the first place.
2267 *
2268 * Note that we should have moved both RDH and iRxDCurrent by now.
2269 */
2270 if (e1kRxDIsCacheEmpty(pThis))
2271 {
2272 /* Cache is empty, reset it and check if we can fetch more. */
2273 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2274 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2275 "iRxDCurrent=%x nRxDFetched=%x\n",
2276 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pThis->iRxDCurrent, pThis->nRxDFetched));
2277 e1kRxDPrefetch(pDevIns, pThis, pRxdc);
2278 }
2279#endif /* E1K_WITH_RXD_CACHE */
2280 /*
2281 * Compute current receive queue length and fire RXDMT0 interrupt
2282 * if we are low on receive buffers
2283 */
2284 uint32_t uRQueueLen = pRxdc->rdh>pRxdc->rdt ? pRxdc->rdlen/sizeof(E1KRXDESC)-pRxdc->rdh+pRxdc->rdt : pRxdc->rdt-pRxdc->rdh;
2285 /*
2286 * The minimum threshold is controlled by RDMTS bits of RCTL:
2287 * 00 = 1/2 of RDLEN
2288 * 01 = 1/4 of RDLEN
2289 * 10 = 1/8 of RDLEN
2290 * 11 = reserved
2291 */
2292 uint32_t uMinRQThreshold = pRxdc->rdlen / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2293 if (uRQueueLen <= uMinRQThreshold)
2294 {
2295 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2296 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2297 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2298 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2299 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2300 }
2301 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2302 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen));
2303 //e1kCsLeave(pThis);
2304}
2305#endif /* IN_RING3 */
2306
2307#ifdef E1K_WITH_RXD_CACHE
2308
2309# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2310
2311/**
2312 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2313 * RX ring if the cache is empty.
2314 *
2315 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2316 * go out of sync with RDH which will cause trouble when EMT checks if the
2317 * cache is empty to do pre-fetch @bugref(6217).
2318 *
2319 * @param pDevIns The device instance.
2320 * @param pThis The device state structure.
2321 * @thread RX
2322 */
2323DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2324{
2325 Assert(e1kCsRxIsOwner(pThis));
2326 /* Check the cache first. */
2327 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2328 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2329 /* Cache is empty, reset it and check if we can fetch more. */
2330 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2331 if (e1kRxDPrefetch(pDevIns, pThis, pRxdc))
2332 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2333 /* Out of Rx descriptors. */
2334 return NULL;
2335}
2336
2337
2338/**
2339 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2340 * pointer. The descriptor gets written back to the RXD ring.
2341 *
2342 * @param pDevIns The device instance.
2343 * @param pThis The device state structure.
2344 * @param pDesc The descriptor being "returned" to the RX ring.
2345 * @thread RX
2346 */
2347DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc, PE1KRXDC pRxdc)
2348{
2349 Assert(e1kCsRxIsOwner(pThis));
2350 pThis->iRxDCurrent++;
2351 // Assert(pDesc >= pThis->aRxDescriptors);
2352 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2353 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2354 // uint32_t rdh = RDH;
2355 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2356 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, pRxdc->rdh), pDesc, sizeof(E1KRXDESC));
2357 /*
2358 * We need to print the descriptor before advancing RDH as it may fetch new
2359 * descriptors into the cache.
2360 */
2361 e1kPrintRDesc(pThis, pDesc);
2362 e1kAdvanceRDH(pDevIns, pThis, pRxdc);
2363}
2364
2365/**
2366 * Store a fragment of received packet at the specifed address.
2367 *
2368 * @param pDevIns The device instance.
2369 * @param pThis The device state structure.
2370 * @param pDesc The next available RX descriptor.
2371 * @param pvBuf The fragment.
2372 * @param cb The size of the fragment.
2373 */
2374static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2375{
2376 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2377 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2378 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2379 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2380 pDesc->u16Length = (uint16_t)cb;
2381 Assert(pDesc->u16Length == cb);
2382 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2383 RT_NOREF(pThis);
2384}
2385
2386# endif /* IN_RING3 */
2387
2388#else /* !E1K_WITH_RXD_CACHE */
2389
2390/**
2391 * Store a fragment of received packet that fits into the next available RX
2392 * buffer.
2393 *
2394 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2395 *
2396 * @param pDevIns The device instance.
2397 * @param pThis The device state structure.
2398 * @param pDesc The next available RX descriptor.
2399 * @param pvBuf The fragment.
2400 * @param cb The size of the fragment.
2401 */
2402static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2403{
2404 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2405 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2406 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2407 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2408 /* Write back the descriptor */
2409 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2410 e1kPrintRDesc(pThis, pDesc);
2411 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2412 /* Advance head */
2413 e1kAdvanceRDH(pDevIns, pThis);
2414 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2415 if (pDesc->status.fEOP)
2416 {
2417 /* Complete packet has been stored -- it is time to let the guest know. */
2418#ifdef E1K_USE_RX_TIMERS
2419 if (RDTR)
2420 {
2421 /* Arm the timer to fire in RDTR usec (discard .024) */
2422 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2423 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2424 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2425 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2426 }
2427 else
2428 {
2429#endif
2430 /* 0 delay means immediate interrupt */
2431 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2432 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2433#ifdef E1K_USE_RX_TIMERS
2434 }
2435#endif
2436 }
2437 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2438}
2439
2440#endif /* !E1K_WITH_RXD_CACHE */
2441
2442/**
2443 * Returns true if it is a broadcast packet.
2444 *
2445 * @returns true if destination address indicates broadcast.
2446 * @param pvBuf The ethernet packet.
2447 */
2448DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2449{
2450 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2451 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2452}
2453
2454/**
2455 * Returns true if it is a multicast packet.
2456 *
2457 * @remarks returns true for broadcast packets as well.
2458 * @returns true if destination address indicates multicast.
2459 * @param pvBuf The ethernet packet.
2460 */
2461DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2462{
2463 return (*(char*)pvBuf) & 1;
2464}
2465
2466#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2467/**
2468 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2469 *
2470 * @remarks We emulate checksum offloading for major packets types only.
2471 *
2472 * @returns VBox status code.
2473 * @param pThis The device state structure.
2474 * @param pFrame The available data.
2475 * @param cb Number of bytes available in the buffer.
2476 * @param status Bit fields containing status info.
2477 */
2478static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2479{
2480 /** @todo
2481 * It is not safe to bypass checksum verification for packets coming
2482 * from real wire. We currently unable to tell where packets are
2483 * coming from so we tell the driver to ignore our checksum flags
2484 * and do verification in software.
2485 */
2486# if 0
2487 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2488
2489 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2490
2491 switch (uEtherType)
2492 {
2493 case 0x800: /* IPv4 */
2494 {
2495 pStatus->fIXSM = false;
2496 pStatus->fIPCS = true;
2497 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2498 /* TCP/UDP checksum offloading works with TCP and UDP only */
2499 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2500 break;
2501 }
2502 case 0x86DD: /* IPv6 */
2503 pStatus->fIXSM = false;
2504 pStatus->fIPCS = false;
2505 pStatus->fTCPCS = true;
2506 break;
2507 default: /* ARP, VLAN, etc. */
2508 pStatus->fIXSM = true;
2509 break;
2510 }
2511# else
2512 pStatus->fIXSM = true;
2513 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2514# endif
2515 return VINF_SUCCESS;
2516}
2517#endif /* IN_RING3 */
2518
2519/**
2520 * Pad and store received packet.
2521 *
2522 * @remarks Make sure that the packet appears to upper layer as one coming
2523 * from real Ethernet: pad it and insert FCS.
2524 *
2525 * @returns VBox status code.
2526 * @param pDevIns The device instance.
2527 * @param pThis The device state structure.
2528 * @param pvBuf The available data.
2529 * @param cb Number of bytes available in the buffer.
2530 * @param status Bit fields containing status info.
2531 */
2532static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2533{
2534#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2535 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2536 uint8_t *ptr = rxPacket;
2537# ifdef E1K_WITH_RXD_CACHE
2538 E1KRXDC rxdc;
2539# endif /* E1K_WITH_RXD_CACHE */
2540
2541 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2542 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2543 return rc;
2544# ifdef E1K_WITH_RXD_CACHE
2545 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2546 {
2547 e1kCsRxLeave(pThis);
2548 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2549 return VINF_SUCCESS;
2550 }
2551# endif /* E1K_WITH_RXD_CACHE */
2552
2553 if (cb > 70) /* unqualified guess */
2554 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2555
2556 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2557 Assert(cb > 16);
2558 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2559 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2560 if (status.fVP)
2561 {
2562 /* VLAN packet -- strip VLAN tag in VLAN mode */
2563 if ((CTRL & CTRL_VME) && cb > 16)
2564 {
2565 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2566 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2567 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2568 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2569 cb -= 4;
2570 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2571 pThis->szPrf, status.u16Special, cb));
2572 }
2573 else
2574 {
2575 status.fVP = false; /* Set VP only if we stripped the tag */
2576 memcpy(rxPacket, pvBuf, cb);
2577 }
2578 }
2579 else
2580 memcpy(rxPacket, pvBuf, cb);
2581 /* Pad short packets */
2582 if (cb < 60)
2583 {
2584 memset(rxPacket + cb, 0, 60 - cb);
2585 cb = 60;
2586 }
2587 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2588 {
2589 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2590 /*
2591 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2592 * is ignored by most of drivers we may as well save us the trouble
2593 * of calculating it (see EthernetCRC CFGM parameter).
2594 */
2595 if (pThis->fEthernetCRC)
2596 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2597 cb += sizeof(uint32_t);
2598 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2599 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2600 }
2601 /* Compute checksum of complete packet */
2602 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2603 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2604 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2605
2606 /* Update stats */
2607 E1K_INC_CNT32(GPRC);
2608 if (e1kIsBroadcast(pvBuf))
2609 E1K_INC_CNT32(BPRC);
2610 else if (e1kIsMulticast(pvBuf))
2611 E1K_INC_CNT32(MPRC);
2612 /* Update octet receive counter */
2613 E1K_ADD_CNT64(GORCL, GORCH, cb);
2614 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2615 if (cb == 64)
2616 E1K_INC_CNT32(PRC64);
2617 else if (cb < 128)
2618 E1K_INC_CNT32(PRC127);
2619 else if (cb < 256)
2620 E1K_INC_CNT32(PRC255);
2621 else if (cb < 512)
2622 E1K_INC_CNT32(PRC511);
2623 else if (cb < 1024)
2624 E1K_INC_CNT32(PRC1023);
2625 else
2626 E1K_INC_CNT32(PRC1522);
2627
2628 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2629
2630# ifdef E1K_WITH_RXD_CACHE
2631 while (cb > 0)
2632 {
2633 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis, &rxdc);
2634
2635 if (pDesc == NULL)
2636 {
2637 E1kLog(("%s Out of receive buffers, dropping the packet "
2638 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2639 pThis->szPrf, cb, e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt));
2640 break;
2641 }
2642# else /* !E1K_WITH_RXD_CACHE */
2643 if (RDH == RDT)
2644 {
2645 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2646 pThis->szPrf));
2647 }
2648 /* Store the packet to receive buffers */
2649 while (RDH != RDT)
2650 {
2651 /* Load the descriptor pointed by head */
2652 E1KRXDESC desc, *pDesc = &desc;
2653 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2654# endif /* !E1K_WITH_RXD_CACHE */
2655 if (pDesc->u64BufAddr)
2656 {
2657 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2658
2659 /* Update descriptor */
2660 pDesc->status = status;
2661 pDesc->u16Checksum = checksum;
2662 pDesc->status.fDD = true;
2663
2664 /*
2665 * We need to leave Rx critical section here or we risk deadlocking
2666 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2667 * page or has an access handler associated with it.
2668 * Note that it is safe to leave the critical section here since
2669 * e1kRegWriteRDT() never modifies RDH. It never touches already
2670 * fetched RxD cache entries either.
2671 */
2672 if (cb > u16RxBufferSize)
2673 {
2674 pDesc->status.fEOP = false;
2675 e1kCsRxLeave(pThis);
2676 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2677 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2678 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2679 return rc;
2680# ifdef E1K_WITH_RXD_CACHE
2681 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2682 {
2683 e1kCsRxLeave(pThis);
2684 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2685 return VINF_SUCCESS;
2686 }
2687# endif /* E1K_WITH_RXD_CACHE */
2688 ptr += u16RxBufferSize;
2689 cb -= u16RxBufferSize;
2690 }
2691 else
2692 {
2693 pDesc->status.fEOP = true;
2694 e1kCsRxLeave(pThis);
2695 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2696# ifdef E1K_WITH_RXD_CACHE
2697 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2698 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2699 return rc;
2700 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2701 {
2702 e1kCsRxLeave(pThis);
2703 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2704 return VINF_SUCCESS;
2705 }
2706 cb = 0;
2707# else /* !E1K_WITH_RXD_CACHE */
2708 pThis->led.Actual.s.fReading = 0;
2709 return VINF_SUCCESS;
2710# endif /* !E1K_WITH_RXD_CACHE */
2711 }
2712 /*
2713 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2714 * is not defined.
2715 */
2716 }
2717# ifdef E1K_WITH_RXD_CACHE
2718 /* Write back the descriptor. */
2719 pDesc->status.fDD = true;
2720 e1kRxDPut(pDevIns, pThis, pDesc, &rxdc);
2721# else /* !E1K_WITH_RXD_CACHE */
2722 else
2723 {
2724 /* Write back the descriptor. */
2725 pDesc->status.fDD = true;
2726 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2727 e1kAdvanceRDH(pDevIns, pThis);
2728 }
2729# endif /* !E1K_WITH_RXD_CACHE */
2730 }
2731
2732 if (cb > 0)
2733 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2734
2735 pThis->led.Actual.s.fReading = 0;
2736
2737 e1kCsRxLeave(pThis);
2738# ifdef E1K_WITH_RXD_CACHE
2739 /* Complete packet has been stored -- it is time to let the guest know. */
2740# ifdef E1K_USE_RX_TIMERS
2741 if (RDTR)
2742 {
2743 /* Arm the timer to fire in RDTR usec (discard .024) */
2744 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2745 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2746 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2747 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2748 }
2749 else
2750 {
2751# endif /* E1K_USE_RX_TIMERS */
2752 /* 0 delay means immediate interrupt */
2753 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2754 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2755# ifdef E1K_USE_RX_TIMERS
2756 }
2757# endif /* E1K_USE_RX_TIMERS */
2758# endif /* E1K_WITH_RXD_CACHE */
2759
2760 return VINF_SUCCESS;
2761#else /* !IN_RING3 */
2762 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2763 return VERR_INTERNAL_ERROR_2;
2764#endif /* !IN_RING3 */
2765}
2766
2767
2768#ifdef IN_RING3
2769/**
2770 * Bring the link up after the configured delay, 5 seconds by default.
2771 *
2772 * @param pDevIns The device instance.
2773 * @param pThis The device state structure.
2774 * @thread any
2775 */
2776DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2777{
2778 E1kLog(("%s Will bring up the link in %d seconds...\n",
2779 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2780 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2781}
2782
2783/**
2784 * Bring up the link immediately.
2785 *
2786 * @param pDevIns The device instance.
2787 * @param pThis The device state structure.
2788 * @param pThisCC The current context instance data.
2789 */
2790DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2791{
2792 E1kLog(("%s Link is up\n", pThis->szPrf));
2793 STATUS |= STATUS_LU;
2794 Phy::setLinkStatus(&pThis->phy, true);
2795 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2796 if (pThisCC->pDrvR3)
2797 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2798 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2799 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2800}
2801
2802/**
2803 * Bring down the link immediately.
2804 *
2805 * @param pDevIns The device instance.
2806 * @param pThis The device state structure.
2807 * @param pThisCC The current context instance data.
2808 */
2809DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2810{
2811 E1kLog(("%s Link is down\n", pThis->szPrf));
2812 STATUS &= ~STATUS_LU;
2813#ifdef E1K_LSC_ON_RESET
2814 Phy::setLinkStatus(&pThis->phy, false);
2815#endif /* E1K_LSC_ON_RESET */
2816 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2817 if (pThisCC->pDrvR3)
2818 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2819}
2820
2821/**
2822 * Bring down the link temporarily.
2823 *
2824 * @param pDevIns The device instance.
2825 * @param pThis The device state structure.
2826 * @param pThisCC The current context instance data.
2827 */
2828DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2829{
2830 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2831 STATUS &= ~STATUS_LU;
2832 Phy::setLinkStatus(&pThis->phy, false);
2833 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2834 /*
2835 * Notifying the associated driver that the link went down (even temporarily)
2836 * seems to be the right thing, but it was not done before. This may cause
2837 * a regression if the driver does not expect the link to go down as a result
2838 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2839 * of code notified the driver that the link was up! See @bugref{7057}.
2840 */
2841 if (pThisCC->pDrvR3)
2842 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2843 e1kBringLinkUpDelayed(pDevIns, pThis);
2844}
2845#endif /* IN_RING3 */
2846
2847#if 0 /* unused */
2848/**
2849 * Read handler for Device Status register.
2850 *
2851 * Get the link status from PHY.
2852 *
2853 * @returns VBox status code.
2854 *
2855 * @param pThis The device state structure.
2856 * @param offset Register offset in memory-mapped frame.
2857 * @param index Register index in register array.
2858 * @param mask Used to implement partial reads (8 and 16-bit).
2859 */
2860static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2861{
2862 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2863 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2864 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2865 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2866 {
2867 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2868 if (Phy::readMDIO(&pThis->phy))
2869 *pu32Value = CTRL | CTRL_MDIO;
2870 else
2871 *pu32Value = CTRL & ~CTRL_MDIO;
2872 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2873 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2874 }
2875 else
2876 {
2877 /* MDIO pin is used for output, ignore it */
2878 *pu32Value = CTRL;
2879 }
2880 return VINF_SUCCESS;
2881}
2882#endif /* unused */
2883
2884/**
2885 * A callback used by PHY to indicate that the link needs to be updated due to
2886 * reset of PHY.
2887 *
2888 * @param pDevIns The device instance.
2889 * @thread any
2890 */
2891void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2892{
2893 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2894
2895 /* Make sure we have cable connected and MAC can talk to PHY */
2896 if (pThis->fCableConnected && (CTRL & CTRL_SLU))
2897 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2898}
2899
2900/**
2901 * Write handler for Device Control register.
2902 *
2903 * Handles reset.
2904 *
2905 * @param pThis The device state structure.
2906 * @param offset Register offset in memory-mapped frame.
2907 * @param index Register index in register array.
2908 * @param value The value to store.
2909 * @param mask Used to implement partial writes (8 and 16-bit).
2910 * @thread EMT
2911 */
2912static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2913{
2914 int rc = VINF_SUCCESS;
2915
2916 if (value & CTRL_RESET)
2917 { /* RST */
2918#ifndef IN_RING3
2919 return VINF_IOM_R3_MMIO_WRITE;
2920#else
2921 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2922#endif
2923 }
2924 else
2925 {
2926#ifdef E1K_LSC_ON_SLU
2927 /*
2928 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2929 * the link is down and the cable is connected, and if they are we
2930 * bring the link up, see @bugref{8624}.
2931 */
2932 if ( (value & CTRL_SLU)
2933 && !(CTRL & CTRL_SLU)
2934 && pThis->fCableConnected
2935 && !(STATUS & STATUS_LU))
2936 {
2937 /* It should take about 2 seconds for the link to come up */
2938 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2939 }
2940#else /* !E1K_LSC_ON_SLU */
2941 if ( (value & CTRL_SLU)
2942 && !(CTRL & CTRL_SLU)
2943 && pThis->fCableConnected
2944 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2945 {
2946 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2947 STATUS |= STATUS_LU;
2948 }
2949#endif /* !E1K_LSC_ON_SLU */
2950 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2951 {
2952 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2953 }
2954 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2955 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2956 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2957 if (value & CTRL_MDC)
2958 {
2959 if (value & CTRL_MDIO_DIR)
2960 {
2961 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2962 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2963 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2964 }
2965 else
2966 {
2967 if (Phy::readMDIO(&pThis->phy))
2968 value |= CTRL_MDIO;
2969 else
2970 value &= ~CTRL_MDIO;
2971 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2972 }
2973 }
2974 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
2975 }
2976
2977 return rc;
2978}
2979
2980/**
2981 * Write handler for EEPROM/Flash Control/Data register.
2982 *
2983 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
2984 *
2985 * @param pThis The device state structure.
2986 * @param offset Register offset in memory-mapped frame.
2987 * @param index Register index in register array.
2988 * @param value The value to store.
2989 * @param mask Used to implement partial writes (8 and 16-bit).
2990 * @thread EMT
2991 */
2992static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2993{
2994 RT_NOREF(pDevIns, offset, index);
2995#ifdef IN_RING3
2996 /* So far we are concerned with lower byte only */
2997 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
2998 {
2999 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
3000 /* Note: 82543GC does not need to request EEPROM access */
3001 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
3002 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3003 pThisCC->eeprom.write(value & EECD_EE_WIRES);
3004 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
3005 }
3006 if (value & EECD_EE_REQ)
3007 EECD |= EECD_EE_REQ|EECD_EE_GNT;
3008 else
3009 EECD &= ~EECD_EE_GNT;
3010 //e1kRegWriteDefault(pThis, offset, index, value );
3011
3012 return VINF_SUCCESS;
3013#else /* !IN_RING3 */
3014 RT_NOREF(pThis, value);
3015 return VINF_IOM_R3_MMIO_WRITE;
3016#endif /* !IN_RING3 */
3017}
3018
3019/**
3020 * Read handler for EEPROM/Flash Control/Data register.
3021 *
3022 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
3023 *
3024 * @returns VBox status code.
3025 *
3026 * @param pThis The device state structure.
3027 * @param offset Register offset in memory-mapped frame.
3028 * @param index Register index in register array.
3029 * @param mask Used to implement partial reads (8 and 16-bit).
3030 * @thread EMT
3031 */
3032static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3033{
3034#ifdef IN_RING3
3035 uint32_t value = 0; /* Get rid of false positive in parfait. */
3036 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3037 if (RT_SUCCESS(rc))
3038 {
3039 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3040 {
3041 /* Note: 82543GC does not need to request EEPROM access */
3042 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
3043 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3044 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3045 value |= pThisCC->eeprom.read();
3046 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3047 }
3048 *pu32Value = value;
3049 }
3050
3051 return rc;
3052#else /* !IN_RING3 */
3053 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
3054 return VINF_IOM_R3_MMIO_READ;
3055#endif /* !IN_RING3 */
3056}
3057
3058/**
3059 * Write handler for EEPROM Read register.
3060 *
3061 * Handles EEPROM word access requests, reads EEPROM and stores the result
3062 * into DATA field.
3063 *
3064 * @param pThis The device state structure.
3065 * @param offset Register offset in memory-mapped frame.
3066 * @param index Register index in register array.
3067 * @param value The value to store.
3068 * @param mask Used to implement partial writes (8 and 16-bit).
3069 * @thread EMT
3070 */
3071static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3072{
3073#ifdef IN_RING3
3074 /* Make use of 'writable' and 'readable' masks. */
3075 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3076 /* DONE and DATA are set only if read was triggered by START. */
3077 if (value & EERD_START)
3078 {
3079 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3080 uint16_t tmp;
3081 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3082 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
3083 SET_BITS(EERD, DATA, tmp);
3084 EERD |= EERD_DONE;
3085 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3086 }
3087
3088 return VINF_SUCCESS;
3089#else /* !IN_RING3 */
3090 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
3091 return VINF_IOM_R3_MMIO_WRITE;
3092#endif /* !IN_RING3 */
3093}
3094
3095
3096/**
3097 * Write handler for MDI Control register.
3098 *
3099 * Handles PHY read/write requests; forwards requests to internal PHY device.
3100 *
3101 * @param pThis The device state structure.
3102 * @param offset Register offset in memory-mapped frame.
3103 * @param index Register index in register array.
3104 * @param value The value to store.
3105 * @param mask Used to implement partial writes (8 and 16-bit).
3106 * @thread EMT
3107 */
3108static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3109{
3110 if (value & MDIC_INT_EN)
3111 {
3112 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
3113 pThis->szPrf));
3114 }
3115 else if (value & MDIC_READY)
3116 {
3117 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3118 pThis->szPrf));
3119 }
3120 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3121 {
3122 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3123 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3124 /*
3125 * Some drivers scan the MDIO bus for a PHY. We can work with these
3126 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3127 * at the requested address, see @bugref{7346}.
3128 */
3129 MDIC = MDIC_READY | MDIC_ERROR;
3130 }
3131 else
3132 {
3133 /* Store the value */
3134 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3135 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3136 /* Forward op to PHY */
3137 if (value & MDIC_OP_READ)
3138 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3139 else
3140 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3141 /* Let software know that we are done */
3142 MDIC |= MDIC_READY;
3143 }
3144
3145 return VINF_SUCCESS;
3146}
3147
3148/**
3149 * Write handler for Interrupt Cause Read register.
3150 *
3151 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3152 *
3153 * @param pThis The device state structure.
3154 * @param offset Register offset in memory-mapped frame.
3155 * @param index Register index in register array.
3156 * @param value The value to store.
3157 * @param mask Used to implement partial writes (8 and 16-bit).
3158 * @thread EMT
3159 */
3160static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3161{
3162 ICR &= ~value;
3163
3164 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3165 return VINF_SUCCESS;
3166}
3167
3168/**
3169 * Read handler for Interrupt Cause Read register.
3170 *
3171 * Reading this register acknowledges all interrupts.
3172 *
3173 * @returns VBox status code.
3174 *
3175 * @param pThis The device state structure.
3176 * @param offset Register offset in memory-mapped frame.
3177 * @param index Register index in register array.
3178 * @param mask Not used.
3179 * @thread EMT
3180 */
3181static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3182{
3183 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3184 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3185 return rc;
3186
3187 uint32_t value = 0;
3188 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3189 if (RT_SUCCESS(rc))
3190 {
3191 if (value)
3192 {
3193 if (!pThis->fIntRaised)
3194 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3195 /*
3196 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3197 * with disabled interrupts.
3198 */
3199 //if (IMS)
3200 if (1)
3201 {
3202 /*
3203 * Interrupts were enabled -- we are supposedly at the very
3204 * beginning of interrupt handler
3205 */
3206 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3207 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3208 /* Clear all pending interrupts */
3209 ICR = 0;
3210 pThis->fIntRaised = false;
3211 /* Lower(0) INTA(0) */
3212 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3213
3214 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3215 if (pThis->fIntMaskUsed)
3216 pThis->fDelayInts = true;
3217 }
3218 else
3219 {
3220 /*
3221 * Interrupts are disabled -- in windows guests ICR read is done
3222 * just before re-enabling interrupts
3223 */
3224 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3225 }
3226 }
3227 *pu32Value = value;
3228 }
3229 e1kCsLeave(pThis);
3230
3231 return rc;
3232}
3233
3234/**
3235 * Write handler for Interrupt Cause Set register.
3236 *
3237 * Bits corresponding to 1s in 'value' will be set in ICR register.
3238 *
3239 * @param pThis The device state structure.
3240 * @param offset Register offset in memory-mapped frame.
3241 * @param index Register index in register array.
3242 * @param value The value to store.
3243 * @param mask Used to implement partial writes (8 and 16-bit).
3244 * @thread EMT
3245 */
3246static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3247{
3248 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3249 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3250 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3251}
3252
3253/**
3254 * Write handler for Interrupt Mask Set register.
3255 *
3256 * Will trigger pending interrupts.
3257 *
3258 * @param pThis The device state structure.
3259 * @param offset Register offset in memory-mapped frame.
3260 * @param index Register index in register array.
3261 * @param value The value to store.
3262 * @param mask Used to implement partial writes (8 and 16-bit).
3263 * @thread EMT
3264 */
3265static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3266{
3267 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3268
3269 IMS |= value;
3270 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3271 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3272 /*
3273 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3274 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3275 */
3276 if ((ICR & IMS) && !pThis->fLocked)
3277 {
3278 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3279 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3280 }
3281
3282 return VINF_SUCCESS;
3283}
3284
3285/**
3286 * Write handler for Interrupt Mask Clear register.
3287 *
3288 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3289 *
3290 * @param pThis The device state structure.
3291 * @param offset Register offset in memory-mapped frame.
3292 * @param index Register index in register array.
3293 * @param value The value to store.
3294 * @param mask Used to implement partial writes (8 and 16-bit).
3295 * @thread EMT
3296 */
3297static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3298{
3299 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3300
3301 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3302 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3303 return rc;
3304 if (pThis->fIntRaised)
3305 {
3306 /*
3307 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3308 * Windows to freeze since it may receive an interrupt while still in the very beginning
3309 * of interrupt handler.
3310 */
3311 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3312 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3313 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3314 /* Lower(0) INTA(0) */
3315 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3316 pThis->fIntRaised = false;
3317 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3318 }
3319 IMS &= ~value;
3320 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3321 e1kCsLeave(pThis);
3322
3323 return VINF_SUCCESS;
3324}
3325
3326/**
3327 * Write handler for Receive Control register.
3328 *
3329 * @param pThis The device state structure.
3330 * @param offset Register offset in memory-mapped frame.
3331 * @param index Register index in register array.
3332 * @param value The value to store.
3333 * @param mask Used to implement partial writes (8 and 16-bit).
3334 * @thread EMT
3335 */
3336static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3337{
3338 /* Update promiscuous mode */
3339 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3340 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3341 {
3342 /* Promiscuity has changed, pass the knowledge on. */
3343#ifndef IN_RING3
3344 return VINF_IOM_R3_MMIO_WRITE;
3345#else
3346 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3347 if (pThisCC->pDrvR3)
3348 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3349#endif
3350 }
3351
3352 /* Adjust receive buffer size */
3353 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3354 if (value & RCTL_BSEX)
3355 cbRxBuf *= 16;
3356 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3357 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3358 if (cbRxBuf != pThis->u16RxBSize)
3359 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3360 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3361 Assert(cbRxBuf < 65536);
3362 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3363
3364 /* Update the register */
3365 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3366}
3367
3368/**
3369 * Write handler for Packet Buffer Allocation register.
3370 *
3371 * TXA = 64 - RXA.
3372 *
3373 * @param pThis The device state structure.
3374 * @param offset Register offset in memory-mapped frame.
3375 * @param index Register index in register array.
3376 * @param value The value to store.
3377 * @param mask Used to implement partial writes (8 and 16-bit).
3378 * @thread EMT
3379 */
3380static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3381{
3382 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3383 PBA_st->txa = 64 - PBA_st->rxa;
3384
3385 return VINF_SUCCESS;
3386}
3387
3388/**
3389 * Write handler for Receive Descriptor Tail register.
3390 *
3391 * @remarks Write into RDT forces switch to HC and signal to
3392 * e1kR3NetworkDown_WaitReceiveAvail().
3393 *
3394 * @returns VBox status code.
3395 *
3396 * @param pThis The device state structure.
3397 * @param offset Register offset in memory-mapped frame.
3398 * @param index Register index in register array.
3399 * @param value The value to store.
3400 * @param mask Used to implement partial writes (8 and 16-bit).
3401 * @thread EMT
3402 */
3403static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3404{
3405#ifndef IN_RING3
3406 /* XXX */
3407// return VINF_IOM_R3_MMIO_WRITE;
3408#endif
3409 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3410 if (RT_LIKELY(rc == VINF_SUCCESS))
3411 {
3412 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3413#ifndef E1K_WITH_RXD_CACHE
3414 /*
3415 * Some drivers advance RDT too far, so that it equals RDH. This
3416 * somehow manages to work with real hardware but not with this
3417 * emulated device. We can work with these drivers if we just
3418 * write 1 less when we see a driver writing RDT equal to RDH,
3419 * see @bugref{7346}.
3420 */
3421 if (value == RDH)
3422 {
3423 if (RDH == 0)
3424 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3425 else
3426 value = RDH - 1;
3427 }
3428#endif /* !E1K_WITH_RXD_CACHE */
3429 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3430#ifdef E1K_WITH_RXD_CACHE
3431 E1KRXDC rxdc;
3432 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kRegWriteRDT")))
3433 {
3434 e1kCsRxLeave(pThis);
3435 E1kLog(("%s e1kRegWriteRDT: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
3436 return VINF_SUCCESS;
3437 }
3438 /*
3439 * We need to fetch descriptors now as RDT may go whole circle
3440 * before we attempt to store a received packet. For example,
3441 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3442 * size being only 8 descriptors! Note that we fetch descriptors
3443 * only when the cache is empty to reduce the number of memory reads
3444 * in case of frequent RDT writes. Don't fetch anything when the
3445 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3446 * messed up state.
3447 * Note that despite the cache may seem empty, meaning that there are
3448 * no more available descriptors in it, it may still be used by RX
3449 * thread which has not yet written the last descriptor back but has
3450 * temporarily released the RX lock in order to write the packet body
3451 * to descriptor's buffer. At this point we still going to do prefetch
3452 * but it won't actually fetch anything if there are no unused slots in
3453 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3454 * reset the cache here even if it appears empty. It will be reset at
3455 * a later point in e1kRxDGet().
3456 */
3457 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3458 e1kRxDPrefetch(pDevIns, pThis, &rxdc);
3459#endif /* E1K_WITH_RXD_CACHE */
3460 e1kCsRxLeave(pThis);
3461 if (RT_SUCCESS(rc))
3462 {
3463 /* Signal that we have more receive descriptors available. */
3464 e1kWakeupReceive(pDevIns, pThis);
3465 }
3466 }
3467 return rc;
3468}
3469
3470/**
3471 * Write handler for Receive Delay Timer register.
3472 *
3473 * @param pThis The device state structure.
3474 * @param offset Register offset in memory-mapped frame.
3475 * @param index Register index in register array.
3476 * @param value The value to store.
3477 * @param mask Used to implement partial writes (8 and 16-bit).
3478 * @thread EMT
3479 */
3480static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3481{
3482 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3483 if (value & RDTR_FPD)
3484 {
3485 /* Flush requested, cancel both timers and raise interrupt */
3486#ifdef E1K_USE_RX_TIMERS
3487 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3488 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3489#endif
3490 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3491 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3492 }
3493
3494 return VINF_SUCCESS;
3495}
3496
3497DECLINLINE(uint32_t) e1kGetTxLen(PE1KTXDC pTxdc)
3498{
3499 /**
3500 * Make sure TDT won't change during computation. EMT may modify TDT at
3501 * any moment.
3502 */
3503 uint32_t tdt = pTxdc->tdt;
3504 return (pTxdc->tdh > tdt ? pTxdc->tdlen/sizeof(E1KTXDESC) : 0) + tdt - pTxdc->tdh;
3505}
3506
3507#ifdef IN_RING3
3508
3509# ifdef E1K_TX_DELAY
3510/**
3511 * @callback_method_impl{FNTMTIMERDEV, Transmit Delay Timer handler.}
3512 */
3513static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3514{
3515 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3516 Assert(PDMCritSectIsOwner(&pThis->csTx));
3517 RT_NOREF(hTimer);
3518
3519 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3520# ifdef E1K_INT_STATS
3521 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3522 if (u64Elapsed > pThis->uStatMaxTxDelay)
3523 pThis->uStatMaxTxDelay = u64Elapsed;
3524# endif
3525 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3526 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3527}
3528# endif /* E1K_TX_DELAY */
3529
3530//# ifdef E1K_USE_TX_TIMERS
3531
3532/**
3533 * @callback_method_impl{FNTMTIMERDEV, Transmit Interrupt Delay Timer handler.}
3534 */
3535static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3536{
3537 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3538 Assert(hTimer == pThis->hTIDTimer); RT_NOREF(hTimer);
3539
3540 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3541 /* Cancel absolute delay timer as we have already got attention */
3542# ifndef E1K_NO_TAD
3543 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3544# endif
3545 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3546}
3547
3548/**
3549 * @callback_method_impl{FNTMTIMERDEV, Transmit Absolute Delay Timer handler.}
3550 */
3551static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3552{
3553 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3554 Assert(hTimer == pThis->hTADTimer); RT_NOREF(hTimer);
3555
3556 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3557 /* Cancel interrupt delay timer as we have already got attention */
3558 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3559 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3560}
3561
3562//# endif /* E1K_USE_TX_TIMERS */
3563# ifdef E1K_USE_RX_TIMERS
3564
3565/**
3566 * @callback_method_impl{FNTMTIMERDEV, Receive Interrupt Delay Timer handler.}
3567 */
3568static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3569{
3570 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3571 Assert(hTimer == pThis->hRIDTimer); RT_NOREF(hTimer);
3572
3573 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3574 /* Cancel absolute delay timer as we have already got attention */
3575 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3576 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3577}
3578
3579/**
3580 * @callback_method_impl{FNTMTIMERDEV, Receive Absolute Delay Timer handler.}
3581 */
3582static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3583{
3584 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3585 Assert(hTimer == pThis->hRADTimer); RT_NOREF(hTimer);
3586
3587 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3588 /* Cancel interrupt delay timer as we have already got attention */
3589 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3590 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3591}
3592
3593# endif /* E1K_USE_RX_TIMERS */
3594
3595/**
3596 * @callback_method_impl{FNTMTIMERDEV, Late Interrupt Timer handler.}
3597 */
3598static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3599{
3600 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3601 Assert(hTimer == pThis->hIntTimer); RT_NOREF(hTimer);
3602 RT_NOREF(hTimer);
3603
3604 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3605 STAM_COUNTER_INC(&pThis->StatLateInts);
3606 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3607# if 0
3608 if (pThis->iStatIntLost > -100)
3609 pThis->iStatIntLost--;
3610# endif
3611 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3612 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3613}
3614
3615/**
3616 * @callback_method_impl{FNTMTIMERDEV, Link Up Timer handler.}
3617 */
3618static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3619{
3620 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3621 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3622 Assert(hTimer == pThis->hLUTimer); RT_NOREF(hTimer);
3623
3624 /*
3625 * This can happen if we set the link status to down when the Link up timer was
3626 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3627 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3628 * on reset even if the cable is unplugged (see @bugref{8942}).
3629 */
3630 if (pThis->fCableConnected)
3631 {
3632 /* 82543GC does not have an internal PHY */
3633 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3634 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3635 }
3636# ifdef E1K_LSC_ON_RESET
3637 else if (pThis->eChip == E1K_CHIP_82543GC)
3638 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3639# endif /* E1K_LSC_ON_RESET */
3640}
3641
3642#endif /* IN_RING3 */
3643
3644/**
3645 * Sets up the GSO context according to the TSE new context descriptor.
3646 *
3647 * @param pGso The GSO context to setup.
3648 * @param pCtx The context descriptor.
3649 */
3650DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3651{
3652 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3653
3654 /*
3655 * See if the context descriptor describes something that could be TCP or
3656 * UDP over IPv[46].
3657 */
3658 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3659 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3660 {
3661 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3662 return;
3663 }
3664 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3665 {
3666 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3667 return;
3668 }
3669 if (RT_UNLIKELY( pCtx->dw2.fTCP
3670 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3671 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3672 {
3673 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3674 return;
3675 }
3676
3677 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3678 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3679 {
3680 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3681 return;
3682 }
3683
3684 /* IPv4 checksum offset. */
3685 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3686 {
3687 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3688 return;
3689 }
3690
3691 /* TCP/UDP checksum offsets. */
3692 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3693 != ( pCtx->dw2.fTCP
3694 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3695 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3696 {
3697 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3698 return;
3699 }
3700
3701 /*
3702 * Because of internal networking using a 16-bit size field for GSO context
3703 * plus frame, we have to make sure we don't exceed this.
3704 */
3705 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3706 {
3707 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3708 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3709 return;
3710 }
3711
3712 /*
3713 * We're good for now - we'll do more checks when seeing the data.
3714 * So, figure the type of offloading and setup the context.
3715 */
3716 if (pCtx->dw2.fIP)
3717 {
3718 if (pCtx->dw2.fTCP)
3719 {
3720 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3721 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3722 }
3723 else
3724 {
3725 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3726 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3727 }
3728 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3729 * this yet it seems)... */
3730 }
3731 else
3732 {
3733 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3734 if (pCtx->dw2.fTCP)
3735 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3736 else
3737 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3738 }
3739 pGso->offHdr1 = pCtx->ip.u8CSS;
3740 pGso->offHdr2 = pCtx->tu.u8CSS;
3741 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3742 pGso->cbMaxSeg = pCtx->dw3.u16MSS + (pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP ? pGso->offHdr2 : 0);
3743 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3744 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3745 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3746}
3747
3748/**
3749 * Checks if we can use GSO processing for the current TSE frame.
3750 *
3751 * @param pThis The device state structure.
3752 * @param pGso The GSO context.
3753 * @param pData The first data descriptor of the frame.
3754 * @param pCtx The TSO context descriptor.
3755 */
3756DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3757{
3758 if (!pData->cmd.fTSE)
3759 {
3760 E1kLog2(("e1kCanDoGso: !TSE\n"));
3761 return false;
3762 }
3763 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3764 {
3765 E1kLog(("e1kCanDoGso: VLE\n"));
3766 return false;
3767 }
3768 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3769 {
3770 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3771 return false;
3772 }
3773
3774 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3775 {
3776 case PDMNETWORKGSOTYPE_IPV4_TCP:
3777 case PDMNETWORKGSOTYPE_IPV4_UDP:
3778 if (!pData->dw3.fIXSM)
3779 {
3780 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3781 return false;
3782 }
3783 if (!pData->dw3.fTXSM)
3784 {
3785 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3786 return false;
3787 }
3788 /** @todo what more check should we perform here? Ethernet frame type? */
3789 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3790 return true;
3791
3792 case PDMNETWORKGSOTYPE_IPV6_TCP:
3793 case PDMNETWORKGSOTYPE_IPV6_UDP:
3794 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3795 {
3796 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3797 return false;
3798 }
3799 if (!pData->dw3.fTXSM)
3800 {
3801 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3802 return false;
3803 }
3804 /** @todo what more check should we perform here? Ethernet frame type? */
3805 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3806 return true;
3807
3808 default:
3809 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3810 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3811 return false;
3812 }
3813}
3814
3815/**
3816 * Frees the current xmit buffer.
3817 *
3818 * @param pThis The device state structure.
3819 */
3820static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3821{
3822 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3823 if (pSg)
3824 {
3825 pThisCC->CTX_SUFF(pTxSg) = NULL;
3826
3827 if (pSg->pvAllocator != pThis)
3828 {
3829 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3830 if (pDrv)
3831 pDrv->pfnFreeBuf(pDrv, pSg);
3832 }
3833 else
3834 {
3835 /* loopback */
3836 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3837 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3838 pSg->fFlags = 0;
3839 pSg->pvAllocator = NULL;
3840 }
3841 }
3842}
3843
3844#ifndef E1K_WITH_TXD_CACHE
3845/**
3846 * Allocates an xmit buffer.
3847 *
3848 * @returns See PDMINETWORKUP::pfnAllocBuf.
3849 * @param pThis The device state structure.
3850 * @param cbMin The minimum frame size.
3851 * @param fExactSize Whether cbMin is exact or if we have to max it
3852 * out to the max MTU size.
3853 * @param fGso Whether this is a GSO frame or not.
3854 */
3855DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3856{
3857 /* Adjust cbMin if necessary. */
3858 if (!fExactSize)
3859 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3860
3861 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3862 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3863 e1kXmitFreeBuf(pThis, pThisCC);
3864 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3865
3866 /*
3867 * Allocate the buffer.
3868 */
3869 PPDMSCATTERGATHER pSg;
3870 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3871 {
3872 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3873 if (RT_UNLIKELY(!pDrv))
3874 return VERR_NET_DOWN;
3875 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3876 if (RT_FAILURE(rc))
3877 {
3878 /* Suspend TX as we are out of buffers atm */
3879 STATUS |= STATUS_TXOFF;
3880 return rc;
3881 }
3882 }
3883 else
3884 {
3885 /* Create a loopback using the fallback buffer and preallocated SG. */
3886 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3887 pSg = &pThis->uTxFallback.Sg;
3888 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3889 pSg->cbUsed = 0;
3890 pSg->cbAvailable = 0;
3891 pSg->pvAllocator = pThis;
3892 pSg->pvUser = NULL; /* No GSO here. */
3893 pSg->cSegs = 1;
3894 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3895 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3896 }
3897
3898 pThisCC->CTX_SUFF(pTxSg) = pSg;
3899 return VINF_SUCCESS;
3900}
3901#else /* E1K_WITH_TXD_CACHE */
3902/**
3903 * Allocates an xmit buffer.
3904 *
3905 * @returns See PDMINETWORKUP::pfnAllocBuf.
3906 * @param pThis The device state structure.
3907 * @param cbMin The minimum frame size.
3908 * @param fExactSize Whether cbMin is exact or if we have to max it
3909 * out to the max MTU size.
3910 * @param fGso Whether this is a GSO frame or not.
3911 */
3912DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3913{
3914 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3915 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3916 e1kXmitFreeBuf(pThis, pThisCC);
3917 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3918
3919 /*
3920 * Allocate the buffer.
3921 */
3922 PPDMSCATTERGATHER pSg;
3923 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3924 {
3925 if (pThis->cbTxAlloc == 0)
3926 {
3927 /* Zero packet, no need for the buffer */
3928 return VINF_SUCCESS;
3929 }
3930 if (fGso && pThis->GsoCtx.u8Type == PDMNETWORKGSOTYPE_INVALID)
3931 {
3932 E1kLog3(("Invalid GSO context, won't allocate this packet, cb=%u %s%s\n",
3933 pThis->cbTxAlloc, pThis->fVTag ? "VLAN " : "", pThis->fGSO ? "GSO " : ""));
3934 /* No valid GSO context is available, ignore this packet. */
3935 pThis->cbTxAlloc = 0;
3936 return VINF_SUCCESS;
3937 }
3938
3939 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3940 if (RT_UNLIKELY(!pDrv))
3941 return VERR_NET_DOWN;
3942 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3943 if (RT_FAILURE(rc))
3944 {
3945 /* Suspend TX as we are out of buffers atm */
3946 STATUS |= STATUS_TXOFF;
3947 return rc;
3948 }
3949 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3950 pThis->szPrf, pThis->cbTxAlloc,
3951 pThis->fVTag ? "VLAN " : "",
3952 pThis->fGSO ? "GSO " : ""));
3953 }
3954 else
3955 {
3956 /* Create a loopback using the fallback buffer and preallocated SG. */
3957 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3958 pSg = &pThis->uTxFallback.Sg;
3959 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3960 pSg->cbUsed = 0;
3961 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
3962 pSg->pvAllocator = pThis;
3963 pSg->pvUser = NULL; /* No GSO here. */
3964 pSg->cSegs = 1;
3965 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3966 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3967 }
3968 pThis->cbTxAlloc = 0;
3969
3970 pThisCC->CTX_SUFF(pTxSg) = pSg;
3971 return VINF_SUCCESS;
3972}
3973#endif /* E1K_WITH_TXD_CACHE */
3974
3975/**
3976 * Checks if it's a GSO buffer or not.
3977 *
3978 * @returns true / false.
3979 * @param pTxSg The scatter / gather buffer.
3980 */
3981DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
3982{
3983#if 0
3984 if (!pTxSg)
3985 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
3986 if (pTxSg && pTxSg->pvUser)
3987 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
3988#endif
3989 return pTxSg && pTxSg->pvUser /* GSO indicator */;
3990}
3991
3992#ifndef E1K_WITH_TXD_CACHE
3993/**
3994 * Load transmit descriptor from guest memory.
3995 *
3996 * @param pDevIns The device instance.
3997 * @param pDesc Pointer to descriptor union.
3998 * @param addr Physical address in guest context.
3999 * @thread E1000_TX
4000 */
4001DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
4002{
4003 PDMDevHlpPCIPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4004}
4005#else /* E1K_WITH_TXD_CACHE */
4006/**
4007 * Load transmit descriptors from guest memory.
4008 *
4009 * We need two physical reads in case the tail wrapped around the end of TX
4010 * descriptor ring.
4011 *
4012 * @returns the actual number of descriptors fetched.
4013 * @param pDevIns The device instance.
4014 * @param pThis The device state structure.
4015 * @thread E1000_TX
4016 */
4017DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4018{
4019 Assert(pThis->iTxDCurrent == 0);
4020 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
4021 unsigned nDescsAvailable = e1kGetTxLen(pTxdc) - pThis->nTxDFetched;
4022 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
4023 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
4024 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
4025 unsigned nDescsTotal = pTxdc->tdlen / sizeof(E1KTXDESC);
4026 Assert(nDescsTotal != 0);
4027 if (nDescsTotal == 0)
4028 return 0;
4029 unsigned nFirstNotLoaded = (pTxdc->tdh + pThis->nTxDFetched) % nDescsTotal;
4030 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
4031 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
4032 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
4033 nFirstNotLoaded, nDescsInSingleRead));
4034 if (nDescsToFetch == 0)
4035 return 0;
4036 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
4037 PDMDevHlpPCIPhysRead(pDevIns,
4038 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
4039 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
4040 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
4041 pThis->szPrf, nDescsInSingleRead,
4042 TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC),
4043 nFirstNotLoaded, pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
4044 if (nDescsToFetch > nDescsInSingleRead)
4045 {
4046 PDMDevHlpPCIPhysRead(pDevIns,
4047 ((uint64_t)TDBAH << 32) + TDBAL,
4048 pFirstEmptyDesc + nDescsInSingleRead,
4049 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
4050 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
4051 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
4052 TDBAH, TDBAL));
4053 }
4054 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
4055 return nDescsToFetch;
4056}
4057
4058/**
4059 * Load transmit descriptors from guest memory only if there are no loaded
4060 * descriptors.
4061 *
4062 * @returns true if there are descriptors in cache.
4063 * @param pDevIns The device instance.
4064 * @param pThis The device state structure.
4065 * @thread E1000_TX
4066 */
4067DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4068{
4069 if (pThis->nTxDFetched == 0)
4070 return e1kTxDLoadMore(pDevIns, pThis, pTxdc) != 0;
4071 return true;
4072}
4073#endif /* E1K_WITH_TXD_CACHE */
4074
4075/**
4076 * Write back transmit descriptor to guest memory.
4077 *
4078 * @param pDevIns The device instance.
4079 * @param pThis The device state structure.
4080 * @param pDesc Pointer to descriptor union.
4081 * @param addr Physical address in guest context.
4082 * @thread E1000_TX
4083 */
4084DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4085{
4086 /* Only the last half of the descriptor has to be written back. */
4087 e1kPrintTDesc(pThis, pDesc, "^^^");
4088 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4089}
4090
4091/**
4092 * Transmit complete frame.
4093 *
4094 * @remarks We skip the FCS since we're not responsible for sending anything to
4095 * a real ethernet wire.
4096 *
4097 * @param pDevIns The device instance.
4098 * @param pThis The device state structure.
4099 * @param pThisCC The current context instance data.
4100 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4101 * @thread E1000_TX
4102 */
4103static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4104{
4105 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4106 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4107 Assert(!pSg || pSg->cSegs == 1);
4108
4109 if (cbFrame > 70) /* unqualified guess */
4110 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4111
4112#ifdef E1K_INT_STATS
4113 if (cbFrame <= 1514)
4114 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4115 else if (cbFrame <= 2962)
4116 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4117 else if (cbFrame <= 4410)
4118 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4119 else if (cbFrame <= 5858)
4120 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4121 else if (cbFrame <= 7306)
4122 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4123 else if (cbFrame <= 8754)
4124 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4125 else if (cbFrame <= 16384)
4126 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4127 else if (cbFrame <= 32768)
4128 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4129 else
4130 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4131#endif /* E1K_INT_STATS */
4132
4133 /* Add VLAN tag */
4134 if (cbFrame > 12 && pThis->fVTag)
4135 {
4136 E1kLog3(("%s Inserting VLAN tag %08x\n",
4137 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4138 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4139 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4140 pSg->cbUsed += 4;
4141 cbFrame += 4;
4142 Assert(pSg->cbUsed == cbFrame);
4143 Assert(pSg->cbUsed <= pSg->cbAvailable);
4144 }
4145/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4146 "%.*Rhxd\n"
4147 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4148 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4149
4150 /* Update the stats */
4151 E1K_INC_CNT32(TPT);
4152 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4153 E1K_INC_CNT32(GPTC);
4154 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4155 E1K_INC_CNT32(BPTC);
4156 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4157 E1K_INC_CNT32(MPTC);
4158 /* Update octet transmit counter */
4159 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4160 if (pThisCC->CTX_SUFF(pDrv))
4161 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4162 if (cbFrame == 64)
4163 E1K_INC_CNT32(PTC64);
4164 else if (cbFrame < 128)
4165 E1K_INC_CNT32(PTC127);
4166 else if (cbFrame < 256)
4167 E1K_INC_CNT32(PTC255);
4168 else if (cbFrame < 512)
4169 E1K_INC_CNT32(PTC511);
4170 else if (cbFrame < 1024)
4171 E1K_INC_CNT32(PTC1023);
4172 else
4173 E1K_INC_CNT32(PTC1522);
4174
4175 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4176
4177 /*
4178 * Dump and send the packet.
4179 */
4180 int rc = VERR_NET_DOWN;
4181 if (pSg && pSg->pvAllocator != pThis)
4182 {
4183 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4184
4185 pThisCC->CTX_SUFF(pTxSg) = NULL;
4186 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4187 if (pDrv)
4188 {
4189 /* Release critical section to avoid deadlock in CanReceive */
4190 //e1kCsLeave(pThis);
4191 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4192 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4193 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4194 //e1kCsEnter(pThis, RT_SRC_POS);
4195 }
4196 }
4197 else if (pSg)
4198 {
4199 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4200 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4201
4202 /** @todo do we actually need to check that we're in loopback mode here? */
4203 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4204 {
4205 E1KRXDST status;
4206 RT_ZERO(status);
4207 status.fPIF = true;
4208 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4209 rc = VINF_SUCCESS;
4210 }
4211 e1kXmitFreeBuf(pThis, pThisCC);
4212 }
4213 else
4214 rc = VERR_NET_DOWN;
4215 if (RT_FAILURE(rc))
4216 {
4217 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4218 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4219 }
4220
4221 pThis->led.Actual.s.fWriting = 0;
4222}
4223
4224/**
4225 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4226 *
4227 * @param pThis The device state structure.
4228 * @param pPkt Pointer to the packet.
4229 * @param u16PktLen Total length of the packet.
4230 * @param cso Offset in packet to write checksum at.
4231 * @param css Offset in packet to start computing
4232 * checksum from.
4233 * @param cse Offset in packet to stop computing
4234 * checksum at.
4235 * @param fUdp Replace 0 checksum with all 1s.
4236 * @thread E1000_TX
4237 */
4238static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse, bool fUdp = false)
4239{
4240 RT_NOREF1(pThis);
4241
4242 if (css >= u16PktLen)
4243 {
4244 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4245 pThis->szPrf, cso, u16PktLen));
4246 return;
4247 }
4248
4249 if (cso >= u16PktLen - 1)
4250 {
4251 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4252 pThis->szPrf, cso, u16PktLen));
4253 return;
4254 }
4255
4256 if (cse == 0 || cse >= u16PktLen)
4257 cse = u16PktLen - 1;
4258 else if (cse < css)
4259 {
4260 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4261 pThis->szPrf, css, cse));
4262 return;
4263 }
4264
4265 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4266 if (fUdp && u16ChkSum == 0)
4267 u16ChkSum = ~u16ChkSum; /* 0 means no checksum computed in case of UDP (see @bugref{9883}) */
4268 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4269 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4270 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4271}
4272
4273/**
4274 * Add a part of descriptor's buffer to transmit frame.
4275 *
4276 * @remarks data.u64BufAddr is used unconditionally for both data
4277 * and legacy descriptors since it is identical to
4278 * legacy.u64BufAddr.
4279 *
4280 * @param pDevIns The device instance.
4281 * @param pThis The device state structure.
4282 * @param pDesc Pointer to the descriptor to transmit.
4283 * @param u16Len Length of buffer to the end of segment.
4284 * @param fSend Force packet sending.
4285 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4286 * @thread E1000_TX
4287 */
4288#ifndef E1K_WITH_TXD_CACHE
4289static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4290{
4291 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4292 /* TCP header being transmitted */
4293 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4294 /* IP header being transmitted */
4295 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4296
4297 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4298 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4299 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4300
4301 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4302 E1kLog3(("%s Dump of the segment:\n"
4303 "%.*Rhxd\n"
4304 "%s --- End of dump ---\n",
4305 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4306 pThis->u16TxPktLen += u16Len;
4307 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4308 pThis->szPrf, pThis->u16TxPktLen));
4309 if (pThis->u16HdrRemain > 0)
4310 {
4311 /* The header was not complete, check if it is now */
4312 if (u16Len >= pThis->u16HdrRemain)
4313 {
4314 /* The rest is payload */
4315 u16Len -= pThis->u16HdrRemain;
4316 pThis->u16HdrRemain = 0;
4317 /* Save partial checksum and flags */
4318 pThis->u32SavedCsum = pTcpHdr->chksum;
4319 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4320 /* Clear FIN and PSH flags now and set them only in the last segment */
4321 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4322 }
4323 else
4324 {
4325 /* Still not */
4326 pThis->u16HdrRemain -= u16Len;
4327 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4328 pThis->szPrf, pThis->u16HdrRemain));
4329 return;
4330 }
4331 }
4332
4333 pThis->u32PayRemain -= u16Len;
4334
4335 if (fSend)
4336 {
4337 /* Leave ethernet header intact */
4338 /* IP Total Length = payload + headers - ethernet header */
4339 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4340 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4341 pThis->szPrf, ntohs(pIpHdr->total_len)));
4342 /* Update IP Checksum */
4343 pIpHdr->chksum = 0;
4344 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4345 pThis->contextTSE.ip.u8CSO,
4346 pThis->contextTSE.ip.u8CSS,
4347 pThis->contextTSE.ip.u16CSE);
4348
4349 /* Update TCP flags */
4350 /* Restore original FIN and PSH flags for the last segment */
4351 if (pThis->u32PayRemain == 0)
4352 {
4353 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4354 E1K_INC_CNT32(TSCTC);
4355 }
4356 /* Add TCP length to partial pseudo header sum */
4357 uint32_t csum = pThis->u32SavedCsum
4358 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4359 while (csum >> 16)
4360 csum = (csum >> 16) + (csum & 0xFFFF);
4361 pTcpHdr->chksum = csum;
4362 /* Compute final checksum */
4363 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4364 pThis->contextTSE.tu.u8CSO,
4365 pThis->contextTSE.tu.u8CSS,
4366 pThis->contextTSE.tu.u16CSE);
4367
4368 /*
4369 * Transmit it. If we've use the SG already, allocate a new one before
4370 * we copy of the data.
4371 */
4372 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4373 if (!pTxSg)
4374 {
4375 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4376 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4377 }
4378 if (pTxSg)
4379 {
4380 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4381 Assert(pTxSg->cSegs == 1);
4382 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4383 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4384 pTxSg->cbUsed = pThis->u16TxPktLen;
4385 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4386 }
4387 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4388
4389 /* Update Sequence Number */
4390 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4391 - pThis->contextTSE.dw3.u8HDRLEN);
4392 /* Increment IP identification */
4393 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4394 }
4395}
4396#else /* E1K_WITH_TXD_CACHE */
4397static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4398{
4399 int rc = VINF_SUCCESS;
4400 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4401 /* TCP header being transmitted */
4402 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4403 /* IP header being transmitted */
4404 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4405
4406 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4407 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4408 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4409
4410 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4411 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4412 else
4413 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4414 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4415 E1kLog3(("%s Dump of the segment:\n"
4416 "%.*Rhxd\n"
4417 "%s --- End of dump ---\n",
4418 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4419 pThis->u16TxPktLen += u16Len;
4420 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4421 pThis->szPrf, pThis->u16TxPktLen));
4422 if (pThis->u16HdrRemain > 0)
4423 {
4424 /* The header was not complete, check if it is now */
4425 if (u16Len >= pThis->u16HdrRemain)
4426 {
4427 /* The rest is payload */
4428 u16Len -= pThis->u16HdrRemain;
4429 pThis->u16HdrRemain = 0;
4430 /* Save partial checksum and flags */
4431 pThis->u32SavedCsum = pTcpHdr->chksum;
4432 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4433 /* Clear FIN and PSH flags now and set them only in the last segment */
4434 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4435 }
4436 else
4437 {
4438 /* Still not */
4439 pThis->u16HdrRemain -= u16Len;
4440 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4441 pThis->szPrf, pThis->u16HdrRemain));
4442 return rc;
4443 }
4444 }
4445
4446 if (u16Len > pThis->u32PayRemain)
4447 pThis->u32PayRemain = 0;
4448 else
4449 pThis->u32PayRemain -= u16Len;
4450
4451 if (fSend)
4452 {
4453 /* Leave ethernet header intact */
4454 /* IP Total Length = payload + headers - ethernet header */
4455 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4456 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4457 pThis->szPrf, ntohs(pIpHdr->total_len)));
4458 /* Update IP Checksum */
4459 pIpHdr->chksum = 0;
4460 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4461 pThis->contextTSE.ip.u8CSO,
4462 pThis->contextTSE.ip.u8CSS,
4463 pThis->contextTSE.ip.u16CSE);
4464
4465 /* Update TCP flags */
4466 /* Restore original FIN and PSH flags for the last segment */
4467 if (pThis->u32PayRemain == 0)
4468 {
4469 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4470 E1K_INC_CNT32(TSCTC);
4471 }
4472 /* Add TCP length to partial pseudo header sum */
4473 uint32_t csum = pThis->u32SavedCsum
4474 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4475 while (csum >> 16)
4476 csum = (csum >> 16) + (csum & 0xFFFF);
4477 Assert(csum < 65536);
4478 pTcpHdr->chksum = (uint16_t)csum;
4479 /* Compute final checksum */
4480 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4481 pThis->contextTSE.tu.u8CSO,
4482 pThis->contextTSE.tu.u8CSS,
4483 pThis->contextTSE.tu.u16CSE);
4484
4485 /*
4486 * Transmit it.
4487 */
4488 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4489 if (pTxSg)
4490 {
4491 /* Make sure the packet fits into the allocated buffer */
4492 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4493#ifdef DEBUG
4494 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4495 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4496 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4497#endif /* DEBUG */
4498 Assert(pTxSg->cSegs == 1);
4499 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4500 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4501 pTxSg->cbUsed = cbCopy;
4502 pTxSg->aSegs[0].cbSeg = cbCopy;
4503 }
4504 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4505
4506 /* Update Sequence Number */
4507 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4508 - pThis->contextTSE.dw3.u8HDRLEN);
4509 /* Increment IP identification */
4510 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4511
4512 /* Allocate new buffer for the next segment. */
4513 if (pThis->u32PayRemain)
4514 {
4515 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4516 pThis->contextTSE.dw3.u16MSS)
4517 + pThis->contextTSE.dw3.u8HDRLEN;
4518 /* Do not add VLAN tags to empty packets. */
4519 if (pThis->fVTag && pThis->cbTxAlloc > 0)
4520 pThis->cbTxAlloc += 4;
4521 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4522 }
4523 }
4524
4525 return rc;
4526}
4527#endif /* E1K_WITH_TXD_CACHE */
4528
4529#ifndef E1K_WITH_TXD_CACHE
4530/**
4531 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4532 * frame.
4533 *
4534 * We construct the frame in the fallback buffer first and the copy it to the SG
4535 * buffer before passing it down to the network driver code.
4536 *
4537 * @returns true if the frame should be transmitted, false if not.
4538 *
4539 * @param pThis The device state structure.
4540 * @param pDesc Pointer to the descriptor to transmit.
4541 * @param cbFragment Length of descriptor's buffer.
4542 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4543 * @thread E1000_TX
4544 */
4545static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4546{
4547 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4548 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4549 Assert(pDesc->data.cmd.fTSE);
4550 Assert(!e1kXmitIsGsoBuf(pTxSg));
4551
4552 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4553 Assert(u16MaxPktLen != 0);
4554 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4555
4556 /*
4557 * Carve out segments.
4558 */
4559 do
4560 {
4561 /* Calculate how many bytes we have left in this TCP segment */
4562 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4563 if (cb > cbFragment)
4564 {
4565 /* This descriptor fits completely into current segment */
4566 cb = cbFragment;
4567 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4568 }
4569 else
4570 {
4571 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4572 /*
4573 * Rewind the packet tail pointer to the beginning of payload,
4574 * so we continue writing right beyond the header.
4575 */
4576 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4577 }
4578
4579 pDesc->data.u64BufAddr += cb;
4580 cbFragment -= cb;
4581 } while (cbFragment > 0);
4582
4583 if (pDesc->data.cmd.fEOP)
4584 {
4585 /* End of packet, next segment will contain header. */
4586 if (pThis->u32PayRemain != 0)
4587 E1K_INC_CNT32(TSCTFC);
4588 pThis->u16TxPktLen = 0;
4589 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4590 }
4591
4592 return false;
4593}
4594#else /* E1K_WITH_TXD_CACHE */
4595/**
4596 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4597 * frame.
4598 *
4599 * We construct the frame in the fallback buffer first and the copy it to the SG
4600 * buffer before passing it down to the network driver code.
4601 *
4602 * @returns error code
4603 *
4604 * @param pDevIns The device instance.
4605 * @param pThis The device state structure.
4606 * @param pDesc Pointer to the descriptor to transmit.
4607 * @param cbFragment Length of descriptor's buffer.
4608 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4609 * @thread E1000_TX
4610 */
4611static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4612{
4613#ifdef VBOX_STRICT
4614 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4615 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4616 Assert(pDesc->data.cmd.fTSE);
4617 Assert(!e1kXmitIsGsoBuf(pTxSg));
4618#endif
4619
4620 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4621 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4622 if (u16MaxPktLen == 0)
4623 return VINF_SUCCESS;
4624
4625 /*
4626 * Carve out segments.
4627 */
4628 int rc = VINF_SUCCESS;
4629 do
4630 {
4631 /* Calculate how many bytes we have left in this TCP segment */
4632 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4633 if (cb > pDesc->data.cmd.u20DTALEN)
4634 {
4635 /* This descriptor fits completely into current segment */
4636 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4637 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4638 }
4639 else
4640 {
4641 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4642 /*
4643 * Rewind the packet tail pointer to the beginning of payload,
4644 * so we continue writing right beyond the header.
4645 */
4646 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4647 }
4648
4649 pDesc->data.u64BufAddr += cb;
4650 pDesc->data.cmd.u20DTALEN -= cb;
4651 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4652
4653 if (pDesc->data.cmd.fEOP)
4654 {
4655 /* End of packet, next segment will contain header. */
4656 if (pThis->u32PayRemain != 0)
4657 E1K_INC_CNT32(TSCTFC);
4658 pThis->u16TxPktLen = 0;
4659 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4660 }
4661
4662 return VINF_SUCCESS; /// @todo consider rc;
4663}
4664#endif /* E1K_WITH_TXD_CACHE */
4665
4666
4667/**
4668 * Add descriptor's buffer to transmit frame.
4669 *
4670 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4671 * TSE frames we cannot handle as GSO.
4672 *
4673 * @returns true on success, false on failure.
4674 *
4675 * @param pDevIns The device instance.
4676 * @param pThisCC The current context instance data.
4677 * @param pThis The device state structure.
4678 * @param PhysAddr The physical address of the descriptor buffer.
4679 * @param cbFragment Length of descriptor's buffer.
4680 * @thread E1000_TX
4681 */
4682static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4683{
4684 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4685 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4686 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4687
4688 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4689 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4690 fGso ? "true" : "false"));
4691 PCPDMNETWORKGSO pGso = (PCPDMNETWORKGSO)pTxSg->pvUser;
4692 if (pGso)
4693 {
4694 if (RT_UNLIKELY(pGso->cbMaxSeg == 0))
4695 {
4696 E1kLog(("%s zero-sized fragments are not allowed\n", pThis->szPrf));
4697 return false;
4698 }
4699 if (RT_UNLIKELY(pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP))
4700 {
4701 E1kLog(("%s UDP fragmentation is no longer supported\n", pThis->szPrf));
4702 return false;
4703 }
4704 }
4705 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4706 {
4707 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4708 return false;
4709 }
4710 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4711 {
4712 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4713 return false;
4714 }
4715
4716 if (RT_LIKELY(pTxSg))
4717 {
4718 Assert(pTxSg->cSegs == 1);
4719 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4720 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4721 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4722
4723 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4724
4725 pTxSg->cbUsed = cbNewPkt;
4726 }
4727 pThis->u16TxPktLen = cbNewPkt;
4728
4729 return true;
4730}
4731
4732
4733/**
4734 * Write the descriptor back to guest memory and notify the guest.
4735 *
4736 * @param pThis The device state structure.
4737 * @param pDesc Pointer to the descriptor have been transmitted.
4738 * @param addr Physical address of the descriptor in guest memory.
4739 * @thread E1000_TX
4740 */
4741static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4742{
4743 /*
4744 * We fake descriptor write-back bursting. Descriptors are written back as they are
4745 * processed.
4746 */
4747 /* Let's pretend we process descriptors. Write back with DD set. */
4748 /*
4749 * Prior to r71586 we tried to accomodate the case when write-back bursts
4750 * are enabled without actually implementing bursting by writing back all
4751 * descriptors, even the ones that do not have RS set. This caused kernel
4752 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4753 * associated with written back descriptor if it happened to be a context
4754 * descriptor since context descriptors do not have skb associated to them.
4755 * Starting from r71586 we write back only the descriptors with RS set,
4756 * which is a little bit different from what the real hardware does in
4757 * case there is a chain of data descritors where some of them have RS set
4758 * and others do not. It is very uncommon scenario imho.
4759 * We need to check RPS as well since some legacy drivers use it instead of
4760 * RS even with newer cards.
4761 */
4762 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4763 {
4764 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4765 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4766 if (pDesc->legacy.cmd.fEOP)
4767 {
4768//#ifdef E1K_USE_TX_TIMERS
4769 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4770 {
4771 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4772 //if (pThis->fIntRaised)
4773 //{
4774 // /* Interrupt is already pending, no need for timers */
4775 // ICR |= ICR_TXDW;
4776 //}
4777 //else {
4778 /* Arm the timer to fire in TIVD usec (discard .024) */
4779 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4780# ifndef E1K_NO_TAD
4781 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4782 E1kLog2(("%s Checking if TAD timer is running\n",
4783 pThis->szPrf));
4784 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4785 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4786# endif /* E1K_NO_TAD */
4787 }
4788 else
4789 {
4790 if (pThis->fTidEnabled)
4791 {
4792 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4793 pThis->szPrf));
4794 /* Cancel both timers if armed and fire immediately. */
4795# ifndef E1K_NO_TAD
4796 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4797# endif
4798 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4799 }
4800//#endif /* E1K_USE_TX_TIMERS */
4801 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4802 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4803//#ifdef E1K_USE_TX_TIMERS
4804 }
4805//#endif /* E1K_USE_TX_TIMERS */
4806 }
4807 }
4808 else
4809 {
4810 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4811 }
4812}
4813
4814#ifndef E1K_WITH_TXD_CACHE
4815
4816/**
4817 * Process Transmit Descriptor.
4818 *
4819 * E1000 supports three types of transmit descriptors:
4820 * - legacy data descriptors of older format (context-less).
4821 * - data the same as legacy but providing new offloading capabilities.
4822 * - context sets up the context for following data descriptors.
4823 *
4824 * @param pDevIns The device instance.
4825 * @param pThis The device state structure.
4826 * @param pThisCC The current context instance data.
4827 * @param pDesc Pointer to descriptor union.
4828 * @param addr Physical address of descriptor in guest memory.
4829 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4830 * @thread E1000_TX
4831 */
4832static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4833 RTGCPHYS addr, bool fOnWorkerThread)
4834{
4835 int rc = VINF_SUCCESS;
4836 uint32_t cbVTag = 0;
4837
4838 e1kPrintTDesc(pThis, pDesc, "vvv");
4839
4840//#ifdef E1K_USE_TX_TIMERS
4841 if (pThis->fTidEnabled)
4842 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4843//#endif /* E1K_USE_TX_TIMERS */
4844
4845 switch (e1kGetDescType(pDesc))
4846 {
4847 case E1K_DTYP_CONTEXT:
4848 if (pDesc->context.dw2.fTSE)
4849 {
4850 pThis->contextTSE = pDesc->context;
4851 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4852 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4853 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4854 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4855 }
4856 else
4857 {
4858 pThis->contextNormal = pDesc->context;
4859 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4860 }
4861 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4862 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4863 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4864 pDesc->context.ip.u8CSS,
4865 pDesc->context.ip.u8CSO,
4866 pDesc->context.ip.u16CSE,
4867 pDesc->context.tu.u8CSS,
4868 pDesc->context.tu.u8CSO,
4869 pDesc->context.tu.u16CSE));
4870 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4871 e1kDescReport(pThis, pDesc, addr);
4872 break;
4873
4874 case E1K_DTYP_DATA:
4875 {
4876 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4877 {
4878 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4879 /** @todo Same as legacy when !TSE. See below. */
4880 break;
4881 }
4882 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4883 &pThis->StatTxDescTSEData:
4884 &pThis->StatTxDescData);
4885 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4886 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4887
4888 /*
4889 * The last descriptor of non-TSE packet must contain VLE flag.
4890 * TSE packets have VLE flag in the first descriptor. The later
4891 * case is taken care of a bit later when cbVTag gets assigned.
4892 *
4893 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4894 */
4895 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4896 {
4897 pThis->fVTag = pDesc->data.cmd.fVLE;
4898 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4899 }
4900 /*
4901 * First fragment: Allocate new buffer and save the IXSM and TXSM
4902 * packet options as these are only valid in the first fragment.
4903 */
4904 if (pThis->u16TxPktLen == 0)
4905 {
4906 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4907 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4908 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4909 pThis->fIPcsum ? " IP" : "",
4910 pThis->fTCPcsum ? " TCP/UDP" : ""));
4911 if (pDesc->data.cmd.fTSE)
4912 {
4913 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4914 pThis->fVTag = pDesc->data.cmd.fVLE;
4915 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4916 cbVTag = pThis->fVTag ? 4 : 0;
4917 }
4918 else if (pDesc->data.cmd.fEOP)
4919 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4920 else
4921 cbVTag = 4;
4922 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4923 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4924 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4925 true /*fExactSize*/, true /*fGso*/);
4926 else if (pDesc->data.cmd.fTSE)
4927 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4928 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4929 else
4930 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4931 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4932
4933 /**
4934 * @todo: Perhaps it is not that simple for GSO packets! We may
4935 * need to unwind some changes.
4936 */
4937 if (RT_FAILURE(rc))
4938 {
4939 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4940 break;
4941 }
4942 /** @todo Is there any way to indicating errors other than collisions? Like
4943 * VERR_NET_DOWN. */
4944 }
4945
4946 /*
4947 * Add the descriptor data to the frame. If the frame is complete,
4948 * transmit it and reset the u16TxPktLen field.
4949 */
4950 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
4951 {
4952 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4953 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4954 if (pDesc->data.cmd.fEOP)
4955 {
4956 if ( fRc
4957 && pThisCC->CTX_SUFF(pTxSg)
4958 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
4959 {
4960 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4961 E1K_INC_CNT32(TSCTC);
4962 }
4963 else
4964 {
4965 if (fRc)
4966 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
4967 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
4968 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
4969 e1kXmitFreeBuf(pThis);
4970 E1K_INC_CNT32(TSCTFC);
4971 }
4972 pThis->u16TxPktLen = 0;
4973 }
4974 }
4975 else if (!pDesc->data.cmd.fTSE)
4976 {
4977 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
4978 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
4979 if (pDesc->data.cmd.fEOP)
4980 {
4981 if (fRc && pThisCC->CTX_SUFF(pTxSg))
4982 {
4983 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
4984 if (pThis->fIPcsum)
4985 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4986 pThis->contextNormal.ip.u8CSO,
4987 pThis->contextNormal.ip.u8CSS,
4988 pThis->contextNormal.ip.u16CSE);
4989 if (pThis->fTCPcsum)
4990 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
4991 pThis->contextNormal.tu.u8CSO,
4992 pThis->contextNormal.tu.u8CSS,
4993 pThis->contextNormal.tu.u16CSE,
4994 !pThis->contextNormal.dw2.fTCP);
4995 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4996 }
4997 else
4998 e1kXmitFreeBuf(pThis);
4999 pThis->u16TxPktLen = 0;
5000 }
5001 }
5002 else
5003 {
5004 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5005 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
5006 }
5007
5008 e1kDescReport(pThis, pDesc, addr);
5009 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5010 break;
5011 }
5012
5013 case E1K_DTYP_LEGACY:
5014 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5015 {
5016 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5017 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
5018 break;
5019 }
5020 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5021 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5022
5023 /* First fragment: allocate new buffer. */
5024 if (pThis->u16TxPktLen == 0)
5025 {
5026 if (pDesc->legacy.cmd.fEOP)
5027 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
5028 else
5029 cbVTag = 4;
5030 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
5031 /** @todo reset status bits? */
5032 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
5033 if (RT_FAILURE(rc))
5034 {
5035 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5036 break;
5037 }
5038
5039 /** @todo Is there any way to indicating errors other than collisions? Like
5040 * VERR_NET_DOWN. */
5041 }
5042
5043 /* Add fragment to frame. */
5044 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5045 {
5046 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5047
5048 /* Last fragment: Transmit and reset the packet storage counter. */
5049 if (pDesc->legacy.cmd.fEOP)
5050 {
5051 pThis->fVTag = pDesc->legacy.cmd.fVLE;
5052 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
5053 /** @todo Offload processing goes here. */
5054 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5055 pThis->u16TxPktLen = 0;
5056 }
5057 }
5058 /* Last fragment + failure: free the buffer and reset the storage counter. */
5059 else if (pDesc->legacy.cmd.fEOP)
5060 {
5061 e1kXmitFreeBuf(pThis);
5062 pThis->u16TxPktLen = 0;
5063 }
5064
5065 e1kDescReport(pThis, pDesc, addr);
5066 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5067 break;
5068
5069 default:
5070 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5071 pThis->szPrf, e1kGetDescType(pDesc)));
5072 break;
5073 }
5074
5075 return rc;
5076}
5077
5078#else /* E1K_WITH_TXD_CACHE */
5079
5080/**
5081 * Process Transmit Descriptor.
5082 *
5083 * E1000 supports three types of transmit descriptors:
5084 * - legacy data descriptors of older format (context-less).
5085 * - data the same as legacy but providing new offloading capabilities.
5086 * - context sets up the context for following data descriptors.
5087 *
5088 * @param pDevIns The device instance.
5089 * @param pThis The device state structure.
5090 * @param pThisCC The current context instance data.
5091 * @param pDesc Pointer to descriptor union.
5092 * @param addr Physical address of descriptor in guest memory.
5093 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
5094 * @param cbPacketSize Size of the packet as previously computed.
5095 * @thread E1000_TX
5096 */
5097static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
5098 RTGCPHYS addr, bool fOnWorkerThread)
5099{
5100 int rc = VINF_SUCCESS;
5101
5102 e1kPrintTDesc(pThis, pDesc, "vvv");
5103
5104 if (pDesc->legacy.dw3.fDD)
5105 {
5106 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
5107 e1kDescReport(pDevIns, pThis, pDesc, addr);
5108 return VINF_SUCCESS;
5109 }
5110
5111//#ifdef E1K_USE_TX_TIMERS
5112 if (pThis->fTidEnabled)
5113 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5114//#endif /* E1K_USE_TX_TIMERS */
5115
5116 switch (e1kGetDescType(pDesc))
5117 {
5118 case E1K_DTYP_CONTEXT:
5119 /* The caller have already updated the context */
5120 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5121 e1kDescReport(pDevIns, pThis, pDesc, addr);
5122 break;
5123
5124 case E1K_DTYP_DATA:
5125 {
5126 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5127 &pThis->StatTxDescTSEData:
5128 &pThis->StatTxDescData);
5129 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5130 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5131 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5132 {
5133 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
5134 if (pDesc->data.cmd.fEOP)
5135 {
5136 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5137 pThis->u16TxPktLen = 0;
5138 }
5139 }
5140 else
5141 {
5142 /*
5143 * Add the descriptor data to the frame. If the frame is complete,
5144 * transmit it and reset the u16TxPktLen field.
5145 */
5146 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5147 {
5148 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5149 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5150 if (pDesc->data.cmd.fEOP)
5151 {
5152 if ( fRc
5153 && pThisCC->CTX_SUFF(pTxSg)
5154 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5155 {
5156 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5157 E1K_INC_CNT32(TSCTC);
5158 }
5159 else
5160 {
5161 if (fRc)
5162 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5163 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5164 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5165 e1kXmitFreeBuf(pThis, pThisCC);
5166 E1K_INC_CNT32(TSCTFC);
5167 }
5168 pThis->u16TxPktLen = 0;
5169 }
5170 }
5171 else if (!pDesc->data.cmd.fTSE)
5172 {
5173 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5174 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5175 if (pDesc->data.cmd.fEOP)
5176 {
5177 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5178 {
5179 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5180 if (pThis->fIPcsum)
5181 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5182 pThis->contextNormal.ip.u8CSO,
5183 pThis->contextNormal.ip.u8CSS,
5184 pThis->contextNormal.ip.u16CSE);
5185 if (pThis->fTCPcsum)
5186 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5187 pThis->contextNormal.tu.u8CSO,
5188 pThis->contextNormal.tu.u8CSS,
5189 pThis->contextNormal.tu.u16CSE,
5190 !pThis->contextNormal.dw2.fTCP);
5191 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5192 }
5193 else
5194 e1kXmitFreeBuf(pThis, pThisCC);
5195 pThis->u16TxPktLen = 0;
5196 }
5197 }
5198 else
5199 {
5200 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5201 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5202 }
5203 }
5204 e1kDescReport(pDevIns, pThis, pDesc, addr);
5205 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5206 break;
5207 }
5208
5209 case E1K_DTYP_LEGACY:
5210 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5211 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5212 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5213 {
5214 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5215 }
5216 else
5217 {
5218 /* Add fragment to frame. */
5219 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5220 {
5221 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5222
5223 /* Last fragment: Transmit and reset the packet storage counter. */
5224 if (pDesc->legacy.cmd.fEOP)
5225 {
5226 if (pDesc->legacy.cmd.fIC)
5227 {
5228 e1kInsertChecksum(pThis,
5229 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5230 pThis->u16TxPktLen,
5231 pDesc->legacy.cmd.u8CSO,
5232 pDesc->legacy.dw3.u8CSS,
5233 0);
5234 }
5235 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5236 pThis->u16TxPktLen = 0;
5237 }
5238 }
5239 /* Last fragment + failure: free the buffer and reset the storage counter. */
5240 else if (pDesc->legacy.cmd.fEOP)
5241 {
5242 e1kXmitFreeBuf(pThis, pThisCC);
5243 pThis->u16TxPktLen = 0;
5244 }
5245 }
5246 e1kDescReport(pDevIns, pThis, pDesc, addr);
5247 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5248 break;
5249
5250 default:
5251 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5252 pThis->szPrf, e1kGetDescType(pDesc)));
5253 break;
5254 }
5255
5256 return rc;
5257}
5258
5259DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5260{
5261 if (pDesc->context.dw2.fTSE)
5262 {
5263 pThis->contextTSE = pDesc->context;
5264 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5265 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5266 {
5267 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5268 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5269 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5270 }
5271 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5272 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5273 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5274 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5275 }
5276 else
5277 {
5278 pThis->contextNormal = pDesc->context;
5279 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5280 }
5281 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5282 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5283 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5284 pDesc->context.ip.u8CSS,
5285 pDesc->context.ip.u8CSO,
5286 pDesc->context.ip.u16CSE,
5287 pDesc->context.tu.u8CSS,
5288 pDesc->context.tu.u8CSO,
5289 pDesc->context.tu.u16CSE));
5290}
5291
5292static bool e1kLocateTxPacket(PE1KSTATE pThis)
5293{
5294 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5295 pThis->szPrf, pThis->cbTxAlloc));
5296 /* Check if we have located the packet already. */
5297 if (pThis->cbTxAlloc)
5298 {
5299 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5300 pThis->szPrf, pThis->cbTxAlloc));
5301 return true;
5302 }
5303
5304 bool fTSE = false;
5305 uint32_t cbPacket = 0;
5306
5307 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5308 {
5309 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5310 switch (e1kGetDescType(pDesc))
5311 {
5312 case E1K_DTYP_CONTEXT:
5313 if (cbPacket == 0)
5314 e1kUpdateTxContext(pThis, pDesc);
5315 else
5316 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5317 pThis->szPrf, cbPacket));
5318 continue;
5319 case E1K_DTYP_LEGACY:
5320 /* Skip invalid descriptors. */
5321 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5322 {
5323 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5324 pThis->szPrf, cbPacket));
5325 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5326 continue;
5327 }
5328 /* Skip empty descriptors. */
5329 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5330 break;
5331 cbPacket += pDesc->legacy.cmd.u16Length;
5332 pThis->fGSO = false;
5333 break;
5334 case E1K_DTYP_DATA:
5335 /* Skip invalid descriptors. */
5336 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5337 {
5338 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5339 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5340 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5341 continue;
5342 }
5343 /* Skip empty descriptors. */
5344 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5345 break;
5346 if (cbPacket == 0)
5347 {
5348 /*
5349 * The first fragment: save IXSM and TXSM options
5350 * as these are only valid in the first fragment.
5351 */
5352 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5353 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5354 fTSE = pDesc->data.cmd.fTSE;
5355 /*
5356 * TSE descriptors have VLE bit properly set in
5357 * the first fragment.
5358 */
5359 if (fTSE)
5360 {
5361 pThis->fVTag = pDesc->data.cmd.fVLE;
5362 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5363 }
5364 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5365 }
5366 cbPacket += pDesc->data.cmd.u20DTALEN;
5367 break;
5368 default:
5369 AssertMsgFailed(("Impossible descriptor type!"));
5370 continue;
5371 }
5372 if (pDesc->legacy.cmd.fEOP)
5373 {
5374 /*
5375 * Non-TSE descriptors have VLE bit properly set in
5376 * the last fragment.
5377 */
5378 if (!fTSE)
5379 {
5380 pThis->fVTag = pDesc->data.cmd.fVLE;
5381 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5382 }
5383 /*
5384 * Compute the required buffer size. If we cannot do GSO but still
5385 * have to do segmentation we allocate the first segment only.
5386 */
5387 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5388 cbPacket :
5389 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5390 /* Do not add VLAN tags to empty packets. */
5391 if (pThis->fVTag && pThis->cbTxAlloc > 0)
5392 pThis->cbTxAlloc += 4;
5393 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5394 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5395 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5396 return true;
5397 }
5398 }
5399
5400 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5401 {
5402 /* All descriptors were empty, we need to process them as a dummy packet */
5403 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5404 pThis->szPrf, pThis->cbTxAlloc));
5405 return true;
5406 }
5407 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5408 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5409 return false;
5410}
5411
5412static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread, PE1KTXDC pTxdc)
5413{
5414 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5415 int rc = VINF_SUCCESS;
5416
5417 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5418 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5419
5420 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5421 {
5422 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5423 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5424 pThis->szPrf, TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC), pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
5425 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh), fOnWorkerThread);
5426 if (RT_FAILURE(rc))
5427 break;
5428 if (++pTxdc->tdh * sizeof(E1KTXDESC) >= pTxdc->tdlen)
5429 pTxdc->tdh = 0;
5430 TDH = pTxdc->tdh; /* Sync the actual register and TXDC */
5431 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5432 if (uLowThreshold != 0 && e1kGetTxLen(pTxdc) <= uLowThreshold)
5433 {
5434 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5435 pThis->szPrf, e1kGetTxLen(pTxdc), GET_BITS(TXDCTL, LWTHRESH)*8));
5436 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5437 }
5438 ++pThis->iTxDCurrent;
5439 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5440 break;
5441 }
5442
5443 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5444 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5445 return rc;
5446}
5447
5448#endif /* E1K_WITH_TXD_CACHE */
5449#ifndef E1K_WITH_TXD_CACHE
5450
5451/**
5452 * Transmit pending descriptors.
5453 *
5454 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5455 *
5456 * @param pDevIns The device instance.
5457 * @param pThis The E1000 state.
5458 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5459 */
5460static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5461{
5462 int rc = VINF_SUCCESS;
5463 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5464
5465 /* Check if transmitter is enabled. */
5466 if (!(TCTL & TCTL_EN))
5467 return VINF_SUCCESS;
5468 /*
5469 * Grab the xmit lock of the driver as well as the E1K device state.
5470 */
5471 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5472 if (RT_LIKELY(rc == VINF_SUCCESS))
5473 {
5474 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5475 if (pDrv)
5476 {
5477 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5478 if (RT_FAILURE(rc))
5479 {
5480 e1kCsTxLeave(pThis);
5481 return rc;
5482 }
5483 }
5484 /*
5485 * Process all pending descriptors.
5486 * Note! Do not process descriptors in locked state
5487 */
5488 while (TDH != TDT && !pThis->fLocked)
5489 {
5490 E1KTXDESC desc;
5491 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5492 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5493
5494 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5495 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5496 /* If we failed to transmit descriptor we will try it again later */
5497 if (RT_FAILURE(rc))
5498 break;
5499 if (++TDH * sizeof(desc) >= TDLEN)
5500 TDH = 0;
5501
5502 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5503 {
5504 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5505 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5506 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5507 }
5508
5509 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5510 }
5511
5512 /// @todo uncomment: pThis->uStatIntTXQE++;
5513 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5514 /*
5515 * Release the lock.
5516 */
5517 if (pDrv)
5518 pDrv->pfnEndXmit(pDrv);
5519 e1kCsTxLeave(pThis);
5520 }
5521
5522 return rc;
5523}
5524
5525#else /* E1K_WITH_TXD_CACHE */
5526
5527static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
5528{
5529 unsigned i, cDescs = pTxdc->tdlen / sizeof(E1KTXDESC);
5530 uint32_t tdh = pTxdc->tdh;
5531 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5532 for (i = 0; i < cDescs; ++i)
5533 {
5534 E1KTXDESC desc;
5535 PDMDevHlpPCIPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5536 if (i == tdh)
5537 LogRel(("E1000: >>> "));
5538 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5539 }
5540 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5541 pThis->iTxDCurrent, pTxdc->tdh, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5542 if (tdh > pThis->iTxDCurrent)
5543 tdh -= pThis->iTxDCurrent;
5544 else
5545 tdh = cDescs + tdh - pThis->iTxDCurrent;
5546 for (i = 0; i < pThis->nTxDFetched; ++i)
5547 {
5548 if (i == pThis->iTxDCurrent)
5549 LogRel(("E1000: >>> "));
5550 if (cDescs)
5551 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5552 else
5553 LogRel(("E1000: <lost>: %R[e1ktxd]\n", &pThis->aTxDescriptors[i]));
5554 }
5555}
5556
5557/**
5558 * Transmit pending descriptors.
5559 *
5560 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5561 *
5562 * @param pDevIns The device instance.
5563 * @param pThis The E1000 state.
5564 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5565 */
5566static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5567{
5568 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5569 int rc = VINF_SUCCESS;
5570
5571 /* Check if transmitter is enabled. */
5572 if (!(TCTL & TCTL_EN))
5573 return VINF_SUCCESS;
5574 /*
5575 * Grab the xmit lock of the driver as well as the E1K device state.
5576 */
5577 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5578 if (pDrv)
5579 {
5580 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5581 if (RT_FAILURE(rc))
5582 return rc;
5583 }
5584
5585 /*
5586 * Process all pending descriptors.
5587 * Note! Do not process descriptors in locked state
5588 */
5589 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5590 if (RT_LIKELY(rc == VINF_SUCCESS && (TCTL & TCTL_EN)))
5591 {
5592 E1KTXDC txdc;
5593 bool fTxContextValid = e1kUpdateTxDContext(pDevIns, pThis, &txdc);
5594 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5595 /*
5596 * fIncomplete is set whenever we try to fetch additional descriptors
5597 * for an incomplete packet. If fail to locate a complete packet on
5598 * the next iteration we need to reset the cache or we risk to get
5599 * stuck in this loop forever.
5600 */
5601 bool fIncomplete = false;
5602 while (fTxContextValid && !pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis, &txdc))
5603 {
5604 while (e1kLocateTxPacket(pThis))
5605 {
5606 fIncomplete = false;
5607 /* Found a complete packet, allocate it. */
5608 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5609 /* If we're out of bandwidth we'll come back later. */
5610 if (RT_FAILURE(rc))
5611 goto out;
5612 /* Copy the packet to allocated buffer and send it. */
5613 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread, &txdc);
5614 /* If we're out of bandwidth we'll come back later. */
5615 if (RT_FAILURE(rc))
5616 goto out;
5617 }
5618 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5619 if (RT_UNLIKELY(fIncomplete))
5620 {
5621 static bool fTxDCacheDumped = false;
5622 /*
5623 * The descriptor cache is full, but we were unable to find
5624 * a complete packet in it. Drop the cache and hope that
5625 * the guest driver can recover from network card error.
5626 */
5627 LogRel(("%s: No complete packets in%s TxD cache! "
5628 "Fetched=%d, current=%d, TX len=%d.\n",
5629 pThis->szPrf,
5630 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5631 pThis->nTxDFetched, pThis->iTxDCurrent,
5632 e1kGetTxLen(&txdc)));
5633 if (!fTxDCacheDumped)
5634 {
5635 fTxDCacheDumped = true;
5636 e1kDumpTxDCache(pDevIns, pThis, &txdc);
5637 }
5638 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5639 /*
5640 * Returning an error at this point means Guru in R0
5641 * (see @bugref{6428}).
5642 */
5643# ifdef IN_RING3
5644 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5645# else /* !IN_RING3 */
5646 rc = VINF_IOM_R3_MMIO_WRITE;
5647# endif /* !IN_RING3 */
5648 goto out;
5649 }
5650 if (u8Remain > 0)
5651 {
5652 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5653 "%d more are available\n",
5654 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5655 e1kGetTxLen(&txdc) - u8Remain));
5656
5657 /*
5658 * A packet was partially fetched. Move incomplete packet to
5659 * the beginning of cache buffer, then load more descriptors.
5660 */
5661 memmove(pThis->aTxDescriptors,
5662 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5663 u8Remain * sizeof(E1KTXDESC));
5664 pThis->iTxDCurrent = 0;
5665 pThis->nTxDFetched = u8Remain;
5666 e1kTxDLoadMore(pDevIns, pThis, &txdc);
5667 fIncomplete = true;
5668 }
5669 else
5670 pThis->nTxDFetched = 0;
5671 pThis->iTxDCurrent = 0;
5672 }
5673 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5674 {
5675 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5676 pThis->szPrf));
5677 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5678 }
5679out:
5680 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5681
5682 /// @todo uncomment: pThis->uStatIntTXQE++;
5683 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5684
5685 e1kCsTxLeave(pThis);
5686 }
5687
5688
5689 /*
5690 * Release the lock.
5691 */
5692 if (pDrv)
5693 pDrv->pfnEndXmit(pDrv);
5694 return rc;
5695}
5696
5697#endif /* E1K_WITH_TXD_CACHE */
5698#ifdef IN_RING3
5699
5700/**
5701 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5702 */
5703static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5704{
5705 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5706 PE1KSTATE pThis = pThisCC->pShared;
5707 /* Resume suspended transmission */
5708 STATUS &= ~STATUS_TXOFF;
5709 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5710}
5711
5712/**
5713 * @callback_method_impl{FNPDMTASKDEV,
5714 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5715 * @note Not executed on EMT.
5716 */
5717static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5718{
5719 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5720 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5721
5722 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5723 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5724
5725 RT_NOREF(rc, pvUser);
5726}
5727
5728#endif /* IN_RING3 */
5729
5730/**
5731 * Write handler for Transmit Descriptor Tail register.
5732 *
5733 * @param pThis The device state structure.
5734 * @param offset Register offset in memory-mapped frame.
5735 * @param index Register index in register array.
5736 * @param value The value to store.
5737 * @param mask Used to implement partial writes (8 and 16-bit).
5738 * @thread EMT
5739 */
5740static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5741{
5742 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5743
5744 /* All descriptors starting with head and not including tail belong to us. */
5745 /* Process them. */
5746 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5747 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5748
5749 /* Compose a temporary TX context, breaking TX CS rule, for debugging purposes. */
5750 /* If we decide to transmit, the TX critical section will be entered later in e1kXmitPending(). */
5751 E1KTXDC txdc;
5752 txdc.tdlen = TDLEN;
5753 txdc.tdh = TDH;
5754 txdc.tdt = TDT;
5755 /* Ignore TDT writes when the link is down. */
5756 if (txdc.tdh != txdc.tdt && (STATUS & STATUS_LU))
5757 {
5758 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", txdc.tdh, txdc.tdt, e1kGetTxLen(&txdc)));
5759 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5760 pThis->szPrf, e1kGetTxLen(&txdc)));
5761
5762 /* Transmit pending packets if possible, defer it if we cannot do it
5763 in the current context. */
5764#ifdef E1K_TX_DELAY
5765 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5766 if (RT_LIKELY(rc == VINF_SUCCESS))
5767 {
5768 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5769 {
5770# ifdef E1K_INT_STATS
5771 pThis->u64ArmedAt = RTTimeNanoTS();
5772# endif
5773 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5774 }
5775 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5776 e1kCsTxLeave(pThis);
5777 return rc;
5778 }
5779 /* We failed to enter the TX critical section -- transmit as usual. */
5780#endif /* E1K_TX_DELAY */
5781#ifndef IN_RING3
5782 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5783 if (!pThisCC->CTX_SUFF(pDrv))
5784 {
5785 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5786 rc = VINF_SUCCESS;
5787 }
5788 else
5789#endif
5790 {
5791 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5792 if (rc == VERR_TRY_AGAIN)
5793 rc = VINF_SUCCESS;
5794#ifndef IN_RING3
5795 else if (rc == VERR_SEM_BUSY)
5796 rc = VINF_IOM_R3_MMIO_WRITE;
5797#endif
5798 AssertRC(rc);
5799 }
5800 }
5801
5802 return rc;
5803}
5804
5805/**
5806 * Write handler for Multicast Table Array registers.
5807 *
5808 * @param pThis The device state structure.
5809 * @param offset Register offset in memory-mapped frame.
5810 * @param index Register index in register array.
5811 * @param value The value to store.
5812 * @thread EMT
5813 */
5814static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5815{
5816 RT_NOREF_PV(pDevIns);
5817 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5818 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5819
5820 return VINF_SUCCESS;
5821}
5822
5823/**
5824 * Read handler for Multicast Table Array registers.
5825 *
5826 * @returns VBox status code.
5827 *
5828 * @param pThis The device state structure.
5829 * @param offset Register offset in memory-mapped frame.
5830 * @param index Register index in register array.
5831 * @thread EMT
5832 */
5833static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5834{
5835 RT_NOREF_PV(pDevIns);
5836 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5837 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5838
5839 return VINF_SUCCESS;
5840}
5841
5842/**
5843 * Write handler for Receive Address registers.
5844 *
5845 * @param pThis The device state structure.
5846 * @param offset Register offset in memory-mapped frame.
5847 * @param index Register index in register array.
5848 * @param value The value to store.
5849 * @thread EMT
5850 */
5851static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5852{
5853 RT_NOREF_PV(pDevIns);
5854 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5855 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5856
5857 return VINF_SUCCESS;
5858}
5859
5860/**
5861 * Read handler for Receive Address registers.
5862 *
5863 * @returns VBox status code.
5864 *
5865 * @param pThis The device state structure.
5866 * @param offset Register offset in memory-mapped frame.
5867 * @param index Register index in register array.
5868 * @thread EMT
5869 */
5870static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5871{
5872 RT_NOREF_PV(pDevIns);
5873 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5874 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5875
5876 return VINF_SUCCESS;
5877}
5878
5879/**
5880 * Write handler for VLAN Filter Table Array registers.
5881 *
5882 * @param pThis The device state structure.
5883 * @param offset Register offset in memory-mapped frame.
5884 * @param index Register index in register array.
5885 * @param value The value to store.
5886 * @thread EMT
5887 */
5888static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5889{
5890 RT_NOREF_PV(pDevIns);
5891 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5892 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5893
5894 return VINF_SUCCESS;
5895}
5896
5897/**
5898 * Read handler for VLAN Filter Table Array registers.
5899 *
5900 * @returns VBox status code.
5901 *
5902 * @param pThis The device state structure.
5903 * @param offset Register offset in memory-mapped frame.
5904 * @param index Register index in register array.
5905 * @thread EMT
5906 */
5907static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5908{
5909 RT_NOREF_PV(pDevIns);
5910 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5911 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5912
5913 return VINF_SUCCESS;
5914}
5915
5916/**
5917 * Read handler for unimplemented registers.
5918 *
5919 * Merely reports reads from unimplemented registers.
5920 *
5921 * @returns VBox status code.
5922 *
5923 * @param pThis The device state structure.
5924 * @param offset Register offset in memory-mapped frame.
5925 * @param index Register index in register array.
5926 * @thread EMT
5927 */
5928static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5929{
5930 RT_NOREF(pDevIns, pThis, offset, index);
5931 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5932 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5933 *pu32Value = 0;
5934
5935 return VINF_SUCCESS;
5936}
5937
5938/**
5939 * Default register read handler with automatic clear operation.
5940 *
5941 * Retrieves the value of register from register array in device state structure.
5942 * Then resets all bits.
5943 *
5944 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5945 * done in the caller.
5946 *
5947 * @returns VBox status code.
5948 *
5949 * @param pThis The device state structure.
5950 * @param offset Register offset in memory-mapped frame.
5951 * @param index Register index in register array.
5952 * @thread EMT
5953 */
5954static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5955{
5956 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5957 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
5958 pThis->auRegs[index] = 0;
5959
5960 return rc;
5961}
5962
5963/**
5964 * Default register read handler.
5965 *
5966 * Retrieves the value of register from register array in device state structure.
5967 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
5968 *
5969 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5970 * done in the caller.
5971 *
5972 * @returns VBox status code.
5973 *
5974 * @param pThis The device state structure.
5975 * @param offset Register offset in memory-mapped frame.
5976 * @param index Register index in register array.
5977 * @thread EMT
5978 */
5979static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5980{
5981 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
5982
5983 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
5984 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
5985
5986 return VINF_SUCCESS;
5987}
5988
5989/**
5990 * Write handler for unimplemented registers.
5991 *
5992 * Merely reports writes to unimplemented registers.
5993 *
5994 * @param pThis The device state structure.
5995 * @param offset Register offset in memory-mapped frame.
5996 * @param index Register index in register array.
5997 * @param value The value to store.
5998 * @thread EMT
5999 */
6000
6001 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6002{
6003 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
6004
6005 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
6006 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6007
6008 return VINF_SUCCESS;
6009}
6010
6011/**
6012 * Default register write handler.
6013 *
6014 * Stores the value to the register array in device state structure. Only bits
6015 * corresponding to 1s both in 'writable' and 'mask' will be stored.
6016 *
6017 * @returns VBox status code.
6018 *
6019 * @param pThis The device state structure.
6020 * @param offset Register offset in memory-mapped frame.
6021 * @param index Register index in register array.
6022 * @param value The value to store.
6023 * @param mask Used to implement partial writes (8 and 16-bit).
6024 * @thread EMT
6025 */
6026
6027static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6028{
6029 RT_NOREF(pDevIns, offset);
6030
6031 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6032 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
6033 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
6034
6035 return VINF_SUCCESS;
6036}
6037
6038/**
6039 * Search register table for matching register.
6040 *
6041 * @returns Index in the register table or -1 if not found.
6042 *
6043 * @param offReg Register offset in memory-mapped region.
6044 * @thread EMT
6045 */
6046static int e1kRegLookup(uint32_t offReg)
6047{
6048
6049#if 0
6050 int index;
6051
6052 for (index = 0; index < E1K_NUM_OF_REGS; index++)
6053 {
6054 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
6055 {
6056 return index;
6057 }
6058 }
6059#else
6060 int iStart = 0;
6061 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
6062 for (;;)
6063 {
6064 int i = (iEnd - iStart) / 2 + iStart;
6065 uint32_t offCur = g_aE1kRegMap[i].offset;
6066 if (offReg < offCur)
6067 {
6068 if (i == iStart)
6069 break;
6070 iEnd = i;
6071 }
6072 else if (offReg >= offCur + g_aE1kRegMap[i].size)
6073 {
6074 i++;
6075 if (i == iEnd)
6076 break;
6077 iStart = i;
6078 }
6079 else
6080 return i;
6081 Assert(iEnd > iStart);
6082 }
6083
6084 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6085 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
6086 return (int)i;
6087
6088# ifdef VBOX_STRICT
6089 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6090 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
6091# endif
6092
6093#endif
6094
6095 return -1;
6096}
6097
6098/**
6099 * Handle unaligned register read operation.
6100 *
6101 * Looks up and calls appropriate handler.
6102 *
6103 * @returns VBox status code.
6104 *
6105 * @param pDevIns The device instance.
6106 * @param pThis The device state structure.
6107 * @param offReg Register offset in memory-mapped frame.
6108 * @param pv Where to store the result.
6109 * @param cb Number of bytes to read.
6110 * @thread EMT
6111 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
6112 * accesses we have to take care of that ourselves.
6113 */
6114static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
6115{
6116 uint32_t u32 = 0;
6117 uint32_t shift;
6118 int rc = VINF_SUCCESS;
6119 int index = e1kRegLookup(offReg);
6120#ifdef LOG_ENABLED
6121 char buf[9];
6122#endif
6123
6124 /*
6125 * From the spec:
6126 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6127 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6128 */
6129
6130 /*
6131 * To be able to read bytes and short word we convert them to properly
6132 * shifted 32-bit words and masks. The idea is to keep register-specific
6133 * handlers simple. Most accesses will be 32-bit anyway.
6134 */
6135 uint32_t mask;
6136 switch (cb)
6137 {
6138 case 4: mask = 0xFFFFFFFF; break;
6139 case 2: mask = 0x0000FFFF; break;
6140 case 1: mask = 0x000000FF; break;
6141 default:
6142 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6143 }
6144 if (index >= 0)
6145 {
6146 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6147 if (g_aE1kRegMap[index].readable)
6148 {
6149 /* Make the mask correspond to the bits we are about to read. */
6150 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6151 mask <<= shift;
6152 if (!mask)
6153 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6154 /*
6155 * Read it. Pass the mask so the handler knows what has to be read.
6156 * Mask out irrelevant bits.
6157 */
6158 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6159 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6160 return rc;
6161 //pThis->fDelayInts = false;
6162 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6163 //pThis->iStatIntLostOne = 0;
6164 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6165 u32 &= mask;
6166 //e1kCsLeave(pThis);
6167 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6168 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6169 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6170 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6171 /* Shift back the result. */
6172 u32 >>= shift;
6173 }
6174 else
6175 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6176 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6177 if (IOM_SUCCESS(rc))
6178 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6179 }
6180 else
6181 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6182 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6183
6184 memcpy(pv, &u32, cb);
6185 return rc;
6186}
6187
6188/**
6189 * Handle 4 byte aligned and sized read operation.
6190 *
6191 * Looks up and calls appropriate handler.
6192 *
6193 * @returns VBox status code.
6194 *
6195 * @param pDevIns The device instance.
6196 * @param pThis The device state structure.
6197 * @param offReg Register offset in memory-mapped frame.
6198 * @param pu32 Where to store the result.
6199 * @thread EMT
6200 */
6201static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6202{
6203 Assert(!(offReg & 3));
6204
6205 /*
6206 * Lookup the register and check that it's readable.
6207 */
6208 VBOXSTRICTRC rc = VINF_SUCCESS;
6209 int idxReg = e1kRegLookup(offReg);
6210 if (RT_LIKELY(idxReg >= 0))
6211 {
6212 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6213 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6214 {
6215 /*
6216 * Read it. Pass the mask so the handler knows what has to be read.
6217 * Mask out irrelevant bits.
6218 */
6219 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6220 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6221 // return rc;
6222 //pThis->fDelayInts = false;
6223 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6224 //pThis->iStatIntLostOne = 0;
6225 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6226 //e1kCsLeave(pThis);
6227 Log6(("%s At %08X read %08X from %s (%s)\n",
6228 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6229 if (IOM_SUCCESS(rc))
6230 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6231 }
6232 else
6233 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6234 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6235 }
6236 else
6237 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6238 return rc;
6239}
6240
6241/**
6242 * Handle 4 byte sized and aligned register write operation.
6243 *
6244 * Looks up and calls appropriate handler.
6245 *
6246 * @returns VBox status code.
6247 *
6248 * @param pDevIns The device instance.
6249 * @param pThis The device state structure.
6250 * @param offReg Register offset in memory-mapped frame.
6251 * @param u32Value The value to write.
6252 * @thread EMT
6253 */
6254static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6255{
6256 VBOXSTRICTRC rc = VINF_SUCCESS;
6257 int index = e1kRegLookup(offReg);
6258 if (RT_LIKELY(index >= 0))
6259 {
6260 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6261 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6262 {
6263 /*
6264 * Write it. Pass the mask so the handler knows what has to be written.
6265 * Mask out irrelevant bits.
6266 */
6267 Log6(("%s At %08X write %08X to %s (%s)\n",
6268 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6269 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6270 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6271 // return rc;
6272 //pThis->fDelayInts = false;
6273 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6274 //pThis->iStatIntLostOne = 0;
6275 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6276 //e1kCsLeave(pThis);
6277 }
6278 else
6279 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6280 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6281 if (IOM_SUCCESS(rc))
6282 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6283 }
6284 else
6285 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6286 pThis->szPrf, offReg, u32Value));
6287 return rc;
6288}
6289
6290
6291/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6292
6293/**
6294 * @callback_method_impl{FNIOMMMIONEWREAD}
6295 */
6296static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6297{
6298 RT_NOREF2(pvUser, cb);
6299 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6300 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6301
6302 Assert(off < E1K_MM_SIZE);
6303 Assert(cb == 4);
6304 Assert(!(off & 3));
6305
6306 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6307
6308 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6309 return rcStrict;
6310}
6311
6312/**
6313 * @callback_method_impl{FNIOMMMIONEWWRITE}
6314 */
6315static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6316{
6317 RT_NOREF2(pvUser, cb);
6318 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6319 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6320
6321 Assert(off < E1K_MM_SIZE);
6322 Assert(cb == 4);
6323 Assert(!(off & 3));
6324
6325 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6326
6327 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6328 return rcStrict;
6329}
6330
6331/**
6332 * @callback_method_impl{FNIOMIOPORTNEWIN}
6333 */
6334static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6335{
6336 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6337 VBOXSTRICTRC rc;
6338 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6339 RT_NOREF_PV(pvUser);
6340
6341 if (RT_LIKELY(cb == 4))
6342 switch (offPort)
6343 {
6344 case 0x00: /* IOADDR */
6345 *pu32 = pThis->uSelectedReg;
6346 Log9(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6347 rc = VINF_SUCCESS;
6348 break;
6349
6350 case 0x04: /* IODATA */
6351 if (!(pThis->uSelectedReg & 3))
6352 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6353 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6354 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6355 if (rc == VINF_IOM_R3_MMIO_READ)
6356 rc = VINF_IOM_R3_IOPORT_READ;
6357 Log9(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6358 break;
6359
6360 default:
6361 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6362 /** @todo r=bird: Check what real hardware returns here. */
6363 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6364 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6365 break;
6366 }
6367 else
6368 {
6369 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6370 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6371 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6372 }
6373 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6374 return rc;
6375}
6376
6377
6378/**
6379 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6380 */
6381static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6382{
6383 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6384 VBOXSTRICTRC rc;
6385 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6386 RT_NOREF_PV(pvUser);
6387
6388 Log9(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6389 if (RT_LIKELY(cb == 4))
6390 {
6391 switch (offPort)
6392 {
6393 case 0x00: /* IOADDR */
6394 pThis->uSelectedReg = u32;
6395 Log9(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6396 rc = VINF_SUCCESS;
6397 break;
6398
6399 case 0x04: /* IODATA */
6400 Log9(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6401 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6402 {
6403 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6404 if (rc == VINF_IOM_R3_MMIO_WRITE)
6405 rc = VINF_IOM_R3_IOPORT_WRITE;
6406 }
6407 else
6408 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6409 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6410 break;
6411
6412 default:
6413 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6414 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6415 }
6416 }
6417 else
6418 {
6419 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6420 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6421 }
6422
6423 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6424 return rc;
6425}
6426
6427#ifdef IN_RING3
6428
6429/**
6430 * Dump complete device state to log.
6431 *
6432 * @param pThis Pointer to device state.
6433 */
6434static void e1kDumpState(PE1KSTATE pThis)
6435{
6436 RT_NOREF(pThis);
6437 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6438 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6439# ifdef E1K_INT_STATS
6440 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6441 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6442 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6443 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6444 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6445 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6446 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6447 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6448 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6449 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6450 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6451 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6452 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6453 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6454 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6455 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6456 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6457 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6458 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6459 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6460 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6461 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6462 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6463 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6464 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6465 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6466 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6467 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6468 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6469 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6470 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6471 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6472 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6473 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6474 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6475 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6476 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6477 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6478 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6479# endif /* E1K_INT_STATS */
6480}
6481
6482
6483/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6484
6485/**
6486 * Check if the device can receive data now.
6487 * This must be called before the pfnRecieve() method is called.
6488 *
6489 * @returns Number of bytes the device can receive.
6490 * @param pDevIns The device instance.
6491 * @param pThis The instance data.
6492 * @thread EMT
6493 */
6494static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6495{
6496#ifndef E1K_WITH_RXD_CACHE
6497 size_t cb;
6498
6499 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6500 return VERR_NET_NO_BUFFER_SPACE;
6501
6502 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6503 {
6504 E1KRXDESC desc;
6505 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6506 if (desc.status.fDD)
6507 cb = 0;
6508 else
6509 cb = pThis->u16RxBSize;
6510 }
6511 else if (RDH < RDT)
6512 cb = (RDT - RDH) * pThis->u16RxBSize;
6513 else if (RDH > RDT)
6514 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6515 else
6516 {
6517 cb = 0;
6518 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6519 }
6520 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6521 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6522
6523 e1kCsRxLeave(pThis);
6524 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6525#else /* E1K_WITH_RXD_CACHE */
6526 int rc = VINF_SUCCESS;
6527
6528 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6529 return VERR_NET_NO_BUFFER_SPACE;
6530 E1KRXDC rxdc;
6531 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kCanReceive")))
6532 {
6533 e1kCsRxLeave(pThis);
6534 E1kLog(("%s e1kCanReceive: failed to update Rx context, returning VERR_NET_NO_BUFFER_SPACE\n", pThis->szPrf));
6535 return VERR_NET_NO_BUFFER_SPACE;
6536 }
6537
6538 if (RT_UNLIKELY(rxdc.rdlen == sizeof(E1KRXDESC)))
6539 {
6540 E1KRXDESC desc;
6541 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, rxdc.rdh), &desc, sizeof(desc));
6542 if (desc.status.fDD)
6543 rc = VERR_NET_NO_BUFFER_SPACE;
6544 }
6545 else if (e1kRxDIsCacheEmpty(pThis) && rxdc.rdh == rxdc.rdt)
6546 {
6547 /* Cache is empty, so is the RX ring. */
6548 rc = VERR_NET_NO_BUFFER_SPACE;
6549 }
6550 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6551 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6552 e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt, rxdc.rdlen, pThis->u16RxBSize, rc));
6553
6554 e1kCsRxLeave(pThis);
6555 return rc;
6556#endif /* E1K_WITH_RXD_CACHE */
6557}
6558
6559/**
6560 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6561 */
6562static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6563{
6564 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6565 PE1KSTATE pThis = pThisCC->pShared;
6566 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6567
6568 int rc = e1kCanReceive(pDevIns, pThis);
6569
6570 if (RT_SUCCESS(rc))
6571 return VINF_SUCCESS;
6572 if (RT_UNLIKELY(cMillies == 0))
6573 return VERR_NET_NO_BUFFER_SPACE;
6574
6575 rc = VERR_INTERRUPTED;
6576 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6577 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6578 VMSTATE enmVMState;
6579 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6580 || enmVMState == VMSTATE_RUNNING_LS))
6581 {
6582 int rc2 = e1kCanReceive(pDevIns, pThis);
6583 if (RT_SUCCESS(rc2))
6584 {
6585 rc = VINF_SUCCESS;
6586 break;
6587 }
6588 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6589 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6590 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6591 }
6592 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6593 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6594
6595 return rc;
6596}
6597
6598
6599/**
6600 * Matches the packet addresses against Receive Address table. Looks for
6601 * exact matches only.
6602 *
6603 * @returns true if address matches.
6604 * @param pThis Pointer to the state structure.
6605 * @param pvBuf The ethernet packet.
6606 * @param cb Number of bytes available in the packet.
6607 * @thread EMT
6608 */
6609static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6610{
6611 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6612 {
6613 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6614
6615 /* Valid address? */
6616 if (ra->ctl & RA_CTL_AV)
6617 {
6618 Assert((ra->ctl & RA_CTL_AS) < 2);
6619 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6620 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6621 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6622 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6623 /*
6624 * Address Select:
6625 * 00b = Destination address
6626 * 01b = Source address
6627 * 10b = Reserved
6628 * 11b = Reserved
6629 * Since ethernet header is (DA, SA, len) we can use address
6630 * select as index.
6631 */
6632 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6633 ra->addr, sizeof(ra->addr)) == 0)
6634 return true;
6635 }
6636 }
6637
6638 return false;
6639}
6640
6641/**
6642 * Matches the packet addresses against Multicast Table Array.
6643 *
6644 * @remarks This is imperfect match since it matches not exact address but
6645 * a subset of addresses.
6646 *
6647 * @returns true if address matches.
6648 * @param pThis Pointer to the state structure.
6649 * @param pvBuf The ethernet packet.
6650 * @param cb Number of bytes available in the packet.
6651 * @thread EMT
6652 */
6653static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6654{
6655 /* Get bits 32..47 of destination address */
6656 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6657
6658 unsigned offset = GET_BITS(RCTL, MO);
6659 /*
6660 * offset means:
6661 * 00b = bits 36..47
6662 * 01b = bits 35..46
6663 * 10b = bits 34..45
6664 * 11b = bits 32..43
6665 */
6666 if (offset < 3)
6667 u16Bit = u16Bit >> (4 - offset);
6668 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6669}
6670
6671/**
6672 * Determines if the packet is to be delivered to upper layer.
6673 *
6674 * The following filters supported:
6675 * - Exact Unicast/Multicast
6676 * - Promiscuous Unicast/Multicast
6677 * - Multicast
6678 * - VLAN
6679 *
6680 * @returns true if packet is intended for this node.
6681 * @param pThis Pointer to the state structure.
6682 * @param pvBuf The ethernet packet.
6683 * @param cb Number of bytes available in the packet.
6684 * @param pStatus Bit field to store status bits.
6685 * @thread EMT
6686 */
6687static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6688{
6689 Assert(cb > 14);
6690 /* Assume that we fail to pass exact filter. */
6691 pStatus->fPIF = false;
6692 pStatus->fVP = false;
6693 /* Discard oversized packets */
6694 if (cb > E1K_MAX_RX_PKT_SIZE)
6695 {
6696 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6697 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6698 E1K_INC_CNT32(ROC);
6699 return false;
6700 }
6701 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6702 {
6703 /* When long packet reception is disabled packets over 1522 are discarded */
6704 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6705 pThis->szPrf, cb));
6706 E1K_INC_CNT32(ROC);
6707 return false;
6708 }
6709
6710 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6711 /* Compare TPID with VLAN Ether Type */
6712 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6713 {
6714 pStatus->fVP = true;
6715 /* Is VLAN filtering enabled? */
6716 if (RCTL & RCTL_VFE)
6717 {
6718 /* It is 802.1q packet indeed, let's filter by VID */
6719 if (RCTL & RCTL_CFIEN)
6720 {
6721 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6722 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6723 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6724 !!(RCTL & RCTL_CFI)));
6725 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6726 {
6727 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6728 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6729 return false;
6730 }
6731 }
6732 else
6733 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6734 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6735 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6736 {
6737 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6738 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6739 return false;
6740 }
6741 }
6742 }
6743 /* Broadcast filtering */
6744 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6745 return true;
6746 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6747 if (e1kIsMulticast(pvBuf))
6748 {
6749 /* Is multicast promiscuous enabled? */
6750 if (RCTL & RCTL_MPE)
6751 return true;
6752 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6753 /* Try perfect matches first */
6754 if (e1kPerfectMatch(pThis, pvBuf))
6755 {
6756 pStatus->fPIF = true;
6757 return true;
6758 }
6759 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6760 if (e1kImperfectMatch(pThis, pvBuf))
6761 return true;
6762 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6763 }
6764 else {
6765 /* Is unicast promiscuous enabled? */
6766 if (RCTL & RCTL_UPE)
6767 return true;
6768 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6769 if (e1kPerfectMatch(pThis, pvBuf))
6770 {
6771 pStatus->fPIF = true;
6772 return true;
6773 }
6774 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6775 }
6776 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6777 return false;
6778}
6779
6780/**
6781 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6782 */
6783static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6784{
6785 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6786 PE1KSTATE pThis = pThisCC->pShared;
6787 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6788 int rc = VINF_SUCCESS;
6789
6790 /*
6791 * Drop packets if the VM is not running yet/anymore.
6792 */
6793 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6794 if ( enmVMState != VMSTATE_RUNNING
6795 && enmVMState != VMSTATE_RUNNING_LS)
6796 {
6797 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6798 return VINF_SUCCESS;
6799 }
6800
6801 /* Discard incoming packets in locked state */
6802 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6803 {
6804 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6805 return VINF_SUCCESS;
6806 }
6807
6808 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6809
6810 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6811 // return VERR_PERMISSION_DENIED;
6812
6813 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6814
6815 /* Update stats */
6816 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6817 {
6818 E1K_INC_CNT32(TPR);
6819 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6820 e1kCsLeave(pThis);
6821 }
6822 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6823 E1KRXDST status;
6824 RT_ZERO(status);
6825 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6826 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6827 if (fPassed)
6828 {
6829 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6830 }
6831 //e1kCsLeave(pThis);
6832 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6833
6834 return rc;
6835}
6836
6837
6838/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6839
6840/**
6841 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6842 */
6843static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6844{
6845 if (iLUN == 0)
6846 {
6847 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6848 *ppLed = &pThisCC->pShared->led;
6849 return VINF_SUCCESS;
6850 }
6851 return VERR_PDM_LUN_NOT_FOUND;
6852}
6853
6854
6855/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6856
6857/**
6858 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6859 */
6860static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6861{
6862 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6863 pThisCC->eeprom.getMac(pMac);
6864 return VINF_SUCCESS;
6865}
6866
6867/**
6868 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6869 */
6870static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6871{
6872 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6873 PE1KSTATE pThis = pThisCC->pShared;
6874 if (STATUS & STATUS_LU)
6875 return PDMNETWORKLINKSTATE_UP;
6876 return PDMNETWORKLINKSTATE_DOWN;
6877}
6878
6879/**
6880 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6881 */
6882static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6883{
6884 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6885 PE1KSTATE pThis = pThisCC->pShared;
6886 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6887
6888 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6889 switch (enmState)
6890 {
6891 case PDMNETWORKLINKSTATE_UP:
6892 pThis->fCableConnected = true;
6893 /* If link was down, bring it up after a while. */
6894 if (!(STATUS & STATUS_LU))
6895 e1kBringLinkUpDelayed(pDevIns, pThis);
6896 break;
6897 case PDMNETWORKLINKSTATE_DOWN:
6898 pThis->fCableConnected = false;
6899 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6900 * We might have to set the link state before the driver initializes us. */
6901 Phy::setLinkStatus(&pThis->phy, false);
6902 /* If link was up, bring it down. */
6903 if (STATUS & STATUS_LU)
6904 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6905 break;
6906 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6907 /*
6908 * There is not much sense in bringing down the link if it has not come up yet.
6909 * If it is up though, we bring it down temporarely, then bring it up again.
6910 */
6911 if (STATUS & STATUS_LU)
6912 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6913 break;
6914 default:
6915 ;
6916 }
6917 return VINF_SUCCESS;
6918}
6919
6920
6921/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6922
6923/**
6924 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6925 */
6926static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6927{
6928 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6929 Assert(&pThisCC->IBase == pInterface);
6930
6931 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6932 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6933 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6934 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6935 return NULL;
6936}
6937
6938
6939/* -=-=-=-=- Saved State -=-=-=-=- */
6940
6941/**
6942 * Saves the configuration.
6943 *
6944 * @param pThis The E1K state.
6945 * @param pSSM The handle to the saved state.
6946 */
6947static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
6948{
6949 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6950 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
6951}
6952
6953/**
6954 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
6955 */
6956static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
6957{
6958 RT_NOREF(uPass);
6959 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
6960 return VINF_SSM_DONT_CALL_AGAIN;
6961}
6962
6963/**
6964 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
6965 */
6966static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6967{
6968 RT_NOREF(pSSM);
6969 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6970
6971 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
6972 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6973 return rc;
6974 e1kCsLeave(pThis);
6975 return VINF_SUCCESS;
6976#if 0
6977 /* 1) Prevent all threads from modifying the state and memory */
6978 //pThis->fLocked = true;
6979 /* 2) Cancel all timers */
6980#ifdef E1K_TX_DELAY
6981 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
6982#endif /* E1K_TX_DELAY */
6983//#ifdef E1K_USE_TX_TIMERS
6984 if (pThis->fTidEnabled)
6985 {
6986 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
6987#ifndef E1K_NO_TAD
6988 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
6989#endif /* E1K_NO_TAD */
6990 }
6991//#endif /* E1K_USE_TX_TIMERS */
6992#ifdef E1K_USE_RX_TIMERS
6993 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
6994 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
6995#endif /* E1K_USE_RX_TIMERS */
6996 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
6997 /* 3) Did I forget anything? */
6998 E1kLog(("%s Locked\n", pThis->szPrf));
6999 return VINF_SUCCESS;
7000#endif
7001}
7002
7003/**
7004 * @callback_method_impl{FNSSMDEVSAVEEXEC}
7005 */
7006static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7007{
7008 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7009 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7010 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7011
7012 e1kSaveConfig(pHlp, pThis, pSSM);
7013 pThisCC->eeprom.save(pHlp, pSSM);
7014 e1kDumpState(pThis);
7015 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
7016 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
7017 Phy::saveState(pHlp, pSSM, &pThis->phy);
7018 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
7019 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
7020 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7021 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
7022 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
7023 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
7024 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
7025 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
7026 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
7027/** @todo State wrt to the TSE buffer is incomplete, so little point in
7028 * saving this actually. */
7029 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
7030 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
7031 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
7032 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7033 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7034 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
7035 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
7036#ifdef E1K_WITH_TXD_CACHE
7037# if 0
7038 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
7039 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
7040 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7041# else
7042 /*
7043 * There is no point in storing TX descriptor cache entries as we can simply
7044 * fetch them again. Moreover, normally the cache is always empty when we
7045 * save the state. Store zero entries for compatibility.
7046 */
7047 pHlp->pfnSSMPutU8(pSSM, 0);
7048# endif
7049#endif /* E1K_WITH_TXD_CACHE */
7050/** @todo GSO requires some more state here. */
7051 E1kLog(("%s State has been saved\n", pThis->szPrf));
7052 return VINF_SUCCESS;
7053}
7054
7055#if 0
7056/**
7057 * @callback_method_impl{FNSSMDEVSAVEDONE}
7058 */
7059static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7060{
7061 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7062
7063 /* If VM is being powered off unlocking will result in assertions in PGM */
7064 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
7065 pThis->fLocked = false;
7066 else
7067 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
7068 E1kLog(("%s Unlocked\n", pThis->szPrf));
7069 return VINF_SUCCESS;
7070}
7071#endif
7072
7073/**
7074 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
7075 */
7076static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7077{
7078 RT_NOREF(pSSM);
7079 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7080
7081 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
7082 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7083 return rc;
7084 e1kCsLeave(pThis);
7085 return VINF_SUCCESS;
7086}
7087
7088/**
7089 * @callback_method_impl{FNSSMDEVLOADEXEC}
7090 */
7091static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7092{
7093 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7094 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7095 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7096 int rc;
7097
7098 if ( uVersion != E1K_SAVEDSTATE_VERSION
7099#ifdef E1K_WITH_TXD_CACHE
7100 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
7101#endif /* E1K_WITH_TXD_CACHE */
7102 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
7103 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
7104 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7105
7106 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
7107 || uPass != SSM_PASS_FINAL)
7108 {
7109 /* config checks */
7110 RTMAC macConfigured;
7111 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
7112 AssertRCReturn(rc, rc);
7113 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
7114 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
7115 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
7116
7117 E1KCHIP eChip;
7118 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
7119 AssertRCReturn(rc, rc);
7120 if (eChip != pThis->eChip)
7121 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
7122 }
7123
7124 if (uPass == SSM_PASS_FINAL)
7125 {
7126 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
7127 {
7128 rc = pThisCC->eeprom.load(pHlp, pSSM);
7129 AssertRCReturn(rc, rc);
7130 }
7131 /* the state */
7132 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7133 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7134 /** @todo PHY could be made a separate device with its own versioning */
7135 Phy::loadState(pHlp, pSSM, &pThis->phy);
7136 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7137 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7138 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7139 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7140 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7141 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7142 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7143 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7144 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7145 AssertRCReturn(rc, rc);
7146 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7147 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7148 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7149 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7150 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7151 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7152 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7153 AssertRCReturn(rc, rc);
7154 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7155 {
7156 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7157 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7158 AssertRCReturn(rc, rc);
7159 }
7160 else
7161 {
7162 pThis->fVTag = false;
7163 pThis->u16VTagTCI = 0;
7164 }
7165#ifdef E1K_WITH_TXD_CACHE
7166 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7167 {
7168 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7169 AssertRCReturn(rc, rc);
7170 if (pThis->nTxDFetched)
7171 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7172 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7173 }
7174 else
7175 pThis->nTxDFetched = 0;
7176 /**
7177 * @todo Perhaps we should not store TXD cache as the entries can be
7178 * simply fetched again from guest's memory. Or can't they?
7179 */
7180#endif /* E1K_WITH_TXD_CACHE */
7181#ifdef E1K_WITH_RXD_CACHE
7182 /*
7183 * There is no point in storing the RX descriptor cache in the saved
7184 * state, we just need to make sure it is empty.
7185 */
7186 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7187#endif /* E1K_WITH_RXD_CACHE */
7188 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7189 AssertRCReturn(rc, rc);
7190
7191 /* derived state */
7192 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7193
7194 E1kLog(("%s State has been restored\n", pThis->szPrf));
7195 e1kDumpState(pThis);
7196 }
7197 return VINF_SUCCESS;
7198}
7199
7200/**
7201 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7202 */
7203static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7204{
7205 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7206 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7207 RT_NOREF(pSSM);
7208
7209 /* Update promiscuous mode */
7210 if (pThisCC->pDrvR3)
7211 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7212
7213 /*
7214 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7215 * passed to us. We go through all this stuff if the link was up and we
7216 * wasn't teleported.
7217 */
7218 if ( (STATUS & STATUS_LU)
7219 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7220 && pThis->cMsLinkUpDelay)
7221 {
7222 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7223 }
7224 return VINF_SUCCESS;
7225}
7226
7227
7228
7229/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7230
7231/**
7232 * @callback_method_impl{FNRTSTRFORMATTYPE}
7233 */
7234static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7235 void *pvArgOutput,
7236 const char *pszType,
7237 void const *pvValue,
7238 int cchWidth,
7239 int cchPrecision,
7240 unsigned fFlags,
7241 void *pvUser)
7242{
7243 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7244 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7245 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7246 if (!pDesc)
7247 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7248
7249 size_t cbPrintf = 0;
7250 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7251 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7252 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7253 pDesc->status.fPIF ? "PIF" : "pif",
7254 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7255 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7256 pDesc->status.fVP ? "VP" : "vp",
7257 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7258 pDesc->status.fEOP ? "EOP" : "eop",
7259 pDesc->status.fDD ? "DD" : "dd",
7260 pDesc->status.fRXE ? "RXE" : "rxe",
7261 pDesc->status.fIPE ? "IPE" : "ipe",
7262 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7263 pDesc->status.fCE ? "CE" : "ce",
7264 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7265 E1K_SPEC_VLAN(pDesc->status.u16Special),
7266 E1K_SPEC_PRI(pDesc->status.u16Special));
7267 return cbPrintf;
7268}
7269
7270/**
7271 * @callback_method_impl{FNRTSTRFORMATTYPE}
7272 */
7273static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7274 void *pvArgOutput,
7275 const char *pszType,
7276 void const *pvValue,
7277 int cchWidth,
7278 int cchPrecision,
7279 unsigned fFlags,
7280 void *pvUser)
7281{
7282 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7283 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7284 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7285 if (!pDesc)
7286 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7287
7288 size_t cbPrintf = 0;
7289 switch (e1kGetDescType(pDesc))
7290 {
7291 case E1K_DTYP_CONTEXT:
7292 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7293 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7294 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7295 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7296 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7297 pDesc->context.dw2.fIDE ? " IDE":"",
7298 pDesc->context.dw2.fRS ? " RS" :"",
7299 pDesc->context.dw2.fTSE ? " TSE":"",
7300 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7301 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7302 pDesc->context.dw2.u20PAYLEN,
7303 pDesc->context.dw3.u8HDRLEN,
7304 pDesc->context.dw3.u16MSS,
7305 pDesc->context.dw3.fDD?"DD":"");
7306 break;
7307 case E1K_DTYP_DATA:
7308 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7309 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7310 pDesc->data.u64BufAddr,
7311 pDesc->data.cmd.u20DTALEN,
7312 pDesc->data.cmd.fIDE ? " IDE" :"",
7313 pDesc->data.cmd.fVLE ? " VLE" :"",
7314 pDesc->data.cmd.fRPS ? " RPS" :"",
7315 pDesc->data.cmd.fRS ? " RS" :"",
7316 pDesc->data.cmd.fTSE ? " TSE" :"",
7317 pDesc->data.cmd.fIFCS? " IFCS":"",
7318 pDesc->data.cmd.fEOP ? " EOP" :"",
7319 pDesc->data.dw3.fDD ? " DD" :"",
7320 pDesc->data.dw3.fEC ? " EC" :"",
7321 pDesc->data.dw3.fLC ? " LC" :"",
7322 pDesc->data.dw3.fTXSM? " TXSM":"",
7323 pDesc->data.dw3.fIXSM? " IXSM":"",
7324 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7325 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7326 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7327 break;
7328 case E1K_DTYP_LEGACY:
7329 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7330 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7331 pDesc->data.u64BufAddr,
7332 pDesc->legacy.cmd.u16Length,
7333 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7334 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7335 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7336 pDesc->legacy.cmd.fRS ? " RS" :"",
7337 pDesc->legacy.cmd.fIC ? " IC" :"",
7338 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7339 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7340 pDesc->legacy.dw3.fDD ? " DD" :"",
7341 pDesc->legacy.dw3.fEC ? " EC" :"",
7342 pDesc->legacy.dw3.fLC ? " LC" :"",
7343 pDesc->legacy.cmd.u8CSO,
7344 pDesc->legacy.dw3.u8CSS,
7345 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7346 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7347 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7348 break;
7349 default:
7350 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7351 break;
7352 }
7353
7354 return cbPrintf;
7355}
7356
7357/** Initializes debug helpers (logging format types). */
7358static int e1kInitDebugHelpers(void)
7359{
7360 int rc = VINF_SUCCESS;
7361 static bool s_fHelpersRegistered = false;
7362 if (!s_fHelpersRegistered)
7363 {
7364 s_fHelpersRegistered = true;
7365 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7366 AssertRCReturn(rc, rc);
7367 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7368 AssertRCReturn(rc, rc);
7369 }
7370 return rc;
7371}
7372
7373/**
7374 * Status info callback.
7375 *
7376 * @param pDevIns The device instance.
7377 * @param pHlp The output helpers.
7378 * @param pszArgs The arguments.
7379 */
7380static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7381{
7382 RT_NOREF(pszArgs);
7383 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7384 unsigned i;
7385 // bool fRcvRing = false;
7386 // bool fXmtRing = false;
7387
7388 /*
7389 * Parse args.
7390 if (pszArgs)
7391 {
7392 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7393 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7394 }
7395 */
7396
7397 /*
7398 * Show info.
7399 */
7400 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7401 pDevIns->iInstance,
7402 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7403 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7404 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7405 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7406
7407 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7408
7409 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7410 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7411
7412 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7413 {
7414 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7415 if (ra->ctl & RA_CTL_AV)
7416 {
7417 const char *pcszTmp;
7418 switch (ra->ctl & RA_CTL_AS)
7419 {
7420 case 0: pcszTmp = "DST"; break;
7421 case 1: pcszTmp = "SRC"; break;
7422 default: pcszTmp = "reserved";
7423 }
7424 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7425 }
7426 }
7427 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7428 uint32_t rdh = RDH;
7429 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7430 for (i = 0; i < cDescs; ++i)
7431 {
7432 E1KRXDESC desc;
7433 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7434 &desc, sizeof(desc));
7435 if (i == rdh)
7436 pHlp->pfnPrintf(pHlp, ">>> ");
7437 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7438 }
7439#ifdef E1K_WITH_RXD_CACHE
7440 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7441 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7442 if (rdh > pThis->iRxDCurrent)
7443 rdh -= pThis->iRxDCurrent;
7444 else
7445 rdh = cDescs + rdh - pThis->iRxDCurrent;
7446 for (i = 0; i < pThis->nRxDFetched; ++i)
7447 {
7448 if (i == pThis->iRxDCurrent)
7449 pHlp->pfnPrintf(pHlp, ">>> ");
7450 if (cDescs)
7451 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7452 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7453 &pThis->aRxDescriptors[i]);
7454 else
7455 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1krxd]\n",
7456 &pThis->aRxDescriptors[i]);
7457 }
7458#endif /* E1K_WITH_RXD_CACHE */
7459
7460 cDescs = TDLEN / sizeof(E1KTXDESC);
7461 uint32_t tdh = TDH;
7462 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7463 for (i = 0; i < cDescs; ++i)
7464 {
7465 E1KTXDESC desc;
7466 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7467 &desc, sizeof(desc));
7468 if (i == tdh)
7469 pHlp->pfnPrintf(pHlp, ">>> ");
7470 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7471 }
7472#ifdef E1K_WITH_TXD_CACHE
7473 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7474 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7475 if (tdh > pThis->iTxDCurrent)
7476 tdh -= pThis->iTxDCurrent;
7477 else
7478 tdh = cDescs + tdh - pThis->iTxDCurrent;
7479 for (i = 0; i < pThis->nTxDFetched; ++i)
7480 {
7481 if (i == pThis->iTxDCurrent)
7482 pHlp->pfnPrintf(pHlp, ">>> ");
7483 if (cDescs)
7484 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7485 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7486 &pThis->aTxDescriptors[i]);
7487 else
7488 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1ktxd]\n",
7489 &pThis->aTxDescriptors[i]);
7490 }
7491#endif /* E1K_WITH_TXD_CACHE */
7492
7493
7494#ifdef E1K_INT_STATS
7495 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7496 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7497 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7498 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7499 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7500 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7501 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7502 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7503 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7504 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7505 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7506 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7507 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7508 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7509 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7510 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7511 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7512 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7513 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7514 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7515 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7516 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7517 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7518 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7519 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7520 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7521 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7522 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7523 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7524 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7525 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7526 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7527 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7528 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7529 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7530 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7531 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7532 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7533#endif /* E1K_INT_STATS */
7534
7535 e1kCsLeave(pThis);
7536}
7537
7538
7539
7540/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7541
7542/**
7543 * Detach notification.
7544 *
7545 * One port on the network card has been disconnected from the network.
7546 *
7547 * @param pDevIns The device instance.
7548 * @param iLUN The logical unit which is being detached.
7549 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7550 */
7551static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7552{
7553 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7554 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7555 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7556 RT_NOREF(fFlags);
7557
7558 AssertLogRelReturnVoid(iLUN == 0);
7559
7560 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7561
7562 /** @todo r=pritesh still need to check if i missed
7563 * to clean something in this function
7564 */
7565
7566 /*
7567 * Zero some important members.
7568 */
7569 pThisCC->pDrvBase = NULL;
7570 pThisCC->pDrvR3 = NULL;
7571#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7572 pThisR0->pDrvR0 = NIL_RTR0PTR;
7573 pThisRC->pDrvRC = NIL_RTRCPTR;
7574#endif
7575
7576 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7577}
7578
7579/**
7580 * Attach the Network attachment.
7581 *
7582 * One port on the network card has been connected to a network.
7583 *
7584 * @returns VBox status code.
7585 * @param pDevIns The device instance.
7586 * @param iLUN The logical unit which is being attached.
7587 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7588 *
7589 * @remarks This code path is not used during construction.
7590 */
7591static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7592{
7593 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7594 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7595 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7596 RT_NOREF(fFlags);
7597
7598 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7599
7600 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7601
7602 /*
7603 * Attach the driver.
7604 */
7605 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7606 if (RT_SUCCESS(rc))
7607 {
7608 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7609 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7610 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7611 if (RT_SUCCESS(rc))
7612 {
7613#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7614 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7615 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7616#endif
7617 }
7618 }
7619 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7620 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7621 {
7622 /* This should never happen because this function is not called
7623 * if there is no driver to attach! */
7624 Log(("%s No attached driver!\n", pThis->szPrf));
7625 }
7626
7627 /*
7628 * Temporary set the link down if it was up so that the guest will know
7629 * that we have change the configuration of the network card
7630 */
7631 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7632 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7633
7634 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7635 return rc;
7636}
7637
7638/**
7639 * @copydoc FNPDMDEVPOWEROFF
7640 */
7641static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7642{
7643 /* Poke thread waiting for buffer space. */
7644 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7645}
7646
7647/**
7648 * @copydoc FNPDMDEVRESET
7649 */
7650static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7651{
7652 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7653 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7654#ifdef E1K_TX_DELAY
7655 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7656#endif /* E1K_TX_DELAY */
7657 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7658 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7659 e1kXmitFreeBuf(pThis, pThisCC);
7660 pThis->u16TxPktLen = 0;
7661 pThis->fIPcsum = false;
7662 pThis->fTCPcsum = false;
7663 pThis->fIntMaskUsed = false;
7664 pThis->fDelayInts = false;
7665 pThis->fLocked = false;
7666 pThis->u64AckedAt = 0;
7667 e1kR3HardReset(pDevIns, pThis, pThisCC);
7668}
7669
7670/**
7671 * @copydoc FNPDMDEVSUSPEND
7672 */
7673static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7674{
7675 /* Poke thread waiting for buffer space. */
7676 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7677}
7678
7679/**
7680 * Device relocation callback.
7681 *
7682 * When this callback is called the device instance data, and if the
7683 * device have a GC component, is being relocated, or/and the selectors
7684 * have been changed. The device must use the chance to perform the
7685 * necessary pointer relocations and data updates.
7686 *
7687 * Before the GC code is executed the first time, this function will be
7688 * called with a 0 delta so GC pointer calculations can be one in one place.
7689 *
7690 * @param pDevIns Pointer to the device instance.
7691 * @param offDelta The relocation delta relative to the old location.
7692 *
7693 * @remark A relocation CANNOT fail.
7694 */
7695static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7696{
7697 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7698 if (pThisRC)
7699 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7700 RT_NOREF(offDelta);
7701}
7702
7703/**
7704 * Destruct a device instance.
7705 *
7706 * We need to free non-VM resources only.
7707 *
7708 * @returns VBox status code.
7709 * @param pDevIns The device instance data.
7710 * @thread EMT
7711 */
7712static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7713{
7714 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7715 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7716
7717 e1kDumpState(pThis);
7718 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7719 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7720 {
7721 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7722 {
7723 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7724 RTThreadYield();
7725 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7726 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7727 }
7728#ifdef E1K_WITH_TX_CS
7729 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7730#endif /* E1K_WITH_TX_CS */
7731 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7732 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7733 }
7734 return VINF_SUCCESS;
7735}
7736
7737
7738/**
7739 * Set PCI configuration space registers.
7740 *
7741 * @param pci Reference to PCI device structure.
7742 * @thread EMT
7743 */
7744static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7745{
7746 Assert(eChip < RT_ELEMENTS(g_aChips));
7747 /* Configure PCI Device, assume 32-bit mode ******************************/
7748 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7749 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7750 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7751 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7752
7753 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7754 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7755 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7756 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7757 /* Stepping A2 */
7758 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7759 /* Ethernet adapter */
7760 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7761 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7762 /* normal single function Ethernet controller */
7763 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7764 /* Memory Register Base Address */
7765 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7766 /* Memory Flash Base Address */
7767 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7768 /* IO Register Base Address */
7769 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7770 /* Expansion ROM Base Address */
7771 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7772 /* Capabilities Pointer */
7773 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7774 /* Interrupt Pin: INTA# */
7775 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7776 /* Max_Lat/Min_Gnt: very high priority and time slice */
7777 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7778 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7779
7780 /* PCI Power Management Registers ****************************************/
7781 /* Capability ID: PCI Power Management Registers */
7782 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7783 /* Next Item Pointer: PCI-X */
7784 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7785 /* Power Management Capabilities: PM disabled, DSI */
7786 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7787 0x0002 | VBOX_PCI_PM_CAP_DSI);
7788 /* Power Management Control / Status Register: PM disabled */
7789 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7790 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7791 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7792 /* Data Register: PM disabled, always 0 */
7793 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7794
7795 /* PCI-X Configuration Registers *****************************************/
7796 /* Capability ID: PCI-X Configuration Registers */
7797 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7798#ifdef E1K_WITH_MSI
7799 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7800#else
7801 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7802 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7803#endif
7804 /* PCI-X Command: Enable Relaxed Ordering */
7805 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7806 /* PCI-X Status: 32-bit, 66MHz*/
7807 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7808 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7809}
7810
7811/**
7812 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7813 */
7814static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7815{
7816 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7817 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7818 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7819 int rc;
7820
7821 /*
7822 * Initialize the instance data (state).
7823 * Note! Caller has initialized it to ZERO already.
7824 */
7825 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7826 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7827 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7828 pThis->u16TxPktLen = 0;
7829 pThis->fIPcsum = false;
7830 pThis->fTCPcsum = false;
7831 pThis->fIntMaskUsed = false;
7832 pThis->fDelayInts = false;
7833 pThis->fLocked = false;
7834 pThis->u64AckedAt = 0;
7835 pThis->led.u32Magic = PDMLED_MAGIC;
7836 pThis->u32PktNo = 1;
7837
7838 pThisCC->pDevInsR3 = pDevIns;
7839 pThisCC->pShared = pThis;
7840
7841 /* Interfaces */
7842 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7843
7844 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7845 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7846 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7847
7848 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7849
7850 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7851 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7852 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7853
7854 /*
7855 * Internal validations.
7856 */
7857 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7858 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7859 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7860 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7861 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7862 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7863 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7864 VERR_INTERNAL_ERROR_4);
7865
7866 /*
7867 * Validate configuration.
7868 */
7869 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7870 "MAC|"
7871 "CableConnected|"
7872 "AdapterType|"
7873 "LineSpeed|"
7874 "ItrEnabled|"
7875 "ItrRxEnabled|"
7876 "EthernetCRC|"
7877 "GSOEnabled|"
7878 "LinkUpDelay|"
7879 "StatNo",
7880 "");
7881
7882 /** @todo LineSpeed unused! */
7883
7884 /*
7885 * Get config params
7886 */
7887 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7888 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7889 if (RT_FAILURE(rc))
7890 return PDMDEV_SET_ERROR(pDevIns, rc,
7891 N_("Configuration error: Failed to get MAC address"));
7892 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7893 if (RT_FAILURE(rc))
7894 return PDMDEV_SET_ERROR(pDevIns, rc,
7895 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7896 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7897 if (RT_FAILURE(rc))
7898 return PDMDEV_SET_ERROR(pDevIns, rc,
7899 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7900 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7901
7902 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7903 if (RT_FAILURE(rc))
7904 return PDMDEV_SET_ERROR(pDevIns, rc,
7905 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7906
7907 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7908 if (RT_FAILURE(rc))
7909 return PDMDEV_SET_ERROR(pDevIns, rc,
7910 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7911
7912 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7913 if (RT_FAILURE(rc))
7914 return PDMDEV_SET_ERROR(pDevIns, rc,
7915 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7916
7917 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7918 if (RT_FAILURE(rc))
7919 return PDMDEV_SET_ERROR(pDevIns, rc,
7920 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7921
7922 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7923 if (RT_FAILURE(rc))
7924 return PDMDEV_SET_ERROR(pDevIns, rc,
7925 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7926
7927 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7928 if (RT_FAILURE(rc))
7929 return PDMDEV_SET_ERROR(pDevIns, rc,
7930 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7931 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7932 if (pThis->cMsLinkUpDelay > 5000)
7933 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7934 else if (pThis->cMsLinkUpDelay == 0)
7935 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7936
7937 uint32_t uStatNo = (uint32_t)iInstance;
7938 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7939 if (RT_FAILURE(rc))
7940 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7941
7942 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7943 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7944 pThis->fEthernetCRC ? "on" : "off",
7945 pThis->fGSOEnabled ? "enabled" : "disabled",
7946 pThis->fItrEnabled ? "enabled" : "disabled",
7947 pThis->fItrRxEnabled ? "enabled" : "disabled",
7948 pThis->fTidEnabled ? "enabled" : "disabled",
7949 pDevIns->fR0Enabled ? "enabled" : "disabled",
7950 pDevIns->fRCEnabled ? "enabled" : "disabled"));
7951
7952 /*
7953 * Initialize sub-components and register everything with the VMM.
7954 */
7955
7956 /* Initialize the EEPROM. */
7957 pThisCC->eeprom.init(pThis->macConfigured);
7958
7959 /* Initialize internal PHY. */
7960 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
7961
7962 /* Initialize critical sections. We do our own locking. */
7963 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7964 AssertRCReturn(rc, rc);
7965
7966 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
7967 AssertRCReturn(rc, rc);
7968 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
7969 AssertRCReturn(rc, rc);
7970#ifdef E1K_WITH_TX_CS
7971 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
7972 AssertRCReturn(rc, rc);
7973#endif
7974
7975 /* Saved state registration. */
7976 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
7977 NULL, e1kLiveExec, NULL,
7978 e1kSavePrep, e1kSaveExec, NULL,
7979 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
7980 AssertRCReturn(rc, rc);
7981
7982 /* Set PCI config registers and register ourselves with the PCI bus. */
7983 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
7984 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
7985 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
7986 AssertRCReturn(rc, rc);
7987
7988#ifdef E1K_WITH_MSI
7989 PDMMSIREG MsiReg;
7990 RT_ZERO(MsiReg);
7991 MsiReg.cMsiVectors = 1;
7992 MsiReg.iMsiCapOffset = 0x80;
7993 MsiReg.iMsiNextOffset = 0x0;
7994 MsiReg.fMsi64bit = false;
7995 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7996 AssertRCReturn(rc, rc);
7997#endif
7998
7999 /*
8000 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
8001 * From the spec (regarding flags):
8002 * For registers that should be accessed as 32-bit double words,
8003 * partial writes (less than a 32-bit double word) is ignored.
8004 * Partial reads return all 32 bits of data regardless of the
8005 * byte enables.
8006 */
8007 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
8008 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
8009 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
8010 AssertRCReturn(rc, rc);
8011 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
8012 AssertRCReturn(rc, rc);
8013
8014 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
8015 static IOMIOPORTDESC const s_aExtDescs[] =
8016 {
8017 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8018 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8019 { NULL, NULL, NULL, NULL }
8020 };
8021 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
8022 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
8023 AssertRCReturn(rc, rc);
8024 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
8025 AssertRCReturn(rc, rc);
8026
8027 /* Create transmit queue */
8028 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
8029 AssertRCReturn(rc, rc);
8030
8031#ifdef E1K_TX_DELAY
8032 /* Create Transmit Delay Timer */
8033 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis,
8034 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Delay", &pThis->hTXDTimer);
8035 AssertRCReturn(rc, rc);
8036 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
8037 AssertRCReturn(rc, rc);
8038#endif /* E1K_TX_DELAY */
8039
8040//#ifdef E1K_USE_TX_TIMERS
8041 if (pThis->fTidEnabled)
8042 {
8043 /* Create Transmit Interrupt Delay Timer */
8044 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis,
8045 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit IRQ Delay", &pThis->hTIDTimer);
8046 AssertRCReturn(rc, rc);
8047
8048# ifndef E1K_NO_TAD
8049 /* Create Transmit Absolute Delay Timer */
8050 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis,
8051 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Abs Delay", &pThis->hTADTimer);
8052 AssertRCReturn(rc, rc);
8053# endif /* E1K_NO_TAD */
8054 }
8055//#endif /* E1K_USE_TX_TIMERS */
8056
8057#ifdef E1K_USE_RX_TIMERS
8058 /* Create Receive Interrupt Delay Timer */
8059 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis,
8060 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv IRQ Delay", &pThis->hRIDTimer);
8061 AssertRCReturn(rc, rc);
8062
8063 /* Create Receive Absolute Delay Timer */
8064 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis,
8065 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv Abs Delay", &pThis->hRADTimer);
8066 AssertRCReturn(rc, rc);
8067#endif /* E1K_USE_RX_TIMERS */
8068
8069 /* Create Late Interrupt Timer */
8070 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis,
8071 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Late IRQ", &pThis->hIntTimer);
8072 AssertRCReturn(rc, rc);
8073
8074 /* Create Link Up Timer */
8075 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis,
8076 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Link Up", &pThis->hLUTimer);
8077 AssertRCReturn(rc, rc);
8078
8079 /* Register the info item */
8080 char szTmp[20];
8081 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
8082 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
8083
8084 /* Status driver */
8085 PPDMIBASE pBase;
8086 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
8087 if (RT_FAILURE(rc))
8088 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
8089 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8090
8091 /* Network driver */
8092 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
8093 if (RT_SUCCESS(rc))
8094 {
8095 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
8096 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
8097
8098#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
8099 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
8100 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
8101#endif
8102 }
8103 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
8104 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
8105 {
8106 /* No error! */
8107 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
8108 }
8109 else
8110 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
8111
8112 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
8113 AssertRCReturn(rc, rc);
8114
8115 rc = e1kInitDebugHelpers();
8116 AssertRCReturn(rc, rc);
8117
8118 e1kR3HardReset(pDevIns, pThis, pThisCC);
8119
8120 /*
8121 * Register statistics.
8122 * The /Public/ bits are official and used by session info in the GUI.
8123 */
8124 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8125 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
8126 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8127 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
8128 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8129 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
8130
8131 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
8132 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
8133
8134#if defined(VBOX_WITH_STATISTICS)
8135 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
8136 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
8137 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
8138 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
8139 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8140 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8141 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8142 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8143 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8144 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8145 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8146 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8147 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8148 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8149 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8150 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8151 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8152 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8153 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8154 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8155 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8156 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8157 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8158 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8159 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8160
8161 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8162 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8163 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8164 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8165 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8166 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8167 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8168 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8169 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8170 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8171 {
8172 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8173 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8174 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8175 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8176 }
8177#endif /* VBOX_WITH_STATISTICS */
8178
8179#ifdef E1K_INT_STATS
8180 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8181 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8182 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8183 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8184 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8185 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8186 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8187 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8188 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8189 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8190 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8191 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8192 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8193 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8194 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8195 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8196 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8197 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8198 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8199 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8200 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8201 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8202 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8203 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8204 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8205 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8206 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8207 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8208 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8209 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8210 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8211 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8212 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8213 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8214 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8215 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8216 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8217 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8218 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8219 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8220 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8221#endif /* E1K_INT_STATS */
8222
8223 return VINF_SUCCESS;
8224}
8225
8226#else /* !IN_RING3 */
8227
8228/**
8229 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8230 */
8231static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8232{
8233 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8234 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8235 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8236
8237 /* Initialize context specific state data: */
8238 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8239 /** @todo @bugref{9218} ring-0 driver stuff */
8240 pThisCC->CTX_SUFF(pDrv) = NULL;
8241 pThisCC->CTX_SUFF(pTxSg) = NULL;
8242
8243 /* Configure critical sections the same way: */
8244 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8245 AssertRCReturn(rc, rc);
8246
8247 /* Set up MMIO and I/O port callbacks for this context: */
8248 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8249 AssertRCReturn(rc, rc);
8250
8251 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8252 AssertRCReturn(rc, rc);
8253
8254 return VINF_SUCCESS;
8255}
8256
8257#endif /* !IN_RING3 */
8258
8259/**
8260 * The device registration structure.
8261 */
8262const PDMDEVREG g_DeviceE1000 =
8263{
8264 /* .u32version = */ PDM_DEVREG_VERSION,
8265 /* .uReserved0 = */ 0,
8266 /* .szName = */ "e1000",
8267 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8268 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8269 /* .cMaxInstances = */ ~0U,
8270 /* .uSharedVersion = */ 42,
8271 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8272 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8273 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8274 /* .cMaxPciDevices = */ 1,
8275 /* .cMaxMsixVectors = */ 0,
8276 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8277#if defined(IN_RING3)
8278 /* .pszRCMod = */ "VBoxDDRC.rc",
8279 /* .pszR0Mod = */ "VBoxDDR0.r0",
8280 /* .pfnConstruct = */ e1kR3Construct,
8281 /* .pfnDestruct = */ e1kR3Destruct,
8282 /* .pfnRelocate = */ e1kR3Relocate,
8283 /* .pfnMemSetup = */ NULL,
8284 /* .pfnPowerOn = */ NULL,
8285 /* .pfnReset = */ e1kR3Reset,
8286 /* .pfnSuspend = */ e1kR3Suspend,
8287 /* .pfnResume = */ NULL,
8288 /* .pfnAttach = */ e1kR3Attach,
8289 /* .pfnDeatch = */ e1kR3Detach,
8290 /* .pfnQueryInterface = */ NULL,
8291 /* .pfnInitComplete = */ NULL,
8292 /* .pfnPowerOff = */ e1kR3PowerOff,
8293 /* .pfnSoftReset = */ NULL,
8294 /* .pfnReserved0 = */ NULL,
8295 /* .pfnReserved1 = */ NULL,
8296 /* .pfnReserved2 = */ NULL,
8297 /* .pfnReserved3 = */ NULL,
8298 /* .pfnReserved4 = */ NULL,
8299 /* .pfnReserved5 = */ NULL,
8300 /* .pfnReserved6 = */ NULL,
8301 /* .pfnReserved7 = */ NULL,
8302#elif defined(IN_RING0)
8303 /* .pfnEarlyConstruct = */ NULL,
8304 /* .pfnConstruct = */ e1kRZConstruct,
8305 /* .pfnDestruct = */ NULL,
8306 /* .pfnFinalDestruct = */ NULL,
8307 /* .pfnRequest = */ NULL,
8308 /* .pfnReserved0 = */ NULL,
8309 /* .pfnReserved1 = */ NULL,
8310 /* .pfnReserved2 = */ NULL,
8311 /* .pfnReserved3 = */ NULL,
8312 /* .pfnReserved4 = */ NULL,
8313 /* .pfnReserved5 = */ NULL,
8314 /* .pfnReserved6 = */ NULL,
8315 /* .pfnReserved7 = */ NULL,
8316#elif defined(IN_RC)
8317 /* .pfnConstruct = */ e1kRZConstruct,
8318 /* .pfnReserved0 = */ NULL,
8319 /* .pfnReserved1 = */ NULL,
8320 /* .pfnReserved2 = */ NULL,
8321 /* .pfnReserved3 = */ NULL,
8322 /* .pfnReserved4 = */ NULL,
8323 /* .pfnReserved5 = */ NULL,
8324 /* .pfnReserved6 = */ NULL,
8325 /* .pfnReserved7 = */ NULL,
8326#else
8327# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8328#endif
8329 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8330};
8331
8332#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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