VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 88490

Last change on this file since 88490 was 88490, checked in by vboxsync, 4 years ago

Network: Do not bring up links for "not attached" adapters.
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1/* $Id: DevE1000.cpp 88490 2021-04-13 10:55:07Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2020 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280/** Gets the specfieid bits from the register. */
281#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
282#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
284#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
285#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286
287#define CTRL_SLU UINT32_C(0x00000040)
288#define CTRL_MDIO UINT32_C(0x00100000)
289#define CTRL_MDC UINT32_C(0x00200000)
290#define CTRL_MDIO_DIR UINT32_C(0x01000000)
291#define CTRL_MDC_DIR UINT32_C(0x02000000)
292#define CTRL_RESET UINT32_C(0x04000000)
293#define CTRL_VME UINT32_C(0x40000000)
294
295#define STATUS_LU UINT32_C(0x00000002)
296#define STATUS_TXOFF UINT32_C(0x00000010)
297
298#define EECD_EE_WIRES UINT32_C(0x0F)
299#define EECD_EE_REQ UINT32_C(0x40)
300#define EECD_EE_GNT UINT32_C(0x80)
301
302#define EERD_START UINT32_C(0x00000001)
303#define EERD_DONE UINT32_C(0x00000010)
304#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
305#define EERD_DATA_SHIFT 16
306#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
307#define EERD_ADDR_SHIFT 8
308
309#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
310#define MDIC_DATA_SHIFT 0
311#define MDIC_REG_MASK UINT32_C(0x001F0000)
312#define MDIC_REG_SHIFT 16
313#define MDIC_PHY_MASK UINT32_C(0x03E00000)
314#define MDIC_PHY_SHIFT 21
315#define MDIC_OP_WRITE UINT32_C(0x04000000)
316#define MDIC_OP_READ UINT32_C(0x08000000)
317#define MDIC_READY UINT32_C(0x10000000)
318#define MDIC_INT_EN UINT32_C(0x20000000)
319#define MDIC_ERROR UINT32_C(0x40000000)
320
321#define TCTL_EN UINT32_C(0x00000002)
322#define TCTL_PSP UINT32_C(0x00000008)
323
324#define RCTL_EN UINT32_C(0x00000002)
325#define RCTL_UPE UINT32_C(0x00000008)
326#define RCTL_MPE UINT32_C(0x00000010)
327#define RCTL_LPE UINT32_C(0x00000020)
328#define RCTL_LBM_MASK UINT32_C(0x000000C0)
329#define RCTL_LBM_SHIFT 6
330#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
331#define RCTL_RDMTS_SHIFT 8
332#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
333#define RCTL_MO_MASK UINT32_C(0x00003000)
334#define RCTL_MO_SHIFT 12
335#define RCTL_BAM UINT32_C(0x00008000)
336#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
337#define RCTL_BSIZE_SHIFT 16
338#define RCTL_VFE UINT32_C(0x00040000)
339#define RCTL_CFIEN UINT32_C(0x00080000)
340#define RCTL_CFI UINT32_C(0x00100000)
341#define RCTL_BSEX UINT32_C(0x02000000)
342#define RCTL_SECRC UINT32_C(0x04000000)
343
344#define ICR_TXDW UINT32_C(0x00000001)
345#define ICR_TXQE UINT32_C(0x00000002)
346#define ICR_LSC UINT32_C(0x00000004)
347#define ICR_RXDMT0 UINT32_C(0x00000010)
348#define ICR_RXT0 UINT32_C(0x00000080)
349#define ICR_TXD_LOW UINT32_C(0x00008000)
350#define RDTR_FPD UINT32_C(0x80000000)
351
352#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
353typedef struct
354{
355 unsigned rxa : 7;
356 unsigned rxa_r : 9;
357 unsigned txa : 16;
358} PBAST;
359AssertCompileSize(PBAST, 4);
360
361#define TXDCTL_WTHRESH_MASK 0x003F0000
362#define TXDCTL_WTHRESH_SHIFT 16
363#define TXDCTL_LWTHRESH_MASK 0xFE000000
364#define TXDCTL_LWTHRESH_SHIFT 25
365
366#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
367#define RXCSUM_PCSS_SHIFT 0
368
369/** @name Register access macros
370 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
371 * @{ */
372#define CTRL pThis->auRegs[CTRL_IDX]
373#define STATUS pThis->auRegs[STATUS_IDX]
374#define EECD pThis->auRegs[EECD_IDX]
375#define EERD pThis->auRegs[EERD_IDX]
376#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
377#define FLA pThis->auRegs[FLA_IDX]
378#define MDIC pThis->auRegs[MDIC_IDX]
379#define FCAL pThis->auRegs[FCAL_IDX]
380#define FCAH pThis->auRegs[FCAH_IDX]
381#define FCT pThis->auRegs[FCT_IDX]
382#define VET pThis->auRegs[VET_IDX]
383#define ICR pThis->auRegs[ICR_IDX]
384#define ITR pThis->auRegs[ITR_IDX]
385#define ICS pThis->auRegs[ICS_IDX]
386#define IMS pThis->auRegs[IMS_IDX]
387#define IMC pThis->auRegs[IMC_IDX]
388#define RCTL pThis->auRegs[RCTL_IDX]
389#define FCTTV pThis->auRegs[FCTTV_IDX]
390#define TXCW pThis->auRegs[TXCW_IDX]
391#define RXCW pThis->auRegs[RXCW_IDX]
392#define TCTL pThis->auRegs[TCTL_IDX]
393#define TIPG pThis->auRegs[TIPG_IDX]
394#define AIFS pThis->auRegs[AIFS_IDX]
395#define LEDCTL pThis->auRegs[LEDCTL_IDX]
396#define PBA pThis->auRegs[PBA_IDX]
397#define FCRTL pThis->auRegs[FCRTL_IDX]
398#define FCRTH pThis->auRegs[FCRTH_IDX]
399#define RDFH pThis->auRegs[RDFH_IDX]
400#define RDFT pThis->auRegs[RDFT_IDX]
401#define RDFHS pThis->auRegs[RDFHS_IDX]
402#define RDFTS pThis->auRegs[RDFTS_IDX]
403#define RDFPC pThis->auRegs[RDFPC_IDX]
404#define RDBAL pThis->auRegs[RDBAL_IDX]
405#define RDBAH pThis->auRegs[RDBAH_IDX]
406#define RDLEN pThis->auRegs[RDLEN_IDX]
407#define RDH pThis->auRegs[RDH_IDX]
408#define RDT pThis->auRegs[RDT_IDX]
409#define RDTR pThis->auRegs[RDTR_IDX]
410#define RXDCTL pThis->auRegs[RXDCTL_IDX]
411#define RADV pThis->auRegs[RADV_IDX]
412#define RSRPD pThis->auRegs[RSRPD_IDX]
413#define TXDMAC pThis->auRegs[TXDMAC_IDX]
414#define TDFH pThis->auRegs[TDFH_IDX]
415#define TDFT pThis->auRegs[TDFT_IDX]
416#define TDFHS pThis->auRegs[TDFHS_IDX]
417#define TDFTS pThis->auRegs[TDFTS_IDX]
418#define TDFPC pThis->auRegs[TDFPC_IDX]
419#define TDBAL pThis->auRegs[TDBAL_IDX]
420#define TDBAH pThis->auRegs[TDBAH_IDX]
421#define TDLEN pThis->auRegs[TDLEN_IDX]
422#define TDH pThis->auRegs[TDH_IDX]
423#define TDT pThis->auRegs[TDT_IDX]
424#define TIDV pThis->auRegs[TIDV_IDX]
425#define TXDCTL pThis->auRegs[TXDCTL_IDX]
426#define TADV pThis->auRegs[TADV_IDX]
427#define TSPMT pThis->auRegs[TSPMT_IDX]
428#define CRCERRS pThis->auRegs[CRCERRS_IDX]
429#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
430#define SYMERRS pThis->auRegs[SYMERRS_IDX]
431#define RXERRC pThis->auRegs[RXERRC_IDX]
432#define MPC pThis->auRegs[MPC_IDX]
433#define SCC pThis->auRegs[SCC_IDX]
434#define ECOL pThis->auRegs[ECOL_IDX]
435#define MCC pThis->auRegs[MCC_IDX]
436#define LATECOL pThis->auRegs[LATECOL_IDX]
437#define COLC pThis->auRegs[COLC_IDX]
438#define DC pThis->auRegs[DC_IDX]
439#define TNCRS pThis->auRegs[TNCRS_IDX]
440/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
441#define CEXTERR pThis->auRegs[CEXTERR_IDX]
442#define RLEC pThis->auRegs[RLEC_IDX]
443#define XONRXC pThis->auRegs[XONRXC_IDX]
444#define XONTXC pThis->auRegs[XONTXC_IDX]
445#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
446#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
447#define FCRUC pThis->auRegs[FCRUC_IDX]
448#define PRC64 pThis->auRegs[PRC64_IDX]
449#define PRC127 pThis->auRegs[PRC127_IDX]
450#define PRC255 pThis->auRegs[PRC255_IDX]
451#define PRC511 pThis->auRegs[PRC511_IDX]
452#define PRC1023 pThis->auRegs[PRC1023_IDX]
453#define PRC1522 pThis->auRegs[PRC1522_IDX]
454#define GPRC pThis->auRegs[GPRC_IDX]
455#define BPRC pThis->auRegs[BPRC_IDX]
456#define MPRC pThis->auRegs[MPRC_IDX]
457#define GPTC pThis->auRegs[GPTC_IDX]
458#define GORCL pThis->auRegs[GORCL_IDX]
459#define GORCH pThis->auRegs[GORCH_IDX]
460#define GOTCL pThis->auRegs[GOTCL_IDX]
461#define GOTCH pThis->auRegs[GOTCH_IDX]
462#define RNBC pThis->auRegs[RNBC_IDX]
463#define RUC pThis->auRegs[RUC_IDX]
464#define RFC pThis->auRegs[RFC_IDX]
465#define ROC pThis->auRegs[ROC_IDX]
466#define RJC pThis->auRegs[RJC_IDX]
467#define MGTPRC pThis->auRegs[MGTPRC_IDX]
468#define MGTPDC pThis->auRegs[MGTPDC_IDX]
469#define MGTPTC pThis->auRegs[MGTPTC_IDX]
470#define TORL pThis->auRegs[TORL_IDX]
471#define TORH pThis->auRegs[TORH_IDX]
472#define TOTL pThis->auRegs[TOTL_IDX]
473#define TOTH pThis->auRegs[TOTH_IDX]
474#define TPR pThis->auRegs[TPR_IDX]
475#define TPT pThis->auRegs[TPT_IDX]
476#define PTC64 pThis->auRegs[PTC64_IDX]
477#define PTC127 pThis->auRegs[PTC127_IDX]
478#define PTC255 pThis->auRegs[PTC255_IDX]
479#define PTC511 pThis->auRegs[PTC511_IDX]
480#define PTC1023 pThis->auRegs[PTC1023_IDX]
481#define PTC1522 pThis->auRegs[PTC1522_IDX]
482#define MPTC pThis->auRegs[MPTC_IDX]
483#define BPTC pThis->auRegs[BPTC_IDX]
484#define TSCTC pThis->auRegs[TSCTC_IDX]
485#define TSCTFC pThis->auRegs[TSCTFC_IDX]
486#define RXCSUM pThis->auRegs[RXCSUM_IDX]
487#define WUC pThis->auRegs[WUC_IDX]
488#define WUFC pThis->auRegs[WUFC_IDX]
489#define WUS pThis->auRegs[WUS_IDX]
490#define MANC pThis->auRegs[MANC_IDX]
491#define IPAV pThis->auRegs[IPAV_IDX]
492#define WUPL pThis->auRegs[WUPL_IDX]
493/** @} */
494
495/**
496 * Indices of memory-mapped registers in register table.
497 */
498typedef enum
499{
500 CTRL_IDX,
501 STATUS_IDX,
502 EECD_IDX,
503 EERD_IDX,
504 CTRL_EXT_IDX,
505 FLA_IDX,
506 MDIC_IDX,
507 FCAL_IDX,
508 FCAH_IDX,
509 FCT_IDX,
510 VET_IDX,
511 ICR_IDX,
512 ITR_IDX,
513 ICS_IDX,
514 IMS_IDX,
515 IMC_IDX,
516 RCTL_IDX,
517 FCTTV_IDX,
518 TXCW_IDX,
519 RXCW_IDX,
520 TCTL_IDX,
521 TIPG_IDX,
522 AIFS_IDX,
523 LEDCTL_IDX,
524 PBA_IDX,
525 FCRTL_IDX,
526 FCRTH_IDX,
527 RDFH_IDX,
528 RDFT_IDX,
529 RDFHS_IDX,
530 RDFTS_IDX,
531 RDFPC_IDX,
532 RDBAL_IDX,
533 RDBAH_IDX,
534 RDLEN_IDX,
535 RDH_IDX,
536 RDT_IDX,
537 RDTR_IDX,
538 RXDCTL_IDX,
539 RADV_IDX,
540 RSRPD_IDX,
541 TXDMAC_IDX,
542 TDFH_IDX,
543 TDFT_IDX,
544 TDFHS_IDX,
545 TDFTS_IDX,
546 TDFPC_IDX,
547 TDBAL_IDX,
548 TDBAH_IDX,
549 TDLEN_IDX,
550 TDH_IDX,
551 TDT_IDX,
552 TIDV_IDX,
553 TXDCTL_IDX,
554 TADV_IDX,
555 TSPMT_IDX,
556 CRCERRS_IDX,
557 ALGNERRC_IDX,
558 SYMERRS_IDX,
559 RXERRC_IDX,
560 MPC_IDX,
561 SCC_IDX,
562 ECOL_IDX,
563 MCC_IDX,
564 LATECOL_IDX,
565 COLC_IDX,
566 DC_IDX,
567 TNCRS_IDX,
568 SEC_IDX,
569 CEXTERR_IDX,
570 RLEC_IDX,
571 XONRXC_IDX,
572 XONTXC_IDX,
573 XOFFRXC_IDX,
574 XOFFTXC_IDX,
575 FCRUC_IDX,
576 PRC64_IDX,
577 PRC127_IDX,
578 PRC255_IDX,
579 PRC511_IDX,
580 PRC1023_IDX,
581 PRC1522_IDX,
582 GPRC_IDX,
583 BPRC_IDX,
584 MPRC_IDX,
585 GPTC_IDX,
586 GORCL_IDX,
587 GORCH_IDX,
588 GOTCL_IDX,
589 GOTCH_IDX,
590 RNBC_IDX,
591 RUC_IDX,
592 RFC_IDX,
593 ROC_IDX,
594 RJC_IDX,
595 MGTPRC_IDX,
596 MGTPDC_IDX,
597 MGTPTC_IDX,
598 TORL_IDX,
599 TORH_IDX,
600 TOTL_IDX,
601 TOTH_IDX,
602 TPR_IDX,
603 TPT_IDX,
604 PTC64_IDX,
605 PTC127_IDX,
606 PTC255_IDX,
607 PTC511_IDX,
608 PTC1023_IDX,
609 PTC1522_IDX,
610 MPTC_IDX,
611 BPTC_IDX,
612 TSCTC_IDX,
613 TSCTFC_IDX,
614 RXCSUM_IDX,
615 WUC_IDX,
616 WUFC_IDX,
617 WUS_IDX,
618 MANC_IDX,
619 IPAV_IDX,
620 WUPL_IDX,
621 MTA_IDX,
622 RA_IDX,
623 VFTA_IDX,
624 IP4AT_IDX,
625 IP6AT_IDX,
626 WUPM_IDX,
627 FFLT_IDX,
628 FFMT_IDX,
629 FFVT_IDX,
630 PBM_IDX,
631 RA_82542_IDX,
632 MTA_82542_IDX,
633 VFTA_82542_IDX,
634 E1K_NUM_OF_REGS
635} E1kRegIndex;
636
637#define E1K_NUM_OF_32BIT_REGS MTA_IDX
638/** The number of registers with strictly increasing offset. */
639#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
640
641
642/**
643 * Define E1000-specific EEPROM layout.
644 */
645struct E1kEEPROM
646{
647 public:
648 EEPROM93C46 eeprom;
649
650#ifdef IN_RING3
651 /**
652 * Initialize EEPROM content.
653 *
654 * @param macAddr MAC address of E1000.
655 */
656 void init(RTMAC &macAddr)
657 {
658 eeprom.init();
659 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
660 eeprom.m_au16Data[0x04] = 0xFFFF;
661 /*
662 * bit 3 - full support for power management
663 * bit 10 - full duplex
664 */
665 eeprom.m_au16Data[0x0A] = 0x4408;
666 eeprom.m_au16Data[0x0B] = 0x001E;
667 eeprom.m_au16Data[0x0C] = 0x8086;
668 eeprom.m_au16Data[0x0D] = 0x100E;
669 eeprom.m_au16Data[0x0E] = 0x8086;
670 eeprom.m_au16Data[0x0F] = 0x3040;
671 eeprom.m_au16Data[0x21] = 0x7061;
672 eeprom.m_au16Data[0x22] = 0x280C;
673 eeprom.m_au16Data[0x23] = 0x00C8;
674 eeprom.m_au16Data[0x24] = 0x00C8;
675 eeprom.m_au16Data[0x2F] = 0x0602;
676 updateChecksum();
677 };
678
679 /**
680 * Compute the checksum as required by E1000 and store it
681 * in the last word.
682 */
683 void updateChecksum()
684 {
685 uint16_t u16Checksum = 0;
686
687 for (int i = 0; i < eeprom.SIZE-1; i++)
688 u16Checksum += eeprom.m_au16Data[i];
689 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
690 };
691
692 /**
693 * First 6 bytes of EEPROM contain MAC address.
694 *
695 * @returns MAC address of E1000.
696 */
697 void getMac(PRTMAC pMac)
698 {
699 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
700 };
701
702 uint32_t read()
703 {
704 return eeprom.read();
705 }
706
707 void write(uint32_t u32Wires)
708 {
709 eeprom.write(u32Wires);
710 }
711
712 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
713 {
714 return eeprom.readWord(u32Addr, pu16Value);
715 }
716
717 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
718 {
719 return eeprom.load(pHlp, pSSM);
720 }
721
722 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
723 {
724 eeprom.save(pHlp, pSSM);
725 }
726#endif /* IN_RING3 */
727};
728
729
730#define E1K_SPEC_VLAN(s) (s & 0xFFF)
731#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
732#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
733
734struct E1kRxDStatus
735{
736 /** @name Descriptor Status field (3.2.3.1)
737 * @{ */
738 unsigned fDD : 1; /**< Descriptor Done. */
739 unsigned fEOP : 1; /**< End of packet. */
740 unsigned fIXSM : 1; /**< Ignore checksum indication. */
741 unsigned fVP : 1; /**< VLAN, matches VET. */
742 unsigned : 1;
743 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
744 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
745 unsigned fPIF : 1; /**< Passed in-exact filter */
746 /** @} */
747 /** @name Descriptor Errors field (3.2.3.2)
748 * (Only valid when fEOP and fDD are set.)
749 * @{ */
750 unsigned fCE : 1; /**< CRC or alignment error. */
751 unsigned : 4; /**< Reserved, varies with different models... */
752 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
753 unsigned fIPE : 1; /**< IP Checksum error. */
754 unsigned fRXE : 1; /**< RX Data error. */
755 /** @} */
756 /** @name Descriptor Special field (3.2.3.3)
757 * @{ */
758 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
759 /** @} */
760};
761typedef struct E1kRxDStatus E1KRXDST;
762
763struct E1kRxDesc_st
764{
765 uint64_t u64BufAddr; /**< Address of data buffer */
766 uint16_t u16Length; /**< Length of data in buffer */
767 uint16_t u16Checksum; /**< Packet checksum */
768 E1KRXDST status;
769};
770typedef struct E1kRxDesc_st E1KRXDESC;
771AssertCompileSize(E1KRXDESC, 16);
772
773#define E1K_DTYP_LEGACY -1
774#define E1K_DTYP_CONTEXT 0
775#define E1K_DTYP_DATA 1
776
777struct E1kTDLegacy
778{
779 uint64_t u64BufAddr; /**< Address of data buffer */
780 struct TDLCmd_st
781 {
782 unsigned u16Length : 16;
783 unsigned u8CSO : 8;
784 /* CMD field : 8 */
785 unsigned fEOP : 1;
786 unsigned fIFCS : 1;
787 unsigned fIC : 1;
788 unsigned fRS : 1;
789 unsigned fRPS : 1;
790 unsigned fDEXT : 1;
791 unsigned fVLE : 1;
792 unsigned fIDE : 1;
793 } cmd;
794 struct TDLDw3_st
795 {
796 /* STA field */
797 unsigned fDD : 1;
798 unsigned fEC : 1;
799 unsigned fLC : 1;
800 unsigned fTURSV : 1;
801 /* RSV field */
802 unsigned u4RSV : 4;
803 /* CSS field */
804 unsigned u8CSS : 8;
805 /* Special field*/
806 unsigned u16Special: 16;
807 } dw3;
808};
809
810/**
811 * TCP/IP Context Transmit Descriptor, section 3.3.6.
812 */
813struct E1kTDContext
814{
815 struct CheckSum_st
816 {
817 /** TSE: Header start. !TSE: Checksum start. */
818 unsigned u8CSS : 8;
819 /** Checksum offset - where to store it. */
820 unsigned u8CSO : 8;
821 /** Checksum ending (inclusive) offset, 0 = end of packet. */
822 unsigned u16CSE : 16;
823 } ip;
824 struct CheckSum_st tu;
825 struct TDCDw2_st
826 {
827 /** TSE: The total number of payload bytes for this context. Sans header. */
828 unsigned u20PAYLEN : 20;
829 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
830 unsigned u4DTYP : 4;
831 /** TUCMD field, 8 bits
832 * @{ */
833 /** TSE: TCP (set) or UDP (clear). */
834 unsigned fTCP : 1;
835 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
836 * the IP header. Does not affect the checksumming.
837 * @remarks 82544GC/EI interprets a cleared field differently. */
838 unsigned fIP : 1;
839 /** TSE: TCP segmentation enable. When clear the context describes */
840 unsigned fTSE : 1;
841 /** Report status (only applies to dw3.fDD for here). */
842 unsigned fRS : 1;
843 /** Reserved, MBZ. */
844 unsigned fRSV1 : 1;
845 /** Descriptor extension, must be set for this descriptor type. */
846 unsigned fDEXT : 1;
847 /** Reserved, MBZ. */
848 unsigned fRSV2 : 1;
849 /** Interrupt delay enable. */
850 unsigned fIDE : 1;
851 /** @} */
852 } dw2;
853 struct TDCDw3_st
854 {
855 /** Descriptor Done. */
856 unsigned fDD : 1;
857 /** Reserved, MBZ. */
858 unsigned u7RSV : 7;
859 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
860 unsigned u8HDRLEN : 8;
861 /** TSO: Maximum segment size. */
862 unsigned u16MSS : 16;
863 } dw3;
864};
865typedef struct E1kTDContext E1KTXCTX;
866
867/**
868 * TCP/IP Data Transmit Descriptor, section 3.3.7.
869 */
870struct E1kTDData
871{
872 uint64_t u64BufAddr; /**< Address of data buffer */
873 struct TDDCmd_st
874 {
875 /** The total length of data pointed to by this descriptor. */
876 unsigned u20DTALEN : 20;
877 /** The descriptor type - E1K_DTYP_DATA (1). */
878 unsigned u4DTYP : 4;
879 /** @name DCMD field, 8 bits (3.3.7.1).
880 * @{ */
881 /** End of packet. Note TSCTFC update. */
882 unsigned fEOP : 1;
883 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
884 unsigned fIFCS : 1;
885 /** Use the TSE context when set and the normal when clear. */
886 unsigned fTSE : 1;
887 /** Report status (dw3.STA). */
888 unsigned fRS : 1;
889 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
890 unsigned fRPS : 1;
891 /** Descriptor extension, must be set for this descriptor type. */
892 unsigned fDEXT : 1;
893 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
894 * Insert dw3.SPECIAL after ethernet header. */
895 unsigned fVLE : 1;
896 /** Interrupt delay enable. */
897 unsigned fIDE : 1;
898 /** @} */
899 } cmd;
900 struct TDDDw3_st
901 {
902 /** @name STA field (3.3.7.2)
903 * @{ */
904 unsigned fDD : 1; /**< Descriptor done. */
905 unsigned fEC : 1; /**< Excess collision. */
906 unsigned fLC : 1; /**< Late collision. */
907 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
908 unsigned fTURSV : 1;
909 /** @} */
910 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
911 /** @name POPTS (Packet Option) field (3.3.7.3)
912 * @{ */
913 unsigned fIXSM : 1; /**< Insert IP checksum. */
914 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
915 unsigned u6RSV : 6; /**< Reserved, MBZ. */
916 /** @} */
917 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
918 * Requires fEOP, fVLE and CTRL.VME to be set.
919 * @{ */
920 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
921 /** @} */
922 } dw3;
923};
924typedef struct E1kTDData E1KTXDAT;
925
926union E1kTxDesc
927{
928 struct E1kTDLegacy legacy;
929 struct E1kTDContext context;
930 struct E1kTDData data;
931};
932typedef union E1kTxDesc E1KTXDESC;
933AssertCompileSize(E1KTXDESC, 16);
934
935#define RA_CTL_AS 0x0003
936#define RA_CTL_AV 0x8000
937
938union E1kRecAddr
939{
940 uint32_t au32[32];
941 struct RAArray
942 {
943 uint8_t addr[6];
944 uint16_t ctl;
945 } array[16];
946};
947typedef struct E1kRecAddr::RAArray E1KRAELEM;
948typedef union E1kRecAddr E1KRA;
949AssertCompileSize(E1KRA, 8*16);
950
951#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
952#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
953#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
954#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
955
956/** @todo use+extend RTNETIPV4 */
957struct E1kIpHeader
958{
959 /* type of service / version / header length */
960 uint16_t tos_ver_hl;
961 /* total length */
962 uint16_t total_len;
963 /* identification */
964 uint16_t ident;
965 /* fragment offset field */
966 uint16_t offset;
967 /* time to live / protocol*/
968 uint16_t ttl_proto;
969 /* checksum */
970 uint16_t chksum;
971 /* source IP address */
972 uint32_t src;
973 /* destination IP address */
974 uint32_t dest;
975};
976AssertCompileSize(struct E1kIpHeader, 20);
977
978#define E1K_TCP_FIN UINT16_C(0x01)
979#define E1K_TCP_SYN UINT16_C(0x02)
980#define E1K_TCP_RST UINT16_C(0x04)
981#define E1K_TCP_PSH UINT16_C(0x08)
982#define E1K_TCP_ACK UINT16_C(0x10)
983#define E1K_TCP_URG UINT16_C(0x20)
984#define E1K_TCP_ECE UINT16_C(0x40)
985#define E1K_TCP_CWR UINT16_C(0x80)
986#define E1K_TCP_FLAGS UINT16_C(0x3f)
987
988/** @todo use+extend RTNETTCP */
989struct E1kTcpHeader
990{
991 uint16_t src;
992 uint16_t dest;
993 uint32_t seqno;
994 uint32_t ackno;
995 uint16_t hdrlen_flags;
996 uint16_t wnd;
997 uint16_t chksum;
998 uint16_t urgp;
999};
1000AssertCompileSize(struct E1kTcpHeader, 20);
1001
1002
1003#ifdef E1K_WITH_TXD_CACHE
1004/** The current Saved state version. */
1005# define E1K_SAVEDSTATE_VERSION 4
1006/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1007# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1008#else /* !E1K_WITH_TXD_CACHE */
1009/** The current Saved state version. */
1010# define E1K_SAVEDSTATE_VERSION 3
1011#endif /* !E1K_WITH_TXD_CACHE */
1012/** Saved state version for VirtualBox 4.1 and earlier.
1013 * These did not include VLAN tag fields. */
1014#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1015/** Saved state version for VirtualBox 3.0 and earlier.
1016 * This did not include the configuration part nor the E1kEEPROM. */
1017#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1018
1019/**
1020 * E1000 shared device state.
1021 *
1022 * This is shared between ring-0 and ring-3.
1023 */
1024typedef struct E1KSTATE
1025{
1026 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1027
1028 /** Handle to PCI region \#0, the MMIO region. */
1029 IOMIOPORTHANDLE hMmioRegion;
1030 /** Handle to PCI region \#2, the I/O ports. */
1031 IOMIOPORTHANDLE hIoPorts;
1032
1033 /** Receive Interrupt Delay Timer. */
1034 TMTIMERHANDLE hRIDTimer;
1035 /** Receive Absolute Delay Timer. */
1036 TMTIMERHANDLE hRADTimer;
1037 /** Transmit Interrupt Delay Timer. */
1038 TMTIMERHANDLE hTIDTimer;
1039 /** Transmit Absolute Delay Timer. */
1040 TMTIMERHANDLE hTADTimer;
1041 /** Transmit Delay Timer. */
1042 TMTIMERHANDLE hTXDTimer;
1043 /** Late Interrupt Timer. */
1044 TMTIMERHANDLE hIntTimer;
1045 /** Link Up(/Restore) Timer. */
1046 TMTIMERHANDLE hLUTimer;
1047
1048 /** Transmit task. */
1049 PDMTASKHANDLE hTxTask;
1050
1051 /** Critical section - what is it protecting? */
1052 PDMCRITSECT cs;
1053 /** RX Critical section. */
1054 PDMCRITSECT csRx;
1055#ifdef E1K_WITH_TX_CS
1056 /** TX Critical section. */
1057 PDMCRITSECT csTx;
1058#endif /* E1K_WITH_TX_CS */
1059 /** MAC address obtained from the configuration. */
1060 RTMAC macConfigured;
1061 uint16_t u16Padding0;
1062 /** EMT: Last time the interrupt was acknowledged. */
1063 uint64_t u64AckedAt;
1064 /** All: Used for eliminating spurious interrupts. */
1065 bool fIntRaised;
1066 /** EMT: false if the cable is disconnected by the GUI. */
1067 bool fCableConnected;
1068 /** EMT: Compute Ethernet CRC for RX packets. */
1069 bool fEthernetCRC;
1070 /** All: throttle interrupts. */
1071 bool fItrEnabled;
1072 /** All: throttle RX interrupts. */
1073 bool fItrRxEnabled;
1074 /** All: Delay TX interrupts using TIDV/TADV. */
1075 bool fTidEnabled;
1076 bool afPadding[2];
1077 /** Link up delay (in milliseconds). */
1078 uint32_t cMsLinkUpDelay;
1079
1080 /** All: Device register storage. */
1081 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1082 /** TX/RX: Status LED. */
1083 PDMLED led;
1084 /** TX/RX: Number of packet being sent/received to show in debug log. */
1085 uint32_t u32PktNo;
1086
1087 /** EMT: Offset of the register to be read via IO. */
1088 uint32_t uSelectedReg;
1089 /** EMT: Multicast Table Array. */
1090 uint32_t auMTA[128];
1091 /** EMT: Receive Address registers. */
1092 E1KRA aRecAddr;
1093 /** EMT: VLAN filter table array. */
1094 uint32_t auVFTA[128];
1095 /** EMT: Receive buffer size. */
1096 uint16_t u16RxBSize;
1097 /** EMT: Locked state -- no state alteration possible. */
1098 bool fLocked;
1099 /** EMT: */
1100 bool fDelayInts;
1101 /** All: */
1102 bool fIntMaskUsed;
1103
1104 /** N/A: */
1105 bool volatile fMaybeOutOfSpace;
1106 /** EMT: Gets signalled when more RX descriptors become available. */
1107 SUPSEMEVENT hEventMoreRxDescAvail;
1108#ifdef E1K_WITH_RXD_CACHE
1109 /** RX: Fetched RX descriptors. */
1110 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1111 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1112 /** RX: Actual number of fetched RX descriptors. */
1113 uint32_t nRxDFetched;
1114 /** RX: Index in cache of RX descriptor being processed. */
1115 uint32_t iRxDCurrent;
1116#endif /* E1K_WITH_RXD_CACHE */
1117
1118 /** TX: Context used for TCP segmentation packets. */
1119 E1KTXCTX contextTSE;
1120 /** TX: Context used for ordinary packets. */
1121 E1KTXCTX contextNormal;
1122#ifdef E1K_WITH_TXD_CACHE
1123 /** TX: Fetched TX descriptors. */
1124 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1125 /** TX: Actual number of fetched TX descriptors. */
1126 uint8_t nTxDFetched;
1127 /** TX: Index in cache of TX descriptor being processed. */
1128 uint8_t iTxDCurrent;
1129 /** TX: Will this frame be sent as GSO. */
1130 bool fGSO;
1131 /** Alignment padding. */
1132 bool fReserved;
1133 /** TX: Number of bytes in next packet. */
1134 uint32_t cbTxAlloc;
1135
1136#endif /* E1K_WITH_TXD_CACHE */
1137 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1138 * applicable to the current TSE mode. */
1139 PDMNETWORKGSO GsoCtx;
1140 /** Scratch space for holding the loopback / fallback scatter / gather
1141 * descriptor. */
1142 union
1143 {
1144 PDMSCATTERGATHER Sg;
1145 uint8_t padding[8 * sizeof(RTUINTPTR)];
1146 } uTxFallback;
1147 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1148 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1149 /** TX: Number of bytes assembled in TX packet buffer. */
1150 uint16_t u16TxPktLen;
1151 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1152 bool fGSOEnabled;
1153 /** TX: IP checksum has to be inserted if true. */
1154 bool fIPcsum;
1155 /** TX: TCP/UDP checksum has to be inserted if true. */
1156 bool fTCPcsum;
1157 /** TX: VLAN tag has to be inserted if true. */
1158 bool fVTag;
1159 /** TX: TCI part of VLAN tag to be inserted. */
1160 uint16_t u16VTagTCI;
1161 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1162 uint32_t u32PayRemain;
1163 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1164 uint16_t u16HdrRemain;
1165 /** TX TSE fallback: Flags from template header. */
1166 uint16_t u16SavedFlags;
1167 /** TX TSE fallback: Partial checksum from template header. */
1168 uint32_t u32SavedCsum;
1169 /** ?: Emulated controller type. */
1170 E1KCHIP eChip;
1171
1172 /** EMT: Physical interface emulation. */
1173 PHY phy;
1174
1175#if 0
1176 /** Alignment padding. */
1177 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1178#endif
1179
1180 STAMCOUNTER StatReceiveBytes;
1181 STAMCOUNTER StatTransmitBytes;
1182#if defined(VBOX_WITH_STATISTICS)
1183 STAMPROFILEADV StatMMIOReadRZ;
1184 STAMPROFILEADV StatMMIOReadR3;
1185 STAMPROFILEADV StatMMIOWriteRZ;
1186 STAMPROFILEADV StatMMIOWriteR3;
1187 STAMPROFILEADV StatEEPROMRead;
1188 STAMPROFILEADV StatEEPROMWrite;
1189 STAMPROFILEADV StatIOReadRZ;
1190 STAMPROFILEADV StatIOReadR3;
1191 STAMPROFILEADV StatIOWriteRZ;
1192 STAMPROFILEADV StatIOWriteR3;
1193 STAMPROFILEADV StatLateIntTimer;
1194 STAMCOUNTER StatLateInts;
1195 STAMCOUNTER StatIntsRaised;
1196 STAMCOUNTER StatIntsPrevented;
1197 STAMPROFILEADV StatReceive;
1198 STAMPROFILEADV StatReceiveCRC;
1199 STAMPROFILEADV StatReceiveFilter;
1200 STAMPROFILEADV StatReceiveStore;
1201 STAMPROFILEADV StatTransmitRZ;
1202 STAMPROFILEADV StatTransmitR3;
1203 STAMPROFILE StatTransmitSendRZ;
1204 STAMPROFILE StatTransmitSendR3;
1205 STAMPROFILE StatRxOverflow;
1206 STAMCOUNTER StatRxOverflowWakeupRZ;
1207 STAMCOUNTER StatRxOverflowWakeupR3;
1208 STAMCOUNTER StatTxDescCtxNormal;
1209 STAMCOUNTER StatTxDescCtxTSE;
1210 STAMCOUNTER StatTxDescLegacy;
1211 STAMCOUNTER StatTxDescData;
1212 STAMCOUNTER StatTxDescTSEData;
1213 STAMCOUNTER StatTxPathFallback;
1214 STAMCOUNTER StatTxPathGSO;
1215 STAMCOUNTER StatTxPathRegular;
1216 STAMCOUNTER StatPHYAccesses;
1217 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1218 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1219#endif /* VBOX_WITH_STATISTICS */
1220
1221#ifdef E1K_INT_STATS
1222 /* Internal stats */
1223 uint64_t u64ArmedAt;
1224 uint64_t uStatMaxTxDelay;
1225 uint32_t uStatInt;
1226 uint32_t uStatIntTry;
1227 uint32_t uStatIntLower;
1228 uint32_t uStatNoIntICR;
1229 int32_t iStatIntLost;
1230 int32_t iStatIntLostOne;
1231 uint32_t uStatIntIMS;
1232 uint32_t uStatIntSkip;
1233 uint32_t uStatIntLate;
1234 uint32_t uStatIntMasked;
1235 uint32_t uStatIntEarly;
1236 uint32_t uStatIntRx;
1237 uint32_t uStatIntTx;
1238 uint32_t uStatIntICS;
1239 uint32_t uStatIntRDTR;
1240 uint32_t uStatIntRXDMT0;
1241 uint32_t uStatIntTXQE;
1242 uint32_t uStatTxNoRS;
1243 uint32_t uStatTxIDE;
1244 uint32_t uStatTxDelayed;
1245 uint32_t uStatTxDelayExp;
1246 uint32_t uStatTAD;
1247 uint32_t uStatTID;
1248 uint32_t uStatRAD;
1249 uint32_t uStatRID;
1250 uint32_t uStatRxFrm;
1251 uint32_t uStatTxFrm;
1252 uint32_t uStatDescCtx;
1253 uint32_t uStatDescDat;
1254 uint32_t uStatDescLeg;
1255 uint32_t uStatTx1514;
1256 uint32_t uStatTx2962;
1257 uint32_t uStatTx4410;
1258 uint32_t uStatTx5858;
1259 uint32_t uStatTx7306;
1260 uint32_t uStatTx8754;
1261 uint32_t uStatTx16384;
1262 uint32_t uStatTx32768;
1263 uint32_t uStatTxLarge;
1264 uint32_t uStatAlign;
1265#endif /* E1K_INT_STATS */
1266} E1KSTATE;
1267/** Pointer to the E1000 device state. */
1268typedef E1KSTATE *PE1KSTATE;
1269
1270/**
1271 * E1000 ring-3 device state
1272 *
1273 * @implements PDMINETWORKDOWN
1274 * @implements PDMINETWORKCONFIG
1275 * @implements PDMILEDPORTS
1276 */
1277typedef struct E1KSTATER3
1278{
1279 PDMIBASE IBase;
1280 PDMINETWORKDOWN INetworkDown;
1281 PDMINETWORKCONFIG INetworkConfig;
1282 /** LED interface */
1283 PDMILEDPORTS ILeds;
1284 /** Attached network driver. */
1285 R3PTRTYPE(PPDMIBASE) pDrvBase;
1286 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1287
1288 /** Pointer to the shared state. */
1289 R3PTRTYPE(PE1KSTATE) pShared;
1290
1291 /** Device instance. */
1292 PPDMDEVINSR3 pDevInsR3;
1293 /** Attached network driver. */
1294 PPDMINETWORKUPR3 pDrvR3;
1295 /** The scatter / gather buffer used for the current outgoing packet. */
1296 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1297
1298 /** EMT: EEPROM emulation */
1299 E1kEEPROM eeprom;
1300} E1KSTATER3;
1301/** Pointer to the E1000 ring-3 device state. */
1302typedef E1KSTATER3 *PE1KSTATER3;
1303
1304
1305/**
1306 * E1000 ring-0 device state
1307 */
1308typedef struct E1KSTATER0
1309{
1310 /** Device instance. */
1311 PPDMDEVINSR0 pDevInsR0;
1312 /** Attached network driver. */
1313 PPDMINETWORKUPR0 pDrvR0;
1314 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1315 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1316} E1KSTATER0;
1317/** Pointer to the E1000 ring-0 device state. */
1318typedef E1KSTATER0 *PE1KSTATER0;
1319
1320
1321/**
1322 * E1000 raw-mode device state
1323 */
1324typedef struct E1KSTATERC
1325{
1326 /** Device instance. */
1327 PPDMDEVINSRC pDevInsRC;
1328 /** Attached network driver. */
1329 PPDMINETWORKUPRC pDrvRC;
1330 /** The scatter / gather buffer used for the current outgoing packet. */
1331 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1332} E1KSTATERC;
1333/** Pointer to the E1000 raw-mode device state. */
1334typedef E1KSTATERC *PE1KSTATERC;
1335
1336
1337/** @def PE1KSTATECC
1338 * Pointer to the instance data for the current context. */
1339#ifdef IN_RING3
1340typedef E1KSTATER3 E1KSTATECC;
1341typedef PE1KSTATER3 PE1KSTATECC;
1342#elif defined(IN_RING0)
1343typedef E1KSTATER0 E1KSTATECC;
1344typedef PE1KSTATER0 PE1KSTATECC;
1345#elif defined(IN_RC)
1346typedef E1KSTATERC E1KSTATECC;
1347typedef PE1KSTATERC PE1KSTATECC;
1348#else
1349# error "Not IN_RING3, IN_RING0 or IN_RC"
1350#endif
1351
1352
1353#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1354
1355/* Forward declarations ******************************************************/
1356static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1357
1358/**
1359 * E1000 register read handler.
1360 */
1361typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1362/**
1363 * E1000 register write handler.
1364 */
1365typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1366
1367static FNE1KREGREAD e1kRegReadUnimplemented;
1368static FNE1KREGWRITE e1kRegWriteUnimplemented;
1369static FNE1KREGREAD e1kRegReadAutoClear;
1370static FNE1KREGREAD e1kRegReadDefault;
1371static FNE1KREGWRITE e1kRegWriteDefault;
1372#if 0 /* unused */
1373static FNE1KREGREAD e1kRegReadCTRL;
1374#endif
1375static FNE1KREGWRITE e1kRegWriteCTRL;
1376static FNE1KREGREAD e1kRegReadEECD;
1377static FNE1KREGWRITE e1kRegWriteEECD;
1378static FNE1KREGWRITE e1kRegWriteEERD;
1379static FNE1KREGWRITE e1kRegWriteMDIC;
1380static FNE1KREGREAD e1kRegReadICR;
1381static FNE1KREGWRITE e1kRegWriteICR;
1382static FNE1KREGREAD e1kRegReadICS;
1383static FNE1KREGWRITE e1kRegWriteICS;
1384static FNE1KREGWRITE e1kRegWriteIMS;
1385static FNE1KREGWRITE e1kRegWriteIMC;
1386static FNE1KREGWRITE e1kRegWriteRCTL;
1387static FNE1KREGWRITE e1kRegWritePBA;
1388static FNE1KREGWRITE e1kRegWriteRDT;
1389static FNE1KREGWRITE e1kRegWriteRDTR;
1390static FNE1KREGWRITE e1kRegWriteTDT;
1391static FNE1KREGREAD e1kRegReadMTA;
1392static FNE1KREGWRITE e1kRegWriteMTA;
1393static FNE1KREGREAD e1kRegReadRA;
1394static FNE1KREGWRITE e1kRegWriteRA;
1395static FNE1KREGREAD e1kRegReadVFTA;
1396static FNE1KREGWRITE e1kRegWriteVFTA;
1397
1398/**
1399 * Register map table.
1400 *
1401 * Override pfnRead and pfnWrite to get register-specific behavior.
1402 */
1403static const struct E1kRegMap_st
1404{
1405 /** Register offset in the register space. */
1406 uint32_t offset;
1407 /** Size in bytes. Registers of size > 4 are in fact tables. */
1408 uint32_t size;
1409 /** Readable bits. */
1410 uint32_t readable;
1411 /** Writable bits. */
1412 uint32_t writable;
1413 /** Read callback. */
1414 FNE1KREGREAD *pfnRead;
1415 /** Write callback. */
1416 FNE1KREGWRITE *pfnWrite;
1417 /** Abbreviated name. */
1418 const char *abbrev;
1419 /** Full name. */
1420 const char *name;
1421} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1422{
1423 /* offset size read mask write mask read callback write callback abbrev full name */
1424 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1425 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1426 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1427 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1428 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1429 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1430 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1431 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1432 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1433 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1434 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1435 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1436 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1437 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1438 { 0x000c8, 0x00004, 0x0001F6DF, 0xFFFFFFFF, e1kRegReadICS , e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1439 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1440 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1441 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1442 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1443 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1444 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1445 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1446 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1447 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1448 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1449 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1450 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1451 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1452 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1453 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1454 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1455 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1456 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1457 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1458 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1459 { 0x02808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1460 { 0x02810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1461 { 0x02818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1462 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1463 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1464 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1465 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1466 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1467 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1468 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1469 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1470 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1471 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1472 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1473 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1474 { 0x03808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1475 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1476 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1477 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1478 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1479 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1480 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1481 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1482 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1483 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1484 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1485 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1486 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1487 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1488 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1489 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1490 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1491 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1492 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1493 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1494 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1495 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1496 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1497 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1498 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1499 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1500 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1501 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1502 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1503 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1504 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1505 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1506 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1507 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1508 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1509 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1510 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1511 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1512 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1513 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1514 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1515 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1516 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1517 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1518 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1519 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1520 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1521 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1522 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1523 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1524 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1525 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1526 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1527 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1528 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1529 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1530 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1531 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1532 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1533 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1534 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1535 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1536 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1537 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1538 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1539 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1540 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1541 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1542 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1543 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1544 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1545 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1546 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1547 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1548 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1549 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1550 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1551 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1552 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1553 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1554 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1555 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1556 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1557 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1558 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1559};
1560
1561#ifdef LOG_ENABLED
1562
1563/**
1564 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1565 *
1566 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1567 *
1568 * @returns The buffer.
1569 *
1570 * @param u32 The word to convert into string.
1571 * @param mask Selects which bytes to convert.
1572 * @param buf Where to put the result.
1573 */
1574static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1575{
1576 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1577 {
1578 if (mask & 0xF)
1579 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1580 else
1581 *ptr = '.';
1582 }
1583 buf[8] = 0;
1584 return buf;
1585}
1586
1587/**
1588 * Returns timer name for debug purposes.
1589 *
1590 * @returns The timer name.
1591 *
1592 * @param pThis The device state structure.
1593 * @param hTimer The timer to name.
1594 */
1595DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1596{
1597 if (hTimer == pThis->hTIDTimer)
1598 return "TID";
1599 if (hTimer == pThis->hTADTimer)
1600 return "TAD";
1601 if (hTimer == pThis->hRIDTimer)
1602 return "RID";
1603 if (hTimer == pThis->hRADTimer)
1604 return "RAD";
1605 if (hTimer == pThis->hIntTimer)
1606 return "Int";
1607 if (hTimer == pThis->hTXDTimer)
1608 return "TXD";
1609 if (hTimer == pThis->hLUTimer)
1610 return "LinkUp";
1611 return "unknown";
1612}
1613
1614#endif /* LOG_ENABLED */
1615
1616/**
1617 * Arm a timer.
1618 *
1619 * @param pDevIns The device instance.
1620 * @param pThis Pointer to the device state structure.
1621 * @param hTimer The timer to arm.
1622 * @param uExpireIn Expiration interval in microseconds.
1623 */
1624DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1625{
1626 if (pThis->fLocked)
1627 return;
1628
1629 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1630 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1631 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1632 AssertRC(rc);
1633}
1634
1635#ifdef IN_RING3
1636/**
1637 * Cancel a timer.
1638 *
1639 * @param pDevIns The device instance.
1640 * @param pThis Pointer to the device state structure.
1641 * @param pTimer Pointer to the timer.
1642 */
1643DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1644{
1645 E1kLog2(("%s Stopping %s timer...\n",
1646 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1647 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1648 if (RT_FAILURE(rc))
1649 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1650 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1651 RT_NOREF_PV(pThis);
1652}
1653#endif /* IN_RING3 */
1654
1655#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1656#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1657
1658#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1659#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1660#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1661
1662#ifndef E1K_WITH_TX_CS
1663# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1664# define e1kCsTxLeave(ps) do { } while (0)
1665#else /* E1K_WITH_TX_CS */
1666# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1667# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1668# define e1kCsTxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csTx)
1669#endif /* E1K_WITH_TX_CS */
1670
1671
1672#ifdef E1K_WITH_TXD_CACHE
1673/*
1674 * Transmit Descriptor Register Context
1675 */
1676struct E1kTxDContext
1677{
1678 uint32_t tdlen;
1679 uint32_t tdh;
1680 uint32_t tdt;
1681};
1682typedef struct E1kTxDContext E1KTXDC, *PE1KTXDC;
1683
1684DECLINLINE(bool) e1kUpdateTxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pContext)
1685{
1686 Assert(e1kCsTxIsOwner(pThis));
1687 if (!e1kCsTxIsOwner(pThis))
1688 {
1689 memset(pContext, 0, sizeof(E1KTXDC));
1690 return false;
1691 }
1692 pContext->tdlen = TDLEN;
1693 pContext->tdh = TDH;
1694 pContext->tdt = TDT;
1695 uint32_t cTxRingSize = pContext->tdlen / sizeof(E1KTXDESC);
1696#ifdef DEBUG
1697 if (pContext->tdh >= cTxRingSize)
1698 {
1699 Log(("%s e1kUpdateTxDContext: will return false because TDH too big (%u >= %u)\n",
1700 pThis->szPrf, pContext->tdh, cTxRingSize));
1701 return VINF_SUCCESS;
1702 }
1703 if (pContext->tdt >= cTxRingSize)
1704 {
1705 Log(("%s e1kUpdateTxDContext: will return false because TDT too big (%u >= %u)\n",
1706 pThis->szPrf, pContext->tdt, cTxRingSize));
1707 return VINF_SUCCESS;
1708 }
1709#endif /* DEBUG */
1710 return pContext->tdh < cTxRingSize && pContext->tdt < cTxRingSize;
1711}
1712#endif /* E1K_WITH_TXD_CACHE */
1713#ifdef E1K_WITH_RXD_CACHE
1714/*
1715 * Receive Descriptor Register Context
1716 */
1717struct E1kRxDContext
1718{
1719 uint32_t rdlen;
1720 uint32_t rdh;
1721 uint32_t rdt;
1722};
1723typedef struct E1kRxDContext E1KRXDC, *PE1KRXDC;
1724
1725DECLINLINE(bool) e1kUpdateRxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pContext, const char *pcszCallee)
1726{
1727 Assert(e1kCsRxIsOwner(pThis));
1728 if (!e1kCsRxIsOwner(pThis))
1729 return false;
1730 pContext->rdlen = RDLEN;
1731 pContext->rdh = RDH;
1732 pContext->rdt = RDT;
1733 uint32_t cRxRingSize = pContext->rdlen / sizeof(E1KRXDESC);
1734 /*
1735 * Note that the checks for RDT are a bit different. Some guests, OS/2 for
1736 * example, intend to use all descriptors in RX ring, so they point RDT
1737 * right beyond the last descriptor in the ring. While this is not
1738 * acceptable for other registers, it works out fine for RDT.
1739 */
1740#ifdef DEBUG
1741 if (pContext->rdh >= cRxRingSize)
1742 {
1743 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDH too big (%u >= %u)\n",
1744 pThis->szPrf, pcszCallee, pContext->rdh, cRxRingSize));
1745 return VINF_SUCCESS;
1746 }
1747 if (pContext->rdt > cRxRingSize)
1748 {
1749 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDT too big (%u > %u)\n",
1750 pThis->szPrf, pcszCallee, pContext->rdt, cRxRingSize));
1751 return VINF_SUCCESS;
1752 }
1753#else /* !DEBUG */
1754 RT_NOREF(pcszCallee);
1755#endif /* !DEBUG */
1756 return pContext->rdh < cRxRingSize && pContext->rdt <= cRxRingSize; // && (RCTL & RCTL_EN);
1757}
1758#endif /* E1K_WITH_RXD_CACHE */
1759
1760/**
1761 * Wakeup the RX thread.
1762 */
1763static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1764{
1765 if ( pThis->fMaybeOutOfSpace
1766 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1767 {
1768 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1769 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1770 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1771 AssertRC(rc);
1772 }
1773}
1774
1775#ifdef IN_RING3
1776
1777/**
1778 * Hardware reset. Revert all registers to initial values.
1779 *
1780 * @param pDevIns The device instance.
1781 * @param pThis The device state structure.
1782 * @param pThisCC The current context instance data.
1783 */
1784static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1785{
1786 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1787 /* No interrupts should survive device reset, see @bugref(9556). */
1788 if (pThis->fIntRaised)
1789 {
1790 /* Lower(0) INTA(0) */
1791 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1792 pThis->fIntRaised = false;
1793 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1794 }
1795 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1796 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1797#ifdef E1K_INIT_RA0
1798 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1799 sizeof(pThis->macConfigured.au8));
1800 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1801#endif /* E1K_INIT_RA0 */
1802 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1803 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1804 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1805 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1806 Assert(GET_BITS(RCTL, BSIZE) == 0);
1807 pThis->u16RxBSize = 2048;
1808
1809 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1810 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1811 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1812
1813 /* Reset promiscuous mode */
1814 if (pThisCC->pDrvR3)
1815 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1816
1817#ifdef E1K_WITH_TXD_CACHE
1818 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1819 if (RT_LIKELY(rc == VINF_SUCCESS))
1820 {
1821 pThis->nTxDFetched = 0;
1822 pThis->iTxDCurrent = 0;
1823 pThis->fGSO = false;
1824 pThis->cbTxAlloc = 0;
1825 e1kCsTxLeave(pThis);
1826 }
1827#endif /* E1K_WITH_TXD_CACHE */
1828#ifdef E1K_WITH_RXD_CACHE
1829 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1830 {
1831 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1832 e1kCsRxLeave(pThis);
1833 }
1834#endif /* E1K_WITH_RXD_CACHE */
1835#ifdef E1K_LSC_ON_RESET
1836 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1837 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1838 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1839#endif /* E1K_LSC_ON_RESET */
1840}
1841
1842#endif /* IN_RING3 */
1843
1844/**
1845 * Compute Internet checksum.
1846 *
1847 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1848 *
1849 * @param pThis The device state structure.
1850 * @param cpPacket The packet.
1851 * @param cb The size of the packet.
1852 * @param pszText A string denoting direction of packet transfer.
1853 *
1854 * @return The 1's complement of the 1's complement sum.
1855 *
1856 * @thread E1000_TX
1857 */
1858static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1859{
1860 uint32_t csum = 0;
1861 uint16_t *pu16 = (uint16_t *)pvBuf;
1862
1863 while (cb > 1)
1864 {
1865 csum += *pu16++;
1866 cb -= 2;
1867 }
1868 if (cb)
1869 csum += *(uint8_t*)pu16;
1870 while (csum >> 16)
1871 csum = (csum >> 16) + (csum & 0xFFFF);
1872 Assert(csum < 65536);
1873 return (uint16_t)~csum;
1874}
1875
1876/**
1877 * Dump a packet to debug log.
1878 *
1879 * @param pDevIns The device instance.
1880 * @param pThis The device state structure.
1881 * @param cpPacket The packet.
1882 * @param cb The size of the packet.
1883 * @param pszText A string denoting direction of packet transfer.
1884 * @thread E1000_TX
1885 */
1886DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1887{
1888#ifdef DEBUG
1889 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1890 {
1891 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1892 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1893 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1894 {
1895 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1896 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1897 if (*(cpPacket+14+6) == 0x6)
1898 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1899 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1900 }
1901 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1902 {
1903 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1904 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1905 if (*(cpPacket+14+6) == 0x6)
1906 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1907 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1908 }
1909 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1910 e1kCsLeave(pThis);
1911 }
1912#else
1913 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1914 {
1915 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1916 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1917 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1918 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1919 else
1920 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1921 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1922 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1923 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1924 e1kCsLeave(pThis);
1925 }
1926 RT_NOREF2(cb, pszText);
1927#endif
1928}
1929
1930/**
1931 * Determine the type of transmit descriptor.
1932 *
1933 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1934 *
1935 * @param pDesc Pointer to descriptor union.
1936 * @thread E1000_TX
1937 */
1938DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1939{
1940 if (pDesc->legacy.cmd.fDEXT)
1941 return pDesc->context.dw2.u4DTYP;
1942 return E1K_DTYP_LEGACY;
1943}
1944
1945
1946#ifdef E1K_WITH_RXD_CACHE
1947/**
1948 * Return the number of RX descriptor that belong to the hardware.
1949 *
1950 * @returns the number of available descriptors in RX ring.
1951 * @param pRxdc The receive descriptor register context.
1952 * @thread ???
1953 */
1954DECLINLINE(uint32_t) e1kGetRxLen(PE1KRXDC pRxdc)
1955{
1956 /**
1957 * Make sure RDT won't change during computation. EMT may modify RDT at
1958 * any moment.
1959 */
1960 uint32_t rdt = pRxdc->rdt;
1961 return (pRxdc->rdh > rdt ? pRxdc->rdlen/sizeof(E1KRXDESC) : 0) + rdt - pRxdc->rdh;
1962}
1963
1964DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1965{
1966 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1967 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1968}
1969
1970DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1971{
1972 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1973}
1974
1975/**
1976 * Load receive descriptors from guest memory. The caller needs to be in Rx
1977 * critical section.
1978 *
1979 * We need two physical reads in case the tail wrapped around the end of RX
1980 * descriptor ring.
1981 *
1982 * @returns the actual number of descriptors fetched.
1983 * @param pDevIns The device instance.
1984 * @param pThis The device state structure.
1985 * @thread EMT, RX
1986 */
1987DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
1988{
1989 E1kLog3(("%s e1kRxDPrefetch: RDH=%x RDT=%x RDLEN=%x "
1990 "iRxDCurrent=%x nRxDFetched=%x\n",
1991 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pRxdc->rdlen, pThis->iRxDCurrent, pThis->nRxDFetched));
1992 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1993 unsigned nDescsAvailable = e1kGetRxLen(pRxdc) - e1kRxDInCache(pThis);
1994 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1995 unsigned nDescsTotal = pRxdc->rdlen / sizeof(E1KRXDESC);
1996 Assert(nDescsTotal != 0);
1997 if (nDescsTotal == 0)
1998 return 0;
1999 unsigned nFirstNotLoaded = (pRxdc->rdh + e1kRxDInCache(pThis)) % nDescsTotal;
2000 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2001 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2002 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2003 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2004 nFirstNotLoaded, nDescsInSingleRead));
2005 if (nDescsToFetch == 0)
2006 return 0;
2007 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2008 PDMDevHlpPCIPhysRead(pDevIns,
2009 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2010 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2011 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2012 // unsigned i, j;
2013 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2014 // {
2015 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2016 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2017 // }
2018 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2019 pThis->szPrf, nDescsInSingleRead,
2020 RDBAH, RDBAL + pRxdc->rdh * sizeof(E1KRXDESC),
2021 nFirstNotLoaded, pRxdc->rdlen, pRxdc->rdh, pRxdc->rdt));
2022 if (nDescsToFetch > nDescsInSingleRead)
2023 {
2024 PDMDevHlpPCIPhysRead(pDevIns,
2025 ((uint64_t)RDBAH << 32) + RDBAL,
2026 pFirstEmptyDesc + nDescsInSingleRead,
2027 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2028 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2029 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2030 // {
2031 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2032 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2033 // }
2034 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2035 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2036 RDBAH, RDBAL));
2037 }
2038 pThis->nRxDFetched += nDescsToFetch;
2039 return nDescsToFetch;
2040}
2041
2042# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2043/**
2044 * Dump receive descriptor to debug log.
2045 *
2046 * @param pThis The device state structure.
2047 * @param pDesc Pointer to the descriptor.
2048 * @thread E1000_RX
2049 */
2050static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
2051{
2052 RT_NOREF2(pThis, pDesc);
2053 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
2054 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
2055 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
2056 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
2057 pDesc->status.fPIF ? "PIF" : "pif",
2058 pDesc->status.fIPCS ? "IPCS" : "ipcs",
2059 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
2060 pDesc->status.fVP ? "VP" : "vp",
2061 pDesc->status.fIXSM ? "IXSM" : "ixsm",
2062 pDesc->status.fEOP ? "EOP" : "eop",
2063 pDesc->status.fDD ? "DD" : "dd",
2064 pDesc->status.fRXE ? "RXE" : "rxe",
2065 pDesc->status.fIPE ? "IPE" : "ipe",
2066 pDesc->status.fTCPE ? "TCPE" : "tcpe",
2067 pDesc->status.fCE ? "CE" : "ce",
2068 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
2069 E1K_SPEC_VLAN(pDesc->status.u16Special),
2070 E1K_SPEC_PRI(pDesc->status.u16Special)));
2071}
2072# endif /* IN_RING3 */
2073#endif /* E1K_WITH_RXD_CACHE */
2074
2075/**
2076 * Dump transmit descriptor to debug log.
2077 *
2078 * @param pThis The device state structure.
2079 * @param pDesc Pointer to descriptor union.
2080 * @param pszDir A string denoting direction of descriptor transfer
2081 * @thread E1000_TX
2082 */
2083static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
2084 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
2085{
2086 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
2087
2088 /*
2089 * Unfortunately we cannot use our format handler here, we want R0 logging
2090 * as well.
2091 */
2092 switch (e1kGetDescType(pDesc))
2093 {
2094 case E1K_DTYP_CONTEXT:
2095 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2096 pThis->szPrf, pszDir, pszDir));
2097 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2098 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2099 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2100 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2101 pDesc->context.dw2.fIDE ? " IDE":"",
2102 pDesc->context.dw2.fRS ? " RS" :"",
2103 pDesc->context.dw2.fTSE ? " TSE":"",
2104 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2105 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2106 pDesc->context.dw2.u20PAYLEN,
2107 pDesc->context.dw3.u8HDRLEN,
2108 pDesc->context.dw3.u16MSS,
2109 pDesc->context.dw3.fDD?"DD":""));
2110 break;
2111 case E1K_DTYP_DATA:
2112 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2113 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2114 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2115 pDesc->data.u64BufAddr,
2116 pDesc->data.cmd.u20DTALEN));
2117 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2118 pDesc->data.cmd.fIDE ? " IDE" :"",
2119 pDesc->data.cmd.fVLE ? " VLE" :"",
2120 pDesc->data.cmd.fRPS ? " RPS" :"",
2121 pDesc->data.cmd.fRS ? " RS" :"",
2122 pDesc->data.cmd.fTSE ? " TSE" :"",
2123 pDesc->data.cmd.fIFCS? " IFCS":"",
2124 pDesc->data.cmd.fEOP ? " EOP" :"",
2125 pDesc->data.dw3.fDD ? " DD" :"",
2126 pDesc->data.dw3.fEC ? " EC" :"",
2127 pDesc->data.dw3.fLC ? " LC" :"",
2128 pDesc->data.dw3.fTXSM? " TXSM":"",
2129 pDesc->data.dw3.fIXSM? " IXSM":"",
2130 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2131 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2132 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2133 break;
2134 case E1K_DTYP_LEGACY:
2135 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2136 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2137 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2138 pDesc->data.u64BufAddr,
2139 pDesc->legacy.cmd.u16Length));
2140 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2141 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2142 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2143 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2144 pDesc->legacy.cmd.fRS ? " RS" :"",
2145 pDesc->legacy.cmd.fIC ? " IC" :"",
2146 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2147 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2148 pDesc->legacy.dw3.fDD ? " DD" :"",
2149 pDesc->legacy.dw3.fEC ? " EC" :"",
2150 pDesc->legacy.dw3.fLC ? " LC" :"",
2151 pDesc->legacy.cmd.u8CSO,
2152 pDesc->legacy.dw3.u8CSS,
2153 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2154 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2155 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2156 break;
2157 default:
2158 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2159 pThis->szPrf, pszDir, pszDir));
2160 break;
2161 }
2162}
2163
2164/**
2165 * Raise an interrupt later.
2166 *
2167 * @param pThis The device state structure.
2168 */
2169DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2170{
2171 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2172 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2173}
2174
2175/**
2176 * Raise interrupt if not masked.
2177 *
2178 * @param pThis The device state structure.
2179 */
2180static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause)
2181{
2182 int rc = e1kCsEnter(pThis, rcBusy);
2183 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2184 return rc;
2185
2186 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2187 ICR |= u32IntCause;
2188 if (ICR & IMS)
2189 {
2190 if (pThis->fIntRaised)
2191 {
2192 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2193 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2194 pThis->szPrf, ICR & IMS));
2195 }
2196 else
2197 {
2198 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2199 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2200 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2201 {
2202 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2203 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2204 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2205 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2206 }
2207 else
2208 {
2209
2210 /* Since we are delivering the interrupt now
2211 * there is no need to do it later -- stop the timer.
2212 */
2213 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2214 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2215 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2216 /* Got at least one unmasked interrupt cause */
2217 pThis->fIntRaised = true;
2218 /* Raise(1) INTA(0) */
2219 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2220 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2221 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2222 pThis->szPrf, ICR & IMS));
2223 }
2224 }
2225 }
2226 else
2227 {
2228 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2229 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2230 pThis->szPrf, ICR, IMS));
2231 }
2232 e1kCsLeave(pThis);
2233 return VINF_SUCCESS;
2234}
2235
2236/**
2237 * Compute the physical address of the descriptor.
2238 *
2239 * @returns the physical address of the descriptor.
2240 *
2241 * @param baseHigh High-order 32 bits of descriptor table address.
2242 * @param baseLow Low-order 32 bits of descriptor table address.
2243 * @param idxDesc The descriptor index in the table.
2244 */
2245DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2246{
2247 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2248 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2249}
2250
2251#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2252/**
2253 * Advance the head pointer of the receive descriptor queue.
2254 *
2255 * @remarks RDH always points to the next available RX descriptor.
2256 *
2257 * @param pDevIns The device instance.
2258 * @param pThis The device state structure.
2259 */
2260DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2261{
2262 Assert(e1kCsRxIsOwner(pThis));
2263 //e1kCsEnter(pThis, RT_SRC_POS);
2264 if (++pRxdc->rdh * sizeof(E1KRXDESC) >= pRxdc->rdlen)
2265 pRxdc->rdh = 0;
2266 RDH = pRxdc->rdh; /* Sync the actual register and RXDC */
2267#ifdef E1K_WITH_RXD_CACHE
2268 /*
2269 * We need to fetch descriptors now as the guest may advance RDT all the way
2270 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2271 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2272 * check if the receiver is enabled. It must be, otherwise we won't get here
2273 * in the first place.
2274 *
2275 * Note that we should have moved both RDH and iRxDCurrent by now.
2276 */
2277 if (e1kRxDIsCacheEmpty(pThis))
2278 {
2279 /* Cache is empty, reset it and check if we can fetch more. */
2280 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2281 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2282 "iRxDCurrent=%x nRxDFetched=%x\n",
2283 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pThis->iRxDCurrent, pThis->nRxDFetched));
2284 e1kRxDPrefetch(pDevIns, pThis, pRxdc);
2285 }
2286#endif /* E1K_WITH_RXD_CACHE */
2287 /*
2288 * Compute current receive queue length and fire RXDMT0 interrupt
2289 * if we are low on receive buffers
2290 */
2291 uint32_t uRQueueLen = pRxdc->rdh>pRxdc->rdt ? pRxdc->rdlen/sizeof(E1KRXDESC)-pRxdc->rdh+pRxdc->rdt : pRxdc->rdt-pRxdc->rdh;
2292 /*
2293 * The minimum threshold is controlled by RDMTS bits of RCTL:
2294 * 00 = 1/2 of RDLEN
2295 * 01 = 1/4 of RDLEN
2296 * 10 = 1/8 of RDLEN
2297 * 11 = reserved
2298 */
2299 uint32_t uMinRQThreshold = pRxdc->rdlen / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2300 if (uRQueueLen <= uMinRQThreshold)
2301 {
2302 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2303 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2304 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2305 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2306 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2307 }
2308 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2309 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen));
2310 //e1kCsLeave(pThis);
2311}
2312#endif /* IN_RING3 */
2313
2314#ifdef E1K_WITH_RXD_CACHE
2315
2316# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2317
2318/**
2319 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2320 * RX ring if the cache is empty.
2321 *
2322 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2323 * go out of sync with RDH which will cause trouble when EMT checks if the
2324 * cache is empty to do pre-fetch @bugref(6217).
2325 *
2326 * @param pDevIns The device instance.
2327 * @param pThis The device state structure.
2328 * @thread RX
2329 */
2330DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2331{
2332 Assert(e1kCsRxIsOwner(pThis));
2333 /* Check the cache first. */
2334 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2335 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2336 /* Cache is empty, reset it and check if we can fetch more. */
2337 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2338 if (e1kRxDPrefetch(pDevIns, pThis, pRxdc))
2339 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2340 /* Out of Rx descriptors. */
2341 return NULL;
2342}
2343
2344
2345/**
2346 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2347 * pointer. The descriptor gets written back to the RXD ring.
2348 *
2349 * @param pDevIns The device instance.
2350 * @param pThis The device state structure.
2351 * @param pDesc The descriptor being "returned" to the RX ring.
2352 * @thread RX
2353 */
2354DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc, PE1KRXDC pRxdc)
2355{
2356 Assert(e1kCsRxIsOwner(pThis));
2357 pThis->iRxDCurrent++;
2358 // Assert(pDesc >= pThis->aRxDescriptors);
2359 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2360 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2361 // uint32_t rdh = RDH;
2362 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2363 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, pRxdc->rdh), pDesc, sizeof(E1KRXDESC));
2364 /*
2365 * We need to print the descriptor before advancing RDH as it may fetch new
2366 * descriptors into the cache.
2367 */
2368 e1kPrintRDesc(pThis, pDesc);
2369 e1kAdvanceRDH(pDevIns, pThis, pRxdc);
2370}
2371
2372/**
2373 * Store a fragment of received packet at the specifed address.
2374 *
2375 * @param pDevIns The device instance.
2376 * @param pThis The device state structure.
2377 * @param pDesc The next available RX descriptor.
2378 * @param pvBuf The fragment.
2379 * @param cb The size of the fragment.
2380 */
2381static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2382{
2383 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2384 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2385 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2386 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2387 pDesc->u16Length = (uint16_t)cb;
2388 Assert(pDesc->u16Length == cb);
2389 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2390 RT_NOREF(pThis);
2391}
2392
2393# endif /* IN_RING3 */
2394
2395#else /* !E1K_WITH_RXD_CACHE */
2396
2397/**
2398 * Store a fragment of received packet that fits into the next available RX
2399 * buffer.
2400 *
2401 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2402 *
2403 * @param pDevIns The device instance.
2404 * @param pThis The device state structure.
2405 * @param pDesc The next available RX descriptor.
2406 * @param pvBuf The fragment.
2407 * @param cb The size of the fragment.
2408 */
2409static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2410{
2411 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2412 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2413 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2414 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2415 /* Write back the descriptor */
2416 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2417 e1kPrintRDesc(pThis, pDesc);
2418 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2419 /* Advance head */
2420 e1kAdvanceRDH(pDevIns, pThis);
2421 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2422 if (pDesc->status.fEOP)
2423 {
2424 /* Complete packet has been stored -- it is time to let the guest know. */
2425#ifdef E1K_USE_RX_TIMERS
2426 if (RDTR)
2427 {
2428 /* Arm the timer to fire in RDTR usec (discard .024) */
2429 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2430 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2431 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2432 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2433 }
2434 else
2435 {
2436#endif
2437 /* 0 delay means immediate interrupt */
2438 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2439 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2440#ifdef E1K_USE_RX_TIMERS
2441 }
2442#endif
2443 }
2444 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2445}
2446
2447#endif /* !E1K_WITH_RXD_CACHE */
2448
2449/**
2450 * Returns true if it is a broadcast packet.
2451 *
2452 * @returns true if destination address indicates broadcast.
2453 * @param pvBuf The ethernet packet.
2454 */
2455DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2456{
2457 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2458 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2459}
2460
2461/**
2462 * Returns true if it is a multicast packet.
2463 *
2464 * @remarks returns true for broadcast packets as well.
2465 * @returns true if destination address indicates multicast.
2466 * @param pvBuf The ethernet packet.
2467 */
2468DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2469{
2470 return (*(char*)pvBuf) & 1;
2471}
2472
2473#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2474/**
2475 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2476 *
2477 * @remarks We emulate checksum offloading for major packets types only.
2478 *
2479 * @returns VBox status code.
2480 * @param pThis The device state structure.
2481 * @param pFrame The available data.
2482 * @param cb Number of bytes available in the buffer.
2483 * @param status Bit fields containing status info.
2484 */
2485static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2486{
2487 /** @todo
2488 * It is not safe to bypass checksum verification for packets coming
2489 * from real wire. We currently unable to tell where packets are
2490 * coming from so we tell the driver to ignore our checksum flags
2491 * and do verification in software.
2492 */
2493# if 0
2494 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2495
2496 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2497
2498 switch (uEtherType)
2499 {
2500 case 0x800: /* IPv4 */
2501 {
2502 pStatus->fIXSM = false;
2503 pStatus->fIPCS = true;
2504 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2505 /* TCP/UDP checksum offloading works with TCP and UDP only */
2506 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2507 break;
2508 }
2509 case 0x86DD: /* IPv6 */
2510 pStatus->fIXSM = false;
2511 pStatus->fIPCS = false;
2512 pStatus->fTCPCS = true;
2513 break;
2514 default: /* ARP, VLAN, etc. */
2515 pStatus->fIXSM = true;
2516 break;
2517 }
2518# else
2519 pStatus->fIXSM = true;
2520 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2521# endif
2522 return VINF_SUCCESS;
2523}
2524#endif /* IN_RING3 */
2525
2526/**
2527 * Pad and store received packet.
2528 *
2529 * @remarks Make sure that the packet appears to upper layer as one coming
2530 * from real Ethernet: pad it and insert FCS.
2531 *
2532 * @returns VBox status code.
2533 * @param pDevIns The device instance.
2534 * @param pThis The device state structure.
2535 * @param pvBuf The available data.
2536 * @param cb Number of bytes available in the buffer.
2537 * @param status Bit fields containing status info.
2538 */
2539static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2540{
2541#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2542 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2543 uint8_t *ptr = rxPacket;
2544# ifdef E1K_WITH_RXD_CACHE
2545 E1KRXDC rxdc;
2546# endif /* E1K_WITH_RXD_CACHE */
2547
2548 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2549 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2550 return rc;
2551# ifdef E1K_WITH_RXD_CACHE
2552 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2553 {
2554 e1kCsRxLeave(pThis);
2555 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2556 return VINF_SUCCESS;
2557 }
2558# endif /* E1K_WITH_RXD_CACHE */
2559
2560 if (cb > 70) /* unqualified guess */
2561 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2562
2563 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2564 Assert(cb > 16);
2565 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2566 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2567 if (status.fVP)
2568 {
2569 /* VLAN packet -- strip VLAN tag in VLAN mode */
2570 if ((CTRL & CTRL_VME) && cb > 16)
2571 {
2572 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2573 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2574 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2575 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2576 cb -= 4;
2577 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2578 pThis->szPrf, status.u16Special, cb));
2579 }
2580 else
2581 {
2582 status.fVP = false; /* Set VP only if we stripped the tag */
2583 memcpy(rxPacket, pvBuf, cb);
2584 }
2585 }
2586 else
2587 memcpy(rxPacket, pvBuf, cb);
2588 /* Pad short packets */
2589 if (cb < 60)
2590 {
2591 memset(rxPacket + cb, 0, 60 - cb);
2592 cb = 60;
2593 }
2594 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2595 {
2596 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2597 /*
2598 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2599 * is ignored by most of drivers we may as well save us the trouble
2600 * of calculating it (see EthernetCRC CFGM parameter).
2601 */
2602 if (pThis->fEthernetCRC)
2603 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2604 cb += sizeof(uint32_t);
2605 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2606 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2607 }
2608 /* Compute checksum of complete packet */
2609 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2610 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2611 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2612
2613 /* Update stats */
2614 E1K_INC_CNT32(GPRC);
2615 if (e1kIsBroadcast(pvBuf))
2616 E1K_INC_CNT32(BPRC);
2617 else if (e1kIsMulticast(pvBuf))
2618 E1K_INC_CNT32(MPRC);
2619 /* Update octet receive counter */
2620 E1K_ADD_CNT64(GORCL, GORCH, cb);
2621 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2622 if (cb == 64)
2623 E1K_INC_CNT32(PRC64);
2624 else if (cb < 128)
2625 E1K_INC_CNT32(PRC127);
2626 else if (cb < 256)
2627 E1K_INC_CNT32(PRC255);
2628 else if (cb < 512)
2629 E1K_INC_CNT32(PRC511);
2630 else if (cb < 1024)
2631 E1K_INC_CNT32(PRC1023);
2632 else
2633 E1K_INC_CNT32(PRC1522);
2634
2635 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2636
2637# ifdef E1K_WITH_RXD_CACHE
2638 while (cb > 0)
2639 {
2640 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis, &rxdc);
2641
2642 if (pDesc == NULL)
2643 {
2644 E1kLog(("%s Out of receive buffers, dropping the packet "
2645 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2646 pThis->szPrf, cb, e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt));
2647 break;
2648 }
2649# else /* !E1K_WITH_RXD_CACHE */
2650 if (RDH == RDT)
2651 {
2652 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2653 pThis->szPrf));
2654 }
2655 /* Store the packet to receive buffers */
2656 while (RDH != RDT)
2657 {
2658 /* Load the descriptor pointed by head */
2659 E1KRXDESC desc, *pDesc = &desc;
2660 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2661# endif /* !E1K_WITH_RXD_CACHE */
2662 if (pDesc->u64BufAddr)
2663 {
2664 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2665
2666 /* Update descriptor */
2667 pDesc->status = status;
2668 pDesc->u16Checksum = checksum;
2669 pDesc->status.fDD = true;
2670
2671 /*
2672 * We need to leave Rx critical section here or we risk deadlocking
2673 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2674 * page or has an access handler associated with it.
2675 * Note that it is safe to leave the critical section here since
2676 * e1kRegWriteRDT() never modifies RDH. It never touches already
2677 * fetched RxD cache entries either.
2678 */
2679 if (cb > u16RxBufferSize)
2680 {
2681 pDesc->status.fEOP = false;
2682 e1kCsRxLeave(pThis);
2683 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2684 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2685 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2686 return rc;
2687# ifdef E1K_WITH_RXD_CACHE
2688 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2689 {
2690 e1kCsRxLeave(pThis);
2691 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2692 return VINF_SUCCESS;
2693 }
2694# endif /* E1K_WITH_RXD_CACHE */
2695 ptr += u16RxBufferSize;
2696 cb -= u16RxBufferSize;
2697 }
2698 else
2699 {
2700 pDesc->status.fEOP = true;
2701 e1kCsRxLeave(pThis);
2702 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2703# ifdef E1K_WITH_RXD_CACHE
2704 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2705 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2706 return rc;
2707 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2708 {
2709 e1kCsRxLeave(pThis);
2710 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2711 return VINF_SUCCESS;
2712 }
2713 cb = 0;
2714# else /* !E1K_WITH_RXD_CACHE */
2715 pThis->led.Actual.s.fReading = 0;
2716 return VINF_SUCCESS;
2717# endif /* !E1K_WITH_RXD_CACHE */
2718 }
2719 /*
2720 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2721 * is not defined.
2722 */
2723 }
2724# ifdef E1K_WITH_RXD_CACHE
2725 /* Write back the descriptor. */
2726 pDesc->status.fDD = true;
2727 e1kRxDPut(pDevIns, pThis, pDesc, &rxdc);
2728# else /* !E1K_WITH_RXD_CACHE */
2729 else
2730 {
2731 /* Write back the descriptor. */
2732 pDesc->status.fDD = true;
2733 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2734 e1kAdvanceRDH(pDevIns, pThis);
2735 }
2736# endif /* !E1K_WITH_RXD_CACHE */
2737 }
2738
2739 if (cb > 0)
2740 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2741
2742 pThis->led.Actual.s.fReading = 0;
2743
2744 e1kCsRxLeave(pThis);
2745# ifdef E1K_WITH_RXD_CACHE
2746 /* Complete packet has been stored -- it is time to let the guest know. */
2747# ifdef E1K_USE_RX_TIMERS
2748 if (RDTR)
2749 {
2750 /* Arm the timer to fire in RDTR usec (discard .024) */
2751 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2752 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2753 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2754 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2755 }
2756 else
2757 {
2758# endif /* E1K_USE_RX_TIMERS */
2759 /* 0 delay means immediate interrupt */
2760 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2761 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2762# ifdef E1K_USE_RX_TIMERS
2763 }
2764# endif /* E1K_USE_RX_TIMERS */
2765# endif /* E1K_WITH_RXD_CACHE */
2766
2767 return VINF_SUCCESS;
2768#else /* !IN_RING3 */
2769 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2770 return VERR_INTERNAL_ERROR_2;
2771#endif /* !IN_RING3 */
2772}
2773
2774
2775#ifdef IN_RING3
2776/**
2777 * Bring the link up after the configured delay, 5 seconds by default.
2778 *
2779 * @param pDevIns The device instance.
2780 * @param pThis The device state structure.
2781 * @thread any
2782 */
2783DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2784{
2785 E1kLog(("%s Will bring up the link in %d seconds...\n",
2786 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2787 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2788}
2789
2790/**
2791 * Bring up the link immediately.
2792 *
2793 * @param pDevIns The device instance.
2794 * @param pThis The device state structure.
2795 * @param pThisCC The current context instance data.
2796 */
2797DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2798{
2799 E1kLog(("%s Link is up\n", pThis->szPrf));
2800 STATUS |= STATUS_LU;
2801 Phy::setLinkStatus(&pThis->phy, true);
2802 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2803 if (pThisCC->pDrvR3)
2804 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2805 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2806 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2807}
2808
2809/**
2810 * Bring down the link immediately.
2811 *
2812 * @param pDevIns The device instance.
2813 * @param pThis The device state structure.
2814 * @param pThisCC The current context instance data.
2815 */
2816DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2817{
2818 E1kLog(("%s Link is down\n", pThis->szPrf));
2819 STATUS &= ~STATUS_LU;
2820#ifdef E1K_LSC_ON_RESET
2821 Phy::setLinkStatus(&pThis->phy, false);
2822#endif /* E1K_LSC_ON_RESET */
2823 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2824 if (pThisCC->pDrvR3)
2825 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2826}
2827
2828/**
2829 * Bring down the link temporarily.
2830 *
2831 * @param pDevIns The device instance.
2832 * @param pThis The device state structure.
2833 * @param pThisCC The current context instance data.
2834 */
2835DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2836{
2837 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2838 STATUS &= ~STATUS_LU;
2839 Phy::setLinkStatus(&pThis->phy, false);
2840 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2841 /*
2842 * Notifying the associated driver that the link went down (even temporarily)
2843 * seems to be the right thing, but it was not done before. This may cause
2844 * a regression if the driver does not expect the link to go down as a result
2845 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2846 * of code notified the driver that the link was up! See @bugref{7057}.
2847 */
2848 if (pThisCC->pDrvR3)
2849 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2850 e1kBringLinkUpDelayed(pDevIns, pThis);
2851}
2852#endif /* IN_RING3 */
2853
2854#if 0 /* unused */
2855/**
2856 * Read handler for Device Status register.
2857 *
2858 * Get the link status from PHY.
2859 *
2860 * @returns VBox status code.
2861 *
2862 * @param pThis The device state structure.
2863 * @param offset Register offset in memory-mapped frame.
2864 * @param index Register index in register array.
2865 * @param mask Used to implement partial reads (8 and 16-bit).
2866 */
2867static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2868{
2869 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2870 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2871 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2872 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2873 {
2874 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2875 if (Phy::readMDIO(&pThis->phy))
2876 *pu32Value = CTRL | CTRL_MDIO;
2877 else
2878 *pu32Value = CTRL & ~CTRL_MDIO;
2879 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2880 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2881 }
2882 else
2883 {
2884 /* MDIO pin is used for output, ignore it */
2885 *pu32Value = CTRL;
2886 }
2887 return VINF_SUCCESS;
2888}
2889#endif /* unused */
2890
2891/**
2892 * A helper function to detect the link state to the other side of "the wire".
2893 *
2894 * When deciding to bring up the link we need to take into account both if the
2895 * cable is connected and if our device is actually connected to the outside
2896 * world. If no driver is attached we won't be able to allocate TX buffers,
2897 * which will prevent us from TX descriptor processing, which will result in
2898 * "TX unit hang" in the guest.
2899 *
2900 * @returns true if the device is connected to something.
2901 *
2902 * @param pDevIns The device instance.
2903 */
2904DECLINLINE(bool) e1kIsConnected(PPDMDEVINS pDevIns)
2905{
2906 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2907 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2908 return pThis->fCableConnected && pThisCC->CTX_SUFF(pDrv);
2909}
2910
2911/**
2912 * A callback used by PHY to indicate that the link needs to be updated due to
2913 * reset of PHY.
2914 *
2915 * @param pDevIns The device instance.
2916 * @thread any
2917 */
2918void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2919{
2920 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2921
2922 /* Make sure we have cable connected and MAC can talk to PHY */
2923 if (e1kIsConnected(pDevIns) && (CTRL & CTRL_SLU))
2924 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2925}
2926
2927/**
2928 * Write handler for Device Control register.
2929 *
2930 * Handles reset.
2931 *
2932 * @param pThis The device state structure.
2933 * @param offset Register offset in memory-mapped frame.
2934 * @param index Register index in register array.
2935 * @param value The value to store.
2936 * @param mask Used to implement partial writes (8 and 16-bit).
2937 * @thread EMT
2938 */
2939static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2940{
2941 int rc = VINF_SUCCESS;
2942
2943 if (value & CTRL_RESET)
2944 { /* RST */
2945#ifndef IN_RING3
2946 return VINF_IOM_R3_MMIO_WRITE;
2947#else
2948 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2949#endif
2950 }
2951 else
2952 {
2953#ifdef E1K_LSC_ON_SLU
2954 /*
2955 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2956 * the link is down and the cable is connected, and if they are we
2957 * bring the link up, see @bugref{8624}.
2958 */
2959 if ( (value & CTRL_SLU)
2960 && !(CTRL & CTRL_SLU)
2961 && pThis->fCableConnected
2962 && !(STATUS & STATUS_LU))
2963 {
2964 /* It should take about 2 seconds for the link to come up */
2965 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2966 }
2967#else /* !E1K_LSC_ON_SLU */
2968 if ( (value & CTRL_SLU)
2969 && !(CTRL & CTRL_SLU)
2970 && e1kIsConnected(pDevIns)
2971 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2972 {
2973 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2974 STATUS |= STATUS_LU;
2975 }
2976#endif /* !E1K_LSC_ON_SLU */
2977 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2978 {
2979 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2980 }
2981 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2982 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2983 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2984 if (value & CTRL_MDC)
2985 {
2986 if (value & CTRL_MDIO_DIR)
2987 {
2988 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2989 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2990 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2991 }
2992 else
2993 {
2994 if (Phy::readMDIO(&pThis->phy))
2995 value |= CTRL_MDIO;
2996 else
2997 value &= ~CTRL_MDIO;
2998 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2999 }
3000 }
3001 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3002 }
3003
3004 return rc;
3005}
3006
3007/**
3008 * Write handler for EEPROM/Flash Control/Data register.
3009 *
3010 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
3011 *
3012 * @param pThis The device state structure.
3013 * @param offset Register offset in memory-mapped frame.
3014 * @param index Register index in register array.
3015 * @param value The value to store.
3016 * @param mask Used to implement partial writes (8 and 16-bit).
3017 * @thread EMT
3018 */
3019static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3020{
3021 RT_NOREF(pDevIns, offset, index);
3022#ifdef IN_RING3
3023 /* So far we are concerned with lower byte only */
3024 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3025 {
3026 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
3027 /* Note: 82543GC does not need to request EEPROM access */
3028 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
3029 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3030 pThisCC->eeprom.write(value & EECD_EE_WIRES);
3031 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
3032 }
3033 if (value & EECD_EE_REQ)
3034 EECD |= EECD_EE_REQ|EECD_EE_GNT;
3035 else
3036 EECD &= ~EECD_EE_GNT;
3037 //e1kRegWriteDefault(pThis, offset, index, value );
3038
3039 return VINF_SUCCESS;
3040#else /* !IN_RING3 */
3041 RT_NOREF(pThis, value);
3042 return VINF_IOM_R3_MMIO_WRITE;
3043#endif /* !IN_RING3 */
3044}
3045
3046/**
3047 * Read handler for EEPROM/Flash Control/Data register.
3048 *
3049 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
3050 *
3051 * @returns VBox status code.
3052 *
3053 * @param pThis The device state structure.
3054 * @param offset Register offset in memory-mapped frame.
3055 * @param index Register index in register array.
3056 * @param mask Used to implement partial reads (8 and 16-bit).
3057 * @thread EMT
3058 */
3059static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3060{
3061#ifdef IN_RING3
3062 uint32_t value = 0; /* Get rid of false positive in parfait. */
3063 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3064 if (RT_SUCCESS(rc))
3065 {
3066 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3067 {
3068 /* Note: 82543GC does not need to request EEPROM access */
3069 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
3070 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3071 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3072 value |= pThisCC->eeprom.read();
3073 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3074 }
3075 *pu32Value = value;
3076 }
3077
3078 return rc;
3079#else /* !IN_RING3 */
3080 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
3081 return VINF_IOM_R3_MMIO_READ;
3082#endif /* !IN_RING3 */
3083}
3084
3085/**
3086 * Write handler for EEPROM Read register.
3087 *
3088 * Handles EEPROM word access requests, reads EEPROM and stores the result
3089 * into DATA field.
3090 *
3091 * @param pThis The device state structure.
3092 * @param offset Register offset in memory-mapped frame.
3093 * @param index Register index in register array.
3094 * @param value The value to store.
3095 * @param mask Used to implement partial writes (8 and 16-bit).
3096 * @thread EMT
3097 */
3098static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3099{
3100#ifdef IN_RING3
3101 /* Make use of 'writable' and 'readable' masks. */
3102 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3103 /* DONE and DATA are set only if read was triggered by START. */
3104 if (value & EERD_START)
3105 {
3106 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3107 uint16_t tmp;
3108 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3109 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
3110 SET_BITS(EERD, DATA, tmp);
3111 EERD |= EERD_DONE;
3112 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3113 }
3114
3115 return VINF_SUCCESS;
3116#else /* !IN_RING3 */
3117 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
3118 return VINF_IOM_R3_MMIO_WRITE;
3119#endif /* !IN_RING3 */
3120}
3121
3122
3123/**
3124 * Write handler for MDI Control register.
3125 *
3126 * Handles PHY read/write requests; forwards requests to internal PHY device.
3127 *
3128 * @param pThis The device state structure.
3129 * @param offset Register offset in memory-mapped frame.
3130 * @param index Register index in register array.
3131 * @param value The value to store.
3132 * @param mask Used to implement partial writes (8 and 16-bit).
3133 * @thread EMT
3134 */
3135static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3136{
3137 if (value & MDIC_INT_EN)
3138 {
3139 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
3140 pThis->szPrf));
3141 }
3142 else if (value & MDIC_READY)
3143 {
3144 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3145 pThis->szPrf));
3146 }
3147 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3148 {
3149 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3150 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3151 /*
3152 * Some drivers scan the MDIO bus for a PHY. We can work with these
3153 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3154 * at the requested address, see @bugref{7346}.
3155 */
3156 MDIC = MDIC_READY | MDIC_ERROR;
3157 }
3158 else
3159 {
3160 /* Store the value */
3161 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3162 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3163 /* Forward op to PHY */
3164 if (value & MDIC_OP_READ)
3165 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3166 else
3167 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3168 /* Let software know that we are done */
3169 MDIC |= MDIC_READY;
3170 }
3171
3172 return VINF_SUCCESS;
3173}
3174
3175/**
3176 * Write handler for Interrupt Cause Read register.
3177 *
3178 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3179 *
3180 * @param pThis The device state structure.
3181 * @param offset Register offset in memory-mapped frame.
3182 * @param index Register index in register array.
3183 * @param value The value to store.
3184 * @param mask Used to implement partial writes (8 and 16-bit).
3185 * @thread EMT
3186 */
3187static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3188{
3189 ICR &= ~value;
3190
3191 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3192 return VINF_SUCCESS;
3193}
3194
3195/**
3196 * Read handler for Interrupt Cause Read register.
3197 *
3198 * Reading this register acknowledges all interrupts.
3199 *
3200 * @returns VBox status code.
3201 *
3202 * @param pThis The device state structure.
3203 * @param offset Register offset in memory-mapped frame.
3204 * @param index Register index in register array.
3205 * @param mask Not used.
3206 * @thread EMT
3207 */
3208static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3209{
3210 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3211 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3212 return rc;
3213
3214 uint32_t value = 0;
3215 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3216 if (RT_SUCCESS(rc))
3217 {
3218 if (value)
3219 {
3220 if (!pThis->fIntRaised)
3221 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3222 /*
3223 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3224 * with disabled interrupts.
3225 */
3226 //if (IMS)
3227 if (1)
3228 {
3229 /*
3230 * Interrupts were enabled -- we are supposedly at the very
3231 * beginning of interrupt handler
3232 */
3233 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3234 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3235 /* Clear all pending interrupts */
3236 ICR = 0;
3237 pThis->fIntRaised = false;
3238 /* Lower(0) INTA(0) */
3239 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3240
3241 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3242 if (pThis->fIntMaskUsed)
3243 pThis->fDelayInts = true;
3244 }
3245 else
3246 {
3247 /*
3248 * Interrupts are disabled -- in windows guests ICR read is done
3249 * just before re-enabling interrupts
3250 */
3251 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3252 }
3253 }
3254 *pu32Value = value;
3255 }
3256 e1kCsLeave(pThis);
3257
3258 return rc;
3259}
3260
3261/**
3262 * Read handler for Interrupt Cause Set register.
3263 *
3264 * VxWorks driver uses this undocumented feature of real H/W to read ICR without acknowledging interrupts.
3265 *
3266 * @returns VBox status code.
3267 *
3268 * @param pThis The device state structure.
3269 * @param offset Register offset in memory-mapped frame.
3270 * @param index Register index in register array.
3271 * @param pu32Value Where to store the value of the register.
3272 * @thread EMT
3273 */
3274static int e1kRegReadICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3275{
3276 RT_NOREF_PV(index);
3277 return e1kRegReadDefault(pDevIns, pThis, offset, ICR_IDX, pu32Value);
3278}
3279
3280/**
3281 * Write handler for Interrupt Cause Set register.
3282 *
3283 * Bits corresponding to 1s in 'value' will be set in ICR register.
3284 *
3285 * @param pThis The device state structure.
3286 * @param offset Register offset in memory-mapped frame.
3287 * @param index Register index in register array.
3288 * @param value The value to store.
3289 * @param mask Used to implement partial writes (8 and 16-bit).
3290 * @thread EMT
3291 */
3292static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3293{
3294 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3295 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3296 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3297}
3298
3299/**
3300 * Write handler for Interrupt Mask Set register.
3301 *
3302 * Will trigger pending interrupts.
3303 *
3304 * @param pThis The device state structure.
3305 * @param offset Register offset in memory-mapped frame.
3306 * @param index Register index in register array.
3307 * @param value The value to store.
3308 * @param mask Used to implement partial writes (8 and 16-bit).
3309 * @thread EMT
3310 */
3311static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3312{
3313 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3314
3315 IMS |= value;
3316 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3317 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3318 /*
3319 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3320 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3321 */
3322 if ((ICR & IMS) && !pThis->fLocked)
3323 {
3324 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3325 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3326 }
3327
3328 return VINF_SUCCESS;
3329}
3330
3331/**
3332 * Write handler for Interrupt Mask Clear register.
3333 *
3334 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3335 *
3336 * @param pThis The device state structure.
3337 * @param offset Register offset in memory-mapped frame.
3338 * @param index Register index in register array.
3339 * @param value The value to store.
3340 * @param mask Used to implement partial writes (8 and 16-bit).
3341 * @thread EMT
3342 */
3343static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3344{
3345 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3346
3347 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3348 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3349 return rc;
3350 if (pThis->fIntRaised)
3351 {
3352 /*
3353 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3354 * Windows to freeze since it may receive an interrupt while still in the very beginning
3355 * of interrupt handler.
3356 */
3357 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3358 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3359 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3360 /* Lower(0) INTA(0) */
3361 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3362 pThis->fIntRaised = false;
3363 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3364 }
3365 IMS &= ~value;
3366 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3367 e1kCsLeave(pThis);
3368
3369 return VINF_SUCCESS;
3370}
3371
3372/**
3373 * Write handler for Receive Control register.
3374 *
3375 * @param pThis The device state structure.
3376 * @param offset Register offset in memory-mapped frame.
3377 * @param index Register index in register array.
3378 * @param value The value to store.
3379 * @param mask Used to implement partial writes (8 and 16-bit).
3380 * @thread EMT
3381 */
3382static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3383{
3384 /* Update promiscuous mode */
3385 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3386 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3387 {
3388 /* Promiscuity has changed, pass the knowledge on. */
3389#ifndef IN_RING3
3390 return VINF_IOM_R3_MMIO_WRITE;
3391#else
3392 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3393 if (pThisCC->pDrvR3)
3394 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3395#endif
3396 }
3397
3398 /* Adjust receive buffer size */
3399 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3400 if (value & RCTL_BSEX)
3401 cbRxBuf *= 16;
3402 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3403 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3404 if (cbRxBuf != pThis->u16RxBSize)
3405 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3406 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3407 Assert(cbRxBuf < 65536);
3408 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3409
3410 /* Update the register */
3411 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3412}
3413
3414/**
3415 * Write handler for Packet Buffer Allocation register.
3416 *
3417 * TXA = 64 - RXA.
3418 *
3419 * @param pThis The device state structure.
3420 * @param offset Register offset in memory-mapped frame.
3421 * @param index Register index in register array.
3422 * @param value The value to store.
3423 * @param mask Used to implement partial writes (8 and 16-bit).
3424 * @thread EMT
3425 */
3426static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3427{
3428 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3429 PBA_st->txa = 64 - PBA_st->rxa;
3430
3431 return VINF_SUCCESS;
3432}
3433
3434/**
3435 * Write handler for Receive Descriptor Tail register.
3436 *
3437 * @remarks Write into RDT forces switch to HC and signal to
3438 * e1kR3NetworkDown_WaitReceiveAvail().
3439 *
3440 * @returns VBox status code.
3441 *
3442 * @param pThis The device state structure.
3443 * @param offset Register offset in memory-mapped frame.
3444 * @param index Register index in register array.
3445 * @param value The value to store.
3446 * @param mask Used to implement partial writes (8 and 16-bit).
3447 * @thread EMT
3448 */
3449static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3450{
3451#ifndef IN_RING3
3452 /* XXX */
3453// return VINF_IOM_R3_MMIO_WRITE;
3454#endif
3455 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3456 if (RT_LIKELY(rc == VINF_SUCCESS))
3457 {
3458 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3459#ifndef E1K_WITH_RXD_CACHE
3460 /*
3461 * Some drivers advance RDT too far, so that it equals RDH. This
3462 * somehow manages to work with real hardware but not with this
3463 * emulated device. We can work with these drivers if we just
3464 * write 1 less when we see a driver writing RDT equal to RDH,
3465 * see @bugref{7346}.
3466 */
3467 if (value == RDH)
3468 {
3469 if (RDH == 0)
3470 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3471 else
3472 value = RDH - 1;
3473 }
3474#endif /* !E1K_WITH_RXD_CACHE */
3475 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3476#ifdef E1K_WITH_RXD_CACHE
3477 E1KRXDC rxdc;
3478 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kRegWriteRDT")))
3479 {
3480 e1kCsRxLeave(pThis);
3481 E1kLog(("%s e1kRegWriteRDT: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
3482 return VINF_SUCCESS;
3483 }
3484 /*
3485 * We need to fetch descriptors now as RDT may go whole circle
3486 * before we attempt to store a received packet. For example,
3487 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3488 * size being only 8 descriptors! Note that we fetch descriptors
3489 * only when the cache is empty to reduce the number of memory reads
3490 * in case of frequent RDT writes. Don't fetch anything when the
3491 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3492 * messed up state.
3493 * Note that despite the cache may seem empty, meaning that there are
3494 * no more available descriptors in it, it may still be used by RX
3495 * thread which has not yet written the last descriptor back but has
3496 * temporarily released the RX lock in order to write the packet body
3497 * to descriptor's buffer. At this point we still going to do prefetch
3498 * but it won't actually fetch anything if there are no unused slots in
3499 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3500 * reset the cache here even if it appears empty. It will be reset at
3501 * a later point in e1kRxDGet().
3502 */
3503 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3504 e1kRxDPrefetch(pDevIns, pThis, &rxdc);
3505#endif /* E1K_WITH_RXD_CACHE */
3506 e1kCsRxLeave(pThis);
3507 if (RT_SUCCESS(rc))
3508 {
3509 /* Signal that we have more receive descriptors available. */
3510 e1kWakeupReceive(pDevIns, pThis);
3511 }
3512 }
3513 return rc;
3514}
3515
3516/**
3517 * Write handler for Receive Delay Timer register.
3518 *
3519 * @param pThis The device state structure.
3520 * @param offset Register offset in memory-mapped frame.
3521 * @param index Register index in register array.
3522 * @param value The value to store.
3523 * @param mask Used to implement partial writes (8 and 16-bit).
3524 * @thread EMT
3525 */
3526static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3527{
3528 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3529 if (value & RDTR_FPD)
3530 {
3531 /* Flush requested, cancel both timers and raise interrupt */
3532#ifdef E1K_USE_RX_TIMERS
3533 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3534 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3535#endif
3536 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3537 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3538 }
3539
3540 return VINF_SUCCESS;
3541}
3542
3543DECLINLINE(uint32_t) e1kGetTxLen(PE1KTXDC pTxdc)
3544{
3545 /**
3546 * Make sure TDT won't change during computation. EMT may modify TDT at
3547 * any moment.
3548 */
3549 uint32_t tdt = pTxdc->tdt;
3550 return (pTxdc->tdh > tdt ? pTxdc->tdlen/sizeof(E1KTXDESC) : 0) + tdt - pTxdc->tdh;
3551}
3552
3553#ifdef IN_RING3
3554
3555# ifdef E1K_TX_DELAY
3556/**
3557 * @callback_method_impl{FNTMTIMERDEV, Transmit Delay Timer handler.}
3558 */
3559static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3560{
3561 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3562 Assert(PDMCritSectIsOwner(&pThis->csTx));
3563 RT_NOREF(hTimer);
3564
3565 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3566# ifdef E1K_INT_STATS
3567 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3568 if (u64Elapsed > pThis->uStatMaxTxDelay)
3569 pThis->uStatMaxTxDelay = u64Elapsed;
3570# endif
3571 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3572 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3573}
3574# endif /* E1K_TX_DELAY */
3575
3576//# ifdef E1K_USE_TX_TIMERS
3577
3578/**
3579 * @callback_method_impl{FNTMTIMERDEV, Transmit Interrupt Delay Timer handler.}
3580 */
3581static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3582{
3583 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3584 Assert(hTimer == pThis->hTIDTimer); RT_NOREF(hTimer);
3585
3586 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3587 /* Cancel absolute delay timer as we have already got attention */
3588# ifndef E1K_NO_TAD
3589 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3590# endif
3591 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3592}
3593
3594/**
3595 * @callback_method_impl{FNTMTIMERDEV, Transmit Absolute Delay Timer handler.}
3596 */
3597static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3598{
3599 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3600 Assert(hTimer == pThis->hTADTimer); RT_NOREF(hTimer);
3601
3602 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3603 /* Cancel interrupt delay timer as we have already got attention */
3604 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3605 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3606}
3607
3608//# endif /* E1K_USE_TX_TIMERS */
3609# ifdef E1K_USE_RX_TIMERS
3610
3611/**
3612 * @callback_method_impl{FNTMTIMERDEV, Receive Interrupt Delay Timer handler.}
3613 */
3614static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3615{
3616 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3617 Assert(hTimer == pThis->hRIDTimer); RT_NOREF(hTimer);
3618
3619 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3620 /* Cancel absolute delay timer as we have already got attention */
3621 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3622 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3623}
3624
3625/**
3626 * @callback_method_impl{FNTMTIMERDEV, Receive Absolute Delay Timer handler.}
3627 */
3628static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3629{
3630 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3631 Assert(hTimer == pThis->hRADTimer); RT_NOREF(hTimer);
3632
3633 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3634 /* Cancel interrupt delay timer as we have already got attention */
3635 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3636 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3637}
3638
3639# endif /* E1K_USE_RX_TIMERS */
3640
3641/**
3642 * @callback_method_impl{FNTMTIMERDEV, Late Interrupt Timer handler.}
3643 */
3644static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3645{
3646 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3647 Assert(hTimer == pThis->hIntTimer); RT_NOREF(hTimer);
3648 RT_NOREF(hTimer);
3649
3650 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3651 STAM_COUNTER_INC(&pThis->StatLateInts);
3652 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3653# if 0
3654 if (pThis->iStatIntLost > -100)
3655 pThis->iStatIntLost--;
3656# endif
3657 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3658 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3659}
3660
3661/**
3662 * @callback_method_impl{FNTMTIMERDEV, Link Up Timer handler.}
3663 */
3664static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3665{
3666 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3667 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3668 Assert(hTimer == pThis->hLUTimer); RT_NOREF(hTimer);
3669
3670 /*
3671 * This can happen if we set the link status to down when the Link up timer was
3672 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3673 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3674 * on reset even if the cable is unplugged (see @bugref{8942}).
3675 */
3676 if (e1kIsConnected(pDevIns))
3677 {
3678 /* 82543GC does not have an internal PHY */
3679 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3680 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3681 }
3682# ifdef E1K_LSC_ON_RESET
3683 else if (pThis->eChip == E1K_CHIP_82543GC)
3684 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3685# endif /* E1K_LSC_ON_RESET */
3686}
3687
3688#endif /* IN_RING3 */
3689
3690/**
3691 * Sets up the GSO context according to the TSE new context descriptor.
3692 *
3693 * @param pGso The GSO context to setup.
3694 * @param pCtx The context descriptor.
3695 */
3696DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3697{
3698 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3699
3700 /*
3701 * See if the context descriptor describes something that could be TCP or
3702 * UDP over IPv[46].
3703 */
3704 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3705 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3706 {
3707 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3708 return;
3709 }
3710 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3711 {
3712 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3713 return;
3714 }
3715 if (RT_UNLIKELY( pCtx->dw2.fTCP
3716 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3717 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3718 {
3719 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3720 return;
3721 }
3722
3723 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3724 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3725 {
3726 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3727 return;
3728 }
3729
3730 /* IPv4 checksum offset. */
3731 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3732 {
3733 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3734 return;
3735 }
3736
3737 /* TCP/UDP checksum offsets. */
3738 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3739 != ( pCtx->dw2.fTCP
3740 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3741 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3742 {
3743 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3744 return;
3745 }
3746
3747 /*
3748 * Because of internal networking using a 16-bit size field for GSO context
3749 * plus frame, we have to make sure we don't exceed this.
3750 */
3751 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3752 {
3753 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3754 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3755 return;
3756 }
3757
3758 /*
3759 * We're good for now - we'll do more checks when seeing the data.
3760 * So, figure the type of offloading and setup the context.
3761 */
3762 if (pCtx->dw2.fIP)
3763 {
3764 if (pCtx->dw2.fTCP)
3765 {
3766 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3767 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3768 }
3769 else
3770 {
3771 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3772 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3773 }
3774 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3775 * this yet it seems)... */
3776 }
3777 else
3778 {
3779 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3780 if (pCtx->dw2.fTCP)
3781 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3782 else
3783 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3784 }
3785 pGso->offHdr1 = pCtx->ip.u8CSS;
3786 pGso->offHdr2 = pCtx->tu.u8CSS;
3787 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3788 pGso->cbMaxSeg = pCtx->dw3.u16MSS + (pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP ? pGso->offHdr2 : 0);
3789 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3790 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3791 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3792}
3793
3794/**
3795 * Checks if we can use GSO processing for the current TSE frame.
3796 *
3797 * @param pThis The device state structure.
3798 * @param pGso The GSO context.
3799 * @param pData The first data descriptor of the frame.
3800 * @param pCtx The TSO context descriptor.
3801 */
3802DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3803{
3804 if (!pData->cmd.fTSE)
3805 {
3806 E1kLog2(("e1kCanDoGso: !TSE\n"));
3807 return false;
3808 }
3809 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3810 {
3811 E1kLog(("e1kCanDoGso: VLE\n"));
3812 return false;
3813 }
3814 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3815 {
3816 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3817 return false;
3818 }
3819
3820 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3821 {
3822 case PDMNETWORKGSOTYPE_IPV4_TCP:
3823 case PDMNETWORKGSOTYPE_IPV4_UDP:
3824 if (!pData->dw3.fIXSM)
3825 {
3826 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3827 return false;
3828 }
3829 if (!pData->dw3.fTXSM)
3830 {
3831 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3832 return false;
3833 }
3834 /** @todo what more check should we perform here? Ethernet frame type? */
3835 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3836 return true;
3837
3838 case PDMNETWORKGSOTYPE_IPV6_TCP:
3839 case PDMNETWORKGSOTYPE_IPV6_UDP:
3840 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3841 {
3842 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3843 return false;
3844 }
3845 if (!pData->dw3.fTXSM)
3846 {
3847 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3848 return false;
3849 }
3850 /** @todo what more check should we perform here? Ethernet frame type? */
3851 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3852 return true;
3853
3854 default:
3855 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3856 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3857 return false;
3858 }
3859}
3860
3861/**
3862 * Frees the current xmit buffer.
3863 *
3864 * @param pThis The device state structure.
3865 */
3866static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3867{
3868 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3869 if (pSg)
3870 {
3871 pThisCC->CTX_SUFF(pTxSg) = NULL;
3872
3873 if (pSg->pvAllocator != pThis)
3874 {
3875 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3876 if (pDrv)
3877 pDrv->pfnFreeBuf(pDrv, pSg);
3878 }
3879 else
3880 {
3881 /* loopback */
3882 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3883 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3884 pSg->fFlags = 0;
3885 pSg->pvAllocator = NULL;
3886 }
3887 }
3888}
3889
3890#ifndef E1K_WITH_TXD_CACHE
3891/**
3892 * Allocates an xmit buffer.
3893 *
3894 * @returns See PDMINETWORKUP::pfnAllocBuf.
3895 * @param pThis The device state structure.
3896 * @param cbMin The minimum frame size.
3897 * @param fExactSize Whether cbMin is exact or if we have to max it
3898 * out to the max MTU size.
3899 * @param fGso Whether this is a GSO frame or not.
3900 */
3901DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3902{
3903 /* Adjust cbMin if necessary. */
3904 if (!fExactSize)
3905 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3906
3907 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3908 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3909 e1kXmitFreeBuf(pThis, pThisCC);
3910 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3911
3912 /*
3913 * Allocate the buffer.
3914 */
3915 PPDMSCATTERGATHER pSg;
3916 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3917 {
3918 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3919 if (RT_UNLIKELY(!pDrv))
3920 return VERR_NET_DOWN;
3921 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3922 if (RT_FAILURE(rc))
3923 {
3924 /* Suspend TX as we are out of buffers atm */
3925 STATUS |= STATUS_TXOFF;
3926 return rc;
3927 }
3928 }
3929 else
3930 {
3931 /* Create a loopback using the fallback buffer and preallocated SG. */
3932 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3933 pSg = &pThis->uTxFallback.Sg;
3934 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3935 pSg->cbUsed = 0;
3936 pSg->cbAvailable = 0;
3937 pSg->pvAllocator = pThis;
3938 pSg->pvUser = NULL; /* No GSO here. */
3939 pSg->cSegs = 1;
3940 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3941 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3942 }
3943
3944 pThisCC->CTX_SUFF(pTxSg) = pSg;
3945 return VINF_SUCCESS;
3946}
3947#else /* E1K_WITH_TXD_CACHE */
3948/**
3949 * Allocates an xmit buffer.
3950 *
3951 * @returns See PDMINETWORKUP::pfnAllocBuf.
3952 * @param pThis The device state structure.
3953 * @param cbMin The minimum frame size.
3954 * @param fExactSize Whether cbMin is exact or if we have to max it
3955 * out to the max MTU size.
3956 * @param fGso Whether this is a GSO frame or not.
3957 */
3958DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3959{
3960 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3961 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3962 e1kXmitFreeBuf(pThis, pThisCC);
3963 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3964
3965 /*
3966 * Allocate the buffer.
3967 */
3968 PPDMSCATTERGATHER pSg;
3969 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3970 {
3971 if (pThis->cbTxAlloc == 0)
3972 {
3973 /* Zero packet, no need for the buffer */
3974 return VINF_SUCCESS;
3975 }
3976 if (fGso && pThis->GsoCtx.u8Type == PDMNETWORKGSOTYPE_INVALID)
3977 {
3978 E1kLog3(("Invalid GSO context, won't allocate this packet, cb=%u %s%s\n",
3979 pThis->cbTxAlloc, pThis->fVTag ? "VLAN " : "", pThis->fGSO ? "GSO " : ""));
3980 /* No valid GSO context is available, ignore this packet. */
3981 pThis->cbTxAlloc = 0;
3982 return VINF_SUCCESS;
3983 }
3984
3985 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3986 if (RT_UNLIKELY(!pDrv))
3987 return VERR_NET_DOWN;
3988 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3989 if (RT_FAILURE(rc))
3990 {
3991 /* Suspend TX as we are out of buffers atm */
3992 STATUS |= STATUS_TXOFF;
3993 return rc;
3994 }
3995 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
3996 pThis->szPrf, pThis->cbTxAlloc,
3997 pThis->fVTag ? "VLAN " : "",
3998 pThis->fGSO ? "GSO " : ""));
3999 }
4000 else
4001 {
4002 /* Create a loopback using the fallback buffer and preallocated SG. */
4003 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
4004 pSg = &pThis->uTxFallback.Sg;
4005 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
4006 pSg->cbUsed = 0;
4007 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
4008 pSg->pvAllocator = pThis;
4009 pSg->pvUser = NULL; /* No GSO here. */
4010 pSg->cSegs = 1;
4011 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
4012 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
4013 }
4014 pThis->cbTxAlloc = 0;
4015
4016 pThisCC->CTX_SUFF(pTxSg) = pSg;
4017 return VINF_SUCCESS;
4018}
4019#endif /* E1K_WITH_TXD_CACHE */
4020
4021/**
4022 * Checks if it's a GSO buffer or not.
4023 *
4024 * @returns true / false.
4025 * @param pTxSg The scatter / gather buffer.
4026 */
4027DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
4028{
4029#if 0
4030 if (!pTxSg)
4031 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
4032 if (pTxSg && pTxSg->pvUser)
4033 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
4034#endif
4035 return pTxSg && pTxSg->pvUser /* GSO indicator */;
4036}
4037
4038#ifndef E1K_WITH_TXD_CACHE
4039/**
4040 * Load transmit descriptor from guest memory.
4041 *
4042 * @param pDevIns The device instance.
4043 * @param pDesc Pointer to descriptor union.
4044 * @param addr Physical address in guest context.
4045 * @thread E1000_TX
4046 */
4047DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
4048{
4049 PDMDevHlpPCIPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4050}
4051#else /* E1K_WITH_TXD_CACHE */
4052/**
4053 * Load transmit descriptors from guest memory.
4054 *
4055 * We need two physical reads in case the tail wrapped around the end of TX
4056 * descriptor ring.
4057 *
4058 * @returns the actual number of descriptors fetched.
4059 * @param pDevIns The device instance.
4060 * @param pThis The device state structure.
4061 * @thread E1000_TX
4062 */
4063DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4064{
4065 Assert(pThis->iTxDCurrent == 0);
4066 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
4067 unsigned nDescsAvailable = e1kGetTxLen(pTxdc) - pThis->nTxDFetched;
4068 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
4069 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
4070 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
4071 unsigned nDescsTotal = pTxdc->tdlen / sizeof(E1KTXDESC);
4072 Assert(nDescsTotal != 0);
4073 if (nDescsTotal == 0)
4074 return 0;
4075 unsigned nFirstNotLoaded = (pTxdc->tdh + pThis->nTxDFetched) % nDescsTotal;
4076 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
4077 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
4078 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
4079 nFirstNotLoaded, nDescsInSingleRead));
4080 if (nDescsToFetch == 0)
4081 return 0;
4082 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
4083 PDMDevHlpPCIPhysRead(pDevIns,
4084 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
4085 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
4086 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
4087 pThis->szPrf, nDescsInSingleRead,
4088 TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC),
4089 nFirstNotLoaded, pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
4090 if (nDescsToFetch > nDescsInSingleRead)
4091 {
4092 PDMDevHlpPCIPhysRead(pDevIns,
4093 ((uint64_t)TDBAH << 32) + TDBAL,
4094 pFirstEmptyDesc + nDescsInSingleRead,
4095 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
4096 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
4097 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
4098 TDBAH, TDBAL));
4099 }
4100 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
4101 return nDescsToFetch;
4102}
4103
4104/**
4105 * Load transmit descriptors from guest memory only if there are no loaded
4106 * descriptors.
4107 *
4108 * @returns true if there are descriptors in cache.
4109 * @param pDevIns The device instance.
4110 * @param pThis The device state structure.
4111 * @thread E1000_TX
4112 */
4113DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4114{
4115 if (pThis->nTxDFetched == 0)
4116 return e1kTxDLoadMore(pDevIns, pThis, pTxdc) != 0;
4117 return true;
4118}
4119#endif /* E1K_WITH_TXD_CACHE */
4120
4121/**
4122 * Write back transmit descriptor to guest memory.
4123 *
4124 * @param pDevIns The device instance.
4125 * @param pThis The device state structure.
4126 * @param pDesc Pointer to descriptor union.
4127 * @param addr Physical address in guest context.
4128 * @thread E1000_TX
4129 */
4130DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4131{
4132 /* Only the last half of the descriptor has to be written back. */
4133 e1kPrintTDesc(pThis, pDesc, "^^^");
4134 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4135}
4136
4137/**
4138 * Transmit complete frame.
4139 *
4140 * @remarks We skip the FCS since we're not responsible for sending anything to
4141 * a real ethernet wire.
4142 *
4143 * @param pDevIns The device instance.
4144 * @param pThis The device state structure.
4145 * @param pThisCC The current context instance data.
4146 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4147 * @thread E1000_TX
4148 */
4149static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4150{
4151 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4152 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4153 Assert(!pSg || pSg->cSegs == 1);
4154
4155 if (cbFrame > 70) /* unqualified guess */
4156 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4157
4158#ifdef E1K_INT_STATS
4159 if (cbFrame <= 1514)
4160 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4161 else if (cbFrame <= 2962)
4162 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4163 else if (cbFrame <= 4410)
4164 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4165 else if (cbFrame <= 5858)
4166 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4167 else if (cbFrame <= 7306)
4168 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4169 else if (cbFrame <= 8754)
4170 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4171 else if (cbFrame <= 16384)
4172 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4173 else if (cbFrame <= 32768)
4174 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4175 else
4176 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4177#endif /* E1K_INT_STATS */
4178
4179 /* Add VLAN tag */
4180 if (cbFrame > 12 && pThis->fVTag)
4181 {
4182 E1kLog3(("%s Inserting VLAN tag %08x\n",
4183 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4184 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4185 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4186 pSg->cbUsed += 4;
4187 cbFrame += 4;
4188 Assert(pSg->cbUsed == cbFrame);
4189 Assert(pSg->cbUsed <= pSg->cbAvailable);
4190 }
4191/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4192 "%.*Rhxd\n"
4193 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4194 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4195
4196 /* Update the stats */
4197 E1K_INC_CNT32(TPT);
4198 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4199 E1K_INC_CNT32(GPTC);
4200 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4201 E1K_INC_CNT32(BPTC);
4202 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4203 E1K_INC_CNT32(MPTC);
4204 /* Update octet transmit counter */
4205 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4206 if (pThisCC->CTX_SUFF(pDrv))
4207 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4208 if (cbFrame == 64)
4209 E1K_INC_CNT32(PTC64);
4210 else if (cbFrame < 128)
4211 E1K_INC_CNT32(PTC127);
4212 else if (cbFrame < 256)
4213 E1K_INC_CNT32(PTC255);
4214 else if (cbFrame < 512)
4215 E1K_INC_CNT32(PTC511);
4216 else if (cbFrame < 1024)
4217 E1K_INC_CNT32(PTC1023);
4218 else
4219 E1K_INC_CNT32(PTC1522);
4220
4221 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4222
4223 /*
4224 * Dump and send the packet.
4225 */
4226 int rc = VERR_NET_DOWN;
4227 if (pSg && pSg->pvAllocator != pThis)
4228 {
4229 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4230
4231 pThisCC->CTX_SUFF(pTxSg) = NULL;
4232 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4233 if (pDrv)
4234 {
4235 /* Release critical section to avoid deadlock in CanReceive */
4236 //e1kCsLeave(pThis);
4237 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4238 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4239 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4240 //e1kCsEnter(pThis, RT_SRC_POS);
4241 }
4242 }
4243 else if (pSg)
4244 {
4245 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4246 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4247
4248 /** @todo do we actually need to check that we're in loopback mode here? */
4249 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4250 {
4251 E1KRXDST status;
4252 RT_ZERO(status);
4253 status.fPIF = true;
4254 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4255 rc = VINF_SUCCESS;
4256 }
4257 e1kXmitFreeBuf(pThis, pThisCC);
4258 }
4259 else
4260 rc = VERR_NET_DOWN;
4261 if (RT_FAILURE(rc))
4262 {
4263 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4264 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4265 }
4266
4267 pThis->led.Actual.s.fWriting = 0;
4268}
4269
4270/**
4271 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4272 *
4273 * @param pThis The device state structure.
4274 * @param pPkt Pointer to the packet.
4275 * @param u16PktLen Total length of the packet.
4276 * @param cso Offset in packet to write checksum at.
4277 * @param css Offset in packet to start computing
4278 * checksum from.
4279 * @param cse Offset in packet to stop computing
4280 * checksum at.
4281 * @param fUdp Replace 0 checksum with all 1s.
4282 * @thread E1000_TX
4283 */
4284static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse, bool fUdp = false)
4285{
4286 RT_NOREF1(pThis);
4287
4288 if (css >= u16PktLen)
4289 {
4290 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4291 pThis->szPrf, cso, u16PktLen));
4292 return;
4293 }
4294
4295 if (cso >= u16PktLen - 1)
4296 {
4297 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4298 pThis->szPrf, cso, u16PktLen));
4299 return;
4300 }
4301
4302 if (cse == 0 || cse >= u16PktLen)
4303 cse = u16PktLen - 1;
4304 else if (cse < css)
4305 {
4306 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4307 pThis->szPrf, css, cse));
4308 return;
4309 }
4310
4311 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4312 if (fUdp && u16ChkSum == 0)
4313 u16ChkSum = ~u16ChkSum; /* 0 means no checksum computed in case of UDP (see @bugref{9883}) */
4314 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4315 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4316 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4317}
4318
4319/**
4320 * Add a part of descriptor's buffer to transmit frame.
4321 *
4322 * @remarks data.u64BufAddr is used unconditionally for both data
4323 * and legacy descriptors since it is identical to
4324 * legacy.u64BufAddr.
4325 *
4326 * @param pDevIns The device instance.
4327 * @param pThis The device state structure.
4328 * @param pDesc Pointer to the descriptor to transmit.
4329 * @param u16Len Length of buffer to the end of segment.
4330 * @param fSend Force packet sending.
4331 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4332 * @thread E1000_TX
4333 */
4334#ifndef E1K_WITH_TXD_CACHE
4335static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4336{
4337 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4338 /* TCP header being transmitted */
4339 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4340 /* IP header being transmitted */
4341 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4342
4343 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4344 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4345 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4346
4347 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4348 E1kLog3(("%s Dump of the segment:\n"
4349 "%.*Rhxd\n"
4350 "%s --- End of dump ---\n",
4351 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4352 pThis->u16TxPktLen += u16Len;
4353 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4354 pThis->szPrf, pThis->u16TxPktLen));
4355 if (pThis->u16HdrRemain > 0)
4356 {
4357 /* The header was not complete, check if it is now */
4358 if (u16Len >= pThis->u16HdrRemain)
4359 {
4360 /* The rest is payload */
4361 u16Len -= pThis->u16HdrRemain;
4362 pThis->u16HdrRemain = 0;
4363 /* Save partial checksum and flags */
4364 pThis->u32SavedCsum = pTcpHdr->chksum;
4365 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4366 /* Clear FIN and PSH flags now and set them only in the last segment */
4367 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4368 }
4369 else
4370 {
4371 /* Still not */
4372 pThis->u16HdrRemain -= u16Len;
4373 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4374 pThis->szPrf, pThis->u16HdrRemain));
4375 return;
4376 }
4377 }
4378
4379 pThis->u32PayRemain -= u16Len;
4380
4381 if (fSend)
4382 {
4383 /* Leave ethernet header intact */
4384 /* IP Total Length = payload + headers - ethernet header */
4385 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4386 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4387 pThis->szPrf, ntohs(pIpHdr->total_len)));
4388 /* Update IP Checksum */
4389 pIpHdr->chksum = 0;
4390 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4391 pThis->contextTSE.ip.u8CSO,
4392 pThis->contextTSE.ip.u8CSS,
4393 pThis->contextTSE.ip.u16CSE);
4394
4395 /* Update TCP flags */
4396 /* Restore original FIN and PSH flags for the last segment */
4397 if (pThis->u32PayRemain == 0)
4398 {
4399 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4400 E1K_INC_CNT32(TSCTC);
4401 }
4402 /* Add TCP length to partial pseudo header sum */
4403 uint32_t csum = pThis->u32SavedCsum
4404 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4405 while (csum >> 16)
4406 csum = (csum >> 16) + (csum & 0xFFFF);
4407 pTcpHdr->chksum = csum;
4408 /* Compute final checksum */
4409 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4410 pThis->contextTSE.tu.u8CSO,
4411 pThis->contextTSE.tu.u8CSS,
4412 pThis->contextTSE.tu.u16CSE);
4413
4414 /*
4415 * Transmit it. If we've use the SG already, allocate a new one before
4416 * we copy of the data.
4417 */
4418 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4419 if (!pTxSg)
4420 {
4421 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4422 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4423 }
4424 if (pTxSg)
4425 {
4426 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4427 Assert(pTxSg->cSegs == 1);
4428 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4429 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4430 pTxSg->cbUsed = pThis->u16TxPktLen;
4431 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4432 }
4433 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4434
4435 /* Update Sequence Number */
4436 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4437 - pThis->contextTSE.dw3.u8HDRLEN);
4438 /* Increment IP identification */
4439 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4440 }
4441}
4442#else /* E1K_WITH_TXD_CACHE */
4443static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4444{
4445 int rc = VINF_SUCCESS;
4446 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4447 /* TCP header being transmitted */
4448 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4449 /* IP header being transmitted */
4450 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4451
4452 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4453 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4454 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4455
4456 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4457 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4458 else
4459 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4460 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4461 E1kLog3(("%s Dump of the segment:\n"
4462 "%.*Rhxd\n"
4463 "%s --- End of dump ---\n",
4464 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4465 pThis->u16TxPktLen += u16Len;
4466 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4467 pThis->szPrf, pThis->u16TxPktLen));
4468 if (pThis->u16HdrRemain > 0)
4469 {
4470 /* The header was not complete, check if it is now */
4471 if (u16Len >= pThis->u16HdrRemain)
4472 {
4473 /* The rest is payload */
4474 u16Len -= pThis->u16HdrRemain;
4475 pThis->u16HdrRemain = 0;
4476 /* Save partial checksum and flags */
4477 pThis->u32SavedCsum = pTcpHdr->chksum;
4478 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4479 /* Clear FIN and PSH flags now and set them only in the last segment */
4480 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4481 }
4482 else
4483 {
4484 /* Still not */
4485 pThis->u16HdrRemain -= u16Len;
4486 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4487 pThis->szPrf, pThis->u16HdrRemain));
4488 return rc;
4489 }
4490 }
4491
4492 if (u16Len > pThis->u32PayRemain)
4493 pThis->u32PayRemain = 0;
4494 else
4495 pThis->u32PayRemain -= u16Len;
4496
4497 if (fSend)
4498 {
4499 /* Leave ethernet header intact */
4500 /* IP Total Length = payload + headers - ethernet header */
4501 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4502 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4503 pThis->szPrf, ntohs(pIpHdr->total_len)));
4504 /* Update IP Checksum */
4505 pIpHdr->chksum = 0;
4506 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4507 pThis->contextTSE.ip.u8CSO,
4508 pThis->contextTSE.ip.u8CSS,
4509 pThis->contextTSE.ip.u16CSE);
4510
4511 /* Update TCP flags */
4512 /* Restore original FIN and PSH flags for the last segment */
4513 if (pThis->u32PayRemain == 0)
4514 {
4515 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4516 E1K_INC_CNT32(TSCTC);
4517 }
4518 /* Add TCP length to partial pseudo header sum */
4519 uint32_t csum = pThis->u32SavedCsum
4520 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4521 while (csum >> 16)
4522 csum = (csum >> 16) + (csum & 0xFFFF);
4523 Assert(csum < 65536);
4524 pTcpHdr->chksum = (uint16_t)csum;
4525 /* Compute final checksum */
4526 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4527 pThis->contextTSE.tu.u8CSO,
4528 pThis->contextTSE.tu.u8CSS,
4529 pThis->contextTSE.tu.u16CSE);
4530
4531 /*
4532 * Transmit it.
4533 */
4534 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4535 if (pTxSg)
4536 {
4537 /* Make sure the packet fits into the allocated buffer */
4538 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4539#ifdef DEBUG
4540 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4541 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4542 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4543#endif /* DEBUG */
4544 Assert(pTxSg->cSegs == 1);
4545 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4546 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4547 pTxSg->cbUsed = cbCopy;
4548 pTxSg->aSegs[0].cbSeg = cbCopy;
4549 }
4550 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4551
4552 /* Update Sequence Number */
4553 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4554 - pThis->contextTSE.dw3.u8HDRLEN);
4555 /* Increment IP identification */
4556 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4557
4558 /* Allocate new buffer for the next segment. */
4559 if (pThis->u32PayRemain)
4560 {
4561 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4562 pThis->contextTSE.dw3.u16MSS)
4563 + pThis->contextTSE.dw3.u8HDRLEN;
4564 /* Do not add VLAN tags to empty packets. */
4565 if (pThis->fVTag && pThis->cbTxAlloc > 0)
4566 pThis->cbTxAlloc += 4;
4567 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4568 }
4569 }
4570
4571 return rc;
4572}
4573#endif /* E1K_WITH_TXD_CACHE */
4574
4575#ifndef E1K_WITH_TXD_CACHE
4576/**
4577 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4578 * frame.
4579 *
4580 * We construct the frame in the fallback buffer first and the copy it to the SG
4581 * buffer before passing it down to the network driver code.
4582 *
4583 * @returns true if the frame should be transmitted, false if not.
4584 *
4585 * @param pThis The device state structure.
4586 * @param pDesc Pointer to the descriptor to transmit.
4587 * @param cbFragment Length of descriptor's buffer.
4588 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4589 * @thread E1000_TX
4590 */
4591static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4592{
4593 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4594 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4595 Assert(pDesc->data.cmd.fTSE);
4596 Assert(!e1kXmitIsGsoBuf(pTxSg));
4597
4598 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4599 Assert(u16MaxPktLen != 0);
4600 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4601
4602 /*
4603 * Carve out segments.
4604 */
4605 do
4606 {
4607 /* Calculate how many bytes we have left in this TCP segment */
4608 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4609 if (cb > cbFragment)
4610 {
4611 /* This descriptor fits completely into current segment */
4612 cb = cbFragment;
4613 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4614 }
4615 else
4616 {
4617 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4618 /*
4619 * Rewind the packet tail pointer to the beginning of payload,
4620 * so we continue writing right beyond the header.
4621 */
4622 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4623 }
4624
4625 pDesc->data.u64BufAddr += cb;
4626 cbFragment -= cb;
4627 } while (cbFragment > 0);
4628
4629 if (pDesc->data.cmd.fEOP)
4630 {
4631 /* End of packet, next segment will contain header. */
4632 if (pThis->u32PayRemain != 0)
4633 E1K_INC_CNT32(TSCTFC);
4634 pThis->u16TxPktLen = 0;
4635 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4636 }
4637
4638 return false;
4639}
4640#else /* E1K_WITH_TXD_CACHE */
4641/**
4642 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4643 * frame.
4644 *
4645 * We construct the frame in the fallback buffer first and the copy it to the SG
4646 * buffer before passing it down to the network driver code.
4647 *
4648 * @returns error code
4649 *
4650 * @param pDevIns The device instance.
4651 * @param pThis The device state structure.
4652 * @param pDesc Pointer to the descriptor to transmit.
4653 * @param cbFragment Length of descriptor's buffer.
4654 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4655 * @thread E1000_TX
4656 */
4657static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4658{
4659#ifdef VBOX_STRICT
4660 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4661 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4662 Assert(pDesc->data.cmd.fTSE);
4663 Assert(!e1kXmitIsGsoBuf(pTxSg));
4664#endif
4665
4666 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4667 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4668 if (u16MaxPktLen == 0)
4669 return VINF_SUCCESS;
4670
4671 /*
4672 * Carve out segments.
4673 */
4674 int rc = VINF_SUCCESS;
4675 do
4676 {
4677 /* Calculate how many bytes we have left in this TCP segment */
4678 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4679 if (cb > pDesc->data.cmd.u20DTALEN)
4680 {
4681 /* This descriptor fits completely into current segment */
4682 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4683 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4684 }
4685 else
4686 {
4687 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4688 /*
4689 * Rewind the packet tail pointer to the beginning of payload,
4690 * so we continue writing right beyond the header.
4691 */
4692 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4693 }
4694
4695 pDesc->data.u64BufAddr += cb;
4696 pDesc->data.cmd.u20DTALEN -= cb;
4697 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4698
4699 if (pDesc->data.cmd.fEOP)
4700 {
4701 /* End of packet, next segment will contain header. */
4702 if (pThis->u32PayRemain != 0)
4703 E1K_INC_CNT32(TSCTFC);
4704 pThis->u16TxPktLen = 0;
4705 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4706 }
4707
4708 return VINF_SUCCESS; /// @todo consider rc;
4709}
4710#endif /* E1K_WITH_TXD_CACHE */
4711
4712
4713/**
4714 * Add descriptor's buffer to transmit frame.
4715 *
4716 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4717 * TSE frames we cannot handle as GSO.
4718 *
4719 * @returns true on success, false on failure.
4720 *
4721 * @param pDevIns The device instance.
4722 * @param pThisCC The current context instance data.
4723 * @param pThis The device state structure.
4724 * @param PhysAddr The physical address of the descriptor buffer.
4725 * @param cbFragment Length of descriptor's buffer.
4726 * @thread E1000_TX
4727 */
4728static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4729{
4730 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4731 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4732 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4733
4734 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4735 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4736 fGso ? "true" : "false"));
4737 PCPDMNETWORKGSO pGso = (PCPDMNETWORKGSO)pTxSg->pvUser;
4738 if (pGso)
4739 {
4740 if (RT_UNLIKELY(pGso->cbMaxSeg == 0))
4741 {
4742 E1kLog(("%s zero-sized fragments are not allowed\n", pThis->szPrf));
4743 return false;
4744 }
4745 if (RT_UNLIKELY(pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP))
4746 {
4747 E1kLog(("%s UDP fragmentation is no longer supported\n", pThis->szPrf));
4748 return false;
4749 }
4750 }
4751 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4752 {
4753 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4754 return false;
4755 }
4756 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4757 {
4758 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4759 return false;
4760 }
4761
4762 if (RT_LIKELY(pTxSg))
4763 {
4764 Assert(pTxSg->cSegs == 1);
4765 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4766 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4767 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4768
4769 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4770
4771 pTxSg->cbUsed = cbNewPkt;
4772 }
4773 pThis->u16TxPktLen = cbNewPkt;
4774
4775 return true;
4776}
4777
4778
4779/**
4780 * Write the descriptor back to guest memory and notify the guest.
4781 *
4782 * @param pThis The device state structure.
4783 * @param pDesc Pointer to the descriptor have been transmitted.
4784 * @param addr Physical address of the descriptor in guest memory.
4785 * @thread E1000_TX
4786 */
4787static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4788{
4789 /*
4790 * We fake descriptor write-back bursting. Descriptors are written back as they are
4791 * processed.
4792 */
4793 /* Let's pretend we process descriptors. Write back with DD set. */
4794 /*
4795 * Prior to r71586 we tried to accomodate the case when write-back bursts
4796 * are enabled without actually implementing bursting by writing back all
4797 * descriptors, even the ones that do not have RS set. This caused kernel
4798 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4799 * associated with written back descriptor if it happened to be a context
4800 * descriptor since context descriptors do not have skb associated to them.
4801 * Starting from r71586 we write back only the descriptors with RS set,
4802 * which is a little bit different from what the real hardware does in
4803 * case there is a chain of data descritors where some of them have RS set
4804 * and others do not. It is very uncommon scenario imho.
4805 * We need to check RPS as well since some legacy drivers use it instead of
4806 * RS even with newer cards.
4807 */
4808 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4809 {
4810 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4811 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4812 if (pDesc->legacy.cmd.fEOP)
4813 {
4814//#ifdef E1K_USE_TX_TIMERS
4815 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4816 {
4817 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4818 //if (pThis->fIntRaised)
4819 //{
4820 // /* Interrupt is already pending, no need for timers */
4821 // ICR |= ICR_TXDW;
4822 //}
4823 //else {
4824 /* Arm the timer to fire in TIVD usec (discard .024) */
4825 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4826# ifndef E1K_NO_TAD
4827 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4828 E1kLog2(("%s Checking if TAD timer is running\n",
4829 pThis->szPrf));
4830 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4831 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4832# endif /* E1K_NO_TAD */
4833 }
4834 else
4835 {
4836 if (pThis->fTidEnabled)
4837 {
4838 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4839 pThis->szPrf));
4840 /* Cancel both timers if armed and fire immediately. */
4841# ifndef E1K_NO_TAD
4842 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4843# endif
4844 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4845 }
4846//#endif /* E1K_USE_TX_TIMERS */
4847 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4848 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4849//#ifdef E1K_USE_TX_TIMERS
4850 }
4851//#endif /* E1K_USE_TX_TIMERS */
4852 }
4853 }
4854 else
4855 {
4856 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4857 }
4858}
4859
4860#ifndef E1K_WITH_TXD_CACHE
4861
4862/**
4863 * Process Transmit Descriptor.
4864 *
4865 * E1000 supports three types of transmit descriptors:
4866 * - legacy data descriptors of older format (context-less).
4867 * - data the same as legacy but providing new offloading capabilities.
4868 * - context sets up the context for following data descriptors.
4869 *
4870 * @param pDevIns The device instance.
4871 * @param pThis The device state structure.
4872 * @param pThisCC The current context instance data.
4873 * @param pDesc Pointer to descriptor union.
4874 * @param addr Physical address of descriptor in guest memory.
4875 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4876 * @thread E1000_TX
4877 */
4878static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4879 RTGCPHYS addr, bool fOnWorkerThread)
4880{
4881 int rc = VINF_SUCCESS;
4882 uint32_t cbVTag = 0;
4883
4884 e1kPrintTDesc(pThis, pDesc, "vvv");
4885
4886//#ifdef E1K_USE_TX_TIMERS
4887 if (pThis->fTidEnabled)
4888 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4889//#endif /* E1K_USE_TX_TIMERS */
4890
4891 switch (e1kGetDescType(pDesc))
4892 {
4893 case E1K_DTYP_CONTEXT:
4894 if (pDesc->context.dw2.fTSE)
4895 {
4896 pThis->contextTSE = pDesc->context;
4897 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4898 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4899 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4900 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4901 }
4902 else
4903 {
4904 pThis->contextNormal = pDesc->context;
4905 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4906 }
4907 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4908 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4909 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4910 pDesc->context.ip.u8CSS,
4911 pDesc->context.ip.u8CSO,
4912 pDesc->context.ip.u16CSE,
4913 pDesc->context.tu.u8CSS,
4914 pDesc->context.tu.u8CSO,
4915 pDesc->context.tu.u16CSE));
4916 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4917 e1kDescReport(pThis, pDesc, addr);
4918 break;
4919
4920 case E1K_DTYP_DATA:
4921 {
4922 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4923 {
4924 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4925 /** @todo Same as legacy when !TSE. See below. */
4926 break;
4927 }
4928 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4929 &pThis->StatTxDescTSEData:
4930 &pThis->StatTxDescData);
4931 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4932 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4933
4934 /*
4935 * The last descriptor of non-TSE packet must contain VLE flag.
4936 * TSE packets have VLE flag in the first descriptor. The later
4937 * case is taken care of a bit later when cbVTag gets assigned.
4938 *
4939 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4940 */
4941 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4942 {
4943 pThis->fVTag = pDesc->data.cmd.fVLE;
4944 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4945 }
4946 /*
4947 * First fragment: Allocate new buffer and save the IXSM and TXSM
4948 * packet options as these are only valid in the first fragment.
4949 */
4950 if (pThis->u16TxPktLen == 0)
4951 {
4952 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4953 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4954 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4955 pThis->fIPcsum ? " IP" : "",
4956 pThis->fTCPcsum ? " TCP/UDP" : ""));
4957 if (pDesc->data.cmd.fTSE)
4958 {
4959 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4960 pThis->fVTag = pDesc->data.cmd.fVLE;
4961 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4962 cbVTag = pThis->fVTag ? 4 : 0;
4963 }
4964 else if (pDesc->data.cmd.fEOP)
4965 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4966 else
4967 cbVTag = 4;
4968 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4969 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4970 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4971 true /*fExactSize*/, true /*fGso*/);
4972 else if (pDesc->data.cmd.fTSE)
4973 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4974 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4975 else
4976 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4977 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4978
4979 /**
4980 * @todo: Perhaps it is not that simple for GSO packets! We may
4981 * need to unwind some changes.
4982 */
4983 if (RT_FAILURE(rc))
4984 {
4985 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4986 break;
4987 }
4988 /** @todo Is there any way to indicating errors other than collisions? Like
4989 * VERR_NET_DOWN. */
4990 }
4991
4992 /*
4993 * Add the descriptor data to the frame. If the frame is complete,
4994 * transmit it and reset the u16TxPktLen field.
4995 */
4996 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
4997 {
4998 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
4999 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5000 if (pDesc->data.cmd.fEOP)
5001 {
5002 if ( fRc
5003 && pThisCC->CTX_SUFF(pTxSg)
5004 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5005 {
5006 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5007 E1K_INC_CNT32(TSCTC);
5008 }
5009 else
5010 {
5011 if (fRc)
5012 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5013 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5014 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5015 e1kXmitFreeBuf(pThis);
5016 E1K_INC_CNT32(TSCTFC);
5017 }
5018 pThis->u16TxPktLen = 0;
5019 }
5020 }
5021 else if (!pDesc->data.cmd.fTSE)
5022 {
5023 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5024 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5025 if (pDesc->data.cmd.fEOP)
5026 {
5027 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5028 {
5029 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5030 if (pThis->fIPcsum)
5031 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5032 pThis->contextNormal.ip.u8CSO,
5033 pThis->contextNormal.ip.u8CSS,
5034 pThis->contextNormal.ip.u16CSE);
5035 if (pThis->fTCPcsum)
5036 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5037 pThis->contextNormal.tu.u8CSO,
5038 pThis->contextNormal.tu.u8CSS,
5039 pThis->contextNormal.tu.u16CSE,
5040 !pThis->contextNormal.dw2.fTCP);
5041 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5042 }
5043 else
5044 e1kXmitFreeBuf(pThis);
5045 pThis->u16TxPktLen = 0;
5046 }
5047 }
5048 else
5049 {
5050 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5051 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
5052 }
5053
5054 e1kDescReport(pThis, pDesc, addr);
5055 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5056 break;
5057 }
5058
5059 case E1K_DTYP_LEGACY:
5060 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5061 {
5062 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5063 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
5064 break;
5065 }
5066 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5067 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5068
5069 /* First fragment: allocate new buffer. */
5070 if (pThis->u16TxPktLen == 0)
5071 {
5072 if (pDesc->legacy.cmd.fEOP)
5073 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
5074 else
5075 cbVTag = 4;
5076 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
5077 /** @todo reset status bits? */
5078 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
5079 if (RT_FAILURE(rc))
5080 {
5081 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5082 break;
5083 }
5084
5085 /** @todo Is there any way to indicating errors other than collisions? Like
5086 * VERR_NET_DOWN. */
5087 }
5088
5089 /* Add fragment to frame. */
5090 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5091 {
5092 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5093
5094 /* Last fragment: Transmit and reset the packet storage counter. */
5095 if (pDesc->legacy.cmd.fEOP)
5096 {
5097 pThis->fVTag = pDesc->legacy.cmd.fVLE;
5098 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
5099 /** @todo Offload processing goes here. */
5100 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5101 pThis->u16TxPktLen = 0;
5102 }
5103 }
5104 /* Last fragment + failure: free the buffer and reset the storage counter. */
5105 else if (pDesc->legacy.cmd.fEOP)
5106 {
5107 e1kXmitFreeBuf(pThis);
5108 pThis->u16TxPktLen = 0;
5109 }
5110
5111 e1kDescReport(pThis, pDesc, addr);
5112 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5113 break;
5114
5115 default:
5116 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5117 pThis->szPrf, e1kGetDescType(pDesc)));
5118 break;
5119 }
5120
5121 return rc;
5122}
5123
5124#else /* E1K_WITH_TXD_CACHE */
5125
5126/**
5127 * Process Transmit Descriptor.
5128 *
5129 * E1000 supports three types of transmit descriptors:
5130 * - legacy data descriptors of older format (context-less).
5131 * - data the same as legacy but providing new offloading capabilities.
5132 * - context sets up the context for following data descriptors.
5133 *
5134 * @param pDevIns The device instance.
5135 * @param pThis The device state structure.
5136 * @param pThisCC The current context instance data.
5137 * @param pDesc Pointer to descriptor union.
5138 * @param addr Physical address of descriptor in guest memory.
5139 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
5140 * @param cbPacketSize Size of the packet as previously computed.
5141 * @thread E1000_TX
5142 */
5143static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
5144 RTGCPHYS addr, bool fOnWorkerThread)
5145{
5146 int rc = VINF_SUCCESS;
5147
5148 e1kPrintTDesc(pThis, pDesc, "vvv");
5149
5150 if (pDesc->legacy.dw3.fDD)
5151 {
5152 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
5153 e1kDescReport(pDevIns, pThis, pDesc, addr);
5154 return VINF_SUCCESS;
5155 }
5156
5157//#ifdef E1K_USE_TX_TIMERS
5158 if (pThis->fTidEnabled)
5159 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5160//#endif /* E1K_USE_TX_TIMERS */
5161
5162 switch (e1kGetDescType(pDesc))
5163 {
5164 case E1K_DTYP_CONTEXT:
5165 /* The caller have already updated the context */
5166 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5167 e1kDescReport(pDevIns, pThis, pDesc, addr);
5168 break;
5169
5170 case E1K_DTYP_DATA:
5171 {
5172 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5173 &pThis->StatTxDescTSEData:
5174 &pThis->StatTxDescData);
5175 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5176 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5177 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5178 {
5179 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
5180 if (pDesc->data.cmd.fEOP)
5181 {
5182 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5183 pThis->u16TxPktLen = 0;
5184 }
5185 }
5186 else
5187 {
5188 /*
5189 * Add the descriptor data to the frame. If the frame is complete,
5190 * transmit it and reset the u16TxPktLen field.
5191 */
5192 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5193 {
5194 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5195 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5196 if (pDesc->data.cmd.fEOP)
5197 {
5198 if ( fRc
5199 && pThisCC->CTX_SUFF(pTxSg)
5200 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5201 {
5202 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5203 E1K_INC_CNT32(TSCTC);
5204 }
5205 else
5206 {
5207 if (fRc)
5208 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5209 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5210 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5211 e1kXmitFreeBuf(pThis, pThisCC);
5212 E1K_INC_CNT32(TSCTFC);
5213 }
5214 pThis->u16TxPktLen = 0;
5215 }
5216 }
5217 else if (!pDesc->data.cmd.fTSE)
5218 {
5219 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5220 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5221 if (pDesc->data.cmd.fEOP)
5222 {
5223 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5224 {
5225 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5226 if (pThis->fIPcsum)
5227 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5228 pThis->contextNormal.ip.u8CSO,
5229 pThis->contextNormal.ip.u8CSS,
5230 pThis->contextNormal.ip.u16CSE);
5231 if (pThis->fTCPcsum)
5232 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5233 pThis->contextNormal.tu.u8CSO,
5234 pThis->contextNormal.tu.u8CSS,
5235 pThis->contextNormal.tu.u16CSE,
5236 !pThis->contextNormal.dw2.fTCP);
5237 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5238 }
5239 else
5240 e1kXmitFreeBuf(pThis, pThisCC);
5241 pThis->u16TxPktLen = 0;
5242 }
5243 }
5244 else
5245 {
5246 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5247 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5248 }
5249 }
5250 e1kDescReport(pDevIns, pThis, pDesc, addr);
5251 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5252 break;
5253 }
5254
5255 case E1K_DTYP_LEGACY:
5256 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5257 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5258 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5259 {
5260 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5261 }
5262 else
5263 {
5264 /* Add fragment to frame. */
5265 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5266 {
5267 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5268
5269 /* Last fragment: Transmit and reset the packet storage counter. */
5270 if (pDesc->legacy.cmd.fEOP)
5271 {
5272 if (pDesc->legacy.cmd.fIC)
5273 {
5274 e1kInsertChecksum(pThis,
5275 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5276 pThis->u16TxPktLen,
5277 pDesc->legacy.cmd.u8CSO,
5278 pDesc->legacy.dw3.u8CSS,
5279 0);
5280 }
5281 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5282 pThis->u16TxPktLen = 0;
5283 }
5284 }
5285 /* Last fragment + failure: free the buffer and reset the storage counter. */
5286 else if (pDesc->legacy.cmd.fEOP)
5287 {
5288 e1kXmitFreeBuf(pThis, pThisCC);
5289 pThis->u16TxPktLen = 0;
5290 }
5291 }
5292 e1kDescReport(pDevIns, pThis, pDesc, addr);
5293 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5294 break;
5295
5296 default:
5297 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5298 pThis->szPrf, e1kGetDescType(pDesc)));
5299 break;
5300 }
5301
5302 return rc;
5303}
5304
5305DECLINLINE(void) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5306{
5307 if (pDesc->context.dw2.fTSE)
5308 {
5309 pThis->contextTSE = pDesc->context;
5310 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5311 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5312 {
5313 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5314 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5315 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5316 }
5317 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5318 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5319 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5320 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5321 }
5322 else
5323 {
5324 pThis->contextNormal = pDesc->context;
5325 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5326 }
5327 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5328 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5329 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5330 pDesc->context.ip.u8CSS,
5331 pDesc->context.ip.u8CSO,
5332 pDesc->context.ip.u16CSE,
5333 pDesc->context.tu.u8CSS,
5334 pDesc->context.tu.u8CSO,
5335 pDesc->context.tu.u16CSE));
5336}
5337
5338static bool e1kLocateTxPacket(PE1KSTATE pThis)
5339{
5340 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5341 pThis->szPrf, pThis->cbTxAlloc));
5342 /* Check if we have located the packet already. */
5343 if (pThis->cbTxAlloc)
5344 {
5345 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5346 pThis->szPrf, pThis->cbTxAlloc));
5347 return true;
5348 }
5349
5350 bool fTSE = false;
5351 uint32_t cbPacket = 0;
5352
5353 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5354 {
5355 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5356 switch (e1kGetDescType(pDesc))
5357 {
5358 case E1K_DTYP_CONTEXT:
5359 if (cbPacket == 0)
5360 e1kUpdateTxContext(pThis, pDesc);
5361 else
5362 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5363 pThis->szPrf, cbPacket));
5364 continue;
5365 case E1K_DTYP_LEGACY:
5366 /* Skip invalid descriptors. */
5367 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5368 {
5369 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5370 pThis->szPrf, cbPacket));
5371 pDesc->legacy.dw3.fDD = true; /* Make sure it is skipped by processing */
5372 continue;
5373 }
5374 /* Skip empty descriptors. */
5375 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5376 break;
5377 cbPacket += pDesc->legacy.cmd.u16Length;
5378 pThis->fGSO = false;
5379 break;
5380 case E1K_DTYP_DATA:
5381 /* Skip invalid descriptors. */
5382 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5383 {
5384 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5385 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5386 pDesc->data.dw3.fDD = true; /* Make sure it is skipped by processing */
5387 continue;
5388 }
5389 /* Skip empty descriptors. */
5390 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5391 break;
5392 if (cbPacket == 0)
5393 {
5394 /*
5395 * The first fragment: save IXSM and TXSM options
5396 * as these are only valid in the first fragment.
5397 */
5398 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5399 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5400 fTSE = pDesc->data.cmd.fTSE;
5401 /*
5402 * TSE descriptors have VLE bit properly set in
5403 * the first fragment.
5404 */
5405 if (fTSE)
5406 {
5407 pThis->fVTag = pDesc->data.cmd.fVLE;
5408 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5409 }
5410 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5411 }
5412 cbPacket += pDesc->data.cmd.u20DTALEN;
5413 break;
5414 default:
5415 AssertMsgFailed(("Impossible descriptor type!"));
5416 continue;
5417 }
5418 if (pDesc->legacy.cmd.fEOP)
5419 {
5420 /*
5421 * Non-TSE descriptors have VLE bit properly set in
5422 * the last fragment.
5423 */
5424 if (!fTSE)
5425 {
5426 pThis->fVTag = pDesc->data.cmd.fVLE;
5427 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5428 }
5429 /*
5430 * Compute the required buffer size. If we cannot do GSO but still
5431 * have to do segmentation we allocate the first segment only.
5432 */
5433 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5434 cbPacket :
5435 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5436 /* Do not add VLAN tags to empty packets. */
5437 if (pThis->fVTag && pThis->cbTxAlloc > 0)
5438 pThis->cbTxAlloc += 4;
5439 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5440 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5441 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5442 return true;
5443 }
5444 }
5445
5446 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5447 {
5448 /* All descriptors were empty, we need to process them as a dummy packet */
5449 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5450 pThis->szPrf, pThis->cbTxAlloc));
5451 return true;
5452 }
5453 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5454 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5455 return false;
5456}
5457
5458static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread, PE1KTXDC pTxdc)
5459{
5460 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5461 int rc = VINF_SUCCESS;
5462
5463 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5464 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5465
5466 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5467 {
5468 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5469 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5470 pThis->szPrf, TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC), pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
5471 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh), fOnWorkerThread);
5472 if (RT_FAILURE(rc))
5473 break;
5474 if (++pTxdc->tdh * sizeof(E1KTXDESC) >= pTxdc->tdlen)
5475 pTxdc->tdh = 0;
5476 TDH = pTxdc->tdh; /* Sync the actual register and TXDC */
5477 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5478 if (uLowThreshold != 0 && e1kGetTxLen(pTxdc) <= uLowThreshold)
5479 {
5480 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5481 pThis->szPrf, e1kGetTxLen(pTxdc), GET_BITS(TXDCTL, LWTHRESH)*8));
5482 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5483 }
5484 ++pThis->iTxDCurrent;
5485 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5486 break;
5487 }
5488
5489 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5490 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5491 return rc;
5492}
5493
5494#endif /* E1K_WITH_TXD_CACHE */
5495#ifndef E1K_WITH_TXD_CACHE
5496
5497/**
5498 * Transmit pending descriptors.
5499 *
5500 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5501 *
5502 * @param pDevIns The device instance.
5503 * @param pThis The E1000 state.
5504 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5505 */
5506static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5507{
5508 int rc = VINF_SUCCESS;
5509 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5510
5511 /* Check if transmitter is enabled. */
5512 if (!(TCTL & TCTL_EN))
5513 return VINF_SUCCESS;
5514 /*
5515 * Grab the xmit lock of the driver as well as the E1K device state.
5516 */
5517 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5518 if (RT_LIKELY(rc == VINF_SUCCESS))
5519 {
5520 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5521 if (pDrv)
5522 {
5523 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5524 if (RT_FAILURE(rc))
5525 {
5526 e1kCsTxLeave(pThis);
5527 return rc;
5528 }
5529 }
5530 /*
5531 * Process all pending descriptors.
5532 * Note! Do not process descriptors in locked state
5533 */
5534 while (TDH != TDT && !pThis->fLocked)
5535 {
5536 E1KTXDESC desc;
5537 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5538 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5539
5540 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5541 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5542 /* If we failed to transmit descriptor we will try it again later */
5543 if (RT_FAILURE(rc))
5544 break;
5545 if (++TDH * sizeof(desc) >= TDLEN)
5546 TDH = 0;
5547
5548 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5549 {
5550 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5551 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5552 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5553 }
5554
5555 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5556 }
5557
5558 /// @todo uncomment: pThis->uStatIntTXQE++;
5559 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5560 /*
5561 * Release the lock.
5562 */
5563 if (pDrv)
5564 pDrv->pfnEndXmit(pDrv);
5565 e1kCsTxLeave(pThis);
5566 }
5567
5568 return rc;
5569}
5570
5571#else /* E1K_WITH_TXD_CACHE */
5572
5573static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
5574{
5575 unsigned i, cDescs = pTxdc->tdlen / sizeof(E1KTXDESC);
5576 uint32_t tdh = pTxdc->tdh;
5577 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5578 for (i = 0; i < cDescs; ++i)
5579 {
5580 E1KTXDESC desc;
5581 PDMDevHlpPCIPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5582 if (i == tdh)
5583 LogRel(("E1000: >>> "));
5584 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5585 }
5586 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5587 pThis->iTxDCurrent, pTxdc->tdh, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5588 if (tdh > pThis->iTxDCurrent)
5589 tdh -= pThis->iTxDCurrent;
5590 else
5591 tdh = cDescs + tdh - pThis->iTxDCurrent;
5592 for (i = 0; i < pThis->nTxDFetched; ++i)
5593 {
5594 if (i == pThis->iTxDCurrent)
5595 LogRel(("E1000: >>> "));
5596 if (cDescs)
5597 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5598 else
5599 LogRel(("E1000: <lost>: %R[e1ktxd]\n", &pThis->aTxDescriptors[i]));
5600 }
5601}
5602
5603/**
5604 * Transmit pending descriptors.
5605 *
5606 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5607 *
5608 * @param pDevIns The device instance.
5609 * @param pThis The E1000 state.
5610 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5611 */
5612static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5613{
5614 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5615 int rc = VINF_SUCCESS;
5616
5617 /* Check if transmitter is enabled. */
5618 if (!(TCTL & TCTL_EN))
5619 return VINF_SUCCESS;
5620 /*
5621 * Grab the xmit lock of the driver as well as the E1K device state.
5622 */
5623 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5624 if (pDrv)
5625 {
5626 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5627 if (RT_FAILURE(rc))
5628 return rc;
5629 }
5630
5631 /*
5632 * Process all pending descriptors.
5633 * Note! Do not process descriptors in locked state
5634 */
5635 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5636 if (RT_LIKELY(rc == VINF_SUCCESS && (TCTL & TCTL_EN)))
5637 {
5638 E1KTXDC txdc;
5639 bool fTxContextValid = e1kUpdateTxDContext(pDevIns, pThis, &txdc);
5640 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5641 /*
5642 * fIncomplete is set whenever we try to fetch additional descriptors
5643 * for an incomplete packet. If fail to locate a complete packet on
5644 * the next iteration we need to reset the cache or we risk to get
5645 * stuck in this loop forever.
5646 */
5647 bool fIncomplete = false;
5648 while (fTxContextValid && !pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis, &txdc))
5649 {
5650 while (e1kLocateTxPacket(pThis))
5651 {
5652 fIncomplete = false;
5653 /* Found a complete packet, allocate it. */
5654 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5655 /* If we're out of bandwidth we'll come back later. */
5656 if (RT_FAILURE(rc))
5657 goto out;
5658 /* Copy the packet to allocated buffer and send it. */
5659 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread, &txdc);
5660 /* If we're out of bandwidth we'll come back later. */
5661 if (RT_FAILURE(rc))
5662 goto out;
5663 }
5664 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5665 if (RT_UNLIKELY(fIncomplete))
5666 {
5667 static bool fTxDCacheDumped = false;
5668 /*
5669 * The descriptor cache is full, but we were unable to find
5670 * a complete packet in it. Drop the cache and hope that
5671 * the guest driver can recover from network card error.
5672 */
5673 LogRel(("%s: No complete packets in%s TxD cache! "
5674 "Fetched=%d, current=%d, TX len=%d.\n",
5675 pThis->szPrf,
5676 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5677 pThis->nTxDFetched, pThis->iTxDCurrent,
5678 e1kGetTxLen(&txdc)));
5679 if (!fTxDCacheDumped)
5680 {
5681 fTxDCacheDumped = true;
5682 e1kDumpTxDCache(pDevIns, pThis, &txdc);
5683 }
5684 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5685 /*
5686 * Returning an error at this point means Guru in R0
5687 * (see @bugref{6428}).
5688 */
5689# ifdef IN_RING3
5690 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5691# else /* !IN_RING3 */
5692 rc = VINF_IOM_R3_MMIO_WRITE;
5693# endif /* !IN_RING3 */
5694 goto out;
5695 }
5696 if (u8Remain > 0)
5697 {
5698 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5699 "%d more are available\n",
5700 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5701 e1kGetTxLen(&txdc) - u8Remain));
5702
5703 /*
5704 * A packet was partially fetched. Move incomplete packet to
5705 * the beginning of cache buffer, then load more descriptors.
5706 */
5707 memmove(pThis->aTxDescriptors,
5708 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5709 u8Remain * sizeof(E1KTXDESC));
5710 pThis->iTxDCurrent = 0;
5711 pThis->nTxDFetched = u8Remain;
5712 e1kTxDLoadMore(pDevIns, pThis, &txdc);
5713 fIncomplete = true;
5714 }
5715 else
5716 pThis->nTxDFetched = 0;
5717 pThis->iTxDCurrent = 0;
5718 }
5719 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5720 {
5721 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5722 pThis->szPrf));
5723 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5724 }
5725out:
5726 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5727
5728 /// @todo uncomment: pThis->uStatIntTXQE++;
5729 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5730
5731 e1kCsTxLeave(pThis);
5732 }
5733
5734
5735 /*
5736 * Release the lock.
5737 */
5738 if (pDrv)
5739 pDrv->pfnEndXmit(pDrv);
5740 return rc;
5741}
5742
5743#endif /* E1K_WITH_TXD_CACHE */
5744#ifdef IN_RING3
5745
5746/**
5747 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5748 */
5749static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5750{
5751 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5752 PE1KSTATE pThis = pThisCC->pShared;
5753 /* Resume suspended transmission */
5754 STATUS &= ~STATUS_TXOFF;
5755 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5756}
5757
5758/**
5759 * @callback_method_impl{FNPDMTASKDEV,
5760 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5761 * @note Not executed on EMT.
5762 */
5763static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5764{
5765 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5766 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5767
5768 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5769 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5770
5771 RT_NOREF(rc, pvUser);
5772}
5773
5774#endif /* IN_RING3 */
5775
5776/**
5777 * Write handler for Transmit Descriptor Tail register.
5778 *
5779 * @param pThis The device state structure.
5780 * @param offset Register offset in memory-mapped frame.
5781 * @param index Register index in register array.
5782 * @param value The value to store.
5783 * @param mask Used to implement partial writes (8 and 16-bit).
5784 * @thread EMT
5785 */
5786static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5787{
5788 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5789
5790 /* All descriptors starting with head and not including tail belong to us. */
5791 /* Process them. */
5792 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5793 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5794
5795 /* Compose a temporary TX context, breaking TX CS rule, for debugging purposes. */
5796 /* If we decide to transmit, the TX critical section will be entered later in e1kXmitPending(). */
5797 E1KTXDC txdc;
5798 txdc.tdlen = TDLEN;
5799 txdc.tdh = TDH;
5800 txdc.tdt = TDT;
5801 /* Ignore TDT writes when the link is down. */
5802 if (txdc.tdh != txdc.tdt && (STATUS & STATUS_LU))
5803 {
5804 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", txdc.tdh, txdc.tdt, e1kGetTxLen(&txdc)));
5805 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5806 pThis->szPrf, e1kGetTxLen(&txdc)));
5807
5808 /* Transmit pending packets if possible, defer it if we cannot do it
5809 in the current context. */
5810#ifdef E1K_TX_DELAY
5811 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5812 if (RT_LIKELY(rc == VINF_SUCCESS))
5813 {
5814 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5815 {
5816# ifdef E1K_INT_STATS
5817 pThis->u64ArmedAt = RTTimeNanoTS();
5818# endif
5819 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5820 }
5821 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5822 e1kCsTxLeave(pThis);
5823 return rc;
5824 }
5825 /* We failed to enter the TX critical section -- transmit as usual. */
5826#endif /* E1K_TX_DELAY */
5827#ifndef IN_RING3
5828 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5829 if (!pThisCC->CTX_SUFF(pDrv))
5830 {
5831 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5832 rc = VINF_SUCCESS;
5833 }
5834 else
5835#endif
5836 {
5837 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5838 if (rc == VERR_TRY_AGAIN)
5839 rc = VINF_SUCCESS;
5840#ifndef IN_RING3
5841 else if (rc == VERR_SEM_BUSY)
5842 rc = VINF_IOM_R3_MMIO_WRITE;
5843#endif
5844 AssertRC(rc);
5845 }
5846 }
5847
5848 return rc;
5849}
5850
5851/**
5852 * Write handler for Multicast Table Array registers.
5853 *
5854 * @param pThis The device state structure.
5855 * @param offset Register offset in memory-mapped frame.
5856 * @param index Register index in register array.
5857 * @param value The value to store.
5858 * @thread EMT
5859 */
5860static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5861{
5862 RT_NOREF_PV(pDevIns);
5863 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5864 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5865
5866 return VINF_SUCCESS;
5867}
5868
5869/**
5870 * Read handler for Multicast Table Array registers.
5871 *
5872 * @returns VBox status code.
5873 *
5874 * @param pThis The device state structure.
5875 * @param offset Register offset in memory-mapped frame.
5876 * @param index Register index in register array.
5877 * @thread EMT
5878 */
5879static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5880{
5881 RT_NOREF_PV(pDevIns);
5882 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5883 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5884
5885 return VINF_SUCCESS;
5886}
5887
5888/**
5889 * Write handler for Receive Address registers.
5890 *
5891 * @param pThis The device state structure.
5892 * @param offset Register offset in memory-mapped frame.
5893 * @param index Register index in register array.
5894 * @param value The value to store.
5895 * @thread EMT
5896 */
5897static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5898{
5899 RT_NOREF_PV(pDevIns);
5900 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5901 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5902
5903 return VINF_SUCCESS;
5904}
5905
5906/**
5907 * Read handler for Receive Address registers.
5908 *
5909 * @returns VBox status code.
5910 *
5911 * @param pThis The device state structure.
5912 * @param offset Register offset in memory-mapped frame.
5913 * @param index Register index in register array.
5914 * @thread EMT
5915 */
5916static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5917{
5918 RT_NOREF_PV(pDevIns);
5919 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5920 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5921
5922 return VINF_SUCCESS;
5923}
5924
5925/**
5926 * Write handler for VLAN Filter Table Array registers.
5927 *
5928 * @param pThis The device state structure.
5929 * @param offset Register offset in memory-mapped frame.
5930 * @param index Register index in register array.
5931 * @param value The value to store.
5932 * @thread EMT
5933 */
5934static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5935{
5936 RT_NOREF_PV(pDevIns);
5937 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5938 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5939
5940 return VINF_SUCCESS;
5941}
5942
5943/**
5944 * Read handler for VLAN Filter Table Array registers.
5945 *
5946 * @returns VBox status code.
5947 *
5948 * @param pThis The device state structure.
5949 * @param offset Register offset in memory-mapped frame.
5950 * @param index Register index in register array.
5951 * @thread EMT
5952 */
5953static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5954{
5955 RT_NOREF_PV(pDevIns);
5956 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5957 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5958
5959 return VINF_SUCCESS;
5960}
5961
5962/**
5963 * Read handler for unimplemented registers.
5964 *
5965 * Merely reports reads from unimplemented registers.
5966 *
5967 * @returns VBox status code.
5968 *
5969 * @param pThis The device state structure.
5970 * @param offset Register offset in memory-mapped frame.
5971 * @param index Register index in register array.
5972 * @thread EMT
5973 */
5974static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5975{
5976 RT_NOREF(pDevIns, pThis, offset, index);
5977 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5978 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5979 *pu32Value = 0;
5980
5981 return VINF_SUCCESS;
5982}
5983
5984/**
5985 * Default register read handler with automatic clear operation.
5986 *
5987 * Retrieves the value of register from register array in device state structure.
5988 * Then resets all bits.
5989 *
5990 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
5991 * done in the caller.
5992 *
5993 * @returns VBox status code.
5994 *
5995 * @param pThis The device state structure.
5996 * @param offset Register offset in memory-mapped frame.
5997 * @param index Register index in register array.
5998 * @thread EMT
5999 */
6000static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6001{
6002 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6003 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
6004 pThis->auRegs[index] = 0;
6005
6006 return rc;
6007}
6008
6009/**
6010 * Default register read handler.
6011 *
6012 * Retrieves the value of register from register array in device state structure.
6013 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
6014 *
6015 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
6016 * done in the caller.
6017 *
6018 * @returns VBox status code.
6019 *
6020 * @param pThis The device state structure.
6021 * @param offset Register offset in memory-mapped frame.
6022 * @param index Register index in register array.
6023 * @thread EMT
6024 */
6025static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6026{
6027 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
6028
6029 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6030 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
6031
6032 return VINF_SUCCESS;
6033}
6034
6035/**
6036 * Write handler for unimplemented registers.
6037 *
6038 * Merely reports writes to unimplemented registers.
6039 *
6040 * @param pThis The device state structure.
6041 * @param offset Register offset in memory-mapped frame.
6042 * @param index Register index in register array.
6043 * @param value The value to store.
6044 * @thread EMT
6045 */
6046
6047 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6048{
6049 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
6050
6051 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
6052 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6053
6054 return VINF_SUCCESS;
6055}
6056
6057/**
6058 * Default register write handler.
6059 *
6060 * Stores the value to the register array in device state structure. Only bits
6061 * corresponding to 1s both in 'writable' and 'mask' will be stored.
6062 *
6063 * @returns VBox status code.
6064 *
6065 * @param pThis The device state structure.
6066 * @param offset Register offset in memory-mapped frame.
6067 * @param index Register index in register array.
6068 * @param value The value to store.
6069 * @param mask Used to implement partial writes (8 and 16-bit).
6070 * @thread EMT
6071 */
6072
6073static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6074{
6075 RT_NOREF(pDevIns, offset);
6076
6077 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6078 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
6079 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
6080
6081 return VINF_SUCCESS;
6082}
6083
6084/**
6085 * Search register table for matching register.
6086 *
6087 * @returns Index in the register table or -1 if not found.
6088 *
6089 * @param offReg Register offset in memory-mapped region.
6090 * @thread EMT
6091 */
6092static int e1kRegLookup(uint32_t offReg)
6093{
6094
6095#if 0
6096 int index;
6097
6098 for (index = 0; index < E1K_NUM_OF_REGS; index++)
6099 {
6100 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
6101 {
6102 return index;
6103 }
6104 }
6105#else
6106 int iStart = 0;
6107 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
6108 for (;;)
6109 {
6110 int i = (iEnd - iStart) / 2 + iStart;
6111 uint32_t offCur = g_aE1kRegMap[i].offset;
6112 if (offReg < offCur)
6113 {
6114 if (i == iStart)
6115 break;
6116 iEnd = i;
6117 }
6118 else if (offReg >= offCur + g_aE1kRegMap[i].size)
6119 {
6120 i++;
6121 if (i == iEnd)
6122 break;
6123 iStart = i;
6124 }
6125 else
6126 return i;
6127 Assert(iEnd > iStart);
6128 }
6129
6130 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6131 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
6132 return (int)i;
6133
6134# ifdef VBOX_STRICT
6135 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6136 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
6137# endif
6138
6139#endif
6140
6141 return -1;
6142}
6143
6144/**
6145 * Handle unaligned register read operation.
6146 *
6147 * Looks up and calls appropriate handler.
6148 *
6149 * @returns VBox status code.
6150 *
6151 * @param pDevIns The device instance.
6152 * @param pThis The device state structure.
6153 * @param offReg Register offset in memory-mapped frame.
6154 * @param pv Where to store the result.
6155 * @param cb Number of bytes to read.
6156 * @thread EMT
6157 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
6158 * accesses we have to take care of that ourselves.
6159 */
6160static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
6161{
6162 uint32_t u32 = 0;
6163 uint32_t shift;
6164 int rc = VINF_SUCCESS;
6165 int index = e1kRegLookup(offReg);
6166#ifdef LOG_ENABLED
6167 char buf[9];
6168#endif
6169
6170 /*
6171 * From the spec:
6172 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6173 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6174 */
6175
6176 /*
6177 * To be able to read bytes and short word we convert them to properly
6178 * shifted 32-bit words and masks. The idea is to keep register-specific
6179 * handlers simple. Most accesses will be 32-bit anyway.
6180 */
6181 uint32_t mask;
6182 switch (cb)
6183 {
6184 case 4: mask = 0xFFFFFFFF; break;
6185 case 2: mask = 0x0000FFFF; break;
6186 case 1: mask = 0x000000FF; break;
6187 default:
6188 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6189 }
6190 if (index >= 0)
6191 {
6192 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6193 if (g_aE1kRegMap[index].readable)
6194 {
6195 /* Make the mask correspond to the bits we are about to read. */
6196 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6197 mask <<= shift;
6198 if (!mask)
6199 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6200 /*
6201 * Read it. Pass the mask so the handler knows what has to be read.
6202 * Mask out irrelevant bits.
6203 */
6204 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6205 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6206 return rc;
6207 //pThis->fDelayInts = false;
6208 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6209 //pThis->iStatIntLostOne = 0;
6210 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6211 u32 &= mask;
6212 //e1kCsLeave(pThis);
6213 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6214 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6215 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6216 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6217 /* Shift back the result. */
6218 u32 >>= shift;
6219 }
6220 else
6221 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6222 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6223 if (IOM_SUCCESS(rc))
6224 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6225 }
6226 else
6227 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6228 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6229
6230 memcpy(pv, &u32, cb);
6231 return rc;
6232}
6233
6234/**
6235 * Handle 4 byte aligned and sized read operation.
6236 *
6237 * Looks up and calls appropriate handler.
6238 *
6239 * @returns VBox status code.
6240 *
6241 * @param pDevIns The device instance.
6242 * @param pThis The device state structure.
6243 * @param offReg Register offset in memory-mapped frame.
6244 * @param pu32 Where to store the result.
6245 * @thread EMT
6246 */
6247static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6248{
6249 Assert(!(offReg & 3));
6250
6251 /*
6252 * Lookup the register and check that it's readable.
6253 */
6254 VBOXSTRICTRC rc = VINF_SUCCESS;
6255 int idxReg = e1kRegLookup(offReg);
6256 if (RT_LIKELY(idxReg >= 0))
6257 {
6258 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6259 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6260 {
6261 /*
6262 * Read it. Pass the mask so the handler knows what has to be read.
6263 * Mask out irrelevant bits.
6264 */
6265 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6266 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6267 // return rc;
6268 //pThis->fDelayInts = false;
6269 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6270 //pThis->iStatIntLostOne = 0;
6271 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6272 //e1kCsLeave(pThis);
6273 Log6(("%s At %08X read %08X from %s (%s)\n",
6274 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6275 if (IOM_SUCCESS(rc))
6276 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6277 }
6278 else
6279 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6280 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6281 }
6282 else
6283 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6284 return rc;
6285}
6286
6287/**
6288 * Handle 4 byte sized and aligned register write operation.
6289 *
6290 * Looks up and calls appropriate handler.
6291 *
6292 * @returns VBox status code.
6293 *
6294 * @param pDevIns The device instance.
6295 * @param pThis The device state structure.
6296 * @param offReg Register offset in memory-mapped frame.
6297 * @param u32Value The value to write.
6298 * @thread EMT
6299 */
6300static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6301{
6302 VBOXSTRICTRC rc = VINF_SUCCESS;
6303 int index = e1kRegLookup(offReg);
6304 if (RT_LIKELY(index >= 0))
6305 {
6306 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6307 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6308 {
6309 /*
6310 * Write it. Pass the mask so the handler knows what has to be written.
6311 * Mask out irrelevant bits.
6312 */
6313 Log6(("%s At %08X write %08X to %s (%s)\n",
6314 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6315 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6316 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6317 // return rc;
6318 //pThis->fDelayInts = false;
6319 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6320 //pThis->iStatIntLostOne = 0;
6321 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6322 //e1kCsLeave(pThis);
6323 }
6324 else
6325 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6326 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6327 if (IOM_SUCCESS(rc))
6328 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6329 }
6330 else
6331 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6332 pThis->szPrf, offReg, u32Value));
6333 return rc;
6334}
6335
6336
6337/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6338
6339/**
6340 * @callback_method_impl{FNIOMMMIONEWREAD}
6341 */
6342static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6343{
6344 RT_NOREF2(pvUser, cb);
6345 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6346 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6347
6348 Assert(off < E1K_MM_SIZE);
6349 Assert(cb == 4);
6350 Assert(!(off & 3));
6351
6352 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6353
6354 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6355 return rcStrict;
6356}
6357
6358/**
6359 * @callback_method_impl{FNIOMMMIONEWWRITE}
6360 */
6361static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6362{
6363 RT_NOREF2(pvUser, cb);
6364 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6365 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6366
6367 Assert(off < E1K_MM_SIZE);
6368 Assert(cb == 4);
6369 Assert(!(off & 3));
6370
6371 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6372
6373 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6374 return rcStrict;
6375}
6376
6377/**
6378 * @callback_method_impl{FNIOMIOPORTNEWIN}
6379 */
6380static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6381{
6382 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6383 VBOXSTRICTRC rc;
6384 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6385 RT_NOREF_PV(pvUser);
6386
6387 if (RT_LIKELY(cb == 4))
6388 switch (offPort)
6389 {
6390 case 0x00: /* IOADDR */
6391 *pu32 = pThis->uSelectedReg;
6392 Log9(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6393 rc = VINF_SUCCESS;
6394 break;
6395
6396 case 0x04: /* IODATA */
6397 if (!(pThis->uSelectedReg & 3))
6398 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6399 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6400 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6401 if (rc == VINF_IOM_R3_MMIO_READ)
6402 rc = VINF_IOM_R3_IOPORT_READ;
6403 Log9(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6404 break;
6405
6406 default:
6407 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6408 /** @todo r=bird: Check what real hardware returns here. */
6409 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6410 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6411 break;
6412 }
6413 else
6414 {
6415 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6416 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6417 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6418 }
6419 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6420 return rc;
6421}
6422
6423
6424/**
6425 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6426 */
6427static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6428{
6429 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6430 VBOXSTRICTRC rc;
6431 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6432 RT_NOREF_PV(pvUser);
6433
6434 Log9(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6435 if (RT_LIKELY(cb == 4))
6436 {
6437 switch (offPort)
6438 {
6439 case 0x00: /* IOADDR */
6440 pThis->uSelectedReg = u32;
6441 Log9(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6442 rc = VINF_SUCCESS;
6443 break;
6444
6445 case 0x04: /* IODATA */
6446 Log9(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6447 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6448 {
6449 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6450 if (rc == VINF_IOM_R3_MMIO_WRITE)
6451 rc = VINF_IOM_R3_IOPORT_WRITE;
6452 }
6453 else
6454 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6455 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6456 break;
6457
6458 default:
6459 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6460 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6461 }
6462 }
6463 else
6464 {
6465 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6466 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6467 }
6468
6469 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6470 return rc;
6471}
6472
6473#ifdef IN_RING3
6474
6475/**
6476 * Dump complete device state to log.
6477 *
6478 * @param pThis Pointer to device state.
6479 */
6480static void e1kDumpState(PE1KSTATE pThis)
6481{
6482 RT_NOREF(pThis);
6483 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6484 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6485# ifdef E1K_INT_STATS
6486 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6487 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6488 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6489 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6490 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6491 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6492 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6493 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6494 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6495 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6496 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6497 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6498 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6499 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6500 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6501 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6502 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6503 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6504 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6505 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6506 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6507 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6508 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6509 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6510 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6511 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6512 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6513 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6514 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6515 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6516 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6517 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6518 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6519 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6520 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6521 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6522 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6523 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6524 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6525# endif /* E1K_INT_STATS */
6526}
6527
6528
6529/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6530
6531/**
6532 * Check if the device can receive data now.
6533 * This must be called before the pfnRecieve() method is called.
6534 *
6535 * @returns Number of bytes the device can receive.
6536 * @param pDevIns The device instance.
6537 * @param pThis The instance data.
6538 * @thread EMT
6539 */
6540static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6541{
6542#ifndef E1K_WITH_RXD_CACHE
6543 size_t cb;
6544
6545 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6546 return VERR_NET_NO_BUFFER_SPACE;
6547
6548 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6549 {
6550 E1KRXDESC desc;
6551 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6552 if (desc.status.fDD)
6553 cb = 0;
6554 else
6555 cb = pThis->u16RxBSize;
6556 }
6557 else if (RDH < RDT)
6558 cb = (RDT - RDH) * pThis->u16RxBSize;
6559 else if (RDH > RDT)
6560 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6561 else
6562 {
6563 cb = 0;
6564 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6565 }
6566 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6567 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6568
6569 e1kCsRxLeave(pThis);
6570 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6571#else /* E1K_WITH_RXD_CACHE */
6572 int rc = VINF_SUCCESS;
6573
6574 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6575 return VERR_NET_NO_BUFFER_SPACE;
6576 E1KRXDC rxdc;
6577 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kCanReceive")))
6578 {
6579 e1kCsRxLeave(pThis);
6580 E1kLog(("%s e1kCanReceive: failed to update Rx context, returning VERR_NET_NO_BUFFER_SPACE\n", pThis->szPrf));
6581 return VERR_NET_NO_BUFFER_SPACE;
6582 }
6583
6584 if (RT_UNLIKELY(rxdc.rdlen == sizeof(E1KRXDESC)))
6585 {
6586 E1KRXDESC desc;
6587 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, rxdc.rdh), &desc, sizeof(desc));
6588 if (desc.status.fDD)
6589 rc = VERR_NET_NO_BUFFER_SPACE;
6590 }
6591 else if (e1kRxDIsCacheEmpty(pThis) && rxdc.rdh == rxdc.rdt)
6592 {
6593 /* Cache is empty, so is the RX ring. */
6594 rc = VERR_NET_NO_BUFFER_SPACE;
6595 }
6596 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6597 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6598 e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt, rxdc.rdlen, pThis->u16RxBSize, rc));
6599
6600 e1kCsRxLeave(pThis);
6601 return rc;
6602#endif /* E1K_WITH_RXD_CACHE */
6603}
6604
6605/**
6606 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6607 */
6608static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6609{
6610 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6611 PE1KSTATE pThis = pThisCC->pShared;
6612 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6613
6614 int rc = e1kCanReceive(pDevIns, pThis);
6615
6616 if (RT_SUCCESS(rc))
6617 return VINF_SUCCESS;
6618 if (RT_UNLIKELY(cMillies == 0))
6619 return VERR_NET_NO_BUFFER_SPACE;
6620
6621 rc = VERR_INTERRUPTED;
6622 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6623 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6624 VMSTATE enmVMState;
6625 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6626 || enmVMState == VMSTATE_RUNNING_LS))
6627 {
6628 int rc2 = e1kCanReceive(pDevIns, pThis);
6629 if (RT_SUCCESS(rc2))
6630 {
6631 rc = VINF_SUCCESS;
6632 break;
6633 }
6634 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6635 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6636 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6637 }
6638 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6639 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6640
6641 return rc;
6642}
6643
6644
6645/**
6646 * Matches the packet addresses against Receive Address table. Looks for
6647 * exact matches only.
6648 *
6649 * @returns true if address matches.
6650 * @param pThis Pointer to the state structure.
6651 * @param pvBuf The ethernet packet.
6652 * @param cb Number of bytes available in the packet.
6653 * @thread EMT
6654 */
6655static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6656{
6657 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6658 {
6659 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6660
6661 /* Valid address? */
6662 if (ra->ctl & RA_CTL_AV)
6663 {
6664 Assert((ra->ctl & RA_CTL_AS) < 2);
6665 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6666 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6667 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6668 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6669 /*
6670 * Address Select:
6671 * 00b = Destination address
6672 * 01b = Source address
6673 * 10b = Reserved
6674 * 11b = Reserved
6675 * Since ethernet header is (DA, SA, len) we can use address
6676 * select as index.
6677 */
6678 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6679 ra->addr, sizeof(ra->addr)) == 0)
6680 return true;
6681 }
6682 }
6683
6684 return false;
6685}
6686
6687/**
6688 * Matches the packet addresses against Multicast Table Array.
6689 *
6690 * @remarks This is imperfect match since it matches not exact address but
6691 * a subset of addresses.
6692 *
6693 * @returns true if address matches.
6694 * @param pThis Pointer to the state structure.
6695 * @param pvBuf The ethernet packet.
6696 * @param cb Number of bytes available in the packet.
6697 * @thread EMT
6698 */
6699static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6700{
6701 /* Get bits 32..47 of destination address */
6702 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6703
6704 unsigned offset = GET_BITS(RCTL, MO);
6705 /*
6706 * offset means:
6707 * 00b = bits 36..47
6708 * 01b = bits 35..46
6709 * 10b = bits 34..45
6710 * 11b = bits 32..43
6711 */
6712 if (offset < 3)
6713 u16Bit = u16Bit >> (4 - offset);
6714 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6715}
6716
6717/**
6718 * Determines if the packet is to be delivered to upper layer.
6719 *
6720 * The following filters supported:
6721 * - Exact Unicast/Multicast
6722 * - Promiscuous Unicast/Multicast
6723 * - Multicast
6724 * - VLAN
6725 *
6726 * @returns true if packet is intended for this node.
6727 * @param pThis Pointer to the state structure.
6728 * @param pvBuf The ethernet packet.
6729 * @param cb Number of bytes available in the packet.
6730 * @param pStatus Bit field to store status bits.
6731 * @thread EMT
6732 */
6733static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6734{
6735 Assert(cb > 14);
6736 /* Assume that we fail to pass exact filter. */
6737 pStatus->fPIF = false;
6738 pStatus->fVP = false;
6739 /* Discard oversized packets */
6740 if (cb > E1K_MAX_RX_PKT_SIZE)
6741 {
6742 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6743 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6744 E1K_INC_CNT32(ROC);
6745 return false;
6746 }
6747 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6748 {
6749 /* When long packet reception is disabled packets over 1522 are discarded */
6750 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6751 pThis->szPrf, cb));
6752 E1K_INC_CNT32(ROC);
6753 return false;
6754 }
6755
6756 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6757 /* Compare TPID with VLAN Ether Type */
6758 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6759 {
6760 pStatus->fVP = true;
6761 /* Is VLAN filtering enabled? */
6762 if (RCTL & RCTL_VFE)
6763 {
6764 /* It is 802.1q packet indeed, let's filter by VID */
6765 if (RCTL & RCTL_CFIEN)
6766 {
6767 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6768 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6769 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6770 !!(RCTL & RCTL_CFI)));
6771 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6772 {
6773 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6774 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6775 return false;
6776 }
6777 }
6778 else
6779 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6780 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6781 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6782 {
6783 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6784 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6785 return false;
6786 }
6787 }
6788 }
6789 /* Broadcast filtering */
6790 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6791 return true;
6792 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6793 if (e1kIsMulticast(pvBuf))
6794 {
6795 /* Is multicast promiscuous enabled? */
6796 if (RCTL & RCTL_MPE)
6797 return true;
6798 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6799 /* Try perfect matches first */
6800 if (e1kPerfectMatch(pThis, pvBuf))
6801 {
6802 pStatus->fPIF = true;
6803 return true;
6804 }
6805 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6806 if (e1kImperfectMatch(pThis, pvBuf))
6807 return true;
6808 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6809 }
6810 else {
6811 /* Is unicast promiscuous enabled? */
6812 if (RCTL & RCTL_UPE)
6813 return true;
6814 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6815 if (e1kPerfectMatch(pThis, pvBuf))
6816 {
6817 pStatus->fPIF = true;
6818 return true;
6819 }
6820 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6821 }
6822 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6823 return false;
6824}
6825
6826/**
6827 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6828 */
6829static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6830{
6831 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6832 PE1KSTATE pThis = pThisCC->pShared;
6833 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6834 int rc = VINF_SUCCESS;
6835
6836 /*
6837 * Drop packets if the VM is not running yet/anymore.
6838 */
6839 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6840 if ( enmVMState != VMSTATE_RUNNING
6841 && enmVMState != VMSTATE_RUNNING_LS)
6842 {
6843 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6844 return VINF_SUCCESS;
6845 }
6846
6847 /* Discard incoming packets in locked state */
6848 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6849 {
6850 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6851 return VINF_SUCCESS;
6852 }
6853
6854 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6855
6856 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6857 // return VERR_PERMISSION_DENIED;
6858
6859 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6860
6861 /* Update stats */
6862 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6863 {
6864 E1K_INC_CNT32(TPR);
6865 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6866 e1kCsLeave(pThis);
6867 }
6868 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6869 E1KRXDST status;
6870 RT_ZERO(status);
6871 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6872 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6873 if (fPassed)
6874 {
6875 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6876 }
6877 //e1kCsLeave(pThis);
6878 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6879
6880 return rc;
6881}
6882
6883
6884/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6885
6886/**
6887 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6888 */
6889static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6890{
6891 if (iLUN == 0)
6892 {
6893 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6894 *ppLed = &pThisCC->pShared->led;
6895 return VINF_SUCCESS;
6896 }
6897 return VERR_PDM_LUN_NOT_FOUND;
6898}
6899
6900
6901/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6902
6903/**
6904 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6905 */
6906static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6907{
6908 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6909 pThisCC->eeprom.getMac(pMac);
6910 return VINF_SUCCESS;
6911}
6912
6913/**
6914 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6915 */
6916static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6917{
6918 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6919 PE1KSTATE pThis = pThisCC->pShared;
6920 if (STATUS & STATUS_LU)
6921 return PDMNETWORKLINKSTATE_UP;
6922 return PDMNETWORKLINKSTATE_DOWN;
6923}
6924
6925/**
6926 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6927 */
6928static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6929{
6930 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6931 PE1KSTATE pThis = pThisCC->pShared;
6932 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6933
6934 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6935 switch (enmState)
6936 {
6937 case PDMNETWORKLINKSTATE_UP:
6938 pThis->fCableConnected = true;
6939 /* If link was down, bring it up after a while. */
6940 if (!(STATUS & STATUS_LU))
6941 e1kBringLinkUpDelayed(pDevIns, pThis);
6942 break;
6943 case PDMNETWORKLINKSTATE_DOWN:
6944 pThis->fCableConnected = false;
6945 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6946 * We might have to set the link state before the driver initializes us. */
6947 Phy::setLinkStatus(&pThis->phy, false);
6948 /* If link was up, bring it down. */
6949 if (STATUS & STATUS_LU)
6950 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6951 break;
6952 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6953 /*
6954 * There is not much sense in bringing down the link if it has not come up yet.
6955 * If it is up though, we bring it down temporarely, then bring it up again.
6956 */
6957 if (STATUS & STATUS_LU)
6958 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6959 break;
6960 default:
6961 ;
6962 }
6963 return VINF_SUCCESS;
6964}
6965
6966
6967/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6968
6969/**
6970 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6971 */
6972static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6973{
6974 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6975 Assert(&pThisCC->IBase == pInterface);
6976
6977 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6978 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6979 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6980 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6981 return NULL;
6982}
6983
6984
6985/* -=-=-=-=- Saved State -=-=-=-=- */
6986
6987/**
6988 * Saves the configuration.
6989 *
6990 * @param pThis The E1K state.
6991 * @param pSSM The handle to the saved state.
6992 */
6993static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
6994{
6995 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
6996 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
6997}
6998
6999/**
7000 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
7001 */
7002static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
7003{
7004 RT_NOREF(uPass);
7005 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
7006 return VINF_SSM_DONT_CALL_AGAIN;
7007}
7008
7009/**
7010 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
7011 */
7012static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7013{
7014 RT_NOREF(pSSM);
7015 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7016
7017 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
7018 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7019 return rc;
7020 e1kCsLeave(pThis);
7021 return VINF_SUCCESS;
7022#if 0
7023 /* 1) Prevent all threads from modifying the state and memory */
7024 //pThis->fLocked = true;
7025 /* 2) Cancel all timers */
7026#ifdef E1K_TX_DELAY
7027 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7028#endif /* E1K_TX_DELAY */
7029//#ifdef E1K_USE_TX_TIMERS
7030 if (pThis->fTidEnabled)
7031 {
7032 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
7033#ifndef E1K_NO_TAD
7034 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
7035#endif /* E1K_NO_TAD */
7036 }
7037//#endif /* E1K_USE_TX_TIMERS */
7038#ifdef E1K_USE_RX_TIMERS
7039 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
7040 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
7041#endif /* E1K_USE_RX_TIMERS */
7042 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7043 /* 3) Did I forget anything? */
7044 E1kLog(("%s Locked\n", pThis->szPrf));
7045 return VINF_SUCCESS;
7046#endif
7047}
7048
7049/**
7050 * @callback_method_impl{FNSSMDEVSAVEEXEC}
7051 */
7052static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7053{
7054 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7055 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7056 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7057
7058 e1kSaveConfig(pHlp, pThis, pSSM);
7059 pThisCC->eeprom.save(pHlp, pSSM);
7060 e1kDumpState(pThis);
7061 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
7062 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
7063 Phy::saveState(pHlp, pSSM, &pThis->phy);
7064 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
7065 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
7066 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7067 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
7068 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
7069 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
7070 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
7071 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
7072 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
7073/** @todo State wrt to the TSE buffer is incomplete, so little point in
7074 * saving this actually. */
7075 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
7076 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
7077 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
7078 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7079 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7080 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
7081 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
7082#ifdef E1K_WITH_TXD_CACHE
7083# if 0
7084 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
7085 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
7086 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7087# else
7088 /*
7089 * There is no point in storing TX descriptor cache entries as we can simply
7090 * fetch them again. Moreover, normally the cache is always empty when we
7091 * save the state. Store zero entries for compatibility.
7092 */
7093 pHlp->pfnSSMPutU8(pSSM, 0);
7094# endif
7095#endif /* E1K_WITH_TXD_CACHE */
7096/** @todo GSO requires some more state here. */
7097 E1kLog(("%s State has been saved\n", pThis->szPrf));
7098 return VINF_SUCCESS;
7099}
7100
7101#if 0
7102/**
7103 * @callback_method_impl{FNSSMDEVSAVEDONE}
7104 */
7105static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7106{
7107 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7108
7109 /* If VM is being powered off unlocking will result in assertions in PGM */
7110 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
7111 pThis->fLocked = false;
7112 else
7113 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
7114 E1kLog(("%s Unlocked\n", pThis->szPrf));
7115 return VINF_SUCCESS;
7116}
7117#endif
7118
7119/**
7120 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
7121 */
7122static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7123{
7124 RT_NOREF(pSSM);
7125 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7126
7127 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
7128 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7129 return rc;
7130 e1kCsLeave(pThis);
7131 return VINF_SUCCESS;
7132}
7133
7134/**
7135 * @callback_method_impl{FNSSMDEVLOADEXEC}
7136 */
7137static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7138{
7139 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7140 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7141 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7142 int rc;
7143
7144 if ( uVersion != E1K_SAVEDSTATE_VERSION
7145#ifdef E1K_WITH_TXD_CACHE
7146 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
7147#endif /* E1K_WITH_TXD_CACHE */
7148 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
7149 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
7150 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7151
7152 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
7153 || uPass != SSM_PASS_FINAL)
7154 {
7155 /* config checks */
7156 RTMAC macConfigured;
7157 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
7158 AssertRCReturn(rc, rc);
7159 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
7160 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
7161 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
7162
7163 E1KCHIP eChip;
7164 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
7165 AssertRCReturn(rc, rc);
7166 if (eChip != pThis->eChip)
7167 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
7168 }
7169
7170 if (uPass == SSM_PASS_FINAL)
7171 {
7172 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
7173 {
7174 rc = pThisCC->eeprom.load(pHlp, pSSM);
7175 AssertRCReturn(rc, rc);
7176 }
7177 /* the state */
7178 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7179 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7180 /** @todo PHY could be made a separate device with its own versioning */
7181 Phy::loadState(pHlp, pSSM, &pThis->phy);
7182 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7183 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7184 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7185 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7186 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7187 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7188 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7189 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7190 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7191 AssertRCReturn(rc, rc);
7192 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7193 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7194 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7195 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7196 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7197 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7198 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7199 AssertRCReturn(rc, rc);
7200 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7201 {
7202 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7203 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7204 AssertRCReturn(rc, rc);
7205 }
7206 else
7207 {
7208 pThis->fVTag = false;
7209 pThis->u16VTagTCI = 0;
7210 }
7211#ifdef E1K_WITH_TXD_CACHE
7212 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7213 {
7214 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7215 AssertRCReturn(rc, rc);
7216 if (pThis->nTxDFetched)
7217 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7218 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7219 }
7220 else
7221 pThis->nTxDFetched = 0;
7222 /**
7223 * @todo Perhaps we should not store TXD cache as the entries can be
7224 * simply fetched again from guest's memory. Or can't they?
7225 */
7226#endif /* E1K_WITH_TXD_CACHE */
7227#ifdef E1K_WITH_RXD_CACHE
7228 /*
7229 * There is no point in storing the RX descriptor cache in the saved
7230 * state, we just need to make sure it is empty.
7231 */
7232 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7233#endif /* E1K_WITH_RXD_CACHE */
7234 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7235 AssertRCReturn(rc, rc);
7236
7237 /* derived state */
7238 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7239
7240 E1kLog(("%s State has been restored\n", pThis->szPrf));
7241 e1kDumpState(pThis);
7242 }
7243 return VINF_SUCCESS;
7244}
7245
7246/**
7247 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7248 */
7249static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7250{
7251 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7252 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7253 RT_NOREF(pSSM);
7254
7255 /* Update promiscuous mode */
7256 if (pThisCC->pDrvR3)
7257 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7258
7259 /*
7260 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7261 * passed to us. We go through all this stuff if the link was up and we
7262 * wasn't teleported.
7263 */
7264 if ( (STATUS & STATUS_LU)
7265 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7266 && pThis->cMsLinkUpDelay)
7267 {
7268 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7269 }
7270 return VINF_SUCCESS;
7271}
7272
7273
7274
7275/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7276
7277/**
7278 * @callback_method_impl{FNRTSTRFORMATTYPE}
7279 */
7280static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7281 void *pvArgOutput,
7282 const char *pszType,
7283 void const *pvValue,
7284 int cchWidth,
7285 int cchPrecision,
7286 unsigned fFlags,
7287 void *pvUser)
7288{
7289 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7290 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7291 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7292 if (!pDesc)
7293 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7294
7295 size_t cbPrintf = 0;
7296 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7297 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7298 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7299 pDesc->status.fPIF ? "PIF" : "pif",
7300 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7301 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7302 pDesc->status.fVP ? "VP" : "vp",
7303 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7304 pDesc->status.fEOP ? "EOP" : "eop",
7305 pDesc->status.fDD ? "DD" : "dd",
7306 pDesc->status.fRXE ? "RXE" : "rxe",
7307 pDesc->status.fIPE ? "IPE" : "ipe",
7308 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7309 pDesc->status.fCE ? "CE" : "ce",
7310 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7311 E1K_SPEC_VLAN(pDesc->status.u16Special),
7312 E1K_SPEC_PRI(pDesc->status.u16Special));
7313 return cbPrintf;
7314}
7315
7316/**
7317 * @callback_method_impl{FNRTSTRFORMATTYPE}
7318 */
7319static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7320 void *pvArgOutput,
7321 const char *pszType,
7322 void const *pvValue,
7323 int cchWidth,
7324 int cchPrecision,
7325 unsigned fFlags,
7326 void *pvUser)
7327{
7328 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7329 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7330 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7331 if (!pDesc)
7332 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7333
7334 size_t cbPrintf = 0;
7335 switch (e1kGetDescType(pDesc))
7336 {
7337 case E1K_DTYP_CONTEXT:
7338 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7339 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7340 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7341 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7342 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7343 pDesc->context.dw2.fIDE ? " IDE":"",
7344 pDesc->context.dw2.fRS ? " RS" :"",
7345 pDesc->context.dw2.fTSE ? " TSE":"",
7346 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7347 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7348 pDesc->context.dw2.u20PAYLEN,
7349 pDesc->context.dw3.u8HDRLEN,
7350 pDesc->context.dw3.u16MSS,
7351 pDesc->context.dw3.fDD?"DD":"");
7352 break;
7353 case E1K_DTYP_DATA:
7354 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7355 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7356 pDesc->data.u64BufAddr,
7357 pDesc->data.cmd.u20DTALEN,
7358 pDesc->data.cmd.fIDE ? " IDE" :"",
7359 pDesc->data.cmd.fVLE ? " VLE" :"",
7360 pDesc->data.cmd.fRPS ? " RPS" :"",
7361 pDesc->data.cmd.fRS ? " RS" :"",
7362 pDesc->data.cmd.fTSE ? " TSE" :"",
7363 pDesc->data.cmd.fIFCS? " IFCS":"",
7364 pDesc->data.cmd.fEOP ? " EOP" :"",
7365 pDesc->data.dw3.fDD ? " DD" :"",
7366 pDesc->data.dw3.fEC ? " EC" :"",
7367 pDesc->data.dw3.fLC ? " LC" :"",
7368 pDesc->data.dw3.fTXSM? " TXSM":"",
7369 pDesc->data.dw3.fIXSM? " IXSM":"",
7370 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7371 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7372 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7373 break;
7374 case E1K_DTYP_LEGACY:
7375 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7376 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7377 pDesc->data.u64BufAddr,
7378 pDesc->legacy.cmd.u16Length,
7379 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7380 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7381 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7382 pDesc->legacy.cmd.fRS ? " RS" :"",
7383 pDesc->legacy.cmd.fIC ? " IC" :"",
7384 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7385 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7386 pDesc->legacy.dw3.fDD ? " DD" :"",
7387 pDesc->legacy.dw3.fEC ? " EC" :"",
7388 pDesc->legacy.dw3.fLC ? " LC" :"",
7389 pDesc->legacy.cmd.u8CSO,
7390 pDesc->legacy.dw3.u8CSS,
7391 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7392 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7393 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7394 break;
7395 default:
7396 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7397 break;
7398 }
7399
7400 return cbPrintf;
7401}
7402
7403/** Initializes debug helpers (logging format types). */
7404static int e1kInitDebugHelpers(void)
7405{
7406 int rc = VINF_SUCCESS;
7407 static bool s_fHelpersRegistered = false;
7408 if (!s_fHelpersRegistered)
7409 {
7410 s_fHelpersRegistered = true;
7411 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7412 AssertRCReturn(rc, rc);
7413 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7414 AssertRCReturn(rc, rc);
7415 }
7416 return rc;
7417}
7418
7419/**
7420 * Status info callback.
7421 *
7422 * @param pDevIns The device instance.
7423 * @param pHlp The output helpers.
7424 * @param pszArgs The arguments.
7425 */
7426static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7427{
7428 RT_NOREF(pszArgs);
7429 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7430 unsigned i;
7431 // bool fRcvRing = false;
7432 // bool fXmtRing = false;
7433
7434 /*
7435 * Parse args.
7436 if (pszArgs)
7437 {
7438 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7439 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7440 }
7441 */
7442
7443 /*
7444 * Show info.
7445 */
7446 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7447 pDevIns->iInstance,
7448 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7449 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7450 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7451 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7452
7453 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7454
7455 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7456 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7457
7458 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7459 {
7460 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7461 if (ra->ctl & RA_CTL_AV)
7462 {
7463 const char *pcszTmp;
7464 switch (ra->ctl & RA_CTL_AS)
7465 {
7466 case 0: pcszTmp = "DST"; break;
7467 case 1: pcszTmp = "SRC"; break;
7468 default: pcszTmp = "reserved";
7469 }
7470 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7471 }
7472 }
7473 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7474 uint32_t rdh = RDH;
7475 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7476 for (i = 0; i < cDescs; ++i)
7477 {
7478 E1KRXDESC desc;
7479 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7480 &desc, sizeof(desc));
7481 if (i == rdh)
7482 pHlp->pfnPrintf(pHlp, ">>> ");
7483 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7484 }
7485#ifdef E1K_WITH_RXD_CACHE
7486 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7487 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7488 if (rdh > pThis->iRxDCurrent)
7489 rdh -= pThis->iRxDCurrent;
7490 else
7491 rdh = cDescs + rdh - pThis->iRxDCurrent;
7492 for (i = 0; i < pThis->nRxDFetched; ++i)
7493 {
7494 if (i == pThis->iRxDCurrent)
7495 pHlp->pfnPrintf(pHlp, ">>> ");
7496 if (cDescs)
7497 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7498 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7499 &pThis->aRxDescriptors[i]);
7500 else
7501 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1krxd]\n",
7502 &pThis->aRxDescriptors[i]);
7503 }
7504#endif /* E1K_WITH_RXD_CACHE */
7505
7506 cDescs = TDLEN / sizeof(E1KTXDESC);
7507 uint32_t tdh = TDH;
7508 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7509 for (i = 0; i < cDescs; ++i)
7510 {
7511 E1KTXDESC desc;
7512 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7513 &desc, sizeof(desc));
7514 if (i == tdh)
7515 pHlp->pfnPrintf(pHlp, ">>> ");
7516 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7517 }
7518#ifdef E1K_WITH_TXD_CACHE
7519 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7520 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7521 if (tdh > pThis->iTxDCurrent)
7522 tdh -= pThis->iTxDCurrent;
7523 else
7524 tdh = cDescs + tdh - pThis->iTxDCurrent;
7525 for (i = 0; i < pThis->nTxDFetched; ++i)
7526 {
7527 if (i == pThis->iTxDCurrent)
7528 pHlp->pfnPrintf(pHlp, ">>> ");
7529 if (cDescs)
7530 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7531 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7532 &pThis->aTxDescriptors[i]);
7533 else
7534 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1ktxd]\n",
7535 &pThis->aTxDescriptors[i]);
7536 }
7537#endif /* E1K_WITH_TXD_CACHE */
7538
7539
7540#ifdef E1K_INT_STATS
7541 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7542 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7543 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7544 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7545 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7546 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7547 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7548 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7549 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7550 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7551 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7552 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7553 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7554 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7555 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7556 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7557 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7558 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7559 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7560 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7561 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7562 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7563 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7564 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7565 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7566 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7567 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7568 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7569 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7570 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7571 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7572 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7573 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7574 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7575 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7576 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7577 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7578 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7579#endif /* E1K_INT_STATS */
7580
7581 e1kCsLeave(pThis);
7582}
7583
7584
7585
7586/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7587
7588/**
7589 * Detach notification.
7590 *
7591 * One port on the network card has been disconnected from the network.
7592 *
7593 * @param pDevIns The device instance.
7594 * @param iLUN The logical unit which is being detached.
7595 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7596 */
7597static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7598{
7599 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7600 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7601 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7602 RT_NOREF(fFlags);
7603
7604 AssertLogRelReturnVoid(iLUN == 0);
7605
7606 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7607
7608 /** @todo r=pritesh still need to check if i missed
7609 * to clean something in this function
7610 */
7611
7612 /*
7613 * Zero some important members.
7614 */
7615 pThisCC->pDrvBase = NULL;
7616 pThisCC->pDrvR3 = NULL;
7617#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7618 pThisR0->pDrvR0 = NIL_RTR0PTR;
7619 pThisRC->pDrvRC = NIL_RTRCPTR;
7620#endif
7621
7622 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7623}
7624
7625/**
7626 * Attach the Network attachment.
7627 *
7628 * One port on the network card has been connected to a network.
7629 *
7630 * @returns VBox status code.
7631 * @param pDevIns The device instance.
7632 * @param iLUN The logical unit which is being attached.
7633 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7634 *
7635 * @remarks This code path is not used during construction.
7636 */
7637static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7638{
7639 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7640 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7641 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7642 RT_NOREF(fFlags);
7643
7644 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7645
7646 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7647
7648 /*
7649 * Attach the driver.
7650 */
7651 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7652 if (RT_SUCCESS(rc))
7653 {
7654 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7655 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7656 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7657 if (RT_SUCCESS(rc))
7658 {
7659#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7660 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7661 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7662#endif
7663 }
7664 }
7665 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7666 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7667 {
7668 /* This should never happen because this function is not called
7669 * if there is no driver to attach! */
7670 Log(("%s No attached driver!\n", pThis->szPrf));
7671 }
7672
7673 /*
7674 * Temporary set the link down if it was up so that the guest will know
7675 * that we have change the configuration of the network card
7676 */
7677 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7678 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7679
7680 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7681 return rc;
7682}
7683
7684/**
7685 * @copydoc FNPDMDEVPOWEROFF
7686 */
7687static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7688{
7689 /* Poke thread waiting for buffer space. */
7690 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7691}
7692
7693/**
7694 * @copydoc FNPDMDEVRESET
7695 */
7696static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7697{
7698 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7699 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7700#ifdef E1K_TX_DELAY
7701 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7702#endif /* E1K_TX_DELAY */
7703 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7704 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7705 e1kXmitFreeBuf(pThis, pThisCC);
7706 pThis->u16TxPktLen = 0;
7707 pThis->fIPcsum = false;
7708 pThis->fTCPcsum = false;
7709 pThis->fIntMaskUsed = false;
7710 pThis->fDelayInts = false;
7711 pThis->fLocked = false;
7712 pThis->u64AckedAt = 0;
7713 e1kR3HardReset(pDevIns, pThis, pThisCC);
7714}
7715
7716/**
7717 * @copydoc FNPDMDEVSUSPEND
7718 */
7719static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7720{
7721 /* Poke thread waiting for buffer space. */
7722 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7723}
7724
7725/**
7726 * Device relocation callback.
7727 *
7728 * When this callback is called the device instance data, and if the
7729 * device have a GC component, is being relocated, or/and the selectors
7730 * have been changed. The device must use the chance to perform the
7731 * necessary pointer relocations and data updates.
7732 *
7733 * Before the GC code is executed the first time, this function will be
7734 * called with a 0 delta so GC pointer calculations can be one in one place.
7735 *
7736 * @param pDevIns Pointer to the device instance.
7737 * @param offDelta The relocation delta relative to the old location.
7738 *
7739 * @remark A relocation CANNOT fail.
7740 */
7741static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7742{
7743 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7744 if (pThisRC)
7745 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7746 RT_NOREF(offDelta);
7747}
7748
7749/**
7750 * Destruct a device instance.
7751 *
7752 * We need to free non-VM resources only.
7753 *
7754 * @returns VBox status code.
7755 * @param pDevIns The device instance data.
7756 * @thread EMT
7757 */
7758static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7759{
7760 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7761 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7762
7763 e1kDumpState(pThis);
7764 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7765 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7766 {
7767 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7768 {
7769 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7770 RTThreadYield();
7771 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7772 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7773 }
7774#ifdef E1K_WITH_TX_CS
7775 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7776#endif /* E1K_WITH_TX_CS */
7777 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7778 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7779 }
7780 return VINF_SUCCESS;
7781}
7782
7783
7784/**
7785 * Set PCI configuration space registers.
7786 *
7787 * @param pci Reference to PCI device structure.
7788 * @thread EMT
7789 */
7790static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7791{
7792 Assert(eChip < RT_ELEMENTS(g_aChips));
7793 /* Configure PCI Device, assume 32-bit mode ******************************/
7794 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7795 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7796 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7797 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7798
7799 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7800 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7801 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7802 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7803 /* Stepping A2 */
7804 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7805 /* Ethernet adapter */
7806 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7807 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7808 /* normal single function Ethernet controller */
7809 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7810 /* Memory Register Base Address */
7811 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7812 /* Memory Flash Base Address */
7813 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7814 /* IO Register Base Address */
7815 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7816 /* Expansion ROM Base Address */
7817 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7818 /* Capabilities Pointer */
7819 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7820 /* Interrupt Pin: INTA# */
7821 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7822 /* Max_Lat/Min_Gnt: very high priority and time slice */
7823 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7824 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7825
7826 /* PCI Power Management Registers ****************************************/
7827 /* Capability ID: PCI Power Management Registers */
7828 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7829 /* Next Item Pointer: PCI-X */
7830 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7831 /* Power Management Capabilities: PM disabled, DSI */
7832 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7833 0x0002 | VBOX_PCI_PM_CAP_DSI);
7834 /* Power Management Control / Status Register: PM disabled */
7835 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7836 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7837 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7838 /* Data Register: PM disabled, always 0 */
7839 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7840
7841 /* PCI-X Configuration Registers *****************************************/
7842 /* Capability ID: PCI-X Configuration Registers */
7843 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7844#ifdef E1K_WITH_MSI
7845 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7846#else
7847 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7848 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7849#endif
7850 /* PCI-X Command: Enable Relaxed Ordering */
7851 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7852 /* PCI-X Status: 32-bit, 66MHz*/
7853 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7854 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7855}
7856
7857/**
7858 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7859 */
7860static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7861{
7862 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7863 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7864 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7865 int rc;
7866
7867 /*
7868 * Initialize the instance data (state).
7869 * Note! Caller has initialized it to ZERO already.
7870 */
7871 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7872 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7873 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7874 pThis->u16TxPktLen = 0;
7875 pThis->fIPcsum = false;
7876 pThis->fTCPcsum = false;
7877 pThis->fIntMaskUsed = false;
7878 pThis->fDelayInts = false;
7879 pThis->fLocked = false;
7880 pThis->u64AckedAt = 0;
7881 pThis->led.u32Magic = PDMLED_MAGIC;
7882 pThis->u32PktNo = 1;
7883
7884 pThisCC->pDevInsR3 = pDevIns;
7885 pThisCC->pShared = pThis;
7886
7887 /* Interfaces */
7888 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7889
7890 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7891 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7892 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7893
7894 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7895
7896 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7897 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7898 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7899
7900 /*
7901 * Internal validations.
7902 */
7903 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7904 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7905 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7906 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7907 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7908 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7909 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7910 VERR_INTERNAL_ERROR_4);
7911
7912 /*
7913 * Validate configuration.
7914 */
7915 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7916 "MAC|"
7917 "CableConnected|"
7918 "AdapterType|"
7919 "LineSpeed|"
7920 "ItrEnabled|"
7921 "ItrRxEnabled|"
7922 "EthernetCRC|"
7923 "GSOEnabled|"
7924 "LinkUpDelay|"
7925 "StatNo",
7926 "");
7927
7928 /** @todo LineSpeed unused! */
7929
7930 /*
7931 * Get config params
7932 */
7933 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7934 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7935 if (RT_FAILURE(rc))
7936 return PDMDEV_SET_ERROR(pDevIns, rc,
7937 N_("Configuration error: Failed to get MAC address"));
7938 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7939 if (RT_FAILURE(rc))
7940 return PDMDEV_SET_ERROR(pDevIns, rc,
7941 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7942 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7943 if (RT_FAILURE(rc))
7944 return PDMDEV_SET_ERROR(pDevIns, rc,
7945 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7946 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7947
7948 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7949 if (RT_FAILURE(rc))
7950 return PDMDEV_SET_ERROR(pDevIns, rc,
7951 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7952
7953 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7954 if (RT_FAILURE(rc))
7955 return PDMDEV_SET_ERROR(pDevIns, rc,
7956 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7957
7958 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7959 if (RT_FAILURE(rc))
7960 return PDMDEV_SET_ERROR(pDevIns, rc,
7961 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7962
7963 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7964 if (RT_FAILURE(rc))
7965 return PDMDEV_SET_ERROR(pDevIns, rc,
7966 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7967
7968 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7969 if (RT_FAILURE(rc))
7970 return PDMDEV_SET_ERROR(pDevIns, rc,
7971 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7972
7973 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7974 if (RT_FAILURE(rc))
7975 return PDMDEV_SET_ERROR(pDevIns, rc,
7976 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7977 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7978 if (pThis->cMsLinkUpDelay > 5000)
7979 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7980 else if (pThis->cMsLinkUpDelay == 0)
7981 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7982
7983 uint32_t uStatNo = (uint32_t)iInstance;
7984 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7985 if (RT_FAILURE(rc))
7986 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7987
7988 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7989 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
7990 pThis->fEthernetCRC ? "on" : "off",
7991 pThis->fGSOEnabled ? "enabled" : "disabled",
7992 pThis->fItrEnabled ? "enabled" : "disabled",
7993 pThis->fItrRxEnabled ? "enabled" : "disabled",
7994 pThis->fTidEnabled ? "enabled" : "disabled",
7995 pDevIns->fR0Enabled ? "enabled" : "disabled",
7996 pDevIns->fRCEnabled ? "enabled" : "disabled"));
7997
7998 /*
7999 * Initialize sub-components and register everything with the VMM.
8000 */
8001
8002 /* Initialize the EEPROM. */
8003 pThisCC->eeprom.init(pThis->macConfigured);
8004
8005 /* Initialize internal PHY. */
8006 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
8007
8008 /* Initialize critical sections. We do our own locking. */
8009 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8010 AssertRCReturn(rc, rc);
8011
8012 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
8013 AssertRCReturn(rc, rc);
8014 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
8015 AssertRCReturn(rc, rc);
8016#ifdef E1K_WITH_TX_CS
8017 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
8018 AssertRCReturn(rc, rc);
8019#endif
8020
8021 /* Saved state registration. */
8022 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
8023 NULL, e1kLiveExec, NULL,
8024 e1kSavePrep, e1kSaveExec, NULL,
8025 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
8026 AssertRCReturn(rc, rc);
8027
8028 /* Set PCI config registers and register ourselves with the PCI bus. */
8029 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
8030 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
8031 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
8032 AssertRCReturn(rc, rc);
8033
8034#ifdef E1K_WITH_MSI
8035 PDMMSIREG MsiReg;
8036 RT_ZERO(MsiReg);
8037 MsiReg.cMsiVectors = 1;
8038 MsiReg.iMsiCapOffset = 0x80;
8039 MsiReg.iMsiNextOffset = 0x0;
8040 MsiReg.fMsi64bit = false;
8041 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
8042 AssertRCReturn(rc, rc);
8043#endif
8044
8045 /*
8046 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
8047 * From the spec (regarding flags):
8048 * For registers that should be accessed as 32-bit double words,
8049 * partial writes (less than a 32-bit double word) is ignored.
8050 * Partial reads return all 32 bits of data regardless of the
8051 * byte enables.
8052 */
8053 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
8054 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
8055 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
8056 AssertRCReturn(rc, rc);
8057 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
8058 AssertRCReturn(rc, rc);
8059
8060 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
8061 static IOMIOPORTDESC const s_aExtDescs[] =
8062 {
8063 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8064 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8065 { NULL, NULL, NULL, NULL }
8066 };
8067 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
8068 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
8069 AssertRCReturn(rc, rc);
8070 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
8071 AssertRCReturn(rc, rc);
8072
8073 /* Create transmit queue */
8074 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
8075 AssertRCReturn(rc, rc);
8076
8077#ifdef E1K_TX_DELAY
8078 /* Create Transmit Delay Timer */
8079 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis,
8080 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Delay", &pThis->hTXDTimer);
8081 AssertRCReturn(rc, rc);
8082 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
8083 AssertRCReturn(rc, rc);
8084#endif /* E1K_TX_DELAY */
8085
8086//#ifdef E1K_USE_TX_TIMERS
8087 if (pThis->fTidEnabled)
8088 {
8089 /* Create Transmit Interrupt Delay Timer */
8090 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis,
8091 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit IRQ Delay", &pThis->hTIDTimer);
8092 AssertRCReturn(rc, rc);
8093
8094# ifndef E1K_NO_TAD
8095 /* Create Transmit Absolute Delay Timer */
8096 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis,
8097 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Abs Delay", &pThis->hTADTimer);
8098 AssertRCReturn(rc, rc);
8099# endif /* E1K_NO_TAD */
8100 }
8101//#endif /* E1K_USE_TX_TIMERS */
8102
8103#ifdef E1K_USE_RX_TIMERS
8104 /* Create Receive Interrupt Delay Timer */
8105 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis,
8106 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv IRQ Delay", &pThis->hRIDTimer);
8107 AssertRCReturn(rc, rc);
8108
8109 /* Create Receive Absolute Delay Timer */
8110 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis,
8111 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv Abs Delay", &pThis->hRADTimer);
8112 AssertRCReturn(rc, rc);
8113#endif /* E1K_USE_RX_TIMERS */
8114
8115 /* Create Late Interrupt Timer */
8116 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis,
8117 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Late IRQ", &pThis->hIntTimer);
8118 AssertRCReturn(rc, rc);
8119
8120 /* Create Link Up Timer */
8121 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis,
8122 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Link Up", &pThis->hLUTimer);
8123 AssertRCReturn(rc, rc);
8124
8125 /* Register the info item */
8126 char szTmp[20];
8127 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
8128 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
8129
8130 /* Status driver */
8131 PPDMIBASE pBase;
8132 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
8133 if (RT_FAILURE(rc))
8134 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
8135 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8136
8137 /* Network driver */
8138 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
8139 if (RT_SUCCESS(rc))
8140 {
8141 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
8142 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
8143
8144#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
8145 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
8146 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
8147#endif
8148 }
8149 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
8150 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
8151 {
8152 /* No error! */
8153 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
8154 }
8155 else
8156 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
8157
8158 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
8159 AssertRCReturn(rc, rc);
8160
8161 rc = e1kInitDebugHelpers();
8162 AssertRCReturn(rc, rc);
8163
8164 e1kR3HardReset(pDevIns, pThis, pThisCC);
8165
8166 /*
8167 * Register statistics.
8168 * The /Public/ bits are official and used by session info in the GUI.
8169 */
8170 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8171 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
8172 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8173 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
8174 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8175 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
8176
8177 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
8178 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
8179
8180#if defined(VBOX_WITH_STATISTICS)
8181 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
8182 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
8183 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
8184 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
8185 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8186 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8187 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8188 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8189 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8190 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8191 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8192 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8193 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8194 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8195 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8196 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8197 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8198 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8199 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8200 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8201 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8202 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8203 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8204 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8205 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8206
8207 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8208 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8209 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8210 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8211 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8212 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8213 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8214 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8215 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8216 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8217 {
8218 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8219 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8220 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8221 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8222 }
8223#endif /* VBOX_WITH_STATISTICS */
8224
8225#ifdef E1K_INT_STATS
8226 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8227 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8228 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8229 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8230 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8231 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8232 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8233 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8234 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8235 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8236 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8237 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8238 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8239 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8240 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8241 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8242 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8243 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8244 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8245 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8246 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8247 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8248 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8249 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8250 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8251 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8252 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8253 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8254 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8255 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8256 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8257 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8258 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8259 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8260 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8261 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8262 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8263 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8264 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8265 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8266 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8267#endif /* E1K_INT_STATS */
8268
8269 return VINF_SUCCESS;
8270}
8271
8272#else /* !IN_RING3 */
8273
8274/**
8275 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8276 */
8277static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8278{
8279 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8280 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8281 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8282
8283 /* Initialize context specific state data: */
8284 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8285 /** @todo @bugref{9218} ring-0 driver stuff */
8286 pThisCC->CTX_SUFF(pDrv) = NULL;
8287 pThisCC->CTX_SUFF(pTxSg) = NULL;
8288
8289 /* Configure critical sections the same way: */
8290 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8291 AssertRCReturn(rc, rc);
8292
8293 /* Set up MMIO and I/O port callbacks for this context: */
8294 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8295 AssertRCReturn(rc, rc);
8296
8297 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8298 AssertRCReturn(rc, rc);
8299
8300 return VINF_SUCCESS;
8301}
8302
8303#endif /* !IN_RING3 */
8304
8305/**
8306 * The device registration structure.
8307 */
8308const PDMDEVREG g_DeviceE1000 =
8309{
8310 /* .u32version = */ PDM_DEVREG_VERSION,
8311 /* .uReserved0 = */ 0,
8312 /* .szName = */ "e1000",
8313 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8314 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8315 /* .cMaxInstances = */ ~0U,
8316 /* .uSharedVersion = */ 42,
8317 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8318 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8319 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8320 /* .cMaxPciDevices = */ 1,
8321 /* .cMaxMsixVectors = */ 0,
8322 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8323#if defined(IN_RING3)
8324 /* .pszRCMod = */ "VBoxDDRC.rc",
8325 /* .pszR0Mod = */ "VBoxDDR0.r0",
8326 /* .pfnConstruct = */ e1kR3Construct,
8327 /* .pfnDestruct = */ e1kR3Destruct,
8328 /* .pfnRelocate = */ e1kR3Relocate,
8329 /* .pfnMemSetup = */ NULL,
8330 /* .pfnPowerOn = */ NULL,
8331 /* .pfnReset = */ e1kR3Reset,
8332 /* .pfnSuspend = */ e1kR3Suspend,
8333 /* .pfnResume = */ NULL,
8334 /* .pfnAttach = */ e1kR3Attach,
8335 /* .pfnDeatch = */ e1kR3Detach,
8336 /* .pfnQueryInterface = */ NULL,
8337 /* .pfnInitComplete = */ NULL,
8338 /* .pfnPowerOff = */ e1kR3PowerOff,
8339 /* .pfnSoftReset = */ NULL,
8340 /* .pfnReserved0 = */ NULL,
8341 /* .pfnReserved1 = */ NULL,
8342 /* .pfnReserved2 = */ NULL,
8343 /* .pfnReserved3 = */ NULL,
8344 /* .pfnReserved4 = */ NULL,
8345 /* .pfnReserved5 = */ NULL,
8346 /* .pfnReserved6 = */ NULL,
8347 /* .pfnReserved7 = */ NULL,
8348#elif defined(IN_RING0)
8349 /* .pfnEarlyConstruct = */ NULL,
8350 /* .pfnConstruct = */ e1kRZConstruct,
8351 /* .pfnDestruct = */ NULL,
8352 /* .pfnFinalDestruct = */ NULL,
8353 /* .pfnRequest = */ NULL,
8354 /* .pfnReserved0 = */ NULL,
8355 /* .pfnReserved1 = */ NULL,
8356 /* .pfnReserved2 = */ NULL,
8357 /* .pfnReserved3 = */ NULL,
8358 /* .pfnReserved4 = */ NULL,
8359 /* .pfnReserved5 = */ NULL,
8360 /* .pfnReserved6 = */ NULL,
8361 /* .pfnReserved7 = */ NULL,
8362#elif defined(IN_RC)
8363 /* .pfnConstruct = */ e1kRZConstruct,
8364 /* .pfnReserved0 = */ NULL,
8365 /* .pfnReserved1 = */ NULL,
8366 /* .pfnReserved2 = */ NULL,
8367 /* .pfnReserved3 = */ NULL,
8368 /* .pfnReserved4 = */ NULL,
8369 /* .pfnReserved5 = */ NULL,
8370 /* .pfnReserved6 = */ NULL,
8371 /* .pfnReserved7 = */ NULL,
8372#else
8373# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8374#endif
8375 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8376};
8377
8378#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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