VirtualBox

source: vbox/trunk/src/VBox/Devices/Network/DevE1000.cpp@ 89825

Last change on this file since 89825 was 89588, checked in by vboxsync, 3 years ago

Intel IOMMU: bugref:9967 DevE1000: Avoid including local macros defines (esp. without a fairly unique prefix) to avoid potential conflicts when testing device struct size/alignment which includes code/headers from other devices.
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1/* $Id: DevE1000.cpp 89588 2021-06-10 08:39:50Z vboxsync $ */
2/** @file
3 * DevE1000 - Intel 82540EM Ethernet Controller Emulation.
4 *
5 * Implemented in accordance with the specification:
6 *
7 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
8 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
9 *
10 * 317453-002 Revision 3.5
11 *
12 * @todo IPv6 checksum offloading support
13 * @todo Flexible Filter / Wakeup (optional?)
14 */
15
16/*
17 * Copyright (C) 2007-2020 Oracle Corporation
18 *
19 * This file is part of VirtualBox Open Source Edition (OSE), as
20 * available from http://www.virtualbox.org. This file is free software;
21 * you can redistribute it and/or modify it under the terms of the GNU
22 * General Public License (GPL) as published by the Free Software
23 * Foundation, in version 2 as it comes in the "COPYING" file of the
24 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
25 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_E1000
33#include <iprt/crc.h>
34#include <iprt/ctype.h>
35#include <iprt/net.h>
36#include <iprt/semaphore.h>
37#include <iprt/string.h>
38#include <iprt/time.h>
39#include <iprt/uuid.h>
40#include <VBox/vmm/pdmdev.h>
41#include <VBox/vmm/pdmnetifs.h>
42#include <VBox/vmm/pdmnetinline.h>
43#include <VBox/param.h>
44#include "VBoxDD.h"
45
46#include "DevEEPROM.h"
47#include "DevE1000Phy.h"
48
49
50/*********************************************************************************************************************************
51* Defined Constants And Macros *
52*********************************************************************************************************************************/
53/** @name E1000 Build Options
54 * @{ */
55/** @def E1K_INIT_RA0
56 * E1K_INIT_RA0 forces E1000 to set the first entry in Receive Address filter
57 * table to MAC address obtained from CFGM. Most guests read MAC address from
58 * EEPROM and write it to RA[0] explicitly, but Mac OS X seems to depend on it
59 * being already set (see @bugref{4657}).
60 */
61#define E1K_INIT_RA0
62/** @def E1K_LSC_ON_RESET
63 * E1K_LSC_ON_RESET causes e1000 to generate Link Status Change
64 * interrupt after hard reset. This makes the E1K_LSC_ON_SLU option unnecessary.
65 * With unplugged cable, LSC is triggerred for 82543GC only.
66 */
67#define E1K_LSC_ON_RESET
68/** @def E1K_LSC_ON_SLU
69 * E1K_LSC_ON_SLU causes E1000 to generate Link Status Change interrupt when
70 * the guest driver brings up the link via STATUS.LU bit. Again the only guest
71 * that requires it is Mac OS X (see @bugref{4657}).
72 */
73//#define E1K_LSC_ON_SLU
74/** @def E1K_INIT_LINKUP_DELAY
75 * E1K_INIT_LINKUP_DELAY prevents the link going up while the driver is still
76 * in init (see @bugref{8624}).
77 */
78#define E1K_INIT_LINKUP_DELAY_US (2000 * 1000)
79/** @def E1K_IMS_INT_DELAY_NS
80 * E1K_IMS_INT_DELAY_NS prevents interrupt storms in Windows guests on enabling
81 * interrupts (see @bugref{8624}).
82 */
83#define E1K_IMS_INT_DELAY_NS 100
84/** @def E1K_TX_DELAY
85 * E1K_TX_DELAY aims to improve guest-host transfer rate for TCP streams by
86 * preventing packets to be sent immediately. It allows to send several
87 * packets in a batch reducing the number of acknowledgments. Note that it
88 * effectively disables R0 TX path, forcing sending in R3.
89 */
90//#define E1K_TX_DELAY 150
91/** @def E1K_USE_TX_TIMERS
92 * E1K_USE_TX_TIMERS aims to reduce the number of generated TX interrupts if a
93 * guest driver set the delays via the Transmit Interrupt Delay Value (TIDV)
94 * register. Enabling it showed no positive effects on existing guests so it
95 * stays disabled. See sections 3.2.7.1 and 3.4.3.1 in "8254x Family of Gigabit
96 * Ethernet Controllers Software Developer’s Manual" for more detailed
97 * explanation.
98 */
99//#define E1K_USE_TX_TIMERS
100/** @def E1K_NO_TAD
101 * E1K_NO_TAD disables one of two timers enabled by E1K_USE_TX_TIMERS, the
102 * Transmit Absolute Delay time. This timer sets the maximum time interval
103 * during which TX interrupts can be postponed (delayed). It has no effect
104 * if E1K_USE_TX_TIMERS is not defined.
105 */
106//#define E1K_NO_TAD
107/** @def E1K_REL_DEBUG
108 * E1K_REL_DEBUG enables debug logging of l1, l2, l3 in release build.
109 */
110//#define E1K_REL_DEBUG
111/** @def E1K_INT_STATS
112 * E1K_INT_STATS enables collection of internal statistics used for
113 * debugging of delayed interrupts, etc.
114 */
115#define E1K_INT_STATS
116/** @def E1K_WITH_MSI
117 * E1K_WITH_MSI enables rudimentary MSI support. Not implemented.
118 */
119//#define E1K_WITH_MSI
120/** @def E1K_WITH_TX_CS
121 * E1K_WITH_TX_CS protects e1kXmitPending with a critical section.
122 */
123#define E1K_WITH_TX_CS
124/** @def E1K_WITH_TXD_CACHE
125 * E1K_WITH_TXD_CACHE causes E1000 to fetch multiple TX descriptors in a
126 * single physical memory read (or two if it wraps around the end of TX
127 * descriptor ring). It is required for proper functioning of bandwidth
128 * resource control as it allows to compute exact sizes of packets prior
129 * to allocating their buffers (see @bugref{5582}).
130 */
131#define E1K_WITH_TXD_CACHE
132/** @def E1K_WITH_RXD_CACHE
133 * E1K_WITH_RXD_CACHE causes E1000 to fetch multiple RX descriptors in a
134 * single physical memory read (or two if it wraps around the end of RX
135 * descriptor ring). Intel's packet driver for DOS needs this option in
136 * order to work properly (see @bugref{6217}).
137 */
138#define E1K_WITH_RXD_CACHE
139/** @def E1K_WITH_PREREG_MMIO
140 * E1K_WITH_PREREG_MMIO enables a new style MMIO registration and is
141 * currently only done for testing the relateted PDM, IOM and PGM code. */
142//#define E1K_WITH_PREREG_MMIO
143/* @} */
144/* End of Options ************************************************************/
145
146#ifdef E1K_WITH_TXD_CACHE
147/**
148 * E1K_TXD_CACHE_SIZE specifies the maximum number of TX descriptors stored
149 * in the state structure. It limits the amount of descriptors loaded in one
150 * batch read. For example, Linux guest may use up to 20 descriptors per
151 * TSE packet. The largest TSE packet seen (Windows guest) was 45 descriptors.
152 */
153# define E1K_TXD_CACHE_SIZE 64u
154#endif /* E1K_WITH_TXD_CACHE */
155
156#ifdef E1K_WITH_RXD_CACHE
157/**
158 * E1K_RXD_CACHE_SIZE specifies the maximum number of RX descriptors stored
159 * in the state structure. It limits the amount of descriptors loaded in one
160 * batch read. For example, XP guest adds 15 RX descriptors at a time.
161 */
162# define E1K_RXD_CACHE_SIZE 16u
163#endif /* E1K_WITH_RXD_CACHE */
164
165
166/* Little helpers ************************************************************/
167#undef htons
168#undef ntohs
169#undef htonl
170#undef ntohl
171#define htons(x) ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8))
172#define ntohs(x) htons(x)
173#define htonl(x) ASMByteSwapU32(x)
174#define ntohl(x) htonl(x)
175
176#ifndef DEBUG
177# ifdef E1K_REL_DEBUG
178# define DEBUG
179# define E1kLog(a) LogRel(a)
180# define E1kLog2(a) LogRel(a)
181# define E1kLog3(a) LogRel(a)
182# define E1kLogX(x, a) LogRel(a)
183//# define E1kLog3(a) do {} while (0)
184# else
185# define E1kLog(a) do {} while (0)
186# define E1kLog2(a) do {} while (0)
187# define E1kLog3(a) do {} while (0)
188# define E1kLogX(x, a) do {} while (0)
189# endif
190#else
191# define E1kLog(a) Log(a)
192# define E1kLog2(a) Log2(a)
193# define E1kLog3(a) Log3(a)
194# define E1kLogX(x, a) LogIt(x, LOG_GROUP, a)
195//# define E1kLog(a) do {} while (0)
196//# define E1kLog2(a) do {} while (0)
197//# define E1kLog3(a) do {} while (0)
198#endif
199
200#if 0
201# define LOG_ENABLED
202# define E1kLogRel(a) LogRel(a)
203# undef Log6
204# define Log6(a) LogRel(a)
205#else
206# define E1kLogRel(a) do { } while (0)
207#endif
208
209//#undef DEBUG
210
211#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
212
213#define E1K_INC_CNT32(cnt) \
214do { \
215 if (cnt < UINT32_MAX) \
216 cnt++; \
217} while (0)
218
219#define E1K_ADD_CNT64(cntLo, cntHi, val) \
220do { \
221 uint64_t u64Cnt = RT_MAKE_U64(cntLo, cntHi); \
222 uint64_t tmp = u64Cnt; \
223 u64Cnt += val; \
224 if (tmp > u64Cnt ) \
225 u64Cnt = UINT64_MAX; \
226 cntLo = (uint32_t)u64Cnt; \
227 cntHi = (uint32_t)(u64Cnt >> 32); \
228} while (0)
229
230#ifdef E1K_INT_STATS
231# define E1K_INC_ISTAT_CNT(cnt) do { ++cnt; } while (0)
232#else /* E1K_INT_STATS */
233# define E1K_INC_ISTAT_CNT(cnt) do { } while (0)
234#endif /* E1K_INT_STATS */
235
236
237/*****************************************************************************/
238
239typedef uint32_t E1KCHIP;
240#define E1K_CHIP_82540EM 0
241#define E1K_CHIP_82543GC 1
242#define E1K_CHIP_82545EM 2
243
244#ifdef IN_RING3
245/** Different E1000 chips. */
246static const struct E1kChips
247{
248 uint16_t uPCIVendorId;
249 uint16_t uPCIDeviceId;
250 uint16_t uPCISubsystemVendorId;
251 uint16_t uPCISubsystemId;
252 const char *pcszName;
253} g_aChips[] =
254{
255 /* Vendor Device SSVendor SubSys Name */
256 { 0x8086,
257 /* Temporary code, as MSI-aware driver dislike 0x100E. How to do that right? */
258# ifdef E1K_WITH_MSI
259 0x105E,
260# else
261 0x100E,
262# endif
263 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
264 { 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
265 { 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
266};
267#endif /* IN_RING3 */
268
269
270/* The size of register area mapped to I/O space */
271#define E1K_IOPORT_SIZE 0x8
272/* The size of memory-mapped register area */
273#define E1K_MM_SIZE 0x20000
274
275#define E1K_MAX_TX_PKT_SIZE 16288
276#define E1K_MAX_RX_PKT_SIZE 16384
277
278/*****************************************************************************/
279
280#ifndef VBOX_DEVICE_STRUCT_TESTCASE
281/** Gets the specfieid bits from the register. */
282#define GET_BITS(reg, bits) ((reg & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
283#define GET_BITS_V(val, reg, bits) ((val & reg##_##bits##_MASK) >> reg##_##bits##_SHIFT)
284#define BITS(reg, bits, bitval) (bitval << reg##_##bits##_SHIFT)
285#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
286#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
287
288#define CTRL_SLU UINT32_C(0x00000040)
289#define CTRL_MDIO UINT32_C(0x00100000)
290#define CTRL_MDC UINT32_C(0x00200000)
291#define CTRL_MDIO_DIR UINT32_C(0x01000000)
292#define CTRL_MDC_DIR UINT32_C(0x02000000)
293#define CTRL_RESET UINT32_C(0x04000000)
294#define CTRL_VME UINT32_C(0x40000000)
295
296#define STATUS_LU UINT32_C(0x00000002)
297#define STATUS_TXOFF UINT32_C(0x00000010)
298
299#define EECD_EE_WIRES UINT32_C(0x0F)
300#define EECD_EE_REQ UINT32_C(0x40)
301#define EECD_EE_GNT UINT32_C(0x80)
302
303#define EERD_START UINT32_C(0x00000001)
304#define EERD_DONE UINT32_C(0x00000010)
305#define EERD_DATA_MASK UINT32_C(0xFFFF0000)
306#define EERD_DATA_SHIFT 16
307#define EERD_ADDR_MASK UINT32_C(0x0000FF00)
308#define EERD_ADDR_SHIFT 8
309
310#define MDIC_DATA_MASK UINT32_C(0x0000FFFF)
311#define MDIC_DATA_SHIFT 0
312#define MDIC_REG_MASK UINT32_C(0x001F0000)
313#define MDIC_REG_SHIFT 16
314#define MDIC_PHY_MASK UINT32_C(0x03E00000)
315#define MDIC_PHY_SHIFT 21
316#define MDIC_OP_WRITE UINT32_C(0x04000000)
317#define MDIC_OP_READ UINT32_C(0x08000000)
318#define MDIC_READY UINT32_C(0x10000000)
319#define MDIC_INT_EN UINT32_C(0x20000000)
320#define MDIC_ERROR UINT32_C(0x40000000)
321
322#define TCTL_EN UINT32_C(0x00000002)
323#define TCTL_PSP UINT32_C(0x00000008)
324
325#define RCTL_EN UINT32_C(0x00000002)
326#define RCTL_UPE UINT32_C(0x00000008)
327#define RCTL_MPE UINT32_C(0x00000010)
328#define RCTL_LPE UINT32_C(0x00000020)
329#define RCTL_LBM_MASK UINT32_C(0x000000C0)
330#define RCTL_LBM_SHIFT 6
331#define RCTL_RDMTS_MASK UINT32_C(0x00000300)
332#define RCTL_RDMTS_SHIFT 8
333#define RCTL_LBM_TCVR UINT32_C(3) /**< PHY or external SerDes loopback. */
334#define RCTL_MO_MASK UINT32_C(0x00003000)
335#define RCTL_MO_SHIFT 12
336#define RCTL_BAM UINT32_C(0x00008000)
337#define RCTL_BSIZE_MASK UINT32_C(0x00030000)
338#define RCTL_BSIZE_SHIFT 16
339#define RCTL_VFE UINT32_C(0x00040000)
340#define RCTL_CFIEN UINT32_C(0x00080000)
341#define RCTL_CFI UINT32_C(0x00100000)
342#define RCTL_BSEX UINT32_C(0x02000000)
343#define RCTL_SECRC UINT32_C(0x04000000)
344
345#define ICR_TXDW UINT32_C(0x00000001)
346#define ICR_TXQE UINT32_C(0x00000002)
347#define ICR_LSC UINT32_C(0x00000004)
348#define ICR_RXDMT0 UINT32_C(0x00000010)
349#define ICR_RXT0 UINT32_C(0x00000080)
350#define ICR_TXD_LOW UINT32_C(0x00008000)
351#define RDTR_FPD UINT32_C(0x80000000)
352
353#define PBA_st ((PBAST*)(pThis->auRegs + PBA_IDX))
354typedef struct
355{
356 unsigned rxa : 7;
357 unsigned rxa_r : 9;
358 unsigned txa : 16;
359} PBAST;
360AssertCompileSize(PBAST, 4);
361
362#define TXDCTL_WTHRESH_MASK 0x003F0000
363#define TXDCTL_WTHRESH_SHIFT 16
364#define TXDCTL_LWTHRESH_MASK 0xFE000000
365#define TXDCTL_LWTHRESH_SHIFT 25
366
367#define RXCSUM_PCSS_MASK UINT32_C(0x000000FF)
368#define RXCSUM_PCSS_SHIFT 0
369
370/** @name Register access macros
371 * @remarks These ASSUME alocal variable @a pThis of type PE1KSTATE.
372 * @{ */
373#define CTRL pThis->auRegs[CTRL_IDX]
374#define STATUS pThis->auRegs[STATUS_IDX]
375#define EECD pThis->auRegs[EECD_IDX]
376#define EERD pThis->auRegs[EERD_IDX]
377#define CTRL_EXT pThis->auRegs[CTRL_EXT_IDX]
378#define FLA pThis->auRegs[FLA_IDX]
379#define MDIC pThis->auRegs[MDIC_IDX]
380#define FCAL pThis->auRegs[FCAL_IDX]
381#define FCAH pThis->auRegs[FCAH_IDX]
382#define FCT pThis->auRegs[FCT_IDX]
383#define VET pThis->auRegs[VET_IDX]
384#define ICR pThis->auRegs[ICR_IDX]
385#define ITR pThis->auRegs[ITR_IDX]
386#define ICS pThis->auRegs[ICS_IDX]
387#define IMS pThis->auRegs[IMS_IDX]
388#define IMC pThis->auRegs[IMC_IDX]
389#define RCTL pThis->auRegs[RCTL_IDX]
390#define FCTTV pThis->auRegs[FCTTV_IDX]
391#define TXCW pThis->auRegs[TXCW_IDX]
392#define RXCW pThis->auRegs[RXCW_IDX]
393#define TCTL pThis->auRegs[TCTL_IDX]
394#define TIPG pThis->auRegs[TIPG_IDX]
395#define AIFS pThis->auRegs[AIFS_IDX]
396#define LEDCTL pThis->auRegs[LEDCTL_IDX]
397#define PBA pThis->auRegs[PBA_IDX]
398#define FCRTL pThis->auRegs[FCRTL_IDX]
399#define FCRTH pThis->auRegs[FCRTH_IDX]
400#define RDFH pThis->auRegs[RDFH_IDX]
401#define RDFT pThis->auRegs[RDFT_IDX]
402#define RDFHS pThis->auRegs[RDFHS_IDX]
403#define RDFTS pThis->auRegs[RDFTS_IDX]
404#define RDFPC pThis->auRegs[RDFPC_IDX]
405#define RDBAL pThis->auRegs[RDBAL_IDX]
406#define RDBAH pThis->auRegs[RDBAH_IDX]
407#define RDLEN pThis->auRegs[RDLEN_IDX]
408#define RDH pThis->auRegs[RDH_IDX]
409#define RDT pThis->auRegs[RDT_IDX]
410#define RDTR pThis->auRegs[RDTR_IDX]
411#define RXDCTL pThis->auRegs[RXDCTL_IDX]
412#define RADV pThis->auRegs[RADV_IDX]
413#define RSRPD pThis->auRegs[RSRPD_IDX]
414#define TXDMAC pThis->auRegs[TXDMAC_IDX]
415#define TDFH pThis->auRegs[TDFH_IDX]
416#define TDFT pThis->auRegs[TDFT_IDX]
417#define TDFHS pThis->auRegs[TDFHS_IDX]
418#define TDFTS pThis->auRegs[TDFTS_IDX]
419#define TDFPC pThis->auRegs[TDFPC_IDX]
420#define TDBAL pThis->auRegs[TDBAL_IDX]
421#define TDBAH pThis->auRegs[TDBAH_IDX]
422#define TDLEN pThis->auRegs[TDLEN_IDX]
423#define TDH pThis->auRegs[TDH_IDX]
424#define TDT pThis->auRegs[TDT_IDX]
425#define TIDV pThis->auRegs[TIDV_IDX]
426#define TXDCTL pThis->auRegs[TXDCTL_IDX]
427#define TADV pThis->auRegs[TADV_IDX]
428#define TSPMT pThis->auRegs[TSPMT_IDX]
429#define CRCERRS pThis->auRegs[CRCERRS_IDX]
430#define ALGNERRC pThis->auRegs[ALGNERRC_IDX]
431#define SYMERRS pThis->auRegs[SYMERRS_IDX]
432#define RXERRC pThis->auRegs[RXERRC_IDX]
433#define MPC pThis->auRegs[MPC_IDX]
434#define SCC pThis->auRegs[SCC_IDX]
435#define ECOL pThis->auRegs[ECOL_IDX]
436#define MCC pThis->auRegs[MCC_IDX]
437#define LATECOL pThis->auRegs[LATECOL_IDX]
438#define COLC pThis->auRegs[COLC_IDX]
439#define DC pThis->auRegs[DC_IDX]
440#define TNCRS pThis->auRegs[TNCRS_IDX]
441/* #define SEC pThis->auRegs[SEC_IDX] Conflict with sys/time.h */
442#define CEXTERR pThis->auRegs[CEXTERR_IDX]
443#define RLEC pThis->auRegs[RLEC_IDX]
444#define XONRXC pThis->auRegs[XONRXC_IDX]
445#define XONTXC pThis->auRegs[XONTXC_IDX]
446#define XOFFRXC pThis->auRegs[XOFFRXC_IDX]
447#define XOFFTXC pThis->auRegs[XOFFTXC_IDX]
448#define FCRUC pThis->auRegs[FCRUC_IDX]
449#define PRC64 pThis->auRegs[PRC64_IDX]
450#define PRC127 pThis->auRegs[PRC127_IDX]
451#define PRC255 pThis->auRegs[PRC255_IDX]
452#define PRC511 pThis->auRegs[PRC511_IDX]
453#define PRC1023 pThis->auRegs[PRC1023_IDX]
454#define PRC1522 pThis->auRegs[PRC1522_IDX]
455#define GPRC pThis->auRegs[GPRC_IDX]
456#define BPRC pThis->auRegs[BPRC_IDX]
457#define MPRC pThis->auRegs[MPRC_IDX]
458#define GPTC pThis->auRegs[GPTC_IDX]
459#define GORCL pThis->auRegs[GORCL_IDX]
460#define GORCH pThis->auRegs[GORCH_IDX]
461#define GOTCL pThis->auRegs[GOTCL_IDX]
462#define GOTCH pThis->auRegs[GOTCH_IDX]
463#define RNBC pThis->auRegs[RNBC_IDX]
464#define RUC pThis->auRegs[RUC_IDX]
465#define RFC pThis->auRegs[RFC_IDX]
466#define ROC pThis->auRegs[ROC_IDX]
467#define RJC pThis->auRegs[RJC_IDX]
468#define MGTPRC pThis->auRegs[MGTPRC_IDX]
469#define MGTPDC pThis->auRegs[MGTPDC_IDX]
470#define MGTPTC pThis->auRegs[MGTPTC_IDX]
471#define TORL pThis->auRegs[TORL_IDX]
472#define TORH pThis->auRegs[TORH_IDX]
473#define TOTL pThis->auRegs[TOTL_IDX]
474#define TOTH pThis->auRegs[TOTH_IDX]
475#define TPR pThis->auRegs[TPR_IDX]
476#define TPT pThis->auRegs[TPT_IDX]
477#define PTC64 pThis->auRegs[PTC64_IDX]
478#define PTC127 pThis->auRegs[PTC127_IDX]
479#define PTC255 pThis->auRegs[PTC255_IDX]
480#define PTC511 pThis->auRegs[PTC511_IDX]
481#define PTC1023 pThis->auRegs[PTC1023_IDX]
482#define PTC1522 pThis->auRegs[PTC1522_IDX]
483#define MPTC pThis->auRegs[MPTC_IDX]
484#define BPTC pThis->auRegs[BPTC_IDX]
485#define TSCTC pThis->auRegs[TSCTC_IDX]
486#define TSCTFC pThis->auRegs[TSCTFC_IDX]
487#define RXCSUM pThis->auRegs[RXCSUM_IDX]
488#define WUC pThis->auRegs[WUC_IDX]
489#define WUFC pThis->auRegs[WUFC_IDX]
490#define WUS pThis->auRegs[WUS_IDX]
491#define MANC pThis->auRegs[MANC_IDX]
492#define IPAV pThis->auRegs[IPAV_IDX]
493#define WUPL pThis->auRegs[WUPL_IDX]
494/** @} */
495#endif /* VBOX_DEVICE_STRUCT_TESTCASE */
496
497/**
498 * Indices of memory-mapped registers in register table.
499 */
500typedef enum
501{
502 CTRL_IDX,
503 STATUS_IDX,
504 EECD_IDX,
505 EERD_IDX,
506 CTRL_EXT_IDX,
507 FLA_IDX,
508 MDIC_IDX,
509 FCAL_IDX,
510 FCAH_IDX,
511 FCT_IDX,
512 VET_IDX,
513 ICR_IDX,
514 ITR_IDX,
515 ICS_IDX,
516 IMS_IDX,
517 IMC_IDX,
518 RCTL_IDX,
519 FCTTV_IDX,
520 TXCW_IDX,
521 RXCW_IDX,
522 TCTL_IDX,
523 TIPG_IDX,
524 AIFS_IDX,
525 LEDCTL_IDX,
526 PBA_IDX,
527 FCRTL_IDX,
528 FCRTH_IDX,
529 RDFH_IDX,
530 RDFT_IDX,
531 RDFHS_IDX,
532 RDFTS_IDX,
533 RDFPC_IDX,
534 RDBAL_IDX,
535 RDBAH_IDX,
536 RDLEN_IDX,
537 RDH_IDX,
538 RDT_IDX,
539 RDTR_IDX,
540 RXDCTL_IDX,
541 RADV_IDX,
542 RSRPD_IDX,
543 TXDMAC_IDX,
544 TDFH_IDX,
545 TDFT_IDX,
546 TDFHS_IDX,
547 TDFTS_IDX,
548 TDFPC_IDX,
549 TDBAL_IDX,
550 TDBAH_IDX,
551 TDLEN_IDX,
552 TDH_IDX,
553 TDT_IDX,
554 TIDV_IDX,
555 TXDCTL_IDX,
556 TADV_IDX,
557 TSPMT_IDX,
558 CRCERRS_IDX,
559 ALGNERRC_IDX,
560 SYMERRS_IDX,
561 RXERRC_IDX,
562 MPC_IDX,
563 SCC_IDX,
564 ECOL_IDX,
565 MCC_IDX,
566 LATECOL_IDX,
567 COLC_IDX,
568 DC_IDX,
569 TNCRS_IDX,
570 SEC_IDX,
571 CEXTERR_IDX,
572 RLEC_IDX,
573 XONRXC_IDX,
574 XONTXC_IDX,
575 XOFFRXC_IDX,
576 XOFFTXC_IDX,
577 FCRUC_IDX,
578 PRC64_IDX,
579 PRC127_IDX,
580 PRC255_IDX,
581 PRC511_IDX,
582 PRC1023_IDX,
583 PRC1522_IDX,
584 GPRC_IDX,
585 BPRC_IDX,
586 MPRC_IDX,
587 GPTC_IDX,
588 GORCL_IDX,
589 GORCH_IDX,
590 GOTCL_IDX,
591 GOTCH_IDX,
592 RNBC_IDX,
593 RUC_IDX,
594 RFC_IDX,
595 ROC_IDX,
596 RJC_IDX,
597 MGTPRC_IDX,
598 MGTPDC_IDX,
599 MGTPTC_IDX,
600 TORL_IDX,
601 TORH_IDX,
602 TOTL_IDX,
603 TOTH_IDX,
604 TPR_IDX,
605 TPT_IDX,
606 PTC64_IDX,
607 PTC127_IDX,
608 PTC255_IDX,
609 PTC511_IDX,
610 PTC1023_IDX,
611 PTC1522_IDX,
612 MPTC_IDX,
613 BPTC_IDX,
614 TSCTC_IDX,
615 TSCTFC_IDX,
616 RXCSUM_IDX,
617 WUC_IDX,
618 WUFC_IDX,
619 WUS_IDX,
620 MANC_IDX,
621 IPAV_IDX,
622 WUPL_IDX,
623 MTA_IDX,
624 RA_IDX,
625 VFTA_IDX,
626 IP4AT_IDX,
627 IP6AT_IDX,
628 WUPM_IDX,
629 FFLT_IDX,
630 FFMT_IDX,
631 FFVT_IDX,
632 PBM_IDX,
633 RA_82542_IDX,
634 MTA_82542_IDX,
635 VFTA_82542_IDX,
636 E1K_NUM_OF_REGS
637} E1kRegIndex;
638
639#define E1K_NUM_OF_32BIT_REGS MTA_IDX
640/** The number of registers with strictly increasing offset. */
641#define E1K_NUM_OF_BINARY_SEARCHABLE (WUPL_IDX + 1)
642
643
644/**
645 * Define E1000-specific EEPROM layout.
646 */
647struct E1kEEPROM
648{
649 public:
650 EEPROM93C46 eeprom;
651
652#ifdef IN_RING3
653 /**
654 * Initialize EEPROM content.
655 *
656 * @param macAddr MAC address of E1000.
657 */
658 void init(RTMAC &macAddr)
659 {
660 eeprom.init();
661 memcpy(eeprom.m_au16Data, macAddr.au16, sizeof(macAddr.au16));
662 eeprom.m_au16Data[0x04] = 0xFFFF;
663 /*
664 * bit 3 - full support for power management
665 * bit 10 - full duplex
666 */
667 eeprom.m_au16Data[0x0A] = 0x4408;
668 eeprom.m_au16Data[0x0B] = 0x001E;
669 eeprom.m_au16Data[0x0C] = 0x8086;
670 eeprom.m_au16Data[0x0D] = 0x100E;
671 eeprom.m_au16Data[0x0E] = 0x8086;
672 eeprom.m_au16Data[0x0F] = 0x3040;
673 eeprom.m_au16Data[0x21] = 0x7061;
674 eeprom.m_au16Data[0x22] = 0x280C;
675 eeprom.m_au16Data[0x23] = 0x00C8;
676 eeprom.m_au16Data[0x24] = 0x00C8;
677 eeprom.m_au16Data[0x2F] = 0x0602;
678 updateChecksum();
679 };
680
681 /**
682 * Compute the checksum as required by E1000 and store it
683 * in the last word.
684 */
685 void updateChecksum()
686 {
687 uint16_t u16Checksum = 0;
688
689 for (int i = 0; i < eeprom.SIZE-1; i++)
690 u16Checksum += eeprom.m_au16Data[i];
691 eeprom.m_au16Data[eeprom.SIZE-1] = 0xBABA - u16Checksum;
692 };
693
694 /**
695 * First 6 bytes of EEPROM contain MAC address.
696 *
697 * @returns MAC address of E1000.
698 */
699 void getMac(PRTMAC pMac)
700 {
701 memcpy(pMac->au16, eeprom.m_au16Data, sizeof(pMac->au16));
702 };
703
704 uint32_t read()
705 {
706 return eeprom.read();
707 }
708
709 void write(uint32_t u32Wires)
710 {
711 eeprom.write(u32Wires);
712 }
713
714 bool readWord(uint32_t u32Addr, uint16_t *pu16Value)
715 {
716 return eeprom.readWord(u32Addr, pu16Value);
717 }
718
719 int load(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
720 {
721 return eeprom.load(pHlp, pSSM);
722 }
723
724 void save(PCPDMDEVHLPR3 pHlp, PSSMHANDLE pSSM)
725 {
726 eeprom.save(pHlp, pSSM);
727 }
728#endif /* IN_RING3 */
729};
730
731
732#define E1K_SPEC_VLAN(s) (s & 0xFFF)
733#define E1K_SPEC_CFI(s) (!!((s>>12) & 0x1))
734#define E1K_SPEC_PRI(s) ((s>>13) & 0x7)
735
736struct E1kRxDStatus
737{
738 /** @name Descriptor Status field (3.2.3.1)
739 * @{ */
740 unsigned fDD : 1; /**< Descriptor Done. */
741 unsigned fEOP : 1; /**< End of packet. */
742 unsigned fIXSM : 1; /**< Ignore checksum indication. */
743 unsigned fVP : 1; /**< VLAN, matches VET. */
744 unsigned : 1;
745 unsigned fTCPCS : 1; /**< RCP Checksum calculated on the packet. */
746 unsigned fIPCS : 1; /**< IP Checksum calculated on the packet. */
747 unsigned fPIF : 1; /**< Passed in-exact filter */
748 /** @} */
749 /** @name Descriptor Errors field (3.2.3.2)
750 * (Only valid when fEOP and fDD are set.)
751 * @{ */
752 unsigned fCE : 1; /**< CRC or alignment error. */
753 unsigned : 4; /**< Reserved, varies with different models... */
754 unsigned fTCPE : 1; /**< TCP/UDP checksum error. */
755 unsigned fIPE : 1; /**< IP Checksum error. */
756 unsigned fRXE : 1; /**< RX Data error. */
757 /** @} */
758 /** @name Descriptor Special field (3.2.3.3)
759 * @{ */
760 unsigned u16Special : 16; /**< VLAN: Id, Canonical form, Priority. */
761 /** @} */
762};
763typedef struct E1kRxDStatus E1KRXDST;
764
765struct E1kRxDesc_st
766{
767 uint64_t u64BufAddr; /**< Address of data buffer */
768 uint16_t u16Length; /**< Length of data in buffer */
769 uint16_t u16Checksum; /**< Packet checksum */
770 E1KRXDST status;
771};
772typedef struct E1kRxDesc_st E1KRXDESC;
773AssertCompileSize(E1KRXDESC, 16);
774
775#define E1K_DTYP_LEGACY -1
776#define E1K_DTYP_CONTEXT 0
777#define E1K_DTYP_DATA 1
778
779struct E1kTDLegacy
780{
781 uint64_t u64BufAddr; /**< Address of data buffer */
782 struct TDLCmd_st
783 {
784 unsigned u16Length : 16;
785 unsigned u8CSO : 8;
786 /* CMD field : 8 */
787 unsigned fEOP : 1;
788 unsigned fIFCS : 1;
789 unsigned fIC : 1;
790 unsigned fRS : 1;
791 unsigned fRPS : 1;
792 unsigned fDEXT : 1;
793 unsigned fVLE : 1;
794 unsigned fIDE : 1;
795 } cmd;
796 struct TDLDw3_st
797 {
798 /* STA field */
799 unsigned fDD : 1;
800 unsigned fEC : 1;
801 unsigned fLC : 1;
802 unsigned fTURSV : 1;
803 /* RSV field */
804 unsigned u4RSV : 4;
805 /* CSS field */
806 unsigned u8CSS : 8;
807 /* Special field*/
808 unsigned u16Special: 16;
809 } dw3;
810};
811
812/**
813 * TCP/IP Context Transmit Descriptor, section 3.3.6.
814 */
815struct E1kTDContext
816{
817 struct CheckSum_st
818 {
819 /** TSE: Header start. !TSE: Checksum start. */
820 unsigned u8CSS : 8;
821 /** Checksum offset - where to store it. */
822 unsigned u8CSO : 8;
823 /** Checksum ending (inclusive) offset, 0 = end of packet. */
824 unsigned u16CSE : 16;
825 } ip;
826 struct CheckSum_st tu;
827 struct TDCDw2_st
828 {
829 /** TSE: The total number of payload bytes for this context. Sans header. */
830 unsigned u20PAYLEN : 20;
831 /** The descriptor type - E1K_DTYP_CONTEXT (0). */
832 unsigned u4DTYP : 4;
833 /** TUCMD field, 8 bits
834 * @{ */
835 /** TSE: TCP (set) or UDP (clear). */
836 unsigned fTCP : 1;
837 /** TSE: IPv4 (set) or IPv6 (clear) - for finding the payload length field in
838 * the IP header. Does not affect the checksumming.
839 * @remarks 82544GC/EI interprets a cleared field differently. */
840 unsigned fIP : 1;
841 /** TSE: TCP segmentation enable. When clear the context describes */
842 unsigned fTSE : 1;
843 /** Report status (only applies to dw3.fDD for here). */
844 unsigned fRS : 1;
845 /** Reserved, MBZ. */
846 unsigned fRSV1 : 1;
847 /** Descriptor extension, must be set for this descriptor type. */
848 unsigned fDEXT : 1;
849 /** Reserved, MBZ. */
850 unsigned fRSV2 : 1;
851 /** Interrupt delay enable. */
852 unsigned fIDE : 1;
853 /** @} */
854 } dw2;
855 struct TDCDw3_st
856 {
857 /** Descriptor Done. */
858 unsigned fDD : 1;
859 /** Reserved, MBZ. */
860 unsigned u7RSV : 7;
861 /** TSO: The header (prototype) length (Ethernet[, VLAN tag], IP, TCP/UDP. */
862 unsigned u8HDRLEN : 8;
863 /** TSO: Maximum segment size. */
864 unsigned u16MSS : 16;
865 } dw3;
866};
867typedef struct E1kTDContext E1KTXCTX;
868
869/**
870 * TCP/IP Data Transmit Descriptor, section 3.3.7.
871 */
872struct E1kTDData
873{
874 uint64_t u64BufAddr; /**< Address of data buffer */
875 struct TDDCmd_st
876 {
877 /** The total length of data pointed to by this descriptor. */
878 unsigned u20DTALEN : 20;
879 /** The descriptor type - E1K_DTYP_DATA (1). */
880 unsigned u4DTYP : 4;
881 /** @name DCMD field, 8 bits (3.3.7.1).
882 * @{ */
883 /** End of packet. Note TSCTFC update. */
884 unsigned fEOP : 1;
885 /** Insert Ethernet FCS/CRC (requires fEOP to be set). */
886 unsigned fIFCS : 1;
887 /** Use the TSE context when set and the normal when clear. */
888 unsigned fTSE : 1;
889 /** Report status (dw3.STA). */
890 unsigned fRS : 1;
891 /** Reserved. 82544GC/EI defines this report packet set (RPS). */
892 unsigned fRPS : 1;
893 /** Descriptor extension, must be set for this descriptor type. */
894 unsigned fDEXT : 1;
895 /** VLAN enable, requires CTRL.VME, auto enables FCS/CRC.
896 * Insert dw3.SPECIAL after ethernet header. */
897 unsigned fVLE : 1;
898 /** Interrupt delay enable. */
899 unsigned fIDE : 1;
900 /** @} */
901 } cmd;
902 struct TDDDw3_st
903 {
904 /** @name STA field (3.3.7.2)
905 * @{ */
906 unsigned fDD : 1; /**< Descriptor done. */
907 unsigned fEC : 1; /**< Excess collision. */
908 unsigned fLC : 1; /**< Late collision. */
909 /** Reserved, except for the usual oddball (82544GC/EI) where it's called TU. */
910 unsigned fTURSV : 1;
911 /** @} */
912 unsigned u4RSV : 4; /**< Reserved field, MBZ. */
913 /** @name POPTS (Packet Option) field (3.3.7.3)
914 * @{ */
915 unsigned fIXSM : 1; /**< Insert IP checksum. */
916 unsigned fTXSM : 1; /**< Insert TCP/UDP checksum. */
917 unsigned u6RSV : 6; /**< Reserved, MBZ. */
918 /** @} */
919 /** @name SPECIAL field - VLAN tag to be inserted after ethernet header.
920 * Requires fEOP, fVLE and CTRL.VME to be set.
921 * @{ */
922 unsigned u16Special: 16; /**< VLAN: Id, Canonical form, Priority. */
923 /** @} */
924 } dw3;
925};
926typedef struct E1kTDData E1KTXDAT;
927
928union E1kTxDesc
929{
930 struct E1kTDLegacy legacy;
931 struct E1kTDContext context;
932 struct E1kTDData data;
933};
934typedef union E1kTxDesc E1KTXDESC;
935AssertCompileSize(E1KTXDESC, 16);
936
937#define RA_CTL_AS 0x0003
938#define RA_CTL_AV 0x8000
939
940union E1kRecAddr
941{
942 uint32_t au32[32];
943 struct RAArray
944 {
945 uint8_t addr[6];
946 uint16_t ctl;
947 } array[16];
948};
949typedef struct E1kRecAddr::RAArray E1KRAELEM;
950typedef union E1kRecAddr E1KRA;
951AssertCompileSize(E1KRA, 8*16);
952
953#define E1K_IP_RF UINT16_C(0x8000) /**< reserved fragment flag */
954#define E1K_IP_DF UINT16_C(0x4000) /**< dont fragment flag */
955#define E1K_IP_MF UINT16_C(0x2000) /**< more fragments flag */
956#define E1K_IP_OFFMASK UINT16_C(0x1fff) /**< mask for fragmenting bits */
957
958/** @todo use+extend RTNETIPV4 */
959struct E1kIpHeader
960{
961 /* type of service / version / header length */
962 uint16_t tos_ver_hl;
963 /* total length */
964 uint16_t total_len;
965 /* identification */
966 uint16_t ident;
967 /* fragment offset field */
968 uint16_t offset;
969 /* time to live / protocol*/
970 uint16_t ttl_proto;
971 /* checksum */
972 uint16_t chksum;
973 /* source IP address */
974 uint32_t src;
975 /* destination IP address */
976 uint32_t dest;
977};
978AssertCompileSize(struct E1kIpHeader, 20);
979
980#define E1K_TCP_FIN UINT16_C(0x01)
981#define E1K_TCP_SYN UINT16_C(0x02)
982#define E1K_TCP_RST UINT16_C(0x04)
983#define E1K_TCP_PSH UINT16_C(0x08)
984#define E1K_TCP_ACK UINT16_C(0x10)
985#define E1K_TCP_URG UINT16_C(0x20)
986#define E1K_TCP_ECE UINT16_C(0x40)
987#define E1K_TCP_CWR UINT16_C(0x80)
988#define E1K_TCP_FLAGS UINT16_C(0x3f)
989
990/** @todo use+extend RTNETTCP */
991struct E1kTcpHeader
992{
993 uint16_t src;
994 uint16_t dest;
995 uint32_t seqno;
996 uint32_t ackno;
997 uint16_t hdrlen_flags;
998 uint16_t wnd;
999 uint16_t chksum;
1000 uint16_t urgp;
1001};
1002AssertCompileSize(struct E1kTcpHeader, 20);
1003
1004
1005#ifdef E1K_WITH_TXD_CACHE
1006/** The current Saved state version. */
1007# define E1K_SAVEDSTATE_VERSION 4
1008/** Saved state version for VirtualBox 4.2 with VLAN tag fields. */
1009# define E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG 3
1010#else /* !E1K_WITH_TXD_CACHE */
1011/** The current Saved state version. */
1012# define E1K_SAVEDSTATE_VERSION 3
1013#endif /* !E1K_WITH_TXD_CACHE */
1014/** Saved state version for VirtualBox 4.1 and earlier.
1015 * These did not include VLAN tag fields. */
1016#define E1K_SAVEDSTATE_VERSION_VBOX_41 2
1017/** Saved state version for VirtualBox 3.0 and earlier.
1018 * This did not include the configuration part nor the E1kEEPROM. */
1019#define E1K_SAVEDSTATE_VERSION_VBOX_30 1
1020
1021/**
1022 * E1000 shared device state.
1023 *
1024 * This is shared between ring-0 and ring-3.
1025 */
1026typedef struct E1KSTATE
1027{
1028 char szPrf[8]; /**< Log prefix, e.g. E1000#1. */
1029
1030 /** Handle to PCI region \#0, the MMIO region. */
1031 IOMIOPORTHANDLE hMmioRegion;
1032 /** Handle to PCI region \#2, the I/O ports. */
1033 IOMIOPORTHANDLE hIoPorts;
1034
1035 /** Receive Interrupt Delay Timer. */
1036 TMTIMERHANDLE hRIDTimer;
1037 /** Receive Absolute Delay Timer. */
1038 TMTIMERHANDLE hRADTimer;
1039 /** Transmit Interrupt Delay Timer. */
1040 TMTIMERHANDLE hTIDTimer;
1041 /** Transmit Absolute Delay Timer. */
1042 TMTIMERHANDLE hTADTimer;
1043 /** Transmit Delay Timer. */
1044 TMTIMERHANDLE hTXDTimer;
1045 /** Late Interrupt Timer. */
1046 TMTIMERHANDLE hIntTimer;
1047 /** Link Up(/Restore) Timer. */
1048 TMTIMERHANDLE hLUTimer;
1049
1050 /** Transmit task. */
1051 PDMTASKHANDLE hTxTask;
1052
1053 /** Critical section - what is it protecting? */
1054 PDMCRITSECT cs;
1055 /** RX Critical section. */
1056 PDMCRITSECT csRx;
1057#ifdef E1K_WITH_TX_CS
1058 /** TX Critical section. */
1059 PDMCRITSECT csTx;
1060#endif /* E1K_WITH_TX_CS */
1061 /** MAC address obtained from the configuration. */
1062 RTMAC macConfigured;
1063 uint16_t u16Padding0;
1064 /** EMT: Last time the interrupt was acknowledged. */
1065 uint64_t u64AckedAt;
1066 /** All: Used for eliminating spurious interrupts. */
1067 bool fIntRaised;
1068 /** EMT: false if the cable is disconnected by the GUI. */
1069 bool fCableConnected;
1070 /** EMT: Compute Ethernet CRC for RX packets. */
1071 bool fEthernetCRC;
1072 /** All: throttle interrupts. */
1073 bool fItrEnabled;
1074 /** All: throttle RX interrupts. */
1075 bool fItrRxEnabled;
1076 /** All: Delay TX interrupts using TIDV/TADV. */
1077 bool fTidEnabled;
1078 bool afPadding[2];
1079 /** Link up delay (in milliseconds). */
1080 uint32_t cMsLinkUpDelay;
1081
1082 /** All: Device register storage. */
1083 uint32_t auRegs[E1K_NUM_OF_32BIT_REGS];
1084 /** TX/RX: Status LED. */
1085 PDMLED led;
1086 /** TX/RX: Number of packet being sent/received to show in debug log. */
1087 uint32_t u32PktNo;
1088
1089 /** EMT: Offset of the register to be read via IO. */
1090 uint32_t uSelectedReg;
1091 /** EMT: Multicast Table Array. */
1092 uint32_t auMTA[128];
1093 /** EMT: Receive Address registers. */
1094 E1KRA aRecAddr;
1095 /** EMT: VLAN filter table array. */
1096 uint32_t auVFTA[128];
1097 /** EMT: Receive buffer size. */
1098 uint16_t u16RxBSize;
1099 /** EMT: Locked state -- no state alteration possible. */
1100 bool fLocked;
1101 /** EMT: */
1102 bool fDelayInts;
1103 /** All: */
1104 bool fIntMaskUsed;
1105
1106 /** N/A: */
1107 bool volatile fMaybeOutOfSpace;
1108 /** EMT: Gets signalled when more RX descriptors become available. */
1109 SUPSEMEVENT hEventMoreRxDescAvail;
1110#ifdef E1K_WITH_RXD_CACHE
1111 /** RX: Fetched RX descriptors. */
1112 E1KRXDESC aRxDescriptors[E1K_RXD_CACHE_SIZE];
1113 //uint64_t aRxDescAddr[E1K_RXD_CACHE_SIZE];
1114 /** RX: Actual number of fetched RX descriptors. */
1115 uint32_t nRxDFetched;
1116 /** RX: Index in cache of RX descriptor being processed. */
1117 uint32_t iRxDCurrent;
1118#endif /* E1K_WITH_RXD_CACHE */
1119
1120 /** TX: Context used for TCP segmentation packets. */
1121 E1KTXCTX contextTSE;
1122 /** TX: Context used for ordinary packets. */
1123 E1KTXCTX contextNormal;
1124#ifdef E1K_WITH_TXD_CACHE
1125 /** TX: Fetched TX descriptors. */
1126 E1KTXDESC aTxDescriptors[E1K_TXD_CACHE_SIZE];
1127 /** TX: Validity of TX descriptors. Set by e1kLocateTxPacket, used by e1kXmitPacket. */
1128 bool afTxDValid[E1K_TXD_CACHE_SIZE];
1129 /** TX: Actual number of fetched TX descriptors. */
1130 uint8_t nTxDFetched;
1131 /** TX: Index in cache of TX descriptor being processed. */
1132 uint8_t iTxDCurrent;
1133 /** TX: Will this frame be sent as GSO. */
1134 bool fGSO;
1135 /** Alignment padding. */
1136 bool fReserved;
1137 /** TX: Number of bytes in next packet. */
1138 uint32_t cbTxAlloc;
1139
1140#endif /* E1K_WITH_TXD_CACHE */
1141 /** GSO context. u8Type is set to PDMNETWORKGSOTYPE_INVALID when not
1142 * applicable to the current TSE mode. */
1143 PDMNETWORKGSO GsoCtx;
1144 /** Scratch space for holding the loopback / fallback scatter / gather
1145 * descriptor. */
1146 union
1147 {
1148 PDMSCATTERGATHER Sg;
1149 uint8_t padding[8 * sizeof(RTUINTPTR)];
1150 } uTxFallback;
1151 /** TX: Transmit packet buffer use for TSE fallback and loopback. */
1152 uint8_t aTxPacketFallback[E1K_MAX_TX_PKT_SIZE];
1153 /** TX: Number of bytes assembled in TX packet buffer. */
1154 uint16_t u16TxPktLen;
1155 /** TX: False will force segmentation in e1000 instead of sending frames as GSO. */
1156 bool fGSOEnabled;
1157 /** TX: IP checksum has to be inserted if true. */
1158 bool fIPcsum;
1159 /** TX: TCP/UDP checksum has to be inserted if true. */
1160 bool fTCPcsum;
1161 /** TX: VLAN tag has to be inserted if true. */
1162 bool fVTag;
1163 /** TX: TCI part of VLAN tag to be inserted. */
1164 uint16_t u16VTagTCI;
1165 /** TX TSE fallback: Number of payload bytes remaining in TSE context. */
1166 uint32_t u32PayRemain;
1167 /** TX TSE fallback: Number of header bytes remaining in TSE context. */
1168 uint16_t u16HdrRemain;
1169 /** TX TSE fallback: Flags from template header. */
1170 uint16_t u16SavedFlags;
1171 /** TX TSE fallback: Partial checksum from template header. */
1172 uint32_t u32SavedCsum;
1173 /** ?: Emulated controller type. */
1174 E1KCHIP eChip;
1175
1176 /** EMT: Physical interface emulation. */
1177 PHY phy;
1178
1179#if 0
1180 /** Alignment padding. */
1181 uint8_t Alignment[HC_ARCH_BITS == 64 ? 8 : 4];
1182#endif
1183
1184 STAMCOUNTER StatReceiveBytes;
1185 STAMCOUNTER StatTransmitBytes;
1186#if defined(VBOX_WITH_STATISTICS)
1187 STAMPROFILEADV StatMMIOReadRZ;
1188 STAMPROFILEADV StatMMIOReadR3;
1189 STAMPROFILEADV StatMMIOWriteRZ;
1190 STAMPROFILEADV StatMMIOWriteR3;
1191 STAMPROFILEADV StatEEPROMRead;
1192 STAMPROFILEADV StatEEPROMWrite;
1193 STAMPROFILEADV StatIOReadRZ;
1194 STAMPROFILEADV StatIOReadR3;
1195 STAMPROFILEADV StatIOWriteRZ;
1196 STAMPROFILEADV StatIOWriteR3;
1197 STAMPROFILEADV StatLateIntTimer;
1198 STAMCOUNTER StatLateInts;
1199 STAMCOUNTER StatIntsRaised;
1200 STAMCOUNTER StatIntsPrevented;
1201 STAMPROFILEADV StatReceive;
1202 STAMPROFILEADV StatReceiveCRC;
1203 STAMPROFILEADV StatReceiveFilter;
1204 STAMPROFILEADV StatReceiveStore;
1205 STAMPROFILEADV StatTransmitRZ;
1206 STAMPROFILEADV StatTransmitR3;
1207 STAMPROFILE StatTransmitSendRZ;
1208 STAMPROFILE StatTransmitSendR3;
1209 STAMPROFILE StatRxOverflow;
1210 STAMCOUNTER StatRxOverflowWakeupRZ;
1211 STAMCOUNTER StatRxOverflowWakeupR3;
1212 STAMCOUNTER StatTxDescCtxNormal;
1213 STAMCOUNTER StatTxDescCtxTSE;
1214 STAMCOUNTER StatTxDescLegacy;
1215 STAMCOUNTER StatTxDescData;
1216 STAMCOUNTER StatTxDescTSEData;
1217 STAMCOUNTER StatTxPathFallback;
1218 STAMCOUNTER StatTxPathGSO;
1219 STAMCOUNTER StatTxPathRegular;
1220 STAMCOUNTER StatPHYAccesses;
1221 STAMCOUNTER aStatRegWrites[E1K_NUM_OF_REGS];
1222 STAMCOUNTER aStatRegReads[E1K_NUM_OF_REGS];
1223#endif /* VBOX_WITH_STATISTICS */
1224
1225#ifdef E1K_INT_STATS
1226 /* Internal stats */
1227 uint64_t u64ArmedAt;
1228 uint64_t uStatMaxTxDelay;
1229 uint32_t uStatInt;
1230 uint32_t uStatIntTry;
1231 uint32_t uStatIntLower;
1232 uint32_t uStatNoIntICR;
1233 int32_t iStatIntLost;
1234 int32_t iStatIntLostOne;
1235 uint32_t uStatIntIMS;
1236 uint32_t uStatIntSkip;
1237 uint32_t uStatIntLate;
1238 uint32_t uStatIntMasked;
1239 uint32_t uStatIntEarly;
1240 uint32_t uStatIntRx;
1241 uint32_t uStatIntTx;
1242 uint32_t uStatIntICS;
1243 uint32_t uStatIntRDTR;
1244 uint32_t uStatIntRXDMT0;
1245 uint32_t uStatIntTXQE;
1246 uint32_t uStatTxNoRS;
1247 uint32_t uStatTxIDE;
1248 uint32_t uStatTxDelayed;
1249 uint32_t uStatTxDelayExp;
1250 uint32_t uStatTAD;
1251 uint32_t uStatTID;
1252 uint32_t uStatRAD;
1253 uint32_t uStatRID;
1254 uint32_t uStatRxFrm;
1255 uint32_t uStatTxFrm;
1256 uint32_t uStatDescCtx;
1257 uint32_t uStatDescDat;
1258 uint32_t uStatDescLeg;
1259 uint32_t uStatTx1514;
1260 uint32_t uStatTx2962;
1261 uint32_t uStatTx4410;
1262 uint32_t uStatTx5858;
1263 uint32_t uStatTx7306;
1264 uint32_t uStatTx8754;
1265 uint32_t uStatTx16384;
1266 uint32_t uStatTx32768;
1267 uint32_t uStatTxLarge;
1268 uint32_t uStatAlign;
1269#endif /* E1K_INT_STATS */
1270} E1KSTATE;
1271/** Pointer to the E1000 device state. */
1272typedef E1KSTATE *PE1KSTATE;
1273
1274/**
1275 * E1000 ring-3 device state
1276 *
1277 * @implements PDMINETWORKDOWN
1278 * @implements PDMINETWORKCONFIG
1279 * @implements PDMILEDPORTS
1280 */
1281typedef struct E1KSTATER3
1282{
1283 PDMIBASE IBase;
1284 PDMINETWORKDOWN INetworkDown;
1285 PDMINETWORKCONFIG INetworkConfig;
1286 /** LED interface */
1287 PDMILEDPORTS ILeds;
1288 /** Attached network driver. */
1289 R3PTRTYPE(PPDMIBASE) pDrvBase;
1290 R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
1291
1292 /** Pointer to the shared state. */
1293 R3PTRTYPE(PE1KSTATE) pShared;
1294
1295 /** Device instance. */
1296 PPDMDEVINSR3 pDevInsR3;
1297 /** Attached network driver. */
1298 PPDMINETWORKUPR3 pDrvR3;
1299 /** The scatter / gather buffer used for the current outgoing packet. */
1300 R3PTRTYPE(PPDMSCATTERGATHER) pTxSgR3;
1301
1302 /** EMT: EEPROM emulation */
1303 E1kEEPROM eeprom;
1304} E1KSTATER3;
1305/** Pointer to the E1000 ring-3 device state. */
1306typedef E1KSTATER3 *PE1KSTATER3;
1307
1308
1309/**
1310 * E1000 ring-0 device state
1311 */
1312typedef struct E1KSTATER0
1313{
1314 /** Device instance. */
1315 PPDMDEVINSR0 pDevInsR0;
1316 /** Attached network driver. */
1317 PPDMINETWORKUPR0 pDrvR0;
1318 /** The scatter / gather buffer used for the current outgoing packet - R0. */
1319 R0PTRTYPE(PPDMSCATTERGATHER) pTxSgR0;
1320} E1KSTATER0;
1321/** Pointer to the E1000 ring-0 device state. */
1322typedef E1KSTATER0 *PE1KSTATER0;
1323
1324
1325/**
1326 * E1000 raw-mode device state
1327 */
1328typedef struct E1KSTATERC
1329{
1330 /** Device instance. */
1331 PPDMDEVINSRC pDevInsRC;
1332 /** Attached network driver. */
1333 PPDMINETWORKUPRC pDrvRC;
1334 /** The scatter / gather buffer used for the current outgoing packet. */
1335 RCPTRTYPE(PPDMSCATTERGATHER) pTxSgRC;
1336} E1KSTATERC;
1337/** Pointer to the E1000 raw-mode device state. */
1338typedef E1KSTATERC *PE1KSTATERC;
1339
1340
1341/** @def PE1KSTATECC
1342 * Pointer to the instance data for the current context. */
1343#ifdef IN_RING3
1344typedef E1KSTATER3 E1KSTATECC;
1345typedef PE1KSTATER3 PE1KSTATECC;
1346#elif defined(IN_RING0)
1347typedef E1KSTATER0 E1KSTATECC;
1348typedef PE1KSTATER0 PE1KSTATECC;
1349#elif defined(IN_RC)
1350typedef E1KSTATERC E1KSTATECC;
1351typedef PE1KSTATERC PE1KSTATECC;
1352#else
1353# error "Not IN_RING3, IN_RING0 or IN_RC"
1354#endif
1355
1356
1357#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1358
1359/* Forward declarations ******************************************************/
1360static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread);
1361
1362/**
1363 * E1000 register read handler.
1364 */
1365typedef int (FNE1KREGREAD)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value);
1366/**
1367 * E1000 register write handler.
1368 */
1369typedef int (FNE1KREGWRITE)(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t u32Value);
1370
1371static FNE1KREGREAD e1kRegReadUnimplemented;
1372static FNE1KREGWRITE e1kRegWriteUnimplemented;
1373static FNE1KREGREAD e1kRegReadAutoClear;
1374static FNE1KREGREAD e1kRegReadDefault;
1375static FNE1KREGWRITE e1kRegWriteDefault;
1376#if 0 /* unused */
1377static FNE1KREGREAD e1kRegReadCTRL;
1378#endif
1379static FNE1KREGWRITE e1kRegWriteCTRL;
1380static FNE1KREGREAD e1kRegReadEECD;
1381static FNE1KREGWRITE e1kRegWriteEECD;
1382static FNE1KREGWRITE e1kRegWriteEERD;
1383static FNE1KREGWRITE e1kRegWriteMDIC;
1384static FNE1KREGREAD e1kRegReadICR;
1385static FNE1KREGWRITE e1kRegWriteICR;
1386static FNE1KREGREAD e1kRegReadICS;
1387static FNE1KREGWRITE e1kRegWriteICS;
1388static FNE1KREGWRITE e1kRegWriteIMS;
1389static FNE1KREGWRITE e1kRegWriteIMC;
1390static FNE1KREGWRITE e1kRegWriteRCTL;
1391static FNE1KREGWRITE e1kRegWritePBA;
1392static FNE1KREGWRITE e1kRegWriteRDT;
1393static FNE1KREGWRITE e1kRegWriteRDTR;
1394static FNE1KREGWRITE e1kRegWriteTDT;
1395static FNE1KREGREAD e1kRegReadMTA;
1396static FNE1KREGWRITE e1kRegWriteMTA;
1397static FNE1KREGREAD e1kRegReadRA;
1398static FNE1KREGWRITE e1kRegWriteRA;
1399static FNE1KREGREAD e1kRegReadVFTA;
1400static FNE1KREGWRITE e1kRegWriteVFTA;
1401
1402/**
1403 * Register map table.
1404 *
1405 * Override pfnRead and pfnWrite to get register-specific behavior.
1406 */
1407static const struct E1kRegMap_st
1408{
1409 /** Register offset in the register space. */
1410 uint32_t offset;
1411 /** Size in bytes. Registers of size > 4 are in fact tables. */
1412 uint32_t size;
1413 /** Readable bits. */
1414 uint32_t readable;
1415 /** Writable bits. */
1416 uint32_t writable;
1417 /** Read callback. */
1418 FNE1KREGREAD *pfnRead;
1419 /** Write callback. */
1420 FNE1KREGWRITE *pfnWrite;
1421 /** Abbreviated name. */
1422 const char *abbrev;
1423 /** Full name. */
1424 const char *name;
1425} g_aE1kRegMap[E1K_NUM_OF_REGS] =
1426{
1427 /* offset size read mask write mask read callback write callback abbrev full name */
1428 /*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
1429 { 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
1430 { 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
1431 { 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
1432 { 0x00014, 0x00004, 0xFFFFFF10, 0xFFFFFF00, e1kRegReadDefault , e1kRegWriteEERD , "EERD" , "EEPROM Read" },
1433 { 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
1434 { 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
1435 { 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
1436 { 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
1437 { 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
1438 { 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
1439 { 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
1440 { 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
1441 { 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
1442 { 0x000c8, 0x00004, 0x0001F6DF, 0xFFFFFFFF, e1kRegReadICS , e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
1443 { 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
1444 { 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
1445 { 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
1446 { 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
1447 { 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
1448 { 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
1449 { 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
1450 { 0x00410, 0x00004, 0x3FFFFFFF, 0x3FFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIPG" , "Transmit IPG" },
1451 { 0x00458, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "AIFS" , "Adaptive IFS Throttle - AIT" },
1452 { 0x00e00, 0x00004, 0xCFCFCFCF, 0xCFCFCFCF, e1kRegReadDefault , e1kRegWriteDefault , "LEDCTL" , "LED Control" },
1453 { 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
1454 { 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
1455 { 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
1456 { 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
1457 { 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
1458 { 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
1459 { 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
1460 { 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
1461 { 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
1462 { 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
1463 { 0x02808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
1464 { 0x02810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
1465 { 0x02818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
1466 { 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
1467 { 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
1468 { 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
1469 { 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
1470 { 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
1471 { 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
1472 { 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
1473 { 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
1474 { 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
1475 { 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
1476 { 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
1477 { 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
1478 { 0x03808, 0x00004, 0x000FFF80, 0x000FFF80, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
1479 { 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
1480 { 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
1481 { 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
1482 { 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
1483 { 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
1484 { 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TSPMT" , "TCP Segmentation Pad and Threshold" },
1485 { 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
1486 { 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
1487 { 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
1488 { 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
1489 { 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
1490 { 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
1491 { 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
1492 { 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
1493 { 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
1494 { 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
1495 { 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
1496 { 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
1497 { 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
1498 { 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
1499 { 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
1500 { 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
1501 { 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
1502 { 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
1503 { 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
1504 { 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
1505 { 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
1506 { 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
1507 { 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
1508 { 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
1509 { 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
1510 { 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
1511 { 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
1512 { 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
1513 { 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
1514 { 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
1515 { 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
1516 { 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
1517 { 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
1518 { 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
1519 { 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
1520 { 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
1521 { 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
1522 { 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
1523 { 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
1524 { 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
1525 { 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
1526 { 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
1527 { 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
1528 { 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
1529 { 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
1530 { 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
1531 { 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
1532 { 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
1533 { 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
1534 { 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
1535 { 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
1536 { 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
1537 { 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
1538 { 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
1539 { 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
1540 { 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
1541 { 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
1542 { 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
1543 { 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
1544 { 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
1545 { 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
1546 { 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
1547 { 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
1548 { 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
1549 { 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
1550 { 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
1551 { 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
1552 { 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
1553 { 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
1554 { 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
1555 { 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
1556 { 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
1557 { 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
1558 { 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
1559 { 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
1560 { 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA82542" , "Receive Address (64-bit) (n) (82542)" },
1561 { 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA82542", "Multicast Table Array (n) (82542)" },
1562 { 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA82542", "VLAN Filter Table Array (n) (82542)" }
1563};
1564
1565#ifdef LOG_ENABLED
1566
1567/**
1568 * Convert U32 value to hex string. Masked bytes are replaced with dots.
1569 *
1570 * @remarks The mask has half-byte byte (not bit) granularity (e.g. 0000000F).
1571 *
1572 * @returns The buffer.
1573 *
1574 * @param u32 The word to convert into string.
1575 * @param mask Selects which bytes to convert.
1576 * @param buf Where to put the result.
1577 */
1578static char *e1kU32toHex(uint32_t u32, uint32_t mask, char *buf)
1579{
1580 for (char *ptr = buf + 7; ptr >= buf; --ptr, u32 >>=4, mask >>=4)
1581 {
1582 if (mask & 0xF)
1583 *ptr = (u32 & 0xF) + ((u32 & 0xF) > 9 ? '7' : '0');
1584 else
1585 *ptr = '.';
1586 }
1587 buf[8] = 0;
1588 return buf;
1589}
1590
1591/**
1592 * Returns timer name for debug purposes.
1593 *
1594 * @returns The timer name.
1595 *
1596 * @param pThis The device state structure.
1597 * @param hTimer The timer to name.
1598 */
1599DECLINLINE(const char *) e1kGetTimerName(PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1600{
1601 if (hTimer == pThis->hTIDTimer)
1602 return "TID";
1603 if (hTimer == pThis->hTADTimer)
1604 return "TAD";
1605 if (hTimer == pThis->hRIDTimer)
1606 return "RID";
1607 if (hTimer == pThis->hRADTimer)
1608 return "RAD";
1609 if (hTimer == pThis->hIntTimer)
1610 return "Int";
1611 if (hTimer == pThis->hTXDTimer)
1612 return "TXD";
1613 if (hTimer == pThis->hLUTimer)
1614 return "LinkUp";
1615 return "unknown";
1616}
1617
1618#endif /* LOG_ENABLED */
1619
1620/**
1621 * Arm a timer.
1622 *
1623 * @param pDevIns The device instance.
1624 * @param pThis Pointer to the device state structure.
1625 * @param hTimer The timer to arm.
1626 * @param uExpireIn Expiration interval in microseconds.
1627 */
1628DECLINLINE(void) e1kArmTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer, uint32_t uExpireIn)
1629{
1630 if (pThis->fLocked)
1631 return;
1632
1633 E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
1634 pThis->szPrf, e1kGetTimerName(pThis, hTimer), uExpireIn));
1635 int rc = PDMDevHlpTimerSetMicro(pDevIns, hTimer, uExpireIn);
1636 AssertRC(rc);
1637}
1638
1639#ifdef IN_RING3
1640/**
1641 * Cancel a timer.
1642 *
1643 * @param pDevIns The device instance.
1644 * @param pThis Pointer to the device state structure.
1645 * @param pTimer Pointer to the timer.
1646 */
1647DECLINLINE(void) e1kCancelTimer(PPDMDEVINS pDevIns, PE1KSTATE pThis, TMTIMERHANDLE hTimer)
1648{
1649 E1kLog2(("%s Stopping %s timer...\n",
1650 pThis->szPrf, e1kGetTimerName(pThis, hTimer)));
1651 int rc = PDMDevHlpTimerStop(pDevIns, hTimer);
1652 if (RT_FAILURE(rc))
1653 E1kLog2(("%s e1kCancelTimer: TMTimerStop(%s) failed with %Rrc\n",
1654 pThis->szPrf, e1kGetTimerName(pThis, hTimer), rc));
1655 RT_NOREF_PV(pThis);
1656}
1657#endif /* IN_RING3 */
1658
1659#define e1kCsEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->cs, rc)
1660#define e1kCsLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->cs)
1661
1662#define e1kCsRxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csRx, rc)
1663#define e1kCsRxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csRx)
1664#define e1kCsRxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csRx)
1665
1666#ifndef E1K_WITH_TX_CS
1667# define e1kCsTxEnter(ps, rc) VINF_SUCCESS
1668# define e1kCsTxLeave(ps) do { } while (0)
1669#else /* E1K_WITH_TX_CS */
1670# define e1kCsTxEnter(ps, rc) PDMDevHlpCritSectEnter(pDevIns, &ps->csTx, rc)
1671# define e1kCsTxLeave(ps) PDMDevHlpCritSectLeave(pDevIns, &ps->csTx)
1672# define e1kCsTxIsOwner(ps) PDMDevHlpCritSectIsOwner(pDevIns, &ps->csTx)
1673#endif /* E1K_WITH_TX_CS */
1674
1675
1676#ifdef E1K_WITH_TXD_CACHE
1677/*
1678 * Transmit Descriptor Register Context
1679 */
1680struct E1kTxDContext
1681{
1682 uint32_t tdlen;
1683 uint32_t tdh;
1684 uint32_t tdt;
1685};
1686typedef struct E1kTxDContext E1KTXDC, *PE1KTXDC;
1687
1688DECLINLINE(bool) e1kUpdateTxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pContext)
1689{
1690 Assert(e1kCsTxIsOwner(pThis));
1691 if (!e1kCsTxIsOwner(pThis))
1692 {
1693 memset(pContext, 0, sizeof(E1KTXDC));
1694 return false;
1695 }
1696 pContext->tdlen = TDLEN;
1697 pContext->tdh = TDH;
1698 pContext->tdt = TDT;
1699 uint32_t cTxRingSize = pContext->tdlen / sizeof(E1KTXDESC);
1700#ifdef DEBUG
1701 if (pContext->tdh >= cTxRingSize)
1702 {
1703 Log(("%s e1kUpdateTxDContext: will return false because TDH too big (%u >= %u)\n",
1704 pThis->szPrf, pContext->tdh, cTxRingSize));
1705 return VINF_SUCCESS;
1706 }
1707 if (pContext->tdt >= cTxRingSize)
1708 {
1709 Log(("%s e1kUpdateTxDContext: will return false because TDT too big (%u >= %u)\n",
1710 pThis->szPrf, pContext->tdt, cTxRingSize));
1711 return VINF_SUCCESS;
1712 }
1713#endif /* DEBUG */
1714 return pContext->tdh < cTxRingSize && pContext->tdt < cTxRingSize;
1715}
1716#endif /* E1K_WITH_TXD_CACHE */
1717#ifdef E1K_WITH_RXD_CACHE
1718/*
1719 * Receive Descriptor Register Context
1720 */
1721struct E1kRxDContext
1722{
1723 uint32_t rdlen;
1724 uint32_t rdh;
1725 uint32_t rdt;
1726};
1727typedef struct E1kRxDContext E1KRXDC, *PE1KRXDC;
1728
1729DECLINLINE(bool) e1kUpdateRxDContext(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pContext, const char *pcszCallee)
1730{
1731 Assert(e1kCsRxIsOwner(pThis));
1732 if (!e1kCsRxIsOwner(pThis))
1733 return false;
1734 pContext->rdlen = RDLEN;
1735 pContext->rdh = RDH;
1736 pContext->rdt = RDT;
1737 uint32_t cRxRingSize = pContext->rdlen / sizeof(E1KRXDESC);
1738 /*
1739 * Note that the checks for RDT are a bit different. Some guests, OS/2 for
1740 * example, intend to use all descriptors in RX ring, so they point RDT
1741 * right beyond the last descriptor in the ring. While this is not
1742 * acceptable for other registers, it works out fine for RDT.
1743 */
1744#ifdef DEBUG
1745 if (pContext->rdh >= cRxRingSize)
1746 {
1747 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDH too big (%u >= %u)\n",
1748 pThis->szPrf, pcszCallee, pContext->rdh, cRxRingSize));
1749 return VINF_SUCCESS;
1750 }
1751 if (pContext->rdt > cRxRingSize)
1752 {
1753 Log(("%s e1kUpdateRxDContext: called from %s, will return false because RDT too big (%u > %u)\n",
1754 pThis->szPrf, pcszCallee, pContext->rdt, cRxRingSize));
1755 return VINF_SUCCESS;
1756 }
1757#else /* !DEBUG */
1758 RT_NOREF(pcszCallee);
1759#endif /* !DEBUG */
1760 return pContext->rdh < cRxRingSize && pContext->rdt <= cRxRingSize; // && (RCTL & RCTL_EN);
1761}
1762#endif /* E1K_WITH_RXD_CACHE */
1763
1764/**
1765 * Wakeup the RX thread.
1766 */
1767static void e1kWakeupReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
1768{
1769 if ( pThis->fMaybeOutOfSpace
1770 && pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
1771 {
1772 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRxOverflowWakeup));
1773 E1kLog(("%s Waking up Out-of-RX-space semaphore\n", pThis->szPrf));
1774 int rc = PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
1775 AssertRC(rc);
1776 }
1777}
1778
1779#ifdef IN_RING3
1780
1781/**
1782 * Hardware reset. Revert all registers to initial values.
1783 *
1784 * @param pDevIns The device instance.
1785 * @param pThis The device state structure.
1786 * @param pThisCC The current context instance data.
1787 */
1788static void e1kR3HardReset(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
1789{
1790 E1kLog(("%s Hard reset triggered\n", pThis->szPrf));
1791 /* No interrupts should survive device reset, see @bugref(9556). */
1792 if (pThis->fIntRaised)
1793 {
1794 /* Lower(0) INTA(0) */
1795 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
1796 pThis->fIntRaised = false;
1797 E1kLog(("%s e1kR3HardReset: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
1798 }
1799 memset(pThis->auRegs, 0, sizeof(pThis->auRegs));
1800 memset(pThis->aRecAddr.au32, 0, sizeof(pThis->aRecAddr.au32));
1801#ifdef E1K_INIT_RA0
1802 memcpy(pThis->aRecAddr.au32, pThis->macConfigured.au8,
1803 sizeof(pThis->macConfigured.au8));
1804 pThis->aRecAddr.array[0].ctl |= RA_CTL_AV;
1805#endif /* E1K_INIT_RA0 */
1806 STATUS = 0x0081; /* SPEED=10b (1000 Mb/s), FD=1b (Full Duplex) */
1807 EECD = 0x0100; /* EE_PRES=1b (EEPROM present) */
1808 CTRL = 0x0a09; /* FRCSPD=1b SPEED=10b LRST=1b FD=1b */
1809 TSPMT = 0x01000400;/* TSMT=0400h TSPBP=0100h */
1810 Assert(GET_BITS(RCTL, BSIZE) == 0);
1811 pThis->u16RxBSize = 2048;
1812
1813 uint16_t u16LedCtl = 0x0602; /* LED0/LINK_UP#, LED2/LINK100# */
1814 pThisCC->eeprom.readWord(0x2F, &u16LedCtl); /* Read LEDCTL defaults from EEPROM */
1815 LEDCTL = 0x07008300 | (((uint32_t)u16LedCtl & 0xCF00) << 8) | (u16LedCtl & 0xCF); /* Only LED0 and LED2 defaults come from EEPROM */
1816
1817 /* Reset promiscuous mode */
1818 if (pThisCC->pDrvR3)
1819 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, false);
1820
1821#ifdef E1K_WITH_TXD_CACHE
1822 int rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
1823 if (RT_LIKELY(rc == VINF_SUCCESS))
1824 {
1825 pThis->nTxDFetched = 0;
1826 pThis->iTxDCurrent = 0;
1827 pThis->fGSO = false;
1828 pThis->cbTxAlloc = 0;
1829 e1kCsTxLeave(pThis);
1830 }
1831#endif /* E1K_WITH_TXD_CACHE */
1832#ifdef E1K_WITH_RXD_CACHE
1833 if (RT_LIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1834 {
1835 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
1836 e1kCsRxLeave(pThis);
1837 }
1838#endif /* E1K_WITH_RXD_CACHE */
1839#ifdef E1K_LSC_ON_RESET
1840 E1kLog(("%s Will trigger LSC in %d seconds...\n",
1841 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
1842 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
1843#endif /* E1K_LSC_ON_RESET */
1844}
1845
1846#endif /* IN_RING3 */
1847
1848/**
1849 * Compute Internet checksum.
1850 *
1851 * @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
1852 *
1853 * @param pThis The device state structure.
1854 * @param cpPacket The packet.
1855 * @param cb The size of the packet.
1856 * @param pszText A string denoting direction of packet transfer.
1857 *
1858 * @return The 1's complement of the 1's complement sum.
1859 *
1860 * @thread E1000_TX
1861 */
1862static uint16_t e1kCSum16(const void *pvBuf, size_t cb)
1863{
1864 uint32_t csum = 0;
1865 uint16_t *pu16 = (uint16_t *)pvBuf;
1866
1867 while (cb > 1)
1868 {
1869 csum += *pu16++;
1870 cb -= 2;
1871 }
1872 if (cb)
1873 csum += *(uint8_t*)pu16;
1874 while (csum >> 16)
1875 csum = (csum >> 16) + (csum & 0xFFFF);
1876 Assert(csum < 65536);
1877 return (uint16_t)~csum;
1878}
1879
1880/**
1881 * Dump a packet to debug log.
1882 *
1883 * @param pDevIns The device instance.
1884 * @param pThis The device state structure.
1885 * @param cpPacket The packet.
1886 * @param cb The size of the packet.
1887 * @param pszText A string denoting direction of packet transfer.
1888 * @thread E1000_TX
1889 */
1890DECLINLINE(void) e1kPacketDump(PPDMDEVINS pDevIns, PE1KSTATE pThis, const uint8_t *cpPacket, size_t cb, const char *pszText)
1891{
1892#ifdef DEBUG
1893 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1894 {
1895 Log4(("%s --- %s packet #%d: %RTmac => %RTmac (%d bytes) ---\n",
1896 pThis->szPrf, pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cb));
1897 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1898 {
1899 Log4(("%s --- IPv6: %RTnaipv6 => %RTnaipv6\n",
1900 pThis->szPrf, cpPacket+14+8, cpPacket+14+24));
1901 if (*(cpPacket+14+6) == 0x6)
1902 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1903 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1904 }
1905 else if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x800)
1906 {
1907 Log4(("%s --- IPv4: %RTnaipv4 => %RTnaipv4\n",
1908 pThis->szPrf, *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16)));
1909 if (*(cpPacket+14+6) == 0x6)
1910 Log4(("%s --- TCP: seq=%x ack=%x\n", pThis->szPrf,
1911 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1912 }
1913 E1kLog3(("%.*Rhxd\n", cb, cpPacket));
1914 e1kCsLeave(pThis);
1915 }
1916#else
1917 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
1918 {
1919 if (ntohs(*(uint16_t*)(cpPacket+12)) == 0x86DD)
1920 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv6 => %RTnaipv6, seq=%x ack=%x\n",
1921 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket, cpPacket+14+8, cpPacket+14+24,
1922 ntohl(*(uint32_t*)(cpPacket+14+40+4)), ntohl(*(uint32_t*)(cpPacket+14+40+8))));
1923 else
1924 E1kLogRel(("E1000: %s packet #%d, %RTmac => %RTmac, %RTnaipv4 => %RTnaipv4, seq=%x ack=%x\n",
1925 pszText, ++pThis->u32PktNo, cpPacket+6, cpPacket,
1926 *(uint32_t*)(cpPacket+14+12), *(uint32_t*)(cpPacket+14+16),
1927 ntohl(*(uint32_t*)(cpPacket+14+20+4)), ntohl(*(uint32_t*)(cpPacket+14+20+8))));
1928 e1kCsLeave(pThis);
1929 }
1930 RT_NOREF2(cb, pszText);
1931#endif
1932}
1933
1934/**
1935 * Determine the type of transmit descriptor.
1936 *
1937 * @returns Descriptor type. See E1K_DTYP_XXX defines.
1938 *
1939 * @param pDesc Pointer to descriptor union.
1940 * @thread E1000_TX
1941 */
1942DECLINLINE(int) e1kGetDescType(E1KTXDESC *pDesc)
1943{
1944 if (pDesc->legacy.cmd.fDEXT)
1945 return pDesc->context.dw2.u4DTYP;
1946 return E1K_DTYP_LEGACY;
1947}
1948
1949
1950#ifdef E1K_WITH_RXD_CACHE
1951/**
1952 * Return the number of RX descriptor that belong to the hardware.
1953 *
1954 * @returns the number of available descriptors in RX ring.
1955 * @param pRxdc The receive descriptor register context.
1956 * @thread ???
1957 */
1958DECLINLINE(uint32_t) e1kGetRxLen(PE1KRXDC pRxdc)
1959{
1960 /**
1961 * Make sure RDT won't change during computation. EMT may modify RDT at
1962 * any moment.
1963 */
1964 uint32_t rdt = pRxdc->rdt;
1965 return (pRxdc->rdh > rdt ? pRxdc->rdlen/sizeof(E1KRXDESC) : 0) + rdt - pRxdc->rdh;
1966}
1967
1968DECLINLINE(unsigned) e1kRxDInCache(PE1KSTATE pThis)
1969{
1970 return pThis->nRxDFetched > pThis->iRxDCurrent ?
1971 pThis->nRxDFetched - pThis->iRxDCurrent : 0;
1972}
1973
1974DECLINLINE(unsigned) e1kRxDIsCacheEmpty(PE1KSTATE pThis)
1975{
1976 return pThis->iRxDCurrent >= pThis->nRxDFetched;
1977}
1978
1979/**
1980 * Load receive descriptors from guest memory. The caller needs to be in Rx
1981 * critical section.
1982 *
1983 * We need two physical reads in case the tail wrapped around the end of RX
1984 * descriptor ring.
1985 *
1986 * @returns the actual number of descriptors fetched.
1987 * @param pDevIns The device instance.
1988 * @param pThis The device state structure.
1989 * @thread EMT, RX
1990 */
1991DECLINLINE(unsigned) e1kRxDPrefetch(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
1992{
1993 E1kLog3(("%s e1kRxDPrefetch: RDH=%x RDT=%x RDLEN=%x "
1994 "iRxDCurrent=%x nRxDFetched=%x\n",
1995 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pRxdc->rdlen, pThis->iRxDCurrent, pThis->nRxDFetched));
1996 /* We've already loaded pThis->nRxDFetched descriptors past RDH. */
1997 unsigned nDescsAvailable = e1kGetRxLen(pRxdc) - e1kRxDInCache(pThis);
1998 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_RXD_CACHE_SIZE - pThis->nRxDFetched);
1999 unsigned nDescsTotal = pRxdc->rdlen / sizeof(E1KRXDESC);
2000 Assert(nDescsTotal != 0);
2001 if (nDescsTotal == 0)
2002 return 0;
2003 unsigned nFirstNotLoaded = (pRxdc->rdh + e1kRxDInCache(pThis)) % nDescsTotal;
2004 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
2005 E1kLog3(("%s e1kRxDPrefetch: nDescsAvailable=%u nDescsToFetch=%u "
2006 "nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
2007 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
2008 nFirstNotLoaded, nDescsInSingleRead));
2009 if (nDescsToFetch == 0)
2010 return 0;
2011 E1KRXDESC* pFirstEmptyDesc = &pThis->aRxDescriptors[pThis->nRxDFetched];
2012 PDMDevHlpPCIPhysRead(pDevIns,
2013 ((uint64_t)RDBAH << 32) + RDBAL + nFirstNotLoaded * sizeof(E1KRXDESC),
2014 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KRXDESC));
2015 // uint64_t addrBase = ((uint64_t)RDBAH << 32) + RDBAL;
2016 // unsigned i, j;
2017 // for (i = pThis->nRxDFetched; i < pThis->nRxDFetched + nDescsInSingleRead; ++i)
2018 // {
2019 // pThis->aRxDescAddr[i] = addrBase + (nFirstNotLoaded + i - pThis->nRxDFetched) * sizeof(E1KRXDESC);
2020 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2021 // }
2022 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x(0x%x), RDLEN=%08x, RDH=%08x, RDT=%08x\n",
2023 pThis->szPrf, nDescsInSingleRead,
2024 RDBAH, RDBAL + pRxdc->rdh * sizeof(E1KRXDESC),
2025 nFirstNotLoaded, pRxdc->rdlen, pRxdc->rdh, pRxdc->rdt));
2026 if (nDescsToFetch > nDescsInSingleRead)
2027 {
2028 PDMDevHlpPCIPhysRead(pDevIns,
2029 ((uint64_t)RDBAH << 32) + RDBAL,
2030 pFirstEmptyDesc + nDescsInSingleRead,
2031 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KRXDESC));
2032 // Assert(i == pThis->nRxDFetched + nDescsInSingleRead);
2033 // for (j = 0; i < pThis->nRxDFetched + nDescsToFetch; ++i, ++j)
2034 // {
2035 // pThis->aRxDescAddr[i] = addrBase + j * sizeof(E1KRXDESC);
2036 // E1kLog3(("%s aRxDescAddr[%d] = %p\n", pThis->szPrf, i, pThis->aRxDescAddr[i]));
2037 // }
2038 E1kLog3(("%s Fetched %u RX descriptors at %08x%08x\n",
2039 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
2040 RDBAH, RDBAL));
2041 }
2042 pThis->nRxDFetched += nDescsToFetch;
2043 return nDescsToFetch;
2044}
2045
2046# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2047/**
2048 * Dump receive descriptor to debug log.
2049 *
2050 * @param pThis The device state structure.
2051 * @param pDesc Pointer to the descriptor.
2052 * @thread E1000_RX
2053 */
2054static void e1kPrintRDesc(PE1KSTATE pThis, E1KRXDESC *pDesc)
2055{
2056 RT_NOREF2(pThis, pDesc);
2057 E1kLog2(("%s <-- Receive Descriptor (%d bytes):\n", pThis->szPrf, pDesc->u16Length));
2058 E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
2059 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum));
2060 E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
2061 pDesc->status.fPIF ? "PIF" : "pif",
2062 pDesc->status.fIPCS ? "IPCS" : "ipcs",
2063 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
2064 pDesc->status.fVP ? "VP" : "vp",
2065 pDesc->status.fIXSM ? "IXSM" : "ixsm",
2066 pDesc->status.fEOP ? "EOP" : "eop",
2067 pDesc->status.fDD ? "DD" : "dd",
2068 pDesc->status.fRXE ? "RXE" : "rxe",
2069 pDesc->status.fIPE ? "IPE" : "ipe",
2070 pDesc->status.fTCPE ? "TCPE" : "tcpe",
2071 pDesc->status.fCE ? "CE" : "ce",
2072 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
2073 E1K_SPEC_VLAN(pDesc->status.u16Special),
2074 E1K_SPEC_PRI(pDesc->status.u16Special)));
2075}
2076# endif /* IN_RING3 */
2077#endif /* E1K_WITH_RXD_CACHE */
2078
2079/**
2080 * Dump transmit descriptor to debug log.
2081 *
2082 * @param pThis The device state structure.
2083 * @param pDesc Pointer to descriptor union.
2084 * @param pszDir A string denoting direction of descriptor transfer
2085 * @thread E1000_TX
2086 */
2087static void e1kPrintTDesc(PE1KSTATE pThis, E1KTXDESC *pDesc, const char *pszDir,
2088 unsigned uLevel = RTLOGGRPFLAGS_LEVEL_2)
2089{
2090 RT_NOREF4(pThis, pDesc, pszDir, uLevel);
2091
2092 /*
2093 * Unfortunately we cannot use our format handler here, we want R0 logging
2094 * as well.
2095 */
2096 switch (e1kGetDescType(pDesc))
2097 {
2098 case E1K_DTYP_CONTEXT:
2099 E1kLogX(uLevel, ("%s %s Context Transmit Descriptor %s\n",
2100 pThis->szPrf, pszDir, pszDir));
2101 E1kLogX(uLevel, (" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
2102 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
2103 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE));
2104 E1kLogX(uLevel, (" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
2105 pDesc->context.dw2.fIDE ? " IDE":"",
2106 pDesc->context.dw2.fRS ? " RS" :"",
2107 pDesc->context.dw2.fTSE ? " TSE":"",
2108 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
2109 pDesc->context.dw2.fTCP ? "TCP":"UDP",
2110 pDesc->context.dw2.u20PAYLEN,
2111 pDesc->context.dw3.u8HDRLEN,
2112 pDesc->context.dw3.u16MSS,
2113 pDesc->context.dw3.fDD?"DD":""));
2114 break;
2115 case E1K_DTYP_DATA:
2116 E1kLogX(uLevel, ("%s %s Data Transmit Descriptor (%d bytes) %s\n",
2117 pThis->szPrf, pszDir, pDesc->data.cmd.u20DTALEN, pszDir));
2118 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2119 pDesc->data.u64BufAddr,
2120 pDesc->data.cmd.u20DTALEN));
2121 E1kLogX(uLevel, (" DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
2122 pDesc->data.cmd.fIDE ? " IDE" :"",
2123 pDesc->data.cmd.fVLE ? " VLE" :"",
2124 pDesc->data.cmd.fRPS ? " RPS" :"",
2125 pDesc->data.cmd.fRS ? " RS" :"",
2126 pDesc->data.cmd.fTSE ? " TSE" :"",
2127 pDesc->data.cmd.fIFCS? " IFCS":"",
2128 pDesc->data.cmd.fEOP ? " EOP" :"",
2129 pDesc->data.dw3.fDD ? " DD" :"",
2130 pDesc->data.dw3.fEC ? " EC" :"",
2131 pDesc->data.dw3.fLC ? " LC" :"",
2132 pDesc->data.dw3.fTXSM? " TXSM":"",
2133 pDesc->data.dw3.fIXSM? " IXSM":"",
2134 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
2135 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
2136 E1K_SPEC_PRI(pDesc->data.dw3.u16Special)));
2137 break;
2138 case E1K_DTYP_LEGACY:
2139 E1kLogX(uLevel, ("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
2140 pThis->szPrf, pszDir, pDesc->legacy.cmd.u16Length, pszDir));
2141 E1kLogX(uLevel, (" Address=%16LX DTALEN=%05X\n",
2142 pDesc->data.u64BufAddr,
2143 pDesc->legacy.cmd.u16Length));
2144 E1kLogX(uLevel, (" CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
2145 pDesc->legacy.cmd.fIDE ? " IDE" :"",
2146 pDesc->legacy.cmd.fVLE ? " VLE" :"",
2147 pDesc->legacy.cmd.fRPS ? " RPS" :"",
2148 pDesc->legacy.cmd.fRS ? " RS" :"",
2149 pDesc->legacy.cmd.fIC ? " IC" :"",
2150 pDesc->legacy.cmd.fIFCS? " IFCS":"",
2151 pDesc->legacy.cmd.fEOP ? " EOP" :"",
2152 pDesc->legacy.dw3.fDD ? " DD" :"",
2153 pDesc->legacy.dw3.fEC ? " EC" :"",
2154 pDesc->legacy.dw3.fLC ? " LC" :"",
2155 pDesc->legacy.cmd.u8CSO,
2156 pDesc->legacy.dw3.u8CSS,
2157 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
2158 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
2159 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special)));
2160 break;
2161 default:
2162 E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
2163 pThis->szPrf, pszDir, pszDir));
2164 break;
2165 }
2166}
2167
2168/**
2169 * Raise an interrupt later.
2170 *
2171 * @param pThis The device state structure.
2172 */
2173DECLINLINE(void) e1kPostponeInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint64_t nsDeadline)
2174{
2175 if (!PDMDevHlpTimerIsActive(pDevIns, pThis->hIntTimer))
2176 PDMDevHlpTimerSetNano(pDevIns, pThis->hIntTimer, nsDeadline);
2177}
2178
2179/**
2180 * Raise interrupt if not masked.
2181 *
2182 * @param pThis The device state structure.
2183 */
2184static int e1kRaiseInterrupt(PPDMDEVINS pDevIns, PE1KSTATE pThis, int rcBusy, uint32_t u32IntCause)
2185{
2186 int rc = e1kCsEnter(pThis, rcBusy);
2187 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2188 return rc;
2189
2190 E1K_INC_ISTAT_CNT(pThis->uStatIntTry);
2191 ICR |= u32IntCause;
2192 if (ICR & IMS)
2193 {
2194 if (pThis->fIntRaised)
2195 {
2196 E1K_INC_ISTAT_CNT(pThis->uStatIntSkip);
2197 E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
2198 pThis->szPrf, ICR & IMS));
2199 }
2200 else
2201 {
2202 uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
2203 if (!!ITR && tsNow - pThis->u64AckedAt < ITR * 256
2204 && pThis->fItrEnabled && (pThis->fItrRxEnabled || !(ICR & ICR_RXT0)))
2205 {
2206 E1K_INC_ISTAT_CNT(pThis->uStatIntEarly);
2207 E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
2208 pThis->szPrf, (uint32_t)(tsNow - pThis->u64AckedAt), ITR * 256));
2209 e1kPostponeInterrupt(pDevIns, pThis, ITR * 256);
2210 }
2211 else
2212 {
2213
2214 /* Since we are delivering the interrupt now
2215 * there is no need to do it later -- stop the timer.
2216 */
2217 PDMDevHlpTimerStop(pDevIns, pThis->hIntTimer);
2218 E1K_INC_ISTAT_CNT(pThis->uStatInt);
2219 STAM_COUNTER_INC(&pThis->StatIntsRaised);
2220 /* Got at least one unmasked interrupt cause */
2221 pThis->fIntRaised = true;
2222 /* Raise(1) INTA(0) */
2223 E1kLogRel(("E1000: irq RAISED icr&mask=0x%x, icr=0x%x\n", ICR & IMS, ICR));
2224 PDMDevHlpPCISetIrq(pDevIns, 0, 1);
2225 E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
2226 pThis->szPrf, ICR & IMS));
2227 }
2228 }
2229 }
2230 else
2231 {
2232 E1K_INC_ISTAT_CNT(pThis->uStatIntMasked);
2233 E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
2234 pThis->szPrf, ICR, IMS));
2235 }
2236 e1kCsLeave(pThis);
2237 return VINF_SUCCESS;
2238}
2239
2240/**
2241 * Compute the physical address of the descriptor.
2242 *
2243 * @returns the physical address of the descriptor.
2244 *
2245 * @param baseHigh High-order 32 bits of descriptor table address.
2246 * @param baseLow Low-order 32 bits of descriptor table address.
2247 * @param idxDesc The descriptor index in the table.
2248 */
2249DECLINLINE(RTGCPHYS) e1kDescAddr(uint32_t baseHigh, uint32_t baseLow, uint32_t idxDesc)
2250{
2251 AssertCompile(sizeof(E1KRXDESC) == sizeof(E1KTXDESC));
2252 return ((uint64_t)baseHigh << 32) + baseLow + idxDesc * sizeof(E1KRXDESC);
2253}
2254
2255#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2256/**
2257 * Advance the head pointer of the receive descriptor queue.
2258 *
2259 * @remarks RDH always points to the next available RX descriptor.
2260 *
2261 * @param pDevIns The device instance.
2262 * @param pThis The device state structure.
2263 */
2264DECLINLINE(void) e1kAdvanceRDH(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2265{
2266 Assert(e1kCsRxIsOwner(pThis));
2267 //e1kCsEnter(pThis, RT_SRC_POS);
2268 if (++pRxdc->rdh * sizeof(E1KRXDESC) >= pRxdc->rdlen)
2269 pRxdc->rdh = 0;
2270 RDH = pRxdc->rdh; /* Sync the actual register and RXDC */
2271#ifdef E1K_WITH_RXD_CACHE
2272 /*
2273 * We need to fetch descriptors now as the guest may advance RDT all the way
2274 * to RDH as soon as we generate RXDMT0 interrupt. This is mostly to provide
2275 * compatibility with Phar Lap ETS, see @bugref(7346). Note that we do not
2276 * check if the receiver is enabled. It must be, otherwise we won't get here
2277 * in the first place.
2278 *
2279 * Note that we should have moved both RDH and iRxDCurrent by now.
2280 */
2281 if (e1kRxDIsCacheEmpty(pThis))
2282 {
2283 /* Cache is empty, reset it and check if we can fetch more. */
2284 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2285 E1kLog3(("%s e1kAdvanceRDH: Rx cache is empty, RDH=%x RDT=%x "
2286 "iRxDCurrent=%x nRxDFetched=%x\n",
2287 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, pThis->iRxDCurrent, pThis->nRxDFetched));
2288 e1kRxDPrefetch(pDevIns, pThis, pRxdc);
2289 }
2290#endif /* E1K_WITH_RXD_CACHE */
2291 /*
2292 * Compute current receive queue length and fire RXDMT0 interrupt
2293 * if we are low on receive buffers
2294 */
2295 uint32_t uRQueueLen = pRxdc->rdh>pRxdc->rdt ? pRxdc->rdlen/sizeof(E1KRXDESC)-pRxdc->rdh+pRxdc->rdt : pRxdc->rdt-pRxdc->rdh;
2296 /*
2297 * The minimum threshold is controlled by RDMTS bits of RCTL:
2298 * 00 = 1/2 of RDLEN
2299 * 01 = 1/4 of RDLEN
2300 * 10 = 1/8 of RDLEN
2301 * 11 = reserved
2302 */
2303 uint32_t uMinRQThreshold = pRxdc->rdlen / sizeof(E1KRXDESC) / (2 << GET_BITS(RCTL, RDMTS));
2304 if (uRQueueLen <= uMinRQThreshold)
2305 {
2306 E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2307 E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
2308 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen, uMinRQThreshold));
2309 E1K_INC_ISTAT_CNT(pThis->uStatIntRXDMT0);
2310 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXDMT0);
2311 }
2312 E1kLog2(("%s e1kAdvanceRDH: at exit RDH=%x RDT=%x len=%x\n",
2313 pThis->szPrf, pRxdc->rdh, pRxdc->rdt, uRQueueLen));
2314 //e1kCsLeave(pThis);
2315}
2316#endif /* IN_RING3 */
2317
2318#ifdef E1K_WITH_RXD_CACHE
2319
2320# ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2321
2322/**
2323 * Obtain the next RX descriptor from RXD cache, fetching descriptors from the
2324 * RX ring if the cache is empty.
2325 *
2326 * Note that we cannot advance the cache pointer (iRxDCurrent) yet as it will
2327 * go out of sync with RDH which will cause trouble when EMT checks if the
2328 * cache is empty to do pre-fetch @bugref(6217).
2329 *
2330 * @param pDevIns The device instance.
2331 * @param pThis The device state structure.
2332 * @thread RX
2333 */
2334DECLINLINE(E1KRXDESC *) e1kRxDGet(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KRXDC pRxdc)
2335{
2336 Assert(e1kCsRxIsOwner(pThis));
2337 /* Check the cache first. */
2338 if (pThis->iRxDCurrent < pThis->nRxDFetched)
2339 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2340 /* Cache is empty, reset it and check if we can fetch more. */
2341 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
2342 if (e1kRxDPrefetch(pDevIns, pThis, pRxdc))
2343 return &pThis->aRxDescriptors[pThis->iRxDCurrent];
2344 /* Out of Rx descriptors. */
2345 return NULL;
2346}
2347
2348
2349/**
2350 * Return the RX descriptor obtained with e1kRxDGet() and advance the cache
2351 * pointer. The descriptor gets written back to the RXD ring.
2352 *
2353 * @param pDevIns The device instance.
2354 * @param pThis The device state structure.
2355 * @param pDesc The descriptor being "returned" to the RX ring.
2356 * @thread RX
2357 */
2358DECLINLINE(void) e1kRxDPut(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC* pDesc, PE1KRXDC pRxdc)
2359{
2360 Assert(e1kCsRxIsOwner(pThis));
2361 pThis->iRxDCurrent++;
2362 // Assert(pDesc >= pThis->aRxDescriptors);
2363 // Assert(pDesc < pThis->aRxDescriptors + E1K_RXD_CACHE_SIZE);
2364 // uint64_t addr = e1kDescAddr(RDBAH, RDBAL, RDH);
2365 // uint32_t rdh = RDH;
2366 // Assert(pThis->aRxDescAddr[pDesc - pThis->aRxDescriptors] == addr);
2367 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, pRxdc->rdh), pDesc, sizeof(E1KRXDESC));
2368 /*
2369 * We need to print the descriptor before advancing RDH as it may fetch new
2370 * descriptors into the cache.
2371 */
2372 e1kPrintRDesc(pThis, pDesc);
2373 e1kAdvanceRDH(pDevIns, pThis, pRxdc);
2374}
2375
2376/**
2377 * Store a fragment of received packet at the specifed address.
2378 *
2379 * @param pDevIns The device instance.
2380 * @param pThis The device state structure.
2381 * @param pDesc The next available RX descriptor.
2382 * @param pvBuf The fragment.
2383 * @param cb The size of the fragment.
2384 */
2385static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2386{
2387 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2388 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n",
2389 pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2390 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2391 pDesc->u16Length = (uint16_t)cb;
2392 Assert(pDesc->u16Length == cb);
2393 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2394 RT_NOREF(pThis);
2395}
2396
2397# endif /* IN_RING3 */
2398
2399#else /* !E1K_WITH_RXD_CACHE */
2400
2401/**
2402 * Store a fragment of received packet that fits into the next available RX
2403 * buffer.
2404 *
2405 * @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
2406 *
2407 * @param pDevIns The device instance.
2408 * @param pThis The device state structure.
2409 * @param pDesc The next available RX descriptor.
2410 * @param pvBuf The fragment.
2411 * @param cb The size of the fragment.
2412 */
2413static void e1kStoreRxFragment(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
2414{
2415 STAM_PROFILE_ADV_START(&pThis->StatReceiveStore, a);
2416 E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pThis->szPrf, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
2417 PDMDevHlpPCIPhysWrite(pDevIns, pDesc->u64BufAddr, pvBuf, cb);
2418 pDesc->u16Length = (uint16_t)cb; Assert(pDesc->u16Length == cb);
2419 /* Write back the descriptor */
2420 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2421 e1kPrintRDesc(pThis, pDesc);
2422 E1kLogRel(("E1000: Wrote back RX desc, RDH=%x\n", RDH));
2423 /* Advance head */
2424 e1kAdvanceRDH(pDevIns, pThis);
2425 //E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", pThis->szPrf, pDesc->fEOP, RDTR, RADV));
2426 if (pDesc->status.fEOP)
2427 {
2428 /* Complete packet has been stored -- it is time to let the guest know. */
2429#ifdef E1K_USE_RX_TIMERS
2430 if (RDTR)
2431 {
2432 /* Arm the timer to fire in RDTR usec (discard .024) */
2433 e1kArmTimer(pDevIns, pThis, pThis->hRIDTimer, RDTR);
2434 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2435 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->CTX_SUFF(pRADTimer)))
2436 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2437 }
2438 else
2439 {
2440#endif
2441 /* 0 delay means immediate interrupt */
2442 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2443 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2444#ifdef E1K_USE_RX_TIMERS
2445 }
2446#endif
2447 }
2448 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveStore, a);
2449}
2450
2451#endif /* !E1K_WITH_RXD_CACHE */
2452
2453/**
2454 * Returns true if it is a broadcast packet.
2455 *
2456 * @returns true if destination address indicates broadcast.
2457 * @param pvBuf The ethernet packet.
2458 */
2459DECLINLINE(bool) e1kIsBroadcast(const void *pvBuf)
2460{
2461 static const uint8_t s_abBcastAddr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2462 return memcmp(pvBuf, s_abBcastAddr, sizeof(s_abBcastAddr)) == 0;
2463}
2464
2465/**
2466 * Returns true if it is a multicast packet.
2467 *
2468 * @remarks returns true for broadcast packets as well.
2469 * @returns true if destination address indicates multicast.
2470 * @param pvBuf The ethernet packet.
2471 */
2472DECLINLINE(bool) e1kIsMulticast(const void *pvBuf)
2473{
2474 return (*(char*)pvBuf) & 1;
2475}
2476
2477#ifdef IN_RING3 /* currently only used in ring-3 due to stack space requirements of the caller */
2478/**
2479 * Set IXSM, IPCS and TCPCS flags according to the packet type.
2480 *
2481 * @remarks We emulate checksum offloading for major packets types only.
2482 *
2483 * @returns VBox status code.
2484 * @param pThis The device state structure.
2485 * @param pFrame The available data.
2486 * @param cb Number of bytes available in the buffer.
2487 * @param status Bit fields containing status info.
2488 */
2489static int e1kRxChecksumOffload(PE1KSTATE pThis, const uint8_t *pFrame, size_t cb, E1KRXDST *pStatus)
2490{
2491 /** @todo
2492 * It is not safe to bypass checksum verification for packets coming
2493 * from real wire. We currently unable to tell where packets are
2494 * coming from so we tell the driver to ignore our checksum flags
2495 * and do verification in software.
2496 */
2497# if 0
2498 uint16_t uEtherType = ntohs(*(uint16_t*)(pFrame + 12));
2499
2500 E1kLog2(("%s e1kRxChecksumOffload: EtherType=%x\n", pThis->szPrf, uEtherType));
2501
2502 switch (uEtherType)
2503 {
2504 case 0x800: /* IPv4 */
2505 {
2506 pStatus->fIXSM = false;
2507 pStatus->fIPCS = true;
2508 PRTNETIPV4 pIpHdr4 = (PRTNETIPV4)(pFrame + 14);
2509 /* TCP/UDP checksum offloading works with TCP and UDP only */
2510 pStatus->fTCPCS = pIpHdr4->ip_p == 6 || pIpHdr4->ip_p == 17;
2511 break;
2512 }
2513 case 0x86DD: /* IPv6 */
2514 pStatus->fIXSM = false;
2515 pStatus->fIPCS = false;
2516 pStatus->fTCPCS = true;
2517 break;
2518 default: /* ARP, VLAN, etc. */
2519 pStatus->fIXSM = true;
2520 break;
2521 }
2522# else
2523 pStatus->fIXSM = true;
2524 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb);
2525# endif
2526 return VINF_SUCCESS;
2527}
2528#endif /* IN_RING3 */
2529
2530/**
2531 * Pad and store received packet.
2532 *
2533 * @remarks Make sure that the packet appears to upper layer as one coming
2534 * from real Ethernet: pad it and insert FCS.
2535 *
2536 * @returns VBox status code.
2537 * @param pDevIns The device instance.
2538 * @param pThis The device state structure.
2539 * @param pvBuf The available data.
2540 * @param cb Number of bytes available in the buffer.
2541 * @param status Bit fields containing status info.
2542 */
2543static int e1kHandleRxPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST status)
2544{
2545#if defined(IN_RING3) /** @todo Remove this extra copying, it's gonna make us run out of kernel / hypervisor stack! */
2546 uint8_t rxPacket[E1K_MAX_RX_PKT_SIZE];
2547 uint8_t *ptr = rxPacket;
2548# ifdef E1K_WITH_RXD_CACHE
2549 E1KRXDC rxdc;
2550# endif /* E1K_WITH_RXD_CACHE */
2551
2552 int rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2553 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2554 return rc;
2555# ifdef E1K_WITH_RXD_CACHE
2556 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2557 {
2558 e1kCsRxLeave(pThis);
2559 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2560 return VINF_SUCCESS;
2561 }
2562# endif /* E1K_WITH_RXD_CACHE */
2563
2564 if (cb > 70) /* unqualified guess */
2565 pThis->led.Asserted.s.fReading = pThis->led.Actual.s.fReading = 1;
2566
2567 Assert(cb <= E1K_MAX_RX_PKT_SIZE);
2568 Assert(cb > 16);
2569 size_t cbMax = ((RCTL & RCTL_LPE) ? E1K_MAX_RX_PKT_SIZE - 4 : 1518) - (status.fVP ? 0 : 4);
2570 E1kLog3(("%s Max RX packet size is %u\n", pThis->szPrf, cbMax));
2571 if (status.fVP)
2572 {
2573 /* VLAN packet -- strip VLAN tag in VLAN mode */
2574 if ((CTRL & CTRL_VME) && cb > 16)
2575 {
2576 uint16_t *u16Ptr = (uint16_t*)pvBuf;
2577 memcpy(rxPacket, pvBuf, 12); /* Copy src and dst addresses */
2578 status.u16Special = RT_BE2H_U16(u16Ptr[7]); /* Extract VLAN tag */
2579 memcpy(rxPacket + 12, (uint8_t*)pvBuf + 16, cb - 16); /* Copy the rest of the packet */
2580 cb -= 4;
2581 E1kLog3(("%s Stripped tag for VLAN %u (cb=%u)\n",
2582 pThis->szPrf, status.u16Special, cb));
2583 }
2584 else
2585 {
2586 status.fVP = false; /* Set VP only if we stripped the tag */
2587 memcpy(rxPacket, pvBuf, cb);
2588 }
2589 }
2590 else
2591 memcpy(rxPacket, pvBuf, cb);
2592 /* Pad short packets */
2593 if (cb < 60)
2594 {
2595 memset(rxPacket + cb, 0, 60 - cb);
2596 cb = 60;
2597 }
2598 if (!(RCTL & RCTL_SECRC) && cb <= cbMax)
2599 {
2600 STAM_PROFILE_ADV_START(&pThis->StatReceiveCRC, a);
2601 /*
2602 * Add FCS if CRC stripping is not enabled. Since the value of CRC
2603 * is ignored by most of drivers we may as well save us the trouble
2604 * of calculating it (see EthernetCRC CFGM parameter).
2605 */
2606 if (pThis->fEthernetCRC)
2607 *(uint32_t*)(rxPacket + cb) = RTCrc32(rxPacket, cb);
2608 cb += sizeof(uint32_t);
2609 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveCRC, a);
2610 E1kLog3(("%s Added FCS (cb=%u)\n", pThis->szPrf, cb));
2611 }
2612 /* Compute checksum of complete packet */
2613 size_t cbCSumStart = RT_MIN(GET_BITS(RXCSUM, PCSS), cb);
2614 uint16_t checksum = e1kCSum16(rxPacket + cbCSumStart, cb - cbCSumStart);
2615 e1kRxChecksumOffload(pThis, rxPacket, cb, &status);
2616
2617 /* Update stats */
2618 E1K_INC_CNT32(GPRC);
2619 if (e1kIsBroadcast(pvBuf))
2620 E1K_INC_CNT32(BPRC);
2621 else if (e1kIsMulticast(pvBuf))
2622 E1K_INC_CNT32(MPRC);
2623 /* Update octet receive counter */
2624 E1K_ADD_CNT64(GORCL, GORCH, cb);
2625 STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cb);
2626 if (cb == 64)
2627 E1K_INC_CNT32(PRC64);
2628 else if (cb < 128)
2629 E1K_INC_CNT32(PRC127);
2630 else if (cb < 256)
2631 E1K_INC_CNT32(PRC255);
2632 else if (cb < 512)
2633 E1K_INC_CNT32(PRC511);
2634 else if (cb < 1024)
2635 E1K_INC_CNT32(PRC1023);
2636 else
2637 E1K_INC_CNT32(PRC1522);
2638
2639 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm);
2640
2641# ifdef E1K_WITH_RXD_CACHE
2642 while (cb > 0)
2643 {
2644 E1KRXDESC *pDesc = e1kRxDGet(pDevIns, pThis, &rxdc);
2645
2646 if (pDesc == NULL)
2647 {
2648 E1kLog(("%s Out of receive buffers, dropping the packet "
2649 "(cb=%u, in_cache=%u, RDH=%x RDT=%x)\n",
2650 pThis->szPrf, cb, e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt));
2651 break;
2652 }
2653# else /* !E1K_WITH_RXD_CACHE */
2654 if (RDH == RDT)
2655 {
2656 E1kLog(("%s Out of receive buffers, dropping the packet\n",
2657 pThis->szPrf));
2658 }
2659 /* Store the packet to receive buffers */
2660 while (RDH != RDT)
2661 {
2662 /* Load the descriptor pointed by head */
2663 E1KRXDESC desc, *pDesc = &desc;
2664 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
2665# endif /* !E1K_WITH_RXD_CACHE */
2666 if (pDesc->u64BufAddr)
2667 {
2668 uint16_t u16RxBufferSize = pThis->u16RxBSize; /* see @bugref{9427} */
2669
2670 /* Update descriptor */
2671 pDesc->status = status;
2672 pDesc->u16Checksum = checksum;
2673 pDesc->status.fDD = true;
2674
2675 /*
2676 * We need to leave Rx critical section here or we risk deadlocking
2677 * with EMT in e1kRegWriteRDT when the write is to an unallocated
2678 * page or has an access handler associated with it.
2679 * Note that it is safe to leave the critical section here since
2680 * e1kRegWriteRDT() never modifies RDH. It never touches already
2681 * fetched RxD cache entries either.
2682 */
2683 if (cb > u16RxBufferSize)
2684 {
2685 pDesc->status.fEOP = false;
2686 e1kCsRxLeave(pThis);
2687 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, u16RxBufferSize);
2688 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2689 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2690 return rc;
2691# ifdef E1K_WITH_RXD_CACHE
2692 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2693 {
2694 e1kCsRxLeave(pThis);
2695 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2696 return VINF_SUCCESS;
2697 }
2698# endif /* E1K_WITH_RXD_CACHE */
2699 ptr += u16RxBufferSize;
2700 cb -= u16RxBufferSize;
2701 }
2702 else
2703 {
2704 pDesc->status.fEOP = true;
2705 e1kCsRxLeave(pThis);
2706 e1kStoreRxFragment(pDevIns, pThis, pDesc, ptr, cb);
2707# ifdef E1K_WITH_RXD_CACHE
2708 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY);
2709 if (RT_UNLIKELY(rc != VINF_SUCCESS))
2710 return rc;
2711 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kHandleRxPacket")))
2712 {
2713 e1kCsRxLeave(pThis);
2714 E1kLog(("%s e1kHandleRxPacket: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
2715 return VINF_SUCCESS;
2716 }
2717 cb = 0;
2718# else /* !E1K_WITH_RXD_CACHE */
2719 pThis->led.Actual.s.fReading = 0;
2720 return VINF_SUCCESS;
2721# endif /* !E1K_WITH_RXD_CACHE */
2722 }
2723 /*
2724 * Note: RDH is advanced by e1kStoreRxFragment if E1K_WITH_RXD_CACHE
2725 * is not defined.
2726 */
2727 }
2728# ifdef E1K_WITH_RXD_CACHE
2729 /* Write back the descriptor. */
2730 pDesc->status.fDD = true;
2731 e1kRxDPut(pDevIns, pThis, pDesc, &rxdc);
2732# else /* !E1K_WITH_RXD_CACHE */
2733 else
2734 {
2735 /* Write back the descriptor. */
2736 pDesc->status.fDD = true;
2737 PDMDevHlpPCIPhysWrite(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
2738 e1kAdvanceRDH(pDevIns, pThis);
2739 }
2740# endif /* !E1K_WITH_RXD_CACHE */
2741 }
2742
2743 if (cb > 0)
2744 E1kLog(("%s Out of receive buffers, dropping %u bytes", pThis->szPrf, cb));
2745
2746 pThis->led.Actual.s.fReading = 0;
2747
2748 e1kCsRxLeave(pThis);
2749# ifdef E1K_WITH_RXD_CACHE
2750 /* Complete packet has been stored -- it is time to let the guest know. */
2751# ifdef E1K_USE_RX_TIMERS
2752 if (RDTR)
2753 {
2754 /* Arm the timer to fire in RDTR usec (discard .024) */
2755 e1kArmTimer(pThis, pThis->hRIDTimer, RDTR);
2756 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
2757 if (RADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hRADTimer))
2758 e1kArmTimer(pThis, pThis->hRADTimer, RADV);
2759 }
2760 else
2761 {
2762# endif /* E1K_USE_RX_TIMERS */
2763 /* 0 delay means immediate interrupt */
2764 E1K_INC_ISTAT_CNT(pThis->uStatIntRx);
2765 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_RXT0);
2766# ifdef E1K_USE_RX_TIMERS
2767 }
2768# endif /* E1K_USE_RX_TIMERS */
2769# endif /* E1K_WITH_RXD_CACHE */
2770
2771 return VINF_SUCCESS;
2772#else /* !IN_RING3 */
2773 RT_NOREF(pDevIns, pThis, pvBuf, cb, status);
2774 return VERR_INTERNAL_ERROR_2;
2775#endif /* !IN_RING3 */
2776}
2777
2778
2779#ifdef IN_RING3
2780/**
2781 * Bring the link up after the configured delay, 5 seconds by default.
2782 *
2783 * @param pDevIns The device instance.
2784 * @param pThis The device state structure.
2785 * @thread any
2786 */
2787DECLINLINE(void) e1kBringLinkUpDelayed(PPDMDEVINS pDevIns, PE1KSTATE pThis)
2788{
2789 E1kLog(("%s Will bring up the link in %d seconds...\n",
2790 pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
2791 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, pThis->cMsLinkUpDelay * 1000);
2792}
2793
2794/**
2795 * Bring up the link immediately.
2796 *
2797 * @param pDevIns The device instance.
2798 * @param pThis The device state structure.
2799 * @param pThisCC The current context instance data.
2800 */
2801DECLINLINE(void) e1kR3LinkUp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2802{
2803 E1kLog(("%s Link is up\n", pThis->szPrf));
2804 STATUS |= STATUS_LU;
2805 Phy::setLinkStatus(&pThis->phy, true);
2806 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2807 if (pThisCC->pDrvR3)
2808 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_UP);
2809 /* Trigger processing of pending TX descriptors (see @bugref{8942}). */
2810 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
2811}
2812
2813/**
2814 * Bring down the link immediately.
2815 *
2816 * @param pDevIns The device instance.
2817 * @param pThis The device state structure.
2818 * @param pThisCC The current context instance data.
2819 */
2820DECLINLINE(void) e1kR3LinkDown(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2821{
2822 E1kLog(("%s Link is down\n", pThis->szPrf));
2823 STATUS &= ~STATUS_LU;
2824#ifdef E1K_LSC_ON_RESET
2825 Phy::setLinkStatus(&pThis->phy, false);
2826#endif /* E1K_LSC_ON_RESET */
2827 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2828 if (pThisCC->pDrvR3)
2829 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2830}
2831
2832/**
2833 * Bring down the link temporarily.
2834 *
2835 * @param pDevIns The device instance.
2836 * @param pThis The device state structure.
2837 * @param pThisCC The current context instance data.
2838 */
2839DECLINLINE(void) e1kR3LinkDownTemp(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC)
2840{
2841 E1kLog(("%s Link is down temporarily\n", pThis->szPrf));
2842 STATUS &= ~STATUS_LU;
2843 Phy::setLinkStatus(&pThis->phy, false);
2844 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_LSC);
2845 /*
2846 * Notifying the associated driver that the link went down (even temporarily)
2847 * seems to be the right thing, but it was not done before. This may cause
2848 * a regression if the driver does not expect the link to go down as a result
2849 * of sending PDMNETWORKLINKSTATE_DOWN_RESUME to this device. Earlier versions
2850 * of code notified the driver that the link was up! See @bugref{7057}.
2851 */
2852 if (pThisCC->pDrvR3)
2853 pThisCC->pDrvR3->pfnNotifyLinkChanged(pThisCC->pDrvR3, PDMNETWORKLINKSTATE_DOWN);
2854 e1kBringLinkUpDelayed(pDevIns, pThis);
2855}
2856#endif /* IN_RING3 */
2857
2858#if 0 /* unused */
2859/**
2860 * Read handler for Device Status register.
2861 *
2862 * Get the link status from PHY.
2863 *
2864 * @returns VBox status code.
2865 *
2866 * @param pThis The device state structure.
2867 * @param offset Register offset in memory-mapped frame.
2868 * @param index Register index in register array.
2869 * @param mask Used to implement partial reads (8 and 16-bit).
2870 */
2871static int e1kRegReadCTRL(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
2872{
2873 E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
2874 pThis->szPrf, (CTRL & CTRL_MDIO_DIR)?"OUT":"IN ",
2875 (CTRL & CTRL_MDC_DIR)?"OUT":"IN ", !!(CTRL & CTRL_MDC)));
2876 if ((CTRL & CTRL_MDIO_DIR) == 0 && (CTRL & CTRL_MDC))
2877 {
2878 /* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
2879 if (Phy::readMDIO(&pThis->phy))
2880 *pu32Value = CTRL | CTRL_MDIO;
2881 else
2882 *pu32Value = CTRL & ~CTRL_MDIO;
2883 E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
2884 pThis->szPrf, !!(*pu32Value & CTRL_MDIO)));
2885 }
2886 else
2887 {
2888 /* MDIO pin is used for output, ignore it */
2889 *pu32Value = CTRL;
2890 }
2891 return VINF_SUCCESS;
2892}
2893#endif /* unused */
2894
2895/**
2896 * A helper function to detect the link state to the other side of "the wire".
2897 *
2898 * When deciding to bring up the link we need to take into account both if the
2899 * cable is connected and if our device is actually connected to the outside
2900 * world. If no driver is attached we won't be able to allocate TX buffers,
2901 * which will prevent us from TX descriptor processing, which will result in
2902 * "TX unit hang" in the guest.
2903 *
2904 * @returns true if the device is connected to something.
2905 *
2906 * @param pDevIns The device instance.
2907 */
2908DECLINLINE(bool) e1kIsConnected(PPDMDEVINS pDevIns)
2909{
2910 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2911 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
2912 return pThis->fCableConnected && pThisCC->CTX_SUFF(pDrv);
2913}
2914
2915/**
2916 * A callback used by PHY to indicate that the link needs to be updated due to
2917 * reset of PHY.
2918 *
2919 * @param pDevIns The device instance.
2920 * @thread any
2921 */
2922void e1kPhyLinkResetCallback(PPDMDEVINS pDevIns)
2923{
2924 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
2925
2926 /* Make sure we have cable connected and MAC can talk to PHY */
2927 if (e1kIsConnected(pDevIns) && (CTRL & CTRL_SLU))
2928 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2929}
2930
2931/**
2932 * Write handler for Device Control register.
2933 *
2934 * Handles reset.
2935 *
2936 * @param pThis The device state structure.
2937 * @param offset Register offset in memory-mapped frame.
2938 * @param index Register index in register array.
2939 * @param value The value to store.
2940 * @param mask Used to implement partial writes (8 and 16-bit).
2941 * @thread EMT
2942 */
2943static int e1kRegWriteCTRL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
2944{
2945 int rc = VINF_SUCCESS;
2946
2947 if (value & CTRL_RESET)
2948 { /* RST */
2949#ifndef IN_RING3
2950 return VINF_IOM_R3_MMIO_WRITE;
2951#else
2952 e1kR3HardReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
2953#endif
2954 }
2955 else
2956 {
2957#ifdef E1K_LSC_ON_SLU
2958 /*
2959 * When the guest changes 'Set Link Up' bit from 0 to 1 we check if
2960 * the link is down and the cable is connected, and if they are we
2961 * bring the link up, see @bugref{8624}.
2962 */
2963 if ( (value & CTRL_SLU)
2964 && !(CTRL & CTRL_SLU)
2965 && pThis->fCableConnected
2966 && !(STATUS & STATUS_LU))
2967 {
2968 /* It should take about 2 seconds for the link to come up */
2969 e1kArmTimer(pDevIns, pThis, pThis->hLUTimer, E1K_INIT_LINKUP_DELAY_US);
2970 }
2971#else /* !E1K_LSC_ON_SLU */
2972 if ( (value & CTRL_SLU)
2973 && !(CTRL & CTRL_SLU)
2974 && e1kIsConnected(pDevIns)
2975 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hLUTimer))
2976 {
2977 /* PXE does not use LSC interrupts, see @bugref{9113}. */
2978 STATUS |= STATUS_LU;
2979 }
2980#endif /* !E1K_LSC_ON_SLU */
2981 if ((value & CTRL_VME) != (CTRL & CTRL_VME))
2982 {
2983 E1kLog(("%s VLAN Mode %s\n", pThis->szPrf, (value & CTRL_VME) ? "Enabled" : "Disabled"));
2984 }
2985 Log7(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
2986 pThis->szPrf, (value & CTRL_MDIO_DIR)?"OUT":"IN ",
2987 (value & CTRL_MDC_DIR)?"OUT":"IN ", (value & CTRL_MDC)?"HIGH":"LOW ", !!(value & CTRL_MDIO)));
2988 if (value & CTRL_MDC)
2989 {
2990 if (value & CTRL_MDIO_DIR)
2991 {
2992 Log7(("%s e1kRegWriteCTRL: Phy::writeMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
2993 /* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
2994 Phy::writeMDIO(&pThis->phy, !!(value & CTRL_MDIO), pDevIns);
2995 }
2996 else
2997 {
2998 if (Phy::readMDIO(&pThis->phy))
2999 value |= CTRL_MDIO;
3000 else
3001 value &= ~CTRL_MDIO;
3002 Log7(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n", pThis->szPrf, !!(value & CTRL_MDIO)));
3003 }
3004 }
3005 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3006 }
3007
3008 return rc;
3009}
3010
3011/**
3012 * Write handler for EEPROM/Flash Control/Data register.
3013 *
3014 * Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
3015 *
3016 * @param pThis The device state structure.
3017 * @param offset Register offset in memory-mapped frame.
3018 * @param index Register index in register array.
3019 * @param value The value to store.
3020 * @param mask Used to implement partial writes (8 and 16-bit).
3021 * @thread EMT
3022 */
3023static int e1kRegWriteEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3024{
3025 RT_NOREF(pDevIns, offset, index);
3026#ifdef IN_RING3
3027 /* So far we are concerned with lower byte only */
3028 if ((EECD & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3029 {
3030 /* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
3031 /* Note: 82543GC does not need to request EEPROM access */
3032 STAM_PROFILE_ADV_START(&pThis->StatEEPROMWrite, a);
3033 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3034 pThisCC->eeprom.write(value & EECD_EE_WIRES);
3035 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMWrite, a);
3036 }
3037 if (value & EECD_EE_REQ)
3038 EECD |= EECD_EE_REQ|EECD_EE_GNT;
3039 else
3040 EECD &= ~EECD_EE_GNT;
3041 //e1kRegWriteDefault(pThis, offset, index, value );
3042
3043 return VINF_SUCCESS;
3044#else /* !IN_RING3 */
3045 RT_NOREF(pThis, value);
3046 return VINF_IOM_R3_MMIO_WRITE;
3047#endif /* !IN_RING3 */
3048}
3049
3050/**
3051 * Read handler for EEPROM/Flash Control/Data register.
3052 *
3053 * Lower 4 bits come from EEPROM device if EEPROM access has been granted.
3054 *
3055 * @returns VBox status code.
3056 *
3057 * @param pThis The device state structure.
3058 * @param offset Register offset in memory-mapped frame.
3059 * @param index Register index in register array.
3060 * @param mask Used to implement partial reads (8 and 16-bit).
3061 * @thread EMT
3062 */
3063static int e1kRegReadEECD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3064{
3065#ifdef IN_RING3
3066 uint32_t value = 0; /* Get rid of false positive in parfait. */
3067 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3068 if (RT_SUCCESS(rc))
3069 {
3070 if ((value & EECD_EE_GNT) || pThis->eChip == E1K_CHIP_82543GC)
3071 {
3072 /* Note: 82543GC does not need to request EEPROM access */
3073 /* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
3074 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3075 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3076 value |= pThisCC->eeprom.read();
3077 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3078 }
3079 *pu32Value = value;
3080 }
3081
3082 return rc;
3083#else /* !IN_RING3 */
3084 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value);
3085 return VINF_IOM_R3_MMIO_READ;
3086#endif /* !IN_RING3 */
3087}
3088
3089/**
3090 * Write handler for EEPROM Read register.
3091 *
3092 * Handles EEPROM word access requests, reads EEPROM and stores the result
3093 * into DATA field.
3094 *
3095 * @param pThis The device state structure.
3096 * @param offset Register offset in memory-mapped frame.
3097 * @param index Register index in register array.
3098 * @param value The value to store.
3099 * @param mask Used to implement partial writes (8 and 16-bit).
3100 * @thread EMT
3101 */
3102static int e1kRegWriteEERD(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3103{
3104#ifdef IN_RING3
3105 /* Make use of 'writable' and 'readable' masks. */
3106 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3107 /* DONE and DATA are set only if read was triggered by START. */
3108 if (value & EERD_START)
3109 {
3110 STAM_PROFILE_ADV_START(&pThis->StatEEPROMRead, a);
3111 uint16_t tmp;
3112 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3113 if (pThisCC->eeprom.readWord(GET_BITS_V(value, EERD, ADDR), &tmp))
3114 SET_BITS(EERD, DATA, tmp);
3115 EERD |= EERD_DONE;
3116 STAM_PROFILE_ADV_STOP(&pThis->StatEEPROMRead, a);
3117 }
3118
3119 return VINF_SUCCESS;
3120#else /* !IN_RING3 */
3121 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
3122 return VINF_IOM_R3_MMIO_WRITE;
3123#endif /* !IN_RING3 */
3124}
3125
3126
3127/**
3128 * Write handler for MDI Control register.
3129 *
3130 * Handles PHY read/write requests; forwards requests to internal PHY device.
3131 *
3132 * @param pThis The device state structure.
3133 * @param offset Register offset in memory-mapped frame.
3134 * @param index Register index in register array.
3135 * @param value The value to store.
3136 * @param mask Used to implement partial writes (8 and 16-bit).
3137 * @thread EMT
3138 */
3139static int e1kRegWriteMDIC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3140{
3141 if (value & MDIC_INT_EN)
3142 {
3143 E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
3144 pThis->szPrf));
3145 }
3146 else if (value & MDIC_READY)
3147 {
3148 E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
3149 pThis->szPrf));
3150 }
3151 else if (GET_BITS_V(value, MDIC, PHY) != 1)
3152 {
3153 E1kLog(("%s WARNING! Access to invalid PHY detected, phy=%d.\n",
3154 pThis->szPrf, GET_BITS_V(value, MDIC, PHY)));
3155 /*
3156 * Some drivers scan the MDIO bus for a PHY. We can work with these
3157 * drivers if we set MDIC_READY and MDIC_ERROR when there isn't a PHY
3158 * at the requested address, see @bugref{7346}.
3159 */
3160 MDIC = MDIC_READY | MDIC_ERROR;
3161 }
3162 else
3163 {
3164 /* Store the value */
3165 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3166 STAM_COUNTER_INC(&pThis->StatPHYAccesses);
3167 /* Forward op to PHY */
3168 if (value & MDIC_OP_READ)
3169 SET_BITS(MDIC, DATA, Phy::readRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), pDevIns));
3170 else
3171 Phy::writeRegister(&pThis->phy, GET_BITS_V(value, MDIC, REG), value & MDIC_DATA_MASK, pDevIns);
3172 /* Let software know that we are done */
3173 MDIC |= MDIC_READY;
3174 }
3175
3176 return VINF_SUCCESS;
3177}
3178
3179/**
3180 * Write handler for Interrupt Cause Read register.
3181 *
3182 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
3183 *
3184 * @param pThis The device state structure.
3185 * @param offset Register offset in memory-mapped frame.
3186 * @param index Register index in register array.
3187 * @param value The value to store.
3188 * @param mask Used to implement partial writes (8 and 16-bit).
3189 * @thread EMT
3190 */
3191static int e1kRegWriteICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3192{
3193 ICR &= ~value;
3194
3195 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
3196 return VINF_SUCCESS;
3197}
3198
3199/**
3200 * Read handler for Interrupt Cause Read register.
3201 *
3202 * Reading this register acknowledges all interrupts.
3203 *
3204 * @returns VBox status code.
3205 *
3206 * @param pThis The device state structure.
3207 * @param offset Register offset in memory-mapped frame.
3208 * @param index Register index in register array.
3209 * @param mask Not used.
3210 * @thread EMT
3211 */
3212static int e1kRegReadICR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3213{
3214 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
3215 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3216 return rc;
3217
3218 uint32_t value = 0;
3219 rc = e1kRegReadDefault(pDevIns, pThis, offset, index, &value);
3220 if (RT_SUCCESS(rc))
3221 {
3222 if (value)
3223 {
3224 if (!pThis->fIntRaised)
3225 E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
3226 /*
3227 * Not clearing ICR causes QNX to hang as it reads ICR in a loop
3228 * with disabled interrupts.
3229 */
3230 //if (IMS)
3231 if (1)
3232 {
3233 /*
3234 * Interrupts were enabled -- we are supposedly at the very
3235 * beginning of interrupt handler
3236 */
3237 E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
3238 E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
3239 /* Clear all pending interrupts */
3240 ICR = 0;
3241 pThis->fIntRaised = false;
3242 /* Lower(0) INTA(0) */
3243 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3244
3245 pThis->u64AckedAt = PDMDevHlpTimerGet(pDevIns, pThis->hIntTimer);
3246 if (pThis->fIntMaskUsed)
3247 pThis->fDelayInts = true;
3248 }
3249 else
3250 {
3251 /*
3252 * Interrupts are disabled -- in windows guests ICR read is done
3253 * just before re-enabling interrupts
3254 */
3255 E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
3256 }
3257 }
3258 *pu32Value = value;
3259 }
3260 e1kCsLeave(pThis);
3261
3262 return rc;
3263}
3264
3265/**
3266 * Read handler for Interrupt Cause Set register.
3267 *
3268 * VxWorks driver uses this undocumented feature of real H/W to read ICR without acknowledging interrupts.
3269 *
3270 * @returns VBox status code.
3271 *
3272 * @param pThis The device state structure.
3273 * @param offset Register offset in memory-mapped frame.
3274 * @param index Register index in register array.
3275 * @param pu32Value Where to store the value of the register.
3276 * @thread EMT
3277 */
3278static int e1kRegReadICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
3279{
3280 RT_NOREF_PV(index);
3281 return e1kRegReadDefault(pDevIns, pThis, offset, ICR_IDX, pu32Value);
3282}
3283
3284/**
3285 * Write handler for Interrupt Cause Set register.
3286 *
3287 * Bits corresponding to 1s in 'value' will be set in ICR register.
3288 *
3289 * @param pThis The device state structure.
3290 * @param offset Register offset in memory-mapped frame.
3291 * @param index Register index in register array.
3292 * @param value The value to store.
3293 * @param mask Used to implement partial writes (8 and 16-bit).
3294 * @thread EMT
3295 */
3296static int e1kRegWriteICS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3297{
3298 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3299 E1K_INC_ISTAT_CNT(pThis->uStatIntICS);
3300 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable);
3301}
3302
3303/**
3304 * Write handler for Interrupt Mask Set register.
3305 *
3306 * Will trigger pending interrupts.
3307 *
3308 * @param pThis The device state structure.
3309 * @param offset Register offset in memory-mapped frame.
3310 * @param index Register index in register array.
3311 * @param value The value to store.
3312 * @param mask Used to implement partial writes (8 and 16-bit).
3313 * @thread EMT
3314 */
3315static int e1kRegWriteIMS(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3316{
3317 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3318
3319 IMS |= value;
3320 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
3321 E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
3322 /*
3323 * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
3324 * in Windows guests (see @bugref{8624}, @bugref{5023}).
3325 */
3326 if ((ICR & IMS) && !pThis->fLocked)
3327 {
3328 E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
3329 e1kPostponeInterrupt(pDevIns, pThis, E1K_IMS_INT_DELAY_NS);
3330 }
3331
3332 return VINF_SUCCESS;
3333}
3334
3335/**
3336 * Write handler for Interrupt Mask Clear register.
3337 *
3338 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
3339 *
3340 * @param pThis The device state structure.
3341 * @param offset Register offset in memory-mapped frame.
3342 * @param index Register index in register array.
3343 * @param value The value to store.
3344 * @param mask Used to implement partial writes (8 and 16-bit).
3345 * @thread EMT
3346 */
3347static int e1kRegWriteIMC(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3348{
3349 RT_NOREF_PV(offset); RT_NOREF_PV(index);
3350
3351 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3352 if (RT_UNLIKELY(rc != VINF_SUCCESS))
3353 return rc;
3354 if (pThis->fIntRaised)
3355 {
3356 /*
3357 * Technically we should reset fIntRaised in ICR read handler, but it will cause
3358 * Windows to freeze since it may receive an interrupt while still in the very beginning
3359 * of interrupt handler.
3360 */
3361 E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
3362 STAM_COUNTER_INC(&pThis->StatIntsPrevented);
3363 E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
3364 /* Lower(0) INTA(0) */
3365 PDMDevHlpPCISetIrq(pDevIns, 0, 0);
3366 pThis->fIntRaised = false;
3367 E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
3368 }
3369 IMS &= ~value;
3370 E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
3371 e1kCsLeave(pThis);
3372
3373 return VINF_SUCCESS;
3374}
3375
3376/**
3377 * Write handler for Receive Control register.
3378 *
3379 * @param pThis The device state structure.
3380 * @param offset Register offset in memory-mapped frame.
3381 * @param index Register index in register array.
3382 * @param value The value to store.
3383 * @param mask Used to implement partial writes (8 and 16-bit).
3384 * @thread EMT
3385 */
3386static int e1kRegWriteRCTL(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3387{
3388 /* Update promiscuous mode */
3389 bool fBecomePromiscous = !!(value & (RCTL_UPE | RCTL_MPE));
3390 if (fBecomePromiscous != !!( RCTL & (RCTL_UPE | RCTL_MPE)))
3391 {
3392 /* Promiscuity has changed, pass the knowledge on. */
3393#ifndef IN_RING3
3394 return VINF_IOM_R3_MMIO_WRITE;
3395#else
3396 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3397 if (pThisCC->pDrvR3)
3398 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, fBecomePromiscous);
3399#endif
3400 }
3401
3402 /* Adjust receive buffer size */
3403 unsigned cbRxBuf = 2048 >> GET_BITS_V(value, RCTL, BSIZE);
3404 if (value & RCTL_BSEX)
3405 cbRxBuf *= 16;
3406 if (cbRxBuf > E1K_MAX_RX_PKT_SIZE)
3407 cbRxBuf = E1K_MAX_RX_PKT_SIZE;
3408 if (cbRxBuf != pThis->u16RxBSize)
3409 E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d (old %d)\n",
3410 pThis->szPrf, cbRxBuf, pThis->u16RxBSize));
3411 Assert(cbRxBuf < 65536);
3412 pThis->u16RxBSize = (uint16_t)cbRxBuf;
3413
3414 /* Update the register */
3415 return e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3416}
3417
3418/**
3419 * Write handler for Packet Buffer Allocation register.
3420 *
3421 * TXA = 64 - RXA.
3422 *
3423 * @param pThis The device state structure.
3424 * @param offset Register offset in memory-mapped frame.
3425 * @param index Register index in register array.
3426 * @param value The value to store.
3427 * @param mask Used to implement partial writes (8 and 16-bit).
3428 * @thread EMT
3429 */
3430static int e1kRegWritePBA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3431{
3432 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3433 PBA_st->txa = 64 - PBA_st->rxa;
3434
3435 return VINF_SUCCESS;
3436}
3437
3438/**
3439 * Write handler for Receive Descriptor Tail register.
3440 *
3441 * @remarks Write into RDT forces switch to HC and signal to
3442 * e1kR3NetworkDown_WaitReceiveAvail().
3443 *
3444 * @returns VBox status code.
3445 *
3446 * @param pThis The device state structure.
3447 * @param offset Register offset in memory-mapped frame.
3448 * @param index Register index in register array.
3449 * @param value The value to store.
3450 * @param mask Used to implement partial writes (8 and 16-bit).
3451 * @thread EMT
3452 */
3453static int e1kRegWriteRDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3454{
3455#ifndef IN_RING3
3456 /* XXX */
3457// return VINF_IOM_R3_MMIO_WRITE;
3458#endif
3459 int rc = e1kCsRxEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
3460 if (RT_LIKELY(rc == VINF_SUCCESS))
3461 {
3462 E1kLog(("%s e1kRegWriteRDT\n", pThis->szPrf));
3463#ifndef E1K_WITH_RXD_CACHE
3464 /*
3465 * Some drivers advance RDT too far, so that it equals RDH. This
3466 * somehow manages to work with real hardware but not with this
3467 * emulated device. We can work with these drivers if we just
3468 * write 1 less when we see a driver writing RDT equal to RDH,
3469 * see @bugref{7346}.
3470 */
3471 if (value == RDH)
3472 {
3473 if (RDH == 0)
3474 value = (RDLEN / sizeof(E1KRXDESC)) - 1;
3475 else
3476 value = RDH - 1;
3477 }
3478#endif /* !E1K_WITH_RXD_CACHE */
3479 rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3480#ifdef E1K_WITH_RXD_CACHE
3481 E1KRXDC rxdc;
3482 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kRegWriteRDT")))
3483 {
3484 e1kCsRxLeave(pThis);
3485 E1kLog(("%s e1kRegWriteRDT: failed to update Rx context, returning VINF_SUCCESS\n", pThis->szPrf));
3486 return VINF_SUCCESS;
3487 }
3488 /*
3489 * We need to fetch descriptors now as RDT may go whole circle
3490 * before we attempt to store a received packet. For example,
3491 * Intel's DOS drivers use 2 (!) RX descriptors with the total ring
3492 * size being only 8 descriptors! Note that we fetch descriptors
3493 * only when the cache is empty to reduce the number of memory reads
3494 * in case of frequent RDT writes. Don't fetch anything when the
3495 * receiver is disabled either as RDH, RDT, RDLEN can be in some
3496 * messed up state.
3497 * Note that despite the cache may seem empty, meaning that there are
3498 * no more available descriptors in it, it may still be used by RX
3499 * thread which has not yet written the last descriptor back but has
3500 * temporarily released the RX lock in order to write the packet body
3501 * to descriptor's buffer. At this point we still going to do prefetch
3502 * but it won't actually fetch anything if there are no unused slots in
3503 * our "empty" cache (nRxDFetched==E1K_RXD_CACHE_SIZE). We must not
3504 * reset the cache here even if it appears empty. It will be reset at
3505 * a later point in e1kRxDGet().
3506 */
3507 if (e1kRxDIsCacheEmpty(pThis) && (RCTL & RCTL_EN))
3508 e1kRxDPrefetch(pDevIns, pThis, &rxdc);
3509#endif /* E1K_WITH_RXD_CACHE */
3510 e1kCsRxLeave(pThis);
3511 if (RT_SUCCESS(rc))
3512 {
3513 /* Signal that we have more receive descriptors available. */
3514 e1kWakeupReceive(pDevIns, pThis);
3515 }
3516 }
3517 return rc;
3518}
3519
3520/**
3521 * Write handler for Receive Delay Timer register.
3522 *
3523 * @param pThis The device state structure.
3524 * @param offset Register offset in memory-mapped frame.
3525 * @param index Register index in register array.
3526 * @param value The value to store.
3527 * @param mask Used to implement partial writes (8 and 16-bit).
3528 * @thread EMT
3529 */
3530static int e1kRegWriteRDTR(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
3531{
3532 e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
3533 if (value & RDTR_FPD)
3534 {
3535 /* Flush requested, cancel both timers and raise interrupt */
3536#ifdef E1K_USE_RX_TIMERS
3537 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3538 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3539#endif
3540 E1K_INC_ISTAT_CNT(pThis->uStatIntRDTR);
3541 return e1kRaiseInterrupt(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE, ICR_RXT0);
3542 }
3543
3544 return VINF_SUCCESS;
3545}
3546
3547DECLINLINE(uint32_t) e1kGetTxLen(PE1KTXDC pTxdc)
3548{
3549 /**
3550 * Make sure TDT won't change during computation. EMT may modify TDT at
3551 * any moment.
3552 */
3553 uint32_t tdt = pTxdc->tdt;
3554 return (pTxdc->tdh > tdt ? pTxdc->tdlen/sizeof(E1KTXDESC) : 0) + tdt - pTxdc->tdh;
3555}
3556
3557#ifdef IN_RING3
3558
3559# ifdef E1K_TX_DELAY
3560/**
3561 * @callback_method_impl{FNTMTIMERDEV, Transmit Delay Timer handler.}
3562 */
3563static DECLCALLBACK(void) e1kR3TxDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3564{
3565 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3566 Assert(PDMCritSectIsOwner(&pThis->csTx));
3567 RT_NOREF(hTimer);
3568
3569 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayExp);
3570# ifdef E1K_INT_STATS
3571 uint64_t u64Elapsed = RTTimeNanoTS() - pThis->u64ArmedAt;
3572 if (u64Elapsed > pThis->uStatMaxTxDelay)
3573 pThis->uStatMaxTxDelay = u64Elapsed;
3574# endif
3575 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
3576 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN, ("%Rrc\n", rc));
3577}
3578# endif /* E1K_TX_DELAY */
3579
3580//# ifdef E1K_USE_TX_TIMERS
3581
3582/**
3583 * @callback_method_impl{FNTMTIMERDEV, Transmit Interrupt Delay Timer handler.}
3584 */
3585static DECLCALLBACK(void) e1kR3TxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3586{
3587 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3588 Assert(hTimer == pThis->hTIDTimer); RT_NOREF(hTimer);
3589
3590 E1K_INC_ISTAT_CNT(pThis->uStatTID);
3591 /* Cancel absolute delay timer as we have already got attention */
3592# ifndef E1K_NO_TAD
3593 e1kCancelTimer(pDevIns, pThis, pThis->hTADTimer);
3594# endif
3595 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3596}
3597
3598/**
3599 * @callback_method_impl{FNTMTIMERDEV, Transmit Absolute Delay Timer handler.}
3600 */
3601static DECLCALLBACK(void) e1kR3TxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3602{
3603 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3604 Assert(hTimer == pThis->hTADTimer); RT_NOREF(hTimer);
3605
3606 E1K_INC_ISTAT_CNT(pThis->uStatTAD);
3607 /* Cancel interrupt delay timer as we have already got attention */
3608 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
3609 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_TXDW);
3610}
3611
3612//# endif /* E1K_USE_TX_TIMERS */
3613# ifdef E1K_USE_RX_TIMERS
3614
3615/**
3616 * @callback_method_impl{FNTMTIMERDEV, Receive Interrupt Delay Timer handler.}
3617 */
3618static DECLCALLBACK(void) e1kR3RxIntDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3619{
3620 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3621 Assert(hTimer == pThis->hRIDTimer); RT_NOREF(hTimer);
3622
3623 E1K_INC_ISTAT_CNT(pThis->uStatRID);
3624 /* Cancel absolute delay timer as we have already got attention */
3625 e1kCancelTimer(pDevIns, pThis, pThis->hRADTimer);
3626 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3627}
3628
3629/**
3630 * @callback_method_impl{FNTMTIMERDEV, Receive Absolute Delay Timer handler.}
3631 */
3632static DECLCALLBACK(void) e1kR3RxAbsDelayTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3633{
3634 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3635 Assert(hTimer == pThis->hRADTimer); RT_NOREF(hTimer);
3636
3637 E1K_INC_ISTAT_CNT(pThis->uStatRAD);
3638 /* Cancel interrupt delay timer as we have already got attention */
3639 e1kCancelTimer(pDevIns, pThis, pThis->hRIDTimer);
3640 e1kRaiseInterrupt(pDevIns, pThis, VERR_IGNORED, ICR_RXT0);
3641}
3642
3643# endif /* E1K_USE_RX_TIMERS */
3644
3645/**
3646 * @callback_method_impl{FNTMTIMERDEV, Late Interrupt Timer handler.}
3647 */
3648static DECLCALLBACK(void) e1kR3LateIntTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3649{
3650 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3651 Assert(hTimer == pThis->hIntTimer); RT_NOREF(hTimer);
3652 RT_NOREF(hTimer);
3653
3654 STAM_PROFILE_ADV_START(&pThis->StatLateIntTimer, a);
3655 STAM_COUNTER_INC(&pThis->StatLateInts);
3656 E1K_INC_ISTAT_CNT(pThis->uStatIntLate);
3657# if 0
3658 if (pThis->iStatIntLost > -100)
3659 pThis->iStatIntLost--;
3660# endif
3661 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, 0);
3662 STAM_PROFILE_ADV_STOP(&pThis->StatLateIntTimer, a);
3663}
3664
3665/**
3666 * @callback_method_impl{FNTMTIMERDEV, Link Up Timer handler.}
3667 */
3668static DECLCALLBACK(void) e1kR3LinkUpTimer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
3669{
3670 PE1KSTATE pThis = (PE1KSTATE)pvUser;
3671 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
3672 Assert(hTimer == pThis->hLUTimer); RT_NOREF(hTimer);
3673
3674 /*
3675 * This can happen if we set the link status to down when the Link up timer was
3676 * already armed (shortly after e1kLoadDone() or when the cable was disconnected
3677 * and connect+disconnect the cable very quick. Moreover, 82543GC triggers LSC
3678 * on reset even if the cable is unplugged (see @bugref{8942}).
3679 */
3680 if (e1kIsConnected(pDevIns))
3681 {
3682 /* 82543GC does not have an internal PHY */
3683 if (pThis->eChip == E1K_CHIP_82543GC || (CTRL & CTRL_SLU))
3684 e1kR3LinkUp(pDevIns, pThis, pThisCC);
3685 }
3686# ifdef E1K_LSC_ON_RESET
3687 else if (pThis->eChip == E1K_CHIP_82543GC)
3688 e1kR3LinkDown(pDevIns, pThis, pThisCC);
3689# endif /* E1K_LSC_ON_RESET */
3690}
3691
3692#endif /* IN_RING3 */
3693
3694/**
3695 * Sets up the GSO context according to the TSE new context descriptor.
3696 *
3697 * @param pGso The GSO context to setup.
3698 * @param pCtx The context descriptor.
3699 */
3700DECLINLINE(void) e1kSetupGsoCtx(PPDMNETWORKGSO pGso, E1KTXCTX const *pCtx)
3701{
3702 pGso->u8Type = PDMNETWORKGSOTYPE_INVALID;
3703
3704 /*
3705 * See if the context descriptor describes something that could be TCP or
3706 * UDP over IPv[46].
3707 */
3708 /* Check the header ordering and spacing: 1. Ethernet, 2. IP, 3. TCP/UDP. */
3709 if (RT_UNLIKELY( pCtx->ip.u8CSS < sizeof(RTNETETHERHDR) ))
3710 {
3711 E1kLog(("e1kSetupGsoCtx: IPCSS=%#x\n", pCtx->ip.u8CSS));
3712 return;
3713 }
3714 if (RT_UNLIKELY( pCtx->tu.u8CSS < (size_t)pCtx->ip.u8CSS + (pCtx->dw2.fIP ? RTNETIPV4_MIN_LEN : RTNETIPV6_MIN_LEN) ))
3715 {
3716 E1kLog(("e1kSetupGsoCtx: TUCSS=%#x\n", pCtx->tu.u8CSS));
3717 return;
3718 }
3719 if (RT_UNLIKELY( pCtx->dw2.fTCP
3720 ? pCtx->dw3.u8HDRLEN < (size_t)pCtx->tu.u8CSS + RTNETTCP_MIN_LEN
3721 : pCtx->dw3.u8HDRLEN != (size_t)pCtx->tu.u8CSS + RTNETUDP_MIN_LEN ))
3722 {
3723 E1kLog(("e1kSetupGsoCtx: HDRLEN=%#x TCP=%d\n", pCtx->dw3.u8HDRLEN, pCtx->dw2.fTCP));
3724 return;
3725 }
3726
3727 /* The end of the TCP/UDP checksum should stop at the end of the packet or at least after the headers. */
3728 if (RT_UNLIKELY( pCtx->tu.u16CSE > 0 && pCtx->tu.u16CSE <= pCtx->dw3.u8HDRLEN ))
3729 {
3730 E1kLog(("e1kSetupGsoCtx: TUCSE=%#x HDRLEN=%#x\n", pCtx->tu.u16CSE, pCtx->dw3.u8HDRLEN));
3731 return;
3732 }
3733
3734 /* IPv4 checksum offset. */
3735 if (RT_UNLIKELY( pCtx->dw2.fIP && (size_t)pCtx->ip.u8CSO - pCtx->ip.u8CSS != RT_UOFFSETOF(RTNETIPV4, ip_sum) ))
3736 {
3737 E1kLog(("e1kSetupGsoCtx: IPCSO=%#x IPCSS=%#x\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS));
3738 return;
3739 }
3740
3741 /* TCP/UDP checksum offsets. */
3742 if (RT_UNLIKELY( (size_t)pCtx->tu.u8CSO - pCtx->tu.u8CSS
3743 != ( pCtx->dw2.fTCP
3744 ? RT_UOFFSETOF(RTNETTCP, th_sum)
3745 : RT_UOFFSETOF(RTNETUDP, uh_sum) ) ))
3746 {
3747 E1kLog(("e1kSetupGsoCtx: TUCSO=%#x TUCSS=%#x TCP=%d\n", pCtx->ip.u8CSO, pCtx->ip.u8CSS, pCtx->dw2.fTCP));
3748 return;
3749 }
3750
3751 /*
3752 * Because of internal networking using a 16-bit size field for GSO context
3753 * plus frame, we have to make sure we don't exceed this.
3754 */
3755 if (RT_UNLIKELY( pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN > VBOX_MAX_GSO_SIZE ))
3756 {
3757 E1kLog(("e1kSetupGsoCtx: HDRLEN(=%#x) + PAYLEN(=%#x) = %#x, max is %#x\n",
3758 pCtx->dw3.u8HDRLEN, pCtx->dw2.u20PAYLEN, pCtx->dw3.u8HDRLEN + pCtx->dw2.u20PAYLEN, VBOX_MAX_GSO_SIZE));
3759 return;
3760 }
3761
3762 /*
3763 * We're good for now - we'll do more checks when seeing the data.
3764 * So, figure the type of offloading and setup the context.
3765 */
3766 if (pCtx->dw2.fIP)
3767 {
3768 if (pCtx->dw2.fTCP)
3769 {
3770 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_TCP;
3771 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN;
3772 }
3773 else
3774 {
3775 pGso->u8Type = PDMNETWORKGSOTYPE_IPV4_UDP;
3776 pGso->cbHdrsSeg = pCtx->tu.u8CSS; /* IP header only */
3777 }
3778 /** @todo Detect IPv4-IPv6 tunneling (need test setup since linux doesn't do
3779 * this yet it seems)... */
3780 }
3781 else
3782 {
3783 pGso->cbHdrsSeg = pCtx->dw3.u8HDRLEN; /** @todo IPv6 UFO */
3784 if (pCtx->dw2.fTCP)
3785 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_TCP;
3786 else
3787 pGso->u8Type = PDMNETWORKGSOTYPE_IPV6_UDP;
3788 }
3789 pGso->offHdr1 = pCtx->ip.u8CSS;
3790 pGso->offHdr2 = pCtx->tu.u8CSS;
3791 pGso->cbHdrsTotal = pCtx->dw3.u8HDRLEN;
3792 pGso->cbMaxSeg = pCtx->dw3.u16MSS + (pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP ? pGso->offHdr2 : 0);
3793 Assert(PDMNetGsoIsValid(pGso, sizeof(*pGso), pGso->cbMaxSeg * 5));
3794 E1kLog2(("e1kSetupGsoCtx: mss=%#x hdr=%#x hdrseg=%#x hdr1=%#x hdr2=%#x %s\n",
3795 pGso->cbMaxSeg, pGso->cbHdrsTotal, pGso->cbHdrsSeg, pGso->offHdr1, pGso->offHdr2, PDMNetGsoTypeName((PDMNETWORKGSOTYPE)pGso->u8Type) ));
3796}
3797
3798/**
3799 * Checks if we can use GSO processing for the current TSE frame.
3800 *
3801 * @param pThis The device state structure.
3802 * @param pGso The GSO context.
3803 * @param pData The first data descriptor of the frame.
3804 * @param pCtx The TSO context descriptor.
3805 */
3806DECLINLINE(bool) e1kCanDoGso(PE1KSTATE pThis, PCPDMNETWORKGSO pGso, E1KTXDAT const *pData, E1KTXCTX const *pCtx)
3807{
3808 if (!pData->cmd.fTSE)
3809 {
3810 E1kLog2(("e1kCanDoGso: !TSE\n"));
3811 return false;
3812 }
3813 if (pData->cmd.fVLE) /** @todo VLAN tagging. */
3814 {
3815 E1kLog(("e1kCanDoGso: VLE\n"));
3816 return false;
3817 }
3818 if (RT_UNLIKELY(!pThis->fGSOEnabled))
3819 {
3820 E1kLog3(("e1kCanDoGso: GSO disabled via CFGM\n"));
3821 return false;
3822 }
3823
3824 switch ((PDMNETWORKGSOTYPE)pGso->u8Type)
3825 {
3826 case PDMNETWORKGSOTYPE_IPV4_TCP:
3827 case PDMNETWORKGSOTYPE_IPV4_UDP:
3828 if (!pData->dw3.fIXSM)
3829 {
3830 E1kLog(("e1kCanDoGso: !IXSM (IPv4)\n"));
3831 return false;
3832 }
3833 if (!pData->dw3.fTXSM)
3834 {
3835 E1kLog(("e1kCanDoGso: !TXSM (IPv4)\n"));
3836 return false;
3837 }
3838 /** @todo what more check should we perform here? Ethernet frame type? */
3839 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3840 return true;
3841
3842 case PDMNETWORKGSOTYPE_IPV6_TCP:
3843 case PDMNETWORKGSOTYPE_IPV6_UDP:
3844 if (pData->dw3.fIXSM && pCtx->ip.u8CSO)
3845 {
3846 E1kLog(("e1kCanDoGso: IXSM (IPv6)\n"));
3847 return false;
3848 }
3849 if (!pData->dw3.fTXSM)
3850 {
3851 E1kLog(("e1kCanDoGso: TXSM (IPv6)\n"));
3852 return false;
3853 }
3854 /** @todo what more check should we perform here? Ethernet frame type? */
3855 E1kLog2(("e1kCanDoGso: OK, IPv4\n"));
3856 return true;
3857
3858 default:
3859 Assert(pGso->u8Type == PDMNETWORKGSOTYPE_INVALID);
3860 E1kLog2(("e1kCanDoGso: e1kSetupGsoCtx failed\n"));
3861 return false;
3862 }
3863}
3864
3865/**
3866 * Frees the current xmit buffer.
3867 *
3868 * @param pThis The device state structure.
3869 */
3870static void e1kXmitFreeBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC)
3871{
3872 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
3873 if (pSg)
3874 {
3875 pThisCC->CTX_SUFF(pTxSg) = NULL;
3876
3877 if (pSg->pvAllocator != pThis)
3878 {
3879 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3880 if (pDrv)
3881 pDrv->pfnFreeBuf(pDrv, pSg);
3882 }
3883 else
3884 {
3885 /* loopback */
3886 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3887 Assert(pSg->fFlags == (PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3));
3888 pSg->fFlags = 0;
3889 pSg->pvAllocator = NULL;
3890 }
3891 }
3892}
3893
3894#ifndef E1K_WITH_TXD_CACHE
3895/**
3896 * Allocates an xmit buffer.
3897 *
3898 * @returns See PDMINETWORKUP::pfnAllocBuf.
3899 * @param pThis The device state structure.
3900 * @param cbMin The minimum frame size.
3901 * @param fExactSize Whether cbMin is exact or if we have to max it
3902 * out to the max MTU size.
3903 * @param fGso Whether this is a GSO frame or not.
3904 */
3905DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, size_t cbMin, bool fExactSize, bool fGso)
3906{
3907 /* Adjust cbMin if necessary. */
3908 if (!fExactSize)
3909 cbMin = RT_MAX(cbMin, E1K_MAX_TX_PKT_SIZE);
3910
3911 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3912 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3913 e1kXmitFreeBuf(pThis, pThisCC);
3914 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3915
3916 /*
3917 * Allocate the buffer.
3918 */
3919 PPDMSCATTERGATHER pSg;
3920 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3921 {
3922 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3923 if (RT_UNLIKELY(!pDrv))
3924 return VERR_NET_DOWN;
3925 int rc = pDrv->pfnAllocBuf(pDrv, cbMin, fGso ? &pThis->GsoCtx : NULL, &pSg);
3926 if (RT_FAILURE(rc))
3927 {
3928 /* Suspend TX as we are out of buffers atm */
3929 STATUS |= STATUS_TXOFF;
3930 return rc;
3931 }
3932 }
3933 else
3934 {
3935 /* Create a loopback using the fallback buffer and preallocated SG. */
3936 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
3937 pSg = &pThis->uTxFallback.Sg;
3938 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
3939 pSg->cbUsed = 0;
3940 pSg->cbAvailable = 0;
3941 pSg->pvAllocator = pThis;
3942 pSg->pvUser = NULL; /* No GSO here. */
3943 pSg->cSegs = 1;
3944 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
3945 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
3946 }
3947
3948 pThisCC->CTX_SUFF(pTxSg) = pSg;
3949 return VINF_SUCCESS;
3950}
3951#else /* E1K_WITH_TXD_CACHE */
3952/**
3953 * Allocates an xmit buffer.
3954 *
3955 * @returns See PDMINETWORKUP::pfnAllocBuf.
3956 * @param pThis The device state structure.
3957 * @param cbMin The minimum frame size.
3958 * @param fExactSize Whether cbMin is exact or if we have to max it
3959 * out to the max MTU size.
3960 * @param fGso Whether this is a GSO frame or not.
3961 */
3962DECLINLINE(int) e1kXmitAllocBuf(PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fGso)
3963{
3964 /* Deal with existing buffer (descriptor screw up, reset, etc). */
3965 if (RT_UNLIKELY(pThisCC->CTX_SUFF(pTxSg)))
3966 e1kXmitFreeBuf(pThis, pThisCC);
3967 Assert(pThisCC->CTX_SUFF(pTxSg) == NULL);
3968
3969 /*
3970 * Allocate the buffer.
3971 */
3972 PPDMSCATTERGATHER pSg;
3973 if (RT_LIKELY(GET_BITS(RCTL, LBM) != RCTL_LBM_TCVR))
3974 {
3975 if (pThis->cbTxAlloc == 0)
3976 {
3977 /* Zero packet, no need for the buffer */
3978 return VINF_SUCCESS;
3979 }
3980 if (fGso && pThis->GsoCtx.u8Type == PDMNETWORKGSOTYPE_INVALID)
3981 {
3982 E1kLog3(("Invalid GSO context, won't allocate this packet, cb=%u %s%s\n",
3983 pThis->cbTxAlloc, pThis->fVTag ? "VLAN " : "", pThis->fGSO ? "GSO " : ""));
3984 /* No valid GSO context is available, ignore this packet. */
3985 pThis->cbTxAlloc = 0;
3986 return VINF_SUCCESS;
3987 }
3988
3989 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
3990 if (RT_UNLIKELY(!pDrv))
3991 return VERR_NET_DOWN;
3992 int rc = pDrv->pfnAllocBuf(pDrv, pThis->cbTxAlloc, fGso ? &pThis->GsoCtx : NULL, &pSg);
3993 if (RT_FAILURE(rc))
3994 {
3995 /* Suspend TX as we are out of buffers atm */
3996 STATUS |= STATUS_TXOFF;
3997 return rc;
3998 }
3999 E1kLog3(("%s Allocated buffer for TX packet: cb=%u %s%s\n",
4000 pThis->szPrf, pThis->cbTxAlloc,
4001 pThis->fVTag ? "VLAN " : "",
4002 pThis->fGSO ? "GSO " : ""));
4003 }
4004 else
4005 {
4006 /* Create a loopback using the fallback buffer and preallocated SG. */
4007 AssertCompileMemberSize(E1KSTATE, uTxFallback.Sg, 8 * sizeof(size_t));
4008 pSg = &pThis->uTxFallback.Sg;
4009 pSg->fFlags = PDMSCATTERGATHER_FLAGS_MAGIC | PDMSCATTERGATHER_FLAGS_OWNER_3;
4010 pSg->cbUsed = 0;
4011 pSg->cbAvailable = sizeof(pThis->aTxPacketFallback);
4012 pSg->pvAllocator = pThis;
4013 pSg->pvUser = NULL; /* No GSO here. */
4014 pSg->cSegs = 1;
4015 pSg->aSegs[0].pvSeg = pThis->aTxPacketFallback;
4016 pSg->aSegs[0].cbSeg = sizeof(pThis->aTxPacketFallback);
4017 }
4018 pThis->cbTxAlloc = 0;
4019
4020 pThisCC->CTX_SUFF(pTxSg) = pSg;
4021 return VINF_SUCCESS;
4022}
4023#endif /* E1K_WITH_TXD_CACHE */
4024
4025/**
4026 * Checks if it's a GSO buffer or not.
4027 *
4028 * @returns true / false.
4029 * @param pTxSg The scatter / gather buffer.
4030 */
4031DECLINLINE(bool) e1kXmitIsGsoBuf(PDMSCATTERGATHER const *pTxSg)
4032{
4033#if 0
4034 if (!pTxSg)
4035 E1kLog(("e1kXmitIsGsoBuf: pTxSG is NULL\n"));
4036 if (pTxSg && pTxSg->pvUser)
4037 E1kLog(("e1kXmitIsGsoBuf: pvUser is NULL\n"));
4038#endif
4039 return pTxSg && pTxSg->pvUser /* GSO indicator */;
4040}
4041
4042#ifndef E1K_WITH_TXD_CACHE
4043/**
4044 * Load transmit descriptor from guest memory.
4045 *
4046 * @param pDevIns The device instance.
4047 * @param pDesc Pointer to descriptor union.
4048 * @param addr Physical address in guest context.
4049 * @thread E1000_TX
4050 */
4051DECLINLINE(void) e1kLoadDesc(PPDMDEVINS pDevIns, E1KTXDESC *pDesc, RTGCPHYS addr)
4052{
4053 PDMDevHlpPCIPhysRead(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4054}
4055#else /* E1K_WITH_TXD_CACHE */
4056/**
4057 * Load transmit descriptors from guest memory.
4058 *
4059 * We need two physical reads in case the tail wrapped around the end of TX
4060 * descriptor ring.
4061 *
4062 * @returns the actual number of descriptors fetched.
4063 * @param pDevIns The device instance.
4064 * @param pThis The device state structure.
4065 * @thread E1000_TX
4066 */
4067DECLINLINE(unsigned) e1kTxDLoadMore(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4068{
4069 Assert(pThis->iTxDCurrent == 0);
4070 /* We've already loaded pThis->nTxDFetched descriptors past TDH. */
4071 unsigned nDescsAvailable = e1kGetTxLen(pTxdc) - pThis->nTxDFetched;
4072 /* The following two lines ensure that pThis->nTxDFetched never overflows. */
4073 AssertCompile(E1K_TXD_CACHE_SIZE < (256 * sizeof(pThis->nTxDFetched)));
4074 unsigned nDescsToFetch = RT_MIN(nDescsAvailable, E1K_TXD_CACHE_SIZE - pThis->nTxDFetched);
4075 unsigned nDescsTotal = pTxdc->tdlen / sizeof(E1KTXDESC);
4076 Assert(nDescsTotal != 0);
4077 if (nDescsTotal == 0)
4078 return 0;
4079 unsigned nFirstNotLoaded = (pTxdc->tdh + pThis->nTxDFetched) % nDescsTotal;
4080 unsigned nDescsInSingleRead = RT_MIN(nDescsToFetch, nDescsTotal - nFirstNotLoaded);
4081 E1kLog3(("%s e1kTxDLoadMore: nDescsAvailable=%u nDescsToFetch=%u nDescsTotal=%u nFirstNotLoaded=0x%x nDescsInSingleRead=%u\n",
4082 pThis->szPrf, nDescsAvailable, nDescsToFetch, nDescsTotal,
4083 nFirstNotLoaded, nDescsInSingleRead));
4084 if (nDescsToFetch == 0)
4085 return 0;
4086 E1KTXDESC* pFirstEmptyDesc = &pThis->aTxDescriptors[pThis->nTxDFetched];
4087 PDMDevHlpPCIPhysRead(pDevIns,
4088 ((uint64_t)TDBAH << 32) + TDBAL + nFirstNotLoaded * sizeof(E1KTXDESC),
4089 pFirstEmptyDesc, nDescsInSingleRead * sizeof(E1KTXDESC));
4090 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x(0x%x), TDLEN=%08x, TDH=%08x, TDT=%08x\n",
4091 pThis->szPrf, nDescsInSingleRead,
4092 TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC),
4093 nFirstNotLoaded, pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
4094 if (nDescsToFetch > nDescsInSingleRead)
4095 {
4096 PDMDevHlpPCIPhysRead(pDevIns,
4097 ((uint64_t)TDBAH << 32) + TDBAL,
4098 pFirstEmptyDesc + nDescsInSingleRead,
4099 (nDescsToFetch - nDescsInSingleRead) * sizeof(E1KTXDESC));
4100 E1kLog3(("%s Fetched %u TX descriptors at %08x%08x\n",
4101 pThis->szPrf, nDescsToFetch - nDescsInSingleRead,
4102 TDBAH, TDBAL));
4103 }
4104 pThis->nTxDFetched += (uint8_t)nDescsToFetch;
4105 return nDescsToFetch;
4106}
4107
4108/**
4109 * Load transmit descriptors from guest memory only if there are no loaded
4110 * descriptors.
4111 *
4112 * @returns true if there are descriptors in cache.
4113 * @param pDevIns The device instance.
4114 * @param pThis The device state structure.
4115 * @thread E1000_TX
4116 */
4117DECLINLINE(bool) e1kTxDLazyLoad(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
4118{
4119 if (pThis->nTxDFetched == 0)
4120 return e1kTxDLoadMore(pDevIns, pThis, pTxdc) != 0;
4121 return true;
4122}
4123#endif /* E1K_WITH_TXD_CACHE */
4124
4125/**
4126 * Write back transmit descriptor to guest memory.
4127 *
4128 * @param pDevIns The device instance.
4129 * @param pThis The device state structure.
4130 * @param pDesc Pointer to descriptor union.
4131 * @param addr Physical address in guest context.
4132 * @thread E1000_TX
4133 */
4134DECLINLINE(void) e1kWriteBackDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4135{
4136 /* Only the last half of the descriptor has to be written back. */
4137 e1kPrintTDesc(pThis, pDesc, "^^^");
4138 PDMDevHlpPCIPhysWrite(pDevIns, addr, pDesc, sizeof(E1KTXDESC));
4139}
4140
4141/**
4142 * Transmit complete frame.
4143 *
4144 * @remarks We skip the FCS since we're not responsible for sending anything to
4145 * a real ethernet wire.
4146 *
4147 * @param pDevIns The device instance.
4148 * @param pThis The device state structure.
4149 * @param pThisCC The current context instance data.
4150 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4151 * @thread E1000_TX
4152 */
4153static void e1kTransmitFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, bool fOnWorkerThread)
4154{
4155 PPDMSCATTERGATHER pSg = pThisCC->CTX_SUFF(pTxSg);
4156 uint32_t cbFrame = pSg ? (uint32_t)pSg->cbUsed : 0;
4157 Assert(!pSg || pSg->cSegs == 1);
4158
4159 if (cbFrame > 70) /* unqualified guess */
4160 pThis->led.Asserted.s.fWriting = pThis->led.Actual.s.fWriting = 1;
4161
4162#ifdef E1K_INT_STATS
4163 if (cbFrame <= 1514)
4164 E1K_INC_ISTAT_CNT(pThis->uStatTx1514);
4165 else if (cbFrame <= 2962)
4166 E1K_INC_ISTAT_CNT(pThis->uStatTx2962);
4167 else if (cbFrame <= 4410)
4168 E1K_INC_ISTAT_CNT(pThis->uStatTx4410);
4169 else if (cbFrame <= 5858)
4170 E1K_INC_ISTAT_CNT(pThis->uStatTx5858);
4171 else if (cbFrame <= 7306)
4172 E1K_INC_ISTAT_CNT(pThis->uStatTx7306);
4173 else if (cbFrame <= 8754)
4174 E1K_INC_ISTAT_CNT(pThis->uStatTx8754);
4175 else if (cbFrame <= 16384)
4176 E1K_INC_ISTAT_CNT(pThis->uStatTx16384);
4177 else if (cbFrame <= 32768)
4178 E1K_INC_ISTAT_CNT(pThis->uStatTx32768);
4179 else
4180 E1K_INC_ISTAT_CNT(pThis->uStatTxLarge);
4181#endif /* E1K_INT_STATS */
4182
4183 /* Add VLAN tag */
4184 if (cbFrame > 12 && pThis->fVTag)
4185 {
4186 E1kLog3(("%s Inserting VLAN tag %08x\n",
4187 pThis->szPrf, RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16)));
4188 memmove((uint8_t*)pSg->aSegs[0].pvSeg + 16, (uint8_t*)pSg->aSegs[0].pvSeg + 12, cbFrame - 12);
4189 *((uint32_t*)pSg->aSegs[0].pvSeg + 3) = RT_BE2H_U16((uint16_t)VET) | (RT_BE2H_U16(pThis->u16VTagTCI) << 16);
4190 pSg->cbUsed += 4;
4191 cbFrame += 4;
4192 Assert(pSg->cbUsed == cbFrame);
4193 Assert(pSg->cbUsed <= pSg->cbAvailable);
4194 }
4195/* E1kLog2(("%s < < < Outgoing packet. Dump follows: > > >\n"
4196 "%.*Rhxd\n"
4197 "%s < < < < < < < < < < < < < End of dump > > > > > > > > > > > >\n",
4198 pThis->szPrf, cbFrame, pSg->aSegs[0].pvSeg, pThis->szPrf));*/
4199
4200 /* Update the stats */
4201 E1K_INC_CNT32(TPT);
4202 E1K_ADD_CNT64(TOTL, TOTH, cbFrame);
4203 E1K_INC_CNT32(GPTC);
4204 if (pSg && e1kIsBroadcast(pSg->aSegs[0].pvSeg))
4205 E1K_INC_CNT32(BPTC);
4206 else if (pSg && e1kIsMulticast(pSg->aSegs[0].pvSeg))
4207 E1K_INC_CNT32(MPTC);
4208 /* Update octet transmit counter */
4209 E1K_ADD_CNT64(GOTCL, GOTCH, cbFrame);
4210 if (pThisCC->CTX_SUFF(pDrv))
4211 STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, cbFrame);
4212 if (cbFrame == 64)
4213 E1K_INC_CNT32(PTC64);
4214 else if (cbFrame < 128)
4215 E1K_INC_CNT32(PTC127);
4216 else if (cbFrame < 256)
4217 E1K_INC_CNT32(PTC255);
4218 else if (cbFrame < 512)
4219 E1K_INC_CNT32(PTC511);
4220 else if (cbFrame < 1024)
4221 E1K_INC_CNT32(PTC1023);
4222 else
4223 E1K_INC_CNT32(PTC1522);
4224
4225 E1K_INC_ISTAT_CNT(pThis->uStatTxFrm);
4226
4227 /*
4228 * Dump and send the packet.
4229 */
4230 int rc = VERR_NET_DOWN;
4231 if (pSg && pSg->pvAllocator != pThis)
4232 {
4233 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Outgoing");
4234
4235 pThisCC->CTX_SUFF(pTxSg) = NULL;
4236 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
4237 if (pDrv)
4238 {
4239 /* Release critical section to avoid deadlock in CanReceive */
4240 //e1kCsLeave(pThis);
4241 STAM_PROFILE_START(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4242 rc = pDrv->pfnSendBuf(pDrv, pSg, fOnWorkerThread);
4243 STAM_PROFILE_STOP(&pThis->CTX_SUFF_Z(StatTransmitSend), a);
4244 //e1kCsEnter(pThis, RT_SRC_POS);
4245 }
4246 }
4247 else if (pSg)
4248 {
4249 Assert(pSg->aSegs[0].pvSeg == pThis->aTxPacketFallback);
4250 e1kPacketDump(pDevIns, pThis, (uint8_t const *)pSg->aSegs[0].pvSeg, cbFrame, "--> Loopback");
4251
4252 /** @todo do we actually need to check that we're in loopback mode here? */
4253 if (GET_BITS(RCTL, LBM) == RCTL_LBM_TCVR)
4254 {
4255 E1KRXDST status;
4256 RT_ZERO(status);
4257 status.fPIF = true;
4258 e1kHandleRxPacket(pDevIns, pThis, pSg->aSegs[0].pvSeg, cbFrame, status);
4259 rc = VINF_SUCCESS;
4260 }
4261 e1kXmitFreeBuf(pThis, pThisCC);
4262 }
4263 else
4264 rc = VERR_NET_DOWN;
4265 if (RT_FAILURE(rc))
4266 {
4267 E1kLogRel(("E1000: ERROR! pfnSend returned %Rrc\n", rc));
4268 /** @todo handle VERR_NET_DOWN and VERR_NET_NO_BUFFER_SPACE. Signal error ? */
4269 }
4270
4271 pThis->led.Actual.s.fWriting = 0;
4272}
4273
4274/**
4275 * Compute and write internet checksum (e1kCSum16) at the specified offset.
4276 *
4277 * @param pThis The device state structure.
4278 * @param pPkt Pointer to the packet.
4279 * @param u16PktLen Total length of the packet.
4280 * @param cso Offset in packet to write checksum at.
4281 * @param css Offset in packet to start computing
4282 * checksum from.
4283 * @param cse Offset in packet to stop computing
4284 * checksum at.
4285 * @param fUdp Replace 0 checksum with all 1s.
4286 * @thread E1000_TX
4287 */
4288static void e1kInsertChecksum(PE1KSTATE pThis, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse, bool fUdp = false)
4289{
4290 RT_NOREF1(pThis);
4291
4292 if (css >= u16PktLen)
4293 {
4294 E1kLog2(("%s css(%X) is greater than packet length-1(%X), checksum is not inserted\n",
4295 pThis->szPrf, cso, u16PktLen));
4296 return;
4297 }
4298
4299 if (cso >= u16PktLen - 1)
4300 {
4301 E1kLog2(("%s cso(%X) is greater than packet length-2(%X), checksum is not inserted\n",
4302 pThis->szPrf, cso, u16PktLen));
4303 return;
4304 }
4305
4306 if (cse == 0 || cse >= u16PktLen)
4307 cse = u16PktLen - 1;
4308 else if (cse < css)
4309 {
4310 E1kLog2(("%s css(%X) is greater than cse(%X), checksum is not inserted\n",
4311 pThis->szPrf, css, cse));
4312 return;
4313 }
4314
4315 uint16_t u16ChkSum = e1kCSum16(pPkt + css, cse - css + 1);
4316 if (fUdp && u16ChkSum == 0)
4317 u16ChkSum = ~u16ChkSum; /* 0 means no checksum computed in case of UDP (see @bugref{9883}) */
4318 E1kLog2(("%s Inserting csum: %04X at %02X, old value: %04X\n", pThis->szPrf,
4319 u16ChkSum, cso, *(uint16_t*)(pPkt + cso)));
4320 *(uint16_t*)(pPkt + cso) = u16ChkSum;
4321}
4322
4323/**
4324 * Add a part of descriptor's buffer to transmit frame.
4325 *
4326 * @remarks data.u64BufAddr is used unconditionally for both data
4327 * and legacy descriptors since it is identical to
4328 * legacy.u64BufAddr.
4329 *
4330 * @param pDevIns The device instance.
4331 * @param pThis The device state structure.
4332 * @param pDesc Pointer to the descriptor to transmit.
4333 * @param u16Len Length of buffer to the end of segment.
4334 * @param fSend Force packet sending.
4335 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4336 * @thread E1000_TX
4337 */
4338#ifndef E1K_WITH_TXD_CACHE
4339static void e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4340{
4341 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4342 /* TCP header being transmitted */
4343 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4344 /* IP header being transmitted */
4345 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4346
4347 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4348 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4349 Assert(pThis->u32PayRemain + pThis->u16HdrRemain > 0);
4350
4351 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4352 E1kLog3(("%s Dump of the segment:\n"
4353 "%.*Rhxd\n"
4354 "%s --- End of dump ---\n",
4355 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4356 pThis->u16TxPktLen += u16Len;
4357 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4358 pThis->szPrf, pThis->u16TxPktLen));
4359 if (pThis->u16HdrRemain > 0)
4360 {
4361 /* The header was not complete, check if it is now */
4362 if (u16Len >= pThis->u16HdrRemain)
4363 {
4364 /* The rest is payload */
4365 u16Len -= pThis->u16HdrRemain;
4366 pThis->u16HdrRemain = 0;
4367 /* Save partial checksum and flags */
4368 pThis->u32SavedCsum = pTcpHdr->chksum;
4369 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4370 /* Clear FIN and PSH flags now and set them only in the last segment */
4371 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4372 }
4373 else
4374 {
4375 /* Still not */
4376 pThis->u16HdrRemain -= u16Len;
4377 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4378 pThis->szPrf, pThis->u16HdrRemain));
4379 return;
4380 }
4381 }
4382
4383 pThis->u32PayRemain -= u16Len;
4384
4385 if (fSend)
4386 {
4387 /* Leave ethernet header intact */
4388 /* IP Total Length = payload + headers - ethernet header */
4389 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4390 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4391 pThis->szPrf, ntohs(pIpHdr->total_len)));
4392 /* Update IP Checksum */
4393 pIpHdr->chksum = 0;
4394 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4395 pThis->contextTSE.ip.u8CSO,
4396 pThis->contextTSE.ip.u8CSS,
4397 pThis->contextTSE.ip.u16CSE);
4398
4399 /* Update TCP flags */
4400 /* Restore original FIN and PSH flags for the last segment */
4401 if (pThis->u32PayRemain == 0)
4402 {
4403 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4404 E1K_INC_CNT32(TSCTC);
4405 }
4406 /* Add TCP length to partial pseudo header sum */
4407 uint32_t csum = pThis->u32SavedCsum
4408 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4409 while (csum >> 16)
4410 csum = (csum >> 16) + (csum & 0xFFFF);
4411 pTcpHdr->chksum = csum;
4412 /* Compute final checksum */
4413 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4414 pThis->contextTSE.tu.u8CSO,
4415 pThis->contextTSE.tu.u8CSS,
4416 pThis->contextTSE.tu.u16CSE);
4417
4418 /*
4419 * Transmit it. If we've use the SG already, allocate a new one before
4420 * we copy of the data.
4421 */
4422 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4423 if (!pTxSg)
4424 {
4425 e1kXmitAllocBuf(pThis, pThisCC, pThis->u16TxPktLen + (pThis->fVTag ? 4 : 0), true /*fExactSize*/, false /*fGso*/);
4426 pTxSg = pThisCC->CTX_SUFF(pTxSg);
4427 }
4428 if (pTxSg)
4429 {
4430 Assert(pThis->u16TxPktLen <= pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4431 Assert(pTxSg->cSegs == 1);
4432 if (pThis->CCCTX_SUFF(pTxSg)->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4433 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, pThis->u16TxPktLen);
4434 pTxSg->cbUsed = pThis->u16TxPktLen;
4435 pTxSg->aSegs[0].cbSeg = pThis->u16TxPktLen;
4436 }
4437 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4438
4439 /* Update Sequence Number */
4440 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4441 - pThis->contextTSE.dw3.u8HDRLEN);
4442 /* Increment IP identification */
4443 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4444 }
4445}
4446#else /* E1K_WITH_TXD_CACHE */
4447static int e1kFallbackAddSegment(PPDMDEVINS pDevIns, PE1KSTATE pThis, RTGCPHYS PhysAddr, uint16_t u16Len, bool fSend, bool fOnWorkerThread)
4448{
4449 int rc = VINF_SUCCESS;
4450 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
4451 /* TCP header being transmitted */
4452 struct E1kTcpHeader *pTcpHdr = (struct E1kTcpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.tu.u8CSS);
4453 /* IP header being transmitted */
4454 struct E1kIpHeader *pIpHdr = (struct E1kIpHeader *)(pThis->aTxPacketFallback + pThis->contextTSE.ip.u8CSS);
4455
4456 E1kLog3(("%s e1kFallbackAddSegment: Length=%x, remaining payload=%x, header=%x, send=%RTbool\n",
4457 pThis->szPrf, u16Len, pThis->u32PayRemain, pThis->u16HdrRemain, fSend));
4458 AssertReturn(pThis->u32PayRemain + pThis->u16HdrRemain > 0, VINF_SUCCESS);
4459
4460 if (pThis->u16TxPktLen + u16Len <= sizeof(pThis->aTxPacketFallback))
4461 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, pThis->aTxPacketFallback + pThis->u16TxPktLen, u16Len);
4462 else
4463 E1kLog(("%s e1kFallbackAddSegment: writing beyond aTxPacketFallback, u16TxPktLen=%d(0x%x) + u16Len=%d(0x%x) > %d\n",
4464 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, u16Len, u16Len, sizeof(pThis->aTxPacketFallback)));
4465 E1kLog3(("%s Dump of the segment:\n"
4466 "%.*Rhxd\n"
4467 "%s --- End of dump ---\n",
4468 pThis->szPrf, u16Len, pThis->aTxPacketFallback + pThis->u16TxPktLen, pThis->szPrf));
4469 pThis->u16TxPktLen += u16Len;
4470 E1kLog3(("%s e1kFallbackAddSegment: pThis->u16TxPktLen=%x\n",
4471 pThis->szPrf, pThis->u16TxPktLen));
4472 if (pThis->u16HdrRemain > 0)
4473 {
4474 /* The header was not complete, check if it is now */
4475 if (u16Len >= pThis->u16HdrRemain)
4476 {
4477 /* The rest is payload */
4478 u16Len -= pThis->u16HdrRemain;
4479 pThis->u16HdrRemain = 0;
4480 /* Save partial checksum and flags */
4481 pThis->u32SavedCsum = pTcpHdr->chksum;
4482 pThis->u16SavedFlags = pTcpHdr->hdrlen_flags;
4483 /* Clear FIN and PSH flags now and set them only in the last segment */
4484 pTcpHdr->hdrlen_flags &= ~htons(E1K_TCP_FIN | E1K_TCP_PSH);
4485 }
4486 else
4487 {
4488 /* Still not */
4489 pThis->u16HdrRemain -= u16Len;
4490 E1kLog3(("%s e1kFallbackAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
4491 pThis->szPrf, pThis->u16HdrRemain));
4492 return rc;
4493 }
4494 }
4495
4496 if (u16Len > pThis->u32PayRemain)
4497 pThis->u32PayRemain = 0;
4498 else
4499 pThis->u32PayRemain -= u16Len;
4500
4501 if (fSend)
4502 {
4503 /* Leave ethernet header intact */
4504 /* IP Total Length = payload + headers - ethernet header */
4505 pIpHdr->total_len = htons(pThis->u16TxPktLen - pThis->contextTSE.ip.u8CSS);
4506 E1kLog3(("%s e1kFallbackAddSegment: End of packet, pIpHdr->total_len=%x\n",
4507 pThis->szPrf, ntohs(pIpHdr->total_len)));
4508 /* Update IP Checksum */
4509 pIpHdr->chksum = 0;
4510 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4511 pThis->contextTSE.ip.u8CSO,
4512 pThis->contextTSE.ip.u8CSS,
4513 pThis->contextTSE.ip.u16CSE);
4514
4515 /* Update TCP flags */
4516 /* Restore original FIN and PSH flags for the last segment */
4517 if (pThis->u32PayRemain == 0)
4518 {
4519 pTcpHdr->hdrlen_flags = pThis->u16SavedFlags;
4520 E1K_INC_CNT32(TSCTC);
4521 }
4522 /* Add TCP length to partial pseudo header sum */
4523 uint32_t csum = pThis->u32SavedCsum
4524 + htons(pThis->u16TxPktLen - pThis->contextTSE.tu.u8CSS);
4525 while (csum >> 16)
4526 csum = (csum >> 16) + (csum & 0xFFFF);
4527 Assert(csum < 65536);
4528 pTcpHdr->chksum = (uint16_t)csum;
4529 /* Compute final checksum */
4530 e1kInsertChecksum(pThis, pThis->aTxPacketFallback, pThis->u16TxPktLen,
4531 pThis->contextTSE.tu.u8CSO,
4532 pThis->contextTSE.tu.u8CSS,
4533 pThis->contextTSE.tu.u16CSE);
4534
4535 /*
4536 * Transmit it.
4537 */
4538 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4539 if (pTxSg)
4540 {
4541 /* Make sure the packet fits into the allocated buffer */
4542 size_t cbCopy = RT_MIN(pThis->u16TxPktLen, pThisCC->CTX_SUFF(pTxSg)->cbAvailable);
4543#ifdef DEBUG
4544 if (pThis->u16TxPktLen > pTxSg->cbAvailable)
4545 E1kLog(("%s e1kFallbackAddSegment: truncating packet, u16TxPktLen=%d(0x%x) > cbAvailable=%d(0x%x)\n",
4546 pThis->szPrf, pThis->u16TxPktLen, pThis->u16TxPktLen, pTxSg->cbAvailable, pTxSg->cbAvailable));
4547#endif /* DEBUG */
4548 Assert(pTxSg->cSegs == 1);
4549 if (pTxSg->aSegs[0].pvSeg != pThis->aTxPacketFallback)
4550 memcpy(pTxSg->aSegs[0].pvSeg, pThis->aTxPacketFallback, cbCopy);
4551 pTxSg->cbUsed = cbCopy;
4552 pTxSg->aSegs[0].cbSeg = cbCopy;
4553 }
4554 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
4555
4556 /* Update Sequence Number */
4557 pTcpHdr->seqno = htonl(ntohl(pTcpHdr->seqno) + pThis->u16TxPktLen
4558 - pThis->contextTSE.dw3.u8HDRLEN);
4559 /* Increment IP identification */
4560 pIpHdr->ident = htons(ntohs(pIpHdr->ident) + 1);
4561
4562 /* Allocate new buffer for the next segment. */
4563 if (pThis->u32PayRemain)
4564 {
4565 pThis->cbTxAlloc = RT_MIN(pThis->u32PayRemain,
4566 pThis->contextTSE.dw3.u16MSS)
4567 + pThis->contextTSE.dw3.u8HDRLEN;
4568 /* Do not add VLAN tags to empty packets. */
4569 if (pThis->fVTag && pThis->cbTxAlloc > 0)
4570 pThis->cbTxAlloc += 4;
4571 rc = e1kXmitAllocBuf(pThis, pThisCC, false /* fGSO */);
4572 }
4573 }
4574
4575 return rc;
4576}
4577#endif /* E1K_WITH_TXD_CACHE */
4578
4579#ifndef E1K_WITH_TXD_CACHE
4580/**
4581 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4582 * frame.
4583 *
4584 * We construct the frame in the fallback buffer first and the copy it to the SG
4585 * buffer before passing it down to the network driver code.
4586 *
4587 * @returns true if the frame should be transmitted, false if not.
4588 *
4589 * @param pThis The device state structure.
4590 * @param pDesc Pointer to the descriptor to transmit.
4591 * @param cbFragment Length of descriptor's buffer.
4592 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4593 * @thread E1000_TX
4594 */
4595static bool e1kFallbackAddToFrame(PE1KSTATE pThis, E1KTXDESC *pDesc, uint32_t cbFragment, bool fOnWorkerThread)
4596{
4597 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4598 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4599 Assert(pDesc->data.cmd.fTSE);
4600 Assert(!e1kXmitIsGsoBuf(pTxSg));
4601
4602 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4603 Assert(u16MaxPktLen != 0);
4604 Assert(u16MaxPktLen < E1K_MAX_TX_PKT_SIZE);
4605
4606 /*
4607 * Carve out segments.
4608 */
4609 do
4610 {
4611 /* Calculate how many bytes we have left in this TCP segment */
4612 uint32_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4613 if (cb > cbFragment)
4614 {
4615 /* This descriptor fits completely into current segment */
4616 cb = cbFragment;
4617 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4618 }
4619 else
4620 {
4621 e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4622 /*
4623 * Rewind the packet tail pointer to the beginning of payload,
4624 * so we continue writing right beyond the header.
4625 */
4626 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4627 }
4628
4629 pDesc->data.u64BufAddr += cb;
4630 cbFragment -= cb;
4631 } while (cbFragment > 0);
4632
4633 if (pDesc->data.cmd.fEOP)
4634 {
4635 /* End of packet, next segment will contain header. */
4636 if (pThis->u32PayRemain != 0)
4637 E1K_INC_CNT32(TSCTFC);
4638 pThis->u16TxPktLen = 0;
4639 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4640 }
4641
4642 return false;
4643}
4644#else /* E1K_WITH_TXD_CACHE */
4645/**
4646 * TCP segmentation offloading fallback: Add descriptor's buffer to transmit
4647 * frame.
4648 *
4649 * We construct the frame in the fallback buffer first and the copy it to the SG
4650 * buffer before passing it down to the network driver code.
4651 *
4652 * @returns error code
4653 *
4654 * @param pDevIns The device instance.
4655 * @param pThis The device state structure.
4656 * @param pDesc Pointer to the descriptor to transmit.
4657 * @param cbFragment Length of descriptor's buffer.
4658 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4659 * @thread E1000_TX
4660 */
4661static int e1kFallbackAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, bool fOnWorkerThread)
4662{
4663#ifdef VBOX_STRICT
4664 PPDMSCATTERGATHER pTxSg = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC)->CTX_SUFF(pTxSg);
4665 Assert(e1kGetDescType(pDesc) == E1K_DTYP_DATA);
4666 Assert(pDesc->data.cmd.fTSE);
4667 Assert(!e1kXmitIsGsoBuf(pTxSg));
4668#endif
4669
4670 uint16_t u16MaxPktLen = pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw3.u16MSS;
4671 /* We cannot produce empty packets, ignore all TX descriptors (see @bugref{9571}) */
4672 if (u16MaxPktLen == 0)
4673 return VINF_SUCCESS;
4674
4675 /*
4676 * Carve out segments.
4677 */
4678 int rc = VINF_SUCCESS;
4679 do
4680 {
4681 /* Calculate how many bytes we have left in this TCP segment */
4682 uint16_t cb = u16MaxPktLen - pThis->u16TxPktLen;
4683 if (cb > pDesc->data.cmd.u20DTALEN)
4684 {
4685 /* This descriptor fits completely into current segment */
4686 cb = (uint16_t)pDesc->data.cmd.u20DTALEN; /* u20DTALEN at this point is guarantied to fit into 16 bits. */
4687 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, pDesc->data.cmd.fEOP /*fSend*/, fOnWorkerThread);
4688 }
4689 else
4690 {
4691 rc = e1kFallbackAddSegment(pDevIns, pThis, pDesc->data.u64BufAddr, cb, true /*fSend*/, fOnWorkerThread);
4692 /*
4693 * Rewind the packet tail pointer to the beginning of payload,
4694 * so we continue writing right beyond the header.
4695 */
4696 pThis->u16TxPktLen = pThis->contextTSE.dw3.u8HDRLEN;
4697 }
4698
4699 pDesc->data.u64BufAddr += cb;
4700 pDesc->data.cmd.u20DTALEN -= cb;
4701 } while (pDesc->data.cmd.u20DTALEN > 0 && RT_SUCCESS(rc));
4702
4703 if (pDesc->data.cmd.fEOP)
4704 {
4705 /* End of packet, next segment will contain header. */
4706 if (pThis->u32PayRemain != 0)
4707 E1K_INC_CNT32(TSCTFC);
4708 pThis->u16TxPktLen = 0;
4709 e1kXmitFreeBuf(pThis, PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC));
4710 }
4711
4712 return VINF_SUCCESS; /// @todo consider rc;
4713}
4714#endif /* E1K_WITH_TXD_CACHE */
4715
4716
4717/**
4718 * Add descriptor's buffer to transmit frame.
4719 *
4720 * This deals with GSO and normal frames, e1kFallbackAddToFrame deals with the
4721 * TSE frames we cannot handle as GSO.
4722 *
4723 * @returns true on success, false on failure.
4724 *
4725 * @param pDevIns The device instance.
4726 * @param pThisCC The current context instance data.
4727 * @param pThis The device state structure.
4728 * @param PhysAddr The physical address of the descriptor buffer.
4729 * @param cbFragment Length of descriptor's buffer.
4730 * @thread E1000_TX
4731 */
4732static bool e1kAddToFrame(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, RTGCPHYS PhysAddr, uint32_t cbFragment)
4733{
4734 PPDMSCATTERGATHER pTxSg = pThisCC->CTX_SUFF(pTxSg);
4735 bool const fGso = e1kXmitIsGsoBuf(pTxSg);
4736 uint32_t const cbNewPkt = cbFragment + pThis->u16TxPktLen;
4737
4738 LogFlow(("%s e1kAddToFrame: ENTER cbFragment=%d u16TxPktLen=%d cbUsed=%d cbAvailable=%d fGSO=%s\n",
4739 pThis->szPrf, cbFragment, pThis->u16TxPktLen, pTxSg->cbUsed, pTxSg->cbAvailable,
4740 fGso ? "true" : "false"));
4741 PCPDMNETWORKGSO pGso = (PCPDMNETWORKGSO)pTxSg->pvUser;
4742 if (pGso)
4743 {
4744 if (RT_UNLIKELY(pGso->cbMaxSeg == 0))
4745 {
4746 E1kLog(("%s zero-sized fragments are not allowed\n", pThis->szPrf));
4747 return false;
4748 }
4749 if (RT_UNLIKELY(pGso->u8Type == PDMNETWORKGSOTYPE_IPV4_UDP))
4750 {
4751 E1kLog(("%s UDP fragmentation is no longer supported\n", pThis->szPrf));
4752 return false;
4753 }
4754 }
4755 if (RT_UNLIKELY( !fGso && cbNewPkt > E1K_MAX_TX_PKT_SIZE ))
4756 {
4757 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, E1K_MAX_TX_PKT_SIZE));
4758 return false;
4759 }
4760 if (RT_UNLIKELY( cbNewPkt > pTxSg->cbAvailable ))
4761 {
4762 E1kLog(("%s Transmit packet is too large: %u > %u(max)\n", pThis->szPrf, cbNewPkt, pTxSg->cbAvailable));
4763 return false;
4764 }
4765
4766 if (RT_LIKELY(pTxSg))
4767 {
4768 Assert(pTxSg->cSegs == 1);
4769 if (pTxSg->cbUsed != pThis->u16TxPktLen)
4770 E1kLog(("%s e1kAddToFrame: pTxSg->cbUsed=%d(0x%x) != u16TxPktLen=%d(0x%x)\n",
4771 pThis->szPrf, pTxSg->cbUsed, pTxSg->cbUsed, pThis->u16TxPktLen, pThis->u16TxPktLen));
4772
4773 PDMDevHlpPCIPhysRead(pDevIns, PhysAddr, (uint8_t *)pTxSg->aSegs[0].pvSeg + pThis->u16TxPktLen, cbFragment);
4774
4775 pTxSg->cbUsed = cbNewPkt;
4776 }
4777 pThis->u16TxPktLen = cbNewPkt;
4778
4779 return true;
4780}
4781
4782
4783/**
4784 * Write the descriptor back to guest memory and notify the guest.
4785 *
4786 * @param pThis The device state structure.
4787 * @param pDesc Pointer to the descriptor have been transmitted.
4788 * @param addr Physical address of the descriptor in guest memory.
4789 * @thread E1000_TX
4790 */
4791static void e1kDescReport(PPDMDEVINS pDevIns, PE1KSTATE pThis, E1KTXDESC *pDesc, RTGCPHYS addr)
4792{
4793 /*
4794 * We fake descriptor write-back bursting. Descriptors are written back as they are
4795 * processed.
4796 */
4797 /* Let's pretend we process descriptors. Write back with DD set. */
4798 /*
4799 * Prior to r71586 we tried to accomodate the case when write-back bursts
4800 * are enabled without actually implementing bursting by writing back all
4801 * descriptors, even the ones that do not have RS set. This caused kernel
4802 * panics with Linux SMP kernels, as the e1000 driver tried to free up skb
4803 * associated with written back descriptor if it happened to be a context
4804 * descriptor since context descriptors do not have skb associated to them.
4805 * Starting from r71586 we write back only the descriptors with RS set,
4806 * which is a little bit different from what the real hardware does in
4807 * case there is a chain of data descritors where some of them have RS set
4808 * and others do not. It is very uncommon scenario imho.
4809 * We need to check RPS as well since some legacy drivers use it instead of
4810 * RS even with newer cards.
4811 */
4812 if (pDesc->legacy.cmd.fRS || pDesc->legacy.cmd.fRPS)
4813 {
4814 pDesc->legacy.dw3.fDD = 1; /* Descriptor Done */
4815 e1kWriteBackDesc(pDevIns, pThis, pDesc, addr);
4816 if (pDesc->legacy.cmd.fEOP)
4817 {
4818//#ifdef E1K_USE_TX_TIMERS
4819 if (pThis->fTidEnabled && pDesc->legacy.cmd.fIDE)
4820 {
4821 E1K_INC_ISTAT_CNT(pThis->uStatTxIDE);
4822 //if (pThis->fIntRaised)
4823 //{
4824 // /* Interrupt is already pending, no need for timers */
4825 // ICR |= ICR_TXDW;
4826 //}
4827 //else {
4828 /* Arm the timer to fire in TIVD usec (discard .024) */
4829 e1kArmTimer(pDevIns, pThis, pThis->hTIDTimer, TIDV);
4830# ifndef E1K_NO_TAD
4831 /* If absolute timer delay is enabled and the timer is not running yet, arm it. */
4832 E1kLog2(("%s Checking if TAD timer is running\n",
4833 pThis->szPrf));
4834 if (TADV != 0 && !PDMDevHlpTimerIsActive(pDevIns, pThis->hTADTimer))
4835 e1kArmTimer(pDevIns, pThis, pThis->hTADTimer, TADV);
4836# endif /* E1K_NO_TAD */
4837 }
4838 else
4839 {
4840 if (pThis->fTidEnabled)
4841 {
4842 E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
4843 pThis->szPrf));
4844 /* Cancel both timers if armed and fire immediately. */
4845# ifndef E1K_NO_TAD
4846 PDMDevHlpTimerStop(pDevIns, pThis->hTADTimer);
4847# endif
4848 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
4849 }
4850//#endif /* E1K_USE_TX_TIMERS */
4851 E1K_INC_ISTAT_CNT(pThis->uStatIntTx);
4852 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXDW);
4853//#ifdef E1K_USE_TX_TIMERS
4854 }
4855//#endif /* E1K_USE_TX_TIMERS */
4856 }
4857 }
4858 else
4859 {
4860 E1K_INC_ISTAT_CNT(pThis->uStatTxNoRS);
4861 }
4862}
4863
4864#ifndef E1K_WITH_TXD_CACHE
4865
4866/**
4867 * Process Transmit Descriptor.
4868 *
4869 * E1000 supports three types of transmit descriptors:
4870 * - legacy data descriptors of older format (context-less).
4871 * - data the same as legacy but providing new offloading capabilities.
4872 * - context sets up the context for following data descriptors.
4873 *
4874 * @param pDevIns The device instance.
4875 * @param pThis The device state structure.
4876 * @param pThisCC The current context instance data.
4877 * @param pDesc Pointer to descriptor union.
4878 * @param addr Physical address of descriptor in guest memory.
4879 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
4880 * @thread E1000_TX
4881 */
4882static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
4883 RTGCPHYS addr, bool fOnWorkerThread)
4884{
4885 int rc = VINF_SUCCESS;
4886 uint32_t cbVTag = 0;
4887
4888 e1kPrintTDesc(pThis, pDesc, "vvv");
4889
4890//#ifdef E1K_USE_TX_TIMERS
4891 if (pThis->fTidEnabled)
4892 e1kCancelTimer(pDevIns, pThis, pThis->hTIDTimer);
4893//#endif /* E1K_USE_TX_TIMERS */
4894
4895 switch (e1kGetDescType(pDesc))
4896 {
4897 case E1K_DTYP_CONTEXT:
4898 if (pDesc->context.dw2.fTSE)
4899 {
4900 pThis->contextTSE = pDesc->context;
4901 pThis->u32PayRemain = pDesc->context.dw2.u20PAYLEN;
4902 pThis->u16HdrRemain = pDesc->context.dw3.u8HDRLEN;
4903 e1kSetupGsoCtx(&pThis->GsoCtx, &pDesc->context);
4904 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
4905 }
4906 else
4907 {
4908 pThis->contextNormal = pDesc->context;
4909 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
4910 }
4911 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
4912 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
4913 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
4914 pDesc->context.ip.u8CSS,
4915 pDesc->context.ip.u8CSO,
4916 pDesc->context.ip.u16CSE,
4917 pDesc->context.tu.u8CSS,
4918 pDesc->context.tu.u8CSO,
4919 pDesc->context.tu.u16CSE));
4920 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
4921 e1kDescReport(pThis, pDesc, addr);
4922 break;
4923
4924 case E1K_DTYP_DATA:
4925 {
4926 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
4927 {
4928 E1kLog2(("% Empty data descriptor, skipped.\n", pThis->szPrf));
4929 /** @todo Same as legacy when !TSE. See below. */
4930 break;
4931 }
4932 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
4933 &pThis->StatTxDescTSEData:
4934 &pThis->StatTxDescData);
4935 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
4936 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
4937
4938 /*
4939 * The last descriptor of non-TSE packet must contain VLE flag.
4940 * TSE packets have VLE flag in the first descriptor. The later
4941 * case is taken care of a bit later when cbVTag gets assigned.
4942 *
4943 * 1) pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE
4944 */
4945 if (pDesc->data.cmd.fEOP && !pDesc->data.cmd.fTSE)
4946 {
4947 pThis->fVTag = pDesc->data.cmd.fVLE;
4948 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4949 }
4950 /*
4951 * First fragment: Allocate new buffer and save the IXSM and TXSM
4952 * packet options as these are only valid in the first fragment.
4953 */
4954 if (pThis->u16TxPktLen == 0)
4955 {
4956 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
4957 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
4958 E1kLog2(("%s Saving checksum flags:%s%s; \n", pThis->szPrf,
4959 pThis->fIPcsum ? " IP" : "",
4960 pThis->fTCPcsum ? " TCP/UDP" : ""));
4961 if (pDesc->data.cmd.fTSE)
4962 {
4963 /* 2) pDesc->data.cmd.fTSE && pThis->u16TxPktLen == 0 */
4964 pThis->fVTag = pDesc->data.cmd.fVLE;
4965 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
4966 cbVTag = pThis->fVTag ? 4 : 0;
4967 }
4968 else if (pDesc->data.cmd.fEOP)
4969 cbVTag = pDesc->data.cmd.fVLE ? 4 : 0;
4970 else
4971 cbVTag = 4;
4972 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
4973 if (e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE))
4974 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->contextTSE.dw2.u20PAYLEN + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4975 true /*fExactSize*/, true /*fGso*/);
4976 else if (pDesc->data.cmd.fTSE)
4977 rc = e1kXmitAllocBuf(pThis, pThisCC, , pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + cbVTag,
4978 pDesc->data.cmd.fTSE /*fExactSize*/, false /*fGso*/);
4979 else
4980 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->data.cmd.u20DTALEN + cbVTag,
4981 pDesc->data.cmd.fEOP /*fExactSize*/, false /*fGso*/);
4982
4983 /**
4984 * @todo: Perhaps it is not that simple for GSO packets! We may
4985 * need to unwind some changes.
4986 */
4987 if (RT_FAILURE(rc))
4988 {
4989 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
4990 break;
4991 }
4992 /** @todo Is there any way to indicating errors other than collisions? Like
4993 * VERR_NET_DOWN. */
4994 }
4995
4996 /*
4997 * Add the descriptor data to the frame. If the frame is complete,
4998 * transmit it and reset the u16TxPktLen field.
4999 */
5000 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5001 {
5002 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5003 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5004 if (pDesc->data.cmd.fEOP)
5005 {
5006 if ( fRc
5007 && pThisCC->CTX_SUFF(pTxSg)
5008 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5009 {
5010 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5011 E1K_INC_CNT32(TSCTC);
5012 }
5013 else
5014 {
5015 if (fRc)
5016 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5017 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5018 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5019 e1kXmitFreeBuf(pThis);
5020 E1K_INC_CNT32(TSCTFC);
5021 }
5022 pThis->u16TxPktLen = 0;
5023 }
5024 }
5025 else if (!pDesc->data.cmd.fTSE)
5026 {
5027 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5028 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5029 if (pDesc->data.cmd.fEOP)
5030 {
5031 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5032 {
5033 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5034 if (pThis->fIPcsum)
5035 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5036 pThis->contextNormal.ip.u8CSO,
5037 pThis->contextNormal.ip.u8CSS,
5038 pThis->contextNormal.ip.u16CSE);
5039 if (pThis->fTCPcsum)
5040 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5041 pThis->contextNormal.tu.u8CSO,
5042 pThis->contextNormal.tu.u8CSS,
5043 pThis->contextNormal.tu.u16CSE,
5044 !pThis->contextNormal.dw2.fTCP);
5045 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5046 }
5047 else
5048 e1kXmitFreeBuf(pThis);
5049 pThis->u16TxPktLen = 0;
5050 }
5051 }
5052 else
5053 {
5054 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5055 e1kFallbackAddToFrame(pDevIns, pThis, pDesc, pDesc->data.cmd.u20DTALEN, fOnWorkerThread);
5056 }
5057
5058 e1kDescReport(pThis, pDesc, addr);
5059 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5060 break;
5061 }
5062
5063 case E1K_DTYP_LEGACY:
5064 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5065 {
5066 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5067 /** @todo 3.3.3, Length/Buffer Address: RS set -> write DD when processing. */
5068 break;
5069 }
5070 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5071 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5072
5073 /* First fragment: allocate new buffer. */
5074 if (pThis->u16TxPktLen == 0)
5075 {
5076 if (pDesc->legacy.cmd.fEOP)
5077 cbVTag = pDesc->legacy.cmd.fVLE ? 4 : 0;
5078 else
5079 cbVTag = 4;
5080 E1kLog3(("%s About to allocate TX buffer: cbVTag=%u\n", pThis->szPrf, cbVTag));
5081 /** @todo reset status bits? */
5082 rc = e1kXmitAllocBuf(pThis, pThisCC, pDesc->legacy.cmd.u16Length + cbVTag, pDesc->legacy.cmd.fEOP, false /*fGso*/);
5083 if (RT_FAILURE(rc))
5084 {
5085 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5086 break;
5087 }
5088
5089 /** @todo Is there any way to indicating errors other than collisions? Like
5090 * VERR_NET_DOWN. */
5091 }
5092
5093 /* Add fragment to frame. */
5094 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5095 {
5096 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5097
5098 /* Last fragment: Transmit and reset the packet storage counter. */
5099 if (pDesc->legacy.cmd.fEOP)
5100 {
5101 pThis->fVTag = pDesc->legacy.cmd.fVLE;
5102 pThis->u16VTagTCI = pDesc->legacy.dw3.u16Special;
5103 /** @todo Offload processing goes here. */
5104 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5105 pThis->u16TxPktLen = 0;
5106 }
5107 }
5108 /* Last fragment + failure: free the buffer and reset the storage counter. */
5109 else if (pDesc->legacy.cmd.fEOP)
5110 {
5111 e1kXmitFreeBuf(pThis);
5112 pThis->u16TxPktLen = 0;
5113 }
5114
5115 e1kDescReport(pThis, pDesc, addr);
5116 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5117 break;
5118
5119 default:
5120 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5121 pThis->szPrf, e1kGetDescType(pDesc)));
5122 break;
5123 }
5124
5125 return rc;
5126}
5127
5128#else /* E1K_WITH_TXD_CACHE */
5129
5130/**
5131 * Process Transmit Descriptor.
5132 *
5133 * E1000 supports three types of transmit descriptors:
5134 * - legacy data descriptors of older format (context-less).
5135 * - data the same as legacy but providing new offloading capabilities.
5136 * - context sets up the context for following data descriptors.
5137 *
5138 * @param pDevIns The device instance.
5139 * @param pThis The device state structure.
5140 * @param pThisCC The current context instance data.
5141 * @param pDesc Pointer to descriptor union.
5142 * @param addr Physical address of descriptor in guest memory.
5143 * @param fOnWorkerThread Whether we're on a worker thread or an EMT.
5144 * @param cbPacketSize Size of the packet as previously computed.
5145 * @thread E1000_TX
5146 */
5147static int e1kXmitDesc(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KSTATECC pThisCC, E1KTXDESC *pDesc,
5148 RTGCPHYS addr, bool fOnWorkerThread)
5149{
5150 int rc = VINF_SUCCESS;
5151
5152 e1kPrintTDesc(pThis, pDesc, "vvv");
5153
5154//#ifdef E1K_USE_TX_TIMERS
5155 if (pThis->fTidEnabled)
5156 PDMDevHlpTimerStop(pDevIns, pThis->hTIDTimer);
5157//#endif /* E1K_USE_TX_TIMERS */
5158
5159 switch (e1kGetDescType(pDesc))
5160 {
5161 case E1K_DTYP_CONTEXT:
5162 /* The caller have already updated the context */
5163 E1K_INC_ISTAT_CNT(pThis->uStatDescCtx);
5164 e1kDescReport(pDevIns, pThis, pDesc, addr);
5165 break;
5166
5167 case E1K_DTYP_DATA:
5168 {
5169 STAM_COUNTER_INC(pDesc->data.cmd.fTSE?
5170 &pThis->StatTxDescTSEData:
5171 &pThis->StatTxDescData);
5172 E1K_INC_ISTAT_CNT(pThis->uStatDescDat);
5173 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5174 if (pDesc->data.cmd.u20DTALEN == 0 || pDesc->data.u64BufAddr == 0)
5175 {
5176 E1kLog2(("%s Empty data descriptor, skipped.\n", pThis->szPrf));
5177 if (pDesc->data.cmd.fEOP)
5178 {
5179 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5180 pThis->u16TxPktLen = 0;
5181 }
5182 }
5183 else
5184 {
5185 /*
5186 * Add the descriptor data to the frame. If the frame is complete,
5187 * transmit it and reset the u16TxPktLen field.
5188 */
5189 if (e1kXmitIsGsoBuf(pThisCC->CTX_SUFF(pTxSg)))
5190 {
5191 STAM_COUNTER_INC(&pThis->StatTxPathGSO);
5192 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5193 if (pDesc->data.cmd.fEOP)
5194 {
5195 if ( fRc
5196 && pThisCC->CTX_SUFF(pTxSg)
5197 && pThisCC->CTX_SUFF(pTxSg)->cbUsed == (size_t)pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN)
5198 {
5199 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5200 E1K_INC_CNT32(TSCTC);
5201 }
5202 else
5203 {
5204 if (fRc)
5205 E1kLog(("%s bad GSO/TSE %p or %u < %u\n" , pThis->szPrf,
5206 pThisCC->CTX_SUFF(pTxSg), pThisCC->CTX_SUFF(pTxSg) ? pThisCC->CTX_SUFF(pTxSg)->cbUsed : 0,
5207 pThis->contextTSE.dw3.u8HDRLEN + pThis->contextTSE.dw2.u20PAYLEN));
5208 e1kXmitFreeBuf(pThis, pThisCC);
5209 E1K_INC_CNT32(TSCTFC);
5210 }
5211 pThis->u16TxPktLen = 0;
5212 }
5213 }
5214 else if (!pDesc->data.cmd.fTSE)
5215 {
5216 STAM_COUNTER_INC(&pThis->StatTxPathRegular);
5217 bool fRc = e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->data.cmd.u20DTALEN);
5218 if (pDesc->data.cmd.fEOP)
5219 {
5220 if (fRc && pThisCC->CTX_SUFF(pTxSg))
5221 {
5222 Assert(pThisCC->CTX_SUFF(pTxSg)->cSegs == 1);
5223 if (pThis->fIPcsum)
5224 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5225 pThis->contextNormal.ip.u8CSO,
5226 pThis->contextNormal.ip.u8CSS,
5227 pThis->contextNormal.ip.u16CSE);
5228 if (pThis->fTCPcsum)
5229 e1kInsertChecksum(pThis, (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg, pThis->u16TxPktLen,
5230 pThis->contextNormal.tu.u8CSO,
5231 pThis->contextNormal.tu.u8CSS,
5232 pThis->contextNormal.tu.u16CSE,
5233 !pThis->contextNormal.dw2.fTCP);
5234 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5235 }
5236 else
5237 e1kXmitFreeBuf(pThis, pThisCC);
5238 pThis->u16TxPktLen = 0;
5239 }
5240 }
5241 else
5242 {
5243 STAM_COUNTER_INC(&pThis->StatTxPathFallback);
5244 rc = e1kFallbackAddToFrame(pDevIns, pThis, pDesc, fOnWorkerThread);
5245 }
5246 }
5247 e1kDescReport(pDevIns, pThis, pDesc, addr);
5248 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5249 break;
5250 }
5251
5252 case E1K_DTYP_LEGACY:
5253 STAM_COUNTER_INC(&pThis->StatTxDescLegacy);
5254 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5255 if (pDesc->legacy.cmd.u16Length == 0 || pDesc->legacy.u64BufAddr == 0)
5256 {
5257 E1kLog(("%s Empty legacy descriptor, skipped.\n", pThis->szPrf));
5258 }
5259 else
5260 {
5261 /* Add fragment to frame. */
5262 if (e1kAddToFrame(pDevIns, pThis, pThisCC, pDesc->data.u64BufAddr, pDesc->legacy.cmd.u16Length))
5263 {
5264 E1K_INC_ISTAT_CNT(pThis->uStatDescLeg);
5265
5266 /* Last fragment: Transmit and reset the packet storage counter. */
5267 if (pDesc->legacy.cmd.fEOP)
5268 {
5269 if (pDesc->legacy.cmd.fIC)
5270 {
5271 e1kInsertChecksum(pThis,
5272 (uint8_t *)pThisCC->CTX_SUFF(pTxSg)->aSegs[0].pvSeg,
5273 pThis->u16TxPktLen,
5274 pDesc->legacy.cmd.u8CSO,
5275 pDesc->legacy.dw3.u8CSS,
5276 0);
5277 }
5278 e1kTransmitFrame(pDevIns, pThis, pThisCC, fOnWorkerThread);
5279 pThis->u16TxPktLen = 0;
5280 }
5281 }
5282 /* Last fragment + failure: free the buffer and reset the storage counter. */
5283 else if (pDesc->legacy.cmd.fEOP)
5284 {
5285 e1kXmitFreeBuf(pThis, pThisCC);
5286 pThis->u16TxPktLen = 0;
5287 }
5288 }
5289 e1kDescReport(pDevIns, pThis, pDesc, addr);
5290 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5291 break;
5292
5293 default:
5294 E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
5295 pThis->szPrf, e1kGetDescType(pDesc)));
5296 break;
5297 }
5298
5299 return rc;
5300}
5301
5302DECLINLINE(bool) e1kUpdateTxContext(PE1KSTATE pThis, E1KTXDESC *pDesc)
5303{
5304 if (pDesc->context.dw2.fTSE)
5305 {
5306 pThis->contextTSE = pDesc->context;
5307 uint32_t cbMaxSegmentSize = pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN + 4; /*VTAG*/
5308 if (RT_UNLIKELY(cbMaxSegmentSize > E1K_MAX_TX_PKT_SIZE))
5309 {
5310 pThis->contextTSE.dw3.u16MSS = E1K_MAX_TX_PKT_SIZE - pThis->contextTSE.dw3.u8HDRLEN - 4; /*VTAG*/
5311 LogRelMax(10, ("%s: Transmit packet is too large: %u > %u(max). Adjusted MSS to %u.\n",
5312 pThis->szPrf, cbMaxSegmentSize, E1K_MAX_TX_PKT_SIZE, pThis->contextTSE.dw3.u16MSS));
5313 }
5314 pThis->u32PayRemain = pThis->contextTSE.dw2.u20PAYLEN;
5315 pThis->u16HdrRemain = pThis->contextTSE.dw3.u8HDRLEN;
5316 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
5317 STAM_COUNTER_INC(&pThis->StatTxDescCtxTSE);
5318 }
5319 else
5320 {
5321 pThis->contextNormal = pDesc->context;
5322 STAM_COUNTER_INC(&pThis->StatTxDescCtxNormal);
5323 }
5324 E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
5325 ", TU CSS=%02X, TU CSO=%02X, TU CSE=%04X\n", pThis->szPrf,
5326 pDesc->context.dw2.fTSE ? "TSE" : "Normal",
5327 pDesc->context.ip.u8CSS,
5328 pDesc->context.ip.u8CSO,
5329 pDesc->context.ip.u16CSE,
5330 pDesc->context.tu.u8CSS,
5331 pDesc->context.tu.u8CSO,
5332 pDesc->context.tu.u16CSE));
5333 return true; /* Consider returning false for invalid descriptors */
5334}
5335
5336static bool e1kLocateTxPacket(PE1KSTATE pThis)
5337{
5338 LogFlow(("%s e1kLocateTxPacket: ENTER cbTxAlloc=%d\n",
5339 pThis->szPrf, pThis->cbTxAlloc));
5340 /* Check if we have located the packet already. */
5341 if (pThis->cbTxAlloc)
5342 {
5343 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d\n",
5344 pThis->szPrf, pThis->cbTxAlloc));
5345 return true;
5346 }
5347
5348 bool fTSE = false;
5349 uint32_t cbPacket = 0;
5350
5351 /* Since we process one packet at a time we will only mark current packet's descriptors as valid */
5352 memset(pThis->afTxDValid, 0, sizeof(pThis->afTxDValid));
5353 for (int i = pThis->iTxDCurrent; i < pThis->nTxDFetched; ++i)
5354 {
5355 E1KTXDESC *pDesc = &pThis->aTxDescriptors[i];
5356 /* Assume the descriptor valid until proven otherwise. */
5357 pThis->afTxDValid[i] = true;
5358 switch (e1kGetDescType(pDesc))
5359 {
5360 case E1K_DTYP_CONTEXT:
5361 if (cbPacket == 0)
5362 pThis->afTxDValid[i] = e1kUpdateTxContext(pThis, pDesc);
5363 else
5364 E1kLog(("%s e1kLocateTxPacket: ignoring a context descriptor in the middle of a packet, cbPacket=%d\n",
5365 pThis->szPrf, cbPacket));
5366 continue;
5367 case E1K_DTYP_LEGACY:
5368 /* Skip invalid descriptors. */
5369 if (cbPacket > 0 && (pThis->fGSO || fTSE))
5370 {
5371 E1kLog(("%s e1kLocateTxPacket: ignoring a legacy descriptor in the segmentation context, cbPacket=%d\n",
5372 pThis->szPrf, cbPacket));
5373 pThis->afTxDValid[i] = false; /* Make sure it is skipped by processing */
5374 continue;
5375 }
5376 /* Skip empty descriptors. */
5377 if (!pDesc->legacy.u64BufAddr || !pDesc->legacy.cmd.u16Length)
5378 break;
5379 cbPacket += pDesc->legacy.cmd.u16Length;
5380 pThis->fGSO = false;
5381 break;
5382 case E1K_DTYP_DATA:
5383 /* Skip invalid descriptors. */
5384 if (cbPacket > 0 && (bool)pDesc->data.cmd.fTSE != fTSE)
5385 {
5386 E1kLog(("%s e1kLocateTxPacket: ignoring %sTSE descriptor in the %ssegmentation context, cbPacket=%d\n",
5387 pThis->szPrf, pDesc->data.cmd.fTSE ? "" : "non-", fTSE ? "" : "non-", cbPacket));
5388 pThis->afTxDValid[i] = false; /* Make sure it is skipped by processing */
5389 continue;
5390 }
5391 /* Skip empty descriptors. */
5392 if (!pDesc->data.u64BufAddr || !pDesc->data.cmd.u20DTALEN)
5393 break;
5394 if (cbPacket == 0)
5395 {
5396 /*
5397 * The first fragment: save IXSM and TXSM options
5398 * as these are only valid in the first fragment.
5399 */
5400 pThis->fIPcsum = pDesc->data.dw3.fIXSM;
5401 pThis->fTCPcsum = pDesc->data.dw3.fTXSM;
5402 fTSE = pDesc->data.cmd.fTSE;
5403 /*
5404 * TSE descriptors have VLE bit properly set in
5405 * the first fragment.
5406 */
5407 if (fTSE)
5408 {
5409 pThis->fVTag = pDesc->data.cmd.fVLE;
5410 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5411 }
5412 pThis->fGSO = e1kCanDoGso(pThis, &pThis->GsoCtx, &pDesc->data, &pThis->contextTSE);
5413 }
5414 cbPacket += pDesc->data.cmd.u20DTALEN;
5415 break;
5416 default:
5417 AssertMsgFailed(("Impossible descriptor type!"));
5418 continue;
5419 }
5420 if (pDesc->legacy.cmd.fEOP)
5421 {
5422 /*
5423 * Non-TSE descriptors have VLE bit properly set in
5424 * the last fragment.
5425 */
5426 if (!fTSE)
5427 {
5428 pThis->fVTag = pDesc->data.cmd.fVLE;
5429 pThis->u16VTagTCI = pDesc->data.dw3.u16Special;
5430 }
5431 /*
5432 * Compute the required buffer size. If we cannot do GSO but still
5433 * have to do segmentation we allocate the first segment only.
5434 */
5435 pThis->cbTxAlloc = (!fTSE || pThis->fGSO) ?
5436 cbPacket :
5437 RT_MIN(cbPacket, pThis->contextTSE.dw3.u16MSS + pThis->contextTSE.dw3.u8HDRLEN);
5438 /* Do not add VLAN tags to empty packets. */
5439 if (pThis->fVTag && pThis->cbTxAlloc > 0)
5440 pThis->cbTxAlloc += 4;
5441 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d cbPacket=%d%s%s\n",
5442 pThis->szPrf, pThis->cbTxAlloc, cbPacket,
5443 pThis->fGSO ? " GSO" : "", fTSE ? " TSE" : ""));
5444 return true;
5445 }
5446 }
5447
5448 if (cbPacket == 0 && pThis->nTxDFetched - pThis->iTxDCurrent > 0)
5449 {
5450 /* All descriptors were empty, we need to process them as a dummy packet */
5451 LogFlow(("%s e1kLocateTxPacket: RET true cbTxAlloc=%d, zero packet!\n",
5452 pThis->szPrf, pThis->cbTxAlloc));
5453 return true;
5454 }
5455 LogFlow(("%s e1kLocateTxPacket: RET false cbTxAlloc=%d cbPacket=%d\n",
5456 pThis->szPrf, pThis->cbTxAlloc, cbPacket));
5457 return false;
5458}
5459
5460static int e1kXmitPacket(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread, PE1KTXDC pTxdc)
5461{
5462 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5463 int rc = VINF_SUCCESS;
5464
5465 LogFlow(("%s e1kXmitPacket: ENTER current=%d fetched=%d\n",
5466 pThis->szPrf, pThis->iTxDCurrent, pThis->nTxDFetched));
5467
5468 while (pThis->iTxDCurrent < pThis->nTxDFetched)
5469 {
5470 E1KTXDESC *pDesc = &pThis->aTxDescriptors[pThis->iTxDCurrent];
5471 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5472 pThis->szPrf, TDBAH, TDBAL + pTxdc->tdh * sizeof(E1KTXDESC), pTxdc->tdlen, pTxdc->tdh, pTxdc->tdt));
5473 if (!pThis->afTxDValid[pThis->iTxDCurrent])
5474 {
5475 e1kPrintTDesc(pThis, pDesc, "vvv");
5476 E1kLog(("%s e1kXmitDesc: skipping bad descriptor ^^^\n", pThis->szPrf));
5477 e1kDescReport(pDevIns, pThis, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh));
5478 rc = VINF_SUCCESS;
5479 }
5480 else
5481 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, pDesc, e1kDescAddr(TDBAH, TDBAL, pTxdc->tdh), fOnWorkerThread);
5482 if (RT_FAILURE(rc))
5483 break;
5484 if (++pTxdc->tdh * sizeof(E1KTXDESC) >= pTxdc->tdlen)
5485 pTxdc->tdh = 0;
5486 TDH = pTxdc->tdh; /* Sync the actual register and TXDC */
5487 uint32_t uLowThreshold = GET_BITS(TXDCTL, LWTHRESH)*8;
5488 if (uLowThreshold != 0 && e1kGetTxLen(pTxdc) <= uLowThreshold)
5489 {
5490 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5491 pThis->szPrf, e1kGetTxLen(pTxdc), GET_BITS(TXDCTL, LWTHRESH)*8));
5492 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5493 }
5494 ++pThis->iTxDCurrent;
5495 if (e1kGetDescType(pDesc) != E1K_DTYP_CONTEXT && pDesc->legacy.cmd.fEOP)
5496 break;
5497 }
5498
5499 LogFlow(("%s e1kXmitPacket: RET %Rrc current=%d fetched=%d\n",
5500 pThis->szPrf, rc, pThis->iTxDCurrent, pThis->nTxDFetched));
5501 return rc;
5502}
5503
5504#endif /* E1K_WITH_TXD_CACHE */
5505#ifndef E1K_WITH_TXD_CACHE
5506
5507/**
5508 * Transmit pending descriptors.
5509 *
5510 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5511 *
5512 * @param pDevIns The device instance.
5513 * @param pThis The E1000 state.
5514 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5515 */
5516static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5517{
5518 int rc = VINF_SUCCESS;
5519 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5520
5521 /* Check if transmitter is enabled. */
5522 if (!(TCTL & TCTL_EN))
5523 return VINF_SUCCESS;
5524 /*
5525 * Grab the xmit lock of the driver as well as the E1K device state.
5526 */
5527 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5528 if (RT_LIKELY(rc == VINF_SUCCESS))
5529 {
5530 PPDMINETWORKUP pDrv = pThis->CTX_SUFF(pDrv);
5531 if (pDrv)
5532 {
5533 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5534 if (RT_FAILURE(rc))
5535 {
5536 e1kCsTxLeave(pThis);
5537 return rc;
5538 }
5539 }
5540 /*
5541 * Process all pending descriptors.
5542 * Note! Do not process descriptors in locked state
5543 */
5544 while (TDH != TDT && !pThis->fLocked)
5545 {
5546 E1KTXDESC desc;
5547 E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5548 pThis->szPrf, TDBAH, TDBAL + TDH * sizeof(desc), TDLEN, TDH, TDT));
5549
5550 e1kLoadDesc(pDevIns, &desc, ((uint64_t)TDBAH << 32) + TDBAL + TDH * sizeof(desc));
5551 rc = e1kXmitDesc(pDevIns, pThis, pThisCC, &desc, e1kDescAddr(TDBAH, TDBAL, TDH), fOnWorkerThread);
5552 /* If we failed to transmit descriptor we will try it again later */
5553 if (RT_FAILURE(rc))
5554 break;
5555 if (++TDH * sizeof(desc) >= TDLEN)
5556 TDH = 0;
5557
5558 if (e1kGetTxLen(pThis) <= GET_BITS(TXDCTL, LWTHRESH)*8)
5559 {
5560 E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
5561 pThis->szPrf, e1kGetTxLen(pThis), GET_BITS(TXDCTL, LWTHRESH)*8));
5562 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5563 }
5564
5565 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5566 }
5567
5568 /// @todo uncomment: pThis->uStatIntTXQE++;
5569 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5570 /*
5571 * Release the lock.
5572 */
5573 if (pDrv)
5574 pDrv->pfnEndXmit(pDrv);
5575 e1kCsTxLeave(pThis);
5576 }
5577
5578 return rc;
5579}
5580
5581#else /* E1K_WITH_TXD_CACHE */
5582
5583static void e1kDumpTxDCache(PPDMDEVINS pDevIns, PE1KSTATE pThis, PE1KTXDC pTxdc)
5584{
5585 unsigned i, cDescs = pTxdc->tdlen / sizeof(E1KTXDESC);
5586 uint32_t tdh = pTxdc->tdh;
5587 LogRel(("E1000: -- Transmit Descriptors (%d total) --\n", cDescs));
5588 for (i = 0; i < cDescs; ++i)
5589 {
5590 E1KTXDESC desc;
5591 PDMDevHlpPCIPhysRead(pDevIns , e1kDescAddr(TDBAH, TDBAL, i), &desc, sizeof(desc));
5592 if (i == tdh)
5593 LogRel(("E1000: >>> "));
5594 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc));
5595 }
5596 LogRel(("E1000: -- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
5597 pThis->iTxDCurrent, pTxdc->tdh, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE));
5598 if (tdh > pThis->iTxDCurrent)
5599 tdh -= pThis->iTxDCurrent;
5600 else
5601 tdh = cDescs + tdh - pThis->iTxDCurrent;
5602 for (i = 0; i < pThis->nTxDFetched; ++i)
5603 {
5604 if (i == pThis->iTxDCurrent)
5605 LogRel(("E1000: >>> "));
5606 if (cDescs)
5607 LogRel(("E1000: %RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs), &pThis->aTxDescriptors[i]));
5608 else
5609 LogRel(("E1000: <lost>: %R[e1ktxd]\n", &pThis->aTxDescriptors[i]));
5610 }
5611}
5612
5613/**
5614 * Transmit pending descriptors.
5615 *
5616 * @returns VBox status code. VERR_TRY_AGAIN is returned if we're busy.
5617 *
5618 * @param pDevIns The device instance.
5619 * @param pThis The E1000 state.
5620 * @param fOnWorkerThread Whether we're on a worker thread or on an EMT.
5621 */
5622static int e1kXmitPending(PPDMDEVINS pDevIns, PE1KSTATE pThis, bool fOnWorkerThread)
5623{
5624 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5625 int rc = VINF_SUCCESS;
5626
5627 /* Check if transmitter is enabled. */
5628 if (!(TCTL & TCTL_EN))
5629 return VINF_SUCCESS;
5630 /*
5631 * Grab the xmit lock of the driver as well as the E1K device state.
5632 */
5633 PPDMINETWORKUP pDrv = pThisCC->CTX_SUFF(pDrv);
5634 if (pDrv)
5635 {
5636 rc = pDrv->pfnBeginXmit(pDrv, fOnWorkerThread);
5637 if (RT_FAILURE(rc))
5638 return rc;
5639 }
5640
5641 /*
5642 * Process all pending descriptors.
5643 * Note! Do not process descriptors in locked state
5644 */
5645 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5646 if (RT_LIKELY(rc == VINF_SUCCESS && (TCTL & TCTL_EN)))
5647 {
5648 E1KTXDC txdc;
5649 bool fTxContextValid = e1kUpdateTxDContext(pDevIns, pThis, &txdc);
5650 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTransmit), a);
5651 /*
5652 * fIncomplete is set whenever we try to fetch additional descriptors
5653 * for an incomplete packet. If fail to locate a complete packet on
5654 * the next iteration we need to reset the cache or we risk to get
5655 * stuck in this loop forever.
5656 */
5657 bool fIncomplete = false;
5658 while (fTxContextValid && !pThis->fLocked && e1kTxDLazyLoad(pDevIns, pThis, &txdc))
5659 {
5660 while (e1kLocateTxPacket(pThis))
5661 {
5662 fIncomplete = false;
5663 /* Found a complete packet, allocate it. */
5664 rc = e1kXmitAllocBuf(pThis, pThisCC, pThis->fGSO);
5665 /* If we're out of bandwidth we'll come back later. */
5666 if (RT_FAILURE(rc))
5667 goto out;
5668 /* Copy the packet to allocated buffer and send it. */
5669 rc = e1kXmitPacket(pDevIns, pThis, fOnWorkerThread, &txdc);
5670 /* If we're out of bandwidth we'll come back later. */
5671 if (RT_FAILURE(rc))
5672 goto out;
5673 }
5674 uint8_t u8Remain = pThis->nTxDFetched - pThis->iTxDCurrent;
5675 if (RT_UNLIKELY(fIncomplete))
5676 {
5677 static bool fTxDCacheDumped = false;
5678 /*
5679 * The descriptor cache is full, but we were unable to find
5680 * a complete packet in it. Drop the cache and hope that
5681 * the guest driver can recover from network card error.
5682 */
5683 LogRel(("%s: No complete packets in%s TxD cache! "
5684 "Fetched=%d, current=%d, TX len=%d.\n",
5685 pThis->szPrf,
5686 u8Remain == E1K_TXD_CACHE_SIZE ? " full" : "",
5687 pThis->nTxDFetched, pThis->iTxDCurrent,
5688 e1kGetTxLen(&txdc)));
5689 if (!fTxDCacheDumped)
5690 {
5691 fTxDCacheDumped = true;
5692 e1kDumpTxDCache(pDevIns, pThis, &txdc);
5693 }
5694 pThis->iTxDCurrent = pThis->nTxDFetched = 0;
5695 /*
5696 * Returning an error at this point means Guru in R0
5697 * (see @bugref{6428}).
5698 */
5699# ifdef IN_RING3
5700 rc = VERR_NET_INCOMPLETE_TX_PACKET;
5701# else /* !IN_RING3 */
5702 rc = VINF_IOM_R3_MMIO_WRITE;
5703# endif /* !IN_RING3 */
5704 goto out;
5705 }
5706 if (u8Remain > 0)
5707 {
5708 Log4(("%s Incomplete packet at %d. Already fetched %d, "
5709 "%d more are available\n",
5710 pThis->szPrf, pThis->iTxDCurrent, u8Remain,
5711 e1kGetTxLen(&txdc) - u8Remain));
5712
5713 /*
5714 * A packet was partially fetched. Move incomplete packet to
5715 * the beginning of cache buffer, then load more descriptors.
5716 */
5717 memmove(pThis->aTxDescriptors,
5718 &pThis->aTxDescriptors[pThis->iTxDCurrent],
5719 u8Remain * sizeof(E1KTXDESC));
5720 pThis->iTxDCurrent = 0;
5721 pThis->nTxDFetched = u8Remain;
5722 e1kTxDLoadMore(pDevIns, pThis, &txdc);
5723 fIncomplete = true;
5724 }
5725 else
5726 pThis->nTxDFetched = 0;
5727 pThis->iTxDCurrent = 0;
5728 }
5729 if (!pThis->fLocked && GET_BITS(TXDCTL, LWTHRESH) == 0)
5730 {
5731 E1kLog2(("%s Out of transmit descriptors, raise ICR.TXD_LOW\n",
5732 pThis->szPrf));
5733 e1kRaiseInterrupt(pDevIns, pThis, VERR_SEM_BUSY, ICR_TXD_LOW);
5734 }
5735out:
5736 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTransmit), a);
5737
5738 /// @todo uncomment: pThis->uStatIntTXQE++;
5739 /// @todo uncomment: e1kRaiseInterrupt(pDevIns, pThis, ICR_TXQE);
5740
5741 e1kCsTxLeave(pThis);
5742 }
5743
5744
5745 /*
5746 * Release the lock.
5747 */
5748 if (pDrv)
5749 pDrv->pfnEndXmit(pDrv);
5750 return rc;
5751}
5752
5753#endif /* E1K_WITH_TXD_CACHE */
5754#ifdef IN_RING3
5755
5756/**
5757 * @interface_method_impl{PDMINETWORKDOWN,pfnXmitPending}
5758 */
5759static DECLCALLBACK(void) e1kR3NetworkDown_XmitPending(PPDMINETWORKDOWN pInterface)
5760{
5761 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
5762 PE1KSTATE pThis = pThisCC->pShared;
5763 /* Resume suspended transmission */
5764 STATUS &= ~STATUS_TXOFF;
5765 e1kXmitPending(pThisCC->pDevInsR3, pThis, true /*fOnWorkerThread*/);
5766}
5767
5768/**
5769 * @callback_method_impl{FNPDMTASKDEV,
5770 * Executes e1kXmitPending at the behest of ring-0/raw-mode.}
5771 * @note Not executed on EMT.
5772 */
5773static DECLCALLBACK(void) e1kR3TxTaskCallback(PPDMDEVINS pDevIns, void *pvUser)
5774{
5775 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
5776 E1kLog2(("%s e1kR3TxTaskCallback:\n", pThis->szPrf));
5777
5778 int rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5779 AssertMsg(RT_SUCCESS(rc) || rc == VERR_TRY_AGAIN || rc == VERR_NET_DOWN, ("%Rrc\n", rc));
5780
5781 RT_NOREF(rc, pvUser);
5782}
5783
5784#endif /* IN_RING3 */
5785
5786/**
5787 * Write handler for Transmit Descriptor Tail register.
5788 *
5789 * @param pThis The device state structure.
5790 * @param offset Register offset in memory-mapped frame.
5791 * @param index Register index in register array.
5792 * @param value The value to store.
5793 * @param mask Used to implement partial writes (8 and 16-bit).
5794 * @thread EMT
5795 */
5796static int e1kRegWriteTDT(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5797{
5798 int rc = e1kRegWriteDefault(pDevIns, pThis, offset, index, value);
5799
5800 /* All descriptors starting with head and not including tail belong to us. */
5801 /* Process them. */
5802 E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
5803 pThis->szPrf, TDBAL, TDBAH, TDLEN, TDH, TDT));
5804
5805 /* Compose a temporary TX context, breaking TX CS rule, for debugging purposes. */
5806 /* If we decide to transmit, the TX critical section will be entered later in e1kXmitPending(). */
5807 E1KTXDC txdc;
5808 txdc.tdlen = TDLEN;
5809 txdc.tdh = TDH;
5810 txdc.tdt = TDT;
5811 /* Ignore TDT writes when the link is down. */
5812 if (txdc.tdh != txdc.tdt && (STATUS & STATUS_LU))
5813 {
5814 Log5(("E1000: TDT write: TDH=%08x, TDT=%08x, %d descriptors to process\n", txdc.tdh, txdc.tdt, e1kGetTxLen(&txdc)));
5815 E1kLog(("%s e1kRegWriteTDT: %d descriptors to process\n",
5816 pThis->szPrf, e1kGetTxLen(&txdc)));
5817
5818 /* Transmit pending packets if possible, defer it if we cannot do it
5819 in the current context. */
5820#ifdef E1K_TX_DELAY
5821 rc = e1kCsTxEnter(pThis, VERR_SEM_BUSY);
5822 if (RT_LIKELY(rc == VINF_SUCCESS))
5823 {
5824 if (!PDMDevInsTimerIsActive(pDevIns, pThis->hTXDTimer))
5825 {
5826# ifdef E1K_INT_STATS
5827 pThis->u64ArmedAt = RTTimeNanoTS();
5828# endif
5829 e1kArmTimer(pDevIns, pThis, pThis->hTXDTimer, E1K_TX_DELAY);
5830 }
5831 E1K_INC_ISTAT_CNT(pThis->uStatTxDelayed);
5832 e1kCsTxLeave(pThis);
5833 return rc;
5834 }
5835 /* We failed to enter the TX critical section -- transmit as usual. */
5836#endif /* E1K_TX_DELAY */
5837#ifndef IN_RING3
5838 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
5839 if (!pThisCC->CTX_SUFF(pDrv))
5840 {
5841 PDMDevHlpTaskTrigger(pDevIns, pThis->hTxTask);
5842 rc = VINF_SUCCESS;
5843 }
5844 else
5845#endif
5846 {
5847 rc = e1kXmitPending(pDevIns, pThis, false /*fOnWorkerThread*/);
5848 if (rc == VERR_TRY_AGAIN)
5849 rc = VINF_SUCCESS;
5850#ifndef IN_RING3
5851 else if (rc == VERR_SEM_BUSY)
5852 rc = VINF_IOM_R3_MMIO_WRITE;
5853#endif
5854 AssertRC(rc);
5855 }
5856 }
5857
5858 return rc;
5859}
5860
5861/**
5862 * Write handler for Multicast Table Array registers.
5863 *
5864 * @param pThis The device state structure.
5865 * @param offset Register offset in memory-mapped frame.
5866 * @param index Register index in register array.
5867 * @param value The value to store.
5868 * @thread EMT
5869 */
5870static int e1kRegWriteMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5871{
5872 RT_NOREF_PV(pDevIns);
5873 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5874 pThis->auMTA[(offset - g_aE1kRegMap[index].offset) / sizeof(pThis->auMTA[0])] = value;
5875
5876 return VINF_SUCCESS;
5877}
5878
5879/**
5880 * Read handler for Multicast Table Array registers.
5881 *
5882 * @returns VBox status code.
5883 *
5884 * @param pThis The device state structure.
5885 * @param offset Register offset in memory-mapped frame.
5886 * @param index Register index in register array.
5887 * @thread EMT
5888 */
5889static int e1kRegReadMTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5890{
5891 RT_NOREF_PV(pDevIns);
5892 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auMTA), VERR_DEV_IO_ERROR);
5893 *pu32Value = pThis->auMTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auMTA[0])];
5894
5895 return VINF_SUCCESS;
5896}
5897
5898/**
5899 * Write handler for Receive Address registers.
5900 *
5901 * @param pThis The device state structure.
5902 * @param offset Register offset in memory-mapped frame.
5903 * @param index Register index in register array.
5904 * @param value The value to store.
5905 * @thread EMT
5906 */
5907static int e1kRegWriteRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5908{
5909 RT_NOREF_PV(pDevIns);
5910 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5911 pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])] = value;
5912
5913 return VINF_SUCCESS;
5914}
5915
5916/**
5917 * Read handler for Receive Address registers.
5918 *
5919 * @returns VBox status code.
5920 *
5921 * @param pThis The device state structure.
5922 * @param offset Register offset in memory-mapped frame.
5923 * @param index Register index in register array.
5924 * @thread EMT
5925 */
5926static int e1kRegReadRA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5927{
5928 RT_NOREF_PV(pDevIns);
5929 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->aRecAddr.au32), VERR_DEV_IO_ERROR);
5930 *pu32Value = pThis->aRecAddr.au32[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->aRecAddr.au32[0])];
5931
5932 return VINF_SUCCESS;
5933}
5934
5935/**
5936 * Write handler for VLAN Filter Table Array registers.
5937 *
5938 * @param pThis The device state structure.
5939 * @param offset Register offset in memory-mapped frame.
5940 * @param index Register index in register array.
5941 * @param value The value to store.
5942 * @thread EMT
5943 */
5944static int e1kRegWriteVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
5945{
5946 RT_NOREF_PV(pDevIns);
5947 AssertReturn(offset - g_aE1kRegMap[index].offset < sizeof(pThis->auVFTA), VINF_SUCCESS);
5948 pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])] = value;
5949
5950 return VINF_SUCCESS;
5951}
5952
5953/**
5954 * Read handler for VLAN Filter Table Array registers.
5955 *
5956 * @returns VBox status code.
5957 *
5958 * @param pThis The device state structure.
5959 * @param offset Register offset in memory-mapped frame.
5960 * @param index Register index in register array.
5961 * @thread EMT
5962 */
5963static int e1kRegReadVFTA(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5964{
5965 RT_NOREF_PV(pDevIns);
5966 AssertReturn(offset - g_aE1kRegMap[index].offset< sizeof(pThis->auVFTA), VERR_DEV_IO_ERROR);
5967 *pu32Value = pThis->auVFTA[(offset - g_aE1kRegMap[index].offset)/sizeof(pThis->auVFTA[0])];
5968
5969 return VINF_SUCCESS;
5970}
5971
5972/**
5973 * Read handler for unimplemented registers.
5974 *
5975 * Merely reports reads from unimplemented registers.
5976 *
5977 * @returns VBox status code.
5978 *
5979 * @param pThis The device state structure.
5980 * @param offset Register offset in memory-mapped frame.
5981 * @param index Register index in register array.
5982 * @thread EMT
5983 */
5984static int e1kRegReadUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
5985{
5986 RT_NOREF(pDevIns, pThis, offset, index);
5987 E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
5988 pThis->szPrf, offset, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
5989 *pu32Value = 0;
5990
5991 return VINF_SUCCESS;
5992}
5993
5994/**
5995 * Default register read handler with automatic clear operation.
5996 *
5997 * Retrieves the value of register from register array in device state structure.
5998 * Then resets all bits.
5999 *
6000 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
6001 * done in the caller.
6002 *
6003 * @returns VBox status code.
6004 *
6005 * @param pThis The device state structure.
6006 * @param offset Register offset in memory-mapped frame.
6007 * @param index Register index in register array.
6008 * @thread EMT
6009 */
6010static int e1kRegReadAutoClear(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6011{
6012 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6013 int rc = e1kRegReadDefault(pDevIns, pThis, offset, index, pu32Value);
6014 pThis->auRegs[index] = 0;
6015
6016 return rc;
6017}
6018
6019/**
6020 * Default register read handler.
6021 *
6022 * Retrieves the value of register from register array in device state structure.
6023 * Bits corresponding to 0s in 'readable' mask will always read as 0s.
6024 *
6025 * @remarks The 'mask' parameter is simply ignored as masking and shifting is
6026 * done in the caller.
6027 *
6028 * @returns VBox status code.
6029 *
6030 * @param pThis The device state structure.
6031 * @param offset Register offset in memory-mapped frame.
6032 * @param index Register index in register array.
6033 * @thread EMT
6034 */
6035static int e1kRegReadDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
6036{
6037 RT_NOREF_PV(pDevIns); RT_NOREF_PV(offset);
6038
6039 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6040 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable;
6041
6042 return VINF_SUCCESS;
6043}
6044
6045/**
6046 * Write handler for unimplemented registers.
6047 *
6048 * Merely reports writes to unimplemented registers.
6049 *
6050 * @param pThis The device state structure.
6051 * @param offset Register offset in memory-mapped frame.
6052 * @param index Register index in register array.
6053 * @param value The value to store.
6054 * @thread EMT
6055 */
6056
6057 static int e1kRegWriteUnimplemented(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6058{
6059 RT_NOREF_PV(pDevIns); RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value);
6060
6061 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
6062 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6063
6064 return VINF_SUCCESS;
6065}
6066
6067/**
6068 * Default register write handler.
6069 *
6070 * Stores the value to the register array in device state structure. Only bits
6071 * corresponding to 1s both in 'writable' and 'mask' will be stored.
6072 *
6073 * @returns VBox status code.
6074 *
6075 * @param pThis The device state structure.
6076 * @param offset Register offset in memory-mapped frame.
6077 * @param index Register index in register array.
6078 * @param value The value to store.
6079 * @param mask Used to implement partial writes (8 and 16-bit).
6080 * @thread EMT
6081 */
6082
6083static int e1kRegWriteDefault(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
6084{
6085 RT_NOREF(pDevIns, offset);
6086
6087 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR);
6088 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable)
6089 | (pThis->auRegs[index] & ~g_aE1kRegMap[index].writable);
6090
6091 return VINF_SUCCESS;
6092}
6093
6094/**
6095 * Search register table for matching register.
6096 *
6097 * @returns Index in the register table or -1 if not found.
6098 *
6099 * @param offReg Register offset in memory-mapped region.
6100 * @thread EMT
6101 */
6102static int e1kRegLookup(uint32_t offReg)
6103{
6104
6105#if 0
6106 int index;
6107
6108 for (index = 0; index < E1K_NUM_OF_REGS; index++)
6109 {
6110 if (g_aE1kRegMap[index].offset <= offReg && offReg < g_aE1kRegMap[index].offset + g_aE1kRegMap[index].size)
6111 {
6112 return index;
6113 }
6114 }
6115#else
6116 int iStart = 0;
6117 int iEnd = E1K_NUM_OF_BINARY_SEARCHABLE;
6118 for (;;)
6119 {
6120 int i = (iEnd - iStart) / 2 + iStart;
6121 uint32_t offCur = g_aE1kRegMap[i].offset;
6122 if (offReg < offCur)
6123 {
6124 if (i == iStart)
6125 break;
6126 iEnd = i;
6127 }
6128 else if (offReg >= offCur + g_aE1kRegMap[i].size)
6129 {
6130 i++;
6131 if (i == iEnd)
6132 break;
6133 iStart = i;
6134 }
6135 else
6136 return i;
6137 Assert(iEnd > iStart);
6138 }
6139
6140 for (unsigned i = E1K_NUM_OF_BINARY_SEARCHABLE; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6141 if (offReg - g_aE1kRegMap[i].offset < g_aE1kRegMap[i].size)
6142 return (int)i;
6143
6144# ifdef VBOX_STRICT
6145 for (unsigned i = 0; i < RT_ELEMENTS(g_aE1kRegMap); i++)
6146 Assert(offReg - g_aE1kRegMap[i].offset >= g_aE1kRegMap[i].size);
6147# endif
6148
6149#endif
6150
6151 return -1;
6152}
6153
6154/**
6155 * Handle unaligned register read operation.
6156 *
6157 * Looks up and calls appropriate handler.
6158 *
6159 * @returns VBox status code.
6160 *
6161 * @param pDevIns The device instance.
6162 * @param pThis The device state structure.
6163 * @param offReg Register offset in memory-mapped frame.
6164 * @param pv Where to store the result.
6165 * @param cb Number of bytes to read.
6166 * @thread EMT
6167 * @remarks IOM takes care of unaligned and small reads via MMIO. For I/O port
6168 * accesses we have to take care of that ourselves.
6169 */
6170static int e1kRegReadUnaligned(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, void *pv, uint32_t cb)
6171{
6172 uint32_t u32 = 0;
6173 uint32_t shift;
6174 int rc = VINF_SUCCESS;
6175 int index = e1kRegLookup(offReg);
6176#ifdef LOG_ENABLED
6177 char buf[9];
6178#endif
6179
6180 /*
6181 * From the spec:
6182 * For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
6183 * double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
6184 */
6185
6186 /*
6187 * To be able to read bytes and short word we convert them to properly
6188 * shifted 32-bit words and masks. The idea is to keep register-specific
6189 * handlers simple. Most accesses will be 32-bit anyway.
6190 */
6191 uint32_t mask;
6192 switch (cb)
6193 {
6194 case 4: mask = 0xFFFFFFFF; break;
6195 case 2: mask = 0x0000FFFF; break;
6196 case 1: mask = 0x000000FF; break;
6197 default:
6198 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "unsupported op size: offset=%#10x cb=%#10x\n", offReg, cb);
6199 }
6200 if (index >= 0)
6201 {
6202 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6203 if (g_aE1kRegMap[index].readable)
6204 {
6205 /* Make the mask correspond to the bits we are about to read. */
6206 shift = (offReg - g_aE1kRegMap[index].offset) % sizeof(uint32_t) * 8;
6207 mask <<= shift;
6208 if (!mask)
6209 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "Zero mask: offset=%#10x cb=%#10x\n", offReg, cb);
6210 /*
6211 * Read it. Pass the mask so the handler knows what has to be read.
6212 * Mask out irrelevant bits.
6213 */
6214 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6215 if (RT_UNLIKELY(rc != VINF_SUCCESS))
6216 return rc;
6217 //pThis->fDelayInts = false;
6218 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6219 //pThis->iStatIntLostOne = 0;
6220 rc = g_aE1kRegMap[index].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)index, &u32);
6221 u32 &= mask;
6222 //e1kCsLeave(pThis);
6223 E1kLog2(("%s At %08X read %s from %s (%s)\n",
6224 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6225 Log6(("%s At %08X read %s from %s (%s) [UNALIGNED]\n",
6226 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6227 /* Shift back the result. */
6228 u32 >>= shift;
6229 }
6230 else
6231 E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
6232 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf), g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6233 if (IOM_SUCCESS(rc))
6234 STAM_COUNTER_INC(&pThis->aStatRegReads[index]);
6235 }
6236 else
6237 E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
6238 pThis->szPrf, offReg, e1kU32toHex(u32, mask, buf)));
6239
6240 memcpy(pv, &u32, cb);
6241 return rc;
6242}
6243
6244/**
6245 * Handle 4 byte aligned and sized read operation.
6246 *
6247 * Looks up and calls appropriate handler.
6248 *
6249 * @returns VBox status code.
6250 *
6251 * @param pDevIns The device instance.
6252 * @param pThis The device state structure.
6253 * @param offReg Register offset in memory-mapped frame.
6254 * @param pu32 Where to store the result.
6255 * @thread EMT
6256 */
6257static VBOXSTRICTRC e1kRegReadAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t *pu32)
6258{
6259 Assert(!(offReg & 3));
6260
6261 /*
6262 * Lookup the register and check that it's readable.
6263 */
6264 VBOXSTRICTRC rc = VINF_SUCCESS;
6265 int idxReg = e1kRegLookup(offReg);
6266 if (RT_LIKELY(idxReg >= 0))
6267 {
6268 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6269 if (RT_UNLIKELY(g_aE1kRegMap[idxReg].readable))
6270 {
6271 /*
6272 * Read it. Pass the mask so the handler knows what has to be read.
6273 * Mask out irrelevant bits.
6274 */
6275 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6276 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6277 // return rc;
6278 //pThis->fDelayInts = false;
6279 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6280 //pThis->iStatIntLostOne = 0;
6281 rc = g_aE1kRegMap[idxReg].pfnRead(pDevIns, pThis, offReg & 0xFFFFFFFC, (uint32_t)idxReg, pu32);
6282 //e1kCsLeave(pThis);
6283 Log6(("%s At %08X read %08X from %s (%s)\n",
6284 pThis->szPrf, offReg, *pu32, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6285 if (IOM_SUCCESS(rc))
6286 STAM_COUNTER_INC(&pThis->aStatRegReads[idxReg]);
6287 }
6288 else
6289 E1kLog(("%s At %08X read attempt from non-readable register %s (%s)\n",
6290 pThis->szPrf, offReg, g_aE1kRegMap[idxReg].abbrev, g_aE1kRegMap[idxReg].name));
6291 }
6292 else
6293 E1kLog(("%s At %08X read attempt from non-existing register\n", pThis->szPrf, offReg));
6294 return rc;
6295}
6296
6297/**
6298 * Handle 4 byte sized and aligned register write operation.
6299 *
6300 * Looks up and calls appropriate handler.
6301 *
6302 * @returns VBox status code.
6303 *
6304 * @param pDevIns The device instance.
6305 * @param pThis The device state structure.
6306 * @param offReg Register offset in memory-mapped frame.
6307 * @param u32Value The value to write.
6308 * @thread EMT
6309 */
6310static VBOXSTRICTRC e1kRegWriteAlignedU32(PPDMDEVINS pDevIns, PE1KSTATE pThis, uint32_t offReg, uint32_t u32Value)
6311{
6312 VBOXSTRICTRC rc = VINF_SUCCESS;
6313 int index = e1kRegLookup(offReg);
6314 if (RT_LIKELY(index >= 0))
6315 {
6316 RT_UNTRUSTED_VALIDATED_FENCE(); /* paranoia because of port I/O. */
6317 if (RT_LIKELY(g_aE1kRegMap[index].writable))
6318 {
6319 /*
6320 * Write it. Pass the mask so the handler knows what has to be written.
6321 * Mask out irrelevant bits.
6322 */
6323 Log6(("%s At %08X write %08X to %s (%s)\n",
6324 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6325 //rc = e1kCsEnter(pThis, VERR_SEM_BUSY, RT_SRC_POS);
6326 //if (RT_UNLIKELY(rc != VINF_SUCCESS))
6327 // return rc;
6328 //pThis->fDelayInts = false;
6329 //pThis->iStatIntLost += pThis->iStatIntLostOne;
6330 //pThis->iStatIntLostOne = 0;
6331 rc = g_aE1kRegMap[index].pfnWrite(pDevIns, pThis, offReg, (uint32_t)index, u32Value);
6332 //e1kCsLeave(pThis);
6333 }
6334 else
6335 E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
6336 pThis->szPrf, offReg, u32Value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name));
6337 if (IOM_SUCCESS(rc))
6338 STAM_COUNTER_INC(&pThis->aStatRegWrites[index]);
6339 }
6340 else
6341 E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
6342 pThis->szPrf, offReg, u32Value));
6343 return rc;
6344}
6345
6346
6347/* -=-=-=-=- MMIO and I/O Port Callbacks -=-=-=-=- */
6348
6349/**
6350 * @callback_method_impl{FNIOMMMIONEWREAD}
6351 */
6352static DECLCALLBACK(VBOXSTRICTRC) e1kMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, uint32_t cb)
6353{
6354 RT_NOREF2(pvUser, cb);
6355 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6356 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6357
6358 Assert(off < E1K_MM_SIZE);
6359 Assert(cb == 4);
6360 Assert(!(off & 3));
6361
6362 VBOXSTRICTRC rcStrict = e1kRegReadAlignedU32(pDevIns, pThis, (uint32_t)off, (uint32_t *)pv);
6363
6364 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIORead), a);
6365 return rcStrict;
6366}
6367
6368/**
6369 * @callback_method_impl{FNIOMMMIONEWWRITE}
6370 */
6371static DECLCALLBACK(VBOXSTRICTRC) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, uint32_t cb)
6372{
6373 RT_NOREF2(pvUser, cb);
6374 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6375 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6376
6377 Assert(off < E1K_MM_SIZE);
6378 Assert(cb == 4);
6379 Assert(!(off & 3));
6380
6381 VBOXSTRICTRC rcStrict = e1kRegWriteAlignedU32(pDevIns, pThis, (uint32_t)off, *(uint32_t const *)pv);
6382
6383 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatMMIOWrite), a);
6384 return rcStrict;
6385}
6386
6387/**
6388 * @callback_method_impl{FNIOMIOPORTNEWIN}
6389 */
6390static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb)
6391{
6392 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6393 VBOXSTRICTRC rc;
6394 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a);
6395 RT_NOREF_PV(pvUser);
6396
6397 if (RT_LIKELY(cb == 4))
6398 switch (offPort)
6399 {
6400 case 0x00: /* IOADDR */
6401 *pu32 = pThis->uSelectedReg;
6402 Log9(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6403 rc = VINF_SUCCESS;
6404 break;
6405
6406 case 0x04: /* IODATA */
6407 if (!(pThis->uSelectedReg & 3))
6408 rc = e1kRegReadAlignedU32(pDevIns, pThis, pThis->uSelectedReg, pu32);
6409 else /** @todo r=bird: I wouldn't be surprised if this unaligned branch wasn't necessary. */
6410 rc = e1kRegReadUnaligned(pDevIns, pThis, pThis->uSelectedReg, pu32, cb);
6411 if (rc == VINF_IOM_R3_MMIO_READ)
6412 rc = VINF_IOM_R3_IOPORT_READ;
6413 Log9(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", pThis->szPrf, pThis->uSelectedReg, *pu32));
6414 break;
6415
6416 default:
6417 E1kLog(("%s e1kIOPortIn: invalid port %#010x\n", pThis->szPrf, offPort));
6418 /** @todo r=bird: Check what real hardware returns here. */
6419 //rc = VERR_IOM_IOPORT_UNUSED; /* Why not? */
6420 rc = VINF_IOM_MMIO_UNUSED_00; /* used to return VINF_SUCCESS and not touch *pu32, which amounted to this. */
6421 break;
6422 }
6423 else
6424 {
6425 E1kLog(("%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x", pThis->szPrf, offPort, cb));
6426 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb);
6427 *pu32 = 0; /** @todo r=bird: Check what real hardware returns here. (Didn't used to set a value here, picked zero as that's what we'd end up in most cases.) */
6428 }
6429 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIORead), a);
6430 return rc;
6431}
6432
6433
6434/**
6435 * @callback_method_impl{FNIOMIOPORTNEWOUT}
6436 */
6437static DECLCALLBACK(VBOXSTRICTRC) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb)
6438{
6439 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
6440 VBOXSTRICTRC rc;
6441 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6442 RT_NOREF_PV(pvUser);
6443
6444 Log9(("%s e1kIOPortOut: offPort=%RTiop value=%08x\n", pThis->szPrf, offPort, u32));
6445 if (RT_LIKELY(cb == 4))
6446 {
6447 switch (offPort)
6448 {
6449 case 0x00: /* IOADDR */
6450 pThis->uSelectedReg = u32;
6451 Log9(("%s e1kIOPortOut: IOADDR(0), selected register %08x\n", pThis->szPrf, pThis->uSelectedReg));
6452 rc = VINF_SUCCESS;
6453 break;
6454
6455 case 0x04: /* IODATA */
6456 Log9(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", pThis->szPrf, pThis->uSelectedReg, u32));
6457 if (RT_LIKELY(!(pThis->uSelectedReg & 3)))
6458 {
6459 rc = e1kRegWriteAlignedU32(pDevIns, pThis, pThis->uSelectedReg, u32);
6460 if (rc == VINF_IOM_R3_MMIO_WRITE)
6461 rc = VINF_IOM_R3_IOPORT_WRITE;
6462 }
6463 else
6464 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS,
6465 "Spec violation: misaligned offset: %#10x, ignored.\n", pThis->uSelectedReg);
6466 break;
6467
6468 default:
6469 E1kLog(("%s e1kIOPortOut: invalid port %#010x\n", pThis->szPrf, offPort));
6470 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "invalid port %#010x\n", offPort);
6471 }
6472 }
6473 else
6474 {
6475 E1kLog(("%s e1kIOPortOut: invalid op size: offPort=%RTiop cb=%08x\n", pThis->szPrf, offPort, cb));
6476 rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "%s: invalid op size: offPort=%RTiop cb=%#x\n", pThis->szPrf, offPort, cb);
6477 }
6478
6479 STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatIOWrite), a);
6480 return rc;
6481}
6482
6483#ifdef IN_RING3
6484
6485/**
6486 * Dump complete device state to log.
6487 *
6488 * @param pThis Pointer to device state.
6489 */
6490static void e1kDumpState(PE1KSTATE pThis)
6491{
6492 RT_NOREF(pThis);
6493 for (int i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
6494 E1kLog2(("%s: %8.8s = %08x\n", pThis->szPrf, g_aE1kRegMap[i].abbrev, pThis->auRegs[i]));
6495# ifdef E1K_INT_STATS
6496 LogRel(("%s: Interrupt attempts: %d\n", pThis->szPrf, pThis->uStatIntTry));
6497 LogRel(("%s: Interrupts raised : %d\n", pThis->szPrf, pThis->uStatInt));
6498 LogRel(("%s: Interrupts lowered: %d\n", pThis->szPrf, pThis->uStatIntLower));
6499 LogRel(("%s: ICR outside ISR : %d\n", pThis->szPrf, pThis->uStatNoIntICR));
6500 LogRel(("%s: IMS raised ints : %d\n", pThis->szPrf, pThis->uStatIntIMS));
6501 LogRel(("%s: Interrupts skipped: %d\n", pThis->szPrf, pThis->uStatIntSkip));
6502 LogRel(("%s: Masked interrupts : %d\n", pThis->szPrf, pThis->uStatIntMasked));
6503 LogRel(("%s: Early interrupts : %d\n", pThis->szPrf, pThis->uStatIntEarly));
6504 LogRel(("%s: Late interrupts : %d\n", pThis->szPrf, pThis->uStatIntLate));
6505 LogRel(("%s: Lost interrupts : %d\n", pThis->szPrf, pThis->iStatIntLost));
6506 LogRel(("%s: Interrupts by RX : %d\n", pThis->szPrf, pThis->uStatIntRx));
6507 LogRel(("%s: Interrupts by TX : %d\n", pThis->szPrf, pThis->uStatIntTx));
6508 LogRel(("%s: Interrupts by ICS : %d\n", pThis->szPrf, pThis->uStatIntICS));
6509 LogRel(("%s: Interrupts by RDTR: %d\n", pThis->szPrf, pThis->uStatIntRDTR));
6510 LogRel(("%s: Interrupts by RDMT: %d\n", pThis->szPrf, pThis->uStatIntRXDMT0));
6511 LogRel(("%s: Interrupts by TXQE: %d\n", pThis->szPrf, pThis->uStatIntTXQE));
6512 LogRel(("%s: TX int delay asked: %d\n", pThis->szPrf, pThis->uStatTxIDE));
6513 LogRel(("%s: TX delayed: %d\n", pThis->szPrf, pThis->uStatTxDelayed));
6514 LogRel(("%s: TX delay expired: %d\n", pThis->szPrf, pThis->uStatTxDelayExp));
6515 LogRel(("%s: TX no report asked: %d\n", pThis->szPrf, pThis->uStatTxNoRS));
6516 LogRel(("%s: TX abs timer expd : %d\n", pThis->szPrf, pThis->uStatTAD));
6517 LogRel(("%s: TX int timer expd : %d\n", pThis->szPrf, pThis->uStatTID));
6518 LogRel(("%s: RX abs timer expd : %d\n", pThis->szPrf, pThis->uStatRAD));
6519 LogRel(("%s: RX int timer expd : %d\n", pThis->szPrf, pThis->uStatRID));
6520 LogRel(("%s: TX CTX descriptors: %d\n", pThis->szPrf, pThis->uStatDescCtx));
6521 LogRel(("%s: TX DAT descriptors: %d\n", pThis->szPrf, pThis->uStatDescDat));
6522 LogRel(("%s: TX LEG descriptors: %d\n", pThis->szPrf, pThis->uStatDescLeg));
6523 LogRel(("%s: Received frames : %d\n", pThis->szPrf, pThis->uStatRxFrm));
6524 LogRel(("%s: Transmitted frames: %d\n", pThis->szPrf, pThis->uStatTxFrm));
6525 LogRel(("%s: TX frames up to 1514: %d\n", pThis->szPrf, pThis->uStatTx1514));
6526 LogRel(("%s: TX frames up to 2962: %d\n", pThis->szPrf, pThis->uStatTx2962));
6527 LogRel(("%s: TX frames up to 4410: %d\n", pThis->szPrf, pThis->uStatTx4410));
6528 LogRel(("%s: TX frames up to 5858: %d\n", pThis->szPrf, pThis->uStatTx5858));
6529 LogRel(("%s: TX frames up to 7306: %d\n", pThis->szPrf, pThis->uStatTx7306));
6530 LogRel(("%s: TX frames up to 8754: %d\n", pThis->szPrf, pThis->uStatTx8754));
6531 LogRel(("%s: TX frames up to 16384: %d\n", pThis->szPrf, pThis->uStatTx16384));
6532 LogRel(("%s: TX frames up to 32768: %d\n", pThis->szPrf, pThis->uStatTx32768));
6533 LogRel(("%s: Larger TX frames : %d\n", pThis->szPrf, pThis->uStatTxLarge));
6534 LogRel(("%s: Max TX Delay : %lld\n", pThis->szPrf, pThis->uStatMaxTxDelay));
6535# endif /* E1K_INT_STATS */
6536}
6537
6538
6539/* -=-=-=-=- PDMINETWORKDOWN -=-=-=-=- */
6540
6541/**
6542 * Check if the device can receive data now.
6543 * This must be called before the pfnRecieve() method is called.
6544 *
6545 * @returns Number of bytes the device can receive.
6546 * @param pDevIns The device instance.
6547 * @param pThis The instance data.
6548 * @thread EMT
6549 */
6550static int e1kCanReceive(PPDMDEVINS pDevIns, PE1KSTATE pThis)
6551{
6552#ifndef E1K_WITH_RXD_CACHE
6553 size_t cb;
6554
6555 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6556 return VERR_NET_NO_BUFFER_SPACE;
6557
6558 if (RT_UNLIKELY(RDLEN == sizeof(E1KRXDESC)))
6559 {
6560 E1KRXDESC desc;
6561 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, RDH), &desc, sizeof(desc));
6562 if (desc.status.fDD)
6563 cb = 0;
6564 else
6565 cb = pThis->u16RxBSize;
6566 }
6567 else if (RDH < RDT)
6568 cb = (RDT - RDH) * pThis->u16RxBSize;
6569 else if (RDH > RDT)
6570 cb = (RDLEN/sizeof(E1KRXDESC) - RDH + RDT) * pThis->u16RxBSize;
6571 else
6572 {
6573 cb = 0;
6574 E1kLogRel(("E1000: OUT of RX descriptors!\n"));
6575 }
6576 E1kLog2(("%s e1kCanReceive: at exit RDH=%d RDT=%d RDLEN=%d u16RxBSize=%d cb=%lu\n",
6577 pThis->szPrf, RDH, RDT, RDLEN, pThis->u16RxBSize, cb));
6578
6579 e1kCsRxLeave(pThis);
6580 return cb > 0 ? VINF_SUCCESS : VERR_NET_NO_BUFFER_SPACE;
6581#else /* E1K_WITH_RXD_CACHE */
6582 int rc = VINF_SUCCESS;
6583
6584 if (RT_UNLIKELY(e1kCsRxEnter(pThis, VERR_SEM_BUSY) != VINF_SUCCESS))
6585 return VERR_NET_NO_BUFFER_SPACE;
6586 E1KRXDC rxdc;
6587 if (RT_UNLIKELY(!e1kUpdateRxDContext(pDevIns, pThis, &rxdc, "e1kCanReceive")))
6588 {
6589 e1kCsRxLeave(pThis);
6590 E1kLog(("%s e1kCanReceive: failed to update Rx context, returning VERR_NET_NO_BUFFER_SPACE\n", pThis->szPrf));
6591 return VERR_NET_NO_BUFFER_SPACE;
6592 }
6593
6594 if (RT_UNLIKELY(rxdc.rdlen == sizeof(E1KRXDESC)))
6595 {
6596 E1KRXDESC desc;
6597 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, rxdc.rdh), &desc, sizeof(desc));
6598 if (desc.status.fDD)
6599 rc = VERR_NET_NO_BUFFER_SPACE;
6600 }
6601 else if (e1kRxDIsCacheEmpty(pThis) && rxdc.rdh == rxdc.rdt)
6602 {
6603 /* Cache is empty, so is the RX ring. */
6604 rc = VERR_NET_NO_BUFFER_SPACE;
6605 }
6606 E1kLog2(("%s e1kCanReceive: at exit in_cache=%d RDH=%d RDT=%d RDLEN=%d"
6607 " u16RxBSize=%d rc=%Rrc\n", pThis->szPrf,
6608 e1kRxDInCache(pThis), rxdc.rdh, rxdc.rdt, rxdc.rdlen, pThis->u16RxBSize, rc));
6609
6610 e1kCsRxLeave(pThis);
6611 return rc;
6612#endif /* E1K_WITH_RXD_CACHE */
6613}
6614
6615/**
6616 * @interface_method_impl{PDMINETWORKDOWN,pfnWaitReceiveAvail}
6617 */
6618static DECLCALLBACK(int) e1kR3NetworkDown_WaitReceiveAvail(PPDMINETWORKDOWN pInterface, RTMSINTERVAL cMillies)
6619{
6620 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6621 PE1KSTATE pThis = pThisCC->pShared;
6622 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6623
6624 int rc = e1kCanReceive(pDevIns, pThis);
6625
6626 if (RT_SUCCESS(rc))
6627 return VINF_SUCCESS;
6628 if (RT_UNLIKELY(cMillies == 0))
6629 return VERR_NET_NO_BUFFER_SPACE;
6630
6631 rc = VERR_INTERRUPTED;
6632 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, true);
6633 STAM_PROFILE_START(&pThis->StatRxOverflow, a);
6634 VMSTATE enmVMState;
6635 while (RT_LIKELY( (enmVMState = PDMDevHlpVMState(pDevIns)) == VMSTATE_RUNNING
6636 || enmVMState == VMSTATE_RUNNING_LS))
6637 {
6638 int rc2 = e1kCanReceive(pDevIns, pThis);
6639 if (RT_SUCCESS(rc2))
6640 {
6641 rc = VINF_SUCCESS;
6642 break;
6643 }
6644 E1kLogRel(("E1000: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", cMillies));
6645 E1kLog(("%s: e1kR3NetworkDown_WaitReceiveAvail: waiting cMillies=%u...\n", pThis->szPrf, cMillies));
6646 PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEventMoreRxDescAvail, cMillies);
6647 }
6648 STAM_PROFILE_STOP(&pThis->StatRxOverflow, a);
6649 ASMAtomicXchgBool(&pThis->fMaybeOutOfSpace, false);
6650
6651 return rc;
6652}
6653
6654
6655/**
6656 * Matches the packet addresses against Receive Address table. Looks for
6657 * exact matches only.
6658 *
6659 * @returns true if address matches.
6660 * @param pThis Pointer to the state structure.
6661 * @param pvBuf The ethernet packet.
6662 * @param cb Number of bytes available in the packet.
6663 * @thread EMT
6664 */
6665static bool e1kPerfectMatch(PE1KSTATE pThis, const void *pvBuf)
6666{
6667 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
6668 {
6669 E1KRAELEM* ra = pThis->aRecAddr.array + i;
6670
6671 /* Valid address? */
6672 if (ra->ctl & RA_CTL_AV)
6673 {
6674 Assert((ra->ctl & RA_CTL_AS) < 2);
6675 //unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
6676 //E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
6677 // pThis->szPrf, pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
6678 // ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
6679 /*
6680 * Address Select:
6681 * 00b = Destination address
6682 * 01b = Source address
6683 * 10b = Reserved
6684 * 11b = Reserved
6685 * Since ethernet header is (DA, SA, len) we can use address
6686 * select as index.
6687 */
6688 if (memcmp((char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS),
6689 ra->addr, sizeof(ra->addr)) == 0)
6690 return true;
6691 }
6692 }
6693
6694 return false;
6695}
6696
6697/**
6698 * Matches the packet addresses against Multicast Table Array.
6699 *
6700 * @remarks This is imperfect match since it matches not exact address but
6701 * a subset of addresses.
6702 *
6703 * @returns true if address matches.
6704 * @param pThis Pointer to the state structure.
6705 * @param pvBuf The ethernet packet.
6706 * @param cb Number of bytes available in the packet.
6707 * @thread EMT
6708 */
6709static bool e1kImperfectMatch(PE1KSTATE pThis, const void *pvBuf)
6710{
6711 /* Get bits 32..47 of destination address */
6712 uint16_t u16Bit = ((uint16_t*)pvBuf)[2];
6713
6714 unsigned offset = GET_BITS(RCTL, MO);
6715 /*
6716 * offset means:
6717 * 00b = bits 36..47
6718 * 01b = bits 35..46
6719 * 10b = bits 34..45
6720 * 11b = bits 32..43
6721 */
6722 if (offset < 3)
6723 u16Bit = u16Bit >> (4 - offset);
6724 return ASMBitTest(pThis->auMTA, u16Bit & 0xFFF);
6725}
6726
6727/**
6728 * Determines if the packet is to be delivered to upper layer.
6729 *
6730 * The following filters supported:
6731 * - Exact Unicast/Multicast
6732 * - Promiscuous Unicast/Multicast
6733 * - Multicast
6734 * - VLAN
6735 *
6736 * @returns true if packet is intended for this node.
6737 * @param pThis Pointer to the state structure.
6738 * @param pvBuf The ethernet packet.
6739 * @param cb Number of bytes available in the packet.
6740 * @param pStatus Bit field to store status bits.
6741 * @thread EMT
6742 */
6743static bool e1kAddressFilter(PE1KSTATE pThis, const void *pvBuf, size_t cb, E1KRXDST *pStatus)
6744{
6745 Assert(cb > 14);
6746 /* Assume that we fail to pass exact filter. */
6747 pStatus->fPIF = false;
6748 pStatus->fVP = false;
6749 /* Discard oversized packets */
6750 if (cb > E1K_MAX_RX_PKT_SIZE)
6751 {
6752 E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
6753 pThis->szPrf, cb, E1K_MAX_RX_PKT_SIZE));
6754 E1K_INC_CNT32(ROC);
6755 return false;
6756 }
6757 else if (!(RCTL & RCTL_LPE) && cb > 1522)
6758 {
6759 /* When long packet reception is disabled packets over 1522 are discarded */
6760 E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
6761 pThis->szPrf, cb));
6762 E1K_INC_CNT32(ROC);
6763 return false;
6764 }
6765
6766 uint16_t *u16Ptr = (uint16_t*)pvBuf;
6767 /* Compare TPID with VLAN Ether Type */
6768 if (RT_BE2H_U16(u16Ptr[6]) == VET)
6769 {
6770 pStatus->fVP = true;
6771 /* Is VLAN filtering enabled? */
6772 if (RCTL & RCTL_VFE)
6773 {
6774 /* It is 802.1q packet indeed, let's filter by VID */
6775 if (RCTL & RCTL_CFIEN)
6776 {
6777 E1kLog3(("%s VLAN filter: VLAN=%d CFI=%d RCTL_CFI=%d\n", pThis->szPrf,
6778 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7])),
6779 E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])),
6780 !!(RCTL & RCTL_CFI)));
6781 if (E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])) != !!(RCTL & RCTL_CFI))
6782 {
6783 E1kLog2(("%s Packet filter: CFIs do not match in packet and RCTL (%d!=%d)\n",
6784 pThis->szPrf, E1K_SPEC_CFI(RT_BE2H_U16(u16Ptr[7])), !!(RCTL & RCTL_CFI)));
6785 return false;
6786 }
6787 }
6788 else
6789 E1kLog3(("%s VLAN filter: VLAN=%d\n", pThis->szPrf,
6790 E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6791 if (!ASMBitTest(pThis->auVFTA, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))))
6792 {
6793 E1kLog2(("%s Packet filter: no VLAN match (id=%d)\n",
6794 pThis->szPrf, E1K_SPEC_VLAN(RT_BE2H_U16(u16Ptr[7]))));
6795 return false;
6796 }
6797 }
6798 }
6799 /* Broadcast filtering */
6800 if (e1kIsBroadcast(pvBuf) && (RCTL & RCTL_BAM))
6801 return true;
6802 E1kLog2(("%s Packet filter: not a broadcast\n", pThis->szPrf));
6803 if (e1kIsMulticast(pvBuf))
6804 {
6805 /* Is multicast promiscuous enabled? */
6806 if (RCTL & RCTL_MPE)
6807 return true;
6808 E1kLog2(("%s Packet filter: no promiscuous multicast\n", pThis->szPrf));
6809 /* Try perfect matches first */
6810 if (e1kPerfectMatch(pThis, pvBuf))
6811 {
6812 pStatus->fPIF = true;
6813 return true;
6814 }
6815 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6816 if (e1kImperfectMatch(pThis, pvBuf))
6817 return true;
6818 E1kLog2(("%s Packet filter: no imperfect match\n", pThis->szPrf));
6819 }
6820 else {
6821 /* Is unicast promiscuous enabled? */
6822 if (RCTL & RCTL_UPE)
6823 return true;
6824 E1kLog2(("%s Packet filter: no promiscuous unicast\n", pThis->szPrf));
6825 if (e1kPerfectMatch(pThis, pvBuf))
6826 {
6827 pStatus->fPIF = true;
6828 return true;
6829 }
6830 E1kLog2(("%s Packet filter: no perfect match\n", pThis->szPrf));
6831 }
6832 E1kLog2(("%s Packet filter: packet discarded\n", pThis->szPrf));
6833 return false;
6834}
6835
6836/**
6837 * @interface_method_impl{PDMINETWORKDOWN,pfnReceive}
6838 */
6839static DECLCALLBACK(int) e1kR3NetworkDown_Receive(PPDMINETWORKDOWN pInterface, const void *pvBuf, size_t cb)
6840{
6841 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkDown);
6842 PE1KSTATE pThis = pThisCC->pShared;
6843 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6844 int rc = VINF_SUCCESS;
6845
6846 /*
6847 * Drop packets if the VM is not running yet/anymore.
6848 */
6849 VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);
6850 if ( enmVMState != VMSTATE_RUNNING
6851 && enmVMState != VMSTATE_RUNNING_LS)
6852 {
6853 E1kLog(("%s Dropping incoming packet as VM is not running.\n", pThis->szPrf));
6854 return VINF_SUCCESS;
6855 }
6856
6857 /* Discard incoming packets in locked state */
6858 if (!(RCTL & RCTL_EN) || pThis->fLocked || !(STATUS & STATUS_LU))
6859 {
6860 E1kLog(("%s Dropping incoming packet as receive operation is disabled.\n", pThis->szPrf));
6861 return VINF_SUCCESS;
6862 }
6863
6864 STAM_PROFILE_ADV_START(&pThis->StatReceive, a);
6865
6866 //if (!e1kCsEnter(pThis, RT_SRC_POS))
6867 // return VERR_PERMISSION_DENIED;
6868
6869 e1kPacketDump(pDevIns, pThis, (const uint8_t*)pvBuf, cb, "<-- Incoming");
6870
6871 /* Update stats */
6872 if (RT_LIKELY(e1kCsEnter(pThis, VERR_SEM_BUSY) == VINF_SUCCESS))
6873 {
6874 E1K_INC_CNT32(TPR);
6875 E1K_ADD_CNT64(TORL, TORH, cb < 64? 64 : cb);
6876 e1kCsLeave(pThis);
6877 }
6878 STAM_PROFILE_ADV_START(&pThis->StatReceiveFilter, a);
6879 E1KRXDST status;
6880 RT_ZERO(status);
6881 bool fPassed = e1kAddressFilter(pThis, pvBuf, cb, &status);
6882 STAM_PROFILE_ADV_STOP(&pThis->StatReceiveFilter, a);
6883 if (fPassed)
6884 {
6885 rc = e1kHandleRxPacket(pDevIns, pThis, pvBuf, cb, status);
6886 }
6887 //e1kCsLeave(pThis);
6888 STAM_PROFILE_ADV_STOP(&pThis->StatReceive, a);
6889
6890 return rc;
6891}
6892
6893
6894/* -=-=-=-=- PDMILEDPORTS -=-=-=-=- */
6895
6896/**
6897 * @interface_method_impl{PDMILEDPORTS,pfnQueryStatusLed}
6898 */
6899static DECLCALLBACK(int) e1kR3QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
6900{
6901 if (iLUN == 0)
6902 {
6903 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, ILeds);
6904 *ppLed = &pThisCC->pShared->led;
6905 return VINF_SUCCESS;
6906 }
6907 return VERR_PDM_LUN_NOT_FOUND;
6908}
6909
6910
6911/* -=-=-=-=- PDMINETWORKCONFIG -=-=-=-=- */
6912
6913/**
6914 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetMac}
6915 */
6916static DECLCALLBACK(int) e1kR3GetMac(PPDMINETWORKCONFIG pInterface, PRTMAC pMac)
6917{
6918 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6919 pThisCC->eeprom.getMac(pMac);
6920 return VINF_SUCCESS;
6921}
6922
6923/**
6924 * @interface_method_impl{PDMINETWORKCONFIG,pfnGetLinkState}
6925 */
6926static DECLCALLBACK(PDMNETWORKLINKSTATE) e1kR3GetLinkState(PPDMINETWORKCONFIG pInterface)
6927{
6928 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6929 PE1KSTATE pThis = pThisCC->pShared;
6930 if (STATUS & STATUS_LU)
6931 return PDMNETWORKLINKSTATE_UP;
6932 return PDMNETWORKLINKSTATE_DOWN;
6933}
6934
6935/**
6936 * @interface_method_impl{PDMINETWORKCONFIG,pfnSetLinkState}
6937 */
6938static DECLCALLBACK(int) e1kR3SetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
6939{
6940 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, INetworkConfig);
6941 PE1KSTATE pThis = pThisCC->pShared;
6942 PPDMDEVINS pDevIns = pThisCC->pDevInsR3;
6943
6944 E1kLog(("%s e1kR3SetLinkState: enmState=%d\n", pThis->szPrf, enmState));
6945 switch (enmState)
6946 {
6947 case PDMNETWORKLINKSTATE_UP:
6948 pThis->fCableConnected = true;
6949 /* If link was down, bring it up after a while. */
6950 if (!(STATUS & STATUS_LU))
6951 e1kBringLinkUpDelayed(pDevIns, pThis);
6952 break;
6953 case PDMNETWORKLINKSTATE_DOWN:
6954 pThis->fCableConnected = false;
6955 /* Always set the phy link state to down, regardless of the STATUS_LU bit.
6956 * We might have to set the link state before the driver initializes us. */
6957 Phy::setLinkStatus(&pThis->phy, false);
6958 /* If link was up, bring it down. */
6959 if (STATUS & STATUS_LU)
6960 e1kR3LinkDown(pDevIns, pThis, pThisCC);
6961 break;
6962 case PDMNETWORKLINKSTATE_DOWN_RESUME:
6963 /*
6964 * There is not much sense in bringing down the link if it has not come up yet.
6965 * If it is up though, we bring it down temporarely, then bring it up again.
6966 */
6967 if (STATUS & STATUS_LU)
6968 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
6969 break;
6970 default:
6971 ;
6972 }
6973 return VINF_SUCCESS;
6974}
6975
6976
6977/* -=-=-=-=- PDMIBASE -=-=-=-=- */
6978
6979/**
6980 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
6981 */
6982static DECLCALLBACK(void *) e1kR3QueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
6983{
6984 PE1KSTATECC pThisCC = RT_FROM_MEMBER(pInterface, E1KSTATECC, IBase);
6985 Assert(&pThisCC->IBase == pInterface);
6986
6987 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
6988 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKDOWN, &pThisCC->INetworkDown);
6989 PDMIBASE_RETURN_INTERFACE(pszIID, PDMINETWORKCONFIG, &pThisCC->INetworkConfig);
6990 PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThisCC->ILeds);
6991 return NULL;
6992}
6993
6994
6995/* -=-=-=-=- Saved State -=-=-=-=- */
6996
6997/**
6998 * Saves the configuration.
6999 *
7000 * @param pThis The E1K state.
7001 * @param pSSM The handle to the saved state.
7002 */
7003static void e1kSaveConfig(PCPDMDEVHLPR3 pHlp, PE1KSTATE pThis, PSSMHANDLE pSSM)
7004{
7005 pHlp->pfnSSMPutMem(pSSM, &pThis->macConfigured, sizeof(pThis->macConfigured));
7006 pHlp->pfnSSMPutU32(pSSM, pThis->eChip);
7007}
7008
7009/**
7010 * @callback_method_impl{FNSSMDEVLIVEEXEC,Save basic configuration.}
7011 */
7012static DECLCALLBACK(int) e1kLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
7013{
7014 RT_NOREF(uPass);
7015 e1kSaveConfig(pDevIns->pHlpR3, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE), pSSM);
7016 return VINF_SSM_DONT_CALL_AGAIN;
7017}
7018
7019/**
7020 * @callback_method_impl{FNSSMDEVSAVEPREP,Synchronize.}
7021 */
7022static DECLCALLBACK(int) e1kSavePrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7023{
7024 RT_NOREF(pSSM);
7025 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7026
7027 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
7028 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7029 return rc;
7030 e1kCsLeave(pThis);
7031 return VINF_SUCCESS;
7032#if 0
7033 /* 1) Prevent all threads from modifying the state and memory */
7034 //pThis->fLocked = true;
7035 /* 2) Cancel all timers */
7036#ifdef E1K_TX_DELAY
7037 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTXDTimer));
7038#endif /* E1K_TX_DELAY */
7039//#ifdef E1K_USE_TX_TIMERS
7040 if (pThis->fTidEnabled)
7041 {
7042 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTIDTimer));
7043#ifndef E1K_NO_TAD
7044 e1kCancelTimer(pThis, pThis->CTX_SUFF(pTADTimer));
7045#endif /* E1K_NO_TAD */
7046 }
7047//#endif /* E1K_USE_TX_TIMERS */
7048#ifdef E1K_USE_RX_TIMERS
7049 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRIDTimer));
7050 e1kCancelTimer(pThis, pThis->CTX_SUFF(pRADTimer));
7051#endif /* E1K_USE_RX_TIMERS */
7052 e1kCancelTimer(pThis, pThis->CTX_SUFF(pIntTimer));
7053 /* 3) Did I forget anything? */
7054 E1kLog(("%s Locked\n", pThis->szPrf));
7055 return VINF_SUCCESS;
7056#endif
7057}
7058
7059/**
7060 * @callback_method_impl{FNSSMDEVSAVEEXEC}
7061 */
7062static DECLCALLBACK(int) e1kSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7063{
7064 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7065 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7066 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7067
7068 e1kSaveConfig(pHlp, pThis, pSSM);
7069 pThisCC->eeprom.save(pHlp, pSSM);
7070 e1kDumpState(pThis);
7071 pHlp->pfnSSMPutMem(pSSM, pThis->auRegs, sizeof(pThis->auRegs));
7072 pHlp->pfnSSMPutBool(pSSM, pThis->fIntRaised);
7073 Phy::saveState(pHlp, pSSM, &pThis->phy);
7074 pHlp->pfnSSMPutU32(pSSM, pThis->uSelectedReg);
7075 pHlp->pfnSSMPutMem(pSSM, pThis->auMTA, sizeof(pThis->auMTA));
7076 pHlp->pfnSSMPutMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7077 pHlp->pfnSSMPutMem(pSSM, pThis->auVFTA, sizeof(pThis->auVFTA));
7078 pHlp->pfnSSMPutU64(pSSM, pThis->u64AckedAt);
7079 pHlp->pfnSSMPutU16(pSSM, pThis->u16RxBSize);
7080 //pHlp->pfnSSMPutBool(pSSM, pThis->fDelayInts);
7081 //pHlp->pfnSSMPutBool(pSSM, pThis->fIntMaskUsed);
7082 pHlp->pfnSSMPutU16(pSSM, pThis->u16TxPktLen);
7083/** @todo State wrt to the TSE buffer is incomplete, so little point in
7084 * saving this actually. */
7085 pHlp->pfnSSMPutMem(pSSM, pThis->aTxPacketFallback, pThis->u16TxPktLen);
7086 pHlp->pfnSSMPutBool(pSSM, pThis->fIPcsum);
7087 pHlp->pfnSSMPutBool(pSSM, pThis->fTCPcsum);
7088 pHlp->pfnSSMPutMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7089 pHlp->pfnSSMPutMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7090 pHlp->pfnSSMPutBool(pSSM, pThis->fVTag);
7091 pHlp->pfnSSMPutU16(pSSM, pThis->u16VTagTCI);
7092#ifdef E1K_WITH_TXD_CACHE
7093# if 0
7094 pHlp->pfnSSMPutU8(pSSM, pThis->nTxDFetched);
7095 pHlp->pfnSSMPutMem(pSSM, pThis->aTxDescriptors,
7096 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7097# else
7098 /*
7099 * There is no point in storing TX descriptor cache entries as we can simply
7100 * fetch them again. Moreover, normally the cache is always empty when we
7101 * save the state. Store zero entries for compatibility.
7102 */
7103 pHlp->pfnSSMPutU8(pSSM, 0);
7104# endif
7105#endif /* E1K_WITH_TXD_CACHE */
7106/** @todo GSO requires some more state here. */
7107 E1kLog(("%s State has been saved\n", pThis->szPrf));
7108 return VINF_SUCCESS;
7109}
7110
7111#if 0
7112/**
7113 * @callback_method_impl{FNSSMDEVSAVEDONE}
7114 */
7115static DECLCALLBACK(int) e1kSaveDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7116{
7117 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7118
7119 /* If VM is being powered off unlocking will result in assertions in PGM */
7120 if (PDMDevHlpGetVM(pDevIns)->enmVMState == VMSTATE_RUNNING)
7121 pThis->fLocked = false;
7122 else
7123 E1kLog(("%s VM is not running -- remain locked\n", pThis->szPrf));
7124 E1kLog(("%s Unlocked\n", pThis->szPrf));
7125 return VINF_SUCCESS;
7126}
7127#endif
7128
7129/**
7130 * @callback_method_impl{FNSSMDEVLOADPREP,Synchronize.}
7131 */
7132static DECLCALLBACK(int) e1kLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7133{
7134 RT_NOREF(pSSM);
7135 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7136
7137 int rc = e1kCsEnter(pThis, VERR_SEM_BUSY);
7138 if (RT_UNLIKELY(rc != VINF_SUCCESS))
7139 return rc;
7140 e1kCsLeave(pThis);
7141 return VINF_SUCCESS;
7142}
7143
7144/**
7145 * @callback_method_impl{FNSSMDEVLOADEXEC}
7146 */
7147static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
7148{
7149 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7150 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7151 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7152 int rc;
7153
7154 if ( uVersion != E1K_SAVEDSTATE_VERSION
7155#ifdef E1K_WITH_TXD_CACHE
7156 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG
7157#endif /* E1K_WITH_TXD_CACHE */
7158 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_41
7159 && uVersion != E1K_SAVEDSTATE_VERSION_VBOX_30)
7160 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
7161
7162 if ( uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30
7163 || uPass != SSM_PASS_FINAL)
7164 {
7165 /* config checks */
7166 RTMAC macConfigured;
7167 rc = pHlp->pfnSSMGetMem(pSSM, &macConfigured, sizeof(macConfigured));
7168 AssertRCReturn(rc, rc);
7169 if ( memcmp(&macConfigured, &pThis->macConfigured, sizeof(macConfigured))
7170 && (uPass == 0 || !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)) )
7171 LogRel(("%s: The mac address differs: config=%RTmac saved=%RTmac\n", pThis->szPrf, &pThis->macConfigured, &macConfigured));
7172
7173 E1KCHIP eChip;
7174 rc = pHlp->pfnSSMGetU32(pSSM, &eChip);
7175 AssertRCReturn(rc, rc);
7176 if (eChip != pThis->eChip)
7177 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("The chip type differs: config=%u saved=%u"), pThis->eChip, eChip);
7178 }
7179
7180 if (uPass == SSM_PASS_FINAL)
7181 {
7182 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_30)
7183 {
7184 rc = pThisCC->eeprom.load(pHlp, pSSM);
7185 AssertRCReturn(rc, rc);
7186 }
7187 /* the state */
7188 pHlp->pfnSSMGetMem(pSSM, &pThis->auRegs, sizeof(pThis->auRegs));
7189 pHlp->pfnSSMGetBool(pSSM, &pThis->fIntRaised);
7190 /** @todo PHY could be made a separate device with its own versioning */
7191 Phy::loadState(pHlp, pSSM, &pThis->phy);
7192 pHlp->pfnSSMGetU32(pSSM, &pThis->uSelectedReg);
7193 pHlp->pfnSSMGetMem(pSSM, &pThis->auMTA, sizeof(pThis->auMTA));
7194 pHlp->pfnSSMGetMem(pSSM, &pThis->aRecAddr, sizeof(pThis->aRecAddr));
7195 pHlp->pfnSSMGetMem(pSSM, &pThis->auVFTA, sizeof(pThis->auVFTA));
7196 pHlp->pfnSSMGetU64(pSSM, &pThis->u64AckedAt);
7197 pHlp->pfnSSMGetU16(pSSM, &pThis->u16RxBSize);
7198 //pHlp->pfnSSMGetBool(pSSM, pThis->fDelayInts);
7199 //pHlp->pfnSSMGetBool(pSSM, pThis->fIntMaskUsed);
7200 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16TxPktLen);
7201 AssertRCReturn(rc, rc);
7202 if (pThis->u16TxPktLen > sizeof(pThis->aTxPacketFallback))
7203 pThis->u16TxPktLen = sizeof(pThis->aTxPacketFallback);
7204 pHlp->pfnSSMGetMem(pSSM, &pThis->aTxPacketFallback[0], pThis->u16TxPktLen);
7205 pHlp->pfnSSMGetBool(pSSM, &pThis->fIPcsum);
7206 pHlp->pfnSSMGetBool(pSSM, &pThis->fTCPcsum);
7207 pHlp->pfnSSMGetMem(pSSM, &pThis->contextTSE, sizeof(pThis->contextTSE));
7208 rc = pHlp->pfnSSMGetMem(pSSM, &pThis->contextNormal, sizeof(pThis->contextNormal));
7209 AssertRCReturn(rc, rc);
7210 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_41)
7211 {
7212 pHlp->pfnSSMGetBool(pSSM, &pThis->fVTag);
7213 rc = pHlp->pfnSSMGetU16(pSSM, &pThis->u16VTagTCI);
7214 AssertRCReturn(rc, rc);
7215 }
7216 else
7217 {
7218 pThis->fVTag = false;
7219 pThis->u16VTagTCI = 0;
7220 }
7221#ifdef E1K_WITH_TXD_CACHE
7222 if (uVersion > E1K_SAVEDSTATE_VERSION_VBOX_42_VTAG)
7223 {
7224 rc = pHlp->pfnSSMGetU8(pSSM, &pThis->nTxDFetched);
7225 AssertRCReturn(rc, rc);
7226 if (pThis->nTxDFetched)
7227 pHlp->pfnSSMGetMem(pSSM, pThis->aTxDescriptors,
7228 pThis->nTxDFetched * sizeof(pThis->aTxDescriptors[0]));
7229 }
7230 else
7231 pThis->nTxDFetched = 0;
7232 /**
7233 * @todo Perhaps we should not store TXD cache as the entries can be
7234 * simply fetched again from guest's memory. Or can't they?
7235 */
7236#endif /* E1K_WITH_TXD_CACHE */
7237#ifdef E1K_WITH_RXD_CACHE
7238 /*
7239 * There is no point in storing the RX descriptor cache in the saved
7240 * state, we just need to make sure it is empty.
7241 */
7242 pThis->iRxDCurrent = pThis->nRxDFetched = 0;
7243#endif /* E1K_WITH_RXD_CACHE */
7244 rc = pHlp->pfnSSMHandleGetStatus(pSSM);
7245 AssertRCReturn(rc, rc);
7246
7247 /* derived state */
7248 e1kSetupGsoCtx(&pThis->GsoCtx, &pThis->contextTSE);
7249
7250 E1kLog(("%s State has been restored\n", pThis->szPrf));
7251 e1kDumpState(pThis);
7252 }
7253 return VINF_SUCCESS;
7254}
7255
7256/**
7257 * @callback_method_impl{FNSSMDEVLOADDONE, Link status adjustments after loading.}
7258 */
7259static DECLCALLBACK(int) e1kLoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
7260{
7261 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7262 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7263 RT_NOREF(pSSM);
7264
7265 /* Update promiscuous mode */
7266 if (pThisCC->pDrvR3)
7267 pThisCC->pDrvR3->pfnSetPromiscuousMode(pThisCC->pDrvR3, !!(RCTL & (RCTL_UPE | RCTL_MPE)));
7268
7269 /*
7270 * Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
7271 * passed to us. We go through all this stuff if the link was up and we
7272 * wasn't teleported.
7273 */
7274 if ( (STATUS & STATUS_LU)
7275 && !PDMDevHlpVMTeleportedAndNotFullyResumedYet(pDevIns)
7276 && pThis->cMsLinkUpDelay)
7277 {
7278 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7279 }
7280 return VINF_SUCCESS;
7281}
7282
7283
7284
7285/* -=-=-=-=- Debug Info + Log Types -=-=-=-=- */
7286
7287/**
7288 * @callback_method_impl{FNRTSTRFORMATTYPE}
7289 */
7290static DECLCALLBACK(size_t) e1kFmtRxDesc(PFNRTSTROUTPUT pfnOutput,
7291 void *pvArgOutput,
7292 const char *pszType,
7293 void const *pvValue,
7294 int cchWidth,
7295 int cchPrecision,
7296 unsigned fFlags,
7297 void *pvUser)
7298{
7299 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7300 AssertReturn(strcmp(pszType, "e1krxd") == 0, 0);
7301 E1KRXDESC* pDesc = (E1KRXDESC*)pvValue;
7302 if (!pDesc)
7303 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_RXD");
7304
7305 size_t cbPrintf = 0;
7306 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Address=%16LX Length=%04X Csum=%04X\n",
7307 pDesc->u64BufAddr, pDesc->u16Length, pDesc->u16Checksum);
7308 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, " STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x",
7309 pDesc->status.fPIF ? "PIF" : "pif",
7310 pDesc->status.fIPCS ? "IPCS" : "ipcs",
7311 pDesc->status.fTCPCS ? "TCPCS" : "tcpcs",
7312 pDesc->status.fVP ? "VP" : "vp",
7313 pDesc->status.fIXSM ? "IXSM" : "ixsm",
7314 pDesc->status.fEOP ? "EOP" : "eop",
7315 pDesc->status.fDD ? "DD" : "dd",
7316 pDesc->status.fRXE ? "RXE" : "rxe",
7317 pDesc->status.fIPE ? "IPE" : "ipe",
7318 pDesc->status.fTCPE ? "TCPE" : "tcpe",
7319 pDesc->status.fCE ? "CE" : "ce",
7320 E1K_SPEC_CFI(pDesc->status.u16Special) ? "CFI" :"cfi",
7321 E1K_SPEC_VLAN(pDesc->status.u16Special),
7322 E1K_SPEC_PRI(pDesc->status.u16Special));
7323 return cbPrintf;
7324}
7325
7326/**
7327 * @callback_method_impl{FNRTSTRFORMATTYPE}
7328 */
7329static DECLCALLBACK(size_t) e1kFmtTxDesc(PFNRTSTROUTPUT pfnOutput,
7330 void *pvArgOutput,
7331 const char *pszType,
7332 void const *pvValue,
7333 int cchWidth,
7334 int cchPrecision,
7335 unsigned fFlags,
7336 void *pvUser)
7337{
7338 RT_NOREF(cchWidth, cchPrecision, fFlags, pvUser);
7339 AssertReturn(strcmp(pszType, "e1ktxd") == 0, 0);
7340 E1KTXDESC *pDesc = (E1KTXDESC*)pvValue;
7341 if (!pDesc)
7342 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "NULL_TXD");
7343
7344 size_t cbPrintf = 0;
7345 switch (e1kGetDescType(pDesc))
7346 {
7347 case E1K_DTYP_CONTEXT:
7348 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Context\n"
7349 " IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n"
7350 " TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s",
7351 pDesc->context.ip.u8CSS, pDesc->context.ip.u8CSO, pDesc->context.ip.u16CSE,
7352 pDesc->context.tu.u8CSS, pDesc->context.tu.u8CSO, pDesc->context.tu.u16CSE,
7353 pDesc->context.dw2.fIDE ? " IDE":"",
7354 pDesc->context.dw2.fRS ? " RS" :"",
7355 pDesc->context.dw2.fTSE ? " TSE":"",
7356 pDesc->context.dw2.fIP ? "IPv4":"IPv6",
7357 pDesc->context.dw2.fTCP ? "TCP":"UDP",
7358 pDesc->context.dw2.u20PAYLEN,
7359 pDesc->context.dw3.u8HDRLEN,
7360 pDesc->context.dw3.u16MSS,
7361 pDesc->context.dw3.fDD?"DD":"");
7362 break;
7363 case E1K_DTYP_DATA:
7364 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Data Address=%16LX DTALEN=%05X\n"
7365 " DCMD:%s%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x",
7366 pDesc->data.u64BufAddr,
7367 pDesc->data.cmd.u20DTALEN,
7368 pDesc->data.cmd.fIDE ? " IDE" :"",
7369 pDesc->data.cmd.fVLE ? " VLE" :"",
7370 pDesc->data.cmd.fRPS ? " RPS" :"",
7371 pDesc->data.cmd.fRS ? " RS" :"",
7372 pDesc->data.cmd.fTSE ? " TSE" :"",
7373 pDesc->data.cmd.fIFCS? " IFCS":"",
7374 pDesc->data.cmd.fEOP ? " EOP" :"",
7375 pDesc->data.dw3.fDD ? " DD" :"",
7376 pDesc->data.dw3.fEC ? " EC" :"",
7377 pDesc->data.dw3.fLC ? " LC" :"",
7378 pDesc->data.dw3.fTXSM? " TXSM":"",
7379 pDesc->data.dw3.fIXSM? " IXSM":"",
7380 E1K_SPEC_CFI(pDesc->data.dw3.u16Special) ? "CFI" :"cfi",
7381 E1K_SPEC_VLAN(pDesc->data.dw3.u16Special),
7382 E1K_SPEC_PRI(pDesc->data.dw3.u16Special));
7383 break;
7384 case E1K_DTYP_LEGACY:
7385 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Type=Legacy Address=%16LX DTALEN=%05X\n"
7386 " CMD:%s%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x",
7387 pDesc->data.u64BufAddr,
7388 pDesc->legacy.cmd.u16Length,
7389 pDesc->legacy.cmd.fIDE ? " IDE" :"",
7390 pDesc->legacy.cmd.fVLE ? " VLE" :"",
7391 pDesc->legacy.cmd.fRPS ? " RPS" :"",
7392 pDesc->legacy.cmd.fRS ? " RS" :"",
7393 pDesc->legacy.cmd.fIC ? " IC" :"",
7394 pDesc->legacy.cmd.fIFCS? " IFCS":"",
7395 pDesc->legacy.cmd.fEOP ? " EOP" :"",
7396 pDesc->legacy.dw3.fDD ? " DD" :"",
7397 pDesc->legacy.dw3.fEC ? " EC" :"",
7398 pDesc->legacy.dw3.fLC ? " LC" :"",
7399 pDesc->legacy.cmd.u8CSO,
7400 pDesc->legacy.dw3.u8CSS,
7401 E1K_SPEC_CFI(pDesc->legacy.dw3.u16Special) ? "CFI" :"cfi",
7402 E1K_SPEC_VLAN(pDesc->legacy.dw3.u16Special),
7403 E1K_SPEC_PRI(pDesc->legacy.dw3.u16Special));
7404 break;
7405 default:
7406 cbPrintf += RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "Invalid Transmit Descriptor");
7407 break;
7408 }
7409
7410 return cbPrintf;
7411}
7412
7413/** Initializes debug helpers (logging format types). */
7414static int e1kInitDebugHelpers(void)
7415{
7416 int rc = VINF_SUCCESS;
7417 static bool s_fHelpersRegistered = false;
7418 if (!s_fHelpersRegistered)
7419 {
7420 s_fHelpersRegistered = true;
7421 rc = RTStrFormatTypeRegister("e1krxd", e1kFmtRxDesc, NULL);
7422 AssertRCReturn(rc, rc);
7423 rc = RTStrFormatTypeRegister("e1ktxd", e1kFmtTxDesc, NULL);
7424 AssertRCReturn(rc, rc);
7425 }
7426 return rc;
7427}
7428
7429/**
7430 * Status info callback.
7431 *
7432 * @param pDevIns The device instance.
7433 * @param pHlp The output helpers.
7434 * @param pszArgs The arguments.
7435 */
7436static DECLCALLBACK(void) e1kInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
7437{
7438 RT_NOREF(pszArgs);
7439 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7440 unsigned i;
7441 // bool fRcvRing = false;
7442 // bool fXmtRing = false;
7443
7444 /*
7445 * Parse args.
7446 if (pszArgs)
7447 {
7448 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv");
7449 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt");
7450 }
7451 */
7452
7453 /*
7454 * Show info.
7455 */
7456 pHlp->pfnPrintf(pHlp, "E1000 #%d: port=%04x mmio=%RGp mac-cfg=%RTmac %s%s%s\n",
7457 pDevIns->iInstance,
7458 PDMDevHlpIoPortGetMappingAddress(pDevIns, pThis->hIoPorts),
7459 PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmioRegion),
7460 &pThis->macConfigured, g_aChips[pThis->eChip].pcszName,
7461 pDevIns->fRCEnabled ? " RC" : "", pDevIns->fR0Enabled ? " R0" : "");
7462
7463 e1kCsEnter(pThis, VERR_INTERNAL_ERROR); /* Not sure why but PCNet does it */
7464
7465 for (i = 0; i < E1K_NUM_OF_32BIT_REGS; ++i)
7466 pHlp->pfnPrintf(pHlp, "%8.8s = %08x\n", g_aE1kRegMap[i].abbrev, pThis->auRegs[i]);
7467
7468 for (i = 0; i < RT_ELEMENTS(pThis->aRecAddr.array); i++)
7469 {
7470 E1KRAELEM* ra = pThis->aRecAddr.array + i;
7471 if (ra->ctl & RA_CTL_AV)
7472 {
7473 const char *pcszTmp;
7474 switch (ra->ctl & RA_CTL_AS)
7475 {
7476 case 0: pcszTmp = "DST"; break;
7477 case 1: pcszTmp = "SRC"; break;
7478 default: pcszTmp = "reserved";
7479 }
7480 pHlp->pfnPrintf(pHlp, "RA%02d: %s %RTmac\n", i, pcszTmp, ra->addr);
7481 }
7482 }
7483 unsigned cDescs = RDLEN / sizeof(E1KRXDESC);
7484 uint32_t rdh = RDH;
7485 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors (%d total) --\n", cDescs);
7486 for (i = 0; i < cDescs; ++i)
7487 {
7488 E1KRXDESC desc;
7489 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(RDBAH, RDBAL, i),
7490 &desc, sizeof(desc));
7491 if (i == rdh)
7492 pHlp->pfnPrintf(pHlp, ">>> ");
7493 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n", e1kDescAddr(RDBAH, RDBAL, i), &desc);
7494 }
7495#ifdef E1K_WITH_RXD_CACHE
7496 pHlp->pfnPrintf(pHlp, "\n-- Receive Descriptors in Cache (at %d (RDH %d)/ fetched %d / max %d) --\n",
7497 pThis->iRxDCurrent, RDH, pThis->nRxDFetched, E1K_RXD_CACHE_SIZE);
7498 if (rdh > pThis->iRxDCurrent)
7499 rdh -= pThis->iRxDCurrent;
7500 else
7501 rdh = cDescs + rdh - pThis->iRxDCurrent;
7502 for (i = 0; i < pThis->nRxDFetched; ++i)
7503 {
7504 if (i == pThis->iRxDCurrent)
7505 pHlp->pfnPrintf(pHlp, ">>> ");
7506 if (cDescs)
7507 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1krxd]\n",
7508 e1kDescAddr(RDBAH, RDBAL, rdh++ % cDescs),
7509 &pThis->aRxDescriptors[i]);
7510 else
7511 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1krxd]\n",
7512 &pThis->aRxDescriptors[i]);
7513 }
7514#endif /* E1K_WITH_RXD_CACHE */
7515
7516 cDescs = TDLEN / sizeof(E1KTXDESC);
7517 uint32_t tdh = TDH;
7518 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors (%d total) --\n", cDescs);
7519 for (i = 0; i < cDescs; ++i)
7520 {
7521 E1KTXDESC desc;
7522 PDMDevHlpPCIPhysRead(pDevIns, e1kDescAddr(TDBAH, TDBAL, i),
7523 &desc, sizeof(desc));
7524 if (i == tdh)
7525 pHlp->pfnPrintf(pHlp, ">>> ");
7526 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n", e1kDescAddr(TDBAH, TDBAL, i), &desc);
7527 }
7528#ifdef E1K_WITH_TXD_CACHE
7529 pHlp->pfnPrintf(pHlp, "\n-- Transmit Descriptors in Cache (at %d (TDH %d)/ fetched %d / max %d) --\n",
7530 pThis->iTxDCurrent, TDH, pThis->nTxDFetched, E1K_TXD_CACHE_SIZE);
7531 if (tdh > pThis->iTxDCurrent)
7532 tdh -= pThis->iTxDCurrent;
7533 else
7534 tdh = cDescs + tdh - pThis->iTxDCurrent;
7535 for (i = 0; i < pThis->nTxDFetched; ++i)
7536 {
7537 if (i == pThis->iTxDCurrent)
7538 pHlp->pfnPrintf(pHlp, ">>> ");
7539 if (cDescs)
7540 pHlp->pfnPrintf(pHlp, "%RGp: %R[e1ktxd]\n",
7541 e1kDescAddr(TDBAH, TDBAL, tdh++ % cDescs),
7542 &pThis->aTxDescriptors[i]);
7543 else
7544 pHlp->pfnPrintf(pHlp, "<lost>: %R[e1ktxd]\n",
7545 &pThis->aTxDescriptors[i]);
7546 }
7547#endif /* E1K_WITH_TXD_CACHE */
7548
7549
7550#ifdef E1K_INT_STATS
7551 pHlp->pfnPrintf(pHlp, "Interrupt attempts: %d\n", pThis->uStatIntTry);
7552 pHlp->pfnPrintf(pHlp, "Interrupts raised : %d\n", pThis->uStatInt);
7553 pHlp->pfnPrintf(pHlp, "Interrupts lowered: %d\n", pThis->uStatIntLower);
7554 pHlp->pfnPrintf(pHlp, "ICR outside ISR : %d\n", pThis->uStatNoIntICR);
7555 pHlp->pfnPrintf(pHlp, "IMS raised ints : %d\n", pThis->uStatIntIMS);
7556 pHlp->pfnPrintf(pHlp, "Interrupts skipped: %d\n", pThis->uStatIntSkip);
7557 pHlp->pfnPrintf(pHlp, "Masked interrupts : %d\n", pThis->uStatIntMasked);
7558 pHlp->pfnPrintf(pHlp, "Early interrupts : %d\n", pThis->uStatIntEarly);
7559 pHlp->pfnPrintf(pHlp, "Late interrupts : %d\n", pThis->uStatIntLate);
7560 pHlp->pfnPrintf(pHlp, "Lost interrupts : %d\n", pThis->iStatIntLost);
7561 pHlp->pfnPrintf(pHlp, "Interrupts by RX : %d\n", pThis->uStatIntRx);
7562 pHlp->pfnPrintf(pHlp, "Interrupts by TX : %d\n", pThis->uStatIntTx);
7563 pHlp->pfnPrintf(pHlp, "Interrupts by ICS : %d\n", pThis->uStatIntICS);
7564 pHlp->pfnPrintf(pHlp, "Interrupts by RDTR: %d\n", pThis->uStatIntRDTR);
7565 pHlp->pfnPrintf(pHlp, "Interrupts by RDMT: %d\n", pThis->uStatIntRXDMT0);
7566 pHlp->pfnPrintf(pHlp, "Interrupts by TXQE: %d\n", pThis->uStatIntTXQE);
7567 pHlp->pfnPrintf(pHlp, "TX int delay asked: %d\n", pThis->uStatTxIDE);
7568 pHlp->pfnPrintf(pHlp, "TX delayed: %d\n", pThis->uStatTxDelayed);
7569 pHlp->pfnPrintf(pHlp, "TX delayed expired: %d\n", pThis->uStatTxDelayExp);
7570 pHlp->pfnPrintf(pHlp, "TX no report asked: %d\n", pThis->uStatTxNoRS);
7571 pHlp->pfnPrintf(pHlp, "TX abs timer expd : %d\n", pThis->uStatTAD);
7572 pHlp->pfnPrintf(pHlp, "TX int timer expd : %d\n", pThis->uStatTID);
7573 pHlp->pfnPrintf(pHlp, "RX abs timer expd : %d\n", pThis->uStatRAD);
7574 pHlp->pfnPrintf(pHlp, "RX int timer expd : %d\n", pThis->uStatRID);
7575 pHlp->pfnPrintf(pHlp, "TX CTX descriptors: %d\n", pThis->uStatDescCtx);
7576 pHlp->pfnPrintf(pHlp, "TX DAT descriptors: %d\n", pThis->uStatDescDat);
7577 pHlp->pfnPrintf(pHlp, "TX LEG descriptors: %d\n", pThis->uStatDescLeg);
7578 pHlp->pfnPrintf(pHlp, "Received frames : %d\n", pThis->uStatRxFrm);
7579 pHlp->pfnPrintf(pHlp, "Transmitted frames: %d\n", pThis->uStatTxFrm);
7580 pHlp->pfnPrintf(pHlp, "TX frames up to 1514: %d\n", pThis->uStatTx1514);
7581 pHlp->pfnPrintf(pHlp, "TX frames up to 2962: %d\n", pThis->uStatTx2962);
7582 pHlp->pfnPrintf(pHlp, "TX frames up to 4410: %d\n", pThis->uStatTx4410);
7583 pHlp->pfnPrintf(pHlp, "TX frames up to 5858: %d\n", pThis->uStatTx5858);
7584 pHlp->pfnPrintf(pHlp, "TX frames up to 7306: %d\n", pThis->uStatTx7306);
7585 pHlp->pfnPrintf(pHlp, "TX frames up to 8754: %d\n", pThis->uStatTx8754);
7586 pHlp->pfnPrintf(pHlp, "TX frames up to 16384: %d\n", pThis->uStatTx16384);
7587 pHlp->pfnPrintf(pHlp, "TX frames up to 32768: %d\n", pThis->uStatTx32768);
7588 pHlp->pfnPrintf(pHlp, "Larger TX frames : %d\n", pThis->uStatTxLarge);
7589#endif /* E1K_INT_STATS */
7590
7591 e1kCsLeave(pThis);
7592}
7593
7594
7595
7596/* -=-=-=-=- PDMDEVREG -=-=-=-=- */
7597
7598/**
7599 * Detach notification.
7600 *
7601 * One port on the network card has been disconnected from the network.
7602 *
7603 * @param pDevIns The device instance.
7604 * @param iLUN The logical unit which is being detached.
7605 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7606 */
7607static DECLCALLBACK(void) e1kR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7608{
7609 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7610 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7611 Log(("%s e1kR3Detach:\n", pThis->szPrf));
7612 RT_NOREF(fFlags);
7613
7614 AssertLogRelReturnVoid(iLUN == 0);
7615
7616 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7617
7618 /** @todo r=pritesh still need to check if i missed
7619 * to clean something in this function
7620 */
7621
7622 /*
7623 * Zero some important members.
7624 */
7625 pThisCC->pDrvBase = NULL;
7626 pThisCC->pDrvR3 = NULL;
7627#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7628 pThisR0->pDrvR0 = NIL_RTR0PTR;
7629 pThisRC->pDrvRC = NIL_RTRCPTR;
7630#endif
7631
7632 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7633}
7634
7635/**
7636 * Attach the Network attachment.
7637 *
7638 * One port on the network card has been connected to a network.
7639 *
7640 * @returns VBox status code.
7641 * @param pDevIns The device instance.
7642 * @param iLUN The logical unit which is being attached.
7643 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
7644 *
7645 * @remarks This code path is not used during construction.
7646 */
7647static DECLCALLBACK(int) e1kR3Attach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
7648{
7649 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7650 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7651 LogFlow(("%s e1kR3Attach:\n", pThis->szPrf));
7652 RT_NOREF(fFlags);
7653
7654 AssertLogRelReturn(iLUN == 0, VERR_PDM_NO_SUCH_LUN);
7655
7656 PDMDevHlpCritSectEnter(pDevIns, &pThis->cs, VERR_SEM_BUSY);
7657
7658 /*
7659 * Attach the driver.
7660 */
7661 int rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
7662 if (RT_SUCCESS(rc))
7663 {
7664 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
7665 AssertMsgStmt(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"),
7666 rc = VERR_PDM_MISSING_INTERFACE_BELOW);
7667 if (RT_SUCCESS(rc))
7668 {
7669#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
7670 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
7671 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
7672#endif
7673 }
7674 }
7675 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
7676 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
7677 {
7678 /* This should never happen because this function is not called
7679 * if there is no driver to attach! */
7680 Log(("%s No attached driver!\n", pThis->szPrf));
7681 }
7682
7683 /*
7684 * Temporary set the link down if it was up so that the guest will know
7685 * that we have change the configuration of the network card
7686 */
7687 if ((STATUS & STATUS_LU) && RT_SUCCESS(rc))
7688 e1kR3LinkDownTemp(pDevIns, pThis, pThisCC);
7689
7690 PDMDevHlpCritSectLeave(pDevIns, &pThis->cs);
7691 return rc;
7692}
7693
7694/**
7695 * @copydoc FNPDMDEVPOWEROFF
7696 */
7697static DECLCALLBACK(void) e1kR3PowerOff(PPDMDEVINS pDevIns)
7698{
7699 /* Poke thread waiting for buffer space. */
7700 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7701}
7702
7703/**
7704 * @copydoc FNPDMDEVRESET
7705 */
7706static DECLCALLBACK(void) e1kR3Reset(PPDMDEVINS pDevIns)
7707{
7708 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7709 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7710#ifdef E1K_TX_DELAY
7711 e1kCancelTimer(pDevIns, pThis, pThis->hTXDTimer);
7712#endif /* E1K_TX_DELAY */
7713 e1kCancelTimer(pDevIns, pThis, pThis->hIntTimer);
7714 e1kCancelTimer(pDevIns, pThis, pThis->hLUTimer);
7715 e1kXmitFreeBuf(pThis, pThisCC);
7716 pThis->u16TxPktLen = 0;
7717 pThis->fIPcsum = false;
7718 pThis->fTCPcsum = false;
7719 pThis->fIntMaskUsed = false;
7720 pThis->fDelayInts = false;
7721 pThis->fLocked = false;
7722 pThis->u64AckedAt = 0;
7723 e1kR3HardReset(pDevIns, pThis, pThisCC);
7724}
7725
7726/**
7727 * @copydoc FNPDMDEVSUSPEND
7728 */
7729static DECLCALLBACK(void) e1kR3Suspend(PPDMDEVINS pDevIns)
7730{
7731 /* Poke thread waiting for buffer space. */
7732 e1kWakeupReceive(pDevIns, PDMDEVINS_2_DATA(pDevIns, PE1KSTATE));
7733}
7734
7735/**
7736 * Device relocation callback.
7737 *
7738 * When this callback is called the device instance data, and if the
7739 * device have a GC component, is being relocated, or/and the selectors
7740 * have been changed. The device must use the chance to perform the
7741 * necessary pointer relocations and data updates.
7742 *
7743 * Before the GC code is executed the first time, this function will be
7744 * called with a 0 delta so GC pointer calculations can be one in one place.
7745 *
7746 * @param pDevIns Pointer to the device instance.
7747 * @param offDelta The relocation delta relative to the old location.
7748 *
7749 * @remark A relocation CANNOT fail.
7750 */
7751static DECLCALLBACK(void) e1kR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
7752{
7753 PE1KSTATERC pThisRC = PDMINS_2_DATA_RC(pDevIns, PE1KSTATERC);
7754 if (pThisRC)
7755 pThisRC->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
7756 RT_NOREF(offDelta);
7757}
7758
7759/**
7760 * Destruct a device instance.
7761 *
7762 * We need to free non-VM resources only.
7763 *
7764 * @returns VBox status code.
7765 * @param pDevIns The device instance data.
7766 * @thread EMT
7767 */
7768static DECLCALLBACK(int) e1kR3Destruct(PPDMDEVINS pDevIns)
7769{
7770 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
7771 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7772
7773 e1kDumpState(pThis);
7774 E1kLog(("%s Destroying instance\n", pThis->szPrf));
7775 if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->cs))
7776 {
7777 if (pThis->hEventMoreRxDescAvail != NIL_SUPSEMEVENT)
7778 {
7779 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEventMoreRxDescAvail);
7780 RTThreadYield();
7781 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEventMoreRxDescAvail);
7782 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7783 }
7784#ifdef E1K_WITH_TX_CS
7785 PDMDevHlpCritSectDelete(pDevIns, &pThis->csTx);
7786#endif /* E1K_WITH_TX_CS */
7787 PDMDevHlpCritSectDelete(pDevIns, &pThis->csRx);
7788 PDMDevHlpCritSectDelete(pDevIns, &pThis->cs);
7789 }
7790 return VINF_SUCCESS;
7791}
7792
7793
7794/**
7795 * Set PCI configuration space registers.
7796 *
7797 * @param pci Reference to PCI device structure.
7798 * @thread EMT
7799 */
7800static void e1kR3ConfigurePciDev(PPDMPCIDEV pPciDev, E1KCHIP eChip)
7801{
7802 Assert(eChip < RT_ELEMENTS(g_aChips));
7803 /* Configure PCI Device, assume 32-bit mode ******************************/
7804 PDMPciDevSetVendorId(pPciDev, g_aChips[eChip].uPCIVendorId);
7805 PDMPciDevSetDeviceId(pPciDev, g_aChips[eChip].uPCIDeviceId);
7806 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID, g_aChips[eChip].uPCISubsystemVendorId);
7807 PDMPciDevSetWord( pPciDev, VBOX_PCI_SUBSYSTEM_ID, g_aChips[eChip].uPCISubsystemId);
7808
7809 PDMPciDevSetWord( pPciDev, VBOX_PCI_COMMAND, 0x0000);
7810 /* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
7811 PDMPciDevSetWord( pPciDev, VBOX_PCI_STATUS,
7812 VBOX_PCI_STATUS_DEVSEL_MEDIUM | VBOX_PCI_STATUS_CAP_LIST | VBOX_PCI_STATUS_66MHZ);
7813 /* Stepping A2 */
7814 PDMPciDevSetByte( pPciDev, VBOX_PCI_REVISION_ID, 0x02);
7815 /* Ethernet adapter */
7816 PDMPciDevSetByte( pPciDev, VBOX_PCI_CLASS_PROG, 0x00);
7817 PDMPciDevSetWord( pPciDev, VBOX_PCI_CLASS_DEVICE, 0x0200);
7818 /* normal single function Ethernet controller */
7819 PDMPciDevSetByte( pPciDev, VBOX_PCI_HEADER_TYPE, 0x00);
7820 /* Memory Register Base Address */
7821 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_0, 0x00000000);
7822 /* Memory Flash Base Address */
7823 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_1, 0x00000000);
7824 /* IO Register Base Address */
7825 PDMPciDevSetDWord(pPciDev, VBOX_PCI_BASE_ADDRESS_2, 0x00000001);
7826 /* Expansion ROM Base Address */
7827 PDMPciDevSetDWord(pPciDev, VBOX_PCI_ROM_ADDRESS, 0x00000000);
7828 /* Capabilities Pointer */
7829 PDMPciDevSetByte( pPciDev, VBOX_PCI_CAPABILITY_LIST, 0xDC);
7830 /* Interrupt Pin: INTA# */
7831 PDMPciDevSetByte( pPciDev, VBOX_PCI_INTERRUPT_PIN, 0x01);
7832 /* Max_Lat/Min_Gnt: very high priority and time slice */
7833 PDMPciDevSetByte( pPciDev, VBOX_PCI_MIN_GNT, 0xFF);
7834 PDMPciDevSetByte( pPciDev, VBOX_PCI_MAX_LAT, 0x00);
7835
7836 /* PCI Power Management Registers ****************************************/
7837 /* Capability ID: PCI Power Management Registers */
7838 PDMPciDevSetByte( pPciDev, 0xDC, VBOX_PCI_CAP_ID_PM);
7839 /* Next Item Pointer: PCI-X */
7840 PDMPciDevSetByte( pPciDev, 0xDC + 1, 0xE4);
7841 /* Power Management Capabilities: PM disabled, DSI */
7842 PDMPciDevSetWord( pPciDev, 0xDC + 2,
7843 0x0002 | VBOX_PCI_PM_CAP_DSI);
7844 /* Power Management Control / Status Register: PM disabled */
7845 PDMPciDevSetWord( pPciDev, 0xDC + 4, 0x0000);
7846 /* PMCSR_BSE Bridge Support Extensions: Not supported */
7847 PDMPciDevSetByte( pPciDev, 0xDC + 6, 0x00);
7848 /* Data Register: PM disabled, always 0 */
7849 PDMPciDevSetByte( pPciDev, 0xDC + 7, 0x00);
7850
7851 /* PCI-X Configuration Registers *****************************************/
7852 /* Capability ID: PCI-X Configuration Registers */
7853 PDMPciDevSetByte( pPciDev, 0xE4, VBOX_PCI_CAP_ID_PCIX);
7854#ifdef E1K_WITH_MSI
7855 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x80);
7856#else
7857 /* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
7858 PDMPciDevSetByte( pPciDev, 0xE4 + 1, 0x00);
7859#endif
7860 /* PCI-X Command: Enable Relaxed Ordering */
7861 PDMPciDevSetWord( pPciDev, 0xE4 + 2, VBOX_PCI_X_CMD_ERO);
7862 /* PCI-X Status: 32-bit, 66MHz*/
7863 /** @todo is this value really correct? fff8 doesn't look like actual PCI address */
7864 PDMPciDevSetDWord(pPciDev, 0xE4 + 4, 0x0040FFF8);
7865}
7866
7867/**
7868 * @interface_method_impl{PDMDEVREG,pfnConstruct}
7869 */
7870static DECLCALLBACK(int) e1kR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
7871{
7872 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7873 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
7874 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
7875 int rc;
7876
7877 /*
7878 * Initialize the instance data (state).
7879 * Note! Caller has initialized it to ZERO already.
7880 */
7881 RTStrPrintf(pThis->szPrf, sizeof(pThis->szPrf), "E1000#%d", iInstance);
7882 E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", pThis->szPrf, sizeof(E1KRXDESC)));
7883 pThis->hEventMoreRxDescAvail = NIL_SUPSEMEVENT;
7884 pThis->u16TxPktLen = 0;
7885 pThis->fIPcsum = false;
7886 pThis->fTCPcsum = false;
7887 pThis->fIntMaskUsed = false;
7888 pThis->fDelayInts = false;
7889 pThis->fLocked = false;
7890 pThis->u64AckedAt = 0;
7891 pThis->led.u32Magic = PDMLED_MAGIC;
7892 pThis->u32PktNo = 1;
7893
7894 pThisCC->pDevInsR3 = pDevIns;
7895 pThisCC->pShared = pThis;
7896
7897 /* Interfaces */
7898 pThisCC->IBase.pfnQueryInterface = e1kR3QueryInterface;
7899
7900 pThisCC->INetworkDown.pfnWaitReceiveAvail = e1kR3NetworkDown_WaitReceiveAvail;
7901 pThisCC->INetworkDown.pfnReceive = e1kR3NetworkDown_Receive;
7902 pThisCC->INetworkDown.pfnXmitPending = e1kR3NetworkDown_XmitPending;
7903
7904 pThisCC->ILeds.pfnQueryStatusLed = e1kR3QueryStatusLed;
7905
7906 pThisCC->INetworkConfig.pfnGetMac = e1kR3GetMac;
7907 pThisCC->INetworkConfig.pfnGetLinkState = e1kR3GetLinkState;
7908 pThisCC->INetworkConfig.pfnSetLinkState = e1kR3SetLinkState;
7909
7910 /*
7911 * Internal validations.
7912 */
7913 for (uint32_t iReg = 1; iReg < E1K_NUM_OF_BINARY_SEARCHABLE; iReg++)
7914 AssertLogRelMsgReturn( g_aE1kRegMap[iReg].offset > g_aE1kRegMap[iReg - 1].offset
7915 && g_aE1kRegMap[iReg].offset + g_aE1kRegMap[iReg].size
7916 >= g_aE1kRegMap[iReg - 1].offset + g_aE1kRegMap[iReg - 1].size,
7917 ("%s@%#xLB%#x vs %s@%#xLB%#x\n",
7918 g_aE1kRegMap[iReg].abbrev, g_aE1kRegMap[iReg].offset, g_aE1kRegMap[iReg].size,
7919 g_aE1kRegMap[iReg - 1].abbrev, g_aE1kRegMap[iReg - 1].offset, g_aE1kRegMap[iReg - 1].size),
7920 VERR_INTERNAL_ERROR_4);
7921
7922 /*
7923 * Validate configuration.
7924 */
7925 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
7926 "MAC|"
7927 "CableConnected|"
7928 "AdapterType|"
7929 "LineSpeed|"
7930 "ItrEnabled|"
7931 "ItrRxEnabled|"
7932 "EthernetCRC|"
7933 "GSOEnabled|"
7934 "LinkUpDelay|"
7935 "StatNo",
7936 "");
7937
7938 /** @todo LineSpeed unused! */
7939
7940 /*
7941 * Get config params
7942 */
7943 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
7944 rc = pHlp->pfnCFGMQueryBytes(pCfg, "MAC", pThis->macConfigured.au8, sizeof(pThis->macConfigured.au8));
7945 if (RT_FAILURE(rc))
7946 return PDMDEV_SET_ERROR(pDevIns, rc,
7947 N_("Configuration error: Failed to get MAC address"));
7948 rc = pHlp->pfnCFGMQueryBool(pCfg, "CableConnected", &pThis->fCableConnected);
7949 if (RT_FAILURE(rc))
7950 return PDMDEV_SET_ERROR(pDevIns, rc,
7951 N_("Configuration error: Failed to get the value of 'CableConnected'"));
7952 rc = pHlp->pfnCFGMQueryU32(pCfg, "AdapterType", (uint32_t*)&pThis->eChip);
7953 if (RT_FAILURE(rc))
7954 return PDMDEV_SET_ERROR(pDevIns, rc,
7955 N_("Configuration error: Failed to get the value of 'AdapterType'"));
7956 Assert(pThis->eChip <= E1K_CHIP_82545EM);
7957
7958 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "EthernetCRC", &pThis->fEthernetCRC, true);
7959 if (RT_FAILURE(rc))
7960 return PDMDEV_SET_ERROR(pDevIns, rc,
7961 N_("Configuration error: Failed to get the value of 'EthernetCRC'"));
7962
7963 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "GSOEnabled", &pThis->fGSOEnabled, true);
7964 if (RT_FAILURE(rc))
7965 return PDMDEV_SET_ERROR(pDevIns, rc,
7966 N_("Configuration error: Failed to get the value of 'GSOEnabled'"));
7967
7968 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrEnabled", &pThis->fItrEnabled, false);
7969 if (RT_FAILURE(rc))
7970 return PDMDEV_SET_ERROR(pDevIns, rc,
7971 N_("Configuration error: Failed to get the value of 'ItrEnabled'"));
7972
7973 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ItrRxEnabled", &pThis->fItrRxEnabled, true);
7974 if (RT_FAILURE(rc))
7975 return PDMDEV_SET_ERROR(pDevIns, rc,
7976 N_("Configuration error: Failed to get the value of 'ItrRxEnabled'"));
7977
7978 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "TidEnabled", &pThis->fTidEnabled, false);
7979 if (RT_FAILURE(rc))
7980 return PDMDEV_SET_ERROR(pDevIns, rc,
7981 N_("Configuration error: Failed to get the value of 'TidEnabled'"));
7982
7983 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "LinkUpDelay", (uint32_t*)&pThis->cMsLinkUpDelay, 3000); /* ms */
7984 if (RT_FAILURE(rc))
7985 return PDMDEV_SET_ERROR(pDevIns, rc,
7986 N_("Configuration error: Failed to get the value of 'LinkUpDelay'"));
7987 Assert(pThis->cMsLinkUpDelay <= 300000); /* less than 5 minutes */
7988 if (pThis->cMsLinkUpDelay > 5000)
7989 LogRel(("%s: WARNING! Link up delay is set to %u seconds!\n", pThis->szPrf, pThis->cMsLinkUpDelay / 1000));
7990 else if (pThis->cMsLinkUpDelay == 0)
7991 LogRel(("%s: WARNING! Link up delay is disabled!\n", pThis->szPrf));
7992
7993 uint32_t uStatNo = (uint32_t)iInstance;
7994 rc = pHlp->pfnCFGMQueryU32Def(pCfg, "StatNo", &uStatNo, (uint32_t)iInstance);
7995 if (RT_FAILURE(rc))
7996 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to get the \"StatNo\" value"));
7997
7998 LogRel(("%s: Chip=%s LinkUpDelay=%ums EthernetCRC=%s GSO=%s Itr=%s ItrRx=%s TID=%s R0=%s RC=%s\n", pThis->szPrf,
7999 g_aChips[pThis->eChip].pcszName, pThis->cMsLinkUpDelay,
8000 pThis->fEthernetCRC ? "on" : "off",
8001 pThis->fGSOEnabled ? "enabled" : "disabled",
8002 pThis->fItrEnabled ? "enabled" : "disabled",
8003 pThis->fItrRxEnabled ? "enabled" : "disabled",
8004 pThis->fTidEnabled ? "enabled" : "disabled",
8005 pDevIns->fR0Enabled ? "enabled" : "disabled",
8006 pDevIns->fRCEnabled ? "enabled" : "disabled"));
8007
8008 /*
8009 * Initialize sub-components and register everything with the VMM.
8010 */
8011
8012 /* Initialize the EEPROM. */
8013 pThisCC->eeprom.init(pThis->macConfigured);
8014
8015 /* Initialize internal PHY. */
8016 Phy::init(&pThis->phy, iInstance, pThis->eChip == E1K_CHIP_82543GC ? PHY_EPID_M881000 : PHY_EPID_M881011);
8017
8018 /* Initialize critical sections. We do our own locking. */
8019 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8020 AssertRCReturn(rc, rc);
8021
8022 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->cs, RT_SRC_POS, "E1000#%d", iInstance);
8023 AssertRCReturn(rc, rc);
8024 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csRx, RT_SRC_POS, "E1000#%dRX", iInstance);
8025 AssertRCReturn(rc, rc);
8026#ifdef E1K_WITH_TX_CS
8027 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csTx, RT_SRC_POS, "E1000#%dTX", iInstance);
8028 AssertRCReturn(rc, rc);
8029#endif
8030
8031 /* Saved state registration. */
8032 rc = PDMDevHlpSSMRegisterEx(pDevIns, E1K_SAVEDSTATE_VERSION, sizeof(E1KSTATE), NULL,
8033 NULL, e1kLiveExec, NULL,
8034 e1kSavePrep, e1kSaveExec, NULL,
8035 e1kLoadPrep, e1kLoadExec, e1kLoadDone);
8036 AssertRCReturn(rc, rc);
8037
8038 /* Set PCI config registers and register ourselves with the PCI bus. */
8039 PDMPCIDEV_ASSERT_VALID(pDevIns, pDevIns->apPciDevs[0]);
8040 e1kR3ConfigurePciDev(pDevIns->apPciDevs[0], pThis->eChip);
8041 rc = PDMDevHlpPCIRegister(pDevIns, pDevIns->apPciDevs[0]);
8042 AssertRCReturn(rc, rc);
8043
8044#ifdef E1K_WITH_MSI
8045 PDMMSIREG MsiReg;
8046 RT_ZERO(MsiReg);
8047 MsiReg.cMsiVectors = 1;
8048 MsiReg.iMsiCapOffset = 0x80;
8049 MsiReg.iMsiNextOffset = 0x0;
8050 MsiReg.fMsi64bit = false;
8051 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
8052 AssertRCReturn(rc, rc);
8053#endif
8054
8055 /*
8056 * Map our registers to memory space (region 0, see e1kR3ConfigurePciDev)
8057 * From the spec (regarding flags):
8058 * For registers that should be accessed as 32-bit double words,
8059 * partial writes (less than a 32-bit double word) is ignored.
8060 * Partial reads return all 32 bits of data regardless of the
8061 * byte enables.
8062 */
8063 rc = PDMDevHlpMmioCreateEx(pDevIns, E1K_MM_SIZE, IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD,
8064 pDevIns->apPciDevs[0], 0 /*iPciRegion*/,
8065 e1kMMIOWrite, e1kMMIORead, NULL /*pfnFill*/, NULL /*pvUser*/, "E1000", &pThis->hMmioRegion);
8066 AssertRCReturn(rc, rc);
8067 rc = PDMDevHlpPCIIORegionRegisterMmio(pDevIns, 0, E1K_MM_SIZE, PCI_ADDRESS_SPACE_MEM, pThis->hMmioRegion, NULL);
8068 AssertRCReturn(rc, rc);
8069
8070 /* Map our registers to IO space (region 2, see e1kR3ConfigurePciDev) */
8071 static IOMIOPORTDESC const s_aExtDescs[] =
8072 {
8073 { "IOADDR", "IOADDR", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8074 { "IODATA", "IODATA", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL }, { "unused", "unused", NULL, NULL },
8075 { NULL, NULL, NULL, NULL }
8076 };
8077 rc = PDMDevHlpIoPortCreate(pDevIns, E1K_IOPORT_SIZE, pDevIns->apPciDevs[0], 2 /*iPciRegion*/,
8078 e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/, "E1000", s_aExtDescs, &pThis->hIoPorts);
8079 AssertRCReturn(rc, rc);
8080 rc = PDMDevHlpPCIIORegionRegisterIo(pDevIns, 2, E1K_IOPORT_SIZE, pThis->hIoPorts);
8081 AssertRCReturn(rc, rc);
8082
8083 /* Create transmit queue */
8084 rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "E1000-Xmit", e1kR3TxTaskCallback, NULL, &pThis->hTxTask);
8085 AssertRCReturn(rc, rc);
8086
8087#ifdef E1K_TX_DELAY
8088 /* Create Transmit Delay Timer */
8089 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxDelayTimer, pThis,
8090 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Delay", &pThis->hTXDTimer);
8091 AssertRCReturn(rc, rc);
8092 rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->hTXDTimer, &pThis->csTx);
8093 AssertRCReturn(rc, rc);
8094#endif /* E1K_TX_DELAY */
8095
8096//#ifdef E1K_USE_TX_TIMERS
8097 if (pThis->fTidEnabled)
8098 {
8099 /* Create Transmit Interrupt Delay Timer */
8100 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxIntDelayTimer, pThis,
8101 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit IRQ Delay", &pThis->hTIDTimer);
8102 AssertRCReturn(rc, rc);
8103
8104# ifndef E1K_NO_TAD
8105 /* Create Transmit Absolute Delay Timer */
8106 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3TxAbsDelayTimer, pThis,
8107 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Xmit Abs Delay", &pThis->hTADTimer);
8108 AssertRCReturn(rc, rc);
8109# endif /* E1K_NO_TAD */
8110 }
8111//#endif /* E1K_USE_TX_TIMERS */
8112
8113#ifdef E1K_USE_RX_TIMERS
8114 /* Create Receive Interrupt Delay Timer */
8115 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxIntDelayTimer, pThis,
8116 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv IRQ Delay", &pThis->hRIDTimer);
8117 AssertRCReturn(rc, rc);
8118
8119 /* Create Receive Absolute Delay Timer */
8120 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3RxAbsDelayTimer, pThis,
8121 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Recv Abs Delay", &pThis->hRADTimer);
8122 AssertRCReturn(rc, rc);
8123#endif /* E1K_USE_RX_TIMERS */
8124
8125 /* Create Late Interrupt Timer */
8126 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LateIntTimer, pThis,
8127 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Late IRQ", &pThis->hIntTimer);
8128 AssertRCReturn(rc, rc);
8129
8130 /* Create Link Up Timer */
8131 rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL, e1kR3LinkUpTimer, pThis,
8132 TMTIMER_FLAGS_NO_CRIT_SECT | TMTIMER_FLAGS_RING0, "E1000 Link Up", &pThis->hLUTimer);
8133 AssertRCReturn(rc, rc);
8134
8135 /* Register the info item */
8136 char szTmp[20];
8137 RTStrPrintf(szTmp, sizeof(szTmp), "e1k%d", iInstance);
8138 PDMDevHlpDBGFInfoRegister(pDevIns, szTmp, "E1000 info.", e1kInfo);
8139
8140 /* Status driver */
8141 PPDMIBASE pBase;
8142 rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThisCC->IBase, &pBase, "Status Port");
8143 if (RT_FAILURE(rc))
8144 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the status LUN"));
8145 pThisCC->pLedsConnector = PDMIBASE_QUERY_INTERFACE(pBase, PDMILEDCONNECTORS);
8146
8147 /* Network driver */
8148 rc = PDMDevHlpDriverAttach(pDevIns, 0, &pThisCC->IBase, &pThisCC->pDrvBase, "Network Port");
8149 if (RT_SUCCESS(rc))
8150 {
8151 pThisCC->pDrvR3 = PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMINETWORKUP);
8152 AssertMsgReturn(pThisCC->pDrvR3, ("Failed to obtain the PDMINETWORKUP interface!\n"), VERR_PDM_MISSING_INTERFACE_BELOW);
8153
8154#if 0 /** @todo @bugref{9218} ring-0 driver stuff */
8155 pThisR0->pDrvR0 = PDMIBASER0_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASER0), PDMINETWORKUP);
8156 pThisRC->pDrvRC = PDMIBASERC_QUERY_INTERFACE(PDMIBASE_QUERY_INTERFACE(pThisCC->pDrvBase, PDMIBASERC), PDMINETWORKUP);
8157#endif
8158 }
8159 else if ( rc == VERR_PDM_NO_ATTACHED_DRIVER
8160 || rc == VERR_PDM_CFG_MISSING_DRIVER_NAME)
8161 {
8162 /* No error! */
8163 E1kLog(("%s This adapter is not attached to any network!\n", pThis->szPrf));
8164 }
8165 else
8166 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach the network LUN"));
8167
8168 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEventMoreRxDescAvail);
8169 AssertRCReturn(rc, rc);
8170
8171 rc = e1kInitDebugHelpers();
8172 AssertRCReturn(rc, rc);
8173
8174 e1kR3HardReset(pDevIns, pThis, pThisCC);
8175
8176 /*
8177 * Register statistics.
8178 * The /Public/ bits are official and used by session info in the GUI.
8179 */
8180 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8181 "Amount of data received", "/Public/NetAdapter/%u/BytesReceived", uStatNo);
8182 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
8183 "Amount of data transmitted", "/Public/NetAdapter/%u/BytesTransmitted", uStatNo);
8184 PDMDevHlpSTAMRegisterF(pDevIns, &pDevIns->iInstance, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
8185 "Device instance number", "/Public/NetAdapter/%u/%s", uStatNo, pDevIns->pReg->szName);
8186
8187 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveBytes, STAMTYPE_COUNTER, "ReceiveBytes", STAMUNIT_BYTES, "Amount of data received");
8188 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitBytes, STAMTYPE_COUNTER, "TransmitBytes", STAMUNIT_BYTES, "Amount of data transmitted");
8189
8190#if defined(VBOX_WITH_STATISTICS)
8191 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadRZ, STAMTYPE_PROFILE, "MMIO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in RZ");
8192 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadR3, STAMTYPE_PROFILE, "MMIO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in R3");
8193 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteRZ, STAMTYPE_PROFILE, "MMIO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in RZ");
8194 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteR3, STAMTYPE_PROFILE, "MMIO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in R3");
8195 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMRead, STAMTYPE_PROFILE, "EEPROM/Read", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads");
8196 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatEEPROMWrite, STAMTYPE_PROFILE, "EEPROM/Write", STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes");
8197 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadRZ, STAMTYPE_PROFILE, "IO/ReadRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in RZ");
8198 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOReadR3, STAMTYPE_PROFILE, "IO/ReadR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in R3");
8199 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteRZ, STAMTYPE_PROFILE, "IO/WriteRZ", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in RZ");
8200 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIOWriteR3, STAMTYPE_PROFILE, "IO/WriteR3", STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in R3");
8201 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateIntTimer, STAMTYPE_PROFILE, "LateInt/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling late int timer");
8202 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatLateInts, STAMTYPE_COUNTER, "LateInt/Occured", STAMUNIT_OCCURENCES, "Number of late interrupts");
8203 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsRaised, STAMTYPE_COUNTER, "Interrupts/Raised", STAMUNIT_OCCURENCES, "Number of raised interrupts");
8204 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntsPrevented, STAMTYPE_COUNTER, "Interrupts/Prevented", STAMUNIT_OCCURENCES, "Number of prevented interrupts");
8205 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceive, STAMTYPE_PROFILE, "Receive/Total", STAMUNIT_TICKS_PER_CALL, "Profiling receive");
8206 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveCRC, STAMTYPE_PROFILE, "Receive/CRC", STAMUNIT_TICKS_PER_CALL, "Profiling receive checksumming");
8207 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveFilter, STAMTYPE_PROFILE, "Receive/Filter", STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering");
8208 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatReceiveStore, STAMTYPE_PROFILE, "Receive/Store", STAMUNIT_TICKS_PER_CALL, "Profiling receive storing");
8209 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflow, STAMTYPE_PROFILE, "RxOverflow", STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows");
8210 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupRZ, STAMTYPE_COUNTER, "RxOverflowWakeupRZ", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in RZ");
8211 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRxOverflowWakeupR3, STAMTYPE_COUNTER, "RxOverflowWakeupR3", STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups in R3");
8212 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitRZ, STAMTYPE_PROFILE, "Transmit/TotalRZ", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in RZ");
8213 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitR3, STAMTYPE_PROFILE, "Transmit/TotalR3", STAMUNIT_TICKS_PER_CALL, "Profiling transmits in R3");
8214 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendRZ, STAMTYPE_PROFILE, "Transmit/SendRZ", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in RZ");
8215 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTransmitSendR3, STAMTYPE_PROFILE, "Transmit/SendR3", STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in R3");
8216
8217 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxNormal, STAMTYPE_COUNTER, "TxDesc/ContexNormal", STAMUNIT_OCCURENCES, "Number of normal context descriptors");
8218 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescCtxTSE, STAMTYPE_COUNTER, "TxDesc/ContextTSE", STAMUNIT_OCCURENCES, "Number of TSE context descriptors");
8219 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescData, STAMTYPE_COUNTER, "TxDesc/Data", STAMUNIT_OCCURENCES, "Number of TX data descriptors");
8220 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescLegacy, STAMTYPE_COUNTER, "TxDesc/Legacy", STAMUNIT_OCCURENCES, "Number of TX legacy descriptors");
8221 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxDescTSEData, STAMTYPE_COUNTER, "TxDesc/TSEData", STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors");
8222 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathFallback, STAMTYPE_COUNTER, "TxPath/Fallback", STAMUNIT_OCCURENCES, "Fallback TSE descriptor path");
8223 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathGSO, STAMTYPE_COUNTER, "TxPath/GSO", STAMUNIT_OCCURENCES, "GSO TSE descriptor path");
8224 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTxPathRegular, STAMTYPE_COUNTER, "TxPath/Normal", STAMUNIT_OCCURENCES, "Regular descriptor path");
8225 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPHYAccesses, STAMTYPE_COUNTER, "PHYAccesses", STAMUNIT_OCCURENCES, "Number of PHY accesses");
8226 for (unsigned iReg = 0; iReg < E1K_NUM_OF_REGS; iReg++)
8227 {
8228 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8229 g_aE1kRegMap[iReg].name, "Regs/%s-Reads", g_aE1kRegMap[iReg].abbrev);
8230 PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[iReg], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
8231 g_aE1kRegMap[iReg].name, "Regs/%s-Writes", g_aE1kRegMap[iReg].abbrev);
8232 }
8233#endif /* VBOX_WITH_STATISTICS */
8234
8235#ifdef E1K_INT_STATS
8236 PDMDevHlpSTAMRegister(pDevIns, &pThis->u64ArmedAt, STAMTYPE_U64, "u64ArmedAt", STAMUNIT_NS, NULL);
8237 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatMaxTxDelay, STAMTYPE_U64, "uStatMaxTxDelay", STAMUNIT_NS, NULL);
8238 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatInt, STAMTYPE_U32, "uStatInt", STAMUNIT_NS, NULL);
8239 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTry, STAMTYPE_U32, "uStatIntTry", STAMUNIT_NS, NULL);
8240 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLower, STAMTYPE_U32, "uStatIntLower", STAMUNIT_NS, NULL);
8241 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatNoIntICR, STAMTYPE_U32, "uStatNoIntICR", STAMUNIT_NS, NULL);
8242 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLost, STAMTYPE_U32, "iStatIntLost", STAMUNIT_NS, NULL);
8243 PDMDevHlpSTAMRegister(pDevIns, &pThis->iStatIntLostOne, STAMTYPE_U32, "iStatIntLostOne", STAMUNIT_NS, NULL);
8244 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntIMS, STAMTYPE_U32, "uStatIntIMS", STAMUNIT_NS, NULL);
8245 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntSkip, STAMTYPE_U32, "uStatIntSkip", STAMUNIT_NS, NULL);
8246 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntLate, STAMTYPE_U32, "uStatIntLate", STAMUNIT_NS, NULL);
8247 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntMasked, STAMTYPE_U32, "uStatIntMasked", STAMUNIT_NS, NULL);
8248 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntEarly, STAMTYPE_U32, "uStatIntEarly", STAMUNIT_NS, NULL);
8249 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRx, STAMTYPE_U32, "uStatIntRx", STAMUNIT_NS, NULL);
8250 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTx, STAMTYPE_U32, "uStatIntTx", STAMUNIT_NS, NULL);
8251 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntICS, STAMTYPE_U32, "uStatIntICS", STAMUNIT_NS, NULL);
8252 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRDTR, STAMTYPE_U32, "uStatIntRDTR", STAMUNIT_NS, NULL);
8253 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntRXDMT0, STAMTYPE_U32, "uStatIntRXDMT0", STAMUNIT_NS, NULL);
8254 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatIntTXQE, STAMTYPE_U32, "uStatIntTXQE", STAMUNIT_NS, NULL);
8255 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxNoRS, STAMTYPE_U32, "uStatTxNoRS", STAMUNIT_NS, NULL);
8256 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxIDE, STAMTYPE_U32, "uStatTxIDE", STAMUNIT_NS, NULL);
8257 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayed, STAMTYPE_U32, "uStatTxDelayed", STAMUNIT_NS, NULL);
8258 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxDelayExp, STAMTYPE_U32, "uStatTxDelayExp", STAMUNIT_NS, NULL);
8259 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTAD, STAMTYPE_U32, "uStatTAD", STAMUNIT_NS, NULL);
8260 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTID, STAMTYPE_U32, "uStatTID", STAMUNIT_NS, NULL);
8261 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRAD, STAMTYPE_U32, "uStatRAD", STAMUNIT_NS, NULL);
8262 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRID, STAMTYPE_U32, "uStatRID", STAMUNIT_NS, NULL);
8263 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatRxFrm, STAMTYPE_U32, "uStatRxFrm", STAMUNIT_NS, NULL);
8264 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxFrm, STAMTYPE_U32, "uStatTxFrm", STAMUNIT_NS, NULL);
8265 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescCtx, STAMTYPE_U32, "uStatDescCtx", STAMUNIT_NS, NULL);
8266 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescDat, STAMTYPE_U32, "uStatDescDat", STAMUNIT_NS, NULL);
8267 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatDescLeg, STAMTYPE_U32, "uStatDescLeg", STAMUNIT_NS, NULL);
8268 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx1514, STAMTYPE_U32, "uStatTx1514", STAMUNIT_NS, NULL);
8269 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx2962, STAMTYPE_U32, "uStatTx2962", STAMUNIT_NS, NULL);
8270 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx4410, STAMTYPE_U32, "uStatTx4410", STAMUNIT_NS, NULL);
8271 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx5858, STAMTYPE_U32, "uStatTx5858", STAMUNIT_NS, NULL);
8272 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx7306, STAMTYPE_U32, "uStatTx7306", STAMUNIT_NS, NULL);
8273 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx8754, STAMTYPE_U32, "uStatTx8754", STAMUNIT_NS, NULL);
8274 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx16384, STAMTYPE_U32, "uStatTx16384", STAMUNIT_NS, NULL);
8275 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTx32768, STAMTYPE_U32, "uStatTx32768", STAMUNIT_NS, NULL);
8276 PDMDevHlpSTAMRegister(pDevIns, &pThis->uStatTxLarge, STAMTYPE_U32, "uStatTxLarge", STAMUNIT_NS, NULL);
8277#endif /* E1K_INT_STATS */
8278
8279 return VINF_SUCCESS;
8280}
8281
8282#else /* !IN_RING3 */
8283
8284/**
8285 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
8286 */
8287static DECLCALLBACK(int) e1kRZConstruct(PPDMDEVINS pDevIns)
8288{
8289 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
8290 PE1KSTATE pThis = PDMDEVINS_2_DATA(pDevIns, PE1KSTATE);
8291 PE1KSTATECC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PE1KSTATECC);
8292
8293 /* Initialize context specific state data: */
8294 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
8295 /** @todo @bugref{9218} ring-0 driver stuff */
8296 pThisCC->CTX_SUFF(pDrv) = NULL;
8297 pThisCC->CTX_SUFF(pTxSg) = NULL;
8298
8299 /* Configure critical sections the same way: */
8300 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
8301 AssertRCReturn(rc, rc);
8302
8303 /* Set up MMIO and I/O port callbacks for this context: */
8304 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmioRegion, e1kMMIOWrite, e1kMMIORead, NULL /*pvUser*/);
8305 AssertRCReturn(rc, rc);
8306
8307 rc = PDMDevHlpIoPortSetUpContext(pDevIns, pThis->hIoPorts, e1kIOPortOut, e1kIOPortIn, NULL /*pvUser*/);
8308 AssertRCReturn(rc, rc);
8309
8310 return VINF_SUCCESS;
8311}
8312
8313#endif /* !IN_RING3 */
8314
8315/**
8316 * The device registration structure.
8317 */
8318const PDMDEVREG g_DeviceE1000 =
8319{
8320 /* .u32version = */ PDM_DEVREG_VERSION,
8321 /* .uReserved0 = */ 0,
8322 /* .szName = */ "e1000",
8323 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
8324 /* .fClass = */ PDM_DEVREG_CLASS_NETWORK,
8325 /* .cMaxInstances = */ ~0U,
8326 /* .uSharedVersion = */ 42,
8327 /* .cbInstanceShared = */ sizeof(E1KSTATE),
8328 /* .cbInstanceCC = */ sizeof(E1KSTATECC),
8329 /* .cbInstanceRC = */ sizeof(E1KSTATERC),
8330 /* .cMaxPciDevices = */ 1,
8331 /* .cMaxMsixVectors = */ 0,
8332 /* .pszDescription = */ "Intel PRO/1000 MT Desktop Ethernet.",
8333#if defined(IN_RING3)
8334 /* .pszRCMod = */ "VBoxDDRC.rc",
8335 /* .pszR0Mod = */ "VBoxDDR0.r0",
8336 /* .pfnConstruct = */ e1kR3Construct,
8337 /* .pfnDestruct = */ e1kR3Destruct,
8338 /* .pfnRelocate = */ e1kR3Relocate,
8339 /* .pfnMemSetup = */ NULL,
8340 /* .pfnPowerOn = */ NULL,
8341 /* .pfnReset = */ e1kR3Reset,
8342 /* .pfnSuspend = */ e1kR3Suspend,
8343 /* .pfnResume = */ NULL,
8344 /* .pfnAttach = */ e1kR3Attach,
8345 /* .pfnDeatch = */ e1kR3Detach,
8346 /* .pfnQueryInterface = */ NULL,
8347 /* .pfnInitComplete = */ NULL,
8348 /* .pfnPowerOff = */ e1kR3PowerOff,
8349 /* .pfnSoftReset = */ NULL,
8350 /* .pfnReserved0 = */ NULL,
8351 /* .pfnReserved1 = */ NULL,
8352 /* .pfnReserved2 = */ NULL,
8353 /* .pfnReserved3 = */ NULL,
8354 /* .pfnReserved4 = */ NULL,
8355 /* .pfnReserved5 = */ NULL,
8356 /* .pfnReserved6 = */ NULL,
8357 /* .pfnReserved7 = */ NULL,
8358#elif defined(IN_RING0)
8359 /* .pfnEarlyConstruct = */ NULL,
8360 /* .pfnConstruct = */ e1kRZConstruct,
8361 /* .pfnDestruct = */ NULL,
8362 /* .pfnFinalDestruct = */ NULL,
8363 /* .pfnRequest = */ NULL,
8364 /* .pfnReserved0 = */ NULL,
8365 /* .pfnReserved1 = */ NULL,
8366 /* .pfnReserved2 = */ NULL,
8367 /* .pfnReserved3 = */ NULL,
8368 /* .pfnReserved4 = */ NULL,
8369 /* .pfnReserved5 = */ NULL,
8370 /* .pfnReserved6 = */ NULL,
8371 /* .pfnReserved7 = */ NULL,
8372#elif defined(IN_RC)
8373 /* .pfnConstruct = */ e1kRZConstruct,
8374 /* .pfnReserved0 = */ NULL,
8375 /* .pfnReserved1 = */ NULL,
8376 /* .pfnReserved2 = */ NULL,
8377 /* .pfnReserved3 = */ NULL,
8378 /* .pfnReserved4 = */ NULL,
8379 /* .pfnReserved5 = */ NULL,
8380 /* .pfnReserved6 = */ NULL,
8381 /* .pfnReserved7 = */ NULL,
8382#else
8383# error "Not in IN_RING3, IN_RING0 or IN_RC!"
8384#endif
8385 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
8386};
8387
8388#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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