1 | /** @file
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2 | * Microware-compatible 64x16-bit 93C46 EEPROM Emulation.
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3 | */
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4 |
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5 | /*
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6 | * Copyright (C) 2007 innotek GmbH
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7 | *
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8 | * This file is part of VirtualBox Open Source Edition (OSE), as
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9 | * available from http://www.virtualbox.org. This file is free software;
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10 | * you can redistribute it and/or modify it under the terms of the GNU
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11 | * General Public License as published by the Free Software Foundation,
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12 | * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
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13 | * distribution. VirtualBox OSE is distributed in the hope that it will
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14 | * be useful, but WITHOUT ANY WARRANTY of any kind.
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15 | */
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16 |
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17 | /* Interface */
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18 | #include <iprt/types.h>
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19 |
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20 | /**
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21 | * 93C46-compatible EEPROM device emulation.
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22 | */
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23 | class EEPROM93C46 {
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24 | public:
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25 | EEPROM93C46(const uint16_t * initial = 0);
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26 |
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27 | /** General definitions */
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28 | enum {
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29 | /** Size of EEPROM in words */
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30 | SIZE = 64,
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31 | /** Number of bits per word */
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32 | WORD_SIZE = 16,
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33 | /** Number of address bits */
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34 | ADDR_SIZE = 6,
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35 | /** Number of bits in opcode */
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36 | OPCODE_SIZE = 2,
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37 | /** The most significant bit mask in data word */
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38 | DATA_MSB = 1<<(WORD_SIZE-1),
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39 | /** Address mask */
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40 | ADDR_MASK = (1<<ADDR_SIZE)-1,
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41 | /** The most significant bit mask in op+addr bit sequence */
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42 | OPADDR_MSB = 1<<(OPCODE_SIZE+ADDR_SIZE-1)
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43 | };
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44 | /**
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45 | * Names of signal wires
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46 | */
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47 | enum Wires {
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48 | SK=0x1, ///< Clock
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49 | CS=0x2, ///< Chip Select
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50 | DI=0x4, ///< Data In
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51 | DO=0x8 ///< Data Out
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52 | };
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53 |
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54 |
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55 | uint32_t read();
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56 | void write(uint32_t wires);
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57 |
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58 | /* @todo save and load methods */
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59 |
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60 | protected:
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61 | /** Actual content of EEPROM */
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62 | uint16_t data[SIZE];
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63 |
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64 | private:
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65 | /** current state.
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66 | *
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67 | * EEPROM operates as a simple state machine. Events are primarily
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68 | * triggered at positive edge of clock signal (SK). Refer to the
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69 | * timing diagrams of 93C46 to get better understanding.
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70 | */
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71 | enum State {
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72 | /** Initial state. Waiting for start condition (CS, SK, DI high). */
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73 | STANDBY,
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74 | /** Reading data in, shifting in the bits into 'word'. */
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75 | READING_DI,
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76 | /** Writing data out, shifting out the bits from 'word'. */
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77 | WRITING_DO,
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78 | /** Waiting for CS=0 to indicate we are busy (DO=0). */
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79 | WAITING_CS_FALL,
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80 | /** Waiting for CS=1 to indicate we are ready (DO=1). */
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81 | WAITING_CS_RISE
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82 | } state;
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83 | /** setting writeEnable to false prevents write and erase operations */
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84 | bool writeEnabled;
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85 | /** intermediate storage */
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86 | uint16_t word;
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87 | /** currently processed bit in 'word' */
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88 | uint16_t mask;
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89 | /** decoded address */
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90 | uint16_t addr;
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91 | /** Data Out, Data In, Chip Select, Clock */
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92 | uint32_t internalWires;
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93 |
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94 | /** Pointer to decoded operation. When no operation has been decoded yet
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95 | * it points to opDecode.
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96 | */
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97 | State (EEPROM93C46::*op)(void);
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98 |
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99 | // Operation handlers
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100 | State opDecode();
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101 | State opRead();
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102 | State opWrite();
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103 | State opWriteAll();
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104 |
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105 | /** Helper method to implement write protection */
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106 | void storeWord(uint32_t addr, uint16_t value);
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107 | };
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