ahci.c@ 39591

Last change on this file since 39591 was 39591, checked in by vboxsync, 13 years ago
Messing with read sizes some more.
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1	/* $Id: ahci.c 39591 2011-12-12 18:09:12Z vboxsync $ */
2	/** @file
3	* AHCI host adapter driver to boot from SATA disks.
4	*/
5
6	/*
7	* Copyright (C) 2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	//@todo!!!! save/restore high bits of EAX/ECX and whatever else may be needed.
19
20	#include <stdint.h>
21	#include <string.h>
22	#include "biosint.h"
23	#include "ebda.h"
24	#include "inlines.h"
25	#include "pciutil.h"
26	#include "vds.h"
27
28	#if DEBUG_AHCI
29	# define DBG_AHCI(...) BX_INFO(__VA_ARGS__)
30	#else
31	# define DBG_AHCI(...)
32	#endif
33
34	/* Number of S/G table entries in EDDS. */
35	#define NUM_EDDS_SG 16
36
37
38	/**
39	* AHCI PRDT structure.
40	*/
41	typedef struct
42	{
43	uint32_t phys_addr;
44	uint32_t something;
45	uint32_t reserved;
46	uint32_t len;
47	} ahci_prdt;
48
49	/**
50	* AHCI controller data.
51	*/
52	typedef struct
53	{
54	/** The AHCI command list as defined by chapter 4.2.2 of the Intel AHCI spec.
55	* Because the BIOS doesn't support NCQ only the first command header is defined
56	* to save memory. - Must be aligned on a 1K boundary.
57	*/
58	uint32_t aCmdHdr[0x8];
59	/** Align the next structure on a 128 byte boundary. */
60	uint8_t abAlignment1[0x60];
61	/** The command table of one request as defined by chapter 4.2.3 of the Intel AHCI spec.
62	* Must be aligned on 128 byte boundary.
63	*/
64	uint8_t abCmd[0x40];
65	/** The ATAPI command region.
66	* Located 40h bytes after the beginning of the CFIS (Command FIS).
67	*/
68	uint8_t abAcmd[0x20];
69	/** Align the PRDT structure on a 128 byte boundary. */
70	uint8_t abAlignment2[0x20];
71	/** Physical Region Descriptor Table (PRDT) array. In other
72	* words, a scatter/gather descriptor list.
73	*/
74	ahci_prdt aPrdt[16];
75	/** Memory for the received command FIS area as specified by chapter 4.2.1
76	* of the Intel AHCI spec. This area is normally 256 bytes big but to save memory
77	* only the first 96 bytes are used because it is assumed that the controller
78	* never writes to the UFIS or reserved area. - Must be aligned on a 256byte boundary.
79	*/
80	uint8_t abFisRecv[0x60];
81	/** Base I/O port for the index/data register pair. */
82	uint16_t iobase;
83	/** Current port which uses the memory to communicate with the controller. */
84	uint8_t cur_port;
85	/** VDS EDDS DMA buffer descriptor structure. */
86	vds_edds edds;
87	vds_sg edds_more_sg[NUM_EDDS_SG - 1];
88	} ahci_t;
89
90	#define AhciData ((ahci_t *) 0)
91
92	/** PCI configuration fields. */
93	#define PCI_CONFIG_CAP 0x34
94
95	#define PCI_CAP_ID_SATACR 0x12
96	#define VBOX_AHCI_NO_DEVICE 0xffff
97
98	#define RT_BIT_32(bit) ((uint32_t)(1L << (bit)))
99
100	/** Global register set. */
101	#define AHCI_HBA_SIZE 0x100
102
103	//@todo: what are the casts good for?
104	#define AHCI_REG_CAP ((uint32_t)0x00)
105	#define AHCI_REG_GHC ((uint32_t)0x04)
106	# define AHCI_GHC_AE RT_BIT_32(31)
107	# define AHCI_GHC_IR RT_BIT_32(1)
108	# define AHCI_GHC_HR RT_BIT_32(0)
109	#define AHCI_REG_IS ((uint32_t)0x08)
110	#define AHCI_REG_PI ((uint32_t)0x0c)
111	#define AHCI_REG_VS ((uint32_t)0x10)
112
113	/** Per port register set. */
114	#define AHCI_PORT_SIZE 0x80
115
116	#define AHCI_REG_PORT_CLB 0x00
117	#define AHCI_REG_PORT_CLBU 0x04
118	#define AHCI_REG_PORT_FB 0x08
119	#define AHCI_REG_PORT_FBU 0x0c
120	#define AHCI_REG_PORT_IS 0x10
121	# define AHCI_REG_PORT_IS_DHRS RT_BIT_32(0)
122	# define AHCI_REG_PORT_IS_TFES RT_BIT_32(30)
123	#define AHCI_REG_PORT_IE 0x14
124	#define AHCI_REG_PORT_CMD 0x18
125	# define AHCI_REG_PORT_CMD_ST RT_BIT_32(0)
126	# define AHCI_REG_PORT_CMD_FRE RT_BIT_32(4)
127	# define AHCI_REG_PORT_CMD_FR RT_BIT_32(14)
128	# define AHCI_REG_PORT_CMD_CR RT_BIT_32(15)
129	#define AHCI_REG_PORT_TFD 0x20
130	#define AHCI_REG_PORT_SIG 0x24
131	#define AHCI_REG_PORT_SSTS 0x28
132	#define AHCI_REG_PORT_SCTL 0x2c
133	#define AHCI_REG_PORT_SERR 0x30
134	#define AHCI_REG_PORT_SACT 0x34
135	#define AHCI_REG_PORT_CI 0x38
136
137	/** Returns the absolute register offset from a given port and port register. */
138	#define AHCI_PORT_REG(port, reg) ((uint32_t)(AHCI_HBA_SIZE + (port) * AHCI_PORT_SIZE + (reg)))
139
140	#define AHCI_REG_IDX 0
141	#define AHCI_REG_DATA 4
142
143	/** Writes the given value to a AHCI register. */
144	#define AHCI_WRITE_REG(iobase, reg, val) \
145	outpd((iobase) + AHCI_REG_IDX, (uint32_t)(reg)); \
146	outpd((iobase) + AHCI_REG_DATA, (uint32_t)(val))
147
148	/** Reads from a AHCI register. */
149	#define AHCI_READ_REG(iobase, reg, val) \
150	outpd((iobase) + AHCI_REG_IDX, (uint32_t)(reg)); \
151	(val) = inpd((iobase) + AHCI_REG_DATA)
152
153	/** Writes to the given port register. */
154	#define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val) \
155	AHCI_WRITE_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
156
157	/** Reads from the given port register. */
158	#define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val) \
159	AHCI_READ_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
160
161	#define ATA_CMD_IDENTIFY_DEVICE 0xEC
162	#define ATA_CMD_IDENTIFY_PACKET 0xA1
163	#define ATA_CMD_PACKET 0xA0
164	#define AHCI_CMD_READ_DMA_EXT 0x25
165	#define AHCI_CMD_WRITE_DMA_EXT 0x35
166
167
168	/* Warning: Destroys high bits of EAX. */
169	uint32_t inpd(uint16_t port);
170	#pragma aux inpd = \
171	".386" \
172	"in eax, dx" \
173	"mov dx, ax" \
174	"shr eax, 16" \
175	"xchg ax, dx" \
176	parm [dx] value [dx ax] modify nomemory;
177
178	void outpd(uint16_t port, uint32_t val);
179	#pragma aux outpd = \
180	".386" \
181	"xchg ax, cx" \
182	"shl eax, 16" \
183	"mov ax, cx" \
184	"out dx, eax" \
185	parm [dx] [cx ax] modify nomemory;
186
187
188	/**
189	* Sets a given set of bits in a register.
190	*/
191	static void ahci_ctrl_set_bits(uint16_t iobase, uint32_t reg, uint32_t mask)
192	{
193	outpd(iobase + AHCI_REG_IDX, reg);
194	outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) \| mask);
195	}
196
197	/**
198	* Clears a given set of bits in a register.
199	*/
200	static void ahci_ctrl_clear_bits(uint16_t iobase, uint32_t reg, uint32_t mask)
201	{
202	outpd(iobase + AHCI_REG_IDX, reg);
203	outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
204	}
205
206	/**
207	* Returns whether at least one of the bits in the given mask is set
208	* for a register.
209	*/
210	static uint8_t ahci_ctrl_is_bit_set(uint16_t iobase, uint32_t reg, uint32_t mask)
211	{
212	outpd(iobase + AHCI_REG_IDX, reg);
213	return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
214	}
215
216	/**
217	* Extracts a range of bits from a register and shifts them
218	* to the right.
219	*/
220	static uint16_t ahci_ctrl_extract_bits(uint32_t val, uint32_t mask, uint8_t shift)
221	{
222	return (val & mask) >> shift;
223	}
224
225	/**
226	* Converts a segment:offset pair into a 32bit physical address.
227	*/
228	static uint32_t ahci_addr_to_phys(void __far *ptr)
229	{
230	return ((uint32_t)FP_SEG(ptr) << 4) + FP_OFF(ptr);
231	}
232
233	/**
234	* Issues a command to the SATA controller and waits for completion.
235	*/
236	static void ahci_port_cmd_sync(ahci_t __far *ahci, uint8_t val, uint16_t cbData)
237	{
238	uint16_t io_base;
239	uint8_t port;
240
241	port = ahci->cur_port;
242	io_base = ahci->iobase;
243
244	if (port != 0xff)
245	{
246	/* Prepare the command header. */
247	ahci->aCmdHdr[0] = RT_BIT_32(16) \| RT_BIT_32(7) \| val;
248	ahci->aCmdHdr[1] = 0; //cbData; //@todo: Is this really an input parameter?
249	ahci->aCmdHdr[2] = ahci_addr_to_phys(&ahci->abCmd[0]);
250
251	/* Enable Command and FIS receive engine. */
252	ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
253	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
254
255	/* Queue command. */
256	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CI, 0x1);
257
258	/* Wait for a D2H FIS. */
259	DBG_AHCI("AHCI: Waiting for D2H FIS\n");
260	while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
261	AHCI_REG_PORT_IS_DHRS \| AHCI_REG_PORT_IS_TFES) == 0)
262	{
263	// This is where we'd need some kind of a yield functionality...
264	}
265
266	ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
267	AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
268
269	/* Disable command engine. */
270	ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
271	AHCI_REG_PORT_CMD_ST);
272
273	/** @todo: Examine status. */
274	}
275	else
276	DBG_AHCI("AHCI: Invalid port given\n");
277	}
278
279	/**
280	* Issue command to device.
281	*/
282	static void ahci_cmd_data(bio_dsk_t __far *bios_dsk, uint8_t cmd)
283	{
284	ahci_t __far *ahci = bios_dsk->ahci_seg :> 0;
285	uint16_t n_sect = bios_dsk->drqp.nsect;
286	uint16_t sectsz = bios_dsk->drqp.sect_sz;
287
288	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
289
290	/* Prepare the FIS. */
291	ahci->abCmd[0] = 0x27; /* FIS type H2D. */
292	ahci->abCmd[1] = 1 << 7; /* Command update. */
293	ahci->abCmd[2] = cmd;
294	ahci->abCmd[3] = 0;
295
296	ahci->abCmd[4] = bios_dsk->drqp.lba & 0xff;
297	ahci->abCmd[5] = (bios_dsk->drqp.lba >> 8) & 0xff;
298	ahci->abCmd[6] = (bios_dsk->drqp.lba >> 16) & 0xff;
299	ahci->abCmd[7] = RT_BIT_32(6); /* LBA access. */
300
301	ahci->abCmd[8] = (bios_dsk->drqp.lba >> 24) & 0xff;
302	ahci->abCmd[9] = 0;
303	ahci->abCmd[10] = 0;
304	ahci->abCmd[11] = 0;
305
306	ahci->abCmd[12] = (uint8_t)(n_sect & 0xff);
307	ahci->abCmd[13] = (uint8_t)((n_sect >> 8) & 0xff);
308
309	/* Lock memory needed for DMA. */
310	ahci->edds.num_avail = NUM_EDDS_SG;
311	vds_build_sg_list(&ahci->edds, bios_dsk->drqp.buffer, (uint32_t)n_sect * sectsz);
312
313	/* Set up the PRDT. */
314	ahci->aPrdt[0].phys_addr = ahci->edds.u.sg[0].phys_addr;
315	ahci->aPrdt[0].len = ahci->edds.u.sg[0].size - 1;
316
317	/* Build variable part first of command dword (reuses 'cmd'). */
318	if (cmd == AHCI_CMD_WRITE_DMA_EXT)
319	cmd = RT_BIT_32(6); /* Indicate write to device. */
320	else if (cmd == ATA_CMD_PACKET) {
321	cmd \|= RT_BIT_32(5); /* Indicate ATAPI command. */
322	ahci->abCmd[3] \|= 1; /* DMA transfers. */
323	} else
324	cmd = 0;
325
326	cmd \|= 5; /* Five DWORDs. */
327
328	ahci_port_cmd_sync(ahci, cmd, n_sect * sectsz);
329
330	/* Unlock the buffer again. */
331	vds_free_sg_list(&ahci->edds);
332	}
333
334	/**
335	* Deinits the curent active port.
336	*/
337	static void ahci_port_deinit_current(ahci_t __far *ahci)
338	{
339	uint16_t io_base;
340	uint8_t port;
341
342	io_base = ahci->iobase;
343	port = ahci->cur_port;
344
345	if (port != 0xff)
346	{
347	/* Put the port into an idle state. */
348	ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
349	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
350
351	while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
352	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST \| AHCI_REG_PORT_CMD_FR \| AHCI_REG_PORT_CMD_CR) == 1)
353	{
354	DBG_AHCI("AHCI: Waiting for the port to idle\n");
355	}
356
357	/*
358	* Port idles, set up memory for commands and received FIS and program the
359	* address registers.
360	*/
361	//@todo: merge memsets?
362	_fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
363	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
364	_fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
365
366	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FB, 0);
367	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FBU, 0);
368
369	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLB, 0);
370	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLBU, 0);
371
372	/* Disable all interrupts. */
373	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_IE, 0);
374
375	ahci->cur_port = 0xff;
376	}
377	}
378
379	/**
380	* Brings a port into a minimal state to make device detection possible
381	* or to queue requests.
382	*/
383	static void ahci_port_init(ahci_t __far *ahci, uint8_t u8Port)
384	{
385	/* Deinit any other port first. */
386	ahci_port_deinit_current(ahci);
387
388	/* Put the port into an idle state. */
389	ahci_ctrl_clear_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
390	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
391
392	while (ahci_ctrl_is_bit_set(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
393	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST \| AHCI_REG_PORT_CMD_FR \| AHCI_REG_PORT_CMD_CR) == 1)
394	{
395	DBG_AHCI("AHCI: Waiting for the port to idle\n");
396	}
397
398	/*
399	* Port idles, set up memory for commands and received FIS and program the
400	* address registers.
401	*/
402	//@todo: just one memset?
403	_fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
404	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
405	_fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
406
407	DBG_AHCI("AHCI: FIS receive area %lx from %x:%x\n",
408	ahci_addr_to_phys(&ahci->abFisRecv), FP_SEG(ahci), &AhciData->abFisRecv);
409	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FB, ahci_addr_to_phys(&ahci->abFisRecv));
410	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FBU, 0);
411
412	DBG_AHCI("AHCI: CMD list area %lx\n", ahci_addr_to_phys(&ahci->aCmdHdr));
413	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLB, ahci_addr_to_phys(&ahci->aCmdHdr));
414	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLBU, 0);
415
416	/* Disable all interrupts. */
417	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IE, 0);
418	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IS, 0xffffffff);
419	/* Clear all errors. */
420	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
421
422	ahci->cur_port = u8Port;
423	}
424
425	/**
426	* Read sectors from an attached AHCI device.
427	*
428	* @returns status code.
429	* @param bios_dsk Pointer to disk request packet (in the
430	* EBDA).
431	*/
432	int ahci_read_sectors(bio_dsk_t __far *bios_dsk)
433	{
434	uint16_t device_id;
435
436	device_id = bios_dsk->drqp.dev_id - BX_MAX_ATA_DEVICES - BX_MAX_SCSI_DEVICES;
437	if (device_id > BX_MAX_AHCI_DEVICES)
438	BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
439
440	DBG_AHCI("%s: %u sectors @ LBA %lu, device %d, port %d\n", __func__,
441	bios_dsk->drqp.nsect, bios_dsk->drqp.lba, device_id,
442	bios_dsk->ahcidev[device_id].port);
443
444	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
445	ahci_cmd_data(bios_dsk, AHCI_CMD_READ_DMA_EXT);
446	#ifdef DMA_WORKAROUND
447	rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.nsect * 512 / 2);
448	#endif
449	return 0; //@todo!!
450	}
451
452	/**
453	* Write sectors to an attached AHCI device.
454	*
455	* @returns status code.
456	* @param bios_dsk Pointer to disk request packet (in the
457	* EBDA).
458	*/
459	int ahci_write_sectors(bio_dsk_t __far *bios_dsk)
460	{
461	uint16_t device_id;
462
463	device_id = bios_dsk->drqp.dev_id - BX_MAX_ATA_DEVICES - BX_MAX_SCSI_DEVICES;
464	if (device_id > BX_MAX_AHCI_DEVICES)
465	BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
466
467	DBG_AHCI("%s: %u sectors @ LBA %lu, device %d, port %d\n", __func__,
468	bios_dsk->drqp.nsect, bios_dsk->drqp.lba, device_id,
469	bios_dsk->ahcidev[device_id].port);
470
471	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
472	ahci_cmd_data(bios_dsk, AHCI_CMD_WRITE_DMA_EXT);
473	return 0; //@todo!!
474	}
475
476	//@todo: move
477	#define ATA_DATA_NO 0x00
478	#define ATA_DATA_IN 0x01
479	#define ATA_DATA_OUT 0x02
480
481	uint16_t ahci_cmd_packet(uint16_t device_id, uint8_t cmdlen, char __far *cmdbuf,
482	uint16_t header, uint32_t length, uint8_t inout, char __far *buffer)
483	{
484	bio_dsk_t __far *bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
485	ahci_t __far *ahci = bios_dsk->ahci_seg :> 0;
486
487	/* Data out is currently not supported. */
488	if (inout == ATA_DATA_OUT) {
489	BX_INFO("%s: DATA_OUT not supported yet\n", __func__);
490	return 1;
491	}
492
493	/* The header length must be even. */
494	if (header & 1) {
495	DBG_AHCI("%s: header must be even (%04x)\n", __func__, header);
496	return 1;
497	}
498
499	/* Convert to AHCI specific device number. */
500	device_id = device_id - BX_MAX_ATA_DEVICES - BX_MAX_SCSI_DEVICES;
501
502	DBG_AHCI("%s: reading %lu bytes, header %u, device %d, port %d\n", __func__,
503	length, header, device_id, bios_dsk->ahcidev[device_id].port);
504	DBG_AHCI("%s: reading %u %u-byte sectors\n", __func__,
505	bios_dsk->drqp.nsect, bios_dsk->drqp.sect_sz);
506
507	bios_dsk->drqp.lba = (uint32_t)length << 8; //@todo: xfer length limit
508	bios_dsk->drqp.buffer = buffer;
509	bios_dsk->drqp.nsect = length / bios_dsk->drqp.sect_sz;
510	// bios_dsk->drqp.sect_sz = 2048;
511
512	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
513
514	/* Copy the ATAPI command where the HBA can fetch it. */
515	_fmemcpy(ahci->abAcmd, cmdbuf, cmdlen);
516
517	/* Reset transferred counts. */
518	// @todo: clear in calling code?
519	bios_dsk->drqp.trsfsectors = 0;
520	bios_dsk->drqp.trsfbytes = 0;
521
522	ahci_cmd_data(bios_dsk, ATA_CMD_PACKET);
523	DBG_AHCI("%s: transferred %lu bytes\n", __func__, ahci->aCmdHdr[1]);
524	bios_dsk->drqp.trsfbytes = ahci->aCmdHdr[1];
525	#ifdef DMA_WORKAROUND
526	rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.trsfbytes / 2);
527	#endif
528	return ahci->aCmdHdr[1] == 0 ? 4 : 0;
529	// return 0; //@todo!!
530	}
531
532	static void ahci_port_detect_device(ahci_t __far *ahci, uint8_t u8Port)
533	{
534	uint32_t val;
535	bio_dsk_t __far *bios_dsk;
536
537	ahci_port_init(ahci, u8Port);
538
539	bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
540
541	/* Reset connection. */
542	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0x01);
543	/*
544	* According to the spec we should wait at least 1msec until the reset
545	* is cleared but this is a virtual controller so we don't have to.
546	*/
547	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0);
548
549	/* Check if there is a device on the port. */
550	VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
551	if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 0x3)
552	{
553	uint8_t abBuffer[0x0200];
554	uint8_t hdcount, devcount_ahci, hd_index;
555	uint8_t cdcount;
556	uint8_t removable;
557
558	devcount_ahci = bios_dsk->ahci_devcnt;
559
560	DBG_AHCI("AHCI: Device detected on port %d\n", u8Port);
561
562	//@todo: Merge common HD/CDROM detection code
563	if (devcount_ahci < BX_MAX_AHCI_DEVICES)
564	{
565	/* Device detected, enable FIS receive. */
566	ahci_ctrl_set_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
567	AHCI_REG_PORT_CMD_FRE);
568
569	/* Check signature to determine device type. */
570	VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SIG, val);
571	if (val == 0x101)
572	{
573	uint32_t cSectors;
574	uint16_t cCylinders, cHeads, cSectorsPerTrack;
575	uint8_t idxCmosChsBase;
576
577	DBG_AHCI("AHCI: Detected hard disk\n");
578
579	/* Identify device. */
580	bios_dsk->drqp.lba = 0;
581	bios_dsk->drqp.buffer = &abBuffer;
582	bios_dsk->drqp.nsect = 1;
583	bios_dsk->drqp.sect_sz = 512;
584	ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_DEVICE);
585
586	/* Calculate index into the generic device table. */
587	hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
588
589	removable = *(abBuffer+0) & 0x80 ? 1 : 0;
590	cCylinders = (uint16_t )(abBuffer+(1*2)); // word 1
591	cHeads = (uint16_t )(abBuffer+(3*2)); // word 3
592	cSectorsPerTrack = (uint16_t )(abBuffer+(6*2)); // word 6
593	cSectors = (uint32_t )(abBuffer+(60*2)); // word 60 and word 61
594
595	/** @todo update sectors to be a 64 bit number (also lba...). */
596	if (cSectors == 268435455)
597	cSectors = (uint16_t )(abBuffer+(100*2)); // words 100 to 103 (someday)
598
599	DBG_AHCI("AHCI: %ld sectors\n", cSectors);
600
601	bios_dsk->ahcidev[devcount_ahci].port = u8Port;
602	bios_dsk->devices[hd_index].type = ATA_TYPE_AHCI;
603	bios_dsk->devices[hd_index].device = ATA_DEVICE_HD;
604	bios_dsk->devices[hd_index].removable = removable;
605	bios_dsk->devices[hd_index].lock = 0;
606	bios_dsk->devices[hd_index].blksize = 512;
607	bios_dsk->devices[hd_index].translation = ATA_TRANSLATION_LBA;
608	bios_dsk->devices[hd_index].sectors = cSectors;
609
610	bios_dsk->devices[hd_index].pchs.heads = cHeads;
611	bios_dsk->devices[hd_index].pchs.cylinders = cCylinders;
612	bios_dsk->devices[hd_index].pchs.spt = cSectorsPerTrack;
613
614	/* Get logical CHS geometry. */
615	switch (devcount_ahci)
616	{
617	case 0:
618	idxCmosChsBase = 0x40;
619	break;
620	case 1:
621	idxCmosChsBase = 0x48;
622	break;
623	case 2:
624	idxCmosChsBase = 0x50;
625	break;
626	case 3:
627	idxCmosChsBase = 0x58;
628	break;
629	default:
630	idxCmosChsBase = 0;
631	}
632	if (idxCmosChsBase != 0)
633	{
634	cCylinders = inb_cmos(idxCmosChsBase) + (inb_cmos(idxCmosChsBase+1) << 8);
635	cHeads = inb_cmos(idxCmosChsBase+2);
636	cSectorsPerTrack = inb_cmos(idxCmosChsBase+7);
637	}
638	else
639	{
640	cCylinders = 0;
641	cHeads = 0;
642	cSectorsPerTrack = 0;
643	}
644	DBG_AHCI("AHCI: Dev %d LCHS=%d/%d/%d\n",
645	devcount_ahci, cCylinders, cHeads, cSectorsPerTrack);
646
647	bios_dsk->devices[hd_index].lchs.heads = cHeads;
648	bios_dsk->devices[hd_index].lchs.cylinders = cCylinders;
649	bios_dsk->devices[hd_index].lchs.spt = cSectorsPerTrack;
650
651	/* Store the ID of the disk in the BIOS hdidmap. */
652	hdcount = bios_dsk->hdcount;
653	bios_dsk->hdidmap[hdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
654	hdcount++;
655	bios_dsk->hdcount = hdcount;
656
657	/* Update hdcount in the BDA. */
658	hdcount = read_byte(0x40, 0x75);
659	hdcount++;
660	write_byte(0x40, 0x75, hdcount);
661	}
662	else if (val == 0xeb140101)
663	{
664	DBG_AHCI("AHCI: Detected ATAPI device\n");
665
666	/* Identify packet device. */
667	bios_dsk->drqp.lba = 0;
668	bios_dsk->drqp.buffer = &abBuffer;
669	bios_dsk->drqp.nsect = 1;
670	bios_dsk->drqp.sect_sz = 512;
671	ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_PACKET);
672
673	/* Calculate index into the generic device table. */
674	hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
675
676	removable = *(abBuffer+0) & 0x80 ? 1 : 0;
677
678	bios_dsk->ahcidev[devcount_ahci].port = u8Port;
679	bios_dsk->devices[hd_index].type = ATA_TYPE_AHCI;
680	bios_dsk->devices[hd_index].device = ATA_DEVICE_CDROM;
681	bios_dsk->devices[hd_index].removable = removable;
682	bios_dsk->devices[hd_index].blksize = 2048;
683
684	/* Store the ID of the device in the BIOS cdidmap. */
685	cdcount = bios_dsk->cdcount;
686	bios_dsk->cdidmap[cdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
687	cdcount++;
688	bios_dsk->cdcount = cdcount;
689	}
690	else
691	DBG_AHCI("AHCI: Ignoring unknown device\n");
692
693	devcount_ahci++;
694	bios_dsk->ahci_devcnt = devcount_ahci;
695	}
696	else
697	DBG_AHCI("AHCI: Reached maximum device count, skipping\n");
698	}
699	}
700
701	/**
702	* Allocates 1K of conventional memory.
703	*/
704	static uint16_t ahci_mem_alloc(void)
705	{
706	uint16_t base_mem_kb;
707	uint16_t ahci_seg;
708
709	base_mem_kb = read_word(0x00, 0x0413);
710
711	DBG_AHCI("AHCI: %dK of base mem\n", base_mem_kb);
712
713	if (base_mem_kb == 0)
714	return 0;
715
716	base_mem_kb--; /* Allocate one block. */
717	ahci_seg = (((uint32_t)base_mem_kb * 1024) >> 4); /* Calculate start segment. */
718
719	write_word(0x00, 0x0413, base_mem_kb);
720
721	return ahci_seg;
722	}
723
724	/**
725	* Initializes the AHCI HBA and detects attached devices.
726	*/
727	static int ahci_hba_init(uint16_t io_base)
728	{
729	uint8_t i, cPorts;
730	uint32_t val;
731	uint16_t ebda_seg;
732	uint16_t ahci_seg;
733
734	ebda_seg = read_word(0x0040, 0x000E);
735
736	AHCI_READ_REG(io_base, AHCI_REG_VS, val);
737	DBG_AHCI("AHCI: Controller version: 0x%x (major) 0x%x (minor)\n",
738	ahci_ctrl_extract_bits(val, 0xffff0000, 16),
739	ahci_ctrl_extract_bits(val, 0x0000ffff, 0));
740
741	/* Allocate 1K of base memory. */
742	ahci_seg = ahci_mem_alloc();
743	if (ahci_seg == 0)
744	{
745	DBG_AHCI("AHCI: Could not allocate 1K of memory, can't boot from controller\n");
746	return 0;
747	}
748	DBG_AHCI("AHCI: ahci_seg=%04x, size=%04x, pointer at EBDA:%04x (EBDA size=%04x)\n",
749	ahci_seg, sizeof(ahci_t), (uint16_t)&EbdaData->bdisk.ahci_seg, sizeof(ebda_data_t));
750
751	write_word(ebda_seg, (uint16_t)&EbdaData->bdisk.ahci_seg, ahci_seg);
752	write_byte(ebda_seg, (uint16_t)&EbdaData->bdisk.ahci_devcnt, 0);
753	write_byte(ahci_seg, (uint16_t)&AhciData->cur_port, 0xff);
754	write_word(ahci_seg, (uint16_t)&AhciData->iobase, io_base);
755
756	/* Reset the controller. */
757	ahci_ctrl_set_bits(io_base, AHCI_REG_GHC, AHCI_GHC_HR);
758	do
759	{
760	AHCI_READ_REG(io_base, AHCI_REG_GHC, val);
761	} while (val & AHCI_GHC_HR != 0);
762
763	AHCI_READ_REG(io_base, AHCI_REG_CAP, val);
764	cPorts = ahci_ctrl_extract_bits(val, 0x1f, 0) + 1; /* Extract number of ports.*/
765
766	DBG_AHCI("AHCI: HBA has %u ports\n", cPorts);
767
768	/* Go through the ports. */
769	i = 0;
770	while (i < 32)
771	{
772	if (ahci_ctrl_is_bit_set(io_base, AHCI_REG_PI, RT_BIT_32(i)) != 0)
773	{
774	DBG_AHCI("AHCI: Port %u is present\n", i);
775	ahci_port_detect_device(ahci_seg :> 0, i);
776	cPorts--;
777	if (cPorts == 0)
778	break;
779	}
780	i++;
781	}
782
783	return 0;
784	}
785
786	/**
787	* Init the AHCI driver and detect attached disks.
788	*/
789	void BIOSCALL ahci_init(void)
790	{
791	uint16_t busdevfn;
792
793	busdevfn = pci_find_classcode(0x00010601);
794	if (busdevfn != VBOX_AHCI_NO_DEVICE)
795	{
796	uint8_t u8Bus, u8DevFn;
797	uint8_t u8PciCapOff;
798
799	u8Bus = (busdevfn & 0xff00) >> 8;
800	u8DevFn = busdevfn & 0x00ff;
801
802	DBG_AHCI("AHCI HBA at Bus %u DevFn 0x%x (raw 0x%x)\n", u8Bus, u8DevFn, busdevfn);
803
804	/* Examine the capability list and search for the Serial ATA Capability Register. */
805	u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
806
807	while (u8PciCapOff != 0)
808	{
809	uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
810
811	DBG_AHCI("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
812
813	if (u8PciCapId == PCI_CAP_ID_SATACR)
814	break;
815
816	/* Go on to the next capability. */
817	u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
818	}
819
820	if (u8PciCapOff != 0)
821	{
822	uint8_t u8Rev;
823
824	DBG_AHCI("AHCI HBA with SATA Capability register at 0x%x\n", u8PciCapOff);
825
826	/* Advance to the stuff behind the id and next capability pointer. */
827	u8PciCapOff += 2;
828
829	u8Rev = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
830	if (u8Rev == 0x10)
831	{
832	/* Read the SATACR1 register and get the bar and offset of the index/data pair register. */
833	uint8_t u8Bar = 0x00;
834	uint16_t u16Off = 0x00;
835	uint16_t u16BarOff = pci_read_config_word(u8Bus, u8DevFn, u8PciCapOff + 2);
836
837	DBG_AHCI("SATACR1: 0x%x\n", u16BarOff);
838
839	switch (u16BarOff & 0xf)
840	{
841	case 0x04:
842	u8Bar = 0x10;
843	break;
844	case 0x05:
845	u8Bar = 0x14;
846	break;
847	case 0x06:
848	u8Bar = 0x18;
849	break;
850	case 0x07:
851	u8Bar = 0x1c;
852	break;
853	case 0x08:
854	u8Bar = 0x20;
855	break;
856	case 0x09:
857	u8Bar = 0x24;
858	break;
859	case 0x0f:
860	default:
861	/* Reserved or unsupported. */
862	DBG_AHCI("BAR 0x%x unsupported\n", u16BarOff & 0xf);
863	}
864
865	/* Get the offset inside the BAR from bits 4:15. */
866	u16Off = (u16BarOff >> 4) * 4;
867
868	if (u8Bar != 0x00)
869	{
870	uint32_t u32Bar = pci_read_config_dword(u8Bus, u8DevFn, u8Bar);
871
872	DBG_AHCI("BAR at 0x%x : 0x%x\n", u8Bar, u32Bar);
873
874	if ((u32Bar & 0x01) != 0)
875	{
876	int rc;
877	uint16_t u16AhciIoBase = (u32Bar & 0xfff0) + u16Off;
878
879	DBG_AHCI("I/O base: 0x%x\n", u16AhciIoBase);
880	rc = ahci_hba_init(u16AhciIoBase);
881	}
882	else
883	DBG_AHCI("BAR is MMIO\n");
884	}
885	}
886	else
887	DBG_AHCI("Invalid revision 0x%x\n", u8Rev);
888	}
889	else
890	DBG_AHCI("AHCI HBA with no usable Index/Data register pair!\n");
891	}
892	else
893	DBG_AHCI("No AHCI HBA!\n");
894	}

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source: vbox/trunk/src/VBox/Devices/PC/BIOS-new/ahci.c@ 39591

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