ahci.c@ 104068

Last change on this file since 104068 was 104068, checked in by vboxsync, 8 months ago
BIOS: Build real VDS S/G lists in AHCI driver, don't just fake it.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 34.7 KB

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1	/* $Id: ahci.c 104068 2024-03-26 16:38:31Z vboxsync $ */
2	/** @file
3	* AHCI host adapter driver to boot from SATA disks.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#include <stdint.h>
29	#include <string.h>
30	#include "biosint.h"
31	#include "ebda.h"
32	#include "inlines.h"
33	#include "pciutil.h"
34	#include "vds.h"
35
36	#if DEBUG_AHCI
37	# define DBG_AHCI(...) BX_INFO(__VA_ARGS__)
38	#else
39	# define DBG_AHCI(...)
40	#endif
41
42	/* Number of S/G table entries in EDDS. */
43	#define NUM_EDDS_SG 17
44
45
46	/**
47	* AHCI PRDT structure.
48	*/
49	typedef struct
50	{
51	uint32_t phys_addr;
52	uint32_t something;
53	uint32_t reserved;
54	uint32_t len;
55	} ahci_prdt;
56
57	/**
58	* SATA D2H FIS (Device to Host Frame Information Structure).
59	*/
60	typedef struct {
61	uint8_t fis_type; /* 34h */
62	uint8_t intr; /* Bit 6 indicates interrupt status. */
63	uint8_t status; /* Status register. */
64	uint8_t error; /* Error register. */
65	uint8_t sec_no; /* Sector number register. */
66	uint8_t cyl_lo; /* Cylinder low register. */
67	uint8_t cyl_hi; /* Cylinder high register. */
68	uint8_t dev_hd; /* Device/head register. */
69	uint8_t sec_no_exp; /* Expanded sector number register. */
70	uint8_t cyl_lo_exp; /* Expanded cylinder low register. */
71	uint8_t cyl_hi_exp; /* Expanded cylinder high register. */
72	uint8_t resvd0;
73	uint8_t sec_cn; /* Sector count register. */
74	uint8_t sec_cn_exp; /* Expanded sector count register. */
75	uint16_t resvd1;
76	uint32_t resvd2;
77	} fis_d2h;
78
79	ct_assert(sizeof(fis_d2h) == 20);
80
81	/**
82	* AHCI controller data.
83	*/
84	typedef struct
85	{
86	/** The AHCI command list as defined by chapter 4.2.2 of the Intel AHCI spec.
87	* Because the BIOS doesn't support NCQ only the first command header is defined
88	* to save memory. - Must be aligned on a 1K boundary.
89	*/
90	uint32_t aCmdHdr[0x8];
91	/** Align the next structure on a 128 byte boundary. */
92	uint8_t abAlignment1[0x60];
93	/** The command table of one request as defined by chapter 4.2.3 of the Intel AHCI spec.
94	* Must be aligned on 128 byte boundary.
95	*/
96	uint8_t abCmd[0x40];
97	/** The ATAPI command region.
98	* Located 40h bytes after the beginning of the CFIS (Command FIS).
99	*/
100	uint8_t abAcmd[0x20];
101	/** Align the PRDT structure on a 128 byte boundary. */
102	uint8_t abAlignment2[0x20];
103	/** Physical Region Descriptor Table (PRDT) array. In other
104	* words, a scatter/gather descriptor list.
105	*/
106	ahci_prdt aPrdt[16];
107	/** Memory for the received command FIS area as specified by chapter 4.2.1
108	* of the Intel AHCI spec. This area is normally 256 bytes big but to save memory
109	* only the first 96 bytes are used because it is assumed that the controller
110	* never writes to the UFIS or reserved area. - Must be aligned on a 256byte boundary.
111	*/
112	uint8_t abFisRecv[0x60];
113	/** Base I/O port for the index/data register pair. */
114	uint16_t iobase;
115	/** Current port which uses the memory to communicate with the controller. */
116	uint8_t cur_port;
117	/** Current PRD index (for pre/post skip). */
118	uint8_t cur_prd;
119	/** Saved high bits of EAX. */
120	uint16_t saved_eax_hi;
121	/** VDS EDDS DMA buffer descriptor structure. */
122	vds_edds edds;
123	vds_sg edds_more_sg[NUM_EDDS_SG - 1];
124	} ahci_t;
125
126	/* The AHCI specific data must fit into 1KB (statically allocated). */
127	ct_assert(sizeof(ahci_t) <= 1024);
128
129	/** PCI configuration fields. */
130	#define PCI_CONFIG_CAP 0x34
131
132	#define PCI_CAP_ID_SATACR 0x12
133	#define VBOX_AHCI_NO_DEVICE 0xffff
134
135	#define RT_BIT_32(bit) ((uint32_t)(1L << (bit)))
136
137	/** Global register set. */
138	#define AHCI_HBA_SIZE 0x100
139
140	/// @todo what are the casts good for?
141	#define AHCI_REG_CAP ((uint32_t)0x00)
142	#define AHCI_REG_GHC ((uint32_t)0x04)
143	# define AHCI_GHC_AE RT_BIT_32(31)
144	# define AHCI_GHC_IR RT_BIT_32(1)
145	# define AHCI_GHC_HR RT_BIT_32(0)
146	#define AHCI_REG_IS ((uint32_t)0x08)
147	#define AHCI_REG_PI ((uint32_t)0x0c)
148	#define AHCI_REG_VS ((uint32_t)0x10)
149
150	/** Per port register set. */
151	#define AHCI_PORT_SIZE 0x80
152
153	#define AHCI_REG_PORT_CLB 0x00
154	#define AHCI_REG_PORT_CLBU 0x04
155	#define AHCI_REG_PORT_FB 0x08
156	#define AHCI_REG_PORT_FBU 0x0c
157	#define AHCI_REG_PORT_IS 0x10
158	# define AHCI_REG_PORT_IS_DHRS RT_BIT_32(0)
159	# define AHCI_REG_PORT_IS_TFES RT_BIT_32(30)
160	#define AHCI_REG_PORT_IE 0x14
161	#define AHCI_REG_PORT_CMD 0x18
162	# define AHCI_REG_PORT_CMD_ST RT_BIT_32(0)
163	# define AHCI_REG_PORT_CMD_FRE RT_BIT_32(4)
164	# define AHCI_REG_PORT_CMD_FR RT_BIT_32(14)
165	# define AHCI_REG_PORT_CMD_CR RT_BIT_32(15)
166	#define AHCI_REG_PORT_TFD 0x20
167	#define AHCI_REG_PORT_SIG 0x24
168	#define AHCI_REG_PORT_SSTS 0x28
169	#define AHCI_REG_PORT_SCTL 0x2c
170	#define AHCI_REG_PORT_SERR 0x30
171	#define AHCI_REG_PORT_SACT 0x34
172	#define AHCI_REG_PORT_CI 0x38
173
174	/** Returns the absolute register offset from a given port and port register. */
175	#define AHCI_PORT_REG(port, reg) (AHCI_HBA_SIZE + (port) * AHCI_PORT_SIZE + (reg))
176
177	#define AHCI_REG_IDX 0
178	#define AHCI_REG_DATA 4
179
180	/** Writes the given value to a AHCI register. */
181	#define AHCI_WRITE_REG(iobase, reg, val) \
182	outpd((iobase) + AHCI_REG_IDX, reg); \
183	outpd((iobase) + AHCI_REG_DATA, val)
184
185	/** Reads from a AHCI register. */
186	#define AHCI_READ_REG(iobase, reg, val) \
187	outpd((iobase) + AHCI_REG_IDX, reg); \
188	(val) = inpd((iobase) + AHCI_REG_DATA)
189
190	/** Writes to the given port register. */
191	#define VBOXAHCI_PORT_WRITE_REG(iobase, port, reg, val) \
192	AHCI_WRITE_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
193
194	/** Reads from the given port register. */
195	#define VBOXAHCI_PORT_READ_REG(iobase, port, reg, val) \
196	AHCI_READ_REG((iobase), AHCI_PORT_REG((port), (reg)), val)
197
198	#define ATA_CMD_IDENTIFY_DEVICE 0xEC
199	#define ATA_CMD_IDENTIFY_PACKET 0xA1
200	#define ATA_CMD_PACKET 0xA0
201	#define AHCI_CMD_READ_DMA_EXT 0x25
202	#define AHCI_CMD_WRITE_DMA_EXT 0x35
203
204
205	/* Warning: Destroys high bits of EAX. */
206	uint32_t inpd(uint16_t port);
207	#pragma aux inpd = \
208	".386" \
209	"in eax, dx" \
210	"mov dx, ax" \
211	"shr eax, 16" \
212	"xchg ax, dx" \
213	parm [dx] value [dx ax] modify nomemory;
214
215	/* Warning: Destroys high bits of EAX. */
216	void outpd(uint16_t port, uint32_t val);
217	#pragma aux outpd = \
218	".386" \
219	"xchg ax, cx" \
220	"shl eax, 16" \
221	"mov ax, cx" \
222	"out dx, eax" \
223	parm [dx] [cx ax] modify nomemory;
224
225
226	/* Machinery to save/restore high bits of EAX. 32-bit port I/O needs to use
227	* EAX, but saving/restoring EAX around each port access would be inefficient.
228	* Instead, each externally callable routine must save the high bits before
229	* modifying them and restore the high bits before exiting.
230	*/
231
232	/* Note: Reading high EAX bits destroys them - must be restored later. */
233	uint16_t eax_hi_rd(void);
234	#pragma aux eax_hi_rd = \
235	".386" \
236	"shr eax, 16" \
237	value [ax] modify nomemory;
238
239	void eax_hi_wr(uint16_t);
240	#pragma aux eax_hi_wr = \
241	".386" \
242	"shl eax, 16" \
243	parm [ax] modify nomemory;
244
245	void inline high_bits_save(ahci_t __far *ahci)
246	{
247	ahci->saved_eax_hi = eax_hi_rd();
248	}
249
250	void inline high_bits_restore(ahci_t __far *ahci)
251	{
252	eax_hi_wr(ahci->saved_eax_hi);
253	}
254
255	/**
256	* Sets a given set of bits in a register.
257	*/
258	static void inline ahci_ctrl_set_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
259	{
260	outpd(iobase + AHCI_REG_IDX, reg);
261	outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) \| mask);
262	}
263
264	/**
265	* Clears a given set of bits in a register.
266	*/
267	static void inline ahci_ctrl_clear_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
268	{
269	outpd(iobase + AHCI_REG_IDX, reg);
270	outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
271	}
272
273	/**
274	* Returns whether at least one of the bits in the given mask is set
275	* for a register.
276	*/
277	static uint8_t inline ahci_ctrl_is_bit_set(uint16_t iobase, uint16_t reg, uint32_t mask)
278	{
279	outpd(iobase + AHCI_REG_IDX, reg);
280	return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
281	}
282
283	/**
284	* Extracts a range of bits from a register and shifts them
285	* to the right.
286	*/
287	static uint16_t ahci_ctrl_extract_bits(uint32_t val, uint32_t mask, uint8_t shift)
288	{
289	return (val & mask) >> shift;
290	}
291
292	/**
293	* Converts a segment:offset pair into a 32bit physical address.
294	*/
295	static uint32_t ahci_addr_to_phys(void __far *ptr)
296	{
297	return ((uint32_t)FP_SEG(ptr) << 4) + FP_OFF(ptr);
298	}
299
300	/**
301	* Issues a command to the SATA controller and waits for completion.
302	*/
303	static void ahci_port_cmd_sync(ahci_t __far *ahci, uint8_t val)
304	{
305	uint16_t io_base;
306	uint8_t port;
307
308	port = ahci->cur_port;
309	io_base = ahci->iobase;
310
311	if (port != 0xff)
312	{
313	/* Prepare the command header. */
314	ahci->aCmdHdr[0] = ((uint32_t)ahci->cur_prd << 16) \| RT_BIT_32(7) \| val;
315	ahci->aCmdHdr[1] = 0;
316	ahci->aCmdHdr[2] = ahci_addr_to_phys(&ahci->abCmd[0]);
317
318	/* Enable Command and FIS receive engine. */
319	ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
320	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
321
322	/* Queue command. */
323	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CI, 0x1);
324
325	/* Wait for a D2H FIS. */
326	DBG_AHCI("AHCI: Waiting for D2H FIS\n");
327	while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
328	AHCI_REG_PORT_IS_DHRS \| AHCI_REG_PORT_IS_TFES) == 0)
329	{
330	// This is where we'd need some kind of a yield functionality...
331	}
332
333	ahci_ctrl_set_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_IS),
334	AHCI_REG_PORT_IS_DHRS); /* Acknowledge received D2H FIS. */
335
336	/* Disable command engine. */
337	ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
338	AHCI_REG_PORT_CMD_ST);
339	/* Caller must examine status. */
340	}
341	else
342	DBG_AHCI("AHCI: Invalid port given\n");
343	}
344
345	/**
346	* Issue command to device.
347	*/
348	static uint16_t ahci_cmd_data(bio_dsk_t __far *bios_dsk, uint8_t cmd)
349	{
350	ahci_t __far *ahci = bios_dsk->ahci_seg :> 0;
351	uint16_t n_sect = bios_dsk->drqp.nsect;
352	uint16_t sectsz = bios_dsk->drqp.sect_sz;
353	fis_d2h __far *d2h;
354	int i;
355
356	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
357
358	/* Prepare the FIS. */
359	ahci->abCmd[0] = 0x27; /* FIS type H2D. */
360	ahci->abCmd[1] = 1 << 7; /* Command update. */
361	ahci->abCmd[2] = cmd;
362	ahci->abCmd[3] = 0;
363
364	ahci->abCmd[4] = bios_dsk->drqp.lba & 0xff;
365	ahci->abCmd[5] = (bios_dsk->drqp.lba >> 8) & 0xff;
366	ahci->abCmd[6] = (bios_dsk->drqp.lba >> 16) & 0xff;
367	ahci->abCmd[7] = RT_BIT_32(6); /* LBA access. */
368
369	ahci->abCmd[8] = (bios_dsk->drqp.lba >> 24) & 0xff;
370	ahci->abCmd[9] = (bios_dsk->drqp.lba >> 32) & 0xff;
371	ahci->abCmd[10] = (bios_dsk->drqp.lba >> 40) & 0xff;
372	ahci->abCmd[11] = 0;
373
374	ahci->abCmd[12] = (uint8_t)(n_sect & 0xff);
375	ahci->abCmd[13] = (uint8_t)((n_sect >> 8) & 0xff);
376
377	/* Lock memory needed for DMA. */
378	ahci->edds.num_avail = NUM_EDDS_SG;
379	DBG_AHCI("AHCI: S/G list for %lu bytes\n", (uint32_t)n_sect * sectsz);
380	vds_build_sg_list(&ahci->edds, bios_dsk->drqp.buffer, (uint32_t)n_sect * sectsz);
381
382	/* Set up the PRDT. */
383	for (i = 0; i < ahci->edds.num_used; ++i)
384	{
385	ahci->aPrdt[ahci->cur_prd].len = ahci->edds.u.sg[i].size - 1;
386	ahci->aPrdt[ahci->cur_prd].phys_addr = ahci->edds.u.sg[i].phys_addr;
387	++ahci->cur_prd;
388	}
389
390	#if DEBUG_AHCI
391	{
392	uint16_t prdt_idx;
393
394	for (prdt_idx = 0; prdt_idx < ahci->cur_prd; ++prdt_idx) {
395	DBG_AHCI("S/G entry %u: %5lu bytes @ %08lX\n", prdt_idx,
396	ahci->aPrdt[prdt_idx].len + 1, ahci->aPrdt[prdt_idx].phys_addr);
397	}
398	}
399	#endif
400
401	/* Build variable part of first command DWORD (reuses 'cmd'). */
402	if (cmd == AHCI_CMD_WRITE_DMA_EXT)
403	cmd = RT_BIT_32(6); /* Indicate a write to device. */
404	else if (cmd == ATA_CMD_PACKET) {
405	cmd \|= RT_BIT_32(5); /* Indicate ATAPI command. */
406	ahci->abCmd[3] \|= 1; /* DMA transfers. */
407	} else
408	cmd = 0;
409
410	cmd \|= 5; /* Five DWORDs. */
411
412	ahci_port_cmd_sync(ahci, cmd);
413
414	/* Examine operation status. */
415	d2h = (void __far *)&ahci->abFisRecv[0x40];
416	DBG_AHCI("AHCI: ERR=%02x, STAT=%02x, SCNT=%02x\n", d2h->error, d2h->status, d2h->sec_cn);
417
418	/* Unlock the buffer again. */
419	vds_free_sg_list(&ahci->edds);
420	return d2h->error ? 4 : 0;
421	}
422
423	/**
424	* Deinits the curent active port.
425	*/
426	static void ahci_port_deinit_current(ahci_t __far *ahci)
427	{
428	uint16_t io_base;
429	uint8_t port;
430
431	io_base = ahci->iobase;
432	port = ahci->cur_port;
433
434	if (port != 0xff)
435	{
436	/* Put the port into an idle state. */
437	ahci_ctrl_clear_bits(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
438	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
439
440	while (ahci_ctrl_is_bit_set(io_base, AHCI_PORT_REG(port, AHCI_REG_PORT_CMD),
441	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST \| AHCI_REG_PORT_CMD_FR \| AHCI_REG_PORT_CMD_CR) == 1)
442	{
443	DBG_AHCI("AHCI: Waiting for the port to idle\n");
444	}
445
446	/*
447	* Port idles, set up memory for commands and received FIS and program the
448	* address registers.
449	*/
450	/// @todo merge memsets?
451	_fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
452	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
453	_fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
454
455	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FB, 0);
456	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_FBU, 0);
457
458	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLB, 0);
459	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_CLBU, 0);
460
461	/* Disable all interrupts. */
462	VBOXAHCI_PORT_WRITE_REG(io_base, port, AHCI_REG_PORT_IE, 0);
463
464	ahci->cur_port = 0xff;
465	}
466	}
467
468	/**
469	* Brings a port into a minimal state to make device detection possible
470	* or to queue requests.
471	*/
472	static void ahci_port_init(ahci_t __far *ahci, uint8_t u8Port)
473	{
474	/* Deinit any other port first. */
475	ahci_port_deinit_current(ahci);
476
477	/* Put the port into an idle state. */
478	ahci_ctrl_clear_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
479	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST);
480
481	while (ahci_ctrl_is_bit_set(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
482	AHCI_REG_PORT_CMD_FRE \| AHCI_REG_PORT_CMD_ST \| AHCI_REG_PORT_CMD_FR \| AHCI_REG_PORT_CMD_CR) == 1)
483	{
484	DBG_AHCI("AHCI: Waiting for the port to idle\n");
485	}
486
487	/*
488	* Port idles, set up memory for commands and received FIS and program the
489	* address registers.
490	*/
491	/// @todo just one memset?
492	_fmemset(&ahci->aCmdHdr[0], 0, sizeof(ahci->aCmdHdr));
493	_fmemset(&ahci->abCmd[0], 0, sizeof(ahci->abCmd));
494	_fmemset(&ahci->abFisRecv[0], 0, sizeof(ahci->abFisRecv));
495
496	DBG_AHCI("AHCI: FIS receive area %lx from %x:%x\n",
497	ahci_addr_to_phys(&ahci->abFisRecv), FP_SEG(ahci->abFisRecv), FP_OFF(ahci->abFisRecv));
498	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FB, ahci_addr_to_phys(&ahci->abFisRecv));
499	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_FBU, 0);
500
501	DBG_AHCI("AHCI: CMD list area %lx\n", ahci_addr_to_phys(&ahci->aCmdHdr));
502	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLB, ahci_addr_to_phys(&ahci->aCmdHdr));
503	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_CLBU, 0);
504
505	/* Disable all interrupts. */
506	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IE, 0);
507	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_IS, 0xffffffff);
508	/* Clear all errors. */
509	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
510
511	ahci->cur_port = u8Port;
512	ahci->cur_prd = 0;
513	}
514
515	/**
516	* Read sectors from an attached AHCI device.
517	*
518	* @returns status code.
519	* @param bios_dsk Pointer to disk request packet (in the
520	* EBDA).
521	*/
522	int ahci_read_sectors(bio_dsk_t __far *bios_dsk)
523	{
524	uint16_t device_id;
525	uint16_t rc;
526
527	device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
528	if (device_id > BX_MAX_AHCI_DEVICES)
529	BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
530
531	DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
532	bios_dsk->drqp.nsect, bios_dsk->drqp.lba,
533	device_id, bios_dsk->ahcidev[device_id].port);
534
535	high_bits_save(bios_dsk->ahci_seg :> 0);
536	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
537	rc = ahci_cmd_data(bios_dsk, AHCI_CMD_READ_DMA_EXT);
538	DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
539	bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
540	#ifdef DMA_WORKAROUND
541	rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.nsect * 512 / 2);
542	#endif
543	high_bits_restore(bios_dsk->ahci_seg :> 0);
544	return rc;
545	}
546
547	/**
548	* Write sectors to an attached AHCI device.
549	*
550	* @returns status code.
551	* @param bios_dsk Pointer to disk request packet (in the
552	* EBDA).
553	*/
554	int ahci_write_sectors(bio_dsk_t __far *bios_dsk)
555	{
556	uint16_t device_id;
557	uint16_t rc;
558
559	device_id = VBOX_GET_AHCI_DEVICE(bios_dsk->drqp.dev_id);
560	if (device_id > BX_MAX_AHCI_DEVICES)
561	BX_PANIC("%s: device_id out of range %d\n", __func__, device_id);
562
563	DBG_AHCI("%s: %u sectors @ LBA 0x%llx, device %d, port %d\n", __func__,
564	bios_dsk->drqp.nsect, bios_dsk->drqp.lba, device_id,
565	bios_dsk->ahcidev[device_id].port);
566
567	high_bits_save(bios_dsk->ahci_seg :> 0);
568	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
569	rc = ahci_cmd_data(bios_dsk, AHCI_CMD_WRITE_DMA_EXT);
570	DBG_AHCI("%s: transferred %lu bytes\n", __func__, ((ahci_t __far *)(bios_dsk->ahci_seg :> 0))->aCmdHdr[1]);
571	bios_dsk->drqp.trsfsectors = bios_dsk->drqp.nsect;
572	high_bits_restore(bios_dsk->ahci_seg :> 0);
573	return rc;
574	}
575
576	/// @todo move
577	#define ATA_DATA_NO 0x00
578	#define ATA_DATA_IN 0x01
579	#define ATA_DATA_OUT 0x02
580
581	uint16_t ahci_cmd_packet(uint16_t device_id, uint8_t cmdlen, char __far *cmdbuf,
582	uint32_t length, uint8_t inout, char __far *buffer)
583	{
584	bio_dsk_t __far *bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
585	ahci_t __far *ahci;
586
587	/* Data out is currently not supported. */
588	if (inout == ATA_DATA_OUT) {
589	BX_INFO("%s: DATA_OUT not supported yet\n", __func__);
590	return 1;
591	}
592
593	/* Convert to AHCI specific device number. */
594	device_id = VBOX_GET_AHCI_DEVICE(device_id);
595
596	DBG_AHCI("%s: reading %lu bytes, device %d, port %d\n", __func__,
597	length, device_id, bios_dsk->ahcidev[device_id].port);
598	DBG_AHCI("%s: reading %u %u-byte sectors\n", __func__,
599	bios_dsk->drqp.nsect, bios_dsk->drqp.sect_sz);
600
601	bios_dsk->drqp.lba = length << 8; /// @todo xfer length limit
602	bios_dsk->drqp.buffer = buffer;
603	bios_dsk->drqp.nsect = length / bios_dsk->drqp.sect_sz;
604	// bios_dsk->drqp.sect_sz = 2048;
605
606	ahci = bios_dsk->ahci_seg :> 0;
607	high_bits_save(ahci);
608
609	ahci_port_init(bios_dsk->ahci_seg :> 0, bios_dsk->ahcidev[device_id].port);
610
611	/* Copy the ATAPI command where the HBA can fetch it. */
612	_fmemcpy(ahci->abAcmd, cmdbuf, cmdlen);
613
614	/* Reset transferred counts. */
615	/// @todo clear in calling code?
616	bios_dsk->drqp.trsfsectors = 0;
617	bios_dsk->drqp.trsfbytes = 0;
618
619	ahci_cmd_data(bios_dsk, ATA_CMD_PACKET);
620	DBG_AHCI("%s: transferred %lu bytes\n", __func__, ahci->aCmdHdr[1]);
621	bios_dsk->drqp.trsfbytes = ahci->aCmdHdr[1];
622	#ifdef DMA_WORKAROUND
623	rep_movsw(bios_dsk->drqp.buffer, bios_dsk->drqp.buffer, bios_dsk->drqp.trsfbytes / 2);
624	#endif
625	high_bits_restore(ahci);
626
627	return ahci->aCmdHdr[1] == 0 ? 4 : 0;
628	}
629
630	void ahci_port_detect_device(ahci_t __far *ahci, uint8_t u8Port)
631	{
632	uint32_t val;
633	bio_dsk_t __far *bios_dsk;
634	volatile uint32_t __far *ticks;
635	uint32_t end_tick;
636	int device_found = 0;
637
638	ahci_port_init(ahci, u8Port);
639
640	bios_dsk = read_word(0x0040, 0x000E) :> &EbdaData->bdisk;
641
642	/* Reset connection. */
643	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0x01);
644	/*
645	* According to the spec we should wait at least 1msec until the reset
646	* is cleared but this is a virtual controller so we don't have to.
647	*/
648	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SCTL, 0);
649
650	/*
651	* We do however have to wait for the device to initialize (the port reset
652	* to complete). That can take up to 10ms according to the SATA spec (device
653	* must send COMINIT within 10ms of COMRESET). We should be generous with
654	* the wait because in the typical case there are no ports without a device
655	* attached.
656	*/
657	ticks = MK_FP( 0x40, 0x6C );
658	end_tick = ticks + 3; / Wait up to five BIOS ticks, something in 150ms range. */
659
660	while( *ticks < end_tick )
661	{
662	/* If PxSSTS.DET is 3, everything went fine. */
663	VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SSTS, val);
664	if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 3) {
665	device_found = 1;
666	break;
667	}
668	}
669
670	/* Timed out, no device detected. */
671	if (!device_found) {
672	DBG_AHCI("AHCI: Timed out, no device detected on port %d\n", u8Port);
673	return;
674	}
675
676	if (ahci_ctrl_extract_bits(val, 0xfL, 0) == 0x3)
677	{
678	uint8_t abBuffer[0x0200];
679	uint8_t hdcount, devcount_ahci, hd_index;
680	uint8_t cdcount;
681	uint8_t removable;
682
683	/* Clear all errors after the reset. */
684	VBOXAHCI_PORT_WRITE_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SERR, 0xffffffff);
685
686	devcount_ahci = bios_dsk->ahci_devcnt;
687
688	DBG_AHCI("AHCI: Device detected on port %d\n", u8Port);
689
690	/// @todo Merge common HD/CDROM detection code
691	if (devcount_ahci < BX_MAX_AHCI_DEVICES)
692	{
693	/* Device detected, enable FIS receive. */
694	ahci_ctrl_set_bits(ahci->iobase, AHCI_PORT_REG(u8Port, AHCI_REG_PORT_CMD),
695	AHCI_REG_PORT_CMD_FRE);
696
697	/* Check signature to determine device type. */
698	VBOXAHCI_PORT_READ_REG(ahci->iobase, u8Port, AHCI_REG_PORT_SIG, val);
699	if (val == 0x101)
700	{
701	uint64_t sectors;
702	uint16_t cylinders, heads, spt;
703	chs_t lgeo;
704	uint8_t idxCmosChsBase;
705
706	DBG_AHCI("AHCI: Detected hard disk\n");
707
708	/* Identify device. */
709	bios_dsk->drqp.lba = 0;
710	bios_dsk->drqp.buffer = &abBuffer;
711	bios_dsk->drqp.nsect = 1;
712	bios_dsk->drqp.sect_sz = 512;
713	ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_DEVICE);
714
715	/* Calculate index into the generic device table. */
716	hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
717
718	removable = *(abBuffer+0) & 0x80 ? 1 : 0;
719	cylinders = (uint16_t )(abBuffer+(1*2)); // word 1
720	heads = (uint16_t )(abBuffer+(3*2)); // word 3
721	spt = (uint16_t )(abBuffer+(6*2)); // word 6
722	sectors = (uint32_t )(abBuffer+(60*2)); // word 60 and word 61
723
724	if (sectors == 0x0FFFFFFF) /* For disks bigger than ~128GB */
725	sectors = (uint64_t )(abBuffer+(100*2)); // words 100 to 103
726
727	DBG_AHCI("AHCI: 0x%llx sectors\n", sectors);
728
729	bios_dsk->ahcidev[devcount_ahci].port = u8Port;
730	bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
731	bios_dsk->devices[hd_index].device = DSK_DEVICE_HD;
732	bios_dsk->devices[hd_index].removable = removable;
733	bios_dsk->devices[hd_index].lock = 0;
734	bios_dsk->devices[hd_index].blksize = 512;
735	bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_LBA;
736	bios_dsk->devices[hd_index].sectors = sectors;
737
738	bios_dsk->devices[hd_index].pchs.heads = heads;
739	bios_dsk->devices[hd_index].pchs.cylinders = cylinders;
740	bios_dsk->devices[hd_index].pchs.spt = spt;
741
742	/* Get logical CHS geometry. */
743	switch (devcount_ahci)
744	{
745	case 0:
746	idxCmosChsBase = 0x40;
747	break;
748	case 1:
749	idxCmosChsBase = 0x48;
750	break;
751	case 2:
752	idxCmosChsBase = 0x50;
753	break;
754	case 3:
755	idxCmosChsBase = 0x58;
756	break;
757	default:
758	idxCmosChsBase = 0;
759	}
760	if (idxCmosChsBase && inb_cmos(idxCmosChsBase+7))
761	{
762	lgeo.cylinders = get_cmos_word(idxCmosChsBase /, idxCmosChsBase+1/);
763	lgeo.heads = inb_cmos(idxCmosChsBase + 2);
764	lgeo.spt = inb_cmos(idxCmosChsBase + 7);
765	}
766	else
767	set_geom_lba(&lgeo, sectors); /* Default EDD-style translated LBA geometry. */
768
769	BX_INFO("AHCI %d-P#%d: PCHS=%u/%u/%u LCHS=%u/%u/%u 0x%llx sectors\n", devcount_ahci,
770	u8Port, cylinders, heads, spt, lgeo.cylinders, lgeo.heads, lgeo.spt,
771	sectors);
772
773	bios_dsk->devices[hd_index].lchs = lgeo;
774
775	/* Store the ID of the disk in the BIOS hdidmap. */
776	hdcount = bios_dsk->hdcount;
777	bios_dsk->hdidmap[hdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
778	hdcount++;
779	bios_dsk->hdcount = hdcount;
780
781	/* Update hdcount in the BDA. */
782	hdcount = read_byte(0x40, 0x75);
783	hdcount++;
784	write_byte(0x40, 0x75, hdcount);
785	}
786	else if (val == 0xeb140101)
787	{
788	DBG_AHCI("AHCI: Detected ATAPI device\n");
789
790	/* Identify packet device. */
791	bios_dsk->drqp.lba = 0;
792	bios_dsk->drqp.buffer = &abBuffer;
793	bios_dsk->drqp.nsect = 1;
794	bios_dsk->drqp.sect_sz = 512;
795	ahci_cmd_data(bios_dsk, ATA_CMD_IDENTIFY_PACKET);
796
797	/* Calculate index into the generic device table. */
798	hd_index = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
799
800	removable = *(abBuffer+0) & 0x80 ? 1 : 0;
801
802	bios_dsk->ahcidev[devcount_ahci].port = u8Port;
803	bios_dsk->devices[hd_index].type = DSK_TYPE_AHCI;
804	bios_dsk->devices[hd_index].device = DSK_DEVICE_CDROM;
805	bios_dsk->devices[hd_index].removable = removable;
806	bios_dsk->devices[hd_index].blksize = 2048;
807	bios_dsk->devices[hd_index].translation = GEO_TRANSLATION_NONE;
808
809	/* Store the ID of the device in the BIOS cdidmap. */
810	cdcount = bios_dsk->cdcount;
811	bios_dsk->cdidmap[cdcount] = devcount_ahci + BX_MAX_ATA_DEVICES + BX_MAX_SCSI_DEVICES;
812	cdcount++;
813	bios_dsk->cdcount = cdcount;
814	}
815	else
816	DBG_AHCI("AHCI: Ignoring unknown device\n");
817
818	devcount_ahci++;
819	bios_dsk->ahci_devcnt = devcount_ahci;
820	}
821	else
822	DBG_AHCI("AHCI: Reached maximum device count, skipping\n");
823	}
824	}
825
826	/**
827	* Allocates 1K of conventional memory.
828	*/
829	static uint16_t ahci_mem_alloc(void)
830	{
831	uint16_t base_mem_kb;
832	uint16_t ahci_seg;
833
834	base_mem_kb = read_word(0x00, 0x0413);
835
836	DBG_AHCI("AHCI: %dK of base mem\n", base_mem_kb);
837
838	if (base_mem_kb == 0)
839	return 0;
840
841	base_mem_kb--; /* Allocate one block. */
842	ahci_seg = (((uint32_t)base_mem_kb * 1024) >> 4); /* Calculate start segment. */
843
844	write_word(0x00, 0x0413, base_mem_kb);
845
846	return ahci_seg;
847	}
848
849	/**
850	* Initializes the AHCI HBA and detects attached devices.
851	*/
852	static int ahci_hba_init(uint16_t io_base)
853	{
854	uint8_t i, cPorts;
855	uint32_t val;
856	uint16_t ebda_seg;
857	uint16_t ahci_seg;
858	bio_dsk_t __far *bios_dsk;
859	ahci_t __far *ahci;
860
861
862	ebda_seg = read_word(0x0040, 0x000E);
863	bios_dsk = ebda_seg :> &EbdaData->bdisk;
864
865	AHCI_READ_REG(io_base, AHCI_REG_VS, val);
866	DBG_AHCI("AHCI: Controller version: 0x%x (major) 0x%x (minor)\n",
867	ahci_ctrl_extract_bits(val, 0xffff0000, 16),
868	ahci_ctrl_extract_bits(val, 0x0000ffff, 0));
869
870	/* Allocate 1K of base memory. */
871	ahci_seg = ahci_mem_alloc();
872	if (ahci_seg == 0)
873	{
874	DBG_AHCI("AHCI: Could not allocate 1K of memory, can't boot from controller\n");
875	return 0;
876	}
877	DBG_AHCI("AHCI: ahci_seg=%04x, size=%04x, pointer at EBDA:%04x (EBDA size=%04x)\n",
878	ahci_seg, sizeof(ahci_t), (uint16_t)&EbdaData->bdisk.ahci_seg, sizeof(ebda_data_t));
879
880	bios_dsk->ahci_seg = ahci_seg;
881	bios_dsk->ahci_devcnt = 0;
882
883	ahci = ahci_seg :> 0;
884	ahci->cur_port = 0xff;
885	ahci->iobase = io_base;
886
887	/* Reset the controller. */
888	ahci_ctrl_set_bits(io_base, AHCI_REG_GHC, AHCI_GHC_HR);
889	do
890	{
891	AHCI_READ_REG(io_base, AHCI_REG_GHC, val);
892	} while ((val & AHCI_GHC_HR) != 0);
893
894	AHCI_READ_REG(io_base, AHCI_REG_CAP, val);
895	cPorts = ahci_ctrl_extract_bits(val, 0x1f, 0) + 1; /* Extract number of ports.*/
896
897	DBG_AHCI("AHCI: HBA has %u ports\n", cPorts);
898
899	/* Go through the ports. */
900	i = 0;
901	while (i < 32)
902	{
903	if (ahci_ctrl_is_bit_set(io_base, AHCI_REG_PI, RT_BIT_32(i)) != 0)
904	{
905	DBG_AHCI("AHCI: Port %u is present\n", i);
906	ahci_port_detect_device(ahci_seg :> 0, i);
907	cPorts--;
908	if (cPorts == 0)
909	break;
910	}
911	i++;
912	}
913
914	return 0;
915	}
916
917	/**
918	* Init the AHCI driver and detect attached disks.
919	*/
920	void BIOSCALL ahci_init(void)
921	{
922	uint16_t busdevfn;
923
924	busdevfn = pci_find_classcode(0x00010601);
925	if (busdevfn != VBOX_AHCI_NO_DEVICE)
926	{
927	uint8_t u8Bus, u8DevFn;
928	uint8_t u8PciCapOff;
929
930	u8Bus = (busdevfn & 0xff00) >> 8;
931	u8DevFn = busdevfn & 0x00ff;
932
933	DBG_AHCI("AHCI HBA at Bus %u DevFn 0x%x (raw 0x%x)\n", u8Bus, u8DevFn, busdevfn);
934
935	/* Examine the capability list and search for the Serial ATA Capability Register. */
936	u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, PCI_CONFIG_CAP);
937
938	while (u8PciCapOff != 0)
939	{
940	uint8_t u8PciCapId = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
941
942	DBG_AHCI("Capability ID 0x%x at 0x%x\n", u8PciCapId, u8PciCapOff);
943
944	if (u8PciCapId == PCI_CAP_ID_SATACR)
945	break;
946
947	/* Go on to the next capability. */
948	u8PciCapOff = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff + 1);
949	}
950
951	if (u8PciCapOff != 0)
952	{
953	uint8_t u8Rev;
954
955	DBG_AHCI("AHCI HBA with SATA Capability register at 0x%x\n", u8PciCapOff);
956
957	/* Advance to the stuff behind the id and next capability pointer. */
958	u8PciCapOff += 2;
959
960	u8Rev = pci_read_config_byte(u8Bus, u8DevFn, u8PciCapOff);
961	if (u8Rev == 0x10)
962	{
963	/* Read the SATACR1 register and get the bar and offset of the index/data pair register. */
964	uint8_t u8Bar = 0x00;
965	uint16_t u16Off = 0x00;
966	uint16_t u16BarOff = pci_read_config_word(u8Bus, u8DevFn, u8PciCapOff + 2);
967
968	DBG_AHCI("SATACR1: 0x%x\n", u16BarOff);
969
970	switch (u16BarOff & 0xf)
971	{
972	case 0x04:
973	u8Bar = 0x10;
974	break;
975	case 0x05:
976	u8Bar = 0x14;
977	break;
978	case 0x06:
979	u8Bar = 0x18;
980	break;
981	case 0x07:
982	u8Bar = 0x1c;
983	break;
984	case 0x08:
985	u8Bar = 0x20;
986	break;
987	case 0x09:
988	u8Bar = 0x24;
989	break;
990	case 0x0f:
991	default:
992	/* Reserved or unsupported. */
993	DBG_AHCI("BAR 0x%x unsupported\n", u16BarOff & 0xf);
994	}
995
996	/* Get the offset inside the BAR from bits 4:15. */
997	u16Off = (u16BarOff >> 4) * 4;
998
999	if (u8Bar != 0x00)
1000	{
1001	uint32_t u32Bar = pci_read_config_dword(u8Bus, u8DevFn, u8Bar);
1002
1003	DBG_AHCI("BAR at 0x%x : 0x%x\n", u8Bar, u32Bar);
1004
1005	if ((u32Bar & 0x01) != 0)
1006	{
1007	int rc;
1008	uint16_t u16AhciIoBase = (u32Bar & 0xfff0) + u16Off;
1009
1010	/* Enable PCI memory, I/O, bus mastering access in command register. */
1011	pci_write_config_word(u8Bus, u8DevFn, 4, 0x7);
1012
1013	DBG_AHCI("I/O base: 0x%x\n", u16AhciIoBase);
1014	rc = ahci_hba_init(u16AhciIoBase);
1015	}
1016	else
1017	DBG_AHCI("BAR is MMIO\n");
1018	}
1019	}
1020	else
1021	DBG_AHCI("Invalid revision 0x%x\n", u8Rev);
1022	}
1023	else
1024	DBG_AHCI("AHCI HBA with no usable Index/Data register pair!\n");
1025	}
1026	else
1027	DBG_AHCI("No AHCI HBA!\n");
1028	}

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source: vbox/trunk/src/VBox/Devices/PC/BIOS/ahci.c@ 104068

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