VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 19167

Last change on this file since 19167 was 19007, checked in by vboxsync, 16 years ago

Main: centralized control for extended device profiles, ACPI cleanup
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 75.6 KB
Line 
1/* $Id: DevACPI.cpp 19007 2009-04-18 08:07:59Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43/* the compiled DSL */
44#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
45# include <vboxaml.hex>
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57#define PM1a_EVT_BLK 0x00004000
58#define PM1b_EVT_BLK 0x00000000 /**< not supported */
59#define PM1a_CTL_BLK 0x00004004
60#define PM1b_CTL_BLK 0x00000000 /**< not supported */
61#define PM2_CTL_BLK 0x00000000 /**< not supported */
62#define PM_TMR_BLK 0x00004008
63#define GPE0_BLK 0x00004020
64#define GPE1_BLK 0x00000000 /**< not supported */
65#define BAT_INDEX 0x00004040
66#define BAT_DATA 0x00004044
67#define SYSI_INDEX 0x00004048
68#define SYSI_DATA 0x0000404c
69#define ACPI_RESET_BLK 0x00004050
70
71/* PM1x status register bits */
72#define TMR_STS RT_BIT(0)
73#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
74#define BM_STS RT_BIT(4)
75#define GBL_STS RT_BIT(5)
76#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
77#define PWRBTN_STS RT_BIT(8)
78#define SLPBTN_STS RT_BIT(9)
79#define RTC_STS RT_BIT(10)
80#define IGN_STS RT_BIT(11)
81#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
82#define WAK_STS RT_BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN RT_BIT(0)
87#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
88#define GBL_EN RT_BIT(5)
89#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
90#define PWRBTN_EN RT_BIT(8)
91#define SLPBTN_EN RT_BIT(9)
92#define RTC_EN RT_BIT(10)
93#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN RT_BIT(0)
99#define BM_RLD RT_BIT(1)
100#define GBL_RLS RT_BIT(2)
101#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
102#define IGN_CNT RT_BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN RT_BIT(13)
106#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
136 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
137 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
138 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
139 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
140 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
141 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
142 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
143 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
144 SYSTEM_INFO_INDEX_END = 11,
145 SYSTEM_INFO_INDEX_INVALID = 0x80,
146 SYSTEM_INFO_INDEX_VALID = 0x200
147};
148
149#define AC_OFFLINE 0
150#define AC_ONLINE 1
151
152#define BAT_TECH_PRIMARY 1
153#define BAT_TECH_SECONDARY 2
154
155#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
156#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
157#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
158#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
159#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
160
161
162/*******************************************************************************
163* Structures and Typedefs *
164*******************************************************************************/
165/**
166 * The ACPI device state.
167 */
168typedef struct ACPIState
169{
170 PCIDevice dev;
171 uint16_t pm1a_en;
172 uint16_t pm1a_sts;
173 uint16_t pm1a_ctl;
174 /** Number of logical CPUs in guest */
175 uint16_t cCpus;
176 int64_t pm_timer_initial;
177 PTMTIMERR3 tsR3;
178 PTMTIMERR0 tsR0;
179 PTMTIMERRC tsRC;
180
181 uint32_t gpe0_en;
182 uint32_t gpe0_sts;
183
184 unsigned int uBatteryIndex;
185 uint32_t au8BatteryInfo[13];
186
187 unsigned int uSystemInfoIndex;
188 uint64_t u64RamSize;
189 /** The number of bytes above 4GB. */
190 uint64_t cbRamHigh;
191 /** The number of bytes below 4GB. */
192 uint32_t cbRamLow;
193
194 /** Current ACPI S* state. We support S0 and S5 */
195 uint32_t uSleepState;
196 uint8_t au8RSDPPage[0x1000];
197 /** This is a workaround for incorrect index field handling by Intels ACPICA.
198 * The system info _INI method writes to offset 0x200. We either observe a
199 * write request to index 0x80 (in that case we don't change the index) or a
200 * write request to offset 0x200 (in that case we divide the index value by
201 * 4. Note that the _STA method is sometimes called prior to the _INI method
202 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
203 * acpiBatIndexWrite() for handling this. */
204 uint8_t u8IndexShift;
205 /** provide an I/O-APIC */
206 uint8_t u8UseIOApic;
207 /** provide a floppy controller */
208 bool fUseFdc;
209 /** If High Precision Event Timer device should be supported */
210 bool fUseHpet;
211 /** If System Management Controller device should be supported */
212 bool fUseSmc;
213 /** the guest handled the last power button event */
214 bool fPowerButtonHandled;
215 /** If ACPI CPU device should be shown */
216 bool fShowCpu;
217 /** If Real Time Clock ACPI object to be shown */
218 bool fShowRtc;
219 /** Aligning IBase. */
220 bool afAlignment[5];
221
222 /** ACPI port base interface. */
223 PDMIBASE IBase;
224 /** ACPI port interface. */
225 PDMIACPIPORT IACPIPort;
226 /** Pointer to the device instance. */
227 PPDMDEVINSR3 pDevIns;
228 /** Pointer to the driver base interface */
229 R3PTRTYPE(PPDMIBASE) pDrvBase;
230 /** Pointer to the driver connector interface */
231 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
232} ACPIState;
233
234#pragma pack(1)
235
236/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
237struct ACPIGENADDR
238{
239 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
240 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
241 uint8_t u8RegisterBitOffset; /**< bit offset of register */
242 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
243 uint64_t u64Address; /**< 64-bit address of register */
244};
245AssertCompileSize(ACPIGENADDR, 12);
246
247/** Root System Description Pointer */
248struct ACPITBLRSDP
249{
250 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
251 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
252 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
253 uint8_t u8Revision; /**< revision number, currently 2 */
254#define ACPI_REVISION 2 /**< ACPI 3.0 */
255 uint32_t u32RSDT; /**< phys addr of RSDT */
256 uint32_t u32Length; /**< bytes of this table */
257 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
258 uint8_t u8ExtChecksum; /**< checksum of entire table */
259 uint8_t u8Reserved[3]; /**< reserved */
260};
261AssertCompileSize(ACPITBLRSDP, 36);
262
263/** System Description Table Header */
264struct ACPITBLHEADER
265{
266 uint8_t au8Signature[4]; /**< table identifier */
267 uint32_t u32Length; /**< length of the table including header */
268 uint8_t u8Revision; /**< revision number */
269 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
270 uint8_t au8OemId[6]; /**< OEM-supplied string */
271 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
272 uint32_t u32OemRevision; /**< OEM-supplied revision number */
273 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
274 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
275};
276AssertCompileSize(ACPITBLHEADER, 36);
277
278/** Root System Description Table */
279struct ACPITBLRSDT
280{
281 ACPITBLHEADER header;
282 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
283};
284AssertCompileSize(ACPITBLRSDT, 40);
285
286/** Extended System Description Table */
287struct ACPITBLXSDT
288{
289 ACPITBLHEADER header;
290 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
291};
292AssertCompileSize(ACPITBLXSDT, 44);
293
294/** Fixed ACPI Description Table */
295struct ACPITBLFADT
296{
297 ACPITBLHEADER header;
298 uint32_t u32FACS; /**< phys. address of FACS */
299 uint32_t u32DSDT; /**< phys. address of DSDT */
300 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
301#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
302#define INT_MODEL_MULTIPLE_APIC 2
303 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
304 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
305#define SCI_INT 9
306 uint32_t u32SMICmd; /**< system port address of SMI command port */
307#define SMI_CMD 0x0000442e
308 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
309#define ACPI_ENABLE 0xa1
310 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
311#define ACPI_DISABLE 0xa0
312 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
313 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
314 state control responsibility */
315 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
316 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
317 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
318 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
319 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
320 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
321 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
322 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
323 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
324 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
325 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
326 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
327 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
328#define GPE0_BLK_LEN 2
329 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
330#define GPE1_BLK_LEN 0
331 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
332#define GPE1_BASE 0
333 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
334 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
335#define P_LVL2_LAT 101 /**< C2 state not supported */
336 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
337#define P_LVL3_LAT 1001 /**< C3 state not supported */
338 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
339 lines from any processors memory caches */
340#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
341 uint16_t u16FlushStride; /**< cache line width */
342#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
343 uint8_t u8DutyOffset;
344 uint8_t u8DutyWidth;
345 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
346 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
347 uint8_t u8Century; /**< RTC CMOS RAM index of century */
348 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
349#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
350 (COM too?) */
351#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
352#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
353 uint8_t u8Must0_0; /**< must be 0 */
354 uint32_t u32Flags; /**< fixed feature flags */
355#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
356#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
357#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
358#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
359#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
360#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
361#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
362#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
363#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
364#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
365#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
366#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
367#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
368#define FADT_FL_CPU_SW_SLP RT_BIT(13)
369#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
370#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
371#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
372#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
373#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
374#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
375 ACPIGENADDR ResetReg; /**< ext addr of reset register */
376 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
377#define ACPI_RESET_REG_VAL 0x10
378 uint8_t au8Must0_1[3]; /**< must be 0 */
379 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
380 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
381 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
382 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
383 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
384 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
385 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
386 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
387 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
388 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
389};
390AssertCompileSize(ACPITBLFADT, 244);
391
392/** Firmware ACPI Control Structure */
393struct ACPITBLFACS
394{
395 uint8_t au8Signature[4]; /**< 'FACS' */
396 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
397 uint32_t u32HWSignature; /**< systems HW signature at last boot */
398 uint32_t u32FWVector; /**< address of waking vector */
399 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
400 uint32_t u32Flags; /**< FACS flags */
401 uint64_t u64X_FWVector; /**< 64-bit waking vector */
402 uint8_t u8Version; /**< version of this table */
403 uint8_t au8Reserved[31]; /**< zero */
404};
405AssertCompileSize(ACPITBLFACS, 64);
406
407/** Processor Local APIC Structure */
408struct ACPITBLLAPIC
409{
410 uint8_t u8Type; /**< 0 = LAPIC */
411 uint8_t u8Length; /**< 8 */
412 uint8_t u8ProcId; /**< processor ID */
413 uint8_t u8ApicId; /**< local APIC ID */
414 uint32_t u32Flags; /**< Flags */
415#define LAPIC_ENABLED 0x1
416};
417AssertCompileSize(ACPITBLLAPIC, 8);
418
419/** I/O APIC Structure */
420struct ACPITBLIOAPIC
421{
422 uint8_t u8Type; /**< 1 == I/O APIC */
423 uint8_t u8Length; /**< 12 */
424 uint8_t u8IOApicId; /**< I/O APIC ID */
425 uint8_t u8Reserved; /**< 0 */
426 uint32_t u32Address; /**< phys address to access I/O APIC */
427 uint32_t u32GSIB; /**< global system interrupt number to start */
428};
429AssertCompileSize(ACPITBLIOAPIC, 12);
430
431# ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
432
433# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
434
435/**
436 * Multiple APIC Description Table.
437 *
438 * This structure looks somewhat convoluted due layout of MADT table in MP case.
439 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
440 * use regular C structure and proxy to raw memory instead.
441 */
442class AcpiTableMADT
443{
444 /**
445 * All actual data stored in dynamically allocated memory pointed by this field.
446 */
447 uint8_t *m_pbData;
448 /**
449 * Number of CPU entries in this MADT.
450 */
451 uint32_t m_cCpus;
452
453public:
454 /**
455 * Address of ACPI header
456 */
457 inline ACPITBLHEADER *header_addr(void) const
458 {
459 return (ACPITBLHEADER *)m_pbData;
460 }
461
462 /**
463 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
464 * although address is the same for all of them.
465 */
466 inline uint32_t *u32LAPIC_addr(void) const
467 {
468 return (uint32_t *)(header_addr() + 1);
469 }
470
471 /**
472 * Address of APIC flags
473 */
474 inline uint32_t *u32Flags_addr(void) const
475 {
476 return (uint32_t *)(u32LAPIC_addr() + 1);
477 }
478
479 /**
480 * Address of per-CPU LAPIC descriptions
481 */
482 inline ACPITBLLAPIC *LApics_addr(void) const
483 {
484 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
485 }
486
487 /**
488 * Address of IO APIC description
489 */
490 inline ACPITBLIOAPIC *IOApic_addr(void) const
491 {
492 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
493 }
494
495 /**
496 * Size of MADT.
497 * Note that this function assumes IOApic to be the last field in structure.
498 */
499 inline uint32_t size(void) const
500 {
501 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
502 }
503
504 /**
505 * Raw data of MADT.
506 */
507 inline const uint8_t *data(void) const
508 {
509 return m_pbData;
510 }
511
512 /**
513 * Size of MADT for given ACPI config, useful to compute layout.
514 */
515 static uint32_t sizeFor(ACPIState *s)
516 {
517 return AcpiTableMADT(s->cCpus).size();
518 }
519
520 /*
521 * Constructor, only works in Ring 3, doesn't look like a big deal.
522 */
523 AcpiTableMADT(uint32_t cCpus)
524 {
525 m_cCpus = cCpus;
526 uint32_t cb = size();
527 m_pbData = (uint8_t *)RTMemAllocZ(cb);
528 }
529
530 ~AcpiTableMADT()
531 {
532 RTMemFree(m_pbData);
533 }
534};
535# endif /* IN_RING3 */
536
537#pragma pack()
538
539
540#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
541/*******************************************************************************
542* Internal Functions *
543*******************************************************************************/
544__BEGIN_DECLS
545PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
546#ifdef IN_RING3
547PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
548PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
549PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
550PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
551PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
552PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
553PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
554PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
555PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
556PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
557PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
558PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
559PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
560PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
561PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
562PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
563# ifdef DEBUG_ACPI
564PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
565PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
566# endif
567#endif /* IN_RING3 */
568__END_DECLS
569
570
571#ifdef IN_RING3
572
573/* Simple acpiChecksum: all the bytes must add up to 0. */
574static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
575{
576 uint8_t sum = 0;
577 for (size_t i = 0; i < len; ++i)
578 sum += data[i];
579 return -sum;
580}
581
582static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
583 uint32_t u32Length, uint8_t u8Revision)
584{
585 memcpy(header->au8Signature, au8Signature, 4);
586 header->u32Length = RT_H2LE_U32(u32Length);
587 header->u8Revision = u8Revision;
588 memcpy(header->au8OemId, "VBOX ", 6);
589 memcpy(header->au8OemTabId, "VBOX", 4);
590 memcpy(header->au8OemTabId+4, au8Signature, 4);
591 header->u32OemRevision = RT_H2LE_U32(1);
592 memcpy(header->au8CreatorId, "ASL ", 4);
593 header->u32CreatorRev = RT_H2LE_U32(0x61);
594}
595
596static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
597 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
598 uint8_t u8AccessSize, uint64_t u64Address)
599{
600 g->u8AddressSpaceId = u8AddressSpaceId;
601 g->u8RegisterBitWidth = u8RegisterBitWidth;
602 g->u8RegisterBitOffset = u8RegisterBitOffset;
603 g->u8AccessSize = u8AccessSize;
604 g->u64Address = RT_H2LE_U64(u64Address);
605}
606
607static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
608{
609 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
610}
611
612/** Differentiated System Description Table (DSDT) */
613static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr)
614{
615 acpiPhyscpy(s, addr, AmlCode, sizeof(AmlCode));
616}
617
618/** Firmware ACPI Control Structure (FACS) */
619static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
620{
621 ACPITBLFACS facs;
622
623 memset(&facs, 0, sizeof(facs));
624 memcpy(facs.au8Signature, "FACS", 4);
625 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
626 facs.u32HWSignature = RT_H2LE_U32(0);
627 facs.u32FWVector = RT_H2LE_U32(0);
628 facs.u32GlobalLock = RT_H2LE_U32(0);
629 facs.u32Flags = RT_H2LE_U32(0);
630 facs.u64X_FWVector = RT_H2LE_U64(0);
631 facs.u8Version = 1;
632
633 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
634}
635
636/** Fixed ACPI Description Table (FADT aka FACP) */
637static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
638{
639 ACPITBLFADT fadt;
640
641 memset(&fadt, 0, sizeof(fadt));
642 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
643 fadt.u32FACS = RT_H2LE_U32(facs_addr);
644 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
645 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
646 fadt.u8PreferredPMProfile = 0; /* unspecified */
647 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
648 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
649 fadt.u8AcpiEnable = ACPI_ENABLE;
650 fadt.u8AcpiDisable = ACPI_DISABLE;
651 fadt.u8S4BIOSReq = 0;
652 fadt.u8PStateCnt = 0;
653 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
654 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
655 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
656 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
657 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
658 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
659 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
660 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
661 fadt.u8PM1EVTLEN = 4;
662 fadt.u8PM1CTLLEN = 2;
663 fadt.u8PM2CTLLEN = 0;
664 fadt.u8PMTMLEN = 4;
665 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
666 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
667 fadt.u8GPE1BASE = GPE1_BASE;
668 fadt.u8CSTCNT = 0;
669 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
670 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
671 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
672 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
673 fadt.u8DutyOffset = 0;
674 fadt.u8DutyWidth = 0;
675 fadt.u8DayAlarm = 0;
676 fadt.u8MonAlarm = 0;
677 fadt.u8Century = 0;
678 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
679 /** @note WBINVD is required for ACPI versions newer than 1.0 */
680 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
681 | FADT_FL_FIX_RTC
682 | FADT_FL_TMR_VAL_EXT);
683 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
684 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
685 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
686 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
687 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
688 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
689 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
690 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
691 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
692 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
693 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
694 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
695 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
696 acpiPhyscpy(s, addr, &fadt, sizeof(fadt));
697}
698
699/**
700 * Root System Description Table.
701 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
702 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
703 */
704static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
705{
706 ACPITBLRSDT *rsdt;
707 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
708
709 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
710 if (!rsdt)
711 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
712
713 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
714 for (unsigned int i = 0; i < nb_entries; ++i)
715 {
716 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
717 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
718 }
719 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
720 acpiPhyscpy(s, addr, rsdt, size);
721 RTMemFree(rsdt);
722 return VINF_SUCCESS;
723}
724
725/** Extended System Description Table. */
726static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
727{
728 ACPITBLXSDT *xsdt;
729 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
730
731 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
732 if (!xsdt)
733 return VERR_NO_TMP_MEMORY;
734
735 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
736 for (unsigned int i = 0; i < nb_entries; ++i)
737 {
738 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
739 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
740 }
741 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
742 acpiPhyscpy(s, addr, xsdt, size);
743 RTMemFree(xsdt);
744 return VINF_SUCCESS;
745}
746
747/** Root System Description Pointer (RSDP) */
748static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
749{
750 memset(rsdp, 0, sizeof(*rsdp));
751
752 /* ACPI 1.0 part (RSDT */
753 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
754 memcpy(rsdp->au8OemId, "VBOX ", 6);
755 rsdp->u8Revision = ACPI_REVISION;
756 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
757 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
758
759 /* ACPI 2.0 part (XSDT) */
760 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
761 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
762 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
763}
764
765/**
766 * Multiple APIC Description Table.
767 *
768 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
769 *
770 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
771 */
772static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
773{
774 uint16_t cpus = s->cCpus;
775 AcpiTableMADT madt(cpus);
776
777 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
778
779 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
780 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
781
782 ACPITBLLAPIC* lapic = madt.LApics_addr();
783 for (uint16_t i = 0; i < cpus; i++)
784 {
785 lapic->u8Type = 0;
786 lapic->u8Length = sizeof(ACPITBLLAPIC);
787 lapic->u8ProcId = i;
788 lapic->u8ApicId = i;
789 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
790 lapic++;
791 }
792
793 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
794
795 ioapic->u8Type = 1;
796 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
797 ioapic->u8IOApicId = cpus;
798 ioapic->u8Reserved = 0;
799 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
800 ioapic->u32GSIB = RT_H2LE_U32(0);
801
802 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
803 acpiPhyscpy(s, addr, madt.data(), madt.size());
804}
805
806/* SCI IRQ */
807DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
808{
809 if (s->pm1a_ctl & SCI_EN)
810 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
811}
812
813DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
814{
815 return en & ~(RSR_EN | IGN_EN);
816}
817
818DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
819{
820 return sts & ~(RSR_STS | IGN_STS);
821}
822
823DECLINLINE(int) pm1a_level(ACPIState *s)
824{
825 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
826}
827
828DECLINLINE(int) gpe0_level(ACPIState *s)
829{
830 return (s->gpe0_en & s->gpe0_sts) != 0;
831}
832
833static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
834{
835 int old_level, new_level;
836
837 if (gpe0_level(s))
838 return;
839
840 old_level = pm1a_level(s);
841 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
842
843 s->pm1a_en = en;
844 s->pm1a_sts = sts;
845
846 if (new_level != old_level)
847 acpiSetIrq(s, new_level);
848}
849
850static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
851{
852 int old_level, new_level;
853
854 if (pm1a_level(s))
855 return;
856
857 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
858 new_level = (en & sts) != 0;
859
860 s->gpe0_en = en;
861 s->gpe0_sts = sts;
862
863 if (new_level != old_level)
864 acpiSetIrq(s, new_level);
865}
866
867static int acpiPowerDown(ACPIState *s)
868{
869 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
870 if (RT_FAILURE(rc))
871 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
872 return rc;
873}
874
875/** Converts a ACPI port interface pointer to an ACPI state pointer. */
876#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
877
878/**
879 * Send an ACPI power off event.
880 *
881 * @returns VBox status code
882 * @param pInterface Pointer to the interface structure containing the called function pointer.
883 */
884static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
885{
886 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
887 s->fPowerButtonHandled = false;
888 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
889 return VINF_SUCCESS;
890}
891
892/**
893 * Check if the ACPI power button event was handled.
894 *
895 * @returns VBox status code
896 * @param pInterface Pointer to the interface structure containing the called function pointer.
897 * @param pfHandled Return true if the power button event was handled by the guest.
898 */
899static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
900{
901 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
902 *pfHandled = s->fPowerButtonHandled;
903 return VINF_SUCCESS;
904}
905
906/**
907 * Check if the Guest entered into G0 (working) or G1 (sleeping).
908 *
909 * @returns VBox status code
910 * @param pInterface Pointer to the interface structure containing the called function pointer.
911 * @param pfEntered Return true if the guest entered the ACPI mode.
912 */
913static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
914{
915 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
916 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
917 return VINF_SUCCESS;
918}
919
920/**
921 * Send an ACPI sleep button event.
922 *
923 * @returns VBox status code
924 * @param pInterface Pointer to the interface structure containing the called function pointer.
925 */
926static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
927{
928 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
929 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
930 return VINF_SUCCESS;
931}
932
933/* PM1a_EVT_BLK enable */
934static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
935{
936 uint16_t val = s->pm1a_en;
937 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
938 return val;
939}
940
941static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
942{
943 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
944 val &= ~(RSR_EN | IGN_EN);
945 update_pm1a(s, s->pm1a_sts, val);
946}
947
948/* PM1a_EVT_BLK status */
949static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
950{
951 uint16_t val = s->pm1a_sts;
952 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
953 return val;
954}
955
956static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
957{
958 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
959 if (val & PWRBTN_STS)
960 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
961 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
962 update_pm1a(s, val, s->pm1a_en);
963}
964
965/* PM1a_CTL_BLK */
966static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
967{
968 uint16_t val = s->pm1a_ctl;
969 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
970 return val;
971}
972
973static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
974{
975 uint32_t uSleepState;
976
977 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
978 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
979
980 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
981 if (uSleepState != s->uSleepState)
982 {
983 s->uSleepState = uSleepState;
984 switch (uSleepState)
985 {
986 case 0x00: /* S0 */
987 break;
988 case 0x05: /* S5 */
989 LogRel(("Entering S5 (power down)\n"));
990 return acpiPowerDown(s);
991 default:
992 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
993 break;
994 }
995 }
996 return VINF_SUCCESS;
997}
998
999/* GPE0_BLK */
1000static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1001{
1002 uint8_t val = s->gpe0_en;
1003 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1004 return val;
1005}
1006
1007static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1008{
1009 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1010 update_gpe0(s, s->gpe0_sts, val);
1011}
1012
1013static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1014{
1015 uint8_t val = s->gpe0_sts;
1016 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1017 return val;
1018}
1019
1020static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1021{
1022 val = s->gpe0_sts & ~val;
1023 update_gpe0(s, val, s->gpe0_en);
1024 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1025}
1026
1027static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1028{
1029 int rc = VINF_SUCCESS;
1030
1031 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1032 if (val == ACPI_RESET_REG_VAL)
1033 {
1034# ifndef IN_RING3
1035 rc = VINF_IOM_HC_IOPORT_WRITE;
1036# else /* IN_RING3 */
1037 rc = PDMDevHlpVMReset(s->pDevIns);
1038# endif /* !IN_RING3 */
1039 }
1040 return rc;
1041}
1042
1043/* SMI */
1044static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1045{
1046 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1047 if (val == ACPI_ENABLE)
1048 s->pm1a_ctl |= SCI_EN;
1049 else if (val == ACPI_DISABLE)
1050 s->pm1a_ctl &= ~SCI_EN;
1051 else
1052 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1053}
1054
1055static uint32_t find_rsdp_space(void)
1056{
1057 return 0xe0000;
1058}
1059
1060static void acpiPMTimerReset(ACPIState *s)
1061{
1062 uint64_t interval, freq;
1063
1064 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1065 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1066 Log(("interval = %RU64\n", interval));
1067 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1068}
1069
1070static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1071{
1072 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1073
1074 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1075 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1076 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1077
1078 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1079 acpiPMTimerReset(s);
1080}
1081
1082/**
1083 * _BST method.
1084 */
1085static void acpiFetchBatteryStatus(ACPIState *s)
1086{
1087 uint32_t *p = s->au8BatteryInfo;
1088 bool fPresent; /* battery present? */
1089 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1090 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1091 uint32_t hostPresentRate; /* 0..1000 */
1092 int rc;
1093
1094 if (!s->pDrv)
1095 return;
1096 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1097 &hostBatteryState, &hostPresentRate);
1098 AssertRC(rc);
1099
1100 /* default values */
1101 p[BAT_STATUS_STATE] = hostBatteryState;
1102 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1103 : hostPresentRate * 50; /* mW */
1104 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1105 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1106
1107 /* did we get a valid battery state? */
1108 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1109 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1110 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1111 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1112}
1113
1114/**
1115 * _BIF method.
1116 */
1117static void acpiFetchBatteryInfo(ACPIState *s)
1118{
1119 uint32_t *p = s->au8BatteryInfo;
1120
1121 p[BAT_INFO_UNITS] = 0; /* mWh */
1122 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1123 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1124 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1125 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1126 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1127 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1128 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1129 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1130}
1131
1132/**
1133 * _STA method.
1134 */
1135static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1136{
1137 bool fPresent; /* battery present? */
1138 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1139 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1140 uint32_t hostPresentRate; /* 0..1000 */
1141 int rc;
1142
1143 if (!s->pDrv)
1144 return 0;
1145 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1146 &hostBatteryState, &hostPresentRate);
1147 AssertRC(rc);
1148
1149 return fPresent
1150 ? STA_DEVICE_PRESENT_MASK /* present */
1151 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1152 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1153 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1154 | STA_BATTERY_PRESENT_MASK /* battery is present */
1155 : 0; /* device not present */
1156}
1157
1158static uint32_t acpiGetPowerSource(ACPIState *s)
1159{
1160 PDMACPIPOWERSOURCE ps;
1161
1162 /* query the current power source from the host driver */
1163 if (!s->pDrv)
1164 return AC_ONLINE;
1165 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1166 AssertRC(rc);
1167 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1168}
1169
1170PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1171{
1172 ACPIState *s = (ACPIState *)pvUser;
1173
1174 switch (cb)
1175 {
1176 case 4:
1177 u32 >>= s->u8IndexShift;
1178 /* see comment at the declaration of u8IndexShift */
1179 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1180 {
1181 s->u8IndexShift = 2;
1182 u32 >>= 2;
1183 }
1184 Assert(u32 < BAT_INDEX_LAST);
1185 s->uBatteryIndex = u32;
1186 break;
1187 default:
1188 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1189 break;
1190 }
1191 return VINF_SUCCESS;
1192}
1193
1194PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1195{
1196 ACPIState *s = (ACPIState *)pvUser;
1197
1198 switch (cb)
1199 {
1200 case 4:
1201 switch (s->uBatteryIndex)
1202 {
1203 case BAT_STATUS_STATE:
1204 acpiFetchBatteryStatus(s);
1205 case BAT_STATUS_PRESENT_RATE:
1206 case BAT_STATUS_REMAINING_CAPACITY:
1207 case BAT_STATUS_PRESENT_VOLTAGE:
1208 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1209 break;
1210
1211 case BAT_INFO_UNITS:
1212 acpiFetchBatteryInfo(s);
1213 case BAT_INFO_DESIGN_CAPACITY:
1214 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1215 case BAT_INFO_TECHNOLOGY:
1216 case BAT_INFO_DESIGN_VOLTAGE:
1217 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1218 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1219 case BAT_INFO_CAPACITY_GRANULARITY_1:
1220 case BAT_INFO_CAPACITY_GRANULARITY_2:
1221 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1222 break;
1223
1224 case BAT_DEVICE_STATUS:
1225 *pu32 = acpiGetBatteryDeviceStatus(s);
1226 break;
1227
1228 case BAT_POWER_SOURCE:
1229 *pu32 = acpiGetPowerSource(s);
1230 break;
1231
1232 default:
1233 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1234 break;
1235 }
1236 break;
1237 default:
1238 return VERR_IOM_IOPORT_UNUSED;
1239 }
1240 return VINF_SUCCESS;
1241}
1242
1243PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1244{
1245 ACPIState *s = (ACPIState *)pvUser;
1246
1247 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1248 switch (cb)
1249 {
1250 case 4:
1251 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1252 s->uSystemInfoIndex = u32;
1253 else
1254 {
1255 /* see comment at the declaration of u8IndexShift */
1256 if (s->u8IndexShift == 0)
1257 {
1258 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1259 {
1260 s->u8IndexShift = 2;
1261 }
1262 }
1263
1264 u32 >>= s->u8IndexShift;
1265 Assert(u32 < SYSTEM_INFO_INDEX_END);
1266 s->uSystemInfoIndex = u32;
1267 }
1268 break;
1269
1270 default:
1271 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1272 break;
1273 }
1274 return VINF_SUCCESS;
1275}
1276
1277PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1278{
1279 ACPIState *s = (ACPIState *)pvUser;
1280
1281 switch (cb)
1282 {
1283 case 4:
1284 switch (s->uSystemInfoIndex)
1285 {
1286 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1287 *pu32 = s->cbRamLow;
1288 break;
1289
1290 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1291 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1292 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1293 break;
1294
1295 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1296 *pu32 = s->u8UseIOApic;
1297 break;
1298
1299 case SYSTEM_INFO_INDEX_HPET_STATUS:
1300 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1301 | STA_DEVICE_ENABLED_MASK
1302 | STA_DEVICE_SHOW_IN_UI_MASK
1303 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1304 : 0;
1305 break;
1306
1307 case SYSTEM_INFO_INDEX_SMC_STATUS:
1308 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1309 | STA_DEVICE_ENABLED_MASK
1310 /* no need to show this device in the UI */
1311 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1312 : 0;
1313 break;
1314
1315 case SYSTEM_INFO_INDEX_FDC_STATUS:
1316 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1317 | STA_DEVICE_ENABLED_MASK
1318 | STA_DEVICE_SHOW_IN_UI_MASK
1319 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1320 : 0;
1321 break;
1322
1323 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1324 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1325 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1326 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1327 *pu32 = s->fShowCpu
1328 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1329 ? STA_DEVICE_PRESENT_MASK
1330 | STA_DEVICE_ENABLED_MASK
1331 | STA_DEVICE_SHOW_IN_UI_MASK
1332 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1333 : 0;
1334 break;
1335
1336 case SYSTEM_INFO_INDEX_RTC_STATUS:
1337 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1338 | STA_DEVICE_ENABLED_MASK
1339 | STA_DEVICE_SHOW_IN_UI_MASK
1340 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1341 : 0;
1342 break;
1343
1344 /* Solaris 9 tries to read from this index */
1345 case SYSTEM_INFO_INDEX_INVALID:
1346 *pu32 = 0;
1347 break;
1348
1349 default:
1350 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1351 break;
1352 }
1353 break;
1354
1355 default:
1356 return VERR_IOM_IOPORT_UNUSED;
1357 }
1358
1359 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1360 return VINF_SUCCESS;
1361}
1362
1363PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1364{
1365 ACPIState *s = (ACPIState *)pvUser;
1366
1367 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1368
1369 if (cb == 4 && u32 == 0xbadc0de)
1370 {
1371 switch (s->uSystemInfoIndex)
1372 {
1373 case SYSTEM_INFO_INDEX_INVALID:
1374 s->u8IndexShift = 0;
1375 break;
1376
1377 case SYSTEM_INFO_INDEX_VALID:
1378 s->u8IndexShift = 2;
1379 break;
1380
1381 default:
1382 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1383 Port, cb, u32, s->uSystemInfoIndex));
1384 break;
1385 }
1386 }
1387 else
1388 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1389 return VINF_SUCCESS;
1390}
1391
1392/** @todo Don't call functions, but do the job in the read/write handlers
1393 * here! */
1394
1395/* IO Helpers */
1396PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1397{
1398 switch (cb)
1399 {
1400 case 2:
1401 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1402 break;
1403 default:
1404 return VERR_IOM_IOPORT_UNUSED;
1405 }
1406 return VINF_SUCCESS;
1407}
1408
1409PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1410{
1411 switch (cb)
1412 {
1413 case 2:
1414 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1415 break;
1416 default:
1417 return VERR_IOM_IOPORT_UNUSED;
1418 }
1419 return VINF_SUCCESS;
1420}
1421
1422PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1423{
1424 switch (cb)
1425 {
1426 case 2:
1427 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1428 break;
1429 default:
1430 return VERR_IOM_IOPORT_UNUSED;
1431 }
1432 return VINF_SUCCESS;
1433}
1434
1435PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1436{
1437 switch (cb)
1438 {
1439 case 2:
1440 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1441 break;
1442 default:
1443 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1444 break;
1445 }
1446 return VINF_SUCCESS;
1447}
1448
1449PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1450{
1451 switch (cb)
1452 {
1453 case 2:
1454 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1455 break;
1456 default:
1457 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1458 break;
1459 }
1460 return VINF_SUCCESS;
1461}
1462
1463PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1464{
1465 switch (cb)
1466 {
1467 case 2:
1468 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1469 default:
1470 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1471 break;
1472 }
1473 return VINF_SUCCESS;
1474}
1475
1476#endif /* IN_RING3 */
1477
1478/**
1479 * PMTMR readable from host/guest.
1480 */
1481PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1482{
1483 if (cb == 4)
1484 {
1485 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1486 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1487 int64_t elapsed = now - s->pm_timer_initial;
1488
1489 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1490 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1491 return VINF_SUCCESS;
1492 }
1493 return VERR_IOM_IOPORT_UNUSED;
1494}
1495
1496#ifdef IN_RING3
1497
1498PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1499{
1500 switch (cb)
1501 {
1502 case 1:
1503 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1504 break;
1505 default:
1506 return VERR_IOM_IOPORT_UNUSED;
1507 }
1508 return VINF_SUCCESS;
1509}
1510
1511PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1512{
1513 switch (cb)
1514 {
1515 case 1:
1516 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1517 break;
1518 default:
1519 return VERR_IOM_IOPORT_UNUSED;
1520 }
1521 return VINF_SUCCESS;
1522}
1523
1524PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1525{
1526 switch (cb)
1527 {
1528 case 1:
1529 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1530 break;
1531 default:
1532 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1533 break;
1534 }
1535 return VINF_SUCCESS;
1536}
1537
1538PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1539{
1540 switch (cb)
1541 {
1542 case 1:
1543 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1544 break;
1545 default:
1546 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1547 break;
1548 }
1549 return VINF_SUCCESS;
1550}
1551
1552PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1553{
1554 switch (cb)
1555 {
1556 case 1:
1557 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1558 break;
1559 default:
1560 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1561 break;
1562 }
1563 return VINF_SUCCESS;
1564}
1565
1566PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1567{
1568 switch (cb)
1569 {
1570 case 1:
1571 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1572 default:
1573 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1574 break;
1575 }
1576 return VINF_SUCCESS;
1577}
1578
1579#ifdef DEBUG_ACPI
1580
1581PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1582{
1583 switch (cb)
1584 {
1585 case 1:
1586 Log(("%#x\n", u32 & 0xff));
1587 break;
1588 case 2:
1589 Log(("%#6x\n", u32 & 0xffff));
1590 case 4:
1591 Log(("%#10x\n", u32));
1592 break;
1593 default:
1594 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1595 break;
1596 }
1597 return VINF_SUCCESS;
1598}
1599
1600PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1601{
1602 switch (cb)
1603 {
1604 case 1:
1605 Log(("%c", u32 & 0xff));
1606 break;
1607 default:
1608 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1609 break;
1610 }
1611 return VINF_SUCCESS;
1612}
1613
1614#endif /* DEBUG_ACPI */
1615
1616
1617/**
1618 * Saved state structure description.
1619 */
1620static const SSMFIELD g_AcpiSavedStateFields[] =
1621{
1622 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1623 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1624 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1625 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1626 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1627 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1628 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1629 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1630 SSMFIELD_ENTRY(ACPIState, u64RamSize), /** @todo not necessary to save this. */
1631 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1632 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1633 SSMFIELD_ENTRY(ACPIState, uSleepState),
1634 SSMFIELD_ENTRY_TERM()
1635};
1636
1637static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1638{
1639 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1640 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1641}
1642
1643static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1644 uint32_t u32Version)
1645{
1646 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1647 int rc;
1648
1649 if (u32Version != 4)
1650 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1651
1652 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1653 if (RT_SUCCESS(rc))
1654 {
1655 acpiFetchBatteryStatus(s);
1656 acpiFetchBatteryInfo(s);
1657 acpiPMTimerReset(s);
1658 }
1659 return rc;
1660}
1661
1662/**
1663 * Queries an interface to the driver.
1664 *
1665 * @returns Pointer to interface.
1666 * @returns NULL if the interface was not supported by the driver.
1667 * @param pInterface Pointer to this interface structure.
1668 * @param enmInterface The requested interface identification.
1669 * @thread Any thread.
1670 */
1671static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1672{
1673 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1674 switch (enmInterface)
1675 {
1676 case PDMINTERFACE_BASE:
1677 return &pThis->IBase;
1678 case PDMINTERFACE_ACPI_PORT:
1679 return &pThis->IACPIPort;
1680 default:
1681 return NULL;
1682 }
1683}
1684
1685/**
1686 * Create the ACPI tables.
1687 */
1688static int acpiPlantTables(ACPIState *s)
1689{
1690 int rc;
1691 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1692 uint32_t addend = 0;
1693 RTGCPHYS32 rsdt_addrs[4];
1694 uint32_t cAddr;
1695 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1696 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1697
1698 cAddr = 1; /* FADT */
1699 if (s->u8UseIOApic)
1700 cAddr++; /* MADT */
1701
1702 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1703 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1704
1705 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1706 if (RT_FAILURE(rc))
1707 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1708 N_("Configuration error: Querying "
1709 "\"RamSize\" as integer failed"));
1710
1711 uint32_t cbRamHole;
1712 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1713 if (RT_FAILURE(rc))
1714 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1715 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1716
1717 /*
1718 * Calc the sizes for the high and low regions.
1719 */
1720 const uint64_t offRamHole = _4G - cbRamHole;
1721 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1722 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1723 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1724 {
1725 /* Note: This is also enforced by DevPcBios.cpp. */
1726 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1727 cbRamLow = UINT32_C(0xffe00000);
1728 }
1729 s->cbRamLow = (uint32_t)cbRamLow;
1730
1731 rsdt_addr = 0;
1732 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1733 fadt_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1734 facs_addr = RT_ALIGN_32(fadt_addr + sizeof(ACPITBLFADT), 16);
1735 if (s->u8UseIOApic)
1736 {
1737 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1738 /**
1739 * @todo nike: maybe some refactoring needed to compute tables layout,
1740 * but as this code is executed only once it doesn't make sense to optimize much
1741 */
1742 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1743 }
1744 else
1745 {
1746 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1747 }
1748
1749 last_addr = RT_ALIGN_32(dsdt_addr + sizeof(AmlCode), 16);
1750 if (last_addr > 0x10000)
1751 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1752 N_("Error: ACPI tables > 64KB"));
1753
1754 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1755 addend = s->cbRamLow - 0x10000;
1756 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1757 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1758 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1759 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1760 acpiSetupDSDT(s, dsdt_addr + addend);
1761 acpiSetupFACS(s, facs_addr + addend);
1762 acpiSetupFADT(s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1763
1764 rsdt_addrs[0] = fadt_addr + addend;
1765 if (s->u8UseIOApic)
1766 {
1767 acpiSetupMADT(s, apic_addr + addend);
1768 rsdt_addrs[1] = apic_addr + addend;
1769 }
1770
1771 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1772 if (RT_FAILURE(rc))
1773 return rc;
1774 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, rsdt_addrs);
1775}
1776
1777/**
1778 * Construct a device instance for a VM.
1779 *
1780 * @returns VBox status.
1781 * @param pDevIns The device instance data.
1782 * If the registration structure is needed, pDevIns->pDevReg points to it.
1783 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1784 * The device number is also found in pDevIns->iInstance, but since it's
1785 * likely to be freqently used PDM passes it as parameter.
1786 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1787 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1788 * iInstance it's expected to be used a bit in this function.
1789 */
1790static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1791{
1792 int rc;
1793 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1794 uint32_t rsdp_addr;
1795 PCIDevice *dev;
1796 bool fGCEnabled;
1797 bool fR0Enabled;
1798
1799 /* Validate and read the configuration. */
1800 if (!CFGMR3AreValuesValid(pCfgHandle,
1801 "RamSize\0"
1802 "RamHoleSize\0"
1803 "IOAPIC\0"
1804 "NumCPUs\0"
1805 "GCEnabled\0"
1806 "R0Enabled\0"
1807 "HpetEnabled\0"
1808 "SmcEnabled\0"
1809 "FdcEnabled\0"
1810 "ShowRtc\0"
1811 "ShowCpu\0"
1812 ))
1813 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1814 N_("Configuration error: Invalid config key for ACPI device"));
1815
1816 s->pDevIns = pDevIns;
1817
1818 /* query whether we are supposed to present an IOAPIC */
1819 rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1820 if (RT_FAILURE(rc))
1821 return PDMDEV_SET_ERROR(pDevIns, rc,
1822 N_("Configuration error: Failed to read \"IOAPIC\""));
1823
1824 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1825 if (RT_FAILURE(rc))
1826 return PDMDEV_SET_ERROR(pDevIns, rc,
1827 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1828
1829 /* query whether we are supposed to present an FDC controller */
1830 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1831 if (RT_FAILURE(rc))
1832 return PDMDEV_SET_ERROR(pDevIns, rc,
1833 N_("Configuration error: Failed to read \"FdcEnabled\""));
1834
1835 /* query whether we are supposed to present HPET */
1836 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1837 if (RT_FAILURE(rc))
1838 return PDMDEV_SET_ERROR(pDevIns, rc,
1839 N_("Configuration error: Failed to read \"HpetEnabled\""));
1840 /* query whether we are supposed to present SMC */
1841 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1842 if (RT_FAILURE(rc))
1843 return PDMDEV_SET_ERROR(pDevIns, rc,
1844 N_("Configuration error: Failed to read \"SmcEnabled\""));
1845
1846 /* query whether we are supposed to present RTC object */
1847 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowRtc", &s->fShowRtc, false);
1848 if (RT_FAILURE(rc))
1849 return PDMDEV_SET_ERROR(pDevIns, rc,
1850 N_("Configuration error: Failed to read \"ShowRtc\""));
1851
1852 /* query whether we are supposed to present CPU objects */
1853 rc = CFGMR3QueryBoolDef(pCfgHandle, "ShowCpu", &s->fShowCpu, false);
1854 if (RT_FAILURE(rc))
1855 return PDMDEV_SET_ERROR(pDevIns, rc,
1856 N_("Configuration error: Failed to read \"ShowCpu\""));
1857
1858 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1859 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1860 fGCEnabled = true;
1861 else if (RT_FAILURE(rc))
1862 return PDMDEV_SET_ERROR(pDevIns, rc,
1863 N_("Configuration error: Failed to read \"GCEnabled\""));
1864
1865 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1866 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1867 fR0Enabled = true;
1868 else if (RT_FAILURE(rc))
1869 return PDMDEV_SET_ERROR(pDevIns, rc,
1870 N_("configuration error: failed to read R0Enabled as boolean"));
1871
1872 /* */
1873 rsdp_addr = find_rsdp_space();
1874 if (!rsdp_addr)
1875 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1876 N_("Can not find space for RSDP. ACPI is disabled"));
1877
1878 rc = acpiPlantTables(s);
1879 if (RT_FAILURE(rc))
1880 return rc;
1881
1882 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
1883 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
1884 if (RT_FAILURE(rc))
1885 return rc;
1886
1887#define R(addr, cnt, writer, reader, description) \
1888 do { \
1889 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
1890 NULL, NULL, description); \
1891 if (RT_FAILURE(rc)) \
1892 return rc; \
1893 } while (0)
1894#define L (GPE0_BLK_LEN / 2)
1895
1896 R(PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1897 R(PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1898 R(PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1899 R(PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1900 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1901#ifdef DEBUG_ACPI
1902 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1903 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1904#endif
1905 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1906 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1907 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1908 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1909 R(GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1910 R(GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1911 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1912#undef L
1913#undef R
1914
1915 /* register GC stuff */
1916 if (fGCEnabled)
1917 {
1918 rc = PDMDevHlpIOPortRegisterGC(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1919 NULL, NULL, "ACPI PM Timer");
1920 AssertRCReturn(rc, rc);
1921 }
1922
1923 /* register R0 stuff */
1924 if (fR0Enabled)
1925 {
1926 rc = PDMDevHlpIOPortRegisterR0(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1927 NULL, NULL, "ACPI PM Timer");
1928 AssertRCReturn(rc, rc);
1929 }
1930
1931 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1932 if (RT_FAILURE(rc))
1933 {
1934 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1935 return rc;
1936 }
1937
1938 s->tsR0 = TMTimerR0Ptr(s->tsR3);
1939 s->tsRC = TMTimerRCPtr(s->tsR3);
1940 s->pm_timer_initial = TMTimerGet(s->tsR3);
1941 acpiPMTimerReset(s);
1942
1943 dev = &s->dev;
1944 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1945 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1946
1947 dev->config[0x04] = 0x01; /* command */
1948 dev->config[0x05] = 0x00;
1949
1950 dev->config[0x06] = 0x80; /* status */
1951 dev->config[0x07] = 0x02;
1952 dev->config[0x08] = 0x08;
1953 dev->config[0x09] = 0x00;
1954
1955 dev->config[0x0a] = 0x80;
1956 dev->config[0x0b] = 0x06;
1957
1958 dev->config[0x0e] = 0x80;
1959 dev->config[0x0f] = 0x00;
1960
1961#if 0 /* The ACPI controller usually has no subsystem ID. */
1962 dev->config[0x2c] = 0x86;
1963 dev->config[0x2d] = 0x80;
1964 dev->config[0x2e] = 0x00;
1965 dev->config[0x2f] = 0x00;
1966#endif
1967 dev->config[0x3c] = SCI_INT;
1968
1969 rc = PDMDevHlpPCIRegister(pDevIns, dev);
1970 if (RT_FAILURE(rc))
1971 return rc;
1972
1973 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1974 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1975 if (RT_FAILURE(rc))
1976 return rc;
1977
1978 /*
1979 * Interfaces
1980 */
1981 /* IBase */
1982 s->IBase.pfnQueryInterface = acpiQueryInterface;
1983 /* IACPIPort */
1984 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1985 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1986 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1987 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
1988
1989 /*
1990 * Get the corresponding connector interface
1991 */
1992 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1993 if (RT_SUCCESS(rc))
1994 {
1995 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
1996 if (!s->pDrv)
1997 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1998 N_("LUN #0 doesn't have an ACPI connector interface"));
1999 }
2000 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2001 {
2002 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2003 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2004 rc = VINF_SUCCESS;
2005 }
2006 else
2007 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2008
2009 return rc;
2010}
2011
2012/**
2013 * Relocates the GC pointer members.
2014 */
2015static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2016{
2017 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2018 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2019}
2020
2021static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2022{
2023 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2024
2025 s->pm1a_en = 0;
2026 s->pm1a_sts = 0;
2027 s->pm1a_ctl = 0;
2028 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2029 acpiPMTimerReset(s);
2030 s->uBatteryIndex = 0;
2031 s->uSystemInfoIndex = 0;
2032 s->gpe0_en = 0;
2033 s->gpe0_sts = 0;
2034 s->uSleepState = 0;
2035
2036 acpiPlantTables(s);
2037}
2038
2039/**
2040 * The device registration structure.
2041 */
2042const PDMDEVREG g_DeviceACPI =
2043{
2044 /* u32Version */
2045 PDM_DEVREG_VERSION,
2046 /* szDeviceName */
2047 "acpi",
2048 /* szRCMod */
2049 "VBoxDDGC.gc",
2050 /* szR0Mod */
2051 "VBoxDDR0.r0",
2052 /* pszDescription */
2053 "Advanced Configuration and Power Interface",
2054 /* fFlags */
2055 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2056 /* fClass */
2057 PDM_DEVREG_CLASS_ACPI,
2058 /* cMaxInstances */
2059 ~0,
2060 /* cbInstance */
2061 sizeof(ACPIState),
2062 /* pfnConstruct */
2063 acpiConstruct,
2064 /* pfnDestruct */
2065 NULL,
2066 /* pfnRelocate */
2067 acpiRelocate,
2068 /* pfnIOCtl */
2069 NULL,
2070 /* pfnPowerOn */
2071 NULL,
2072 /* pfnReset */
2073 acpiReset,
2074 /* pfnSuspend */
2075 NULL,
2076 /* pfnResume */
2077 NULL,
2078 /* pfnAttach */
2079 NULL,
2080 /* pfnDetach */
2081 NULL,
2082 /* pfnQueryInterface. */
2083 NULL,
2084 /* pfnInitComplete */
2085 NULL,
2086 /* pfnPowerOff */
2087 NULL,
2088 /* pfnSoftReset */
2089 NULL,
2090 /* u32VersionEnd */
2091 PDM_DEVREG_VERSION
2092};
2093
2094#endif /* IN_RING3 */
2095#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette