VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 2685

Last change on this file since 2685 was 2546, checked in by vboxsync, 18 years ago

cosmetical fixes
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 60.0 KB
Line 
1/** @file
2 *
3 * VBox basic PC devices:
4 * Advanced Configuration and Power Interface (ACPI) device
5 */
6
7/*
8 * Copyright (C) 2006 InnoTek Systemberatung GmbH
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License as published by the Free Software Foundation,
14 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
15 * distribution. VirtualBox OSE is distributed in the hope that it will
16 * be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * If you received this file as part of a commercial VirtualBox
19 * distribution, then only the terms of your commercial VirtualBox
20 * license agreement apply instead of the previous paragraph.
21 */
22
23#define LOG_GROUP LOG_GROUP_DEV_ACPI
24
25#include <VBox/pdm.h>
26#include <VBox/log.h>
27#include <iprt/assert.h>
28#include <iprt/asm.h>
29#ifdef IN_RING3
30#include <iprt/alloc.h>
31#endif /* IN_RING3 */
32
33#include "Builtins.h"
34#include "vl_vbox.h"
35
36#ifdef LOG_ENABLED
37#define DEBUG_ACPI
38#endif
39
40/* the compiled DSL */
41#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
42#include <vboxaml.hex>
43#endif /* !IN_RING3 */
44
45#define IO_READ_PROTO(name) \
46 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
47 RTIOPORT Port, uint32_t *pu32, unsigned cb)
48
49#define IO_WRITE_PROTO(name) \
50 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
51 RTIOPORT Port, uint32_t u32, unsigned cb)
52
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57#define PM1a_EVT_BLK 0x00004000
58#define PM1b_EVT_BLK 0x00000000 /**< not supported */
59#define PM1a_CTL_BLK 0x00004004
60#define PM1b_CTL_BLK 0x00000000 /**< not supported */
61#define PM2_CTL_BLK 0x00000000 /**< not supported */
62#define PM_TMR_BLK 0x00004008
63#define GPE0_BLK 0x00004020
64#define GPE1_BLK 0x00000000 /**< not supported */
65#define BAT_INDEX 0x00004040
66#define BAT_DATA 0x00004044
67#define SYSI_INDEX 0x00004048
68#define SYSI_DATA 0x0000404c
69#define ACPI_RESET_BLK 0x00004050
70
71/* PM1x status register bits */
72#define TMR_STS BIT(0)
73#define RSR1_STS (BIT(1) | BIT(2) | BIT(3))
74#define BM_STS BIT(4)
75#define GBL_STS BIT(5)
76#define RSR2_STS (BIT(6) | BIT(7))
77#define PWRBTN_STS BIT(8)
78#define SLPBTN_STS BIT(9)
79#define RTC_STS BIT(10)
80#define IGN_STS BIT(11)
81#define RSR3_STS (BIT(12) | BIT(13) | BIT(14))
82#define WAK_STS BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN BIT(0)
87#define RSR1_EN (BIT(1) | BIT(2) | BIT(3) | BIT(4))
88#define GBL_EN BIT(5)
89#define RSR2_EN (BIT(6) | BIT(7))
90#define PWRBTN_EN BIT(8)
91#define SLPBTN_EN BIT(9)
92#define RTC_EN BIT(10)
93#define RSR3_EN (BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN BIT(0)
99#define BM_RLD BIT(1)
100#define GBL_RLS BIT(2)
101#define RSR1_CNT (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8))
102#define IGN_CNT BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN BIT(13)
106#define RSR2_CNT (BIT(14) | BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED BIT (0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_LAST = 2,
136 SYSTEM_INFO_INDEX_INVALID = 0x80,
137 SYSTEM_INFO_INDEX_VALID = 0x200
138};
139
140#define AC_OFFLINE 0
141#define AC_ONLINE 1
142
143#define BAT_TECH_PRIMARY 1
144#define BAT_TECH_SECONDARY 2
145
146#define BAT_STATUS_DISCHARGING_MASK BIT (0)
147#define BAT_STATUS_CHARGING_MASK BIT (1)
148#define BAT_STATUS_CRITICAL_MASK BIT (2)
149
150#define STA_DEVICE_PRESENT_MASK BIT (0)
151#define STA_DEVICE_ENABLED_MASK BIT (1)
152#define STA_DEVICE_SHOW_IN_UI_MASK BIT (2)
153#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK BIT (3)
154#define STA_BATTERY_PRESENT_MASK BIT (4)
155
156struct ACPIState
157{
158 PCIDevice dev;
159 uint16_t pm1a_en;
160 uint16_t pm1a_sts;
161 uint16_t pm1a_ctl;
162 uint16_t Alignment0;
163 int64_t pm_timer_initial;
164 PTMTIMERHC tsHC;
165 PTMTIMERGC tsGC;
166
167 uint32_t gpe0_en;
168 uint32_t gpe0_sts;
169
170 unsigned int uBatteryIndex;
171 uint32_t au8BatteryInfo[13];
172
173 unsigned int uSystemInfoIndex;
174 uint64_t u64RamSize;
175
176 /** Current ACPI S* state. We support S0 and S5 */
177 uint32_t uSleepState;
178 uint8_t au8RSDPPage[0x1000];
179 uint8_t u8IndexShift;
180 uint8_t u8UseIOApic;
181
182 /** ACPI port base interface. */
183 PDMIBASE IBase;
184 /** ACPI port interface. */
185 PDMIACPIPORT IACPIPort;
186 /** Pointer to the device instance. */
187 PPDMDEVINSR3 pDevIns;
188 /** Pointer to the driver base interface */
189 R3PTRTYPE(PPDMIBASE) pDrvBase;
190 /** Pointer to the driver connector interface */
191 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
192};
193
194#pragma pack(1)
195
196/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
197struct ACPIGENADDR
198{
199 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
200 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
201 uint8_t u8RegisterBitOffset; /**< bit offset of register */
202 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
203 uint64_t u64Address; /**< 64-bit address of register */
204};
205AssertCompileSize(ACPIGENADDR, 12);
206
207/** Root System Description Pointer */
208struct ACPITBLRSDP
209{
210 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
211 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
212 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
213 uint8_t u8Revision; /**< revision number, currently 2 */
214#define ACPI_REVISION 2 /**< ACPI 3.0 */
215 uint32_t u32RSDT; /**< phys addr of RSDT */
216 uint32_t u32Length; /**< bytes of this table */
217 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
218 uint8_t u8ExtChecksum; /**< checksum of entire table */
219 uint8_t u8Reserved[3]; /**< reserved */
220};
221AssertCompileSize(ACPITBLRSDP, 36);
222
223/** System Description Table Header */
224struct ACPITBLHEADER
225{
226 uint8_t au8Signature[4]; /**< table identifier */
227 uint32_t u32Length; /**< length of the table including header */
228 uint8_t u8Revision; /**< revision number */
229 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
230 uint8_t au8OemId[6]; /**< OEM-supplied string */
231 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
232 uint32_t u32OemRevision; /**< OEM-supplied revision number */
233 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
234 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
235};
236AssertCompileSize(ACPITBLHEADER, 36);
237
238/** Root System Description Table */
239struct ACPITBLRSDT
240{
241 ACPITBLHEADER header;
242 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
243};
244AssertCompileSize(ACPITBLRSDT, 40);
245
246/** Extended System Description Table */
247struct ACPITBLXSDT
248{
249 ACPITBLHEADER header;
250 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
251};
252AssertCompileSize(ACPITBLXSDT, 44);
253
254/** Fixed ACPI Description Table */
255struct ACPITBLFADT
256{
257 ACPITBLHEADER header;
258 uint32_t u32FACS; /**< phys. address of FACS */
259 uint32_t u32DSDT; /**< phys. address of DSDT */
260 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
261#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
262#define INT_MODEL_MULTIPLE_APIC 2
263 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
264 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
265#define SCI_INT 9
266 uint32_t u32SMICmd; /**< system port address of SMI command port */
267#define SMI_CMD 0x0000442e
268 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
269#define ACPI_ENABLE 0xa1
270 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
271#define ACPI_DISABLE 0xa0
272 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
273 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
274 state control responsibility */
275 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
276 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
277 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
278 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
279 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
280 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
281 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
282 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
283 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
284 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
285 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
286 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
287 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
288#define GPE0_BLK_LEN 2
289 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
290#define GPE1_BLK_LEN 0
291 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
292#define GPE1_BASE 0
293 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
294 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
295#define P_LVL2_LAT 101 /**< C2 state not supported */
296 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
297#define P_LVL3_LAT 1001 /**< C3 state not supported */
298 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
299 lines from any processors memory caches */
300#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
301 uint16_t u16FlushStride; /**< cache line width */
302#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
303 uint8_t u8DutyOffset;
304 uint8_t u8DutyWidth;
305 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
306 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
307 uint8_t u8Century; /**< RTC CMOS RAM index of century */
308 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
309#define IAPC_BOOT_ARCH_LEGACY_DEV BIT(0) /**< legacy devices present such as LPT
310 (COM too?) */
311#define IAPC_BOOT_ARCH_8042 BIT(1) /**< legacy keyboard device present */
312#define IAPC_BOOT_ARCH_NO_VGA BIT(2) /**< VGA not present */
313 uint8_t u8Must0_0; /**< must be 0 */
314 uint32_t u32Flags; /**< fixed feature flags */
315#define FADT_FL_WBINVD BIT(0) /**< emulation of WBINVD available */
316#define FADT_FL_WBINVD_FLUSH BIT(1)
317#define FADT_FL_PROC_C1 BIT(2) /**< 1=C1 supported on all processors */
318#define FADT_FL_P_LVL2_UP BIT(3) /**< 1=C2 works on SMP and UNI systems */
319#define FADT_FL_PWR_BUTTON BIT(4) /**< 1=power button handled as ctrl method dev */
320#define FADT_FL_SLP_BUTTON BIT(5) /**< 1=sleep button handled as ctrl method dev */
321#define FADT_FL_FIX_RTC BIT(6) /**< 0=RTC wake status in fixed register */
322#define FADT_FL_RTC_S4 BIT(7) /**< 1=RTC can wake system from S4 */
323#define FADT_FL_TMR_VAL_EXT BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
324#define FADT_FL_DCK_CAP BIT(9) /**< 0=system cannot support docking */
325#define FADT_FL_RESET_REG_SUP BIT(10) /**< 1=system supports system resets */
326#define FADT_FL_SEALED_CASE BIT(11) /**< 1=case is sealed */
327#define FADT_FL_HEADLESS BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
328#define FADT_FL_CPU_SW_SLP BIT(13)
329#define FADT_FL_PCI_EXT_WAK BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
330#define FADT_FL_USE_PLATFORM_CLOCK BIT(15) /**< 1=system has ACPI PM timer */
331#define FADT_FL_S4_RTC_STS_VALID BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
332#define FADT_FL_REMOVE_POWER_ON_CAPABLE BIT(17) /**< 1=platform can remote power on */
333#define FADT_FL_FORCE_APIC_CLUSTER_MODEL BIT(18)
334#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE BIT(19)
335 ACPIGENADDR ResetReg; /**< ext addr of reset register */
336 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
337#define ACPI_RESET_REG_VAL 0x10
338 uint8_t au8Must0_1[3]; /**< must be 0 */
339 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
340 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
341 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
342 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
343 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
344 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
345 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
346 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
347 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
348 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
349};
350AssertCompileSize(ACPITBLFADT, 244);
351
352/** Firmware ACPI Control Structure */
353struct ACPITBLFACS
354{
355 uint8_t au8Signature[4]; /**< 'FACS' */
356 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
357 uint32_t u32HWSignature; /**< systems HW signature at last boot */
358 uint32_t u32FWVector; /**< address of waking vector */
359 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
360 uint32_t u32Flags; /**< FACS flags */
361 uint64_t u64X_FWVector; /**< 64-bit waking vector */
362 uint8_t u8Version; /**< version of this table */
363 uint8_t au8Reserved[31]; /**< zero */
364};
365AssertCompileSize(ACPITBLFACS, 64);
366
367/** Processor Local APIC Structure */
368struct ACPITBLLAPIC
369{
370 uint8_t u8Type; /**< 0 = LAPIC */
371 uint8_t u8Length; /**< 8 */
372 uint8_t u8ProcId; /**< processor ID */
373 uint8_t u8ApicId; /**< local APIC ID */
374 uint32_t u32Flags; /**< Flags */
375#define LAPIC_ENABLED 0x1
376};
377AssertCompileSize(ACPITBLLAPIC, 8);
378
379/** I/O APIC Structure */
380struct ACPITBLIOAPIC
381{
382 uint8_t u8Type; /**< 1 == I/O APIC */
383 uint8_t u8Length; /**< 12 */
384 uint8_t u8IOApicId; /**< I/O APIC ID */
385 uint8_t u8Reserved; /**< 0 */
386 uint32_t u32Address; /**< phys address to access I/O APIC */
387 uint32_t u32GSIB; /**< global system interrupt number to start */
388};
389AssertCompileSize(ACPITBLIOAPIC, 12);
390
391/** Multiple APIC Description Table */
392struct ACPITBLMADT
393{
394 ACPITBLHEADER header;
395 uint32_t u32LAPIC; /**< local APIC address */
396 uint32_t u32Flags; /**< Flags */
397#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
398 ACPITBLLAPIC LApic;
399 ACPITBLIOAPIC IOApic;
400};
401AssertCompileSize(ACPITBLMADT, 64);
402
403#pragma pack()
404
405
406#ifndef VBOX_DEVICE_STRUCT_TESTCASE
407__BEGIN_DECLS
408IO_READ_PROTO (acpiPMTmrRead);
409#ifdef IN_RING3
410IO_READ_PROTO (acpiPm1aEnRead);
411IO_WRITE_PROTO (acpiPM1aEnWrite);
412IO_READ_PROTO (acpiPm1aStsRead);
413IO_WRITE_PROTO (acpiPM1aStsWrite);
414IO_READ_PROTO (acpiPm1aCtlRead);
415IO_WRITE_PROTO (acpiPM1aCtlWrite);
416IO_WRITE_PROTO (acpiSmiWrite);
417IO_WRITE_PROTO (acpiBatIndexWrite);
418IO_READ_PROTO (acpiBatDataRead);
419IO_READ_PROTO (acpiSysInfoDataRead);
420IO_WRITE_PROTO (acpiSysInfoDataWrite);
421IO_READ_PROTO (acpiGpe0EnRead);
422IO_WRITE_PROTO (acpiGpe0EnWrite);
423IO_READ_PROTO (acpiGpe0StsRead);
424IO_WRITE_PROTO (acpiGpe0StsWrite);
425IO_WRITE_PROTO (acpiResetWrite);
426# ifdef DEBUG_ACPI
427IO_WRITE_PROTO (acpiDhexWrite);
428IO_WRITE_PROTO (acpiDchrWrite);
429# endif
430#endif
431__END_DECLS
432
433#ifdef IN_RING3
434
435/* Simple acpiChecksum: all the bytes must add up to 0. */
436static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
437{
438 uint8_t sum = 0;
439 for (size_t i = 0; i < len; ++i)
440 sum += data[i];
441 return -sum;
442}
443
444static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
445 uint32_t u32Length, uint8_t u8Revision)
446{
447 memcpy(header->au8Signature, au8Signature, 4);
448 header->u32Length = cpu_to_le32(u32Length);
449 header->u8Revision = u8Revision;
450 memcpy(header->au8OemId, "VBOX ", 6);
451 memcpy(header->au8OemTabId, "VBOX", 4);
452 memcpy(header->au8OemTabId+4, au8Signature, 4);
453 header->u32OemRevision = cpu_to_le32(1);
454 memcpy(header->au8CreatorId, "ASL ", 4);
455 header->u32CreatorRev = cpu_to_le32(0x61);
456}
457
458static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
459 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
460 uint8_t u8AccessSize, uint64_t u64Address)
461{
462 g->u8AddressSpaceId = u8AddressSpaceId;
463 g->u8RegisterBitWidth = u8RegisterBitWidth;
464 g->u8RegisterBitOffset = u8RegisterBitOffset;
465 g->u8AccessSize = u8AccessSize;
466 g->u64Address = cpu_to_le64(u64Address);
467}
468
469static void acpiPhyscpy (ACPIState *s, RTGCPHYS dst, const void * const src, size_t size)
470{
471 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
472}
473
474/* Differentiated System Description Table (DSDT) */
475static void acpiSetupDSDT (ACPIState *s, RTGCPHYS addr)
476{
477 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
478}
479
480/* Firmware ACPI Control Structure (FACS) */
481static void acpiSetupFACS (ACPIState *s, RTGCPHYS addr)
482{
483 ACPITBLFACS facs;
484
485 memset (&facs, 0, sizeof(facs));
486 memcpy (facs.au8Signature, "FACS", 4);
487 facs.u32Length = cpu_to_le32(sizeof(ACPITBLFACS));
488 facs.u32HWSignature = cpu_to_le32(0);
489 facs.u32FWVector = cpu_to_le32(0);
490 facs.u32GlobalLock = cpu_to_le32(0);
491 facs.u32Flags = cpu_to_le32(0);
492 facs.u64X_FWVector = cpu_to_le64(0);
493 facs.u8Version = 1;
494
495 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
496}
497
498/* Fixed ACPI Description Table (FADT aka FACP) */
499static void acpiSetupFADT (ACPIState *s, RTGCPHYS addr, uint32_t facs_addr, uint32_t dsdt_addr)
500{
501 ACPITBLFADT fadt;
502
503 memset (&fadt, 0, sizeof(fadt));
504 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
505 fadt.u32FACS = cpu_to_le32(facs_addr);
506 fadt.u32DSDT = cpu_to_le32(dsdt_addr);
507 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
508 fadt.u8PreferredPMProfile = 0; /* unspecified */
509 fadt.u16SCIInt = cpu_to_le16(SCI_INT);
510 fadt.u32SMICmd = cpu_to_le32(SMI_CMD);
511 fadt.u8AcpiEnable = ACPI_ENABLE;
512 fadt.u8AcpiDisable = ACPI_DISABLE;
513 fadt.u8S4BIOSReq = 0;
514 fadt.u8PStateCnt = 0;
515 fadt.u32PM1aEVTBLK = cpu_to_le32(PM1a_EVT_BLK);
516 fadt.u32PM1bEVTBLK = cpu_to_le32(PM1b_EVT_BLK);
517 fadt.u32PM1aCTLBLK = cpu_to_le32(PM1a_CTL_BLK);
518 fadt.u32PM1bCTLBLK = cpu_to_le32(PM1b_CTL_BLK);
519 fadt.u32PM2CTLBLK = cpu_to_le32(PM2_CTL_BLK);
520 fadt.u32PMTMRBLK = cpu_to_le32(PM_TMR_BLK);
521 fadt.u32GPE0BLK = cpu_to_le32(GPE0_BLK);
522 fadt.u32GPE1BLK = cpu_to_le32(GPE1_BLK);
523 fadt.u8PM1EVTLEN = 4;
524 fadt.u8PM1CTLLEN = 2;
525 fadt.u8PM2CTLLEN = 0;
526 fadt.u8PMTMLEN = 4;
527 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
528 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
529 fadt.u8GPE1BASE = GPE1_BASE;
530 fadt.u8CSTCNT = 0;
531 fadt.u16PLVL2LAT = cpu_to_le16(P_LVL2_LAT);
532 fadt.u16PLVL3LAT = cpu_to_le16(P_LVL3_LAT);
533 fadt.u16FlushSize = cpu_to_le16(FLUSH_SIZE);
534 fadt.u16FlushStride = cpu_to_le16(FLUSH_STRIDE);
535 fadt.u8DutyOffset = 0;
536 fadt.u8DutyWidth = 0;
537 fadt.u8DayAlarm = 0;
538 fadt.u8MonAlarm = 0;
539 fadt.u8Century = 0;
540 fadt.u16IAPCBOOTARCH = cpu_to_le16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
541 /** @note WBINVD is required for ACPI versions newer than 1.0 */
542 fadt.u32Flags = cpu_to_le32( FADT_FL_WBINVD | FADT_FL_SLP_BUTTON
543 | FADT_FL_FIX_RTC | FADT_FL_TMR_VAL_EXT);
544 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
545 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
546 fadt.u64XFACS = cpu_to_le64((uint64_t)facs_addr);
547 fadt.u64XDSDT = cpu_to_le64((uint64_t)dsdt_addr);
548 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
549 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
550 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
551 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
552 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
553 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
554 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
555 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
556 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
557 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
558}
559
560/*
561 * Root System Description Table.
562 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
563 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
564 */
565static int acpiSetupRSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
566{
567 ACPITBLRSDT *rsdt;
568 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
569
570 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
571 if (!rsdt)
572 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
573
574 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
575 for (unsigned int i = 0; i < nb_entries; ++i)
576 {
577 rsdt->u32Entry[i] = cpu_to_le32(addrs[i]);
578 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
579 }
580 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
581 acpiPhyscpy (s, addr, rsdt, size);
582 RTMemFree (rsdt);
583 return VINF_SUCCESS;
584}
585
586/* Extended System Description Table. */
587static int acpiSetupXSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
588{
589 ACPITBLXSDT *xsdt;
590 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
591
592 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
593 if (!xsdt)
594 return VERR_NO_TMP_MEMORY;
595
596 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
597 for (unsigned int i = 0; i < nb_entries; ++i)
598 {
599 xsdt->u64Entry[i] = cpu_to_le64((uint64_t)addrs[i]);
600 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
601 }
602 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
603 acpiPhyscpy (s, addr, xsdt, size);
604 RTMemFree (xsdt);
605 return VINF_SUCCESS;
606}
607
608/* Root System Description Pointer (RSDP) */
609static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
610{
611 memset(rsdp, 0, sizeof(*rsdp));
612
613 /* ACPI 1.0 part (RSDT */
614 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
615 memcpy(rsdp->au8OemId, "VBOX ", 6);
616 rsdp->u8Revision = ACPI_REVISION;
617 rsdp->u32RSDT = cpu_to_le32(rsdt_addr);
618 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
619
620 /* ACPI 2.0 part (XSDT) */
621 rsdp->u32Length = cpu_to_le32(sizeof(ACPITBLRSDP));
622 rsdp->u64XSDT = cpu_to_le64(xsdt_addr);
623 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
624}
625
626/* Multiple APIC Description Table. */
627/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
628/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
629static void acpiSetupMADT (ACPIState *s, RTGCPHYS addr)
630{
631 ACPITBLMADT madt;
632
633 /* Don't call this function if u8UseIOApic==false! */
634 Assert(s->u8UseIOApic);
635
636 memset(&madt, 0, sizeof(madt));
637 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
638
639 madt.u32LAPIC = cpu_to_le32(0xfee00000);
640 madt.u32Flags = cpu_to_le32(PCAT_COMPAT);
641
642 madt.LApic.u8Type = 0;
643 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
644 madt.LApic.u8ProcId = 0;
645 madt.LApic.u8ApicId = 0;
646 madt.LApic.u32Flags = cpu_to_le32(LAPIC_ENABLED);
647
648 madt.IOApic.u8Type = 1;
649 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
650 madt.IOApic.u8IOApicId = 0;
651 madt.IOApic.u8Reserved = 0;
652 madt.IOApic.u32Address = cpu_to_le32(0xfec00000);
653 madt.IOApic.u32GSIB = cpu_to_le32(0);
654
655 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
656 acpiPhyscpy (s, addr, &madt, sizeof(madt));
657}
658
659/* SCI IRQ */
660DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
661{
662 if (s->pm1a_ctl & SCI_EN)
663 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
664}
665
666DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
667{
668 return en & ~(RSR_EN | IGN_EN);
669}
670
671DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
672{
673 return sts & ~(RSR_STS | IGN_STS);
674}
675
676DECLINLINE(int) pm1a_level (ACPIState *s)
677{
678 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
679}
680
681DECLINLINE(int) gpe0_level (ACPIState *s)
682{
683 return (s->gpe0_en & s->gpe0_sts) != 0;
684}
685
686static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
687{
688 int old_level, new_level;
689
690 if (gpe0_level (s))
691 return;
692
693 old_level = pm1a_level (s);
694 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
695
696 s->pm1a_en = en;
697 s->pm1a_sts = sts;
698
699 if (new_level != old_level)
700 acpiSetIrq (s, new_level);
701}
702
703static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
704{
705 int old_level, new_level;
706
707 if (pm1a_level (s))
708 return;
709
710 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
711 new_level = (en & sts) != 0;
712
713 s->gpe0_en = en;
714 s->gpe0_sts = sts;
715
716 if (new_level != old_level)
717 acpiSetIrq (s, new_level);
718}
719
720static int acpiPowerDown (ACPIState *s)
721{
722 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
723 if (VBOX_FAILURE (rc))
724 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
725 return rc;
726}
727
728/** Converts a ACPI port interface pointer to an ACPI state pointer. */
729#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
730
731/**
732 * Send an ACPI power off event.
733 *
734 * @returns VBox status code
735 * @param pInterface Pointer to the interface structure containing the called function pointer.
736 */
737static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
738{
739 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
740 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
741 return VINF_SUCCESS;
742}
743
744/* PM1a_EVT_BLK enable */
745static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
746{
747 uint16_t val = s->pm1a_en;
748 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
749 return val;
750}
751
752static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
753{
754 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
755 val &= ~(RSR_EN | IGN_EN);
756 update_pm1a (s, s->pm1a_sts, val);
757}
758
759/* PM1a_EVT_BLK status */
760static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
761{
762 uint16_t val = s->pm1a_sts;
763 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
764 return val;
765}
766
767static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
768{
769 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
770 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
771 update_pm1a (s, val, s->pm1a_en);
772}
773
774/* PM1a_CTL_BLK */
775static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
776{
777 uint16_t val = s->pm1a_ctl;
778 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
779 return val;
780}
781
782static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
783{
784 uint32_t uSleepState;
785
786 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
787 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
788
789 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
790 if (uSleepState != s->uSleepState)
791 {
792 s->uSleepState = uSleepState;
793 switch (uSleepState)
794 {
795 case 0x00: /* S0 */
796 break;
797 case 0x05: /* S5 */
798 LogRel (("Entering S5 (power down)\n"));
799 return acpiPowerDown (s);
800 default:
801 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
802 break;
803 }
804 }
805 return VINF_SUCCESS;
806}
807
808/* GPE0_BLK */
809static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
810{
811 uint8_t val = s->gpe0_en;
812 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
813 return val;
814}
815
816static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
817{
818 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
819 update_gpe0 (s, s->gpe0_sts, val);
820}
821
822static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
823{
824 uint8_t val = s->gpe0_sts;
825 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
826 return val;
827}
828
829static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
830{
831 val = s->gpe0_sts & ~val;
832 update_gpe0 (s, val, s->gpe0_en);
833 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
834}
835
836static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
837{
838 int rc = VINF_SUCCESS;
839
840 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
841 if (val == ACPI_RESET_REG_VAL)
842 {
843# ifndef IN_RING3
844 rc = VINF_IOM_HC_IOPORT_WRITE;
845# else /* IN_RING3 */
846 rc = PDMDevHlpVMReset(s->pDevIns);
847# endif /* !IN_RING3 */
848 }
849 return rc;
850}
851
852/* SMI */
853static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
854{
855 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
856 if (val == ACPI_ENABLE)
857 s->pm1a_ctl |= SCI_EN;
858 else if (val == ACPI_DISABLE)
859 s->pm1a_ctl &= ~SCI_EN;
860 else
861 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
862}
863
864static uint32_t find_rsdp_space (void)
865{
866 return 0xe0000;
867}
868
869static void acpiPMTimerReset (ACPIState *s)
870{
871 uint64_t interval, freq;
872
873 freq = TMTimerGetFreq (s->CTXSUFF(ts));
874 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
875 Log (("interval = %RU64\n", interval));
876 TMTimerSet (s->CTXSUFF(ts), TMTimerGet (s->CTXSUFF(ts)) + interval);
877}
878
879static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
880{
881 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
882
883 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
884 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
885 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
886
887 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
888 acpiPMTimerReset (s);
889}
890
891/**
892 * _BST method.
893 */
894static void acpiFetchBatteryStatus (ACPIState *s)
895{
896 uint32_t *p = s->au8BatteryInfo;
897 bool fPresent; /* battery present? */
898 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
899 PDMACPIBATSTATE hostBatteryState; /* bitfield */
900 uint32_t hostPresentRate; /* 0..1000 */
901 int rc;
902
903 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
904 &hostBatteryState, &hostPresentRate);
905 AssertRC (rc);
906
907 /* default values */
908 p[BAT_STATUS_STATE] = hostBatteryState;
909 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
910 : hostPresentRate * 50; /* mW */
911 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
912 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
913
914 /* did we get a valid battery state? */
915 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
916 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
917 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
918 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
919}
920
921/**
922 * _BIF method.
923 */
924static void acpiFetchBatteryInfo (ACPIState *s)
925{
926 uint32_t *p = s->au8BatteryInfo;
927
928 p[BAT_INFO_UNITS] = 0; /* mWh */
929 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
930 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
931 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
932 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
933 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
934 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
935 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
936 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
937}
938
939/**
940 * _STA method.
941 */
942static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
943{
944 bool fPresent; /* battery present? */
945 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
946 PDMACPIBATSTATE hostBatteryState; /* bitfield */
947 uint32_t hostPresentRate; /* 0..1000 */
948 int rc;
949
950 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
951 &hostBatteryState, &hostPresentRate);
952 AssertRC (rc);
953
954 return fPresent
955 ? STA_DEVICE_PRESENT_MASK /* present */
956 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
957 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
958 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
959 | STA_BATTERY_PRESENT_MASK /* battery is present */
960 : 0; /* device not present */
961}
962
963static uint32_t acpiGetPowerSource (ACPIState *s)
964{
965 PDMACPIPOWERSOURCE ps;
966
967 /* query the current power source from the host driver */
968 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
969 AssertRC (rc);
970 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
971}
972
973IO_WRITE_PROTO (acpiBatIndexWrite)
974{
975 ACPIState *s = (ACPIState *)pvUser;
976
977 switch (cb)
978 {
979 case 4:
980 u32 >>= s->u8IndexShift;
981 Assert (u32 < BAT_INDEX_LAST);
982 s->uBatteryIndex = u32;
983 break;
984 default:
985 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
986 break;
987 }
988 return VINF_SUCCESS;
989}
990
991IO_READ_PROTO (acpiBatDataRead)
992{
993 ACPIState *s = (ACPIState *)pvUser;
994
995 switch (cb)
996 {
997 case 4:
998 switch (s->uBatteryIndex)
999 {
1000 case BAT_STATUS_STATE:
1001 acpiFetchBatteryStatus(s);
1002 case BAT_STATUS_PRESENT_RATE:
1003 case BAT_STATUS_REMAINING_CAPACITY:
1004 case BAT_STATUS_PRESENT_VOLTAGE:
1005 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1006 break;
1007
1008 case BAT_INFO_UNITS:
1009 acpiFetchBatteryInfo(s);
1010 case BAT_INFO_DESIGN_CAPACITY:
1011 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1012 case BAT_INFO_TECHNOLOGY:
1013 case BAT_INFO_DESIGN_VOLTAGE:
1014 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1015 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1016 case BAT_INFO_CAPACITY_GRANULARITY_1:
1017 case BAT_INFO_CAPACITY_GRANULARITY_2:
1018 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1019 break;
1020
1021 case BAT_DEVICE_STATUS:
1022 *pu32 = acpiGetBatteryDeviceStatus(s);
1023 break;
1024
1025 case BAT_POWER_SOURCE:
1026 *pu32 = acpiGetPowerSource(s);
1027 break;
1028
1029 default:
1030 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1031 break;
1032 }
1033 break;
1034 default:
1035 return VERR_IOM_IOPORT_UNUSED;
1036 }
1037// LogRel(("Query %04x => %08x\n", s->uBatteryIndex, *pu32));
1038 return VINF_SUCCESS;
1039}
1040
1041IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1042{
1043 ACPIState *s = (ACPIState *)pvUser;
1044
1045 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1046 switch (cb) {
1047 case 4:
1048 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1049 s->uSystemInfoIndex = u32;
1050 else
1051 {
1052 u32 >>= s->u8IndexShift;
1053 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1054 s->uSystemInfoIndex = u32;
1055 }
1056 break;
1057
1058 default:
1059 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1060 break;
1061 }
1062 return VINF_SUCCESS;
1063}
1064
1065IO_READ_PROTO (acpiSysInfoDataRead)
1066{
1067 ACPIState *s = (ACPIState *)pvUser;
1068
1069 switch (cb)
1070 {
1071 case 4:
1072 switch (s->uSystemInfoIndex)
1073 {
1074 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1075 *pu32 = s->u64RamSize;
1076 break;
1077
1078 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1079 *pu32 = s->u8UseIOApic;
1080 break;
1081
1082 default:
1083 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1084 break;
1085 }
1086 break;
1087
1088 default:
1089 return VERR_IOM_IOPORT_UNUSED;
1090 }
1091
1092 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1093 return VINF_SUCCESS;
1094}
1095
1096IO_WRITE_PROTO (acpiSysInfoDataWrite)
1097{
1098 ACPIState *s = (ACPIState *)pvUser;
1099
1100 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1101
1102 if (cb == 4 && u32 == 0xbadc0de)
1103 {
1104 switch (s->uSystemInfoIndex)
1105 {
1106 case SYSTEM_INFO_INDEX_INVALID:
1107 s->u8IndexShift = 0;
1108 break;
1109
1110 case SYSTEM_INFO_INDEX_VALID:
1111 s->u8IndexShift = 2;
1112 break;
1113
1114 default:
1115 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1116 Port, cb, u32, s->uSystemInfoIndex));
1117 break;
1118 }
1119 }
1120 else
1121 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1122 return VINF_SUCCESS;
1123}
1124
1125/* IO Helpers */
1126IO_READ_PROTO (acpiPm1aEnRead)
1127{
1128 switch (cb)
1129 {
1130 case 2:
1131 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1132 break;
1133 default:
1134 return VERR_IOM_IOPORT_UNUSED;
1135 }
1136 return VINF_SUCCESS;
1137}
1138
1139IO_READ_PROTO (acpiPm1aStsRead)
1140{
1141 switch (cb)
1142 {
1143 case 2:
1144 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1145 break;
1146 default:
1147 return VERR_IOM_IOPORT_UNUSED;
1148 }
1149 return VINF_SUCCESS;
1150}
1151
1152IO_READ_PROTO (acpiPm1aCtlRead)
1153{
1154 switch (cb)
1155 {
1156 case 2:
1157 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1158 break;
1159 default:
1160 return VERR_IOM_IOPORT_UNUSED;
1161 }
1162 return VINF_SUCCESS;
1163}
1164
1165IO_WRITE_PROTO (acpiPM1aEnWrite)
1166{
1167 switch (cb)
1168 {
1169 case 2:
1170 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1171 break;
1172 default:
1173 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1174 break;
1175 }
1176 return VINF_SUCCESS;
1177}
1178
1179IO_WRITE_PROTO (acpiPM1aStsWrite)
1180{
1181 switch (cb)
1182 {
1183 case 2:
1184 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1185 break;
1186 default:
1187 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1188 break;
1189 }
1190 return VINF_SUCCESS;
1191}
1192
1193IO_WRITE_PROTO (acpiPM1aCtlWrite)
1194{
1195 switch (cb)
1196 {
1197 case 2:
1198 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1199 default:
1200 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1201 break;
1202 }
1203 return VINF_SUCCESS;
1204}
1205
1206#endif /* IN_RING3 */
1207
1208/**
1209 * PMTMR readable from host/guest.
1210 */
1211IO_READ_PROTO (acpiPMTmrRead)
1212{
1213 if (cb == 4)
1214 {
1215 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1216 int64_t now = TMTimerGet (s->CTXSUFF(ts));
1217 int64_t elapsed = now - s->pm_timer_initial;
1218
1219 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTXSUFF(ts)));
1220 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1221 return VINF_SUCCESS;
1222 }
1223 return VERR_IOM_IOPORT_UNUSED;
1224}
1225
1226#ifdef IN_RING3
1227
1228IO_READ_PROTO (acpiGpe0StsRead)
1229{
1230 switch (cb)
1231 {
1232 case 1:
1233 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1234 break;
1235 default:
1236 return VERR_IOM_IOPORT_UNUSED;
1237 }
1238 return VINF_SUCCESS;
1239}
1240
1241IO_READ_PROTO (acpiGpe0EnRead)
1242{
1243 switch (cb)
1244 {
1245 case 1:
1246 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1247 break;
1248 default:
1249 return VERR_IOM_IOPORT_UNUSED;
1250 }
1251 return VINF_SUCCESS;
1252}
1253
1254IO_WRITE_PROTO (acpiGpe0StsWrite)
1255{
1256 switch (cb)
1257 {
1258 case 1:
1259 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1260 break;
1261 default:
1262 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1263 break;
1264 }
1265 return VINF_SUCCESS;
1266}
1267
1268IO_WRITE_PROTO (acpiGpe0EnWrite)
1269{
1270 switch (cb)
1271 {
1272 case 1:
1273 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1274 break;
1275 default:
1276 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1277 break;
1278 }
1279 return VINF_SUCCESS;
1280}
1281
1282IO_WRITE_PROTO (acpiSmiWrite)
1283{
1284 switch (cb)
1285 {
1286 case 1:
1287 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1288 break;
1289 default:
1290 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1291 break;
1292 }
1293 return VINF_SUCCESS;
1294}
1295
1296IO_WRITE_PROTO (acpiResetWrite)
1297{
1298 switch (cb)
1299 {
1300 case 1:
1301 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1302 default:
1303 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1304 break;
1305 }
1306 return VINF_SUCCESS;
1307}
1308
1309#ifdef DEBUG_ACPI
1310
1311IO_WRITE_PROTO (acpiDhexWrite)
1312{
1313 switch (cb)
1314 {
1315 case 1:
1316 Log (("%#x\n", u32 & 0xff));
1317 break;
1318 case 2:
1319 Log (("%#6x\n", u32 & 0xffff));
1320 case 4:
1321 Log (("%#10x\n", u32));
1322 break;
1323 default:
1324 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1325 break;
1326 }
1327 return VINF_SUCCESS;
1328}
1329
1330IO_WRITE_PROTO (acpiDchrWrite)
1331{
1332 switch (cb)
1333 {
1334 case 1:
1335 Log (("%c", u32 & 0xff));
1336 break;
1337 default:
1338 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1339 break;
1340 }
1341 return VINF_SUCCESS;
1342}
1343
1344#endif /* DEBUG_ACPI */
1345
1346
1347/**
1348 * Saved state structure description.
1349 */
1350static const SSMFIELD g_AcpiSavedStateFields[] =
1351{
1352 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1353 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1354 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1355 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1356 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1357 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1358 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1359 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1360 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1361 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1362 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1363 SSMFIELD_ENTRY (ACPIState, uSleepState),
1364 SSMFIELD_ENTRY_TERM ()
1365};
1366
1367static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1368{
1369 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1370 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1371}
1372
1373static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1374 uint32_t u32Version)
1375{
1376 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1377 int rc;
1378
1379 if (u32Version != 4)
1380 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1381
1382 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1383 if (VBOX_SUCCESS (rc))
1384 {
1385 acpiFetchBatteryStatus (s);
1386 acpiFetchBatteryInfo (s);
1387 acpiPMTimerReset (s);
1388 }
1389 return rc;
1390}
1391
1392/**
1393 * Queries an interface to the driver.
1394 *
1395 * @returns Pointer to interface.
1396 * @returns NULL if the interface was not supported by the driver.
1397 * @param pInterface Pointer to this interface structure.
1398 * @param enmInterface The requested interface identification.
1399 * @thread Any thread.
1400 */
1401static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1402{
1403 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1404 switch (enmInterface)
1405 {
1406 case PDMINTERFACE_BASE:
1407 return &pData->IBase;
1408 case PDMINTERFACE_ACPI_PORT:
1409 return &pData->IACPIPort;
1410 default:
1411 return NULL;
1412 }
1413}
1414
1415/**
1416 * Create the ACPI tables.
1417 */
1418static int acpiPlantTables (ACPIState *s)
1419{
1420 int rc;
1421 uint32_t rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1422 uint32_t addend = 0;
1423 uint32_t rsdt_addrs[4];
1424 uint32_t cAddr;
1425 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1426 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1427
1428 cAddr = 1; /* FADT */
1429 if (s->u8UseIOApic)
1430 cAddr++; /* MADT */
1431
1432 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1433 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1434
1435 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1436 if (VBOX_FAILURE (rc))
1437 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1438 N_("Configuration error: Querying "
1439 "\"RamSize\" as integer failed"));
1440
1441 if (s->u64RamSize > (0xffffffff - 0x10000))
1442 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1443 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1444 "value is 4095MB"));
1445
1446 rsdt_addr = 0;
1447 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1448 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1449 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1450 if (s->u8UseIOApic)
1451 {
1452 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1453 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1454 }
1455 else
1456 {
1457 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1458 }
1459
1460 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1461 if (last_addr > 0x10000)
1462 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1463 N_("Error: ACPI tables > 64KB!"));
1464
1465 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1466 addend = (uint32_t) s->u64RamSize - 0x10000;
1467 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1468 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1469 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1470 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1471 acpiSetupDSDT (s, dsdt_addr + addend);
1472 acpiSetupFACS (s, facs_addr + addend);
1473 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1474
1475 rsdt_addrs[0] = fadt_addr + addend;
1476 if (s->u8UseIOApic)
1477 {
1478 acpiSetupMADT (s, apic_addr + addend);
1479 rsdt_addrs[1] = apic_addr + addend;
1480 }
1481
1482 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1483 if (VBOX_FAILURE(rc))
1484 return rc;
1485 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1486}
1487
1488/**
1489 * Construct a device instance for a VM.
1490 *
1491 * @returns VBox status.
1492 * @param pDevIns The device instance data.
1493 * If the registration structure is needed, pDevIns->pDevReg points to it.
1494 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1495 * The device number is also found in pDevIns->iInstance, but since it's
1496 * likely to be freqently used PDM passes it as parameter.
1497 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1498 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1499 * iInstance it's expected to be used a bit in this function.
1500 */
1501static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1502{
1503 int rc;
1504 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1505 uint32_t rsdp_addr;
1506 PCIDevice *dev;
1507 bool fGCEnabled;
1508 bool fR0Enabled;
1509
1510 /* Validate and read the configuration. */
1511 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0"))
1512 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1513 N_("Configuration error: Invalid config key for ACPI device"));
1514
1515 s->pDevIns = pDevIns;
1516
1517 /* query whether we are supposed to present an IOAPIC */
1518 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1519 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1520 s->u8UseIOApic = 1;
1521 else if (VBOX_FAILURE (rc))
1522 return PDMDEV_SET_ERROR(pDevIns, rc,
1523 N_("Configuration error: Failed to read \"IOAPIC\"."));
1524
1525 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1526 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1527 fGCEnabled = true;
1528 else if (VBOX_FAILURE (rc))
1529 return PDMDEV_SET_ERROR(pDevIns, rc,
1530 N_("Configuration error: Failed to read \"GCEnabled\"."));
1531
1532 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1533 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1534 fR0Enabled = true;
1535 else if (VBOX_FAILURE(rc))
1536 return PDMDEV_SET_ERROR(pDevIns, rc,
1537 N_("configuration error: failed to read R0Enabled as boolean."));
1538
1539 /* */
1540 rsdp_addr = find_rsdp_space ();
1541 if (!rsdp_addr)
1542 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1543 N_("Can not find space for RSDP. ACPI is disabled."));
1544
1545 rc = acpiPlantTables (s);
1546 if (VBOX_FAILURE (rc))
1547 return rc;
1548
1549 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, "ACPI RSDP");
1550 if (VBOX_FAILURE (rc))
1551 return rc;
1552
1553#define R(addr, cnt, writer, reader, description) \
1554 do { \
1555 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1556 NULL, NULL, description); \
1557 if (VBOX_FAILURE (rc)) \
1558 return rc; \
1559 } while (0)
1560#define L (GPE0_BLK_LEN / 2)
1561
1562 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1563 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1564 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1565 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1566 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1567#ifdef DEBUG_ACPI
1568 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1569 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1570#endif
1571 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1572 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1573 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1574 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1575 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1576 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1577 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1578#undef L
1579#undef R
1580
1581 /* register GC stuff */
1582 if (fGCEnabled)
1583 {
1584 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1585 NULL, NULL, "ACPI PM Timer");
1586 AssertRCReturn(rc, rc);
1587 }
1588
1589 /* register R0 stuff */
1590 if (fR0Enabled)
1591 {
1592 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1593 NULL, NULL, "ACPI PM Timer");
1594 AssertRCReturn(rc, rc);
1595 }
1596
1597 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsHC);
1598 if (VBOX_FAILURE(rc))
1599 {
1600 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1601 return rc;
1602 }
1603
1604 s->tsGC = TMTimerGCPtr (s->tsHC);
1605 s->pm_timer_initial = TMTimerGet (s->tsHC);
1606 acpiPMTimerReset (s);
1607
1608 dev = &s->dev;
1609 dev->config[0x00] = 0x86;
1610 dev->config[0x01] = 0x80;
1611
1612 dev->config[0x02] = 0x13;
1613 dev->config[0x03] = 0x71;
1614
1615 dev->config[0x04] = 0x01;
1616 dev->config[0x05] = 0x00;
1617
1618 dev->config[0x06] = 0x80;
1619 dev->config[0x07] = 0x02;
1620 dev->config[0x08] = 0x08;
1621 dev->config[0x09] = 0x00;
1622
1623 dev->config[0x0a] = 0x80;
1624 dev->config[0x0b] = 0x06;
1625
1626 dev->config[0x0e] = 0x80;
1627 dev->config[0x0f] = 0x00;
1628
1629#if 0 /* The ACPI controller usually has no subsystem ID. */
1630 dev->config[0x2c] = 0x86;
1631 dev->config[0x2d] = 0x80;
1632 dev->config[0x2e] = 0x00;
1633 dev->config[0x2f] = 0x00;
1634#endif
1635 dev->config[0x3c] = SCI_INT;
1636
1637 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1638 if (VBOX_FAILURE (rc))
1639 return rc;
1640
1641 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1642 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1643 if (VBOX_FAILURE(rc))
1644 return rc;
1645
1646 /*
1647 * Interfaces
1648 */
1649 /* IBase */
1650 s->IBase.pfnQueryInterface = acpiQueryInterface;
1651 /* IACPIPort */
1652 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1653
1654 /*
1655 * Get the corresponding connector interface
1656 */
1657 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1658 if (VBOX_SUCCESS (rc))
1659 {
1660 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1661 PDMINTERFACE_ACPI_CONNECTOR);
1662 if (!s->pDrv)
1663 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1664 N_("LUN #0 doesn't have an ACPI connector interface!\n"));
1665 }
1666 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1667 {
1668 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1669 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1670 rc = VINF_SUCCESS;
1671 }
1672 else
1673 return PDMDEV_SET_ERROR(pDevIns, rc,
1674 N_("Failed to attach LUN #0!"));
1675
1676 return rc;
1677}
1678
1679/**
1680 * Relocates the GC pointer members.
1681 */
1682static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1683{
1684 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1685 s->tsGC = TMTimerGCPtr (s->tsHC);
1686}
1687
1688static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1689{
1690 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1691
1692 s->pm1a_en = 0;
1693 s->pm1a_sts = 0;
1694 s->pm1a_ctl = 0;
1695 s->pm_timer_initial = TMTimerGet (s->CTXSUFF(ts));
1696 acpiPMTimerReset(s);
1697 s->uBatteryIndex = 0;
1698 s->uSystemInfoIndex = 0;
1699 s->gpe0_en = 0;
1700 s->gpe0_sts = 0;
1701 s->uSleepState = 0;
1702
1703 acpiPlantTables(s);
1704}
1705
1706/**
1707 * The device registration structure.
1708 */
1709const PDMDEVREG g_DeviceACPI =
1710{
1711 /* u32Version */
1712 PDM_DEVREG_VERSION,
1713 /* szDeviceName */
1714 "acpi",
1715 /* szGCMod */
1716 "VBoxDDGC.gc",
1717 /* szR0Mod */
1718 "VBoxDDR0.r0",
1719 /* pszDescription */
1720 "Advanced Configuration and Power Interface",
1721 /* fFlags */
1722 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1723 /* fClass */
1724 PDM_DEVREG_CLASS_ACPI,
1725 /* cMaxInstances */
1726 ~0,
1727 /* cbInstance */
1728 sizeof(ACPIState),
1729 /* pfnConstruct */
1730 acpiConstruct,
1731 /* pfnDestruct */
1732 NULL,
1733 /* pfnRelocate */
1734 acpiRelocate,
1735 /* pfnIOCtl */
1736 NULL,
1737 /* pfnPowerOn */
1738 NULL,
1739 /* pfnReset */
1740 acpiReset,
1741 /* pfnSuspend */
1742 NULL,
1743 /* pfnResume */
1744 NULL,
1745 /* pfnAttach */
1746 NULL,
1747 /* pfnDetach */
1748 NULL,
1749 /* pfnQueryInterface. */
1750 NULL
1751};
1752
1753#endif /* IN_RING3 */
1754#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1755
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette