VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 35351

Last change on this file since 35351 was 35346, checked in by vboxsync, 14 years ago

VMM reorg: Moving the public include files from include/VBox to include/VBox/vmm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 106.4 KB
Line 
1/* $Id: DevACPI.cpp 35346 2010-12-27 16:13:13Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DEV_ACPI
22#include <VBox/vmm/pdmdev.h>
23#include <VBox/vmm/pgm.h>
24#include <VBox/log.h>
25#include <VBox/param.h>
26#include <iprt/assert.h>
27#include <iprt/asm.h>
28#include <iprt/asm-math.h>
29#ifdef IN_RING3
30# include <iprt/alloc.h>
31# include <iprt/string.h>
32# include <iprt/uuid.h>
33#endif /* IN_RING3 */
34
35#include "../Builtins.h"
36
37#ifdef LOG_ENABLED
38# define DEBUG_ACPI
39#endif
40
41#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
42int acpiPrepareDsdt(PPDMDEVINS pDevIns, void* *ppPtr, size_t *puDsdtLen);
43int acpiCleanupDsdt(PPDMDEVINS pDevIns, void* pPtr);
44
45int acpiPrepareSsdt(PPDMDEVINS pDevIns, void* *ppPtr, size_t *puSsdtLen);
46int acpiCleanupSsdt(PPDMDEVINS pDevIns, void* pPtr);
47#endif /* !IN_RING3 */
48
49
50
51/*******************************************************************************
52* Defined Constants And Macros *
53*******************************************************************************/
54#define DEBUG_HEX 0x3000
55#define DEBUG_CHR 0x3001
56
57#define PM_TMR_FREQ 3579545
58/* Default base for PM PIIX4 device */
59#define PM_PORT_BASE 0x4000
60/* Port offsets in PM device */
61enum
62{
63 PM1a_EVT_OFFSET = 0x00,
64 PM1b_EVT_OFFSET = -1, /**< not supported */
65 PM1a_CTL_OFFSET = 0x04,
66 PM1b_CTL_OFFSET = -1, /**< not supported */
67 PM2_CTL_OFFSET = -1, /**< not supported */
68 PM_TMR_OFFSET = 0x08,
69 GPE0_OFFSET = 0x20,
70 GPE1_OFFSET = -1 /**< not supported */
71};
72
73#define BAT_INDEX 0x00004040
74#define BAT_DATA 0x00004044
75#define SYSI_INDEX 0x00004048
76#define SYSI_DATA 0x0000404c
77#define ACPI_RESET_BLK 0x00004050
78
79/* PM1x status register bits */
80#define TMR_STS RT_BIT(0)
81#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
82#define BM_STS RT_BIT(4)
83#define GBL_STS RT_BIT(5)
84#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
85#define PWRBTN_STS RT_BIT(8)
86#define SLPBTN_STS RT_BIT(9)
87#define RTC_STS RT_BIT(10)
88#define IGN_STS RT_BIT(11)
89#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
90#define WAK_STS RT_BIT(15)
91#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
92
93/* PM1x enable register bits */
94#define TMR_EN RT_BIT(0)
95#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
96#define GBL_EN RT_BIT(5)
97#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
98#define PWRBTN_EN RT_BIT(8)
99#define SLPBTN_EN RT_BIT(9)
100#define RTC_EN RT_BIT(10)
101#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
102#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
103#define IGN_EN 0
104
105/* PM1x control register bits */
106#define SCI_EN RT_BIT(0)
107#define BM_RLD RT_BIT(1)
108#define GBL_RLS RT_BIT(2)
109#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
110#define IGN_CNT RT_BIT(9)
111#define SLP_TYPx_SHIFT 10
112#define SLP_TYPx_MASK 7
113#define SLP_EN RT_BIT(13)
114#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
115#define RSR_CNT (RSR1_CNT | RSR2_CNT)
116
117#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
118
119enum
120{
121 BAT_STATUS_STATE = 0x00, /**< BST battery state */
122 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
123 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
124 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
125 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
126 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
127 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
128 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
129 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
130 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
131 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
132 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
133 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
134 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
135 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
136 BAT_INDEX_LAST
137};
138
139enum
140{
141 CPU_EVENT_TYPE_ADD = 0x01, /**< Event type add */
142 CPU_EVENT_TYPE_REMOVE = 0x03 /**< Event type remove */
143};
144
145enum
146{
147 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
148 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
149 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
150 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
151 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
152 SYSTEM_INFO_INDEX_CPU0_STATUS = 5, /**< For compatibility with older saved states. */
153 SYSTEM_INFO_INDEX_CPU1_STATUS = 6, /**< For compatibility with older saved states. */
154 SYSTEM_INFO_INDEX_CPU2_STATUS = 7, /**< For compatibility with older saved states. */
155 SYSTEM_INFO_INDEX_CPU3_STATUS = 8, /**< For compatibility with older saved states. */
156 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
157 SYSTEM_INFO_INDEX_RTC_STATUS = 10,
158 SYSTEM_INFO_INDEX_CPU_LOCKED = 11, /**< Contains a flag indicating whether the CPU is locked or not */
159 SYSTEM_INFO_INDEX_CPU_LOCK_CHECK = 12, /**< For which CPU the lock status should be checked */
160 SYSTEM_INFO_INDEX_CPU_EVENT_TYPE = 13, /**< Type of the CPU hot-plug event */
161 SYSTEM_INFO_INDEX_CPU_EVENT = 14, /**< The CPU id the event is for */
162 SYSTEM_INFO_INDEX_NIC_ADDRESS = 15, /**< NIC PCI address, or 0 */
163 SYSTEM_INFO_INDEX_AUDIO_ADDRESS = 16, /**< Audio card PCI address, or 0 */
164 SYSTEM_INFO_INDEX_POWER_STATES = 17,
165 SYSTEM_INFO_INDEX_IOC_ADDRESS = 18, /**< IO controller PCI address */
166 SYSTEM_INFO_INDEX_HBC_ADDRESS = 19, /**< host bus controller PCI address */
167 SYSTEM_INFO_INDEX_PCI_BASE = 20, /**< PCI bus MCFG MMIO range base */
168 SYSTEM_INFO_INDEX_PCI_LENGTH = 21, /**< PCI bus MCFG MMIO range length */
169 SYSTEM_INFO_INDEX_END = 22,
170 SYSTEM_INFO_INDEX_INVALID = 0x80,
171 SYSTEM_INFO_INDEX_VALID = 0x200
172};
173
174#define AC_OFFLINE 0
175#define AC_ONLINE 1
176
177#define BAT_TECH_PRIMARY 1
178#define BAT_TECH_SECONDARY 2
179
180#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
181#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
182#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
183#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
184#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
185
186
187/*******************************************************************************
188* Structures and Typedefs *
189*******************************************************************************/
190/**
191 * The ACPI device state.
192 */
193typedef struct ACPIState
194{
195 PCIDevice dev;
196 uint16_t pm1a_en;
197 uint16_t pm1a_sts;
198 uint16_t pm1a_ctl;
199 /** Number of logical CPUs in guest */
200 uint16_t cCpus;
201 int64_t pm_timer_initial;
202 PTMTIMERR3 tsR3;
203 PTMTIMERR0 tsR0;
204 PTMTIMERRC tsRC;
205
206 uint32_t gpe0_en;
207 uint32_t gpe0_sts;
208
209 unsigned int uBatteryIndex;
210 uint32_t au8BatteryInfo[13];
211
212 unsigned int uSystemInfoIndex;
213 uint64_t u64RamSize;
214 /** The number of bytes above 4GB. */
215 uint64_t cbRamHigh;
216 /** The number of bytes below 4GB. */
217 uint32_t cbRamLow;
218
219 /** Current ACPI S* state. We support S0 and S5. */
220 uint32_t uSleepState;
221 uint8_t au8RSDPPage[0x1000];
222 /** This is a workaround for incorrect index field handling by Intels ACPICA.
223 * The system info _INI method writes to offset 0x200. We either observe a
224 * write request to index 0x80 (in that case we don't change the index) or a
225 * write request to offset 0x200 (in that case we divide the index value by
226 * 4. Note that the _STA method is sometimes called prior to the _INI method
227 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
228 * acpiBatIndexWrite() for handling this. */
229 uint8_t u8IndexShift;
230 /** provide an I/O-APIC */
231 uint8_t u8UseIOApic;
232 /** provide a floppy controller */
233 bool fUseFdc;
234 /** If High Precision Event Timer device should be supported */
235 bool fUseHpet;
236 /** If System Management Controller device should be supported */
237 bool fUseSmc;
238 /** the guest handled the last power button event */
239 bool fPowerButtonHandled;
240 /** If ACPI CPU device should be shown */
241 bool fShowCpu;
242 /** If Real Time Clock ACPI object to be shown */
243 bool fShowRtc;
244 /** I/O port address of PM device. */
245 RTIOPORT uPmIoPortBase;
246 /** Flag whether the GC part of the device is enabled. */
247 bool fGCEnabled;
248 /** Flag whether the R0 part of the device is enabled. */
249 bool fR0Enabled;
250 /** Array of flags of attached CPUs */
251 VMCPUSET CpuSetAttached;
252 /** Which CPU to check for the locked status. */
253 uint32_t idCpuLockCheck;
254 /** Mask of locked CPUs (used by the guest). */
255 VMCPUSET CpuSetLocked;
256 /** The CPU event type. */
257 uint32_t u32CpuEventType;
258 /** The CPU id affected. */
259 uint32_t u32CpuEvent;
260 /** Flag whether CPU hot plugging is enabled. */
261 bool fCpuHotPlug;
262 /** If MCFG ACPI table shown to the guest */
263 bool fUseMcfg;
264 /** Primary NIC PCI address. */
265 uint32_t u32NicPciAddress;
266 /** Primary audio card PCI address. */
267 uint32_t u32AudioPciAddress;
268 /** Flag whether S1 power state is enabled. */
269 bool fS1Enabled;
270 /** Flag whether S4 power state is enabled. */
271 bool fS4Enabled;
272 /** Flag whether S1 triggers a state save. */
273 bool fSuspendToSavedState;
274 /** Flag whether to set WAK_STS on resume (restore included). */
275 bool fSetWakeupOnResume;
276 /** PCI address of the IO controller device. */
277 uint32_t u32IocPciAddress;
278 /** PCI address of the host bus controller device. */
279 uint32_t u32HbcPciAddress;
280 /* Physical address of PCI config space MMIO region */
281 uint64_t u64PciConfigMMioAddress;
282 /* Length of PCI config space MMIO region */
283 uint64_t u64PciConfigMMioLength;
284
285 /** ACPI port base interface. */
286 PDMIBASE IBase;
287 /** ACPI port interface. */
288 PDMIACPIPORT IACPIPort;
289 /** Pointer to the device instance. */
290 PPDMDEVINSR3 pDevIns;
291 /** Pointer to the driver base interface. */
292 R3PTRTYPE(PPDMIBASE) pDrvBase;
293 /** Pointer to the driver connector interface. */
294 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
295
296 /** Pointer to default PCI config read function. */
297 R3PTRTYPE(PFNPCICONFIGREAD) pfnAcpiPciConfigRead;
298 /** Pointer to default PCI config write function. */
299 R3PTRTYPE(PFNPCICONFIGWRITE) pfnAcpiPciConfigWrite;
300} ACPIState;
301
302#pragma pack(1)
303
304/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
305struct ACPIGENADDR
306{
307 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
308 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
309 uint8_t u8RegisterBitOffset; /**< bit offset of register */
310 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
311 uint64_t u64Address; /**< 64-bit address of register */
312};
313AssertCompileSize(ACPIGENADDR, 12);
314
315/** Root System Description Pointer */
316struct ACPITBLRSDP
317{
318 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
319 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
320 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
321 uint8_t u8Revision; /**< revision number, currently 2 */
322#define ACPI_REVISION 2 /**< ACPI 3.0 */
323 uint32_t u32RSDT; /**< phys addr of RSDT */
324 uint32_t u32Length; /**< bytes of this table */
325 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
326 uint8_t u8ExtChecksum; /**< checksum of entire table */
327 uint8_t u8Reserved[3]; /**< reserved */
328};
329AssertCompileSize(ACPITBLRSDP, 36);
330
331/** System Description Table Header */
332struct ACPITBLHEADER
333{
334 uint8_t au8Signature[4]; /**< table identifier */
335 uint32_t u32Length; /**< length of the table including header */
336 uint8_t u8Revision; /**< revision number */
337 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
338 uint8_t au8OemId[6]; /**< OEM-supplied string */
339 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
340 uint32_t u32OemRevision; /**< OEM-supplied revision number */
341 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
342 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
343};
344AssertCompileSize(ACPITBLHEADER, 36);
345
346/** Root System Description Table */
347struct ACPITBLRSDT
348{
349 ACPITBLHEADER header;
350 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
351};
352AssertCompileSize(ACPITBLRSDT, 40);
353
354/** Extended System Description Table */
355struct ACPITBLXSDT
356{
357 ACPITBLHEADER header;
358 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
359};
360AssertCompileSize(ACPITBLXSDT, 44);
361
362/** Fixed ACPI Description Table */
363struct ACPITBLFADT
364{
365 ACPITBLHEADER header;
366 uint32_t u32FACS; /**< phys. address of FACS */
367 uint32_t u32DSDT; /**< phys. address of DSDT */
368 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
369#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
370#define INT_MODEL_MULTIPLE_APIC 2
371 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
372 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
373#define SCI_INT 9
374 uint32_t u32SMICmd; /**< system port address of SMI command port */
375#define SMI_CMD 0x0000442e
376 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownership of ACPIregs */
377#define ACPI_ENABLE 0xa1
378 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownership of ACPIregs */
379#define ACPI_DISABLE 0xa0
380 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
381 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
382 state control responsibility */
383 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
384 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
385 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
386 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
387 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
388 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
389 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
390 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
391 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
392 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
393 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
394 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
395 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
396#define GPE0_BLK_LEN 2
397 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
398#define GPE1_BLK_LEN 0
399 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
400#define GPE1_BASE 0
401 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
402 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
403#define P_LVL2_LAT 101 /**< C2 state not supported */
404 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
405#define P_LVL3_LAT 1001 /**< C3 state not supported */
406 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
407 lines from any processors memory caches */
408#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
409 uint16_t u16FlushStride; /**< cache line width */
410#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
411 uint8_t u8DutyOffset;
412 uint8_t u8DutyWidth;
413 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
414 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
415 uint8_t u8Century; /**< RTC CMOS RAM index of century */
416 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
417#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
418 (COM too?) */
419#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
420#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
421 uint8_t u8Must0_0; /**< must be 0 */
422 uint32_t u32Flags; /**< fixed feature flags */
423#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
424#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
425#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
426#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
427#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
428#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
429#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
430#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
431#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
432#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
433#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
434#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
435#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
436#define FADT_FL_CPU_SW_SLP RT_BIT(13)
437#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
438#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
439#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
440#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
441#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
442#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
443
444 /** Start of the ACPI 2.0 extension. */
445 ACPIGENADDR ResetReg; /**< ext addr of reset register */
446 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
447#define ACPI_RESET_REG_VAL 0x10
448 uint8_t au8Must0_1[3]; /**< must be 0 */
449 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
450 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
451 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
452 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
453 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
454 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
455 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
456 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
457 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
458 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
459};
460AssertCompileSize(ACPITBLFADT, 244);
461#define ACPITBLFADT_VERSION1_SIZE RT_OFFSETOF(ACPITBLFADT, ResetReg)
462
463/** Firmware ACPI Control Structure */
464struct ACPITBLFACS
465{
466 uint8_t au8Signature[4]; /**< 'FACS' */
467 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
468 uint32_t u32HWSignature; /**< systems HW signature at last boot */
469 uint32_t u32FWVector; /**< address of waking vector */
470 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
471 uint32_t u32Flags; /**< FACS flags */
472 uint64_t u64X_FWVector; /**< 64-bit waking vector */
473 uint8_t u8Version; /**< version of this table */
474 uint8_t au8Reserved[31]; /**< zero */
475};
476AssertCompileSize(ACPITBLFACS, 64);
477
478/** Processor Local APIC Structure */
479struct ACPITBLLAPIC
480{
481 uint8_t u8Type; /**< 0 = LAPIC */
482 uint8_t u8Length; /**< 8 */
483 uint8_t u8ProcId; /**< processor ID */
484 uint8_t u8ApicId; /**< local APIC ID */
485 uint32_t u32Flags; /**< Flags */
486#define LAPIC_ENABLED 0x1
487};
488AssertCompileSize(ACPITBLLAPIC, 8);
489
490/** I/O APIC Structure */
491struct ACPITBLIOAPIC
492{
493 uint8_t u8Type; /**< 1 == I/O APIC */
494 uint8_t u8Length; /**< 12 */
495 uint8_t u8IOApicId; /**< I/O APIC ID */
496 uint8_t u8Reserved; /**< 0 */
497 uint32_t u32Address; /**< phys address to access I/O APIC */
498 uint32_t u32GSIB; /**< global system interrupt number to start */
499};
500AssertCompileSize(ACPITBLIOAPIC, 12);
501
502/** Interrupt Source Override Structure */
503struct ACPITBLISO
504{
505 uint8_t u8Type; /**< 2 == Interrupt Source Override*/
506 uint8_t u8Length; /**< 10 */
507 uint8_t u8Bus; /**< Bus */
508 uint8_t u8Source; /**< Bus-relative interrupt source (IRQ) */
509 uint32_t u32GSI; /**< Global System Interrupt */
510 uint16_t u16Flags; /**< MPS INTI flags Global */
511};
512AssertCompileSize(ACPITBLISO, 10);
513#define NUMBER_OF_IRQ_SOURCE_OVERRIDES 2
514
515/** HPET Descriptor Structure */
516struct ACPITBLHPET
517{
518 ACPITBLHEADER aHeader;
519 uint32_t u32Id; /**< hardware ID of event timer block
520 [31:16] PCI vendor ID of first timer block
521 [15] legacy replacement IRQ routing capable
522 [14] reserved
523 [13] COUNT_SIZE_CAP counter size
524 [12:8] number of comparators in first timer block
525 [7:0] hardware rev ID */
526 ACPIGENADDR HpetAddr; /**< lower 32-bit base address */
527 uint8_t u32Number; /**< sequence number starting at 0 */
528 uint16_t u32MinTick; /**< minimum clock ticks which can be set without
529 lost interrupts while the counter is programmed
530 to operate in periodic mode. Unit: clock tick. */
531 uint8_t u8Attributes; /**< page protection and OEM attribute. */
532};
533AssertCompileSize(ACPITBLHPET, 56);
534
535/** MCFG Descriptor Structure */
536typedef struct ACPITBLMCFG
537{
538 ACPITBLHEADER aHeader;
539 uint64_t u64Reserved;
540} ACPITBLMCFG;
541AssertCompileSize(ACPITBLMCFG, 44);
542
543/** Number of such entries can be computed from the whole table length in header */
544typedef struct ACPITBLMCFGENTRY
545{
546 uint64_t u64BaseAddress;
547 uint16_t u16PciSegmentGroup;
548 uint8_t u8StartBus;
549 uint8_t u8EndBus;
550 uint32_t u32Reserved;
551} ACPITBLMCFGENTRY;
552AssertCompileSize(ACPITBLMCFGENTRY, 16);
553
554# ifdef IN_RING3 /** @todo r=bird: Move this down to where it's used. */
555
556# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
557
558/**
559 * Multiple APIC Description Table.
560 *
561 * This structure looks somewhat convoluted due layout of MADT table in MP case.
562 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
563 * use regular C structure and proxy to raw memory instead.
564 */
565class AcpiTableMADT
566{
567 /**
568 * All actual data stored in dynamically allocated memory pointed by this field.
569 */
570 uint8_t *m_pbData;
571 /**
572 * Number of CPU entries in this MADT.
573 */
574 uint32_t m_cCpus;
575
576 /**
577 * Number of interrupt overrides.
578 */
579 uint32_t m_cIsos;
580
581public:
582 /**
583 * Address of ACPI header
584 */
585 inline ACPITBLHEADER *header_addr(void) const
586 {
587 return (ACPITBLHEADER *)m_pbData;
588 }
589
590 /**
591 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
592 * although address is the same for all of them.
593 */
594 inline uint32_t *u32LAPIC_addr(void) const
595 {
596 return (uint32_t *)(header_addr() + 1);
597 }
598
599 /**
600 * Address of APIC flags
601 */
602 inline uint32_t *u32Flags_addr(void) const
603 {
604 return (uint32_t *)(u32LAPIC_addr() + 1);
605 }
606
607 /**
608 * Address of ISO description
609 */
610 inline ACPITBLISO *ISO_addr(void) const
611 {
612 return (ACPITBLISO *)(u32Flags_addr() + 1);
613 }
614
615 /**
616 * Address of per-CPU LAPIC descriptions
617 */
618 inline ACPITBLLAPIC *LApics_addr(void) const
619 {
620 return (ACPITBLLAPIC *)(ISO_addr() + m_cIsos);
621 }
622
623 /**
624 * Address of IO APIC description
625 */
626 inline ACPITBLIOAPIC *IOApic_addr(void) const
627 {
628 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
629 }
630
631 /**
632 * Size of MADT.
633 * Note that this function assumes IOApic to be the last field in structure.
634 */
635 inline uint32_t size(void) const
636 {
637 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
638 }
639
640 /**
641 * Raw data of MADT.
642 */
643 inline const uint8_t *data(void) const
644 {
645 return m_pbData;
646 }
647
648 /**
649 * Size of MADT for given ACPI config, useful to compute layout.
650 */
651 static uint32_t sizeFor(ACPIState *s, uint32_t cIsos)
652 {
653 return AcpiTableMADT(s->cCpus, cIsos).size();
654 }
655
656 /*
657 * Constructor, only works in Ring 3, doesn't look like a big deal.
658 */
659 AcpiTableMADT(uint32_t cCpus, uint32_t cIsos)
660 {
661 m_cCpus = cCpus;
662 m_cIsos = cIsos;
663 m_pbData = NULL; /* size() uses this and gcc will complain if not initialized. */
664 uint32_t cb = size();
665 m_pbData = (uint8_t *)RTMemAllocZ(cb);
666 }
667
668 ~AcpiTableMADT()
669 {
670 RTMemFree(m_pbData);
671 }
672};
673# endif /* IN_RING3 */
674
675#pragma pack()
676
677
678#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
679/*******************************************************************************
680* Internal Functions *
681*******************************************************************************/
682RT_C_DECLS_BEGIN
683PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
684#ifdef IN_RING3
685PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
686PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
687PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
688PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
689PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
690PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
691PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
692PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
693PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
694PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
695PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
696PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
697PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
698PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
699PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
700PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
701# ifdef DEBUG_ACPI
702PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
703PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
704# endif
705#endif /* IN_RING3 */
706RT_C_DECLS_END
707
708
709#ifdef IN_RING3
710
711static RTIOPORT acpiPmPort(ACPIState* pAcpi, int32_t offset)
712{
713 Assert(pAcpi->uPmIoPortBase != 0);
714
715 if (offset == -1)
716 return 0;
717
718 return RTIOPORT(pAcpi->uPmIoPortBase + offset);
719}
720
721/* Simple acpiChecksum: all the bytes must add up to 0. */
722static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
723{
724 uint8_t sum = 0;
725 for (size_t i = 0; i < len; ++i)
726 sum += data[i];
727 return -sum;
728}
729
730static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
731 uint32_t u32Length, uint8_t u8Revision)
732{
733 memcpy(header->au8Signature, au8Signature, 4);
734 header->u32Length = RT_H2LE_U32(u32Length);
735 header->u8Revision = u8Revision;
736 memcpy(header->au8OemId, "VBOX ", 6);
737 memcpy(header->au8OemTabId, "VBOX", 4);
738 memcpy(header->au8OemTabId+4, au8Signature, 4);
739 header->u32OemRevision = RT_H2LE_U32(1);
740 memcpy(header->au8CreatorId, "ASL ", 4);
741 header->u32CreatorRev = RT_H2LE_U32(0x61);
742}
743
744static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
745 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
746 uint8_t u8AccessSize, uint64_t u64Address)
747{
748 g->u8AddressSpaceId = u8AddressSpaceId;
749 g->u8RegisterBitWidth = u8RegisterBitWidth;
750 g->u8RegisterBitOffset = u8RegisterBitOffset;
751 g->u8AccessSize = u8AccessSize;
752 g->u64Address = RT_H2LE_U64(u64Address);
753}
754
755static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
756{
757 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
758}
759
760/** Differentiated System Description Table (DSDT) */
761
762static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr,
763 void* pPtr, size_t uDsdtLen)
764{
765 acpiPhyscpy(s, addr, pPtr, uDsdtLen);
766}
767
768/** Secondary System Description Table (SSDT) */
769
770static void acpiSetupSSDT(ACPIState *s, RTGCPHYS32 addr,
771 void* pPtr, size_t uSsdtLen)
772{
773 acpiPhyscpy(s, addr, pPtr, uSsdtLen);
774}
775
776/** Firmware ACPI Control Structure (FACS) */
777static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
778{
779 ACPITBLFACS facs;
780
781 memset(&facs, 0, sizeof(facs));
782 memcpy(facs.au8Signature, "FACS", 4);
783 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
784 facs.u32HWSignature = RT_H2LE_U32(0);
785 facs.u32FWVector = RT_H2LE_U32(0);
786 facs.u32GlobalLock = RT_H2LE_U32(0);
787 facs.u32Flags = RT_H2LE_U32(0);
788 facs.u64X_FWVector = RT_H2LE_U64(0);
789 facs.u8Version = 1;
790
791 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
792}
793
794/** Fixed ACPI Description Table (FADT aka FACP) */
795static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 GCPhysAcpi1, RTGCPHYS32 GCPhysAcpi2, RTGCPHYS32 GCPhysFacs, RTGCPHYS GCPhysDsdt)
796{
797 ACPITBLFADT fadt;
798
799 /* First the ACPI version 2+ version of the structure. */
800 memset(&fadt, 0, sizeof(fadt));
801 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
802 fadt.u32FACS = RT_H2LE_U32(GCPhysFacs);
803 fadt.u32DSDT = RT_H2LE_U32(GCPhysDsdt);
804 fadt.u8IntModel = 0; /* dropped from the ACPI 2.0 spec. */
805 fadt.u8PreferredPMProfile = 0; /* unspecified */
806 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
807 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
808 fadt.u8AcpiEnable = ACPI_ENABLE;
809 fadt.u8AcpiDisable = ACPI_DISABLE;
810 fadt.u8S4BIOSReq = 0;
811 fadt.u8PStateCnt = 0;
812 fadt.u32PM1aEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_EVT_OFFSET));
813 fadt.u32PM1bEVTBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_EVT_OFFSET));
814 fadt.u32PM1aCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1a_CTL_OFFSET));
815 fadt.u32PM1bCTLBLK = RT_H2LE_U32(acpiPmPort(s, PM1b_CTL_OFFSET));
816 fadt.u32PM2CTLBLK = RT_H2LE_U32(acpiPmPort(s, PM2_CTL_OFFSET));
817 fadt.u32PMTMRBLK = RT_H2LE_U32(acpiPmPort(s, PM_TMR_OFFSET));
818 fadt.u32GPE0BLK = RT_H2LE_U32(acpiPmPort(s, GPE0_OFFSET));
819 fadt.u32GPE1BLK = RT_H2LE_U32(acpiPmPort(s, GPE1_OFFSET));
820 fadt.u8PM1EVTLEN = 4;
821 fadt.u8PM1CTLLEN = 2;
822 fadt.u8PM2CTLLEN = 0;
823 fadt.u8PMTMLEN = 4;
824 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
825 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
826 fadt.u8GPE1BASE = GPE1_BASE;
827 fadt.u8CSTCNT = 0;
828 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
829 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
830 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
831 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
832 fadt.u8DutyOffset = 0;
833 fadt.u8DutyWidth = 0;
834 fadt.u8DayAlarm = 0;
835 fadt.u8MonAlarm = 0;
836 fadt.u8Century = 0;
837 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
838 /** @note WBINVD is required for ACPI versions newer than 1.0 */
839 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
840 | FADT_FL_FIX_RTC
841 | FADT_FL_TMR_VAL_EXT
842 | FADT_FL_RESET_REG_SUP);
843
844 /* We have to force physical APIC mode or Linux can't use more than 8 CPUs */
845 if (s->fCpuHotPlug)
846 fadt.u32Flags |= RT_H2LE_U32(FADT_FL_FORCE_APIC_PHYS_DEST_MODE);
847
848 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
849 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
850 fadt.u64XFACS = RT_H2LE_U64((uint64_t)GCPhysFacs);
851 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)GCPhysDsdt);
852 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, acpiPmPort(s, PM1a_EVT_OFFSET));
853 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_EVT_OFFSET));
854 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, acpiPmPort(s, PM1a_CTL_OFFSET));
855 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM1b_CTL_OFFSET));
856 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, acpiPmPort(s, PM2_CTL_OFFSET));
857 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, acpiPmPort(s, PM_TMR_OFFSET));
858 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, acpiPmPort(s, GPE0_OFFSET));
859 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, acpiPmPort(s, GPE1_OFFSET));
860 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
861 acpiPhyscpy(s, GCPhysAcpi2, &fadt, sizeof(fadt));
862
863 /* Now the ACPI 1.0 version. */
864 fadt.header.u32Length = ACPITBLFADT_VERSION1_SIZE;
865 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
866 fadt.header.u8Checksum = 0; /* Must be zeroed before recalculating checksum! */
867 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, ACPITBLFADT_VERSION1_SIZE);
868 acpiPhyscpy(s, GCPhysAcpi1, &fadt, ACPITBLFADT_VERSION1_SIZE);
869}
870
871/**
872 * Root System Description Table.
873 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
874 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
875 */
876static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
877{
878 ACPITBLRSDT *rsdt;
879 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
880
881 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
882 if (!rsdt)
883 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
884
885 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
886 for (unsigned int i = 0; i < nb_entries; ++i)
887 {
888 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
889 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
890 }
891 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
892 acpiPhyscpy(s, addr, rsdt, size);
893 RTMemFree(rsdt);
894 return VINF_SUCCESS;
895}
896
897/** Extended System Description Table. */
898static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
899{
900 ACPITBLXSDT *xsdt;
901 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
902
903 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
904 if (!xsdt)
905 return VERR_NO_TMP_MEMORY;
906
907 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
908 for (unsigned int i = 0; i < nb_entries; ++i)
909 {
910 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
911 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
912 }
913 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
914 acpiPhyscpy(s, addr, xsdt, size);
915 RTMemFree(xsdt);
916 return VINF_SUCCESS;
917}
918
919/** Root System Description Pointer (RSDP) */
920static void acpiSetupRSDP(ACPITBLRSDP *rsdp, RTGCPHYS32 GCPhysRsdt, RTGCPHYS GCPhysXsdt)
921{
922 memset(rsdp, 0, sizeof(*rsdp));
923
924 /* ACPI 1.0 part (RSDT */
925 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
926 memcpy(rsdp->au8OemId, "VBOX ", 6);
927 rsdp->u8Revision = ACPI_REVISION;
928 rsdp->u32RSDT = RT_H2LE_U32(GCPhysRsdt);
929 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
930
931 /* ACPI 2.0 part (XSDT) */
932 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
933 rsdp->u64XSDT = RT_H2LE_U64(GCPhysXsdt);
934 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
935}
936
937/**
938 * Multiple APIC Description Table.
939 *
940 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
941 *
942 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
943 */
944static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
945{
946 uint16_t cpus = s->cCpus;
947 AcpiTableMADT madt(cpus, NUMBER_OF_IRQ_SOURCE_OVERRIDES);
948
949 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
950
951 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
952 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
953
954 /* LAPICs records */
955 ACPITBLLAPIC* lapic = madt.LApics_addr();
956 for (uint16_t i = 0; i < cpus; i++)
957 {
958 lapic->u8Type = 0;
959 lapic->u8Length = sizeof(ACPITBLLAPIC);
960 lapic->u8ProcId = i;
961 /** Must match numbering convention in MPTABLES */
962 lapic->u8ApicId = i;
963 lapic->u32Flags = VMCPUSET_IS_PRESENT(&s->CpuSetAttached, i) ? RT_H2LE_U32(LAPIC_ENABLED) : 0;
964 lapic++;
965 }
966
967 /* IO-APIC record */
968 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
969 ioapic->u8Type = 1;
970 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
971 /** Must match MP tables ID */
972 ioapic->u8IOApicId = cpus;
973 ioapic->u8Reserved = 0;
974 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
975 ioapic->u32GSIB = RT_H2LE_U32(0);
976
977 /* Interrupt Source Overrides */
978 /* Flags:
979 bits[3:2]:
980 00 conforms to the bus
981 01 edge-triggered
982 10 reserved
983 11 level-triggered
984 bits[1:0]
985 00 conforms to the bus
986 01 active-high
987 10 reserved
988 11 active-low */
989 /* If changing, also update PDMIsaSetIrq() and MPS */
990 ACPITBLISO* isos = madt.ISO_addr();
991 /* Timer interrupt rule IRQ0 to GSI2 */
992 isos[0].u8Type = 2;
993 isos[0].u8Length = sizeof(ACPITBLISO);
994 isos[0].u8Bus = 0; /* Must be 0 */
995 isos[0].u8Source = 0; /* IRQ0 */
996 isos[0].u32GSI = 2; /* connected to pin 2 */
997 isos[0].u16Flags = 0; /* conform to the bus */
998
999 /* ACPI interrupt rule - IRQ9 to GSI9 */
1000 isos[1].u8Type = 2;
1001 isos[1].u8Length = sizeof(ACPITBLISO);
1002 isos[1].u8Bus = 0; /* Must be 0 */
1003 isos[1].u8Source = 9; /* IRQ9 */
1004 isos[1].u32GSI = 9; /* connected to pin 9 */
1005 isos[1].u16Flags = 0xd; /* active high, level triggered */
1006 Assert(NUMBER_OF_IRQ_SOURCE_OVERRIDES == 2);
1007
1008 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
1009 acpiPhyscpy(s, addr, madt.data(), madt.size());
1010}
1011
1012
1013/** High Performance Event Timer (HPET) descriptor */
1014static void acpiSetupHPET(ACPIState *s, RTGCPHYS32 addr)
1015{
1016 ACPITBLHPET hpet;
1017
1018 memset(&hpet, 0, sizeof(hpet));
1019
1020 acpiPrepareHeader(&hpet.aHeader, "HPET", sizeof(hpet), 1);
1021 /* Keep base address consistent with appropriate DSDT entry (vbox.dsl) */
1022 acpiWriteGenericAddr(&hpet.HpetAddr,
1023 0 /* Memory address space */,
1024 64 /* Register bit width */,
1025 0 /* Bit offset */,
1026 0, /* Register access size, is it correct? */
1027 0xfed00000 /* Address */);
1028
1029 hpet.u32Id = 0x8086a201; /* must match what HPET ID returns, is it correct ? */
1030 hpet.u32Number = 0;
1031 hpet.u32MinTick = 4096;
1032 hpet.u8Attributes = 0;
1033
1034 hpet.aHeader.u8Checksum = acpiChecksum((uint8_t *)&hpet, sizeof(hpet));
1035
1036 acpiPhyscpy(s, addr, (const uint8_t *)&hpet, sizeof(hpet));
1037}
1038
1039/** MMCONFIG PCI config space access (MCFG) descriptor */
1040static void acpiSetupMCFG(ACPIState *s, RTGCPHYS32 addr)
1041{
1042 struct {
1043 ACPITBLMCFG hdr;
1044 ACPITBLMCFGENTRY entry;
1045 } tbl;
1046
1047 uint8_t u8StartBus = 0;
1048 uint8_t u8EndBus = (s->u64PciConfigMMioLength >> 20) - 1;
1049
1050 memset(&tbl, 0, sizeof(tbl));
1051
1052 acpiPrepareHeader(&tbl.hdr.aHeader, "MCFG", sizeof(tbl), 1);
1053 tbl.entry.u64BaseAddress = s->u64PciConfigMMioAddress;
1054 tbl.entry.u8StartBus = u8StartBus;
1055 tbl.entry.u8EndBus = u8EndBus;
1056 // u16PciSegmentGroup must match _SEG in ACPI table
1057
1058 tbl.hdr.aHeader.u8Checksum = acpiChecksum((uint8_t *)&tbl, sizeof(tbl));
1059
1060 acpiPhyscpy(s, addr, (const uint8_t *)&tbl, sizeof(tbl));
1061}
1062
1063/* SCI IRQ */
1064DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
1065{
1066 if (s->pm1a_ctl & SCI_EN)
1067 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
1068}
1069
1070DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
1071{
1072 return en & ~(RSR_EN | IGN_EN);
1073}
1074
1075DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
1076{
1077 return sts & ~(RSR_STS | IGN_STS);
1078}
1079
1080DECLINLINE(int) pm1a_level(ACPIState *s)
1081{
1082 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
1083}
1084
1085DECLINLINE(int) gpe0_level(ACPIState *s)
1086{
1087 return (s->gpe0_en & s->gpe0_sts) != 0;
1088}
1089
1090static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
1091{
1092 int old_level, new_level;
1093
1094 if (gpe0_level(s))
1095 return;
1096
1097 old_level = pm1a_level(s);
1098 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
1099
1100 Log(("update_pm1a() old=%x new=%x\n", old_level, new_level));
1101
1102 s->pm1a_en = en;
1103 s->pm1a_sts = sts;
1104
1105 if (new_level != old_level)
1106 acpiSetIrq(s, new_level);
1107}
1108
1109static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
1110{
1111 int old_level, new_level;
1112
1113 if (pm1a_level(s))
1114 return;
1115
1116 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
1117 new_level = (en & sts) != 0;
1118
1119 s->gpe0_en = en;
1120 s->gpe0_sts = sts;
1121
1122 if (new_level != old_level)
1123 acpiSetIrq(s, new_level);
1124}
1125
1126static int acpiPowerDown(ACPIState *s)
1127{
1128 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
1129 if (RT_FAILURE(rc))
1130 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
1131 return rc;
1132}
1133
1134static int acpiSleep(ACPIState *pThis)
1135{
1136 int rc;
1137
1138 /* We must set WAK_STS on resume (includes restore) so the guest knows that
1139 we've woken up and can continue executing code. The guest is probably
1140 reading the PMSTS register in a loop to check this. */
1141 pThis->fSetWakeupOnResume = true;
1142 if (pThis->fSuspendToSavedState)
1143 {
1144 rc = PDMDevHlpVMSuspendSaveAndPowerOff(pThis->pDevIns);
1145 if (rc != VERR_NOT_SUPPORTED)
1146 AssertRC(rc);
1147 else
1148 {
1149 LogRel(("ACPI: PDMDevHlpVMSuspendSaveAndPowerOff is not supported, falling back to suspend-only\n"));
1150 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
1151 AssertRC(rc);
1152 }
1153 }
1154 else
1155 {
1156 rc = PDMDevHlpVMSuspend(pThis->pDevIns);
1157 AssertRC(rc);
1158 }
1159 return rc;
1160}
1161
1162/** Converts a ACPI port interface pointer to an ACPI state pointer. */
1163#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
1164
1165/**
1166 * Send an ACPI power off event.
1167 *
1168 * @returns VBox status code
1169 * @param pInterface Pointer to the interface structure containing the called function pointer.
1170 */
1171static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
1172{
1173 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
1174 Log(("acpiPowerButtonPress: handled=%d status=%x\n", s->fPowerButtonHandled, s->pm1a_sts));
1175 s->fPowerButtonHandled = false;
1176 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
1177 return VINF_SUCCESS;
1178}
1179
1180/**
1181 * Check if the ACPI power button event was handled.
1182 *
1183 * @returns VBox status code
1184 * @param pInterface Pointer to the interface structure containing the called function pointer.
1185 * @param pfHandled Return true if the power button event was handled by the guest.
1186 */
1187static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
1188{
1189 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
1190 *pfHandled = s->fPowerButtonHandled;
1191 return VINF_SUCCESS;
1192}
1193
1194/**
1195 * Check if the Guest entered into G0 (working) or G1 (sleeping).
1196 *
1197 * @returns VBox status code
1198 * @param pInterface Pointer to the interface structure containing the called function pointer.
1199 * @param pfEntered Return true if the guest entered the ACPI mode.
1200 */
1201static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
1202{
1203 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
1204 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
1205 return VINF_SUCCESS;
1206}
1207
1208static DECLCALLBACK(int) acpiGetCpuStatus(PPDMIACPIPORT pInterface, unsigned uCpu, bool *pfLocked)
1209{
1210 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
1211 *pfLocked = VMCPUSET_IS_PRESENT(&s->CpuSetLocked, uCpu);
1212 return VINF_SUCCESS;
1213}
1214
1215/**
1216 * Send an ACPI sleep button event.
1217 *
1218 * @returns VBox status code
1219 * @param pInterface Pointer to the interface structure containing the called function pointer.
1220 */
1221static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
1222{
1223 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
1224 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
1225 return VINF_SUCCESS;
1226}
1227
1228/* PM1a_EVT_BLK enable */
1229static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
1230{
1231 uint16_t val = s->pm1a_en;
1232 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
1233 return val;
1234}
1235
1236static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
1237{
1238 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
1239 val &= ~(RSR_EN | IGN_EN);
1240 update_pm1a(s, s->pm1a_sts, val);
1241}
1242
1243/* PM1a_EVT_BLK status */
1244static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
1245{
1246 uint16_t val = s->pm1a_sts;
1247 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
1248 return val;
1249}
1250
1251static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
1252{
1253 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
1254 if (val & PWRBTN_STS)
1255 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1256 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
1257 update_pm1a(s, val, s->pm1a_en);
1258}
1259
1260/* PM1a_CTL_BLK */
1261static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
1262{
1263 uint16_t val = s->pm1a_ctl;
1264 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
1265 return val;
1266}
1267
1268static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
1269{
1270 uint32_t uSleepState;
1271
1272 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
1273 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1274
1275 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1276 if (uSleepState != s->uSleepState)
1277 {
1278 s->uSleepState = uSleepState;
1279 switch (uSleepState)
1280 {
1281 case 0x00: /* S0 */
1282 break;
1283 case 0x01: /* S1 */
1284 LogRel(("Entering S1 power state (powered-on suspend)\n"));
1285 return acpiSleep(s);
1286 case 0x04: /* S4 */
1287 LogRel(("Entering S4 power state (suspend to disk)\n"));
1288 return acpiPowerDown(s);/* Same behavior as S5 */
1289 case 0x05: /* S5 */
1290 LogRel(("Entering S5 power state (power down)\n"));
1291 return acpiPowerDown(s);
1292 default:
1293 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
1294 break;
1295 }
1296 }
1297 return VINF_SUCCESS;
1298}
1299
1300/* GPE0_BLK */
1301static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1302{
1303 uint8_t val = s->gpe0_en;
1304 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1305 return val;
1306}
1307
1308static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1309{
1310 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1311 update_gpe0(s, s->gpe0_sts, val);
1312}
1313
1314static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1315{
1316 uint8_t val = s->gpe0_sts;
1317 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1318 return val;
1319}
1320
1321static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1322{
1323 val = s->gpe0_sts & ~val;
1324 update_gpe0(s, val, s->gpe0_en);
1325 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1326}
1327
1328static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1329{
1330 int rc = VINF_SUCCESS;
1331
1332 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1333 if (val == ACPI_RESET_REG_VAL)
1334 {
1335# ifndef IN_RING3
1336 rc = VINF_IOM_HC_IOPORT_WRITE;
1337# else /* IN_RING3 */
1338 rc = PDMDevHlpVMReset(s->pDevIns);
1339# endif /* !IN_RING3 */
1340 }
1341 return rc;
1342}
1343
1344/* SMI */
1345static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1346{
1347 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1348 if (val == ACPI_ENABLE)
1349 s->pm1a_ctl |= SCI_EN;
1350 else if (val == ACPI_DISABLE)
1351 s->pm1a_ctl &= ~SCI_EN;
1352 else
1353 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1354}
1355
1356static uint32_t find_rsdp_space(void)
1357{
1358 return 0xe0000;
1359}
1360
1361static int acpiPMTimerReset(ACPIState *s)
1362{
1363 uint64_t interval, freq;
1364
1365 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1366 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1367 Log(("interval = %RU64\n", interval));
1368 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1369
1370 return VINF_SUCCESS;
1371}
1372
1373static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1374{
1375 ACPIState *s = (ACPIState *)pvUser;
1376
1377 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1378 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1379 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1380
1381 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1382 acpiPMTimerReset(s);
1383}
1384
1385/**
1386 * _BST method.
1387 */
1388static int acpiFetchBatteryStatus(ACPIState *s)
1389{
1390 uint32_t *p = s->au8BatteryInfo;
1391 bool fPresent; /* battery present? */
1392 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1393 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1394 uint32_t hostPresentRate; /* 0..1000 */
1395 int rc;
1396
1397 if (!s->pDrv)
1398 return VINF_SUCCESS;
1399 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1400 &hostBatteryState, &hostPresentRate);
1401 AssertRC(rc);
1402
1403 /* default values */
1404 p[BAT_STATUS_STATE] = hostBatteryState;
1405 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1406 : hostPresentRate * 50; /* mW */
1407 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1408 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1409
1410 /* did we get a valid battery state? */
1411 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1412 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1413 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1414 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1415
1416 return VINF_SUCCESS;
1417}
1418
1419/**
1420 * _BIF method.
1421 */
1422static int acpiFetchBatteryInfo(ACPIState *s)
1423{
1424 uint32_t *p = s->au8BatteryInfo;
1425
1426 p[BAT_INFO_UNITS] = 0; /* mWh */
1427 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1428 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1429 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1430 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1431 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1432 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1433 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1434 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1435
1436 return VINF_SUCCESS;
1437}
1438
1439/**
1440 * _STA method.
1441 */
1442static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1443{
1444 bool fPresent; /* battery present? */
1445 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1446 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1447 uint32_t hostPresentRate; /* 0..1000 */
1448 int rc;
1449
1450 if (!s->pDrv)
1451 return 0;
1452 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1453 &hostBatteryState, &hostPresentRate);
1454 AssertRC(rc);
1455
1456 return fPresent
1457 ? STA_DEVICE_PRESENT_MASK /* present */
1458 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1459 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1460 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1461 | STA_BATTERY_PRESENT_MASK /* battery is present */
1462 : 0; /* device not present */
1463}
1464
1465static uint32_t acpiGetPowerSource(ACPIState *s)
1466{
1467 PDMACPIPOWERSOURCE ps;
1468
1469 /* query the current power source from the host driver */
1470 if (!s->pDrv)
1471 return AC_ONLINE;
1472 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1473 AssertRC(rc);
1474 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1475}
1476
1477PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1478{
1479 ACPIState *s = (ACPIState *)pvUser;
1480
1481 switch (cb)
1482 {
1483 case 4:
1484 u32 >>= s->u8IndexShift;
1485 /* see comment at the declaration of u8IndexShift */
1486 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1487 {
1488 s->u8IndexShift = 2;
1489 u32 >>= 2;
1490 }
1491 Assert(u32 < BAT_INDEX_LAST);
1492 s->uBatteryIndex = u32;
1493 break;
1494 default:
1495 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1496 break;
1497 }
1498 return VINF_SUCCESS;
1499}
1500
1501PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1502{
1503 ACPIState *s = (ACPIState *)pvUser;
1504
1505 switch (cb)
1506 {
1507 case 4:
1508 switch (s->uBatteryIndex)
1509 {
1510 case BAT_STATUS_STATE:
1511 acpiFetchBatteryStatus(s);
1512 case BAT_STATUS_PRESENT_RATE:
1513 case BAT_STATUS_REMAINING_CAPACITY:
1514 case BAT_STATUS_PRESENT_VOLTAGE:
1515 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1516 break;
1517
1518 case BAT_INFO_UNITS:
1519 acpiFetchBatteryInfo(s);
1520 case BAT_INFO_DESIGN_CAPACITY:
1521 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1522 case BAT_INFO_TECHNOLOGY:
1523 case BAT_INFO_DESIGN_VOLTAGE:
1524 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1525 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1526 case BAT_INFO_CAPACITY_GRANULARITY_1:
1527 case BAT_INFO_CAPACITY_GRANULARITY_2:
1528 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1529 break;
1530
1531 case BAT_DEVICE_STATUS:
1532 *pu32 = acpiGetBatteryDeviceStatus(s);
1533 break;
1534
1535 case BAT_POWER_SOURCE:
1536 *pu32 = acpiGetPowerSource(s);
1537 break;
1538
1539 default:
1540 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1541 break;
1542 }
1543 break;
1544 default:
1545 return VERR_IOM_IOPORT_UNUSED;
1546 }
1547 return VINF_SUCCESS;
1548}
1549
1550PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1551{
1552 ACPIState *s = (ACPIState *)pvUser;
1553
1554 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1555 switch (cb)
1556 {
1557 case 4:
1558 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1559 s->uSystemInfoIndex = u32;
1560 else
1561 {
1562 /* see comment at the declaration of u8IndexShift */
1563 if ((u32 > SYSTEM_INFO_INDEX_END) && (s->u8IndexShift == 0))
1564 {
1565 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1566 {
1567 s->u8IndexShift = 2;
1568 }
1569 }
1570
1571 u32 >>= s->u8IndexShift;
1572 Assert(u32 < SYSTEM_INFO_INDEX_END);
1573 s->uSystemInfoIndex = u32;
1574 }
1575 break;
1576
1577 default:
1578 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1579 break;
1580 }
1581 return VINF_SUCCESS;
1582}
1583
1584PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1585{
1586 ACPIState *s = (ACPIState *)pvUser;
1587
1588 switch (cb)
1589 {
1590 case 4:
1591 switch (s->uSystemInfoIndex)
1592 {
1593 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1594 *pu32 = s->cbRamLow;
1595 break;
1596
1597 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1598 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1599 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1600 break;
1601
1602 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1603 *pu32 = s->u8UseIOApic;
1604 break;
1605
1606 case SYSTEM_INFO_INDEX_HPET_STATUS:
1607 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1608 | STA_DEVICE_ENABLED_MASK
1609 | STA_DEVICE_SHOW_IN_UI_MASK
1610 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1611 : 0;
1612 break;
1613
1614 case SYSTEM_INFO_INDEX_SMC_STATUS:
1615 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1616 | STA_DEVICE_ENABLED_MASK
1617 /* no need to show this device in the UI */
1618 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1619 : 0;
1620 break;
1621
1622 case SYSTEM_INFO_INDEX_FDC_STATUS:
1623 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1624 | STA_DEVICE_ENABLED_MASK
1625 | STA_DEVICE_SHOW_IN_UI_MASK
1626 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1627 : 0;
1628 break;
1629
1630 case SYSTEM_INFO_INDEX_NIC_ADDRESS:
1631 *pu32 = s->u32NicPciAddress;
1632 break;
1633
1634 case SYSTEM_INFO_INDEX_AUDIO_ADDRESS:
1635 *pu32 = s->u32AudioPciAddress;
1636 break;
1637
1638 case SYSTEM_INFO_INDEX_POWER_STATES:
1639 *pu32 = RT_BIT(0) | RT_BIT(5); /* S1 and S5 always exposed */
1640 if (s->fS1Enabled) /* Optionally expose S1 and S4 */
1641 *pu32 |= RT_BIT(1);
1642 if (s->fS4Enabled)
1643 *pu32 |= RT_BIT(4);
1644 break;
1645
1646 case SYSTEM_INFO_INDEX_IOC_ADDRESS:
1647 *pu32 = s->u32IocPciAddress;
1648 break;
1649
1650 case SYSTEM_INFO_INDEX_HBC_ADDRESS:
1651 *pu32 = s->u32HbcPciAddress;
1652 break;
1653
1654 case SYSTEM_INFO_INDEX_PCI_BASE:
1655 /** @todo: couldn't MCFG be in 64-bit range? */
1656 Assert(s->u64PciConfigMMioAddress < 0xffffffff);
1657 *pu32 = (uint32_t)s->u64PciConfigMMioAddress;
1658 break;
1659
1660 case SYSTEM_INFO_INDEX_PCI_LENGTH:
1661 /** @todo: couldn't MCFG be in 64-bit range? */
1662 Assert(s->u64PciConfigMMioLength< 0xffffffff);
1663 *pu32 = (uint32_t)s->u64PciConfigMMioLength;
1664 break;
1665
1666 /* This is only for compatibility with older saved states that
1667 may include ACPI code that read these values. Legacy is
1668 a wonderful thing, isn't it? :-) */
1669 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1670 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1671 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1672 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1673 *pu32 = ( s->fShowCpu
1674 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1675 && VMCPUSET_IS_PRESENT(&s->CpuSetAttached,
1676 s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS))
1677 ? ( STA_DEVICE_PRESENT_MASK
1678 | STA_DEVICE_ENABLED_MASK
1679 | STA_DEVICE_SHOW_IN_UI_MASK
1680 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1681 : 0;
1682 break;
1683
1684 case SYSTEM_INFO_INDEX_RTC_STATUS:
1685 *pu32 = s->fShowRtc ? ( STA_DEVICE_PRESENT_MASK
1686 | STA_DEVICE_ENABLED_MASK
1687 | STA_DEVICE_SHOW_IN_UI_MASK
1688 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1689 : 0;
1690 break;
1691
1692 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1693 {
1694 if (s->idCpuLockCheck < VMM_MAX_CPU_COUNT)
1695 {
1696 *pu32 = VMCPUSET_IS_PRESENT(&s->CpuSetLocked, s->idCpuLockCheck);
1697 s->idCpuLockCheck = UINT32_C(0xffffffff); /* Make the entry invalid */
1698 }
1699 else
1700 {
1701 AssertMsgFailed(("ACPI: CPU lock check protocol violation\n"));
1702 /* Always return locked status just to be safe */
1703 *pu32 = 1;
1704 }
1705 break;
1706 }
1707
1708 case SYSTEM_INFO_INDEX_CPU_EVENT_TYPE:
1709 *pu32 = s->u32CpuEventType;
1710 break;
1711
1712 case SYSTEM_INFO_INDEX_CPU_EVENT:
1713 *pu32 = s->u32CpuEvent;
1714 break;
1715
1716 /* Solaris 9 tries to read from this index */
1717 case SYSTEM_INFO_INDEX_INVALID:
1718 *pu32 = 0;
1719 break;
1720
1721 default:
1722 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1723 break;
1724 }
1725 break;
1726
1727 default:
1728 return VERR_IOM_IOPORT_UNUSED;
1729 }
1730
1731 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1732 return VINF_SUCCESS;
1733}
1734
1735PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1736{
1737 ACPIState *s = (ACPIState *)pvUser;
1738
1739 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1740
1741 if (cb == 4)
1742 {
1743 switch (s->uSystemInfoIndex)
1744 {
1745 case SYSTEM_INFO_INDEX_INVALID:
1746 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1747 s->u8IndexShift = 0;
1748 break;
1749
1750 case SYSTEM_INFO_INDEX_VALID:
1751 AssertMsg(u32 == 0xbadc0de, ("u32=%u\n", u32));
1752 s->u8IndexShift = 2;
1753 break;
1754
1755 case SYSTEM_INFO_INDEX_CPU_LOCK_CHECK:
1756 s->idCpuLockCheck = u32;
1757 break;
1758
1759 case SYSTEM_INFO_INDEX_CPU_LOCKED:
1760 if (u32 < s->cCpus)
1761 VMCPUSET_DEL(&s->CpuSetLocked, u32); /* Unlock the CPU */
1762 else
1763 LogRel(("ACPI: CPU %u does not exist\n", u32));
1764 break;
1765
1766 default:
1767 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1768 Port, cb, u32, s->uSystemInfoIndex));
1769 break;
1770 }
1771 }
1772 else
1773 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1774 return VINF_SUCCESS;
1775}
1776
1777/** @todo Don't call functions, but do the job in the read/write handlers
1778 * here! */
1779
1780/* IO Helpers */
1781PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1782{
1783 switch (cb)
1784 {
1785 case 2:
1786 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1787 break;
1788 default:
1789 return VERR_IOM_IOPORT_UNUSED;
1790 }
1791 return VINF_SUCCESS;
1792}
1793
1794PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1795{
1796 switch (cb)
1797 {
1798 case 2:
1799 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1800 break;
1801 default:
1802 AssertMsgFailed(("PM1 status read: width %d\n", cb));
1803 return VERR_IOM_IOPORT_UNUSED;
1804 }
1805 return VINF_SUCCESS;
1806}
1807
1808PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1809{
1810 switch (cb)
1811 {
1812 case 2:
1813 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1814 break;
1815 default:
1816 AssertMsgFailed(("PM1 control read: width %d\n", cb));
1817 return VERR_IOM_IOPORT_UNUSED;
1818 }
1819 return VINF_SUCCESS;
1820}
1821
1822PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1823{
1824 switch (cb)
1825 {
1826 case 2:
1827 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1828 break;
1829 case 4:
1830 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32 & 0xffff);
1831 break;
1832 default:
1833 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1834 break;
1835 }
1836 return VINF_SUCCESS;
1837}
1838
1839PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1840{
1841 switch (cb)
1842 {
1843 case 2:
1844 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1845 break;
1846 case 4:
1847 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32 & 0xffff);
1848 break;
1849 default:
1850 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1851 break;
1852 }
1853 return VINF_SUCCESS;
1854}
1855
1856PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1857{
1858 switch (cb)
1859 {
1860 case 2:
1861 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1862 case 4:
1863 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32 & 0xffff);
1864 default:
1865 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1866 break;
1867 }
1868 return VINF_SUCCESS;
1869}
1870
1871#endif /* IN_RING3 */
1872
1873/**
1874 * PMTMR readable from host/guest.
1875 */
1876PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1877{
1878 if (cb == 4)
1879 {
1880 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1881 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1882 int64_t elapsed = now - s->pm_timer_initial;
1883
1884 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1885 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1886 return VINF_SUCCESS;
1887 }
1888 return VERR_IOM_IOPORT_UNUSED;
1889}
1890
1891#ifdef IN_RING3
1892
1893PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1894{
1895 switch (cb)
1896 {
1897 case 1:
1898 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1899 break;
1900 default:
1901 return VERR_IOM_IOPORT_UNUSED;
1902 }
1903 return VINF_SUCCESS;
1904}
1905
1906PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1907{
1908 switch (cb)
1909 {
1910 case 1:
1911 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1912 break;
1913 default:
1914 return VERR_IOM_IOPORT_UNUSED;
1915 }
1916 return VINF_SUCCESS;
1917}
1918
1919PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1920{
1921 switch (cb)
1922 {
1923 case 1:
1924 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1925 break;
1926 default:
1927 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1928 break;
1929 }
1930 return VINF_SUCCESS;
1931}
1932
1933PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1934{
1935 switch (cb)
1936 {
1937 case 1:
1938 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1939 break;
1940 default:
1941 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1942 break;
1943 }
1944 return VINF_SUCCESS;
1945}
1946
1947PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1948{
1949 switch (cb)
1950 {
1951 case 1:
1952 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1953 break;
1954 default:
1955 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1956 break;
1957 }
1958 return VINF_SUCCESS;
1959}
1960
1961PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1962{
1963 switch (cb)
1964 {
1965 case 1:
1966 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1967 default:
1968 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1969 break;
1970 }
1971 return VINF_SUCCESS;
1972}
1973
1974#ifdef DEBUG_ACPI
1975
1976PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1977{
1978 switch (cb)
1979 {
1980 case 1:
1981 Log(("%#x\n", u32 & 0xff));
1982 break;
1983 case 2:
1984 Log(("%#6x\n", u32 & 0xffff));
1985 case 4:
1986 Log(("%#10x\n", u32));
1987 break;
1988 default:
1989 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1990 break;
1991 }
1992 return VINF_SUCCESS;
1993}
1994
1995PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1996{
1997 switch (cb)
1998 {
1999 case 1:
2000 Log(("%c", u32 & 0xff));
2001 break;
2002 default:
2003 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
2004 break;
2005 }
2006 return VINF_SUCCESS;
2007}
2008
2009#endif /* DEBUG_ACPI */
2010
2011static int acpiRegisterPmHandlers(ACPIState* pThis)
2012{
2013 int rc = VINF_SUCCESS;
2014
2015#define R(offset, cnt, writer, reader, description) \
2016 do { \
2017 rc = PDMDevHlpIOPortRegister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt, pThis, writer, reader, \
2018 NULL, NULL, description); \
2019 if (RT_FAILURE(rc)) \
2020 return rc; \
2021 } while (0)
2022#define L (GPE0_BLK_LEN / 2)
2023
2024 R(PM1a_EVT_OFFSET+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
2025 R(PM1a_EVT_OFFSET, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
2026 R(PM1a_CTL_OFFSET, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
2027 R(PM_TMR_OFFSET, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
2028 R(GPE0_OFFSET + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
2029 R(GPE0_OFFSET, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
2030#undef L
2031#undef R
2032
2033 /* register RC stuff */
2034 if (pThis->fGCEnabled)
2035 {
2036 rc = PDMDevHlpIOPortRegisterRC(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
2037 1, 0, NULL, "acpiPMTmrRead",
2038 NULL, NULL, "ACPI PM Timer");
2039 AssertRCReturn(rc, rc);
2040 }
2041
2042 /* register R0 stuff */
2043 if (pThis->fR0Enabled)
2044 {
2045 rc = PDMDevHlpIOPortRegisterR0(pThis->pDevIns, acpiPmPort(pThis, PM_TMR_OFFSET),
2046 1, 0, NULL, "acpiPMTmrRead",
2047 NULL, NULL, "ACPI PM Timer");
2048 AssertRCReturn(rc, rc);
2049 }
2050
2051 return rc;
2052}
2053
2054static int acpiUnregisterPmHandlers(ACPIState *pThis)
2055{
2056#define U(offset, cnt) \
2057 do { \
2058 int rc = PDMDevHlpIOPortDeregister(pThis->pDevIns, acpiPmPort(pThis, offset), cnt); \
2059 AssertRCReturn(rc, rc); \
2060 } while (0)
2061#define L (GPE0_BLK_LEN / 2)
2062
2063 U(PM1a_EVT_OFFSET+2, 1);
2064 U(PM1a_EVT_OFFSET, 1);
2065 U(PM1a_CTL_OFFSET, 1);
2066 U(PM_TMR_OFFSET, 1);
2067 U(GPE0_OFFSET + L, L);
2068 U(GPE0_OFFSET, L);
2069#undef L
2070#undef U
2071
2072 return VINF_SUCCESS;
2073}
2074
2075/**
2076 * Saved state structure description, version 4.
2077 */
2078static const SSMFIELD g_AcpiSavedStateFields4[] =
2079{
2080 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2081 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2082 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2083 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
2084 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2085 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2086 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2087 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2088 SSMFIELD_ENTRY(ACPIState, u64RamSize),
2089 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2090 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
2091 SSMFIELD_ENTRY(ACPIState, uSleepState),
2092 SSMFIELD_ENTRY_TERM()
2093};
2094
2095/**
2096 * Saved state structure description, version 5.
2097 */
2098static const SSMFIELD g_AcpiSavedStateFields5[] =
2099{
2100 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2101 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2102 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2103 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
2104 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2105 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2106 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2107 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2108 SSMFIELD_ENTRY(ACPIState, uSleepState),
2109 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2110 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2111 SSMFIELD_ENTRY_TERM()
2112};
2113
2114/**
2115 * Saved state structure description, version 6.
2116 */
2117static const SSMFIELD g_AcpiSavedStateFields6[] =
2118{
2119 SSMFIELD_ENTRY(ACPIState, pm1a_en),
2120 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
2121 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
2122 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
2123 SSMFIELD_ENTRY(ACPIState, gpe0_en),
2124 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
2125 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
2126 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
2127 SSMFIELD_ENTRY(ACPIState, uSleepState),
2128 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
2129 SSMFIELD_ENTRY(ACPIState, uPmIoPortBase),
2130 SSMFIELD_ENTRY(ACPIState, fSuspendToSavedState),
2131 SSMFIELD_ENTRY_TERM()
2132};
2133
2134
2135/**
2136 * @callback_method_impl{FNSSMDEVSAVEEXEC}
2137 */
2138static DECLCALLBACK(int) acpiSaveState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
2139{
2140 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2141 return SSMR3PutStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
2142}
2143
2144/**
2145 * @callback_method_impl{FNSSMDEVLOADEXEC}
2146 */
2147static DECLCALLBACK(int) acpiLoadState(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
2148 uint32_t uVersion, uint32_t uPass)
2149{
2150 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2151 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2152
2153 /*
2154 * Unregister PM handlers, will register with actual base after state
2155 * successfully loaded.
2156 */
2157 int rc = acpiUnregisterPmHandlers(pThis);
2158 if (RT_FAILURE(rc))
2159 return rc;
2160
2161 switch (uVersion)
2162 {
2163 case 4:
2164 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields4[0]);
2165 break;
2166 case 5:
2167 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields5[0]);
2168 break;
2169 case 6:
2170 rc = SSMR3GetStruct(pSSMHandle, pThis, &g_AcpiSavedStateFields6[0]);
2171 break;
2172 default:
2173 rc = VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2174 break;
2175 }
2176 if (RT_SUCCESS(rc))
2177 {
2178 rc = acpiRegisterPmHandlers(pThis);
2179 if (RT_FAILURE(rc))
2180 return rc;
2181 rc = acpiFetchBatteryStatus(pThis);
2182 if (RT_FAILURE(rc))
2183 return rc;
2184 rc = acpiFetchBatteryInfo(pThis);
2185 if (RT_FAILURE(rc))
2186 return rc;
2187 rc = acpiPMTimerReset(pThis);
2188 if (RT_FAILURE(rc))
2189 return rc;
2190 }
2191 return rc;
2192}
2193
2194/**
2195 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
2196 */
2197static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, const char *pszIID)
2198{
2199 ACPIState *pThis = RT_FROM_MEMBER(pInterface, ACPIState, IBase);
2200 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
2201 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIACPIPORT, &pThis->IACPIPort);
2202 return NULL;
2203}
2204
2205/**
2206 * Create the ACPI tables.
2207 */
2208static int acpiPlantTables(ACPIState *s)
2209{
2210 int rc;
2211 RTGCPHYS32 GCPhysCur, GCPhysRsdt, GCPhysXsdt, GCPhysFadtAcpi1, GCPhysFadtAcpi2, GCPhysFacs, GCPhysDsdt;
2212 RTGCPHYS32 GCPhysHpet = 0, GCPhysApic = 0, GCPhysSsdt = 0, GCPhysMcfg = 0;
2213 uint32_t addend = 0;
2214 RTGCPHYS32 aGCPhysRsdt[8];
2215 RTGCPHYS32 aGCPhysXsdt[8];
2216 uint32_t cAddr, iMadt = 0, iHpet = 0, iSsdt = 0, iMcfg = 0;
2217 size_t cbRsdt = sizeof(ACPITBLHEADER);
2218 size_t cbXsdt = sizeof(ACPITBLHEADER);
2219
2220 cAddr = 1; /* FADT */
2221 if (s->u8UseIOApic)
2222 iMadt = cAddr++; /* MADT */
2223
2224 if (s->fUseHpet)
2225 iHpet = cAddr++; /* HPET */
2226
2227 if (s->fUseMcfg)
2228 iMcfg = cAddr++; /* MCFG */
2229
2230 iSsdt = cAddr++; /* SSDT */
2231
2232 Assert(cAddr < RT_ELEMENTS(aGCPhysRsdt));
2233 Assert(cAddr < RT_ELEMENTS(aGCPhysXsdt));
2234
2235 cbRsdt += cAddr*sizeof(uint32_t); /* each entry: 32 bits phys. address. */
2236 cbXsdt += cAddr*sizeof(uint64_t); /* each entry: 64 bits phys. address. */
2237
2238 rc = CFGMR3QueryU64(s->pDevIns->pCfg, "RamSize", &s->u64RamSize);
2239 if (RT_FAILURE(rc))
2240 return PDMDEV_SET_ERROR(s->pDevIns, rc,
2241 N_("Configuration error: Querying \"RamSize\" as integer failed"));
2242
2243 uint32_t cbRamHole;
2244 rc = CFGMR3QueryU32Def(s->pDevIns->pCfg, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
2245 if (RT_FAILURE(rc))
2246 return PDMDEV_SET_ERROR(s->pDevIns, rc,
2247 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
2248
2249 /*
2250 * Calculate the sizes for the high and low regions.
2251 */
2252 const uint64_t offRamHole = _4G - cbRamHole;
2253 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
2254 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
2255 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
2256 {
2257 /* Note: This is also enforced by DevPcBios.cpp. */
2258 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
2259 cbRamLow = UINT32_C(0xffe00000);
2260 }
2261 s->cbRamLow = (uint32_t)cbRamLow;
2262
2263 GCPhysCur = 0;
2264 GCPhysRsdt = GCPhysCur;
2265
2266 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbRsdt, 16);
2267 GCPhysXsdt = GCPhysCur;
2268
2269 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbXsdt, 16);
2270 GCPhysFadtAcpi1 = GCPhysCur;
2271
2272 GCPhysCur = RT_ALIGN_32(GCPhysCur + ACPITBLFADT_VERSION1_SIZE, 16);
2273 GCPhysFadtAcpi2 = GCPhysCur;
2274
2275 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFADT), 64);
2276 GCPhysFacs = GCPhysCur;
2277
2278 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLFACS), 16);
2279 if (s->u8UseIOApic)
2280 {
2281 GCPhysApic = GCPhysCur;
2282 GCPhysCur = RT_ALIGN_32(GCPhysCur + AcpiTableMADT::sizeFor(s, NUMBER_OF_IRQ_SOURCE_OVERRIDES), 16);
2283 }
2284 if (s->fUseHpet)
2285 {
2286 GCPhysHpet = GCPhysCur;
2287 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLHPET), 16);
2288 }
2289 if (s->fUseMcfg)
2290 {
2291 GCPhysMcfg = GCPhysCur;
2292 /* Assume one entry */
2293 GCPhysCur = RT_ALIGN_32(GCPhysCur + sizeof(ACPITBLMCFG) + sizeof(ACPITBLMCFGENTRY), 16);
2294 }
2295
2296 void* pSsdtCode = NULL;
2297 size_t cbSsdtSize = 0;
2298 rc = acpiPrepareSsdt(s->pDevIns, &pSsdtCode, &cbSsdtSize);
2299 if (RT_FAILURE(rc))
2300 return rc;
2301
2302 GCPhysSsdt = GCPhysCur;
2303 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbSsdtSize, 16);
2304
2305 GCPhysDsdt = GCPhysCur;
2306
2307 void* pDsdtCode = NULL;
2308 size_t cbDsdtSize = 0;
2309 rc = acpiPrepareDsdt(s->pDevIns, &pDsdtCode, &cbDsdtSize);
2310 if (RT_FAILURE(rc))
2311 return rc;
2312
2313 GCPhysCur = RT_ALIGN_32(GCPhysCur + cbDsdtSize, 16);
2314
2315 if (GCPhysCur > 0x10000)
2316 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
2317 N_("Error: ACPI tables bigger than 64KB"));
2318
2319 Log(("RSDP 0x%08X\n", find_rsdp_space()));
2320 addend = s->cbRamLow - 0x10000;
2321 Log(("RSDT 0x%08X XSDT 0x%08X\n", GCPhysRsdt + addend, GCPhysXsdt + addend));
2322 Log(("FACS 0x%08X FADT (1.0) 0x%08X, FADT (2+) 0x%08X\n", GCPhysFacs + addend, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend));
2323 Log(("DSDT 0x%08X", GCPhysDsdt + addend));
2324 if (s->u8UseIOApic)
2325 Log((" MADT 0x%08X", GCPhysApic + addend));
2326 if (s->fUseHpet)
2327 Log((" HPET 0x%08X", GCPhysHpet + addend));
2328 if (s->fUseMcfg)
2329 Log((" MCFG 0x%08X", GCPhysMcfg + addend));
2330 Log((" SSDT 0x%08X", GCPhysSsdt + addend));
2331 Log(("\n"));
2332
2333 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, GCPhysRsdt + addend, GCPhysXsdt + addend);
2334 acpiSetupDSDT(s, GCPhysDsdt + addend, pDsdtCode, cbDsdtSize);
2335 acpiCleanupDsdt(s->pDevIns, pDsdtCode);
2336 acpiSetupFACS(s, GCPhysFacs + addend);
2337 acpiSetupFADT(s, GCPhysFadtAcpi1 + addend, GCPhysFadtAcpi2 + addend, GCPhysFacs + addend, GCPhysDsdt + addend);
2338
2339 aGCPhysRsdt[0] = GCPhysFadtAcpi1 + addend;
2340 aGCPhysXsdt[0] = GCPhysFadtAcpi2 + addend;
2341 if (s->u8UseIOApic)
2342 {
2343 acpiSetupMADT(s, GCPhysApic + addend);
2344 aGCPhysRsdt[iMadt] = GCPhysApic + addend;
2345 aGCPhysXsdt[iMadt] = GCPhysApic + addend;
2346 }
2347 if (s->fUseHpet)
2348 {
2349 acpiSetupHPET(s, GCPhysHpet + addend);
2350 aGCPhysRsdt[iHpet] = GCPhysHpet + addend;
2351 aGCPhysXsdt[iHpet] = GCPhysHpet + addend;
2352 }
2353 if (s->fUseMcfg)
2354 {
2355 acpiSetupMCFG(s, GCPhysMcfg + addend);
2356 aGCPhysRsdt[iMcfg] = GCPhysMcfg + addend;
2357 aGCPhysXsdt[iMcfg] = GCPhysMcfg + addend;
2358 }
2359
2360 acpiSetupSSDT(s, GCPhysSsdt + addend, pSsdtCode, cbSsdtSize);
2361 acpiCleanupSsdt(s->pDevIns, pSsdtCode);
2362 aGCPhysRsdt[iSsdt] = GCPhysSsdt + addend;
2363 aGCPhysXsdt[iSsdt] = GCPhysSsdt + addend;
2364
2365 rc = acpiSetupRSDT(s, GCPhysRsdt + addend, cAddr, aGCPhysRsdt);
2366 if (RT_FAILURE(rc))
2367 return rc;
2368 return acpiSetupXSDT(s, GCPhysXsdt + addend, cAddr, aGCPhysXsdt);
2369}
2370
2371static int acpiUpdatePmHandlers(ACPIState *pThis, RTIOPORT uNewBase)
2372{
2373 Log(("acpi: rebasing PM 0x%x -> 0x%x\n", pThis->uPmIoPortBase, uNewBase));
2374 if (uNewBase != pThis->uPmIoPortBase)
2375 {
2376 int rc;
2377
2378 rc = acpiUnregisterPmHandlers(pThis);
2379 if (RT_FAILURE(rc))
2380 return rc;
2381
2382 pThis->uPmIoPortBase = uNewBase;
2383
2384 rc = acpiRegisterPmHandlers(pThis);
2385 if (RT_FAILURE(rc))
2386 return rc;
2387
2388 /* We have to update FADT table acccording to the new base */
2389 rc = acpiPlantTables(pThis);
2390 AssertRC(rc);
2391 if (RT_FAILURE(rc))
2392 return rc;
2393 }
2394
2395 return VINF_SUCCESS;
2396}
2397
2398static uint32_t acpiPciConfigRead(PPCIDEVICE pPciDev, uint32_t Address, unsigned cb)
2399{
2400 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2401 ACPIState* pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2402
2403 Log2(("acpi: PCI config read: 0x%x (%d)\n", Address, cb));
2404
2405 return pThis->pfnAcpiPciConfigRead(pPciDev, Address, cb);
2406}
2407
2408static void acpiPciConfigWrite(PPCIDEVICE pPciDev, uint32_t Address, uint32_t u32Value, unsigned cb)
2409{
2410 PPDMDEVINS pDevIns = pPciDev->pDevIns;
2411 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2412
2413 Log2(("acpi: PCI config write: 0x%x -> 0x%x (%d)\n", u32Value, Address, cb));
2414
2415
2416 if (Address == VBOX_PCI_INTERRUPT_LINE)
2417 {
2418 Log(("acpi: ignore interrupt line settings: %d, we'll use hardcoded value %d\n", u32Value, SCI_INT));
2419 u32Value = SCI_INT;
2420 }
2421
2422 pThis->pfnAcpiPciConfigWrite(pPciDev, Address, u32Value, cb);
2423
2424 /* PMREGMISC written */
2425 if (Address == 0x80)
2426 {
2427 /* Check Power Management IO Space Enable (PMIOSE) bit */
2428 if (pPciDev->config[0x80] & 0x1)
2429 {
2430 int rc;
2431
2432 RTIOPORT uNewBase = RTIOPORT(PCIDevGetDWord(pPciDev, 0x40));
2433 uNewBase &= 0xffc0;
2434
2435 rc = acpiUpdatePmHandlers(pThis, uNewBase);
2436 AssertRC(rc);
2437 }
2438 }
2439}
2440
2441/**
2442 * Attach a new CPU.
2443 *
2444 * @returns VBox status code.
2445 * @param pDevIns The device instance.
2446 * @param iLUN The logical unit which is being attached.
2447 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2448 *
2449 * @remarks This code path is not used during construction.
2450 */
2451static DECLCALLBACK(int) acpiAttach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2452{
2453 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2454
2455 LogFlow(("acpiAttach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2456
2457 AssertMsgReturn(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2458 ("Hot-plug flag is not set\n"),
2459 VERR_NOT_SUPPORTED);
2460 AssertReturn(iLUN < VMM_MAX_CPU_COUNT, VERR_PDM_NO_SUCH_LUN);
2461
2462 /* Check if it was already attached */
2463 if (VMCPUSET_IS_PRESENT(&s->CpuSetAttached, iLUN))
2464 return VINF_SUCCESS;
2465
2466 PPDMIBASE IBaseTmp;
2467 int rc = PDMDevHlpDriverAttach(pDevIns, iLUN, &s->IBase, &IBaseTmp, "ACPI CPU");
2468
2469 if (RT_SUCCESS(rc))
2470 {
2471 /* Enable the CPU */
2472 VMCPUSET_ADD(&s->CpuSetAttached, iLUN);
2473
2474 /*
2475 * Lock the CPU because we don't know if the guest will use it or not.
2476 * Prevents ejection while the CPU is still used
2477 */
2478 VMCPUSET_ADD(&s->CpuSetLocked, iLUN);
2479 s->u32CpuEventType = CPU_EVENT_TYPE_ADD;
2480 s->u32CpuEvent = iLUN;
2481 /* Notify the guest */
2482 update_gpe0(s, s->gpe0_sts | 0x2, s->gpe0_en);
2483 }
2484 return rc;
2485}
2486
2487/**
2488 * Detach notification.
2489 *
2490 * @param pDevIns The device instance.
2491 * @param iLUN The logical unit which is being detached.
2492 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
2493 */
2494static DECLCALLBACK(void) acpiDetach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
2495{
2496 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2497
2498 LogFlow(("acpiDetach: pDevIns=%p iLUN=%u fFlags=%#x\n", pDevIns, iLUN, fFlags));
2499
2500 AssertMsgReturnVoid(!(fFlags & PDM_TACH_FLAGS_NOT_HOT_PLUG),
2501 ("Hot-plug flag is not set\n"));
2502
2503 /* Check if it was already detached */
2504 if (VMCPUSET_IS_PRESENT(&s->CpuSetAttached, iLUN))
2505 {
2506 AssertMsgReturnVoid(!(VMCPUSET_IS_PRESENT(&s->CpuSetLocked, iLUN)), ("CPU is still locked by the guest\n"));
2507
2508 /* Disable the CPU */
2509 VMCPUSET_DEL(&s->CpuSetAttached, iLUN);
2510 s->u32CpuEventType = CPU_EVENT_TYPE_REMOVE;
2511 s->u32CpuEvent = iLUN;
2512 /* Notify the guest */
2513 update_gpe0(s, s->gpe0_sts | 0x2, s->gpe0_en);
2514 }
2515}
2516
2517/**
2518 * @interface_method_impl{PDMDEVREG,pfnResume}
2519 */
2520static DECLCALLBACK(void) acpiResume(PPDMDEVINS pDevIns)
2521{
2522 ACPIState *pThis = PDMINS_2_DATA(pDevIns, ACPIState *);
2523 if (pThis->fSetWakeupOnResume)
2524 {
2525 Log(("acpiResume: setting WAK_STS\n"));
2526 pThis->fSetWakeupOnResume = false;
2527 pThis->pm1a_sts |= WAK_STS;
2528 }
2529}
2530
2531/**
2532 * @interface_method_impl{PDMDEVREG,pfnReset}
2533 */
2534static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2535{
2536 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2537
2538 s->pm1a_en = 0;
2539 s->pm1a_sts = 0;
2540 s->pm1a_ctl = 0;
2541 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2542 acpiPMTimerReset(s);
2543 s->uBatteryIndex = 0;
2544 s->uSystemInfoIndex = 0;
2545 s->gpe0_en = 0;
2546 s->gpe0_sts = 0;
2547 s->uSleepState = 0;
2548
2549 /** @todo Should we really reset PM base? */
2550 acpiUpdatePmHandlers(s, PM_PORT_BASE);
2551
2552 acpiPlantTables(s);
2553}
2554
2555/**
2556 * @interface_method_impl{PDMDEVREG,pfnRelocate}
2557 */
2558static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2559{
2560 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2561 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2562}
2563
2564/**
2565 * @interface_method_impl{PDMDEVREG,pfnConstruct}
2566 */
2567static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2568{
2569 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2570 PCIDevice *dev = &s->dev;
2571 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2572
2573 /* Validate and read the configuration. */
2574 if (!CFGMR3AreValuesValid(pCfg,
2575 "RamSize\0"
2576 "RamHoleSize\0"
2577 "IOAPIC\0"
2578 "NumCPUs\0"
2579 "GCEnabled\0"
2580 "R0Enabled\0"
2581 "HpetEnabled\0"
2582 "McfgEnabled\0"
2583 "McfgBase\0"
2584 "McfgLength\0"
2585 "SmcEnabled\0"
2586 "FdcEnabled\0"
2587 "ShowRtc\0"
2588 "ShowCpu\0"
2589 "NicPciAddress\0"
2590 "AudioPciAddress\0"
2591 "IocPciAddress\0"
2592 "HostBusPciAddress\0"
2593 "EnableSuspendToDisk\0"
2594 "PowerS1Enabled\0"
2595 "PowerS4Enabled\0"
2596 "CpuHotPlug\0"
2597 "AmlFilePath\0"
2598 ))
2599 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
2600 N_("Configuration error: Invalid config key for ACPI device"));
2601
2602 s->pDevIns = pDevIns;
2603
2604 /* query whether we are supposed to present an IOAPIC */
2605 int rc = CFGMR3QueryU8Def(pCfg, "IOAPIC", &s->u8UseIOApic, 1);
2606 if (RT_FAILURE(rc))
2607 return PDMDEV_SET_ERROR(pDevIns, rc,
2608 N_("Configuration error: Failed to read \"IOAPIC\""));
2609
2610 rc = CFGMR3QueryU16Def(pCfg, "NumCPUs", &s->cCpus, 1);
2611 if (RT_FAILURE(rc))
2612 return PDMDEV_SET_ERROR(pDevIns, rc,
2613 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
2614
2615 /* query whether we are supposed to present an FDC controller */
2616 rc = CFGMR3QueryBoolDef(pCfg, "FdcEnabled", &s->fUseFdc, true);
2617 if (RT_FAILURE(rc))
2618 return PDMDEV_SET_ERROR(pDevIns, rc,
2619 N_("Configuration error: Failed to read \"FdcEnabled\""));
2620
2621 /* query whether we are supposed to present HPET */
2622 rc = CFGMR3QueryBoolDef(pCfg, "HpetEnabled", &s->fUseHpet, false);
2623 if (RT_FAILURE(rc))
2624 return PDMDEV_SET_ERROR(pDevIns, rc,
2625 N_("Configuration error: Failed to read \"HpetEnabled\""));
2626 /* query MCFG configuration */
2627 rc = CFGMR3QueryU64Def(pCfg, "McfgBase", &s->u64PciConfigMMioAddress, 0);
2628 if (RT_FAILURE(rc))
2629 return PDMDEV_SET_ERROR(pDevIns, rc,
2630 N_("Configuration error: Failed to read \"McfgBase\""));
2631 rc = CFGMR3QueryU64Def(pCfg, "McfgLength", &s->u64PciConfigMMioLength, 0);
2632 if (RT_FAILURE(rc))
2633 return PDMDEV_SET_ERROR(pDevIns, rc,
2634 N_("Configuration error: Failed to read \"McfgLength\""));
2635 s->fUseMcfg = (s->u64PciConfigMMioAddress != 0) && (s->u64PciConfigMMioLength != 0);
2636
2637 /* query whether we are supposed to present SMC */
2638 rc = CFGMR3QueryBoolDef(pCfg, "SmcEnabled", &s->fUseSmc, false);
2639 if (RT_FAILURE(rc))
2640 return PDMDEV_SET_ERROR(pDevIns, rc,
2641 N_("Configuration error: Failed to read \"SmcEnabled\""));
2642
2643 /* query whether we are supposed to present RTC object */
2644 rc = CFGMR3QueryBoolDef(pCfg, "ShowRtc", &s->fShowRtc, false);
2645 if (RT_FAILURE(rc))
2646 return PDMDEV_SET_ERROR(pDevIns, rc,
2647 N_("Configuration error: Failed to read \"ShowRtc\""));
2648
2649 /* query whether we are supposed to present CPU objects */
2650 rc = CFGMR3QueryBoolDef(pCfg, "ShowCpu", &s->fShowCpu, false);
2651 if (RT_FAILURE(rc))
2652 return PDMDEV_SET_ERROR(pDevIns, rc,
2653 N_("Configuration error: Failed to read \"ShowCpu\""));
2654
2655 /* query primary NIC PCI address */
2656 rc = CFGMR3QueryU32Def(pCfg, "NicPciAddress", &s->u32NicPciAddress, 0);
2657 if (RT_FAILURE(rc))
2658 return PDMDEV_SET_ERROR(pDevIns, rc,
2659 N_("Configuration error: Failed to read \"NicPciAddress\""));
2660
2661 /* query primary NIC PCI address */
2662 rc = CFGMR3QueryU32Def(pCfg, "AudioPciAddress", &s->u32AudioPciAddress, 0);
2663 if (RT_FAILURE(rc))
2664 return PDMDEV_SET_ERROR(pDevIns, rc,
2665 N_("Configuration error: Failed to read \"AudioPciAddress\""));
2666
2667 /* query IO controller (southbridge) PCI address */
2668 rc = CFGMR3QueryU32Def(pCfg, "IocPciAddress", &s->u32IocPciAddress, 0);
2669 if (RT_FAILURE(rc))
2670 return PDMDEV_SET_ERROR(pDevIns, rc,
2671 N_("Configuration error: Failed to read \"IocPciAddress\""));
2672
2673 /* query host bus controller PCI address */
2674 rc = CFGMR3QueryU32Def(pCfg, "HostBusPciAddress", &s->u32HbcPciAddress, 0);
2675 if (RT_FAILURE(rc))
2676 return PDMDEV_SET_ERROR(pDevIns, rc,
2677 N_("Configuration error: Failed to read \"HostBusPciAddress\""));
2678
2679 /* query whether S1 power state should be exposed */
2680 rc = CFGMR3QueryBoolDef(pCfg, "PowerS1Enabled", &s->fS1Enabled, true);
2681 if (RT_FAILURE(rc))
2682 return PDMDEV_SET_ERROR(pDevIns, rc,
2683 N_("Configuration error: Failed to read \"PowerS1Enabled\""));
2684
2685 /* query whether S4 power state should be exposed */
2686 rc = CFGMR3QueryBoolDef(pCfg, "PowerS4Enabled", &s->fS4Enabled, true);
2687 if (RT_FAILURE(rc))
2688 return PDMDEV_SET_ERROR(pDevIns, rc,
2689 N_("Configuration error: Failed to read \"PowerS1Enabled\""));
2690
2691 /* query whether S1 power state should save the VM state */
2692 rc = CFGMR3QueryBoolDef(pCfg, "EnableSuspendToDisk", &s->fSuspendToSavedState, false);
2693 if (RT_FAILURE(rc))
2694 return PDMDEV_SET_ERROR(pDevIns, rc,
2695 N_("Configuration error: Failed to read \"EnableSuspendToDisk\""));
2696
2697 /* query whether we are allow CPU hot plugging */
2698 rc = CFGMR3QueryBoolDef(pCfg, "CpuHotPlug", &s->fCpuHotPlug, false);
2699 if (RT_FAILURE(rc))
2700 return PDMDEV_SET_ERROR(pDevIns, rc,
2701 N_("Configuration error: Failed to read \"CpuHotPlug\""));
2702
2703 rc = CFGMR3QueryBool(pCfg, "GCEnabled", &s->fGCEnabled);
2704 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2705 s->fGCEnabled = true;
2706 else if (RT_FAILURE(rc))
2707 return PDMDEV_SET_ERROR(pDevIns, rc,
2708 N_("Configuration error: Failed to read \"GCEnabled\""));
2709
2710 rc = CFGMR3QueryBool(pCfg, "R0Enabled", &s->fR0Enabled);
2711 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
2712 s->fR0Enabled = true;
2713 else if (RT_FAILURE(rc))
2714 return PDMDEV_SET_ERROR(pDevIns, rc,
2715 N_("configuration error: failed to read R0Enabled as boolean"));
2716
2717 /*
2718 * Interfaces
2719 */
2720 /* IBase */
2721 s->IBase.pfnQueryInterface = acpiQueryInterface;
2722 /* IACPIPort */
2723 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
2724 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
2725 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
2726 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
2727 s->IACPIPort.pfnGetCpuStatus = acpiGetCpuStatus;
2728
2729 VMCPUSET_EMPTY(&s->CpuSetAttached);
2730 VMCPUSET_EMPTY(&s->CpuSetLocked);
2731 s->idCpuLockCheck = UINT32_C(0xffffffff);
2732 s->u32CpuEventType = 0;
2733 s->u32CpuEvent = UINT32_C(0xffffffff);
2734
2735 /* The first CPU can't be attached/detached */
2736 VMCPUSET_ADD(&s->CpuSetAttached, 0);
2737 VMCPUSET_ADD(&s->CpuSetLocked, 0);
2738
2739 /* Try to attach the other CPUs */
2740 for (unsigned i = 1; i < s->cCpus; i++)
2741 {
2742 if (s->fCpuHotPlug)
2743 {
2744 PPDMIBASE IBaseTmp;
2745 rc = PDMDevHlpDriverAttach(pDevIns, i, &s->IBase, &IBaseTmp, "ACPI CPU");
2746
2747 if (RT_SUCCESS(rc))
2748 {
2749 VMCPUSET_ADD(&s->CpuSetAttached, i);
2750 VMCPUSET_ADD(&s->CpuSetLocked, i);
2751 Log(("acpi: Attached CPU %u\n", i));
2752 }
2753 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2754 Log(("acpi: CPU %u not attached yet\n", i));
2755 else
2756 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach CPU object\n"));
2757 }
2758 else
2759 {
2760 /* CPU is always attached if hot-plug is not enabled. */
2761 VMCPUSET_ADD(&s->CpuSetAttached, i);
2762 VMCPUSET_ADD(&s->CpuSetLocked, i);
2763 }
2764 }
2765
2766
2767 /* Set default port base */
2768 s->uPmIoPortBase = PM_PORT_BASE;
2769
2770 /*
2771 * FDC and SMC try to use the same non-shareable interrupt (6),
2772 * enable only one device.
2773 */
2774 if (s->fUseSmc)
2775 s->fUseFdc = false;
2776
2777 /* */
2778 RTGCPHYS32 GCPhysRsdp = find_rsdp_space();
2779 if (!GCPhysRsdp)
2780 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
2781 N_("Can not find space for RSDP. ACPI is disabled"));
2782
2783 rc = acpiPlantTables(s);
2784 if (RT_FAILURE(rc))
2785 return rc;
2786
2787 rc = PDMDevHlpROMRegister(pDevIns, GCPhysRsdp, 0x1000, s->au8RSDPPage, 0x1000,
2788 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
2789 if (RT_FAILURE(rc))
2790 return rc;
2791
2792 rc = acpiRegisterPmHandlers(s);
2793 if (RT_FAILURE(rc))
2794 return rc;
2795
2796#define R(addr, cnt, writer, reader, description) \
2797 do { \
2798 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
2799 NULL, NULL, description); \
2800 if (RT_FAILURE(rc)) \
2801 return rc; \
2802 } while (0)
2803 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
2804#ifdef DEBUG_ACPI
2805 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
2806 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
2807#endif
2808 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
2809 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
2810 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
2811 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
2812 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
2813#undef R
2814
2815 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, dev,
2816 TMTIMER_FLAGS_DEFAULT_CRIT_SECT, "ACPI Timer", &s->tsR3);
2817 if (RT_FAILURE(rc))
2818 {
2819 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
2820 return rc;
2821 }
2822
2823 s->tsR0 = TMTimerR0Ptr(s->tsR3);
2824 s->tsRC = TMTimerRCPtr(s->tsR3);
2825 s->pm_timer_initial = TMTimerGet(s->tsR3);
2826 acpiPMTimerReset(s);
2827
2828 PCIDevSetVendorId(dev, 0x8086); /* Intel */
2829 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
2830
2831 /* See p. 50 of PIIX4 manual */
2832 PCIDevSetCommand(dev, 0x01);
2833 PCIDevSetStatus(dev, 0x0280);
2834
2835 PCIDevSetRevisionId(dev, 0x08);
2836
2837 PCIDevSetClassProg(dev, 0x00);
2838 PCIDevSetClassSub(dev, 0x80);
2839 PCIDevSetClassBase(dev, 0x06);
2840
2841 PCIDevSetHeaderType(dev, 0x80);
2842
2843 PCIDevSetBIST(dev, 0x00);
2844
2845 PCIDevSetInterruptLine(dev, SCI_INT);
2846 PCIDevSetInterruptPin (dev, 0x01);
2847
2848 dev->config[0x40] = 0x01; /* PM base address, this bit marks it as IO range, not PA */
2849
2850#if 0
2851 int smb_io_base = 0xb100;
2852 dev->config[0x90] = smb_io_base | 1; /* SMBus base address */
2853 dev->config[0x90] = smb_io_base >> 8;
2854#endif
2855
2856 rc = PDMDevHlpPCIRegister(pDevIns, dev);
2857 if (RT_FAILURE(rc))
2858 return rc;
2859
2860 PDMDevHlpPCISetConfigCallbacks(pDevIns, dev,
2861 acpiPciConfigRead, &s->pfnAcpiPciConfigRead,
2862 acpiPciConfigWrite, &s->pfnAcpiPciConfigWrite);
2863
2864 rc = PDMDevHlpSSMRegister(pDevIns, 6, sizeof(*s), acpiSaveState, acpiLoadState);
2865 if (RT_FAILURE(rc))
2866 return rc;
2867
2868 /*
2869 * Get the corresponding connector interface
2870 */
2871 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2872 if (RT_SUCCESS(rc))
2873 {
2874 s->pDrv = PDMIBASE_QUERY_INTERFACE(s->pDrvBase, PDMIACPICONNECTOR);
2875 if (!s->pDrv)
2876 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2877 N_("LUN #0 doesn't have an ACPI connector interface"));
2878 }
2879 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2880 {
2881 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2882 pDevIns->pReg->szName, pDevIns->iInstance));
2883 rc = VINF_SUCCESS;
2884 }
2885 else
2886 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2887
2888 return rc;
2889}
2890
2891/**
2892 * The device registration structure.
2893 */
2894const PDMDEVREG g_DeviceACPI =
2895{
2896 /* u32Version */
2897 PDM_DEVREG_VERSION,
2898 /* szName */
2899 "acpi",
2900 /* szRCMod */
2901 "VBoxDDGC.gc",
2902 /* szR0Mod */
2903 "VBoxDDR0.r0",
2904 /* pszDescription */
2905 "Advanced Configuration and Power Interface",
2906 /* fFlags */
2907 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2908 /* fClass */
2909 PDM_DEVREG_CLASS_ACPI,
2910 /* cMaxInstances */
2911 ~0,
2912 /* cbInstance */
2913 sizeof(ACPIState),
2914 /* pfnConstruct */
2915 acpiConstruct,
2916 /* pfnDestruct */
2917 NULL,
2918 /* pfnRelocate */
2919 acpiRelocate,
2920 /* pfnIOCtl */
2921 NULL,
2922 /* pfnPowerOn */
2923 NULL,
2924 /* pfnReset */
2925 acpiReset,
2926 /* pfnSuspend */
2927 NULL,
2928 /* pfnResume */
2929 acpiResume,
2930 /* pfnAttach */
2931 acpiAttach,
2932 /* pfnDetach */
2933 acpiDetach,
2934 /* pfnQueryInterface. */
2935 NULL,
2936 /* pfnInitComplete */
2937 NULL,
2938 /* pfnPowerOff */
2939 NULL,
2940 /* pfnSoftReset */
2941 NULL,
2942 /* u32VersionEnd */
2943 PDM_DEVREG_VERSION
2944};
2945
2946#endif /* IN_RING3 */
2947#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette