VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 4612

Last change on this file since 4612 was 4382, checked in by vboxsync, 17 years ago

Extended the ROMRegister DevHlp interface to include a fShadow flag. Added a interface intented for write proecting shadow ROM after the POST is over.
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File size: 60.7 KB
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1/* $Id: DevACPI.cpp 4382 2007-08-27 11:28:55Z vboxsync $ */
2/** @file
3 * Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License as published by the Free Software Foundation,
13 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14 * distribution. VirtualBox OSE is distributed in the hope that it will
15 * be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#define LOG_GROUP LOG_GROUP_DEV_ACPI
19
20#include <VBox/pdmdev.h>
21#include <VBox/log.h>
22#include <iprt/assert.h>
23#include <iprt/asm.h>
24#ifdef IN_RING3
25#include <iprt/alloc.h>
26#include <iprt/string.h>
27#endif /* IN_RING3 */
28
29#include "Builtins.h"
30
31#ifdef LOG_ENABLED
32#define DEBUG_ACPI
33#endif
34
35/* the compiled DSL */
36#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
37#include <vboxaml.hex>
38#endif /* !IN_RING3 */
39
40#define IO_READ_PROTO(name) \
41 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
42 RTIOPORT Port, uint32_t *pu32, unsigned cb)
43
44#define IO_WRITE_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t u32, unsigned cb)
47
48#define DEBUG_HEX 0x3000
49#define DEBUG_CHR 0x3001
50
51#define PM_TMR_FREQ 3579545
52#define PM1a_EVT_BLK 0x00004000
53#define PM1b_EVT_BLK 0x00000000 /**< not supported */
54#define PM1a_CTL_BLK 0x00004004
55#define PM1b_CTL_BLK 0x00000000 /**< not supported */
56#define PM2_CTL_BLK 0x00000000 /**< not supported */
57#define PM_TMR_BLK 0x00004008
58#define GPE0_BLK 0x00004020
59#define GPE1_BLK 0x00000000 /**< not supported */
60#define BAT_INDEX 0x00004040
61#define BAT_DATA 0x00004044
62#define SYSI_INDEX 0x00004048
63#define SYSI_DATA 0x0000404c
64#define ACPI_RESET_BLK 0x00004050
65
66/* PM1x status register bits */
67#define TMR_STS BIT(0)
68#define RSR1_STS (BIT(1) | BIT(2) | BIT(3))
69#define BM_STS BIT(4)
70#define GBL_STS BIT(5)
71#define RSR2_STS (BIT(6) | BIT(7))
72#define PWRBTN_STS BIT(8)
73#define SLPBTN_STS BIT(9)
74#define RTC_STS BIT(10)
75#define IGN_STS BIT(11)
76#define RSR3_STS (BIT(12) | BIT(13) | BIT(14))
77#define WAK_STS BIT(15)
78#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
79
80/* PM1x enable register bits */
81#define TMR_EN BIT(0)
82#define RSR1_EN (BIT(1) | BIT(2) | BIT(3) | BIT(4))
83#define GBL_EN BIT(5)
84#define RSR2_EN (BIT(6) | BIT(7))
85#define PWRBTN_EN BIT(8)
86#define SLPBTN_EN BIT(9)
87#define RTC_EN BIT(10)
88#define RSR3_EN (BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15))
89#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
90#define IGN_EN 0
91
92/* PM1x control register bits */
93#define SCI_EN BIT(0)
94#define BM_RLD BIT(1)
95#define GBL_RLS BIT(2)
96#define RSR1_CNT (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8))
97#define IGN_CNT BIT(9)
98#define SLP_TYPx_SHIFT 10
99#define SLP_TYPx_MASK 7
100#define SLP_EN BIT(13)
101#define RSR2_CNT (BIT(14) | BIT(15))
102#define RSR_CNT (RSR1_CNT | RSR2_CNT)
103
104#define GPE0_BATTERY_INFO_CHANGED BIT (0)
105
106enum
107{
108 BAT_STATUS_STATE = 0x00, /**< BST battery state */
109 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
110 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
111 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
112 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
113 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
114 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
115 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
116 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
117 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
118 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
119 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
120 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
121 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
122 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
123 BAT_INDEX_LAST
124};
125
126enum
127{
128 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
129 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
130 SYSTEM_INFO_INDEX_LAST = 2,
131 SYSTEM_INFO_INDEX_INVALID = 0x80,
132 SYSTEM_INFO_INDEX_VALID = 0x200
133};
134
135#define AC_OFFLINE 0
136#define AC_ONLINE 1
137
138#define BAT_TECH_PRIMARY 1
139#define BAT_TECH_SECONDARY 2
140
141#define BAT_STATUS_DISCHARGING_MASK BIT (0)
142#define BAT_STATUS_CHARGING_MASK BIT (1)
143#define BAT_STATUS_CRITICAL_MASK BIT (2)
144
145#define STA_DEVICE_PRESENT_MASK BIT (0)
146#define STA_DEVICE_ENABLED_MASK BIT (1)
147#define STA_DEVICE_SHOW_IN_UI_MASK BIT (2)
148#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK BIT (3)
149#define STA_BATTERY_PRESENT_MASK BIT (4)
150
151struct ACPIState
152{
153 PCIDevice dev;
154 uint16_t pm1a_en;
155 uint16_t pm1a_sts;
156 uint16_t pm1a_ctl;
157 uint16_t Alignment0;
158 int64_t pm_timer_initial;
159 PTMTIMERHC tsHC;
160 PTMTIMERGC tsGC;
161
162 uint32_t gpe0_en;
163 uint32_t gpe0_sts;
164
165 unsigned int uBatteryIndex;
166 uint32_t au8BatteryInfo[13];
167
168 unsigned int uSystemInfoIndex;
169 uint64_t u64RamSize;
170
171 /** Current ACPI S* state. We support S0 and S5 */
172 uint32_t uSleepState;
173 uint8_t au8RSDPPage[0x1000];
174 /** This is a workaround for incorrect index field handling by Intels ACPICA.
175 * The system info _INI method writes to offset 0x200. We either observe a
176 * write request to index 0x80 (in that case we don't change the index) or a
177 * write request to offset 0x200 (in that case we divide the index value by
178 * 4. Note that the _STA method is sometimes called prior to the _INI method
179 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
180 * acpiBatIndexWrite() for handling this. */
181 uint8_t u8IndexShift;
182 uint8_t u8UseIOApic;
183
184 /** ACPI port base interface. */
185 PDMIBASE IBase;
186 /** ACPI port interface. */
187 PDMIACPIPORT IACPIPort;
188 /** Pointer to the device instance. */
189 PPDMDEVINSR3 pDevIns;
190 /** Pointer to the driver base interface */
191 R3PTRTYPE(PPDMIBASE) pDrvBase;
192 /** Pointer to the driver connector interface */
193 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
194};
195
196#pragma pack(1)
197
198/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
199struct ACPIGENADDR
200{
201 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
202 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
203 uint8_t u8RegisterBitOffset; /**< bit offset of register */
204 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
205 uint64_t u64Address; /**< 64-bit address of register */
206};
207AssertCompileSize(ACPIGENADDR, 12);
208
209/** Root System Description Pointer */
210struct ACPITBLRSDP
211{
212 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
213 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
214 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
215 uint8_t u8Revision; /**< revision number, currently 2 */
216#define ACPI_REVISION 2 /**< ACPI 3.0 */
217 uint32_t u32RSDT; /**< phys addr of RSDT */
218 uint32_t u32Length; /**< bytes of this table */
219 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
220 uint8_t u8ExtChecksum; /**< checksum of entire table */
221 uint8_t u8Reserved[3]; /**< reserved */
222};
223AssertCompileSize(ACPITBLRSDP, 36);
224
225/** System Description Table Header */
226struct ACPITBLHEADER
227{
228 uint8_t au8Signature[4]; /**< table identifier */
229 uint32_t u32Length; /**< length of the table including header */
230 uint8_t u8Revision; /**< revision number */
231 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
232 uint8_t au8OemId[6]; /**< OEM-supplied string */
233 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
234 uint32_t u32OemRevision; /**< OEM-supplied revision number */
235 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
236 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
237};
238AssertCompileSize(ACPITBLHEADER, 36);
239
240/** Root System Description Table */
241struct ACPITBLRSDT
242{
243 ACPITBLHEADER header;
244 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
245};
246AssertCompileSize(ACPITBLRSDT, 40);
247
248/** Extended System Description Table */
249struct ACPITBLXSDT
250{
251 ACPITBLHEADER header;
252 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
253};
254AssertCompileSize(ACPITBLXSDT, 44);
255
256/** Fixed ACPI Description Table */
257struct ACPITBLFADT
258{
259 ACPITBLHEADER header;
260 uint32_t u32FACS; /**< phys. address of FACS */
261 uint32_t u32DSDT; /**< phys. address of DSDT */
262 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
263#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
264#define INT_MODEL_MULTIPLE_APIC 2
265 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
266 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
267#define SCI_INT 9
268 uint32_t u32SMICmd; /**< system port address of SMI command port */
269#define SMI_CMD 0x0000442e
270 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
271#define ACPI_ENABLE 0xa1
272 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
273#define ACPI_DISABLE 0xa0
274 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
275 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
276 state control responsibility */
277 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
278 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
279 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
280 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
281 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
282 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
283 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
284 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
285 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
286 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
287 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
288 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
289 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
290#define GPE0_BLK_LEN 2
291 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
292#define GPE1_BLK_LEN 0
293 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
294#define GPE1_BASE 0
295 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
296 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
297#define P_LVL2_LAT 101 /**< C2 state not supported */
298 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
299#define P_LVL3_LAT 1001 /**< C3 state not supported */
300 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
301 lines from any processors memory caches */
302#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
303 uint16_t u16FlushStride; /**< cache line width */
304#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
305 uint8_t u8DutyOffset;
306 uint8_t u8DutyWidth;
307 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
308 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
309 uint8_t u8Century; /**< RTC CMOS RAM index of century */
310 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
311#define IAPC_BOOT_ARCH_LEGACY_DEV BIT(0) /**< legacy devices present such as LPT
312 (COM too?) */
313#define IAPC_BOOT_ARCH_8042 BIT(1) /**< legacy keyboard device present */
314#define IAPC_BOOT_ARCH_NO_VGA BIT(2) /**< VGA not present */
315 uint8_t u8Must0_0; /**< must be 0 */
316 uint32_t u32Flags; /**< fixed feature flags */
317#define FADT_FL_WBINVD BIT(0) /**< emulation of WBINVD available */
318#define FADT_FL_WBINVD_FLUSH BIT(1)
319#define FADT_FL_PROC_C1 BIT(2) /**< 1=C1 supported on all processors */
320#define FADT_FL_P_LVL2_UP BIT(3) /**< 1=C2 works on SMP and UNI systems */
321#define FADT_FL_PWR_BUTTON BIT(4) /**< 1=power button handled as ctrl method dev */
322#define FADT_FL_SLP_BUTTON BIT(5) /**< 1=sleep button handled as ctrl method dev */
323#define FADT_FL_FIX_RTC BIT(6) /**< 0=RTC wake status in fixed register */
324#define FADT_FL_RTC_S4 BIT(7) /**< 1=RTC can wake system from S4 */
325#define FADT_FL_TMR_VAL_EXT BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
326#define FADT_FL_DCK_CAP BIT(9) /**< 0=system cannot support docking */
327#define FADT_FL_RESET_REG_SUP BIT(10) /**< 1=system supports system resets */
328#define FADT_FL_SEALED_CASE BIT(11) /**< 1=case is sealed */
329#define FADT_FL_HEADLESS BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
330#define FADT_FL_CPU_SW_SLP BIT(13)
331#define FADT_FL_PCI_EXT_WAK BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
332#define FADT_FL_USE_PLATFORM_CLOCK BIT(15) /**< 1=system has ACPI PM timer */
333#define FADT_FL_S4_RTC_STS_VALID BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
334#define FADT_FL_REMOVE_POWER_ON_CAPABLE BIT(17) /**< 1=platform can remote power on */
335#define FADT_FL_FORCE_APIC_CLUSTER_MODEL BIT(18)
336#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE BIT(19)
337 ACPIGENADDR ResetReg; /**< ext addr of reset register */
338 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
339#define ACPI_RESET_REG_VAL 0x10
340 uint8_t au8Must0_1[3]; /**< must be 0 */
341 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
342 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
343 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
344 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
345 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
346 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
347 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
348 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
349 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
350 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
351};
352AssertCompileSize(ACPITBLFADT, 244);
353
354/** Firmware ACPI Control Structure */
355struct ACPITBLFACS
356{
357 uint8_t au8Signature[4]; /**< 'FACS' */
358 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
359 uint32_t u32HWSignature; /**< systems HW signature at last boot */
360 uint32_t u32FWVector; /**< address of waking vector */
361 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
362 uint32_t u32Flags; /**< FACS flags */
363 uint64_t u64X_FWVector; /**< 64-bit waking vector */
364 uint8_t u8Version; /**< version of this table */
365 uint8_t au8Reserved[31]; /**< zero */
366};
367AssertCompileSize(ACPITBLFACS, 64);
368
369/** Processor Local APIC Structure */
370struct ACPITBLLAPIC
371{
372 uint8_t u8Type; /**< 0 = LAPIC */
373 uint8_t u8Length; /**< 8 */
374 uint8_t u8ProcId; /**< processor ID */
375 uint8_t u8ApicId; /**< local APIC ID */
376 uint32_t u32Flags; /**< Flags */
377#define LAPIC_ENABLED 0x1
378};
379AssertCompileSize(ACPITBLLAPIC, 8);
380
381/** I/O APIC Structure */
382struct ACPITBLIOAPIC
383{
384 uint8_t u8Type; /**< 1 == I/O APIC */
385 uint8_t u8Length; /**< 12 */
386 uint8_t u8IOApicId; /**< I/O APIC ID */
387 uint8_t u8Reserved; /**< 0 */
388 uint32_t u32Address; /**< phys address to access I/O APIC */
389 uint32_t u32GSIB; /**< global system interrupt number to start */
390};
391AssertCompileSize(ACPITBLIOAPIC, 12);
392
393/** Multiple APIC Description Table */
394struct ACPITBLMADT
395{
396 ACPITBLHEADER header;
397 uint32_t u32LAPIC; /**< local APIC address */
398 uint32_t u32Flags; /**< Flags */
399#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
400 ACPITBLLAPIC LApic;
401 ACPITBLIOAPIC IOApic;
402};
403AssertCompileSize(ACPITBLMADT, 64);
404
405#pragma pack()
406
407
408#ifndef VBOX_DEVICE_STRUCT_TESTCASE
409__BEGIN_DECLS
410IO_READ_PROTO (acpiPMTmrRead);
411#ifdef IN_RING3
412IO_READ_PROTO (acpiPm1aEnRead);
413IO_WRITE_PROTO (acpiPM1aEnWrite);
414IO_READ_PROTO (acpiPm1aStsRead);
415IO_WRITE_PROTO (acpiPM1aStsWrite);
416IO_READ_PROTO (acpiPm1aCtlRead);
417IO_WRITE_PROTO (acpiPM1aCtlWrite);
418IO_WRITE_PROTO (acpiSmiWrite);
419IO_WRITE_PROTO (acpiBatIndexWrite);
420IO_READ_PROTO (acpiBatDataRead);
421IO_READ_PROTO (acpiSysInfoDataRead);
422IO_WRITE_PROTO (acpiSysInfoDataWrite);
423IO_READ_PROTO (acpiGpe0EnRead);
424IO_WRITE_PROTO (acpiGpe0EnWrite);
425IO_READ_PROTO (acpiGpe0StsRead);
426IO_WRITE_PROTO (acpiGpe0StsWrite);
427IO_WRITE_PROTO (acpiResetWrite);
428# ifdef DEBUG_ACPI
429IO_WRITE_PROTO (acpiDhexWrite);
430IO_WRITE_PROTO (acpiDchrWrite);
431# endif
432#endif
433__END_DECLS
434
435#ifdef IN_RING3
436
437/* Simple acpiChecksum: all the bytes must add up to 0. */
438static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
439{
440 uint8_t sum = 0;
441 for (size_t i = 0; i < len; ++i)
442 sum += data[i];
443 return -sum;
444}
445
446static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
447 uint32_t u32Length, uint8_t u8Revision)
448{
449 memcpy(header->au8Signature, au8Signature, 4);
450 header->u32Length = RT_H2LE_U32(u32Length);
451 header->u8Revision = u8Revision;
452 memcpy(header->au8OemId, "VBOX ", 6);
453 memcpy(header->au8OemTabId, "VBOX", 4);
454 memcpy(header->au8OemTabId+4, au8Signature, 4);
455 header->u32OemRevision = RT_H2LE_U32(1);
456 memcpy(header->au8CreatorId, "ASL ", 4);
457 header->u32CreatorRev = RT_H2LE_U32(0x61);
458}
459
460static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
461 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
462 uint8_t u8AccessSize, uint64_t u64Address)
463{
464 g->u8AddressSpaceId = u8AddressSpaceId;
465 g->u8RegisterBitWidth = u8RegisterBitWidth;
466 g->u8RegisterBitOffset = u8RegisterBitOffset;
467 g->u8AccessSize = u8AccessSize;
468 g->u64Address = RT_H2LE_U64(u64Address);
469}
470
471static void acpiPhyscpy (ACPIState *s, RTGCPHYS dst, const void * const src, size_t size)
472{
473 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
474}
475
476/* Differentiated System Description Table (DSDT) */
477static void acpiSetupDSDT (ACPIState *s, RTGCPHYS addr)
478{
479 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
480}
481
482/* Firmware ACPI Control Structure (FACS) */
483static void acpiSetupFACS (ACPIState *s, RTGCPHYS addr)
484{
485 ACPITBLFACS facs;
486
487 memset (&facs, 0, sizeof(facs));
488 memcpy (facs.au8Signature, "FACS", 4);
489 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
490 facs.u32HWSignature = RT_H2LE_U32(0);
491 facs.u32FWVector = RT_H2LE_U32(0);
492 facs.u32GlobalLock = RT_H2LE_U32(0);
493 facs.u32Flags = RT_H2LE_U32(0);
494 facs.u64X_FWVector = RT_H2LE_U64(0);
495 facs.u8Version = 1;
496
497 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
498}
499
500/* Fixed ACPI Description Table (FADT aka FACP) */
501static void acpiSetupFADT (ACPIState *s, RTGCPHYS addr, uint32_t facs_addr, uint32_t dsdt_addr)
502{
503 ACPITBLFADT fadt;
504
505 memset (&fadt, 0, sizeof(fadt));
506 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
507 fadt.u32FACS = RT_H2LE_U32(facs_addr);
508 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
509 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
510 fadt.u8PreferredPMProfile = 0; /* unspecified */
511 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
512 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
513 fadt.u8AcpiEnable = ACPI_ENABLE;
514 fadt.u8AcpiDisable = ACPI_DISABLE;
515 fadt.u8S4BIOSReq = 0;
516 fadt.u8PStateCnt = 0;
517 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
518 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
519 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
520 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
521 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
522 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
523 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
524 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
525 fadt.u8PM1EVTLEN = 4;
526 fadt.u8PM1CTLLEN = 2;
527 fadt.u8PM2CTLLEN = 0;
528 fadt.u8PMTMLEN = 4;
529 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
530 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
531 fadt.u8GPE1BASE = GPE1_BASE;
532 fadt.u8CSTCNT = 0;
533 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
534 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
535 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
536 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
537 fadt.u8DutyOffset = 0;
538 fadt.u8DutyWidth = 0;
539 fadt.u8DayAlarm = 0;
540 fadt.u8MonAlarm = 0;
541 fadt.u8Century = 0;
542 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
543 /** @note WBINVD is required for ACPI versions newer than 1.0 */
544 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD | FADT_FL_SLP_BUTTON
545 | FADT_FL_FIX_RTC | FADT_FL_TMR_VAL_EXT);
546 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
547 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
548 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
549 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
550 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
551 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
552 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
553 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
554 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
555 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
556 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
557 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
558 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
559 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
560}
561
562/*
563 * Root System Description Table.
564 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
565 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
566 */
567static int acpiSetupRSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
568{
569 ACPITBLRSDT *rsdt;
570 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
571
572 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
573 if (!rsdt)
574 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
575
576 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
577 for (unsigned int i = 0; i < nb_entries; ++i)
578 {
579 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
580 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
581 }
582 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
583 acpiPhyscpy (s, addr, rsdt, size);
584 RTMemFree (rsdt);
585 return VINF_SUCCESS;
586}
587
588/* Extended System Description Table. */
589static int acpiSetupXSDT (ACPIState *s, RTGCPHYS addr, unsigned int nb_entries, uint32_t *addrs)
590{
591 ACPITBLXSDT *xsdt;
592 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
593
594 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
595 if (!xsdt)
596 return VERR_NO_TMP_MEMORY;
597
598 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
599 for (unsigned int i = 0; i < nb_entries; ++i)
600 {
601 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
602 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
603 }
604 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
605 acpiPhyscpy (s, addr, xsdt, size);
606 RTMemFree (xsdt);
607 return VINF_SUCCESS;
608}
609
610/* Root System Description Pointer (RSDP) */
611static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
612{
613 memset(rsdp, 0, sizeof(*rsdp));
614
615 /* ACPI 1.0 part (RSDT */
616 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
617 memcpy(rsdp->au8OemId, "VBOX ", 6);
618 rsdp->u8Revision = ACPI_REVISION;
619 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
620 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
621
622 /* ACPI 2.0 part (XSDT) */
623 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
624 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
625 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
626}
627
628/* Multiple APIC Description Table. */
629/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
630/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
631static void acpiSetupMADT (ACPIState *s, RTGCPHYS addr)
632{
633 ACPITBLMADT madt;
634
635 /* Don't call this function if u8UseIOApic==false! */
636 Assert(s->u8UseIOApic);
637
638 memset(&madt, 0, sizeof(madt));
639 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
640
641 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
642 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
643
644 madt.LApic.u8Type = 0;
645 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
646 madt.LApic.u8ProcId = 0;
647 madt.LApic.u8ApicId = 0;
648 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
649
650 madt.IOApic.u8Type = 1;
651 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
652 madt.IOApic.u8IOApicId = 0;
653 madt.IOApic.u8Reserved = 0;
654 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
655 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
656
657 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
658 acpiPhyscpy (s, addr, &madt, sizeof(madt));
659}
660
661/* SCI IRQ */
662DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
663{
664 if (s->pm1a_ctl & SCI_EN)
665 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
666}
667
668DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
669{
670 return en & ~(RSR_EN | IGN_EN);
671}
672
673DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
674{
675 return sts & ~(RSR_STS | IGN_STS);
676}
677
678DECLINLINE(int) pm1a_level (ACPIState *s)
679{
680 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
681}
682
683DECLINLINE(int) gpe0_level (ACPIState *s)
684{
685 return (s->gpe0_en & s->gpe0_sts) != 0;
686}
687
688static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
689{
690 int old_level, new_level;
691
692 if (gpe0_level (s))
693 return;
694
695 old_level = pm1a_level (s);
696 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
697
698 s->pm1a_en = en;
699 s->pm1a_sts = sts;
700
701 if (new_level != old_level)
702 acpiSetIrq (s, new_level);
703}
704
705static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
706{
707 int old_level, new_level;
708
709 if (pm1a_level (s))
710 return;
711
712 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
713 new_level = (en & sts) != 0;
714
715 s->gpe0_en = en;
716 s->gpe0_sts = sts;
717
718 if (new_level != old_level)
719 acpiSetIrq (s, new_level);
720}
721
722static int acpiPowerDown (ACPIState *s)
723{
724 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
725 if (VBOX_FAILURE (rc))
726 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
727 return rc;
728}
729
730/** Converts a ACPI port interface pointer to an ACPI state pointer. */
731#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
732
733/**
734 * Send an ACPI power off event.
735 *
736 * @returns VBox status code
737 * @param pInterface Pointer to the interface structure containing the called function pointer.
738 */
739static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
740{
741 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
742 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
743 return VINF_SUCCESS;
744}
745
746/* PM1a_EVT_BLK enable */
747static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
748{
749 uint16_t val = s->pm1a_en;
750 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
751 return val;
752}
753
754static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
755{
756 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
757 val &= ~(RSR_EN | IGN_EN);
758 update_pm1a (s, s->pm1a_sts, val);
759}
760
761/* PM1a_EVT_BLK status */
762static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
763{
764 uint16_t val = s->pm1a_sts;
765 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
766 return val;
767}
768
769static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
770{
771 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
772 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
773 update_pm1a (s, val, s->pm1a_en);
774}
775
776/* PM1a_CTL_BLK */
777static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
778{
779 uint16_t val = s->pm1a_ctl;
780 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
781 return val;
782}
783
784static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
785{
786 uint32_t uSleepState;
787
788 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
789 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
790
791 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
792 if (uSleepState != s->uSleepState)
793 {
794 s->uSleepState = uSleepState;
795 switch (uSleepState)
796 {
797 case 0x00: /* S0 */
798 break;
799 case 0x05: /* S5 */
800 LogRel (("Entering S5 (power down)\n"));
801 return acpiPowerDown (s);
802 default:
803 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
804 break;
805 }
806 }
807 return VINF_SUCCESS;
808}
809
810/* GPE0_BLK */
811static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
812{
813 uint8_t val = s->gpe0_en;
814 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
815 return val;
816}
817
818static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
819{
820 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
821 update_gpe0 (s, s->gpe0_sts, val);
822}
823
824static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
825{
826 uint8_t val = s->gpe0_sts;
827 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
828 return val;
829}
830
831static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
832{
833 val = s->gpe0_sts & ~val;
834 update_gpe0 (s, val, s->gpe0_en);
835 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
836}
837
838static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
839{
840 int rc = VINF_SUCCESS;
841
842 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
843 if (val == ACPI_RESET_REG_VAL)
844 {
845# ifndef IN_RING3
846 rc = VINF_IOM_HC_IOPORT_WRITE;
847# else /* IN_RING3 */
848 rc = PDMDevHlpVMReset(s->pDevIns);
849# endif /* !IN_RING3 */
850 }
851 return rc;
852}
853
854/* SMI */
855static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
856{
857 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
858 if (val == ACPI_ENABLE)
859 s->pm1a_ctl |= SCI_EN;
860 else if (val == ACPI_DISABLE)
861 s->pm1a_ctl &= ~SCI_EN;
862 else
863 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
864}
865
866static uint32_t find_rsdp_space (void)
867{
868 return 0xe0000;
869}
870
871static void acpiPMTimerReset (ACPIState *s)
872{
873 uint64_t interval, freq;
874
875 freq = TMTimerGetFreq (s->CTXSUFF(ts));
876 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
877 Log (("interval = %RU64\n", interval));
878 TMTimerSet (s->CTXSUFF(ts), TMTimerGet (s->CTXSUFF(ts)) + interval);
879}
880
881static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
882{
883 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
884
885 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
886 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
887 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
888
889 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
890 acpiPMTimerReset (s);
891}
892
893/**
894 * _BST method.
895 */
896static void acpiFetchBatteryStatus (ACPIState *s)
897{
898 uint32_t *p = s->au8BatteryInfo;
899 bool fPresent; /* battery present? */
900 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
901 PDMACPIBATSTATE hostBatteryState; /* bitfield */
902 uint32_t hostPresentRate; /* 0..1000 */
903 int rc;
904
905 if (!s->pDrv)
906 return;
907 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
908 &hostBatteryState, &hostPresentRate);
909 AssertRC (rc);
910
911 /* default values */
912 p[BAT_STATUS_STATE] = hostBatteryState;
913 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
914 : hostPresentRate * 50; /* mW */
915 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
916 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
917
918 /* did we get a valid battery state? */
919 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
920 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
921 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
922 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
923}
924
925/**
926 * _BIF method.
927 */
928static void acpiFetchBatteryInfo (ACPIState *s)
929{
930 uint32_t *p = s->au8BatteryInfo;
931
932 p[BAT_INFO_UNITS] = 0; /* mWh */
933 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
934 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
935 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
936 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
937 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
938 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
939 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
940 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
941}
942
943/**
944 * _STA method.
945 */
946static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
947{
948 bool fPresent; /* battery present? */
949 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
950 PDMACPIBATSTATE hostBatteryState; /* bitfield */
951 uint32_t hostPresentRate; /* 0..1000 */
952 int rc;
953
954 if (!s->pDrv)
955 return 0;
956 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
957 &hostBatteryState, &hostPresentRate);
958 AssertRC (rc);
959
960 return fPresent
961 ? STA_DEVICE_PRESENT_MASK /* present */
962 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
963 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
964 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
965 | STA_BATTERY_PRESENT_MASK /* battery is present */
966 : 0; /* device not present */
967}
968
969static uint32_t acpiGetPowerSource (ACPIState *s)
970{
971 PDMACPIPOWERSOURCE ps;
972
973 /* query the current power source from the host driver */
974 if (!s->pDrv)
975 return AC_ONLINE;
976 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
977 AssertRC (rc);
978 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
979}
980
981IO_WRITE_PROTO (acpiBatIndexWrite)
982{
983 ACPIState *s = (ACPIState *)pvUser;
984
985 switch (cb)
986 {
987 case 4:
988 u32 >>= s->u8IndexShift;
989 /* see comment at the declaration of u8IndexShift */
990 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
991 {
992 s->u8IndexShift = 2;
993 u32 >>= 2;
994 }
995 Assert (u32 < BAT_INDEX_LAST);
996 s->uBatteryIndex = u32;
997 break;
998 default:
999 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1000 break;
1001 }
1002 return VINF_SUCCESS;
1003}
1004
1005IO_READ_PROTO (acpiBatDataRead)
1006{
1007 ACPIState *s = (ACPIState *)pvUser;
1008
1009 switch (cb)
1010 {
1011 case 4:
1012 switch (s->uBatteryIndex)
1013 {
1014 case BAT_STATUS_STATE:
1015 acpiFetchBatteryStatus(s);
1016 case BAT_STATUS_PRESENT_RATE:
1017 case BAT_STATUS_REMAINING_CAPACITY:
1018 case BAT_STATUS_PRESENT_VOLTAGE:
1019 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1020 break;
1021
1022 case BAT_INFO_UNITS:
1023 acpiFetchBatteryInfo(s);
1024 case BAT_INFO_DESIGN_CAPACITY:
1025 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1026 case BAT_INFO_TECHNOLOGY:
1027 case BAT_INFO_DESIGN_VOLTAGE:
1028 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1029 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1030 case BAT_INFO_CAPACITY_GRANULARITY_1:
1031 case BAT_INFO_CAPACITY_GRANULARITY_2:
1032 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1033 break;
1034
1035 case BAT_DEVICE_STATUS:
1036 *pu32 = acpiGetBatteryDeviceStatus(s);
1037 break;
1038
1039 case BAT_POWER_SOURCE:
1040 *pu32 = acpiGetPowerSource(s);
1041 break;
1042
1043 default:
1044 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1045 break;
1046 }
1047 break;
1048 default:
1049 return VERR_IOM_IOPORT_UNUSED;
1050 }
1051// LogRel(("Query %04x => %08x\n", s->uBatteryIndex, *pu32));
1052 return VINF_SUCCESS;
1053}
1054
1055IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1056{
1057 ACPIState *s = (ACPIState *)pvUser;
1058
1059 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1060 switch (cb) {
1061 case 4:
1062 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1063 s->uSystemInfoIndex = u32;
1064 else
1065 {
1066 u32 >>= s->u8IndexShift;
1067 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1068 s->uSystemInfoIndex = u32;
1069 }
1070 break;
1071
1072 default:
1073 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1074 break;
1075 }
1076 return VINF_SUCCESS;
1077}
1078
1079IO_READ_PROTO (acpiSysInfoDataRead)
1080{
1081 ACPIState *s = (ACPIState *)pvUser;
1082
1083 switch (cb)
1084 {
1085 case 4:
1086 switch (s->uSystemInfoIndex)
1087 {
1088 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1089 *pu32 = s->u64RamSize;
1090 break;
1091
1092 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1093 *pu32 = s->u8UseIOApic;
1094 break;
1095
1096 default:
1097 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1098 break;
1099 }
1100 break;
1101
1102 default:
1103 return VERR_IOM_IOPORT_UNUSED;
1104 }
1105
1106 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1107 return VINF_SUCCESS;
1108}
1109
1110IO_WRITE_PROTO (acpiSysInfoDataWrite)
1111{
1112 ACPIState *s = (ACPIState *)pvUser;
1113
1114 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1115
1116 if (cb == 4 && u32 == 0xbadc0de)
1117 {
1118 switch (s->uSystemInfoIndex)
1119 {
1120 case SYSTEM_INFO_INDEX_INVALID:
1121 s->u8IndexShift = 0;
1122 break;
1123
1124 case SYSTEM_INFO_INDEX_VALID:
1125 s->u8IndexShift = 2;
1126 break;
1127
1128 default:
1129 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1130 Port, cb, u32, s->uSystemInfoIndex));
1131 break;
1132 }
1133 }
1134 else
1135 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1136 return VINF_SUCCESS;
1137}
1138
1139/* IO Helpers */
1140IO_READ_PROTO (acpiPm1aEnRead)
1141{
1142 switch (cb)
1143 {
1144 case 2:
1145 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1146 break;
1147 default:
1148 return VERR_IOM_IOPORT_UNUSED;
1149 }
1150 return VINF_SUCCESS;
1151}
1152
1153IO_READ_PROTO (acpiPm1aStsRead)
1154{
1155 switch (cb)
1156 {
1157 case 2:
1158 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1159 break;
1160 default:
1161 return VERR_IOM_IOPORT_UNUSED;
1162 }
1163 return VINF_SUCCESS;
1164}
1165
1166IO_READ_PROTO (acpiPm1aCtlRead)
1167{
1168 switch (cb)
1169 {
1170 case 2:
1171 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1172 break;
1173 default:
1174 return VERR_IOM_IOPORT_UNUSED;
1175 }
1176 return VINF_SUCCESS;
1177}
1178
1179IO_WRITE_PROTO (acpiPM1aEnWrite)
1180{
1181 switch (cb)
1182 {
1183 case 2:
1184 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1185 break;
1186 default:
1187 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1188 break;
1189 }
1190 return VINF_SUCCESS;
1191}
1192
1193IO_WRITE_PROTO (acpiPM1aStsWrite)
1194{
1195 switch (cb)
1196 {
1197 case 2:
1198 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1199 break;
1200 default:
1201 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1202 break;
1203 }
1204 return VINF_SUCCESS;
1205}
1206
1207IO_WRITE_PROTO (acpiPM1aCtlWrite)
1208{
1209 switch (cb)
1210 {
1211 case 2:
1212 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1213 default:
1214 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1215 break;
1216 }
1217 return VINF_SUCCESS;
1218}
1219
1220#endif /* IN_RING3 */
1221
1222/**
1223 * PMTMR readable from host/guest.
1224 */
1225IO_READ_PROTO (acpiPMTmrRead)
1226{
1227 if (cb == 4)
1228 {
1229 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1230 int64_t now = TMTimerGet (s->CTXSUFF(ts));
1231 int64_t elapsed = now - s->pm_timer_initial;
1232
1233 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTXSUFF(ts)));
1234 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1235 return VINF_SUCCESS;
1236 }
1237 return VERR_IOM_IOPORT_UNUSED;
1238}
1239
1240#ifdef IN_RING3
1241
1242IO_READ_PROTO (acpiGpe0StsRead)
1243{
1244 switch (cb)
1245 {
1246 case 1:
1247 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1248 break;
1249 default:
1250 return VERR_IOM_IOPORT_UNUSED;
1251 }
1252 return VINF_SUCCESS;
1253}
1254
1255IO_READ_PROTO (acpiGpe0EnRead)
1256{
1257 switch (cb)
1258 {
1259 case 1:
1260 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1261 break;
1262 default:
1263 return VERR_IOM_IOPORT_UNUSED;
1264 }
1265 return VINF_SUCCESS;
1266}
1267
1268IO_WRITE_PROTO (acpiGpe0StsWrite)
1269{
1270 switch (cb)
1271 {
1272 case 1:
1273 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1274 break;
1275 default:
1276 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1277 break;
1278 }
1279 return VINF_SUCCESS;
1280}
1281
1282IO_WRITE_PROTO (acpiGpe0EnWrite)
1283{
1284 switch (cb)
1285 {
1286 case 1:
1287 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1288 break;
1289 default:
1290 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1291 break;
1292 }
1293 return VINF_SUCCESS;
1294}
1295
1296IO_WRITE_PROTO (acpiSmiWrite)
1297{
1298 switch (cb)
1299 {
1300 case 1:
1301 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1302 break;
1303 default:
1304 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1305 break;
1306 }
1307 return VINF_SUCCESS;
1308}
1309
1310IO_WRITE_PROTO (acpiResetWrite)
1311{
1312 switch (cb)
1313 {
1314 case 1:
1315 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1316 default:
1317 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1318 break;
1319 }
1320 return VINF_SUCCESS;
1321}
1322
1323#ifdef DEBUG_ACPI
1324
1325IO_WRITE_PROTO (acpiDhexWrite)
1326{
1327 switch (cb)
1328 {
1329 case 1:
1330 Log (("%#x\n", u32 & 0xff));
1331 break;
1332 case 2:
1333 Log (("%#6x\n", u32 & 0xffff));
1334 case 4:
1335 Log (("%#10x\n", u32));
1336 break;
1337 default:
1338 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1339 break;
1340 }
1341 return VINF_SUCCESS;
1342}
1343
1344IO_WRITE_PROTO (acpiDchrWrite)
1345{
1346 switch (cb)
1347 {
1348 case 1:
1349 Log (("%c", u32 & 0xff));
1350 break;
1351 default:
1352 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1353 break;
1354 }
1355 return VINF_SUCCESS;
1356}
1357
1358#endif /* DEBUG_ACPI */
1359
1360
1361/**
1362 * Saved state structure description.
1363 */
1364static const SSMFIELD g_AcpiSavedStateFields[] =
1365{
1366 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1367 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1368 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1369 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1370 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1371 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1372 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1373 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1374 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1375 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1376 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1377 SSMFIELD_ENTRY (ACPIState, uSleepState),
1378 SSMFIELD_ENTRY_TERM ()
1379};
1380
1381static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1382{
1383 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1384 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1385}
1386
1387static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1388 uint32_t u32Version)
1389{
1390 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1391 int rc;
1392
1393 if (u32Version != 4)
1394 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1395
1396 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1397 if (VBOX_SUCCESS (rc))
1398 {
1399 acpiFetchBatteryStatus (s);
1400 acpiFetchBatteryInfo (s);
1401 acpiPMTimerReset (s);
1402 }
1403 return rc;
1404}
1405
1406/**
1407 * Queries an interface to the driver.
1408 *
1409 * @returns Pointer to interface.
1410 * @returns NULL if the interface was not supported by the driver.
1411 * @param pInterface Pointer to this interface structure.
1412 * @param enmInterface The requested interface identification.
1413 * @thread Any thread.
1414 */
1415static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1416{
1417 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1418 switch (enmInterface)
1419 {
1420 case PDMINTERFACE_BASE:
1421 return &pData->IBase;
1422 case PDMINTERFACE_ACPI_PORT:
1423 return &pData->IACPIPort;
1424 default:
1425 return NULL;
1426 }
1427}
1428
1429/**
1430 * Create the ACPI tables.
1431 */
1432static int acpiPlantTables (ACPIState *s)
1433{
1434 int rc;
1435 uint32_t rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1436 uint32_t addend = 0;
1437 uint32_t rsdt_addrs[4];
1438 uint32_t cAddr;
1439 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1440 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1441
1442 cAddr = 1; /* FADT */
1443 if (s->u8UseIOApic)
1444 cAddr++; /* MADT */
1445
1446 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1447 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1448
1449 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1450 if (VBOX_FAILURE (rc))
1451 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1452 N_("Configuration error: Querying "
1453 "\"RamSize\" as integer failed"));
1454
1455 if (s->u64RamSize > (0xffffffff - 0x10000))
1456 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1457 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1458 "value is 4095MB"));
1459
1460 rsdt_addr = 0;
1461 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1462 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1463 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1464 if (s->u8UseIOApic)
1465 {
1466 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1467 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1468 }
1469 else
1470 {
1471 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1472 }
1473
1474 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1475 if (last_addr > 0x10000)
1476 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1477 N_("Error: ACPI tables > 64KB!"));
1478
1479 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1480 addend = (uint32_t) s->u64RamSize - 0x10000;
1481 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1482 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1483 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1484 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1485 acpiSetupDSDT (s, dsdt_addr + addend);
1486 acpiSetupFACS (s, facs_addr + addend);
1487 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1488
1489 rsdt_addrs[0] = fadt_addr + addend;
1490 if (s->u8UseIOApic)
1491 {
1492 acpiSetupMADT (s, apic_addr + addend);
1493 rsdt_addrs[1] = apic_addr + addend;
1494 }
1495
1496 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1497 if (VBOX_FAILURE(rc))
1498 return rc;
1499 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1500}
1501
1502/**
1503 * Construct a device instance for a VM.
1504 *
1505 * @returns VBox status.
1506 * @param pDevIns The device instance data.
1507 * If the registration structure is needed, pDevIns->pDevReg points to it.
1508 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1509 * The device number is also found in pDevIns->iInstance, but since it's
1510 * likely to be freqently used PDM passes it as parameter.
1511 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1512 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1513 * iInstance it's expected to be used a bit in this function.
1514 */
1515static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1516{
1517 int rc;
1518 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1519 uint32_t rsdp_addr;
1520 PCIDevice *dev;
1521 bool fGCEnabled;
1522 bool fR0Enabled;
1523
1524 /* Validate and read the configuration. */
1525 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0"))
1526 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1527 N_("Configuration error: Invalid config key for ACPI device"));
1528
1529 s->pDevIns = pDevIns;
1530
1531 /* query whether we are supposed to present an IOAPIC */
1532 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1533 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1534 s->u8UseIOApic = 1;
1535 else if (VBOX_FAILURE (rc))
1536 return PDMDEV_SET_ERROR(pDevIns, rc,
1537 N_("Configuration error: Failed to read \"IOAPIC\"."));
1538
1539 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1540 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1541 fGCEnabled = true;
1542 else if (VBOX_FAILURE (rc))
1543 return PDMDEV_SET_ERROR(pDevIns, rc,
1544 N_("Configuration error: Failed to read \"GCEnabled\"."));
1545
1546 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1547 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1548 fR0Enabled = true;
1549 else if (VBOX_FAILURE(rc))
1550 return PDMDEV_SET_ERROR(pDevIns, rc,
1551 N_("configuration error: failed to read R0Enabled as boolean."));
1552
1553 /* */
1554 rsdp_addr = find_rsdp_space ();
1555 if (!rsdp_addr)
1556 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1557 N_("Can not find space for RSDP. ACPI is disabled."));
1558
1559 rc = acpiPlantTables (s);
1560 if (VBOX_FAILURE (rc))
1561 return rc;
1562
1563 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1564 if (VBOX_FAILURE (rc))
1565 return rc;
1566
1567#define R(addr, cnt, writer, reader, description) \
1568 do { \
1569 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1570 NULL, NULL, description); \
1571 if (VBOX_FAILURE (rc)) \
1572 return rc; \
1573 } while (0)
1574#define L (GPE0_BLK_LEN / 2)
1575
1576 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1577 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1578 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1579 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1580 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1581#ifdef DEBUG_ACPI
1582 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1583 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1584#endif
1585 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1586 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1587 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1588 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1589 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1590 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1591 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1592#undef L
1593#undef R
1594
1595 /* register GC stuff */
1596 if (fGCEnabled)
1597 {
1598 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1599 NULL, NULL, "ACPI PM Timer");
1600 AssertRCReturn(rc, rc);
1601 }
1602
1603 /* register R0 stuff */
1604 if (fR0Enabled)
1605 {
1606 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1607 NULL, NULL, "ACPI PM Timer");
1608 AssertRCReturn(rc, rc);
1609 }
1610
1611 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsHC);
1612 if (VBOX_FAILURE(rc))
1613 {
1614 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1615 return rc;
1616 }
1617
1618 s->tsGC = TMTimerGCPtr (s->tsHC);
1619 s->pm_timer_initial = TMTimerGet (s->tsHC);
1620 acpiPMTimerReset (s);
1621
1622 dev = &s->dev;
1623 dev->config[0x00] = 0x86;
1624 dev->config[0x01] = 0x80;
1625
1626 dev->config[0x02] = 0x13;
1627 dev->config[0x03] = 0x71;
1628
1629 dev->config[0x04] = 0x01;
1630 dev->config[0x05] = 0x00;
1631
1632 dev->config[0x06] = 0x80;
1633 dev->config[0x07] = 0x02;
1634 dev->config[0x08] = 0x08;
1635 dev->config[0x09] = 0x00;
1636
1637 dev->config[0x0a] = 0x80;
1638 dev->config[0x0b] = 0x06;
1639
1640 dev->config[0x0e] = 0x80;
1641 dev->config[0x0f] = 0x00;
1642
1643#if 0 /* The ACPI controller usually has no subsystem ID. */
1644 dev->config[0x2c] = 0x86;
1645 dev->config[0x2d] = 0x80;
1646 dev->config[0x2e] = 0x00;
1647 dev->config[0x2f] = 0x00;
1648#endif
1649 dev->config[0x3c] = SCI_INT;
1650
1651 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1652 if (VBOX_FAILURE (rc))
1653 return rc;
1654
1655 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1656 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1657 if (VBOX_FAILURE(rc))
1658 return rc;
1659
1660 /*
1661 * Interfaces
1662 */
1663 /* IBase */
1664 s->IBase.pfnQueryInterface = acpiQueryInterface;
1665 /* IACPIPort */
1666 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1667
1668 /*
1669 * Get the corresponding connector interface
1670 */
1671 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1672 if (VBOX_SUCCESS (rc))
1673 {
1674 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1675 PDMINTERFACE_ACPI_CONNECTOR);
1676 if (!s->pDrv)
1677 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1678 N_("LUN #0 doesn't have an ACPI connector interface!\n"));
1679 }
1680 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1681 {
1682 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1683 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1684 rc = VINF_SUCCESS;
1685 }
1686 else
1687 return PDMDEV_SET_ERROR(pDevIns, rc,
1688 N_("Failed to attach LUN #0!"));
1689
1690 return rc;
1691}
1692
1693/**
1694 * Relocates the GC pointer members.
1695 */
1696static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1697{
1698 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1699 s->tsGC = TMTimerGCPtr (s->tsHC);
1700}
1701
1702static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1703{
1704 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1705
1706 s->pm1a_en = 0;
1707 s->pm1a_sts = 0;
1708 s->pm1a_ctl = 0;
1709 s->pm_timer_initial = TMTimerGet (s->CTXSUFF(ts));
1710 acpiPMTimerReset(s);
1711 s->uBatteryIndex = 0;
1712 s->uSystemInfoIndex = 0;
1713 s->gpe0_en = 0;
1714 s->gpe0_sts = 0;
1715 s->uSleepState = 0;
1716
1717 acpiPlantTables(s);
1718}
1719
1720/**
1721 * The device registration structure.
1722 */
1723const PDMDEVREG g_DeviceACPI =
1724{
1725 /* u32Version */
1726 PDM_DEVREG_VERSION,
1727 /* szDeviceName */
1728 "acpi",
1729 /* szGCMod */
1730 "VBoxDDGC.gc",
1731 /* szR0Mod */
1732 "VBoxDDR0.r0",
1733 /* pszDescription */
1734 "Advanced Configuration and Power Interface",
1735 /* fFlags */
1736 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1737 /* fClass */
1738 PDM_DEVREG_CLASS_ACPI,
1739 /* cMaxInstances */
1740 ~0,
1741 /* cbInstance */
1742 sizeof(ACPIState),
1743 /* pfnConstruct */
1744 acpiConstruct,
1745 /* pfnDestruct */
1746 NULL,
1747 /* pfnRelocate */
1748 acpiRelocate,
1749 /* pfnIOCtl */
1750 NULL,
1751 /* pfnPowerOn */
1752 NULL,
1753 /* pfnReset */
1754 acpiReset,
1755 /* pfnSuspend */
1756 NULL,
1757 /* pfnResume */
1758 NULL,
1759 /* pfnAttach */
1760 NULL,
1761 /* pfnDetach */
1762 NULL,
1763 /* pfnQueryInterface. */
1764 NULL
1765};
1766
1767#endif /* IN_RING3 */
1768#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1769
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