VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 9152

Last change on this file since 9152 was 8155, checked in by vboxsync, 17 years ago

The Big Sun Rebranding Header Change
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1/* $Id: DevACPI.cpp 8155 2008-04-18 15:16:47Z vboxsync $ */
2/** @file
3 * Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23
24#include <VBox/pdmdev.h>
25#include <VBox/log.h>
26#include <iprt/assert.h>
27#include <iprt/asm.h>
28#ifdef IN_RING3
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31#endif /* IN_RING3 */
32
33#include "Builtins.h"
34
35#ifdef LOG_ENABLED
36#define DEBUG_ACPI
37#endif
38
39/* the compiled DSL */
40#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
41#include <vboxaml.hex>
42#endif /* !IN_RING3 */
43
44#define IO_READ_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t *pu32, unsigned cb)
47
48#define IO_WRITE_PROTO(name) \
49 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
50 RTIOPORT Port, uint32_t u32, unsigned cb)
51
52#define DEBUG_HEX 0x3000
53#define DEBUG_CHR 0x3001
54
55#define PM_TMR_FREQ 3579545
56#define PM1a_EVT_BLK 0x00004000
57#define PM1b_EVT_BLK 0x00000000 /**< not supported */
58#define PM1a_CTL_BLK 0x00004004
59#define PM1b_CTL_BLK 0x00000000 /**< not supported */
60#define PM2_CTL_BLK 0x00000000 /**< not supported */
61#define PM_TMR_BLK 0x00004008
62#define GPE0_BLK 0x00004020
63#define GPE1_BLK 0x00000000 /**< not supported */
64#define BAT_INDEX 0x00004040
65#define BAT_DATA 0x00004044
66#define SYSI_INDEX 0x00004048
67#define SYSI_DATA 0x0000404c
68#define ACPI_RESET_BLK 0x00004050
69
70/* PM1x status register bits */
71#define TMR_STS RT_BIT(0)
72#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
73#define BM_STS RT_BIT(4)
74#define GBL_STS RT_BIT(5)
75#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
76#define PWRBTN_STS RT_BIT(8)
77#define SLPBTN_STS RT_BIT(9)
78#define RTC_STS RT_BIT(10)
79#define IGN_STS RT_BIT(11)
80#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
81#define WAK_STS RT_BIT(15)
82#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
83
84/* PM1x enable register bits */
85#define TMR_EN RT_BIT(0)
86#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
87#define GBL_EN RT_BIT(5)
88#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
89#define PWRBTN_EN RT_BIT(8)
90#define SLPBTN_EN RT_BIT(9)
91#define RTC_EN RT_BIT(10)
92#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
93#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
94#define IGN_EN 0
95
96/* PM1x control register bits */
97#define SCI_EN RT_BIT(0)
98#define BM_RLD RT_BIT(1)
99#define GBL_RLS RT_BIT(2)
100#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
101#define IGN_CNT RT_BIT(9)
102#define SLP_TYPx_SHIFT 10
103#define SLP_TYPx_MASK 7
104#define SLP_EN RT_BIT(13)
105#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
106#define RSR_CNT (RSR1_CNT | RSR2_CNT)
107
108#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
109
110enum
111{
112 BAT_STATUS_STATE = 0x00, /**< BST battery state */
113 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
114 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
115 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
116 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
117 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
118 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
119 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
120 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
121 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
122 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
123 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
124 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
125 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
126 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
127 BAT_INDEX_LAST
128};
129
130enum
131{
132 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
133 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
134 SYSTEM_INFO_INDEX_LAST = 2,
135 SYSTEM_INFO_INDEX_INVALID = 0x80,
136 SYSTEM_INFO_INDEX_VALID = 0x200
137};
138
139#define AC_OFFLINE 0
140#define AC_ONLINE 1
141
142#define BAT_TECH_PRIMARY 1
143#define BAT_TECH_SECONDARY 2
144
145#define BAT_STATUS_DISCHARGING_MASK RT_BIT(0)
146#define BAT_STATUS_CHARGING_MASK RT_BIT(1)
147#define BAT_STATUS_CRITICAL_MASK RT_BIT(2)
148
149#define STA_DEVICE_PRESENT_MASK RT_BIT(0)
150#define STA_DEVICE_ENABLED_MASK RT_BIT(1)
151#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2)
152#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3)
153#define STA_BATTERY_PRESENT_MASK RT_BIT(4)
154
155struct ACPIState
156{
157 PCIDevice dev;
158 uint16_t pm1a_en;
159 uint16_t pm1a_sts;
160 uint16_t pm1a_ctl;
161 uint16_t Alignment0;
162 int64_t pm_timer_initial;
163 R3R0PTRTYPE(PTMTIMER) tsHC;
164 GCPTRTYPE(PTMTIMER) tsGC;
165
166 uint32_t gpe0_en;
167 uint32_t gpe0_sts;
168
169 unsigned int uBatteryIndex;
170 uint32_t au8BatteryInfo[13];
171
172 unsigned int uSystemInfoIndex;
173 uint64_t u64RamSize;
174
175 /** Current ACPI S* state. We support S0 and S5 */
176 uint32_t uSleepState;
177 uint8_t au8RSDPPage[0x1000];
178 /** This is a workaround for incorrect index field handling by Intels ACPICA.
179 * The system info _INI method writes to offset 0x200. We either observe a
180 * write request to index 0x80 (in that case we don't change the index) or a
181 * write request to offset 0x200 (in that case we divide the index value by
182 * 4. Note that the _STA method is sometimes called prior to the _INI method
183 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
184 * acpiBatIndexWrite() for handling this. */
185 uint8_t u8IndexShift;
186 uint8_t u8UseIOApic;
187 bool fPowerButtonHandled;
188
189 /** ACPI port base interface. */
190 PDMIBASE IBase;
191 /** ACPI port interface. */
192 PDMIACPIPORT IACPIPort;
193 /** Pointer to the device instance. */
194 PPDMDEVINSR3 pDevIns;
195 /** Pointer to the driver base interface */
196 R3PTRTYPE(PPDMIBASE) pDrvBase;
197 /** Pointer to the driver connector interface */
198 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
199};
200
201#pragma pack(1)
202
203/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
204struct ACPIGENADDR
205{
206 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
207 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
208 uint8_t u8RegisterBitOffset; /**< bit offset of register */
209 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
210 uint64_t u64Address; /**< 64-bit address of register */
211};
212AssertCompileSize(ACPIGENADDR, 12);
213
214/** Root System Description Pointer */
215struct ACPITBLRSDP
216{
217 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
218 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
219 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
220 uint8_t u8Revision; /**< revision number, currently 2 */
221#define ACPI_REVISION 2 /**< ACPI 3.0 */
222 uint32_t u32RSDT; /**< phys addr of RSDT */
223 uint32_t u32Length; /**< bytes of this table */
224 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
225 uint8_t u8ExtChecksum; /**< checksum of entire table */
226 uint8_t u8Reserved[3]; /**< reserved */
227};
228AssertCompileSize(ACPITBLRSDP, 36);
229
230/** System Description Table Header */
231struct ACPITBLHEADER
232{
233 uint8_t au8Signature[4]; /**< table identifier */
234 uint32_t u32Length; /**< length of the table including header */
235 uint8_t u8Revision; /**< revision number */
236 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
237 uint8_t au8OemId[6]; /**< OEM-supplied string */
238 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
239 uint32_t u32OemRevision; /**< OEM-supplied revision number */
240 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
241 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
242};
243AssertCompileSize(ACPITBLHEADER, 36);
244
245/** Root System Description Table */
246struct ACPITBLRSDT
247{
248 ACPITBLHEADER header;
249 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
250};
251AssertCompileSize(ACPITBLRSDT, 40);
252
253/** Extended System Description Table */
254struct ACPITBLXSDT
255{
256 ACPITBLHEADER header;
257 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
258};
259AssertCompileSize(ACPITBLXSDT, 44);
260
261/** Fixed ACPI Description Table */
262struct ACPITBLFADT
263{
264 ACPITBLHEADER header;
265 uint32_t u32FACS; /**< phys. address of FACS */
266 uint32_t u32DSDT; /**< phys. address of DSDT */
267 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
268#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
269#define INT_MODEL_MULTIPLE_APIC 2
270 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
271 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
272#define SCI_INT 9
273 uint32_t u32SMICmd; /**< system port address of SMI command port */
274#define SMI_CMD 0x0000442e
275 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
276#define ACPI_ENABLE 0xa1
277 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
278#define ACPI_DISABLE 0xa0
279 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
280 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
281 state control responsibility */
282 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
283 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
284 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
285 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
286 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
287 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
288 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
289 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
290 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
291 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
292 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
293 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
294 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
295#define GPE0_BLK_LEN 2
296 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
297#define GPE1_BLK_LEN 0
298 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
299#define GPE1_BASE 0
300 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
301 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
302#define P_LVL2_LAT 101 /**< C2 state not supported */
303 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
304#define P_LVL3_LAT 1001 /**< C3 state not supported */
305 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
306 lines from any processors memory caches */
307#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
308 uint16_t u16FlushStride; /**< cache line width */
309#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
310 uint8_t u8DutyOffset;
311 uint8_t u8DutyWidth;
312 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
313 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
314 uint8_t u8Century; /**< RTC CMOS RAM index of century */
315 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
316#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
317 (COM too?) */
318#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
319#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
320 uint8_t u8Must0_0; /**< must be 0 */
321 uint32_t u32Flags; /**< fixed feature flags */
322#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
323#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
324#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
325#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
326#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
327#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
328#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
329#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
330#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
331#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
332#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
333#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
334#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
335#define FADT_FL_CPU_SW_SLP RT_BIT(13)
336#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
337#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
338#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
339#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
340#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
341#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
342 ACPIGENADDR ResetReg; /**< ext addr of reset register */
343 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
344#define ACPI_RESET_REG_VAL 0x10
345 uint8_t au8Must0_1[3]; /**< must be 0 */
346 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
347 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
348 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
349 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
350 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
351 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
352 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
353 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
354 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
355 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
356};
357AssertCompileSize(ACPITBLFADT, 244);
358
359/** Firmware ACPI Control Structure */
360struct ACPITBLFACS
361{
362 uint8_t au8Signature[4]; /**< 'FACS' */
363 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
364 uint32_t u32HWSignature; /**< systems HW signature at last boot */
365 uint32_t u32FWVector; /**< address of waking vector */
366 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
367 uint32_t u32Flags; /**< FACS flags */
368 uint64_t u64X_FWVector; /**< 64-bit waking vector */
369 uint8_t u8Version; /**< version of this table */
370 uint8_t au8Reserved[31]; /**< zero */
371};
372AssertCompileSize(ACPITBLFACS, 64);
373
374/** Processor Local APIC Structure */
375struct ACPITBLLAPIC
376{
377 uint8_t u8Type; /**< 0 = LAPIC */
378 uint8_t u8Length; /**< 8 */
379 uint8_t u8ProcId; /**< processor ID */
380 uint8_t u8ApicId; /**< local APIC ID */
381 uint32_t u32Flags; /**< Flags */
382#define LAPIC_ENABLED 0x1
383};
384AssertCompileSize(ACPITBLLAPIC, 8);
385
386/** I/O APIC Structure */
387struct ACPITBLIOAPIC
388{
389 uint8_t u8Type; /**< 1 == I/O APIC */
390 uint8_t u8Length; /**< 12 */
391 uint8_t u8IOApicId; /**< I/O APIC ID */
392 uint8_t u8Reserved; /**< 0 */
393 uint32_t u32Address; /**< phys address to access I/O APIC */
394 uint32_t u32GSIB; /**< global system interrupt number to start */
395};
396AssertCompileSize(ACPITBLIOAPIC, 12);
397
398/** Multiple APIC Description Table */
399struct ACPITBLMADT
400{
401 ACPITBLHEADER header;
402 uint32_t u32LAPIC; /**< local APIC address */
403 uint32_t u32Flags; /**< Flags */
404#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
405 ACPITBLLAPIC LApic;
406 ACPITBLIOAPIC IOApic;
407};
408AssertCompileSize(ACPITBLMADT, 64);
409
410#pragma pack()
411
412
413#ifndef VBOX_DEVICE_STRUCT_TESTCASE
414__BEGIN_DECLS
415IO_READ_PROTO (acpiPMTmrRead);
416#ifdef IN_RING3
417IO_READ_PROTO (acpiPm1aEnRead);
418IO_WRITE_PROTO (acpiPM1aEnWrite);
419IO_READ_PROTO (acpiPm1aStsRead);
420IO_WRITE_PROTO (acpiPM1aStsWrite);
421IO_READ_PROTO (acpiPm1aCtlRead);
422IO_WRITE_PROTO (acpiPM1aCtlWrite);
423IO_WRITE_PROTO (acpiSmiWrite);
424IO_WRITE_PROTO (acpiBatIndexWrite);
425IO_READ_PROTO (acpiBatDataRead);
426IO_READ_PROTO (acpiSysInfoDataRead);
427IO_WRITE_PROTO (acpiSysInfoDataWrite);
428IO_READ_PROTO (acpiGpe0EnRead);
429IO_WRITE_PROTO (acpiGpe0EnWrite);
430IO_READ_PROTO (acpiGpe0StsRead);
431IO_WRITE_PROTO (acpiGpe0StsWrite);
432IO_WRITE_PROTO (acpiResetWrite);
433# ifdef DEBUG_ACPI
434IO_WRITE_PROTO (acpiDhexWrite);
435IO_WRITE_PROTO (acpiDchrWrite);
436# endif
437#endif
438__END_DECLS
439
440#ifdef IN_RING3
441
442/* Simple acpiChecksum: all the bytes must add up to 0. */
443static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
444{
445 uint8_t sum = 0;
446 for (size_t i = 0; i < len; ++i)
447 sum += data[i];
448 return -sum;
449}
450
451static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
452 uint32_t u32Length, uint8_t u8Revision)
453{
454 memcpy(header->au8Signature, au8Signature, 4);
455 header->u32Length = RT_H2LE_U32(u32Length);
456 header->u8Revision = u8Revision;
457 memcpy(header->au8OemId, "VBOX ", 6);
458 memcpy(header->au8OemTabId, "VBOX", 4);
459 memcpy(header->au8OemTabId+4, au8Signature, 4);
460 header->u32OemRevision = RT_H2LE_U32(1);
461 memcpy(header->au8CreatorId, "ASL ", 4);
462 header->u32CreatorRev = RT_H2LE_U32(0x61);
463}
464
465static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
466 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
467 uint8_t u8AccessSize, uint64_t u64Address)
468{
469 g->u8AddressSpaceId = u8AddressSpaceId;
470 g->u8RegisterBitWidth = u8RegisterBitWidth;
471 g->u8RegisterBitOffset = u8RegisterBitOffset;
472 g->u8AccessSize = u8AccessSize;
473 g->u64Address = RT_H2LE_U64(u64Address);
474}
475
476static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
477{
478 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
479}
480
481/* Differentiated System Description Table (DSDT) */
482static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
483{
484 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
485}
486
487/* Firmware ACPI Control Structure (FACS) */
488static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
489{
490 ACPITBLFACS facs;
491
492 memset (&facs, 0, sizeof(facs));
493 memcpy (facs.au8Signature, "FACS", 4);
494 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
495 facs.u32HWSignature = RT_H2LE_U32(0);
496 facs.u32FWVector = RT_H2LE_U32(0);
497 facs.u32GlobalLock = RT_H2LE_U32(0);
498 facs.u32Flags = RT_H2LE_U32(0);
499 facs.u64X_FWVector = RT_H2LE_U64(0);
500 facs.u8Version = 1;
501
502 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
503}
504
505/* Fixed ACPI Description Table (FADT aka FACP) */
506static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
507{
508 ACPITBLFADT fadt;
509
510 memset (&fadt, 0, sizeof(fadt));
511 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
512 fadt.u32FACS = RT_H2LE_U32(facs_addr);
513 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
514 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
515 fadt.u8PreferredPMProfile = 0; /* unspecified */
516 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
517 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
518 fadt.u8AcpiEnable = ACPI_ENABLE;
519 fadt.u8AcpiDisable = ACPI_DISABLE;
520 fadt.u8S4BIOSReq = 0;
521 fadt.u8PStateCnt = 0;
522 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
523 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
524 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
525 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
526 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
527 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
528 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
529 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
530 fadt.u8PM1EVTLEN = 4;
531 fadt.u8PM1CTLLEN = 2;
532 fadt.u8PM2CTLLEN = 0;
533 fadt.u8PMTMLEN = 4;
534 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
535 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
536 fadt.u8GPE1BASE = GPE1_BASE;
537 fadt.u8CSTCNT = 0;
538 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
539 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
540 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
541 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
542 fadt.u8DutyOffset = 0;
543 fadt.u8DutyWidth = 0;
544 fadt.u8DayAlarm = 0;
545 fadt.u8MonAlarm = 0;
546 fadt.u8Century = 0;
547 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
548 /** @note WBINVD is required for ACPI versions newer than 1.0 */
549 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
550 | FADT_FL_FIX_RTC
551 | FADT_FL_TMR_VAL_EXT);
552 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
553 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
554 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
555 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
556 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
557 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
558 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
559 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
560 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
561 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
562 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
563 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
564 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
565 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
566}
567
568/*
569 * Root System Description Table.
570 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
571 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
572 */
573static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
574{
575 ACPITBLRSDT *rsdt;
576 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
577
578 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
579 if (!rsdt)
580 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
581
582 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
583 for (unsigned int i = 0; i < nb_entries; ++i)
584 {
585 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
586 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
587 }
588 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
589 acpiPhyscpy (s, addr, rsdt, size);
590 RTMemFree (rsdt);
591 return VINF_SUCCESS;
592}
593
594/* Extended System Description Table. */
595static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
596{
597 ACPITBLXSDT *xsdt;
598 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
599
600 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
601 if (!xsdt)
602 return VERR_NO_TMP_MEMORY;
603
604 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
605 for (unsigned int i = 0; i < nb_entries; ++i)
606 {
607 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
608 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
609 }
610 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
611 acpiPhyscpy (s, addr, xsdt, size);
612 RTMemFree (xsdt);
613 return VINF_SUCCESS;
614}
615
616/* Root System Description Pointer (RSDP) */
617static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
618{
619 memset(rsdp, 0, sizeof(*rsdp));
620
621 /* ACPI 1.0 part (RSDT */
622 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
623 memcpy(rsdp->au8OemId, "VBOX ", 6);
624 rsdp->u8Revision = ACPI_REVISION;
625 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
626 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
627
628 /* ACPI 2.0 part (XSDT) */
629 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
630 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
631 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
632}
633
634/* Multiple APIC Description Table. */
635/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
636/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
637static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
638{
639 ACPITBLMADT madt;
640
641 /* Don't call this function if u8UseIOApic==false! */
642 Assert(s->u8UseIOApic);
643
644 memset(&madt, 0, sizeof(madt));
645 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
646
647 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
648 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
649
650 madt.LApic.u8Type = 0;
651 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
652 madt.LApic.u8ProcId = 0;
653 madt.LApic.u8ApicId = 0;
654 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
655
656 madt.IOApic.u8Type = 1;
657 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
658 madt.IOApic.u8IOApicId = 0;
659 madt.IOApic.u8Reserved = 0;
660 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
661 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
662
663 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
664 acpiPhyscpy (s, addr, &madt, sizeof(madt));
665}
666
667/* SCI IRQ */
668DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
669{
670 if (s->pm1a_ctl & SCI_EN)
671 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
672}
673
674DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
675{
676 return en & ~(RSR_EN | IGN_EN);
677}
678
679DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
680{
681 return sts & ~(RSR_STS | IGN_STS);
682}
683
684DECLINLINE(int) pm1a_level (ACPIState *s)
685{
686 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
687}
688
689DECLINLINE(int) gpe0_level (ACPIState *s)
690{
691 return (s->gpe0_en & s->gpe0_sts) != 0;
692}
693
694static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
695{
696 int old_level, new_level;
697
698 if (gpe0_level (s))
699 return;
700
701 old_level = pm1a_level (s);
702 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
703
704 s->pm1a_en = en;
705 s->pm1a_sts = sts;
706
707 if (new_level != old_level)
708 acpiSetIrq (s, new_level);
709}
710
711static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
712{
713 int old_level, new_level;
714
715 if (pm1a_level (s))
716 return;
717
718 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
719 new_level = (en & sts) != 0;
720
721 s->gpe0_en = en;
722 s->gpe0_sts = sts;
723
724 if (new_level != old_level)
725 acpiSetIrq (s, new_level);
726}
727
728static int acpiPowerDown (ACPIState *s)
729{
730 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
731 if (VBOX_FAILURE (rc))
732 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
733 return rc;
734}
735
736/** Converts a ACPI port interface pointer to an ACPI state pointer. */
737#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
738
739/**
740 * Send an ACPI power off event.
741 *
742 * @returns VBox status code
743 * @param pInterface Pointer to the interface structure containing the called function pointer.
744 */
745static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
746{
747 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
748 s->fPowerButtonHandled = false;
749 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
750 return VINF_SUCCESS;
751}
752
753static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
754{
755 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
756 *pfHandled = s->fPowerButtonHandled;
757 return VINF_SUCCESS;
758}
759
760/**
761 * Send an ACPI sleep button event.
762 *
763 * @returns VBox status code
764 * @param pInterface Pointer to the interface structure containing the called function pointer.
765 */
766static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
767{
768 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
769 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
770 return VINF_SUCCESS;
771}
772
773/* PM1a_EVT_BLK enable */
774static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
775{
776 uint16_t val = s->pm1a_en;
777 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
778 return val;
779}
780
781static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
782{
783 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
784 val &= ~(RSR_EN | IGN_EN);
785 update_pm1a (s, s->pm1a_sts, val);
786}
787
788/* PM1a_EVT_BLK status */
789static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
790{
791 uint16_t val = s->pm1a_sts;
792 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
793 return val;
794}
795
796static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
797{
798 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
799 if (val & PWRBTN_STS)
800 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
801 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
802 update_pm1a (s, val, s->pm1a_en);
803}
804
805/* PM1a_CTL_BLK */
806static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
807{
808 uint16_t val = s->pm1a_ctl;
809 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
810 return val;
811}
812
813static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
814{
815 uint32_t uSleepState;
816
817 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
818 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
819
820 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
821 if (uSleepState != s->uSleepState)
822 {
823 s->uSleepState = uSleepState;
824 switch (uSleepState)
825 {
826 case 0x00: /* S0 */
827 break;
828 case 0x05: /* S5 */
829 LogRel (("Entering S5 (power down)\n"));
830 return acpiPowerDown (s);
831 default:
832 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
833 break;
834 }
835 }
836 return VINF_SUCCESS;
837}
838
839/* GPE0_BLK */
840static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
841{
842 uint8_t val = s->gpe0_en;
843 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
844 return val;
845}
846
847static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
848{
849 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
850 update_gpe0 (s, s->gpe0_sts, val);
851}
852
853static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
854{
855 uint8_t val = s->gpe0_sts;
856 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
857 return val;
858}
859
860static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
861{
862 val = s->gpe0_sts & ~val;
863 update_gpe0 (s, val, s->gpe0_en);
864 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
865}
866
867static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
868{
869 int rc = VINF_SUCCESS;
870
871 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
872 if (val == ACPI_RESET_REG_VAL)
873 {
874# ifndef IN_RING3
875 rc = VINF_IOM_HC_IOPORT_WRITE;
876# else /* IN_RING3 */
877 rc = PDMDevHlpVMReset(s->pDevIns);
878# endif /* !IN_RING3 */
879 }
880 return rc;
881}
882
883/* SMI */
884static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
885{
886 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
887 if (val == ACPI_ENABLE)
888 s->pm1a_ctl |= SCI_EN;
889 else if (val == ACPI_DISABLE)
890 s->pm1a_ctl &= ~SCI_EN;
891 else
892 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
893}
894
895static uint32_t find_rsdp_space (void)
896{
897 return 0xe0000;
898}
899
900static void acpiPMTimerReset (ACPIState *s)
901{
902 uint64_t interval, freq;
903
904 freq = TMTimerGetFreq (s->CTXSUFF(ts));
905 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
906 Log (("interval = %RU64\n", interval));
907 TMTimerSet (s->CTXSUFF(ts), TMTimerGet (s->CTXSUFF(ts)) + interval);
908}
909
910static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
911{
912 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
913
914 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
915 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
916 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
917
918 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
919 acpiPMTimerReset (s);
920}
921
922/**
923 * _BST method.
924 */
925static void acpiFetchBatteryStatus (ACPIState *s)
926{
927 uint32_t *p = s->au8BatteryInfo;
928 bool fPresent; /* battery present? */
929 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
930 PDMACPIBATSTATE hostBatteryState; /* bitfield */
931 uint32_t hostPresentRate; /* 0..1000 */
932 int rc;
933
934 if (!s->pDrv)
935 return;
936 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
937 &hostBatteryState, &hostPresentRate);
938 AssertRC (rc);
939
940 /* default values */
941 p[BAT_STATUS_STATE] = hostBatteryState;
942 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
943 : hostPresentRate * 50; /* mW */
944 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
945 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
946
947 /* did we get a valid battery state? */
948 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
949 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
950 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
951 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
952}
953
954/**
955 * _BIF method.
956 */
957static void acpiFetchBatteryInfo (ACPIState *s)
958{
959 uint32_t *p = s->au8BatteryInfo;
960
961 p[BAT_INFO_UNITS] = 0; /* mWh */
962 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
963 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
964 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
965 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
966 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
967 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
968 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
969 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
970}
971
972/**
973 * _STA method.
974 */
975static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
976{
977 bool fPresent; /* battery present? */
978 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
979 PDMACPIBATSTATE hostBatteryState; /* bitfield */
980 uint32_t hostPresentRate; /* 0..1000 */
981 int rc;
982
983 if (!s->pDrv)
984 return 0;
985 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
986 &hostBatteryState, &hostPresentRate);
987 AssertRC (rc);
988
989 return fPresent
990 ? STA_DEVICE_PRESENT_MASK /* present */
991 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
992 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
993 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
994 | STA_BATTERY_PRESENT_MASK /* battery is present */
995 : 0; /* device not present */
996}
997
998static uint32_t acpiGetPowerSource (ACPIState *s)
999{
1000 PDMACPIPOWERSOURCE ps;
1001
1002 /* query the current power source from the host driver */
1003 if (!s->pDrv)
1004 return AC_ONLINE;
1005 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1006 AssertRC (rc);
1007 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1008}
1009
1010IO_WRITE_PROTO (acpiBatIndexWrite)
1011{
1012 ACPIState *s = (ACPIState *)pvUser;
1013
1014 switch (cb)
1015 {
1016 case 4:
1017 u32 >>= s->u8IndexShift;
1018 /* see comment at the declaration of u8IndexShift */
1019 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1020 {
1021 s->u8IndexShift = 2;
1022 u32 >>= 2;
1023 }
1024 Assert (u32 < BAT_INDEX_LAST);
1025 s->uBatteryIndex = u32;
1026 break;
1027 default:
1028 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1029 break;
1030 }
1031 return VINF_SUCCESS;
1032}
1033
1034IO_READ_PROTO (acpiBatDataRead)
1035{
1036 ACPIState *s = (ACPIState *)pvUser;
1037
1038 switch (cb)
1039 {
1040 case 4:
1041 switch (s->uBatteryIndex)
1042 {
1043 case BAT_STATUS_STATE:
1044 acpiFetchBatteryStatus(s);
1045 case BAT_STATUS_PRESENT_RATE:
1046 case BAT_STATUS_REMAINING_CAPACITY:
1047 case BAT_STATUS_PRESENT_VOLTAGE:
1048 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1049 break;
1050
1051 case BAT_INFO_UNITS:
1052 acpiFetchBatteryInfo(s);
1053 case BAT_INFO_DESIGN_CAPACITY:
1054 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1055 case BAT_INFO_TECHNOLOGY:
1056 case BAT_INFO_DESIGN_VOLTAGE:
1057 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1058 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1059 case BAT_INFO_CAPACITY_GRANULARITY_1:
1060 case BAT_INFO_CAPACITY_GRANULARITY_2:
1061 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1062 break;
1063
1064 case BAT_DEVICE_STATUS:
1065 *pu32 = acpiGetBatteryDeviceStatus(s);
1066 break;
1067
1068 case BAT_POWER_SOURCE:
1069 *pu32 = acpiGetPowerSource(s);
1070 break;
1071
1072 default:
1073 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1074 break;
1075 }
1076 break;
1077 default:
1078 return VERR_IOM_IOPORT_UNUSED;
1079 }
1080 return VINF_SUCCESS;
1081}
1082
1083IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1084{
1085 ACPIState *s = (ACPIState *)pvUser;
1086
1087 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1088 switch (cb) {
1089 case 4:
1090 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1091 s->uSystemInfoIndex = u32;
1092 else
1093 {
1094 u32 >>= s->u8IndexShift;
1095 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1096 s->uSystemInfoIndex = u32;
1097 }
1098 break;
1099
1100 default:
1101 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1102 break;
1103 }
1104 return VINF_SUCCESS;
1105}
1106
1107IO_READ_PROTO (acpiSysInfoDataRead)
1108{
1109 ACPIState *s = (ACPIState *)pvUser;
1110
1111 switch (cb)
1112 {
1113 case 4:
1114 switch (s->uSystemInfoIndex)
1115 {
1116 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1117 *pu32 = s->u64RamSize;
1118 break;
1119
1120 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1121 *pu32 = s->u8UseIOApic;
1122 break;
1123
1124 default:
1125 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1126 break;
1127 }
1128 break;
1129
1130 default:
1131 return VERR_IOM_IOPORT_UNUSED;
1132 }
1133
1134 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1135 return VINF_SUCCESS;
1136}
1137
1138IO_WRITE_PROTO (acpiSysInfoDataWrite)
1139{
1140 ACPIState *s = (ACPIState *)pvUser;
1141
1142 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1143
1144 if (cb == 4 && u32 == 0xbadc0de)
1145 {
1146 switch (s->uSystemInfoIndex)
1147 {
1148 case SYSTEM_INFO_INDEX_INVALID:
1149 s->u8IndexShift = 0;
1150 break;
1151
1152 case SYSTEM_INFO_INDEX_VALID:
1153 s->u8IndexShift = 2;
1154 break;
1155
1156 default:
1157 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1158 Port, cb, u32, s->uSystemInfoIndex));
1159 break;
1160 }
1161 }
1162 else
1163 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1164 return VINF_SUCCESS;
1165}
1166
1167/* IO Helpers */
1168IO_READ_PROTO (acpiPm1aEnRead)
1169{
1170 switch (cb)
1171 {
1172 case 2:
1173 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1174 break;
1175 default:
1176 return VERR_IOM_IOPORT_UNUSED;
1177 }
1178 return VINF_SUCCESS;
1179}
1180
1181IO_READ_PROTO (acpiPm1aStsRead)
1182{
1183 switch (cb)
1184 {
1185 case 2:
1186 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1187 break;
1188 default:
1189 return VERR_IOM_IOPORT_UNUSED;
1190 }
1191 return VINF_SUCCESS;
1192}
1193
1194IO_READ_PROTO (acpiPm1aCtlRead)
1195{
1196 switch (cb)
1197 {
1198 case 2:
1199 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1200 break;
1201 default:
1202 return VERR_IOM_IOPORT_UNUSED;
1203 }
1204 return VINF_SUCCESS;
1205}
1206
1207IO_WRITE_PROTO (acpiPM1aEnWrite)
1208{
1209 switch (cb)
1210 {
1211 case 2:
1212 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1213 break;
1214 default:
1215 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1216 break;
1217 }
1218 return VINF_SUCCESS;
1219}
1220
1221IO_WRITE_PROTO (acpiPM1aStsWrite)
1222{
1223 switch (cb)
1224 {
1225 case 2:
1226 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1227 break;
1228 default:
1229 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1230 break;
1231 }
1232 return VINF_SUCCESS;
1233}
1234
1235IO_WRITE_PROTO (acpiPM1aCtlWrite)
1236{
1237 switch (cb)
1238 {
1239 case 2:
1240 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1241 default:
1242 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1243 break;
1244 }
1245 return VINF_SUCCESS;
1246}
1247
1248#endif /* IN_RING3 */
1249
1250/**
1251 * PMTMR readable from host/guest.
1252 */
1253IO_READ_PROTO (acpiPMTmrRead)
1254{
1255 if (cb == 4)
1256 {
1257 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1258 int64_t now = TMTimerGet (s->CTXSUFF(ts));
1259 int64_t elapsed = now - s->pm_timer_initial;
1260
1261 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTXSUFF(ts)));
1262 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1263 return VINF_SUCCESS;
1264 }
1265 return VERR_IOM_IOPORT_UNUSED;
1266}
1267
1268#ifdef IN_RING3
1269
1270IO_READ_PROTO (acpiGpe0StsRead)
1271{
1272 switch (cb)
1273 {
1274 case 1:
1275 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1276 break;
1277 default:
1278 return VERR_IOM_IOPORT_UNUSED;
1279 }
1280 return VINF_SUCCESS;
1281}
1282
1283IO_READ_PROTO (acpiGpe0EnRead)
1284{
1285 switch (cb)
1286 {
1287 case 1:
1288 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1289 break;
1290 default:
1291 return VERR_IOM_IOPORT_UNUSED;
1292 }
1293 return VINF_SUCCESS;
1294}
1295
1296IO_WRITE_PROTO (acpiGpe0StsWrite)
1297{
1298 switch (cb)
1299 {
1300 case 1:
1301 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1302 break;
1303 default:
1304 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1305 break;
1306 }
1307 return VINF_SUCCESS;
1308}
1309
1310IO_WRITE_PROTO (acpiGpe0EnWrite)
1311{
1312 switch (cb)
1313 {
1314 case 1:
1315 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1316 break;
1317 default:
1318 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1319 break;
1320 }
1321 return VINF_SUCCESS;
1322}
1323
1324IO_WRITE_PROTO (acpiSmiWrite)
1325{
1326 switch (cb)
1327 {
1328 case 1:
1329 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1330 break;
1331 default:
1332 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1333 break;
1334 }
1335 return VINF_SUCCESS;
1336}
1337
1338IO_WRITE_PROTO (acpiResetWrite)
1339{
1340 switch (cb)
1341 {
1342 case 1:
1343 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1344 default:
1345 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1346 break;
1347 }
1348 return VINF_SUCCESS;
1349}
1350
1351#ifdef DEBUG_ACPI
1352
1353IO_WRITE_PROTO (acpiDhexWrite)
1354{
1355 switch (cb)
1356 {
1357 case 1:
1358 Log (("%#x\n", u32 & 0xff));
1359 break;
1360 case 2:
1361 Log (("%#6x\n", u32 & 0xffff));
1362 case 4:
1363 Log (("%#10x\n", u32));
1364 break;
1365 default:
1366 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1367 break;
1368 }
1369 return VINF_SUCCESS;
1370}
1371
1372IO_WRITE_PROTO (acpiDchrWrite)
1373{
1374 switch (cb)
1375 {
1376 case 1:
1377 Log (("%c", u32 & 0xff));
1378 break;
1379 default:
1380 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1381 break;
1382 }
1383 return VINF_SUCCESS;
1384}
1385
1386#endif /* DEBUG_ACPI */
1387
1388
1389/**
1390 * Saved state structure description.
1391 */
1392static const SSMFIELD g_AcpiSavedStateFields[] =
1393{
1394 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1395 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1396 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1397 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1398 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1399 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1400 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1401 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1402 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1403 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1404 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1405 SSMFIELD_ENTRY (ACPIState, uSleepState),
1406 SSMFIELD_ENTRY_TERM ()
1407};
1408
1409static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1410{
1411 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1412 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1413}
1414
1415static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1416 uint32_t u32Version)
1417{
1418 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1419 int rc;
1420
1421 if (u32Version != 4)
1422 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1423
1424 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1425 if (VBOX_SUCCESS (rc))
1426 {
1427 acpiFetchBatteryStatus (s);
1428 acpiFetchBatteryInfo (s);
1429 acpiPMTimerReset (s);
1430 }
1431 return rc;
1432}
1433
1434/**
1435 * Queries an interface to the driver.
1436 *
1437 * @returns Pointer to interface.
1438 * @returns NULL if the interface was not supported by the driver.
1439 * @param pInterface Pointer to this interface structure.
1440 * @param enmInterface The requested interface identification.
1441 * @thread Any thread.
1442 */
1443static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1444{
1445 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1446 switch (enmInterface)
1447 {
1448 case PDMINTERFACE_BASE:
1449 return &pData->IBase;
1450 case PDMINTERFACE_ACPI_PORT:
1451 return &pData->IACPIPort;
1452 default:
1453 return NULL;
1454 }
1455}
1456
1457/**
1458 * Create the ACPI tables.
1459 */
1460static int acpiPlantTables (ACPIState *s)
1461{
1462 int rc;
1463 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1464 uint32_t addend = 0;
1465 RTGCPHYS32 rsdt_addrs[4];
1466 uint32_t cAddr;
1467 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1468 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1469
1470 cAddr = 1; /* FADT */
1471 if (s->u8UseIOApic)
1472 cAddr++; /* MADT */
1473
1474 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1475 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1476
1477 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1478 if (VBOX_FAILURE (rc))
1479 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1480 N_("Configuration error: Querying "
1481 "\"RamSize\" as integer failed"));
1482
1483 if (s->u64RamSize > (0xffffffff - 0x10000))
1484 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1485 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1486 "value is 4095MB"));
1487
1488 rsdt_addr = 0;
1489 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1490 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1491 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1492 if (s->u8UseIOApic)
1493 {
1494 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1495 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1496 }
1497 else
1498 {
1499 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1500 }
1501
1502 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1503 if (last_addr > 0x10000)
1504 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1505 N_("Error: ACPI tables > 64KB"));
1506
1507 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1508 addend = (uint32_t) s->u64RamSize - 0x10000;
1509 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1510 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1511 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1512 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1513 acpiSetupDSDT (s, dsdt_addr + addend);
1514 acpiSetupFACS (s, facs_addr + addend);
1515 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1516
1517 rsdt_addrs[0] = fadt_addr + addend;
1518 if (s->u8UseIOApic)
1519 {
1520 acpiSetupMADT (s, apic_addr + addend);
1521 rsdt_addrs[1] = apic_addr + addend;
1522 }
1523
1524 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1525 if (VBOX_FAILURE(rc))
1526 return rc;
1527 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1528}
1529
1530/**
1531 * Construct a device instance for a VM.
1532 *
1533 * @returns VBox status.
1534 * @param pDevIns The device instance data.
1535 * If the registration structure is needed, pDevIns->pDevReg points to it.
1536 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1537 * The device number is also found in pDevIns->iInstance, but since it's
1538 * likely to be freqently used PDM passes it as parameter.
1539 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1540 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1541 * iInstance it's expected to be used a bit in this function.
1542 */
1543static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1544{
1545 int rc;
1546 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1547 uint32_t rsdp_addr;
1548 PCIDevice *dev;
1549 bool fGCEnabled;
1550 bool fR0Enabled;
1551
1552 /* Validate and read the configuration. */
1553 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0"))
1554 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1555 N_("Configuration error: Invalid config key for ACPI device"));
1556
1557 s->pDevIns = pDevIns;
1558
1559 /* query whether we are supposed to present an IOAPIC */
1560 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1561 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1562 s->u8UseIOApic = 1;
1563 else if (VBOX_FAILURE (rc))
1564 return PDMDEV_SET_ERROR(pDevIns, rc,
1565 N_("Configuration error: Failed to read \"IOAPIC\""));
1566
1567 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1568 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1569 fGCEnabled = true;
1570 else if (VBOX_FAILURE (rc))
1571 return PDMDEV_SET_ERROR(pDevIns, rc,
1572 N_("Configuration error: Failed to read \"GCEnabled\""));
1573
1574 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1575 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1576 fR0Enabled = true;
1577 else if (VBOX_FAILURE(rc))
1578 return PDMDEV_SET_ERROR(pDevIns, rc,
1579 N_("configuration error: failed to read R0Enabled as boolean"));
1580
1581 /* */
1582 rsdp_addr = find_rsdp_space ();
1583 if (!rsdp_addr)
1584 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1585 N_("Can not find space for RSDP. ACPI is disabled"));
1586
1587 rc = acpiPlantTables (s);
1588 if (VBOX_FAILURE (rc))
1589 return rc;
1590
1591 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1592 if (VBOX_FAILURE (rc))
1593 return rc;
1594
1595#define R(addr, cnt, writer, reader, description) \
1596 do { \
1597 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1598 NULL, NULL, description); \
1599 if (VBOX_FAILURE (rc)) \
1600 return rc; \
1601 } while (0)
1602#define L (GPE0_BLK_LEN / 2)
1603
1604 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1605 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1606 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1607 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1608 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1609#ifdef DEBUG_ACPI
1610 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1611 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1612#endif
1613 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1614 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1615 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1616 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1617 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1618 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1619 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1620#undef L
1621#undef R
1622
1623 /* register GC stuff */
1624 if (fGCEnabled)
1625 {
1626 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1627 NULL, NULL, "ACPI PM Timer");
1628 AssertRCReturn(rc, rc);
1629 }
1630
1631 /* register R0 stuff */
1632 if (fR0Enabled)
1633 {
1634 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1635 NULL, NULL, "ACPI PM Timer");
1636 AssertRCReturn(rc, rc);
1637 }
1638
1639 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsHC);
1640 if (VBOX_FAILURE(rc))
1641 {
1642 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1643 return rc;
1644 }
1645
1646 s->tsGC = TMTimerGCPtr (s->tsHC);
1647 s->pm_timer_initial = TMTimerGet (s->tsHC);
1648 acpiPMTimerReset (s);
1649
1650 dev = &s->dev;
1651 dev->config[0x00] = 0x86;
1652 dev->config[0x01] = 0x80;
1653
1654 dev->config[0x02] = 0x13;
1655 dev->config[0x03] = 0x71;
1656
1657 dev->config[0x04] = 0x01;
1658 dev->config[0x05] = 0x00;
1659
1660 dev->config[0x06] = 0x80;
1661 dev->config[0x07] = 0x02;
1662 dev->config[0x08] = 0x08;
1663 dev->config[0x09] = 0x00;
1664
1665 dev->config[0x0a] = 0x80;
1666 dev->config[0x0b] = 0x06;
1667
1668 dev->config[0x0e] = 0x80;
1669 dev->config[0x0f] = 0x00;
1670
1671#if 0 /* The ACPI controller usually has no subsystem ID. */
1672 dev->config[0x2c] = 0x86;
1673 dev->config[0x2d] = 0x80;
1674 dev->config[0x2e] = 0x00;
1675 dev->config[0x2f] = 0x00;
1676#endif
1677 dev->config[0x3c] = SCI_INT;
1678
1679 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1680 if (VBOX_FAILURE (rc))
1681 return rc;
1682
1683 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1684 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1685 if (VBOX_FAILURE(rc))
1686 return rc;
1687
1688 /*
1689 * Interfaces
1690 */
1691 /* IBase */
1692 s->IBase.pfnQueryInterface = acpiQueryInterface;
1693 /* IACPIPort */
1694 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1695 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1696 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1697
1698 /*
1699 * Get the corresponding connector interface
1700 */
1701 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1702 if (VBOX_SUCCESS (rc))
1703 {
1704 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1705 PDMINTERFACE_ACPI_CONNECTOR);
1706 if (!s->pDrv)
1707 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1708 N_("LUN #0 doesn't have an ACPI connector interface"));
1709 }
1710 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1711 {
1712 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1713 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1714 rc = VINF_SUCCESS;
1715 }
1716 else
1717 return PDMDEV_SET_ERROR(pDevIns, rc,
1718 N_("Failed to attach LUN #0"));
1719
1720 return rc;
1721}
1722
1723/**
1724 * Relocates the GC pointer members.
1725 */
1726static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1727{
1728 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1729 s->tsGC = TMTimerGCPtr (s->tsHC);
1730}
1731
1732static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1733{
1734 ACPIState *s = PDMINS2DATA (pDevIns, ACPIState *);
1735
1736 s->pm1a_en = 0;
1737 s->pm1a_sts = 0;
1738 s->pm1a_ctl = 0;
1739 s->pm_timer_initial = TMTimerGet (s->CTXSUFF(ts));
1740 acpiPMTimerReset(s);
1741 s->uBatteryIndex = 0;
1742 s->uSystemInfoIndex = 0;
1743 s->gpe0_en = 0;
1744 s->gpe0_sts = 0;
1745 s->uSleepState = 0;
1746
1747 acpiPlantTables(s);
1748}
1749
1750/**
1751 * The device registration structure.
1752 */
1753const PDMDEVREG g_DeviceACPI =
1754{
1755 /* u32Version */
1756 PDM_DEVREG_VERSION,
1757 /* szDeviceName */
1758 "acpi",
1759 /* szGCMod */
1760 "VBoxDDGC.gc",
1761 /* szR0Mod */
1762 "VBoxDDR0.r0",
1763 /* pszDescription */
1764 "Advanced Configuration and Power Interface",
1765 /* fFlags */
1766 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1767 /* fClass */
1768 PDM_DEVREG_CLASS_ACPI,
1769 /* cMaxInstances */
1770 ~0,
1771 /* cbInstance */
1772 sizeof(ACPIState),
1773 /* pfnConstruct */
1774 acpiConstruct,
1775 /* pfnDestruct */
1776 NULL,
1777 /* pfnRelocate */
1778 acpiRelocate,
1779 /* pfnIOCtl */
1780 NULL,
1781 /* pfnPowerOn */
1782 NULL,
1783 /* pfnReset */
1784 acpiReset,
1785 /* pfnSuspend */
1786 NULL,
1787 /* pfnResume */
1788 NULL,
1789 /* pfnAttach */
1790 NULL,
1791 /* pfnDetach */
1792 NULL,
1793 /* pfnQueryInterface. */
1794 NULL
1795};
1796
1797#endif /* IN_RING3 */
1798#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1799
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