VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 11165

Last change on this file since 11165 was 11165, checked in by vboxsync, 16 years ago

#1865: ACPI.
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1/* $Id: DevACPI.cpp 11165 2008-08-06 00:19:54Z vboxsync $ */
2/** @file
3 * Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23
24#include <VBox/pdmdev.h>
25#include <VBox/log.h>
26#include <iprt/assert.h>
27#include <iprt/asm.h>
28#ifdef IN_RING3
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31#endif /* IN_RING3 */
32
33#include "Builtins.h"
34
35#ifdef LOG_ENABLED
36#define DEBUG_ACPI
37#endif
38
39/* the compiled DSL */
40#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
41#include <vboxaml.hex>
42#endif /* !IN_RING3 */
43
44#define IO_READ_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t *pu32, unsigned cb)
47
48#define IO_WRITE_PROTO(name) \
49 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
50 RTIOPORT Port, uint32_t u32, unsigned cb)
51
52#define DEBUG_HEX 0x3000
53#define DEBUG_CHR 0x3001
54
55#define PM_TMR_FREQ 3579545
56#define PM1a_EVT_BLK 0x00004000
57#define PM1b_EVT_BLK 0x00000000 /**< not supported */
58#define PM1a_CTL_BLK 0x00004004
59#define PM1b_CTL_BLK 0x00000000 /**< not supported */
60#define PM2_CTL_BLK 0x00000000 /**< not supported */
61#define PM_TMR_BLK 0x00004008
62#define GPE0_BLK 0x00004020
63#define GPE1_BLK 0x00000000 /**< not supported */
64#define BAT_INDEX 0x00004040
65#define BAT_DATA 0x00004044
66#define SYSI_INDEX 0x00004048
67#define SYSI_DATA 0x0000404c
68#define ACPI_RESET_BLK 0x00004050
69#define FDC_STATUS 0x00004054
70
71/* PM1x status register bits */
72#define TMR_STS RT_BIT(0)
73#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
74#define BM_STS RT_BIT(4)
75#define GBL_STS RT_BIT(5)
76#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
77#define PWRBTN_STS RT_BIT(8)
78#define SLPBTN_STS RT_BIT(9)
79#define RTC_STS RT_BIT(10)
80#define IGN_STS RT_BIT(11)
81#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
82#define WAK_STS RT_BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN RT_BIT(0)
87#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
88#define GBL_EN RT_BIT(5)
89#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
90#define PWRBTN_EN RT_BIT(8)
91#define SLPBTN_EN RT_BIT(9)
92#define RTC_EN RT_BIT(10)
93#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN RT_BIT(0)
99#define BM_RLD RT_BIT(1)
100#define GBL_RLS RT_BIT(2)
101#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
102#define IGN_CNT RT_BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN RT_BIT(13)
106#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_LAST = 2,
136 SYSTEM_INFO_INDEX_INVALID = 0x80,
137 SYSTEM_INFO_INDEX_VALID = 0x200
138};
139
140#define AC_OFFLINE 0
141#define AC_ONLINE 1
142
143#define BAT_TECH_PRIMARY 1
144#define BAT_TECH_SECONDARY 2
145
146#define BAT_STATUS_DISCHARGING_MASK RT_BIT(0)
147#define BAT_STATUS_CHARGING_MASK RT_BIT(1)
148#define BAT_STATUS_CRITICAL_MASK RT_BIT(2)
149
150#define STA_DEVICE_PRESENT_MASK RT_BIT(0)
151#define STA_DEVICE_ENABLED_MASK RT_BIT(1)
152#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2)
153#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3)
154#define STA_BATTERY_PRESENT_MASK RT_BIT(4)
155
156struct ACPIState
157{
158 PCIDevice dev;
159 uint16_t pm1a_en;
160 uint16_t pm1a_sts;
161 uint16_t pm1a_ctl;
162 uint16_t Alignment0;
163 int64_t pm_timer_initial;
164 PTMTIMERR3 tsR3;
165 PTMTIMERR0 tsR0;
166 PTMTIMERRC tsRC;
167
168 uint32_t gpe0_en;
169 uint32_t gpe0_sts;
170
171 unsigned int uBatteryIndex;
172 uint32_t au8BatteryInfo[13];
173
174 unsigned int uSystemInfoIndex;
175 uint64_t u64RamSize;
176
177 /** Current ACPI S* state. We support S0 and S5 */
178 uint32_t uSleepState;
179 uint8_t au8RSDPPage[0x1000];
180 /** This is a workaround for incorrect index field handling by Intels ACPICA.
181 * The system info _INI method writes to offset 0x200. We either observe a
182 * write request to index 0x80 (in that case we don't change the index) or a
183 * write request to offset 0x200 (in that case we divide the index value by
184 * 4. Note that the _STA method is sometimes called prior to the _INI method
185 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
186 * acpiBatIndexWrite() for handling this. */
187 uint8_t u8IndexShift;
188 uint8_t u8UseIOApic;
189 uint8_t u8UseFdc;
190 bool fPowerButtonHandled;
191
192 /** ACPI port base interface. */
193 PDMIBASE IBase;
194 /** ACPI port interface. */
195 PDMIACPIPORT IACPIPort;
196 /** Pointer to the device instance. */
197 PPDMDEVINSR3 pDevIns;
198 /** Pointer to the driver base interface */
199 R3PTRTYPE(PPDMIBASE) pDrvBase;
200 /** Pointer to the driver connector interface */
201 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
202};
203
204#pragma pack(1)
205
206/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
207struct ACPIGENADDR
208{
209 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
210 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
211 uint8_t u8RegisterBitOffset; /**< bit offset of register */
212 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
213 uint64_t u64Address; /**< 64-bit address of register */
214};
215AssertCompileSize(ACPIGENADDR, 12);
216
217/** Root System Description Pointer */
218struct ACPITBLRSDP
219{
220 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
221 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
222 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
223 uint8_t u8Revision; /**< revision number, currently 2 */
224#define ACPI_REVISION 2 /**< ACPI 3.0 */
225 uint32_t u32RSDT; /**< phys addr of RSDT */
226 uint32_t u32Length; /**< bytes of this table */
227 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
228 uint8_t u8ExtChecksum; /**< checksum of entire table */
229 uint8_t u8Reserved[3]; /**< reserved */
230};
231AssertCompileSize(ACPITBLRSDP, 36);
232
233/** System Description Table Header */
234struct ACPITBLHEADER
235{
236 uint8_t au8Signature[4]; /**< table identifier */
237 uint32_t u32Length; /**< length of the table including header */
238 uint8_t u8Revision; /**< revision number */
239 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
240 uint8_t au8OemId[6]; /**< OEM-supplied string */
241 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
242 uint32_t u32OemRevision; /**< OEM-supplied revision number */
243 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
244 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
245};
246AssertCompileSize(ACPITBLHEADER, 36);
247
248/** Root System Description Table */
249struct ACPITBLRSDT
250{
251 ACPITBLHEADER header;
252 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
253};
254AssertCompileSize(ACPITBLRSDT, 40);
255
256/** Extended System Description Table */
257struct ACPITBLXSDT
258{
259 ACPITBLHEADER header;
260 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
261};
262AssertCompileSize(ACPITBLXSDT, 44);
263
264/** Fixed ACPI Description Table */
265struct ACPITBLFADT
266{
267 ACPITBLHEADER header;
268 uint32_t u32FACS; /**< phys. address of FACS */
269 uint32_t u32DSDT; /**< phys. address of DSDT */
270 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
271#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
272#define INT_MODEL_MULTIPLE_APIC 2
273 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
274 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
275#define SCI_INT 9
276 uint32_t u32SMICmd; /**< system port address of SMI command port */
277#define SMI_CMD 0x0000442e
278 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
279#define ACPI_ENABLE 0xa1
280 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
281#define ACPI_DISABLE 0xa0
282 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
283 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
284 state control responsibility */
285 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
286 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
287 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
288 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
289 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
290 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
291 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
292 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
293 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
294 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
295 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
296 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
297 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
298#define GPE0_BLK_LEN 2
299 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
300#define GPE1_BLK_LEN 0
301 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
302#define GPE1_BASE 0
303 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
304 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
305#define P_LVL2_LAT 101 /**< C2 state not supported */
306 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
307#define P_LVL3_LAT 1001 /**< C3 state not supported */
308 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
309 lines from any processors memory caches */
310#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
311 uint16_t u16FlushStride; /**< cache line width */
312#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
313 uint8_t u8DutyOffset;
314 uint8_t u8DutyWidth;
315 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
316 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
317 uint8_t u8Century; /**< RTC CMOS RAM index of century */
318 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
319#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
320 (COM too?) */
321#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
322#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
323 uint8_t u8Must0_0; /**< must be 0 */
324 uint32_t u32Flags; /**< fixed feature flags */
325#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
326#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
327#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
328#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
329#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
330#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
331#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
332#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
333#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
334#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
335#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
336#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
337#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
338#define FADT_FL_CPU_SW_SLP RT_BIT(13)
339#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
340#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
341#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
342#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
343#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
344#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
345 ACPIGENADDR ResetReg; /**< ext addr of reset register */
346 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
347#define ACPI_RESET_REG_VAL 0x10
348 uint8_t au8Must0_1[3]; /**< must be 0 */
349 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
350 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
351 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
352 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
353 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
354 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
355 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
356 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
357 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
358 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
359};
360AssertCompileSize(ACPITBLFADT, 244);
361
362/** Firmware ACPI Control Structure */
363struct ACPITBLFACS
364{
365 uint8_t au8Signature[4]; /**< 'FACS' */
366 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
367 uint32_t u32HWSignature; /**< systems HW signature at last boot */
368 uint32_t u32FWVector; /**< address of waking vector */
369 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
370 uint32_t u32Flags; /**< FACS flags */
371 uint64_t u64X_FWVector; /**< 64-bit waking vector */
372 uint8_t u8Version; /**< version of this table */
373 uint8_t au8Reserved[31]; /**< zero */
374};
375AssertCompileSize(ACPITBLFACS, 64);
376
377/** Processor Local APIC Structure */
378struct ACPITBLLAPIC
379{
380 uint8_t u8Type; /**< 0 = LAPIC */
381 uint8_t u8Length; /**< 8 */
382 uint8_t u8ProcId; /**< processor ID */
383 uint8_t u8ApicId; /**< local APIC ID */
384 uint32_t u32Flags; /**< Flags */
385#define LAPIC_ENABLED 0x1
386};
387AssertCompileSize(ACPITBLLAPIC, 8);
388
389/** I/O APIC Structure */
390struct ACPITBLIOAPIC
391{
392 uint8_t u8Type; /**< 1 == I/O APIC */
393 uint8_t u8Length; /**< 12 */
394 uint8_t u8IOApicId; /**< I/O APIC ID */
395 uint8_t u8Reserved; /**< 0 */
396 uint32_t u32Address; /**< phys address to access I/O APIC */
397 uint32_t u32GSIB; /**< global system interrupt number to start */
398};
399AssertCompileSize(ACPITBLIOAPIC, 12);
400
401/** Multiple APIC Description Table */
402struct ACPITBLMADT
403{
404 ACPITBLHEADER header;
405 uint32_t u32LAPIC; /**< local APIC address */
406 uint32_t u32Flags; /**< Flags */
407#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
408 ACPITBLLAPIC LApic;
409 ACPITBLIOAPIC IOApic;
410};
411AssertCompileSize(ACPITBLMADT, 64);
412
413#pragma pack()
414
415
416#ifndef VBOX_DEVICE_STRUCT_TESTCASE
417__BEGIN_DECLS
418IO_READ_PROTO (acpiPMTmrRead);
419#ifdef IN_RING3
420IO_READ_PROTO (acpiPm1aEnRead);
421IO_WRITE_PROTO (acpiPM1aEnWrite);
422IO_READ_PROTO (acpiPm1aStsRead);
423IO_WRITE_PROTO (acpiPM1aStsWrite);
424IO_READ_PROTO (acpiPm1aCtlRead);
425IO_WRITE_PROTO (acpiPM1aCtlWrite);
426IO_WRITE_PROTO (acpiSmiWrite);
427IO_WRITE_PROTO (acpiBatIndexWrite);
428IO_READ_PROTO (acpiBatDataRead);
429IO_READ_PROTO (acpiFdcStatusRead);
430IO_READ_PROTO (acpiSysInfoDataRead);
431IO_WRITE_PROTO (acpiSysInfoDataWrite);
432IO_READ_PROTO (acpiGpe0EnRead);
433IO_WRITE_PROTO (acpiGpe0EnWrite);
434IO_READ_PROTO (acpiGpe0StsRead);
435IO_WRITE_PROTO (acpiGpe0StsWrite);
436IO_WRITE_PROTO (acpiResetWrite);
437# ifdef DEBUG_ACPI
438IO_WRITE_PROTO (acpiDhexWrite);
439IO_WRITE_PROTO (acpiDchrWrite);
440# endif
441#endif
442__END_DECLS
443
444#ifdef IN_RING3
445
446/* Simple acpiChecksum: all the bytes must add up to 0. */
447static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
448{
449 uint8_t sum = 0;
450 for (size_t i = 0; i < len; ++i)
451 sum += data[i];
452 return -sum;
453}
454
455static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
456 uint32_t u32Length, uint8_t u8Revision)
457{
458 memcpy(header->au8Signature, au8Signature, 4);
459 header->u32Length = RT_H2LE_U32(u32Length);
460 header->u8Revision = u8Revision;
461 memcpy(header->au8OemId, "VBOX ", 6);
462 memcpy(header->au8OemTabId, "VBOX", 4);
463 memcpy(header->au8OemTabId+4, au8Signature, 4);
464 header->u32OemRevision = RT_H2LE_U32(1);
465 memcpy(header->au8CreatorId, "ASL ", 4);
466 header->u32CreatorRev = RT_H2LE_U32(0x61);
467}
468
469static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
470 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
471 uint8_t u8AccessSize, uint64_t u64Address)
472{
473 g->u8AddressSpaceId = u8AddressSpaceId;
474 g->u8RegisterBitWidth = u8RegisterBitWidth;
475 g->u8RegisterBitOffset = u8RegisterBitOffset;
476 g->u8AccessSize = u8AccessSize;
477 g->u64Address = RT_H2LE_U64(u64Address);
478}
479
480static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
481{
482 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
483}
484
485/* Differentiated System Description Table (DSDT) */
486static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
487{
488 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
489}
490
491/* Firmware ACPI Control Structure (FACS) */
492static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
493{
494 ACPITBLFACS facs;
495
496 memset (&facs, 0, sizeof(facs));
497 memcpy (facs.au8Signature, "FACS", 4);
498 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
499 facs.u32HWSignature = RT_H2LE_U32(0);
500 facs.u32FWVector = RT_H2LE_U32(0);
501 facs.u32GlobalLock = RT_H2LE_U32(0);
502 facs.u32Flags = RT_H2LE_U32(0);
503 facs.u64X_FWVector = RT_H2LE_U64(0);
504 facs.u8Version = 1;
505
506 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
507}
508
509/* Fixed ACPI Description Table (FADT aka FACP) */
510static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
511{
512 ACPITBLFADT fadt;
513
514 memset (&fadt, 0, sizeof(fadt));
515 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
516 fadt.u32FACS = RT_H2LE_U32(facs_addr);
517 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
518 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
519 fadt.u8PreferredPMProfile = 0; /* unspecified */
520 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
521 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
522 fadt.u8AcpiEnable = ACPI_ENABLE;
523 fadt.u8AcpiDisable = ACPI_DISABLE;
524 fadt.u8S4BIOSReq = 0;
525 fadt.u8PStateCnt = 0;
526 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
527 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
528 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
529 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
530 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
531 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
532 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
533 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
534 fadt.u8PM1EVTLEN = 4;
535 fadt.u8PM1CTLLEN = 2;
536 fadt.u8PM2CTLLEN = 0;
537 fadt.u8PMTMLEN = 4;
538 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
539 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
540 fadt.u8GPE1BASE = GPE1_BASE;
541 fadt.u8CSTCNT = 0;
542 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
543 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
544 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
545 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
546 fadt.u8DutyOffset = 0;
547 fadt.u8DutyWidth = 0;
548 fadt.u8DayAlarm = 0;
549 fadt.u8MonAlarm = 0;
550 fadt.u8Century = 0;
551 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
552 /** @note WBINVD is required for ACPI versions newer than 1.0 */
553 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
554 | FADT_FL_FIX_RTC
555 | FADT_FL_TMR_VAL_EXT);
556 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
557 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
558 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
559 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
560 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
561 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
562 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
563 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
564 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
565 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
566 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
567 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
568 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
569 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
570}
571
572/*
573 * Root System Description Table.
574 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
575 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
576 */
577static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
578{
579 ACPITBLRSDT *rsdt;
580 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
581
582 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
583 if (!rsdt)
584 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
585
586 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
587 for (unsigned int i = 0; i < nb_entries; ++i)
588 {
589 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
590 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
591 }
592 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
593 acpiPhyscpy (s, addr, rsdt, size);
594 RTMemFree (rsdt);
595 return VINF_SUCCESS;
596}
597
598/* Extended System Description Table. */
599static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
600{
601 ACPITBLXSDT *xsdt;
602 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
603
604 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
605 if (!xsdt)
606 return VERR_NO_TMP_MEMORY;
607
608 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
609 for (unsigned int i = 0; i < nb_entries; ++i)
610 {
611 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
612 Log(("Setup XSDT: [%d] = %VX64\n", i, xsdt->u64Entry[i]));
613 }
614 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
615 acpiPhyscpy (s, addr, xsdt, size);
616 RTMemFree (xsdt);
617 return VINF_SUCCESS;
618}
619
620/* Root System Description Pointer (RSDP) */
621static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
622{
623 memset(rsdp, 0, sizeof(*rsdp));
624
625 /* ACPI 1.0 part (RSDT */
626 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
627 memcpy(rsdp->au8OemId, "VBOX ", 6);
628 rsdp->u8Revision = ACPI_REVISION;
629 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
630 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
631
632 /* ACPI 2.0 part (XSDT) */
633 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
634 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
635 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
636}
637
638/* Multiple APIC Description Table. */
639/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
640/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
641static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
642{
643 ACPITBLMADT madt;
644
645 /* Don't call this function if u8UseIOApic==false! */
646 Assert(s->u8UseIOApic);
647
648 memset(&madt, 0, sizeof(madt));
649 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
650
651 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
652 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
653
654 madt.LApic.u8Type = 0;
655 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
656 madt.LApic.u8ProcId = 0;
657 madt.LApic.u8ApicId = 0;
658 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
659
660 madt.IOApic.u8Type = 1;
661 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
662 madt.IOApic.u8IOApicId = 0;
663 madt.IOApic.u8Reserved = 0;
664 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
665 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
666
667 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
668 acpiPhyscpy (s, addr, &madt, sizeof(madt));
669}
670
671/* SCI IRQ */
672DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
673{
674 if (s->pm1a_ctl & SCI_EN)
675 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
676}
677
678DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
679{
680 return en & ~(RSR_EN | IGN_EN);
681}
682
683DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
684{
685 return sts & ~(RSR_STS | IGN_STS);
686}
687
688DECLINLINE(int) pm1a_level (ACPIState *s)
689{
690 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
691}
692
693DECLINLINE(int) gpe0_level (ACPIState *s)
694{
695 return (s->gpe0_en & s->gpe0_sts) != 0;
696}
697
698static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
699{
700 int old_level, new_level;
701
702 if (gpe0_level (s))
703 return;
704
705 old_level = pm1a_level (s);
706 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
707
708 s->pm1a_en = en;
709 s->pm1a_sts = sts;
710
711 if (new_level != old_level)
712 acpiSetIrq (s, new_level);
713}
714
715static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
716{
717 int old_level, new_level;
718
719 if (pm1a_level (s))
720 return;
721
722 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
723 new_level = (en & sts) != 0;
724
725 s->gpe0_en = en;
726 s->gpe0_sts = sts;
727
728 if (new_level != old_level)
729 acpiSetIrq (s, new_level);
730}
731
732static int acpiPowerDown (ACPIState *s)
733{
734 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
735 if (VBOX_FAILURE (rc))
736 AssertMsgFailed (("Could not power down the VM. rc = %Vrc\n", rc));
737 return rc;
738}
739
740/** Converts a ACPI port interface pointer to an ACPI state pointer. */
741#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
742
743/**
744 * Send an ACPI power off event.
745 *
746 * @returns VBox status code
747 * @param pInterface Pointer to the interface structure containing the called function pointer.
748 */
749static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
750{
751 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
752 s->fPowerButtonHandled = false;
753 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
754 return VINF_SUCCESS;
755}
756
757static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
758{
759 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
760 *pfHandled = s->fPowerButtonHandled;
761 return VINF_SUCCESS;
762}
763
764/**
765 * Send an ACPI sleep button event.
766 *
767 * @returns VBox status code
768 * @param pInterface Pointer to the interface structure containing the called function pointer.
769 */
770static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
771{
772 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
773 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
774 return VINF_SUCCESS;
775}
776
777/* PM1a_EVT_BLK enable */
778static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
779{
780 uint16_t val = s->pm1a_en;
781 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
782 return val;
783}
784
785static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
786{
787 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
788 val &= ~(RSR_EN | IGN_EN);
789 update_pm1a (s, s->pm1a_sts, val);
790}
791
792/* PM1a_EVT_BLK status */
793static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
794{
795 uint16_t val = s->pm1a_sts;
796 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
797 return val;
798}
799
800static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
801{
802 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
803 if (val & PWRBTN_STS)
804 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
805 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
806 update_pm1a (s, val, s->pm1a_en);
807}
808
809/* PM1a_CTL_BLK */
810static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
811{
812 uint16_t val = s->pm1a_ctl;
813 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
814 return val;
815}
816
817static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
818{
819 uint32_t uSleepState;
820
821 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
822 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
823
824 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
825 if (uSleepState != s->uSleepState)
826 {
827 s->uSleepState = uSleepState;
828 switch (uSleepState)
829 {
830 case 0x00: /* S0 */
831 break;
832 case 0x05: /* S5 */
833 LogRel (("Entering S5 (power down)\n"));
834 return acpiPowerDown (s);
835 default:
836 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
837 break;
838 }
839 }
840 return VINF_SUCCESS;
841}
842
843/* GPE0_BLK */
844static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
845{
846 uint8_t val = s->gpe0_en;
847 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
848 return val;
849}
850
851static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
852{
853 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
854 update_gpe0 (s, s->gpe0_sts, val);
855}
856
857static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
858{
859 uint8_t val = s->gpe0_sts;
860 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
861 return val;
862}
863
864static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
865{
866 val = s->gpe0_sts & ~val;
867 update_gpe0 (s, val, s->gpe0_en);
868 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
869}
870
871static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
872{
873 int rc = VINF_SUCCESS;
874
875 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
876 if (val == ACPI_RESET_REG_VAL)
877 {
878# ifndef IN_RING3
879 rc = VINF_IOM_HC_IOPORT_WRITE;
880# else /* IN_RING3 */
881 rc = PDMDevHlpVMReset(s->pDevIns);
882# endif /* !IN_RING3 */
883 }
884 return rc;
885}
886
887/* SMI */
888static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
889{
890 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
891 if (val == ACPI_ENABLE)
892 s->pm1a_ctl |= SCI_EN;
893 else if (val == ACPI_DISABLE)
894 s->pm1a_ctl &= ~SCI_EN;
895 else
896 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
897}
898
899static uint32_t find_rsdp_space (void)
900{
901 return 0xe0000;
902}
903
904static void acpiPMTimerReset (ACPIState *s)
905{
906 uint64_t interval, freq;
907
908 freq = TMTimerGetFreq (s->CTX_SUFF(ts));
909 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
910 Log (("interval = %RU64\n", interval));
911 TMTimerSet (s->CTX_SUFF(ts), TMTimerGet (s->CTX_SUFF(ts)) + interval);
912}
913
914static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
915{
916 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
917
918 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
919 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
920 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
921
922 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
923 acpiPMTimerReset (s);
924}
925
926/**
927 * _BST method.
928 */
929static void acpiFetchBatteryStatus (ACPIState *s)
930{
931 uint32_t *p = s->au8BatteryInfo;
932 bool fPresent; /* battery present? */
933 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
934 PDMACPIBATSTATE hostBatteryState; /* bitfield */
935 uint32_t hostPresentRate; /* 0..1000 */
936 int rc;
937
938 if (!s->pDrv)
939 return;
940 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
941 &hostBatteryState, &hostPresentRate);
942 AssertRC (rc);
943
944 /* default values */
945 p[BAT_STATUS_STATE] = hostBatteryState;
946 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
947 : hostPresentRate * 50; /* mW */
948 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
949 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
950
951 /* did we get a valid battery state? */
952 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
953 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
954 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
955 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
956}
957
958/**
959 * _BIF method.
960 */
961static void acpiFetchBatteryInfo (ACPIState *s)
962{
963 uint32_t *p = s->au8BatteryInfo;
964
965 p[BAT_INFO_UNITS] = 0; /* mWh */
966 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
967 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
968 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
969 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
970 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
971 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
972 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
973 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
974}
975
976/**
977 * _STA method.
978 */
979static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
980{
981 bool fPresent; /* battery present? */
982 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
983 PDMACPIBATSTATE hostBatteryState; /* bitfield */
984 uint32_t hostPresentRate; /* 0..1000 */
985 int rc;
986
987 if (!s->pDrv)
988 return 0;
989 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
990 &hostBatteryState, &hostPresentRate);
991 AssertRC (rc);
992
993 return fPresent
994 ? STA_DEVICE_PRESENT_MASK /* present */
995 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
996 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
997 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
998 | STA_BATTERY_PRESENT_MASK /* battery is present */
999 : 0; /* device not present */
1000}
1001
1002static uint32_t acpiGetPowerSource (ACPIState *s)
1003{
1004 PDMACPIPOWERSOURCE ps;
1005
1006 /* query the current power source from the host driver */
1007 if (!s->pDrv)
1008 return AC_ONLINE;
1009 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1010 AssertRC (rc);
1011 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1012}
1013
1014IO_WRITE_PROTO (acpiBatIndexWrite)
1015{
1016 ACPIState *s = (ACPIState *)pvUser;
1017
1018 switch (cb)
1019 {
1020 case 4:
1021 u32 >>= s->u8IndexShift;
1022 /* see comment at the declaration of u8IndexShift */
1023 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1024 {
1025 s->u8IndexShift = 2;
1026 u32 >>= 2;
1027 }
1028 Assert (u32 < BAT_INDEX_LAST);
1029 s->uBatteryIndex = u32;
1030 break;
1031 default:
1032 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1033 break;
1034 }
1035 return VINF_SUCCESS;
1036}
1037
1038IO_READ_PROTO (acpiBatDataRead)
1039{
1040 ACPIState *s = (ACPIState *)pvUser;
1041
1042 switch (cb)
1043 {
1044 case 4:
1045 switch (s->uBatteryIndex)
1046 {
1047 case BAT_STATUS_STATE:
1048 acpiFetchBatteryStatus(s);
1049 case BAT_STATUS_PRESENT_RATE:
1050 case BAT_STATUS_REMAINING_CAPACITY:
1051 case BAT_STATUS_PRESENT_VOLTAGE:
1052 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1053 break;
1054
1055 case BAT_INFO_UNITS:
1056 acpiFetchBatteryInfo(s);
1057 case BAT_INFO_DESIGN_CAPACITY:
1058 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1059 case BAT_INFO_TECHNOLOGY:
1060 case BAT_INFO_DESIGN_VOLTAGE:
1061 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1062 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1063 case BAT_INFO_CAPACITY_GRANULARITY_1:
1064 case BAT_INFO_CAPACITY_GRANULARITY_2:
1065 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1066 break;
1067
1068 case BAT_DEVICE_STATUS:
1069 *pu32 = acpiGetBatteryDeviceStatus(s);
1070 break;
1071
1072 case BAT_POWER_SOURCE:
1073 *pu32 = acpiGetPowerSource(s);
1074 break;
1075
1076 default:
1077 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1078 break;
1079 }
1080 break;
1081 default:
1082 return VERR_IOM_IOPORT_UNUSED;
1083 }
1084 return VINF_SUCCESS;
1085}
1086
1087IO_READ_PROTO (acpiFdcStatusRead)
1088{
1089 ACPIState *s = (ACPIState *)pvUser;
1090
1091 switch (cb)
1092 {
1093 case 4:
1094 *pu32 = s->u8UseFdc
1095 ? STA_DEVICE_PRESENT_MASK /* present */
1096 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1097 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1098 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1099 : 0; /* device not present */
1100 break;
1101 default:
1102 return VERR_IOM_IOPORT_UNUSED;
1103 }
1104 return VINF_SUCCESS;
1105}
1106
1107IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1108{
1109 ACPIState *s = (ACPIState *)pvUser;
1110
1111 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1112 switch (cb) {
1113 case 4:
1114 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1115 s->uSystemInfoIndex = u32;
1116 else
1117 {
1118 u32 >>= s->u8IndexShift;
1119 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1120 s->uSystemInfoIndex = u32;
1121 }
1122 break;
1123
1124 default:
1125 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1126 break;
1127 }
1128 return VINF_SUCCESS;
1129}
1130
1131IO_READ_PROTO (acpiSysInfoDataRead)
1132{
1133 ACPIState *s = (ACPIState *)pvUser;
1134
1135 switch (cb)
1136 {
1137 case 4:
1138 switch (s->uSystemInfoIndex)
1139 {
1140 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1141 *pu32 = s->u64RamSize;
1142 break;
1143
1144 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1145 *pu32 = s->u8UseIOApic;
1146 break;
1147
1148 default:
1149 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1150 break;
1151 }
1152 break;
1153
1154 default:
1155 return VERR_IOM_IOPORT_UNUSED;
1156 }
1157
1158 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1159 return VINF_SUCCESS;
1160}
1161
1162IO_WRITE_PROTO (acpiSysInfoDataWrite)
1163{
1164 ACPIState *s = (ACPIState *)pvUser;
1165
1166 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1167
1168 if (cb == 4 && u32 == 0xbadc0de)
1169 {
1170 switch (s->uSystemInfoIndex)
1171 {
1172 case SYSTEM_INFO_INDEX_INVALID:
1173 s->u8IndexShift = 0;
1174 break;
1175
1176 case SYSTEM_INFO_INDEX_VALID:
1177 s->u8IndexShift = 2;
1178 break;
1179
1180 default:
1181 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1182 Port, cb, u32, s->uSystemInfoIndex));
1183 break;
1184 }
1185 }
1186 else
1187 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1188 return VINF_SUCCESS;
1189}
1190
1191/* IO Helpers */
1192IO_READ_PROTO (acpiPm1aEnRead)
1193{
1194 switch (cb)
1195 {
1196 case 2:
1197 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1198 break;
1199 default:
1200 return VERR_IOM_IOPORT_UNUSED;
1201 }
1202 return VINF_SUCCESS;
1203}
1204
1205IO_READ_PROTO (acpiPm1aStsRead)
1206{
1207 switch (cb)
1208 {
1209 case 2:
1210 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1211 break;
1212 default:
1213 return VERR_IOM_IOPORT_UNUSED;
1214 }
1215 return VINF_SUCCESS;
1216}
1217
1218IO_READ_PROTO (acpiPm1aCtlRead)
1219{
1220 switch (cb)
1221 {
1222 case 2:
1223 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1224 break;
1225 default:
1226 return VERR_IOM_IOPORT_UNUSED;
1227 }
1228 return VINF_SUCCESS;
1229}
1230
1231IO_WRITE_PROTO (acpiPM1aEnWrite)
1232{
1233 switch (cb)
1234 {
1235 case 2:
1236 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1237 break;
1238 default:
1239 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1240 break;
1241 }
1242 return VINF_SUCCESS;
1243}
1244
1245IO_WRITE_PROTO (acpiPM1aStsWrite)
1246{
1247 switch (cb)
1248 {
1249 case 2:
1250 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1251 break;
1252 default:
1253 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1254 break;
1255 }
1256 return VINF_SUCCESS;
1257}
1258
1259IO_WRITE_PROTO (acpiPM1aCtlWrite)
1260{
1261 switch (cb)
1262 {
1263 case 2:
1264 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1265 default:
1266 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1267 break;
1268 }
1269 return VINF_SUCCESS;
1270}
1271
1272#endif /* IN_RING3 */
1273
1274/**
1275 * PMTMR readable from host/guest.
1276 */
1277IO_READ_PROTO (acpiPMTmrRead)
1278{
1279 if (cb == 4)
1280 {
1281 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1282 int64_t now = TMTimerGet (s->CTX_SUFF(ts));
1283 int64_t elapsed = now - s->pm_timer_initial;
1284
1285 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTX_SUFF(ts)));
1286 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1287 return VINF_SUCCESS;
1288 }
1289 return VERR_IOM_IOPORT_UNUSED;
1290}
1291
1292#ifdef IN_RING3
1293
1294IO_READ_PROTO (acpiGpe0StsRead)
1295{
1296 switch (cb)
1297 {
1298 case 1:
1299 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1300 break;
1301 default:
1302 return VERR_IOM_IOPORT_UNUSED;
1303 }
1304 return VINF_SUCCESS;
1305}
1306
1307IO_READ_PROTO (acpiGpe0EnRead)
1308{
1309 switch (cb)
1310 {
1311 case 1:
1312 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1313 break;
1314 default:
1315 return VERR_IOM_IOPORT_UNUSED;
1316 }
1317 return VINF_SUCCESS;
1318}
1319
1320IO_WRITE_PROTO (acpiGpe0StsWrite)
1321{
1322 switch (cb)
1323 {
1324 case 1:
1325 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1326 break;
1327 default:
1328 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1329 break;
1330 }
1331 return VINF_SUCCESS;
1332}
1333
1334IO_WRITE_PROTO (acpiGpe0EnWrite)
1335{
1336 switch (cb)
1337 {
1338 case 1:
1339 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1340 break;
1341 default:
1342 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1343 break;
1344 }
1345 return VINF_SUCCESS;
1346}
1347
1348IO_WRITE_PROTO (acpiSmiWrite)
1349{
1350 switch (cb)
1351 {
1352 case 1:
1353 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1354 break;
1355 default:
1356 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1357 break;
1358 }
1359 return VINF_SUCCESS;
1360}
1361
1362IO_WRITE_PROTO (acpiResetWrite)
1363{
1364 switch (cb)
1365 {
1366 case 1:
1367 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1368 default:
1369 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1370 break;
1371 }
1372 return VINF_SUCCESS;
1373}
1374
1375#ifdef DEBUG_ACPI
1376
1377IO_WRITE_PROTO (acpiDhexWrite)
1378{
1379 switch (cb)
1380 {
1381 case 1:
1382 Log (("%#x\n", u32 & 0xff));
1383 break;
1384 case 2:
1385 Log (("%#6x\n", u32 & 0xffff));
1386 case 4:
1387 Log (("%#10x\n", u32));
1388 break;
1389 default:
1390 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1391 break;
1392 }
1393 return VINF_SUCCESS;
1394}
1395
1396IO_WRITE_PROTO (acpiDchrWrite)
1397{
1398 switch (cb)
1399 {
1400 case 1:
1401 Log (("%c", u32 & 0xff));
1402 break;
1403 default:
1404 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1405 break;
1406 }
1407 return VINF_SUCCESS;
1408}
1409
1410#endif /* DEBUG_ACPI */
1411
1412
1413/**
1414 * Saved state structure description.
1415 */
1416static const SSMFIELD g_AcpiSavedStateFields[] =
1417{
1418 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1419 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1420 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1421 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1422 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1423 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1424 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1425 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1426 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1427 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1428 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1429 SSMFIELD_ENTRY (ACPIState, uSleepState),
1430 SSMFIELD_ENTRY_TERM ()
1431};
1432
1433static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1434{
1435 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1436 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1437}
1438
1439static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1440 uint32_t u32Version)
1441{
1442 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1443 int rc;
1444
1445 if (u32Version != 4)
1446 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1447
1448 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1449 if (VBOX_SUCCESS (rc))
1450 {
1451 acpiFetchBatteryStatus (s);
1452 acpiFetchBatteryInfo (s);
1453 acpiPMTimerReset (s);
1454 }
1455 return rc;
1456}
1457
1458/**
1459 * Queries an interface to the driver.
1460 *
1461 * @returns Pointer to interface.
1462 * @returns NULL if the interface was not supported by the driver.
1463 * @param pInterface Pointer to this interface structure.
1464 * @param enmInterface The requested interface identification.
1465 * @thread Any thread.
1466 */
1467static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1468{
1469 ACPIState *pData = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1470 switch (enmInterface)
1471 {
1472 case PDMINTERFACE_BASE:
1473 return &pData->IBase;
1474 case PDMINTERFACE_ACPI_PORT:
1475 return &pData->IACPIPort;
1476 default:
1477 return NULL;
1478 }
1479}
1480
1481/**
1482 * Create the ACPI tables.
1483 */
1484static int acpiPlantTables (ACPIState *s)
1485{
1486 int rc;
1487 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1488 uint32_t addend = 0;
1489 RTGCPHYS32 rsdt_addrs[4];
1490 uint32_t cAddr;
1491 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1492 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1493
1494 cAddr = 1; /* FADT */
1495 if (s->u8UseIOApic)
1496 cAddr++; /* MADT */
1497
1498 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1499 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1500
1501 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1502 if (VBOX_FAILURE (rc))
1503 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1504 N_("Configuration error: Querying "
1505 "\"RamSize\" as integer failed"));
1506
1507 if (s->u64RamSize > (0xffffffff - 0x10000))
1508 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1509 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1510 "value is 4095MB"));
1511
1512 rsdt_addr = 0;
1513 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1514 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1515 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1516 if (s->u8UseIOApic)
1517 {
1518 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1519 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1520 }
1521 else
1522 {
1523 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1524 }
1525
1526 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1527 if (last_addr > 0x10000)
1528 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1529 N_("Error: ACPI tables > 64KB"));
1530
1531 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1532 addend = (uint32_t) s->u64RamSize - 0x10000;
1533 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1534 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1535 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1536 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1537 acpiSetupDSDT (s, dsdt_addr + addend);
1538 acpiSetupFACS (s, facs_addr + addend);
1539 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1540
1541 rsdt_addrs[0] = fadt_addr + addend;
1542 if (s->u8UseIOApic)
1543 {
1544 acpiSetupMADT (s, apic_addr + addend);
1545 rsdt_addrs[1] = apic_addr + addend;
1546 }
1547
1548 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1549 if (VBOX_FAILURE(rc))
1550 return rc;
1551 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1552}
1553
1554/**
1555 * Construct a device instance for a VM.
1556 *
1557 * @returns VBox status.
1558 * @param pDevIns The device instance data.
1559 * If the registration structure is needed, pDevIns->pDevReg points to it.
1560 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1561 * The device number is also found in pDevIns->iInstance, but since it's
1562 * likely to be freqently used PDM passes it as parameter.
1563 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1564 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1565 * iInstance it's expected to be used a bit in this function.
1566 */
1567static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1568{
1569 int rc;
1570 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1571 uint32_t rsdp_addr;
1572 PCIDevice *dev;
1573 bool fGCEnabled;
1574 bool fR0Enabled;
1575
1576 /* Validate and read the configuration. */
1577 if (!CFGMR3AreValuesValid (pCfgHandle, "RamSize\0IOAPIC\0GCEnabled\0R0Enabled\0FdcEnabled\0"))
1578 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1579 N_("Configuration error: Invalid config key for ACPI device"));
1580
1581 s->pDevIns = pDevIns;
1582
1583 /* query whether we are supposed to present an IOAPIC */
1584 rc = CFGMR3QueryU8 (pCfgHandle, "IOAPIC", &s->u8UseIOApic);
1585 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1586 s->u8UseIOApic = 1;
1587 else if (VBOX_FAILURE (rc))
1588 return PDMDEV_SET_ERROR(pDevIns, rc,
1589 N_("Configuration error: Failed to read \"IOAPIC\""));
1590
1591 /* query whether we are supposed to present an FDC controller */
1592 rc = CFGMR3QueryU8 (pCfgHandle, "FdcEnabled", &s->u8UseFdc);
1593 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1594 s->u8UseFdc = 1;
1595 else if (VBOX_FAILURE (rc))
1596 return PDMDEV_SET_ERROR(pDevIns, rc,
1597 N_("Configuration error: Failed to read \"FdcEnabled\""));
1598
1599 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1600 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1601 fGCEnabled = true;
1602 else if (VBOX_FAILURE (rc))
1603 return PDMDEV_SET_ERROR(pDevIns, rc,
1604 N_("Configuration error: Failed to read \"GCEnabled\""));
1605
1606 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1607 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1608 fR0Enabled = true;
1609 else if (VBOX_FAILURE(rc))
1610 return PDMDEV_SET_ERROR(pDevIns, rc,
1611 N_("configuration error: failed to read R0Enabled as boolean"));
1612
1613 /* */
1614 rsdp_addr = find_rsdp_space ();
1615 if (!rsdp_addr)
1616 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1617 N_("Can not find space for RSDP. ACPI is disabled"));
1618
1619 rc = acpiPlantTables (s);
1620 if (VBOX_FAILURE (rc))
1621 return rc;
1622
1623 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1624 if (VBOX_FAILURE (rc))
1625 return rc;
1626
1627#define R(addr, cnt, writer, reader, description) \
1628 do { \
1629 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1630 NULL, NULL, description); \
1631 if (VBOX_FAILURE (rc)) \
1632 return rc; \
1633 } while (0)
1634#define L (GPE0_BLK_LEN / 2)
1635
1636 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1637 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1638 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1639 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1640 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1641#ifdef DEBUG_ACPI
1642 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1643 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1644#endif
1645 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1646 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1647 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1648 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1649 R (FDC_STATUS, 1, NULL, acpiFdcStatusRead, "ACPI FDC status index");
1650 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1651 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1652 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1653#undef L
1654#undef R
1655
1656 /* register GC stuff */
1657 if (fGCEnabled)
1658 {
1659 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1660 NULL, NULL, "ACPI PM Timer");
1661 AssertRCReturn(rc, rc);
1662 }
1663
1664 /* register R0 stuff */
1665 if (fR0Enabled)
1666 {
1667 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1668 NULL, NULL, "ACPI PM Timer");
1669 AssertRCReturn(rc, rc);
1670 }
1671
1672 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1673 if (VBOX_FAILURE(rc))
1674 {
1675 AssertMsgFailed(("pfnTMTimerCreate -> %Vrc\n", rc));
1676 return rc;
1677 }
1678
1679 s->tsR0 = TMTimerR0Ptr (s->tsR3);
1680 s->tsRC = TMTimerRCPtr (s->tsR3);
1681 s->pm_timer_initial = TMTimerGet (s->tsR3);
1682 acpiPMTimerReset (s);
1683
1684 dev = &s->dev;
1685 dev->config[0x00] = 0x86;
1686 dev->config[0x01] = 0x80;
1687
1688 dev->config[0x02] = 0x13;
1689 dev->config[0x03] = 0x71;
1690
1691 dev->config[0x04] = 0x01;
1692 dev->config[0x05] = 0x00;
1693
1694 dev->config[0x06] = 0x80;
1695 dev->config[0x07] = 0x02;
1696 dev->config[0x08] = 0x08;
1697 dev->config[0x09] = 0x00;
1698
1699 dev->config[0x0a] = 0x80;
1700 dev->config[0x0b] = 0x06;
1701
1702 dev->config[0x0e] = 0x80;
1703 dev->config[0x0f] = 0x00;
1704
1705#if 0 /* The ACPI controller usually has no subsystem ID. */
1706 dev->config[0x2c] = 0x86;
1707 dev->config[0x2d] = 0x80;
1708 dev->config[0x2e] = 0x00;
1709 dev->config[0x2f] = 0x00;
1710#endif
1711 dev->config[0x3c] = SCI_INT;
1712
1713 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1714 if (VBOX_FAILURE (rc))
1715 return rc;
1716
1717 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1718 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1719 if (VBOX_FAILURE(rc))
1720 return rc;
1721
1722 /*
1723 * Interfaces
1724 */
1725 /* IBase */
1726 s->IBase.pfnQueryInterface = acpiQueryInterface;
1727 /* IACPIPort */
1728 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1729 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1730 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1731
1732 /*
1733 * Get the corresponding connector interface
1734 */
1735 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1736 if (VBOX_SUCCESS (rc))
1737 {
1738 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1739 PDMINTERFACE_ACPI_CONNECTOR);
1740 if (!s->pDrv)
1741 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1742 N_("LUN #0 doesn't have an ACPI connector interface"));
1743 }
1744 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1745 {
1746 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1747 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1748 rc = VINF_SUCCESS;
1749 }
1750 else
1751 return PDMDEV_SET_ERROR(pDevIns, rc,
1752 N_("Failed to attach LUN #0"));
1753
1754 return rc;
1755}
1756
1757/**
1758 * Relocates the GC pointer members.
1759 */
1760static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1761{
1762 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1763 s->tsRC = TMTimerGCPtr (s->CTX_SUFF(ts));
1764}
1765
1766static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
1767{
1768 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1769
1770 s->pm1a_en = 0;
1771 s->pm1a_sts = 0;
1772 s->pm1a_ctl = 0;
1773 s->pm_timer_initial = TMTimerGet (s->CTX_SUFF(ts));
1774 acpiPMTimerReset(s);
1775 s->uBatteryIndex = 0;
1776 s->uSystemInfoIndex = 0;
1777 s->gpe0_en = 0;
1778 s->gpe0_sts = 0;
1779 s->uSleepState = 0;
1780
1781 acpiPlantTables(s);
1782}
1783
1784/**
1785 * The device registration structure.
1786 */
1787const PDMDEVREG g_DeviceACPI =
1788{
1789 /* u32Version */
1790 PDM_DEVREG_VERSION,
1791 /* szDeviceName */
1792 "acpi",
1793 /* szGCMod */
1794 "VBoxDDGC.gc",
1795 /* szR0Mod */
1796 "VBoxDDR0.r0",
1797 /* pszDescription */
1798 "Advanced Configuration and Power Interface",
1799 /* fFlags */
1800 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
1801 /* fClass */
1802 PDM_DEVREG_CLASS_ACPI,
1803 /* cMaxInstances */
1804 ~0,
1805 /* cbInstance */
1806 sizeof(ACPIState),
1807 /* pfnConstruct */
1808 acpiConstruct,
1809 /* pfnDestruct */
1810 NULL,
1811 /* pfnRelocate */
1812 acpiRelocate,
1813 /* pfnIOCtl */
1814 NULL,
1815 /* pfnPowerOn */
1816 NULL,
1817 /* pfnReset */
1818 acpiReset,
1819 /* pfnSuspend */
1820 NULL,
1821 /* pfnResume */
1822 NULL,
1823 /* pfnAttach */
1824 NULL,
1825 /* pfnDetach */
1826 NULL,
1827 /* pfnQueryInterface. */
1828 NULL
1829};
1830
1831#endif /* IN_RING3 */
1832#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1833
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