VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 17322

Last change on this file since 17322 was 16746, checked in by vboxsync, 16 years ago

SMP guests: implement support for multiple CPU ACPI objects (#ifdef'ed VBOX_WITH_SMP_GUESTS)
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1/* $Id: DevACPI.cpp 16746 2009-02-13 16:06:37Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/pdmdev.h>
24#include <VBox/log.h>
25#include <iprt/assert.h>
26#include <iprt/asm.h>
27#ifdef IN_RING3
28# include <iprt/alloc.h>
29# include <iprt/string.h>
30#endif /* IN_RING3 */
31
32#include "../Builtins.h"
33
34#ifdef LOG_ENABLED
35# define DEBUG_ACPI
36#endif
37
38/* the compiled DSL */
39#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
40#include <vboxaml.hex>
41#endif /* !IN_RING3 */
42
43#define IO_READ_PROTO(name) \
44 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
45 RTIOPORT Port, uint32_t *pu32, unsigned cb)
46
47#define IO_WRITE_PROTO(name) \
48 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
49 RTIOPORT Port, uint32_t u32, unsigned cb)
50
51#define DEBUG_HEX 0x3000
52#define DEBUG_CHR 0x3001
53
54#define PM_TMR_FREQ 3579545
55#define PM1a_EVT_BLK 0x00004000
56#define PM1b_EVT_BLK 0x00000000 /**< not supported */
57#define PM1a_CTL_BLK 0x00004004
58#define PM1b_CTL_BLK 0x00000000 /**< not supported */
59#define PM2_CTL_BLK 0x00000000 /**< not supported */
60#define PM_TMR_BLK 0x00004008
61#define GPE0_BLK 0x00004020
62#define GPE1_BLK 0x00000000 /**< not supported */
63#define BAT_INDEX 0x00004040
64#define BAT_DATA 0x00004044
65#define SYSI_INDEX 0x00004048
66#define SYSI_DATA 0x0000404c
67#define ACPI_RESET_BLK 0x00004050
68
69/* PM1x status register bits */
70#define TMR_STS RT_BIT(0)
71#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
72#define BM_STS RT_BIT(4)
73#define GBL_STS RT_BIT(5)
74#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
75#define PWRBTN_STS RT_BIT(8)
76#define SLPBTN_STS RT_BIT(9)
77#define RTC_STS RT_BIT(10)
78#define IGN_STS RT_BIT(11)
79#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
80#define WAK_STS RT_BIT(15)
81#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
82
83/* PM1x enable register bits */
84#define TMR_EN RT_BIT(0)
85#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
86#define GBL_EN RT_BIT(5)
87#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
88#define PWRBTN_EN RT_BIT(8)
89#define SLPBTN_EN RT_BIT(9)
90#define RTC_EN RT_BIT(10)
91#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
92#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
93#define IGN_EN 0
94
95/* PM1x control register bits */
96#define SCI_EN RT_BIT(0)
97#define BM_RLD RT_BIT(1)
98#define GBL_RLS RT_BIT(2)
99#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
100#define IGN_CNT RT_BIT(9)
101#define SLP_TYPx_SHIFT 10
102#define SLP_TYPx_MASK 7
103#define SLP_EN RT_BIT(13)
104#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
105#define RSR_CNT (RSR1_CNT | RSR2_CNT)
106
107#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
108
109enum
110{
111 BAT_STATUS_STATE = 0x00, /**< BST battery state */
112 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
113 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
114 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
115 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
116 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
117 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
118 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
119 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
120 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
121 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
122 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
123 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
124 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
125 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
126 BAT_INDEX_LAST
127};
128
129enum
130{
131 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
132 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
133 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
134 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
135 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
136 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
137 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
138 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
139 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
140 SYSTEM_INFO_INDEX_LAST = 9,
141 SYSTEM_INFO_INDEX_INVALID = 0x80,
142 SYSTEM_INFO_INDEX_VALID = 0x200
143};
144
145#define AC_OFFLINE 0
146#define AC_ONLINE 1
147
148#define BAT_TECH_PRIMARY 1
149#define BAT_TECH_SECONDARY 2
150
151#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
152#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
153#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
154#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
155#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
156
157struct ACPIState
158{
159 PCIDevice dev;
160 uint16_t pm1a_en;
161 uint16_t pm1a_sts;
162 uint16_t pm1a_ctl;
163 /** Number of logical CPUs in guest */
164 uint16_t cCpus;
165 int64_t pm_timer_initial;
166 PTMTIMERR3 tsR3;
167 PTMTIMERR0 tsR0;
168 PTMTIMERRC tsRC;
169
170 uint32_t gpe0_en;
171 uint32_t gpe0_sts;
172
173 unsigned int uBatteryIndex;
174 uint32_t au8BatteryInfo[13];
175
176 unsigned int uSystemInfoIndex;
177 uint64_t u64RamSize;
178
179 /** Current ACPI S* state. We support S0 and S5 */
180 uint32_t uSleepState;
181 uint8_t au8RSDPPage[0x1000];
182 /** This is a workaround for incorrect index field handling by Intels ACPICA.
183 * The system info _INI method writes to offset 0x200. We either observe a
184 * write request to index 0x80 (in that case we don't change the index) or a
185 * write request to offset 0x200 (in that case we divide the index value by
186 * 4. Note that the _STA method is sometimes called prior to the _INI method
187 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
188 * acpiBatIndexWrite() for handling this. */
189 uint8_t u8IndexShift;
190 /** provide an I/O-APIC */
191 uint8_t u8UseIOApic;
192 /** provide a floppy controller */
193 bool fUseFdc;
194 /** If High Precision Event Timer device should be supported */
195 bool fUseHpet;
196 /** If System Management Controller device should be supported */
197 bool fUseSmc;
198 /** the guest handled the last power button event */
199 bool fPowerButtonHandled;
200 /** If ACPI CPU device should be shown */
201 bool fShowCpu;
202 /** Aligning IBase. */
203 bool afAlignment[2];
204
205 /** ACPI port base interface. */
206 PDMIBASE IBase;
207 /** ACPI port interface. */
208 PDMIACPIPORT IACPIPort;
209 /** Pointer to the device instance. */
210 PPDMDEVINSR3 pDevIns;
211 /** Pointer to the driver base interface */
212 R3PTRTYPE(PPDMIBASE) pDrvBase;
213 /** Pointer to the driver connector interface */
214 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
215};
216
217#pragma pack(1)
218
219/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
220struct ACPIGENADDR
221{
222 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
223 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
224 uint8_t u8RegisterBitOffset; /**< bit offset of register */
225 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
226 uint64_t u64Address; /**< 64-bit address of register */
227};
228AssertCompileSize(ACPIGENADDR, 12);
229
230/** Root System Description Pointer */
231struct ACPITBLRSDP
232{
233 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
234 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
235 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
236 uint8_t u8Revision; /**< revision number, currently 2 */
237#define ACPI_REVISION 2 /**< ACPI 3.0 */
238 uint32_t u32RSDT; /**< phys addr of RSDT */
239 uint32_t u32Length; /**< bytes of this table */
240 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
241 uint8_t u8ExtChecksum; /**< checksum of entire table */
242 uint8_t u8Reserved[3]; /**< reserved */
243};
244AssertCompileSize(ACPITBLRSDP, 36);
245
246/** System Description Table Header */
247struct ACPITBLHEADER
248{
249 uint8_t au8Signature[4]; /**< table identifier */
250 uint32_t u32Length; /**< length of the table including header */
251 uint8_t u8Revision; /**< revision number */
252 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
253 uint8_t au8OemId[6]; /**< OEM-supplied string */
254 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
255 uint32_t u32OemRevision; /**< OEM-supplied revision number */
256 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
257 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
258};
259AssertCompileSize(ACPITBLHEADER, 36);
260
261/** Root System Description Table */
262struct ACPITBLRSDT
263{
264 ACPITBLHEADER header;
265 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
266};
267AssertCompileSize(ACPITBLRSDT, 40);
268
269/** Extended System Description Table */
270struct ACPITBLXSDT
271{
272 ACPITBLHEADER header;
273 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
274};
275AssertCompileSize(ACPITBLXSDT, 44);
276
277/** Fixed ACPI Description Table */
278struct ACPITBLFADT
279{
280 ACPITBLHEADER header;
281 uint32_t u32FACS; /**< phys. address of FACS */
282 uint32_t u32DSDT; /**< phys. address of DSDT */
283 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
284#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
285#define INT_MODEL_MULTIPLE_APIC 2
286 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
287 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
288#define SCI_INT 9
289 uint32_t u32SMICmd; /**< system port address of SMI command port */
290#define SMI_CMD 0x0000442e
291 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
292#define ACPI_ENABLE 0xa1
293 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
294#define ACPI_DISABLE 0xa0
295 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
296 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
297 state control responsibility */
298 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
299 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
300 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
301 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
302 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
303 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
304 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
305 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
306 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
307 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
308 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
309 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
310 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
311#define GPE0_BLK_LEN 2
312 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
313#define GPE1_BLK_LEN 0
314 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
315#define GPE1_BASE 0
316 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
317 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
318#define P_LVL2_LAT 101 /**< C2 state not supported */
319 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
320#define P_LVL3_LAT 1001 /**< C3 state not supported */
321 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
322 lines from any processors memory caches */
323#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
324 uint16_t u16FlushStride; /**< cache line width */
325#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
326 uint8_t u8DutyOffset;
327 uint8_t u8DutyWidth;
328 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
329 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
330 uint8_t u8Century; /**< RTC CMOS RAM index of century */
331 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
332#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
333 (COM too?) */
334#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
335#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
336 uint8_t u8Must0_0; /**< must be 0 */
337 uint32_t u32Flags; /**< fixed feature flags */
338#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
339#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
340#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
341#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
342#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
343#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
344#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
345#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
346#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
347#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
348#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
349#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
350#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
351#define FADT_FL_CPU_SW_SLP RT_BIT(13)
352#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
353#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
354#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
355#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
356#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
357#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
358 ACPIGENADDR ResetReg; /**< ext addr of reset register */
359 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
360#define ACPI_RESET_REG_VAL 0x10
361 uint8_t au8Must0_1[3]; /**< must be 0 */
362 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
363 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
364 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
365 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
366 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
367 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
368 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
369 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
370 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
371 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
372};
373AssertCompileSize(ACPITBLFADT, 244);
374
375/** Firmware ACPI Control Structure */
376struct ACPITBLFACS
377{
378 uint8_t au8Signature[4]; /**< 'FACS' */
379 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
380 uint32_t u32HWSignature; /**< systems HW signature at last boot */
381 uint32_t u32FWVector; /**< address of waking vector */
382 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
383 uint32_t u32Flags; /**< FACS flags */
384 uint64_t u64X_FWVector; /**< 64-bit waking vector */
385 uint8_t u8Version; /**< version of this table */
386 uint8_t au8Reserved[31]; /**< zero */
387};
388AssertCompileSize(ACPITBLFACS, 64);
389
390/** Processor Local APIC Structure */
391struct ACPITBLLAPIC
392{
393 uint8_t u8Type; /**< 0 = LAPIC */
394 uint8_t u8Length; /**< 8 */
395 uint8_t u8ProcId; /**< processor ID */
396 uint8_t u8ApicId; /**< local APIC ID */
397 uint32_t u32Flags; /**< Flags */
398#define LAPIC_ENABLED 0x1
399};
400AssertCompileSize(ACPITBLLAPIC, 8);
401
402/** I/O APIC Structure */
403struct ACPITBLIOAPIC
404{
405 uint8_t u8Type; /**< 1 == I/O APIC */
406 uint8_t u8Length; /**< 12 */
407 uint8_t u8IOApicId; /**< I/O APIC ID */
408 uint8_t u8Reserved; /**< 0 */
409 uint32_t u32Address; /**< phys address to access I/O APIC */
410 uint32_t u32GSIB; /**< global system interrupt number to start */
411};
412AssertCompileSize(ACPITBLIOAPIC, 12);
413
414#ifdef VBOX_WITH_SMP_GUESTS
415#ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
416
417# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
418
419/**
420 * Multiple APIC Description Table.
421 *
422 * This structure looks somewhat convoluted due layout of MADT table in MP case.
423 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
424 * use regular C structure and proxy to raw memory instead.
425 */
426class AcpiTableMADT
427{
428 /**
429 * All actual data stored in dynamically allocated memory pointed by this field.
430 */
431 uint8_t* pData;
432 /**
433 * Number of CPU entries in this MADT.
434 */
435 uint32_t cCpus;
436
437 public:
438 /**
439 * Address of ACPI header
440 */
441 inline ACPITBLHEADER* header_addr() const
442 {
443 return (ACPITBLHEADER*)pData;
444 }
445
446 /**
447 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
448 * although address is the same for all of them.
449 */
450 inline uint32_t* u32LAPIC_addr() const
451 {
452 return (uint32_t*)(header_addr() + 1);
453 }
454
455 /**
456 * Address of APIC flags
457 */
458 inline uint32_t* u32Flags_addr() const
459 {
460 return (uint32_t*)(u32LAPIC_addr() + 1);
461 }
462
463 /**
464 * Address of per-CPU LAPIC descriptions
465 */
466 inline ACPITBLLAPIC* LApics_addr() const
467 {
468 return (ACPITBLLAPIC*)(u32Flags_addr() + 1);
469 }
470
471 /**
472 * Address of IO APIC description
473 */
474 inline ACPITBLIOAPIC* IOApic_addr() const
475 {
476 return (ACPITBLIOAPIC*)(LApics_addr() + cCpus);
477 }
478
479 /**
480 * Size of MADT.
481 * Note that this function assumes IOApic to be the last field in structure.
482 */
483 inline uint32_t size() const
484 {
485 return (uint8_t*)(IOApic_addr() + 1)-(uint8_t*)header_addr();
486 }
487
488 /**
489 * Raw data of MADT.
490 */
491 inline const uint8_t* data() const
492 {
493 return pData;
494 }
495
496 /**
497 * Size of MADT for given ACPI config, useful to compute layout.
498 */
499 static uint32_t sizeFor(ACPIState *s)
500 {
501 return AcpiTableMADT(s->cCpus).size();
502 }
503
504 /*
505 * Constructor, only works in Ring 3, doesn't look like a big deal.
506 */
507 AcpiTableMADT(uint16_t cpus)
508 {
509 cCpus = cpus;
510 pData = 0;
511 uint32_t sSize = size();
512 pData = (uint8_t*)RTMemAllocZ(sSize);
513 }
514
515 ~AcpiTableMADT()
516 {
517 RTMemFree(pData);
518 }
519};
520#endif /* IN_RING3 */
521
522#else /* !VBOX_WITH_SMP_GUESTS */
523/** Multiple APIC Description Table */
524struct ACPITBLMADT
525{
526 ACPITBLHEADER header;
527 uint32_t u32LAPIC; /**< local APIC address */
528 uint32_t u32Flags; /**< Flags */
529#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
530 ACPITBLLAPIC LApic;
531 ACPITBLIOAPIC IOApic;
532};
533AssertCompileSize(ACPITBLMADT, 64);
534#endif /* !VBOX_WITH_SMP_GUESTS */
535
536#pragma pack()
537
538
539#ifndef VBOX_DEVICE_STRUCT_TESTCASE
540__BEGIN_DECLS
541IO_READ_PROTO (acpiPMTmrRead);
542#ifdef IN_RING3
543IO_READ_PROTO (acpiPm1aEnRead);
544IO_WRITE_PROTO (acpiPM1aEnWrite);
545IO_READ_PROTO (acpiPm1aStsRead);
546IO_WRITE_PROTO (acpiPM1aStsWrite);
547IO_READ_PROTO (acpiPm1aCtlRead);
548IO_WRITE_PROTO (acpiPM1aCtlWrite);
549IO_WRITE_PROTO (acpiSmiWrite);
550IO_WRITE_PROTO (acpiBatIndexWrite);
551IO_READ_PROTO (acpiBatDataRead);
552IO_READ_PROTO (acpiSysInfoDataRead);
553IO_WRITE_PROTO (acpiSysInfoDataWrite);
554IO_READ_PROTO (acpiGpe0EnRead);
555IO_WRITE_PROTO (acpiGpe0EnWrite);
556IO_READ_PROTO (acpiGpe0StsRead);
557IO_WRITE_PROTO (acpiGpe0StsWrite);
558IO_WRITE_PROTO (acpiResetWrite);
559# ifdef DEBUG_ACPI
560IO_WRITE_PROTO (acpiDhexWrite);
561IO_WRITE_PROTO (acpiDchrWrite);
562# endif
563#endif
564__END_DECLS
565
566#ifdef IN_RING3
567
568/* Simple acpiChecksum: all the bytes must add up to 0. */
569static uint8_t acpiChecksum (const uint8_t * const data, uint32_t len)
570{
571 uint8_t sum = 0;
572 for (size_t i = 0; i < len; ++i)
573 sum += data[i];
574 return -sum;
575}
576
577static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
578 uint32_t u32Length, uint8_t u8Revision)
579{
580 memcpy(header->au8Signature, au8Signature, 4);
581 header->u32Length = RT_H2LE_U32(u32Length);
582 header->u8Revision = u8Revision;
583 memcpy(header->au8OemId, "VBOX ", 6);
584 memcpy(header->au8OemTabId, "VBOX", 4);
585 memcpy(header->au8OemTabId+4, au8Signature, 4);
586 header->u32OemRevision = RT_H2LE_U32(1);
587 memcpy(header->au8CreatorId, "ASL ", 4);
588 header->u32CreatorRev = RT_H2LE_U32(0x61);
589}
590
591static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
592 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
593 uint8_t u8AccessSize, uint64_t u64Address)
594{
595 g->u8AddressSpaceId = u8AddressSpaceId;
596 g->u8RegisterBitWidth = u8RegisterBitWidth;
597 g->u8RegisterBitOffset = u8RegisterBitOffset;
598 g->u8AccessSize = u8AccessSize;
599 g->u64Address = RT_H2LE_U64(u64Address);
600}
601
602static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
603{
604 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
605}
606
607/* Differentiated System Description Table (DSDT) */
608static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
609{
610 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
611}
612
613/* Firmware ACPI Control Structure (FACS) */
614static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
615{
616 ACPITBLFACS facs;
617
618 memset (&facs, 0, sizeof(facs));
619 memcpy (facs.au8Signature, "FACS", 4);
620 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
621 facs.u32HWSignature = RT_H2LE_U32(0);
622 facs.u32FWVector = RT_H2LE_U32(0);
623 facs.u32GlobalLock = RT_H2LE_U32(0);
624 facs.u32Flags = RT_H2LE_U32(0);
625 facs.u64X_FWVector = RT_H2LE_U64(0);
626 facs.u8Version = 1;
627
628 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
629}
630
631/* Fixed ACPI Description Table (FADT aka FACP) */
632static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
633{
634 ACPITBLFADT fadt;
635
636 memset (&fadt, 0, sizeof(fadt));
637 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
638 fadt.u32FACS = RT_H2LE_U32(facs_addr);
639 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
640 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
641 fadt.u8PreferredPMProfile = 0; /* unspecified */
642 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
643 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
644 fadt.u8AcpiEnable = ACPI_ENABLE;
645 fadt.u8AcpiDisable = ACPI_DISABLE;
646 fadt.u8S4BIOSReq = 0;
647 fadt.u8PStateCnt = 0;
648 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
649 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
650 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
651 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
652 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
653 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
654 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
655 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
656 fadt.u8PM1EVTLEN = 4;
657 fadt.u8PM1CTLLEN = 2;
658 fadt.u8PM2CTLLEN = 0;
659 fadt.u8PMTMLEN = 4;
660 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
661 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
662 fadt.u8GPE1BASE = GPE1_BASE;
663 fadt.u8CSTCNT = 0;
664 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
665 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
666 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
667 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
668 fadt.u8DutyOffset = 0;
669 fadt.u8DutyWidth = 0;
670 fadt.u8DayAlarm = 0;
671 fadt.u8MonAlarm = 0;
672 fadt.u8Century = 0;
673 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
674 /** @note WBINVD is required for ACPI versions newer than 1.0 */
675 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
676 | FADT_FL_FIX_RTC
677 | FADT_FL_TMR_VAL_EXT);
678 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
679 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
680 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
681 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
682 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
683 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
684 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
685 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
686 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
687 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
688 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
689 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
690 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
691 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
692}
693
694/*
695 * Root System Description Table.
696 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
697 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
698 */
699static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
700{
701 ACPITBLRSDT *rsdt;
702 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
703
704 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
705 if (!rsdt)
706 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
707
708 acpiPrepareHeader (&rsdt->header, "RSDT", size, 1);
709 for (unsigned int i = 0; i < nb_entries; ++i)
710 {
711 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
712 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
713 }
714 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
715 acpiPhyscpy (s, addr, rsdt, size);
716 RTMemFree (rsdt);
717 return VINF_SUCCESS;
718}
719
720/* Extended System Description Table. */
721static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
722{
723 ACPITBLXSDT *xsdt;
724 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
725
726 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
727 if (!xsdt)
728 return VERR_NO_TMP_MEMORY;
729
730 acpiPrepareHeader (&xsdt->header, "XSDT", size, 1 /* according to ACPI 3.0 specs */);
731 for (unsigned int i = 0; i < nb_entries; ++i)
732 {
733 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
734 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
735 }
736 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
737 acpiPhyscpy (s, addr, xsdt, size);
738 RTMemFree (xsdt);
739 return VINF_SUCCESS;
740}
741
742/* Root System Description Pointer (RSDP) */
743static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
744{
745 memset(rsdp, 0, sizeof(*rsdp));
746
747 /* ACPI 1.0 part (RSDT */
748 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
749 memcpy(rsdp->au8OemId, "VBOX ", 6);
750 rsdp->u8Revision = ACPI_REVISION;
751 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
752 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
753
754 /* ACPI 2.0 part (XSDT) */
755 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
756 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
757 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
758}
759
760/* Multiple APIC Description Table. */
761/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
762/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
763static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
764{
765#ifdef VBOX_WITH_SMP_GUESTS
766 uint16_t cpus = s->cCpus;
767 AcpiTableMADT madt(cpus);
768
769 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
770
771 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
772 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
773
774 ACPITBLLAPIC* lapic = madt.LApics_addr();
775 for (uint16_t i = 0; i < cpus; i++)
776 {
777 lapic->u8Type = 0;
778 lapic->u8Length = sizeof(ACPITBLLAPIC);
779 lapic->u8ProcId = i;
780 lapic->u8ApicId = i;
781 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
782 lapic++;
783 }
784
785 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
786
787 ioapic->u8Type = 1;
788 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
789 ioapic->u8IOApicId = cpus;
790 ioapic->u8Reserved = 0;
791 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
792 ioapic->u32GSIB = RT_H2LE_U32(0);
793
794 madt.header_addr()->u8Checksum = acpiChecksum (madt.data(), madt.size());
795 acpiPhyscpy (s, addr, madt.data(), madt.size());
796
797#else /* !VBOX_WITH_SMP_GUESTS */
798 ACPITBLMADT madt;
799
800 /* Don't call this function if u8UseIOApic==false! */
801 Assert(s->u8UseIOApic);
802
803 memset(&madt, 0, sizeof(madt));
804 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
805
806 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
807 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
808
809 madt.LApic.u8Type = 0;
810 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
811 madt.LApic.u8ProcId = 0;
812 madt.LApic.u8ApicId = 0;
813 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
814
815 madt.IOApic.u8Type = 1;
816 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
817 madt.IOApic.u8IOApicId = 1;
818 madt.IOApic.u8Reserved = 0;
819 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
820 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
821
822 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
823 acpiPhyscpy (s, addr, &madt, sizeof(madt));
824#endif /* !VBOX_WITH_SMP_GUESTS */
825}
826
827/* SCI IRQ */
828DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
829{
830 if (s->pm1a_ctl & SCI_EN)
831 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
832}
833
834DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
835{
836 return en & ~(RSR_EN | IGN_EN);
837}
838
839DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
840{
841 return sts & ~(RSR_STS | IGN_STS);
842}
843
844DECLINLINE(int) pm1a_level (ACPIState *s)
845{
846 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
847}
848
849DECLINLINE(int) gpe0_level (ACPIState *s)
850{
851 return (s->gpe0_en & s->gpe0_sts) != 0;
852}
853
854static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
855{
856 int old_level, new_level;
857
858 if (gpe0_level (s))
859 return;
860
861 old_level = pm1a_level (s);
862 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
863
864 s->pm1a_en = en;
865 s->pm1a_sts = sts;
866
867 if (new_level != old_level)
868 acpiSetIrq (s, new_level);
869}
870
871static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
872{
873 int old_level, new_level;
874
875 if (pm1a_level (s))
876 return;
877
878 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
879 new_level = (en & sts) != 0;
880
881 s->gpe0_en = en;
882 s->gpe0_sts = sts;
883
884 if (new_level != old_level)
885 acpiSetIrq (s, new_level);
886}
887
888static int acpiPowerDown (ACPIState *s)
889{
890 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
891 if (RT_FAILURE (rc))
892 AssertMsgFailed (("Could not power down the VM. rc = %Rrc\n", rc));
893 return rc;
894}
895
896/** Converts a ACPI port interface pointer to an ACPI state pointer. */
897#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
898
899/**
900 * Send an ACPI power off event.
901 *
902 * @returns VBox status code
903 * @param pInterface Pointer to the interface structure containing the called function pointer.
904 */
905static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
906{
907 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
908 s->fPowerButtonHandled = false;
909 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
910 return VINF_SUCCESS;
911}
912
913/**
914 * Check if the ACPI power button event was handled.
915 *
916 * @returns VBox status code
917 * @param pInterface Pointer to the interface structure containing the called function pointer.
918 * @param pfHandled Return true if the power button event was handled by the guest.
919 */
920static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
921{
922 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
923 *pfHandled = s->fPowerButtonHandled;
924 return VINF_SUCCESS;
925}
926
927/**
928 * Check if the Guest entered into G0 (working) or G1 (sleeping).
929 *
930 * @returns VBox status code
931 * @param pInterface Pointer to the interface structure containing the called function pointer.
932 * @param pfEntered Return true if the guest entered the ACPI mode.
933 */
934static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
935{
936 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
937 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
938 return VINF_SUCCESS;
939}
940
941/**
942 * Send an ACPI sleep button event.
943 *
944 * @returns VBox status code
945 * @param pInterface Pointer to the interface structure containing the called function pointer.
946 */
947static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
948{
949 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
950 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
951 return VINF_SUCCESS;
952}
953
954/* PM1a_EVT_BLK enable */
955static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
956{
957 uint16_t val = s->pm1a_en;
958 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
959 return val;
960}
961
962static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
963{
964 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
965 val &= ~(RSR_EN | IGN_EN);
966 update_pm1a (s, s->pm1a_sts, val);
967}
968
969/* PM1a_EVT_BLK status */
970static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
971{
972 uint16_t val = s->pm1a_sts;
973 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
974 return val;
975}
976
977static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
978{
979 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
980 if (val & PWRBTN_STS)
981 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
982 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
983 update_pm1a (s, val, s->pm1a_en);
984}
985
986/* PM1a_CTL_BLK */
987static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
988{
989 uint16_t val = s->pm1a_ctl;
990 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
991 return val;
992}
993
994static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
995{
996 uint32_t uSleepState;
997
998 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
999 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1000
1001 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1002 if (uSleepState != s->uSleepState)
1003 {
1004 s->uSleepState = uSleepState;
1005 switch (uSleepState)
1006 {
1007 case 0x00: /* S0 */
1008 break;
1009 case 0x05: /* S5 */
1010 LogRel (("Entering S5 (power down)\n"));
1011 return acpiPowerDown (s);
1012 default:
1013 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
1014 break;
1015 }
1016 }
1017 return VINF_SUCCESS;
1018}
1019
1020/* GPE0_BLK */
1021static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
1022{
1023 uint8_t val = s->gpe0_en;
1024 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
1025 return val;
1026}
1027
1028static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1029{
1030 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
1031 update_gpe0 (s, s->gpe0_sts, val);
1032}
1033
1034static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
1035{
1036 uint8_t val = s->gpe0_sts;
1037 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
1038 return val;
1039}
1040
1041static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1042{
1043 val = s->gpe0_sts & ~val;
1044 update_gpe0 (s, val, s->gpe0_en);
1045 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
1046}
1047
1048static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1049{
1050 int rc = VINF_SUCCESS;
1051
1052 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1053 if (val == ACPI_RESET_REG_VAL)
1054 {
1055# ifndef IN_RING3
1056 rc = VINF_IOM_HC_IOPORT_WRITE;
1057# else /* IN_RING3 */
1058 rc = PDMDevHlpVMReset(s->pDevIns);
1059# endif /* !IN_RING3 */
1060 }
1061 return rc;
1062}
1063
1064/* SMI */
1065static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
1066{
1067 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
1068 if (val == ACPI_ENABLE)
1069 s->pm1a_ctl |= SCI_EN;
1070 else if (val == ACPI_DISABLE)
1071 s->pm1a_ctl &= ~SCI_EN;
1072 else
1073 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1074}
1075
1076static uint32_t find_rsdp_space (void)
1077{
1078 return 0xe0000;
1079}
1080
1081static void acpiPMTimerReset (ACPIState *s)
1082{
1083 uint64_t interval, freq;
1084
1085 freq = TMTimerGetFreq (s->CTX_SUFF(ts));
1086 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
1087 Log (("interval = %RU64\n", interval));
1088 TMTimerSet (s->CTX_SUFF(ts), TMTimerGet (s->CTX_SUFF(ts)) + interval);
1089}
1090
1091static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
1092{
1093 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1094
1095 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1096 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1097 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1098
1099 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1100 acpiPMTimerReset (s);
1101}
1102
1103/**
1104 * _BST method.
1105 */
1106static void acpiFetchBatteryStatus (ACPIState *s)
1107{
1108 uint32_t *p = s->au8BatteryInfo;
1109 bool fPresent; /* battery present? */
1110 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1111 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1112 uint32_t hostPresentRate; /* 0..1000 */
1113 int rc;
1114
1115 if (!s->pDrv)
1116 return;
1117 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1118 &hostBatteryState, &hostPresentRate);
1119 AssertRC (rc);
1120
1121 /* default values */
1122 p[BAT_STATUS_STATE] = hostBatteryState;
1123 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1124 : hostPresentRate * 50; /* mW */
1125 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1126 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1127
1128 /* did we get a valid battery state? */
1129 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1130 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1131 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1132 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1133}
1134
1135/**
1136 * _BIF method.
1137 */
1138static void acpiFetchBatteryInfo (ACPIState *s)
1139{
1140 uint32_t *p = s->au8BatteryInfo;
1141
1142 p[BAT_INFO_UNITS] = 0; /* mWh */
1143 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1144 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1145 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1146 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1147 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1148 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1149 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1150 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1151}
1152
1153/**
1154 * _STA method.
1155 */
1156static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
1157{
1158 bool fPresent; /* battery present? */
1159 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1160 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1161 uint32_t hostPresentRate; /* 0..1000 */
1162 int rc;
1163
1164 if (!s->pDrv)
1165 return 0;
1166 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1167 &hostBatteryState, &hostPresentRate);
1168 AssertRC (rc);
1169
1170 return fPresent
1171 ? STA_DEVICE_PRESENT_MASK /* present */
1172 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1173 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1174 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1175 | STA_BATTERY_PRESENT_MASK /* battery is present */
1176 : 0; /* device not present */
1177}
1178
1179static uint32_t acpiGetPowerSource (ACPIState *s)
1180{
1181 PDMACPIPOWERSOURCE ps;
1182
1183 /* query the current power source from the host driver */
1184 if (!s->pDrv)
1185 return AC_ONLINE;
1186 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1187 AssertRC (rc);
1188 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1189}
1190
1191IO_WRITE_PROTO (acpiBatIndexWrite)
1192{
1193 ACPIState *s = (ACPIState *)pvUser;
1194
1195 switch (cb)
1196 {
1197 case 4:
1198 u32 >>= s->u8IndexShift;
1199 /* see comment at the declaration of u8IndexShift */
1200 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1201 {
1202 s->u8IndexShift = 2;
1203 u32 >>= 2;
1204 }
1205 Assert (u32 < BAT_INDEX_LAST);
1206 s->uBatteryIndex = u32;
1207 break;
1208 default:
1209 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1210 break;
1211 }
1212 return VINF_SUCCESS;
1213}
1214
1215IO_READ_PROTO (acpiBatDataRead)
1216{
1217 ACPIState *s = (ACPIState *)pvUser;
1218
1219 switch (cb)
1220 {
1221 case 4:
1222 switch (s->uBatteryIndex)
1223 {
1224 case BAT_STATUS_STATE:
1225 acpiFetchBatteryStatus(s);
1226 case BAT_STATUS_PRESENT_RATE:
1227 case BAT_STATUS_REMAINING_CAPACITY:
1228 case BAT_STATUS_PRESENT_VOLTAGE:
1229 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1230 break;
1231
1232 case BAT_INFO_UNITS:
1233 acpiFetchBatteryInfo(s);
1234 case BAT_INFO_DESIGN_CAPACITY:
1235 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1236 case BAT_INFO_TECHNOLOGY:
1237 case BAT_INFO_DESIGN_VOLTAGE:
1238 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1239 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1240 case BAT_INFO_CAPACITY_GRANULARITY_1:
1241 case BAT_INFO_CAPACITY_GRANULARITY_2:
1242 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1243 break;
1244
1245 case BAT_DEVICE_STATUS:
1246 *pu32 = acpiGetBatteryDeviceStatus(s);
1247 break;
1248
1249 case BAT_POWER_SOURCE:
1250 *pu32 = acpiGetPowerSource(s);
1251 break;
1252
1253 default:
1254 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1255 break;
1256 }
1257 break;
1258 default:
1259 return VERR_IOM_IOPORT_UNUSED;
1260 }
1261 return VINF_SUCCESS;
1262}
1263
1264IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1265{
1266 ACPIState *s = (ACPIState *)pvUser;
1267
1268 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1269 switch (cb) {
1270 case 4:
1271 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1272 s->uSystemInfoIndex = u32;
1273 else
1274 {
1275 /* see comment at the declaration of u8IndexShift */
1276 if (s->u8IndexShift == 0)
1277 {
1278 if (((u32 >> 2) < SYSTEM_INFO_INDEX_LAST) && ((u32 & 0x3)) == 0)
1279 {
1280 s->u8IndexShift = 2;
1281 }
1282 }
1283
1284 u32 >>= s->u8IndexShift;
1285 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1286 s->uSystemInfoIndex = u32;
1287 }
1288 break;
1289
1290 default:
1291 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1292 break;
1293 }
1294 return VINF_SUCCESS;
1295}
1296
1297IO_READ_PROTO (acpiSysInfoDataRead)
1298{
1299 ACPIState *s = (ACPIState *)pvUser;
1300
1301 switch (cb)
1302 {
1303 case 4:
1304 switch (s->uSystemInfoIndex)
1305 {
1306 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1307 *pu32 = s->u64RamSize;
1308 break;
1309
1310 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1311 *pu32 = s->u8UseIOApic;
1312 break;
1313
1314 case SYSTEM_INFO_INDEX_HPET_STATUS:
1315 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1316 | STA_DEVICE_ENABLED_MASK
1317 | STA_DEVICE_SHOW_IN_UI_MASK
1318 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1319 : 0;
1320 break;
1321
1322 case SYSTEM_INFO_INDEX_SMC_STATUS:
1323 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1324 | STA_DEVICE_ENABLED_MASK
1325 /* no need to show this device in the UI */
1326 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1327 : 0;
1328 break;
1329
1330 case SYSTEM_INFO_INDEX_FDC_STATUS:
1331 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1332 | STA_DEVICE_ENABLED_MASK
1333 | STA_DEVICE_SHOW_IN_UI_MASK
1334 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1335 : 0;
1336 break;
1337 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1338 *pu32 = s->fShowCpu ? ( STA_DEVICE_PRESENT_MASK
1339 | STA_DEVICE_ENABLED_MASK
1340 | STA_DEVICE_SHOW_IN_UI_MASK
1341 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1342 : 0;
1343 break;
1344
1345 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1346 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1347 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1348#ifdef VBOX_WITH_SMP_GUESTS
1349 *pu32 = (s->fShowCpu &&
1350 s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < cCpus)
1351 ? ( STA_DEVICE_PRESENT_MASK
1352 | STA_DEVICE_ENABLED_MASK
1353 | STA_DEVICE_SHOW_IN_UI_MASK
1354 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1355 : 0;
1356#else
1357 *pu32 = 0;
1358#endif
1359 break;
1360
1361 /* Solaris 9 tries to read from this index */
1362 case SYSTEM_INFO_INDEX_INVALID:
1363 *pu32 = 0;
1364 break;
1365
1366 default:
1367 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1368 break;
1369 }
1370 break;
1371
1372 default:
1373 return VERR_IOM_IOPORT_UNUSED;
1374 }
1375
1376 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1377 return VINF_SUCCESS;
1378}
1379
1380IO_WRITE_PROTO (acpiSysInfoDataWrite)
1381{
1382 ACPIState *s = (ACPIState *)pvUser;
1383
1384 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1385
1386 if (cb == 4 && u32 == 0xbadc0de)
1387 {
1388 switch (s->uSystemInfoIndex)
1389 {
1390 case SYSTEM_INFO_INDEX_INVALID:
1391 s->u8IndexShift = 0;
1392 break;
1393
1394 case SYSTEM_INFO_INDEX_VALID:
1395 s->u8IndexShift = 2;
1396 break;
1397
1398 default:
1399 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1400 Port, cb, u32, s->uSystemInfoIndex));
1401 break;
1402 }
1403 }
1404 else
1405 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1406 return VINF_SUCCESS;
1407}
1408
1409/* IO Helpers */
1410IO_READ_PROTO (acpiPm1aEnRead)
1411{
1412 switch (cb)
1413 {
1414 case 2:
1415 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1416 break;
1417 default:
1418 return VERR_IOM_IOPORT_UNUSED;
1419 }
1420 return VINF_SUCCESS;
1421}
1422
1423IO_READ_PROTO (acpiPm1aStsRead)
1424{
1425 switch (cb)
1426 {
1427 case 2:
1428 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1429 break;
1430 default:
1431 return VERR_IOM_IOPORT_UNUSED;
1432 }
1433 return VINF_SUCCESS;
1434}
1435
1436IO_READ_PROTO (acpiPm1aCtlRead)
1437{
1438 switch (cb)
1439 {
1440 case 2:
1441 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1442 break;
1443 default:
1444 return VERR_IOM_IOPORT_UNUSED;
1445 }
1446 return VINF_SUCCESS;
1447}
1448
1449IO_WRITE_PROTO (acpiPM1aEnWrite)
1450{
1451 switch (cb)
1452 {
1453 case 2:
1454 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1455 break;
1456 default:
1457 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1458 break;
1459 }
1460 return VINF_SUCCESS;
1461}
1462
1463IO_WRITE_PROTO (acpiPM1aStsWrite)
1464{
1465 switch (cb)
1466 {
1467 case 2:
1468 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1469 break;
1470 default:
1471 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1472 break;
1473 }
1474 return VINF_SUCCESS;
1475}
1476
1477IO_WRITE_PROTO (acpiPM1aCtlWrite)
1478{
1479 switch (cb)
1480 {
1481 case 2:
1482 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1483 default:
1484 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1485 break;
1486 }
1487 return VINF_SUCCESS;
1488}
1489
1490#endif /* IN_RING3 */
1491
1492/**
1493 * PMTMR readable from host/guest.
1494 */
1495IO_READ_PROTO (acpiPMTmrRead)
1496{
1497 if (cb == 4)
1498 {
1499 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1500 int64_t now = TMTimerGet (s->CTX_SUFF(ts));
1501 int64_t elapsed = now - s->pm_timer_initial;
1502
1503 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTX_SUFF(ts)));
1504 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1505 return VINF_SUCCESS;
1506 }
1507 return VERR_IOM_IOPORT_UNUSED;
1508}
1509
1510#ifdef IN_RING3
1511
1512IO_READ_PROTO (acpiGpe0StsRead)
1513{
1514 switch (cb)
1515 {
1516 case 1:
1517 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1518 break;
1519 default:
1520 return VERR_IOM_IOPORT_UNUSED;
1521 }
1522 return VINF_SUCCESS;
1523}
1524
1525IO_READ_PROTO (acpiGpe0EnRead)
1526{
1527 switch (cb)
1528 {
1529 case 1:
1530 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1531 break;
1532 default:
1533 return VERR_IOM_IOPORT_UNUSED;
1534 }
1535 return VINF_SUCCESS;
1536}
1537
1538IO_WRITE_PROTO (acpiGpe0StsWrite)
1539{
1540 switch (cb)
1541 {
1542 case 1:
1543 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1544 break;
1545 default:
1546 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1547 break;
1548 }
1549 return VINF_SUCCESS;
1550}
1551
1552IO_WRITE_PROTO (acpiGpe0EnWrite)
1553{
1554 switch (cb)
1555 {
1556 case 1:
1557 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1558 break;
1559 default:
1560 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1561 break;
1562 }
1563 return VINF_SUCCESS;
1564}
1565
1566IO_WRITE_PROTO (acpiSmiWrite)
1567{
1568 switch (cb)
1569 {
1570 case 1:
1571 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1572 break;
1573 default:
1574 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1575 break;
1576 }
1577 return VINF_SUCCESS;
1578}
1579
1580IO_WRITE_PROTO (acpiResetWrite)
1581{
1582 switch (cb)
1583 {
1584 case 1:
1585 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1586 default:
1587 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1588 break;
1589 }
1590 return VINF_SUCCESS;
1591}
1592
1593#ifdef DEBUG_ACPI
1594
1595IO_WRITE_PROTO (acpiDhexWrite)
1596{
1597 switch (cb)
1598 {
1599 case 1:
1600 Log (("%#x\n", u32 & 0xff));
1601 break;
1602 case 2:
1603 Log (("%#6x\n", u32 & 0xffff));
1604 case 4:
1605 Log (("%#10x\n", u32));
1606 break;
1607 default:
1608 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1609 break;
1610 }
1611 return VINF_SUCCESS;
1612}
1613
1614IO_WRITE_PROTO (acpiDchrWrite)
1615{
1616 switch (cb)
1617 {
1618 case 1:
1619 Log (("%c", u32 & 0xff));
1620 break;
1621 default:
1622 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1623 break;
1624 }
1625 return VINF_SUCCESS;
1626}
1627
1628#endif /* DEBUG_ACPI */
1629
1630
1631/**
1632 * Saved state structure description.
1633 */
1634static const SSMFIELD g_AcpiSavedStateFields[] =
1635{
1636 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1637 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1638 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1639 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1640 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1641 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1642 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1643 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1644 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1645 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1646 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1647 SSMFIELD_ENTRY (ACPIState, uSleepState),
1648 SSMFIELD_ENTRY_TERM ()
1649};
1650
1651static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1652{
1653 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1654 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1655}
1656
1657static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1658 uint32_t u32Version)
1659{
1660 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1661 int rc;
1662
1663 if (u32Version != 4)
1664 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1665
1666 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1667 if (RT_SUCCESS (rc))
1668 {
1669 acpiFetchBatteryStatus (s);
1670 acpiFetchBatteryInfo (s);
1671 acpiPMTimerReset (s);
1672 }
1673 return rc;
1674}
1675
1676/**
1677 * Queries an interface to the driver.
1678 *
1679 * @returns Pointer to interface.
1680 * @returns NULL if the interface was not supported by the driver.
1681 * @param pInterface Pointer to this interface structure.
1682 * @param enmInterface The requested interface identification.
1683 * @thread Any thread.
1684 */
1685static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1686{
1687 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1688 switch (enmInterface)
1689 {
1690 case PDMINTERFACE_BASE:
1691 return &pThis->IBase;
1692 case PDMINTERFACE_ACPI_PORT:
1693 return &pThis->IACPIPort;
1694 default:
1695 return NULL;
1696 }
1697}
1698
1699/**
1700 * Create the ACPI tables.
1701 */
1702static int acpiPlantTables (ACPIState *s)
1703{
1704 int rc;
1705 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1706 uint32_t addend = 0;
1707 RTGCPHYS32 rsdt_addrs[4];
1708 uint32_t cAddr;
1709 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1710 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1711
1712 cAddr = 1; /* FADT */
1713 if (s->u8UseIOApic)
1714 cAddr++; /* MADT */
1715
1716 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1717 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1718
1719 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1720 if (RT_FAILURE (rc))
1721 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1722 N_("Configuration error: Querying "
1723 "\"RamSize\" as integer failed"));
1724
1725 if (s->u64RamSize > (0xffffffff - 0x10000))
1726 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1727 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1728 "value is 4095MB"));
1729 rsdt_addr = 0;
1730 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1731 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1732 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1733 if (s->u8UseIOApic)
1734 {
1735 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1736#ifdef VBOX_WITH_SMP_GUESTS
1737 /**
1738 * @todo nike: maybe some refactoring needed to compute tables layout,
1739 * but as this code is executed only once it doesn't make sense to optimize much
1740 */
1741 dsdt_addr = RT_ALIGN_32 (apic_addr + AcpiTableMADT::sizeFor(s), 16);
1742#else
1743 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1744#endif
1745 }
1746 else
1747 {
1748 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1749 }
1750
1751 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1752 if (last_addr > 0x10000)
1753 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1754 N_("Error: ACPI tables > 64KB"));
1755
1756 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1757 addend = (uint32_t) s->u64RamSize - 0x10000;
1758 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1759 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1760 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1761 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1762 acpiSetupDSDT (s, dsdt_addr + addend);
1763 acpiSetupFACS (s, facs_addr + addend);
1764 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1765
1766 rsdt_addrs[0] = fadt_addr + addend;
1767 if (s->u8UseIOApic)
1768 {
1769 acpiSetupMADT (s, apic_addr + addend);
1770 rsdt_addrs[1] = apic_addr + addend;
1771 }
1772
1773 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1774 if (RT_FAILURE(rc))
1775 return rc;
1776 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1777}
1778
1779/**
1780 * Construct a device instance for a VM.
1781 *
1782 * @returns VBox status.
1783 * @param pDevIns The device instance data.
1784 * If the registration structure is needed, pDevIns->pDevReg points to it.
1785 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1786 * The device number is also found in pDevIns->iInstance, but since it's
1787 * likely to be freqently used PDM passes it as parameter.
1788 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1789 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1790 * iInstance it's expected to be used a bit in this function.
1791 */
1792static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1793{
1794 int rc;
1795 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1796 uint32_t rsdp_addr;
1797 PCIDevice *dev;
1798 bool fGCEnabled;
1799 bool fR0Enabled;
1800
1801 /* Validate and read the configuration. */
1802 if (!CFGMR3AreValuesValid (pCfgHandle,
1803 "RamSize\0"
1804 "IOAPIC\0"
1805 "NumCPUs\0"
1806 "GCEnabled\0"
1807 "R0Enabled\0"
1808 "HpetEnabled\0"
1809 "SmcEnabled\0"
1810 "FdcEnabled\0"
1811 ))
1812 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1813 N_("Configuration error: Invalid config key for ACPI device"));
1814
1815 s->pDevIns = pDevIns;
1816
1817 /* query whether we are supposed to present an IOAPIC */
1818 rc = CFGMR3QueryU8Def (pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1819 if (RT_FAILURE (rc))
1820 return PDMDEV_SET_ERROR(pDevIns, rc,
1821 N_("Configuration error: Failed to read \"IOAPIC\""));
1822
1823 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1824 if (RT_FAILURE(rc))
1825 return PDMDEV_SET_ERROR(pDevIns, rc,
1826 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1827
1828 /* query whether we are supposed to present an FDC controller */
1829 rc = CFGMR3QueryBoolDef (pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1830 if (RT_FAILURE (rc))
1831 return PDMDEV_SET_ERROR(pDevIns, rc,
1832 N_("Configuration error: Failed to read \"FdcEnabled\""));
1833
1834 /* query whether we are supposed to present HPET */
1835 rc = CFGMR3QueryBoolDef (pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1836 if (RT_FAILURE(rc))
1837 return PDMDEV_SET_ERROR(pDevIns, rc,
1838 N_("Configuration error: Failed to read \"HpetEnabled\""));
1839 /* query whether we are supposed to present SMC */
1840 rc = CFGMR3QueryBoolDef (pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1841 if (RT_FAILURE(rc))
1842 return PDMDEV_SET_ERROR(pDevIns, rc,
1843 N_("Configuration error: Failed to read \"SmcEnabled\""));
1844 /** @todo: a bit of hack: if we have SMC, also show CPU object in ACPI tables */
1845 s->fShowCpu = s->fUseSmc;
1846
1847 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1848 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1849 fGCEnabled = true;
1850 else if (RT_FAILURE (rc))
1851 return PDMDEV_SET_ERROR(pDevIns, rc,
1852 N_("Configuration error: Failed to read \"GCEnabled\""));
1853
1854 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1855 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1856 fR0Enabled = true;
1857 else if (RT_FAILURE(rc))
1858 return PDMDEV_SET_ERROR(pDevIns, rc,
1859 N_("configuration error: failed to read R0Enabled as boolean"));
1860
1861 /* */
1862 rsdp_addr = find_rsdp_space ();
1863 if (!rsdp_addr)
1864 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1865 N_("Can not find space for RSDP. ACPI is disabled"));
1866
1867 rc = acpiPlantTables (s);
1868 if (RT_FAILURE (rc))
1869 return rc;
1870
1871 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1872 if (RT_FAILURE (rc))
1873 return rc;
1874
1875#define R(addr, cnt, writer, reader, description) \
1876 do { \
1877 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1878 NULL, NULL, description); \
1879 if (RT_FAILURE (rc)) \
1880 return rc; \
1881 } while (0)
1882#define L (GPE0_BLK_LEN / 2)
1883
1884 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1885 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1886 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1887 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1888 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1889#ifdef DEBUG_ACPI
1890 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1891 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1892#endif
1893 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1894 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1895 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1896 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1897 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1898 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1899 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1900#undef L
1901#undef R
1902
1903 /* register GC stuff */
1904 if (fGCEnabled)
1905 {
1906 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1907 NULL, NULL, "ACPI PM Timer");
1908 AssertRCReturn(rc, rc);
1909 }
1910
1911 /* register R0 stuff */
1912 if (fR0Enabled)
1913 {
1914 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1915 NULL, NULL, "ACPI PM Timer");
1916 AssertRCReturn(rc, rc);
1917 }
1918
1919 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1920 if (RT_FAILURE(rc))
1921 {
1922 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1923 return rc;
1924 }
1925
1926 s->tsR0 = TMTimerR0Ptr (s->tsR3);
1927 s->tsRC = TMTimerRCPtr (s->tsR3);
1928 s->pm_timer_initial = TMTimerGet (s->tsR3);
1929 acpiPMTimerReset (s);
1930
1931 dev = &s->dev;
1932 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1933 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1934
1935 dev->config[0x04] = 0x01; /* command */
1936 dev->config[0x05] = 0x00;
1937
1938 dev->config[0x06] = 0x80; /* status */
1939 dev->config[0x07] = 0x02;
1940 dev->config[0x08] = 0x08;
1941 dev->config[0x09] = 0x00;
1942
1943 dev->config[0x0a] = 0x80;
1944 dev->config[0x0b] = 0x06;
1945
1946 dev->config[0x0e] = 0x80;
1947 dev->config[0x0f] = 0x00;
1948
1949#if 0 /* The ACPI controller usually has no subsystem ID. */
1950 dev->config[0x2c] = 0x86;
1951 dev->config[0x2d] = 0x80;
1952 dev->config[0x2e] = 0x00;
1953 dev->config[0x2f] = 0x00;
1954#endif
1955 dev->config[0x3c] = SCI_INT;
1956
1957 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1958 if (RT_FAILURE (rc))
1959 return rc;
1960
1961 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1962 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1963 if (RT_FAILURE(rc))
1964 return rc;
1965
1966 /*
1967 * Interfaces
1968 */
1969 /* IBase */
1970 s->IBase.pfnQueryInterface = acpiQueryInterface;
1971 /* IACPIPort */
1972 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1973 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1974 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1975 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
1976
1977 /*
1978 * Get the corresponding connector interface
1979 */
1980 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1981 if (RT_SUCCESS (rc))
1982 {
1983 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
1984 PDMINTERFACE_ACPI_CONNECTOR);
1985 if (!s->pDrv)
1986 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
1987 N_("LUN #0 doesn't have an ACPI connector interface"));
1988 }
1989 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
1990 {
1991 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
1992 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
1993 rc = VINF_SUCCESS;
1994 }
1995 else
1996 return PDMDEV_SET_ERROR(pDevIns, rc,
1997 N_("Failed to attach LUN #0"));
1998
1999 return rc;
2000}
2001
2002/**
2003 * Relocates the GC pointer members.
2004 */
2005static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2006{
2007 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
2008 s->tsRC = TMTimerRCPtr (s->CTX_SUFF(ts));
2009}
2010
2011static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
2012{
2013 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
2014
2015 s->pm1a_en = 0;
2016 s->pm1a_sts = 0;
2017 s->pm1a_ctl = 0;
2018 s->pm_timer_initial = TMTimerGet (s->CTX_SUFF(ts));
2019 acpiPMTimerReset(s);
2020 s->uBatteryIndex = 0;
2021 s->uSystemInfoIndex = 0;
2022 s->gpe0_en = 0;
2023 s->gpe0_sts = 0;
2024 s->uSleepState = 0;
2025
2026 acpiPlantTables(s);
2027}
2028
2029/**
2030 * The device registration structure.
2031 */
2032const PDMDEVREG g_DeviceACPI =
2033{
2034 /* u32Version */
2035 PDM_DEVREG_VERSION,
2036 /* szDeviceName */
2037 "acpi",
2038 /* szRCMod */
2039 "VBoxDDGC.gc",
2040 /* szR0Mod */
2041 "VBoxDDR0.r0",
2042 /* pszDescription */
2043 "Advanced Configuration and Power Interface",
2044 /* fFlags */
2045 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2046 /* fClass */
2047 PDM_DEVREG_CLASS_ACPI,
2048 /* cMaxInstances */
2049 ~0,
2050 /* cbInstance */
2051 sizeof(ACPIState),
2052 /* pfnConstruct */
2053 acpiConstruct,
2054 /* pfnDestruct */
2055 NULL,
2056 /* pfnRelocate */
2057 acpiRelocate,
2058 /* pfnIOCtl */
2059 NULL,
2060 /* pfnPowerOn */
2061 NULL,
2062 /* pfnReset */
2063 acpiReset,
2064 /* pfnSuspend */
2065 NULL,
2066 /* pfnResume */
2067 NULL,
2068 /* pfnAttach */
2069 NULL,
2070 /* pfnDetach */
2071 NULL,
2072 /* pfnQueryInterface. */
2073 NULL,
2074 /* pfnInitComplete */
2075 NULL,
2076 /* pfnPowerOff */
2077 NULL,
2078 /* pfnSoftReset */
2079 NULL,
2080 /* u32VersionEnd */
2081 PDM_DEVREG_VERSION
2082};
2083
2084#endif /* IN_RING3 */
2085#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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