VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 17555

Last change on this file since 17555 was 17542, checked in by vboxsync, 16 years ago

Main,VBoxBFE,DevPcBios,DevACPI: RamHoleSize.
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1/* $Id: DevACPI.cpp 17542 2009-03-08 08:52:07Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#define LOG_GROUP LOG_GROUP_DEV_ACPI
23#include <VBox/pdmdev.h>
24#include <VBox/log.h>
25#include <VBox/param.h>
26#include <iprt/assert.h>
27#include <iprt/asm.h>
28#ifdef IN_RING3
29# include <iprt/alloc.h>
30# include <iprt/string.h>
31#endif /* IN_RING3 */
32
33#include "../Builtins.h"
34
35#ifdef LOG_ENABLED
36# define DEBUG_ACPI
37#endif
38
39/* the compiled DSL */
40#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
41#include <vboxaml.hex>
42#endif /* !IN_RING3 */
43
44#define IO_READ_PROTO(name) \
45 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
46 RTIOPORT Port, uint32_t *pu32, unsigned cb)
47
48#define IO_WRITE_PROTO(name) \
49 PDMBOTHCBDECL(int) name (PPDMDEVINS pDevIns, void *pvUser, \
50 RTIOPORT Port, uint32_t u32, unsigned cb)
51
52#define DEBUG_HEX 0x3000
53#define DEBUG_CHR 0x3001
54
55#define PM_TMR_FREQ 3579545
56#define PM1a_EVT_BLK 0x00004000
57#define PM1b_EVT_BLK 0x00000000 /**< not supported */
58#define PM1a_CTL_BLK 0x00004004
59#define PM1b_CTL_BLK 0x00000000 /**< not supported */
60#define PM2_CTL_BLK 0x00000000 /**< not supported */
61#define PM_TMR_BLK 0x00004008
62#define GPE0_BLK 0x00004020
63#define GPE1_BLK 0x00000000 /**< not supported */
64#define BAT_INDEX 0x00004040
65#define BAT_DATA 0x00004044
66#define SYSI_INDEX 0x00004048
67#define SYSI_DATA 0x0000404c
68#define ACPI_RESET_BLK 0x00004050
69
70/* PM1x status register bits */
71#define TMR_STS RT_BIT(0)
72#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
73#define BM_STS RT_BIT(4)
74#define GBL_STS RT_BIT(5)
75#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
76#define PWRBTN_STS RT_BIT(8)
77#define SLPBTN_STS RT_BIT(9)
78#define RTC_STS RT_BIT(10)
79#define IGN_STS RT_BIT(11)
80#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
81#define WAK_STS RT_BIT(15)
82#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
83
84/* PM1x enable register bits */
85#define TMR_EN RT_BIT(0)
86#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
87#define GBL_EN RT_BIT(5)
88#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
89#define PWRBTN_EN RT_BIT(8)
90#define SLPBTN_EN RT_BIT(9)
91#define RTC_EN RT_BIT(10)
92#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
93#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
94#define IGN_EN 0
95
96/* PM1x control register bits */
97#define SCI_EN RT_BIT(0)
98#define BM_RLD RT_BIT(1)
99#define GBL_RLS RT_BIT(2)
100#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
101#define IGN_CNT RT_BIT(9)
102#define SLP_TYPx_SHIFT 10
103#define SLP_TYPx_MASK 7
104#define SLP_EN RT_BIT(13)
105#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
106#define RSR_CNT (RSR1_CNT | RSR2_CNT)
107
108#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
109
110enum
111{
112 BAT_STATUS_STATE = 0x00, /**< BST battery state */
113 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
114 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
115 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
116 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
117 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
118 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
119 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
120 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
121 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
122 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
123 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
124 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
125 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
126 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
127 BAT_INDEX_LAST
128};
129
130enum
131{
132 SYSTEM_INFO_INDEX_MEMORY_LENGTH = 0,
133 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
134 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
135 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
136 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
137 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
138 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
139 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
140 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
141 SYSTEM_INFO_INDEX_LAST = 9,
142 SYSTEM_INFO_INDEX_INVALID = 0x80,
143 SYSTEM_INFO_INDEX_VALID = 0x200
144};
145
146#define AC_OFFLINE 0
147#define AC_ONLINE 1
148
149#define BAT_TECH_PRIMARY 1
150#define BAT_TECH_SECONDARY 2
151
152#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
153#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
154#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
155#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
156#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
157
158struct ACPIState
159{
160 PCIDevice dev;
161 uint16_t pm1a_en;
162 uint16_t pm1a_sts;
163 uint16_t pm1a_ctl;
164 /** Number of logical CPUs in guest */
165 uint16_t cCpus;
166 int64_t pm_timer_initial;
167 PTMTIMERR3 tsR3;
168 PTMTIMERR0 tsR0;
169 PTMTIMERRC tsRC;
170
171 uint32_t gpe0_en;
172 uint32_t gpe0_sts;
173
174 unsigned int uBatteryIndex;
175 uint32_t au8BatteryInfo[13];
176
177 unsigned int uSystemInfoIndex;
178 uint64_t u64RamSize;
179
180 /** Current ACPI S* state. We support S0 and S5 */
181 uint32_t uSleepState;
182 uint8_t au8RSDPPage[0x1000];
183 /** This is a workaround for incorrect index field handling by Intels ACPICA.
184 * The system info _INI method writes to offset 0x200. We either observe a
185 * write request to index 0x80 (in that case we don't change the index) or a
186 * write request to offset 0x200 (in that case we divide the index value by
187 * 4. Note that the _STA method is sometimes called prior to the _INI method
188 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
189 * acpiBatIndexWrite() for handling this. */
190 uint8_t u8IndexShift;
191 /** provide an I/O-APIC */
192 uint8_t u8UseIOApic;
193 /** provide a floppy controller */
194 bool fUseFdc;
195 /** If High Precision Event Timer device should be supported */
196 bool fUseHpet;
197 /** If System Management Controller device should be supported */
198 bool fUseSmc;
199 /** the guest handled the last power button event */
200 bool fPowerButtonHandled;
201 /** If ACPI CPU device should be shown */
202 bool fShowCpu;
203 /** Aligning IBase. */
204 bool afAlignment[2];
205
206 /** ACPI port base interface. */
207 PDMIBASE IBase;
208 /** ACPI port interface. */
209 PDMIACPIPORT IACPIPort;
210 /** Pointer to the device instance. */
211 PPDMDEVINSR3 pDevIns;
212 /** Pointer to the driver base interface */
213 R3PTRTYPE(PPDMIBASE) pDrvBase;
214 /** Pointer to the driver connector interface */
215 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
216};
217
218#pragma pack(1)
219
220/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
221struct ACPIGENADDR
222{
223 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
224 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
225 uint8_t u8RegisterBitOffset; /**< bit offset of register */
226 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
227 uint64_t u64Address; /**< 64-bit address of register */
228};
229AssertCompileSize(ACPIGENADDR, 12);
230
231/** Root System Description Pointer */
232struct ACPITBLRSDP
233{
234 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
235 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
236 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
237 uint8_t u8Revision; /**< revision number, currently 2 */
238#define ACPI_REVISION 2 /**< ACPI 3.0 */
239 uint32_t u32RSDT; /**< phys addr of RSDT */
240 uint32_t u32Length; /**< bytes of this table */
241 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
242 uint8_t u8ExtChecksum; /**< checksum of entire table */
243 uint8_t u8Reserved[3]; /**< reserved */
244};
245AssertCompileSize(ACPITBLRSDP, 36);
246
247/** System Description Table Header */
248struct ACPITBLHEADER
249{
250 uint8_t au8Signature[4]; /**< table identifier */
251 uint32_t u32Length; /**< length of the table including header */
252 uint8_t u8Revision; /**< revision number */
253 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
254 uint8_t au8OemId[6]; /**< OEM-supplied string */
255 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
256 uint32_t u32OemRevision; /**< OEM-supplied revision number */
257 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
258 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
259};
260AssertCompileSize(ACPITBLHEADER, 36);
261
262/** Root System Description Table */
263struct ACPITBLRSDT
264{
265 ACPITBLHEADER header;
266 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
267};
268AssertCompileSize(ACPITBLRSDT, 40);
269
270/** Extended System Description Table */
271struct ACPITBLXSDT
272{
273 ACPITBLHEADER header;
274 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
275};
276AssertCompileSize(ACPITBLXSDT, 44);
277
278/** Fixed ACPI Description Table */
279struct ACPITBLFADT
280{
281 ACPITBLHEADER header;
282 uint32_t u32FACS; /**< phys. address of FACS */
283 uint32_t u32DSDT; /**< phys. address of DSDT */
284 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
285#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
286#define INT_MODEL_MULTIPLE_APIC 2
287 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
288 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
289#define SCI_INT 9
290 uint32_t u32SMICmd; /**< system port address of SMI command port */
291#define SMI_CMD 0x0000442e
292 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
293#define ACPI_ENABLE 0xa1
294 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
295#define ACPI_DISABLE 0xa0
296 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
297 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
298 state control responsibility */
299 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
300 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
301 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
302 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
303 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
304 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
305 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
306 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
307 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
308 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
309 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
310 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
311 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
312#define GPE0_BLK_LEN 2
313 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
314#define GPE1_BLK_LEN 0
315 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
316#define GPE1_BASE 0
317 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
318 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
319#define P_LVL2_LAT 101 /**< C2 state not supported */
320 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
321#define P_LVL3_LAT 1001 /**< C3 state not supported */
322 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
323 lines from any processors memory caches */
324#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
325 uint16_t u16FlushStride; /**< cache line width */
326#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
327 uint8_t u8DutyOffset;
328 uint8_t u8DutyWidth;
329 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
330 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
331 uint8_t u8Century; /**< RTC CMOS RAM index of century */
332 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
333#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
334 (COM too?) */
335#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
336#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
337 uint8_t u8Must0_0; /**< must be 0 */
338 uint32_t u32Flags; /**< fixed feature flags */
339#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
340#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
341#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
342#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
343#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
344#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
345#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
346#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
347#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
348#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
349#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
350#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
351#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
352#define FADT_FL_CPU_SW_SLP RT_BIT(13)
353#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
354#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
355#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
356#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
357#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
358#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
359 ACPIGENADDR ResetReg; /**< ext addr of reset register */
360 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
361#define ACPI_RESET_REG_VAL 0x10
362 uint8_t au8Must0_1[3]; /**< must be 0 */
363 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
364 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
365 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
366 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
367 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
368 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
369 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
370 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
371 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
372 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
373};
374AssertCompileSize(ACPITBLFADT, 244);
375
376/** Firmware ACPI Control Structure */
377struct ACPITBLFACS
378{
379 uint8_t au8Signature[4]; /**< 'FACS' */
380 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
381 uint32_t u32HWSignature; /**< systems HW signature at last boot */
382 uint32_t u32FWVector; /**< address of waking vector */
383 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
384 uint32_t u32Flags; /**< FACS flags */
385 uint64_t u64X_FWVector; /**< 64-bit waking vector */
386 uint8_t u8Version; /**< version of this table */
387 uint8_t au8Reserved[31]; /**< zero */
388};
389AssertCompileSize(ACPITBLFACS, 64);
390
391/** Processor Local APIC Structure */
392struct ACPITBLLAPIC
393{
394 uint8_t u8Type; /**< 0 = LAPIC */
395 uint8_t u8Length; /**< 8 */
396 uint8_t u8ProcId; /**< processor ID */
397 uint8_t u8ApicId; /**< local APIC ID */
398 uint32_t u32Flags; /**< Flags */
399#define LAPIC_ENABLED 0x1
400};
401AssertCompileSize(ACPITBLLAPIC, 8);
402
403/** I/O APIC Structure */
404struct ACPITBLIOAPIC
405{
406 uint8_t u8Type; /**< 1 == I/O APIC */
407 uint8_t u8Length; /**< 12 */
408 uint8_t u8IOApicId; /**< I/O APIC ID */
409 uint8_t u8Reserved; /**< 0 */
410 uint32_t u32Address; /**< phys address to access I/O APIC */
411 uint32_t u32GSIB; /**< global system interrupt number to start */
412};
413AssertCompileSize(ACPITBLIOAPIC, 12);
414
415#ifdef VBOX_WITH_SMP_GUESTS
416#ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
417
418# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
419
420/**
421 * Multiple APIC Description Table.
422 *
423 * This structure looks somewhat convoluted due layout of MADT table in MP case.
424 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
425 * use regular C structure and proxy to raw memory instead.
426 */
427class AcpiTableMADT
428{
429 /**
430 * All actual data stored in dynamically allocated memory pointed by this field.
431 */
432 uint8_t* pData;
433 /**
434 * Number of CPU entries in this MADT.
435 */
436 uint32_t cCpus;
437
438 public:
439 /**
440 * Address of ACPI header
441 */
442 inline ACPITBLHEADER* header_addr() const
443 {
444 return (ACPITBLHEADER*)pData;
445 }
446
447 /**
448 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
449 * although address is the same for all of them.
450 */
451 inline uint32_t* u32LAPIC_addr() const
452 {
453 return (uint32_t*)(header_addr() + 1);
454 }
455
456 /**
457 * Address of APIC flags
458 */
459 inline uint32_t* u32Flags_addr() const
460 {
461 return (uint32_t*)(u32LAPIC_addr() + 1);
462 }
463
464 /**
465 * Address of per-CPU LAPIC descriptions
466 */
467 inline ACPITBLLAPIC* LApics_addr() const
468 {
469 return (ACPITBLLAPIC*)(u32Flags_addr() + 1);
470 }
471
472 /**
473 * Address of IO APIC description
474 */
475 inline ACPITBLIOAPIC* IOApic_addr() const
476 {
477 return (ACPITBLIOAPIC*)(LApics_addr() + cCpus);
478 }
479
480 /**
481 * Size of MADT.
482 * Note that this function assumes IOApic to be the last field in structure.
483 */
484 inline uint32_t size() const
485 {
486 return (uint8_t*)(IOApic_addr() + 1)-(uint8_t*)header_addr();
487 }
488
489 /**
490 * Raw data of MADT.
491 */
492 inline const uint8_t* data() const
493 {
494 return pData;
495 }
496
497 /**
498 * Size of MADT for given ACPI config, useful to compute layout.
499 */
500 static uint32_t sizeFor(ACPIState *s)
501 {
502 return AcpiTableMADT(s->cCpus).size();
503 }
504
505 /*
506 * Constructor, only works in Ring 3, doesn't look like a big deal.
507 */
508 AcpiTableMADT(uint16_t cpus)
509 {
510 cCpus = cpus;
511 pData = 0;
512 uint32_t sSize = size();
513 pData = (uint8_t*)RTMemAllocZ(sSize);
514 }
515
516 ~AcpiTableMADT()
517 {
518 RTMemFree(pData);
519 }
520};
521#endif /* IN_RING3 */
522
523#else /* !VBOX_WITH_SMP_GUESTS */
524/** Multiple APIC Description Table */
525struct ACPITBLMADT
526{
527 ACPITBLHEADER header;
528 uint32_t u32LAPIC; /**< local APIC address */
529 uint32_t u32Flags; /**< Flags */
530#define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
531 ACPITBLLAPIC LApic;
532 ACPITBLIOAPIC IOApic;
533};
534AssertCompileSize(ACPITBLMADT, 64);
535#endif /* !VBOX_WITH_SMP_GUESTS */
536
537#pragma pack()
538
539
540#ifndef VBOX_DEVICE_STRUCT_TESTCASE
541__BEGIN_DECLS
542IO_READ_PROTO (acpiPMTmrRead);
543#ifdef IN_RING3
544IO_READ_PROTO (acpiPm1aEnRead);
545IO_WRITE_PROTO (acpiPM1aEnWrite);
546IO_READ_PROTO (acpiPm1aStsRead);
547IO_WRITE_PROTO (acpiPM1aStsWrite);
548IO_READ_PROTO (acpiPm1aCtlRead);
549IO_WRITE_PROTO (acpiPM1aCtlWrite);
550IO_WRITE_PROTO (acpiSmiWrite);
551IO_WRITE_PROTO (acpiBatIndexWrite);
552IO_READ_PROTO (acpiBatDataRead);
553IO_READ_PROTO (acpiSysInfoDataRead);
554IO_WRITE_PROTO (acpiSysInfoDataWrite);
555IO_READ_PROTO (acpiGpe0EnRead);
556IO_WRITE_PROTO (acpiGpe0EnWrite);
557IO_READ_PROTO (acpiGpe0StsRead);
558IO_WRITE_PROTO (acpiGpe0StsWrite);
559IO_WRITE_PROTO (acpiResetWrite);
560# ifdef DEBUG_ACPI
561IO_WRITE_PROTO (acpiDhexWrite);
562IO_WRITE_PROTO (acpiDchrWrite);
563# endif
564#endif
565__END_DECLS
566
567#ifdef IN_RING3
568
569/* Simple acpiChecksum: all the bytes must add up to 0. */
570static uint8_t acpiChecksum (const uint8_t * const data, size_t len)
571{
572 uint8_t sum = 0;
573 for (size_t i = 0; i < len; ++i)
574 sum += data[i];
575 return -sum;
576}
577
578static void acpiPrepareHeader (ACPITBLHEADER *header, const char au8Signature[4],
579 uint32_t u32Length, uint8_t u8Revision)
580{
581 memcpy(header->au8Signature, au8Signature, 4);
582 header->u32Length = RT_H2LE_U32(u32Length);
583 header->u8Revision = u8Revision;
584 memcpy(header->au8OemId, "VBOX ", 6);
585 memcpy(header->au8OemTabId, "VBOX", 4);
586 memcpy(header->au8OemTabId+4, au8Signature, 4);
587 header->u32OemRevision = RT_H2LE_U32(1);
588 memcpy(header->au8CreatorId, "ASL ", 4);
589 header->u32CreatorRev = RT_H2LE_U32(0x61);
590}
591
592static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
593 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
594 uint8_t u8AccessSize, uint64_t u64Address)
595{
596 g->u8AddressSpaceId = u8AddressSpaceId;
597 g->u8RegisterBitWidth = u8RegisterBitWidth;
598 g->u8RegisterBitOffset = u8RegisterBitOffset;
599 g->u8AccessSize = u8AccessSize;
600 g->u64Address = RT_H2LE_U64(u64Address);
601}
602
603static void acpiPhyscpy (ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
604{
605 PDMDevHlpPhysWrite (s->pDevIns, dst, src, size);
606}
607
608/* Differentiated System Description Table (DSDT) */
609static void acpiSetupDSDT (ACPIState *s, RTGCPHYS32 addr)
610{
611 acpiPhyscpy (s, addr, AmlCode, sizeof(AmlCode));
612}
613
614/* Firmware ACPI Control Structure (FACS) */
615static void acpiSetupFACS (ACPIState *s, RTGCPHYS32 addr)
616{
617 ACPITBLFACS facs;
618
619 memset (&facs, 0, sizeof(facs));
620 memcpy (facs.au8Signature, "FACS", 4);
621 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
622 facs.u32HWSignature = RT_H2LE_U32(0);
623 facs.u32FWVector = RT_H2LE_U32(0);
624 facs.u32GlobalLock = RT_H2LE_U32(0);
625 facs.u32Flags = RT_H2LE_U32(0);
626 facs.u64X_FWVector = RT_H2LE_U64(0);
627 facs.u8Version = 1;
628
629 acpiPhyscpy (s, addr, (const uint8_t*)&facs, sizeof(facs));
630}
631
632/* Fixed ACPI Description Table (FADT aka FACP) */
633static void acpiSetupFADT (ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
634{
635 ACPITBLFADT fadt;
636
637 memset (&fadt, 0, sizeof(fadt));
638 acpiPrepareHeader (&fadt.header, "FACP", sizeof(fadt), 4);
639 fadt.u32FACS = RT_H2LE_U32(facs_addr);
640 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
641 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
642 fadt.u8PreferredPMProfile = 0; /* unspecified */
643 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
644 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
645 fadt.u8AcpiEnable = ACPI_ENABLE;
646 fadt.u8AcpiDisable = ACPI_DISABLE;
647 fadt.u8S4BIOSReq = 0;
648 fadt.u8PStateCnt = 0;
649 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
650 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
651 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
652 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
653 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
654 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
655 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
656 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
657 fadt.u8PM1EVTLEN = 4;
658 fadt.u8PM1CTLLEN = 2;
659 fadt.u8PM2CTLLEN = 0;
660 fadt.u8PMTMLEN = 4;
661 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
662 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
663 fadt.u8GPE1BASE = GPE1_BASE;
664 fadt.u8CSTCNT = 0;
665 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
666 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
667 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
668 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
669 fadt.u8DutyOffset = 0;
670 fadt.u8DutyWidth = 0;
671 fadt.u8DayAlarm = 0;
672 fadt.u8MonAlarm = 0;
673 fadt.u8Century = 0;
674 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
675 /** @note WBINVD is required for ACPI versions newer than 1.0 */
676 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
677 | FADT_FL_FIX_RTC
678 | FADT_FL_TMR_VAL_EXT);
679 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
680 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
681 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
682 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
683 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
684 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
685 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
686 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
687 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
688 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
689 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
690 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
691 fadt.header.u8Checksum = acpiChecksum ((uint8_t*)&fadt, sizeof(fadt));
692 acpiPhyscpy (s, addr, &fadt, sizeof(fadt));
693}
694
695/*
696 * Root System Description Table.
697 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
698 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
699 */
700static int acpiSetupRSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
701{
702 ACPITBLRSDT *rsdt;
703 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
704
705 rsdt = (ACPITBLRSDT*)RTMemAllocZ (size);
706 if (!rsdt)
707 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
708
709 acpiPrepareHeader (&rsdt->header, "RSDT", (uint32_t)size, 1);
710 for (unsigned int i = 0; i < nb_entries; ++i)
711 {
712 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
713 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
714 }
715 rsdt->header.u8Checksum = acpiChecksum ((uint8_t*)rsdt, size);
716 acpiPhyscpy (s, addr, rsdt, size);
717 RTMemFree (rsdt);
718 return VINF_SUCCESS;
719}
720
721/* Extended System Description Table. */
722static int acpiSetupXSDT (ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
723{
724 ACPITBLXSDT *xsdt;
725 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
726
727 xsdt = (ACPITBLXSDT*)RTMemAllocZ (size);
728 if (!xsdt)
729 return VERR_NO_TMP_MEMORY;
730
731 acpiPrepareHeader (&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
732 for (unsigned int i = 0; i < nb_entries; ++i)
733 {
734 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
735 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
736 }
737 xsdt->header.u8Checksum = acpiChecksum ((uint8_t*)xsdt, size);
738 acpiPhyscpy (s, addr, xsdt, size);
739 RTMemFree (xsdt);
740 return VINF_SUCCESS;
741}
742
743/* Root System Description Pointer (RSDP) */
744static void acpiSetupRSDP (ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
745{
746 memset(rsdp, 0, sizeof(*rsdp));
747
748 /* ACPI 1.0 part (RSDT */
749 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
750 memcpy(rsdp->au8OemId, "VBOX ", 6);
751 rsdp->u8Revision = ACPI_REVISION;
752 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
753 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
754
755 /* ACPI 2.0 part (XSDT) */
756 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
757 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
758 rsdp->u8ExtChecksum = acpiChecksum ((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
759}
760
761/* Multiple APIC Description Table. */
762/** @todo All hardcoded, should set this up based on the actual VM config!!!!! */
763/** @note APIC without IO-APIC hangs Windows Vista therefore we setup both */
764static void acpiSetupMADT (ACPIState *s, RTGCPHYS32 addr)
765{
766#ifdef VBOX_WITH_SMP_GUESTS
767 uint16_t cpus = s->cCpus;
768 AcpiTableMADT madt(cpus);
769
770 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
771
772 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
773 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
774
775 ACPITBLLAPIC* lapic = madt.LApics_addr();
776 for (uint16_t i = 0; i < cpus; i++)
777 {
778 lapic->u8Type = 0;
779 lapic->u8Length = sizeof(ACPITBLLAPIC);
780 lapic->u8ProcId = i;
781 lapic->u8ApicId = i;
782 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
783 lapic++;
784 }
785
786 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
787
788 ioapic->u8Type = 1;
789 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
790 ioapic->u8IOApicId = cpus;
791 ioapic->u8Reserved = 0;
792 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
793 ioapic->u32GSIB = RT_H2LE_U32(0);
794
795 madt.header_addr()->u8Checksum = acpiChecksum (madt.data(), madt.size());
796 acpiPhyscpy (s, addr, madt.data(), madt.size());
797
798#else /* !VBOX_WITH_SMP_GUESTS */
799 ACPITBLMADT madt;
800
801 /* Don't call this function if u8UseIOApic==false! */
802 Assert(s->u8UseIOApic);
803
804 memset(&madt, 0, sizeof(madt));
805 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
806
807 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
808 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
809
810 madt.LApic.u8Type = 0;
811 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
812 madt.LApic.u8ProcId = 0;
813 madt.LApic.u8ApicId = 0;
814 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
815
816 madt.IOApic.u8Type = 1;
817 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
818 madt.IOApic.u8IOApicId = 1;
819 madt.IOApic.u8Reserved = 0;
820 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
821 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
822
823 madt.header.u8Checksum = acpiChecksum ((uint8_t*)&madt, sizeof(madt));
824 acpiPhyscpy (s, addr, &madt, sizeof(madt));
825#endif /* !VBOX_WITH_SMP_GUESTS */
826}
827
828/* SCI IRQ */
829DECLINLINE(void) acpiSetIrq (ACPIState *s, int level)
830{
831 if (s->pm1a_ctl & SCI_EN)
832 PDMDevHlpPCISetIrq (s->pDevIns, -1, level);
833}
834
835DECLINLINE(uint32_t) pm1a_pure_en (uint32_t en)
836{
837 return en & ~(RSR_EN | IGN_EN);
838}
839
840DECLINLINE(uint32_t) pm1a_pure_sts (uint32_t sts)
841{
842 return sts & ~(RSR_STS | IGN_STS);
843}
844
845DECLINLINE(int) pm1a_level (ACPIState *s)
846{
847 return (pm1a_pure_en (s->pm1a_en) & pm1a_pure_sts (s->pm1a_sts)) != 0;
848}
849
850DECLINLINE(int) gpe0_level (ACPIState *s)
851{
852 return (s->gpe0_en & s->gpe0_sts) != 0;
853}
854
855static void update_pm1a (ACPIState *s, uint32_t sts, uint32_t en)
856{
857 int old_level, new_level;
858
859 if (gpe0_level (s))
860 return;
861
862 old_level = pm1a_level (s);
863 new_level = (pm1a_pure_en (en) & pm1a_pure_sts (sts)) != 0;
864
865 s->pm1a_en = en;
866 s->pm1a_sts = sts;
867
868 if (new_level != old_level)
869 acpiSetIrq (s, new_level);
870}
871
872static void update_gpe0 (ACPIState *s, uint32_t sts, uint32_t en)
873{
874 int old_level, new_level;
875
876 if (pm1a_level (s))
877 return;
878
879 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
880 new_level = (en & sts) != 0;
881
882 s->gpe0_en = en;
883 s->gpe0_sts = sts;
884
885 if (new_level != old_level)
886 acpiSetIrq (s, new_level);
887}
888
889static int acpiPowerDown (ACPIState *s)
890{
891 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
892 if (RT_FAILURE (rc))
893 AssertMsgFailed (("Could not power down the VM. rc = %Rrc\n", rc));
894 return rc;
895}
896
897/** Converts a ACPI port interface pointer to an ACPI state pointer. */
898#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
899
900/**
901 * Send an ACPI power off event.
902 *
903 * @returns VBox status code
904 * @param pInterface Pointer to the interface structure containing the called function pointer.
905 */
906static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
907{
908 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
909 s->fPowerButtonHandled = false;
910 update_pm1a (s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
911 return VINF_SUCCESS;
912}
913
914/**
915 * Check if the ACPI power button event was handled.
916 *
917 * @returns VBox status code
918 * @param pInterface Pointer to the interface structure containing the called function pointer.
919 * @param pfHandled Return true if the power button event was handled by the guest.
920 */
921static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
922{
923 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
924 *pfHandled = s->fPowerButtonHandled;
925 return VINF_SUCCESS;
926}
927
928/**
929 * Check if the Guest entered into G0 (working) or G1 (sleeping).
930 *
931 * @returns VBox status code
932 * @param pInterface Pointer to the interface structure containing the called function pointer.
933 * @param pfEntered Return true if the guest entered the ACPI mode.
934 */
935static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
936{
937 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
938 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
939 return VINF_SUCCESS;
940}
941
942/**
943 * Send an ACPI sleep button event.
944 *
945 * @returns VBox status code
946 * @param pInterface Pointer to the interface structure containing the called function pointer.
947 */
948static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
949{
950 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
951 update_pm1a (s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
952 return VINF_SUCCESS;
953}
954
955/* PM1a_EVT_BLK enable */
956static uint32_t acpiPm1aEnReadw (ACPIState *s, uint32_t addr)
957{
958 uint16_t val = s->pm1a_en;
959 Log (("acpi: acpiPm1aEnReadw -> %#x\n", val));
960 return val;
961}
962
963static void acpiPM1aEnWritew (ACPIState *s, uint32_t addr, uint32_t val)
964{
965 Log (("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
966 val &= ~(RSR_EN | IGN_EN);
967 update_pm1a (s, s->pm1a_sts, val);
968}
969
970/* PM1a_EVT_BLK status */
971static uint32_t acpiPm1aStsReadw (ACPIState *s, uint32_t addr)
972{
973 uint16_t val = s->pm1a_sts;
974 Log (("acpi: acpiPm1aStsReadw -> %#x\n", val));
975 return val;
976}
977
978static void acpiPM1aStsWritew (ACPIState *s, uint32_t addr, uint32_t val)
979{
980 Log (("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
981 if (val & PWRBTN_STS)
982 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
983 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
984 update_pm1a (s, val, s->pm1a_en);
985}
986
987/* PM1a_CTL_BLK */
988static uint32_t acpiPm1aCtlReadw (ACPIState *s, uint32_t addr)
989{
990 uint16_t val = s->pm1a_ctl;
991 Log (("acpi: acpiPm1aCtlReadw -> %#x\n", val));
992 return val;
993}
994
995static int acpiPM1aCtlWritew (ACPIState *s, uint32_t addr, uint32_t val)
996{
997 uint32_t uSleepState;
998
999 Log (("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
1000 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1001
1002 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1003 if (uSleepState != s->uSleepState)
1004 {
1005 s->uSleepState = uSleepState;
1006 switch (uSleepState)
1007 {
1008 case 0x00: /* S0 */
1009 break;
1010 case 0x05: /* S5 */
1011 LogRel (("Entering S5 (power down)\n"));
1012 return acpiPowerDown (s);
1013 default:
1014 AssertMsgFailed (("Unknown sleep state %#x\n", uSleepState));
1015 break;
1016 }
1017 }
1018 return VINF_SUCCESS;
1019}
1020
1021/* GPE0_BLK */
1022static uint32_t acpiGpe0EnReadb (ACPIState *s, uint32_t addr)
1023{
1024 uint8_t val = s->gpe0_en;
1025 Log (("acpi: acpiGpe0EnReadl -> %#x\n", val));
1026 return val;
1027}
1028
1029static void acpiGpe0EnWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1030{
1031 Log (("acpi: acpiGpe0EnWritel <- %#x\n", val));
1032 update_gpe0 (s, s->gpe0_sts, val);
1033}
1034
1035static uint32_t acpiGpe0StsReadb (ACPIState *s, uint32_t addr)
1036{
1037 uint8_t val = s->gpe0_sts;
1038 Log (("acpi: acpiGpe0StsReadl -> %#x\n", val));
1039 return val;
1040}
1041
1042static void acpiGpe0StsWriteb (ACPIState *s, uint32_t addr, uint32_t val)
1043{
1044 val = s->gpe0_sts & ~val;
1045 update_gpe0 (s, val, s->gpe0_en);
1046 Log (("acpi: acpiGpe0StsWritel <- %#x\n", val));
1047}
1048
1049static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1050{
1051 int rc = VINF_SUCCESS;
1052
1053 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1054 if (val == ACPI_RESET_REG_VAL)
1055 {
1056# ifndef IN_RING3
1057 rc = VINF_IOM_HC_IOPORT_WRITE;
1058# else /* IN_RING3 */
1059 rc = PDMDevHlpVMReset(s->pDevIns);
1060# endif /* !IN_RING3 */
1061 }
1062 return rc;
1063}
1064
1065/* SMI */
1066static void acpiSmiWriteU8 (ACPIState *s, uint32_t addr, uint32_t val)
1067{
1068 Log (("acpi: acpiSmiWriteU8 %#x\n", val));
1069 if (val == ACPI_ENABLE)
1070 s->pm1a_ctl |= SCI_EN;
1071 else if (val == ACPI_DISABLE)
1072 s->pm1a_ctl &= ~SCI_EN;
1073 else
1074 Log (("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1075}
1076
1077static uint32_t find_rsdp_space (void)
1078{
1079 return 0xe0000;
1080}
1081
1082static void acpiPMTimerReset (ACPIState *s)
1083{
1084 uint64_t interval, freq;
1085
1086 freq = TMTimerGetFreq (s->CTX_SUFF(ts));
1087 interval = ASMMultU64ByU32DivByU32 (0xffffffff, freq, PM_TMR_FREQ);
1088 Log (("interval = %RU64\n", interval));
1089 TMTimerSet (s->CTX_SUFF(ts), TMTimerGet (s->CTX_SUFF(ts)) + interval);
1090}
1091
1092static DECLCALLBACK(void) acpiTimer (PPDMDEVINS pDevIns, PTMTIMER pTimer)
1093{
1094 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1095
1096 Log (("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1097 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1098 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1099
1100 update_pm1a (s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1101 acpiPMTimerReset (s);
1102}
1103
1104/**
1105 * _BST method.
1106 */
1107static void acpiFetchBatteryStatus (ACPIState *s)
1108{
1109 uint32_t *p = s->au8BatteryInfo;
1110 bool fPresent; /* battery present? */
1111 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1112 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1113 uint32_t hostPresentRate; /* 0..1000 */
1114 int rc;
1115
1116 if (!s->pDrv)
1117 return;
1118 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1119 &hostBatteryState, &hostPresentRate);
1120 AssertRC (rc);
1121
1122 /* default values */
1123 p[BAT_STATUS_STATE] = hostBatteryState;
1124 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1125 : hostPresentRate * 50; /* mW */
1126 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1127 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1128
1129 /* did we get a valid battery state? */
1130 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1131 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1132 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1133 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1134}
1135
1136/**
1137 * _BIF method.
1138 */
1139static void acpiFetchBatteryInfo (ACPIState *s)
1140{
1141 uint32_t *p = s->au8BatteryInfo;
1142
1143 p[BAT_INFO_UNITS] = 0; /* mWh */
1144 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1145 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1146 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1147 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1148 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1149 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1150 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1151 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1152}
1153
1154/**
1155 * _STA method.
1156 */
1157static uint32_t acpiGetBatteryDeviceStatus (ACPIState *s)
1158{
1159 bool fPresent; /* battery present? */
1160 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1161 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1162 uint32_t hostPresentRate; /* 0..1000 */
1163 int rc;
1164
1165 if (!s->pDrv)
1166 return 0;
1167 rc = s->pDrv->pfnQueryBatteryStatus (s->pDrv, &fPresent, &hostRemainingCapacity,
1168 &hostBatteryState, &hostPresentRate);
1169 AssertRC (rc);
1170
1171 return fPresent
1172 ? STA_DEVICE_PRESENT_MASK /* present */
1173 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1174 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1175 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1176 | STA_BATTERY_PRESENT_MASK /* battery is present */
1177 : 0; /* device not present */
1178}
1179
1180static uint32_t acpiGetPowerSource (ACPIState *s)
1181{
1182 PDMACPIPOWERSOURCE ps;
1183
1184 /* query the current power source from the host driver */
1185 if (!s->pDrv)
1186 return AC_ONLINE;
1187 int rc = s->pDrv->pfnQueryPowerSource (s->pDrv, &ps);
1188 AssertRC (rc);
1189 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1190}
1191
1192IO_WRITE_PROTO (acpiBatIndexWrite)
1193{
1194 ACPIState *s = (ACPIState *)pvUser;
1195
1196 switch (cb)
1197 {
1198 case 4:
1199 u32 >>= s->u8IndexShift;
1200 /* see comment at the declaration of u8IndexShift */
1201 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1202 {
1203 s->u8IndexShift = 2;
1204 u32 >>= 2;
1205 }
1206 Assert (u32 < BAT_INDEX_LAST);
1207 s->uBatteryIndex = u32;
1208 break;
1209 default:
1210 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1211 break;
1212 }
1213 return VINF_SUCCESS;
1214}
1215
1216IO_READ_PROTO (acpiBatDataRead)
1217{
1218 ACPIState *s = (ACPIState *)pvUser;
1219
1220 switch (cb)
1221 {
1222 case 4:
1223 switch (s->uBatteryIndex)
1224 {
1225 case BAT_STATUS_STATE:
1226 acpiFetchBatteryStatus(s);
1227 case BAT_STATUS_PRESENT_RATE:
1228 case BAT_STATUS_REMAINING_CAPACITY:
1229 case BAT_STATUS_PRESENT_VOLTAGE:
1230 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1231 break;
1232
1233 case BAT_INFO_UNITS:
1234 acpiFetchBatteryInfo(s);
1235 case BAT_INFO_DESIGN_CAPACITY:
1236 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1237 case BAT_INFO_TECHNOLOGY:
1238 case BAT_INFO_DESIGN_VOLTAGE:
1239 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1240 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1241 case BAT_INFO_CAPACITY_GRANULARITY_1:
1242 case BAT_INFO_CAPACITY_GRANULARITY_2:
1243 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1244 break;
1245
1246 case BAT_DEVICE_STATUS:
1247 *pu32 = acpiGetBatteryDeviceStatus(s);
1248 break;
1249
1250 case BAT_POWER_SOURCE:
1251 *pu32 = acpiGetPowerSource(s);
1252 break;
1253
1254 default:
1255 AssertMsgFailed (("Invalid battery index %d\n", s->uBatteryIndex));
1256 break;
1257 }
1258 break;
1259 default:
1260 return VERR_IOM_IOPORT_UNUSED;
1261 }
1262 return VINF_SUCCESS;
1263}
1264
1265IO_WRITE_PROTO (acpiSysInfoIndexWrite)
1266{
1267 ACPIState *s = (ACPIState *)pvUser;
1268
1269 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1270 switch (cb) {
1271 case 4:
1272 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1273 s->uSystemInfoIndex = u32;
1274 else
1275 {
1276 /* see comment at the declaration of u8IndexShift */
1277 if (s->u8IndexShift == 0)
1278 {
1279 if (((u32 >> 2) < SYSTEM_INFO_INDEX_LAST) && ((u32 & 0x3)) == 0)
1280 {
1281 s->u8IndexShift = 2;
1282 }
1283 }
1284
1285 u32 >>= s->u8IndexShift;
1286 Assert (u32 < SYSTEM_INFO_INDEX_LAST);
1287 s->uSystemInfoIndex = u32;
1288 }
1289 break;
1290
1291 default:
1292 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1293 break;
1294 }
1295 return VINF_SUCCESS;
1296}
1297
1298IO_READ_PROTO (acpiSysInfoDataRead)
1299{
1300 ACPIState *s = (ACPIState *)pvUser;
1301
1302 switch (cb)
1303 {
1304 case 4:
1305 switch (s->uSystemInfoIndex)
1306 {
1307 case SYSTEM_INFO_INDEX_MEMORY_LENGTH:
1308 *pu32 = s->u64RamSize;
1309 break;
1310
1311 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1312 *pu32 = s->u8UseIOApic;
1313 break;
1314
1315 case SYSTEM_INFO_INDEX_HPET_STATUS:
1316 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1317 | STA_DEVICE_ENABLED_MASK
1318 | STA_DEVICE_SHOW_IN_UI_MASK
1319 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1320 : 0;
1321 break;
1322
1323 case SYSTEM_INFO_INDEX_SMC_STATUS:
1324 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1325 | STA_DEVICE_ENABLED_MASK
1326 /* no need to show this device in the UI */
1327 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1328 : 0;
1329 break;
1330
1331 case SYSTEM_INFO_INDEX_FDC_STATUS:
1332 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1333 | STA_DEVICE_ENABLED_MASK
1334 | STA_DEVICE_SHOW_IN_UI_MASK
1335 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1336 : 0;
1337 break;
1338 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1339 *pu32 = s->fShowCpu ? ( STA_DEVICE_PRESENT_MASK
1340 | STA_DEVICE_ENABLED_MASK
1341 | STA_DEVICE_SHOW_IN_UI_MASK
1342 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1343 : 0;
1344 break;
1345
1346 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1347 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1348 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1349#ifdef VBOX_WITH_SMP_GUESTS
1350 *pu32 = (s->fShowCpu &&
1351 s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < cCpus)
1352 ? ( STA_DEVICE_PRESENT_MASK
1353 | STA_DEVICE_ENABLED_MASK
1354 | STA_DEVICE_SHOW_IN_UI_MASK
1355 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1356 : 0;
1357#else
1358 *pu32 = 0;
1359#endif
1360 break;
1361
1362 /* Solaris 9 tries to read from this index */
1363 case SYSTEM_INFO_INDEX_INVALID:
1364 *pu32 = 0;
1365 break;
1366
1367 default:
1368 AssertMsgFailed (("Invalid system info index %d\n", s->uSystemInfoIndex));
1369 break;
1370 }
1371 break;
1372
1373 default:
1374 return VERR_IOM_IOPORT_UNUSED;
1375 }
1376
1377 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1378 return VINF_SUCCESS;
1379}
1380
1381IO_WRITE_PROTO (acpiSysInfoDataWrite)
1382{
1383 ACPIState *s = (ACPIState *)pvUser;
1384
1385 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1386
1387 if (cb == 4 && u32 == 0xbadc0de)
1388 {
1389 switch (s->uSystemInfoIndex)
1390 {
1391 case SYSTEM_INFO_INDEX_INVALID:
1392 s->u8IndexShift = 0;
1393 break;
1394
1395 case SYSTEM_INFO_INDEX_VALID:
1396 s->u8IndexShift = 2;
1397 break;
1398
1399 default:
1400 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1401 Port, cb, u32, s->uSystemInfoIndex));
1402 break;
1403 }
1404 }
1405 else
1406 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1407 return VINF_SUCCESS;
1408}
1409
1410/* IO Helpers */
1411IO_READ_PROTO (acpiPm1aEnRead)
1412{
1413 switch (cb)
1414 {
1415 case 2:
1416 *pu32 = acpiPm1aEnReadw ((ACPIState*)pvUser, Port);
1417 break;
1418 default:
1419 return VERR_IOM_IOPORT_UNUSED;
1420 }
1421 return VINF_SUCCESS;
1422}
1423
1424IO_READ_PROTO (acpiPm1aStsRead)
1425{
1426 switch (cb)
1427 {
1428 case 2:
1429 *pu32 = acpiPm1aStsReadw ((ACPIState*)pvUser, Port);
1430 break;
1431 default:
1432 return VERR_IOM_IOPORT_UNUSED;
1433 }
1434 return VINF_SUCCESS;
1435}
1436
1437IO_READ_PROTO (acpiPm1aCtlRead)
1438{
1439 switch (cb)
1440 {
1441 case 2:
1442 *pu32 = acpiPm1aCtlReadw ((ACPIState*)pvUser, Port);
1443 break;
1444 default:
1445 return VERR_IOM_IOPORT_UNUSED;
1446 }
1447 return VINF_SUCCESS;
1448}
1449
1450IO_WRITE_PROTO (acpiPM1aEnWrite)
1451{
1452 switch (cb)
1453 {
1454 case 2:
1455 acpiPM1aEnWritew ((ACPIState*)pvUser, Port, u32);
1456 break;
1457 default:
1458 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1459 break;
1460 }
1461 return VINF_SUCCESS;
1462}
1463
1464IO_WRITE_PROTO (acpiPM1aStsWrite)
1465{
1466 switch (cb)
1467 {
1468 case 2:
1469 acpiPM1aStsWritew ((ACPIState*)pvUser, Port, u32);
1470 break;
1471 default:
1472 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1473 break;
1474 }
1475 return VINF_SUCCESS;
1476}
1477
1478IO_WRITE_PROTO (acpiPM1aCtlWrite)
1479{
1480 switch (cb)
1481 {
1482 case 2:
1483 return acpiPM1aCtlWritew ((ACPIState*)pvUser, Port, u32);
1484 default:
1485 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1486 break;
1487 }
1488 return VINF_SUCCESS;
1489}
1490
1491#endif /* IN_RING3 */
1492
1493/**
1494 * PMTMR readable from host/guest.
1495 */
1496IO_READ_PROTO (acpiPMTmrRead)
1497{
1498 if (cb == 4)
1499 {
1500 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1501 int64_t now = TMTimerGet (s->CTX_SUFF(ts));
1502 int64_t elapsed = now - s->pm_timer_initial;
1503
1504 *pu32 = ASMMultU64ByU32DivByU32 (elapsed, PM_TMR_FREQ, TMTimerGetFreq (s->CTX_SUFF(ts)));
1505 Log (("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1506 return VINF_SUCCESS;
1507 }
1508 return VERR_IOM_IOPORT_UNUSED;
1509}
1510
1511#ifdef IN_RING3
1512
1513IO_READ_PROTO (acpiGpe0StsRead)
1514{
1515 switch (cb)
1516 {
1517 case 1:
1518 *pu32 = acpiGpe0StsReadb ((ACPIState*)pvUser, Port);
1519 break;
1520 default:
1521 return VERR_IOM_IOPORT_UNUSED;
1522 }
1523 return VINF_SUCCESS;
1524}
1525
1526IO_READ_PROTO (acpiGpe0EnRead)
1527{
1528 switch (cb)
1529 {
1530 case 1:
1531 *pu32 = acpiGpe0EnReadb ((ACPIState*)pvUser, Port);
1532 break;
1533 default:
1534 return VERR_IOM_IOPORT_UNUSED;
1535 }
1536 return VINF_SUCCESS;
1537}
1538
1539IO_WRITE_PROTO (acpiGpe0StsWrite)
1540{
1541 switch (cb)
1542 {
1543 case 1:
1544 acpiGpe0StsWriteb ((ACPIState*)pvUser, Port, u32);
1545 break;
1546 default:
1547 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1548 break;
1549 }
1550 return VINF_SUCCESS;
1551}
1552
1553IO_WRITE_PROTO (acpiGpe0EnWrite)
1554{
1555 switch (cb)
1556 {
1557 case 1:
1558 acpiGpe0EnWriteb ((ACPIState*)pvUser, Port, u32);
1559 break;
1560 default:
1561 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1562 break;
1563 }
1564 return VINF_SUCCESS;
1565}
1566
1567IO_WRITE_PROTO (acpiSmiWrite)
1568{
1569 switch (cb)
1570 {
1571 case 1:
1572 acpiSmiWriteU8 ((ACPIState*)pvUser, Port, u32);
1573 break;
1574 default:
1575 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1576 break;
1577 }
1578 return VINF_SUCCESS;
1579}
1580
1581IO_WRITE_PROTO (acpiResetWrite)
1582{
1583 switch (cb)
1584 {
1585 case 1:
1586 return acpiResetWriteU8 ((ACPIState*)pvUser, Port, u32);
1587 default:
1588 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1589 break;
1590 }
1591 return VINF_SUCCESS;
1592}
1593
1594#ifdef DEBUG_ACPI
1595
1596IO_WRITE_PROTO (acpiDhexWrite)
1597{
1598 switch (cb)
1599 {
1600 case 1:
1601 Log (("%#x\n", u32 & 0xff));
1602 break;
1603 case 2:
1604 Log (("%#6x\n", u32 & 0xffff));
1605 case 4:
1606 Log (("%#10x\n", u32));
1607 break;
1608 default:
1609 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1610 break;
1611 }
1612 return VINF_SUCCESS;
1613}
1614
1615IO_WRITE_PROTO (acpiDchrWrite)
1616{
1617 switch (cb)
1618 {
1619 case 1:
1620 Log (("%c", u32 & 0xff));
1621 break;
1622 default:
1623 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1624 break;
1625 }
1626 return VINF_SUCCESS;
1627}
1628
1629#endif /* DEBUG_ACPI */
1630
1631
1632/**
1633 * Saved state structure description.
1634 */
1635static const SSMFIELD g_AcpiSavedStateFields[] =
1636{
1637 SSMFIELD_ENTRY (ACPIState, pm1a_en),
1638 SSMFIELD_ENTRY (ACPIState, pm1a_sts),
1639 SSMFIELD_ENTRY (ACPIState, pm1a_ctl),
1640 SSMFIELD_ENTRY (ACPIState, pm_timer_initial),
1641 SSMFIELD_ENTRY (ACPIState, gpe0_en),
1642 SSMFIELD_ENTRY (ACPIState, gpe0_sts),
1643 SSMFIELD_ENTRY (ACPIState, uBatteryIndex),
1644 SSMFIELD_ENTRY (ACPIState, uSystemInfoIndex),
1645 SSMFIELD_ENTRY (ACPIState, u64RamSize),
1646 SSMFIELD_ENTRY (ACPIState, u8IndexShift),
1647 SSMFIELD_ENTRY (ACPIState, u8UseIOApic),
1648 SSMFIELD_ENTRY (ACPIState, uSleepState),
1649 SSMFIELD_ENTRY_TERM ()
1650};
1651
1652static DECLCALLBACK(int) acpi_save_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1653{
1654 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1655 return SSMR3PutStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1656}
1657
1658static DECLCALLBACK(int) acpi_load_state (PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1659 uint32_t u32Version)
1660{
1661 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1662 int rc;
1663
1664 if (u32Version != 4)
1665 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1666
1667 rc = SSMR3GetStruct (pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1668 if (RT_SUCCESS (rc))
1669 {
1670 acpiFetchBatteryStatus (s);
1671 acpiFetchBatteryInfo (s);
1672 acpiPMTimerReset (s);
1673 }
1674 return rc;
1675}
1676
1677/**
1678 * Queries an interface to the driver.
1679 *
1680 * @returns Pointer to interface.
1681 * @returns NULL if the interface was not supported by the driver.
1682 * @param pInterface Pointer to this interface structure.
1683 * @param enmInterface The requested interface identification.
1684 * @thread Any thread.
1685 */
1686static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1687{
1688 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1689 switch (enmInterface)
1690 {
1691 case PDMINTERFACE_BASE:
1692 return &pThis->IBase;
1693 case PDMINTERFACE_ACPI_PORT:
1694 return &pThis->IACPIPort;
1695 default:
1696 return NULL;
1697 }
1698}
1699
1700/**
1701 * Create the ACPI tables.
1702 */
1703static int acpiPlantTables (ACPIState *s)
1704{
1705 int rc;
1706 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1707 uint32_t addend = 0;
1708 RTGCPHYS32 rsdt_addrs[4];
1709 uint32_t cAddr;
1710 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1711 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1712
1713 cAddr = 1; /* FADT */
1714 if (s->u8UseIOApic)
1715 cAddr++; /* MADT */
1716
1717 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1718 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1719
1720 rc = CFGMR3QueryU64 (s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1721 if (RT_FAILURE (rc))
1722 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1723 N_("Configuration error: Querying "
1724 "\"RamSize\" as integer failed"));
1725
1726 uint32_t cbRamHole;
1727 rc = CFGMR3QueryU32Def (s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1728 if (RT_FAILURE (rc))
1729 return PDMDEV_SET_ERROR (s->pDevIns, rc,
1730 N_ ("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1731 const uint64_t offRamHole = _4G - cbRamHole;
1732
1733#if 0 /** @todo 4GB: This needs adjusting fixing! I've disabled it to test big mem configs. */
1734 if (s->u64RamSize > (0xffffffff - 0x10000))
1735 return PDMDEV_SET_ERROR(s->pDevIns, VERR_OUT_OF_RANGE,
1736 N_("Configuration error: Invalid \"RamSize\", maximum allowed "
1737 "value is 4095MB"));
1738#endif
1739
1740 rsdt_addr = 0;
1741 xsdt_addr = RT_ALIGN_32 (rsdt_addr + rsdt_tbl_len, 16);
1742 fadt_addr = RT_ALIGN_32 (xsdt_addr + xsdt_tbl_len, 16);
1743 facs_addr = RT_ALIGN_32 (fadt_addr + sizeof(ACPITBLFADT), 16);
1744 if (s->u8UseIOApic)
1745 {
1746 apic_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1747#ifdef VBOX_WITH_SMP_GUESTS
1748 /**
1749 * @todo nike: maybe some refactoring needed to compute tables layout,
1750 * but as this code is executed only once it doesn't make sense to optimize much
1751 */
1752 dsdt_addr = RT_ALIGN_32 (apic_addr + AcpiTableMADT::sizeFor(s), 16);
1753#else
1754 dsdt_addr = RT_ALIGN_32 (apic_addr + sizeof(ACPITBLMADT), 16);
1755#endif
1756 }
1757 else
1758 {
1759 dsdt_addr = RT_ALIGN_32 (facs_addr + sizeof(ACPITBLFACS), 16);
1760 }
1761
1762 last_addr = RT_ALIGN_32 (dsdt_addr + sizeof(AmlCode), 16);
1763 if (last_addr > 0x10000)
1764 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1765 N_("Error: ACPI tables > 64KB"));
1766
1767 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1768#if 1 /** @todo 4GB: Quick hack, may need revising. */
1769 addend = (uint32_t) RT_MIN (s->u64RamSize, offRamHole) - 0x10000;
1770#else
1771 addend = (uint32_t) s->u64RamSize - 0x10000;
1772#endif
1773 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1774 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1775 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1776 acpiSetupRSDP ((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1777 acpiSetupDSDT (s, dsdt_addr + addend);
1778 acpiSetupFACS (s, facs_addr + addend);
1779 acpiSetupFADT (s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1780
1781 rsdt_addrs[0] = fadt_addr + addend;
1782 if (s->u8UseIOApic)
1783 {
1784 acpiSetupMADT (s, apic_addr + addend);
1785 rsdt_addrs[1] = apic_addr + addend;
1786 }
1787
1788 rc = acpiSetupRSDT (s, rsdt_addr + addend, cAddr, rsdt_addrs);
1789 if (RT_FAILURE(rc))
1790 return rc;
1791 return acpiSetupXSDT (s, xsdt_addr + addend, cAddr, rsdt_addrs);
1792}
1793
1794/**
1795 * Construct a device instance for a VM.
1796 *
1797 * @returns VBox status.
1798 * @param pDevIns The device instance data.
1799 * If the registration structure is needed, pDevIns->pDevReg points to it.
1800 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1801 * The device number is also found in pDevIns->iInstance, but since it's
1802 * likely to be freqently used PDM passes it as parameter.
1803 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1804 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1805 * iInstance it's expected to be used a bit in this function.
1806 */
1807static DECLCALLBACK(int) acpiConstruct (PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1808{
1809 int rc;
1810 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
1811 uint32_t rsdp_addr;
1812 PCIDevice *dev;
1813 bool fGCEnabled;
1814 bool fR0Enabled;
1815
1816 /* Validate and read the configuration. */
1817 if (!CFGMR3AreValuesValid (pCfgHandle,
1818 "RamSize\0"
1819 "RamHoleSize\0"
1820 "IOAPIC\0"
1821 "NumCPUs\0"
1822 "GCEnabled\0"
1823 "R0Enabled\0"
1824 "HpetEnabled\0"
1825 "SmcEnabled\0"
1826 "FdcEnabled\0"
1827 ))
1828 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1829 N_("Configuration error: Invalid config key for ACPI device"));
1830
1831 s->pDevIns = pDevIns;
1832
1833 /* query whether we are supposed to present an IOAPIC */
1834 rc = CFGMR3QueryU8Def (pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1835 if (RT_FAILURE (rc))
1836 return PDMDEV_SET_ERROR(pDevIns, rc,
1837 N_("Configuration error: Failed to read \"IOAPIC\""));
1838
1839 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1840 if (RT_FAILURE(rc))
1841 return PDMDEV_SET_ERROR(pDevIns, rc,
1842 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1843
1844 /* query whether we are supposed to present an FDC controller */
1845 rc = CFGMR3QueryBoolDef (pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1846 if (RT_FAILURE (rc))
1847 return PDMDEV_SET_ERROR(pDevIns, rc,
1848 N_("Configuration error: Failed to read \"FdcEnabled\""));
1849
1850 /* query whether we are supposed to present HPET */
1851 rc = CFGMR3QueryBoolDef (pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1852 if (RT_FAILURE(rc))
1853 return PDMDEV_SET_ERROR(pDevIns, rc,
1854 N_("Configuration error: Failed to read \"HpetEnabled\""));
1855 /* query whether we are supposed to present SMC */
1856 rc = CFGMR3QueryBoolDef (pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1857 if (RT_FAILURE(rc))
1858 return PDMDEV_SET_ERROR(pDevIns, rc,
1859 N_("Configuration error: Failed to read \"SmcEnabled\""));
1860 /** @todo: a bit of hack: if we have SMC, also show CPU object in ACPI tables */
1861 s->fShowCpu = s->fUseSmc;
1862
1863 rc = CFGMR3QueryBool (pCfgHandle, "GCEnabled", &fGCEnabled);
1864 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1865 fGCEnabled = true;
1866 else if (RT_FAILURE (rc))
1867 return PDMDEV_SET_ERROR(pDevIns, rc,
1868 N_("Configuration error: Failed to read \"GCEnabled\""));
1869
1870 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1871 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1872 fR0Enabled = true;
1873 else if (RT_FAILURE(rc))
1874 return PDMDEV_SET_ERROR(pDevIns, rc,
1875 N_("configuration error: failed to read R0Enabled as boolean"));
1876
1877 /* */
1878 rsdp_addr = find_rsdp_space ();
1879 if (!rsdp_addr)
1880 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1881 N_("Can not find space for RSDP. ACPI is disabled"));
1882
1883 rc = acpiPlantTables (s);
1884 if (RT_FAILURE (rc))
1885 return rc;
1886
1887 rc = PDMDevHlpROMRegister (pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage, false /* fShadow */, "ACPI RSDP");
1888 if (RT_FAILURE (rc))
1889 return rc;
1890
1891#define R(addr, cnt, writer, reader, description) \
1892 do { \
1893 rc = PDMDevHlpIOPortRegister (pDevIns, addr, cnt, s, writer, reader, \
1894 NULL, NULL, description); \
1895 if (RT_FAILURE (rc)) \
1896 return rc; \
1897 } while (0)
1898#define L (GPE0_BLK_LEN / 2)
1899
1900 R (PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1901 R (PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1902 R (PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1903 R (PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1904 R (SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1905#ifdef DEBUG_ACPI
1906 R (DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1907 R (DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1908#endif
1909 R (BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1910 R (BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1911 R (SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1912 R (SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1913 R (GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1914 R (GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1915 R (ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1916#undef L
1917#undef R
1918
1919 /* register GC stuff */
1920 if (fGCEnabled)
1921 {
1922 rc = PDMDevHlpIOPortRegisterGC (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1923 NULL, NULL, "ACPI PM Timer");
1924 AssertRCReturn(rc, rc);
1925 }
1926
1927 /* register R0 stuff */
1928 if (fR0Enabled)
1929 {
1930 rc = PDMDevHlpIOPortRegisterR0 (pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1931 NULL, NULL, "ACPI PM Timer");
1932 AssertRCReturn(rc, rc);
1933 }
1934
1935 rc = PDMDevHlpTMTimerCreate (pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1936 if (RT_FAILURE(rc))
1937 {
1938 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1939 return rc;
1940 }
1941
1942 s->tsR0 = TMTimerR0Ptr (s->tsR3);
1943 s->tsRC = TMTimerRCPtr (s->tsR3);
1944 s->pm_timer_initial = TMTimerGet (s->tsR3);
1945 acpiPMTimerReset (s);
1946
1947 dev = &s->dev;
1948 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1949 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1950
1951 dev->config[0x04] = 0x01; /* command */
1952 dev->config[0x05] = 0x00;
1953
1954 dev->config[0x06] = 0x80; /* status */
1955 dev->config[0x07] = 0x02;
1956 dev->config[0x08] = 0x08;
1957 dev->config[0x09] = 0x00;
1958
1959 dev->config[0x0a] = 0x80;
1960 dev->config[0x0b] = 0x06;
1961
1962 dev->config[0x0e] = 0x80;
1963 dev->config[0x0f] = 0x00;
1964
1965#if 0 /* The ACPI controller usually has no subsystem ID. */
1966 dev->config[0x2c] = 0x86;
1967 dev->config[0x2d] = 0x80;
1968 dev->config[0x2e] = 0x00;
1969 dev->config[0x2f] = 0x00;
1970#endif
1971 dev->config[0x3c] = SCI_INT;
1972
1973 rc = PDMDevHlpPCIRegister (pDevIns, dev);
1974 if (RT_FAILURE (rc))
1975 return rc;
1976
1977 rc = PDMDevHlpSSMRegister (pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
1978 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
1979 if (RT_FAILURE(rc))
1980 return rc;
1981
1982 /*
1983 * Interfaces
1984 */
1985 /* IBase */
1986 s->IBase.pfnQueryInterface = acpiQueryInterface;
1987 /* IACPIPort */
1988 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
1989 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
1990 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
1991 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
1992
1993 /*
1994 * Get the corresponding connector interface
1995 */
1996 rc = PDMDevHlpDriverAttach (pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
1997 if (RT_SUCCESS (rc))
1998 {
1999 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface (s->pDrvBase,
2000 PDMINTERFACE_ACPI_CONNECTOR);
2001 if (!s->pDrv)
2002 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2003 N_("LUN #0 doesn't have an ACPI connector interface"));
2004 }
2005 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2006 {
2007 Log (("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2008 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2009 rc = VINF_SUCCESS;
2010 }
2011 else
2012 return PDMDEV_SET_ERROR(pDevIns, rc,
2013 N_("Failed to attach LUN #0"));
2014
2015 return rc;
2016}
2017
2018/**
2019 * Relocates the GC pointer members.
2020 */
2021static DECLCALLBACK(void) acpiRelocate (PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2022{
2023 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
2024 s->tsRC = TMTimerRCPtr (s->CTX_SUFF(ts));
2025}
2026
2027static DECLCALLBACK(void) acpiReset (PPDMDEVINS pDevIns)
2028{
2029 ACPIState *s = PDMINS_2_DATA (pDevIns, ACPIState *);
2030
2031 s->pm1a_en = 0;
2032 s->pm1a_sts = 0;
2033 s->pm1a_ctl = 0;
2034 s->pm_timer_initial = TMTimerGet (s->CTX_SUFF(ts));
2035 acpiPMTimerReset(s);
2036 s->uBatteryIndex = 0;
2037 s->uSystemInfoIndex = 0;
2038 s->gpe0_en = 0;
2039 s->gpe0_sts = 0;
2040 s->uSleepState = 0;
2041
2042 acpiPlantTables(s);
2043}
2044
2045/**
2046 * The device registration structure.
2047 */
2048const PDMDEVREG g_DeviceACPI =
2049{
2050 /* u32Version */
2051 PDM_DEVREG_VERSION,
2052 /* szDeviceName */
2053 "acpi",
2054 /* szRCMod */
2055 "VBoxDDGC.gc",
2056 /* szR0Mod */
2057 "VBoxDDR0.r0",
2058 /* pszDescription */
2059 "Advanced Configuration and Power Interface",
2060 /* fFlags */
2061 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2062 /* fClass */
2063 PDM_DEVREG_CLASS_ACPI,
2064 /* cMaxInstances */
2065 ~0,
2066 /* cbInstance */
2067 sizeof(ACPIState),
2068 /* pfnConstruct */
2069 acpiConstruct,
2070 /* pfnDestruct */
2071 NULL,
2072 /* pfnRelocate */
2073 acpiRelocate,
2074 /* pfnIOCtl */
2075 NULL,
2076 /* pfnPowerOn */
2077 NULL,
2078 /* pfnReset */
2079 acpiReset,
2080 /* pfnSuspend */
2081 NULL,
2082 /* pfnResume */
2083 NULL,
2084 /* pfnAttach */
2085 NULL,
2086 /* pfnDetach */
2087 NULL,
2088 /* pfnQueryInterface. */
2089 NULL,
2090 /* pfnInitComplete */
2091 NULL,
2092 /* pfnPowerOff */
2093 NULL,
2094 /* pfnSoftReset */
2095 NULL,
2096 /* u32VersionEnd */
2097 PDM_DEVREG_VERSION
2098};
2099
2100#endif /* IN_RING3 */
2101#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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