VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevACPI.cpp@ 18672

Last change on this file since 18672 was 18143, checked in by vboxsync, 16 years ago

VMM,Devices: Changed ROM registration and fixed some shadowed ROM issues in the new phys code.
  • Property svn:eol-style set to native
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File size: 76.6 KB
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1/* $Id: DevACPI.cpp 18143 2009-03-23 15:10:24Z vboxsync $ */
2/** @file
3 * DevACPI - Advanced Configuration and Power Interface (ACPI) Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22/*******************************************************************************
23* Header Files *
24*******************************************************************************/
25#define LOG_GROUP LOG_GROUP_DEV_ACPI
26#include <VBox/pdmdev.h>
27#include <VBox/pgm.h>
28#include <VBox/log.h>
29#include <VBox/param.h>
30#include <iprt/assert.h>
31#include <iprt/asm.h>
32#ifdef IN_RING3
33# include <iprt/alloc.h>
34# include <iprt/string.h>
35#endif /* IN_RING3 */
36
37#include "../Builtins.h"
38
39#ifdef LOG_ENABLED
40# define DEBUG_ACPI
41#endif
42
43/* the compiled DSL */
44#if defined(IN_RING3) && !defined(VBOX_DEVICE_STRUCT_TESTCASE)
45# include <vboxaml.hex>
46#endif /* !IN_RING3 */
47
48
49
50/*******************************************************************************
51* Defined Constants And Macros *
52*******************************************************************************/
53#define DEBUG_HEX 0x3000
54#define DEBUG_CHR 0x3001
55
56#define PM_TMR_FREQ 3579545
57#define PM1a_EVT_BLK 0x00004000
58#define PM1b_EVT_BLK 0x00000000 /**< not supported */
59#define PM1a_CTL_BLK 0x00004004
60#define PM1b_CTL_BLK 0x00000000 /**< not supported */
61#define PM2_CTL_BLK 0x00000000 /**< not supported */
62#define PM_TMR_BLK 0x00004008
63#define GPE0_BLK 0x00004020
64#define GPE1_BLK 0x00000000 /**< not supported */
65#define BAT_INDEX 0x00004040
66#define BAT_DATA 0x00004044
67#define SYSI_INDEX 0x00004048
68#define SYSI_DATA 0x0000404c
69#define ACPI_RESET_BLK 0x00004050
70
71/* PM1x status register bits */
72#define TMR_STS RT_BIT(0)
73#define RSR1_STS (RT_BIT(1) | RT_BIT(2) | RT_BIT(3))
74#define BM_STS RT_BIT(4)
75#define GBL_STS RT_BIT(5)
76#define RSR2_STS (RT_BIT(6) | RT_BIT(7))
77#define PWRBTN_STS RT_BIT(8)
78#define SLPBTN_STS RT_BIT(9)
79#define RTC_STS RT_BIT(10)
80#define IGN_STS RT_BIT(11)
81#define RSR3_STS (RT_BIT(12) | RT_BIT(13) | RT_BIT(14))
82#define WAK_STS RT_BIT(15)
83#define RSR_STS (RSR1_STS | RSR2_STS | RSR3_STS)
84
85/* PM1x enable register bits */
86#define TMR_EN RT_BIT(0)
87#define RSR1_EN (RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4))
88#define GBL_EN RT_BIT(5)
89#define RSR2_EN (RT_BIT(6) | RT_BIT(7))
90#define PWRBTN_EN RT_BIT(8)
91#define SLPBTN_EN RT_BIT(9)
92#define RTC_EN RT_BIT(10)
93#define RSR3_EN (RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(14) | RT_BIT(15))
94#define RSR_EN (RSR1_EN | RSR2_EN | RSR3_EN)
95#define IGN_EN 0
96
97/* PM1x control register bits */
98#define SCI_EN RT_BIT(0)
99#define BM_RLD RT_BIT(1)
100#define GBL_RLS RT_BIT(2)
101#define RSR1_CNT (RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7) | RT_BIT(8))
102#define IGN_CNT RT_BIT(9)
103#define SLP_TYPx_SHIFT 10
104#define SLP_TYPx_MASK 7
105#define SLP_EN RT_BIT(13)
106#define RSR2_CNT (RT_BIT(14) | RT_BIT(15))
107#define RSR_CNT (RSR1_CNT | RSR2_CNT)
108
109#define GPE0_BATTERY_INFO_CHANGED RT_BIT(0)
110
111enum
112{
113 BAT_STATUS_STATE = 0x00, /**< BST battery state */
114 BAT_STATUS_PRESENT_RATE = 0x01, /**< BST battery present rate */
115 BAT_STATUS_REMAINING_CAPACITY = 0x02, /**< BST battery remaining capacity */
116 BAT_STATUS_PRESENT_VOLTAGE = 0x03, /**< BST battery present voltage */
117 BAT_INFO_UNITS = 0x04, /**< BIF power unit */
118 BAT_INFO_DESIGN_CAPACITY = 0x05, /**< BIF design capacity */
119 BAT_INFO_LAST_FULL_CHARGE_CAPACITY = 0x06, /**< BIF last full charge capacity */
120 BAT_INFO_TECHNOLOGY = 0x07, /**< BIF battery technology */
121 BAT_INFO_DESIGN_VOLTAGE = 0x08, /**< BIF design voltage */
122 BAT_INFO_DESIGN_CAPACITY_OF_WARNING = 0x09, /**< BIF design capacity of warning */
123 BAT_INFO_DESIGN_CAPACITY_OF_LOW = 0x0A, /**< BIF design capacity of low */
124 BAT_INFO_CAPACITY_GRANULARITY_1 = 0x0B, /**< BIF battery capacity granularity 1 */
125 BAT_INFO_CAPACITY_GRANULARITY_2 = 0x0C, /**< BIF battery capacity granularity 2 */
126 BAT_DEVICE_STATUS = 0x0D, /**< STA device status */
127 BAT_POWER_SOURCE = 0x0E, /**< PSR power source */
128 BAT_INDEX_LAST
129};
130
131enum
132{
133 SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH = 0,
134 SYSTEM_INFO_INDEX_USE_IOAPIC = 1,
135 SYSTEM_INFO_INDEX_HPET_STATUS = 2,
136 SYSTEM_INFO_INDEX_SMC_STATUS = 3,
137 SYSTEM_INFO_INDEX_FDC_STATUS = 4,
138 SYSTEM_INFO_INDEX_CPU0_STATUS = 5,
139 SYSTEM_INFO_INDEX_CPU1_STATUS = 6,
140 SYSTEM_INFO_INDEX_CPU2_STATUS = 7,
141 SYSTEM_INFO_INDEX_CPU3_STATUS = 8,
142 SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH= 9,
143 SYSTEM_INFO_INDEX_END = 10,
144 SYSTEM_INFO_INDEX_INVALID = 0x80,
145 SYSTEM_INFO_INDEX_VALID = 0x200
146};
147
148#define AC_OFFLINE 0
149#define AC_ONLINE 1
150
151#define BAT_TECH_PRIMARY 1
152#define BAT_TECH_SECONDARY 2
153
154#define STA_DEVICE_PRESENT_MASK RT_BIT(0) /**< present */
155#define STA_DEVICE_ENABLED_MASK RT_BIT(1) /**< enabled and decodes its resources */
156#define STA_DEVICE_SHOW_IN_UI_MASK RT_BIT(2) /**< should be shown in UI */
157#define STA_DEVICE_FUNCTIONING_PROPERLY_MASK RT_BIT(3) /**< functioning properly */
158#define STA_BATTERY_PRESENT_MASK RT_BIT(4) /**< the battery is present */
159
160
161/*******************************************************************************
162* Structures and Typedefs *
163*******************************************************************************/
164/**
165 * The ACPI device state.
166 */
167typedef struct ACPIState
168{
169 PCIDevice dev;
170 uint16_t pm1a_en;
171 uint16_t pm1a_sts;
172 uint16_t pm1a_ctl;
173 /** Number of logical CPUs in guest */
174 uint16_t cCpus;
175 int64_t pm_timer_initial;
176 PTMTIMERR3 tsR3;
177 PTMTIMERR0 tsR0;
178 PTMTIMERRC tsRC;
179
180 uint32_t gpe0_en;
181 uint32_t gpe0_sts;
182
183 unsigned int uBatteryIndex;
184 uint32_t au8BatteryInfo[13];
185
186 unsigned int uSystemInfoIndex;
187 uint64_t u64RamSize;
188 /** The number of bytes above 4GB. */
189 uint64_t cbRamHigh;
190 /** The number of bytes below 4GB. */
191 uint32_t cbRamLow;
192
193 /** Current ACPI S* state. We support S0 and S5 */
194 uint32_t uSleepState;
195 uint8_t au8RSDPPage[0x1000];
196 /** This is a workaround for incorrect index field handling by Intels ACPICA.
197 * The system info _INI method writes to offset 0x200. We either observe a
198 * write request to index 0x80 (in that case we don't change the index) or a
199 * write request to offset 0x200 (in that case we divide the index value by
200 * 4. Note that the _STA method is sometimes called prior to the _INI method
201 * (ACPI spec 6.3.7, _STA). See the special case for BAT_DEVICE_STATUS in
202 * acpiBatIndexWrite() for handling this. */
203 uint8_t u8IndexShift;
204 /** provide an I/O-APIC */
205 uint8_t u8UseIOApic;
206 /** provide a floppy controller */
207 bool fUseFdc;
208 /** If High Precision Event Timer device should be supported */
209 bool fUseHpet;
210 /** If System Management Controller device should be supported */
211 bool fUseSmc;
212 /** the guest handled the last power button event */
213 bool fPowerButtonHandled;
214 /** If ACPI CPU device should be shown */
215 bool fShowCpu;
216 /** Aligning IBase. */
217 bool afAlignment[6];
218
219 /** ACPI port base interface. */
220 PDMIBASE IBase;
221 /** ACPI port interface. */
222 PDMIACPIPORT IACPIPort;
223 /** Pointer to the device instance. */
224 PPDMDEVINSR3 pDevIns;
225 /** Pointer to the driver base interface */
226 R3PTRTYPE(PPDMIBASE) pDrvBase;
227 /** Pointer to the driver connector interface */
228 R3PTRTYPE(PPDMIACPICONNECTOR) pDrv;
229} ACPIState;
230
231#pragma pack(1)
232
233/** Generic Address Structure (see ACPIspec 3.0, 5.2.3.1) */
234struct ACPIGENADDR
235{
236 uint8_t u8AddressSpaceId; /**< 0=sys, 1=IO, 2=PCICfg, 3=emb, 4=SMBus */
237 uint8_t u8RegisterBitWidth; /**< size in bits of the given register */
238 uint8_t u8RegisterBitOffset; /**< bit offset of register */
239 uint8_t u8AccessSize; /**< 1=byte, 2=word, 3=dword, 4=qword */
240 uint64_t u64Address; /**< 64-bit address of register */
241};
242AssertCompileSize(ACPIGENADDR, 12);
243
244/** Root System Description Pointer */
245struct ACPITBLRSDP
246{
247 uint8_t au8Signature[8]; /**< 'RSD PTR ' */
248 uint8_t u8Checksum; /**< checksum for the first 20 bytes */
249 uint8_t au8OemId[6]; /**< OEM-supplied identifier */
250 uint8_t u8Revision; /**< revision number, currently 2 */
251#define ACPI_REVISION 2 /**< ACPI 3.0 */
252 uint32_t u32RSDT; /**< phys addr of RSDT */
253 uint32_t u32Length; /**< bytes of this table */
254 uint64_t u64XSDT; /**< 64-bit phys addr of XSDT */
255 uint8_t u8ExtChecksum; /**< checksum of entire table */
256 uint8_t u8Reserved[3]; /**< reserved */
257};
258AssertCompileSize(ACPITBLRSDP, 36);
259
260/** System Description Table Header */
261struct ACPITBLHEADER
262{
263 uint8_t au8Signature[4]; /**< table identifier */
264 uint32_t u32Length; /**< length of the table including header */
265 uint8_t u8Revision; /**< revision number */
266 uint8_t u8Checksum; /**< all fields inclusive this add to zero */
267 uint8_t au8OemId[6]; /**< OEM-supplied string */
268 uint8_t au8OemTabId[8]; /**< to identify the particular data table */
269 uint32_t u32OemRevision; /**< OEM-supplied revision number */
270 uint8_t au8CreatorId[4]; /**< ID for the ASL compiler */
271 uint32_t u32CreatorRev; /**< revision for the ASL compiler */
272};
273AssertCompileSize(ACPITBLHEADER, 36);
274
275/** Root System Description Table */
276struct ACPITBLRSDT
277{
278 ACPITBLHEADER header;
279 uint32_t u32Entry[1]; /**< array of phys. addresses to other tables */
280};
281AssertCompileSize(ACPITBLRSDT, 40);
282
283/** Extended System Description Table */
284struct ACPITBLXSDT
285{
286 ACPITBLHEADER header;
287 uint64_t u64Entry[1]; /**< array of phys. addresses to other tables */
288};
289AssertCompileSize(ACPITBLXSDT, 44);
290
291/** Fixed ACPI Description Table */
292struct ACPITBLFADT
293{
294 ACPITBLHEADER header;
295 uint32_t u32FACS; /**< phys. address of FACS */
296 uint32_t u32DSDT; /**< phys. address of DSDT */
297 uint8_t u8IntModel; /**< was eleminated in ACPI 2.0 */
298#define INT_MODEL_DUAL_PIC 1 /**< for ACPI 2+ */
299#define INT_MODEL_MULTIPLE_APIC 2
300 uint8_t u8PreferredPMProfile; /**< preferred power management profile */
301 uint16_t u16SCIInt; /**< system vector the SCI is wired in 8259 mode */
302#define SCI_INT 9
303 uint32_t u32SMICmd; /**< system port address of SMI command port */
304#define SMI_CMD 0x0000442e
305 uint8_t u8AcpiEnable; /**< SMICmd val to disable ownship of ACPIregs */
306#define ACPI_ENABLE 0xa1
307 uint8_t u8AcpiDisable; /**< SMICmd val to re-enable ownship of ACPIregs */
308#define ACPI_DISABLE 0xa0
309 uint8_t u8S4BIOSReq; /**< SMICmd val to enter S4BIOS state */
310 uint8_t u8PStateCnt; /**< SMICmd val to assume processor performance
311 state control responsibility */
312 uint32_t u32PM1aEVTBLK; /**< port addr of PM1a event regs block */
313 uint32_t u32PM1bEVTBLK; /**< port addr of PM1b event regs block */
314 uint32_t u32PM1aCTLBLK; /**< port addr of PM1a control regs block */
315 uint32_t u32PM1bCTLBLK; /**< port addr of PM1b control regs block */
316 uint32_t u32PM2CTLBLK; /**< port addr of PM2 control regs block */
317 uint32_t u32PMTMRBLK; /**< port addr of PMTMR regs block */
318 uint32_t u32GPE0BLK; /**< port addr of gen-purp event 0 regs block */
319 uint32_t u32GPE1BLK; /**< port addr of gen-purp event 1 regs block */
320 uint8_t u8PM1EVTLEN; /**< bytes decoded by PM1a_EVT_BLK. >= 4 */
321 uint8_t u8PM1CTLLEN; /**< bytes decoded by PM1b_CNT_BLK. >= 2 */
322 uint8_t u8PM2CTLLEN; /**< bytes decoded by PM2_CNT_BLK. >= 1 or 0 */
323 uint8_t u8PMTMLEN; /**< bytes decoded by PM_TMR_BLK. ==4 */
324 uint8_t u8GPE0BLKLEN; /**< bytes decoded by GPE0_BLK. %2==0 */
325#define GPE0_BLK_LEN 2
326 uint8_t u8GPE1BLKLEN; /**< bytes decoded by GPE1_BLK. %2==0 */
327#define GPE1_BLK_LEN 0
328 uint8_t u8GPE1BASE; /**< offset of GPE1 based events */
329#define GPE1_BASE 0
330 uint8_t u8CSTCNT; /**< SMICmd val to indicate OS supp for C states */
331 uint16_t u16PLVL2LAT; /**< us to enter/exit C2. >100 => unsupported */
332#define P_LVL2_LAT 101 /**< C2 state not supported */
333 uint16_t u16PLVL3LAT; /**< us to enter/exit C3. >1000 => unsupported */
334#define P_LVL3_LAT 1001 /**< C3 state not supported */
335 uint16_t u16FlushSize; /**< # of flush strides to read to flush dirty
336 lines from any processors memory caches */
337#define FLUSH_SIZE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
338 uint16_t u16FlushStride; /**< cache line width */
339#define FLUSH_STRIDE 0 /**< Ignored if WBVIND set in FADT_FLAGS */
340 uint8_t u8DutyOffset;
341 uint8_t u8DutyWidth;
342 uint8_t u8DayAlarm; /**< RTC CMOS RAM index of day-of-month alarm */
343 uint8_t u8MonAlarm; /**< RTC CMOS RAM index of month-of-year alarm */
344 uint8_t u8Century; /**< RTC CMOS RAM index of century */
345 uint16_t u16IAPCBOOTARCH; /**< IA-PC boot architecture flags */
346#define IAPC_BOOT_ARCH_LEGACY_DEV RT_BIT(0) /**< legacy devices present such as LPT
347 (COM too?) */
348#define IAPC_BOOT_ARCH_8042 RT_BIT(1) /**< legacy keyboard device present */
349#define IAPC_BOOT_ARCH_NO_VGA RT_BIT(2) /**< VGA not present */
350 uint8_t u8Must0_0; /**< must be 0 */
351 uint32_t u32Flags; /**< fixed feature flags */
352#define FADT_FL_WBINVD RT_BIT(0) /**< emulation of WBINVD available */
353#define FADT_FL_WBINVD_FLUSH RT_BIT(1)
354#define FADT_FL_PROC_C1 RT_BIT(2) /**< 1=C1 supported on all processors */
355#define FADT_FL_P_LVL2_UP RT_BIT(3) /**< 1=C2 works on SMP and UNI systems */
356#define FADT_FL_PWR_BUTTON RT_BIT(4) /**< 1=power button handled as ctrl method dev */
357#define FADT_FL_SLP_BUTTON RT_BIT(5) /**< 1=sleep button handled as ctrl method dev */
358#define FADT_FL_FIX_RTC RT_BIT(6) /**< 0=RTC wake status in fixed register */
359#define FADT_FL_RTC_S4 RT_BIT(7) /**< 1=RTC can wake system from S4 */
360#define FADT_FL_TMR_VAL_EXT RT_BIT(8) /**< 1=TMR_VAL implemented as 32 bit */
361#define FADT_FL_DCK_CAP RT_BIT(9) /**< 0=system cannot support docking */
362#define FADT_FL_RESET_REG_SUP RT_BIT(10) /**< 1=system supports system resets */
363#define FADT_FL_SEALED_CASE RT_BIT(11) /**< 1=case is sealed */
364#define FADT_FL_HEADLESS RT_BIT(12) /**< 1=system cannot detect moni/keyb/mouse */
365#define FADT_FL_CPU_SW_SLP RT_BIT(13)
366#define FADT_FL_PCI_EXT_WAK RT_BIT(14) /**< 1=system supports PCIEXP_WAKE_STS */
367#define FADT_FL_USE_PLATFORM_CLOCK RT_BIT(15) /**< 1=system has ACPI PM timer */
368#define FADT_FL_S4_RTC_STS_VALID RT_BIT(16) /**< 1=RTC_STS flag is valid when waking from S4 */
369#define FADT_FL_REMOVE_POWER_ON_CAPABLE RT_BIT(17) /**< 1=platform can remote power on */
370#define FADT_FL_FORCE_APIC_CLUSTER_MODEL RT_BIT(18)
371#define FADT_FL_FORCE_APIC_PHYS_DEST_MODE RT_BIT(19)
372 ACPIGENADDR ResetReg; /**< ext addr of reset register */
373 uint8_t u8ResetVal; /**< ResetReg value to reset the system */
374#define ACPI_RESET_REG_VAL 0x10
375 uint8_t au8Must0_1[3]; /**< must be 0 */
376 uint64_t u64XFACS; /**< 64-bit phys address of FACS */
377 uint64_t u64XDSDT; /**< 64-bit phys address of DSDT */
378 ACPIGENADDR X_PM1aEVTBLK; /**< ext addr of PM1a event regs block */
379 ACPIGENADDR X_PM1bEVTBLK; /**< ext addr of PM1b event regs block */
380 ACPIGENADDR X_PM1aCTLBLK; /**< ext addr of PM1a control regs block */
381 ACPIGENADDR X_PM1bCTLBLK; /**< ext addr of PM1b control regs block */
382 ACPIGENADDR X_PM2CTLBLK; /**< ext addr of PM2 control regs block */
383 ACPIGENADDR X_PMTMRBLK; /**< ext addr of PMTMR control regs block */
384 ACPIGENADDR X_GPE0BLK; /**< ext addr of GPE1 regs block */
385 ACPIGENADDR X_GPE1BLK; /**< ext addr of GPE1 regs block */
386};
387AssertCompileSize(ACPITBLFADT, 244);
388
389/** Firmware ACPI Control Structure */
390struct ACPITBLFACS
391{
392 uint8_t au8Signature[4]; /**< 'FACS' */
393 uint32_t u32Length; /**< bytes of entire FACS structure >= 64 */
394 uint32_t u32HWSignature; /**< systems HW signature at last boot */
395 uint32_t u32FWVector; /**< address of waking vector */
396 uint32_t u32GlobalLock; /**< global lock to sync HW/SW */
397 uint32_t u32Flags; /**< FACS flags */
398 uint64_t u64X_FWVector; /**< 64-bit waking vector */
399 uint8_t u8Version; /**< version of this table */
400 uint8_t au8Reserved[31]; /**< zero */
401};
402AssertCompileSize(ACPITBLFACS, 64);
403
404/** Processor Local APIC Structure */
405struct ACPITBLLAPIC
406{
407 uint8_t u8Type; /**< 0 = LAPIC */
408 uint8_t u8Length; /**< 8 */
409 uint8_t u8ProcId; /**< processor ID */
410 uint8_t u8ApicId; /**< local APIC ID */
411 uint32_t u32Flags; /**< Flags */
412#define LAPIC_ENABLED 0x1
413};
414AssertCompileSize(ACPITBLLAPIC, 8);
415
416/** I/O APIC Structure */
417struct ACPITBLIOAPIC
418{
419 uint8_t u8Type; /**< 1 == I/O APIC */
420 uint8_t u8Length; /**< 12 */
421 uint8_t u8IOApicId; /**< I/O APIC ID */
422 uint8_t u8Reserved; /**< 0 */
423 uint32_t u32Address; /**< phys address to access I/O APIC */
424 uint32_t u32GSIB; /**< global system interrupt number to start */
425};
426AssertCompileSize(ACPITBLIOAPIC, 12);
427
428#ifdef VBOX_WITH_SMP_GUESTS
429# ifdef IN_RING3 /**@todo r=bird: Move this down to where it's used. */
430
431# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
432
433/**
434 * Multiple APIC Description Table.
435 *
436 * This structure looks somewhat convoluted due layout of MADT table in MP case.
437 * There extpected to be multiple LAPIC records for each CPU, thus we cannot
438 * use regular C structure and proxy to raw memory instead.
439 */
440class AcpiTableMADT
441{
442 /**
443 * All actual data stored in dynamically allocated memory pointed by this field.
444 */
445 uint8_t *m_pbData;
446 /**
447 * Number of CPU entries in this MADT.
448 */
449 uint32_t m_cCpus;
450
451public:
452 /**
453 * Address of ACPI header
454 */
455 inline ACPITBLHEADER *header_addr(void) const
456 {
457 return (ACPITBLHEADER *)m_pbData;
458 }
459
460 /**
461 * Address of local APIC for each CPU. Note that different CPUs address different LAPICs,
462 * although address is the same for all of them.
463 */
464 inline uint32_t *u32LAPIC_addr(void) const
465 {
466 return (uint32_t *)(header_addr() + 1);
467 }
468
469 /**
470 * Address of APIC flags
471 */
472 inline uint32_t *u32Flags_addr(void) const
473 {
474 return (uint32_t *)(u32LAPIC_addr() + 1);
475 }
476
477 /**
478 * Address of per-CPU LAPIC descriptions
479 */
480 inline ACPITBLLAPIC *LApics_addr(void) const
481 {
482 return (ACPITBLLAPIC *)(u32Flags_addr() + 1);
483 }
484
485 /**
486 * Address of IO APIC description
487 */
488 inline ACPITBLIOAPIC *IOApic_addr(void) const
489 {
490 return (ACPITBLIOAPIC *)(LApics_addr() + m_cCpus);
491 }
492
493 /**
494 * Size of MADT.
495 * Note that this function assumes IOApic to be the last field in structure.
496 */
497 inline uint32_t size(void) const
498 {
499 return (uint8_t *)(IOApic_addr() + 1) - (uint8_t *)header_addr();
500 }
501
502 /**
503 * Raw data of MADT.
504 */
505 inline const uint8_t *data(void) const
506 {
507 return m_pbData;
508 }
509
510 /**
511 * Size of MADT for given ACPI config, useful to compute layout.
512 */
513 static uint32_t sizeFor(ACPIState *s)
514 {
515 return AcpiTableMADT(s->cCpus).size();
516 }
517
518 /*
519 * Constructor, only works in Ring 3, doesn't look like a big deal.
520 */
521 AcpiTableMADT(uint32_t cCpus)
522 {
523 m_cCpus = cCpus;
524 uint32_t cb = size();
525 m_pbData = (uint8_t *)RTMemAllocZ(cb);
526 }
527
528 ~AcpiTableMADT()
529 {
530 RTMemFree(m_pbData);
531 }
532};
533# endif /* IN_RING3 */
534
535#else /* !VBOX_WITH_SMP_GUESTS */
536/** Multiple APIC Description Table */
537struct ACPITBLMADT
538{
539 ACPITBLHEADER header;
540 uint32_t u32LAPIC; /**< local APIC address */
541 uint32_t u32Flags; /**< Flags */
542# define PCAT_COMPAT 0x1 /**< system has also a dual-8259 setup */
543 ACPITBLLAPIC LApic;
544 ACPITBLIOAPIC IOApic;
545};
546AssertCompileSize(ACPITBLMADT, 64);
547#endif /* !VBOX_WITH_SMP_GUESTS */
548
549#pragma pack()
550
551
552#ifndef VBOX_DEVICE_STRUCT_TESTCASE /* exclude the rest of the file */
553/*******************************************************************************
554* Internal Functions *
555*******************************************************************************/
556__BEGIN_DECLS
557PDMBOTHCBDECL(int) acpiPMTmrRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
558#ifdef IN_RING3
559PDMBOTHCBDECL(int) acpiPm1aEnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
560PDMBOTHCBDECL(int) acpiPM1aEnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
561PDMBOTHCBDECL(int) acpiPm1aStsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
562PDMBOTHCBDECL(int) acpiPM1aStsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
563PDMBOTHCBDECL(int) acpiPm1aCtlRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
564PDMBOTHCBDECL(int) acpiPM1aCtlWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
565PDMBOTHCBDECL(int) acpiSmiWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
566PDMBOTHCBDECL(int) acpiBatIndexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
567PDMBOTHCBDECL(int) acpiBatDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
568PDMBOTHCBDECL(int) acpiSysInfoDataRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
569PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
570PDMBOTHCBDECL(int) acpiGpe0EnRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
571PDMBOTHCBDECL(int) acpiGpe0EnWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
572PDMBOTHCBDECL(int) acpiGpe0StsRead( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
573PDMBOTHCBDECL(int) acpiGpe0StsWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
574PDMBOTHCBDECL(int) acpiResetWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
575# ifdef DEBUG_ACPI
576PDMBOTHCBDECL(int) acpiDhexWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
577PDMBOTHCBDECL(int) acpiDchrWrite( PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
578# endif
579#endif /* IN_RING3 */
580__END_DECLS
581
582
583#ifdef IN_RING3
584
585/* Simple acpiChecksum: all the bytes must add up to 0. */
586static uint8_t acpiChecksum(const uint8_t * const data, size_t len)
587{
588 uint8_t sum = 0;
589 for (size_t i = 0; i < len; ++i)
590 sum += data[i];
591 return -sum;
592}
593
594static void acpiPrepareHeader(ACPITBLHEADER *header, const char au8Signature[4],
595 uint32_t u32Length, uint8_t u8Revision)
596{
597 memcpy(header->au8Signature, au8Signature, 4);
598 header->u32Length = RT_H2LE_U32(u32Length);
599 header->u8Revision = u8Revision;
600 memcpy(header->au8OemId, "VBOX ", 6);
601 memcpy(header->au8OemTabId, "VBOX", 4);
602 memcpy(header->au8OemTabId+4, au8Signature, 4);
603 header->u32OemRevision = RT_H2LE_U32(1);
604 memcpy(header->au8CreatorId, "ASL ", 4);
605 header->u32CreatorRev = RT_H2LE_U32(0x61);
606}
607
608static void acpiWriteGenericAddr(ACPIGENADDR *g, uint8_t u8AddressSpaceId,
609 uint8_t u8RegisterBitWidth, uint8_t u8RegisterBitOffset,
610 uint8_t u8AccessSize, uint64_t u64Address)
611{
612 g->u8AddressSpaceId = u8AddressSpaceId;
613 g->u8RegisterBitWidth = u8RegisterBitWidth;
614 g->u8RegisterBitOffset = u8RegisterBitOffset;
615 g->u8AccessSize = u8AccessSize;
616 g->u64Address = RT_H2LE_U64(u64Address);
617}
618
619static void acpiPhyscpy(ACPIState *s, RTGCPHYS32 dst, const void * const src, size_t size)
620{
621 PDMDevHlpPhysWrite(s->pDevIns, dst, src, size);
622}
623
624/** Differentiated System Description Table (DSDT) */
625static void acpiSetupDSDT(ACPIState *s, RTGCPHYS32 addr)
626{
627 acpiPhyscpy(s, addr, AmlCode, sizeof(AmlCode));
628}
629
630/** Firmware ACPI Control Structure (FACS) */
631static void acpiSetupFACS(ACPIState *s, RTGCPHYS32 addr)
632{
633 ACPITBLFACS facs;
634
635 memset(&facs, 0, sizeof(facs));
636 memcpy(facs.au8Signature, "FACS", 4);
637 facs.u32Length = RT_H2LE_U32(sizeof(ACPITBLFACS));
638 facs.u32HWSignature = RT_H2LE_U32(0);
639 facs.u32FWVector = RT_H2LE_U32(0);
640 facs.u32GlobalLock = RT_H2LE_U32(0);
641 facs.u32Flags = RT_H2LE_U32(0);
642 facs.u64X_FWVector = RT_H2LE_U64(0);
643 facs.u8Version = 1;
644
645 acpiPhyscpy(s, addr, (const uint8_t *)&facs, sizeof(facs));
646}
647
648/** Fixed ACPI Description Table (FADT aka FACP) */
649static void acpiSetupFADT(ACPIState *s, RTGCPHYS32 addr, uint32_t facs_addr, uint32_t dsdt_addr)
650{
651 ACPITBLFADT fadt;
652
653 memset(&fadt, 0, sizeof(fadt));
654 acpiPrepareHeader(&fadt.header, "FACP", sizeof(fadt), 4);
655 fadt.u32FACS = RT_H2LE_U32(facs_addr);
656 fadt.u32DSDT = RT_H2LE_U32(dsdt_addr);
657 fadt.u8IntModel = INT_MODEL_DUAL_PIC;
658 fadt.u8PreferredPMProfile = 0; /* unspecified */
659 fadt.u16SCIInt = RT_H2LE_U16(SCI_INT);
660 fadt.u32SMICmd = RT_H2LE_U32(SMI_CMD);
661 fadt.u8AcpiEnable = ACPI_ENABLE;
662 fadt.u8AcpiDisable = ACPI_DISABLE;
663 fadt.u8S4BIOSReq = 0;
664 fadt.u8PStateCnt = 0;
665 fadt.u32PM1aEVTBLK = RT_H2LE_U32(PM1a_EVT_BLK);
666 fadt.u32PM1bEVTBLK = RT_H2LE_U32(PM1b_EVT_BLK);
667 fadt.u32PM1aCTLBLK = RT_H2LE_U32(PM1a_CTL_BLK);
668 fadt.u32PM1bCTLBLK = RT_H2LE_U32(PM1b_CTL_BLK);
669 fadt.u32PM2CTLBLK = RT_H2LE_U32(PM2_CTL_BLK);
670 fadt.u32PMTMRBLK = RT_H2LE_U32(PM_TMR_BLK);
671 fadt.u32GPE0BLK = RT_H2LE_U32(GPE0_BLK);
672 fadt.u32GPE1BLK = RT_H2LE_U32(GPE1_BLK);
673 fadt.u8PM1EVTLEN = 4;
674 fadt.u8PM1CTLLEN = 2;
675 fadt.u8PM2CTLLEN = 0;
676 fadt.u8PMTMLEN = 4;
677 fadt.u8GPE0BLKLEN = GPE0_BLK_LEN;
678 fadt.u8GPE1BLKLEN = GPE1_BLK_LEN;
679 fadt.u8GPE1BASE = GPE1_BASE;
680 fadt.u8CSTCNT = 0;
681 fadt.u16PLVL2LAT = RT_H2LE_U16(P_LVL2_LAT);
682 fadt.u16PLVL3LAT = RT_H2LE_U16(P_LVL3_LAT);
683 fadt.u16FlushSize = RT_H2LE_U16(FLUSH_SIZE);
684 fadt.u16FlushStride = RT_H2LE_U16(FLUSH_STRIDE);
685 fadt.u8DutyOffset = 0;
686 fadt.u8DutyWidth = 0;
687 fadt.u8DayAlarm = 0;
688 fadt.u8MonAlarm = 0;
689 fadt.u8Century = 0;
690 fadt.u16IAPCBOOTARCH = RT_H2LE_U16(IAPC_BOOT_ARCH_LEGACY_DEV | IAPC_BOOT_ARCH_8042);
691 /** @note WBINVD is required for ACPI versions newer than 1.0 */
692 fadt.u32Flags = RT_H2LE_U32( FADT_FL_WBINVD
693 | FADT_FL_FIX_RTC
694 | FADT_FL_TMR_VAL_EXT);
695 acpiWriteGenericAddr(&fadt.ResetReg, 1, 8, 0, 1, ACPI_RESET_BLK);
696 fadt.u8ResetVal = ACPI_RESET_REG_VAL;
697 fadt.u64XFACS = RT_H2LE_U64((uint64_t)facs_addr);
698 fadt.u64XDSDT = RT_H2LE_U64((uint64_t)dsdt_addr);
699 acpiWriteGenericAddr(&fadt.X_PM1aEVTBLK, 1, 32, 0, 2, PM1a_EVT_BLK);
700 acpiWriteGenericAddr(&fadt.X_PM1bEVTBLK, 0, 0, 0, 0, PM1b_EVT_BLK);
701 acpiWriteGenericAddr(&fadt.X_PM1aCTLBLK, 1, 16, 0, 2, PM1a_CTL_BLK);
702 acpiWriteGenericAddr(&fadt.X_PM1bCTLBLK, 0, 0, 0, 0, PM1b_CTL_BLK);
703 acpiWriteGenericAddr(&fadt.X_PM2CTLBLK, 0, 0, 0, 0, PM2_CTL_BLK);
704 acpiWriteGenericAddr(&fadt.X_PMTMRBLK, 1, 32, 0, 3, PM_TMR_BLK);
705 acpiWriteGenericAddr(&fadt.X_GPE0BLK, 1, 16, 0, 1, GPE0_BLK);
706 acpiWriteGenericAddr(&fadt.X_GPE1BLK, 0, 0, 0, 0, GPE1_BLK);
707 fadt.header.u8Checksum = acpiChecksum((uint8_t *)&fadt, sizeof(fadt));
708 acpiPhyscpy(s, addr, &fadt, sizeof(fadt));
709}
710
711/**
712 * Root System Description Table.
713 * The RSDT and XSDT tables are basically identical. The only difference is 32 vs 64 bits
714 * addresses for description headers. RSDT is for ACPI 1.0. XSDT for ACPI 2.0 and up.
715 */
716static int acpiSetupRSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
717{
718 ACPITBLRSDT *rsdt;
719 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(rsdt->u32Entry[0]);
720
721 rsdt = (ACPITBLRSDT*)RTMemAllocZ(size);
722 if (!rsdt)
723 return PDMDEV_SET_ERROR(s->pDevIns, VERR_NO_TMP_MEMORY, N_("Cannot allocate RSDT"));
724
725 acpiPrepareHeader(&rsdt->header, "RSDT", (uint32_t)size, 1);
726 for (unsigned int i = 0; i < nb_entries; ++i)
727 {
728 rsdt->u32Entry[i] = RT_H2LE_U32(addrs[i]);
729 Log(("Setup RSDT: [%d] = %x\n", i, rsdt->u32Entry[i]));
730 }
731 rsdt->header.u8Checksum = acpiChecksum((uint8_t*)rsdt, size);
732 acpiPhyscpy(s, addr, rsdt, size);
733 RTMemFree(rsdt);
734 return VINF_SUCCESS;
735}
736
737/** Extended System Description Table. */
738static int acpiSetupXSDT(ACPIState *s, RTGCPHYS32 addr, unsigned int nb_entries, uint32_t *addrs)
739{
740 ACPITBLXSDT *xsdt;
741 const size_t size = sizeof(ACPITBLHEADER) + nb_entries * sizeof(xsdt->u64Entry[0]);
742
743 xsdt = (ACPITBLXSDT*)RTMemAllocZ(size);
744 if (!xsdt)
745 return VERR_NO_TMP_MEMORY;
746
747 acpiPrepareHeader(&xsdt->header, "XSDT", (uint32_t)size, 1 /* according to ACPI 3.0 specs */);
748 for (unsigned int i = 0; i < nb_entries; ++i)
749 {
750 xsdt->u64Entry[i] = RT_H2LE_U64((uint64_t)addrs[i]);
751 Log(("Setup XSDT: [%d] = %RX64\n", i, xsdt->u64Entry[i]));
752 }
753 xsdt->header.u8Checksum = acpiChecksum((uint8_t*)xsdt, size);
754 acpiPhyscpy(s, addr, xsdt, size);
755 RTMemFree(xsdt);
756 return VINF_SUCCESS;
757}
758
759/** Root System Description Pointer (RSDP) */
760static void acpiSetupRSDP(ACPITBLRSDP *rsdp, uint32_t rsdt_addr, uint64_t xsdt_addr)
761{
762 memset(rsdp, 0, sizeof(*rsdp));
763
764 /* ACPI 1.0 part (RSDT */
765 memcpy(rsdp->au8Signature, "RSD PTR ", 8);
766 memcpy(rsdp->au8OemId, "VBOX ", 6);
767 rsdp->u8Revision = ACPI_REVISION;
768 rsdp->u32RSDT = RT_H2LE_U32(rsdt_addr);
769 rsdp->u8Checksum = acpiChecksum((uint8_t*)rsdp, RT_OFFSETOF(ACPITBLRSDP, u32Length));
770
771 /* ACPI 2.0 part (XSDT) */
772 rsdp->u32Length = RT_H2LE_U32(sizeof(ACPITBLRSDP));
773 rsdp->u64XSDT = RT_H2LE_U64(xsdt_addr);
774 rsdp->u8ExtChecksum = acpiChecksum((uint8_t*)rsdp, sizeof(ACPITBLRSDP));
775}
776
777/**
778 * Multiple APIC Description Table.
779 *
780 * @note APIC without IO-APIC hangs Windows Vista therefore we setup both
781 *
782 * @todo All hardcoded, should set this up based on the actual VM config!!!!!
783 */
784static void acpiSetupMADT(ACPIState *s, RTGCPHYS32 addr)
785{
786#ifdef VBOX_WITH_SMP_GUESTS
787 uint16_t cpus = s->cCpus;
788 AcpiTableMADT madt(cpus);
789
790 acpiPrepareHeader(madt.header_addr(), "APIC", madt.size(), 2);
791
792 *madt.u32LAPIC_addr() = RT_H2LE_U32(0xfee00000);
793 *madt.u32Flags_addr() = RT_H2LE_U32(PCAT_COMPAT);
794
795 ACPITBLLAPIC* lapic = madt.LApics_addr();
796 for (uint16_t i = 0; i < cpus; i++)
797 {
798 lapic->u8Type = 0;
799 lapic->u8Length = sizeof(ACPITBLLAPIC);
800 lapic->u8ProcId = i;
801 lapic->u8ApicId = i;
802 lapic->u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
803 lapic++;
804 }
805
806 ACPITBLIOAPIC* ioapic = madt.IOApic_addr();
807
808 ioapic->u8Type = 1;
809 ioapic->u8Length = sizeof(ACPITBLIOAPIC);
810 ioapic->u8IOApicId = cpus;
811 ioapic->u8Reserved = 0;
812 ioapic->u32Address = RT_H2LE_U32(0xfec00000);
813 ioapic->u32GSIB = RT_H2LE_U32(0);
814
815 madt.header_addr()->u8Checksum = acpiChecksum(madt.data(), madt.size());
816 acpiPhyscpy(s, addr, madt.data(), madt.size());
817
818#else /* !VBOX_WITH_SMP_GUESTS */
819 ACPITBLMADT madt;
820
821 /* Don't call this function if u8UseIOApic==false! */
822 Assert(s->u8UseIOApic);
823
824 memset(&madt, 0, sizeof(madt));
825 acpiPrepareHeader(&madt.header, "APIC", sizeof(madt), 2);
826
827 madt.u32LAPIC = RT_H2LE_U32(0xfee00000);
828 madt.u32Flags = RT_H2LE_U32(PCAT_COMPAT);
829
830 madt.LApic.u8Type = 0;
831 madt.LApic.u8Length = sizeof(ACPITBLLAPIC);
832 madt.LApic.u8ProcId = 0;
833 madt.LApic.u8ApicId = 0;
834 madt.LApic.u32Flags = RT_H2LE_U32(LAPIC_ENABLED);
835
836 madt.IOApic.u8Type = 1;
837 madt.IOApic.u8Length = sizeof(ACPITBLIOAPIC);
838 madt.IOApic.u8IOApicId = 1;
839 madt.IOApic.u8Reserved = 0;
840 madt.IOApic.u32Address = RT_H2LE_U32(0xfec00000);
841 madt.IOApic.u32GSIB = RT_H2LE_U32(0);
842
843 madt.header.u8Checksum = acpiChecksum((uint8_t*)&madt, sizeof(madt));
844 acpiPhyscpy(s, addr, &madt, sizeof(madt));
845#endif /* !VBOX_WITH_SMP_GUESTS */
846}
847
848/* SCI IRQ */
849DECLINLINE(void) acpiSetIrq(ACPIState *s, int level)
850{
851 if (s->pm1a_ctl & SCI_EN)
852 PDMDevHlpPCISetIrq(s->pDevIns, -1, level);
853}
854
855DECLINLINE(uint32_t) pm1a_pure_en(uint32_t en)
856{
857 return en & ~(RSR_EN | IGN_EN);
858}
859
860DECLINLINE(uint32_t) pm1a_pure_sts(uint32_t sts)
861{
862 return sts & ~(RSR_STS | IGN_STS);
863}
864
865DECLINLINE(int) pm1a_level(ACPIState *s)
866{
867 return (pm1a_pure_en(s->pm1a_en) & pm1a_pure_sts(s->pm1a_sts)) != 0;
868}
869
870DECLINLINE(int) gpe0_level(ACPIState *s)
871{
872 return (s->gpe0_en & s->gpe0_sts) != 0;
873}
874
875static void update_pm1a(ACPIState *s, uint32_t sts, uint32_t en)
876{
877 int old_level, new_level;
878
879 if (gpe0_level(s))
880 return;
881
882 old_level = pm1a_level(s);
883 new_level = (pm1a_pure_en(en) & pm1a_pure_sts(sts)) != 0;
884
885 s->pm1a_en = en;
886 s->pm1a_sts = sts;
887
888 if (new_level != old_level)
889 acpiSetIrq(s, new_level);
890}
891
892static void update_gpe0(ACPIState *s, uint32_t sts, uint32_t en)
893{
894 int old_level, new_level;
895
896 if (pm1a_level(s))
897 return;
898
899 old_level = (s->gpe0_en & s->gpe0_sts) != 0;
900 new_level = (en & sts) != 0;
901
902 s->gpe0_en = en;
903 s->gpe0_sts = sts;
904
905 if (new_level != old_level)
906 acpiSetIrq(s, new_level);
907}
908
909static int acpiPowerDown(ACPIState *s)
910{
911 int rc = PDMDevHlpVMPowerOff(s->pDevIns);
912 if (RT_FAILURE(rc))
913 AssertMsgFailed(("Could not power down the VM. rc = %Rrc\n", rc));
914 return rc;
915}
916
917/** Converts a ACPI port interface pointer to an ACPI state pointer. */
918#define IACPIPORT_2_ACPISTATE(pInterface) ( (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IACPIPort)) )
919
920/**
921 * Send an ACPI power off event.
922 *
923 * @returns VBox status code
924 * @param pInterface Pointer to the interface structure containing the called function pointer.
925 */
926static DECLCALLBACK(int) acpiPowerButtonPress(PPDMIACPIPORT pInterface)
927{
928 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
929 s->fPowerButtonHandled = false;
930 update_pm1a(s, s->pm1a_sts | PWRBTN_STS, s->pm1a_en);
931 return VINF_SUCCESS;
932}
933
934/**
935 * Check if the ACPI power button event was handled.
936 *
937 * @returns VBox status code
938 * @param pInterface Pointer to the interface structure containing the called function pointer.
939 * @param pfHandled Return true if the power button event was handled by the guest.
940 */
941static DECLCALLBACK(int) acpiGetPowerButtonHandled(PPDMIACPIPORT pInterface, bool *pfHandled)
942{
943 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
944 *pfHandled = s->fPowerButtonHandled;
945 return VINF_SUCCESS;
946}
947
948/**
949 * Check if the Guest entered into G0 (working) or G1 (sleeping).
950 *
951 * @returns VBox status code
952 * @param pInterface Pointer to the interface structure containing the called function pointer.
953 * @param pfEntered Return true if the guest entered the ACPI mode.
954 */
955static DECLCALLBACK(int) acpiGetGuestEnteredACPIMode(PPDMIACPIPORT pInterface, bool *pfEntered)
956{
957 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
958 *pfEntered = (s->pm1a_ctl & SCI_EN) != 0;
959 return VINF_SUCCESS;
960}
961
962/**
963 * Send an ACPI sleep button event.
964 *
965 * @returns VBox status code
966 * @param pInterface Pointer to the interface structure containing the called function pointer.
967 */
968static DECLCALLBACK(int) acpiSleepButtonPress(PPDMIACPIPORT pInterface)
969{
970 ACPIState *s = IACPIPORT_2_ACPISTATE(pInterface);
971 update_pm1a(s, s->pm1a_sts | SLPBTN_STS, s->pm1a_en);
972 return VINF_SUCCESS;
973}
974
975/* PM1a_EVT_BLK enable */
976static uint32_t acpiPm1aEnReadw(ACPIState *s, uint32_t addr)
977{
978 uint16_t val = s->pm1a_en;
979 Log(("acpi: acpiPm1aEnReadw -> %#x\n", val));
980 return val;
981}
982
983static void acpiPM1aEnWritew(ACPIState *s, uint32_t addr, uint32_t val)
984{
985 Log(("acpi: acpiPM1aEnWritew <- %#x (%#x)\n", val, val & ~(RSR_EN | IGN_EN)));
986 val &= ~(RSR_EN | IGN_EN);
987 update_pm1a(s, s->pm1a_sts, val);
988}
989
990/* PM1a_EVT_BLK status */
991static uint32_t acpiPm1aStsReadw(ACPIState *s, uint32_t addr)
992{
993 uint16_t val = s->pm1a_sts;
994 Log(("acpi: acpiPm1aStsReadw -> %#x\n", val));
995 return val;
996}
997
998static void acpiPM1aStsWritew(ACPIState *s, uint32_t addr, uint32_t val)
999{
1000 Log(("acpi: acpiPM1aStsWritew <- %#x (%#x)\n", val, val & ~(RSR_STS | IGN_STS)));
1001 if (val & PWRBTN_STS)
1002 s->fPowerButtonHandled = true; /* Remember that the guest handled the last power button event */
1003 val = s->pm1a_sts & ~(val & ~(RSR_STS | IGN_STS));
1004 update_pm1a(s, val, s->pm1a_en);
1005}
1006
1007/* PM1a_CTL_BLK */
1008static uint32_t acpiPm1aCtlReadw(ACPIState *s, uint32_t addr)
1009{
1010 uint16_t val = s->pm1a_ctl;
1011 Log(("acpi: acpiPm1aCtlReadw -> %#x\n", val));
1012 return val;
1013}
1014
1015static int acpiPM1aCtlWritew(ACPIState *s, uint32_t addr, uint32_t val)
1016{
1017 uint32_t uSleepState;
1018
1019 Log(("acpi: acpiPM1aCtlWritew <- %#x (%#x)\n", val, val & ~(RSR_CNT | IGN_CNT)));
1020 s->pm1a_ctl = val & ~(RSR_CNT | IGN_CNT);
1021
1022 uSleepState = (s->pm1a_ctl >> SLP_TYPx_SHIFT) & SLP_TYPx_MASK;
1023 if (uSleepState != s->uSleepState)
1024 {
1025 s->uSleepState = uSleepState;
1026 switch (uSleepState)
1027 {
1028 case 0x00: /* S0 */
1029 break;
1030 case 0x05: /* S5 */
1031 LogRel(("Entering S5 (power down)\n"));
1032 return acpiPowerDown(s);
1033 default:
1034 AssertMsgFailed(("Unknown sleep state %#x\n", uSleepState));
1035 break;
1036 }
1037 }
1038 return VINF_SUCCESS;
1039}
1040
1041/* GPE0_BLK */
1042static uint32_t acpiGpe0EnReadb(ACPIState *s, uint32_t addr)
1043{
1044 uint8_t val = s->gpe0_en;
1045 Log(("acpi: acpiGpe0EnReadl -> %#x\n", val));
1046 return val;
1047}
1048
1049static void acpiGpe0EnWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1050{
1051 Log(("acpi: acpiGpe0EnWritel <- %#x\n", val));
1052 update_gpe0(s, s->gpe0_sts, val);
1053}
1054
1055static uint32_t acpiGpe0StsReadb(ACPIState *s, uint32_t addr)
1056{
1057 uint8_t val = s->gpe0_sts;
1058 Log(("acpi: acpiGpe0StsReadl -> %#x\n", val));
1059 return val;
1060}
1061
1062static void acpiGpe0StsWriteb(ACPIState *s, uint32_t addr, uint32_t val)
1063{
1064 val = s->gpe0_sts & ~val;
1065 update_gpe0(s, val, s->gpe0_en);
1066 Log(("acpi: acpiGpe0StsWritel <- %#x\n", val));
1067}
1068
1069static int acpiResetWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1070{
1071 int rc = VINF_SUCCESS;
1072
1073 Log(("ACPI: acpiResetWriteU8: %x %x\n", addr, val));
1074 if (val == ACPI_RESET_REG_VAL)
1075 {
1076# ifndef IN_RING3
1077 rc = VINF_IOM_HC_IOPORT_WRITE;
1078# else /* IN_RING3 */
1079 rc = PDMDevHlpVMReset(s->pDevIns);
1080# endif /* !IN_RING3 */
1081 }
1082 return rc;
1083}
1084
1085/* SMI */
1086static void acpiSmiWriteU8(ACPIState *s, uint32_t addr, uint32_t val)
1087{
1088 Log(("acpi: acpiSmiWriteU8 %#x\n", val));
1089 if (val == ACPI_ENABLE)
1090 s->pm1a_ctl |= SCI_EN;
1091 else if (val == ACPI_DISABLE)
1092 s->pm1a_ctl &= ~SCI_EN;
1093 else
1094 Log(("acpi: acpiSmiWriteU8 %#x <- unknown value\n", val));
1095}
1096
1097static uint32_t find_rsdp_space(void)
1098{
1099 return 0xe0000;
1100}
1101
1102static void acpiPMTimerReset(ACPIState *s)
1103{
1104 uint64_t interval, freq;
1105
1106 freq = TMTimerGetFreq(s->CTX_SUFF(ts));
1107 interval = ASMMultU64ByU32DivByU32(0xffffffff, freq, PM_TMR_FREQ);
1108 Log(("interval = %RU64\n", interval));
1109 TMTimerSet(s->CTX_SUFF(ts), TMTimerGet(s->CTX_SUFF(ts)) + interval);
1110}
1111
1112static DECLCALLBACK(void) acpiTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer)
1113{
1114 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1115
1116 Log(("acpi: pm timer sts %#x (%d), en %#x (%d)\n",
1117 s->pm1a_sts, (s->pm1a_sts & TMR_STS) != 0,
1118 s->pm1a_en, (s->pm1a_en & TMR_EN) != 0));
1119
1120 update_pm1a(s, s->pm1a_sts | TMR_STS, s->pm1a_en);
1121 acpiPMTimerReset(s);
1122}
1123
1124/**
1125 * _BST method.
1126 */
1127static void acpiFetchBatteryStatus(ACPIState *s)
1128{
1129 uint32_t *p = s->au8BatteryInfo;
1130 bool fPresent; /* battery present? */
1131 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1132 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1133 uint32_t hostPresentRate; /* 0..1000 */
1134 int rc;
1135
1136 if (!s->pDrv)
1137 return;
1138 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1139 &hostBatteryState, &hostPresentRate);
1140 AssertRC(rc);
1141
1142 /* default values */
1143 p[BAT_STATUS_STATE] = hostBatteryState;
1144 p[BAT_STATUS_PRESENT_RATE] = hostPresentRate == ~0U ? 0xFFFFFFFF
1145 : hostPresentRate * 50; /* mW */
1146 p[BAT_STATUS_REMAINING_CAPACITY] = 50000; /* mWh */
1147 p[BAT_STATUS_PRESENT_VOLTAGE] = 10000; /* mV */
1148
1149 /* did we get a valid battery state? */
1150 if (hostRemainingCapacity != PDM_ACPI_BAT_CAPACITY_UNKNOWN)
1151 p[BAT_STATUS_REMAINING_CAPACITY] = hostRemainingCapacity * 500; /* mWh */
1152 if (hostBatteryState == PDM_ACPI_BAT_STATE_CHARGED)
1153 p[BAT_STATUS_PRESENT_RATE] = 0; /* mV */
1154}
1155
1156/**
1157 * _BIF method.
1158 */
1159static void acpiFetchBatteryInfo(ACPIState *s)
1160{
1161 uint32_t *p = s->au8BatteryInfo;
1162
1163 p[BAT_INFO_UNITS] = 0; /* mWh */
1164 p[BAT_INFO_DESIGN_CAPACITY] = 50000; /* mWh */
1165 p[BAT_INFO_LAST_FULL_CHARGE_CAPACITY] = 50000; /* mWh */
1166 p[BAT_INFO_TECHNOLOGY] = BAT_TECH_PRIMARY;
1167 p[BAT_INFO_DESIGN_VOLTAGE] = 10000; /* mV */
1168 p[BAT_INFO_DESIGN_CAPACITY_OF_WARNING] = 100; /* mWh */
1169 p[BAT_INFO_DESIGN_CAPACITY_OF_LOW] = 50; /* mWh */
1170 p[BAT_INFO_CAPACITY_GRANULARITY_1] = 1; /* mWh */
1171 p[BAT_INFO_CAPACITY_GRANULARITY_2] = 1; /* mWh */
1172}
1173
1174/**
1175 * _STA method.
1176 */
1177static uint32_t acpiGetBatteryDeviceStatus(ACPIState *s)
1178{
1179 bool fPresent; /* battery present? */
1180 PDMACPIBATCAPACITY hostRemainingCapacity; /* 0..100 */
1181 PDMACPIBATSTATE hostBatteryState; /* bitfield */
1182 uint32_t hostPresentRate; /* 0..1000 */
1183 int rc;
1184
1185 if (!s->pDrv)
1186 return 0;
1187 rc = s->pDrv->pfnQueryBatteryStatus(s->pDrv, &fPresent, &hostRemainingCapacity,
1188 &hostBatteryState, &hostPresentRate);
1189 AssertRC(rc);
1190
1191 return fPresent
1192 ? STA_DEVICE_PRESENT_MASK /* present */
1193 | STA_DEVICE_ENABLED_MASK /* enabled and decodes its resources */
1194 | STA_DEVICE_SHOW_IN_UI_MASK /* should be shown in UI */
1195 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK /* functioning properly */
1196 | STA_BATTERY_PRESENT_MASK /* battery is present */
1197 : 0; /* device not present */
1198}
1199
1200static uint32_t acpiGetPowerSource(ACPIState *s)
1201{
1202 PDMACPIPOWERSOURCE ps;
1203
1204 /* query the current power source from the host driver */
1205 if (!s->pDrv)
1206 return AC_ONLINE;
1207 int rc = s->pDrv->pfnQueryPowerSource(s->pDrv, &ps);
1208 AssertRC(rc);
1209 return ps == PDM_ACPI_POWER_SOURCE_BATTERY ? AC_OFFLINE : AC_ONLINE;
1210}
1211
1212PDMBOTHCBDECL(int) acpiBatIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1213{
1214 ACPIState *s = (ACPIState *)pvUser;
1215
1216 switch (cb)
1217 {
1218 case 4:
1219 u32 >>= s->u8IndexShift;
1220 /* see comment at the declaration of u8IndexShift */
1221 if (s->u8IndexShift == 0 && u32 == (BAT_DEVICE_STATUS << 2))
1222 {
1223 s->u8IndexShift = 2;
1224 u32 >>= 2;
1225 }
1226 Assert(u32 < BAT_INDEX_LAST);
1227 s->uBatteryIndex = u32;
1228 break;
1229 default:
1230 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1231 break;
1232 }
1233 return VINF_SUCCESS;
1234}
1235
1236PDMBOTHCBDECL(int) acpiBatDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1237{
1238 ACPIState *s = (ACPIState *)pvUser;
1239
1240 switch (cb)
1241 {
1242 case 4:
1243 switch (s->uBatteryIndex)
1244 {
1245 case BAT_STATUS_STATE:
1246 acpiFetchBatteryStatus(s);
1247 case BAT_STATUS_PRESENT_RATE:
1248 case BAT_STATUS_REMAINING_CAPACITY:
1249 case BAT_STATUS_PRESENT_VOLTAGE:
1250 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1251 break;
1252
1253 case BAT_INFO_UNITS:
1254 acpiFetchBatteryInfo(s);
1255 case BAT_INFO_DESIGN_CAPACITY:
1256 case BAT_INFO_LAST_FULL_CHARGE_CAPACITY:
1257 case BAT_INFO_TECHNOLOGY:
1258 case BAT_INFO_DESIGN_VOLTAGE:
1259 case BAT_INFO_DESIGN_CAPACITY_OF_WARNING:
1260 case BAT_INFO_DESIGN_CAPACITY_OF_LOW:
1261 case BAT_INFO_CAPACITY_GRANULARITY_1:
1262 case BAT_INFO_CAPACITY_GRANULARITY_2:
1263 *pu32 = s->au8BatteryInfo[s->uBatteryIndex];
1264 break;
1265
1266 case BAT_DEVICE_STATUS:
1267 *pu32 = acpiGetBatteryDeviceStatus(s);
1268 break;
1269
1270 case BAT_POWER_SOURCE:
1271 *pu32 = acpiGetPowerSource(s);
1272 break;
1273
1274 default:
1275 AssertMsgFailed(("Invalid battery index %d\n", s->uBatteryIndex));
1276 break;
1277 }
1278 break;
1279 default:
1280 return VERR_IOM_IOPORT_UNUSED;
1281 }
1282 return VINF_SUCCESS;
1283}
1284
1285PDMBOTHCBDECL(int) acpiSysInfoIndexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1286{
1287 ACPIState *s = (ACPIState *)pvUser;
1288
1289 Log(("system_index = %d, %d\n", u32, u32 >> 2));
1290 switch (cb)
1291 {
1292 case 4:
1293 if (u32 == SYSTEM_INFO_INDEX_VALID || u32 == SYSTEM_INFO_INDEX_INVALID)
1294 s->uSystemInfoIndex = u32;
1295 else
1296 {
1297 /* see comment at the declaration of u8IndexShift */
1298 if (s->u8IndexShift == 0)
1299 {
1300 if (((u32 >> 2) < SYSTEM_INFO_INDEX_END) && ((u32 & 0x3)) == 0)
1301 {
1302 s->u8IndexShift = 2;
1303 }
1304 }
1305
1306 u32 >>= s->u8IndexShift;
1307 Assert(u32 < SYSTEM_INFO_INDEX_END);
1308 s->uSystemInfoIndex = u32;
1309 }
1310 break;
1311
1312 default:
1313 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1314 break;
1315 }
1316 return VINF_SUCCESS;
1317}
1318
1319PDMBOTHCBDECL(int) acpiSysInfoDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1320{
1321 ACPIState *s = (ACPIState *)pvUser;
1322
1323 switch (cb)
1324 {
1325 case 4:
1326 switch (s->uSystemInfoIndex)
1327 {
1328 case SYSTEM_INFO_INDEX_LOW_MEMORY_LENGTH:
1329 *pu32 = s->cbRamLow;
1330 break;
1331
1332 case SYSTEM_INFO_INDEX_HIGH_MEMORY_LENGTH:
1333 *pu32 = s->cbRamHigh >> 16; /* 64KB units */
1334 Assert(((uint64_t)*pu32 << 16) == s->cbRamHigh);
1335 break;
1336
1337 case SYSTEM_INFO_INDEX_USE_IOAPIC:
1338 *pu32 = s->u8UseIOApic;
1339 break;
1340
1341 case SYSTEM_INFO_INDEX_HPET_STATUS:
1342 *pu32 = s->fUseHpet ? ( STA_DEVICE_PRESENT_MASK
1343 | STA_DEVICE_ENABLED_MASK
1344 | STA_DEVICE_SHOW_IN_UI_MASK
1345 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1346 : 0;
1347 break;
1348
1349 case SYSTEM_INFO_INDEX_SMC_STATUS:
1350 *pu32 = s->fUseSmc ? ( STA_DEVICE_PRESENT_MASK
1351 | STA_DEVICE_ENABLED_MASK
1352 /* no need to show this device in the UI */
1353 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1354 : 0;
1355 break;
1356
1357 case SYSTEM_INFO_INDEX_FDC_STATUS:
1358 *pu32 = s->fUseFdc ? ( STA_DEVICE_PRESENT_MASK
1359 | STA_DEVICE_ENABLED_MASK
1360 | STA_DEVICE_SHOW_IN_UI_MASK
1361 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1362 : 0;
1363 break;
1364 case SYSTEM_INFO_INDEX_CPU0_STATUS:
1365 *pu32 = s->fShowCpu ? ( STA_DEVICE_PRESENT_MASK
1366 | STA_DEVICE_ENABLED_MASK
1367 | STA_DEVICE_SHOW_IN_UI_MASK
1368 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK)
1369 : 0;
1370 break;
1371
1372 case SYSTEM_INFO_INDEX_CPU1_STATUS:
1373 case SYSTEM_INFO_INDEX_CPU2_STATUS:
1374 case SYSTEM_INFO_INDEX_CPU3_STATUS:
1375#ifdef VBOX_WITH_SMP_GUESTS
1376 *pu32 = s->fShowCpu
1377 && s->uSystemInfoIndex - SYSTEM_INFO_INDEX_CPU0_STATUS < s->cCpus
1378 ? STA_DEVICE_PRESENT_MASK
1379 | STA_DEVICE_ENABLED_MASK
1380 | STA_DEVICE_SHOW_IN_UI_MASK
1381 | STA_DEVICE_FUNCTIONING_PROPERLY_MASK
1382 : 0;
1383#else
1384 *pu32 = 0;
1385#endif
1386 break;
1387
1388 /* Solaris 9 tries to read from this index */
1389 case SYSTEM_INFO_INDEX_INVALID:
1390 *pu32 = 0;
1391 break;
1392
1393 default:
1394 AssertMsgFailed(("Invalid system info index %d\n", s->uSystemInfoIndex));
1395 break;
1396 }
1397 break;
1398
1399 default:
1400 return VERR_IOM_IOPORT_UNUSED;
1401 }
1402
1403 Log(("index %d val %d\n", s->uSystemInfoIndex, *pu32));
1404 return VINF_SUCCESS;
1405}
1406
1407PDMBOTHCBDECL(int) acpiSysInfoDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1408{
1409 ACPIState *s = (ACPIState *)pvUser;
1410
1411 Log(("addr=%#x cb=%d u32=%#x si=%#x\n", Port, cb, u32, s->uSystemInfoIndex));
1412
1413 if (cb == 4 && u32 == 0xbadc0de)
1414 {
1415 switch (s->uSystemInfoIndex)
1416 {
1417 case SYSTEM_INFO_INDEX_INVALID:
1418 s->u8IndexShift = 0;
1419 break;
1420
1421 case SYSTEM_INFO_INDEX_VALID:
1422 s->u8IndexShift = 2;
1423 break;
1424
1425 default:
1426 AssertMsgFailed(("Port=%#x cb=%d u32=%#x system_index=%#x\n",
1427 Port, cb, u32, s->uSystemInfoIndex));
1428 break;
1429 }
1430 }
1431 else
1432 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1433 return VINF_SUCCESS;
1434}
1435
1436/** @todo Don't call functions, but do the job in the read/write handlers
1437 * here! */
1438
1439/* IO Helpers */
1440PDMBOTHCBDECL(int) acpiPm1aEnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1441{
1442 switch (cb)
1443 {
1444 case 2:
1445 *pu32 = acpiPm1aEnReadw((ACPIState*)pvUser, Port);
1446 break;
1447 default:
1448 return VERR_IOM_IOPORT_UNUSED;
1449 }
1450 return VINF_SUCCESS;
1451}
1452
1453PDMBOTHCBDECL(int) acpiPm1aStsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1454{
1455 switch (cb)
1456 {
1457 case 2:
1458 *pu32 = acpiPm1aStsReadw((ACPIState*)pvUser, Port);
1459 break;
1460 default:
1461 return VERR_IOM_IOPORT_UNUSED;
1462 }
1463 return VINF_SUCCESS;
1464}
1465
1466PDMBOTHCBDECL(int) acpiPm1aCtlRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1467{
1468 switch (cb)
1469 {
1470 case 2:
1471 *pu32 = acpiPm1aCtlReadw((ACPIState*)pvUser, Port);
1472 break;
1473 default:
1474 return VERR_IOM_IOPORT_UNUSED;
1475 }
1476 return VINF_SUCCESS;
1477}
1478
1479PDMBOTHCBDECL(int) acpiPM1aEnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1480{
1481 switch (cb)
1482 {
1483 case 2:
1484 acpiPM1aEnWritew((ACPIState*)pvUser, Port, u32);
1485 break;
1486 default:
1487 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1488 break;
1489 }
1490 return VINF_SUCCESS;
1491}
1492
1493PDMBOTHCBDECL(int) acpiPM1aStsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1494{
1495 switch (cb)
1496 {
1497 case 2:
1498 acpiPM1aStsWritew((ACPIState*)pvUser, Port, u32);
1499 break;
1500 default:
1501 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1502 break;
1503 }
1504 return VINF_SUCCESS;
1505}
1506
1507PDMBOTHCBDECL(int) acpiPM1aCtlWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1508{
1509 switch (cb)
1510 {
1511 case 2:
1512 return acpiPM1aCtlWritew((ACPIState*)pvUser, Port, u32);
1513 default:
1514 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1515 break;
1516 }
1517 return VINF_SUCCESS;
1518}
1519
1520#endif /* IN_RING3 */
1521
1522/**
1523 * PMTMR readable from host/guest.
1524 */
1525PDMBOTHCBDECL(int) acpiPMTmrRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1526{
1527 if (cb == 4)
1528 {
1529 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1530 int64_t now = TMTimerGet(s->CTX_SUFF(ts));
1531 int64_t elapsed = now - s->pm_timer_initial;
1532
1533 *pu32 = ASMMultU64ByU32DivByU32(elapsed, PM_TMR_FREQ, TMTimerGetFreq(s->CTX_SUFF(ts)));
1534 Log(("acpi: acpiPMTmrRead -> %#x\n", *pu32));
1535 return VINF_SUCCESS;
1536 }
1537 return VERR_IOM_IOPORT_UNUSED;
1538}
1539
1540#ifdef IN_RING3
1541
1542PDMBOTHCBDECL(int) acpiGpe0StsRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1543{
1544 switch (cb)
1545 {
1546 case 1:
1547 *pu32 = acpiGpe0StsReadb((ACPIState*)pvUser, Port);
1548 break;
1549 default:
1550 return VERR_IOM_IOPORT_UNUSED;
1551 }
1552 return VINF_SUCCESS;
1553}
1554
1555PDMBOTHCBDECL(int) acpiGpe0EnRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1556{
1557 switch (cb)
1558 {
1559 case 1:
1560 *pu32 = acpiGpe0EnReadb((ACPIState*)pvUser, Port);
1561 break;
1562 default:
1563 return VERR_IOM_IOPORT_UNUSED;
1564 }
1565 return VINF_SUCCESS;
1566}
1567
1568PDMBOTHCBDECL(int) acpiGpe0StsWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1569{
1570 switch (cb)
1571 {
1572 case 1:
1573 acpiGpe0StsWriteb((ACPIState*)pvUser, Port, u32);
1574 break;
1575 default:
1576 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1577 break;
1578 }
1579 return VINF_SUCCESS;
1580}
1581
1582PDMBOTHCBDECL(int) acpiGpe0EnWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1583{
1584 switch (cb)
1585 {
1586 case 1:
1587 acpiGpe0EnWriteb((ACPIState*)pvUser, Port, u32);
1588 break;
1589 default:
1590 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1591 break;
1592 }
1593 return VINF_SUCCESS;
1594}
1595
1596PDMBOTHCBDECL(int) acpiSmiWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1597{
1598 switch (cb)
1599 {
1600 case 1:
1601 acpiSmiWriteU8((ACPIState*)pvUser, Port, u32);
1602 break;
1603 default:
1604 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1605 break;
1606 }
1607 return VINF_SUCCESS;
1608}
1609
1610PDMBOTHCBDECL(int) acpiResetWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1611{
1612 switch (cb)
1613 {
1614 case 1:
1615 return acpiResetWriteU8((ACPIState*)pvUser, Port, u32);
1616 default:
1617 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1618 break;
1619 }
1620 return VINF_SUCCESS;
1621}
1622
1623#ifdef DEBUG_ACPI
1624
1625PDMBOTHCBDECL(int) acpiDhexWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1626{
1627 switch (cb)
1628 {
1629 case 1:
1630 Log(("%#x\n", u32 & 0xff));
1631 break;
1632 case 2:
1633 Log(("%#6x\n", u32 & 0xffff));
1634 case 4:
1635 Log(("%#10x\n", u32));
1636 break;
1637 default:
1638 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1639 break;
1640 }
1641 return VINF_SUCCESS;
1642}
1643
1644PDMBOTHCBDECL(int) acpiDchrWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
1645{
1646 switch (cb)
1647 {
1648 case 1:
1649 Log(("%c", u32 & 0xff));
1650 break;
1651 default:
1652 AssertMsgFailed(("Port=%#x cb=%d u32=%#x\n", Port, cb, u32));
1653 break;
1654 }
1655 return VINF_SUCCESS;
1656}
1657
1658#endif /* DEBUG_ACPI */
1659
1660
1661/**
1662 * Saved state structure description.
1663 */
1664static const SSMFIELD g_AcpiSavedStateFields[] =
1665{
1666 SSMFIELD_ENTRY(ACPIState, pm1a_en),
1667 SSMFIELD_ENTRY(ACPIState, pm1a_sts),
1668 SSMFIELD_ENTRY(ACPIState, pm1a_ctl),
1669 SSMFIELD_ENTRY(ACPIState, pm_timer_initial),
1670 SSMFIELD_ENTRY(ACPIState, gpe0_en),
1671 SSMFIELD_ENTRY(ACPIState, gpe0_sts),
1672 SSMFIELD_ENTRY(ACPIState, uBatteryIndex),
1673 SSMFIELD_ENTRY(ACPIState, uSystemInfoIndex),
1674 SSMFIELD_ENTRY(ACPIState, u64RamSize), /** @todo not necessary to save this. */
1675 SSMFIELD_ENTRY(ACPIState, u8IndexShift),
1676 SSMFIELD_ENTRY(ACPIState, u8UseIOApic),
1677 SSMFIELD_ENTRY(ACPIState, uSleepState),
1678 SSMFIELD_ENTRY_TERM()
1679};
1680
1681static DECLCALLBACK(int) acpi_save_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
1682{
1683 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1684 return SSMR3PutStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1685}
1686
1687static DECLCALLBACK(int) acpi_load_state(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
1688 uint32_t u32Version)
1689{
1690 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1691 int rc;
1692
1693 if (u32Version != 4)
1694 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1695
1696 rc = SSMR3GetStruct(pSSMHandle, s, &g_AcpiSavedStateFields[0]);
1697 if (RT_SUCCESS(rc))
1698 {
1699 acpiFetchBatteryStatus(s);
1700 acpiFetchBatteryInfo(s);
1701 acpiPMTimerReset(s);
1702 }
1703 return rc;
1704}
1705
1706/**
1707 * Queries an interface to the driver.
1708 *
1709 * @returns Pointer to interface.
1710 * @returns NULL if the interface was not supported by the driver.
1711 * @param pInterface Pointer to this interface structure.
1712 * @param enmInterface The requested interface identification.
1713 * @thread Any thread.
1714 */
1715static DECLCALLBACK(void *) acpiQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
1716{
1717 ACPIState *pThis = (ACPIState*)((uintptr_t)pInterface - RT_OFFSETOF(ACPIState, IBase));
1718 switch (enmInterface)
1719 {
1720 case PDMINTERFACE_BASE:
1721 return &pThis->IBase;
1722 case PDMINTERFACE_ACPI_PORT:
1723 return &pThis->IACPIPort;
1724 default:
1725 return NULL;
1726 }
1727}
1728
1729/**
1730 * Create the ACPI tables.
1731 */
1732static int acpiPlantTables(ACPIState *s)
1733{
1734 int rc;
1735 RTGCPHYS32 rsdt_addr, xsdt_addr, fadt_addr, facs_addr, dsdt_addr, last_addr, apic_addr = 0;
1736 uint32_t addend = 0;
1737 RTGCPHYS32 rsdt_addrs[4];
1738 uint32_t cAddr;
1739 size_t rsdt_tbl_len = sizeof(ACPITBLHEADER);
1740 size_t xsdt_tbl_len = sizeof(ACPITBLHEADER);
1741
1742 cAddr = 1; /* FADT */
1743 if (s->u8UseIOApic)
1744 cAddr++; /* MADT */
1745
1746 rsdt_tbl_len += cAddr*4; /* each entry: 32 bits phys. address. */
1747 xsdt_tbl_len += cAddr*8; /* each entry: 64 bits phys. address. */
1748
1749 rc = CFGMR3QueryU64(s->pDevIns->pCfgHandle, "RamSize", &s->u64RamSize);
1750 if (RT_FAILURE(rc))
1751 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1752 N_("Configuration error: Querying "
1753 "\"RamSize\" as integer failed"));
1754
1755 uint32_t cbRamHole;
1756 rc = CFGMR3QueryU32Def(s->pDevIns->pCfgHandle, "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1757 if (RT_FAILURE(rc))
1758 return PDMDEV_SET_ERROR(s->pDevIns, rc,
1759 N_("Configuration error: Querying \"RamHoleSize\" as integer failed"));
1760
1761 /*
1762 * Calc the sizes for the high and low regions.
1763 */
1764 const uint64_t offRamHole = _4G - cbRamHole;
1765 s->cbRamHigh = offRamHole < s->u64RamSize ? s->u64RamSize - offRamHole : 0;
1766 uint64_t cbRamLow = offRamHole < s->u64RamSize ? offRamHole : s->u64RamSize;
1767 if (cbRamLow > UINT32_C(0xffe00000)) /* See MEM3. */
1768 {
1769 /* Note: This is also enforced by DevPcBios.cpp. */
1770 LogRel(("DevACPI: Clipping cbRamLow=%#RX64 down to 0xffe00000.\n", cbRamLow));
1771 cbRamLow = UINT32_C(0xffe00000);
1772 }
1773 s->cbRamLow = (uint32_t)cbRamLow;
1774
1775 rsdt_addr = 0;
1776 xsdt_addr = RT_ALIGN_32(rsdt_addr + rsdt_tbl_len, 16);
1777 fadt_addr = RT_ALIGN_32(xsdt_addr + xsdt_tbl_len, 16);
1778 facs_addr = RT_ALIGN_32(fadt_addr + sizeof(ACPITBLFADT), 16);
1779 if (s->u8UseIOApic)
1780 {
1781 apic_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1782#ifdef VBOX_WITH_SMP_GUESTS
1783 /**
1784 * @todo nike: maybe some refactoring needed to compute tables layout,
1785 * but as this code is executed only once it doesn't make sense to optimize much
1786 */
1787 dsdt_addr = RT_ALIGN_32(apic_addr + AcpiTableMADT::sizeFor(s), 16);
1788#else
1789 dsdt_addr = RT_ALIGN_32(apic_addr + sizeof(ACPITBLMADT), 16);
1790#endif
1791 }
1792 else
1793 {
1794 dsdt_addr = RT_ALIGN_32(facs_addr + sizeof(ACPITBLFACS), 16);
1795 }
1796
1797 last_addr = RT_ALIGN_32(dsdt_addr + sizeof(AmlCode), 16);
1798 if (last_addr > 0x10000)
1799 return PDMDEV_SET_ERROR(s->pDevIns, VERR_TOO_MUCH_DATA,
1800 N_("Error: ACPI tables > 64KB"));
1801
1802 Log(("RSDP 0x%08X\n", find_rsdp_space()));
1803 addend = s->cbRamLow - 0x10000;
1804 Log(("RSDT 0x%08X XSDT 0x%08X\n", rsdt_addr + addend, xsdt_addr + addend));
1805 Log(("FACS 0x%08X FADT 0x%08X\n", facs_addr + addend, fadt_addr + addend));
1806 Log(("DSDT 0x%08X\n", dsdt_addr + addend));
1807 acpiSetupRSDP((ACPITBLRSDP*)s->au8RSDPPage, rsdt_addr + addend, xsdt_addr + addend);
1808 acpiSetupDSDT(s, dsdt_addr + addend);
1809 acpiSetupFACS(s, facs_addr + addend);
1810 acpiSetupFADT(s, fadt_addr + addend, facs_addr + addend, dsdt_addr + addend);
1811
1812 rsdt_addrs[0] = fadt_addr + addend;
1813 if (s->u8UseIOApic)
1814 {
1815 acpiSetupMADT(s, apic_addr + addend);
1816 rsdt_addrs[1] = apic_addr + addend;
1817 }
1818
1819 rc = acpiSetupRSDT(s, rsdt_addr + addend, cAddr, rsdt_addrs);
1820 if (RT_FAILURE(rc))
1821 return rc;
1822 return acpiSetupXSDT(s, xsdt_addr + addend, cAddr, rsdt_addrs);
1823}
1824
1825/**
1826 * Construct a device instance for a VM.
1827 *
1828 * @returns VBox status.
1829 * @param pDevIns The device instance data.
1830 * If the registration structure is needed, pDevIns->pDevReg points to it.
1831 * @param iInstance Instance number. Use this to figure out which registers and such to use.
1832 * The device number is also found in pDevIns->iInstance, but since it's
1833 * likely to be freqently used PDM passes it as parameter.
1834 * @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
1835 * of the device instance. It's also found in pDevIns->pCfgHandle, but like
1836 * iInstance it's expected to be used a bit in this function.
1837 */
1838static DECLCALLBACK(int) acpiConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
1839{
1840 int rc;
1841 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
1842 uint32_t rsdp_addr;
1843 PCIDevice *dev;
1844 bool fGCEnabled;
1845 bool fR0Enabled;
1846
1847 /* Validate and read the configuration. */
1848 if (!CFGMR3AreValuesValid(pCfgHandle,
1849 "RamSize\0"
1850 "RamHoleSize\0"
1851 "IOAPIC\0"
1852 "NumCPUs\0"
1853 "GCEnabled\0"
1854 "R0Enabled\0"
1855 "HpetEnabled\0"
1856 "SmcEnabled\0"
1857 "FdcEnabled\0"
1858 ))
1859 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1860 N_("Configuration error: Invalid config key for ACPI device"));
1861
1862 s->pDevIns = pDevIns;
1863
1864 /* query whether we are supposed to present an IOAPIC */
1865 rc = CFGMR3QueryU8Def(pCfgHandle, "IOAPIC", &s->u8UseIOApic, 1);
1866 if (RT_FAILURE(rc))
1867 return PDMDEV_SET_ERROR(pDevIns, rc,
1868 N_("Configuration error: Failed to read \"IOAPIC\""));
1869
1870 rc = CFGMR3QueryU16Def(pCfgHandle, "NumCPUs", &s->cCpus, 1);
1871 if (RT_FAILURE(rc))
1872 return PDMDEV_SET_ERROR(pDevIns, rc,
1873 N_("Configuration error: Querying \"NumCPUs\" as integer failed"));
1874
1875 /* query whether we are supposed to present an FDC controller */
1876 rc = CFGMR3QueryBoolDef(pCfgHandle, "FdcEnabled", &s->fUseFdc, true);
1877 if (RT_FAILURE(rc))
1878 return PDMDEV_SET_ERROR(pDevIns, rc,
1879 N_("Configuration error: Failed to read \"FdcEnabled\""));
1880
1881 /* query whether we are supposed to present HPET */
1882 rc = CFGMR3QueryBoolDef(pCfgHandle, "HpetEnabled", &s->fUseHpet, false);
1883 if (RT_FAILURE(rc))
1884 return PDMDEV_SET_ERROR(pDevIns, rc,
1885 N_("Configuration error: Failed to read \"HpetEnabled\""));
1886 /* query whether we are supposed to present SMC */
1887 rc = CFGMR3QueryBoolDef(pCfgHandle, "SmcEnabled", &s->fUseSmc, false);
1888 if (RT_FAILURE(rc))
1889 return PDMDEV_SET_ERROR(pDevIns, rc,
1890 N_("Configuration error: Failed to read \"SmcEnabled\""));
1891 /** @todo: a bit of hack: if we have SMC, also show CPU object in ACPI tables */
1892 s->fShowCpu = s->fUseSmc;
1893
1894 rc = CFGMR3QueryBool(pCfgHandle, "GCEnabled", &fGCEnabled);
1895 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1896 fGCEnabled = true;
1897 else if (RT_FAILURE(rc))
1898 return PDMDEV_SET_ERROR(pDevIns, rc,
1899 N_("Configuration error: Failed to read \"GCEnabled\""));
1900
1901 rc = CFGMR3QueryBool(pCfgHandle, "R0Enabled", &fR0Enabled);
1902 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1903 fR0Enabled = true;
1904 else if (RT_FAILURE(rc))
1905 return PDMDEV_SET_ERROR(pDevIns, rc,
1906 N_("configuration error: failed to read R0Enabled as boolean"));
1907
1908 /* */
1909 rsdp_addr = find_rsdp_space();
1910 if (!rsdp_addr)
1911 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY,
1912 N_("Can not find space for RSDP. ACPI is disabled"));
1913
1914 rc = acpiPlantTables(s);
1915 if (RT_FAILURE(rc))
1916 return rc;
1917
1918 rc = PDMDevHlpROMRegister(pDevIns, rsdp_addr, 0x1000, s->au8RSDPPage,
1919 PGMPHYS_ROM_FLAGS_PERMANENT_BINARY, "ACPI RSDP");
1920 if (RT_FAILURE(rc))
1921 return rc;
1922
1923#define R(addr, cnt, writer, reader, description) \
1924 do { \
1925 rc = PDMDevHlpIOPortRegister(pDevIns, addr, cnt, s, writer, reader, \
1926 NULL, NULL, description); \
1927 if (RT_FAILURE(rc)) \
1928 return rc; \
1929 } while (0)
1930#define L (GPE0_BLK_LEN / 2)
1931
1932 R(PM1a_EVT_BLK+2, 1, acpiPM1aEnWrite, acpiPm1aEnRead, "ACPI PM1a Enable");
1933 R(PM1a_EVT_BLK, 1, acpiPM1aStsWrite, acpiPm1aStsRead, "ACPI PM1a Status");
1934 R(PM1a_CTL_BLK, 1, acpiPM1aCtlWrite, acpiPm1aCtlRead, "ACPI PM1a Control");
1935 R(PM_TMR_BLK, 1, NULL, acpiPMTmrRead, "ACPI PM Timer");
1936 R(SMI_CMD, 1, acpiSmiWrite, NULL, "ACPI SMI");
1937#ifdef DEBUG_ACPI
1938 R(DEBUG_HEX, 1, acpiDhexWrite, NULL, "ACPI Debug hex");
1939 R(DEBUG_CHR, 1, acpiDchrWrite, NULL, "ACPI Debug char");
1940#endif
1941 R(BAT_INDEX, 1, acpiBatIndexWrite, NULL, "ACPI Battery status index");
1942 R(BAT_DATA, 1, NULL, acpiBatDataRead, "ACPI Battery status data");
1943 R(SYSI_INDEX, 1, acpiSysInfoIndexWrite, NULL, "ACPI system info index");
1944 R(SYSI_DATA, 1, acpiSysInfoDataWrite, acpiSysInfoDataRead, "ACPI system info data");
1945 R(GPE0_BLK + L, L, acpiGpe0EnWrite, acpiGpe0EnRead, "ACPI GPE0 Enable");
1946 R(GPE0_BLK, L, acpiGpe0StsWrite, acpiGpe0StsRead, "ACPI GPE0 Status");
1947 R(ACPI_RESET_BLK, 1, acpiResetWrite, NULL, "ACPI Reset");
1948#undef L
1949#undef R
1950
1951 /* register GC stuff */
1952 if (fGCEnabled)
1953 {
1954 rc = PDMDevHlpIOPortRegisterGC(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1955 NULL, NULL, "ACPI PM Timer");
1956 AssertRCReturn(rc, rc);
1957 }
1958
1959 /* register R0 stuff */
1960 if (fR0Enabled)
1961 {
1962 rc = PDMDevHlpIOPortRegisterR0(pDevIns, PM_TMR_BLK, 1, 0, NULL, "acpiPMTmrRead",
1963 NULL, NULL, "ACPI PM Timer");
1964 AssertRCReturn(rc, rc);
1965 }
1966
1967 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, acpiTimer, "ACPI Timer", &s->tsR3);
1968 if (RT_FAILURE(rc))
1969 {
1970 AssertMsgFailed(("pfnTMTimerCreate -> %Rrc\n", rc));
1971 return rc;
1972 }
1973
1974 s->tsR0 = TMTimerR0Ptr(s->tsR3);
1975 s->tsRC = TMTimerRCPtr(s->tsR3);
1976 s->pm_timer_initial = TMTimerGet(s->tsR3);
1977 acpiPMTimerReset(s);
1978
1979 dev = &s->dev;
1980 PCIDevSetVendorId(dev, 0x8086); /* Intel */
1981 PCIDevSetDeviceId(dev, 0x7113); /* 82371AB */
1982
1983 dev->config[0x04] = 0x01; /* command */
1984 dev->config[0x05] = 0x00;
1985
1986 dev->config[0x06] = 0x80; /* status */
1987 dev->config[0x07] = 0x02;
1988 dev->config[0x08] = 0x08;
1989 dev->config[0x09] = 0x00;
1990
1991 dev->config[0x0a] = 0x80;
1992 dev->config[0x0b] = 0x06;
1993
1994 dev->config[0x0e] = 0x80;
1995 dev->config[0x0f] = 0x00;
1996
1997#if 0 /* The ACPI controller usually has no subsystem ID. */
1998 dev->config[0x2c] = 0x86;
1999 dev->config[0x2d] = 0x80;
2000 dev->config[0x2e] = 0x00;
2001 dev->config[0x2f] = 0x00;
2002#endif
2003 dev->config[0x3c] = SCI_INT;
2004
2005 rc = PDMDevHlpPCIRegister(pDevIns, dev);
2006 if (RT_FAILURE(rc))
2007 return rc;
2008
2009 rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance, 4, sizeof(*s),
2010 NULL, acpi_save_state, NULL, NULL, acpi_load_state, NULL);
2011 if (RT_FAILURE(rc))
2012 return rc;
2013
2014 /*
2015 * Interfaces
2016 */
2017 /* IBase */
2018 s->IBase.pfnQueryInterface = acpiQueryInterface;
2019 /* IACPIPort */
2020 s->IACPIPort.pfnSleepButtonPress = acpiSleepButtonPress;
2021 s->IACPIPort.pfnPowerButtonPress = acpiPowerButtonPress;
2022 s->IACPIPort.pfnGetPowerButtonHandled = acpiGetPowerButtonHandled;
2023 s->IACPIPort.pfnGetGuestEnteredACPIMode = acpiGetGuestEnteredACPIMode;
2024
2025 /*
2026 * Get the corresponding connector interface
2027 */
2028 rc = PDMDevHlpDriverAttach(pDevIns, 0, &s->IBase, &s->pDrvBase, "ACPI Driver Port");
2029 if (RT_SUCCESS(rc))
2030 {
2031 s->pDrv = (PPDMIACPICONNECTOR)s->pDrvBase->pfnQueryInterface(s->pDrvBase, PDMINTERFACE_ACPI_CONNECTOR);
2032 if (!s->pDrv)
2033 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_MISSING_INTERFACE,
2034 N_("LUN #0 doesn't have an ACPI connector interface"));
2035 }
2036 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
2037 {
2038 Log(("acpi: %s/%d: warning: no driver attached to LUN #0!\n",
2039 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2040 rc = VINF_SUCCESS;
2041 }
2042 else
2043 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to attach LUN #0"));
2044
2045 return rc;
2046}
2047
2048/**
2049 * Relocates the GC pointer members.
2050 */
2051static DECLCALLBACK(void) acpiRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
2052{
2053 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2054 s->tsRC = TMTimerRCPtr(s->CTX_SUFF(ts));
2055}
2056
2057static DECLCALLBACK(void) acpiReset(PPDMDEVINS pDevIns)
2058{
2059 ACPIState *s = PDMINS_2_DATA(pDevIns, ACPIState *);
2060
2061 s->pm1a_en = 0;
2062 s->pm1a_sts = 0;
2063 s->pm1a_ctl = 0;
2064 s->pm_timer_initial = TMTimerGet(s->CTX_SUFF(ts));
2065 acpiPMTimerReset(s);
2066 s->uBatteryIndex = 0;
2067 s->uSystemInfoIndex = 0;
2068 s->gpe0_en = 0;
2069 s->gpe0_sts = 0;
2070 s->uSleepState = 0;
2071
2072 acpiPlantTables(s);
2073}
2074
2075/**
2076 * The device registration structure.
2077 */
2078const PDMDEVREG g_DeviceACPI =
2079{
2080 /* u32Version */
2081 PDM_DEVREG_VERSION,
2082 /* szDeviceName */
2083 "acpi",
2084 /* szRCMod */
2085 "VBoxDDGC.gc",
2086 /* szR0Mod */
2087 "VBoxDDR0.r0",
2088 /* pszDescription */
2089 "Advanced Configuration and Power Interface",
2090 /* fFlags */
2091 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
2092 /* fClass */
2093 PDM_DEVREG_CLASS_ACPI,
2094 /* cMaxInstances */
2095 ~0,
2096 /* cbInstance */
2097 sizeof(ACPIState),
2098 /* pfnConstruct */
2099 acpiConstruct,
2100 /* pfnDestruct */
2101 NULL,
2102 /* pfnRelocate */
2103 acpiRelocate,
2104 /* pfnIOCtl */
2105 NULL,
2106 /* pfnPowerOn */
2107 NULL,
2108 /* pfnReset */
2109 acpiReset,
2110 /* pfnSuspend */
2111 NULL,
2112 /* pfnResume */
2113 NULL,
2114 /* pfnAttach */
2115 NULL,
2116 /* pfnDetach */
2117 NULL,
2118 /* pfnQueryInterface. */
2119 NULL,
2120 /* pfnInitComplete */
2121 NULL,
2122 /* pfnPowerOff */
2123 NULL,
2124 /* pfnSoftReset */
2125 NULL,
2126 /* u32VersionEnd */
2127 PDM_DEVREG_VERSION
2128};
2129
2130#endif /* IN_RING3 */
2131#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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